Started by user snail Running as SYSTEM [EnvInject] - Loading node environment variables. Building remotely on docker-jenkins-agent in workspace /home/jenkins/agent/workspace/gcc-patch [WS-CLEANUP] Deleting project workspace... [WS-CLEANUP] Deferred wipeout is used... [WS-CLEANUP] Done The recommended git tool is: NONE using credential 0adb5fc7-caa2-429d-97d2-c7fa2fa1d884 Cloning the remote Git repository Using shallow clone with depth 1 Avoid fetching tags Cloning repository git@github.com:wangliu-iscas/gcc-patch.git/ > git init /home/jenkins/agent/workspace/gcc-patch # timeout=10 Fetching upstream changes from git@github.com:wangliu-iscas/gcc-patch.git/ > git --version # timeout=10 > git --version # 'git version 2.37.2' using GIT_SSH to set credentials patchwork github wangliu-iscas git ssh key Verifying host key using known hosts file, will automatically accept unseen keys > git fetch --no-tags --force --progress --depth=1 -- git@github.com:wangliu-iscas/gcc-patch.git/ +refs/heads/*:refs/remotes/origin/* # timeout=10 > git config remote.origin.url git@github.com:wangliu-iscas/gcc-patch.git/ # timeout=10 > git config --add remote.origin.fetch +refs/heads/*:refs/remotes/origin/* # timeout=10 Avoid second fetch > git rev-parse refs/remotes/origin/master^{commit} # timeout=10 Checking out Revision e73fe9e162af7b875a54cd78ddbb6bf26d8b06c2 (refs/remotes/origin/master) > git config core.sparsecheckout # timeout=10 > git checkout -f e73fe9e162af7b875a54cd78ddbb6bf26d8b06c2 # timeout=10 Commit message: "libgcc: Quote variable in Makefile.in" > git rev-list --no-walk e73fe9e162af7b875a54cd78ddbb6bf26d8b06c2 # timeout=10 [EnvInject] - Mask passwords that will be passed as build parameters. [EnvInject] - Executing scripts and injecting environment variables after the SCM step. [EnvInject] - Injecting as environment variables the properties content GITHUB_REPO=https://github.com/wangliu-iscas/ PATCHWORK_URL=https://patchwork.plctlab.org [EnvInject] - Variables injected successfully. [gcc-patch] $ /usr/bin/env bash /tmp/jenkins7548160269218921383.sh + git config pw.server https://patchwork.plctlab.org/api/1.2/ + git config pw.project gcc-patch + git config pw.token [*******] ++ date +%Y-%m + now_date=2022-10 + echo 2022-10 2022-10 ++ curl -s -H 'Authorization: Token [*******]' 'https://patchwork.plctlab.org/api/1.2/bundles/?project=gcc-patch&per_page=999' + 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1622 [pushed] c++: loop through array CONSTRUCTOR | | | 1624 [committed] Improve Z flag handling on H8 | | | 1628 OpenACC: Fix struct-component-kind-1.c test | | | 1629 Adding a new thread model to GCC | | | 1630 libstdc++: Use ///< for inline documentation | | | 1632 c++: Disallow jumps into statement expressions | | | 1633 [committed] tree-cfg: Fix a verification diagnostic typo [PR107121] | | | 1634 Fortran: Add OpenMP's assume(s) directives | | | 1636 [RFC.,Fortran] Some clobbering for INTENT(OUT) arrays | | | 1639 Set discriminators for call stmts on the same line within the same basic block | | | 1645 arm: Add missing early clobber to MVE vrev64q_m patterns | | | 1650 [COMMITTED] Do not compare incompatible ranges in ipa-prop. | | | 1653 [COMMITTED] Do not compare nonzero masks for varying. | | | 1651 [COMMITTED] Avoid comparing ranges when sub-ranges is 0. | | | 1652 [COMMITTED] Do not pessimize range in set_nonzero_bits. | | | 1654 [committed] libstdc++: Fix tests broken by C++23 P2266R3 "Simpler implicit move" | | | 1655 [COMMITTED] libsanitizer: Fix Solaris 11.3 compilation of sanitizer_procmaps_solaris.cpp [PR105531] | | | 1657 [committed] c: Adjust LDBL_EPSILON for C2x for IBM long double | | | 1658 PR tree-optimization/107109 - Don't process undefined range. | | | 1661 c++, c, v2: Implement C++23 P1774R8 - Portable assumptions [PR106654] | | | 1662 elf: ELF toolchain --without-{headers, newlib} should provide stdint.h | | | 1663 [committed] libstdc++: Update status docs for compare_exchange padding bits | | | 1664 aarch64: update Ampere-1 core definition | | | 1665 aarch64: fix off-by-one in reading cpuinfo | | | 1666 diagnostics: Add test for fixed _Pragma location issue [PR91669] | | | 1667 c++: install cp-trait.def as part of plugin headers [PR107136] | | | 1668 libstdc++: Implement ranges::join_with_view from P2441R2 | | | 1669 [COMMITTED,PR107130] range-ops: Separate out ffs and popcount optimizations. | | | 1670 [COMMITTED] Convert nonzero mask in irange to wide_int. | | | 1674 middle-end, c++, i386, libgcc: std::bfloat16_t and __bf16 arithmetic support | | | 1675 attribs: Add missing auto_diagnostic_group 3 times | | | 1680 cselib: Skip BImode while keeping track of subvalue relations [PR107088] | | | 1685 [committed] libstdc++: Define functions for freestanding [PR107135] | | | 1683 [committed] libstdc++: Make work freestanding [PR107134] | | | 1682 [committed] libstdc++: Enable std::hash> [PR107139] | | | 1684 [committed] libstdc++: Disable test for freestanding | | | 1686 [RESEND,1/1] p1689r5: initial support | | | 1687 Add --without-makeinfo | | | 1688 [GCC13,V5,1/2] Add a new option -fstrict-flex-arrays[=n] and new attribute strict_flex_array | | | 1689 [GCC13,V5,2/2] Use array_at_struct_end_p in __builtin_object_size [PR101836] | | | 1692 aarch64: Define __ARM_FEATURE_RCPC | | | 1693 [committed] libstdc++: Refactor seed sequence constraints in | | | 1694 [committed] libstdc++: Use new built-ins __remove_cv, __remove_reference etc. | | | 1695 [committed] libstdc++: Fix test FAIL for old std::string ABI | | | 1696 [RFC] libstdc++: Generate error_constants.h from [PR104883] | | | 1697 improved const shifts for AVR targets | | | 1698 [AArch64] Improve immediate expansion [PR106583] | | | 1699 c++ modules: lazy loading from within template [PR99377] | | | 1700 [COMMITTED] Remove assert from set_nonzero_bits. | | | 1701 Fortran: reject procedures and procedure pointers as output item [PR107074] | | | 1703 Fortran: error recovery for invalid types in array constructors [PR107000] | | | 1704 [pushed] c++: fix debug info for array temporary [PR107154] | | | 1705 [v2] c-family: ICE with [[gnu::nocf_check]] [PR106937] | | | 1706 [committed] analyzer: widening_svalues take a function_point rather than a program_point | | | 1707 [committed] analyzer: fold -(-(VAL)) to VAL | | | 1709 [committed] analyzer: move region_model_manager decl to its own header | | | 1708 [committed] analyzer: revamp side-effects of call summaries [PR107072] | | | 1720 c++, c, v3: Implement C++23 P1774R8 - Portable assumptions [PR106654] | | | 1721 [pushed] testsuite: mark a test with xfail | | | 1722 [pushed] analyzer: remove unused variables | | | 1723 IPA: support -flto + -flive-patching=inline-clone | | | 1724 c: support attribs starting with '_' | | | 1725 c: support attribs starting with '_' | | | 1728 [1/2] gcov: test switch/break line counts | | | 1726 [2/2] Split edge when edge locus and dest don't match | | | 1727 c++: Improve handling of foreigner namespace attributes | | | 1729 [COMMITTED,PR,tree-optimization/107052] range-ops: Pass nonzero masks through cast. | | | 1730 [COMMITTED,PR,tree-optimization/107052] range-ops: Pass nonzero masks through cast. | | | 1731 [COMMITTED,PR,tree-optimization/107052] range-ops: Take into account nonzero mask in popcount. | | | 1732 [AArch64] Improve bit tests [PR105773] | | | 1733 [committed] libstdc++: Guard use of new built-in with __has_builtin | | | 1734 [committed] libtdc++: Regenerate Makefile.in after freestanding header changes | | | 1735 [COMMITTED] range-op: Keep nonzero mask up to date with truncating casts. | | | 1736 [pushed] c++: lvalue_kind tweak | | | 1737 [v2] testsuite: Sanitize fails for SP FPU on Arm | | | 1738 Fix wrong code generated by unroll-and-jam pass | | | 1739 [committed] analyzer: fix ICEs seen with call summaries on PR 107060 | | | 1740 [committed] analyzer: simplify some includes | | | 1741 [committed] analyzer: add regression test for PR 107158 | | | 1742 [pushed] contrib: run fetch before pushing Daily bump | | | 1744 [1/3] rs6000: Remove "wD" from *vsx_extract__store | | | 1743 [2/3] rs6000: Rework vsx_extract_ | | | 1745 [3/3] rs6000: Remove the wD constraint | | | 1747 [GCC13,V6,1/2] Add a new option -fstrict-flex-arrays[=n] and new attribute strict_flex_array | | | 1746 [GCC13,V6,2/2] Use array_at_struct_end_p in __builtin_object_size [PR101836] | | | 1748 c++: fixes for derived-to-base reference binding [PR107085] | | | 1749 c: C2x typeof | | | 1750 c++: remove optimize_specialization_lookup_p | | | 1753 [COMMITTED] Do not double print INF and NAN in frange pretty printer. | | | 1755 [COMMITTED] Do not check finite_operands_p twice in range-ops-float. | | | 1754 [COMMITTED] Setting explicit NANs sets UNDEFINED for -ffinite-math-only. | | | 1756 [committed] openmp: Map holds clause to IFN_ASSUME for C/C++ | | | 1757 [committed] arc: Remove max-page-size and common-page-size forced setting | | | 1758 [pushed] git_update_version: add robust logging | | | 1759 [COMMITED] ada: Fix spurious warning on unreferenced refinement constituents | | | 1760 [COMMITED] ada: Disable slice-of-component optimization in some cases | | | 1761 [COMMITED] ada: Do not issue compiler warnings in GNATprove mode | | | 1762 [COMMITED] ada: Clean up slice-of-component optimization | | | 1763 [v2] aarch64: fix off-by-one in reading cpuinfo | | | 1764 [COMMITED] ada: Accessibility error incorrectly flagged on call within Pre'Class expression | | | 1765 [COMMITED] ada: Incorrect inferences drawn from if/elsif/while conditions with -gnatVo | | | 1767 [COMMITED] ada: Add C declarations for Storage Model support | | | 1766 [COMMITED] ada: Fix inserting of validity checks in lock-free protected subprograms | | | 1768 [v2] aarch64: update Ampere-1 core definition | | | 1772 [COMMITED] ada: stack scrubbing: exemplify codegen changes | | | 1769 [COMMITED] ada: hardened booleans: exemplify codegen changes | | | 1770 [COMMITED] ada: hardened conditionals: exemplify codegen changes | | | 1771 [COMMITED] ada: Cleanup related to lock-free protected subprograms | | | 1773 [COMMITED] ada: Reject conditional goto in lock-free protected subprograms | | | 1774 [COMMITED] ada: Minor potential bug in sem_ch6.adb | | | 1775 [COMMITED] ada: Implementation of support for storage models in gigi | | | 1778 tree-optimization/107107 - tail-merging VN wrong-code | | | 1779 [RFC] Add op1_range for __builtin_signbit. | | | 1780 openmp: Map holds clause to IFN_ASSUME for Fortran | | | 1782 middle-end/107115 - avoid bogus redundant store removal during RTL expansion | | | 1783 [RFC] c++: parser - Support for target address spaces in C++ | | | 1784 [v2] c++: fixes for derived-to-base reference binding [PR107085] | | | 1785 gcc-12: FTBFS on hurd-i386 | | | 1786 c++ modules: static var in inline function [PR104433] | | | 1787 c++, v2: Improve handling of foreigner namespace attributes | | | 1788 Reduce DF computation at -O0 | | | 1789 Fix gdb FilteringTypePrinter (again) | | | 1790 [RFA] gimplify: prevent some C++ temporary elision | | | 1791 c++, v3: Improve handling of foreigner namespace attributes | | | 1792 [v2] libstdc++: basic_filebuf: don't flush more often than necessary. | | | 1794 [committed] analyzer: fixes to call_summary_replay::dump_to_pp | | | 1793 [committed] analyzer: fix another ICE in PR 107158 | | | 1795 [COMMITTED,PR107170] Avoid copying incompatible types in legacy VRP. | | | 1796 [rs6000] Fix addg6s builtin with long long parameters. (PR100693) | | | 1797 [v3] c++: fixes for derived-to-base reference binding [PR107085] | | | 1798 [committed] libgcc, arc: Fix build | | | 1799 [v3] c-family: ICE with [[gnu::nocf_check]] [PR106937] | | | 1800 Go patch committed: better argument checking for builtins | | | 1802 PR middle-end/88345: Honor -falign-functions=N even optimized for size. | | | 1804 [committed] Fix comment typos | | | 1805 [pushed] remove dead variables | | | 1806 [pushed] fix clang warnings | | | 1807 [pushed] libdecnumber: remove unused variable | | | 1808 [pushed] contrib: remove extra fetch from git_update_version | | | 1809 [committed] libstdc++: Use bold style for DR titles in the manual | | | 1810 [committed] libstdc++: Shuffle header dependencies of | | | 1811 [committed] libstdc++: Add --disable-libstdcxx-hosted as an alias for hosted-libstdcxx | | | 1812 tree-optimization/107153 - autopar SSA update issue | | | 1813 c++: Lambda context mangling | | | 1814 [v3] testsuite: Sanitize fails for SP FPU on Arm | | | 1815 doc: -falign-functions doesn't override the __attribute__((align(N))) | | | 1816 libiberty: Demangle variadic template lambdas | | | 1817 [v5] libgomp/nvptx: Prepare for reverse-offload callback handling | | | 1818 c++ modules: ICE with bitfield member in class template | | | 1819 libstdc++: Allow emergency EH alloc pool size to be tuned [PR68606] | | | 1820 [v4] c++: fixes for derived-to-base reference binding [PR107085] | | | 1821 [committed] analyzer: extract bits from integer constants [PR105783] | | | 1822 [v3] Fortran: error recovery for invalid types in array constructors [PR107000] | | | 1823 [PATCHv2] libstdc++: Mark pieces of gnu-linux/os_support.h linux-specific | | | 1824 [v4] c-family: ICE with [[gnu::nocf_check]] [PR106937] | | | 1825 [v5] c++: fixes for derived-to-base reference binding [PR107085] | | | 1826 [pushed] c++: track whether we expect a TARGET_EXPR to be elided | | | 1835 preprocessor: Fix tracking of system header state [PR60014, PR60723] | | | 1837 [committed] pru: Optimize DI shifts | | | 1838 [committed] pru: Add cbranchdi4 pattern | | | 1839 Fortran: fix check of polymorphic elements in data transfers [PR100971] | | | 1840 [v4,1/4] OpenMP: Pointers and member mappings | | | 1841 [v4,2/4] OpenMP/OpenACC: Reindent TO/FROM/_CACHE_ stanza in {c_}finish_omp_clause | | | 1843 [v4,3/4] OpenMP/OpenACC: Rework clause expansion and nested struct handling | | | 1842 [v4,4/4] OpenMP/OpenACC: Unordered/non-constant component offset struct mapping | | | 1846 [x86] Fix unrecognizable insn of cvtss2si. | | | 1847 [committed,1/5] arc: Fix enter pattern instruction's offsets | | | 1848 [committed,2/5] arc: Remove Rcr constraint | | | 1850 [committed,3/5] arc: Remove Rcw constraint | | | 1851 [committed,4/5] arc: Remove Rcq constraint. | | | 1849 [committed,5/5] arc: Remove obsolete mRcq and mRcw options. | | | 1852 [committed] openmp, fortran: Fix up IFN_ASSUME call | | | 1853 [GCC] arm: Add cde feature support for Cortex-M55 CPU. | | | 1854 middle-end IFN_ASSUME support [PR106654] | | | 1855 Require fgraphite effective target for pr107153.c test [PR107153] | | | 1856 [RFT] Vectorization of first-order recurrences | | | 1857 [committed] libstdc++: std::make_signed_t should be ill-formed | | | 1862 [COMMITTED] Return non-legacy ranges in range.h. | | | 1859 [COMMITTED] x UNORD x should set NAN on the TRUE side (and !NAN on the FALSE side). | | | 1858 [COMMITTED] The true side of x != x should set NAN. | | | 1861 [COMMITTED] Add frange::maybe_isnan (bool sign). | | | 1860 [COMMITTED] Make range-op-float entries public. | | | 1863 [committed] RISC-V: Add newline to the end of file [NFC] | | | 1864 [committed] RISC-V: Adjust testcase for rvv/base/user-1.c | | | 1865 [committed] RISC-V: Add riscv_vector.h wrapper in testsuite to prevent pull in stdint.h from C library | | | 1866 RISC-V: Add missing vsetvl instruction type. | | | 1867 RISC-V: move struct vector_type_info from *.h to *.cc. | | | 1868 RISC-V: move struct vector_type_info from *.h to *.cc and change "user_name" into "name". | | | 1869 [RFC] Add support for vectors in comparisons (like the C++ frontend does) | | | 1870 Restore default 'sorry' 'TARGET_ASM_CONSTRUCTOR', 'TARGET_ASM_DESTRUCTOR' (was: [PATCH 1/3] STABS: remove -gstabs and -gxcoff functionality) | | | 1876 1/19 modula2 front end: changes outside gcc/m2, libgm2 and gcc/testsuite. | | | 1874 2/19 modula2 front end: Make-lang.in | | | 1882 4/19 modula2 front end: libgm2/libm2pim contents | | | 1872 3/19 modula2 front end: gm2 driver files. | | | 1871 7/19 modula2 front end: libgm2/libm2log contents | | | 1873 6/19 modula2 front end: libgm2/libm2min contents | | | 1881 5/19 modula2 front end: libgm2/libm2iso contents | | | 1877 9/19 modula2 front end: plugin source files | | | 1875 8/19 modula2 front end: libgm2 contents | | | 1883 11/19 modula2 front end: gimple interface *[a-d]*.cc | | | 1884 10/19 modula2 front end: gimple interface header files *.h and *.def | | | 1887 12/19 modula2 front end: gimple interface *[e-f]*.cc | | | 1878 13/19 modula2 front end: gimple interface *[g-m]*.cc | | | 1879 14/19 modula2 front end: gimple interface remainder | | | 1886 15/19 modula2 front end: cc1gm2 additional non modula2 source files | | | 1885 16/19 modula2 front end: bootstrap and documentation tools | | | 1880 17/19 modula2 front end: dejagnu expect library scripts | | | 1888 Avoid calling tracer.trailer() twice. | | | 1889 [v5] c-family: ICE with [[gnu::nocf_check]] [PR106937] | | | 1891 Go patch committed: Only build thunk struct type when needed | | | 1892 Go patch committed: Treat S("") as a string constant | | | 1896 [ICE] Fix for PR107193. | | | 1898 libstdc++: Implement ranges::repeat_view from P2474R2 | | | 1899 [committed,PR,rtl-optimization/107182] Clear EDGE_CROSSING for jump->ret optimization | | | 1900 RISC-V: Move function place to make it looks better. | | | 1901 RISC-V: Refine register_builtin_types function. | | | 1902 RISC-V: Clang-format add_vector_attribute function. | | | 1903 RISC-V: Remove TUPLE size macro define. | | | 1904 RISC-V: Refine riscv-vector-builtins.o include files and makefile. | | | 1905 RISC-V: Clang-format vector_type_index. | | | 1906 [(pushed)] ranger: add override keyword | | | 1907 [PATCH-1,rs6000] Generate permute index directly for little endian target [PR100866] | | | 1908 [x86] Add define_insn_and_split to support general version of "kxnor". | | | 1909 [COMMITTED,PR107195] Set range to zero when nonzero mask is 0. | | | 1913 [committed,1/6] amdgcn: add multiple vector sizes | | | 1910 [committed,2/6] amdgcn: Resolve insn conditions at compile time | | | 1911 [committed,3/6] amdgcn: Add vec_extract for partial vectors | | | 1912 [committed,4/6] amdgcn: vec_init for multiple vector sizes | | | 1914 [committed,5/6] amdgcn: Add vector integer negate insn | | | 1915 [committed,6/6] amdgcn: vector testsuite tweaks | | | 1916 tree-optimization/107212 - SLP reduction of reduction paths | | | 1917 libiberty: Demangling 'M' prefixes | | | 1918 [1/2] gcov: test switch/break line counts | | | 1919 [2/2] gcov: test line count for label in then/else block | | | 1920 c++: Implement excess precision support for C++ [PR107097, PR323] | | | 1921 middle-end, v2: IFN_ASSUME support [PR106654] | | | 1922 [COMMITTED] Move TRUE case first in range-op.cc. | | | 1923 [COMMITTED] Share common ordered comparison code with UN*_EXPR. | | | 1925 [COMMITTED] Implement op1_range operators for unordered comparisons. | | | 1924 [COMMITTED] Implement ABS_EXPR operator for frange. | | | 1926 c++ modules: ICE with templated friend and std namespace [PR100134] | | | 1927 testsuite: Only run -fcf-protection test on i?86/x86_64 [PR107213] | | | 1930 Fortran: check types of source expressions before conversion [PR107215] | | | 1931 c++: ICE with VEC_INIT_EXPR and defarg [PR106925] | | | 1932 Fortran: check types of operands of arithmetic binary operations [PR107217] | | | 1933 [v2,1/3] doc: -falign-functions doesn't override the __attribute__((align(N))) | | | 1935 [v2,2/3] doc: -falign-functions is ignored under -Os | | | 1934 [v2,3/3] doc: -falign-functions is ignored for cold/size-optimized functions | | | 1936 coroutines: Use cp_build_init_expr consistently. | | | 1937 [Ada] Enable support for atomic primitives on SPARC/Linux | | | 1938 Fix emit_group_store regression on big-endian | | | 1939 RISC-V: Add new line at end of file. | | | 1940 Remove AVX512_VP2INTERSECT from PTA_SAPPHIRERAPIDS | | | 1942 LoongArch: Fixed a bug in the loongarch architecture of libitm package. | | | 1943 [V4] rs6000: cannot_force_const_mem for HIGH code rtx[PR106460] | | | 1945 [COMMITTED] Add default relation_kind to floating point range-op entries. | | | 1948 [COMMITTED] Add an frange(type) constructor analogous to the irange version. | | | 1946 [COMMITTED] Disable tree to bool conversion in frange::update_nan. | | | 1944 [COMMITTED] Add method to query the sign of a NAN. | | | 1947 [COMMITTED] Add stubs for floating point range-op tests. | | | 1949 [(pushed)] regenerate configure files | | | 1950 MAINTAINERS: Add myself for write after approval | | | 1951 [v2] rs6000: Rework option -mpowerpc64 handling [PR106680] | | | 1952 machmode: Introduce GET_MODE_NEXT_MODE with previous GET_MODE_WIDER_MODE meaning, add new GET_MODE_WIDER_MODE | | | 1953 [COMMITTED] gcov: rename gcov_write_summary | | | 1954 Add condition coverage profiling | | | 1955 machmode, v2: Introduce GET_MODE_NEXT_MODE with previous GET_MODE_WIDER_MODE meaning, add new GET_MODE_WIDER_MODE | | | 1956 libgcc: Quote variable in Makefile.in | | | 1957 libgomp: Add offload_device_gcn check, add requires-4a.c test | | | 1958 LoongArch: implement count_{leading,trailing}_zeros | | | 1959 [pushed] c++: defer all consteval in default args [DR2631] | | | 1960 [v2] c++: ICE with VEC_INIT_EXPR and defarg [PR106925] | | | 1961 [committed] libgomp: Fix up creation of artificial teams | | | 1962 [committed] libgomp: Add omp_in_explicit_task support | | | 1963 [committed] libgomp: Fix up OpenMP 5.2 feature bullet | | | 1965 vect: Don't pattern match BITFIELD_REF's of non-integrals [PR107226] | | | 1964 ifcvt: Fix bitpos calculation in bitfield lowering [PR107229] | | | 1966 [COMMITTED] Add range-op entry for floating point NEGATE_EXPR. | | | 1967 xtensa: Add workaround for pSRAM cache issue in ESP32 | | | 1968 [wwwdocs] porting_to: Two-stage overload resolution for implicit move removed | | | 1969 Fortran: simplify array constructors with typespec [PR93483, PR107216, PR107219] | | | 1970 libstdc++: respect with-{headers, newlib} for default hosted value | | | 1971 PR 107189 Remove useless _Alloc_node | | | 1972 [committed] c: Do not use *_IS_IEC_60559 == 2 | | | 1973 Optimize indentical permuation in my last r13-3212-gb88adba751da63 | | | 1974 Optimize identical permutation in my last r13-3212-gb88adba751da63 | | | 1975 middle-end, v3: IFN_ASSUME support [PR106654] | | | 1995 [DOCS] Python Language Conventions | | | 2016 Diagnose return statement in match.pd (with { ... } expressions | | | 2033 Fix bogus -Wstringop-overflow warning | | | 2037 [COMMITTED] Add op1_op2_relation for float operands. | | | 2040 [PR24021] Implement PLUS_EXPR range-op entry for floats. | | | 2049 tree-optimization/107160 - avoid reusing multiple accumulators | | | 2052 tree-optimization/107247 - reduce SLP reduction accumulator | | | 2057 [V1] RISC-V: Fix a redefinition bug for the fd-4.c | | | 2061 use proper DECL_INITIAL for VTV | | | 2073 [COMMITTED,1/4] Add partial equivalence support to the relation oracle. | | | 2074 [COMMITTED,2/4] Add equivalence iterator to relation oracle. | | | 2076 [COMMITTED,3/4] Add partial equivalence recognition to cast and bitwise and. | | | 2075 [COMMITTED,4/4] PR tree-optimization/102540 - propagate partial equivs in the cache. | | | 2077 c++ modules: verify_type failure with typedef enum [PR106848] | | | 2091 c++, v2: Implement excess precision support for C++ [PR107097, PR323] | | | 2094 c++: Excess precision for ? int : float or int == float [PR107097, PR82071, PR87390] | | | 2095 middle-end, c++, i386, libgcc, v2: std::bfloat16_t and __bf16 arithmetic support | | | 2099 testsuite: Fix failure in test pr105586.c [PR107171] | | | 2242 libgomp: Add Fortran testcases for omp_in_explicit_task | | | 2343 c++ modules: ICE with dynamic_cast [PR106304] | | | 2353 [committed] analyzer: fix ICE introduced in r13-3168 [PR107210] | | | 2447 Always enable LRA | | | 2463 [committed] c: C2x storage class specifiers in compound literals | | | 2465 [v2] LoongArch: Optimize the implementation of stack check. | | | 2480 rs6000: Enable const_anchor for 'addi' | | | 2530 [committed] wwwdocs: *: Consistently format around | | | 2550 [1/2] Initial Raptorlake Support | | | 2549 [2/2] Initial Meteorlake Support | | | 2553 [1/6] Support Intel AVX-IFMA | | | 2556 [2/6] Support Intel AVX-VNNI-INT8 | | | 2554 [3/6] i386: Add intrinsic for vector __bf16 | | | 2559 [4/6] Support Intel AVX-NE-CONVERT | | | 2558 [5/6] Support Intel CMPccXADD | | | 2555 [6/6] Initial Sierra Forest Support | | | 2563 Support Intel AMX-FP16 ISA | | | 2571 [1/3] Add a parameter for the builtin function of prefetch to align with LLVM | | | 2570 [2/3] Support Intel prefetchit0/t1 | | | 2583 [1/2] Add a parameter for the builtin function of prefetch to align with LLVM | | | 2582 [2/2] Support Intel prefetchit0/t1 | | | 2600 [committed] libstdc++: Use markdown in Doxygen comment | | | 2629 tree-optimization/107254 - check and support live lanes from permutes | | | 2634 [SPARC] Fix PR target/107248 | | | 2635 [COMMITTED] Add cases for CFN_BUILT_IN_SIGNBIT[FL]. | | | 2653 xtensa: Prepare the transition from Reload to LRA | | | 2696 [og12] amdgcn: Use FLAT addressing for all functions with pointer arguments | | | 2697 [og12] OpenACC: Don't gang-privatize artificial variables | | | 2703 [COMMITTED] Drop -0.0 in frange::set() for !HONOR_SIGNED_ZEROS. | | | 2702 [COMMITTED] Normalize ranges over the range for both bounds when -ffinite-math-only. | | | 2704 [COMMITTED] Replace CFN_BUILTIN_SIGNBIT* cases with CASE_FLT_FN. | | | 2705 Check rvc_normal in real_isdenormal. | | | 2714 [committed] libstdc++: Simplify print_raw function for debug assertions | | | 2715 [committed] libstdc++: Disable all emergency EH pool code if obj-count == 0 | | | 2724 Implement range-op entry for __builtin_copysign. | | | 2754 [committed] gfortran.dg/c-interop/deferred-character-2.f90: Fix dg-do | | | 2756 libgcc: Move cfa_how into potential padding in struct frame_state_reg_info | | | 2757 c++ modules: streaming constexpr_fundef [PR101449] | | | 2759 libgomp: fix hang on fatal error | | | 2784 [committed] wwwdocs: *: Omit trailing slash for CSS references | | | 2859 [v2] RISC-V: Implement __clear_cache via __builtin___clear_cache | | | 2833 Fortran: Fixes for kind=4 characters strings [PR107266] | | | 2889 RISC-V: Reorganize mangle_builtin_type.[NFC] | | | 2890 [committed] preprocessor: C2x identifier rules | | | 2903 [v3] btf: Add support to BTF_KIND_ENUM64 type | | | 2920 libstdc++: Address '-Wunused-function' for 'print_raw' (was: [committed] libstdc++: Simplify print_raw function for debug assertions) | | | 2971 [committed] libstdc++: Fix uses_allocator_construction args for cv pair (LWG 3677) | | | 2972 [committed] libstdc++: Implement constexpr std::to_chars for C++23 (P2291R3) | | | 2979 [committed] Fix bug in register move costing on H8/300 | | | 2998 builtins: Add various __builtin_*f{16,32,64,128,32x,64x,128x} builtins | | | 2999 [RFC] libstdc++, v2: Partial library support for std::float{16,32,64,128}_t | | | 3043 [committed] Rename "Z" constraint on H8/300 to "Zz". | | | 3073 [committed] Add new constraints for upcoming autoinc fixes on the H8 | | | 3142 microblaze: use strverscmp() in MICROBLAZE_VERSION_COMPARE() | | | 3146 Fortran: check type of operands of logical operations, comparisons [PR107272] | | | 3148 Don't print discriminators for -fcompare-debug. | | | 3199 Move scanning pass of forwprop-19.c to dse1 for r13-3212-gb88adba751da63 | | | 3252 RISC-V: Fix format[NFC] | | | 3257 Add 'c-c++-common/torture/pr107195-1.c' [PR107195] (was: [COMMITTED] [PR107195] Set range to zero when nonzero mask is 0.) | | | 3271 RISC-V: Add RVV intrinsic basic framework. | | | 3280 RISC-V: Add RVV vsetvl/vsetvlmax intrinsics and tests. | | | 3295 libgcc: Special-case BFD ld unwind table encodings in find_fde_tail | | | 3408 Fix nvptx-specific '-foffload-options' syntax in 'libgomp.c/reverse-offload-sm30.c' (was: [Patch] nvptx/mkoffload.cc: Warn instead of error when reverse offload is not possible) | | | 3411 Tag 'gcc/gimple-expr.cc:mark_addressable_2' as 'static' (was: [PR67891] drop is_gimple_reg test from set_parm_rtl) | | | 3423 GCN: Restore build with GCC 4.8 (was: [committed 1/6] amdgcn: add multiple vector sizes) | | | 3434 libgcc: Mostly vectorize CIE encoding extraction for FDEs | | | 3456 [COMMITTED] Don't set useless relations. | | | 3457 [COMMITTED] Fix nan updating in range-ops. | | | 3458 [COMMITTED] Add relation_trio class for range-ops. | | | 3459 [COMMITTED] Add 3 floating NAN tests. | | | 3462 [COMMITTED] Do not test for -Inf when flag_finite_math_only. | | | 3464 [COMMITTED,PR10582] Add test. | | | 3484 i386: Allow setting target attribute from conditional expression | | | 3572 middle-end, v4: IFN_ASSUME support [PR106654] | | | 3589 libstdc++, v3: Partial library support for std::float{16,32,64,128}_t and std::bfloat16_t | | | 3590 libstdc++: Redefine __from_chars_alnum_to_val's table | | | 3648 d: Remove D-specific version definitions from target headers | | | 3656 [COMMITTED] Make sure exported range for SSA post-dominates the DEF in set_global_ranges_from_unreachable_edges. | | | 3696 libstdc++: Implement ranges::stride_view from P1899R3 | | | 3824 [committed] Add missing splitter for H8 | | | 3827 [committed] Enable REE for H8 | | | 3828 [committed] More infrastructure to avoid bogus RTL on H8 | | | 3832 [committed,PR,target/101697] Fix bogus RTL on the H8 | | | 3859 [COMMITTED] PR tree-optimization/107273 - Merge partial relation precisions properly. | | | 3913 [v2] xtensa: Prepare the transition from Reload to LRA | | | 4008 tree-optimization/107301 - check if we can duplicate block before doing so | | | 4009 ifcvt: Do not lower bitfields if we can't analyze dr's [PR107275] | | | 4043 [v2] Support Intel AVX-VNNI-INT8 | +------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + git config pull.rebase false + git fetch origin master From github.com:wangliu-iscas/gcc-patch * branch master -> FETCH_HEAD + git checkout master Switched to a new branch 'master' branch 'master' set up to track 'origin/master'. + git pull origin master From github.com:wangliu-iscas/gcc-patch * branch master -> FETCH_HEAD Already up to date. + git fetch origin upstream-master From github.com:wangliu-iscas/gcc-patch * branch upstream-master -> FETCH_HEAD + git checkout upstream-master Switched to a new branch 'upstream-master' branch 'upstream-master' set up to track 'origin/upstream-master'. + git remote add upstream https://github.com/gcc-mirror/gcc.git + git pull upstream master From https://github.com/gcc-mirror/gcc * branch master -> FETCH_HEAD * [new branch] master -> upstream/master Updating e73fe9e16..3b3083a59 Fast-forward gcc/c-family/c-common.cc | 4 + gcc/c/c-decl.cc | 137 ++-- gcc/ipa-cp.cc | 1200 ++++++++++++++++---------------- gcc/ipa-fnsummary.cc | 105 +-- gcc/ipa-prop.cc | 370 ++++------ gcc/ipa-prop.h | 261 +++---- gcc/testsuite/gcc.dg/c11-enum-1.c | 14 + gcc/testsuite/gcc.dg/c11-enum-2.c | 14 + gcc/testsuite/gcc.dg/c11-enum-3.c | 14 + gcc/testsuite/gcc.dg/c2x-enum-1.c | 104 +++ gcc/testsuite/gcc.dg/c2x-enum-2.c | 14 + gcc/testsuite/gcc.dg/c2x-enum-3.c | 14 + gcc/testsuite/gcc.dg/c2x-enum-4.c | 14 + gcc/testsuite/gcc.dg/c2x-enum-5.c | 12 + gcc/testsuite/gcc.dg/ipa/ipcp-agg-11.c | 4 +- gcc/testsuite/gcc.dg/ipa/ipcp-agg-8.c | 4 +- gcc/testsuite/gcc.dg/pr30260.c | 6 +- gcc/testsuite/gcc.dg/torture/pr25183.c | 8 +- 18 files changed, 1222 insertions(+), 1077 deletions(-) create mode 100644 gcc/testsuite/gcc.dg/c11-enum-1.c create mode 100644 gcc/testsuite/gcc.dg/c11-enum-2.c create mode 100644 gcc/testsuite/gcc.dg/c11-enum-3.c create mode 100644 gcc/testsuite/gcc.dg/c2x-enum-1.c create mode 100644 gcc/testsuite/gcc.dg/c2x-enum-2.c create mode 100644 gcc/testsuite/gcc.dg/c2x-enum-3.c create mode 100644 gcc/testsuite/gcc.dg/c2x-enum-4.c create mode 100644 gcc/testsuite/gcc.dg/c2x-enum-5.c + git push -u origin upstream-master To github.com:wangliu-iscas/gcc-patch.git/ e73fe9e16..3b3083a59 upstream-master -> upstream-master branch 'upstream-master' set up to track 'origin/upstream-master'. + git checkout master Switched to branch 'master' Your branch is up to date with 'origin/master'. + git merge upstream-master Updating e73fe9e16..3b3083a59 Fast-forward gcc/c-family/c-common.cc | 4 + gcc/c/c-decl.cc | 137 ++-- gcc/ipa-cp.cc | 1200 ++++++++++++++++---------------- gcc/ipa-fnsummary.cc | 105 +-- gcc/ipa-prop.cc | 370 ++++------ gcc/ipa-prop.h | 261 +++---- gcc/testsuite/gcc.dg/c11-enum-1.c | 14 + gcc/testsuite/gcc.dg/c11-enum-2.c | 14 + gcc/testsuite/gcc.dg/c11-enum-3.c | 14 + gcc/testsuite/gcc.dg/c2x-enum-1.c | 104 +++ gcc/testsuite/gcc.dg/c2x-enum-2.c | 14 + gcc/testsuite/gcc.dg/c2x-enum-3.c | 14 + gcc/testsuite/gcc.dg/c2x-enum-4.c | 14 + gcc/testsuite/gcc.dg/c2x-enum-5.c | 12 + gcc/testsuite/gcc.dg/ipa/ipcp-agg-11.c | 4 +- gcc/testsuite/gcc.dg/ipa/ipcp-agg-8.c | 4 +- gcc/testsuite/gcc.dg/pr30260.c | 6 +- gcc/testsuite/gcc.dg/torture/pr25183.c | 8 +- 18 files changed, 1222 insertions(+), 1077 deletions(-) create mode 100644 gcc/testsuite/gcc.dg/c11-enum-1.c create mode 100644 gcc/testsuite/gcc.dg/c11-enum-2.c create mode 100644 gcc/testsuite/gcc.dg/c11-enum-3.c create mode 100644 gcc/testsuite/gcc.dg/c2x-enum-1.c create mode 100644 gcc/testsuite/gcc.dg/c2x-enum-2.c create mode 100644 gcc/testsuite/gcc.dg/c2x-enum-3.c create mode 100644 gcc/testsuite/gcc.dg/c2x-enum-4.c create mode 100644 gcc/testsuite/gcc.dg/c2x-enum-5.c + git push -u origin master To github.com:wangliu-iscas/gcc-patch.git/ e73fe9e16..3b3083a59 master -> master branch 'master' set up to track 'origin/master'. + branchname=series2532-patch4043 ++ git branch -a ++ grep 'series2532-patch4043$' + checkbranch= + checkbranchresult=null + '[' null = series2532-patch4043 ']' + git checkout -b series2532-patch4043 Switched to a new branch 'series2532-patch4043' ++ curl https://patchwork.plctlab.org/api/1.2/series/2532/ % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 1322 100 1322 0 0 60090 0 --:--:-- --:--:-- --:--:-- 60090 + series_response='{"id":2532,"url":"https://patchwork.plctlab.org/api/1.2/series/2532/","web_url":"https://patchwork.plctlab.org/project/gcc-patch/list/?series=2532","project":{"id":1,"url":"https://patchwork.plctlab.org/api/1.2/projects/1/","name":"gcc-patch","link_name":"gcc-patch","list_id":"gcc-patches.gcc.gnu.org","list_email":"gcc-patches@gcc.gnu.org","web_url":"https://gcc.gnu.org/mailman/listinfo/gcc-patches","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"name":"[v2] Support Intel AVX-VNNI-INT8","date":"2022-10-18T09:10:50","submitter":{"id":113,"url":"https://patchwork.plctlab.org/api/1.2/people/113/","name":"Haochen Jiang","email":"haochen.jiang@intel.com"},"version":2,"total":1,"received_total":1,"received_all":true,"mbox":"https://patchwork.plctlab.org/series/2532/mbox/","cover_letter":null,"patches":[{"id":4043,"url":"https://patchwork.plctlab.org/api/1.2/patches/4043/","web_url":"https://patchwork.plctlab.org/project/gcc-patch/patch/20221018091050.82778-1-haochen.jiang@intel.com/","msgid":"<20221018091050.82778-1-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-18T09:10:50","name":"[v2] Support Intel AVX-VNNI-INT8","mbox":"https://patchwork.plctlab.org/project/gcc-patch/patch/20221018091050.82778-1-haochen.jiang@intel.com/mbox/"}]}' ++ echo '{"id":2532,"url":"https://patchwork.plctlab.org/api/1.2/series/2532/","web_url":"https://patchwork.plctlab.org/project/gcc-patch/list/?series=2532","project":{"id":1,"url":"https://patchwork.plctlab.org/api/1.2/projects/1/","name":"gcc-patch","link_name":"gcc-patch","list_id":"gcc-patches.gcc.gnu.org","list_email":"gcc-patches@gcc.gnu.org","web_url":"https://gcc.gnu.org/mailman/listinfo/gcc-patches","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"name":"[v2] Support Intel AVX-VNNI-INT8","date":"2022-10-18T09:10:50","submitter":{"id":113,"url":"https://patchwork.plctlab.org/api/1.2/people/113/","name":"Haochen Jiang","email":"haochen.jiang@intel.com"},"version":2,"total":1,"received_total":1,"received_all":true,"mbox":"https://patchwork.plctlab.org/series/2532/mbox/","cover_letter":null,"patches":[{"id":4043,"url":"https://patchwork.plctlab.org/api/1.2/patches/4043/","web_url":"https://patchwork.plctlab.org/project/gcc-patch/patch/20221018091050.82778-1-haochen.jiang@intel.com/","msgid":"<20221018091050.82778-1-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-18T09:10:50","name":"[v2] Support Intel AVX-VNNI-INT8","mbox":"https://patchwork.plctlab.org/project/gcc-patch/patch/20221018091050.82778-1-haochen.jiang@intel.com/mbox/"}]}' ++ jq '.patches[] | (.id|tostring) + "," + .mbox' + patchid_patchurl='"4043,https://patchwork.plctlab.org/project/gcc-patch/patch/20221018091050.82778-1-haochen.jiang@intel.com/mbox/"' + echo '"4043,https://patchwork.plctlab.org/project/gcc-patch/patch/20221018091050.82778-1-haochen.jiang@intel.com/mbox/"' + IFS=, + read -r series_patch_id series_patch_url ++ echo '"4043' ++ sed 's/"//g' + series_patch_id=4043 ++ echo 'https://patchwork.plctlab.org/project/gcc-patch/patch/20221018091050.82778-1-haochen.jiang@intel.com/mbox/"' ++ sed 's/"//g' + series_patch_url=https://patchwork.plctlab.org/project/gcc-patch/patch/20221018091050.82778-1-haochen.jiang@intel.com/mbox/ ++ git rev-parse HEAD + commitid_before=3b3083a598ca3f4b6203284e01ed39ab6ff0844f + eval '+++ declare -p bout bret declare -- bout="Applying: Support Intel AVX-VNNI-INT8 error: sha1 information is lacking or useless (gcc/common/config/i386/cpuinfo.h). error: could not build fake ancestor hint: Use '\''git am --show-current-patch=diff'\'' to see the failed patch Patch failed at 0001 Support Intel AVX-VNNI-INT8 When you have resolved this problem, run \"git am --continue\". If you prefer to skip this patch, run \"git am --skip\" instead. To restore the original branch and stop patching, run \"git am --abort\"." declare -- bret="128" ++ berr='\''++++ git_am https://patchwork.plctlab.org/project/gcc-patch/patch/20221018091050.82778-1-haochen.jiang@intel.com/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/gcc-patch/patch/20221018091050.82778-1-haochen.jiang@intel.com/mbox/ ++++ curl https://patchwork.plctlab.org/project/gcc-patch/patch/20221018091050.82778-1-haochen.jiang@intel.com/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 67882 100 67882 0 0 1104k 0 --:--:-- --:--:-- --:--:-- 1104k +++ bout='\''\'\'''\''Applying: Support Intel AVX-VNNI-INT8 error: sha1 information is lacking or useless (gcc/common/config/i386/cpuinfo.h). error: could not build fake ancestor hint: Use '\''\'\'''\''\'\''\'\'''\'''\''\'\'''\''git am --show-current-patch=diff'\''\'\'''\''\'\''\'\'''\'''\''\'\'''\'' to see the failed patch Patch failed at 0001 Support Intel AVX-VNNI-INT8 When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort".'\''\'\'''\'' +++ bret=128'\'' ++ declare -p berr declare -- berr="++++ git_am https://patchwork.plctlab.org/project/gcc-patch/patch/20221018091050.82778-1-haochen.jiang@intel.com/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/gcc-patch/patch/20221018091050.82778-1-haochen.jiang@intel.com/mbox/ ++++ curl https://patchwork.plctlab.org/project/gcc-patch/patch/20221018091050.82778-1-haochen.jiang@intel.com/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 67882 100 67882 0 0 1104k 0 --:--:-- --:--:-- --:--:-- 1104k +++ bout='\''Applying: Support Intel AVX-VNNI-INT8 error: sha1 information is lacking or useless (gcc/common/config/i386/cpuinfo.h). error: could not build fake ancestor hint: Use '\''\\'\'''\''git am --show-current-patch=diff'\''\\'\'''\'' to see the failed patch Patch failed at 0001 Support Intel AVX-VNNI-INT8 When you have resolved this problem, run \"git am --continue\". If you prefer to skip this patch, run \"git am --skip\" instead. To restore the original branch and stop patching, run \"git am --abort\".'\'' +++ bret=128"' ++ +++ declare -p bout bret /tmp/jenkins7548160269218921383.sh: line 115: +++: command not found ++ declare -- 'bout=Applying: Support Intel AVX-VNNI-INT8 error: sha1 information is lacking or useless (gcc/common/config/i386/cpuinfo.h). error: could not build fake ancestor hint: Use '\''git am --show-current-patch=diff'\'' to see the failed patch Patch failed at 0001 Support Intel AVX-VNNI-INT8 When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort".' ++ declare -- bret=128 ++ ++ 'berr=++++ git_am https://patchwork.plctlab.org/project/gcc-patch/patch/20221018091050.82778-1-haochen.jiang@intel.com/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/gcc-patch/patch/20221018091050.82778-1-haochen.jiang@intel.com/mbox/ ++++ curl https://patchwork.plctlab.org/project/gcc-patch/patch/20221018091050.82778-1-haochen.jiang@intel.com/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 67882 100 67882 0 0 1104k 0 --:--:-- --:--:-- --:--:-- 1104k +++ bout='\''Applying: Support Intel AVX-VNNI-INT8 error: sha1 information is lacking or useless (gcc/common/config/i386/cpuinfo.h). error: could not build fake ancestor hint: Use '\''\'\'''\''git am --show-current-patch=diff'\''\'\'''\'' to see the failed patch Patch failed at 0001 Support Intel AVX-VNNI-INT8 When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort".'\'' +++ bret=128' /tmp/jenkins7548160269218921383.sh: line 140: ++: command not found ++ ++ declare -p berr /tmp/jenkins7548160269218921383.sh: line 141: ++: command not found ++ declare -- 'berr=++++ git_am https://patchwork.plctlab.org/project/gcc-patch/patch/20221018091050.82778-1-haochen.jiang@intel.com/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/gcc-patch/patch/20221018091050.82778-1-haochen.jiang@intel.com/mbox/ ++++ curl https://patchwork.plctlab.org/project/gcc-patch/patch/20221018091050.82778-1-haochen.jiang@intel.com/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 67882 100 67882 0 0 1104k 0 --:--:-- --:--:-- --:--:-- 1104k +++ bout='\''Applying: Support Intel AVX-VNNI-INT8 error: sha1 information is lacking or useless (gcc/common/config/i386/cpuinfo.h). error: could not build fake ancestor hint: Use '\''\'\'''\''git am --show-current-patch=diff'\''\'\'''\'' to see the failed patch Patch failed at 0001 Support Intel AVX-VNNI-INT8 When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort".'\'' +++ bret=128' ++ git rev-parse HEAD + commitid_after=3b3083a598ca3f4b6203284e01ed39ab6ff0844f + '[' 128 = 0 ']' + [[ ++++ git_am https://patchwork.plctlab.org/project/gcc-patch/patch/20221018091050.82778-1-haochen.jiang@intel.com/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/gcc-patch/patch/20221018091050.82778-1-haochen.jiang@intel.com/mbox/ ++++ curl https://patchwork.plctlab.org/project/gcc-patch/patch/20221018091050.82778-1-haochen.jiang@intel.com/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 67882 100 67882 0 0 1104k 0 --:--:-- --:--:-- --:--:-- 1104k +++ bout='Applying: Support Intel AVX-VNNI-INT8 error: sha1 information is lacking or useless (gcc/common/config/i386/cpuinfo.h). error: could not build fake ancestor hint: Use '\''git am --show-current-patch=diff'\'' to see the failed patch Patch failed at 0001 Support Intel AVX-VNNI-INT8 When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort".' +++ bret=128 =~ sha1 information is lacking or useless ]] + submit_check warning Unresolved https://patchwork.plctlab.org/jenkins/job/gcc-patch/1372/consoleText 'Git am fail log' + check_state=warning + patch_state=Unresolved + repo_url=https://patchwork.plctlab.org/jenkins/job/gcc-patch/1372/consoleText + DESCRIPTION='Git am fail log' + curl -X POST -H 'Authorization: Token [*******]' -F state=warning -F target_url=https://patchwork.plctlab.org/jenkins/job/gcc-patch/1372/consoleText -F context=gcc-patch-check -F 'description=Git am fail log' https://patchwork.plctlab.org/api/patches/4043/checks/ % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 964 100 424 100 540 8153 10384 --:--:-- --:--:-- --:--:-- 18538 {"id":1089,"url":"https://patchwork.plctlab.org/api/patches/4043/checks/1089/","user":{"id":1,"url":"https://patchwork.plctlab.org/api/users/1/","username":"snail","first_name":"","last_name":"","email":"wangliu@iscas.ac.cn"},"date":"2022-10-18T14:16:07.024071","state":"warning","target_url":"https://patchwork.plctlab.org/jenkins/job/gcc-patch/1372/consoleText","context":"gcc-patch-check","description":"Git am fail log"}+ curl -X PATCH -H 'Authorization: Token [*******]' -F state=Unresolved https://patchwork.plctlab.org/api/1.2/patches/4043/ % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0{"id":4043,"url":"https://patchwork.plctlab.org/api/1.2/patches/4043/","web_url":"https://patchwork.plctlab.org/project/gcc-patch/patch/20221018091050.82778-1-haochen.jiang@intel.com/","project":{"id":1,"url":"https://patchwork.plctlab.org/api/1.2/projects/1/","name":"gcc-patch","link_name":"gcc-patch","list_id":"gcc-patches.gcc.gnu.org","list_email":"gcc-patches@gcc.gnu.org","web_url":"https://gcc.gnu.org/mailman/listinfo/gcc-patches","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20221018091050.82778-1-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-18T09:10:50","name":"[v2] Support Intel AVX-VNNI-INT8","commit_ref":null,"pull_url":null,"state":"unresolved","archived":false,"hash":"67f092bf17e3152a8e9d09e9d20c421681b4f35d","submitter":{"id":113,"url":"https://patchwork.plctlab.org/api/1.2/people/113/","name":"Haochen Jiang","email":"haochen.jiang@intel.com"},"delegate":null,"mbox":"https://patchwork.plctlab.org/project/gcc-patch/patch/20221018091050.82778-1-haochen.jiang@intel.com/mbox/","series":[{"id":2532,"url":"https://patchwork.plctlab.org/api/1.2/series/2532/","web_url":"https://patchwork.plctlab.org/project/gcc-patch/list/?series=2532","date":"2022-10-18T09:10:50","name":"[v2] Support Intel AVX-VNNI-INT8","version":2,"mbox":"https://patchwork.plctlab.org/series/2532/mbox/"}],"comments":"https://patchwork.plctlab.org/api/patches/4043/comments/","check":"warning","checks":"https://patchwork.plctlab.org/api/patches/4043/checks/","tags":{},"headers":{"Return-Path":"","Delivered-To":["ouuuleilei@gmail.com","gcc-patches@gcc.gnu.org"],"Received":["by 2002:a5d:4ac7:0:0:0:0:0 with SMTP id y7csp1853567wrs;\n Tue, 18 Oct 2022 02:14:19 -0700 (PDT)","from sourceware.org (ip-8-43-85-97.sourceware.org. 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c=relaxed/relaxed; d=gcc.gnu.org;\n\ts=default; t=1666084443;\n\tbh=hpzqxTOOpnoji4c6Hlf9YSY43lKxV4FuJu0zc72lWQM=;\n\th=To:Subject:Date:In-Reply-To:References:List-Id:List-Unsubscribe:\n\t List-Archive:List-Post:List-Help:List-Subscribe:From:Reply-To:Cc:\n\t From;\n\tb=xOR2pB7CMLps1fcF3+7uwioEEZJLhlojnCD1M0sozrcqA9MEZZivqcPZL1ohux7OP\n\t MVrtjqNd7G/uYxY9Ew933hMLTsQzDPETTXWor81x1S/5+RjkC+MqFhKmARaq8vsTB8\n\t B9XHIlWTteS5RFI4NoZKjB+ZhNSeNLIj6egzCfbc=","X-Original-To":"gcc-patches@gcc.gnu.org","DMARC-Filter":"OpenDMARC Filter v1.4.1 sourceware.org 388A53858D3C","X-IronPort-AV":["E=McAfee;i=\"6500,9779,10503\"; a=\"307133442\"","E=Sophos;i=\"5.95,193,1661842800\"; d=\"scan'208\";a=\"307133442\"","E=McAfee;i=\"6500,9779,10503\"; a=\"631031290\"","E=Sophos;i=\"5.95,193,1661842800\"; d=\"scan'208\";a=\"631031290\""],"X-ExtLoop1":"1","To":"gcc-patches@gcc.gnu.org","Subject":"[PATCH v2] Support Intel AVX-VNNI-INT8","Date":"Tue, 18 Oct 2022 17:10:50 +0800","Message-Id":"<20221018091050.82778-1-haochen.jiang@intel.com>","X-Mailer":"git-send-email 2.18.1","In-Reply-To":"\n ","References":"\n ","X-Spam-Status":"No, score=-11.5 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH,\n DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0,\n KAM_NUMSUBJECT, KAM_SHORT, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL,\n SPF_HELO_NONE,\n SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6","X-Spam-Checker-Version":"SpamAssassin 3.4.6 (2021-04-09) on\n server2.sourceware.org","X-BeenThere":"gcc-patches@gcc.gnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"Gcc-patches mailing list ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","From":"Haochen Jiang via Gcc-patches ","Reply-To":"Haochen Jiang ","Cc":"hongtao.liu@intel.com","Errors-To":"gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org","Sender":"\"Gcc-patches\" ","X-getmail-retrieved-from-mailbox":"=?utf-8?q?INBOX?=","X-GMAIL-THRID":"=?utf-8?q?1746648984697081656?=","X-GMAIL-MSGID":"=?utf-8?q?1747016177358067374?="},"content":"From: Kong Lingling \n\nHi all,\n\nThis is our v2 patch on AVX-VNNI-INT8. This main change in this patch is to\nrename the previous UNSPEC_VPMADDxxx things to new vnni style.\n\nOk for trunk?\n\nBRs,\nHaochen\n\ngcc/ChangeLog\n\n\t* common/config/i386/cpuinfo.h (get_available_features): Detect\n\tavxvnniint8.\n\t* common/config/i386/i386-common.cc\n\t(OPTION_MASK_ISA2_AVXVNNIINT8_SET): New.\n\t(OPTION_MASK_ISA2_AVXVNNIINT8_UNSET): Ditto.\n\t(ix86_handle_option): Handle -mavxvnniint8.\n\t* common/config/i386/i386-cpuinfo.h (enum processor_features):\n\tAdd FEATURE_AVXVNNIINT8.\n\t* common/config/i386/i386-isas.h: Add ISA_NAME_TABLE_ENTRY for\n\tavxvnniint8.\n\t* config.gcc: Add avxvnniint8intrin.h.\n\t* config/i386/avxvnniint8intrin.h: New file.\n\t* config/i386/cpuid.h (bit_AVXVNNIINT8): New.\n\t* config/i386/i386-builtin.def: Add new builtins.\n\t* config/i386/i386-c.cc (ix86_target_macros_internal): Define\n\t__AVXVNNIINT8__.\n\t* config/i386/i386-options.cc (isa2_opts): Add -mavxvnniint8.\n\t(ix86_valid_target_attribute_inner_p): Handle avxvnniint8.\n\t* config/i386/i386-isa.def: Add DEF_PTA(AVXVNNIINT8) New..\n\t* config/i386/i386.opt: Add option -mavxvnniint8.\n\t* config/i386/immintrin.h: Include avxvnniint8intrin.h.\n\t* config/i386/sse.md (UNSPEC_VPMADDUBSWACCD\n\tUNSPEC_VPMADDUBSWACCSSD,UNSPEC_VPMADDWDACCD,\n\tUNSPEC_VPMADDWDACCSSD): Rename according to new style.\n\t(vpdp_): New define_insn.\n\t* doc/extend.texi: Document avxvnniint8.\n\t* doc/invoke.texi: Document -mavxvnniint8.\n\t* doc/sourcebuild.texi: Document target avxvnniint8.\n\ngcc/testsuite/ChangeLog\n\n\t* g++.dg/other/i386-2.C: Add -mavxvnniint8.\n\t* g++.dg/other/i386-3.C: Ditto.\n\t* gcc.target/i386/avx-check.h: Add avxvnniint8 check.\n\t* gcc.target/i386/sse-12.c: Add -mavxvnniint8.\n\t* gcc.target/i386/sse-13.c: Ditto.\n\t* gcc.target/i386/sse-14.c: Ditto.\n\t* gcc.target/i386/sse-22.c: Ditto.\n\t* gcc.target/i386/sse-23.c: Ditto.\n\t* gcc.target/i386/funcspec-56.inc: Add new target attribute.\n\t* lib/target-supports.exp\n\t(check_effective_target_avxvnniint8): New.\n\t* gcc.target/i386/avxvnniint8-1.c: Ditto.\n\t* gcc.target/i386/avxvnniint8-vpdpbssd-2.c: Ditto.\n\t* gcc.target/i386/avxvnniint8-vpdpbssds-2.c: Ditto.\n\t* gcc.target/i386/avxvnniint8-vpdpbsud-2.c: Ditto.\n\t* gcc.target/i386/avxvnniint8-vpdpbsuds-2.c: Ditto.\n\t* gcc.target/i386/avxvnniint8-vpdpbuud-2.c: Ditto.\n\t* gcc.target/i386/avxvnniint8-vpdpbuuds-2.c: Ditto.\n\nCo-authored-by: Hongyu Wang \nCo-authored-by: Haochen Jiang \n---\n gcc/common/config/i386/cpuinfo.h | 2 +\n gcc/common/config/i386/i386-common.cc | 22 ++-\n gcc/common/config/i386/i386-cpuinfo.h | 1 +\n gcc/common/config/i386/i386-isas.h | 2 +\n gcc/config.gcc | 2 +-\n gcc/config/i386/avxvnniint8intrin.h | 138 ++++++++++++++++++\n gcc/config/i386/cpuid.h | 1 +\n gcc/config/i386/i386-builtin.def | 14 ++\n gcc/config/i386/i386-c.cc | 2 +\n gcc/config/i386/i386-isa.def | 1 +\n gcc/config/i386/i386-options.cc | 4 +-\n gcc/config/i386/i386.opt | 5 +\n gcc/config/i386/immintrin.h | 2 +\n gcc/config/i386/sse.md | 71 ++++++---\n gcc/doc/extend.texi | 5 +\n gcc/doc/invoke.texi | 9 +-\n gcc/doc/sourcebuild.texi | 3 +\n gcc/testsuite/g++.dg/other/i386-2.C | 2 +-\n gcc/testsuite/g++.dg/other/i386-3.C | 2 +-\n gcc/testsuite/gcc.target/i386/avx-check.h | 3 +\n gcc/testsuite/gcc.target/i386/avxvnniint8-1.c | 43 ++++++\n .../gcc.target/i386/avxvnniint8-vpdpbssd-2.c | 72 +++++++++\n .../gcc.target/i386/avxvnniint8-vpdpbssds-2.c | 72 +++++++++\n .../gcc.target/i386/avxvnniint8-vpdpbsud-2.c | 72 +++++++++\n .../gcc.target/i386/avxvnniint8-vpdpbsuds-2.c | 72 +++++++++\n .../gcc.target/i386/avxvnniint8-vpdpbuud-2.c | 72 +++++++++\n .../gcc.target/i386/avxvnniint8-vpdpbuuds-2.c | 72 +++++++++\n gcc/testsuite/gcc.target/i386/funcspec-56.inc | 2 +\n gcc/testsuite/gcc.target/i386/sse-12.c | 2 +-\n gcc/testsuite/gcc.target/i386/sse-13.c | 2 +-\n gcc/testsuite/gcc.target/i386/sse-14.c | 2 +-\n gcc/testsuite/gcc.target/i386/sse-22.c | 4 +-\n gcc/testsuite/gcc.target/i386/sse-23.c | 2 +-\n gcc/testsuite/lib/target-supports.exp | 12 ++\n 34 files changed, 758 insertions(+), 34 deletions(-)\n create mode 100644 gcc/config/i386/avxvnniint8intrin.h\n create mode 100644 gcc/testsuite/gcc.target/i386/avxvnniint8-1.c\n create mode 100644 gcc/testsuite/gcc.target/i386/avxvnniint8-vpdpbssd-2.c\n create mode 100644 gcc/testsuite/gcc.target/i386/avxvnniint8-vpdpbssds-2.c\n create mode 100644 gcc/testsuite/gcc.target/i386/avxvnniint8-vpdpbsud-2.c\n create mode 100644 gcc/testsuite/gcc.target/i386/avxvnniint8-vpdpbsuds-2.c\n create mode 100644 gcc/testsuite/gcc.target/i386/avxvnniint8-vpdpbuud-2.c\n create mode 100644 gcc/testsuite/gcc.target/i386/avxvnniint8-vpdpbuuds-2.c","diff":"diff --git a/gcc/common/config/i386/cpuinfo.h b/gcc/common/config/i386/cpuinfo.h\nindex 9bb21c6cacc..bed88003f8e 100644\n--- a/gcc/common/config/i386/cpuinfo.h\n+++ b/gcc/common/config/i386/cpuinfo.h\n@@ -795,6 +795,8 @@ get_available_features (struct __processor_model *cpu_model,\n \t set_feature (FEATURE_AVXVNNI);\n \t if (eax & bit_AVXIFMA)\n \t set_feature (FEATURE_AVXIFMA);\n+\t if (edx & bit_AVXVNNIINT8)\n+\t set_feature (FEATURE_AVXVNNIINT8);\n \t}\n if (avx512_usable)\n \t{\ndiff --git a/gcc/common/config/i386/i386-common.cc b/gcc/common/config/i386/i386-common.cc\nindex 4de7906b247..6a2a7e3d25a 100644\n--- a/gcc/common/config/i386/i386-common.cc\n+++ b/gcc/common/config/i386/i386-common.cc\n@@ -108,6 +108,7 @@ along with GCC; see the file COPYING3. If not see\n #define OPTION_MASK_ISA2_AMX_TILE_SET OPTION_MASK_ISA2_AMX_TILE\n #define OPTION_MASK_ISA2_AMX_INT8_SET OPTION_MASK_ISA2_AMX_INT8\n #define OPTION_MASK_ISA2_AMX_BF16_SET OPTION_MASK_ISA2_AMX_BF16\n+#define OPTION_MASK_ISA2_AVXVNNIINT8_SET OPTION_MASK_ISA2_AVXVNNIINT8\n \n /* SSE4 includes both SSE4.1 and SSE4.2. -msse4 should be the same\n as -msse4.2. */\n@@ -214,7 +215,7 @@ along with GCC; see the file COPYING3. If not see\n (OPTION_MASK_ISA_AVX2 | OPTION_MASK_ISA_AVX512F_UNSET)\n #define OPTION_MASK_ISA2_AVX2_UNSET \\\n (OPTION_MASK_ISA2_AVXIFMA_UNSET | OPTION_MASK_ISA2_AVXVNNI_UNSET \\\n- | OPTION_MASK_ISA2_AVX512F_UNSET)\n+ | OPTION_MASK_ISA2_AVXVNNIINT8_UNSET | OPTION_MASK_ISA2_AVX512F_UNSET)\n #define OPTION_MASK_ISA_AVX512F_UNSET \\\n (OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_AVX512CD_UNSET \\\n | OPTION_MASK_ISA_AVX512PF_UNSET | OPTION_MASK_ISA_AVX512ER_UNSET \\\n@@ -278,6 +279,7 @@ along with GCC; see the file COPYING3. If not see\n #define OPTION_MASK_ISA2_KL_UNSET \\\n (OPTION_MASK_ISA2_KL | OPTION_MASK_ISA2_WIDEKL_UNSET)\n #define OPTION_MASK_ISA2_WIDEKL_UNSET OPTION_MASK_ISA2_WIDEKL\n+#define OPTION_MASK_ISA2_AVXVNNIINT8_UNSET OPTION_MASK_ISA2_AVXVNNIINT8\n \n /* SSE4 includes both SSE4.1 and SSE4.2. -mno-sse4 should the same\n as -mno-sse4.1. */\n@@ -1142,6 +1144,24 @@ ix86_handle_option (struct gcc_options *opts,\n \t}\n return true;\n \n+ case OPT_mavxvnniint8:\n+ if (value)\n+\t{\n+\t opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AVXVNNIINT8_SET;\n+\t opts->x_ix86_isa_flags2_explicit |=\n+\t OPTION_MASK_ISA2_AVXVNNIINT8_SET;\n+\t opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX2_SET;\n+\t opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX2_SET;\n+\t}\n+ else\n+\t{\n+\t opts->x_ix86_isa_flags2 &=\n+\t ~OPTION_MASK_ISA2_AVXVNNIINT8_UNSET;\n+\t opts->x_ix86_isa_flags2_explicit |=\n+\t OPTION_MASK_ISA2_AVXVNNIINT8_UNSET;\n+\t}\n+ return true;\n+\n case OPT_mfma:\n if (value)\n \t{\ndiff --git a/gcc/common/config/i386/i386-cpuinfo.h b/gcc/common/config/i386/i386-cpuinfo.h\nindex 968f9a56a6c..9a6b92fab79 100644\n--- a/gcc/common/config/i386/i386-cpuinfo.h\n+++ b/gcc/common/config/i386/i386-cpuinfo.h\n@@ -241,6 +241,7 @@ enum processor_features\n FEATURE_X86_64_V3,\n FEATURE_X86_64_V4,\n FEATURE_AVXIFMA,\n+ FEATURE_AVXVNNIINT8,\n CPU_FEATURE_MAX\n };\n \ndiff --git a/gcc/common/config/i386/i386-isas.h b/gcc/common/config/i386/i386-isas.h\nindex b05b4bb8f0d..8c1f351056c 100644\n--- a/gcc/common/config/i386/i386-isas.h\n+++ b/gcc/common/config/i386/i386-isas.h\n@@ -176,4 +176,6 @@ ISA_NAMES_TABLE_START\n ISA_NAMES_TABLE_ENTRY(\"x86-64-v3\", FEATURE_X86_64_V3, P_X86_64_V3, NULL)\n ISA_NAMES_TABLE_ENTRY(\"x86-64-v4\", FEATURE_X86_64_V4, P_X86_64_V4, NULL)\n ISA_NAMES_TABLE_ENTRY(\"avxifma\", FEATURE_AVXIFMA, P_NONE, \"-mavxifma\")\n+ ISA_NAMES_TABLE_ENTRY(\"avxvnniint8\", FEATURE_AVXVNNIINT8,\n+\t\t\tP_NONE, \"-mavxvnniint8\")\n ISA_NAMES_TABLE_END\ndiff --git a/gcc/config.gcc b/gcc/config.gcc\nindex d086dbdf8fb..3f7804a54b7 100644\n--- a/gcc/config.gcc\n+++ b/gcc/config.gcc\n@@ -422,7 +422,7 @@ i[34567]86-*-* | x86_64-*-*)\n \t\t amxbf16intrin.h x86gprintrin.h uintrintrin.h\n \t\t hresetintrin.h keylockerintrin.h avxvnniintrin.h\n \t\t mwaitintrin.h avx512fp16intrin.h avx512fp16vlintrin.h\n-\t\t avxifmaintrin.h\"\n+\t\t avxifmaintrin.h avxvnniint8intrin.h\"\n \t;;\n ia64-*-*)\n \textra_headers=ia64intrin.h\ndiff --git a/gcc/config/i386/avxvnniint8intrin.h b/gcc/config/i386/avxvnniint8intrin.h\nnew file mode 100644\nindex 00000000000..362e6f65c2a\n--- /dev/null\n+++ b/gcc/config/i386/avxvnniint8intrin.h\n@@ -0,0 +1,138 @@\n+/* Copyright (C) 2020 Free Software Foundation, Inc.\n+\n+ This file is part of GCC.\n+\n+ GCC is free software; you can redistribute it and/or modify\n+ it under the terms of the GNU General Public License as published by\n+ the Free Software Foundation; either version 3, or (at your option)\n+ any later version.\n+\n+ GCC is distributed in the hope that it will be useful,\n+ but WITHOUT ANY WARRANTY; without even the implied warranty of\n+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n+ GNU General Public License for more details.\n+\n+ Under Section 7 of GPL version 3, you are granted additional\n+ permissions described in the GCC Runtime Library Exception, version\n+ 3.1, as published by the Free Software Foundation.\n+\n+ You should have received a copy of the GNU General Public License and\n+ a copy of the GCC Runtime Library Exception along with this program;\n+ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see\n+ . */\n+\n+#if !defined _IMMINTRIN_H_INCLUDED\n+#error \"Never use directly; include instead.\"\n+#endif\n+\n+#ifndef _AVXVNNIINT8INTRIN_H_INCLUDED\n+#define _AVXVNNIINT8INTRIN_H_INCLUDED\n+\n+#if !defined(__AVXVNNIINT8__)\n+#pragma GCC push_options\n+#pragma GCC target(\"avxvnniint8\")\n+#define __DISABLE_AVXVNNIINT8__\n+#endif /* __AVXVNNIINT8__ */\n+\n+extern __inline __m128i\n+__attribute__((__gnu_inline__, __always_inline__, __artificial__))\n+_mm_dpbssd_epi32 (__m128i __W, __m128i __A, __m128i __B)\n+{\n+ return (__m128i)\n+ __builtin_ia32_vpdpbssd128 ((__v4si) __W, (__v4si) __A, (__v4si) __B);\n+}\n+\n+extern __inline __m128i\n+__attribute__((__gnu_inline__, __always_inline__, __artificial__))\n+_mm_dpbssds_epi32 (__m128i __W, __m128i __A, __m128i __B)\n+{\n+ return (__m128i)\n+ __builtin_ia32_vpdpbssds128 ((__v4si) __W, (__v4si) __A, (__v4si) __B);\n+}\n+\n+extern __inline __m128i\n+__attribute__((__gnu_inline__, __always_inline__, __artificial__))\n+_mm_dpbsud_epi32 (__m128i __W, __m128i __A, __m128i __B)\n+{\n+ return (__m128i)\n+ __builtin_ia32_vpdpbsud128 ((__v4si) __W, (__v4si) __A, (__v4si) __B);\n+}\n+\n+extern __inline __m128i\n+__attribute__((__gnu_inline__, __always_inline__, __artificial__))\n+_mm_dpbsuds_epi32 (__m128i __W, __m128i __A, __m128i __B)\n+{\n+ return (__m128i)\n+ __builtin_ia32_vpdpbsuds128 ((__v4si) __W, (__v4si) __A, (__v4si) __B);\n+}\n+\n+extern __inline __m128i\n+__attribute__((__gnu_inline__, __always_inline__, __artificial__))\n+_mm_dpbuud_epi32 (__m128i __W, __m128i __A, __m128i __B)\n+{\n+ return (__m128i)\n+ __builtin_ia32_vpdpbuud128 ((__v4si) __W, (__v4si) __A, (__v4si) __B);\n+}\n+\n+extern __inline __m128i\n+__attribute__((__gnu_inline__, __always_inline__, __artificial__))\n+_mm_dpbuuds_epi32 (__m128i __W, __m128i __A, __m128i __B)\n+{\n+ return (__m128i)\n+ __builtin_ia32_vpdpbuuds128 ((__v4si) __W, (__v4si) __A, (__v4si) __B);\n+}\n+\n+extern __inline __m256i\n+__attribute__((__gnu_inline__, __always_inline__, __artificial__))\n+_mm256_dpbssd_epi32 (__m256i __W, __m256i __A, __m256i __B)\n+{\n+ return (__m256i)\n+ __builtin_ia32_vpdpbssd256 ((__v8si) __W, (__v8si) __A, (__v8si) __B);\n+}\n+\n+extern __inline __m256i\n+__attribute__((__gnu_inline__, __always_inline__, __artificial__))\n+_mm256_dpbssds_epi32 (__m256i __W, __m256i __A, __m256i __B)\n+{\n+ return (__m256i)\n+ __builtin_ia32_vpdpbssds256 ((__v8si) __W, (__v8si) __A, (__v8si) __B);\n+}\n+\n+extern __inline __m256i\n+__attribute__((__gnu_inline__, __always_inline__, __artificial__))\n+_mm256_dpbsud_epi32 (__m256i __W, __m256i __A, __m256i __B)\n+{\n+ return (__m256i)\n+ __builtin_ia32_vpdpbsud256 ((__v8si) __W, (__v8si) __A, (__v8si) __B);\n+}\n+\n+extern __inline __m256i\n+__attribute__((__gnu_inline__, __always_inline__, __artificial__))\n+_mm256_dpbsuds_epi32 (__m256i __W, __m256i __A, __m256i __B)\n+{\n+ return (__m256i)\n+ __builtin_ia32_vpdpbsuds256 ((__v8si) __W, (__v8si) __A, (__v8si) __B);\n+}\n+\n+extern __inline __m256i\n+__attribute__((__gnu_inline__, __always_inline__, __artificial__))\n+_mm256_dpbuud_epi32 (__m256i __W, __m256i __A, __m256i __B)\n+{\n+ return (__m256i)\n+ __builtin_ia32_vpdpbuud256 ((__v8si) __W, (__v8si) __A, (__v8si) __B);\n+}\n+\n+extern __inline __m256i\n+__attribute__((__gnu_inline__, __always_inline__, __artificial__))\n+_mm256_dpbuuds_epi32 (__m256i __W, __m256i __A, __m256i __B)\n+{\n+ return (__m256i)\n+ __builtin_ia32_vpdpbuuds256 ((__v8si) __W, (__v8si) __A, (__v8si) __B);\n+}\n+\n+#ifdef __DISABLE_AVXVNNIINT8__\n+#undef __DISABLE_AVXVNNIINT8__\n+#pragma GCC pop_options\n+#endif /* __DISABLE_AVXVNNIINT8__ */\n+\n+#endif /* __AVXVNNIINT8INTRIN_H_INCLUDED */\ndiff --git a/gcc/config/i386/cpuid.h b/gcc/config/i386/cpuid.h\nindex 9885699efd5..f5fad22149a 100644\n--- a/gcc/config/i386/cpuid.h\n+++ b/gcc/config/i386/cpuid.h\n@@ -49,6 +49,7 @@\n #define bit_RDRND\t(1 << 30)\n \n /* %edx */\n+#define bit_AVXVNNIINT8 (1 << 4)\n #define bit_CMPXCHG8B\t(1 << 8)\n #define bit_CMOV\t(1 << 15)\n #define bit_MMX\t\t(1 << 23)\ndiff --git a/gcc/config/i386/i386-builtin.def b/gcc/config/i386/i386-builtin.def\nindex 4a89099a00f..e6edae5728b 100644\n--- a/gcc/config/i386/i386-builtin.def\n+++ b/gcc/config/i386/i386-builtin.def\n@@ -2696,6 +2696,20 @@ BDESC (OPTION_MASK_ISA_AVX512VNNI | OPTION_MASK_ISA_AVX512VL, OPTION_MASK_ISA2_A\n BDESC (OPTION_MASK_ISA_AVX512VNNI | OPTION_MASK_ISA_AVX512VL, 0, CODE_FOR_vpdpwssds_v4si_mask, \"__builtin_ia32_vpdpwssds_v4si_mask\", IX86_BUILTIN_VPDPWSSDSV4SI_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_UQI)\n BDESC (OPTION_MASK_ISA_AVX512VNNI | OPTION_MASK_ISA_AVX512VL, 0, CODE_FOR_vpdpwssds_v4si_maskz, \"__builtin_ia32_vpdpwssds_v4si_maskz\", IX86_BUILTIN_VPDPWSSDSV4SI_MASKZ, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_UQI)\n \n+/* AVXVNNIINT8 */\n+BDESC (0, OPTION_MASK_ISA2_AVXVNNIINT8, CODE_FOR_vpdpbssd_v8si, \"__builtin_ia32_vpdpbssd256\", IX86_BUILTIN_VPDPBSSDV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI)\n+BDESC (0, OPTION_MASK_ISA2_AVXVNNIINT8, CODE_FOR_vpdpbssds_v8si, \"__builtin_ia32_vpdpbssds256\", IX86_BUILTIN_VPDPBSSDSV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI)\n+BDESC (0, OPTION_MASK_ISA2_AVXVNNIINT8, CODE_FOR_vpdpbsud_v8si, \"__builtin_ia32_vpdpbsud256\", IX86_BUILTIN_VPDPBSUDV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI)\n+BDESC (0, OPTION_MASK_ISA2_AVXVNNIINT8, CODE_FOR_vpdpbsuds_v8si, \"__builtin_ia32_vpdpbsuds256\", IX86_BUILTIN_VPDPBSUDSV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI)\n+BDESC (0, OPTION_MASK_ISA2_AVXVNNIINT8, CODE_FOR_vpdpbuud_v8si, \"__builtin_ia32_vpdpbuud256\", IX86_BUILTIN_VPDPBUUDV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI)\n+BDESC (0, OPTION_MASK_ISA2_AVXVNNIINT8, CODE_FOR_vpdpbuuds_v8si, \"__builtin_ia32_vpdpbuuds256\", IX86_BUILTIN_VPDPBUUDSV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI)\n+BDESC (0, OPTION_MASK_ISA2_AVXVNNIINT8, CODE_FOR_vpdpbssd_v4si, \"__builtin_ia32_vpdpbssd128\", IX86_BUILTIN_VPDPBSSDV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI)\n+BDESC (0, OPTION_MASK_ISA2_AVXVNNIINT8, CODE_FOR_vpdpbssds_v4si, \"__builtin_ia32_vpdpbssds128\", IX86_BUILTIN_VPDPBSSDSV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI)\n+BDESC (0, OPTION_MASK_ISA2_AVXVNNIINT8, CODE_FOR_vpdpbsud_v4si, \"__builtin_ia32_vpdpbsud128\", IX86_BUILTIN_VPDPBSUDV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI)\n+BDESC (0, OPTION_MASK_ISA2_AVXVNNIINT8, CODE_FOR_vpdpbsuds_v4si, \"__builtin_ia32_vpdpbsuds128\", IX86_BUILTIN_VPDPBSUDSV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI)\n+BDESC (0, OPTION_MASK_ISA2_AVXVNNIINT8, CODE_FOR_vpdpbuud_v4si, \"__builtin_ia32_vpdpbuud128\", IX86_BUILTIN_VPDPBUUDV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI)\n+BDESC (0, OPTION_MASK_ISA2_AVXVNNIINT8, CODE_FOR_vpdpbuuds_v4si, \"__builtin_ia32_vpdpbuuds128\", IX86_BUILTIN_VPDPBUUDSV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI)\n+\n /* VPCLMULQDQ */\n BDESC (OPTION_MASK_ISA_VPCLMULQDQ | OPTION_MASK_ISA_AVX512VL, 0, CODE_FOR_vpclmulqdq_v2di, \"__builtin_ia32_vpclmulqdq_v2di\", IX86_BUILTIN_VPCLMULQDQ2, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT)\n BDESC (OPTION_MASK_ISA_VPCLMULQDQ | OPTION_MASK_ISA_AVX, 0, CODE_FOR_vpclmulqdq_v4di, \"__builtin_ia32_vpclmulqdq_v4di\", IX86_BUILTIN_VPCLMULQDQ4, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_INT)\ndiff --git a/gcc/config/i386/i386-c.cc b/gcc/config/i386/i386-c.cc\nindex 3494ec035d5..a9a35c0a18a 100644\n--- a/gcc/config/i386/i386-c.cc\n+++ b/gcc/config/i386/i386-c.cc\n@@ -635,6 +635,8 @@ ix86_target_macros_internal (HOST_WIDE_INT isa_flag,\n def_or_undef (parse_in, \"__AVXVNNI__\");\n if (isa_flag2 & OPTION_MASK_ISA2_AVXIFMA)\n def_or_undef (parse_in, \"__AVXIFMA__\");\n+ if (isa_flag2 & OPTION_MASK_ISA2_AVXVNNIINT8)\n+ def_or_undef (parse_in, \"__AVXVNNIINT8__\");\n if (TARGET_IAMCU)\n {\n def_or_undef (parse_in, \"__iamcu\");\ndiff --git a/gcc/config/i386/i386-isa.def b/gcc/config/i386/i386-isa.def\nindex 6e0254ce418..c95b917c6ce 100644\n--- a/gcc/config/i386/i386-isa.def\n+++ b/gcc/config/i386/i386-isa.def\n@@ -110,3 +110,4 @@ DEF_PTA(WIDEKL)\n DEF_PTA(AVXVNNI)\n DEF_PTA(AVX512FP16)\n DEF_PTA(AVXIFMA)\n+DEF_PTA(AVXVNNIINT8)\ndiff --git a/gcc/config/i386/i386-options.cc b/gcc/config/i386/i386-options.cc\nindex 5facb64c2a8..3e6d04433a6 100644\n--- a/gcc/config/i386/i386-options.cc\n+++ b/gcc/config/i386/i386-options.cc\n@@ -227,7 +227,8 @@ static struct ix86_target_opts isa2_opts[] =\n { \"-mwidekl\", \tOPTION_MASK_ISA2_WIDEKL },\n { \"-mavxvnni\",\tOPTION_MASK_ISA2_AVXVNNI },\n { \"-mavx512fp16\",\tOPTION_MASK_ISA2_AVX512FP16 },\n- { \"-mavxifma\",\tOPTION_MASK_ISA2_AVXIFMA }\n+ { \"-mavxifma\",\tOPTION_MASK_ISA2_AVXIFMA },\n+ { \"-mavxvnniint8\",\tOPTION_MASK_ISA2_AVXVNNIINT8 }\n };\n static struct ix86_target_opts isa_opts[] =\n {\n@@ -1074,6 +1075,7 @@ ix86_valid_target_attribute_inner_p (tree fndecl, tree args, char *p_strings[],\n IX86_ATTR_ISA (\"avxvnni\", OPT_mavxvnni),\n IX86_ATTR_ISA (\"avx512fp16\", OPT_mavx512fp16),\n IX86_ATTR_ISA (\"avxifma\", OPT_mavxifma),\n+ IX86_ATTR_ISA (\"avxvnniint8\", OPT_mavxvnniint8),\n \n /* enum options */\n IX86_ATTR_ENUM (\"fpmath=\",\tOPT_mfpmath_),\ndiff --git a/gcc/config/i386/i386.opt b/gcc/config/i386/i386.opt\nindex 36e28b7063d..53d534f6392 100644\n--- a/gcc/config/i386/i386.opt\n+++ b/gcc/config/i386/i386.opt\n@@ -1219,3 +1219,8 @@ mavxifma\n Target Mask(ISA2_AVXIFMA) Var(ix86_isa_flags2) Save\n Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, and\n AVXIFMA built-in functions and code generation.\n+\n+mavxvnniint8\n+Target Mask(ISA2_AVXVNNIINT8) Var(ix86_isa_flags2) Save\n+Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and\n+AVXVNNIINT8 built-in functions and code generation.\ndiff --git a/gcc/config/i386/immintrin.h b/gcc/config/i386/immintrin.h\nindex e9d4e975243..ddea249d09b 100644\n--- a/gcc/config/i386/immintrin.h\n+++ b/gcc/config/i386/immintrin.h\n@@ -46,6 +46,8 @@\n \n #include \n \n+#include \n+\n #include \n \n #include \ndiff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md\nindex 331347569ea..6513d189b09 100644\n--- a/gcc/config/i386/sse.md\n+++ b/gcc/config/i386/sse.md\n@@ -166,10 +166,10 @@\n UNSPEC_VPSHLDV\n \n ;; For AVX512VNNI support\n- UNSPEC_VPMADDUBSWACCD\n- UNSPEC_VPMADDUBSWACCSSD\n- UNSPEC_VPMADDWDACCD\n- UNSPEC_VPMADDWDACCSSD\n+ UNSPEC_VPDPBUSD\n+ UNSPEC_VPDPBUSDS\n+ UNSPEC_VPDPWSSD\n+ UNSPEC_VPDPWSSDS\n \n ;; For VAES support\n UNSPEC_VAESDEC\n@@ -200,6 +200,13 @@\n UNSPEC_COMPLEX_FCMUL\n UNSPEC_COMPLEX_MASK\n \n+ ;; For AVX-VNNI-INT8 support\n+ UNSPEC_VPDPBSSD\n+ UNSPEC_VPDPBSSDS\n+ UNSPEC_VPDPBSUD\n+ UNSPEC_VPDPBSUDS\n+ UNSPEC_VPDPBUUD\n+ UNSPEC_VPDPBUUDS\n ])\n \n (define_c_enum \"unspecv\" [\n@@ -28541,7 +28548,7 @@\n \t [(match_operand:V16SI 1 \"register_operand\" \"0\")\n \t (match_operand:V16SI 2 \"register_operand\" \"v\")\n \t (match_operand:V16SI 3 \"nonimmediate_operand\" \"vm\")]\n-\t UNSPEC_VPMADDUBSWACCD))]\n+\t UNSPEC_VPDPBUSD))]\n \"TARGET_AVX512VNNI\"\n \"vpdpbusd\\t{%3, %2, %0|%0, %2, %3}\"\n [(set_attr (\"prefix\") (\"evex\"))])\n@@ -28552,7 +28559,7 @@\n \t [(match_operand:VI4_AVX2 1 \"register_operand\" \"0,0\")\n \t (match_operand:VI4_AVX2 2 \"register_operand\" \"x,v\")\n \t (match_operand:VI4_AVX2 3 \"nonimmediate_operand\" \"xm,vm\")]\n-\t UNSPEC_VPMADDUBSWACCD))]\n+\t UNSPEC_VPDPBUSD))]\n \"TARGET_AVXVNNI || (TARGET_AVX512VNNI && TARGET_AVX512VL)\"\n \"@\n %{vex%} vpdpbusd\\t{%3, %2, %0|%0, %2, %3}\n@@ -28567,7 +28574,7 @@\n \t [(match_operand:VI4_AVX512VL 1 \"register_operand\" \"0\")\n \t (match_operand:VI4_AVX512VL 2 \"register_operand\" \"v\")\n \t (match_operand:VI4_AVX512VL 3 \"nonimmediate_operand\" \"vm\")]\n-\t UNSPEC_VPMADDUBSWACCD)\n+\t UNSPEC_VPDPBUSD)\n \t (match_dup 1)\n \t (match_operand: 4 \"register_operand\" \"Yk\")))]\n \"TARGET_AVX512VNNI\"\n@@ -28596,7 +28603,7 @@\n \t [(match_operand:VI4_AVX512VL 1 \"register_operand\" \"0\")\n \t (match_operand:VI4_AVX512VL 2 \"register_operand\" \"v\")\n \t (match_operand:VI4_AVX512VL 3 \"nonimmediate_operand\" \"vm\")\n-\t ] UNSPEC_VPMADDUBSWACCD)\n+\t ] UNSPEC_VPDPBUSD)\n \t (match_operand:VI4_AVX512VL 4 \"const0_operand\")\n \t (match_operand: 5 \"register_operand\" \"Yk\")))]\n \"TARGET_AVX512VNNI\"\n@@ -28609,7 +28616,7 @@\n \t [(match_operand:V16SI 1 \"register_operand\" \"0\")\n \t (match_operand:V16SI 2 \"register_operand\" \"v\")\n \t (match_operand:V16SI 3 \"nonimmediate_operand\" \"vm\")]\n-\t UNSPEC_VPMADDUBSWACCSSD))]\n+\t UNSPEC_VPDPBUSDS))]\n \"TARGET_AVX512VNNI\"\n \"vpdpbusds\\t{%3, %2, %0|%0, %2, %3}\"\n [(set_attr (\"prefix\") (\"evex\"))])\n@@ -28620,7 +28627,7 @@\n \t [(match_operand:VI4_AVX2 1 \"register_operand\" \"0,0\")\n \t (match_operand:VI4_AVX2 2 \"register_operand\" \"x,v\")\n \t (match_operand:VI4_AVX2 3 \"nonimmediate_operand\" \"xm,vm\")]\n-\t UNSPEC_VPMADDUBSWACCSSD))]\n+\t UNSPEC_VPDPBUSDS))]\n \"TARGET_AVXVNNI || (TARGET_AVX512VNNI && TARGET_AVX512VL)\"\n \"@\n %{vex%} vpdpbusds\\t{%3, %2, %0|%0, %2, %3}\n@@ -28635,7 +28642,7 @@\n \t [(match_operand:VI4_AVX512VL 1 \"register_operand\" \"0\")\n \t (match_operand:VI4_AVX512VL 2 \"register_operand\" \"v\")\n \t (match_operand:VI4_AVX512VL 3 \"nonimmediate_operand\" \"vm\")]\n-\t UNSPEC_VPMADDUBSWACCSSD)\n+\t UNSPEC_VPDPBUSDS)\n \t (match_dup 1)\n \t (match_operand: 4 \"register_operand\" \"Yk\")))]\n \"TARGET_AVX512VNNI\"\n@@ -28664,7 +28671,7 @@\n \t [(match_operand:VI4_AVX512VL 1 \"register_operand\" \"0\")\n \t (match_operand:VI4_AVX512VL 2 \"register_operand\" \"v\")\n \t (match_operand:VI4_AVX512VL 3 \"nonimmediate_operand\" \"vm\")]\n-\t UNSPEC_VPMADDUBSWACCSSD)\n+\t UNSPEC_VPDPBUSDS)\n \t (match_operand:VI4_AVX512VL 4 \"const0_operand\")\n \t (match_operand: 5 \"register_operand\" \"Yk\")))]\n \"TARGET_AVX512VNNI\"\n@@ -28677,7 +28684,7 @@\n \t [(match_operand:V16SI 1 \"register_operand\" \"0\")\n \t (match_operand:V16SI 2 \"register_operand\" \"v\")\n \t (match_operand:V16SI 3 \"nonimmediate_operand\" \"vm\")]\n-\t UNSPEC_VPMADDWDACCD))]\n+\t UNSPEC_VPDPWSSD))]\n \"TARGET_AVX512VNNI\"\n \"vpdpwssd\\t{%3, %2, %0|%0, %2, %3}\"\n [(set_attr (\"prefix\") (\"evex\"))])\n@@ -28688,7 +28695,7 @@\n \t [(match_operand:VI4_AVX2 1 \"register_operand\" \"0,0\")\n \t (match_operand:VI4_AVX2 2 \"register_operand\" \"x,v\")\n \t (match_operand:VI4_AVX2 3 \"nonimmediate_operand\" \"xm,vm\")]\n-\t UNSPEC_VPMADDWDACCD))]\n+\t UNSPEC_VPDPWSSD))]\n \"TARGET_AVXVNNI || (TARGET_AVX512VNNI && TARGET_AVX512VL)\"\n \"@\n %{vex%} vpdpwssd\\t{%3, %2, %0|%0, %2, %3}\n@@ -28703,7 +28710,7 @@\n \t [(match_operand:VI4_AVX512VL 1 \"register_operand\" \"0\")\n \t (match_operand:VI4_AVX512VL 2 \"register_operand\" \"v\")\n \t (match_operand:VI4_AVX512VL 3 \"nonimmediate_operand\" \"vm\")]\n-\t UNSPEC_VPMADDWDACCD)\n+\t UNSPEC_VPDPWSSD)\n \t (match_dup 1)\n \t (match_operand: 4 \"register_operand\" \"Yk\")))]\n \"TARGET_AVX512VNNI\"\n@@ -28732,7 +28739,7 @@\n \t [(match_operand:VI4_AVX512VL 1 \"register_operand\" \"0\")\n \t (match_operand:VI4_AVX512VL 2 \"register_operand\" \"v\")\n \t (match_operand:VI4_AVX512VL 3 \"nonimmediate_operand\" \"vm\")]\n-\t UNSPEC_VPMADDWDACCD)\n+\t UNSPEC_VPDPWSSD)\n \t (match_operand:VI4_AVX512VL 4 \"const0_operand\")\n \t (match_operand: 5 \"register_operand\" \"Yk\")))]\n \"TARGET_AVX512VNNI\"\n@@ -28745,7 +28752,7 @@\n \t [(match_operand:V16SI 1 \"register_operand\" \"0\")\n \t (match_operand:V16SI 2 \"register_operand\" \"v\")\n \t (match_operand:V16SI 3 \"nonimmediate_operand\" \"vm\")]\n-\t UNSPEC_VPMADDWDACCSSD))]\n+\t UNSPEC_VPDPWSSDS))]\n \"TARGET_AVX512VNNI\"\n \"vpdpwssds\\t{%3, %2, %0|%0, %2, %3}\"\n [(set_attr (\"prefix\") (\"evex\"))])\n@@ -28756,7 +28763,7 @@\n \t [(match_operand:VI4_AVX2 1 \"register_operand\" \"0,0\")\n \t (match_operand:VI4_AVX2 2 \"register_operand\" \"x,v\")\n \t (match_operand:VI4_AVX2 3 \"nonimmediate_operand\" \"xm,vm\")]\n-\t UNSPEC_VPMADDWDACCSSD))]\n+\t UNSPEC_VPDPWSSDS))]\n \"TARGET_AVXVNNI || (TARGET_AVX512VNNI && TARGET_AVX512VL)\"\n \"@\n %{vex%} vpdpwssds\\t{%3, %2, %0|%0, %2, %3}\n@@ -28771,7 +28778,7 @@\n \t [(match_operand:VI4_AVX512VL 1 \"register_operand\" \"0\")\n \t (match_operand:VI4_AVX512VL 2 \"register_operand\" \"v\")\n \t (match_operand:VI4_AVX512VL 3 \"nonimmediate_operand\" \"vm\")]\n-\t UNSPEC_VPMADDWDACCSSD)\n+\t UNSPEC_VPDPWSSDS)\n \t (match_dup 1)\n \t (match_operand: 4 \"register_operand\" \"Yk\")))]\n \"TARGET_AVX512VNNI\"\n@@ -28800,7 +28807,7 @@\n \t [(match_operand:VI4_AVX512VL 1 \"register_operand\" \"0\")\n \t (match_operand:VI4_AVX512VL 2 \"register_operand\" \"v\")\n \t (match_operand:VI4_AVX512VL 3 \"nonimmediate_operand\" \"vm\")]\n-\t UNSPEC_VPMADDWDACCSSD)\n+\t UNSPEC_VPDPWSSDS)\n \t (match_operand:VI4_AVX512VL 4 \"const0_operand\")\n \t (match_operand: 5 \"register_operand\" \"Yk\")))]\n \"TARGET_AVX512VNNI\"\n@@ -29241,3 +29248,27 @@\n gcc_unreachable ();\n DONE;\n })\n+\n+(define_int_iterator VPDOTPROD\n+ [UNSPEC_VPDPBSSD\n+ UNSPEC_VPDPBSSDS\n+ UNSPEC_VPDPBSUD\n+ UNSPEC_VPDPBSUDS\n+ UNSPEC_VPDPBUUD\n+ UNSPEC_VPDPBUUDS])\n+\n+(define_int_attr vpdotprodtype\n+ [(UNSPEC_VPDPBSSD \"bssd\") (UNSPEC_VPDPBSSDS \"bssds\")\n+ (UNSPEC_VPDPBSUD \"bsud\") (UNSPEC_VPDPBSUDS \"bsuds\")\n+ (UNSPEC_VPDPBUUD \"buud\") (UNSPEC_VPDPBUUDS \"buuds\")])\n+\n+(define_insn \"vpdp_\"\n+ [(set (match_operand:VI4_AVX 0 \"register_operand\" \"=x\")\n+\t(unspec:VI4_AVX\n+\t [(match_operand:VI4_AVX 1 \"register_operand\" \"0\")\n+\t (match_operand:VI4_AVX 2 \"register_operand\" \"x\")\n+\t (match_operand:VI4_AVX 3 \"nonimmediate_operand\" \"xm\")]\n+\t VPDOTPROD))]\n+ \"TARGET_AVXVNNIINT8\"\n+ \"vpdp\\t{%3, %2, %0|%0, %2, %3}\"\n+ [(set_attr \"prefix\" \"vex\")])\ndiff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi\nindex edecf5c0070..9a8de9fc226 100644\n--- a/gcc/doc/extend.texi\n+++ b/gcc/doc/extend.texi\n@@ -7065,6 +7065,11 @@ Enable/disable the generation of the AVXVNNI instructions.\n @cindex @code{target(\"avxifma\")} function attribute, x86\n Enable/disable the generation of the AVXIFMA instructions.\n \n+@item avxvnniint8\n+@itemx no-avxvnniint8\n+@cindex @code{target(\"avxvnniint8\")} function attribute, x86\n+Enable/disable the generation of the AVXVNNIINT8 instructions.\n+\n @item cld\n @itemx no-cld\n @cindex @code{target(\"cld\")} function attribute, x86\ndiff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi\nindex 2cd617a9d44..1e8c49e391c 100644\n--- a/gcc/doc/invoke.texi\n+++ b/gcc/doc/invoke.texi\n@@ -1436,7 +1436,7 @@ See RS/6000 and PowerPC Options.\n -mavx5124fmaps -mavx512vnni -mavx5124vnniw -mprfchw -mrdpid @gol\n -mrdseed -msgx -mavx512vp2intersect -mserialize -mtsxldtrk@gol\n -mamx-tile -mamx-int8 -mamx-bf16 -muintr -mhreset -mavxvnni@gol\n--mavx512fp16 -mavxifma @gol\n+-mavx512fp16 -mavxifma -mavxvnniint8 @gol\n -mcldemote -mms-bitfields -mno-align-stringops -minline-all-stringops @gol\n -minline-stringops-dynamically -mstringop-strategy=@var{alg} @gol\n -mkl -mwidekl @gol\n@@ -32896,6 +32896,9 @@ preferred alignment to @option{-mpreferred-stack-boundary=2}.\n @need 200\n @itemx -mavxifma\n @opindex mavxifma\n+@need 200\n+@itemx -mavxvnniint8\n+@opindex mavxvnniint8\n These switches enable the use of instructions in the MMX, SSE,\n SSE2, SSE3, SSSE3, SSE4, SSE4A, SSE4.1, SSE4.2, AVX, AVX2, AVX512F, AVX512PF,\n AVX512ER, AVX512CD, AVX512VL, AVX512BW, AVX512DQ, AVX512IFMA, AVX512VBMI, SHA,\n@@ -32906,8 +32909,8 @@ XSAVEOPT, XSAVEC, XSAVES, RTM, HLE, TBM, MWAITX, CLZERO, PKU, AVX512VBMI2,\n GFNI, VAES, WAITPKG, VPCLMULQDQ, AVX512BITALG, MOVDIRI, MOVDIR64B, AVX512BF16,\n ENQCMD, AVX512VPOPCNTDQ, AVX5124FMAPS, AVX512VNNI, AVX5124VNNIW, SERIALIZE,\n UINTR, HRESET, AMXTILE, AMXINT8, AMXBF16, KL, WIDEKL, AVXVNNI, AVX512FP16,\n-AVXIFMA or CLDEMOTE extended instruction sets. Each has a corresponding\n-@option{-mno-} option to disable use of these instructions.\n+AVXIFMA, AVXVNNIINT8 or CLDEMOTE extended instruction sets. Each has a\n+corresponding @option{-mno-} option to disable use of these instructions.\n \n These extensions are also available as built-in functions: see\n @ref{x86 Built-in Functions}, for details of the functions enabled and\ndiff --git a/gcc/doc/sourcebuild.texi b/gcc/doc/sourcebuild.texi\nindex 0173acf4a65..e21a1d381e0 100644\n--- a/gcc/doc/sourcebuild.texi\n+++ b/gcc/doc/sourcebuild.texi\n@@ -2493,6 +2493,9 @@ Target supports the execution of @code{avx512vp2intersect} instructions.\n @item avxifma\n Target supports the execution of @code{avxifma} instructions.\n \n+@item avxvnniint8\n+Target supports the execution of @code{avxvnniint8} instructions.\n+\n @item amx_tile\n Target supports the execution of @code{amx-tile} instructions.\n \ndiff --git a/gcc/testsuite/g++.dg/other/i386-2.C b/gcc/testsuite/g++.dg/other/i386-2.C\nindex 5388606779b..ebd01fe47bc 100644\n--- a/gcc/testsuite/g++.dg/other/i386-2.C\n+++ b/gcc/testsuite/g++.dg/other/i386-2.C\n@@ -1,5 +1,5 @@\n /* { dg-do compile { target i?86-*-* x86_64-*-* } } */\n-/* { dg-options \"-O -pedantic-errors -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512dq -mavx512bw -mavx512vl -mavx512ifma -mavx512vbmi -mavx512vbmi2 -mavx5124fmaps -mavx5124vnniw -mavx512vpopcntdq -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mavx512bitalg -mpconfig -mwbnoinvd -mavx512bf16 -menqcmd -mavx512vp2intersect -mserialize -mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl -mavxvnni -mavx512fp16 -mavxifma\" } */\n+/* { dg-options \"-O -pedantic-errors -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512dq -mavx512bw -mavx512vl -mavx512ifma -mavx512vbmi -mavx512vbmi2 -mavx5124fmaps -mavx5124vnniw -mavx512vpopcntdq -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mavx512bitalg -mpconfig -mwbnoinvd -mavx512bf16 -menqcmd -mavx512vp2intersect -mserialize -mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl -mavxvnni -mavx512fp16 -mavxifma -mavxvnniint8\" } */\n \n /* Test that {,x,e,p,t,s,w,a,b,i}mmintrin.h, mm3dnow.h, fma4intrin.h,\n xopintrin.h, abmintrin.h, bmiintrin.h, tbmintrin.h, lwpintrin.h,\ndiff --git a/gcc/testsuite/g++.dg/other/i386-3.C b/gcc/testsuite/g++.dg/other/i386-3.C\nindex 86cedd3d32f..b66498f1d4c 100644\n--- a/gcc/testsuite/g++.dg/other/i386-3.C\n+++ b/gcc/testsuite/g++.dg/other/i386-3.C\n@@ -1,5 +1,5 @@\n /* { dg-do compile { target i?86-*-* x86_64-*-* } } */\n-/* { dg-options \"-O -fkeep-inline-functions -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512dq -mavx512bw -mavx512vl -mavx512ifma -mavx512vbmi -mavx512vbmi2 -mavx5124fmaps -mavx5124vnniw -mavx512vpopcntdq -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mavx512bitalg -mpconfig -mwbnoinvd -mavx512bf16 -menqcmd -mavx512vp2intersect -mserialize -mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl -mavxvnni -mavx512fp16 -mavxifma\" } */\n+/* { dg-options \"-O -fkeep-inline-functions -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512dq -mavx512bw -mavx512vl -mavx512ifma -mavx512vbmi -mavx512vbmi2 -mavx5124fmaps -mavx5124vnniw -mavx512vpopcntdq -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mavx512bitalg -mpconfig -mwbnoinvd -mavx512bf16 -menqcmd -mavx512vp2intersect -mserialize -mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl -mavxvnni -mavx512fp16 -mavxifma -mavxvnniint8\" } */\n \n /* Test that {,x,e,p,t,s,w,a,b,i}mmintrin.h, mm3dnow.h, fma4intrin.h,\n xopintrin.h, abmintrin.h, bmiintrin.h, tbmintrin.h, lwpintrin.h,\ndiff --git a/gcc/testsuite/gcc.target/i386/avx-check.h b/gcc/testsuite/gcc.target/i386/avx-check.h\nindex 24ee6ab4efd..77507ca2edc 100644\n--- a/gcc/testsuite/gcc.target/i386/avx-check.h\n+++ b/gcc/testsuite/gcc.target/i386/avx-check.h\n@@ -25,6 +25,9 @@ main ()\n && avx_os_support ()\n #ifdef AVXIFMA\n && __builtin_cpu_supports (\"avxifma\")\n+#endif\n+#ifdef AVXVNNIINT8\n+ && __builtin_cpu_supports (\"avxvnniint8\")\n #endif\n )\n {\ndiff --git a/gcc/testsuite/gcc.target/i386/avxvnniint8-1.c b/gcc/testsuite/gcc.target/i386/avxvnniint8-1.c\nnew file mode 100644\nindex 00000000000..d6942f34d6e\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/i386/avxvnniint8-1.c\n@@ -0,0 +1,43 @@\n+/* { dg-do compile } */\n+/* { dg-options \"-mavxvnniint8 -O2\" } */\n+/* { dg-final { scan-assembler-times \"vpdpbssd\\[ \\\\t\\]+\\[^\\{\\n\\]*%ymm\\[0-9\\]+\\[^\\n\\r]*%ymm\\[0-9\\]+\\[^\\n\\r]*%ymm\\[0-9\\]+(?:\\n|\\[ \\\\t\\]+#)\" 1 } } */\n+/* { dg-final { scan-assembler-times \"vpdpbssd\\[ \\\\t\\]+\\[^\\{\\n\\]*%xmm\\[0-9\\]+\\[^\\n\\r]*%xmm\\[0-9\\]+\\[^\\n\\r]*%xmm\\[0-9\\]+(?:\\n|\\[ \\\\t\\]+#)\" 1 } } */\n+/* { dg-final { scan-assembler-times \"vpdpbssds\\[ \\\\t\\]+\\[^\\{\\n\\]*%ymm\\[0-9\\]+\\[^\\n\\r]*%ymm\\[0-9\\]+\\[^\\n\\r]*%ymm\\[0-9\\]+(?:\\n|\\[ \\\\t\\]+#)\" 1 } } */\n+/* { dg-final { scan-assembler-times \"vpdpbssds\\[ \\\\t\\]+\\[^\\{\\n\\]*%xmm\\[0-9\\]+\\[^\\n\\r]*%xmm\\[0-9\\]+\\[^\\n\\r]*%xmm\\[0-9\\]+(?:\\n|\\[ \\\\t\\]+#)\" 1 } } */\n+/* { dg-final { scan-assembler-times \"vpdpbsud\\[ \\\\t\\]+\\[^\\{\\n\\]*%ymm\\[0-9\\]+\\[^\\n\\r]*%ymm\\[0-9\\]+\\[^\\n\\r]*%ymm\\[0-9\\]+(?:\\n|\\[ \\\\t\\]+#)\" 1 } } */\n+/* { dg-final { scan-assembler-times \"vpdpbsud\\[ \\\\t\\]+\\[^\\{\\n\\]*%xmm\\[0-9\\]+\\[^\\n\\r]*%xmm\\[0-9\\]+\\[^\\n\\r]*%xmm\\[0-9\\]+(?:\\n|\\[ \\\\t\\]+#)\" 1 } } */\n+/* { dg-final { scan-assembler-times \"vpdpbsuds\\[ \\\\t\\]+\\[^\\{\\n\\]*%ymm\\[0-9\\]+\\[^\\n\\r]*%ymm\\[0-9\\]+\\[^\\n\\r]*%ymm\\[0-9\\]+(?:\\n|\\[ \\\\t\\]+#)\" 1 } } */\n+/* { dg-final { scan-assembler-times \"vpdpbsuds\\[ \\\\t\\]+\\[^\\{\\n\\]*%xmm\\[0-9\\]+\\[^\\n\\r]*%xmm\\[0-9\\]+\\[^\\n\\r]*%xmm\\[0-9\\]+(?:\\n|\\[ \\\\t\\]+#)\" 1 } } */\n+/* { dg-final { scan-assembler-times \"vpdpbuud\\[ \\\\t\\]+\\[^\\{\\n\\]*%ymm\\[0-9\\]+\\[^\\n\\r]*%ymm\\[0-9\\]+\\[^\\n\\r]*%ymm\\[0-9\\]+(?:\\n|\\[ \\\\t\\]+#)\" 1 } } */\n+/* { dg-final { scan-assembler-times \"vpdpbuud\\[ \\\\t\\]+\\[^\\{\\n\\]*%xmm\\[0-9\\]+\\[^\\n\\r]*%xmm\\[0-9\\]+\\[^\\n\\r]*%xmm\\[0-9\\]+(?:\\n|\\[ \\\\t\\]+#)\" 1 } } */\n+/* { dg-final { scan-assembler-times \"vpdpbuuds\\[ \\\\t\\]+\\[^\\{\\n\\]*%ymm\\[0-9\\]+\\[^\\n\\r]*%ymm\\[0-9\\]+\\[^\\n\\r]*%ymm\\[0-9\\]+(?:\\n|\\[ \\\\t\\]+#)\" 1 } } */\n+/* { dg-final { scan-assembler-times \"vpdpbuuds\\[ \\\\t\\]+\\[^\\{\\n\\]*%xmm\\[0-9\\]+\\[^\\n\\r]*%xmm\\[0-9\\]+\\[^\\n\\r]*%xmm\\[0-9\\]+(?:\\n|\\[ \\\\t\\]+#)\" 1 } } */\n+\n+\n+#include \n+\n+volatile __m256i x,y,z;\n+volatile __m128i x_,y_,z_;\n+volatile __mmask8 m;\n+\n+void extern\n+avxvnniint8_test (void)\n+{\n+ x = _mm256_dpbssd_epi32 (x, y, z);\n+ x_ = _mm_dpbssd_epi32 (x_, y_, z_);\n+\n+ x = _mm256_dpbssds_epi32 (x, y, z);\n+ x_ = _mm_dpbssds_epi32 (x_, y_, z_);\n+\n+ x = _mm256_dpbsud_epi32 (x, y, z);\n+ x_ = _mm_dpbsud_epi32 (x_, y_, z_);\n+\n+ x = _mm256_dpbsuds_epi32 (x, y, z);\n+ x_ = _mm_dpbsuds_epi32 (x_, y_, z_);\n+\n+ x = _mm256_dpbuud_epi32 (x, y, z);\n+ x_ = _mm_dpbuud_epi32 (x_, y_, z_);\n+\n+ x = _mm256_dpbuuds_epi32 (x, y, z);\n+ x_ = _mm_dpbuuds_epi32 (x_, y_, z_);\n+}\ndiff --git a/gcc/testsuite/gcc.target/i386/avxvnniint8-vpdpbssd-2.c b/gcc/testsuite/gcc.target/i386/avxvnniint8-vpdpbssd-2.c\nnew file mode 100644\nindex 00000000000..5016de39621\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/i386/avxvnniint8-vpdpbssd-2.c\n@@ -0,0 +1,72 @@\n+/* { dg-do run } */\n+/* { dg-options \"-O2 -mavxvnniint8\" } */\n+/* { dg-require-effective-target avxvnniint8 } */\n+#define AVXVNNIINT8\n+#ifndef CHECK\n+#define CHECK \"avx-check.h\"\n+#endif\n+\n+#ifndef TEST\n+#define TEST avx_test\n+#endif\n+\n+#include CHECK\n+\n+static void\n+CALC (int *r, int *dst, char *s1, char *s2, int size)\n+{\n+ short tempres[32];\n+ for (int i = 0; i < size; i++) {\n+ tempres[i] = (short) s1[i] * (short) s2[i];\n+ }\n+ for (int i = 0; i < size / 4; i++) {\n+ long long test = (long long) dst[i] + tempres[i * 4] + tempres[i * 4 + 1]\n+\t\t + tempres[i * 4 + 2] + tempres[i * 4 + 3];\n+ r[i] = test;\n+ }\n+}\n+\n+void\n+TEST (void)\n+{\n+ int i;\n+ union256i_d res_256;\n+ union256i_b src2_256;\n+ union256i_b src1_256;\n+ int res_ref_256[8];\n+\n+ for (i = 0; i < 32; i++)\n+ {\n+ int sign = i % 2 ? 1 : -1;\n+ src1_256.a[i] = 10 + 3 * i + sign;\n+ src2_256.a[i] = sign * 10 * i * i;\n+ }\n+\n+ for (i = 0; i < 8; i++)\n+ res_256.a[i] = 0x7fffffff;\n+\n+ CALC (res_ref_256, res_256.a, src1_256.a, src2_256.a, 32);\n+ res_256.x = _mm256_dpbssd_epi32 (res_256.x, src1_256.x, src2_256.x);\n+ if (check_union256i_d (res_256, res_ref_256))\n+ abort ();\n+\n+ union128i_d res_128;\n+ union128i_b src2_128;\n+ union128i_b src1_128;\n+ int res_ref_128[4];\n+\n+ for (i = 0; i < 16; i++)\n+ {\n+ int sign = i % 2 ? 1 : -1;\n+ src1_128.a[i] = 10 + 3 * i * i + sign;\n+ src2_128.a[i] = sign * 10 * i * i;\n+ }\n+\n+ for (i = 0; i < 4; i++)\n+ res_128.a[i] = 0x7fffffff;\n+\n+ CALC (res_ref_128, res_128.a, src1_128.a, src2_128.a, 16);\n+ res_128.x = _mm_dpbssd_epi32 (res_128.x, src1_128.x, src2_128.x);\n+ if (check_union128i_d (res_128, res_ref_128))\n+ abort ();\n+}\ndiff --git a/gcc/testsuite/gcc.target/i386/avxvnniint8-vpdpbssds-2.c b/gcc/testsuite/gcc.target/i386/avxvnniint8-vpdpbssds-2.c\nnew file mode 100644\nindex 00000000000..6de5062e917\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/i386/avxvnniint8-vpdpbssds-2.c\n@@ -0,0 +1,72 @@\n+/* { dg-do run } */\n+/* { dg-options \"-O2 -mavxvnniint8\" } */\n+/* { dg-require-effective-target avxvnniint8 } */\n+#define AVXVNNIINT8\n+#ifndef CHECK\n+#define CHECK \"avx-check.h\"\n+#endif\n+\n+#ifndef TEST\n+#define TEST avx_test\n+#endif\n+\n+#include CHECK\n+\n+static void\n+CALC (int *r, int *dst, char *s1, char *s2, int size)\n+{\n+ short tempres[32];\n+ for (int i = 0; i < size; i++) {\n+ tempres[i] = (short) s1[i] * (short) s2[i];\n+ }\n+ for (int i = 0; i < size / 4; i++) {\n+ long long test = (long long) dst[i] + tempres[i * 4] + tempres[i * 4 + 1]\n+\t\t + tempres[i * 4 + 2] + tempres[i * 4 + 3];\n+ r[i] = test > 0x7FFFFFFF ? 0x7FFFFFFF : test;\n+ }\n+}\n+\n+void\n+TEST (void)\n+{\n+ int i;\n+ union256i_d res_256;\n+ union256i_b src2_256;\n+ union256i_b src1_256;\n+ int res_ref_256[8];\n+\n+ for (i = 0; i < 32; i++)\n+ {\n+ int sign = i % 2 ? 1 : -1;\n+ src1_256.a[i] = 10 + 3 * i + sign;\n+ src2_256.a[i] = sign * 10 * i * i;\n+ }\n+\n+ for (i = 0; i < 8; i++)\n+ res_256.a[i] = 0x7fffffff;\n+\n+ CALC (res_ref_256, res_256.a, src1_256.a, src2_256.a, 32);\n+ res_256.x = _mm256_dpbssds_epi32 (res_256.x, src1_256.x, src2_256.x);\n+ if (check_union256i_d (res_256, res_ref_256))\n+ abort ();\n+\n+ union128i_d res_128;\n+ union128i_b src2_128;\n+ union128i_b src1_128;\n+ int res_ref_128[4];\n+\n+ for (i = 0; i < 16; i++)\n+ {\n+ int sign = i % 2 ? 1 : -1;\n+ src1_128.a[i] = 10 + 3 * i * i + sign;\n+ src2_128.a[i] = sign * 10 * i * i;\n+ }\n+\n+ for (i = 0; i < 4; i++)\n+ res_128.a[i] = 0x7fffffff;\n+\n+ CALC (res_ref_128, res_128.a, src1_128.a, src2_128.a, 16);\n+ res_128.x = _mm_dpbssds_epi32 (res_128.x, src1_128.x, src2_128.x);\n+ if (check_union128i_d (res_128, res_ref_128))\n+ abort ();\n+}\ndiff --git a/gcc/testsuite/gcc.target/i386/avxvnniint8-vpdpbsud-2.c b/gcc/testsuite/gcc.target/i386/avxvnniint8-vpdpbsud-2.c\nnew file mode 100644\nindex 00000000000..6e4ffd1c7be\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/i386/avxvnniint8-vpdpbsud-2.c\n@@ -0,0 +1,72 @@\n+/* { dg-do run } */\n+/* { dg-options \"-O2 -mavxvnniint8\" } */\n+/* { dg-require-effective-target avxvnniint8 } */\n+#define AVXVNNIINT8\n+#ifndef CHECK\n+#define CHECK \"avx-check.h\"\n+#endif\n+\n+#ifndef TEST\n+#define TEST avx_test\n+#endif\n+\n+#include CHECK\n+\n+static void\n+CALC (int *r, int *dst, char *s1, unsigned char *s2, int size)\n+{\n+ short tempres[32];\n+ for (int i = 0; i < size; i++) {\n+ tempres[i] = (short) s1[i] * (unsigned short) s2[i];\n+ }\n+ for (int i = 0; i < size / 4; i++) {\n+ long long test = (long long) dst[i] + tempres[i * 4] + tempres[i * 4 + 1]\n+\t\t + tempres[i * 4 + 2] + tempres[i * 4 + 3];\n+ r[i] = test;\n+ }\n+}\n+\n+void\n+TEST (void)\n+{\n+ int i;\n+ union256i_d res_256;\n+ union256i_b src1_256;\n+ union256i_ub src2_256;\n+ int res_ref_256[8];\n+\n+ for (i = 0; i < 32; i++)\n+ {\n+ int sign = i % 2 ? 1 : -1;\n+ src1_256.a[i] = 10 + 3 * i + sign;\n+ src2_256.a[i] = sign * 10 * i * i;\n+ }\n+\n+ for (i = 0; i < 8; i++)\n+ res_256.a[i] = 0x7fffffff;\n+\n+ CALC (res_ref_256, res_256.a, src1_256.a, src2_256.a, 32);\n+ res_256.x = _mm256_dpbsud_epi32 (res_256.x, src1_256.x, src2_256.x);\n+ if (check_union256i_d (res_256, res_ref_256))\n+ abort ();\n+\n+ union128i_d res_128;\n+ union128i_b src1_128;\n+ union128i_ub src2_128;\n+ int res_ref_128[4];\n+\n+ for (i = 0; i < 16; i++)\n+ {\n+ int sign = i % 2 ? 1 : -1;\n+ src1_128.a[i] = 10 + 3 * i * i + sign;\n+ src2_128.a[i] = sign * 10 * i * i;\n+ }\n+\n+ for (i = 0; i < 4; i++)\n+ res_128.a[i] = 0x7fffffff;\n+\n+ CALC (res_ref_128, res_128.a, src1_128.a, src2_128.a, 16);\n+ res_128.x = _mm_dpbsud_epi32 (res_128.x, src1_128.x, src2_128.x);\n+ if (check_union128i_d (res_128, res_ref_128))\n+ abort ();\n+}\ndiff --git a/gcc/testsuite/gcc.target/i386/avxvnniint8-vpdpbsuds-2.c b/gcc/testsuite/gcc.target/i386/avxvnniint8-vpdpbsuds-2.c\nnew file mode 100644\nindex 00000000000..ad4b6047ecd\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/i386/avxvnniint8-vpdpbsuds-2.c\n@@ -0,0 +1,72 @@\n+/* { dg-do run } */\n+/* { dg-options \"-O2 -mavxvnniint8\" } */\n+/* { dg-require-effective-target avxvnniint8 } */\n+#define AVXVNNIINT8\n+#ifndef CHECK\n+#define CHECK \"avx-check.h\"\n+#endif\n+\n+#ifndef TEST\n+#define TEST avx_test\n+#endif\n+\n+#include CHECK\n+\n+static void\n+CALC (int *r, int *dst, char *s1, unsigned char *s2, int size)\n+{\n+ short tempres[32];\n+ for (int i = 0; i < size; i++) {\n+ tempres[i] = (short) s1[i] * (unsigned short) s2[i];\n+ }\n+ for (int i = 0; i < size / 4; i++) {\n+ long long test = (long long) dst[i] + tempres[i * 4] + tempres[i * 4 + 1]\n+\t\t + tempres[i * 4 + 2] + tempres[i * 4 + 3];\n+ r[i] = test > 0x7FFFFFFF ? 0x7FFFFFFF : test;\n+ }\n+}\n+\n+void\n+TEST (void)\n+{\n+ int i;\n+ union256i_d res_256;\n+ union256i_b src1_256;\n+ union256i_ub src2_256;\n+ int res_ref_256[8];\n+\n+ for (i = 0; i < 32; i++)\n+ {\n+ int sign = i % 2 ? 1 : -1;\n+ src1_256.a[i] = 10 + 3 * i + sign;\n+ src2_256.a[i] = sign * 10 * i * i;\n+ }\n+\n+ for (i = 0; i < 8; i++)\n+ res_256.a[i] = 0x7fffffff;\n+\n+ CALC (res_ref_256, res_256.a, src1_256.a, src2_256.a, 32);\n+ res_256.x = _mm256_dpbsuds_epi32 (res_256.x, src1_256.x, src2_256.x);\n+ if (check_union256i_d (res_256, res_ref_256))\n+ abort ();\n+\n+ union128i_d res_128;\n+ union128i_b src1_128;\n+ union128i_ub src2_128;\n+ int res_ref_128[4];\n+\n+ for (i = 0; i < 16; i++)\n+ {\n+ int sign = i % 2 ? 1 : -1;\n+ src1_128.a[i] = 10 + 3 * i * i + sign;\n+ src2_128.a[i] = sign * 10 * i * i;\n+ }\n+\n+ for (i = 0; i < 4; i++)\n+ res_128.a[i] = 0x7fffffff;\n+\n+ CALC (res_ref_128, res_128.a, src1_128.a, src2_128.a, 16);\n+ res_128.x = _mm_dpbsuds_epi32 (res_128.x, src1_128.x, src2_128.x);\n+ if (check_union128i_d (res_128, res_ref_128))\n+ abort ();\n+}\ndiff --git a/gcc/testsuite/gcc.target/i386/avxvnniint8-vpdpbuud-2.c b/gcc/testsuite/gcc.target/i386/avxvnniint8-vpdpbuud-2.c\nnew file mode 100644\nindex 00000000000..6590915a459\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/i386/avxvnniint8-vpdpbuud-2.c\n@@ -0,0 +1,72 @@\n+/* { dg-do run } */\n+/* { dg-options \"-O2 -mavxvnniint8\" } */\n+/* { dg-require-effective-target avxvnniint8 } */\n+#define AVXVNNIINT8\n+#ifndef CHECK\n+#define CHECK \"avx-check.h\"\n+#endif\n+\n+#ifndef TEST\n+#define TEST avx_test\n+#endif\n+\n+#include CHECK\n+\n+static void\n+CALC (unsigned int *r, unsigned int *dst, unsigned char *s1, unsigned char *s2, int size)\n+{\n+ unsigned short tempres[32];\n+ for (int i = 0; i < size; i++) {\n+ tempres[i] = (unsigned short) s1[i] * (unsigned short) s2[i];\n+ }\n+ for (int i = 0; i < size / 4; i++) {\n+ unsigned int test = (unsigned int) dst[i] + tempres[i * 4] + tempres[i * 4 + 1]\n+\t\t\t+ tempres[i * 4 + 2] + tempres[i * 4 + 3];\n+ r[i] = test;\n+ }\n+}\n+\n+void\n+TEST (void)\n+{\n+ int i;\n+ union256i_ud res_256;\n+ union256i_ub src2_256;\n+ union256i_ub src1_256;\n+ unsigned int res_ref_256[8];\n+\n+ for (i = 0; i < 32; i++)\n+ {\n+ int sign = i % 2 ? 1 : -1;\n+ src1_256.a[i] = 10 + 3 * i + sign;\n+ src2_256.a[i] = sign * 10 * i * i;\n+ }\n+\n+ for (i = 0; i < 8; i++)\n+ res_256.a[i] = 0x7fffffff;\n+\n+ CALC (res_ref_256, res_256.a, src1_256.a, src2_256.a, 32);\n+ res_256.x = _mm256_dpbuud_epi32 (res_256.x, src1_256.x, src2_256.x);\n+ if (check_union256i_ud (res_256, res_ref_256))\n+ abort ();\n+\n+ union128i_ud res_128;\n+ union128i_ub src2_128;\n+ union128i_ub src1_128;\n+ unsigned int res_ref_128[4];\n+\n+ for (i = 0; i < 16; i++)\n+ {\n+ int sign = i % 2 ? 1 : -1;\n+ src1_128.a[i] = 10 + 3 * i * i + sign;\n+ src2_128.a[i] = sign * 10 * i * i;\n+ }\n+\n+ for (i = 0; i < 4; i++)\n+ res_128.a[i] = 0x7fffffff;\n+\n+ CALC (res_ref_128, res_128.a, src1_128.a, src2_128.a, 16);\n+ res_128.x = _mm_dpbuud_epi32 (res_128.x, src1_128.x, src2_128.x);\n+ if (check_union128i_ud (res_128, res_ref_128))\n+ abort ();\n+}\ndiff --git a/gcc/testsuite/gcc.target/i386/avxvnniint8-vpdpbuuds-2.c b/gcc/testsuite/gcc.target/i386/avxvnniint8-vpdpbuuds-2.c\nnew file mode 100644\nindex 00000000000..970e4a5d408\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/i386/avxvnniint8-vpdpbuuds-2.c\n@@ -0,0 +1,72 @@\n+/* { dg-do run } */\n+/* { dg-options \"-O2 -mavxvnniint8\" } */\n+/* { dg-require-effective-target avxvnniint8 } */\n+#define AVXVNNIINT8\n+#ifndef CHECK\n+#define CHECK \"avx-check.h\"\n+#endif\n+\n+#ifndef TEST\n+#define TEST avx_test\n+#endif\n+\n+#include CHECK\n+\n+static void\n+CALC (unsigned int *r, unsigned int *dst, unsigned char *s1, unsigned char *s2, int size)\n+{\n+ unsigned short tempres[32];\n+ for (int i = 0; i < size; i++) {\n+ tempres[i] = (unsigned short) s1[i] * (unsigned short) s2[i];\n+ }\n+ for (int i = 0; i < size / 4; i++) {\n+ unsigned int test = (unsigned int) dst[i] + tempres[i * 4] + tempres[i * 4 + 1]\n+\t\t\t+ tempres[i * 4 + 2] + tempres[i * 4 + 3];\n+ r[i] = test > 0xFFFFFFFF ? 0xFFFFFFFF : test;\n+ }\n+}\n+\n+void\n+TEST (void)\n+{\n+ int i;\n+ union256i_ud res_256;\n+ union256i_ub src2_256;\n+ union256i_ub src1_256;\n+ unsigned int res_ref_256[8];\n+\n+ for (i = 0; i < 32; i++)\n+ {\n+ int sign = i % 2 ? 1 : -1;\n+ src1_256.a[i] = 10 + 3 * i + sign;\n+ src2_256.a[i] = sign * 10 * i * i;\n+ }\n+\n+ for (i = 0; i < 8; i++)\n+ res_256.a[i] = 0x7fffffff;\n+\n+ CALC (res_ref_256, res_256.a, src1_256.a, src2_256.a, 32);\n+ res_256.x = _mm256_dpbuuds_epi32 (res_256.x, src1_256.x, src2_256.x);\n+ if (check_union256i_ud (res_256, res_ref_256))\n+ abort ();\n+\n+ union128i_ud res_128;\n+ union128i_ub src2_128;\n+ union128i_ub src1_128;\n+ unsigned int res_ref_128[4];\n+\n+ for (i = 0; i < 16; i++)\n+ {\n+ int sign = i % 2 ? 1 : -1;\n+ src1_128.a[i] = 10 + 3 * i * i + sign;\n+ src2_128.a[i] = sign * 10 * i * i;\n+ }\n+\n+ for (i = 0; i < 4; i++)\n+ res_128.a[i] = 0x7fffffff;\n+\n+ CALC (res_ref_128, res_128.a, src1_128.a, src2_128.a, 16);\n+ res_128.x = _mm_dpbuuds_epi32 (res_128.x, src1_128.x, src2_128.x);\n+ if (check_union128i_ud (res_128, res_ref_128))\n+ abort ();\n+}\ndiff --git a/gcc/testsuite/gcc.target/i386/funcspec-56.inc b/gcc/testsuite/gcc.target/i386/funcspec-56.inc\nindex 466555c0d06..a681bffe3e7 100644\n--- a/gcc/testsuite/gcc.target/i386/funcspec-56.inc\n+++ b/gcc/testsuite/gcc.target/i386/funcspec-56.inc\n@@ -81,6 +81,7 @@ extern void test_widekl (void)\t\t\t__attribute__((__target__(\"widekl\")));\n extern void test_avxvnni (void)\t\t\t__attribute__((__target__(\"avxvnni\")));\n extern void test_avx512fp16 (void)\t\t__attribute__((__target__(\"avx512fp16\")));\n extern void test_avxifma (void)\t\t\t__attribute__((__target__(\"avxifma\")));\n+extern void test_avxvnniint8 (void)\t\t__attribute__((__target__(\"avxvnniint8\")));\n \n extern void test_no_sgx (void)\t\t\t__attribute__((__target__(\"no-sgx\")));\n extern void test_no_avx5124fmaps(void)\t\t__attribute__((__target__(\"no-avx5124fmaps\")));\n@@ -163,6 +164,7 @@ extern void test_no_widekl (void)\t\t__attribute__((__target__(\"no-widekl\")));\n extern void test_no_avxvnni (void)\t\t__attribute__((__target__(\"no-avxvnni\")));\n extern void test_no_avx512fp16 (void)\t\t__attribute__((__target__(\"no-avx512fp16\")));\n extern void test_no_avxifma (void)\t\t__attribute__((__target__(\"no-avxifma\")));\n+extern void test_no_avxvnniint8 (void)\t\t__attribute__((__target__(\"no-avxvnniint8\")));\n \n extern void test_arch_nocona (void)\t\t__attribute__((__target__(\"arch=nocona\")));\n extern void test_arch_core2 (void)\t\t__attribute__((__target__(\"arch=core2\")));\ndiff --git a/gcc/testsuite/gcc.target/i386/sse-12.c b/gcc/testsuite/gcc.target/i386/sse-12.c\nindex fde56261d8f..ddde2df6657 100644\n--- a/gcc/testsuite/gcc.target/i386/sse-12.c\n+++ b/gcc/testsuite/gcc.target/i386/sse-12.c\n@@ -3,7 +3,7 @@\n popcntintrin.h gfniintrin.h and mm_malloc.h are usable\n with -O -std=c89 -pedantic-errors. */\n /* { dg-do compile } */\n-/* { dg-options \"-O -std=c89 -pedantic-errors -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512bw -mavx512dq -mavx512vl -mavx512vbmi -mavx512vbmi2 -mavx512ifma -mavx5124fmaps -mavx5124vnniw -mavx512vpopcntdq -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mavx512bitalg -mpconfig -mwbnoinvd -mavx512bf16 -menqcmd -mavx512vp2intersect -mserialize -mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl -mavxvnni -mavxifma\" } */\n+/* { dg-options \"-O -std=c89 -pedantic-errors -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512bw -mavx512dq -mavx512vl -mavx512vbmi -mavx512vbmi2 -mavx512ifma -mavx5124fmaps -mavx5124vnniw -mavx512vpopcntdq -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mavx512bitalg -mpconfig -mwbnoinvd -mavx512bf16 -menqcmd -mavx512vp2intersect -mserialize -mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl -mavxvnni -mavxifma -mavxvnniint8\" } */\n \n #include \n \ndiff --git a/gcc/testsuite/gcc.target/i386/sse-13.c b/gcc/testsuite/gcc.target/i386/sse-13.c\nindex bb29555babe..2b293216c6f 100644\n--- a/gcc/testsuite/gcc.target/i386/sse-13.c\n+++ b/gcc/testsuite/gcc.target/i386/sse-13.c\n@@ -1,5 +1,5 @@\n /* { dg-do compile } */\n-/* { dg-options \"-O2 -Werror-implicit-function-declaration -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512vl -mavx512dq -mavx512bw -mavx512vbmi -mavx512vbmi2 -mavx512ifma -mavx5124fmaps -mavx5124vnniw -mavx512vpopcntdq -mavx512vp2intersect -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mavx512bitalg -mpconfig -mwbnoinvd -mavx512bf16 -menqcmd -mserialize -mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl -mavxvnni -mavx512fp16 -mavxifma\" } */\n+/* { dg-options \"-O2 -Werror-implicit-function-declaration -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512vl -mavx512dq -mavx512bw -mavx512vbmi -mavx512vbmi2 -mavx512ifma -mavx5124fmaps -mavx5124vnniw -mavx512vpopcntdq -mavx512vp2intersect -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mavx512bitalg -mpconfig -mwbnoinvd -mavx512bf16 -menqcmd -mserialize -mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl -mavxvnni -mavx512fp16 -mavxifma -mavxvnniint8\" } */\n /* { dg-add-options bind_pic_locally } */\n \n #include \ndiff --git a/gcc/testsuite/gcc.target/i386/sse-14.c b/gcc/testsuite/gcc.target/i386/sse-14.c\nindex f2701ddaaf9..78b51048b90 100644\n--- a/gcc/testsuite/gcc.target/i386/sse-14.c\n+++ b/gcc/testsuite/gcc.target/i386/sse-14.c\n@@ -1,5 +1,5 @@\n /* { dg-do compile } */\n-/* { dg-options \"-O0 -Werror-implicit-function-declaration -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512dq -mavx512bw -mavx512vl -mavx512ifma -mavx512vbmi -mavx512vbmi2 -mavx5124fmaps -mavx5124vnniw -mavx512vpopcntdq -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mpconfig -mwbnoinvd -mavx512vl -mavx512bf16 -menqcmd -mavx512vp2intersect -mserialize -mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl -mavxvnni -mavx512fp16 -mavxifma\" } */\n+/* { dg-options \"-O0 -Werror-implicit-function-declaration -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512dq -mavx512bw -mavx512vl -mavx512ifma -mavx512vbmi -mavx512vbmi2 -mavx5124fmaps -mavx5124vnniw -mavx512vpopcntdq -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mpconfig -mwbnoinvd -mavx512vl -mavx512bf16 -menqcmd -mavx512vp2intersect -mserialize -mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl -mavxvnni -mavx512fp16 -mavxifma -mavxvnniint8\" } */\n /* { dg-add-options bind_pic_locally } */\n \n #include \ndiff --git a/gcc/testsuite/gcc.target/i386/sse-22.c b/gcc/testsuite/gcc.target/i386/sse-22.c\nindex 3d196975b1e..cc1c8cfa4be 100644\n--- a/gcc/testsuite/gcc.target/i386/sse-22.c\n+++ b/gcc/testsuite/gcc.target/i386/sse-22.c\n@@ -103,7 +103,7 @@\n \n \n #ifndef DIFFERENT_PRAGMAS\n-#pragma GCC target (\"sse4a,3dnow,avx,avx2,fma4,xop,aes,pclmul,popcnt,abm,lzcnt,bmi,bmi2,tbm,lwp,fsgsbase,rdrnd,f16c,rtm,rdseed,prfchw,adx,fxsr,xsaveopt,avx512f,avx512er,avx512cd,avx512pf,sha,prefetchwt1,avx512vl,avx512bw,avx512dq,avx512vbmi,avx512vbmi2,avx512ifma,avx5124fmaps,avx5124vnniw,avx512vpopcntdq,gfni,avx512bitalg,avx512bf16,avx512vp2intersect,serialize,tsxldtrk,amx-tile,amx-int8,amx-bf16,kl,widekl,avxvnni,avx512fp16,avxifma\")\n+#pragma GCC target (\"sse4a,3dnow,avx,avx2,fma4,xop,aes,pclmul,popcnt,abm,lzcnt,bmi,bmi2,tbm,lwp,fsgsbase,rdrnd,f16c,rtm,rdseed,prfchw,adx,fxsr,xsaveopt,avx512f,avx512er,avx512cd,avx512pf,sha,prefetchwt1,avx512vl,avx512bw,avx512dq,avx512vbmi,avx512vbmi2,avx512ifma,avx5124fmaps,avx5124vnniw,avx512vpopcntdq,gfni,avx512bitalg,avx512bf16,avx512vp2intersect,serialize,tsxldtrk,amx-tile,amx-int8,amx-bf16,kl,widekl,avxvnni,avx512fp16,avxifma,avxvnniint8\")\n #endif\n \n /* Following intrinsics require immediate arguments. They\n@@ -220,7 +220,7 @@ test_4 (_mm_cmpestrz, int, __m128i, int, __m128i, int, 1)\n \n /* immintrin.h (AVX/AVX2/RDRND/FSGSBASE/F16C/RTM/AVX512F/SHA) */\n #ifdef DIFFERENT_PRAGMAS\n-#pragma GCC target (\"avx,avx2,rdrnd,fsgsbase,f16c,rtm,avx512f,avx512er,avx512cd,avx512pf,sha,avx512vl,avx512bw,avx512dq,avx512ifma,avx512vbmi,avx512vbmi2,avx5124fmaps,avx5124vnniw,avx512vpopcntdq,gfni,avx512bitalg,avx512bf16,avx512vp2intersect,serialize,tsxldtrk,amx-tile,amx-int8,amx-bf16,kl,widekl,avxvnni,avx512fp16,avxifma\")\n+#pragma GCC target (\"avx,avx2,rdrnd,fsgsbase,f16c,rtm,avx512f,avx512er,avx512cd,avx512pf,sha,avx512vl,avx512bw,avx512dq,avx512ifma,avx512vbmi,avx512vbmi2,avx5124fmaps,avx5124vnniw,avx512vpopcntdq,gfni,avx512bitalg,avx512bf16,avx512vp2intersect,serialize,tsxldtrk,amx-tile,amx-int8,amx-bf16,kl,widekl,avxvnni,avx512fp16,avxifma,avxvnniint8\")\n #endif\n #include \n test_1 (_cvtss_sh, unsigned short, float, 1)\ndiff --git a/gcc/testsuite/gcc.target/i386/sse-23.c b/gcc/testsuite/gcc.target/i386/sse-23.c\nindex d3a233f90fc..270f4483491 100644\n--- a/gcc/testsuite/gcc.target/i386/sse-23.c\n+++ b/gcc/testsuite/gcc.target/i386/sse-23.c\n@@ -843,6 +843,6 @@\n #define 100 71985 100 71835 100 150 815k 1744 --:--:-- --:--:-- --:--:-- 817k __builtin_ia32_vpclmulqdq_v2di(A, B, C) __builtin_ia32_vpclmulqdq_v2di(A, B, 1) \n #define __builtin_ia32_vpclmulqdq_v8di(A, B, C) __builtin_ia32_vpclmulqdq_v8di(A, B, 1) \n \n-#pragma GCC target (\"sse4a,3dnow,avx,avx2,fma4,xop,aes,pclmul,popcnt,abm,lzcnt,bmi,bmi2,tbm,lwp,fsgsbase,rdrnd,f16c,fma,rtm,rdseed,prfchw,adx,fxsr,xsaveopt,avx512f,avx512er,avx512cd,avx512pf,sha,prefetchwt1,xsavec,xsaves,clflushopt,avx512bw,avx512dq,avx512vl,avx512vbmi,avx512ifma,avx5124fmaps,avx5124vnniw,avx512vpopcntdq,clwb,mwaitx,clzero,pku,sgx,rdpid,gfni,avx512vbmi2,vpclmulqdq,avx512bitalg,pconfig,wbnoinvd,avx512bf16,enqcmd,avx512vp2intersect,serialize,tsxldtrk,amx-tile,amx-int8,amx-bf16,kl,widekl,avxvnni,avx512fp16,avxifma\")\n+#pragma GCC target (\"sse4a,3dnow,avx,avx2,fma4,xop,aes,pclmul,popcnt,abm,lzcnt,bmi,bmi2,tbm,lwp,fsgsbase,rdrnd,f16c,fma,rtm,rdseed,prfchw,adx,fxsr,xsaveopt,avx512f,avx512er,avx512cd,avx512pf,sha,prefetchwt1,xsavec,xsaves,clflushopt,avx512bw,avx512dq,avx512vl,avx512vbmi,avx512ifma,avx5124fmaps,avx5124vnniw,avx512vpopcntdq,clwb,mwaitx,clzero,pku,sgx,rdpid,gfni,avx512vbmi2,vpclmulqdq,avx512bitalg,pconfig,wbnoinvd,avx512bf16,enqcmd,avx512vp2intersect,serialize,tsxldtrk,amx-tile,amx-int8,amx-bf16,kl,widekl,avxvnni,avx512fp16,avxifma,avxvnniint8\")\n \n #include \ndiff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp\nindex 3d779081ff6..d60d8c699ac 100644\n--- a/gcc/testsuite/lib/target-supports.exp\n+++ b/gcc/testsuite/lib/target-supports.exp\n@@ -9534,6 +9534,18 @@ proc check_effective_target_avxifma { } {\n } \"-O0 -mavxifma\" ]\n }\n \n+# Return 1 if avxvnniint8 instructions can be compiled.\n+proc check_effective_target_avxvnniint8 { } {\n+ return [check_no_compiler_messages avxvnniint8 object {\n+\ttypedef int __v8si __attribute__ ((__vector_size__ (32)));\n+\t__v8si\n+\t_mm256_dpbssd_epi32 (__v8si __A, __v8si __B, __v8si __C)\n+ {\n+\t return __builtin_ia32_vpdpbssd256 (__A, __B, __C);\n+\t}\n+ } \"-O0 -mavxvnniint8\" ]\n+}\n+\n # Return 1 if sse instructions can be compiled.\n proc check_effective_target_sse { } {\n return [check_no_compiler_messages sse object {\n","prefixes":["v2"]}+ exit 1 Build step 'Execute shell' marked build as failure Finished: FAILURE