Started by user snail Running as SYSTEM [EnvInject] - Loading node environment variables. Building remotely on docker-jenkins-agent in workspace /home/jenkins/agent/workspace/gcc-patch [WS-CLEANUP] Deleting project workspace... [WS-CLEANUP] Deferred wipeout is used... [WS-CLEANUP] Done The recommended git tool is: NONE using credential 0adb5fc7-caa2-429d-97d2-c7fa2fa1d884 Cloning the remote Git repository Using shallow clone with depth 1 Avoid fetching tags Cloning repository git@github.com:wangliu-iscas/gcc-patch.git/ > git init /home/jenkins/agent/workspace/gcc-patch # timeout=10 Fetching upstream changes from git@github.com:wangliu-iscas/gcc-patch.git/ > git --version # timeout=10 > git --version # 'git version 2.37.2' using GIT_SSH to set credentials patchwork github wangliu-iscas git ssh key Verifying host key using known hosts file, will automatically accept unseen keys > git fetch --no-tags --force --progress --depth=1 -- git@github.com:wangliu-iscas/gcc-patch.git/ +refs/heads/*:refs/remotes/origin/* # timeout=10 > git config remote.origin.url git@github.com:wangliu-iscas/gcc-patch.git/ # timeout=10 > git config --add remote.origin.fetch +refs/heads/*:refs/remotes/origin/* # timeout=10 Avoid second fetch > git rev-parse refs/remotes/origin/master^{commit} # timeout=10 Checking out Revision b61796663ba1fe8fb83203829398f3f89ec212b7 (refs/remotes/origin/master) > git config core.sparsecheckout # timeout=10 > git checkout -f b61796663ba1fe8fb83203829398f3f89ec212b7 # timeout=10 Commit message: "Fix nvptx-specific '-foffload-options' syntax in 'libgomp.c/reverse-offload-sm30.c'" > git rev-list --no-walk acdb24166d13d87c374e578d2ad5d58249171930 # timeout=10 First time build. Skipping changelog. [EnvInject] - Mask passwords that will be passed as build parameters. [EnvInject] - Executing scripts and injecting environment variables after the SCM step. [EnvInject] - Injecting as environment variables the properties content GITHUB_REPO=https://github.com/wangliu-iscas/ PATCHWORK_URL=https://patchwork.plctlab.org [EnvInject] - Variables injected successfully. [gcc-patch] $ /usr/bin/env bash /tmp/jenkins15495091451203512891.sh + git config pw.server https://patchwork.plctlab.org/api/1.2/ + git config pw.project gcc-patch + git config pw.token [*******] ++ date +%Y-%m + now_date=2022-10 + echo 2022-10 2022-10 ++ curl -s -H 'Authorization: Token [*******]' 'https://patchwork.plctlab.org/api/1.2/bundles/?project=gcc-patch&per_page=999' + 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Improve Z flag handling on H8 | | | 1628 OpenACC: Fix struct-component-kind-1.c test | | | 1629 Adding a new thread model to GCC | | | 1630 libstdc++: Use ///< for inline documentation | | | 1632 c++: Disallow jumps into statement expressions | | | 1633 [committed] tree-cfg: Fix a verification diagnostic typo [PR107121] | | | 1634 Fortran: Add OpenMP's assume(s) directives | | | 1636 [RFC.,Fortran] Some clobbering for INTENT(OUT) arrays | | | 1639 Set discriminators for call stmts on the same line within the same basic block | | | 1645 arm: Add missing early clobber to MVE vrev64q_m patterns | | | 1650 [COMMITTED] Do not compare incompatible ranges in ipa-prop. | | | 1653 [COMMITTED] Do not compare nonzero masks for varying. | | | 1651 [COMMITTED] Avoid comparing ranges when sub-ranges is 0. | | | 1652 [COMMITTED] Do not pessimize range in set_nonzero_bits. | | | 1654 [committed] libstdc++: Fix tests broken by C++23 P2266R3 "Simpler implicit move" | | | 1655 [COMMITTED] libsanitizer: Fix Solaris 11.3 compilation of sanitizer_procmaps_solaris.cpp [PR105531] | | | 1657 [committed] c: Adjust LDBL_EPSILON for C2x for IBM long double | | | 1658 PR tree-optimization/107109 - Don't process undefined range. | | | 1661 c++, c, v2: Implement C++23 P1774R8 - Portable assumptions [PR106654] | | | 1662 elf: ELF toolchain --without-{headers, newlib} should provide stdint.h | | | 1663 [committed] libstdc++: Update status docs for compare_exchange padding bits | | | 1664 aarch64: update Ampere-1 core definition | | | 1665 aarch64: fix off-by-one in reading cpuinfo | | | 1666 diagnostics: Add test for fixed _Pragma location issue [PR91669] | | | 1667 c++: install cp-trait.def as part of plugin headers [PR107136] | | | 1668 libstdc++: Implement ranges::join_with_view from P2441R2 | | | 1669 [COMMITTED,PR107130] range-ops: Separate out ffs and popcount optimizations. | | | 1670 [COMMITTED] Convert nonzero mask in irange to wide_int. | | | 1674 middle-end, c++, i386, libgcc: std::bfloat16_t and __bf16 arithmetic support | | | 1675 attribs: Add missing auto_diagnostic_group 3 times | | | 1680 cselib: Skip BImode while keeping track of subvalue relations [PR107088] | | | 1685 [committed] libstdc++: Define functions for freestanding [PR107135] | | | 1683 [committed] libstdc++: Make work freestanding [PR107134] | | | 1682 [committed] libstdc++: Enable std::hash> [PR107139] | | | 1684 [committed] libstdc++: Disable test for freestanding | | | 1686 [RESEND,1/1] p1689r5: initial support | | | 1687 Add --without-makeinfo | | | 1688 [GCC13,V5,1/2] Add a new option -fstrict-flex-arrays[=n] and new attribute strict_flex_array | | | 1689 [GCC13,V5,2/2] Use array_at_struct_end_p in __builtin_object_size [PR101836] | | | 1692 aarch64: Define __ARM_FEATURE_RCPC | | | 1693 [committed] libstdc++: Refactor seed sequence constraints in | | | 1694 [committed] libstdc++: Use new built-ins __remove_cv, __remove_reference etc. | | | 1695 [committed] libstdc++: Fix test FAIL for old std::string ABI | | | 1696 [RFC] libstdc++: Generate error_constants.h from [PR104883] | | | 1697 improved const shifts for AVR targets | | | 1698 [AArch64] Improve immediate expansion [PR106583] | | | 1699 c++ modules: lazy loading from within template [PR99377] | | | 1700 [COMMITTED] Remove assert from set_nonzero_bits. | | | 1701 Fortran: reject procedures and procedure pointers as output item [PR107074] | | | 1703 Fortran: error recovery for invalid types in array constructors [PR107000] | | | 1704 [pushed] c++: fix debug info for array temporary [PR107154] | | | 1705 [v2] c-family: ICE with [[gnu::nocf_check]] [PR106937] | | | 1706 [committed] analyzer: widening_svalues take a function_point rather than a program_point | | | 1707 [committed] analyzer: fold -(-(VAL)) to VAL | | | 1709 [committed] analyzer: move region_model_manager decl to its own header | | | 1708 [committed] analyzer: revamp side-effects of call summaries [PR107072] | | | 1720 c++, c, v3: Implement C++23 P1774R8 - Portable assumptions [PR106654] | | | 1721 [pushed] testsuite: mark a test with xfail | | | 1722 [pushed] analyzer: remove unused variables | | | 1723 IPA: support -flto + -flive-patching=inline-clone | | | 1724 c: support attribs starting with '_' | | | 1725 c: support attribs starting with '_' | | | 1728 [1/2] gcov: test switch/break line counts | | | 1726 [2/2] Split edge when edge locus and dest don't match | | | 1727 c++: Improve handling of foreigner namespace attributes | | | 1729 [COMMITTED,PR,tree-optimization/107052] range-ops: Pass nonzero masks through cast. | | | 1730 [COMMITTED,PR,tree-optimization/107052] range-ops: Pass nonzero masks through cast. | | | 1731 [COMMITTED,PR,tree-optimization/107052] range-ops: Take into account nonzero mask in popcount. | | | 1732 [AArch64] Improve bit tests [PR105773] | | | 1733 [committed] libstdc++: Guard use of new built-in with __has_builtin | | | 1734 [committed] libtdc++: Regenerate Makefile.in after freestanding header changes | | | 1735 [COMMITTED] range-op: Keep nonzero mask up to date with truncating casts. | | | 1736 [pushed] c++: lvalue_kind tweak | | | 1737 [v2] testsuite: Sanitize fails for SP FPU on Arm | | | 1738 Fix wrong code generated by unroll-and-jam pass | | | 1739 [committed] analyzer: fix ICEs seen with call summaries on PR 107060 | | | 1740 [committed] analyzer: simplify some includes | | | 1741 [committed] analyzer: add regression test for PR 107158 | | | 1742 [pushed] contrib: run fetch before pushing Daily bump | | | 1744 [1/3] rs6000: Remove "wD" from *vsx_extract__store | | | 1743 [2/3] rs6000: Rework vsx_extract_ | | | 1745 [3/3] rs6000: Remove the wD constraint | | | 1747 [GCC13,V6,1/2] Add a new option -fstrict-flex-arrays[=n] and new attribute strict_flex_array | | | 1746 [GCC13,V6,2/2] Use array_at_struct_end_p in __builtin_object_size [PR101836] | | | 1748 c++: fixes for derived-to-base reference binding [PR107085] | | | 1749 c: C2x typeof | | | 1750 c++: remove optimize_specialization_lookup_p | | | 1753 [COMMITTED] Do not double print INF and NAN in frange pretty printer. | | | 1755 [COMMITTED] Do not check finite_operands_p twice in range-ops-float. | | | 1754 [COMMITTED] Setting explicit NANs sets UNDEFINED for -ffinite-math-only. | | | 1756 [committed] openmp: Map holds clause to IFN_ASSUME for C/C++ | | | 1757 [committed] arc: Remove max-page-size and common-page-size forced setting | | | 1758 [pushed] git_update_version: add robust logging | | | 1759 [COMMITED] ada: Fix spurious warning on unreferenced refinement constituents | | | 1760 [COMMITED] ada: Disable slice-of-component optimization in some cases | | | 1761 [COMMITED] ada: Do not issue compiler warnings in GNATprove mode | | | 1762 [COMMITED] ada: Clean up slice-of-component optimization | | | 1763 [v2] aarch64: fix off-by-one in reading cpuinfo | | | 1764 [COMMITED] ada: Accessibility error incorrectly flagged on call within Pre'Class expression | | | 1765 [COMMITED] ada: Incorrect inferences drawn from if/elsif/while conditions with -gnatVo | | | 1767 [COMMITED] ada: Add C declarations for Storage Model support | | | 1768 [v2] aarch64: update Ampere-1 core definition | | | 1766 [COMMITED] ada: Fix inserting of validity checks in lock-free protected subprograms | | | 1772 [COMMITED] ada: stack scrubbing: exemplify codegen changes | | | 1769 [COMMITED] ada: hardened booleans: exemplify codegen changes | | | 1770 [COMMITED] ada: hardened conditionals: exemplify codegen changes | | | 1771 [COMMITED] ada: Cleanup related to lock-free protected subprograms | | | 1773 [COMMITED] ada: Reject conditional goto in lock-free protected subprograms | | | 1774 [COMMITED] ada: Minor potential bug in sem_ch6.adb | | | 1775 [COMMITED] ada: Implementation of support for storage models in gigi | | | 1778 tree-optimization/107107 - tail-merging VN wrong-code | | | 1779 [RFC] Add op1_range for __builtin_signbit. | | | 1780 openmp: Map holds clause to IFN_ASSUME for Fortran | | | 1782 middle-end/107115 - avoid bogus redundant store removal during RTL expansion | | | 1783 [RFC] c++: parser - Support for target address spaces in C++ | | | 1784 [v2] c++: fixes for derived-to-base reference binding [PR107085] | | | 1785 gcc-12: FTBFS on hurd-i386 | | | 1786 c++ modules: static var in inline function [PR104433] | | | 1787 c++, v2: Improve handling of foreigner namespace attributes | | | 1788 Reduce DF computation at -O0 | | | 1789 Fix gdb FilteringTypePrinter (again) | | | 1790 [RFA] gimplify: prevent some C++ temporary elision | | | 1791 c++, v3: Improve handling of foreigner namespace attributes | | | 1792 [v2] libstdc++: basic_filebuf: don't flush more often than necessary. | | | 1794 [committed] analyzer: fixes to call_summary_replay::dump_to_pp | | | 1793 [committed] analyzer: fix another ICE in PR 107158 | | | 1795 [COMMITTED,PR107170] Avoid copying incompatible types in legacy VRP. | | | 1796 [rs6000] Fix addg6s builtin with long long parameters. (PR100693) | | | 1797 [v3] c++: fixes for derived-to-base reference binding [PR107085] | | | 1798 [committed] libgcc, arc: Fix build | | | 1799 [v3] c-family: ICE with [[gnu::nocf_check]] [PR106937] | | | 1800 Go patch committed: better argument checking for builtins | | | 1802 PR middle-end/88345: Honor -falign-functions=N even optimized for size. | | | 1804 [committed] Fix comment typos | | | 1805 [pushed] remove dead variables | | | 1806 [pushed] fix clang warnings | | | 1807 [pushed] libdecnumber: remove unused variable | | | 1808 [pushed] contrib: remove extra fetch from git_update_version | | | 1809 [committed] libstdc++: Use bold style for DR titles in the manual | | | 1810 [committed] libstdc++: Shuffle header dependencies of | | | 1811 [committed] libstdc++: Add --disable-libstdcxx-hosted as an alias for hosted-libstdcxx | | | 1812 tree-optimization/107153 - autopar SSA update issue | | | 1813 c++: Lambda context mangling | | | 1814 [v3] testsuite: Sanitize fails for SP FPU on Arm | | | 1815 doc: -falign-functions doesn't override the __attribute__((align(N))) | | | 1816 libiberty: Demangle variadic template lambdas | | | 1817 [v5] libgomp/nvptx: Prepare for reverse-offload callback handling | | | 1818 c++ modules: ICE with bitfield member in class template | | | 1819 libstdc++: Allow emergency EH alloc pool size to be tuned [PR68606] | | | 1820 [v4] c++: fixes for derived-to-base reference binding [PR107085] | | | 1821 [committed] analyzer: extract bits from integer constants [PR105783] | | | 1822 [v3] Fortran: error recovery for invalid types in array constructors [PR107000] | | | 1823 [PATCHv2] libstdc++: Mark pieces of gnu-linux/os_support.h linux-specific | | | 1824 [v4] c-family: ICE with [[gnu::nocf_check]] [PR106937] | | | 1825 [v5] c++: fixes for derived-to-base reference binding [PR107085] | | | 1826 [pushed] c++: track whether we expect a TARGET_EXPR to be elided | | | 1835 preprocessor: Fix tracking of system header state [PR60014, PR60723] | | | 1837 [committed] pru: Optimize DI shifts | | | 1838 [committed] pru: Add cbranchdi4 pattern | | | 1839 Fortran: fix check of polymorphic elements in data transfers [PR100971] | | | 1840 [v4,1/4] OpenMP: Pointers and member mappings | | | 1841 [v4,2/4] OpenMP/OpenACC: Reindent TO/FROM/_CACHE_ stanza in {c_}finish_omp_clause | | | 1843 [v4,3/4] OpenMP/OpenACC: Rework clause expansion and nested struct handling | | | 1842 [v4,4/4] OpenMP/OpenACC: Unordered/non-constant component offset struct mapping | | | 1846 [x86] Fix unrecognizable insn of cvtss2si. | | | 1847 [committed,1/5] arc: Fix enter pattern instruction's offsets | | | 1848 [committed,2/5] arc: Remove Rcr constraint | | | 1850 [committed,3/5] arc: Remove Rcw constraint | | | 1851 [committed,4/5] arc: Remove Rcq constraint. | | | 1849 [committed,5/5] arc: Remove obsolete mRcq and mRcw options. | | | 1852 [committed] openmp, fortran: Fix up IFN_ASSUME call | | | 1853 [GCC] arm: Add cde feature support for Cortex-M55 CPU. | | | 1854 middle-end IFN_ASSUME support [PR106654] | | | 1855 Require fgraphite effective target for pr107153.c test [PR107153] | | | 1856 [RFT] Vectorization of first-order recurrences | | | 1857 [committed] libstdc++: std::make_signed_t should be ill-formed | | | 1862 [COMMITTED] Return non-legacy ranges in range.h. | | | 1859 [COMMITTED] x UNORD x should set NAN on the TRUE side (and !NAN on the FALSE side). | | | 1858 [COMMITTED] The true side of x != x should set NAN. | | | 1861 [COMMITTED] Add frange::maybe_isnan (bool sign). | | | 1860 [COMMITTED] Make range-op-float entries public. | | | 1863 [committed] RISC-V: Add newline to the end of file [NFC] | | | 1864 [committed] RISC-V: Adjust testcase for rvv/base/user-1.c | | | 1865 [committed] RISC-V: Add riscv_vector.h wrapper in testsuite to prevent pull in stdint.h from C library | | | 1866 RISC-V: Add missing vsetvl instruction type. | | | 1867 RISC-V: move struct vector_type_info from *.h to *.cc. | | | 1868 RISC-V: move struct vector_type_info from *.h to *.cc and change "user_name" into "name". | | | 1869 [RFC] Add support for vectors in comparisons (like the C++ frontend does) | | | 1870 Restore default 'sorry' 'TARGET_ASM_CONSTRUCTOR', 'TARGET_ASM_DESTRUCTOR' (was: [PATCH 1/3] STABS: remove -gstabs and -gxcoff functionality) | | | 1876 1/19 modula2 front end: changes outside gcc/m2, libgm2 and gcc/testsuite. | | | 1874 2/19 modula2 front end: Make-lang.in | | | 1882 4/19 modula2 front end: libgm2/libm2pim contents | | | 1872 3/19 modula2 front end: gm2 driver files. | | | 1881 5/19 modula2 front end: libgm2/libm2iso contents | | | 1873 6/19 modula2 front end: libgm2/libm2min contents | | | 1871 7/19 modula2 front end: libgm2/libm2log contents | | | 1875 8/19 modula2 front end: libgm2 contents | | | 1877 9/19 modula2 front end: plugin source files | | | 1883 11/19 modula2 front end: gimple interface *[a-d]*.cc | | | 1884 10/19 modula2 front end: gimple interface header files *.h and *.def | | | 1887 12/19 modula2 front end: gimple interface *[e-f]*.cc | | | 1878 13/19 modula2 front end: gimple interface *[g-m]*.cc | | | 1879 14/19 modula2 front end: gimple interface remainder | | | 1886 15/19 modula2 front end: cc1gm2 additional non modula2 source files | | | 1885 16/19 modula2 front end: bootstrap and documentation tools | | | 1880 17/19 modula2 front end: dejagnu expect library scripts | | | 1888 Avoid calling tracer.trailer() twice. | | | 1889 [v5] c-family: ICE with [[gnu::nocf_check]] [PR106937] | | | 1891 Go patch committed: Only build thunk struct type when needed | | | 1892 Go patch committed: Treat S("") as a string constant | | | 1896 [ICE] Fix for PR107193. | | | 1898 libstdc++: Implement ranges::repeat_view from P2474R2 | | | 1899 [committed,PR,rtl-optimization/107182] Clear EDGE_CROSSING for jump->ret optimization | | | 1900 RISC-V: Move function place to make it looks better. | | | 1901 RISC-V: Refine register_builtin_types function. | | | 1902 RISC-V: Clang-format add_vector_attribute function. | | | 1903 RISC-V: Remove TUPLE size macro define. | | | 1904 RISC-V: Refine riscv-vector-builtins.o include files and makefile. | | | 1905 RISC-V: Clang-format vector_type_index. | | | 1906 [(pushed)] ranger: add override keyword | | | 1907 [PATCH-1,rs6000] Generate permute index directly for little endian target [PR100866] | | | 1908 [x86] Add define_insn_and_split to support general version of "kxnor". | | | 1909 [COMMITTED,PR107195] Set range to zero when nonzero mask is 0. | | | 1913 [committed,1/6] amdgcn: add multiple vector sizes | | | 1910 [committed,2/6] amdgcn: Resolve insn conditions at compile time | | | 1911 [committed,3/6] amdgcn: Add vec_extract for partial vectors | | | 1912 [committed,4/6] amdgcn: vec_init for multiple vector sizes | | | 1914 [committed,5/6] amdgcn: Add vector integer negate insn | | | 1915 [committed,6/6] amdgcn: vector testsuite tweaks | | | 1916 tree-optimization/107212 - SLP reduction of reduction paths | | | 1917 libiberty: Demangling 'M' prefixes | | | 1918 [1/2] gcov: test switch/break line counts | | | 1919 [2/2] gcov: test line count for label in then/else block | | | 1920 c++: Implement excess precision support for C++ [PR107097, PR323] | | | 1921 middle-end, v2: IFN_ASSUME support [PR106654] | | | 1922 [COMMITTED] Move TRUE case first in range-op.cc. | | | 1923 [COMMITTED] Share common ordered comparison code with UN*_EXPR. | | | 1925 [COMMITTED] Implement op1_range operators for unordered comparisons. | | | 1924 [COMMITTED] Implement ABS_EXPR operator for frange. | | | 1926 c++ modules: ICE with templated friend and std namespace [PR100134] | | | 1927 testsuite: Only run -fcf-protection test on i?86/x86_64 [PR107213] | | | 1930 Fortran: check types of source expressions before conversion [PR107215] | | | 1931 c++: ICE with VEC_INIT_EXPR and defarg [PR106925] | | | 1932 Fortran: check types of operands of arithmetic binary operations [PR107217] | | | 1933 [v2,1/3] doc: -falign-functions doesn't override the __attribute__((align(N))) | | | 1935 [v2,2/3] doc: -falign-functions is ignored under -Os | | | 1934 [v2,3/3] doc: -falign-functions is ignored for cold/size-optimized functions | | | 1936 coroutines: Use cp_build_init_expr consistently. | | | 1937 [Ada] Enable support for atomic primitives on SPARC/Linux | | | 1938 Fix emit_group_store regression on big-endian | | | 1939 RISC-V: Add new line at end of file. | | | 1940 Remove AVX512_VP2INTERSECT from PTA_SAPPHIRERAPIDS | | | 1942 LoongArch: Fixed a bug in the loongarch architecture of libitm package. | | | 1943 [V4] rs6000: cannot_force_const_mem for HIGH code rtx[PR106460] | | | 1945 [COMMITTED] Add default relation_kind to floating point range-op entries. | | | 1948 [COMMITTED] Add an frange(type) constructor analogous to the irange version. | | | 1946 [COMMITTED] Disable tree to bool conversion in frange::update_nan. | | | 1944 [COMMITTED] Add method to query the sign of a NAN. | | | 1947 [COMMITTED] Add stubs for floating point range-op tests. | | | 1949 [(pushed)] regenerate configure files | | | 1950 MAINTAINERS: Add myself for write after approval | | | 1951 [v2] rs6000: Rework option -mpowerpc64 handling [PR106680] | | | 1952 machmode: Introduce GET_MODE_NEXT_MODE with previous GET_MODE_WIDER_MODE meaning, add new GET_MODE_WIDER_MODE | | | 1953 [COMMITTED] gcov: rename gcov_write_summary | | | 1954 Add condition coverage profiling | | | 1955 machmode, v2: Introduce GET_MODE_NEXT_MODE with previous GET_MODE_WIDER_MODE meaning, add new GET_MODE_WIDER_MODE | | | 1956 libgcc: Quote variable in Makefile.in | | | 1957 libgomp: Add offload_device_gcn check, add requires-4a.c test | | | 1958 LoongArch: implement count_{leading,trailing}_zeros | | | 1959 [pushed] c++: defer all consteval in default args [DR2631] | | | 1960 [v2] c++: ICE with VEC_INIT_EXPR and defarg [PR106925] | | | 1961 [committed] libgomp: Fix up creation of artificial teams | | | 1962 [committed] libgomp: Add omp_in_explicit_task support | | | 1963 [committed] libgomp: Fix up OpenMP 5.2 feature bullet | | | 1965 vect: Don't pattern match BITFIELD_REF's of non-integrals [PR107226] | | | 1964 ifcvt: Fix bitpos calculation in bitfield lowering [PR107229] | | | 1966 [COMMITTED] Add range-op entry for floating point NEGATE_EXPR. | | | 1967 xtensa: Add workaround for pSRAM cache issue in ESP32 | | | 1968 [wwwdocs] porting_to: Two-stage overload resolution for implicit move removed | | | 1969 Fortran: simplify array constructors with typespec [PR93483, PR107216, PR107219] | | | 1970 libstdc++: respect with-{headers, newlib} for default hosted value | | | 1971 PR 107189 Remove useless _Alloc_node | | | 1972 [committed] c: Do not use *_IS_IEC_60559 == 2 | | | 1973 Optimize indentical permuation in my last r13-3212-gb88adba751da63 | | | 1974 Optimize identical permutation in my last r13-3212-gb88adba751da63 | | | 1975 middle-end, v3: IFN_ASSUME support [PR106654] | | | 1995 [DOCS] Python Language Conventions | | | 2016 Diagnose return statement in match.pd (with { ... } expressions | | | 2033 Fix bogus -Wstringop-overflow warning | | | 2037 [COMMITTED] Add op1_op2_relation for float operands. | | | 2040 [PR24021] Implement PLUS_EXPR range-op entry for floats. | | | 2049 tree-optimization/107160 - avoid reusing multiple accumulators | | | 2052 tree-optimization/107247 - reduce SLP reduction accumulator | | | 2057 [V1] RISC-V: Fix a redefinition bug for the fd-4.c | | | 2061 use proper DECL_INITIAL for VTV | | | 2073 [COMMITTED,1/4] Add partial equivalence support to the relation oracle. | | | 2074 [COMMITTED,2/4] Add equivalence iterator to relation oracle. | | | 2076 [COMMITTED,3/4] Add partial equivalence recognition to cast and bitwise and. | | | 2075 [COMMITTED,4/4] PR tree-optimization/102540 - propagate partial equivs in the cache. | | | 2077 c++ modules: verify_type failure with typedef enum [PR106848] | | | 2091 c++, v2: Implement excess precision support for C++ [PR107097, PR323] | | | 2094 c++: Excess precision for ? int : float or int == float [PR107097, PR82071, PR87390] | | | 2095 middle-end, c++, i386, libgcc, v2: std::bfloat16_t and __bf16 arithmetic support | | | 2099 testsuite: Fix failure in test pr105586.c [PR107171] | | | 2242 libgomp: Add Fortran testcases for omp_in_explicit_task | | | 2343 c++ modules: ICE with dynamic_cast [PR106304] | | | 2353 [committed] analyzer: fix ICE introduced in r13-3168 [PR107210] | | | 2447 Always enable LRA | | | 2463 [committed] c: C2x storage class specifiers in compound literals | | | 2465 [v2] LoongArch: Optimize the implementation of stack check. | | | 2480 rs6000: Enable const_anchor for 'addi' | | | 2530 [committed] wwwdocs: *: Consistently format around | | | 2550 [1/2] Initial Raptorlake Support | | | 2549 [2/2] Initial Meteorlake Support | | | 2553 [1/6] Support Intel AVX-IFMA | | | 2556 [2/6] Support Intel AVX-VNNI-INT8 | | | 2554 [3/6] i386: Add intrinsic for vector __bf16 | | | 2559 [4/6] Support Intel AVX-NE-CONVERT | | | 2558 [5/6] Support Intel CMPccXADD | | | 2555 [6/6] Initial Sierra Forest Support | | | 2563 Support Intel AMX-FP16 ISA | | | 2571 [1/3] Add a parameter for the builtin function of prefetch to align with LLVM | | | 2570 [2/3] Support Intel prefetchit0/t1 | | | 2583 [1/2] Add a parameter for the builtin function of prefetch to align with LLVM | | | 2582 [2/2] Support Intel prefetchit0/t1 | | | 2600 [committed] libstdc++: Use markdown in Doxygen comment | | | 2629 tree-optimization/107254 - check and support live lanes from permutes | | | 2634 [SPARC] Fix PR target/107248 | | | 2635 [COMMITTED] Add cases for CFN_BUILT_IN_SIGNBIT[FL]. | | | 2653 xtensa: Prepare the transition from Reload to LRA | | | 2696 [og12] amdgcn: Use FLAT addressing for all functions with pointer arguments | | | 2697 [og12] OpenACC: Don't gang-privatize artificial variables | | | 2703 [COMMITTED] Drop -0.0 in frange::set() for !HONOR_SIGNED_ZEROS. | | | 2702 [COMMITTED] Normalize ranges over the range for both bounds when -ffinite-math-only. | | | 2704 [COMMITTED] Replace CFN_BUILTIN_SIGNBIT* cases with CASE_FLT_FN. | | | 2705 Check rvc_normal in real_isdenormal. | | | 2714 [committed] libstdc++: Simplify print_raw function for debug assertions | | | 2715 [committed] libstdc++: Disable all emergency EH pool code if obj-count == 0 | | | 2724 Implement range-op entry for __builtin_copysign. | | | 2754 [committed] gfortran.dg/c-interop/deferred-character-2.f90: Fix dg-do | | | 2756 libgcc: Move cfa_how into potential padding in struct frame_state_reg_info | | | 2757 c++ modules: streaming constexpr_fundef [PR101449] | | | 2759 libgomp: fix hang on fatal error | | | 2784 [committed] wwwdocs: *: Omit trailing slash for CSS references | | | 2859 [v2] RISC-V: Implement __clear_cache via __builtin___clear_cache | | | 2833 Fortran: Fixes for kind=4 characters strings [PR107266] | | | 2889 RISC-V: Reorganize mangle_builtin_type.[NFC] | | | 2890 [committed] preprocessor: C2x identifier rules | | | 2903 [v3] btf: Add support to BTF_KIND_ENUM64 type | | | 2920 libstdc++: Address '-Wunused-function' for 'print_raw' (was: [committed] libstdc++: Simplify print_raw function for debug assertions) | | | 2971 [committed] libstdc++: Fix uses_allocator_construction args for cv pair (LWG 3677) | | | 2972 [committed] libstdc++: Implement constexpr std::to_chars for C++23 (P2291R3) | | | 2979 [committed] Fix bug in register move costing on H8/300 | | | 2998 builtins: Add various __builtin_*f{16,32,64,128,32x,64x,128x} builtins | | | 2999 [RFC] libstdc++, v2: Partial library support for std::float{16,32,64,128}_t | | | 3043 [committed] Rename "Z" constraint on H8/300 to "Zz". | | | 3073 [committed] Add new constraints for upcoming autoinc fixes on the H8 | | | 3142 microblaze: use strverscmp() in MICROBLAZE_VERSION_COMPARE() | | | 3146 Fortran: check type of operands of logical operations, comparisons [PR107272] | | | 3148 Don't print discriminators for -fcompare-debug. | | | 3199 Move scanning pass of forwprop-19.c to dse1 for r13-3212-gb88adba751da63 | | | 3252 RISC-V: Fix format[NFC] | | | 3257 Add 'c-c++-common/torture/pr107195-1.c' [PR107195] (was: [COMMITTED] [PR107195] Set range to zero when nonzero mask is 0.) | | | 3271 RISC-V: Add RVV intrinsic basic framework. | | | 3280 RISC-V: Add RVV vsetvl/vsetvlmax intrinsics and tests. | +------------+---------------------------------------------------------------------------------------------------------------------------------------------------+ + git config pull.rebase false + git fetch origin master From github.com:wangliu-iscas/gcc-patch * branch master -> FETCH_HEAD + git checkout master Switched to a new branch 'master' branch 'master' set up to track 'origin/master'. + git pull origin master From github.com:wangliu-iscas/gcc-patch * branch master -> FETCH_HEAD Already up to date. + git fetch origin upstream-master From github.com:wangliu-iscas/gcc-patch * branch upstream-master -> FETCH_HEAD + git checkout upstream-master Switched to a new branch 'upstream-master' branch 'upstream-master' set up to track 'origin/upstream-master'. + git remote add upstream https://github.com/gcc-mirror/gcc.git + git pull upstream master From https://github.com/gcc-mirror/gcc * branch master -> FETCH_HEAD * [new branch] master -> upstream/master Already up to date. + git push -u origin upstream-master Everything up-to-date branch 'upstream-master' set up to track 'origin/upstream-master'. + git checkout master Switched to branch 'master' Your branch is up to date with 'origin/master'. + git merge upstream-master Already up to date. + git push -u origin master Everything up-to-date branch 'master' set up to track 'origin/master'. + branchname=series2195-patch3280 ++ git branch -a ++ grep 'series2195-patch3280$' + checkbranch= + checkbranchresult=null + '[' null = series2195-patch3280 ']' + git checkout -b series2195-patch3280 Switched to a new branch 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tests.","date":"2022-10-17T08:36:42","submitter":{"id":36,"url":"https://patchwork.plctlab.org/api/1.2/people/36/","name":"juzhe.zhong@rivai.ai","email":"juzhe.zhong@rivai.ai"},"version":1,"total":1,"received_total":1,"received_all":true,"mbox":"https://patchwork.plctlab.org/series/2195/mbox/","cover_letter":null,"patches":[{"id":3280,"url":"https://patchwork.plctlab.org/api/1.2/patches/3280/","web_url":"https://patchwork.plctlab.org/project/gcc-patch/patch/20221017083642.184867-1-juzhe.zhong@rivai.ai/","msgid":"<20221017083642.184867-1-juzhe.zhong@rivai.ai>","list_archive_url":null,"date":"2022-10-17T08:36:42","name":"RISC-V: Add RVV vsetvl/vsetvlmax intrinsics and tests.","mbox":"https://patchwork.plctlab.org/project/gcc-patch/patch/20221017083642.184867-1-juzhe.zhong@rivai.ai/mbox/"}]}' ++ jq '.patches[] | (.id|tostring) + "," + .mbox' ++ echo '{"id":2195,"url":"https://patchwork.plctlab.org/api/1.2/series/2195/","web_url":"https://patchwork.plctlab.org/project/gcc-patch/list/?series=2195","project":{"id":1,"url":"https://patchwork.plctlab.org/api/1.2/projects/1/","name":"gcc-patch","link_name":"gcc-patch","list_id":"gcc-patches.gcc.gnu.org","list_email":"gcc-patches@gcc.gnu.org","web_url":"https://gcc.gnu.org/mailman/listinfo/gcc-patches","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"name":"RISC-V: Add RVV vsetvl/vsetvlmax intrinsics and tests.","date":"2022-10-17T08:36:42","submitter":{"id":36,"url":"https://patchwork.plctlab.org/api/1.2/people/36/","name":"juzhe.zhong@rivai.ai","email":"juzhe.zhong@rivai.ai"},"version":1,"total":1,"received_total":1,"received_all":true,"mbox":"https://patchwork.plctlab.org/series/2195/mbox/","cover_letter":null,"patches":[{"id":3280,"url":"https://patchwork.plctlab.org/api/1.2/patches/3280/","web_url":"https://patchwork.plctlab.org/project/gcc-patch/patch/20221017083642.184867-1-juzhe.zhong@rivai.ai/","msgid":"<20221017083642.184867-1-juzhe.zhong@rivai.ai>","list_archive_url":null,"date":"2022-10-17T08:36:42","name":"RISC-V: Add RVV vsetvl/vsetvlmax intrinsics and tests.","mbox":"https://patchwork.plctlab.org/project/gcc-patch/patch/20221017083642.184867-1-juzhe.zhong@rivai.ai/mbox/"}]}' + patchid_patchurl='"3280,https://patchwork.plctlab.org/project/gcc-patch/patch/20221017083642.184867-1-juzhe.zhong@rivai.ai/mbox/"' + echo '"3280,https://patchwork.plctlab.org/project/gcc-patch/patch/20221017083642.184867-1-juzhe.zhong@rivai.ai/mbox/"' + IFS=, + read -r series_patch_id series_patch_url ++ echo '"3280' ++ sed 's/"//g' + series_patch_id=3280 ++ echo 'https://patchwork.plctlab.org/project/gcc-patch/patch/20221017083642.184867-1-juzhe.zhong@rivai.ai/mbox/"' ++ sed 's/"//g' + series_patch_url=https://patchwork.plctlab.org/project/gcc-patch/patch/20221017083642.184867-1-juzhe.zhong@rivai.ai/mbox/ ++ git rev-parse HEAD + commitid_before=b61796663ba1fe8fb83203829398f3f89ec212b7 + eval '+++ declare -p bout bret declare -- bout="Applying: RISC-V: Add RVV vsetvl/vsetvlmax intrinsics and tests. error: sha1 information is lacking or useless (gcc/config.gcc). error: could not build fake ancestor hint: Use '\''git am --show-current-patch=diff'\'' to see the failed patch Patch failed at 0001 RISC-V: Add RVV vsetvl/vsetvlmax intrinsics and tests. When you have resolved this problem, run \"git am --continue\". If you prefer to skip this patch, run \"git am --skip\" instead. To restore the original branch and stop patching, run \"git am --abort\"." declare -- bret="128" ++ berr='\''++++ git_am https://patchwork.plctlab.org/project/gcc-patch/patch/20221017083642.184867-1-juzhe.zhong@rivai.ai/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/gcc-patch/patch/20221017083642.184867-1-juzhe.zhong@rivai.ai/mbox/ ++++ curl https://patchwork.plctlab.org/project/gcc-patch/patch/20221017083642.184867-1-juzhe.zhong@rivai.ai/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 56090 100 56090 0 0 1304k 0 --:--:-- --:--:-- --:--:-- 1335k +++ bout='\''\'\'''\''Applying: RISC-V: Add RVV vsetvl/vsetvlmax intrinsics and tests. error: sha1 information is lacking or useless (gcc/config.gcc). error: could not build fake ancestor hint: Use '\''\'\'''\''\'\''\'\'''\'''\''\'\'''\''git am --show-current-patch=diff'\''\'\'''\''\'\''\'\'''\'''\''\'\'''\'' to see the failed patch Patch failed at 0001 RISC-V: Add RVV vsetvl/vsetvlmax intrinsics and tests. When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort".'\''\'\'''\'' +++ bret=128'\'' ++ declare -p berr declare -- berr="++++ git_am https://patchwork.plctlab.org/project/gcc-patch/patch/20221017083642.184867-1-juzhe.zhong@rivai.ai/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/gcc-patch/patch/20221017083642.184867-1-juzhe.zhong@rivai.ai/mbox/ ++++ curl https://patchwork.plctlab.org/project/gcc-patch/patch/20221017083642.184867-1-juzhe.zhong@rivai.ai/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 56090 100 56090 0 0 1304k 0 --:--:-- --:--:-- --:--:-- 1335k +++ bout='\''Applying: RISC-V: Add RVV vsetvl/vsetvlmax intrinsics and tests. error: sha1 information is lacking or useless (gcc/config.gcc). error: could not build fake ancestor hint: Use '\''\\'\'''\''git am --show-current-patch=diff'\''\\'\'''\'' to see the failed patch Patch failed at 0001 RISC-V: Add RVV vsetvl/vsetvlmax intrinsics and tests. When you have resolved this problem, run \"git am --continue\". If you prefer to skip this patch, run \"git am --skip\" instead. To restore the original branch and stop patching, run \"git am --abort\".'\'' +++ bret=128"' ++ +++ declare -p bout bret /tmp/jenkins15495091451203512891.sh: line 115: +++: command not found ++ declare -- 'bout=Applying: RISC-V: Add RVV vsetvl/vsetvlmax intrinsics and tests. error: sha1 information is lacking or useless (gcc/config.gcc). error: could not build fake ancestor hint: Use '\''git am --show-current-patch=diff'\'' to see the failed patch Patch failed at 0001 RISC-V: Add RVV vsetvl/vsetvlmax intrinsics and tests. When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort".' ++ declare -- bret=128 ++ ++ 'berr=++++ git_am https://patchwork.plctlab.org/project/gcc-patch/patch/20221017083642.184867-1-juzhe.zhong@rivai.ai/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/gcc-patch/patch/20221017083642.184867-1-juzhe.zhong@rivai.ai/mbox/ ++++ curl https://patchwork.plctlab.org/project/gcc-patch/patch/20221017083642.184867-1-juzhe.zhong@rivai.ai/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 56090 100 56090 0 0 1304k 0 --:--:-- --:--:-- --:--:-- 1335k +++ bout='\''Applying: RISC-V: Add RVV vsetvl/vsetvlmax intrinsics and tests. error: sha1 information is lacking or useless (gcc/config.gcc). error: could not build fake ancestor hint: Use '\''\'\'''\''git am --show-current-patch=diff'\''\'\'''\'' to see the failed patch Patch failed at 0001 RISC-V: Add RVV vsetvl/vsetvlmax intrinsics and tests. When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort".'\'' +++ bret=128' /tmp/jenkins15495091451203512891.sh: line 140: ++: command not found ++ ++ declare -p berr /tmp/jenkins15495091451203512891.sh: line 141: ++: command not found ++ declare -- 'berr=++++ git_am https://patchwork.plctlab.org/project/gcc-patch/patch/20221017083642.184867-1-juzhe.zhong@rivai.ai/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/gcc-patch/patch/20221017083642.184867-1-juzhe.zhong@rivai.ai/mbox/ ++++ curl https://patchwork.plctlab.org/project/gcc-patch/patch/20221017083642.184867-1-juzhe.zhong@rivai.ai/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 56090 100 56090 0 0 1304k 0 --:--:-- --:--:-- --:--:-- 1335k +++ bout='\''Applying: RISC-V: Add RVV vsetvl/vsetvlmax intrinsics and tests. error: sha1 information is lacking or useless (gcc/config.gcc). error: could not build fake ancestor hint: Use '\''\'\'''\''git am --show-current-patch=diff'\''\'\'''\'' to see the failed patch Patch failed at 0001 RISC-V: Add RVV vsetvl/vsetvlmax intrinsics and tests. When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort".'\'' +++ bret=128' ++ git rev-parse HEAD + commitid_after=b61796663ba1fe8fb83203829398f3f89ec212b7 + '[' 128 = 0 ']' + [[ ++++ git_am https://patchwork.plctlab.org/project/gcc-patch/patch/20221017083642.184867-1-juzhe.zhong@rivai.ai/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/gcc-patch/patch/20221017083642.184867-1-juzhe.zhong@rivai.ai/mbox/ ++++ curl https://patchwork.plctlab.org/project/gcc-patch/patch/20221017083642.184867-1-juzhe.zhong@rivai.ai/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 56090 100 56090 0 0 1304k 0 --:--:-- --:--:-- --:--:-- 1335k +++ bout='Applying: RISC-V: Add RVV vsetvl/vsetvlmax intrinsics and tests. error: sha1 information is lacking or useless (gcc/config.gcc). error: could not build fake ancestor hint: Use '\''git am --show-current-patch=diff'\'' to see the failed patch Patch failed at 0001 RISC-V: Add RVV vsetvl/vsetvlmax intrinsics and tests. When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort".' +++ bret=128 =~ sha1 information is lacking or useless ]] + submit_check warning Unresolved https://patchwork.plctlab.org/jenkins/job/gcc-patch/1345/consoleText 'Git am fail log' + check_state=warning + patch_state=Unresolved + repo_url=https://patchwork.plctlab.org/jenkins/job/gcc-patch/1345/consoleText + DESCRIPTION='Git am fail log' + curl -X POST -H 'Authorization: Token [*******]' -F state=warning -F target_url=https://patchwork.plctlab.org/jenkins/job/gcc-patch/1345/consoleText -F context=gcc-patch-check -F 'description=Git am fail log' https://patchwork.plctlab.org/api/patches/3280/checks/ % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 964 100 424 100 540 12114 15428 --:--:-- --:--:-- --:--:-- 27542 {"id":1046,"url":"https://patchwork.plctlab.org/api/patches/3280/checks/1046/","user":{"id":1,"url":"https://patchwork.plctlab.org/api/users/1/","username":"snail","first_name":"","last_name":"","email":"wangliu@iscas.ac.cn"},"date":"2022-10-17T12:17:27.489132","state":"warning","target_url":"https://patchwork.plctlab.org/jenkins/job/gcc-patch/1345/consoleText","context":"gcc-patch-check","description":"Git am fail log"}+ curl -X PATCH -H 'Authorization: Token [*******]' -F state=Unresolved https://patchwork.plctlab.org/api/1.2/patches/3280/ % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0{"id":3280,"url":"https://patchwork.plctlab.org/api/1.2/patches/3280/","web_url":"https://patchwork.plctlab.org/project/gcc-patch/patch/20221017083642.184867-1-juzhe.zhong@rivai.ai/","project":{"id":1,"url":"https://patchwork.plctlab.org/api/1.2/projects/1/","name":"gcc-patch","link_name":"gcc-patch","list_id":"gcc-patches.gcc.gnu.org","list_email":"gcc-patches@gcc.gnu.org","web_url":"https://gcc.gnu.org/mailman/listinfo/gcc-patches","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20221017083642.184867-1-juzhe.zhong@rivai.ai>","list_archive_url":null,"date":"2022-10-17T08:36:42","name":"RISC-V: Add RVV vsetvl/vsetvlmax intrinsics and tests.","commit_ref":null,"pull_url":null,"state":"unresolved","archived":false,"hash":"216c793b960a36231fe26b066e20d672ae828eb9","submitter":{"id":36,"url":"https://patchwork.plctlab.org/api/1.2/people/36/","name":"juzhe.zhong@rivai.ai","email":"juzhe.zhong@rivai.ai"},"delegate":null,"mbox":"https://patchwork.plctlab.org/project/gcc-patch/patch/20221017083642.184867-1-juzhe.zhong@rivai.ai/mbox/","series":[{"id":2195,"url":"https://patchwork.plctlab.org/api/1.2/series/2195/","web_url":"https://patchwork.plctlab.org/project/gcc-patch/list/?series=2195","date":"2022-10-17T08:36:42","name":"RISC-V: Add RVV vsetvl/vsetvlmax intrinsics and tests.","version":1,"mbox":"https://patchwork.plctlab.org/series/2195/mbox/"}],"comments":"https://patchwork.plctlab.org/api/patches/3280/comments/","check":"warning","checks":"https://patchwork.plctlab.org/api/patches/3280/checks/","tags":{},"headers":{"Return-Path":"","Delivered-To":["ouuuleilei@gmail.com","gcc-patches@gcc.gnu.org"],"Received":["by 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2620:52:3:1:0:246e:9693:128c as permitted sender)\n smtp.mailfrom=\"gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org\"","sourceware.org;\n dmarc=none (p=none dis=none) header.from=rivai.ai","sourceware.org; spf=pass smtp.mailfrom=rivai.ai"],"X-Original-To":"gcc-patches@gcc.gnu.org","DMARC-Filter":"OpenDMARC Filter v1.4.1 sourceware.org 463C83858D3C","X-QQ-mid":"bizesmtp87t1665995805t4ofj4s0","X-QQ-SSF":"01400000000000D0K000000A0000000","X-QQ-FEAT":"9E3Ddn8eo0IWxK03d06cPm53CGBqXh3aW83dAnW+UqFhyBV/VPAWDGjTtiuPT\n ppRnuSUyf3+3sHIflCNxtAzbc8KwfcA2ad8wqR7tmqLdvoxs73+OgGz6imHEB9rxKW0AhQP\n MXW31cHL42D08Wqk0Kvtqi7YLUMWIvtdXAGcB6SvUmDzfiPJUNS9io0Phwlgkd7sTYvG/pf\n i7V6z9IBjDQbHRa0MqqtaNcz312mPa58AoAgR803a4krgd13DhU68MdQtk9wZgVPUrEKr2d\n E6MvQTG1ThWL8ZGKyrkQePNyB3A3sydOwV3pyOC30MTZWeCilsPfm1Xouyz+T4wSEjjdwjs\n yQrHdJg1FiF3YlB5K/dJcXRnngHMEc9k08QuqKAVEnk3zvMMlMKLHHxPN9bX9LZi4OoZLUH","X-QQ-GoodBg":"2","From":"juzhe.zhong@rivai.ai","To":"gcc-patches@gcc.gnu.org","Subject":"[PATCH] RISC-V: Add RVV vsetvl/vsetvlmax intrinsics and tests.","Date":"Mon, 17 Oct 2022 16:36:42 +0800","Message-Id":"<20221017083642.184867-1-juzhe.zhong@rivai.ai>","X-Mailer":"git-send-email 2.36.1","MIME-Version":"1.0","Content-Transfer-Encoding":"8bit","X-QQ-SENDSIZE":"520","Feedback-ID":"bizesmtp:rivai.ai:qybglogicsvr:qybglogicsvr7","X-Spam-Status":"No, score=-11.0 required=5.0 tests=BAYES_00, GIT_PATCH_0,\n KAM_ASCII_DIVIDERS, KAM_DMARC_STATUS, KAM_SHORT, RCVD_IN_DNSWL_NONE,\n SCC_10_SHORT_WORD_LINES, SCC_20_SHORT_WORD_LINES, SCC_5_SHORT_WORD_LINES,\n SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6","X-Spam-Checker-Version":"SpamAssassin 3.4.6 (2021-04-09) on\n server2.sourceware.org","X-BeenThere":"gcc-patches@gcc.gnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"Gcc-patches mailing list ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Cc":"kito.cheng@gmail.com, Ju-Zhe Zhong ","Errors-To":"gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org","Sender":"\"Gcc-patches\" ","X-getmail-retrieved-from-mailbox":"=?utf-8?q?INBOX?=","X-GMAIL-THRID":"=?utf-8?q?1746923271067673256?=","X-GMAIL-MSGID":"=?utf-8?q?1746923271067673256?="},"content":"From: Ju-Zhe Zhong \n\ngcc/ChangeLog:\n\n\t* config.gcc: Add riscv-vector-builtins-bases.o and riscv-vector-builtins-shapes.o\n\t* config/riscv/riscv-vector-builtins.cc (DEF_RVV_I_OPS): New macro.\n\t(DEF_RVV_FUNCTION): Ditto.\n\t(handle_pragma_vector): Add intrinsic framework.\n\t* config/riscv/riscv.cc (riscv_print_operand): Add operand print for vsetvl/vsetvlmax.\n\t* config/riscv/riscv.md: include vector.md.\n\t* config/riscv/t-riscv: Add riscv-vector-builtins-bases.o and riscv-vector-builtins-shapes.o\n\t* config/riscv/riscv-vector-builtins-bases.cc: New file.\n\t* config/riscv/riscv-vector-builtins-bases.h: New file.\n\t* config/riscv/riscv-vector-builtins-functions.def: New file.\n\t* config/riscv/riscv-vector-builtins-shapes.cc: New file.\n\t* config/riscv/riscv-vector-builtins-shapes.h: New file.\n\t* config/riscv/riscv-vector-builtins-types.def: New file.\n\t* config/riscv/vector.md: New file.\n\ngcc/testsuite/ChangeLog:\n\n\t* gcc.target/riscv/rvv/base/vsetvl-1.c: New test.\n\n---\n gcc/config.gcc | 2 +-\n .../riscv/riscv-vector-builtins-bases.cc | 104 +++\n .../riscv/riscv-vector-builtins-bases.h | 33 +\n .../riscv/riscv-vector-builtins-functions.def | 43 +\n .../riscv/riscv-vector-builtins-shapes.cc | 104 +++\n .../riscv/riscv-vector-builtins-shapes.h | 33 +\n .../riscv/riscv-vector-builtins-types.def | 50 ++\n gcc/config/riscv/riscv-vector-builtins.cc | 56 ++\n gcc/config/riscv/riscv.cc | 26 +\n gcc/config/riscv/riscv.md | 1 +\n gcc/config/riscv/t-riscv | 28 +-\n gcc/config/riscv/vector.md | 72 ++\n .../gcc.target/riscv/rvv/base/vsetvl-1.c | 750 ++++++++++++++++++\n 13 files changed, 1300 insertions(+), 2 deletions(-)\n create mode 100644 gcc/config/riscv/riscv-vector-builtins-bases.cc\n create mode 100644 gcc/config/riscv/riscv-vector-builtins-bases.h\n create mode 100644 gcc/config/riscv/riscv-vector-builtins-functions.def\n create mode 100644 gcc/config/riscv/riscv-vector-builtins-shapes.cc\n create mode 100644 gcc/config/riscv/riscv-vector-builtins-shapes.h\n create mode 100644 gcc/config/riscv/riscv-vector-builtins-types.def\n create mode 100644 gcc/config/riscv/vector.md\n create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsetvl-1.c","diff":"diff --git a/gcc/config.gcc b/gcc/config.gcc\nindex 486e8790544..3826ae42803 100644\n--- a/gcc/config.gcc\n+++ b/gcc/config.gcc\n@@ -516,7 +516,7 @@ pru-*-*)\n riscv*)\n \tcpu_type=riscv\n \textra_objs=\"riscv-builtins.o riscv-c.o riscv-sr.o riscv-shorten-memrefs.o riscv-selftests.o\"\n-\textra_objs=\"${extra_objs} riscv-vector-builtins.o\"\n+\textra_objs=\"${extra_objs} riscv-vector-builtins.o riscv-vector-builtins-shapes.o riscv-vector-builtins-bases.o\"\n \td_target_objs=\"riscv-d.o\"\n \textra_headers=\"riscv_vector.h\"\n \ttarget_gtfiles=\"$target_gtfiles \\$(srcdir)/config/riscv/riscv-vector-builtins.cc\"\ndiff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc b/gcc/config/riscv/riscv-vector-builtins-bases.cc\nnew file mode 100644\nindex 00000000000..8582c0cae4c\n--- /dev/null\n+++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc\n@@ -0,0 +1,104 @@\n+/* function_base implementation for RISC-V 'V' Extension for GNU compiler.\n+ Copyright (C) 2022-2022 Free Software Foundation, Inc.\n+ Contributed by Ju-Zhe Zhong (juzhe.zhong@rivai.ai), RiVAI Technologies Ltd.\n+\n+ This file is part of GCC.\n+\n+ GCC is free software; you can redistribute it and/or modify it\n+ under the terms of the GNU General Public License as published by\n+ the Free Software Foundation; either version 3, or (at your option)\n+ any later version.\n+\n+ GCC is distributed in the hope that it will be useful, but\n+ WITHOUT ANY WARRANTY; without even the implied warranty of\n+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU\n+ General Public License for more details.\n+\n+ You should have received a copy of the GNU General Public License\n+ along with GCC; see the file COPYING3. If not see\n+ . */\n+\n+#include \"config.h\"\n+#include \"system.h\"\n+#include \"coretypes.h\"\n+#include \"tm.h\"\n+#include \"tree.h\"\n+#include \"rtl.h\"\n+#include \"tm_p.h\"\n+#include \"memmodel.h\"\n+#include \"insn-codes.h\"\n+#include \"optabs.h\"\n+#include \"recog.h\"\n+#include \"expr.h\"\n+#include \"basic-block.h\"\n+#include \"function.h\"\n+#include \"fold-const.h\"\n+#include \"gimple.h\"\n+#include \"gimple-iterator.h\"\n+#include \"gimplify.h\"\n+#include \"explow.h\"\n+#include \"emit-rtl.h\"\n+#include \"tree-vector-builder.h\"\n+#include \"rtx-vector-builder.h\"\n+#include \"riscv-vector-builtins.h\"\n+#include \"riscv-vector-builtins-shapes.h\"\n+#include \"riscv-vector-builtins-bases.h\"\n+\n+using namespace riscv_vector;\n+\n+namespace riscv_vector {\n+\n+/* Implements vsetvl && vsetvlmax. */\n+template\n+class vsetvl : public function_base\n+{\n+public:\n+ unsigned int call_properties (const function_instance &) const\n+ {\n+ return CP_READ_CSR | CP_WRITE_CSR;\n+ }\n+\n+ rtx expand (function_expander &e) const override\n+ {\n+ if (VLMAX_P)\n+ e.add_input_operand (Pmode, gen_rtx_REG (Pmode, 0));\n+ else\n+ e.add_input_operand (0);\n+\n+ tree type = builtin_types[e.type.index].vector;\n+ machine_mode mode = TYPE_MODE (type);\n+ machine_mode inner_mode = GET_MODE_INNER (mode);\n+ /* SEW. */\n+ e.add_input_operand (Pmode,\n+\t\t\t gen_int_mode (GET_MODE_BITSIZE (inner_mode), Pmode));\n+\n+ /* LMUL. Define the bitmap rule as follows:\n+ | 4 | 3 2 1 0 |\n+ | fractional_p | factor |\n+ */\n+ bool fractional_p = known_lt (GET_MODE_SIZE (mode), BYTES_PER_RISCV_VECTOR);\n+ unsigned int factor\n+ = fractional_p ? exact_div (BYTES_PER_RISCV_VECTOR, GET_MODE_SIZE (mode))\n+\t\t\t .to_constant ()\n+\t\t : exact_div (GET_MODE_SIZE (mode), BYTES_PER_RISCV_VECTOR)\n+\t\t\t .to_constant ();\n+ e.add_input_operand (Pmode,\n+\t\t\t gen_int_mode ((fractional_p << 4) | factor, Pmode));\n+\n+ /* TA. */\n+ e.add_input_operand (Pmode, gen_int_mode (1, Pmode));\n+\n+ /* MU. */\n+ e.add_input_operand (Pmode, gen_int_mode (0, Pmode));\n+ return e.generate_insn (code_for_vsetvl (Pmode));\n+ }\n+};\n+\n+static CONSTEXPR const vsetvl vsetvl_obj;\n+static CONSTEXPR const vsetvl vsetvlmax_obj;\n+namespace bases {\n+const function_base *const vsetvl = &vsetvl_obj;\n+const function_base *const vsetvlmax = &vsetvlmax_obj;\n+}\n+\n+} // end namespace riscv_vector\ndiff --git a/gcc/config/riscv/riscv-vector-builtins-bases.h b/gcc/config/riscv/riscv-vector-builtins-bases.h\nnew file mode 100644\nindex 00000000000..a0ae18eef03\n--- /dev/null\n+++ b/gcc/config/riscv/riscv-vector-builtins-bases.h\n@@ -0,0 +1,33 @@\n+/* function_base declaration for RISC-V 'V' Extension for GNU compiler.\n+ Copyright (C) 2022-2022 Free Software Foundation, Inc.\n+ Contributed by Ju-Zhe Zhong (juzhe.zhong@rivai.ai), RiVAI Technologies Ltd.\n+\n+ This file is part of GCC.\n+\n+ GCC is free software; you can redistribute it and/or modify it\n+ under the terms of the GNU General Public License as published by\n+ the Free Software Foundation; either version 3, or (at your option)\n+ any later version.\n+\n+ GCC is distributed in the hope that it will be useful, but\n+ WITHOUT ANY WARRANTY; without even the implied warranty of\n+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU\n+ General Public License for more details.\n+\n+ You should have received a copy of the GNU General Public License\n+ along with GCC; see the file COPYING3. If not see\n+ . */\n+\n+#ifndef GCC_RISCV_VECTOR_BUILTINS_BASES_H\n+#define GCC_RISCV_VECTOR_BUILTINS_BASES_H\n+\n+namespace riscv_vector {\n+\n+namespace bases {\n+extern const function_base *const vsetvl;\n+extern const function_base *const vsetvlmax;\n+}\n+\n+} // end namespace riscv_vector\n+\n+#endif\ndiff --git a/gcc/config/riscv/riscv-vector-builtins-functions.def b/gcc/config/riscv/riscv-vector-builtins-functions.def\nnew file mode 100644\nindex 00000000000..dc41537865e\n--- /dev/null\n+++ b/gcc/config/riscv/riscv-vector-builtins-functions.def\n@@ -0,0 +1,43 @@\n+/* Intrinsic define macros for RISC-V 'V' Extension for GNU compiler.\n+ Copyright (C) 2022-2022 Free Software Foundation, Inc.\n+ Contributed by Juzhe Zhong (juzhe.zhong@rivai.ai), RiVAI Technologies Ltd.\n+\n+This file is part of GCC.\n+\n+GCC is free software; you can redistribute it and/or modify\n+it under the terms of the GNU General Public License as published by\n+the Free Software Foundation; either version 3, or (at your option)\n+any later version.\n+\n+GCC is distributed in the hope that it will be useful,\n+but WITHOUT ANY WARRANTY; without even the implied warranty of\n+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n+GNU General Public License for more details.\n+\n+You should have received a copy of the GNU General Public License\n+along with GCC; see the file COPYING3. If not see\n+. */\n+\n+/* Use \"DEF_RVV_FUNCTION\" macro to define RVV intrinsic functions.\n+\n+ - NAME not only describes the base_name of the functions\n+ but also point to the name of the function_base class.\n+\n+ - SHAPE point to the function_shape class.\n+\n+ - PREDS describes the predication types that are supported in the\n+ functions.\n+\n+ - OPS_INFO describes all information of return type and each\n+ argument type.\n+\n+*/\n+#ifndef DEF_RVV_FUNCTION\n+#define DEF_RVV_FUNCTION(NAME, SHAPE, PREDS, OPS_INFO)\n+#endif\n+\n+/* 6. Configuration-Setting Instructions. */\n+DEF_RVV_FUNCTION (vsetvl, vsetvl, none_preds, i_none_size_size_ops)\n+DEF_RVV_FUNCTION (vsetvlmax, vsetvlmax, none_preds, i_none_size_void_ops)\n+\n+#undef DEF_RVV_FUNCTION\ndiff --git a/gcc/config/riscv/riscv-vector-builtins-shapes.cc b/gcc/config/riscv/riscv-vector-builtins-shapes.cc\nnew file mode 100644\nindex 00000000000..24fc1c02341\n--- /dev/null\n+++ b/gcc/config/riscv/riscv-vector-builtins-shapes.cc\n@@ -0,0 +1,104 @@\n+/* function_shape implementation for RISC-V 'V' Extension for GNU compiler.\n+ Copyright (C) 2022-2022 Free Software Foundation, Inc.\n+ Contributed by Ju-Zhe Zhong (juzhe.zhong@rivai.ai), RiVAI Technologies Ltd.\n+\n+ This file is part of GCC.\n+\n+ GCC is free software; you can redistribute it and/or modify it\n+ under the terms of the GNU General Public License as published by\n+ the Free Software Foundation; either version 3, or (at your option)\n+ any later version.\n+\n+ GCC is distributed in the hope that it will be useful, but\n+ WITHOUT ANY WARRANTY; without even the implied warranty of\n+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU\n+ General Public License for more details.\n+\n+ You should have received a copy of the GNU General Public License\n+ along with GCC; see the file COPYING3. If not see\n+ . */\n+\n+#include \"config.h\"\n+#include \"system.h\"\n+#include \"coretypes.h\"\n+#include \"tm.h\"\n+#include \"tree.h\"\n+#include \"rtl.h\"\n+#include \"tm_p.h\"\n+#include \"memmodel.h\"\n+#include \"insn-codes.h\"\n+#include \"optabs.h\"\n+#include \"riscv-vector-builtins.h\"\n+#include \"riscv-vector-builtins-shapes.h\"\n+\n+namespace riscv_vector {\n+\n+/* Add one function instance for GROUP, using operand suffix at index OI,\n+ mode suffix at index PAIR && bi and predication suffix at index pred_idx. */\n+static void\n+build_one (function_builder &b, const function_group_info &group,\n+\t unsigned int pred_idx, unsigned int vec_type_idx)\n+{\n+ /* Byte forms of non-tuple vlxusegei take 21 arguments. */\n+ auto_vec argument_types;\n+ function_instance function_instance (group.base_name, *group.base,\n+\t\t\t\t *group.shape,\n+\t\t\t\t group.ops_infos.types[vec_type_idx],\n+\t\t\t\t group.preds[pred_idx], &group.ops_infos);\n+ tree return_type = group.ops_infos.ret.get_tree_type (\n+ group.ops_infos.types[vec_type_idx].index);\n+ b.allocate_argument_types (function_instance, argument_types);\n+ b.add_unique_function (function_instance, (*group.shape), return_type,\n+\t\t\t argument_types);\n+}\n+\n+/* Add a function instance for every operand && predicate && args\n+ combination in GROUP. Take the function base name from GROUP && operand\n+ suffix from operand_suffixes && mode suffix from type_suffixes && predication\n+ suffix from predication_suffixes. Use apply_predication to add in\n+ the predicate. */\n+static void\n+build_all (function_builder &b, const function_group_info &group)\n+{\n+ for (unsigned int pred_idx = 0; group.preds[pred_idx] != NUM_PRED_TYPES;\n+ ++pred_idx)\n+ for (unsigned int vec_type_idx = 0;\n+\t group.ops_infos.types[vec_type_idx].index != NUM_VECTOR_TYPES;\n+\t ++vec_type_idx)\n+ build_one (b, group, pred_idx, vec_type_idx);\n+}\n+\n+/* Declare the function shape NAME, pointing it to an instance\n+ of class _def. */\n+#define SHAPE(DEF, VAR) \\\n+ static CONSTEXPR const DEF##_def VAR##_obj; \\\n+ namespace shapes { const function_shape *const VAR = &VAR##_obj; }\n+\n+/* Base class for for build. */\n+struct build_base : public function_shape\n+{\n+ void build (function_builder &b,\n+\t const function_group_info &group) const override\n+ {\n+ build_all (b, group);\n+ }\n+};\n+\n+/* vsetvl_def class. */\n+struct vsetvl_def : public build_base\n+{\n+ char *get_name (function_builder &b, const function_instance &instance,\n+\t\t bool overloaded_p) const override\n+ {\n+ /* vsetvl* instruction doesn't have C++ overloaded functions. */\n+ if (overloaded_p)\n+ return nullptr;\n+ b.append_name (instance.base_name);\n+ b.append_name (type_suffixes[instance.type.index].vsetvl);\n+ return b.finish_name ();\n+ }\n+};\n+SHAPE(vsetvl, vsetvl)\n+SHAPE(vsetvl, vsetvlmax)\n+\n+} // end namespace riscv_vector\ndiff --git a/gcc/config/riscv/riscv-vector-builtins-shapes.h b/gcc/config/riscv/riscv-vector-builtins-shapes.h\nnew file mode 100644\nindex 00000000000..f2d876fb133\n--- /dev/null\n+++ b/gcc/config/riscv/riscv-vector-builtins-shapes.h\n@@ -0,0 +1,33 @@\n+/* function_shape declaration for RISC-V 'V' Extension for GNU compiler.\n+ Copyright (C) 2022-2022 Free Software Foundation, Inc.\n+ Contributed by Ju-Zhe Zhong (juzhe.zhong@rivai.ai), RiVAI Technologies Ltd.\n+\n+ This file is part of GCC.\n+\n+ GCC is free software; you can redistribute it and/or modify it\n+ under the terms of the GNU General Public License as published by\n+ the Free Software Foundation; either version 3, or (at your option)\n+ any later version.\n+\n+ GCC is distributed in the hope that it will be useful, but\n+ WITHOUT ANY WARRANTY; without even the implied warranty of\n+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU\n+ General Public License for more details.\n+\n+ You should have received a copy of the GNU General Public License\n+ along with GCC; see the file COPYING3. If not see\n+ . */\n+\n+#ifndef GCC_RISCV_VECTOR_BUILTINS_SHAPES_H\n+#define GCC_RISCV_VECTOR_BUILTINS_SHAPES_H\n+\n+namespace riscv_vector {\n+\n+namespace shapes {\n+extern const function_shape *const vsetvl;\n+extern const function_shape *const vsetvlmax;\n+}\n+\n+} // end namespace riscv_vector\n+\n+#endif\ndiff --git a/gcc/config/riscv/riscv-vector-builtins-types.def b/gcc/config/riscv/riscv-vector-builtins-types.def\nnew file mode 100644\nindex 00000000000..f282a5e7654\n--- /dev/null\n+++ b/gcc/config/riscv/riscv-vector-builtins-types.def\n@@ -0,0 +1,50 @@\n+/* Intrinsic type iterators for RISC-V 'V' Extension for GNU compiler.\n+ Copyright (C) 2022-2022 Free Software Foundation, Inc.\n+ Contributed by Juzhe Zhong (juzhe.zhong@rivai.ai), RiVAI Technologies Ltd.\n+\n+This file is part of GCC.\n+\n+GCC is free software; you can redistribute it and/or modify\n+it under the terms of the GNU General Public License as published by\n+the Free Software Foundation; either version 3, or (at your option)\n+any later version.\n+\n+GCC is distributed in the hope that it will be useful,\n+but WITHOUT ANY WARRANTY; without even the implied warranty of\n+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n+GNU General Public License for more details.\n+\n+You should have received a copy of the GNU General Public License\n+along with GCC; see the file COPYING3. If not see\n+. */\n+\n+/* Use \"DEF_ALL_SIGNED_INTEGER\" macro include all signed integer which will be\n+ iterated and registered as intrinsic functions. */\n+#ifndef DEF_RVV_I_OPS\n+#define DEF_RVV_I_OPS(TYPE, REQUIRE)\n+#endif\n+\n+DEF_RVV_I_OPS (vint8mf8_t, RVV_REQUIRE_ZVE64)\n+DEF_RVV_I_OPS (vint8mf4_t, 0)\n+DEF_RVV_I_OPS (vint8mf2_t, 0)\n+DEF_RVV_I_OPS (vint8m1_t, 0)\n+DEF_RVV_I_OPS (vint8m2_t, 0)\n+DEF_RVV_I_OPS (vint8m4_t, 0)\n+DEF_RVV_I_OPS (vint8m8_t, 0)\n+DEF_RVV_I_OPS (vint16mf4_t, RVV_REQUIRE_ZVE64)\n+DEF_RVV_I_OPS (vint16mf2_t, 0)\n+DEF_RVV_I_OPS (vint16m1_t, 0)\n+DEF_RVV_I_OPS (vint16m2_t, 0)\n+DEF_RVV_I_OPS (vint16m4_t, 0)\n+DEF_RVV_I_OPS (vint16m8_t, 0)\n+DEF_RVV_I_OPS (vint32mf2_t, RVV_REQUIRE_ZVE64)\n+DEF_RVV_I_OPS (vint32m1_t, 0)\n+DEF_RVV_I_OPS (vint32m2_t, 0)\n+DEF_RVV_I_OPS (vint32m4_t, 0)\n+DEF_RVV_I_OPS (vint32m8_t, 0)\n+DEF_RVV_I_OPS (vint64m1_t, RVV_REQUIRE_ZVE64)\n+DEF_RVV_I_OPS (vint64m2_t, RVV_REQUIRE_ZVE64)\n+DEF_RVV_I_OPS (vint64m4_t, RVV_REQUIRE_ZVE64)\n+DEF_RVV_I_OPS (vint64m8_t, RVV_REQUIRE_ZVE64)\n+\n+#undef DEF_RVV_I_OPS\ndiff --git a/gcc/config/riscv/riscv-vector-builtins.cc b/gcc/config/riscv/riscv-vector-builtins.cc\nindex 5c20788b3ab..dc410788c99 100644\n--- a/gcc/config/riscv/riscv-vector-builtins.cc\n+++ b/gcc/config/riscv/riscv-vector-builtins.cc\n@@ -45,6 +45,8 @@\n #include \"targhooks.h\"\n #include \"regs.h\"\n #include \"riscv-vector-builtins.h\"\n+#include \"riscv-vector-builtins-shapes.h\"\n+#include \"riscv-vector-builtins-bases.h\"\n \n using namespace riscv_vector;\n \n@@ -115,6 +117,49 @@ const char *const predication_suffixes[NUM_PRED_TYPES] = {\n #include \"riscv-vector-builtins.def\"\n };\n \n+/* A list of all signed integer will be registered for intrinsic functions. */\n+static const rvv_type_info i_ops[] = {\n+#define DEF_RVV_I_OPS(TYPE, REQUIRE) {VECTOR_TYPE_##TYPE, REQUIRE},\n+#include \"riscv-vector-builtins-types.def\"\n+ {NUM_VECTOR_TYPES, 0}};\n+\n+static CONSTEXPR const rvv_arg_type_info rvv_arg_type_info_end\n+ = rvv_arg_type_info (NUM_BASE_TYPES);\n+\n+/* A list of args for size_t func (void) function. */\n+static CONSTEXPR const rvv_arg_type_info void_args[]\n+ = {rvv_arg_type_info (RVV_BASE_void), rvv_arg_type_info_end};\n+\n+/* A list of args for size_t func (size_t) function. */\n+static CONSTEXPR const rvv_arg_type_info size_args[]\n+ = {rvv_arg_type_info (RVV_BASE_size), rvv_arg_type_info_end};\n+\n+/* A list of none preds that will be registered for intrinsic functions. */\n+static CONSTEXPR const predication_type_index none_preds[]\n+ = {PRED_TYPE_none, NUM_PRED_TYPES};\n+\n+/* A static operand information for size_t func (void) function registration. */\n+static CONSTEXPR const rvv_op_info i_none_size_void_ops\n+ = {i_ops,\t\t\t\t/* Types */\n+ OP_TYPE_none,\t\t\t/* Suffix */\n+ rvv_arg_type_info (RVV_BASE_size), /* Return type */\n+ void_args /* Args */};\n+\n+/* A static operand information for size_t func (size_t) function registration.\n+ */\n+static CONSTEXPR const rvv_op_info i_none_size_size_ops\n+ = {i_ops,\t\t\t\t/* Types */\n+ OP_TYPE_none,\t\t\t/* Suffix */\n+ rvv_arg_type_info (RVV_BASE_size), /* Return type */\n+ size_args /* Args */};\n+\n+/* A list of all RVV intrinsic functions. */\n+static function_group_info function_groups[] = {\n+#define DEF_RVV_FUNCTION(NAME, SHAPE, PREDS, OPS_INFO) \\\n+ {#NAME, &bases::NAME, &shapes::SHAPE, PREDS, OPS_INFO},\n+#include \"riscv-vector-builtins-functions.def\"\n+};\n+\n /* The RVV types, with their built-in\n \"__rvv..._t\" name. Allow an index of NUM_VECTOR_TYPES, which always\n yields a null tree. */\n@@ -787,11 +832,22 @@ verify_type_context (location_t loc, type_context_kind context, const_tree type,\n void\n handle_pragma_vector ()\n {\n+ if (function_table)\n+ {\n+ error (\"duplicate definition of %qs\", \"riscv_vector.h\");\n+ return;\n+ }\n rvv_switcher rvv;\n \n /* Define the vector and tuple types. */\n for (unsigned int type_i = 0; type_i < NUM_VECTOR_TYPES; ++type_i)\n register_vector_type ((enum vector_type_index) type_i);\n+\n+ /* Define the functions. */\n+ function_table = new hash_table (1023);\n+ function_builder builder;\n+ for (unsigned int i = 0; i < ARRAY_SIZE (function_groups); ++i)\n+ builder.register_function_group (function_groups[i]);\n }\n \n /* Return the function decl with RVV function subcode CODE, or error_mark_node\ndiff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc\nindex ad57b995e7b..90a39047dd7 100644\n--- a/gcc/config/riscv/riscv.cc\n+++ b/gcc/config/riscv/riscv.cc\n@@ -4135,6 +4135,32 @@ riscv_print_operand (FILE *file, rtx op, int letter)\n \n switch (letter)\n {\n+ case 'm': {\n+\tif (code == CONST_INT)\n+\t {\n+\t /* LMUL. Define the bitmap rule as follows:\n+\t | 4 | 3 2 1 0 |\n+\t | fractional_p | factor |\n+\t */\n+\t bool fractional_p = (UINTVAL (op) >> 4) & 0x1;\n+\t unsigned int factor = UINTVAL (op) & 0xf;\n+\t asm_fprintf (file, \"%s%d\", fractional_p ? \"mf\" : \"m\", factor);\n+\t }\n+\telse\n+\t output_operand_lossage (\"invalid vector constant\");\n+\tbreak;\n+ }\n+ case 'p': {\n+\tif (code == CONST_INT)\n+\t {\n+\t /* Tail && Mask policy. */\n+\t bool agnostic_p = UINTVAL (op) & 0x1;\n+\t asm_fprintf (file, \"%s\", agnostic_p ? \"a\" : \"u\");\n+\t }\n+\telse\n+\t output_operand_lossage (\"invalid vector constant\");\n+\tbreak;\n+ }\n case 'h':\n if (code == HIGH)\n \top = XEXP (op, 0);\ndiff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md\nindex 2d1cda2b98f..b3654915fde 100644\n--- a/gcc/config/riscv/riscv.md\n+++ b/gcc/config/riscv/riscv.md\n@@ -2999,3 +2999,4 @@\n (include \"pic.md\")\n (include \"generic.md\")\n (include \"sifive-7.md\")\n+(include \"vector.md\")\ndiff --git a/gcc/config/riscv/t-riscv b/gcc/config/riscv/t-riscv\nindex 15b9e7c01b1..8f67676cad7 100644\n--- a/gcc/config/riscv/t-riscv\n+++ b/gcc/config/riscv/t-riscv\n@@ -11,10 +11,36 @@ riscv-vector-builtins.o: $(srcdir)/config/riscv/riscv-vector-builtins.cc \\\n $(FUNCTION_H) fold-const.h gimplify.h explow.h stor-layout.h $(REGS_H) \\\n alias.h langhooks.h attribs.h stringpool.h \\\n $(srcdir)/config/riscv/riscv-vector-builtins.h \\\n- $(srcdir)/config/riscv/riscv-vector-builtins.def\n+ $(srcdir)/config/riscv/riscv-vector-builtins-shapes.h \\\n+ $(srcdir)/config/riscv/riscv-vector-builtins-bases.h \\\n+ $(srcdir)/config/riscv/riscv-vector-builtins.def \\\n+ $(srcdir)/config/riscv/riscv-vector-builtins-types.def \\\n+ $(srcdir)/config/riscv/riscv-vector-builtins-functions.def\n \t$(COMPILER) -c $(ALL_COMPILERFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) \\\n \t\t$(srcdir)/config/riscv/riscv-vector-builtins.cc\n \n+riscv-vector-builtins-shapes.o: \\\n+ $(srcdir)/config/riscv/riscv-vector-builtins-shapes.cc \\\n+ $(CONFIG_H) $(SYSTEM_H) coretypes.h $(TM_H) $(TREE_H) $(RTL_H) \\\n+ $(TM_P_H) memmodel.h insn-codes.h $(OPTABS_H) \\\n+ $(srcdir)/config/riscv/riscv-vector-builtins.h \\\n+ $(srcdir)/config/riscv/riscv-vector-builtins-shapes.h\n+\t$(COMPILER) -c $(ALL_COMPILERFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) \\\n+\t\t$(srcdir)/config/riscv/riscv-vector-builtins-shapes.cc\n+\n+riscv-vector-builtins-bases.o: \\\n+ $(srcdir)/config/riscv/riscv-vector-builtins-bases.cc \\\n+ $(CONFIG_H) $(SYSTEM_H) coretypes.h $(TM_H) $(TREE_H) $(RTL_H) \\\n+ $(TM_P_H) memmodel.h insn-codes.h $(OPTABS_H) $(RECOG_H) \\\n+ $(EXPR_H) $(BASIC_BLOCK_H) $(FUNCTION_H) fold-const.h $(GIMPLE_H) \\\n+ gimple-iterator.h gimplify.h explow.h $(EMIT_RTL_H) tree-vector-builder.h \\\n+ rtx-vector-builder.h \\\n+ $(srcdir)/config/riscv/riscv-vector-builtins.h \\\n+ $(srcdir)/config/riscv/riscv-vector-builtins-shapes.h \\\n+ $(srcdir)/config/riscv/riscv-vector-builtins-bases.h\n+\t$(COMPILER) -c $(ALL_COMPILERFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) \\\n+\t\t$(srcdir)/config/riscv/riscv-vector-builtins-bases.cc\n+\n riscv-sr.o: $(srcdir)/config/riscv/riscv-sr.cc $(CONFIG_H) \\\n $(SYSTEM_H) $(TM_H)\n \t$(COMPILER) -c $(ALL_COMPILERFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) \\\ndiff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md\nnew file mode 100644\nindex 00000000000..82ce902c0fb\n--- /dev/null\n+++ b/gcc/config/riscv/vector.md\n@@ -0,0 +1,72 @@\n+;; Machine description for RISC-V 'V' Extension for GNU compiler.\n+;; Copyright (C) 2022-2022 Free Software Foundation, Inc.\n+;; Contributed by Juzhe Zhong (juzhe.zhong@rivai.ai), RiVAI Technologies Ltd.\n+\n+;; This file is part of GCC.\n+\n+;; GCC is free software; you can redistribute it and/or modify\n+;; it under the terms of the GNU General Public License as published by\n+;; the Free Software Foundation; either version 3, or (at your option)\n+;; any later version.\n+\n+;; GCC is distributed in the hope that it will be useful,\n+;; but WITHOUT ANY WARRANTY; without even the implied warranty of\n+;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n+;; GNU General Public License for more details.\n+\n+;; You should have received a copy of the GNU General Public License\n+;; along with GCC; see the file COPYING3. If not see\n+;; .\n+\n+;; This file describes the RISC-V 'V' Extension, Version 1.0.\n+;;\n+;; This file include :\n+;;\n+;; - Intrinsics (https://github.com/riscv/rvv-intrinsic-doc)\n+;; - Auto-vectorization (TBD)\n+;; - Combine optimization (TBD)\n+\n+(define_c_enum \"unspec\" [\n+ UNSPEC_VSETVL\n+])\n+\n+;; -----------------------------------------------------------------\n+;; ---- 6. Configuration-Setting Instructions\n+;; -----------------------------------------------------------------\n+;; Includes:\n+;; - 6.1 vsetvli/vsetivl/vsetvl instructions\n+;; -----------------------------------------------------------------\n+\n+;; we dont't define vsetvli as unspec_volatile which has side effects.\n+;; This instruction can be scheduled by the instruction scheduler.\n+;; This means these instructions will be deleted when\n+;; there is no instructions using vl or vtype in the following.\n+;; rd | rs1 | AVL value | Effect on vl\n+;; - | !x0 | x[rs1] | Normal stripmining\n+;; !x0 | x0 | ~0 | Set vl to VLMAX\n+;; operands[0]: VL.\n+;; operands[1]: AVL.\n+;; operands[2]: SEW\n+;; operands[3]: LMUL\n+;; operands[4]: Tail policy 0 or 1 (undisturbed/agnostic)\n+;; operands[5]: Mask policy 0 or 1 (undisturbed/agnostic)\n+(define_insn \"@vsetvl\"\n+ [(set (match_operand:P 0 \"register_operand\" \"=r,r\")\n+\t(unspec:P [(match_operand:P 1 \"csr_operand\" \"r,K\")\n+\t\t (match_operand 2 \"const_int_operand\" \"i,i\")\n+\t\t (match_operand 3 \"const_int_operand\" \"i,i\")\n+\t\t (match_operand 4 \"const_int_operand\" \"i,i\")\n+\t\t (match_operand 5 \"const_int_operand\" \"i,i\")] UNSPEC_VSETVL))\n+ (set (reg:SI VL_REGNUM)\n+\t(unspec:SI [(match_dup 1)\n+\t\t (match_dup 2)\n+\t\t (match_dup 3)] UNSPEC_VSETVL))\n+ (set (reg:SI VTYPE_REGNUM)\n+\t(unspec:SI [(match_dup 2)\n+\t\t (match_dup 3)\n+\t\t (match_dup 4)\n+\t\t (match_dup 5)] UNSPEC_VSETVL))]\n+ \"TARGET_VECTOR\"\n+ \"vset%i1vli\\t%0,%1,e%2,%m3,t%p4,m%p5\"\n+ [(set_attr \"type\" \"vsetvl\")\n+ (set_attr \"mode\" \"\")])\ndiff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsetvl-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsetvl-1.c\nnew file mode 100644\nindex 00000000000..661f2c9170e\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsetvl-1.c\n@@ -0,0 +1,750 @@\n+/* { dg-do compile } */\n+/* { dg-options \"-march=rv32gcv -mabi=ilp32d -O3\" } */\n+\n+#include \n+#include \n+\n+size_t test_vsetvl_e8mf8_imm0()\n+{\n+ size_t vl = vsetvl_e8mf8(0);\n+ return vl;\n+}\n+\n+size_t test_vsetvl_e8mf8_imm31()\n+{\n+ size_t vl = vsetvl_e8mf8(31);\n+ return vl;\n+}\n+\n+size_t test_vsetvl_e8mf8_imm32()\n+{\n+ size_t vl = vsetvl_e8mf8(32);\n+ return vl;\n+}\n+\n+size_t test_vsetvl_e8mf8(size_t avl)\n+{\n+ size_t vl = vsetvl_e8mf8(avl);\n+ return vl;\n+}\n+\n+size_t test_vsetvlmax_e8mf8()\n+{\n+ size_t vl = vsetvlmax_e8mf8();\n+ return vl;\n+}\n+\n+size_t test_vsetvl_e8mf4_imm0()\n+{\n+ size_t vl = vsetvl_e8mf4(0);\n+ return vl;\n+}\n+\n+size_t test_vsetvl_e8mf4_imm31()\n+{\n+ size_t vl = vsetvl_e8mf4(31);\n+ return vl;\n+}\n+\n+size_t test_vsetvl_e8mf4_imm32()\n+{\n+ size_t vl = vsetvl_e8mf4(32);\n+ return vl;\n+}\n+\n+size_t test_vsetvl_e8mf4(size_t avl)\n+{\n+ size_t vl = vsetvl_e8mf4(avl);\n+ return vl;\n+}\n+\n+size_t test_vsetvlmax_e8mf4()\n+{\n+ size_t vl = vsetvlmax_e8mf4();\n+ return vl;\n+}\n+\n+size_t test_vsetvl_e8mf2_imm0()\n+{\n+ size_t vl = vsetvl_e8mf2(0);\n+ return vl;\n+}\n+\n+size_t test_vsetvl_e8mf2_imm31()\n+{\n+ size_t vl = vsetvl_e8mf2(31);\n+ return vl;\n+}\n+\n+size_t test_vsetvl_e8mf2_imm32()\n+{\n+ size_t vl = vsetvl_e8mf2(32);\n+ return vl;\n+}\n+\n+size_t test_vsetvl_e8mf2(size_t avl)\n+{\n+ size_t vl = vsetvl_e8mf2(avl);\n+ return vl;\n+}\n+\n+size_t test_vsetvlmax_e8mf2()\n+{\n+ size_t vl = vsetvlmax_e8mf2();\n+ return vl;\n+}\n+\n+size_t test_vsetvl_e8m1_imm0()\n+{\n+ size_t vl = vsetvl_e8m1(0);\n+ return vl;\n+}\n+\n+size_t test_vsetvl_e8m1_imm31()\n+{\n+ size_t vl = vsetvl_e8m1(31);\n+ return vl;\n+}\n+\n+size_t test_vsetvl_e8m1_imm32()\n+{\n+ size_t vl = vsetvl_e8m1(32);\n+ return vl;\n+}\n+\n+size_t test_vsetvl_e8m1(size_t avl)\n+{\n+ size_t vl = vsetvl_e8m1(avl);\n+ return vl;\n+}\n+\n+size_t test_vsetvlmax_e8m1()\n+{\n+ size_t vl = vsetvlmax_e8m1();\n+ return vl;\n+}\n+\n+size_t test_vsetvl_e8m2_imm0()\n+{\n+ size_t vl = vsetvl_e8m2(0);\n+ return vl;\n+}\n+\n+size_t test_vsetvl_e8m2_imm31()\n+{\n+ size_t vl = vsetvl_e8m2(31);\n+ return vl;\n+}\n+\n+size_t test_vsetvl_e8m2_imm32()\n+{\n+ size_t vl = vsetvl_e8m2(32);\n+ return vl;\n+}\n+\n+size_t test_vsetvl_e8m2(size_t avl)\n+{\n+ size_t vl = vsetvl_e8m2(avl);\n+ return vl;\n+}\n+\n+size_t test_vsetvlmax_e8m2()\n+{\n+ size_t vl = vsetvlmax_e8m2();\n+ return vl;\n+}\n+\n+size_t test_vsetvl_e8m4_imm0()\n+{\n+ size_t vl = vsetvl_e8m4(0);\n+ return vl;\n+}\n+\n+size_t test_vsetvl_e8m4_imm31()\n+{\n+ size_t vl = vsetvl_e8m4(31);\n+ return vl;\n+}\n+\n+size_t test_vsetvl_e8m4_imm32()\n+{\n+ size_t vl = vsetvl_e8m4(32);\n+ return vl;\n+}\n+size_t test_vsetvl_e8m4(size_t avl)\n+{\n+ size_t vl = vsetvl_e8m4(avl);\n+ return vl;\n+}\n+\n+size_t test_vsetvlmax_e8m4()\n+{\n+ size_t vl = vsetvlmax_e8m4();\n+ return vl;\n+}\n+\n+size_t test_vsetvl_e8m8_imm0()\n+{\n+ size_t vl = vsetvl_e8m8(0);\n+ return vl;\n+}\n+\n+size_t test_vsetvl_e8m8_imm31()\n+{\n+ size_t vl = vsetvl_e8m8(31);\n+ return vl;\n+}\n+\n+size_t test_vsetvl_e8m8_imm32()\n+{\n+ size_t vl = vsetvl_e8m8(32);\n+ return vl;\n+}\n+\n+size_t test_vsetvl_e8m8(size_t avl)\n+{\n+ size_t vl = vsetvl_e8m8(avl);\n+ return vl;\n+}\n+\n+size_t test_vsetvlmax_e8m8()\n+{\n+ size_t vl = vsetvlmax_e8m8();\n+ return vl;\n+}\n+\n+size_t test_vsetvl_e16mf4_imm0()\n+{\n+ size_t vl = vsetvl_e16mf4(0);\n+ return vl;\n+}\n+\n+size_t test_vsetvl_e16mf4_imm31()\n+{\n+ size_t vl = vsetvl_e16mf4(31);\n+ return vl;\n+}\n+\n+size_t test_vsetvl_e16mf4_imm32()\n+{\n+ size_t vl = vsetvl_e16mf4(32);\n+ return vl;\n+}\n+\n+size_t test_vsetvl_e16mf4(size_t avl)\n+{\n+ size_t vl = vsetvl_e16mf4(avl);\n+ return vl;\n+}\n+\n+size_t test_vsetvlmax_e16mf4()\n+{\n+ size_t vl = vsetvlmax_e16mf4();\n+ return vl;\n+}\n+\n+size_t test_vsetvl_e16mf2_imm0()\n+{\n+ size_t vl = vsetvl_e16mf2(0);\n+ return vl;\n+}\n+\n+size_t test_vsetvl_e16mf2_imm31()\n+{\n+ size_t vl = vsetvl_e16mf2(31);\n+ return vl;\n+}\n+\n+size_t test_vsetvl_e16mf2_imm32()\n+{\n+ size_t vl = vsetvl_e16mf2(32);\n+ return vl;\n+}\n+\n+size_t test_vsetvl_e16mf2(size_t avl)\n+{\n+ size_t vl = vsetvl_e16mf2(avl);\n+ return vl;\n+}\n+\n+size_t test_vsetvlmax_e16mf2()\n+{\n+ size_t vl = vsetvlmax_e16mf2();\n+ return vl;\n+}\n+\n+size_t test_vsetvl_e16m1_imm0()\n+{\n+ size_t vl = vsetvl_e16m1(0);\n+ return vl;\n+}\n+\n+size_t test_vsetvl_e16m1_imm31()\n+{\n+ size_t vl = vsetvl_e16m1(31);\n+ return vl;\n+}\n+\n+size_t test_vsetvl_e16m1_imm32()\n+{\n+ size_t vl = vsetvl_e16m1(32);\n+ return vl;\n+}\n+\n+size_t test_vsetvl_e16m1(size_t avl)\n+{\n+ size_t vl = vsetvl_e16m1(avl);\n+ return vl;\n+}\n+\n+size_t test_vsetvlmax_e16m1()\n+{\n+ size_t vl = vsetvlmax_e16m1();\n+ return vl;\n+}\n+\n+size_t test_vsetvl_e16m2_imm0()\n+{\n+ size_t vl = vsetvl_e16m2(0);\n+ return vl;\n+}\n+\n+size_t test_vsetvl_e16m2_imm31()\n+{\n+ size_t vl = vsetvl_e16m2(31);\n+ return vl;\n+}\n+\n+size_t test_vsetvl_e16m2_imm32()\n+{\n+ size_t vl = vsetvl_e16m2(32);\n+ return vl;\n+}\n+\n+size_t test_vsetvl_e16m2(size_t avl)\n+{\n+ size_t vl = vsetvl_e16m2(avl);\n+ return vl;\n+}\n+\n+size_t test_vsetvlmax_e16m2()\n+{\n+ size_t vl = vsetvlmax_e16m2();\n+ return vl;\n+}\n+\n+size_t test_vsetvl_e16m4_imm0()\n+{\n+ size_t vl = vsetvl_e16m4(0);\n+ return vl;\n+}\n+\n+size_t test_vsetvl_e16m4_imm31()\n+{\n+ size_t vl = vsetvl_e16m4(31);\n+ return vl;\n+}\n+\n+size_t test_vsetvl_e16m4_imm32()\n+{\n+ size_t vl = vsetvl_e16m4(32);\n+ return vl;\n+}\n+\n+size_t test_vsetvl_e16m4(size_t avl)\n+{\n+ size_t vl = vsetvl_e16m4(avl);\n+ return vl;\n+}\n+\n+size_t test_vsetvlmax_e16m4()\n+{\n+ size_t vl = vsetvlmax_e16m4();\n+ return vl;\n+}\n+\n+size_t test_vsetvl_e16m8_imm0()\n+{\n+ size_t vl = vsetvl_e16m8(0);\n+ return vl;\n+}\n+\n+size_t test_vsetvl_e16m8_imm31()\n+{\n+ size_t vl = vsetvl_e16m8(31);\n+ return vl;\n+}\n+\n+size_t test_vsetvl_e16m8_imm32()\n+{\n+ size_t vl = vsetvl_e16m8(32);\n+ return vl;\n+}\n+\n+size_t test_vsetvl_e16m8(size_t avl)\n+{\n+ size_t vl = vsetvl_e16m8(avl);\n+ return vl;\n+}\n+\n+size_t test_vsetvlmax_e16m8()\n+{\n+ size_t vl = vsetvlmax_e16m8();\n+ return vl;\n+}\n+\n+size_t test_vsetvl_e32mf2_imm0()\n+{\n+ size_t vl = vsetvl_e32mf2(0);\n+ return vl;\n+}\n+\n+size_t test_vsetvl_e32mf2_imm31()\n+{\n+ size_t vl = vsetvl_e32mf2(31);\n+ return vl;\n+}\n+\n+size_t test_vsetvl_e32mf2_imm32()\n+{\n+ size_t vl = vsetvl_e32mf2(32);\n+ return vl;\n+}\n+\n+size_t test_vsetvl_e32mf2(size_t avl)\n+{\n+ size_t vl = vsetvl_e32mf2(avl);\n+ return vl;\n+}\n+\n+size_t test_vsetvlmax_e32mf2()\n+{\n+ size_t vl = vsetvlmax_e32mf2();\n+ return vl;\n+}\n+\n+size_t test_vsetvl_e32m1_imm0()\n+{\n+ size_t vl = vsetvl_e32m1(0);\n+ return vl;\n+}\n+\n+size_t test_vsetvl_e32m1_imm31()\n+{\n+ size_t vl = vsetvl_e32m1(31);\n+ return vl;\n+}\n+\n+size_t test_vsetvl_e32m1_imm32()\n+{\n+ size_t vl = vsetvl_e32m1(32);\n+ return vl;\n+}\n+\n+size_t test_vsetvl_e32m1(size_t avl)\n+{\n+ size_t vl = vsetvl_e32m1(avl);\n+ return vl;\n+}\n+\n+size_t test_vsetvlmax_e32m1()\n+{\n+ size_t vl = vsetvlmax_e32m1();\n+ return vl;\n+}\n+\n+size_t test_vsetvl_e32m2_imm0()\n+{\n+ size_t vl = vsetvl_e32m2(0);\n+ return vl;\n+}\n+\n+size_t test_vsetvl_e32m2_imm31()\n+{\n+ size_t vl = vsetvl_e32m2(31);\n+ return vl;\n+}\n+\n+size_t test_vsetvl_e32m2_imm32()\n+{\n+ size_t vl = vsetvl_e32m2(32);\n+ return vl;\n+}\n+\n+size_t test_vsetvl_e32m2(size_t avl)\n+{\n+ size_t vl = vsetvl_e32m2(avl);\n+ return vl;\n+}\n+\n+size_t test_vsetvlmax_e32m2()\n+{\n+ size_t vl = vsetvlmax_e32m2();\n+ return vl;\n+}\n+\n+size_t test_vsetvl_e32m4_imm0()\n+{\n+ size_t vl = vsetvl_e32m4(0);\n+ return vl;\n+}\n+\n+size_t test_vsetvl_e32m4_imm31()\n+{\n+ size_t vl = vsetvl_e32m4(31);\n+ return vl;\n+}\n+\n+size_t test_vsetvl_e32m4_imm32()\n+{\n+ size_t vl = vsetvl_e32m4(32);\n+ return vl;\n+}\n+\n+size_t test_vsetvl_e32m4(size_t avl)\n+{\n+ size_t vl = vsetvl_e32m4(avl);\n+ return vl;\n+}\n+\n+size_t test_vsetvlmax_e32m4()\n+{\n+ size_t vl = vsetvlmax_e32m4();\n+ return vl;\n+}\n+\n+size_t test_vsetvl_e32m8_imm0()\n+{\n+ size_t vl = vsetvl_e32m8(0);\n+ return vl;\n+}\n+\n+size_t test_vsetvl_e32m8_imm31()\n+{\n+ size_t vl = vsetvl_e32m8(31);\n+ return vl;\n+}\n+\n+size_t test_vsetvl_e32m8_imm32()\n+{\n+ size_t vl = vsetvl_e32m8(32);\n+ return vl;\n+}\n+size_t test_vsetvl_e32m8(size_t avl)\n+{\n+ size_t vl = vsetvl_e32m8(avl);\n+ return vl;\n+}\n+\n+size_t test_vsetvlmax_e32m8()\n+{\n+ size_t vl = vsetvlmax_e32m8();\n+ return vl;\n+}\n+\n+size_t test_vsetvl_e64m1_imm0()\n+{\n+ size_t vl = vsetvl_e64m1(0);\n+ return vl;\n+}\n+\n+size_t test_vsetvl_e64m1_imm31()\n+{\n+ size_t vl = vsetvl_e64m1(31);\n+ return vl;\n+}\n+\n+size_t test_vsetvl_e64m1_imm32()\n+{\n+ size_t vl = vsetvl_e64m1(32);\n+ return vl;\n+}\n+\n+size_t test_vsetvl_e64m1(size_t avl)\n+{\n+ size_t vl = vsetvl_e64m1(avl);\n+ return vl;\n+}\n+\n+size_t test_vsetvlmax_e64m1()\n+{\n+ size_t vl = vsetvlmax_e64m1();\n+ return vl;\n+}\n+\n+size_t test_vsetvl_e64m2_imm0()\n+{\n+ size_t vl = vsetvl_e64m2(0);\n+ return vl;\n+}\n+\n+size_t test_vsetvl_e64m2_imm31()\n+{\n+ size_t vl = vsetvl_e64m2(31);\n+ return vl;\n+}\n+\n+size_t test_vsetvl_e64m2_imm32()\n+{\n+ size_t vl = vsetvl_e64m2(32);\n+ return vl;\n+}\n+size_t test_vsetvl_e64m2(size_t avl)\n+{\n+ size_t vl = vsetvl_e64m2(avl);\n+ return vl;\n+}\n+\n+size_t test_vsetvlmax_e64m2()\n+{\n+ size_t vl = vsetvlmax_e64m2();\n+ return vl;\n+}\n+\n+size_t test_vsetvl_e64m4_imm0()\n+{\n+ size_t vl = vsetvl_e64m4(0);\n+ return vl;\n+}\n+\n+size_t test_vsetvl_e64m4_imm31()\n+{\n+ size_t vl = vsetvl_e64m4(31);\n+ return vl;\n+}\n+\n+size_t test_vsetvl_e64m4_imm32()\n+{\n+ size_t vl = vsetvl_e64m4(32);\n+ return vl;\n+}\n+\n+size_t test_vsetvl_e64m4(size_t avl)\n+{\n+ size_t vl = vsetvl_e64m4(avl);\n+ return vl;\n+}\n+\n+size_t test_vsetvlmax_e64m4()\n+{\n+ size_t vl = vsetvlmax_e64m4();\n+ return vl;\n+}\n+\n+size_t test_vsetvl_e64m8_imm0()\n+{\n+ size_t vl = vsetvl_e64m8(0);\n+ return vl;\n+}\n+\n+size_t test_vsetvl_e64m8_imm31()\n+{\n+ size_t vl = vsetvl_e64m8(31);\n+ return vl;\n+}\n+\n+size_t test_vsetvl_e64m8_imm32()\n+{\n+ size_t vl = vsetvl_e64m8(32);\n+ return vl;\n+}\n+size_t test_vsetvl_e64m8(size_t avl)\n+{\n+ size_t vl = vsetvl_e64m8(avl);\n+ return vl;\n+}\n+\n+size_t test_vsetvlmax_e64m8()\n+{\n+ size_t vl = vsetvlmax_e64m8();\n+ return vl;\n+}\n+\n+/* { dg-final { scan-assembler-times {vsetivli\\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\\s*0,\\s*e8,\\s*mf8,\\s*ta,\\s*mu} 1 } } */\n+/* { dg-final { scan-assembler-times {vsetivli\\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\\s*31,\\s*e8,\\s*mf8,\\s*ta,\\s*mu} 1 } } */\n+/* { dg-final { scan-assembler-times {vsetvli\\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\\s*e8,\\s*mf8,\\s*ta,\\s*mu} 2 } } */\n+/* { dg-final { scan-assembler-times {vsetvli\\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\\s*zero,\\s*e8,\\s*mf8,\\s*ta,\\s*mu} 1 } } */\n+/* { dg-final { scan-assembler-times {vsetivli\\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\\s*0,\\s*e8,\\s*mf4,\\s*ta,\\s*mu} 1 } } */\n+/* { dg-final { scan-assembler-times {vsetivli\\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\\s*31,\\s*e8,\\s*mf4,\\s*ta,\\s*mu} 1 } } */\n+/* { dg-final { scan-assembler-times {vsetvli\\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\\s*e8,\\s*mf4,\\s*ta,\\s*mu} 2 } } */\n+/* { dg-final { scan-assembler-times {vsetvli\\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\\s*zero,\\s*e8,\\s*mf4,\\s*ta,\\s*mu} 1 } } */\n+/* { dg-final { scan-assembler-times {vsetivli\\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\\s*0,\\s*e8,\\s*mf2,\\s*ta,\\s*mu} 1 } } */\n+/* { dg-final { scan-assembler-times {vsetivli\\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\\s*31,\\s*e8,\\s*mf2,\\s*ta,\\s*mu} 1 } } */\n+/* { dg-final { scan-assembler-times {vsetvli\\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\\s*e8,\\s*mf2,\\s*ta,\\s*mu} 2 } } */\n+/* { dg-final { scan-assembler-times {vsetvli\\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\\s*zero,\\s*e8,\\s*mf2,\\s*ta,\\s*mu} 1 } } */\n+/* { dg-final { scan-assembler-times {vsetivli\\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\\s*0,\\s*e8,\\s*m1,\\s*ta,\\s*mu} 1 } } */\n+/* { dg-final { scan-assembler-times {vsetivli\\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\\s*31,\\s*e8,\\s*m1,\\s*ta,\\s*mu} 1 } } */\n+/* { dg-final { scan-assembler-times {vsetvli\\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\\s*e8,\\s*m1,\\s*ta,\\s*mu} 2 } } */\n+/* { dg-final { scan-assembler-times {vsetvli\\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\\s*zero,\\s*e8,\\s*m1,\\s*ta,\\s*mu} 1 } } */\n+/* { dg-final { scan-assembler-times {vsetivli\\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\\s*0,\\s*e8,\\s*m2,\\s*ta,\\s*mu} 1 } } */\n+/* { dg-final { scan-assembler-times {vsetivli\\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\\s*31,\\s*e8,\\s*m2,\\s*ta,\\s*mu} 1 } } */\n+/* { dg-final { scan-assembler-times {vsetvli\\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\\s*e8,\\s*m2,\\s*ta,\\s*mu} 2 } } */\n+/* { dg-final { scan-assembler-times {vsetvli\\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\\s*zero,\\s*e8,\\s*m2,\\s*ta,\\s*mu} 1 } } */\n+/* { dg-final { scan-assembler-times {vsetivli\\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\\s*0,\\s*e8,\\s*m4,\\s*ta,\\s*mu} 1 } } */\n+/* { dg-final { scan-assembler-times {vsetivli\\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\\s*31,\\s*e8,\\s*m4,\\s*ta,\\s*mu} 1 } } */\n+/* { dg-final { scan-assembler-times {vsetvli\\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\\s*e8,\\s*m4,\\s*ta,\\s*mu} 2 } } */\n+/* { dg-final { scan-assembler-times {vsetvli\\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\\s*zero,\\s*e8,\\s*m4,\\s*ta,\\s*mu} 1 } } */\n+/* { dg-final { scan-assembler-times {vsetivli\\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\\s*0,\\s*e8,\\s*m8,\\s*ta,\\s*mu} 1 } } */\n+/* { dg-final { scan-assembler-times {vsetivli\\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\\s*31,\\s*e8,\\s*m8,\\s*ta,\\s*mu} 1 } } */\n+/* { dg-final { scan-assembler-times {vsetvli\\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\\s*e8,\\s*m8,\\s*ta,\\s*mu} 2 } } */\n+/* { dg-final { scan-assembler-times {vsetvli\\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\\s*zero,\\s*e8,\\s*m8,\\s*ta,\\s*mu} 1 } } */\n+/* { dg-final { scan-assembler-times {vsetivli\\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\\s*0,\\s*e16,\\s*mf4,\\s*ta,\\s*mu} 1 } } */\n+/* { dg-final { scan-assembler-times {vsetivli\\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\\s*31,\\s*e16,\\s*mf4,\\s*ta,\\s*mu} 1 } } */\n+/* { dg-final { scan-assembler-times {vsetvli\\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\\s*e16,\\s*mf4,\\s*ta,\\s*mu} 2 } } */\n+/* { dg-final { scan-assembler-times {vsetvli\\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\\s*zero,\\s*e16,\\s*mf4,\\s*ta,\\s*mu} 1 } } */\n+/* { dg-final { scan-assembler-times {vsetivli\\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\\s*0,\\s*e16,\\s*mf2,\\s*ta,\\s*mu} 1 } } */\n+/* { dg-final { scan-assembler-times {vsetivli\\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\\s*31,\\s*e16,\\s*mf2,\\s*ta,\\s*mu} 1 } } */\n+/* { dg-final { scan-assembler-times {vsetvli\\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\\s*e16,\\s*mf2,\\s*ta,\\s*mu} 2 } } */\n+/* { dg-final { scan-assembler-times {vsetvli\\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\\s*zero,\\s*e16,\\s*mf2,\\s*ta,\\s*mu} 1 } } */\n+/* { dg-final { scan-assembler-times {vsetivli\\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\\s*0,\\s*e16,\\s*m1,\\s*ta,\\s*mu} 1 } } */\n+/* { dg-final { scan-assembler-times {vsetivli\\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\\s*31,\\s*e16,\\s*m1,\\s*ta,\\s*mu} 1 } } */\n+/* { dg-final { scan-assembler-times {vsetvli\\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\\s*e16,\\s*m1,\\s*ta,\\s*mu} 2 } } */\n+/* { dg-final { scan-assembler-times {vsetvli\\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\\s*zero,\\s*e16,\\s*m1,\\s*ta,\\s*mu} 1 } } */\n+/* { dg-final { scan-assembler-times {vsetivli\\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\\s*0,\\s*e16,\\s*m2,\\s*ta,\\s*mu} 1 } } */\n+/* { dg-final { scan-assembler-times {vsetivli\\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\\s*31,\\s*e16,\\s*m2,\\s*ta,\\s*mu} 1 } } */\n+/* { dg-final { scan-assembler-times {vsetvli\\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\\s*e16,\\s*m2,\\s*ta,\\s*mu} 2 } } */\n+/* { dg-final { scan-assembler-times {vsetvli\\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\\s*zero,\\s*e16,\\s*m2,\\s*ta,\\s*mu} 1 } } */\n+/* { dg-final { scan-assembler-times {vsetivli\\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\\s*0,\\s*e16,\\s*m4,\\s*ta,\\s*mu} 1 } } */\n+/* { dg-final { scan-assembler-times {vsetivli\\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\\s*31,\\s*e16,\\s*m4,\\s*ta,\\s*mu} 1 } } */\n+/* { dg-final { scan-assembler-times {vsetvli\\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\\s*e16,\\s*m4,\\s*ta,\\s*mu} 2 } } */\n+/* { dg-final { scan-assembler-times {vsetvli\\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\\s*zero,\\s*e16,\\s*m4,\\s*ta,\\s*mu} 1 } } */\n+/* { dg-final { scan-assembler-times {vsetivli\\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\\s*0,\\s*e16,\\s*m8,\\s*ta,\\s*mu} 1 } } */\n+/* { dg-final { scan-assembler-times {vsetivli\\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\\s*31,\\s*e16,\\s*m8,\\s*ta,\\s*mu} 1 } } */\n+/* { dg-final { scan-assembler-times {vsetvli\\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\\s*e16,\\s*m8,\\s*ta,\\s*mu} 2 } } */\n+/* { dg-final { scan-assembler-times {vsetvli\\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\\s*zero,\\s*e16,\\s*m8,\\s*ta,\\s*mu} 1 } } */\n+/* { dg-final { scan-assembler-times {vsetivli\\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\\s*0,\\s*e32,\\s*mf2,\\s*ta,\\s*mu} 1 } } */\n+/* { dg-final { scan-assembler-times {vsetivli\\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\\s*31,\\s*e32,\\s*mf2,\\s*ta,\\s*mu} 1 } } */\n+/* { dg-final { scan-assembler-times {vsetvli\\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\\s*e32,\\s*mf2,\\s*ta,\\s*mu} 2 } } */\n+/* { dg-final { scan-assembler-times {vsetvli\\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\\s*zero,\\s*e32,\\s*mf2,\\s*ta,\\s*mu} 1 } } */\n+/* { dg-final { scan-assembler-times {vsetivli\\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\\s*0,\\s*e32,\\s*m1,\\s*ta,\\s*mu} 1 } } */\n+/* { dg-final { scan-assembler-times {vsetivli\\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\\s*31,\\s*e32,\\s*m1,\\s*ta,\\s*mu} 1 } } */\n+/* { dg-final { scan-assembler-times {vsetvli\\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\\s*e32,\\s*m1,\\s*ta,\\s*mu} 2 } } */\n+/* { dg-final { scan-assembler-times {vsetvli\\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\\s*zero,\\s*e32,\\s*m1,\\s*ta,\\s*mu} 1 } } */\n+/* { dg-final { scan-assembler-times {vsetivli\\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\\s*0,\\s*e32,\\s*m2,\\s*ta,\\s*mu} 1 } } */\n+/* { dg-final { scan-assembler-times {vsetivli\\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\\s*31,\\s*e32,\\s*m2,\\s*ta,\\s*mu} 1 } } */\n+/* { dg-final { scan-assembler-times {vsetvli\\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\\s*e32,\\s*m2,\\s*ta,\\s*mu} 2 } } */\n+/* { dg-final { scan-assembler-times {vsetvli\\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\\s*zero,\\s*e32,\\s*m2,\\s*ta,\\s*mu} 1 } } */\n+/* { dg-final { scan-assembler-times {vsetivli\\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\\s*0,\\s*e32,\\s*m4,\\s*ta,\\s*mu} 1 } } */\n+/* { dg-final { scan-assembler-times {vsetivli\\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\\s*31,\\s*e32,\\s*m4,\\s*ta,\\s*mu} 1 } } */\n+/* { dg-final { scan-assembler-times {vsetvli\\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\\s*e32,\\s*m4,\\s*ta,\\s*mu} 2 } } */\n+/* { dg-final { scan-assembler-times {vsetvli\\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\\s*zero,\\s*e32,\\s*m4,\\s*ta,\\s*mu} 1 } } */\n+/* { dg-final { scan-assembler-times {vsetivli\\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\\s*0,\\s*e32,\\s*m8,\\s*ta,\\s*mu} 1 } } */\n+/* { dg-final { scan-assembler-times {vsetivli\\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\\s*31,\\s*e32,\\s*m8,\\s*ta,\\s*mu} 1 } } */\n+/* { dg-final { scan-assembler-times {vsetvli\\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s 100 60136 100 59986 100 150 1126k 2884 --:--:-- --:--:-- --:--:-- 1129k 11|a[0-7]),\\s*e32,\\s*m8,\\s*ta,\\s*mu} 2 } } */\n+/* { dg-final { scan-assembler-times {vsetvli\\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\\s*zero,\\s*e32,\\s*m8,\\s*ta,\\s*mu} 1 } } */\n+/* { dg-final { scan-assembler-times {vsetivli\\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\\s*0,\\s*e64,\\s*m1,\\s*ta,\\s*mu} 1 } } */\n+/* { dg-final { scan-assembler-times {vsetivli\\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\\s*31,\\s*e64,\\s*m1,\\s*ta,\\s*mu} 1 } } */\n+/* { dg-final { scan-assembler-times {vsetvli\\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\\s*e64,\\s*m1,\\s*ta,\\s*mu} 2 } } */\n+/* { dg-final { scan-assembler-times {vsetvli\\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\\s*zero,\\s*e64,\\s*m1,\\s*ta,\\s*mu} 1 } } */\n+/* { dg-final { scan-assembler-times {vsetivli\\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\\s*0,\\s*e64,\\s*m2,\\s*ta,\\s*mu} 1 } } */\n+/* { dg-final { scan-assembler-times {vsetivli\\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\\s*31,\\s*e64,\\s*m2,\\s*ta,\\s*mu} 1 } } */\n+/* { dg-final { scan-assembler-times {vsetvli\\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\\s*e64,\\s*m2,\\s*ta,\\s*mu} 2 } } */\n+/* { dg-final { scan-assembler-times {vsetvli\\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\\s*zero,\\s*e64,\\s*m2,\\s*ta,\\s*mu} 1 } } */\n+/* { dg-final { scan-assembler-times {vsetivli\\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\\s*0,\\s*e64,\\s*m4,\\s*ta,\\s*mu} 1 } } */\n+/* { dg-final { scan-assembler-times {vsetivli\\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\\s*31,\\s*e64,\\s*m4,\\s*ta,\\s*mu} 1 } } */\n+/* { dg-final { scan-assembler-times {vsetvli\\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\\s*e64,\\s*m4,\\s*ta,\\s*mu} 2 } } */\n+/* { dg-final { scan-assembler-times {vsetvli\\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\\s*zero,\\s*e64,\\s*m4,\\s*ta,\\s*mu} 1 } } */\n+/* { dg-final { scan-assembler-times {vsetivli\\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\\s*0,\\s*e64,\\s*m8,\\s*ta,\\s*mu} 1 } } */\n+/* { dg-final { scan-assembler-times {vsetivli\\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\\s*31,\\s*e64,\\s*m8,\\s*ta,\\s*mu} 1 } } */\n+/* { dg-final { scan-assembler-times {vsetvli\\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\\s*e64,\\s*m8,\\s*ta,\\s*mu} 2 } } */\n+/* { dg-final { scan-assembler-times {vsetvli\\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\\s*zero,\\s*e64,\\s*m8,\\s*ta,\\s*mu} 1 } } */\n","prefixes":[]}+ exit 1 Build step 'Execute shell' marked build as failure Finished: FAILURE