Started by user snail Running as SYSTEM [EnvInject] - Loading node environment variables. Building remotely on docker-jenkins-agent in workspace /home/jenkins/agent/workspace/gcc-patch [WS-CLEANUP] Deleting project workspace... [WS-CLEANUP] Deferred wipeout is used... [WS-CLEANUP] Done The recommended git tool is: NONE using credential 0adb5fc7-caa2-429d-97d2-c7fa2fa1d884 Cloning the remote Git repository Using shallow clone with depth 1 Avoid fetching tags Cloning repository git@github.com:wangliu-iscas/gcc-patch.git/ > git init /home/jenkins/agent/workspace/gcc-patch # timeout=10 Fetching upstream changes from git@github.com:wangliu-iscas/gcc-patch.git/ > git --version # timeout=10 > git --version # 'git version 2.37.2' using GIT_SSH to set credentials patchwork github wangliu-iscas git ssh key Verifying host key using known hosts file, will automatically accept unseen keys > git fetch --no-tags --force --progress --depth=1 -- git@github.com:wangliu-iscas/gcc-patch.git/ +refs/heads/*:refs/remotes/origin/* # timeout=10 > git config remote.origin.url git@github.com:wangliu-iscas/gcc-patch.git/ # timeout=10 > git config --add remote.origin.fetch +refs/heads/*:refs/remotes/origin/* # timeout=10 Avoid second fetch > git rev-parse refs/remotes/origin/master^{commit} # timeout=10 Checking out Revision a75e9bee7c23403d3cc7085a249f230de50c4c3e (refs/remotes/origin/master) > git config core.sparsecheckout # timeout=10 > git checkout -f a75e9bee7c23403d3cc7085a249f230de50c4c3e # timeout=10 Commit message: "Add cases for CFN_BUILT_IN_SIGNBIT[FL]." > git rev-list --no-walk a75e9bee7c23403d3cc7085a249f230de50c4c3e # timeout=10 [EnvInject] - Mask passwords that will be passed as build parameters. [EnvInject] - Executing scripts and injecting environment variables after the SCM step. [EnvInject] - Injecting as environment variables the properties content GITHUB_REPO=https://github.com/wangliu-iscas/ PATCHWORK_URL=https://patchwork.plctlab.org [EnvInject] - Variables injected successfully. [gcc-patch] $ /usr/bin/env bash /tmp/jenkins2803384233662927229.sh + git config pull.rebase false + git fetch origin master From github.com:wangliu-iscas/gcc-patch * branch master -> FETCH_HEAD + git checkout master Switched to a new branch 'master' branch 'master' set up to track 'origin/master'. + git pull origin master From github.com:wangliu-iscas/gcc-patch * branch master -> FETCH_HEAD Already up to date. + git fetch origin upstream-master From github.com:wangliu-iscas/gcc-patch * branch upstream-master -> FETCH_HEAD + git checkout upstream-master Switched to a new branch 'upstream-master' branch 'upstream-master' set up to track 'origin/upstream-master'. + git remote add upstream https://github.com/gcc-mirror/gcc.git + git pull upstream master From https://github.com/gcc-mirror/gcc * branch master -> FETCH_HEAD * [new branch] master -> upstream/master Already up to date. + git push -u origin upstream-master Everything up-to-date branch 'upstream-master' set up to track 'origin/upstream-master'. + git checkout master Switched to branch 'master' Your branch is up to date with 'origin/master'. + git merge upstream-master Already up to date. + git push -u origin master Everything up-to-date branch 'master' set up to track 'origin/master'. + branchname=series1905-patch2570 ++ grep 'series1905-patch2570$' ++ git branch -a + checkbranch= + checkbranchresult=null + '[' null = series1905-patch2570 ']' + git checkout -b series1905-patch2570 Switched to a new branch 'series1905-patch2570' ++ curl https://patchwork.plctlab.org/api/1.2/series/1905/ % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 1865 100 1865 0 0 62166 0 --:--:-- --:--:-- --:--:-- 62166 + series_response='{"id":1905,"url":"https://patchwork.plctlab.org/api/1.2/series/1905/","web_url":"https://patchwork.plctlab.org/project/gcc-patch/list/?series=1905","project":{"id":1,"url":"https://patchwork.plctlab.org/api/1.2/projects/1/","name":"gcc-patch","link_name":"gcc-patch","list_id":"gcc-patches.gcc.gnu.org","list_email":"gcc-patches@gcc.gnu.org","web_url":"https://gcc.gnu.org/mailman/listinfo/gcc-patches","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"name":"[1/3] Add a parameter for the builtin function of prefetch to align with LLVM","date":"2022-10-14T08:19:45","submitter":{"id":113,"url":"https://patchwork.plctlab.org/api/1.2/people/113/","name":"Haochen Jiang","email":"haochen.jiang@intel.com"},"version":1,"total":3,"received_total":2,"received_all":false,"mbox":"https://patchwork.plctlab.org/series/1905/mbox/","cover_letter":null,"patches":[{"id":2571,"url":"https://patchwork.plctlab.org/api/1.2/patches/2571/","web_url":"https://patchwork.plctlab.org/project/gcc-patch/patch/20221014081945.8318-2-haochen.jiang@intel.com/","msgid":"<20221014081945.8318-2-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T08:19:44","name":"[1/3] Add a parameter for the builtin function of prefetch to align with LLVM","mbox":"https://patchwork.plctlab.org/project/gcc-patch/patch/20221014081945.8318-2-haochen.jiang@intel.com/mbox/"},{"id":2570,"url":"https://patchwork.plctlab.org/api/1.2/patches/2570/","web_url":"https://patchwork.plctlab.org/project/gcc-patch/patch/20221014081945.8318-3-haochen.jiang@intel.com/","msgid":"<20221014081945.8318-3-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T08:19:45","name":"[2/3] Support Intel prefetchit0/t1","mbox":"https://patchwork.plctlab.org/project/gcc-patch/patch/20221014081945.8318-3-haochen.jiang@intel.com/mbox/"}]}' ++ jq '.patches[] | (.id|tostring) + "," + .mbox' ++ echo '{"id":1905,"url":"https://patchwork.plctlab.org/api/1.2/series/1905/","web_url":"https://patchwork.plctlab.org/project/gcc-patch/list/?series=1905","project":{"id":1,"url":"https://patchwork.plctlab.org/api/1.2/projects/1/","name":"gcc-patch","link_name":"gcc-patch","list_id":"gcc-patches.gcc.gnu.org","list_email":"gcc-patches@gcc.gnu.org","web_url":"https://gcc.gnu.org/mailman/listinfo/gcc-patches","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"name":"[1/3] Add a parameter for the builtin function of prefetch to align with LLVM","date":"2022-10-14T08:19:45","submitter":{"id":113,"url":"https://patchwork.plctlab.org/api/1.2/people/113/","name":"Haochen Jiang","email":"haochen.jiang@intel.com"},"version":1,"total":3,"received_total":2,"received_all":false,"mbox":"https://patchwork.plctlab.org/series/1905/mbox/","cover_letter":null,"patches":[{"id":2571,"url":"https://patchwork.plctlab.org/api/1.2/patches/2571/","web_url":"https://patchwork.plctlab.org/project/gcc-patch/patch/20221014081945.8318-2-haochen.jiang@intel.com/","msgid":"<20221014081945.8318-2-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T08:19:44","name":"[1/3] Add a parameter for the builtin function of prefetch to align with LLVM","mbox":"https://patchwork.plctlab.org/project/gcc-patch/patch/20221014081945.8318-2-haochen.jiang@intel.com/mbox/"},{"id":2570,"url":"https://patchwork.plctlab.org/api/1.2/patches/2570/","web_url":"https://patchwork.plctlab.org/project/gcc-patch/patch/20221014081945.8318-3-haochen.jiang@intel.com/","msgid":"<20221014081945.8318-3-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T08:19:45","name":"[2/3] Support Intel prefetchit0/t1","mbox":"https://patchwork.plctlab.org/project/gcc-patch/patch/20221014081945.8318-3-haochen.jiang@intel.com/mbox/"}]}' + patchid_patchurl='"2571,https://patchwork.plctlab.org/project/gcc-patch/patch/20221014081945.8318-2-haochen.jiang@intel.com/mbox/" "2570,https://patchwork.plctlab.org/project/gcc-patch/patch/20221014081945.8318-3-haochen.jiang@intel.com/mbox/"' + IFS=, + read -r series_patch_id series_patch_url + echo '"2571,https://patchwork.plctlab.org/project/gcc-patch/patch/20221014081945.8318-2-haochen.jiang@intel.com/mbox/" "2570,https://patchwork.plctlab.org/project/gcc-patch/patch/20221014081945.8318-3-haochen.jiang@intel.com/mbox/"' ++ echo '"2571' ++ sed 's/"//g' + series_patch_id=2571 ++ echo 'https://patchwork.plctlab.org/project/gcc-patch/patch/20221014081945.8318-2-haochen.jiang@intel.com/mbox/"' ++ sed 's/"//g' + series_patch_url=https://patchwork.plctlab.org/project/gcc-patch/patch/20221014081945.8318-2-haochen.jiang@intel.com/mbox/ ++ git rev-parse HEAD + commitid_before=a75e9bee7c23403d3cc7085a249f230de50c4c3e + eval '+++ declare -p bout bret declare -- bout="Applying: Add a parameter for the builtin function of prefetch to align with LLVM" declare -- bret="0" ++ berr='\''++++ git_am https://patchwork.plctlab.org/project/gcc-patch/patch/20221014081945.8318-2-haochen.jiang@intel.com/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/gcc-patch/patch/20221014081945.8318-2-haochen.jiang@intel.com/mbox/ ++++ git am -3 --empty=drop ++++ curl https://patchwork.plctlab.org/project/gcc-patch/patch/20221014081945.8318-2-haochen.jiang@intel.com/mbox/ % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 72390 100 72390 0 0 317k 0 --:--:-- --:--:-- --:--:-- 315k 100 72390 100 72390 0 0 317k 0 --:--:-- --:--:-- --:--:-- 315k +++ bout='\''\'\'''\''Applying: Add a parameter for the builtin function of prefetch to align with LLVM'\''\'\'''\'' +++ bret=0'\'' ++ declare -p berr declare -- berr="++++ git_am https://patchwork.plctlab.org/project/gcc-patch/patch/20221014081945.8318-2-haochen.jiang@intel.com/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/gcc-patch/patch/20221014081945.8318-2-haochen.jiang@intel.com/mbox/ ++++ git am -3 --empty=drop ++++ curl https://patchwork.plctlab.org/project/gcc-patch/patch/20221014081945.8318-2-haochen.jiang@intel.com/mbox/ % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 72390 100 72390 0 0 317k 0 --:--:-- --:--:-- --:--:-- 315k 100 72390 100 72390 0 0 317k 0 --:--:-- --:--:-- --:--:-- 315k +++ bout='\''Applying: Add a parameter for the builtin function of prefetch to align with LLVM'\'' +++ bret=0"' ++ +++ declare -p bout bret /tmp/jenkins2803384233662927229.sh: line 85: +++: command not found ++ declare -- 'bout=Applying: Add a parameter for the builtin function of prefetch to align with LLVM' ++ declare -- bret=0 ++ ++ 'berr=++++ git_am https://patchwork.plctlab.org/project/gcc-patch/patch/20221014081945.8318-2-haochen.jiang@intel.com/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/gcc-patch/patch/20221014081945.8318-2-haochen.jiang@intel.com/mbox/ ++++ git am -3 --empty=drop ++++ curl https://patchwork.plctlab.org/project/gcc-patch/patch/20221014081945.8318-2-haochen.jiang@intel.com/mbox/ % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 72390 100 72390 0 0 317k 0 --:--:-- --:--:-- --:--:-- 315k 100 72390 100 72390 0 0 317k 0 --:--:-- --:--:-- --:--:-- 315k +++ bout='\''Applying: Add a parameter for the builtin function of prefetch to align with LLVM'\'' +++ bret=0' /tmp/jenkins2803384233662927229.sh: line 96: ++: command not found ++ ++ declare -p berr /tmp/jenkins2803384233662927229.sh: line 97: ++: command not found ++ declare -- 'berr=++++ git_am https://patchwork.plctlab.org/project/gcc-patch/patch/20221014081945.8318-2-haochen.jiang@intel.com/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/gcc-patch/patch/20221014081945.8318-2-haochen.jiang@intel.com/mbox/ ++++ git am -3 --empty=drop ++++ curl https://patchwork.plctlab.org/project/gcc-patch/patch/20221014081945.8318-2-haochen.jiang@intel.com/mbox/ % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 72390 100 72390 0 0 317k 0 --:--:-- --:--:-- --:--:-- 315k 100 72390 100 72390 0 0 317k 0 --:--:-- --:--:-- --:--:-- 315k +++ bout='\''Applying: Add a parameter for the builtin function of prefetch to align with LLVM'\'' +++ bret=0' ++ git rev-parse HEAD + commitid_after=05af88ff4d2c95e543ebf4ef1cb8c4b171a009a1 + '[' 0 = 0 ']' + '[' 05af88ff4d2c95e543ebf4ef1cb8c4b171a009a1 = a75e9bee7c23403d3cc7085a249f230de50c4c3e ']' + '[' 2571 = 2570 ']' + IFS=, + read -r series_patch_id series_patch_url ++ sed 's/"//g' ++ echo '"2570' + series_patch_id=2570 ++ sed 's/"//g' ++ echo 'https://patchwork.plctlab.org/project/gcc-patch/patch/20221014081945.8318-3-haochen.jiang@intel.com/mbox/"' + series_patch_url=https://patchwork.plctlab.org/project/gcc-patch/patch/20221014081945.8318-3-haochen.jiang@intel.com/mbox/ ++ git rev-parse HEAD + commitid_before=05af88ff4d2c95e543ebf4ef1cb8c4b171a009a1 + eval '+++ declare -p bout bret declare -- bout="Applying: Support Intel prefetchit0/t1 error: sha1 information is lacking or useless (gcc/common/config/i386/cpuinfo.h). error: could not build fake ancestor hint: Use '\''git am --show-current-patch=diff'\'' to see the failed patch Patch failed at 0001 Support Intel prefetchit0/t1 When you have resolved this problem, run \"git am --continue\". If you prefer to skip this patch, run \"git am --skip\" instead. To restore the original branch and stop patching, run \"git am --abort\"." declare -- bret="128" ++ berr='\''++++ git_am https://patchwork.plctlab.org/project/gcc-patch/patch/20221014081945.8318-3-haochen.jiang@intel.com/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/gcc-patch/patch/20221014081945.8318-3-haochen.jiang@intel.com/mbox/ ++++ curl https://patchwork.plctlab.org/project/gcc-patch/patch/20221014081945.8318-3-haochen.jiang@intel.com/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 48837 100 48837 0 0 781k 0 --:--:-- --:--:-- --:--:-- 781k +++ bout='\''\'\'''\''Applying: Support Intel prefetchit0/t1 error: sha1 information is lacking or useless (gcc/common/config/i386/cpuinfo.h). error: could not build fake ancestor hint: Use '\''\'\'''\''\'\''\'\'''\'''\''\'\'''\''git am --show-current-patch=diff'\''\'\'''\''\'\''\'\'''\'''\''\'\'''\'' to see the failed patch Patch failed at 0001 Support Intel prefetchit0/t1 When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort".'\''\'\'''\'' +++ bret=128'\'' ++ declare -p berr declare -- berr="++++ git_am https://patchwork.plctlab.org/project/gcc-patch/patch/20221014081945.8318-3-haochen.jiang@intel.com/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/gcc-patch/patch/20221014081945.8318-3-haochen.jiang@intel.com/mbox/ ++++ curl https://patchwork.plctlab.org/project/gcc-patch/patch/20221014081945.8318-3-haochen.jiang@intel.com/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 48837 100 48837 0 0 781k 0 --:--:-- --:--:-- --:--:-- 781k +++ bout='\''Applying: Support Intel prefetchit0/t1 error: sha1 information is lacking or useless (gcc/common/config/i386/cpuinfo.h). error: could not build fake ancestor hint: Use '\''\\'\'''\''git am --show-current-patch=diff'\''\\'\'''\'' to see the failed patch Patch failed at 0001 Support Intel prefetchit0/t1 When you have resolved this problem, run \"git am --continue\". If you prefer to skip this patch, run \"git am --skip\" instead. To restore the original branch and stop patching, run \"git am --abort\".'\'' +++ bret=128"' ++ +++ declare -p bout bret /tmp/jenkins2803384233662927229.sh: line 85: +++: command not found ++ declare -- 'bout=Applying: Support Intel prefetchit0/t1 error: sha1 information is lacking or useless (gcc/common/config/i386/cpuinfo.h). error: could not build fake ancestor hint: Use '\''git am --show-current-patch=diff'\'' to see the failed patch Patch failed at 0001 Support Intel prefetchit0/t1 When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort".' ++ declare -- bret=128 ++ ++ 'berr=++++ git_am https://patchwork.plctlab.org/project/gcc-patch/patch/20221014081945.8318-3-haochen.jiang@intel.com/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/gcc-patch/patch/20221014081945.8318-3-haochen.jiang@intel.com/mbox/ ++++ curl https://patchwork.plctlab.org/project/gcc-patch/patch/20221014081945.8318-3-haochen.jiang@intel.com/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 48837 100 48837 0 0 781k 0 --:--:-- --:--:-- --:--:-- 781k +++ bout='\''Applying: Support Intel prefetchit0/t1 error: sha1 information is lacking or useless (gcc/common/config/i386/cpuinfo.h). error: could not build fake ancestor hint: Use '\''\'\'''\''git am --show-current-patch=diff'\''\'\'''\'' to see the failed patch Patch failed at 0001 Support Intel prefetchit0/t1 When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort".'\'' +++ bret=128' /tmp/jenkins2803384233662927229.sh: line 110: ++: command not found ++ ++ declare -p berr /tmp/jenkins2803384233662927229.sh: line 111: ++: command not found ++ declare -- 'berr=++++ git_am https://patchwork.plctlab.org/project/gcc-patch/patch/20221014081945.8318-3-haochen.jiang@intel.com/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/gcc-patch/patch/20221014081945.8318-3-haochen.jiang@intel.com/mbox/ ++++ curl https://patchwork.plctlab.org/project/gcc-patch/patch/20221014081945.8318-3-haochen.jiang@intel.com/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 48837 100 48837 0 0 781k 0 --:--:-- --:--:-- --:--:-- 781k +++ bout='\''Applying: Support Intel prefetchit0/t1 error: sha1 information is lacking or useless (gcc/common/config/i386/cpuinfo.h). error: could not build fake ancestor hint: Use '\''\'\'''\''git am --show-current-patch=diff'\''\'\'''\'' to see the failed patch Patch failed at 0001 Support Intel prefetchit0/t1 When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort".'\'' +++ bret=128' ++ git rev-parse HEAD + commitid_after=05af88ff4d2c95e543ebf4ef1cb8c4b171a009a1 + '[' 128 = 0 ']' + [[ ++++ git_am https://patchwork.plctlab.org/project/gcc-patch/patch/20221014081945.8318-3-haochen.jiang@intel.com/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/gcc-patch/patch/20221014081945.8318-3-haochen.jiang@intel.com/mbox/ ++++ curl https://patchwork.plctlab.org/project/gcc-patch/patch/20221014081945.8318-3-haochen.jiang@intel.com/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 48837 100 48837 0 0 781k 0 --:--:-- --:--:-- --:--:-- 781k +++ bout='Applying: Support Intel prefetchit0/t1 error: sha1 information is lacking or useless (gcc/common/config/i386/cpuinfo.h). error: could not build fake ancestor hint: Use '\''git am --show-current-patch=diff'\'' to see the failed patch Patch failed at 0001 Support Intel prefetchit0/t1 When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort".' +++ bret=128 =~ sha1 information is lacking or useless ]] + submit_check warning Unresolved https://patchwork.plctlab.org/jenkins/job/gcc-patch/1287/consoleText 'Git am fail log' + check_state=warning + patch_state=Unresolved + repo_url=https://patchwork.plctlab.org/jenkins/job/gcc-patch/1287/consoleText + DESCRIPTION='Git am fail log' + curl -X POST -H 'Authorization: Token [*******]' -F state=warning -F target_url=https://patchwork.plctlab.org/jenkins/job/gcc-patch/1287/consoleText -F context=gcc-patch-check -F 'description=Git am fail log' https://patchwork.plctlab.org/api/patches/2570/checks/ % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 962 100 422 100 540 7403 9473 --:--:-- --:--:-- --:--:-- 16877 {"id":964,"url":"https://patchwork.plctlab.org/api/patches/2570/checks/964/","user":{"id":1,"url":"https://patchwork.plctlab.org/api/users/1/","username":"snail","first_name":"","last_name":"","email":"wangliu@iscas.ac.cn"},"date":"2022-10-14T10:23:30.087836","state":"warning","target_url":"https://patchwork.plctlab.org/jenkins/job/gcc-patch/1287/consoleText","context":"gcc-patch-check","description":"Git am fail log"}+ curl -X PATCH -H 'Authorization: Token [*******]' -F state=Unresolved https://patchwork.plctlab.org/api/1.2/patches/2570/ % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0{"id":2570,"url":"https://patchwork.plctlab.org/api/1.2/patches/2570/","web_url":"https://patchwork.plctlab.org/project/gcc-patch/patch/20221014081945.8318-3-haochen.jiang@intel.com/","project":{"id":1,"url":"https://patchwork.plctlab.org/api/1.2/projects/1/","name":"gcc-patch","link_name":"gcc-patch","list_id":"gcc-patches.gcc.gnu.org","list_email":"gcc-patches@gcc.gnu.org","web_url":"https://gcc.gnu.org/mailman/listinfo/gcc-patches","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20221014081945.8318-3-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T08:19:45","name":"[2/3] Support Intel prefetchit0/t1","commit_ref":null,"pull_url":null,"state":"unresolved","archived":false,"hash":"2547f28598bc484488db13126351d3ca95df0f51","submitter":{"id":113,"url":"https://patchwork.plctlab.org/api/1.2/people/113/","name":"Haochen Jiang","email":"haochen.jiang@intel.com"},"delegate":null,"mbox":"https://patchwork.plctlab.org/project/gcc-patch/patch/20221014081945.8318-3-haochen.jiang@intel.com/mbox/","series":[{"id":1905,"url":"https://patchwork.plctlab.org/api/1.2/series/1905/","web_url":"https://patchwork.plctlab.org/project/gcc-patch/list/?series=1905","date":"2022-10-14T08:19:45","name":"[1/3] Add a parameter for the builtin function of prefetch to align with LLVM","version":1,"mbox":"https://patchwork.plctlab.org/series/1905/mbox/"}],"comments":"https://patchwork.plctlab.org/api/patches/2570/comments/","check":"warning","checks":"https://patchwork.plctlab.org/api/patches/2570/checks/","tags":{},"headers":{"Return-Path":"","Delivered-To":["ouuuleilei@gmail.com","gcc-patches@gcc.gnu.org"],"Received":["by 2002:a5d:4ac7:0:0:0:0:0 with SMTP id y7csp62507wrs;\n Fri, 14 Oct 2022 01:21:27 -0700 (PDT)","from sourceware.org (ip-8-43-85-97.sourceware.org. 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KAM_NUMSUBJECT, KAM_SHORT, KAM_STOCKGEN, SPF_HELO_NONE, SPF_NONE,\n TXREP autolearn=ham autolearn_force=no version=3.4.6","X-Spam-Checker-Version":"SpamAssassin 3.4.6 (2021-04-09) on\n server2.sourceware.org","X-BeenThere":"gcc-patches@gcc.gnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"Gcc-patches mailing list ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","From":"Haochen Jiang via Gcc-patches ","Reply-To":"Haochen Jiang ","Cc":"aoliva@gcc.gnu.org, richard.sandiford@arm.com, uweigand@de.ibm.com,\n linkw@gcc.gnu.org, gnu@amylaar.uk, dje.gcc@gmail.com, olegendo@gcc.gnu.org,\n claziss@synopsys.com, segher@kernel.crashing.org, mfortune@gmail.com,\n davem@redhat.com, dave.anglin@bell.net, hubicka@ucw.cz,\n richard.earnshaw@arm.com, rguenther@suse.de, marcus.shawcroft@arm.com,\n ramana.radhakrishnan@arm.com, hongtao.liu@intel.com","Errors-To":"gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org","Sender":"\"Gcc-patches\" ","X-getmail-retrieved-from-mailbox":"=?utf-8?q?INBOX?=","X-GMAIL-THRID":"=?utf-8?q?1746650463641400440?=","X-GMAIL-MSGID":"=?utf-8?q?1746650463641400440?="},"content":"gcc/ChangeLog:\n\n\t* common/config/i386/cpuinfo.h (get_available_features):\n\tDetect PREFETCHI.\n\t* common/config/i386/i386-common.cc\n\t(OPTION_MASK_ISA2_PREFETCHI_SET,\n\tOPTION_MASK_ISA2_PREFETCHI_UNSET): New.\n\t(ix86_handle_option): Handle -mprefetchi.\n\t* common/config/i386/i386-cpuinfo.h (enum processor_features):\n\tAdd FEATURE_PREFETCHI.\n\t* common/config/i386/i386-isas.h: Add ISA_NAME_TABLE_ENTRY for\n\tprefetchi.\n\t* config.gcc: Add prfchiintrin.h.\n\t* config/i386/cpuid.h (bit_PREFETCHI): New.\n\t* config/i386/i386-c.cc (ix86_target_macros_internal): Define\n\t__PREFETCHI__.\n\t* config/i386/i386-isa.def (PREFETCHI):\tAdd DEF_PTA(PREFETCHI).\n\t* config/i386/i386-options.cc (ix86_valid_target_attribute_inner_p):\n\tHandle prefetchi.\n\t* config/i386/i386.md (prefetch): Add handler for prefetchi\n\t(*prefetch_i): New define_insn.\n\t* config/i386/i386.opt: Add option -mprefetchi.\n\t* config/i386/immintrin.h: Include prfchiintrin.h.\n\t* config/i386/predicates.md (local_func_symbolic_operand):\n\tNew predicates.\n\t* config/i386/xmmintrin.h (enum _mm_hint): New enum for prefetchi.\n\t(_mm_prefetch): Handle the highest bit of enum.\n\t* doc/extend.texi: Document prefetchi.\n\t* doc/invoke.texi: Document -mprefetchi.\n\t* doc/sourcebuild.texi: Document target prefetchi.\n\t* config/i386/prfchiintrin.h: New file.\n\ngcc/testsuite/ChangeLog:\n\n\t* g++.dg/other/i386-2.C: Add -mprefetchi.\n\t* g++.dg/other/i386-3.C: Ditto.\n\t* gcc.misc-tests/i386-pf-3dnow-1.c: Add scan-assembler-not for\n\tprefetchit0/t1.\n\t* gcc.misc-tests/i386-pf-athlon-1.c: Ditto.\n\t* gcc.misc-tests/i386-pf-sse-1.c: Ditto.\n\t* gcc.target/i386/avx-1.c: Add -mprefetchi.\n\t* gcc.target/i386/avx-2.c: Ditto.\n\t* gcc.target/i386/funcspec-56.inc: Add new target attribute.\n\t* gcc.target/i386/prefetchi-1.c: Rewrite testcase.\n\t* gcc.target/i386/prefetchi-2.c: New test.\n\t* gcc.target/i386/prefetchi-3.c: Ditto.\n\t* gcc.target/i386/sse-12.c: Add -mprefetchi.\n\t* gcc.target/i386/sse-13.c: Ditto.\n\t* gcc.target/i386/sse-14.c: Ditto.\n\t* gcc.target/i386/sse-22.c: Add prefetchi.\n\t* gcc.target/i386/sse-23.c: Ditto.\n\nCo-authored-by: Hongtao Liu \n---\n gcc/common/config/i386/cpuinfo.h | 2 +\n gcc/common/config/i386/i386-common.cc | 15 ++++\n gcc/common/config/i386/i386-cpuinfo.h | 1 +\n gcc/common/config/i386/i386-isas.h | 1 +\n gcc/config.gcc | 2 +-\n gcc/config/i386/cpuid.h | 1 +\n gcc/config/i386/i386-c.cc | 2 +\n gcc/config/i386/i386-isa.def | 1 +\n gcc/config/i386/i386-options.cc | 4 +-\n gcc/config/i386/i386.md | 90 +++++++++++++------\n gcc/config/i386/i386.opt | 4 +\n gcc/config/i386/immintrin.h | 2 +\n gcc/config/i386/predicates.md | 15 ++++\n gcc/config/i386/prfchiintrin.h | 39 ++++++++\n gcc/config/i386/xmmintrin.h | 6 +-\n gcc/doc/extend.texi | 5 ++\n gcc/doc/invoke.texi | 10 ++-\n gcc/doc/sourcebuild.texi | 3 +\n gcc/testsuite/g++.dg/other/i386-2.C | 2 +-\n gcc/testsuite/g++.dg/other/i386-3.C | 2 +-\n .../gcc.misc-tests/i386-pf-3dnow-1.c | 2 +\n .../gcc.misc-tests/i386-pf-athlon-1.c | 2 +\n gcc/testsuite/gcc.misc-tests/i386-pf-sse-1.c | 2 +\n gcc/testsuite/gcc.target/i386/avx-1.c | 2 +-\n gcc/testsuite/gcc.target/i386/avx-2.c | 2 +-\n gcc/testsuite/gcc.target/i386/funcspec-56.inc | 2 +\n gcc/testsuite/gcc.target/i386/prefetchi-1.c | 36 ++++++--\n gcc/testsuite/gcc.target/i386/prefetchi-2.c | 26 ++++++\n gcc/testsuite/gcc.target/i386/prefetchi-3.c | 15 ++++\n gcc/testsuite/gcc.target/i386/sse-12.c | 2 +-\n gcc/testsuite/gcc.target/i386/sse-13.c | 2 +-\n gcc/testsuite/gcc.target/i386/sse-14.c | 2 +-\n gcc/testsuite/gcc.target/i386/sse-22.c | 4 +-\n gcc/testsuite/gcc.target/i386/sse-23.c | 2 +-\n 34 files changed, 259 insertions(+), 49 deletions(-)\n create mode 100644 gcc/config/i386/prfchiintrin.h\n create mode 100644 gcc/testsuite/gcc.target/i386/prefetchi-2.c\n create mode 100644 gcc/testsuite/gcc.target/i386/prefetchi-3.c","diff":"diff --git a/gcc/common/config/i386/cpuinfo.h b/gcc/common/config/i386/cpuinfo.h\nindex 118f3a42abd..551e0483330 100644\n--- a/gcc/common/config/i386/cpuinfo.h\n+++ b/gcc/common/config/i386/cpuinfo.h\n@@ -797,6 +797,8 @@ get_available_features (struct __processor_model *cpu_model,\n \tset_feature (FEATURE_HRESET);\n if (eax & bit_CMPCCXADD)\n \tset_feature(FEATURE_CMPCCXADD);\n+ if (edx & bit_PREFETCHI)\n+\tset_feature (FEATURE_PREFETCHI);\n if (avx_usable)\n \t{\n \t if (eax & bit_AVXVNNI)\ndiff --git a/gcc/common/config/i386/i386-common.cc b/gcc/common/config/i386/i386-common.cc\nindex f3d00ce4bc9..77ff07a3797 100644\n--- a/gcc/common/config/i386/i386-common.cc\n+++ b/gcc/common/config/i386/i386-common.cc\n@@ -112,6 +112,7 @@ along with GCC; see the file COPYING3. If not see\n #define OPTION_MASK_ISA2_AVXNECONVERT_SET OPTION_MASK_ISA2_AVXNECONVERT\n #define OPTION_MASK_ISA2_CMPCCXADD_SET OPTION_MASK_ISA2_CMPCCXADD\n #define OPTION_MASK_ISA2_AMX_FP16_SET OPTION_MASK_ISA2_AMX_FP16\n+#define OPTION_MASK_ISA2_PREFETCHI_SET OPTION_MASK_ISA2_PREFETCHI\n \n /* SSE4 includes both SSE4.1 and SSE4.2. -msse4 should be the same\n as -msse4.2. */\n@@ -287,6 +288,7 @@ along with GCC; see the file COPYING3. If not see\n #define OPTION_MASK_ISA2_AVXNECONVERT_UNSET OPTION_MASK_ISA2_AVXNECONVERT\n #define OPTION_MASK_ISA2_CMPCCXADD_UNSET OPTION_MASK_ISA2_CMPCCXADD\n #define OPTION_MASK_ISA2_AMX_FP16_UNSET OPTION_MASK_ISA2_AMX_FP16\n+#define OPTION_MASK_ISA2_PREFETCHI_UNSET OPTION_MASK_ISA2_PREFETCHI\n \n /* SSE4 includes both SSE4.1 and SSE4.2. -mno-sse4 should the same\n as -mno-sse4.1. */\n@@ -1211,6 +1213,19 @@ ix86_handle_option (struct gcc_options *opts,\n \t}\n return true;\n \n+ case OPT_mprefetchi:\n+ if (value)\n+\t{\n+\t opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_PREFETCHI_SET;\n+\t opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_PREFETCHI_SET;\n+\t}\n+ else\n+\t{\n+\t opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_PREFETCHI_UNSET;\n+\t opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_PREFETCHI_UNSET;\n+\t}\n+ return true;\n+\n case OPT_mfma:\n if (value)\n \t{\ndiff --git a/gcc/common/config/i386/i386-cpuinfo.h b/gcc/common/config/i386/i386-cpuinfo.h\nindex f9d5b7238ea..3fe69178841 100644\n--- a/gcc/common/config/i386/i386-cpuinfo.h\n+++ b/gcc/common/config/i386/i386-cpuinfo.h\n@@ -246,6 +246,7 @@ enum processor_features\n FEATURE_AVXNECONVERT,\n FEATURE_CMPCCXADD,\n FEATURE_AMX_FP16,\n+ FEATURE_PREFETCHI,\n CPU_FEATURE_MAX\n };\n \ndiff --git a/gcc/common/config/i386/i386-isas.h b/gcc/common/config/i386/i386-isas.h\nindex 7c4a71413b5..8648ea6903c 100644\n--- a/gcc/common/config/i386/i386-isas.h\n+++ b/gcc/common/config/i386/i386-isas.h\n@@ -182,4 +182,5 @@ ISA_NAMES_TABLE_START\n \t\t\tP_NONE, \"-mavxneconvert\")\n ISA_NAMES_TABLE_ENTRY(\"cmpccxadd\", FEATURE_CMPCCXADD, P_NONE, \"-mcmpccxadd\")\n ISA_NAMES_TABLE_ENTRY(\"amx-fp16\", FEATURE_AMX_FP16, P_NONE, \"-mamx-fp16\")\n+ ISA_NAMES_TABLE_ENTRY(\"prefetchi\", FEATURE_PREFETCHI, P_NONE, \"-mprefetchi\")\n ISA_NAMES_TABLE_END\ndiff --git a/gcc/config.gcc b/gcc/config.gcc\nindex 8a8712d1466..ceea7726bfd 100644\n--- a/gcc/config.gcc\n+++ b/gcc/config.gcc\n@@ -423,7 +423,7 @@ i[34567]86-*-* | x86_64-*-*)\n \t\t hresetintrin.h keylockerintrin.h avxvnniintrin.h\n \t\t mwaitintrin.h avx512fp16intrin.h avx512fp16vlintrin.h\n \t\t avxifmaintrin.h avxvnniint8intrin.h avxneconvertintrin.h\n-\t\t cmpccxaddintrin.h amxfp16intrin.h\"\n+\t\t cmpccxaddintrin.h amxfp16intrin.h prfchiintrin.h\"\n \t;;\n ia64-*-*)\n \textra_headers=ia64intrin.h\ndiff --git a/gcc/config/i386/cpuid.h b/gcc/config/i386/cpuid.h\nindex 229c15c5950..92583261883 100644\n--- a/gcc/config/i386/cpuid.h\n+++ b/gcc/config/i386/cpuid.h\n@@ -54,6 +54,7 @@\n #define bit_AVXVNNIINT8 (1 << 4)\n #define bit_AVXNECONVERT (1 << 5)\n #define bit_CMPXCHG8B\t(1 << 8)\n+#define bit_PREFETCHI\t(1 << 14)\n #define bit_CMOV\t(1 << 15)\n #define bit_MMX\t\t(1 << 23)\n #define bit_FXSAVE\t(1 << 24)\ndiff --git a/gcc/config/i386/i386-c.cc b/gcc/config/i386/i386-c.cc\nindex 3020b5f267a..74239002ed6 100644\n--- a/gcc/config/i386/i386-c.cc\n+++ b/gcc/config/i386/i386-c.cc\n@@ -650,6 +650,8 @@ ix86_target_macros_internal (HOST_WIDE_INT isa_flag,\n def_or_undef (parse_in, \"__CMPCCXADD__\");\n if (isa_flag2 & OPTION_MASK_ISA2_AMX_FP16)\n def_or_undef (parse_in, \"__AMX_FP16__\");\n+ if (isa_flag2 & OPTION_MASK_ISA2_PREFETCHI)\n+ def_or_undef (parse_in, \"__PREFETCHI__\");\n if (TARGET_IAMCU)\n {\n def_or_undef (parse_in, \"__iamcu\");\ndiff --git a/gcc/config/i386/i386-isa.def b/gcc/config/i386/i386-isa.def\nindex 55b25763957..f234dcc37d7 100644\n--- a/gcc/config/i386/i386-isa.def\n+++ b/gcc/config/i386/i386-isa.def\n@@ -114,3 +114,4 @@ DEF_PTA(AVXVNNIINT8)\n DEF_PTA(AVXNECONVERT)\n DEF_PTA(CMPCCXADD)\n DEF_PTA(AMX_FP16)\n+DEF_PTA(PREFETCHI)\ndiff --git a/gcc/config/i386/i386-options.cc b/gcc/config/i386/i386-options.cc\nindex bf37c77589e..3f98b09e5cf 100644\n--- a/gcc/config/i386/i386-options.cc\n+++ b/gcc/config/i386/i386-options.cc\n@@ -232,7 +232,8 @@ static struct ix86_target_opts isa2_opts[] =\n { \"-mavxvnniint8\",\tOPTION_MASK_ISA2_AVXVNNIINT8 },\n { \"-mavxneconvert\", OPTION_MASK_ISA2_AVXNECONVERT },\n { \"-mcmpccxadd\", OPTION_MASK_ISA2_CMPCCXADD },\n- { \"-mamx-fp16\", OPTION_MASK_ISA2_AMX_FP16 }\n+ { \"-mamx-fp16\", OPTION_MASK_ISA2_AMX_FP16 },\n+ { \"-mprefetchi\", OPTION_MASK_ISA2_PREFETCHI }\n };\n static struct ix86_target_opts isa_opts[] =\n {\n@@ -1084,6 +1085,7 @@ ix86_valid_target_attribute_inner_p (tree fndecl, tree args, char *p_strings[],\n IX86_ATTR_ISA (\"avxneconvert\", OPT_mavxneconvert),\n IX86_ATTR_ISA (\"cmpccxadd\", OPT_mcmpccxadd),\n IX86_ATTR_ISA (\"amx-fp16\", OPT_mamx_fp16),\n+ IX86_ATTR_ISA (\"prefetchi\", OPT_mprefetchi),\n \n /* enum options */\n IX86_ATTR_ENUM (\"fpmath=\",\tOPT_mfpmath_),\ndiff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md\nindex c65cf14b9f4..fb75f57483b 100644\n--- a/gcc/config/i386/i386.md\n+++ b/gcc/config/i386/i386.md\n@@ -23637,47 +23637,65 @@\n \t (match_operand:SI 1 \"const_int_operand\")\n \t (match_operand:SI 2 \"const_int_operand\")\n \t (match_operand:SI 3 \"const_int_operand\"))]\n- \"TARGET_3DNOW || TARGET_PREFETCH_SSE || TARGET_PRFCHW || TARGET_PREFETCHWT1\"\n+ \"TARGET_3DNOW || TARGET_PREFETCH_SSE || TARGET_PRFCHW || TARGET_PREFETCHWT1\n+ || TARGET_PREFETCHI\"\n {\n- if (INTVAL (operands[3]) == 0)\n- {\n- warning (0, \"instruction prefetch is not supported; using data prefetch\");\n- operands[3] = const1_rtx;\n- }\n bool write = operands[1] != const0_rtx;\n int locality = INTVAL (operands[2]);\n+ bool data = operands[3] != const0_rtx;\n \n gcc_assert (IN_RANGE (locality, 0, 3));\n \n- /* Use 3dNOW prefetch in case we are asking for write prefetch not\n- supported by SSE counterpart (non-SSE2 athlon machines) or the\n- SSE prefetch is not available (K6 machines). Otherwise use SSE\n- prefetch as it allows specifying of locality. */\n-\n- if (write)\n+ if (data)\n {\n- if (TARGET_PREFETCHWT1)\n-\toperands[2] = GEN_INT (MAX (locality, 2)); \n- else if (TARGET_PRFCHW)\n-\toperands[2] = GEN_INT (3);\n- else if (TARGET_3DNOW && !TARGET_SSE2)\n-\toperands[2] = GEN_INT (3);\n- else if (TARGET_PREFETCH_SSE)\n-\toperands[1] = const0_rtx;\n+ /* Use 3dNOW prefetch in case we are asking for write prefetch not\n+\t supported by SSE counterpart (non-SSE2 athlon machines) or the\n+\t SSE prefetch is not available (K6 machines). Otherwise use SSE\n+\t prefetch as it allows specifying of locality. */\n+\n+ if (write)\n+\t{\n+\t if (TARGET_PREFETCHWT1)\n+\t operands[2] = GEN_INT (MAX (locality, 2));\n+\t else if (TARGET_PRFCHW)\n+\t operands[2] = GEN_INT (3);\n+\t else if (TARGET_3DNOW && !TARGET_SSE2)\n+\t operands[2] = GEN_INT (3);\n+\t else if (TARGET_PREFETCH_SSE)\n+\t operands[1] = const0_rtx;\n+\t else\n+\t {\n+\t gcc_assert (TARGET_3DNOW);\n+\t operands[2] = GEN_INT (3);\n+\t }\n+\t}\n else\n \t{\n-\t gcc_assert (TARGET_3DNOW);\n-\t operands[2] = GEN_INT (3);\n+\t if (TARGET_PREFETCH_SSE)\n+\t ;\n+\t else\n+\t {\n+\t gcc_assert (TARGET_3DNOW);\n+\t operands[2] = GEN_INT (3);\n+\t }\n \t}\n }\n else\n {\n- if (TARGET_PREFETCH_SSE)\n+ /* GOT/PLT_PIC should not be available for instruction prefetch.\n+\t It must be real instruction address. */\n+ if (TARGET_PREFETCHI && TARGET_64BIT\n+\t && local_func_symbolic_operand (operands[0], GET_MODE (operands[0])))\n \t;\n else\n \t{\n-\t gcc_assert (TARGET_3DNOW);\n-\t operands[2] = GEN_INT (3);\n+\t /* Ignore the hint. */\n+\t warning (0, \"instruction prefetch applies when in 64-bit mode\"\n+\t\t \" with RIP-relative addressing and\"\n+\t\t \" option %<-mprefetchi%>;\"\n+\t\t \" they stay NOPs otherwise\");\n+\t emit_insn (gen_nop ());\n+\t DONE;\n \t}\n }\n })\n@@ -23733,6 +23751,28 @@\n \t(symbol_ref \"memory_address_length (operands[0], false)\"))\n (set_attr \"memory\" \"none\")])\n \n+(define_insn \"*prefetch_i\"\n+ [(prefetch (match_operand 0 \"local_func_symbolic_operand\" \"p\")\n+\t (const_int 0)\n+\t (match_operand:SI 1 \"const_int_operand\")\n+\t (const_int 0))]\n+ \"TARGET_PREFETCHI\"\n+{\n+ static const char * const patterns[2] = {\n+ \"prefetchit1\\t%a0\", \"prefetchit0\\t%a0\"\n+ };\n+\n+ int locality = INTVAL (operands[1]);\n+ gcc_assert (IN_RANGE (locality, 2, 3));\n+\n+ return patterns[locality - 2];\n+}\n+ [(set_attr \"type\" \"sse\")\n+ (set_attr \"atom_sse_attr\" \"prefetch\")\n+ (set (attr \"length_address\")\n+\t(symbol_ref \"memory_address_length (operands[0], false)\"))\n+ (set_attr \"memory\" \"none\")])\n+\n (define_expand \"stack_protect_set\"\n [(match_operand 0 \"memory_operand\")\n (match_operand 1 \"memory_operand\")]\ndiff --git a/gcc/config/i386/i386.opt b/gcc/config/i386/i386.opt\nindex eaa43946341..1d91103cd54 100644\n--- a/gcc/config/i386/i386.opt\n+++ b/gcc/config/i386/i386.opt\n@@ -1238,3 +1238,7 @@ CMPCCXADD build-in functions and code generation.\n mamx-fp16\n Target Mask(ISA2_AMX_FP16) Var(ix86_isa_flags2) Save\n Support AMX-FP16 built-in functions and code generation.\n+\n+mprefetchi\n+Target Mask(ISA2_PREFETCHI) Var(ix86_isa_flags2) Save\n+Support PREFETCHI built-in functions and code generation.\ndiff --git a/gcc/config/i386/immintrin.h b/gcc/config/i386/immintrin.h\nindex d8415863f52..ac6402653e0 100644\n--- a/gcc/config/i386/immintrin.h\n+++ b/gcc/config/i386/immintrin.h\n@@ -134,6 +134,8 @@\n \n #include \n \n+#include \n+\n #include \n \n #include \ndiff --git a/gcc/config/i386/predicates.md b/gcc/config/i386/predicates.md\nindex c4141a96735..2a3f07224cc 100644\n--- a/gcc/config/i386/predicates.md\n+++ b/gcc/config/i386/predicates.md\n@@ -610,6 +610,21 @@\n return false;\n })\n \n+(define_predicate \"local_func_symbolic_operand\"\n+ (match_operand 0 \"local_symbolic_operand\")\n+{\n+ if (GET_CODE (op) == CONST\n+ && GET_CODE (XEXP (op, 0)) == PLUS\n+ && CONST_INT_P (XEXP (XEXP (op, 0), 1)))\n+ op = XEXP (XEXP (op, 0), 0);\n+\n+ if (GET_CODE (op) == SYMBOL_REF\n+ && !SYMBOL_REF_FUNCTION_P (op))\n+ return false;\n+\n+ return true;\n+})\n+\n ;; Test for a legitimate @GOTOFF operand.\n ;;\n ;; VxWorks does not impose a fixed gap between segments; the run-time\ndiff --git a/gcc/config/i386/prfchiintrin.h b/gcc/config/i386/prfchiintrin.h\nnew file mode 100644\nindex 00000000000..e0240740e0b\n--- /dev/null\n+++ b/gcc/config/i386/prfchiintrin.h\n@@ -0,0 +1,39 @@\n+/* Copyright (C) 2022 Free Software Foundation, Inc.\n+\n+ This file is part of GCC.\n+\n+ GCC is free software; you can redistribute it and/or modify\n+ it under the terms of the GNU General Public License as published by\n+ the Free Software Foundation; either version 3, or (at your option)\n+ any later version.\n+\n+ GCC is distributed in the hope that it will be useful,\n+ but WITHOUT ANY WARRANTY; without even the implied warranty of\n+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n+ GNU General Public License for more details.\n+\n+ Under Section 7 of GPL version 3, you are granted additional\n+ permissions described in the GCC Runtime Library Exception, version\n+ 3.1, as published by the Free Software Foundation.\n+\n+ You should have received a copy of the GNU General Public License and\n+ a copy of the GCC Runtime Library Exception along with this program;\n+ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see\n+ . */\n+\n+#if !defined _IMMINTRIN_H_INCLUDED\n+# error \"Never use directly; include instead.\"\n+#endif\n+\n+#ifndef _PRFCHIINTRIN_H_INCLUDED\n+#define _PRFCHIINTRIN_H_INCLUDED\n+\n+#ifdef __x86_64__\n+extern __inline void __attribute__((__gnu_inline__, __always_inline__, __artificial__))\n+_m_prefetchi (void* __P)\n+{\n+ __builtin_prefetch (__P, 0, 3, 0 /* _MM_HINT_IT0 */);\n+}\n+#endif\n+\n+#endif /* _PRFCHIINTRIN_H_INCLUDED */\ndiff --git a/gcc/config/i386/xmmintrin.h b/gcc/config/i386/xmmintrin.h\nindex 62659080601..2fc644447e1 100644\n--- a/gcc/config/i386/xmmintrin.h\n+++ b/gcc/config/i386/xmmintrin.h\n@@ -36,6 +36,8 @@\n /* Constants for use with _mm_prefetch. */\n enum _mm_hint\n {\n+ _MM_HINT_IT0 = 19,\n+ _MM_HINT_IT1 = 18,\n /* _MM_HINT_ET is _MM_HINT_T with set 3rd bit. */\n _MM_HINT_ET0 = 7,\n _MM_HINT_ET1 = 6,\n@@ -51,11 +53,11 @@ enum _mm_hint\n extern __inline void __attribute__((__gnu_inline__, __always_inline__, __artificial__))\n _mm_prefetch (const void *__P, enum _mm_hint __I)\n {\n- __builtin_prefetch (__P, (__I & 0x4) >> 2, __I & 0x3);\n+ __builtin_prefetch (__P, (__I & 0x4) >> 2, __I & 0x3, ((__I & 0x10) >> 4) ^ 0x1);\n }\n #else\n #define _mm_prefetch(P, I) \\\n- __builtin_prefetch ((P), ((I & 0x4) >> 2), (I & 0x3))\n+ __builtin_prefetch ((P), ((I & 0x4) >> 2), (I & 0x3), (((I & 0x10) >> 4) ^ 0x1))\n #endif\n \n #ifndef __SSE__\ndiff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi\nindex e51d7835e69..2e0493fe8ba 100644\n--- a/gcc/doc/extend.texi\n+++ b/gcc/doc/extend.texi\n@@ -7085,6 +7085,11 @@ Enable/disable the generation of the CMPccXADD instructions.\n @cindex @code{target(\"amx-fp16\")} function attribute, x86\n Enable/disable the generation of the AMX-FP16 instructions.\n \n+@item prefetchi\n+@itemx no-prefetchi\n+@cindex @code{target(\"prefetchi\")} function attribute, x86\n+Enable/disable the generation of the PREFETCHI instructions.\n+\n @item cld\n @itemx no-cld\n @cindex @code{target(\"cld\")} function attribute, x86\ndiff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi\nindex 1014e2ded99..07a597d1b44 100644\n--- a/gcc/doc/invoke.texi\n+++ b/gcc/doc/invoke.texi\n@@ -1437,6 +1437,7 @@ See RS/6000 and PowerPC Options.\n -mrdseed -msgx -mavx512vp2intersect -mserialize -mtsxldtrk@gol\n -mamx-tile -mamx-int8 -mamx-bf16 -muintr -mhreset -mavxvnni@gol\n -mavx512fp16 -mavxifma -mavxvnniint8 -mavxneconvert -mcmpccxadd -mamx-fp16 @gol\n+-mprefetchi @gol\n -mcldemote -mms-bitfields -mno-align-stringops -minline-all-stringops @gol\n -minline-stringops-dynamically -mstringop-strategy=@var{alg} @gol\n -mkl -mwidekl @gol\n@@ -32916,6 +32917,9 @@ preferred alignment to @option{-mpreferred-stack-boundary=2}.\n @need 200\n @itemx -mamx-fp16\n @opindex mamx-fp16\n+@need 200\n+@itemx -mprefetchi\n+@opindex mprefetchi\n These switches enable the use of instructions in the MMX, SSE,\n SSE2, SSE3, SSSE3, SSE4, SSE4A, SSE4.1, SSE4.2, AVX, AVX2, AVX512F, AVX512PF,\n AVX512ER, AVX512CD, AVX512VL, AVX512BW, AVX512DQ, AVX512IFMA, AVX512VBMI, SHA,\n@@ -32926,9 +32930,9 @@ XSAVEOPT, XSAVEC, XSAVES, RTM, HLE, TBM, MWAITX, CLZERO, PKU, AVX512VBMI2,\n GFNI, VAES, WAITPKG, VPCLMULQDQ, AVX512BITALG, MOVDIRI, MOVDIR64B, AVX512BF16,\n ENQCMD, AVX512VPOPCNTDQ, AVX5124FMAPS, AVX512VNNI, AVX5124VNNIW, SERIALIZE,\n UINTR, HRESET, AMXTILE, AMXINT8, AMXBF16, KL, WIDEKL, AVXVNNI, AVX512FP16,\n-AVXIFMA, AVXVNNIINT8, AVXNECONVERT, CMPCCXADD, AMX-FP16 or CLDEMOTE extended\n-instruction sets. Each has a corresponding @option{-mno-} option to disable\n-use of these instructions.\n+AVXIFMA, AVXVNNIINT8, AVXNECONVERT, CMPCCXADD, AMX-FP16, PREFETCHI or CLDEMOTE\n+extended instruction sets. Each has a corresponding @option{-mno-} option to\n+disable use of these instructions.\n \n These extensions are also available as built-in functions: see\n @ref{x86 Built-in Functions}, for details of the functions enabled and\ndiff --git a/gcc/doc/sourcebuild.texi b/gcc/doc/sourcebuild.texi\nindex 5de5e9576d5..58adb6516ed 100644\n--- a/gcc/doc/sourcebuild.texi\n+++ b/gcc/doc/sourcebuild.texi\n@@ -2535,6 +2535,9 @@ Target does not require strict alignment.\n @item pie_copyreloc\n The x86-64 target linker supports PIE with copy reloc.\n \n+@item prefetchi\n+Target supports the execution of @code{prefetchi} instructions.\n+\n @item rdrand\n Target supports x86 @code{rdrand} instruction.\n \ndiff --git a/gcc/testsuite/g++.dg/other/i386-2.C b/gcc/testsuite/g++.dg/other/i386-2.C\nindex 79b84af0a75..ec3b1864ec0 100644\n--- a/gcc/testsuite/g++.dg/other/i386-2.C\n+++ b/gcc/testsuite/g++.dg/other/i386-2.C\n@@ -1,5 +1,5 @@\n /* { dg-do compile { target i?86-*-* x86_64-*-* } } */\n-/* { dg-options \"-O -pedantic-errors -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512dq -mavx512bw -mavx512vl -mavx512ifma -mavx512vbmi -mavx512vbmi2 -mavx5124fmaps -mavx5124vnniw -mavx512vpopcntdq -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mavx512bitalg -mpconfig -mwbnoinvd -mavx512bf16 -menqcmd -mavx512vp2intersect -mserialize -mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl -mavxvnni -mavx512fp16 -mavxifma -mavxvnniint8 -mavxneconvert -mcmpccxadd -mamx-fp16\" } */\n+/* { dg-options \"-O -pedantic-errors -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512dq -mavx512bw -mavx512vl -mavx512ifma -mavx512vbmi -mavx512vbmi2 -mavx5124fmaps -mavx5124vnniw -mavx512vpopcntdq -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mavx512bitalg -mpconfig -mwbnoinvd -mavx512bf16 -menqcmd -mavx512vp2intersect -mserialize -mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl -mavxvnni -mavx512fp16 -mavxifma -mavxvnniint8 -mavxneconvert -mcmpccxadd -mamx-fp16 -mprefetchi\" } */\n \n /* Test that {,x,e,p,t,s,w,a,b,i}mmintrin.h, mm3dnow.h, fma4intrin.h,\n xopintrin.h, abmintrin.h, bmiintrin.h, tbmintrin.h, lwpintrin.h,\ndiff --git a/gcc/testsuite/g++.dg/other/i386-3.C b/gcc/testsuite/g++.dg/other/i386-3.C\nindex c811a4454bf..542275ca057 100644\n--- a/gcc/testsuite/g++.dg/other/i386-3.C\n+++ b/gcc/testsuite/g++.dg/other/i386-3.C\n@@ -1,5 +1,5 @@\n /* { dg-do compile { target i?86-*-* x86_64-*-* } } */\n-/* { dg-options \"-O -fkeep-inline-functions -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512dq -mavx512bw -mavx512vl -mavx512ifma -mavx512vbmi -mavx512vbmi2 -mavx5124fmaps -mavx5124vnniw -mavx512vpopcntdq -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mavx512bitalg -mpconfig -mwbnoinvd -mavx512bf16 -menqcmd -mavx512vp2intersect -mserialize -mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl -mavxvnni -mavx512fp16 -mavxifma -mavxvnniint8 -mavxneconvert -mcmpccxadd -mamx-fp16\" } */\n+/* { dg-options \"-O -fkeep-inline-functions -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512dq -mavx512bw -mavx512vl -mavx512ifma -mavx512vbmi -mavx512vbmi2 -mavx5124fmaps -mavx5124vnniw -mavx512vpopcntdq -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mavx512bitalg -mpconfig -mwbnoinvd -mavx512bf16 -menqcmd -mavx512vp2intersect -mserialize -mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl -mavxvnni -mavx512fp16 -mavxifma -mavxvnniint8 -mavxneconvert -mcmpccxadd -mamx-fp16 -mprefetchi\" } */\n \n /* Test that {,x,e,p,t,s,w,a,b,i}mmintrin.h, mm3dnow.h, fma4intrin.h,\n xopintrin.h, abmintrin.h, bmiintrin.h, tbmintrin.h, lwpintrin.h,\ndiff --git a/gcc/testsuite/gcc.misc-tests/i386-pf-3dnow-1.c b/gcc/testsuite/gcc.misc-tests/i386-pf-3dnow-1.c\nindex eb9197b357c..40367947fb2 100644\n--- a/gcc/testsuite/gcc.misc-tests/i386-pf-3dnow-1.c\n+++ b/gcc/testsuite/gcc.misc-tests/i386-pf-3dnow-1.c\n@@ -29,3 +29,5 @@ int main ()\n /* { dg-final { scan-assembler \"prefetchw\" } } */\n /* { dg-final { scan-assembler-not \"prefetchnta\" } } */\n /* { dg-final { scan-assembler-not \"prefetcht\" } } */\n+/* { dg-final { scan-assembler-not \"prefetchit0\" } } */\n+/* { dg-final { scan-assembler-not \"prefetchit1\" } } */\ndiff --git a/gcc/testsuite/gcc.misc-tests/i386-pf-athlon-1.c b/gcc/testsuite/gcc.misc-tests/i386-pf-athlon-1.c\nindex b5081815f7a..0dda9f65ad5 100644\n--- a/gcc/testsuite/gcc.misc-tests/i386-pf-athlon-1.c\n+++ b/gcc/testsuite/gcc.misc-tests/i386-pf-athlon-1.c\n@@ -29,3 +29,5 @@ int main ()\n /* { dg-final { scan-assembler \"prefetchw\" } } */\n /* { dg-final { scan-assembler \"prefetchnta\" } } */\n /* { dg-final { scan-assembler \"prefetcht\" } } */\n+/* { dg-final { scan-assembler-not \"prefetchit0\" } } */\n+/* { dg-final { scan-assembler-not \"prefetchit1\" } } */\ndiff --git a/gcc/testsuite/gcc.misc-tests/i386-pf-sse-1.c b/gcc/testsuite/gcc.misc-tests/i386-pf-sse-1.c\nindex 936ad9e79ad..44d92f3a06e 100644\n--- a/gcc/testsuite/gcc.misc-tests/i386-pf-sse-1.c\n+++ b/gcc/testsuite/gcc.misc-tests/i386-pf-sse-1.c\n@@ -30,3 +30,5 @@ int main ()\n /* { dg-final { scan-assembler \"prefetcht1\" } } */\n /* { dg-final { scan-assembler \"prefetcht2\" } } */\n /* { dg-final { scan-assembler-not \"prefetchw\" } } */\n+/* { dg-final { scan-assembler-not \"prefetchit0\" } } */\n+/* { dg-final { scan-assembler-not \"prefetchit1\" } } */\ndiff --git a/gcc/testsuite/gcc.target/i386/avx-1.c b/gcc/testsuite/gcc.target/i386/avx-1.c\nindex ea0b9f6bcef..e599d1aa5d3 100644\n--- a/gcc/testsuite/gcc.target/i386/avx-1.c\n+++ b/gcc/testsuite/gcc.target/i386/avx-1.c\n@@ -1,5 +1,5 @@\n /* { dg-do compile } */\n-/* { dg-options \"-O2 -Werror-implicit-function-declaration -march=k8 -m3dnow -mavx -mavx2 -maes -mpclmul -mgfni -mavx512bw -mavx512fp16 -mavx512vl\" } */\n+/* { dg-options \"-O2 -Werror-implicit-function-declaration -march=k8 -m3dnow -mavx -mavx2 -maes -mpclmul -mgfni -mavx512bw -mavx512fp16 -mavx512vl -mprefetchi\" } */\n /* { dg-add-options bind_pic_locally } */\n \n #include \ndiff --git a/gcc/testsuite/gcc.target/i386/avx-2.c b/gcc/testsuite/gcc.target/i386/avx-2.c\nindex 642ae4d7bfb..af1f796fc68 100644\n--- a/gcc/testsuite/gcc.target/i386/avx-2.c\n+++ b/gcc/testsuite/gcc.target/i386/avx-2.c\n@@ -1,5 +1,5 @@\n /* { dg-do compile } */\n-/* { dg-options \"-O0 -Werror-implicit-function-declaration -march=k8 -m3dnow -mavx -mavx2 -msse4a -maes -mpclmul -mavx512bw -mavx512fp16 -mavx512vl\" } */\n+/* { dg-options \"-O0 -Werror-implicit-function-declaration -march=k8 -m3dnow -mavx -mavx2 -msse4a -maes -mpclmul -mavx512bw -mavx512fp16 -mavx512vl -mprefetchi\" } */\n /* { dg-add-options bind_pic_locally } */\n \n #include \ndiff --git a/gcc/testsuite/gcc.target/i386/funcspec-56.inc b/gcc/testsuite/gcc.target/i386/funcspec-56.inc\nindex ef9d4c5f5a4..2028f869f07 100644\n--- a/gcc/testsuite/gcc.target/i386/funcspec-56.inc\n+++ b/gcc/testsuite/gcc.target/i386/funcspec-56.inc\n@@ -85,6 +85,7 @@ extern void test_avxvnniint8 (void)\t\t__attribute__((__target__(\"avxvnniint8\")));\n extern void test_avxneconvert (void)\t\t__attribute__((__target__(\"avxneconvert\")));\n extern void test_cmpccxadd (void)\t\t__attribute__((__target__(\"cmpccxadd\")));\n extern void test_amx_fp16 (void)\t\t__attribute__((__target__(\"amx-fp16\")));\n+extern void test_prefetchi (void) __attribute__((__target__(\"prefetchi\")));\n \n extern void test_no_sgx (void)\t\t\t__attribute__((__target__(\"no-sgx\")));\n extern void test_no_avx5124fmaps(void)\t\t__attribute__((__target__(\"no-avx5124fmaps\")));\n@@ -171,6 +172,7 @@ extern void test_no_avxvnniint8 (void)\t\t__attribute__((__target__(\"no-avxvnniint\n extern void test_no_avxneconvert (void)\t\t__attribute__((__target__(\"no-avxneconvert\")));\n extern void test_no_cmpccxadd (void) __attribute__((__target__(\"no-cmpccxadd\")));\n extern void test_no_amx_fp16 (void)\t\t__attribute__((__target__(\"no-amx-fp16\")));\n+extern void test_no_prefetchi (void) __attribute__((__target__(\"no-prefetchi\")));\n \n extern void test_arch_nocona (void)\t\t__attribute__((__target__(\"arch=nocona\")));\n extern void test_arch_core2 (void)\t\t__attribute__((__target__(\"arch=core2\")));\ndiff --git a/gcc/testsuite/gcc.target/i386/prefetchi-1.c b/gcc/testsuite/gcc.target/i386/prefetchi-1.c\nindex b32d59f2e5f..f6a27ce267f 100644\n--- a/gcc/testsuite/gcc.target/i386/prefetchi-1.c\n+++ b/gcc/testsuite/gcc.target/i386/prefetchi-1.c\n@@ -1,11 +1,33 @@\n-/* { dg-do compile } */\n-/* { dg-options \"-O2 -msse\" } */\n+/* { dg-do compile { target { ! ia32 } } } */\n+/* { dg-options \"-mprefetchi -O2\" } */\n+/* { dg-final { scan-assembler-times \"\\[ \\\\t\\]+prefetchit0\\[ \\\\t\\]+\" 2 } } */\n+/* { dg-final { scan-assembler \"\\[ \\\\t\\]+prefetchit1\\[ \\\\t\\]+\" } } */\n \n-/* Remind users that instruction prefetch is not supported yet. */\n+#include \n \n-void\n-bad(const int* p)\n+int\n+bar (int a)\n {\n- __builtin_prefetch(p, 0, 3, 0);\t/* { dg-warning \"instruction prefetch is not supported; using data prefetch\" } */\n- __builtin_prefetch(p, 0, 2, 0);\t/* { dg-warning \"instruction prefetch is not supported; using data prefetch\" } */\n+ return a + 1;\n+}\n+\n+int\n+foo1 (int b)\n+{\n+ _mm_prefetch (bar, _MM_HINT_IT0);\n+ return bar (b) + 1;\n+}\n+\n+int\n+foo2 (int b)\n+{\n+ _mm_prefetch (bar, _MM_HINT_IT1);\n+ return bar (b) + 1;\n+}\n+\n+int\n+foo3 (int b)\n+{\n+ _m_prefetchi (bar);\n+ return bar (b) + 1;\n }\ndiff --git a/gcc/testsuite/gcc.target/i386/prefetchi-2.c b/gcc/testsuite/gcc.target/i386/prefetchi-2.c\nnew file mode 100644\nindex 00000000000..19a5dd18719\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/i386/prefetchi-2.c\n@@ -0,0 +1,26 @@\n+/* { dg-do compile { target { ia32 } } } */\n+/* { dg-options \"-mprefetchi -fpie -O2\" } */\n+/* { dg-final { scan-assembler-not \"\\[ \\\\t\\]+prefetchit0\" } } */\n+/* { dg-final { scan-assembler-not \"\\[ \\\\t\\]+prefetchit1\" } } */\n+\n+#include \n+\n+int\n+bar (int a)\n+{\n+ return a + 1;\n+}\n+\n+int\n+foo1 (int b)\n+{\n+ __builtin_prefetch (bar, 0, 3, 0); /* { dg-warning \"instruction prefetch applies when in 64-bit mode with RIP-relative addressing and option '-mprefetchi'; they stay NOPs otherwise\" } */\n+ return bar (b) + 1;\n+}\n+\n+int\n+foo2 (int b)\n+{\n+ __builtin_prefetch (bar, 0, 2, 0); /* { dg-warning \"instruction prefetch applies when in 64-bit mode with RIP-relative addressing and option '-mprefetchi'; they stay NOPs otherwise\" } */\n+ return bar (b) + 1;\n+}\ndiff --git a/gcc/testsuite/gcc.target/i386/prefetchi-3.c b/gcc/testsuite/gcc.target/i386/prefetchi-3.c\nnew file mode 100644\nindex 00000000000..cbca2ab34d9\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/i386/prefetchi-3.c\n@@ -0,0 +1,15 @@\n+/* { dg-do compile } */\n+/* { dg-options \"-mprefetchi -O2\" } */\n+/* { dg-final { scan-assembler-not \"prefetchit0\" } } */\n+/* { dg-final { scan-assembler-not \"prefetchit1\" } } */\n+\n+#include \n+\n+void* p;\n+\n+void extern\n+prefetchi_test (void)\n+{\n+ __builtin_prefetch (p, 0, 3, 0); /* { dg-warning \"instruction prefetch applies when in 64-bit mode with RIP-relative addressing and option '-mprefetchi'; they stay NOPs otherwise\" } */\n+ __builtin_prefetch (p, 0, 2, 0); /* { dg-warning \"instruction prefetch applies when in 64-bit mode with RIP-relative addressing and option '-mprefetchi'; they stay NOPs otherwise\" } */\n+}\ndiff --git a/gcc/testsuite/gcc.target/i386/sse-12.c b/gcc/testsuite/gcc.target/i386/sse-12.c\nindex df2684abbb6..8c556f3fcc5 100644\n--- a/gcc/testsuite/gcc.target/i386/sse-12.c\n+++ b/gcc/testsuite/gcc.target/i386/sse-12.c\n@@ -3,7 +3,7 @@\n popcntintrin.h gfniintrin.h and mm_malloc.h are usable\n with -O -std=c89 -pedantic-errors. */\n /* { dg-do compile } */\n-/* { dg-options \"-O -std=c89 -pedantic-errors -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512bw -mavx512dq -mavx512vl -mavx512vbmi -mavx512vbmi2 -mavx512ifma -mavx5124fmaps -mavx5124vnniw -mavx512vpopcntdq -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mavx512bitalg -mpconfig -mwbnoinvd -mavx512bf16 -menqcmd -mavx512vp2intersect -mserialize -mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl -mavxvnni -mavxifma -mavxvnniint8 -mavxneconvert -mamx-fp16\" } */\n+/* { dg-options \"-O -std=c89 -pedantic-errors -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512bw -mavx512dq -mavx512vl -mavx512vbmi -mavx512vbmi2 -mavx512ifma -mavx5124fmaps -mavx5124vnniw -mavx512vpopcntdq -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mavx512bitalg -mpconfig -mwbnoinvd -mavx512bf16 -menqcmd -mavx512vp2intersect -mserialize -mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl -mavxvnni -mavxifma -mavxvnniint8 -mavxneconvert -mamx-fp16 -mprefetchi\" } */\n \n #include \n \ndiff --git a/gcc/testsuite/gcc.target/i386/sse-13.c b/gcc/testsuite/gcc.target/i386/sse-13.c\nindex 6c9742cf494..ee5ba5ae4d5 100644\n--- a/gcc/testsuite/gcc.target/i386/sse-13.c\n+++ b/gcc/testsuite/gcc.target/i386/sse-13.c\n@@ -1,5 +1,5 @@\n /* { dg-do compile } */\n-/* { dg-options \"-O2 -Werror-implicit-function-declaration -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512vl -mavx512dq -mavx512bw -mavx512vbmi -mavx512vbmi2 -mavx512ifma -mavx5124fmaps -mavx5124vnniw -mavx512vpopcntdq -mavx512vp2intersect -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mavx512bitalg -mpconfig -mwbnoinvd -mavx512bf16 -menqcmd -mserialize -mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl -mavxvnni -mavx512fp16 -mavxifma -mavxvnniint8 -mavxneconvert -mcmpccxadd -mamx-fp16\" } */\n+/* { dg-options \"-O2 -Werror-implicit-function-declaration -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512vl -mavx512dq -mavx512bw -mavx512vbmi -mavx512vbmi2 -mavx512ifma -mavx5124fmaps -mavx5124vnniw -mavx512vpopcntdq -mavx512vp2intersect -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mavx512bitalg -mpconfig -mwbnoinvd -mavx512bf16 -menqcmd -mserialize -mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl -mavxvnni -mavx512fp16 -mavxifma -mavxvnniint8 -mavxneconvert -mcmpccxadd -mamx-fp16 -mprefetchi\" } */\n /* { dg-add-options bind_pic_locally } */\n \n #include \ndiff --git a/gcc/testsuite/gcc.target/i386/sse-14.c b/gcc/testsuite/gcc.target/i386/sse-14.c\nindex 4a47d4093a2..4f3bd70d03e 100644\n--- a/gcc/testsuite/gcc.target/i386/sse-14.c\n+++ b/gcc/testsuite/gcc.target/i386/sse-14.c\n@@ -1,5 +1,5 @@\n /* { dg-do compile } */\n-/* { dg-options \"-O0 -Werror-implicit-function-declaration -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512dq -mavx512bw -mavx512vl -mavx512ifma -mavx512vbmi -mavx512vbmi2 -mavx5124fmaps -mavx5124vnniw -mavx512vpopcntdq -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mpconfig -mwbnoinvd -mavx512vl -mavx512bf16 -menqcmd -mavx512vp2intersect -mserialize -mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl -mavxvnni -mavx512fp16 -mavxifma -mavxvnniint8 -mavxneconvert -mamx-fp16\" } */\n+/* { dg-options \"-O0 -Werror-implicit-function-declaration -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512dq -mavx512bw -mavx512vl -mavx512ifma -mavx512vbmi -mavx512vbmi2 -mavx5124fmaps -mavx5124vnniw -mavx512vpopcntdq -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mpconfig -mwbnoinvd -mavx512vl -mavx512bf16 -menqcmd -mavx512vp2intersect -mserialize -mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl -mavxvnni -mavx512fp16 -mavxifma -mavxvnniint8 -mavxneconvert -mamx-fp16 -mprefetchi\" } */\n /* { dg-add-options bind_pic_locally } */\n \n #include \ndiff --git a/gcc/testsuite/gcc.target/i386/sse-22.c b/gcc/testsuite/gcc.target/i386/sse-22.c\nindex 178a2fce492..8bd046b19c2 100644\n--- a/gcc/testsuite/gcc.target/i386/sse-22.c\n+++ b/gcc/testsuite/gcc.target/i386/sse-22.c\n@@ -103,7 +103,7 @@\n \n \n #ifndef DIFFERENT_PRAGMAS\n-#pragma GCC target (\"sse4a,3dnow,avx,avx2,fma4,xop,aes,pclmul,popcnt,abm,lzcnt,bmi,bmi2,tbm,lwp,fsgsbase,rdrnd,f16c,rtm,rdseed,prfchw,adx,fxsr,xsaveopt,avx512f,avx512er,avx512cd,avx512pf,sha,prefetchwt1,avx512vl,avx512bw,avx512dq,avx512vbmi,avx512vbmi2,avx512ifma,avx5124fmaps,avx5124vnniw,avx512vpopcntdq,gfni,avx512bitalg,avx512bf16,avx512vp2intersect,serialize,tsxldtrk,amx-tile,amx-int8,amx-bf16,kl,widekl,avxvnni,avx512fp16,avxifma,avxvnniint8,avxneconvert,amx-fp16\")\n+#pragma GCC target (\"sse4a,3dnow,avx,avx2,fma4,xop,aes,pclmul,popcnt,abm,lzcnt,bmi,bmi2,tbm,lwp,fsgsbase,rdrnd,f16c,rtm,rdseed,prfchw,adx,fxsr,xsaveopt,avx512f,avx512er,avx512cd,avx512pf,sha,prefetchwt1,avx512vl,avx512bw,avx512dq,avx512vbmi,avx512vbmi2,avx512ifma,avx5124fmaps,avx5124vnniw,avx512vpopcntdq,gfni,avx512bitalg,avx512bf16,avx512vp2intersect,serialize,tsxldtrk,amx-tile,amx-int8,amx-bf16,kl,widekl,avxvnni,avx512fp16,avxifma,avxvnniint8,avxneconvert,amx-fp16,prefetchi\")\n #endif\n \n /* Following intrinsics require immediate arguments. They\n@@ -220,7 +220,7 @@ test_4 (_mm_cmpestrz, int, __m128i, int, __m128i, int, 1)\n \n /* immintrin.h (AVX/AVX2/RDRND/FSGSBASE/F16C/RTM/AVX512F/SHA) */\n #ifdef DIFFERENT_PRAGMAS\n-#pragma GCC target (\"avx,avx2 100 51744 100 51594 100 150 1399k 4166 --:--:-- --:--:-- --:--:-- 1403k ,rdrnd,fsgsbase,f16c,rtm,avx512f,avx512er,avx512cd,avx512pf,sha,avx512vl,avx512bw,avx512dq,avx512ifma,avx512vbmi,avx512vbmi2,avx5124fmaps,avx5124vnniw,avx512vpopcntdq,gfni,avx512bitalg,avx512bf16,avx512vp2intersect,serialize,tsxldtrk,amx-tile,amx-int8,amx-bf16,kl,widekl,avxvnni,avx512fp16,avxifma,avxvnniint8,avxneconvert,amx-fp16\")\n+#pragma GCC target (\"avx,avx2,rdrnd,fsgsbase,f16c,rtm,avx512f,avx512er,avx512cd,avx512pf,sha,avx512vl,avx512bw,avx512dq,avx512ifma,avx512vbmi,avx512vbmi2,avx5124fmaps,avx5124vnniw,avx512vpopcntdq,gfni,avx512bitalg,avx512bf16,avx512vp2intersect,serialize,tsxldtrk,amx-tile,amx-int8,amx-bf16,kl,widekl,avxvnni,avx512fp16,avxifma,avxvnniint8,avxneconvert,amx-fp16,prefetchi\")\n #endif\n #include \n test_1 (_cvtss_sh, unsigned short, float, 1)\ndiff --git a/gcc/testsuite/gcc.target/i386/sse-23.c b/gcc/testsuite/gcc.target/i386/sse-23.c\nindex 344913e9a90..16ac9c9b7a4 100644\n--- a/gcc/testsuite/gcc.target/i386/sse-23.c\n+++ b/gcc/testsuite/gcc.target/i386/sse-23.c\n@@ -847,6 +847,6 @@\n #define __builtin_ia32_cmpccxadd(A, B, C, D) __builtin_ia32_cmpccxadd(A, B, C, 1)\n #define __builtin_ia32_cmpccxadd64(A, B, C, D) __builtin_ia32_cmpccxadd64(A, B, C, 1)\n \n-#pragma GCC target (\"sse4a,3dnow,avx,avx2,fma4,xop,aes,pclmul,popcnt,abm,lzcnt,bmi,bmi2,tbm,lwp,fsgsbase,rdrnd,f16c,fma,rtm,rdseed,prfchw,adx,fxsr,xsaveopt,avx512f,avx512er,avx512cd,avx512pf,sha,prefetchwt1,xsavec,xsaves,clflushopt,avx512bw,avx512dq,avx512vl,avx512vbmi,avx512ifma,avx5124fmaps,avx5124vnniw,avx512vpopcntdq,clwb,mwaitx,clzero,pku,sgx,rdpid,gfni,avx512vbmi2,vpclmulqdq,avx512bitalg,pconfig,wbnoinvd,avx512bf16,enqcmd,avx512vp2intersect,serialize,tsxldtrk,amx-tile,amx-int8,amx-bf16,kl,widekl,avxvnni,avx512fp16,avxifma,avxvnniint8,avxneconvert,cmpccxadd,amx-fp16\")\n+#pragma GCC target (\"sse4a,3dnow,avx,avx2,fma4,xop,aes,pclmul,popcnt,abm,lzcnt,bmi,bmi2,tbm,lwp,fsgsbase,rdrnd,f16c,fma,rtm,rdseed,prfchw,adx,fxsr,xsaveopt,avx512f,avx512er,avx512cd,avx512pf,sha,prefetchwt1,xsavec,xsaves,clflushopt,avx512bw,avx512dq,avx512vl,avx512vbmi,avx512ifma,avx5124fmaps,avx5124vnniw,avx512vpopcntdq,clwb,mwaitx,clzero,pku,sgx,rdpid,gfni,avx512vbmi2,vpclmulqdq,avx512bitalg,pconfig,wbnoinvd,avx512bf16,enqcmd,avx512vp2intersect,serialize,tsxldtrk,amx-tile,amx-int8,amx-bf16,kl,widekl,avxvnni,avx512fp16,avxifma,avxvnniint8,avxneconvert,cmpccxadd,amx-fp16,prefetchi\")\n \n #include \n","prefixes":["2/3"]}+ exit 1 Build step 'Execute shell' marked build as failure Finished: FAILURE