Started by user snail Running as SYSTEM [EnvInject] - Loading node environment variables. Building remotely on docker-jenkins-agent in workspace /home/jenkins/agent/workspace/gcc-patch [WS-CLEANUP] Deleting project workspace... [WS-CLEANUP] Deferred wipeout is used... [WS-CLEANUP] Done The recommended git tool is: NONE using credential 0adb5fc7-caa2-429d-97d2-c7fa2fa1d884 Cloning the remote Git repository Using shallow clone with depth 1 Avoid fetching tags Cloning repository git@github.com:wangliu-iscas/gcc-patch.git/ > git init /home/jenkins/agent/workspace/gcc-patch # timeout=10 Fetching upstream changes from git@github.com:wangliu-iscas/gcc-patch.git/ > git --version # timeout=10 > git --version # 'git version 2.37.2' using GIT_SSH to set credentials patchwork github wangliu-iscas git ssh key Verifying host key using known hosts file, will automatically accept unseen keys > git fetch --no-tags --force --progress --depth=1 -- git@github.com:wangliu-iscas/gcc-patch.git/ +refs/heads/*:refs/remotes/origin/* # timeout=10 > git config remote.origin.url git@github.com:wangliu-iscas/gcc-patch.git/ # timeout=10 > git config --add remote.origin.fetch +refs/heads/*:refs/remotes/origin/* # timeout=10 Avoid second fetch > git rev-parse refs/remotes/origin/master^{commit} # timeout=10 Checking out Revision a75e9bee7c23403d3cc7085a249f230de50c4c3e (refs/remotes/origin/master) > git config core.sparsecheckout # timeout=10 > git checkout -f a75e9bee7c23403d3cc7085a249f230de50c4c3e # timeout=10 Commit message: "Add cases for CFN_BUILT_IN_SIGNBIT[FL]." > git rev-list --no-walk a75e9bee7c23403d3cc7085a249f230de50c4c3e # timeout=10 [EnvInject] - Mask passwords that will be passed as build parameters. [EnvInject] - Executing scripts and injecting environment variables after the SCM step. [EnvInject] - Injecting as environment variables the properties content GITHUB_REPO=https://github.com/wangliu-iscas/ PATCHWORK_URL=https://patchwork.plctlab.org [EnvInject] - Variables injected successfully. [gcc-patch] $ /usr/bin/env bash /tmp/jenkins3503245631338122934.sh + git config pull.rebase false + git fetch origin master From github.com:wangliu-iscas/gcc-patch * branch master -> FETCH_HEAD + git checkout master Switched to a new branch 'master' branch 'master' set up to track 'origin/master'. + git pull origin master From github.com:wangliu-iscas/gcc-patch * branch master -> FETCH_HEAD Already up to date. + git fetch origin upstream-master From github.com:wangliu-iscas/gcc-patch * branch upstream-master -> FETCH_HEAD + git checkout upstream-master Switched to a new branch 'upstream-master' branch 'upstream-master' set up to track 'origin/upstream-master'. + git remote add upstream https://github.com/gcc-mirror/gcc.git + git pull upstream master From https://github.com/gcc-mirror/gcc * branch master -> FETCH_HEAD * [new branch] master -> upstream/master Already up to date. + git push -u origin upstream-master Everything up-to-date branch 'upstream-master' set up to track 'origin/upstream-master'. + git checkout master Switched to branch 'master' Your branch is up to date with 'origin/master'. + git merge upstream-master Already up to date. + git push -u origin master Everything up-to-date branch 'master' set up to track 'origin/master'. + branchname=series1901-patch2563 ++ grep 'series1901-patch2563$' ++ git branch -a + checkbranch= + checkbranchresult=null + '[' null = series1901-patch2563 ']' + git checkout -b series1901-patch2563 Switched to a new branch 'series1901-patch2563' ++ curl https://patchwork.plctlab.org/api/1.2/series/1901/ % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 1307 100 1307 0 0 22534 0 --:--:-- --:--:-- --:--:-- 22534 + series_response='{"id":1901,"url":"https://patchwork.plctlab.org/api/1.2/series/1901/","web_url":"https://patchwork.plctlab.org/project/gcc-patch/list/?series=1901","project":{"id":1,"url":"https://patchwork.plctlab.org/api/1.2/projects/1/","name":"gcc-patch","link_name":"gcc-patch","list_id":"gcc-patches.gcc.gnu.org","list_email":"gcc-patches@gcc.gnu.org","web_url":"https://gcc.gnu.org/mailman/listinfo/gcc-patches","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"name":"Support Intel AMX-FP16 ISA","date":"2022-10-14T07:58:43","submitter":{"id":113,"url":"https://patchwork.plctlab.org/api/1.2/people/113/","name":"Haochen Jiang","email":"haochen.jiang@intel.com"},"version":1,"total":1,"received_total":1,"received_all":true,"mbox":"https://patchwork.plctlab.org/series/1901/mbox/","cover_letter":null,"patches":[{"id":2563,"url":"https://patchwork.plctlab.org/api/1.2/patches/2563/","web_url":"https://patchwork.plctlab.org/project/gcc-patch/patch/20221014075843.8074-1-haochen.jiang@intel.com/","msgid":"<20221014075843.8074-1-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T07:58:43","name":"Support Intel AMX-FP16 ISA","mbox":"https://patchwork.plctlab.org/project/gcc-patch/patch/20221014075843.8074-1-haochen.jiang@intel.com/mbox/"}]}' ++ jq '.patches[] | (.id|tostring) + "," + .mbox' ++ echo '{"id":1901,"url":"https://patchwork.plctlab.org/api/1.2/series/1901/","web_url":"https://patchwork.plctlab.org/project/gcc-patch/list/?series=1901","project":{"id":1,"url":"https://patchwork.plctlab.org/api/1.2/projects/1/","name":"gcc-patch","link_name":"gcc-patch","list_id":"gcc-patches.gcc.gnu.org","list_email":"gcc-patches@gcc.gnu.org","web_url":"https://gcc.gnu.org/mailman/listinfo/gcc-patches","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"name":"Support Intel AMX-FP16 ISA","date":"2022-10-14T07:58:43","submitter":{"id":113,"url":"https://patchwork.plctlab.org/api/1.2/people/113/","name":"Haochen Jiang","email":"haochen.jiang@intel.com"},"version":1,"total":1,"received_total":1,"received_all":true,"mbox":"https://patchwork.plctlab.org/series/1901/mbox/","cover_letter":null,"patches":[{"id":2563,"url":"https://patchwork.plctlab.org/api/1.2/patches/2563/","web_url":"https://patchwork.plctlab.org/project/gcc-patch/patch/20221014075843.8074-1-haochen.jiang@intel.com/","msgid":"<20221014075843.8074-1-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T07:58:43","name":"Support Intel AMX-FP16 ISA","mbox":"https://patchwork.plctlab.org/project/gcc-patch/patch/20221014075843.8074-1-haochen.jiang@intel.com/mbox/"}]}' + patchid_patchurl='"2563,https://patchwork.plctlab.org/project/gcc-patch/patch/20221014075843.8074-1-haochen.jiang@intel.com/mbox/"' + IFS=, + read -r series_patch_id series_patch_url + echo '"2563,https://patchwork.plctlab.org/project/gcc-patch/patch/20221014075843.8074-1-haochen.jiang@intel.com/mbox/"' ++ echo '"2563' ++ sed 's/"//g' + series_patch_id=2563 ++ sed 's/"//g' ++ echo 'https://patchwork.plctlab.org/project/gcc-patch/patch/20221014075843.8074-1-haochen.jiang@intel.com/mbox/"' + series_patch_url=https://patchwork.plctlab.org/project/gcc-patch/patch/20221014075843.8074-1-haochen.jiang@intel.com/mbox/ ++ git rev-parse HEAD + commitid_before=a75e9bee7c23403d3cc7085a249f230de50c4c3e + eval '+++ declare -p bout bret declare -- bout="Applying: Support Intel AMX-FP16 ISA error: sha1 information is lacking or useless (gcc/common/config/i386/cpuinfo.h). error: could not build fake ancestor hint: Use '\''git am --show-current-patch=diff'\'' to see the failed patch Patch failed at 0001 Support Intel AMX-FP16 ISA When you have resolved this problem, run \"git am --continue\". If you prefer to skip this patch, run \"git am --skip\" instead. To restore the original branch and stop patching, run \"git am --abort\"." declare -- bret="128" ++ berr='\''++++ git_am https://patchwork.plctlab.org/project/gcc-patch/patch/20221014075843.8074-1-haochen.jiang@intel.com/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/gcc-patch/patch/20221014075843.8074-1-haochen.jiang@intel.com/mbox/ ++++ git am -3 --empty=drop ++++ curl https://patchwork.plctlab.org/project/gcc-patch/patch/20221014075843.8074-1-haochen.jiang@intel.com/mbox/ % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 42785 100 42785 0 0 280k 0 --:--:-- --:--:-- --:--:-- 282k +++ bout='\''\'\'''\''Applying: Support Intel AMX-FP16 ISA error: sha1 information is lacking or useless (gcc/common/config/i386/cpuinfo.h). error: could not build fake ancestor hint: Use '\''\'\'''\''\'\''\'\'''\'''\''\'\'''\''git am --show-current-patch=diff'\''\'\'''\''\'\''\'\'''\'''\''\'\'''\'' to see the failed patch Patch failed at 0001 Support Intel AMX-FP16 ISA When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort".'\''\'\'''\'' +++ bret=128'\'' ++ declare -p berr declare -- berr="++++ git_am https://patchwork.plctlab.org/project/gcc-patch/patch/20221014075843.8074-1-haochen.jiang@intel.com/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/gcc-patch/patch/20221014075843.8074-1-haochen.jiang@intel.com/mbox/ ++++ git am -3 --empty=drop ++++ curl https://patchwork.plctlab.org/project/gcc-patch/patch/20221014075843.8074-1-haochen.jiang@intel.com/mbox/ % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 42785 100 42785 0 0 280k 0 --:--:-- --:--:-- --:--:-- 282k +++ bout='\''Applying: Support Intel AMX-FP16 ISA error: sha1 information is lacking or useless (gcc/common/config/i386/cpuinfo.h). error: could not build fake ancestor hint: Use '\''\\'\'''\''git am --show-current-patch=diff'\''\\'\'''\'' to see the failed patch Patch failed at 0001 Support Intel AMX-FP16 ISA When you have resolved this problem, run \"git am --continue\". If you prefer to skip this patch, run \"git am --skip\" instead. To restore the original branch and stop patching, run \"git am --abort\".'\'' +++ bret=128"' ++ +++ declare -p bout bret /tmp/jenkins3503245631338122934.sh: line 85: +++: command not found ++ declare -- 'bout=Applying: Support Intel AMX-FP16 ISA error: sha1 information is lacking or useless (gcc/common/config/i386/cpuinfo.h). error: could not build fake ancestor hint: Use '\''git am --show-current-patch=diff'\'' to see the failed patch Patch failed at 0001 Support Intel AMX-FP16 ISA When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort".' ++ declare -- bret=128 ++ ++ 'berr=++++ git_am https://patchwork.plctlab.org/project/gcc-patch/patch/20221014075843.8074-1-haochen.jiang@intel.com/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/gcc-patch/patch/20221014075843.8074-1-haochen.jiang@intel.com/mbox/ ++++ git am -3 --empty=drop ++++ curl https://patchwork.plctlab.org/project/gcc-patch/patch/20221014075843.8074-1-haochen.jiang@intel.com/mbox/ % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 42785 100 42785 0 0 280k 0 --:--:-- --:--:-- --:--:-- 282k +++ bout='\''Applying: Support Intel AMX-FP16 ISA error: sha1 information is lacking or useless (gcc/common/config/i386/cpuinfo.h). error: could not build fake ancestor hint: Use '\''\'\'''\''git am --show-current-patch=diff'\''\'\'''\'' to see the failed patch Patch failed at 0001 Support Intel AMX-FP16 ISA When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort".'\'' +++ bret=128' /tmp/jenkins3503245631338122934.sh: line 110: ++: command not found ++ ++ declare -p berr /tmp/jenkins3503245631338122934.sh: line 111: ++: command not found ++ declare -- 'berr=++++ git_am https://patchwork.plctlab.org/project/gcc-patch/patch/20221014075843.8074-1-haochen.jiang@intel.com/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/gcc-patch/patch/20221014075843.8074-1-haochen.jiang@intel.com/mbox/ ++++ git am -3 --empty=drop ++++ curl https://patchwork.plctlab.org/project/gcc-patch/patch/20221014075843.8074-1-haochen.jiang@intel.com/mbox/ % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 42785 100 42785 0 0 280k 0 --:--:-- --:--:-- --:--:-- 282k +++ bout='\''Applying: Support Intel AMX-FP16 ISA error: sha1 information is lacking or useless (gcc/common/config/i386/cpuinfo.h). error: could not build fake ancestor hint: Use '\''\'\'''\''git am --show-current-patch=diff'\''\'\'''\'' to see the failed patch Patch failed at 0001 Support Intel AMX-FP16 ISA When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort".'\'' +++ bret=128' ++ git rev-parse HEAD + commitid_after=a75e9bee7c23403d3cc7085a249f230de50c4c3e + '[' 128 = 0 ']' + [[ ++++ git_am https://patchwork.plctlab.org/project/gcc-patch/patch/20221014075843.8074-1-haochen.jiang@intel.com/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/gcc-patch/patch/20221014075843.8074-1-haochen.jiang@intel.com/mbox/ ++++ git am -3 --empty=drop ++++ curl https://patchwork.plctlab.org/project/gcc-patch/patch/20221014075843.8074-1-haochen.jiang@intel.com/mbox/ % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 42785 100 42785 0 0 280k 0 --:--:-- --:--:-- --:--:-- 282k +++ bout='Applying: Support Intel AMX-FP16 ISA error: sha1 information is lacking or useless (gcc/common/config/i386/cpuinfo.h). error: could not build fake ancestor hint: Use '\''git am --show-current-patch=diff'\'' to see the failed patch Patch failed at 0001 Support Intel AMX-FP16 ISA When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort".' +++ bret=128 =~ sha1 information is lacking or useless ]] + submit_check warning Unresolved https://patchwork.plctlab.org/jenkins/job/gcc-patch/1286/consoleText 'Git am fail log' + check_state=warning + patch_state=Unresolved + repo_url=https://patchwork.plctlab.org/jenkins/job/gcc-patch/1286/consoleText + DESCRIPTION='Git am fail log' + curl -X POST -H 'Authorization: Token [*******]' -F state=warning -F target_url=https://patchwork.plctlab.org/jenkins/job/gcc-patch/1286/consoleText -F context=gcc-patch-check -F 'description=Git am fail log' https://patchwork.plctlab.org/api/patches/2563/checks/ % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 962 100 422 100 540 11722 15000 --:--:-- --:--:-- --:--:-- 26000 {"id":963,"url":"https://patchwork.plctlab.org/api/patches/2563/checks/963/","user":{"id":1,"url":"https://patchwork.plctlab.org/api/users/1/","username":"snail","first_name":"","last_name":"","email":"wangliu@iscas.ac.cn"},"date":"2022-10-14T10:22:43.804903","state":"warning","target_url":"https://patchwork.plctlab.org/jenkins/job/gcc-patch/1286/consoleText","context":"gcc-patch-check","description":"Git am fail log"}+ curl -X PATCH -H 'Authorization: Token [*******]' -F state=Unresolved https://patchwork.plctlab.org/api/1.2/patches/2563/ % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0{"id":2563,"url":"https://patchwork.plctlab.org/api/1.2/patches/2563/","web_url":"https://patchwork.plctlab.org/project/gcc-patch/patch/20221014075843.8074-1-haochen.jiang@intel.com/","project":{"id":1,"url":"https://patchwork.plctlab.org/api/1.2/projects/1/","name":"gcc-patch","link_name":"gcc-patch","list_id":"gcc-patches.gcc.gnu.org","list_email":"gcc-patches@gcc.gnu.org","web_url":"https://gcc.gnu.org/mailman/listinfo/gcc-patches","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20221014075843.8074-1-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T07:58:43","name":"Support Intel AMX-FP16 ISA","commit_ref":null,"pull_url":null,"state":"unresolved","archived":false,"hash":"8accf745356f51864a74e3bac7b6a3c2de839f0c","submitter":{"id":113,"url":"https://patchwork.plctlab.org/api/1.2/people/113/","name":"Haochen Jiang","email":"haochen.jiang@intel.com"},"delegate":null,"mbox":"https://patchwork.plctlab.org/project/gcc-patch/patch/20221014075843.8074-1-haochen.jiang@intel.com/mbox/","series":[{"id":1901,"url":"https://patchwork.plctlab.org/api/1.2/series/1901/","web_url":"https://patchwork.plctlab.org/project/gcc-patch/list/?series=1901","date":"2022-10-14T07:58:43","name":"Support Intel AMX-FP16 ISA","version":1,"mbox":"https://patchwork.plctlab.org/series/1901/mbox/"}],"comments":"https://patchwork.plctlab.org/api/patches/2563/comments/","check":"warning","checks":"https://patchwork.plctlab.org/api/patches/2563/checks/","tags":{},"headers":{"Return-Path":"","Delivered-To":["ouuuleilei@gmail.com","gcc-patches@gcc.gnu.org"],"Received":["by 2002:a5d:4ac7:0:0:0:0:0 with SMTP id y7csp55448wrs;\n Fri, 14 Oct 2022 01:01:06 -0700 (PDT)","from sourceware.org (ip-8-43-85-97.sourceware.org. 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c=relaxed/relaxed; d=gcc.gnu.org;\n\ts=default; t=1665734432;\n\tbh=o7pjLPWH2lVyqU7rK8IOvN5EEBlpHpm417Z0l87Q8zw=;\n\th=To:Subject:Date:List-Id:List-Unsubscribe:List-Archive:List-Post:\n\t List-Help:List-Subscribe:From:Reply-To:Cc:From;\n\tb=vSXVCVmJOZVAYP3l/8R02ewm17DW8W/ZMIpRgRpxfSIleT5YJyhN+bRMBwnWxYfX9\n\t WWj8EP7n20vTlyTtkaCWfrIuv6JWw4pGbXh+ZpPn7wzNrF17ZGV1Qty/3wv0JzP2eh\n\t wus2EuZLZLkUzB7gRJedDtVZC4pmC+kJMIQLPiIE=","X-Original-To":"gcc-patches@gcc.gnu.org","DMARC-Filter":"OpenDMARC Filter v1.4.1 sourceware.org 74232385084C","X-IronPort-AV":["E=McAfee;i=\"6500,9779,10499\"; a=\"292667610\"","E=Sophos;i=\"5.95,182,1661842800\"; d=\"scan'208\";a=\"292667610\"","E=McAfee;i=\"6500,9779,10499\"; a=\"716660501\"","E=Sophos;i=\"5.95,182,1661842800\"; d=\"scan'208\";a=\"716660501\""],"X-ExtLoop1":"1","To":"gcc-patches@gcc.gnu.org","Subject":"[PATCH] Support Intel AMX-FP16 ISA","Date":"Fri, 14 Oct 2022 15:58:43 +0800","Message-Id":"<20221014075843.8074-1-haochen.jiang@intel.com>","X-Mailer":"git-send-email 2.18.1","X-Spam-Status":"No, score=-12.0 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH,\n DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0,\n KAM_SHORT,\n RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_NONE,\n TXREP autolearn=ham autolearn_force=no version=3.4.6","X-Spam-Checker-Version":"SpamAssassin 3.4.6 (2021-04-09) on\n server2.sourceware.org","X-BeenThere":"gcc-patches@gcc.gnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"Gcc-patches mailing list ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","From":"Haochen Jiang via Gcc-patches ","Reply-To":"Haochen Jiang ","Cc":"hongtao.liu@intel.com, Hongyu Wang ","Errors-To":"gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org","Sender":"\"Gcc-patches\" ","X-getmail-retrieved-from-mailbox":"=?utf-8?q?INBOX?=","X-GMAIL-THRID":"=?utf-8?q?1746649183036991310?=","X-GMAIL-MSGID":"=?utf-8?q?1746649183036991310?="},"content":"From: Hongyu Wang \n\nHi all,\n\nThis patch aimed to add Intel AMX-FP16 ISA according to newly\nreleased Intel Architecture Instruction Set Extensions and Future Features.\n\nThe document comes following:\nhttps://www.intel.com/content/www/us/en/develop/download/intel-architecture-instruction-set-extensions-programming-reference.html\n\nRegtested on x86_64-pc-linux-gnu. Ok for trunk?\n\nBRs,\nHaochen\n\ngcc/ChangeLog:\n\n\t* common/config/i386/cpuinfo.h (get_available_features): Detect\n\tamx-fp16.\n\t* common/config/i386/i386-common.cc (OPTION_MASK_ISA2_AMX_FP16_SET,\n\t(OPTION_MASK_ISA2_AMX_FP16_UNSET): New macros.\n\t(ix86_handle_option): Handle -mamx-fp16.\n\t* common/config/i386/i386-cpuinfo.h (enum processor_features):\n\tAdd FEATURE_AMX_FP16.\n\t* common/config/i386/i386-isas.h: Add ISA_NAME_TABLE_ENTRY for\n\tamx-fp16.\n\t* config.gcc: Add amxfp16intrin.h.\n\t* config/i386/cpuid.h (bit_AMX_FP16): New.\n\t* config/i386/i386-c.cc (ix86_target_macros_internal): Define\n\t__AMX_FP16__.\n\t* config/i386/i386-options.cc (isa2_opts): Add -mamx-fp16.\n\t(ix86_valid_target_attribute_inner_p): Add new ATTR.\n\t(ix86_option_override_internal): Handle AMX-FP16.\n\t* config/i386/i386-isas.def: Add DEF_PTA for AMX_FP16.\n\t* config/i386/i386.opt: Add -mamx-fp16.\n\t* config/i386/immintrin.h: Include amxfp16intrin.h.\n\t* doc/extend.texi: Document -mamx-fp16.\n\t* doc/invoke.texi: Document amx-fp16.\n\t* doc/sourcebuild.texi: Document amx_fp16.\n\t* config/i386/amxfp16intrin.h: New file.\n\ngcc/testsuite/ChangeLog:\n\n\t* g++.dg/other/i386-2.C: Add -mamx-fp16.\n\t* g++.dg/other/i386-3.C: Ditto.\n\t* gcc.target/i386/sse-12.c: Ditto.\n\t* gcc.target/i386/sse-13.c: Ditto.\n\t* gcc.target/i386/sse-14.c: Ditto.\n\t* gcc.target/i386/sse-22.c: Ditto.\n\t* gcc.target/i386/sse-23.c: Ditto.\n\t* lib/target-supports.exp: (check_effective_target_amx_fp16):\n\tNew proc.\n\t* gcc.target/i386/funcspec-56.inc: Add new target attribute.\n\t* gcc.target/i386/amx-helper.h: New file to support amx-fp16.\n\t* gcc.target/i386/amxfp16-asmatt-1.c: New test.\n\t* gcc.target/i386/amxfp16-asmintel-1.c: Ditto.\n\t* gcc.target/i386/amxfp16-dpfp16ps-2.c: Ditto.\n\nCo-authored-by: Haochen Jiang \n---\n gcc/common/config/i386/cpuinfo.h | 5 ++\n gcc/common/config/i386/i386-common.cc | 15 +++++\n gcc/common/config/i386/i386-cpuinfo.h | 1 +\n gcc/common/config/i386/i386-isas.h | 1 +\n gcc/config.gcc | 2 +-\n gcc/config/i386/amxfp16intrin.h | 46 ++++++++++++++\n gcc/config/i386/cpuid.h | 1 +\n gcc/config/i386/i386-c.cc | 2 +\n gcc/config/i386/i386-isa.def | 1 +\n gcc/config/i386/i386-options.cc | 4 +-\n gcc/config/i386/i386.opt | 4 ++\n gcc/config/i386/immintrin.h | 2 +\n gcc/doc/extend.texi | 5 ++\n gcc/doc/invoke.texi | 11 ++--\n gcc/doc/sourcebuild.texi | 3 +\n gcc/testsuite/g++.dg/other/i386-2.C | 2 +-\n gcc/testsuite/g++.dg/other/i386-3.C | 2 +-\n gcc/testsuite/gcc.target/i386/amx-check.h | 3 +\n gcc/testsuite/gcc.target/i386/amx-helper.h | 61 +++++++++++++++++++\n .../gcc.target/i386/amxfp16-asmatt-1.c | 13 ++++\n .../gcc.target/i386/amxfp16-asmintel-1.c | 10 +++\n .../gcc.target/i386/amxfp16-dpfp16ps-2.c | 57 +++++++++++++++++\n gcc/testsuite/gcc.target/i386/funcspec-56.inc | 2 +\n gcc/testsuite/gcc.target/i386/sse-12.c | 2 +-\n gcc/testsuite/gcc.target/i386/sse-13.c | 2 +-\n gcc/testsuite/gcc.target/i386/sse-14.c | 2 +-\n gcc/testsuite/gcc.target/i386/sse-22.c | 4 +-\n gcc/testsuite/gcc.target/i386/sse-23.c | 2 +-\n gcc/testsuite/lib/target-supports.exp | 11 ++++\n 29 files changed, 262 insertions(+), 14 deletions(-)\n create mode 100644 gcc/config/i386/amxfp16intrin.h\n create mode 100644 gcc/testsuite/gcc.target/i386/amx-helper.h\n create mode 100644 gcc/testsuite/gcc.target/i386/amxfp16-asmatt-1.c\n create mode 100644 gcc/testsuite/gcc.target/i386/amxfp16-asmintel-1.c\n create mode 100644 gcc/testsuite/gcc.target/i386/amxfp16-dpfp16ps-2.c","diff":"diff --git a/gcc/common/config/i386/cpuinfo.h b/gcc/common/config/i386/cpuinfo.h\nindex cc499c46ed0..118f3a42abd 100644\n--- a/gcc/common/config/i386/cpuinfo.h\n+++ b/gcc/common/config/i386/cpuinfo.h\n@@ -813,6 +813,11 @@ get_available_features (struct __processor_model *cpu_model,\n \t if (eax & bit_AVX512BF16)\n \t set_feature (FEATURE_AVX512BF16);\n \t}\n+ if (amx_usable)\n+\t{\n+\t if (eax & bit_AMX_FP16)\n+\t set_feature (FEATURE_AMX_FP16);\n+\t}\n }\n \n /* Get Advanced Features at level 0xd (eax = 0xd, ecx = 1). */\ndiff --git a/gcc/common/config/i386/i386-common.cc b/gcc/common/config/i386/i386-common.cc\nindex 6ccc4d2f03c..f3d00ce4bc9 100644\n--- a/gcc/common/config/i386/i386-common.cc\n+++ b/gcc/common/config/i386/i386-common.cc\n@@ -111,6 +111,7 @@ along with GCC; see the file COPYING3. If not see\n #define OPTION_MASK_ISA2_AVXVNNIINT8_SET OPTION_MASK_ISA2_AVXVNNIINT8\n #define OPTION_MASK_ISA2_AVXNECONVERT_SET OPTION_MASK_ISA2_AVXNECONVERT\n #define OPTION_MASK_ISA2_CMPCCXADD_SET OPTION_MASK_ISA2_CMPCCXADD\n+#define OPTION_MASK_ISA2_AMX_FP16_SET OPTION_MASK_ISA2_AMX_FP16\n \n /* SSE4 includes both SSE4.1 and SSE4.2. -msse4 should be the same\n as -msse4.2. */\n@@ -285,6 +286,7 @@ along with GCC; see the file COPYING3. If not see\n #define OPTION_MASK_ISA2_AVXVNNIINT8_UNSET OPTION_MASK_ISA2_AVXVNNIINT8\n #define OPTION_MASK_ISA2_AVXNECONVERT_UNSET OPTION_MASK_ISA2_AVXNECONVERT\n #define OPTION_MASK_ISA2_CMPCCXADD_UNSET OPTION_MASK_ISA2_CMPCCXADD\n+#define OPTION_MASK_ISA2_AMX_FP16_UNSET OPTION_MASK_ISA2_AMX_FP16\n \n /* SSE4 includes both SSE4.1 and SSE4.2. -mno-sse4 should the same\n as -mno-sse4.1. */\n@@ -1196,6 +1198,19 @@ ix86_handle_option (struct gcc_options *opts,\n \t}\n return true;\n \n+ case OPT_mamx_fp16:\n+ if (value)\n+\t{\n+\t opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AMX_FP16_SET;\n+\t opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AMX_FP16_SET;\n+\t}\n+ else\n+\t{\n+\t opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AMX_FP16_UNSET;\n+\t opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AMX_FP16_UNSET;\n+\t}\n+ return true;\n+\n case OPT_mfma:\n if (value)\n \t{\ndiff --git a/gcc/common/config/i386/i386-cpuinfo.h b/gcc/common/config/i386/i386-cpuinfo.h\nindex a71a10ebbd7..f9d5b7238ea 100644\n--- a/gcc/common/config/i386/i386-cpuinfo.h\n+++ b/gcc/common/config/i386/i386-cpuinfo.h\n@@ -245,6 +245,7 @@ enum processor_features\n FEATURE_AVXVNNIINT8,\n FEATURE_AVXNECONVERT,\n FEATURE_CMPCCXADD,\n+ FEATURE_AMX_FP16,\n CPU_FEATURE_MAX\n };\n \ndiff --git a/gcc/common/config/i386/i386-isas.h b/gcc/common/config/i386/i386-isas.h\nindex 3035e4a8186..7c4a71413b5 100644\n--- a/gcc/common/config/i386/i386-isas.h\n+++ b/gcc/common/config/i386/i386-isas.h\n@@ -181,4 +181,5 @@ ISA_NAMES_TABLE_START\n ISA_NAMES_TABLE_ENTRY(\"avxneconvert\", FEATURE_AVXNECONVERT,\n \t\t\tP_NONE, \"-mavxneconvert\")\n ISA_NAMES_TABLE_ENTRY(\"cmpccxadd\", FEATURE_CMPCCXADD, P_NONE, \"-mcmpccxadd\")\n+ ISA_NAMES_TABLE_ENTRY(\"amx-fp16\", FEATURE_AMX_FP16, P_NONE, \"-mamx-fp16\")\n ISA_NAMES_TABLE_END\ndiff --git a/gcc/config.gcc b/gcc/config.gcc\nindex c0e10a72bd5..8a8712d1466 100644\n--- a/gcc/config.gcc\n+++ b/gcc/config.gcc\n@@ -423,7 +423,7 @@ i[34567]86-*-* | x86_64-*-*)\n \t\t hresetintrin.h keylockerintrin.h avxvnniintrin.h\n \t\t mwaitintrin.h avx512fp16intrin.h avx512fp16vlintrin.h\n \t\t avxifmaintrin.h avxvnniint8intrin.h avxneconvertintrin.h\n-\t\t cmpccxaddintrin.h\"\n+\t\t cmpccxaddintrin.h amxfp16intrin.h\"\n \t;;\n ia64-*-*)\n \textra_headers=ia64intrin.h\ndiff --git a/gcc/config/i386/amxfp16intrin.h b/gcc/config/i386/amxfp16intrin.h\nnew file mode 100644\nindex 00000000000..6a114741aa9\n--- /dev/null\n+++ b/gcc/config/i386/amxfp16intrin.h\n@@ -0,0 +1,46 @@\n+/* Copyright (C) 2020 Free Software Foundation, Inc.\n+\n+ This file is part of GCC.\n+\n+ GCC is free software; you can redistribute it and/or modify\n+ it under the terms of the GNU General Public License as published by\n+ the Free Software Foundation; either version 3, or (at your option)\n+ any later version.\n+\n+ GCC is distributed in the hope that it will be useful,\n+ but WITHOUT ANY WARRANTY; without even the implied warranty of\n+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n+ GNU General Public License for more details.\n+\n+ Under Section 7 of GPL version 3, you are granted additional\n+ permissions described in the GCC Runtime Library Exception, version\n+ 3.1, as published by the Free Software Foundation.\n+\n+ You should have received a copy of the GNU General Public License and\n+ a copy of the GCC Runtime Library Exception along with this program;\n+ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see\n+ . */\n+\n+#if !defined _IMMINTRIN_H_INCLUDED\n+#error \"Never use directly; include instead.\"\n+#endif\n+\n+#ifndef _AMXFP16INTRIN_H_INCLUDED\n+#define _AMXFP16INTRIN_H_INCLUDED\n+\n+#if defined(__x86_64__)\n+#define _tile_dpfp16ps_internal(dst,src1,src2)\t\t\t\\\n+ __asm__ volatile \\\n+ (\"{tdpfp16ps\\t%%tmm\"#src2\", %%tmm\"#src1\", %%tmm\"#dst\"|tdpfp16ps\\t%%tmm\"#dst\", %%tmm\"#src1\", %%tmm\"#src2\"}\" ::)\n+\n+#define _tile_dpfp16ps(dst,src1,src2)\t\t\t\t\\\n+ _tile_dpfp16ps_internal (dst,src1,src2)\n+\n+#endif\n+\n+#ifdef __DISABLE_AMX_FP16__\n+#undef __DISABLE_AMX_FP16__\n+#pragma GCC pop_options\n+#endif /* __DISABLE_AMX_FP16__ */\n+\n+#endif /* _AMXFP16INTRIN_H_INCLUDED */\ndiff --git a/gcc/config/i386/cpuid.h b/gcc/config/i386/cpuid.h\nindex 19c0d033921..229c15c5950 100644\n--- a/gcc/config/i386/cpuid.h\n+++ b/gcc/config/i386/cpuid.h\n@@ -28,6 +28,7 @@\n #define bit_AVXVNNI\t(1 << 4)\n #define bit_AVX512BF16\t(1 << 5)\n #define bit_CMPCCXADD\t(1 << 7)\n+#define bit_AMX_FP16\t(1 << 21)\n #define bit_HRESET\t(1 << 22)\n #define bit_AVXIFMA\t(1 << 23)\n \ndiff --git a/gcc/config/i386/i386-c.cc b/gcc/config/i386/i386-c.cc\nindex 4494c412995..3020b5f267a 100644\n--- a/gcc/config/i386/i386-c.cc\n+++ b/gcc/config/i386/i386-c.cc\n@@ -648,6 +648,8 @@ ix86_target_macros_internal (HOST_WIDE_INT isa_flag,\n def_or_undef (parse_in, \"__AVXNECONVERT__\");\n if (isa_flag2 & OPTION_MASK_ISA2_CMPCCXADD)\n def_or_undef (parse_in, \"__CMPCCXADD__\");\n+ if (isa_flag2 & OPTION_MASK_ISA2_AMX_FP16)\n+ def_or_undef (parse_in, \"__AMX_FP16__\");\n if (TARGET_IAMCU)\n {\n def_or_undef (parse_in, \"__iamcu\");\ndiff --git a/gcc/config/i386/i386-isa.def b/gcc/config/i386/i386-isa.def\nindex 7ffc73ba23e..55b25763957 100644\n--- a/gcc/config/i386/i386-isa.def\n+++ b/gcc/config/i386/i386-isa.def\n@@ -113,3 +113,4 @@ DEF_PTA(AVXIFMA)\n DEF_PTA(AVXVNNIINT8)\n DEF_PTA(AVXNECONVERT)\n DEF_PTA(CMPCCXADD)\n+DEF_PTA(AMX_FP16)\ndiff --git a/gcc/config/i386/i386-options.cc b/gcc/config/i386/i386-options.cc\nindex 4526dc09fc4..bf37c77589e 100644\n--- a/gcc/config/i386/i386-options.cc\n+++ b/gcc/config/i386/i386-options.cc\n@@ -231,7 +231,8 @@ static struct ix86_target_opts isa2_opts[] =\n { \"-mavxifma\",\tOPTION_MASK_ISA2_AVXIFMA },\n { \"-mavxvnniint8\",\tOPTION_MASK_ISA2_AVXVNNIINT8 },\n { \"-mavxneconvert\", OPTION_MASK_ISA2_AVXNECONVERT },\n- { \"-mcmpccxadd\", OPTION_MASK_ISA2_CMPCCXADD }\n+ { \"-mcmpccxadd\", OPTION_MASK_ISA2_CMPCCXADD },\n+ { \"-mamx-fp16\", OPTION_MASK_ISA2_AMX_FP16 }\n };\n static struct ix86_target_opts isa_opts[] =\n {\n@@ -1082,6 +1083,7 @@ ix86_valid_target_attribute_inner_p (tree fndecl, tree args, char *p_strings[],\n IX86_ATTR_ISA (\"avxvnniint8\", OPT_mavxvnniint8),\n IX86_ATTR_ISA (\"avxneconvert\", OPT_mavxneconvert),\n IX86_ATTR_ISA (\"cmpccxadd\", OPT_mcmpccxadd),\n+ IX86_ATTR_ISA (\"amx-fp16\", OPT_mamx_fp16),\n \n /* enum options */\n IX86_ATTR_ENUM (\"fpmath=\",\tOPT_mfpmath_),\ndiff --git a/gcc/config/i386/i386.opt b/gcc/config/i386/i386.opt\nindex c4a3bdcf960..eaa43946341 100644\n--- a/gcc/config/i386/i386.opt\n+++ b/gcc/config/i386/i386.opt\n@@ -1234,3 +1234,7 @@ mcmpccxadd\n Target Mask(ISA2_CMPCCXADD) Var(ix86_isa_flags2) Save\n Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, and\n CMPCCXADD build-in functions and code generation.\n+\n+mamx-fp16\n+Target Mask(ISA2_AMX_FP16) Var(ix86_isa_flags2) Save\n+Support AMX-FP16 built-in functions and code generation.\ndiff --git a/gcc/config/i386/immintrin.h b/gcc/config/i386/immintrin.h\nindex d7433f639c8..d8415863f52 100644\n--- a/gcc/config/i386/immintrin.h\n+++ b/gcc/config/i386/immintrin.h\n@@ -138,4 +138,6 @@\n \n #include \n \n+#include \n+\n #endif /* _IMMINTRIN_H_INCLUDED */\ndiff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi\nindex adee772f7bc..e51d7835e69 100644\n--- a/gcc/doc/extend.texi\n+++ b/gcc/doc/extend.texi\n@@ -7080,6 +7080,11 @@ Enable/disable the generation of the AVXNECONVERT instructions.\n @cindex @code{target(\"cmpccxadd\")} function attribute, x86\n Enable/disable the generation of the CMPccXADD instructions.\n \n+@item amx-fp16\n+@itemx no-amx-fp16\n+@cindex @code{target(\"amx-fp16\")} function attribute, x86\n+Enable/disable the generation of the AMX-FP16 instructions.\n+\n @item cld\n @itemx no-cld\n @cindex @code{target(\"cld\")} function attribute, x86\ndiff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi\nindex 962c6c177b6..1014e2ded99 100644\n--- a/gcc/doc/invoke.texi\n+++ b/gcc/doc/invoke.texi\n@@ -1436,7 +1436,7 @@ See RS/6000 and PowerPC Options.\n -mavx5124fmaps -mavx512vnni -mavx5124vnniw -mprfchw -mrdpid @gol\n -mrdseed -msgx -mavx512vp2intersect -mserialize -mtsxldtrk@gol\n -mamx-tile -mamx-int8 -mamx-bf16 -muintr -mhreset -mavxvnni@gol\n--mavx512fp16 -mavxifma -mavxvnniint8 -mavxneconvert -mcmpccxadd @gol\n+-mavx512fp16 -mavxifma -mavxvnniint8 -mavxneconvert -mcmpccxadd -mamx-fp16 @gol\n -mcldemote -mms-bitfields -mno-align-stringops -minline-all-stringops @gol\n -minline-stringops-dynamically -mstringop-strategy=@var{alg} @gol\n -mkl -mwidekl @gol\n@@ -32913,6 +32913,9 @@ preferred alignment to @option{-mpreferred-stack-boundary=2}.\n @need 200\n @itemx -mcmpccxadd\n @opindex mcmpccxadd\n+@need 200\n+@itemx -mamx-fp16\n+@opindex mamx-fp16\n These switches enable the use of instructions in the MMX, SSE,\n SSE2, SSE3, SSSE3, SSE4, SSE4A, SSE4.1, SSE4.2, AVX, AVX2, AVX512F, AVX512PF,\n AVX512ER, AVX512CD, AVX512VL, AVX512BW, AVX512DQ, AVX512IFMA, AVX512VBMI, SHA,\n@@ -32923,9 +32926,9 @@ XSAVEOPT, XSAVEC, XSAVES, RTM, HLE, TBM, MWAITX, CLZERO, PKU, AVX512VBMI2,\n GFNI, VAES, WAITPKG, VPCLMULQDQ, AVX512BITALG, MOVDIRI, MOVDIR64B, AVX512BF16,\n ENQCMD, AVX512VPOPCNTDQ, AVX5124FMAPS, AVX512VNNI, AVX5124VNNIW, SERIALIZE,\n UINTR, HRESET, AMXTILE, AMXINT8, AMXBF16, KL, WIDEKL, AVXVNNI, AVX512FP16,\n-AVXIFMA, AVXVNNIINT8, AVXNECONVERT, CMPCCXADD or CLDEMOTE extended instruction\n-sets. Each has a corresponding @option{-mno-} option to disable use of these\n-instructions.\n+AVXIFMA, AVXVNNIINT8, AVXNECONVERT, CMPCCXADD, AMX-FP16 or CLDEMOTE extended\n+instruction sets. Each has a corresponding @option{-mno-} option to disable\n+use of these instructions.\n \n These extensions are also available as built-in functions: see\n @ref{x86 Built-in Functions}, for details of the functions enabled and\ndiff --git a/gcc/doc/sourcebuild.texi b/gcc/doc/sourcebuild.texi\nindex 714595d33bf..5de5e9576d5 100644\n--- a/gcc/doc/sourcebuild.texi\n+++ b/gcc/doc/sourcebuild.texi\n@@ -2508,6 +2508,9 @@ Target supports the execution of @code{amx-int8} instructions.\n @item amx_bf16\n Target supports the execution of @code{amx-bf16} instructions.\n \n+@item amx_fp16\n+Target supports the execution of @code{amx-fp16} instructions.\n+\n @item cell_hw\n Test system can execute AltiVec and Cell PPU instructions.\n \ndiff --git a/gcc/testsuite/g++.dg/other/i386-2.C b/gcc/testsuite/g++.dg/other/i386-2.C\nindex f7dbbbbf619..79b84af0a75 100644\n--- a/gcc/testsuite/g++.dg/other/i386-2.C\n+++ b/gcc/testsuite/g++.dg/other/i386-2.C\n@@ -1,5 +1,5 @@\n /* { dg-do compile { target i?86-*-* x86_64-*-* } } */\n-/* { dg-options \"-O -pedantic-errors -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512dq -mavx512bw -mavx512vl -mavx512ifma -mavx512vbmi -mavx512vbmi2 -mavx5124fmaps -mavx5124vnniw -mavx512vpopcntdq -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mavx512bitalg -mpconfig -mwbnoinvd -mavx512bf16 -menqcmd -mavx512vp2intersect -mserialize -mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl -mavxvnni -mavx512fp16 -mavxifma -mavxvnniint8 -mavxneconvert -mcmpccxadd\" } */\n+/* { dg-options \"-O -pedantic-errors -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512dq -mavx512bw -mavx512vl -mavx512ifma -mavx512vbmi -mavx512vbmi2 -mavx5124fmaps -mavx5124vnniw -mavx512vpopcntdq -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mavx512bitalg -mpconfig -mwbnoinvd -mavx512bf16 -menqcmd -mavx512vp2intersect -mserialize -mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl -mavxvnni -mavx512fp16 -mavxifma -mavxvnniint8 -mavxneconvert -mcmpccxadd -mamx-fp16\" } */\n \n /* Test that {,x,e,p,t,s,w,a,b,i}mmintrin.h, mm3dnow.h, fma4intrin.h,\n xopintrin.h, abmintrin.h, bmiintrin.h, tbmintrin.h, lwpintrin.h,\ndiff --git a/gcc/testsuite/g++.dg/other/i386-3.C b/gcc/testsuite/g++.dg/other/i386-3.C\nindex 2ac5d9f2df5..c811a4454bf 100644\n--- a/gcc/testsuite/g++.dg/other/i386-3.C\n+++ b/gcc/testsuite/g++.dg/other/i386-3.C\n@@ -1,5 +1,5 @@\n /* { dg-do compile { target i?86-*-* x86_64-*-* } } */\n-/* { dg-options \"-O -fkeep-inline-functions -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512dq -mavx512bw -mavx512vl -mavx512ifma -mavx512vbmi -mavx512vbmi2 -mavx5124fmaps -mavx5124vnniw -mavx512vpopcntdq -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mavx512bitalg -mpconfig -mwbnoinvd -mavx512bf16 -menqcmd -mavx512vp2intersect -mserialize -mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl -mavxvnni -mavx512fp16 -mavxifma -mavxvnniint8 -mavxneconvert -mcmpccxadd\" } */\n+/* { dg-options \"-O -fkeep-inline-functions -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512dq -mavx512bw -mavx512vl -mavx512ifma -mavx512vbmi -mavx512vbmi2 -mavx5124fmaps -mavx5124vnniw -mavx512vpopcntdq -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mavx512bitalg -mpconfig -mwbnoinvd -mavx512bf16 -menqcmd -mavx512vp2intersect -mserialize -mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl -mavxvnni -mavx512fp16 -mavxifma -mavxvnniint8 -mavxneconvert -mcmpccxadd -mamx-fp16\" } */\n \n /* Test that {,x,e,p,t,s,w,a,b,i}mmintrin.h, mm3dnow.h, fma4intrin.h,\n xopintrin.h, abmintrin.h, bmiintrin.h, tbmintrin.h, lwpintrin.h,\ndiff --git a/gcc/testsuite/gcc.target/i386/amx-check.h b/gcc/testsuite/gcc.target/i386/amx-check.h\nindex 6fff5ff4631..27dd37bf993 100644\n--- a/gcc/testsuite/gcc.target/i386/amx-check.h\n+++ b/gcc/testsuite/gcc.target/i386/amx-check.h\n@@ -213,6 +213,9 @@ main ()\n #ifdef AMX_BF16\n && __builtin_cpu_supports (\"amx-bf16\")\n #endif\n+#ifdef AMX_FP16\n+ && __builtin_cpu_supports (\"amx-fp16\")\n+#endif\n #ifdef __linux__\n && request_perm_xtile_data ()\n #endif\ndiff --git a/gcc/testsuite/gcc.target/i386/amx-helper.h b/gcc/testsuite/gcc.target/i386/amx-helper.h\nnew file mode 100644\nindex 00000000000..fe24d7067a5\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/i386/amx-helper.h\n@@ -0,0 +1,61 @@\n+#ifndef AMX_HELPER_H_INCLUDED\n+#define AMX_HELPER_H_INCLUDED\n+#if defined(AMX_FP16)\n+#include \n+#include \n+#endif\n+#include \"amx-check.h\"\n+\n+typedef union\n+{\n+ _Float16 f16;\n+ uint16_t u;\n+} union16f_uw;\n+\n+#if defined(AMX_FP16)\n+/* Transformation functions between fp16/float */\n+static uint16_t make_f32_fp16 (float f)\n+{\n+ union16f_uw tmp;\n+ __m128 b = _mm_set_ss (f);\n+ __m128h a;\n+ tmp.f16 = _mm_cvtsh_h (_mm_cvtss_sh (a, b));\n+ return tmp.u;\n+}\n+\n+static float make_fp16_f32 (uint16_t fp)\n+{\n+ union16f_uw tmp;\n+ tmp.u = fp;\n+ __m128h b = _mm_set_sh (tmp.f16);\n+ __m128 a;\n+ return _mm_cvtss_f32 (_mm_cvtsh_ss (a, b));\n+}\n+\n+/* Init tile buffer with fp16 pairs */\n+void init_fp16_max_tile_buffer (uint8_t* buf)\n+{\n+ int i, j;\n+ uint16_t* ptr = (uint16_t *) buf;\n+\n+ for (i = 0; i < 16; i++)\n+ for (j = 0; j < 32; j++)\n+ {\n+ float f = 2.5f * i + 1.25f * j;\n+ ptr[i * 32 + j] = make_f32_fp16 (f);\n+ }\n+}\n+\n+/* Init tile fp16 pair buffer with zero */\n+void init_fp16_max_tile_zero_buffer (uint8_t* buf)\n+{\n+ int i, j;\n+ uint16_t* ptr = (uint16_t *) buf;\n+\n+ for (i = 0; i < 16; i++)\n+ for (j = 0; j < 32; j++)\n+ ptr[i * 32 + j] = make_f32_fp16 (0.0f);\n+}\n+#endif\n+\n+#endif\ndiff --git a/gcc/testsuite/gcc.target/i386/amxfp16-asmatt-1.c b/gcc/testsuite/gcc.target/i386/amxfp16-asmatt-1.c\nnew file mode 100644\nindex 00000000000..09ae6d408f1\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/i386/amxfp16-asmatt-1.c\n@@ -0,0 +1,13 @@\n+/* { dg-do compile { target { ! ia32 } } } */\n+/* { dg-options \"-O2 -mamx-fp16\" } */\n+/* { dg-final { scan-assembler \"tdpfp16ps\\[ \\\\t]+\\[^\\n\\]*%tmm3+\\[^\\n\\]*%tmm2+\\[^\\n\\]*%tmm1\" } } */\n+#include \n+\n+#define TMM1 1\n+#define TMM2 2\n+#define TMM3 3\n+\n+void TEST ()\n+{\n+ _tile_dpfp16ps (TMM1, TMM2, TMM3);\n+}\ndiff --git a/gcc/testsuite/gcc.target/i386/amxfp16-asmintel-1.c b/gcc/testsuite/gcc.target/i386/amxfp16-asmintel-1.c\nnew file mode 100644\nindex 00000000000..a8dff945f23\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/i386/amxfp16-asmintel-1.c\n@@ -0,0 +1,10 @@\n+/* { dg-do compile { target { ! ia32 } } } */\n+/* { dg-require-effective-target masm_intel } */\n+/* { dg-options \"-O2 -mamx-fp16 -masm=intel\" } */\n+/* { dg-final { scan-assembler \"tdpfp16ps\\[ \\\\t]+\\[^\\n\\]*%tmm1+\\[^\\n\\]*%tmm2+\\[^\\n\\]*%tmm3\" } } */\n+#include \n+\n+void TEST ()\n+{\n+ _tile_dpfp16ps (1, 2, 3);\n+}\ndiff --git a/gcc/testsuite/gcc.target/i386/amxfp16-dpfp16ps-2.c b/gcc/testsuite/gcc.target/i386/amxfp16-dpfp16ps-2.c\nnew file mode 100644\nindex 00000000000..2d359a689ea\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/i386/amxfp16-dpfp16ps-2.c\n@@ -0,0 +1,57 @@\n+/* { dg-do run { target { ! ia32 } } } */\n+/* { dg-require-effective-target amx_tile } */\n+/* { dg-require-effective-target amx_fp16 } */\n+/* { dg-require-effective-target avx512fp16 } */\n+/* { dg-options \"-O2 -mamx-tile -mamx-fp16 -mavx512fp16\" } */\n+#define AMX_FP16\n+#define DO_TEST test_amx_fp16_dpfp16ps\n+void test_amx_fp16_dpfp16ps ();\n+#include \"amx-helper.h\"\n+\n+void calc_matrix_dpfp16ps (__tile *dst, __tile *src1, __tile *src2)\n+{\n+ uint16_t *src1_buf = (uint16_t *)src1->buf;\n+ uint16_t *src2_buf = (uint16_t *)src2->buf;\n+ float *dst_buf = (float *)dst->buf;\n+ \n+ int M = src1->rows;\n+ int N = src1->colsb / 4;\n+ int K = src2->colsb / 4;\n+ int i, j, k, t;\n+\n+ for (i = 0; i < M; i++)\n+ for (j = 0; j < N; j++)\n+ for (k = 0; k < K; k++)\n+\tfor (t = 0; t < 2; t+=2)\n+\t { \n+\t dst_buf[i * K + k] += \n+\t (make_fp16_f32 (src1_buf[i * 2 * N + 2 * j + t]) *\n+\t make_fp16_f32 (src2_buf[j * 2 * K + 2 * k + t])) +\n+\t (make_fp16_f32 (src1_buf[i * 2 * N + 2 * j + t + 1]) *\n+\t make_fp16_f32 (src2_buf[j * 2 * K + 2 * k + t + 1]));\n+\t }\n+\n+}\n+\n+void test_amx_fp16_dpfp16ps ()\n+{\n+ __tilecfg_u cfg;\n+ __tile dst, dst_ref, src1, src2;\n+ uint8_t tmp_dst_buf[1024], tmp_dst_zero_buf[1024];\n+\n+ init_fp16_max_tile_buffer (tmp_dst_buf);\n+ init_fp16_max_tile_zero_buffer (tmp_dst_zero_buf);\n+\n+ init_tile_config (&cfg);\n+ init_tile_reg_and_src_with_buffer (1, dst, tmp_dst_zero_buf);\n+ init_tile_reg_and_src_with_buffer (2, src1, tmp_dst_buf);\n+ init_tile_reg_and_src_with_buffer (3, src2, tmp_dst_buf);\n+\n+ calc_matrix_dpfp16ps (&dst, &src1, &src2);\n+ \n+ _tile_dpfp16ps (1, 2, 3);\n+ _tile_stored (1, dst_ref.buf, _STRIDE);\n+\n+ if (!check_float_tile_register (&dst_ref, &dst))\n+ abort ();\n+}\ndiff --git a/gcc/testsuite/gcc.target/i386/funcspec-56.inc b/gcc/testsuite/gcc.target/i386/funcspec-56.inc\nindex f7e9c243597..ef9d4c5f5a4 100644\n--- a/gcc/testsuite/gcc.target/i386/funcspec-56.inc\n+++ b/gcc/testsuite/gcc.target/i386/funcspec-56.inc\n@@ -84,6 +84,7 @@ extern void test_avxifma (void)\t\t\t__attribute__((__target__(\"avxifma\")));\n extern void test_avxvnniint8 (void)\t\t__attribute__((__target__(\"avxvnniint8\")));\n extern void test_avxneconvert (void)\t\t__attribute__((__target__(\"avxneconvert\")));\n extern void test_cmpccxadd (void)\t\t__attribute__((__target__(\"cmpccxadd\")));\n+extern void test_amx_fp16 (void)\t\t__attribute__((__target__(\"amx-fp16\")));\n \n extern void test_no_sgx (void)\t\t\t__attribute__((__target__(\"no-sgx\")));\n extern void test_no_avx5124fmaps(void)\t\t__attribute__((__target__(\"no-avx5124fmaps\")));\n@@ -169,6 +170,7 @@ extern void test_no_avxifma (void)\t\t__attribute__((__target__(\"no-avxifma\")));\n extern void test_no_avxvnniint8 (void)\t\t__attribute__((__target__(\"no-avxvnniint8\")));\n extern void test_no_avxneconvert (void)\t\t__attribute__((__target__(\"no-avxneconvert\")));\n extern void test_no_cmpccxadd (void) __attribute__((__target__(\"no-cmpccxadd\")));\n+extern void test_no_amx_fp16 (void)\t\t__attribute__((__target__(\"no-amx-fp16\")));\n \n extern void test_arch_nocona (void)\t\t__attribute__((__target__(\"arch=nocona\")));\n extern void test_arch_core2 (void)\t\t__attribute__((__target__(\"arch=core2\")));\ndiff --git a/gcc/testsuite/gcc.target/i386/sse-12.c b/gcc/testsuite/gcc.target/i386/sse-12.c\nindex 3eabc49a6ab..df2684abbb6 100644\n--- a/gcc/testsuite/gcc.target/i386/sse-12.c\n+++ b/gcc/testsuite/gcc.target/i386/sse-12.c\n@@ -3,7 +3,7 @@\n popcntintrin.h gfniintrin.h and mm_malloc.h are usable\n with -O -std=c89 -pedantic-errors. */\n /* { dg-do compile } */\n-/* { dg-options \"-O -std=c89 -pedantic-errors -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512bw -mavx512dq -mavx512vl -mavx512vbmi -mavx512vbmi2 -mavx512ifma -mavx5124fmaps -mavx5124vnniw -mavx512vpopcntdq -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mavx512bitalg -mpconfig -mwbnoinvd -mavx512bf16 -menqcmd -mavx512vp2intersect -mserialize -mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl -mavxvnni -mavxifma -mavxvnniint8 -mavxneconvert\" } */\n+/* { dg-options \"-O -std=c89 -pedantic-errors -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512bw -mavx512dq -mavx512vl -mavx512vbmi -mavx512vbmi2 -mavx512ifma -mavx5124fmaps -mavx5124vnniw -mavx512vpopcntdq -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mavx512bitalg -mpconfig -mwbnoinvd -mavx512bf16 -menqcmd -mavx512vp2intersect -mserialize -mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl -mavxvnni -mavxifma -mavxvnniint8 -mavxneconvert -mamx-fp16\" } */\n \n #include \n \ndiff --git a/gcc/testsuite/gcc.target/i386/sse-13.c b/gcc/testsuite/gcc.target/i386/sse-13.c\nindex e947b4347f4..ca662f7bd47 100644\n--- a/gcc/testsuite/gcc.target/i386/sse-13.c\n+++ b/gcc/testsuite/gcc.target/i386/sse-13.c\n@@ -1,5 +1,5 @@\n /* { dg-do compile } */\n-/* { dg-options \"-O2 -Werror-implicit-function-declaration -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512vl -mavx512dq -mavx512bw -mavx512vbmi -mavx512vbmi2 -mavx512ifma -mavx5124fmaps -mavx5124vnniw -mavx512vpopcntdq -mavx512vp2intersect -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mavx512bitalg -mpconfig -mwbnoinvd -mavx512bf16 -menqcmd -mserialize -mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl -mavxvnni -mavx512fp16 -mavxifma -mavxvnniint8 -mavxneconvert -mcmpccxadd\" } */\n+/* { dg-options \"-O2 -Werror-implicit-function-declaration -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512vl -mavx512dq -mavx512bw -mavx512vbmi -mavx512vbmi2 -mavx512ifma -mavx5124fmaps -mavx5124vnniw -mavx512vpopcntdq -mavx512vp2intersect -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mavx512bitalg -mpconfig -mwbnoinvd -mavx512bf16 -menqcmd -mserialize -mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl -mavxvnni -mavx512fp16 -mavxifma -mavxvnniint8 -mavxneconvert -mcmpccxadd -mamx-fp16\" } */\n /* { dg-add-options bind_pic_locally } */\n \n #include \ndiff --git a/gcc/testsuite/gcc.target/i386/sse-14.c b/gcc/testsuite/gcc.target/i386/sse-14.c\nindex b6ee3806dcc..4a47d4093a2 100644\n--- a/gcc/testsuite/gcc.target/i386/sse-14.c\n+++ b/gcc/testsuite/gcc.target/i386/sse-14.c\n@@ -1,5 +1,5 @@\n /* { dg-do compile } */\n-/* { dg-options \"-O0 -Werror-implicit-function-declaration -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512dq -mavx512bw -mavx512vl -mavx512ifma -mavx512vbmi -mavx512vbmi2 -mavx5124fmaps -mavx5124vnniw -mavx512vpopcntdq -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mpconfig -mwbnoinvd -mavx512vl -mavx512bf16 -menqcmd -mavx512vp2intersect -mserialize -mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl -mavxvnni -mavx512fp16 -mavxifma -mavxvnniint8 -mavxneconvert\" } */\n+/* { dg-options \"-O0 -Werror-implicit-function-declaration -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512dq -mavx512bw -mavx512vl -mavx512ifma -mavx512vbmi -mavx512vbmi2 -mavx5124fmaps -mavx5124vnniw -mavx512vpopcntdq -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mpconfig -mwbnoinvd -mavx512vl -mavx512bf16 -menqcmd -mavx512vp2intersect -mserialize -mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl -mavxvnni -mavx512fp16 -mavxifma -mavxvnniint8 -mavxneconvert -mamx-fp16\" } */\n /* { dg-add-options bind_pic_locally } */\n \n #include \ndiff --git a/gcc/testsuite/gcc.target/i386/sse-22.c b/gcc/testsuite/gcc.target/i386/sse-22.c\nindex 71ac0f3da19..178a2fce492 100644\n--- a/gcc/testsuite/gcc.target/i386/sse-22.c\n+++ b/gcc/testsuite/gcc.target/i386/sse-22.c\n@@ -103,7 +103,7 @@\n \n \n #ifndef DIFFERENT_PRAGMAS\n-#pragma GCC target (\"sse4a,3dnow,avx,avx2,fma4,xop,aes,pclmul,popcnt,abm,lzcnt,bmi,bmi2,tbm,lwp,fsgsbase,rdrnd,f16c,rtm,rdseed,prfchw,adx,fxsr,xsaveopt,avx512f,avx512er,avx512cd,avx512pf,sha,prefetchwt1,avx512vl,avx512bw,avx512dq,avx512vbmi,avx512vbmi2,avx512ifma,avx5124fmaps,avx5124vnniw,avx512vpopcntdq,gfni,avx512bitalg,avx512bf16,avx512vp2intersect,serialize,tsxldtrk,amx-tile,amx-int8,amx-bf16,kl,widekl,avxvnni,avx512fp16,avxifma,avxvnniint8,avxneconvert\")\n+#pragma GCC target (\"sse4a,3dnow,avx,avx2,fma4,xop,aes,pclmul,popcnt,abm,lzcnt,bmi,bmi2,tbm,lwp,fsgsbase,rdrnd,f16c,rtm,rdseed,prfchw,adx,fxsr,xsaveopt,avx512f,avx512er,avx512cd,avx512pf,sha,prefetchwt1,avx512vl,avx512bw,avx512dq,avx512vbmi,avx512vbmi2,avx512ifma,avx5124fmaps,avx5124vnniw,avx512vpopcntdq,gfni,avx512bitalg,avx512bf16,avx512vp2intersect,serialize,tsxldtrk,amx-tile,amx-int8,amx-bf16,kl,widekl,avxvnni,avx512fp16,avxifma,avxvnniint8,avxneconvert,amx-fp16\")\n #endif\n \n /* Following intrinsics require immediate arguments. They\n@@ -220,7 +220,7 @@ test_4 (_mm_cmpestrz, int, __m128i, int, __m128i, int, 1)\n \n /* immintrin.h (AVX/AVX2/RDRND/FSGSBASE/F16C/RTM/AVX512F/SHA) */\n #ifdef DIFFERENT_PRAGMAS\n-#pragma GCC target (\"avx,avx2,rdrnd,fsgsbase,f16c,rtm,avx512f,avx512er,avx512cd,avx512pf,sha,avx512vl,avx512bw,avx512dq,avx512ifma,avx512vbmi,avx512vbmi2,avx5124fmaps,avx5124vnniw,avx512vpopcntdq,gfni,avx512bitalg,avx512bf16,avx512vp2intersect,serialize,tsxldtrk,amx-tile,amx-int8,amx-bf16,kl,widekl,avxvnni,avx512fp16,avxifma,avxvnniint8,avxneconvert\")\n+#pragma GCC target (\"avx,avx2,rdrnd,fsgsbase,f16c,rtm,avx512f,avx512er,avx512cd,avx512pf,sha,avx512vl,avx512bw,avx512dq,avx512ifma,avx512vbmi,avx512vbmi2,avx5124fmaps,avx5124vnniw,avx512vpopcntdq,gfni,avx512bitalg,avx512bf16,avx512vp2intersect,serialize,tsxldtrk,amx-tile,amx-int8,amx-bf16,kl,widekl,avxvnni,avx512fp16,avxifma,avxvnniint8,avxneconvert,amx-fp16\")\n #endif\n #include \n test_1 (_cvtss_sh, unsigned short, float, 1)\ndiff --git a/gcc/testsuite/gcc.target/i386/sse-23.c b/gcc/testsuite/gcc.target/i386/sse-23.c\nindex 757ba9c9a7d..ba1310f9f89 100644\n--- a/gcc/testsuite/gcc.target/i386/sse-23.c\n+++ b/gcc/testsuite/gcc.target/i386/sse-23.c\n@@ -847,6 +847,6 @@\n #define __builtin_ia32_cmpccxadd(A, B, C, D) __builtin_ia32_cmpccxadd(A, B, C, 1)\n #define __builtin_ia32_cmpccxadd64(A, B, C, D) __builtin_ia32_cmpccxadd64(A, B, C, 1)\n \n-#pragma GCC target (\"sse4a,3dnow,avx,avx2,fma4,xop,aes,pclmul,popcnt,abm,lzcnt,bmi,bmi2,tbm,lwp,fsgsbase,rdrnd,f16c,fma,rtm,rdseed,prfchw,adx,fxsr,xsaveopt,avx512f,avx512er,avx512cd,avx512pf,sha,prefetchwt1,xsavec,xsaves,clflushopt,avx512bw,avx512dq,avx512vl,avx512vbmi,avx512ifma,avx5124fmaps,avx5124vnniw,avx512vpopcntdq,clwb,mwaitx,clzero,pku,sgx,rdpid,gfni,avx512vbmi2,vpclmulqdq,avx512bitalg,pconfig,wbnoinvd,avx512bf16,enqcmd,avx512vp2intersect,serialize,tsxldtrk,amx-tile,amx-int8,amx-bf16,kl,widekl,avxvnni,avx512fp16,avxifma,avxvnniint8,avxneconvert,cmpccxadd\")\n+#pragma GCC target (\"sse4a,3dnow,avx,avx2,fma4,xop,aes,pclmul,popcnt,abm,lzcnt,bmi,bmi2,tbm,lwp,fsgsbase,rdrnd,f16c,fma,rtm,rdseed,prfchw,adx,fxsr,xsaveopt,avx512f,avx512er,avx512cd,avx512pf,sha,prefetchwt1,xsavec,xsaves,clflushopt,avx512bw,avx512dq,avx512vl,avx512vbmi,avx512ifma,avx5124fmaps,avx5124vnniw,avx512vpopcntdq,clwb,mwaitx,clzero,pku,sgx,rdpid,gfni,avx512vbmi2,vpclmulqdq,avx512bitalg,pconfig,wbnoinvd,avx512bf16,enqcmd,avx512vp2intersect,serialize,tsxldtrk,amx-tile,amx-int8,amx-bf16,kl,widekl,avxvnni,avx512fp16,avxifma,avxvnniint8,avxneconvert,cmpccxadd,amx-fp16\")\n \n #include \ndiff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp\nindex d3b9aafb8f0..c70b6a21642 100644\n--- a/gcc/testsuite/lib/target-supports.exp\n+++ b/gcc/testsuite/lib/target-supports.exp\n@@ -10103,6 +10103,17 @@ proc check_effective_target_amx_bf16 { } {\n } \"-mamx-bf16\" ]\n }\n \n+# Return 1 if amx-fp16 instructions can be compiled.\n+proc check_effective_target_amx_fp16 { } {\n+ return [check_no_compiler_messages amx_fp16 object {\n+\tvoid\n+\tfoo ()\n+\t{\n+\t __asm__ volatile (\"tdpfp16ps\\t%%tmm1, %%tmm2, %%tmm3\" ::);\n+\t}\n+ } \"-mamx-fp16\" ]\n+}\n+\n # Return 1 if vpclmulq 100 45364 100 45214 100 150 833k 2830 --:--:-- --:--:-- --:--:-- 835k dq instructions can be compiled.\n proc check_effective_target_vpclmulqdq { } {\n return [check_no_compiler_messages vpclmulqdq object {\n","prefixes":[]}+ exit 1 Build step 'Execute shell' marked build as failure Finished: FAILURE