Started by user snail Running as SYSTEM [EnvInject] - Loading node environment variables. Building remotely on docker-jenkins-agent in workspace /home/jenkins/agent/workspace/binutils-gdb [WS-CLEANUP] Deleting project workspace... [WS-CLEANUP] Deferred wipeout is used... [WS-CLEANUP] Done The recommended git tool is: NONE using credential 0adb5fc7-caa2-429d-97d2-c7fa2fa1d884 Cloning the remote Git repository Using shallow clone with depth 1 Avoid fetching tags Cloning repository git@github.com:plctlab/patchwork-binutils-gdb.git > git init /home/jenkins/agent/workspace/binutils-gdb # timeout=10 Fetching upstream changes from git@github.com:plctlab/patchwork-binutils-gdb.git > git --version # timeout=10 > git --version # 'git version 2.37.2' using GIT_SSH to set credentials patchwork github wangliu-iscas git ssh key Verifying host key using known hosts file, will automatically accept unseen keys > git fetch --no-tags --force --progress --depth=1 -- git@github.com:plctlab/patchwork-binutils-gdb.git +refs/heads/*:refs/remotes/origin/* # timeout=10 > git config remote.origin.url git@github.com:plctlab/patchwork-binutils-gdb.git # timeout=10 > git config --add remote.origin.fetch +refs/heads/*:refs/remotes/origin/* # timeout=10 Avoid second fetch > git rev-parse refs/remotes/origin/master^{commit} # timeout=10 Checking out Revision f3f7ecc942f3844559142b933aa40b5ef75e3d5e (refs/remotes/origin/master) > git config core.sparsecheckout # timeout=10 > git checkout -f f3f7ecc942f3844559142b933aa40b5ef75e3d5e # timeout=10 Commit message: "gdb/arm: Fix obvious typo in b0b23e06c3a" > git rev-list --no-walk b2059307d86cf02ddd0f81b6d53306a685a9b3b4 # timeout=10 First time build. Skipping changelog. [EnvInject] - Mask passwords that will be passed as build parameters. [EnvInject] - Executing scripts and injecting environment variables after the SCM step. [EnvInject] - Injecting as environment variables the properties content GITHUB_REPO=https://github.com/plctlab/patchwork-binutils-gdb PATCHWORK_URL=https://patchwork.plctlab.org [EnvInject] - Variables injected successfully. [binutils-gdb] $ /usr/bin/env bash /tmp/jenkins18048627011076444890.sh + git config pw.server https://patchwork.plctlab.org/api/1.2/ + git config pw.project binutils-gdb + git config pw.token [*******] ++ date +%Y-%m + now_date=2022-11 ++ date +%Y + now_date_year=2022 + bundle_name=binutils-gdb_2022-11 ++ curl -s -H 'Authorization: Token [*******]' 'https://patchwork.plctlab.org/api/1.2/bundles/?project=binutils-gdb&per_page=999' + bundle_response='[{"id":6,"url":"https://patchwork.plctlab.org/api/1.2/bundles/6/","web_url":"https://patchwork.plctlab.org/bundle/patchwork-bot/binutils-gdb_2022-10/","project":{"id":2,"url":"https://patchwork.plctlab.org/api/1.2/projects/2/","name":"binutils-gdb","link_name":"binutils-gdb","list_id":"binutils.sourceware.org","list_email":"binutils@sourceware.org","web_url":"https://github.com/wangliu-iscas/Patchwork-Bundles/blob/main/binutils-gdb.md","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"name":"binutils-gdb_2022-10","owner":{"id":3,"url":"https://patchwork.plctlab.org/api/1.2/users/3/","username":"patchwork-bot","first_name":"","last_name":"","email":"ouuuleilei@gmail.com"},"patches":[{"id":1592,"url":"https://patchwork.plctlab.org/api/1.2/patches/1592/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/385d01fd-7e57-1f3f-1bae-30aa0c313d63@suse.com/","msgid":"<385d01fd-7e57-1f3f-1bae-30aa0c313d63@suse.com>","list_archive_url":null,"date":"2022-09-30T11:59:45","name":"[3/4] RISC-V/gas: don'\''t open-code insn_length()","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/385d01fd-7e57-1f3f-1bae-30aa0c313d63@suse.com/mbox/"},{"id":1594,"url":"https://patchwork.plctlab.org/api/1.2/patches/1594/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f5757acf-7b90-a0e3-5eea-3b97cc226930@suse.com/","msgid":"","list_archive_url":null,"date":"2022-09-30T12:00:12","name":"[4/4] RISC-V/gas: allow generating up to 176-bit instructions with .insn","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f5757acf-7b90-a0e3-5eea-3b97cc226930@suse.com/mbox/"},{"id":1596,"url":"https://patchwork.plctlab.org/api/1.2/patches/1596/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930140503.38233-1-chigot@adacore.com/","msgid":"<20220930140503.38233-1-chigot@adacore.com>","list_archive_url":null,"date":"2022-09-30T14:05:03","name":"ld/testsuite: consistently add board_ldflags when linking with GCC","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930140503.38233-1-chigot@adacore.com/mbox/"},{"id":1619,"url":"https://patchwork.plctlab.org/api/1.2/patches/1619/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221001014451.532772-1-maskray@google.com/","msgid":"<20221001014451.532772-1-maskray@google.com>","list_archive_url":null,"date":"2022-10-01T01:44:51","name":"gold, dwp: support zstd compressed input debug sections [PR 29641]","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221001014451.532772-1-maskray@google.com/mbox/"},{"id":1620,"url":"https://patchwork.plctlab.org/api/1.2/patches/1620/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221001023846.590825-1-maskray@google.com/","msgid":"<20221001023846.590825-1-maskray@google.com>","list_archive_url":null,"date":"2022-10-01T02:38:46","name":"gold: add --compress-debug-sections=zstd [PR 29641]","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221001023846.590825-1-maskray@google.com/mbox/"},{"id":1623,"url":"https://patchwork.plctlab.org/api/1.2/patches/1623/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b4477c7f666bdeb7f8e998633c7b0cb62310b9ef.1664599545.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-01T04:45:52","name":"[RFC,1/1] RISC-V: Implement common register pair framework","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b4477c7f666bdeb7f8e998633c7b0cb62310b9ef.1664599545.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1625,"url":"https://patchwork.plctlab.org/api/1.2/patches/1625/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/53a265a1f14d17a6f7b106082f610994c5d546e0.1664602025.git.research_trasio@irq.a4lg.com/","msgid":"<53a265a1f14d17a6f7b106082f610994c5d546e0.1664602025.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-01T05:27:31","name":"[RFC,1/1] RISC-V: Implement extension variants","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/53a265a1f14d17a6f7b106082f610994c5d546e0.1664602025.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1626,"url":"https://patchwork.plctlab.org/api/1.2/patches/1626/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8db04962aba9c780f133840a8934353a58f223fe.1664602716.git.research_trasio@irq.a4lg.com/","msgid":"<8db04962aba9c780f133840a8934353a58f223fe.1664602716.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-01T05:39:26","name":"[1/1] RISC-V: Move supervisor instructions after all unprivileged ones","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8db04962aba9c780f133840a8934353a58f223fe.1664602716.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1627,"url":"https://patchwork.plctlab.org/api/1.2/patches/1627/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221001062057.681440-1-maskray@google.com/","msgid":"<20221001062057.681440-1-maskray@google.com>","list_archive_url":null,"date":"2022-10-01T06:20:57","name":"readelf: support zstd compressed debug sections [PR 29640]","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221001062057.681440-1-maskray@google.com/mbox/"},{"id":1631,"url":"https://patchwork.plctlab.org/api/1.2/patches/1631/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/619f112539c0bdecd58e25664f1250a3479a37f5.1664707612.git.aburgess@redhat.com/","msgid":"<619f112539c0bdecd58e25664f1250a3479a37f5.1664707612.git.aburgess@redhat.com>","list_archive_url":null,"date":"2022-10-02T10:47:52","name":"[PATCHv2,2/2] opcodes/arm: add disassembler styling for arm","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/619f112539c0bdecd58e25664f1250a3479a37f5.1664707612.git.aburgess@redhat.com/mbox/"},{"id":1635,"url":"https://patchwork.plctlab.org/api/1.2/patches/1635/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221002185433.gl7dvytfh5wthifx@lug-owl.de/","msgid":"<20221002185433.gl7dvytfh5wthifx@lug-owl.de>","list_archive_url":null,"date":"2022-10-02T18:54:33","name":"diagnostics.h: GCC 13 got -Wself-move, breaks GDB build","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221002185433.gl7dvytfh5wthifx@lug-owl.de/mbox/"},{"id":1637,"url":"https://patchwork.plctlab.org/api/1.2/patches/1637/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003014313.28766-1-mark@harmstone.com/","msgid":"<20221003014313.28766-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-03T01:43:12","name":"[1/2] ld: Add --pdb option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003014313.28766-1-mark@harmstone.com/mbox/"},{"id":1638,"url":"https://patchwork.plctlab.org/api/1.2/patches/1638/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003014313.28766-2-mark@harmstone.com/","msgid":"<20221003014313.28766-2-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-03T01:43:13","name":"[2/2] ld: Add minimal pdb generation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003014313.28766-2-mark@harmstone.com/mbox/"},{"id":1640,"url":"https://patchwork.plctlab.org/api/1.2/patches/1640/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/597ed978-d121-220c-b56b-2ffb94bd091c@suse.cz/","msgid":"<597ed978-d121-220c-b56b-2ffb94bd091c@suse.cz>","list_archive_url":null,"date":"2022-10-03T07:50:38","name":"[1/2] refactor usage of compressed_debug_section_type","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/597ed978-d121-220c-b56b-2ffb94bd091c@suse.cz/mbox/"},{"id":1641,"url":"https://patchwork.plctlab.org/api/1.2/patches/1641/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b8acdd83-f33a-74b8-e21a-23719a0b1a60@suse.cz/","msgid":"","list_archive_url":null,"date":"2022-10-03T07:50:44","name":"[2/2] add --enable-default-compressed-debug-sections-algorithm configure option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b8acdd83-f33a-74b8-e21a-23719a0b1a60@suse.cz/mbox/"},{"id":1642,"url":"https://patchwork.plctlab.org/api/1.2/patches/1642/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003101328.1790113-1-aburgess@redhat.com/","msgid":"<20221003101328.1790113-1-aburgess@redhat.com>","list_archive_url":null,"date":"2022-10-03T10:13:28","name":"opcodes/riscv: style csr names as registers","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003101328.1790113-1-aburgess@redhat.com/mbox/"},{"id":1643,"url":"https://patchwork.plctlab.org/api/1.2/patches/1643/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7ba14fc4472ce97d4f7a4433cad8a571e89f82f4.1664793840.git.research_trasio@irq.a4lg.com/","msgid":"<7ba14fc4472ce97d4f7a4433cad8a571e89f82f4.1664793840.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-03T10:43:59","name":"[v3,1/6] RISC-V: Fix immediates to have \"immediate\" style","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7ba14fc4472ce97d4f7a4433cad8a571e89f82f4.1664793840.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1644,"url":"https://patchwork.plctlab.org/api/1.2/patches/1644/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a498bec37c1fd1dcda57cbf95e5f8cfba09b31d3.1664793840.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-03T10:44:00","name":"[v3,2/6] RISC-V: Fix printf argument types corresponding %x","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a498bec37c1fd1dcda57cbf95e5f8cfba09b31d3.1664793840.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1647,"url":"https://patchwork.plctlab.org/api/1.2/patches/1647/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0002ea716713ace4998a33dde0b81f4f890d10bf.1664793840.git.research_trasio@irq.a4lg.com/","msgid":"<0002ea716713ace4998a33dde0b81f4f890d10bf.1664793840.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-03T10:44:01","name":"[v3,3/6] RISC-V: Optimize riscv_disassemble_data printf","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0002ea716713ace4998a33dde0b81f4f890d10bf.1664793840.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1646,"url":"https://patchwork.plctlab.org/api/1.2/patches/1646/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c65fc3e9aa58965d6768a28c9fd7467fea9897a5.1664793840.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-03T10:44:02","name":"[v3,4/6] RISC-V: Print comma and tabs as the \"text\" style","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c65fc3e9aa58965d6768a28c9fd7467fea9897a5.1664793840.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1648,"url":"https://patchwork.plctlab.org/api/1.2/patches/1648/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5abe1d8a7694417b990e11d8f6cd6789573872e5.1664793840.git.research_trasio@irq.a4lg.com/","msgid":"<5abe1d8a7694417b990e11d8f6cd6789573872e5.1664793840.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-03T10:44:03","name":"[v3,5/6] RISC-V: Fix T-Head immediate types on printing","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5abe1d8a7694417b990e11d8f6cd6789573872e5.1664793840.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1649,"url":"https://patchwork.plctlab.org/api/1.2/patches/1649/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0b68af932117258c908db62cf87c3a15d3cdec41.1664793840.git.research_trasio@irq.a4lg.com/","msgid":"<0b68af932117258c908db62cf87c3a15d3cdec41.1664793840.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-03T10:44:04","name":"[v3,6/6] RISC-V: Print XTheadMemPair literal as \"immediate\"","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0b68af932117258c908db62cf87c3a15d3cdec41.1664793840.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1656,"url":"https://patchwork.plctlab.org/api/1.2/patches/1656/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/87lepxcd6x.fsf@redhat.com/","msgid":"<87lepxcd6x.fsf@redhat.com>","list_archive_url":null,"date":"2022-10-03T12:19:02","name":"Commit: readelf: Do not load section data from offset 0","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/87lepxcd6x.fsf@redhat.com/mbox/"},{"id":1659,"url":"https://patchwork.plctlab.org/api/1.2/patches/1659/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e0d369d419da9c0441f415da7f54352aead8f655.1664707612.git.aburgess@redhat.com/","msgid":"","list_archive_url":null,"date":"2022-10-03T16:37:36","name":"[PATCHv2,1/2] opcodes/arm: use '\''@'\'' consistently for the comment character","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e0d369d419da9c0441f415da7f54352aead8f655.1664707612.git.aburgess@redhat.com/mbox/"},{"id":1660,"url":"https://patchwork.plctlab.org/api/1.2/patches/1660/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003165848.11142-1-palmer@rivosinc.com/","msgid":"<20221003165848.11142-1-palmer@rivosinc.com>","list_archive_url":null,"date":"2022-10-03T16:58:48","name":"gas: NEWS: Mention the T-Head extensions that were recently added","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003165848.11142-1-palmer@rivosinc.com/mbox/"},{"id":1671,"url":"https://patchwork.plctlab.org/api/1.2/patches/1671/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/YzvrMEdkXjIn5Lfz@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-04T08:13:36","name":"Support objcopy changing compression to or from zstd","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/YzvrMEdkXjIn5Lfz@squeak.grove.modra.org/mbox/"},{"id":1673,"url":"https://patchwork.plctlab.org/api/1.2/patches/1673/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0bc857d306bb7c8130e5328dbe6b9ed2fed3ef87.1664873933.git.research_trasio@irq.a4lg.com/","msgid":"<0bc857d306bb7c8130e5328dbe6b9ed2fed3ef87.1664873933.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-04T08:59:07","name":"[1/2] RISC-V: Fix buffer overflow on print_insn_riscv","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0bc857d306bb7c8130e5328dbe6b9ed2fed3ef87.1664873933.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1672,"url":"https://patchwork.plctlab.org/api/1.2/patches/1672/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/89612fe01d902007bf84a7dfb0df5f85d5c166e4.1664873933.git.research_trasio@irq.a4lg.com/","msgid":"<89612fe01d902007bf84a7dfb0df5f85d5c166e4.1664873933.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-04T08:59:08","name":"[2/2] gdb/riscv: Fix buffer overflow on riscv_insn::fetch_instruction","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/89612fe01d902007bf84a7dfb0df5f85d5c166e4.1664873933.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1676,"url":"https://patchwork.plctlab.org/api/1.2/patches/1676/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fc849c94f4adcac1c4ccc5508c7a145a2f13b2a9.1664876744.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-04T09:45:49","name":"[v2,1/2] RISC-V: Fix buffer overflow on print_insn_riscv","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fc849c94f4adcac1c4ccc5508c7a145a2f13b2a9.1664876744.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1677,"url":"https://patchwork.plctlab.org/api/1.2/patches/1677/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4eb6e59ae2e790dbbf2bc92477edd281648d8814.1664876744.git.research_trasio@irq.a4lg.com/","msgid":"<4eb6e59ae2e790dbbf2bc92477edd281648d8814.1664876744.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-04T09:45:50","name":"[v2,2/2] gdb/riscv: Partial support for instructions up to 176-bits","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4eb6e59ae2e790dbbf2bc92477edd281648d8814.1664876744.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1678,"url":"https://patchwork.plctlab.org/api/1.2/patches/1678/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ebf16f9e1f45115d0793952ccb4a94d4233303f9.1664882725.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-04T11:25:56","name":"[v3,1/2] RISC-V: Fix buffer overflow on print_insn_riscv","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ebf16f9e1f45115d0793952ccb4a94d4233303f9.1664882725.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1679,"url":"https://patchwork.plctlab.org/api/1.2/patches/1679/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/83464b09b8649525259c69c853dfa2c9575a204b.1664882725.git.research_trasio@irq.a4lg.com/","msgid":"<83464b09b8649525259c69c853dfa2c9575a204b.1664882725.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-04T11:25:57","name":"[v3,2/2] gdb/riscv: Partial support for instructions up to 176-bit","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/83464b09b8649525259c69c853dfa2c9575a204b.1664882725.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1681,"url":"https://patchwork.plctlab.org/api/1.2/patches/1681/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ffa9c1d7-e8c2-a62b-ef3e-b565c0ffbe5b@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-04T13:56:27","name":"RISC-V: Zicbo{m,p,z} adjustments to riscv_multi_subset_supports_ext()","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ffa9c1d7-e8c2-a62b-ef3e-b565c0ffbe5b@suse.com/mbox/"},{"id":1690,"url":"https://patchwork.plctlab.org/api/1.2/patches/1690/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221004161720.1963953-1-vladimir.mezentsev@oracle.com/","msgid":"<20221004161720.1963953-1-vladimir.mezentsev@oracle.com>","list_archive_url":null,"date":"2022-10-04T16:17:20","name":"gprofng: fix build with --enable-pgo-build=lto","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221004161720.1963953-1-vladimir.mezentsev@oracle.com/mbox/"},{"id":1691,"url":"https://patchwork.plctlab.org/api/1.2/patches/1691/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c0211bc9c57be6c79c6d878ce147f63b657f461d.camel@espressif.com/","msgid":"","list_archive_url":null,"date":"2022-10-04T16:22:05","name":"bfd: xtensa: fix __stop_SECTION literal drop,","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c0211bc9c57be6c79c6d878ce147f63b657f461d.camel@espressif.com/mbox/"},{"id":1702,"url":"https://patchwork.plctlab.org/api/1.2/patches/1702/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5f482299-6c60-b2b3-9abe-f4a55a5a26c5@univ-grenoble-alpes.fr/","msgid":"<5f482299-6c60-b2b3-9abe-f4a55a5a26c5@univ-grenoble-alpes.fr>","list_archive_url":null,"date":"2022-10-04T20:03:20","name":"[RFC] bfd: use bfd_vma for the 64-bit version of put[lb] and get[lb]","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5f482299-6c60-b2b3-9abe-f4a55a5a26c5@univ-grenoble-alpes.fr/mbox/"},{"id":1711,"url":"https://patchwork.plctlab.org/api/1.2/patches/1711/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Yz0Gsxdxe0TePbJT@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-05T04:23:15","name":"PR29647, objdump -S looping","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Yz0Gsxdxe0TePbJT@squeak.grove.modra.org/mbox/"},{"id":1712,"url":"https://patchwork.plctlab.org/api/1.2/patches/1712/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/02d747d2-f57b-0fb5-b893-842b6cc41f2f@suse.com/","msgid":"<02d747d2-f57b-0fb5-b893-842b6cc41f2f@suse.com>","list_archive_url":null,"date":"2022-10-05T07:20:47","name":"[v3,1/7] x86: constify parse_insn()'\''s input","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/02d747d2-f57b-0fb5-b893-842b6cc41f2f@suse.com/mbox/"},{"id":1713,"url":"https://patchwork.plctlab.org/api/1.2/patches/1713/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/925cb740-4e1b-abc4-8526-aaab6faae5e1@suse.com/","msgid":"<925cb740-4e1b-abc4-8526-aaab6faae5e1@suse.com>","list_archive_url":null,"date":"2022-10-05T07:22:19","name":"[v3,2/7] x86: introduce Pass2 insn attribute","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/925cb740-4e1b-abc4-8526-aaab6faae5e1@suse.com/mbox/"},{"id":1714,"url":"https://patchwork.plctlab.org/api/1.2/patches/1714/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e16d3e78-39ca-f715-508f-a4104b8ab9a9@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-05T07:23:51","name":"[v3,3/7] x86: re-work insn/suffix recognition","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e16d3e78-39ca-f715-508f-a4104b8ab9a9@suse.com/mbox/"},{"id":1715,"url":"https://patchwork.plctlab.org/api/1.2/patches/1715/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e4e4b80b-794c-7485-1997-685adab8fb27@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-05T07:24:20","name":"[v3,4/7] x86-64: further re-work insn/suffix recognition to also cover MOVSL","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e4e4b80b-794c-7485-1997-685adab8fb27@suse.com/mbox/"},{"id":1716,"url":"https://patchwork.plctlab.org/api/1.2/patches/1716/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/540678fc-8bff-ec68-c97c-478d2631998c@suse.com/","msgid":"<540678fc-8bff-ec68-c97c-478d2631998c@suse.com>","list_archive_url":null,"date":"2022-10-05T07:24:55","name":"[v3,5/7] ix86: don'\''t recognize/derive Q suffix in the common case","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/540678fc-8bff-ec68-c97c-478d2631998c@suse.com/mbox/"},{"id":1718,"url":"https://patchwork.plctlab.org/api/1.2/patches/1718/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e4692495-7d3d-074d-14f9-364d4a9a998c@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-05T07:25:25","name":"[v3,6/7] x86-64: allow HLE store of accumulator to absolute 32-bit address","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e4692495-7d3d-074d-14f9-364d4a9a998c@suse.com/mbox/"},{"id":1717,"url":"https://patchwork.plctlab.org/api/1.2/patches/1717/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e8014ebd-d16b-17a7-9f34-3700fc164136@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-05T07:25:57","name":"[v3,7/7] x86: move bad-use-of-TLS-reloc check","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e8014ebd-d16b-17a7-9f34-3700fc164136@suse.com/mbox/"},{"id":1719,"url":"https://patchwork.plctlab.org/api/1.2/patches/1719/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1266f001-4511-2662-dba9-14b4d0317c57@suse.com/","msgid":"<1266f001-4511-2662-dba9-14b4d0317c57@suse.com>","list_archive_url":null,"date":"2022-10-05T07:40:50","name":"x86: drop \"regmask\" static variable","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1266f001-4511-2662-dba9-14b4d0317c57@suse.com/mbox/"},{"id":1751,"url":"https://patchwork.plctlab.org/api/1.2/patches/1751/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/af45c5d57c221e43101c2aa38b14f4b4ac12d011.1665031170.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-06T04:40:15","name":"[v2,1/2] RISC-V: Fallback for instructions longer than 64b","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/af45c5d57c221e43101c2aa38b14f4b4ac12d011.1665031170.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1752,"url":"https://patchwork.plctlab.org/api/1.2/patches/1752/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c6e55781245dd3e8e9b8debd6130fc5449dfbd55.1665031170.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-06T04:40:16","name":"[v2,2/2] RISC-V: Improve \"bits undefined\" diagnostics","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c6e55781245dd3e8e9b8debd6130fc5449dfbd55.1665031170.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1776,"url":"https://patchwork.plctlab.org/api/1.2/patches/1776/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d52952119e15357c0e823f8a2398999359588b4d.1665050099.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-06T09:56:30","name":"[v3,1/2] RISC-V: Fallback for instructions longer than 64b","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d52952119e15357c0e823f8a2398999359588b4d.1665050099.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1777,"url":"https://patchwork.plctlab.org/api/1.2/patches/1777/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d907b1997f60ff7823c4a23e281ec9d8ddcbf3f1.1665050099.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-06T09:56:31","name":"[v3,2/2] RISC-V: Improve \"bits undefined\" diagnostics","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d907b1997f60ff7823c4a23e281ec9d8ddcbf3f1.1665050099.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1781,"url":"https://patchwork.plctlab.org/api/1.2/patches/1781/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221006114628.304185-1-chigot@adacore.com/","msgid":"<20221006114628.304185-1-chigot@adacore.com>","list_archive_url":null,"date":"2022-10-06T11:46:28","name":"RISC-V: fix linker message when relaxation deletes bytes","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221006114628.304185-1-chigot@adacore.com/mbox/"},{"id":1801,"url":"https://patchwork.plctlab.org/api/1.2/patches/1801/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Yz+Yhyg7UewC9/kp@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-07T03:09:59","name":"PR29653, objcopy/strip: fuzzed small input file induces large output file","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Yz+Yhyg7UewC9/kp@squeak.grove.modra.org/mbox/"},{"id":1803,"url":"https://patchwork.plctlab.org/api/1.2/patches/1803/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/PH1P110MB16505D9D39EC5B1DE22FE3D5EC5F9@PH1P110MB1650.NAMP110.PROD.OUTLOOK.COM/","msgid":"","list_archive_url":null,"date":"2022-10-07T04:10:07","name":"@CPP_FOR_BUILD@ problem since binutils-2.38","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/PH1P110MB16505D9D39EC5B1DE22FE3D5EC5F9@PH1P110MB1650.NAMP110.PROD.OUTLOOK.COM/mbox/"},{"id":1827,"url":"https://patchwork.plctlab.org/api/1.2/patches/1827/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8e13bce108ac10a0c1dd911e23ec572926f7ae44.1665203374.git.research_trasio@irq.a4lg.com/","msgid":"<8e13bce108ac10a0c1dd911e23ec572926f7ae44.1665203374.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-08T04:29:53","name":"[v2,1/1] RISC-V: Test DWARF register numbers for \"fp\"","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8e13bce108ac10a0c1dd911e23ec572926f7ae44.1665203374.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1828,"url":"https://patchwork.plctlab.org/api/1.2/patches/1828/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0883001b3572e54d3fba264429c7ade2adb66610.1665203441.git.research_trasio@irq.a4lg.com/","msgid":"<0883001b3572e54d3fba264429c7ade2adb66610.1665203441.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-08T04:31:15","name":"[1/1] RISC-V: Move standard hints before all instructions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0883001b3572e54d3fba264429c7ade2adb66610.1665203441.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1829,"url":"https://patchwork.plctlab.org/api/1.2/patches/1829/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/58e16a241d7376fcae2515c6bd5a2b41d275eeba.1665203531.git.research_trasio@irq.a4lg.com/","msgid":"<58e16a241d7376fcae2515c6bd5a2b41d275eeba.1665203531.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-08T04:32:18","name":"[RFC,1/1] RISC-V: Imply '\''Zicsr'\'' from privileged extensions with CSRs","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/58e16a241d7376fcae2515c6bd5a2b41d275eeba.1665203531.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1830,"url":"https://patchwork.plctlab.org/api/1.2/patches/1830/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/cb5076fc96e8f2097779a3abcde843dcdd660031.1665203660.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-08T04:34:23","name":"[1/5] opcodes/riscv-dis.c: Tidying with comments/clarity","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/cb5076fc96e8f2097779a3abcde843dcdd660031.1665203660.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1832,"url":"https://patchwork.plctlab.org/api/1.2/patches/1832/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1f1aa0838bf9c4f10a45fcfe3c682f7efc79d9ae.1665203660.git.research_trasio@irq.a4lg.com/","msgid":"<1f1aa0838bf9c4f10a45fcfe3c682f7efc79d9ae.1665203660.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-08T04:34:24","name":"[2/5] opcodes/riscv-dis.c: Tidying with spacing","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1f1aa0838bf9c4f10a45fcfe3c682f7efc79d9ae.1665203660.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1831,"url":"https://patchwork.plctlab.org/api/1.2/patches/1831/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/740bc5e2d2618d236519b39fedd1a1d7ae4e05da.1665203660.git.research_trasio@irq.a4lg.com/","msgid":"<740bc5e2d2618d236519b39fedd1a1d7ae4e05da.1665203660.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-08T04:34:25","name":"[3/5] opcodes/riscv-dis.c: Use bool type whenever possible","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/740bc5e2d2618d236519b39fedd1a1d7ae4e05da.1665203660.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1833,"url":"https://patchwork.plctlab.org/api/1.2/patches/1833/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6e3a9c235e317f441b4383b3daa68f2051bdc149.1665203660.git.research_trasio@irq.a4lg.com/","msgid":"<6e3a9c235e317f441b4383b3daa68f2051bdc149.1665203660.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-08T04:34:26","name":"[4/5] opcodes/riscv-dis.c: Make XLEN variable static","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6e3a9c235e317f441b4383b3daa68f2051bdc149.1665203660.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1834,"url":"https://patchwork.plctlab.org/api/1.2/patches/1834/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ad929233a62d887495122721340b2f9c80392963.1665203660.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-08T04:34:27","name":"[5/5] opcodes/riscv-dis.c: Remove last_map_state","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ad929233a62d887495122721340b2f9c80392963.1665203660.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1836,"url":"https://patchwork.plctlab.org/api/1.2/patches/1836/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d07e2b6f36ea2fd5830924a9bfeda941b774b687.1665290422.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-09T05:09:22","name":"RISC-V: Move certain arrays to riscv-opc.c","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d07e2b6f36ea2fd5830924a9bfeda941b774b687.1665290422.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1844,"url":"https://patchwork.plctlab.org/api/1.2/patches/1844/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010004623.16582-1-mark@harmstone.com/","msgid":"<20221010004623.16582-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-10T00:46:22","name":"[v2,1/2] ld: Add --pdb option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010004623.16582-1-mark@harmstone.com/mbox/"},{"id":1845,"url":"https://patchwork.plctlab.org/api/1.2/patches/1845/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010004623.16582-2-mark@harmstone.com/","msgid":"<20221010004623.16582-2-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-10T00:46:23","name":"[v2,2/2] ld: Add minimal pdb generation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010004623.16582-2-mark@harmstone.com/mbox/"},{"id":1890,"url":"https://patchwork.plctlab.org/api/1.2/patches/1890/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010200433.414320-1-vladimir.mezentsev@oracle.com/","msgid":"<20221010200433.414320-1-vladimir.mezentsev@oracle.com>","list_archive_url":null,"date":"2022-10-10T20:04:33","name":"gprofng: run tests without installation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010200433.414320-1-vladimir.mezentsev@oracle.com/mbox/"},{"id":1893,"url":"https://patchwork.plctlab.org/api/1.2/patches/1893/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010230426.719238-1-vladimir.mezentsev@oracle.com/","msgid":"<20221010230426.719238-1-vladimir.mezentsev@oracle.com>","list_archive_url":null,"date":"2022-10-10T23:04:26","name":"[2/2] gprofng: use the --libdir path to find libraries","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010230426.719238-1-vladimir.mezentsev@oracle.com/mbox/"},{"id":1894,"url":"https://patchwork.plctlab.org/api/1.2/patches/1894/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010235155.842469-1-vladimir.mezentsev@oracle.com/","msgid":"<20221010235155.842469-1-vladimir.mezentsev@oracle.com>","list_archive_url":null,"date":"2022-10-10T23:51:55","name":"[3/3] gprofng: no need to build version.texi","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010235155.842469-1-vladimir.mezentsev@oracle.com/mbox/"},{"id":1895,"url":"https://patchwork.plctlab.org/api/1.2/patches/1895/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011003702.4287-1-mark@harmstone.com/","msgid":"<20221011003702.4287-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-11T00:37:01","name":"[v3,1/2] ld: Add --pdb option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011003702.4287-1-mark@harmstone.com/mbox/"},{"id":1897,"url":"https://patchwork.plctlab.org/api/1.2/patches/1897/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011003702.4287-2-mark@harmstone.com/","msgid":"<20221011003702.4287-2-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-11T00:37:02","name":"[v3,2/2] ld: Add minimal pdb generation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011003702.4287-2-mark@harmstone.com/mbox/"},{"id":1928,"url":"https://patchwork.plctlab.org/api/1.2/patches/1928/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011175332.17156-1-mark@harmstone.com/","msgid":"<20221011175332.17156-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-11T17:53:31","name":"[v4,1/2] ld: Add --pdb option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011175332.17156-1-mark@harmstone.com/mbox/"},{"id":1929,"url":"https://patchwork.plctlab.org/api/1.2/patches/1929/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011175332.17156-2-mark@harmstone.com/","msgid":"<20221011175332.17156-2-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-11T17:53:32","name":"[v4,2/2] ld: Add minimal pdb generation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011175332.17156-2-mark@harmstone.com/mbox/"},{"id":1941,"url":"https://patchwork.plctlab.org/api/1.2/patches/1941/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221012031005.237446-1-simon.marchi@polymtl.ca/","msgid":"<20221012031005.237446-1-simon.marchi@polymtl.ca>","list_archive_url":null,"date":"2022-10-12T03:10:05","name":"[pushed] Re-apply \"Pass PKG_CONFIG_PATH down from top-level Makefile\"","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221012031005.237446-1-simon.marchi@polymtl.ca/mbox/"},{"id":1976,"url":"https://patchwork.plctlab.org/api/1.2/patches/1976/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1216a3f8-2273-8681-f528-9493a66891f0@suse.com/","msgid":"<1216a3f8-2273-8681-f528-9493a66891f0@suse.com>","list_archive_url":null,"date":"2022-10-13T08:16:49","name":"[v4,1/8] x86: constify parse_insn()'\''s input","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1216a3f8-2273-8681-f528-9493a66891f0@suse.com/mbox/"},{"id":1977,"url":"https://patchwork.plctlab.org/api/1.2/patches/1977/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/11599bbe-c779-aa9f-4d5d-c2243f0e69dc@suse.com/","msgid":"<11599bbe-c779-aa9f-4d5d-c2243f0e69dc@suse.com>","list_archive_url":null,"date":"2022-10-13T08:17:17","name":"[v4,2/8] x86: introduce Pass2 insn attribute","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/11599bbe-c779-aa9f-4d5d-c2243f0e69dc@suse.com/mbox/"},{"id":1978,"url":"https://patchwork.plctlab.org/api/1.2/patches/1978/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/357273a3-060c-23db-72da-3fc9d1be3d2a@suse.com/","msgid":"<357273a3-060c-23db-72da-3fc9d1be3d2a@suse.com>","list_archive_url":null,"date":"2022-10-13T08:18:09","name":"[v4,3/8] x86: re-work insn/suffix recognition","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/357273a3-060c-23db-72da-3fc9d1be3d2a@suse.com/mbox/"},{"id":1979,"url":"https://patchwork.plctlab.org/api/1.2/patches/1979/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0ec0587f-6a7b-45b6-8346-e5d774e73636@suse.com/","msgid":"<0ec0587f-6a7b-45b6-8346-e5d774e73636@suse.com>","list_archive_url":null,"date":"2022-10-13T08:18:39","name":"[v4,4/8] x86-64: further re-work insn/suffix recognition to also cover MOVSL","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0ec0587f-6a7b-45b6-8346-e5d774e73636@suse.com/mbox/"},{"id":1980,"url":"https://patchwork.plctlab.org/api/1.2/patches/1980/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fb617d0b-8759-3169-5a65-1178b7fef3d7@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-13T08:19:34","name":"[v4,5/8] ix86: don'\''t recognize/derive Q suffix in the common case","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fb617d0b-8759-3169-5a65-1178b7fef3d7@suse.com/mbox/"},{"id":1981,"url":"https://patchwork.plctlab.org/api/1.2/patches/1981/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1df3bd01-99c5-f56c-d937-970edd42b2b8@suse.com/","msgid":"<1df3bd01-99c5-f56c-d937-970edd42b2b8@suse.com>","list_archive_url":null,"date":"2022-10-13T08:20:14","name":"[v4,6/8] x86-64: allow HLE store of accumulator to absolute 32-bit address","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1df3bd01-99c5-f56c-d937-970edd42b2b8@suse.com/mbox/"},{"id":1982,"url":"https://patchwork.plctlab.org/api/1.2/patches/1982/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8486a218-39ec-16b2-5c6c-5037196b93cf@suse.com/","msgid":"<8486a218-39ec-16b2-5c6c-5037196b93cf@suse.com>","list_archive_url":null,"date":"2022-10-13T08:21:00","name":"[v4,7/8] x86: move bad-use-of-TLS-reloc check","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8486a218-39ec-16b2-5c6c-5037196b93cf@suse.com/mbox/"},{"id":1983,"url":"https://patchwork.plctlab.org/api/1.2/patches/1983/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7d82692d-93df-fbee-9efb-2f44e8a91df3@suse.com/","msgid":"<7d82692d-93df-fbee-9efb-2f44e8a91df3@suse.com>","list_archive_url":null,"date":"2022-10-13T08:22:00","name":"[v4,8/8] x86: drop (now) stray IsString","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7d82692d-93df-fbee-9efb-2f44e8a91df3@suse.com/mbox/"},{"id":2013,"url":"https://patchwork.plctlab.org/api/1.2/patches/2013/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8ab93d7a617ad480dd786210f46db0e5aa07d1ac.1665655719.git.research_trasio@irq.a4lg.com/","msgid":"<8ab93d7a617ad480dd786210f46db0e5aa07d1ac.1665655719.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-13T10:11:41","name":"include: Declare getopt function on old GNU libc","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8ab93d7a617ad480dd786210f46db0e5aa07d1ac.1665655719.git.research_trasio@irq.a4lg.com/mbox/"},{"id":2352,"url":"https://patchwork.plctlab.org/api/1.2/patches/2352/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221013201332.2747246-1-maskray@google.com/","msgid":"<20221013201332.2747246-1-maskray@google.com>","list_archive_url":null,"date":"2022-10-13T20:13:32","name":"ld: Add --undefined-version","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221013201332.2747246-1-maskray@google.com/mbox/"},{"id":2532,"url":"https://patchwork.plctlab.org/api/1.2/patches/2532/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014063520.1428330-2-zengxiao@eswincomputing.com/","msgid":"<20221014063520.1428330-2-zengxiao@eswincomputing.com>","list_archive_url":null,"date":"2022-10-14T06:35:20","name":"[1/1] RISC-V: Make R_RISCV_SUB6 conforms to riscv abi standard","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014063520.1428330-2-zengxiao@eswincomputing.com/mbox/"},{"id":2560,"url":"https://patchwork.plctlab.org/api/1.2/patches/2560/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/027ae69a-636b-6757-297a-eec42936401e@linaro.org/","msgid":"<027ae69a-636b-6757-297a-eec42936401e@linaro.org>","list_archive_url":null,"date":"2022-10-14T07:58:22","name":"[v3] aarch64-pe support for LD, GAS and BFD","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/027ae69a-636b-6757-297a-eec42936401e@linaro.org/mbox/"},{"id":2602,"url":"https://patchwork.plctlab.org/api/1.2/patches/2602/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-2-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-2-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:39","name":"[01/10] Support Intel AVX-IFMA","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-2-haochen.jiang@intel.com/mbox/"},{"id":2608,"url":"https://patchwork.plctlab.org/api/1.2/patches/2608/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-3-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-3-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:40","name":"[02/10] Support Intel AVX-VNNI-INT8","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-3-haochen.jiang@intel.com/mbox/"},{"id":2611,"url":"https://patchwork.plctlab.org/api/1.2/patches/2611/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-4-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-4-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:41","name":"[03/10] Support Intel AVX-NE-CONVERT","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-4-haochen.jiang@intel.com/mbox/"},{"id":2610,"url":"https://patchwork.plctlab.org/api/1.2/patches/2610/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-5-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-5-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:42","name":"[04/10] Support Intel CMPccXADD","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-5-haochen.jiang@intel.com/mbox/"},{"id":2601,"url":"https://patchwork.plctlab.org/api/1.2/patches/2601/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-6-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-6-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:43","name":"[05/10] Add handler for more i386_cpu_flags","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-6-haochen.jiang@intel.com/mbox/"},{"id":2606,"url":"https://patchwork.plctlab.org/api/1.2/patches/2606/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-7-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-7-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:44","name":"[06/10] Support Intel RAO-INT","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-7-haochen.jiang@intel.com/mbox/"},{"id":2609,"url":"https://patchwork.plctlab.org/api/1.2/patches/2609/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-8-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-8-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:45","name":"[07/10] Support Intel WRMSRNS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-8-haochen.jiang@intel.com/mbox/"},{"id":2605,"url":"https://patchwork.plctlab.org/api/1.2/patches/2605/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-9-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-9-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:46","name":"[08/10] Support Intel MSRLIST","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-9-haochen.jiang@intel.com/mbox/"},{"id":2607,"url":"https://patchwork.plctlab.org/api/1.2/patches/2607/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-10-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-10-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:47","name":"[09/10] Support Intel AMX-FP16","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-10-haochen.jiang@intel.com/mbox/"},{"id":2604,"url":"https://patchwork.plctlab.org/api/1.2/patches/2604/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-11-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-11-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:48","name":"[10/10] Support Intel PREFETCHI","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-11-haochen.jiang@intel.com/mbox/"},{"id":2643,"url":"https://patchwork.plctlab.org/api/1.2/patches/2643/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7bac66be-535e-9051-d674-f2f5ba180e17@suse.com/","msgid":"<7bac66be-535e-9051-d674-f2f5ba180e17@suse.com>","list_archive_url":null,"date":"2022-10-14T10:22:34","name":"x86: fold AVX512-VNNI disassembler entries with AVX-VNNI ones","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7bac66be-535e-9051-d674-f2f5ba180e17@suse.com/mbox/"},{"id":2654,"url":"https://patchwork.plctlab.org/api/1.2/patches/2654/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0lIo5+ncY/MqBEq@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-14T11:31:47","name":"PR29677, Field `the_bfd` of `asymbol` is uninitialised","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0lIo5+ncY/MqBEq@squeak.grove.modra.org/mbox/"},{"id":2656,"url":"https://patchwork.plctlab.org/api/1.2/patches/2656/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0lJksn49ZpABY89@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-14T11:35:46","name":"e200 LSP support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0lJksn49ZpABY89@squeak.grove.modra.org/mbox/"},{"id":2657,"url":"https://patchwork.plctlab.org/api/1.2/patches/2657/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0lJxxYoeD5iDYAD@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-14T11:36:39","name":"PowerPC SPE disassembly and tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0lJxxYoeD5iDYAD@squeak.grove.modra.org/mbox/"},{"id":2695,"url":"https://patchwork.plctlab.org/api/1.2/patches/2695/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/DM6PR12MB4219611F6CC2A0702884A602E7249@DM6PR12MB4219.namprd12.prod.outlook.com/","msgid":"","list_archive_url":null,"date":"2022-10-14T13:29:40","name":"Binutils: Adding new testcase for addr2line.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/DM6PR12MB4219611F6CC2A0702884A602E7249@DM6PR12MB4219.namprd12.prod.outlook.com/mbox/"},{"id":2700,"url":"https://patchwork.plctlab.org/api/1.2/patches/2700/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9fd2c88d-98b2-99a4-419f-c7235b2cf960@suse.com/","msgid":"<9fd2c88d-98b2-99a4-419f-c7235b2cf960@suse.com>","list_archive_url":null,"date":"2022-10-14T14:11:35","name":"x86: properly decode EVEX.W for AVX512_4{FMAPS,VNNIW} insns","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9fd2c88d-98b2-99a4-419f-c7235b2cf960@suse.com/mbox/"},{"id":2981,"url":"https://patchwork.plctlab.org/api/1.2/patches/2981/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0uLzalqjm4C87GN@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-16T04:42:53","name":"PowerPC se_rfmci and VLE, SPE2 and LSP insns with -many","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0uLzalqjm4C87GN@squeak.grove.modra.org/mbox/"},{"id":3152,"url":"https://patchwork.plctlab.org/api/1.2/patches/3152/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221016232419.1135-1-mark@harmstone.com/","msgid":"<20221016232419.1135-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-16T23:24:18","name":"[v5,1/2] ld: Add --pdb option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221016232419.1135-1-mark@harmstone.com/mbox/"},{"id":3151,"url":"https://patchwork.plctlab.org/api/1.2/patches/3151/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221016232419.1135-2-mark@harmstone.com/","msgid":"<20221016232419.1135-2-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-16T23:24:19","name":"[v5,2/2] ld: Add minimal pdb generation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221016232419.1135-2-mark@harmstone.com/mbox/"},{"id":3258,"url":"https://patchwork.plctlab.org/api/1.2/patches/3258/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/19c08747-fa5b-1e67-3dd2-c891a2c0c1fa@suse.com/","msgid":"<19c08747-fa5b-1e67-3dd2-c891a2c0c1fa@suse.com>","list_archive_url":null,"date":"2022-10-17T07:44:51","name":"x86: correct CPU_AMX_{BF16,INT8}_FLAGS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/19c08747-fa5b-1e67-3dd2-c891a2c0c1fa@suse.com/mbox/"},{"id":3272,"url":"https://patchwork.plctlab.org/api/1.2/patches/3272/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/85dd526c-d3a7-72dc-5444-ed5573eebec1@suse.com/","msgid":"<85dd526c-d3a7-72dc-5444-ed5573eebec1@suse.com>","list_archive_url":null,"date":"2022-10-17T08:30:12","name":"x86: generalize gas documentation for disabling of ISA extensions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/85dd526c-d3a7-72dc-5444-ed5573eebec1@suse.com/mbox/"},{"id":3759,"url":"https://patchwork.plctlab.org/api/1.2/patches/3759/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-2-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-2-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:15:58","name":"[V2,01/15] sframe.h: Add SFrame format definition","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-2-indu.bhagat@oracle.com/mbox/"},{"id":3762,"url":"https://patchwork.plctlab.org/api/1.2/patches/3762/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-3-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-3-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:15:59","name":"[V2,02/15] gas: add new command line option --gsframe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-3-indu.bhagat@oracle.com/mbox/"},{"id":3761,"url":"https://patchwork.plctlab.org/api/1.2/patches/3761/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-4-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-4-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:00","name":"[V2,03/15] gas: generate .sframe from CFI directives","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-4-indu.bhagat@oracle.com/mbox/"},{"id":3760,"url":"https://patchwork.plctlab.org/api/1.2/patches/3760/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-5-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-5-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:01","name":"[V2,04/15] gas: testsuite: add new tests for SFrame unwind info","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-5-indu.bhagat@oracle.com/mbox/"},{"id":3764,"url":"https://patchwork.plctlab.org/api/1.2/patches/3764/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-6-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-6-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:02","name":"[V2,05/15] libsframe: add the SFrame library","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-6-indu.bhagat@oracle.com/mbox/"},{"id":3766,"url":"https://patchwork.plctlab.org/api/1.2/patches/3766/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-7-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-7-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:03","name":"[V2,06/15] bfd: linker: merge .sframe sections","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-7-indu.bhagat@oracle.com/mbox/"},{"id":3763,"url":"https://patchwork.plctlab.org/api/1.2/patches/3763/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-8-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-8-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:04","name":"[V2,07/15] readelf/objdump: support for SFrame section","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-8-indu.bhagat@oracle.com/mbox/"},{"id":3765,"url":"https://patchwork.plctlab.org/api/1.2/patches/3765/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-9-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-9-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:05","name":"[V2,08/15] unwinder: generate backtrace using SFrame format","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-9-indu.bhagat@oracle.com/mbox/"},{"id":3770,"url":"https://patchwork.plctlab.org/api/1.2/patches/3770/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-10-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-10-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:06","name":"[V2,09/15] unwinder: Add SFrame unwinder tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-10-indu.bhagat@oracle.com/mbox/"},{"id":3769,"url":"https://patchwork.plctlab.org/api/1.2/patches/3769/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-11-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-11-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:07","name":"[V2,10/15] gdb: sim: buildsystem changes to accommodate libsframe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-11-indu.bhagat@oracle.com/mbox/"},{"id":3771,"url":"https://patchwork.plctlab.org/api/1.2/patches/3771/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-12-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-12-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:08","name":"[V2,11/15] libctf: add libsframe to LDFLAGS and LIBS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-12-indu.bhagat@oracle.com/mbox/"},{"id":3768,"url":"https://patchwork.plctlab.org/api/1.2/patches/3768/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-13-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-13-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:09","name":"[V2,12/15] src-release.sh: Add libsframe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-13-indu.bhagat@oracle.com/mbox/"},{"id":3767,"url":"https://patchwork.plctlab.org/api/1.2/patches/3767/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-14-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-14-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:10","name":"[V2,13/15] binutils/NEWS: add text for SFrame support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-14-indu.bhagat@oracle.com/mbox/"},{"id":3772,"url":"https://patchwork.plctlab.org/api/1.2/patches/3772/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-15-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-15-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:11","name":"[V2,14/15] gas/NEWS: add text about new command line option and SFrame support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-15-indu.bhagat@oracle.com/mbox/"},{"id":3773,"url":"https://patchwork.plctlab.org/api/1.2/patches/3773/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-16-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-16-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:12","name":"[V2,15/15] doc: add SFrame spec file","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-16-indu.bhagat@oracle.com/mbox/"},{"id":3999,"url":"https://patchwork.plctlab.org/api/1.2/patches/3999/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221018081205.17880-1-krebbel@linux.ibm.com/","msgid":"<20221018081205.17880-1-krebbel@linux.ibm.com>","list_archive_url":null,"date":"2022-10-18T08:12:05","name":"[1/1] IBM zSystems: Issue error for *DBL relocs on misaligned symbols","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221018081205.17880-1-krebbel@linux.ibm.com/mbox/"},{"id":4141,"url":"https://patchwork.plctlab.org/api/1.2/patches/4141/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/baffaf673f17692b7bcbd604b31800b189988596.camel@espressif.com/","msgid":"","list_archive_url":null,"date":"2022-10-18T12:12:07","name":"xtensa: use definitions from xtensa-config.h","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/baffaf673f17692b7bcbd604b31800b189988596.camel@espressif.com/mbox/"},{"id":4272,"url":"https://patchwork.plctlab.org/api/1.2/patches/4272/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221018174914.470062-1-hjl.tools@gmail.com/","msgid":"<20221018174914.470062-1-hjl.tools@gmail.com>","list_archive_url":null,"date":"2022-10-18T17:49:14","name":"x86: Disable AVX-VNNI when disabling AVX2","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221018174914.470062-1-hjl.tools@gmail.com/mbox/"},{"id":4998,"url":"https://patchwork.plctlab.org/api/1.2/patches/4998/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c2f76e95-09f6-1d92-7ef4-38a3c2955fcd@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-19T09:52:46","name":"x86: re-work AVX-VNNI support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c2f76e95-09f6-1d92-7ef4-38a3c2955fcd@suse.com/mbox/"},{"id":5276,"url":"https://patchwork.plctlab.org/api/1.2/patches/5276/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0/lLtlKqqsmAx0s@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-19T11:53:18","name":"Fix addr2line test for ppc64 elfv1 and mingw","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0/lLtlKqqsmAx0s@squeak.grove.modra.org/mbox/"},{"id":5424,"url":"https://patchwork.plctlab.org/api/1.2/patches/5424/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/07bfebbf3843b47e13d82d4fa16eb14fec942ef7.1666184962.git.research_trasio@irq.a4lg.com/","msgid":"<07bfebbf3843b47e13d82d4fa16eb14fec942ef7.1666184962.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:09:54","name":"binutils: Remove unused substitution PROGRAM","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/07bfebbf3843b47e13d82d4fa16eb14fec942ef7.1666184962.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5433,"url":"https://patchwork.plctlab.org/api/1.2/patches/5433/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2fa7ff719223232402e82a9c91331aea22ace1bb.1666185116.git.research_trasio@irq.a4lg.com/","msgid":"<2fa7ff719223232402e82a9c91331aea22ace1bb.1666185116.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:11:55","name":"[v2,1/8] RISC-V: Add a space at the end of pinfo","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2fa7ff719223232402e82a9c91331aea22ace1bb.1666185116.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5435,"url":"https://patchwork.plctlab.org/api/1.2/patches/5435/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1b30cce5db2cce3b8edca42ab5da114d0b8c9e93.1666185116.git.research_trasio@irq.a4lg.com/","msgid":"<1b30cce5db2cce3b8edca42ab5da114d0b8c9e93.1666185116.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:11:56","name":"[v2,2/8] RISC-V: Fix obvious misalignments ('\''Zbb'\''/'\''Zba'\'')","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1b30cce5db2cce3b8edca42ab5da114d0b8c9e93.1666185116.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5437,"url":"https://patchwork.plctlab.org/api/1.2/patches/5437/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6b0857aa1a2d15ca1cf00b4dcaae0032efbb88ff.1666185116.git.research_trasio@irq.a4lg.com/","msgid":"<6b0857aa1a2d15ca1cf00b4dcaae0032efbb88ff.1666185116.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:11:57","name":"[v2,3/8] RISC-V: Remove spaces in opcode entries","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6b0857aa1a2d15ca1cf00b4dcaae0032efbb88ff.1666185116.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5436,"url":"https://patchwork.plctlab.org/api/1.2/patches/5436/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/889d956caac0f2e95543a14afaeed97188ce384c.1666185116.git.research_trasio@irq.a4lg.com/","msgid":"<889d956caac0f2e95543a14afaeed97188ce384c.1666185116.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:11:58","name":"[v2,4/8] RISC-V: Remove unused instruction macros","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/889d956caac0f2e95543a14afaeed97188ce384c.1666185116.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5440,"url":"https://patchwork.plctlab.org/api/1.2/patches/5440/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8f226ee20d8a5ef6ad7b6c4408b44794a99d542a.1666185116.git.research_trasio@irq.a4lg.com/","msgid":"<8f226ee20d8a5ef6ad7b6c4408b44794a99d542a.1666185116.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:11:59","name":"[v2,5/8] RISC-V: Complete tidying up with SCALL and SBREAK","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8f226ee20d8a5ef6ad7b6c4408b44794a99d542a.1666185116.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5442,"url":"https://patchwork.plctlab.org/api/1.2/patches/5442/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4070184c454a05a39adf0790951e5856e6b2ecb6.1666185116.git.research_trasio@irq.a4lg.com/","msgid":"<4070184c454a05a39adf0790951e5856e6b2ecb6.1666185116.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:12:00","name":"[v2,6/8] RISC-V: Tidying up with fmv.w.x and fmv.x.w","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4070184c454a05a39adf0790951e5856e6b2ecb6.1666185116.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5438,"url":"https://patchwork.plctlab.org/api/1.2/patches/5438/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c1ccda3e7c8fb297eda46dab3936d5c5977178fc.1666185116.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-19T13:12:01","name":"[v2,7/8] RISC-V: Make alias instructions aliases","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c1ccda3e7c8fb297eda46dab3936d5c5977178fc.1666185116.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5441,"url":"https://patchwork.plctlab.org/api/1.2/patches/5441/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/413cfca82c7e8d8a2e977dfda9135903c9cb7c57.1666185116.git.research_trasio@irq.a4lg.com/","msgid":"<413cfca82c7e8d8a2e977dfda9135903c9cb7c57.1666185116.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:12:02","name":"[v2,8/8] RISC-V: Use defined mask and match values","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/413cfca82c7e8d8a2e977dfda9135903c9cb7c57.1666185116.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5439,"url":"https://patchwork.plctlab.org/api/1.2/patches/5439/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/345c5c3b3a53eab04a1e6e91197de2642095c94f.1666185237.git.research_trasio@irq.a4lg.com/","msgid":"<345c5c3b3a53eab04a1e6e91197de2642095c94f.1666185237.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:14:01","name":"RISC-V: Remove RV32EF conflict","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/345c5c3b3a53eab04a1e6e91197de2642095c94f.1666185237.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5616,"url":"https://patchwork.plctlab.org/api/1.2/patches/5616/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019145608.45213-5-haochen.jiang@intel.com/","msgid":"<20221019145608.45213-5-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T14:56:02","name":"[04/10] Support Intel CMPccXADD","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019145608.45213-5-haochen.jiang@intel.com/mbox/"},{"id":5614,"url":"https://patchwork.plctlab.org/api/1.2/patches/5614/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019145608.45213-6-haochen.jiang@intel.com/","msgid":"<20221019145608.45213-6-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T14:56:03","name":"[05/10] Add handler for more i386_cpu_flags","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019145608.45213-6-haochen.jiang@intel.com/mbox/"},{"id":5672,"url":"https://patchwork.plctlab.org/api/1.2/patches/5672/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-2-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-2-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:25","name":"[01/10] Support Intel AVX-IFMA","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-2-haochen.jiang@intel.com/mbox/"},{"id":5691,"url":"https://patchwork.plctlab.org/api/1.2/patches/5691/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-3-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-3-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:26","name":"[02/10] Support Intel AVX-VNNI-INT8","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-3-haochen.jiang@intel.com/mbox/"},{"id":5690,"url":"https://patchwork.plctlab.org/api/1.2/patches/5690/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-4-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-4-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:27","name":"[03/10] Support Intel AVX-NE-CONVERT","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-4-haochen.jiang@intel.com/mbox/"},{"id":5689,"url":"https://patchwork.plctlab.org/api/1.2/patches/5689/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-5-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-5-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:28","name":"[04/10] Support Intel CMPccXADD","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-5-haochen.jiang@intel.com/mbox/"},{"id":5676,"url":"https://patchwork.plctlab.org/api/1.2/patches/5676/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-6-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-6-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:29","name":"[05/10] Add handler for more i386_cpu_flags","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-6-haochen.jiang@intel.com/mbox/"},{"id":5677,"url":"https://patchwork.plctlab.org/api/1.2/patches/5677/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-7-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-7-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:30","name":"[06/10] Support Intel RAO-INT","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-7-haochen.jiang@intel.com/mbox/"},{"id":5681,"url":"https://patchwork.plctlab.org/api/1.2/patches/5681/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-8-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-8-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:31","name":"[07/10] Support Intel WRMSRNS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-8-haochen.jiang@intel.com/mbox/"},{"id":5682,"url":"https://patchwork.plctlab.org/api/1.2/patches/5682/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-9-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-9-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:32","name":"[08/10] Support Intel MSRLIST","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-9-haochen.jiang@intel.com/mbox/"},{"id":5673,"url":"https://patchwork.plctlab.org/api/1.2/patches/5673/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-10-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-10-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:33","name":"[09/10] Support Intel AMX-FP16","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-10-haochen.jiang@intel.com/mbox/"},{"id":5686,"url":"https://patchwork.plctlab.org/api/1.2/patches/5686/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-11-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-11-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:34","name":"[10/10] Support Intel PREFETCHI","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-11-haochen.jiang@intel.com/mbox/"},{"id":5940,"url":"https://patchwork.plctlab.org/api/1.2/patches/5940/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1CMrFUC8d9lC/NL@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-19T23:47:56","name":"Obsolete beos","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1CMrFUC8d9lC/NL@squeak.grove.modra.org/mbox/"},{"id":6080,"url":"https://patchwork.plctlab.org/api/1.2/patches/6080/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8b99d666e78ba5b9d32c7889a2161c70b3da88df.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<8b99d666e78ba5b9d32c7889a2161c70b3da88df.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:25:47","name":"[01/40] gdb/unittests: PR28413, suppress warnings generated by Gnulib","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8b99d666e78ba5b9d32c7889a2161c70b3da88df.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6081,"url":"https://patchwork.plctlab.org/api/1.2/patches/6081/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b05adb17e401d621dbdad791281bc7af7806906e.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-20T09:25:48","name":"[02/40] sim: Check known getrusage declaration existence","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b05adb17e401d621dbdad791281bc7af7806906e.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6083,"url":"https://patchwork.plctlab.org/api/1.2/patches/6083/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/796962a87e569feeafb5ef636de3c79000ae152c.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<796962a87e569feeafb5ef636de3c79000ae152c.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:25:49","name":"[03/40] sim/aarch64: Remove unused functions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/796962a87e569feeafb5ef636de3c79000ae152c.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6084,"url":"https://patchwork.plctlab.org/api/1.2/patches/6084/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/65223c79fdfd7faf132275415cd9da9852c5bec3.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<65223c79fdfd7faf132275415cd9da9852c5bec3.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:25:50","name":"[04/40] cpu/cris: Initialize some variables on CRIS CPU","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/65223c79fdfd7faf132275415cd9da9852c5bec3.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6082,"url":"https://patchwork.plctlab.org/api/1.2/patches/6082/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/24baefe92148f4b7968115ba13de9b0c863a65f6.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<24baefe92148f4b7968115ba13de9b0c863a65f6.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:25:51","name":"[05/40] cpu/cris: Add u-stall virtual unit to CRIS v32","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/24baefe92148f4b7968115ba13de9b0c863a65f6.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6087,"url":"https://patchwork.plctlab.org/api/1.2/patches/6087/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3904a5c3e80f8548150d8088a92059dd728c7ff8.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<3904a5c3e80f8548150d8088a92059dd728c7ff8.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:25:52","name":"[06/40] sim/cris: Move declarations of f_specific_init","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3904a5c3e80f8548150d8088a92059dd728c7ff8.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6091,"url":"https://patchwork.plctlab.org/api/1.2/patches/6091/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/69ef2d7dd519ed572511890a215a0f6d74e53384.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<69ef2d7dd519ed572511890a215a0f6d74e53384.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:25:53","name":"[07/40] sim/cris: Regenerate with CGEN","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/69ef2d7dd519ed572511890a215a0f6d74e53384.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6085,"url":"https://patchwork.plctlab.org/api/1.2/patches/6085/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/26a3eaf4f5d2e0db6977738ddfd65d82b36e38b2.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<26a3eaf4f5d2e0db6977738ddfd65d82b36e38b2.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:25:54","name":"[08/40] sim/erc32: Insert void parameter","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/26a3eaf4f5d2e0db6977738ddfd65d82b36e38b2.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6086,"url":"https://patchwork.plctlab.org/api/1.2/patches/6086/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/057c2f8392410494c3bc5dc98052246508e6a73e.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<057c2f8392410494c3bc5dc98052246508e6a73e.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:25:55","name":"[09/40] sim/erc32: Use int32_t as event callback argument","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/057c2f8392410494c3bc5dc98052246508e6a73e.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6090,"url":"https://patchwork.plctlab.org/api/1.2/patches/6090/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8c05aec20557191434485be347d37177a2ec5ff2.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<8c05aec20557191434485be347d37177a2ec5ff2.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:25:56","name":"[10/40] sim/erc32: Use int32_t as IRQ callback argument","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8c05aec20557191434485be347d37177a2ec5ff2.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6089,"url":"https://patchwork.plctlab.org/api/1.2/patches/6089/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/afd7757aae21743c29f2aa4135a23b31d4959e9b.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-20T09:25:57","name":"[11/40] cpu/frv: Initialize some variables","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/afd7757aae21743c29f2aa4135a23b31d4959e9b.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6088,"url":"https://patchwork.plctlab.org/api/1.2/patches/6088/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/021dbd238af5dfe74523ed229d2156a155a6bb9e.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<021dbd238af5dfe74523ed229d2156a155a6bb9e.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:25:58","name":"[12/40] sim/frv: Initialize nesr variable","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/021dbd238af5dfe74523ed229d2156a155a6bb9e.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6093,"url":"https://patchwork.plctlab.org/api/1.2/patches/6093/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/51a03f7097921cc48954210cf99e370ae8982ec8.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<51a03f7097921cc48954210cf99e370ae8982ec8.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:25:59","name":"[13/40] sim/frv: Initialize some variables","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/51a03f7097921cc48954210cf99e370ae8982ec8.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6092,"url":"https://patchwork.plctlab.org/api/1.2/patches/6092/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e1baa1be3601612266dc6ae0bdde8426ff2a42c8.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-20T09:26:00","name":"[14/40] sim/frv: Add explicit casts","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e1baa1be3601612266dc6ae0bdde8426ff2a42c8.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6095,"url":"https://patchwork.plctlab.org/api/1.2/patches/6095/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5ab303a5bdfc1da7832f8fa22f57678c9ef1a5fa.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<5ab303a5bdfc1da7832f8fa22f57678c9ef1a5fa.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:26:01","name":"[15/40] sim/h8300: Add \"+ 0x0\" to avoid self-assignments","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5ab303a5bdfc1da7832f8fa22f57678c9ef1a5fa.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6101,"url":"https://patchwork.plctlab.org/api/1.2/patches/6101/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ddff80db3328a2286fe6fbc1240d2abc1e3813eb.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-20T09:26:02","name":"[16/40] sim/lm32: fix some missing function declaration warnings","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ddff80db3328a2286fe6fbc1240d2abc1e3813eb.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6094,"url":"https://patchwork.plctlab.org/api/1.2/patches/6094/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e094b1379231d9ffb59a78cfebbcc84634c779c6.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-20T09:26:03","name":"[17/40] sim/lm32: Add explicit casts","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e094b1379231d9ffb59a78cfebbcc84634c779c6.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6141,"url":"https://patchwork.plctlab.org/api/1.2/patches/6141/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/cabebead-489b-528c-580e-933832417474@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-20T10:25:51","name":"[1/3] x86: emit {evex} prefix when disassembling ambiguous AVX512VL insns","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/cabebead-489b-528c-580e-933832417474@suse.com/mbox/"},{"id":6143,"url":"https://patchwork.plctlab.org/api/1.2/patches/6143/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a032d61c-63a0-23d1-331f-619a2b8bbde3@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-20T10:26:15","name":"[2/3] x86: consolidate VAES tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a032d61c-63a0-23d1-331f-619a2b8bbde3@suse.com/mbox/"},{"id":6142,"url":"https://patchwork.plctlab.org/api/1.2/patches/6142/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7ff09c86-2de7-dc34-3183-5187de3df5ac@suse.com/","msgid":"<7ff09c86-2de7-dc34-3183-5187de3df5ac@suse.com>","list_archive_url":null,"date":"2022-10-20T10:26:40","name":"[3/3] x86: consolidate VPCLMUL tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7ff09c86-2de7-dc34-3183-5187de3df5ac@suse.com/mbox/"},{"id":6228,"url":"https://patchwork.plctlab.org/api/1.2/patches/6228/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.LSU.2.20.2210201432170.29399@wotan.suse.de/","msgid":"","list_archive_url":null,"date":"2022-10-20T14:42:25","name":"x86-64: Use only one default max-page-size","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.LSU.2.20.2210201432170.29399@wotan.suse.de/mbox/"},{"id":6229,"url":"https://patchwork.plctlab.org/api/1.2/patches/6229/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221020144351.1398099-1-chigot@adacore.com/","msgid":"<20221020144351.1398099-1-chigot@adacore.com>","list_archive_url":null,"date":"2022-10-20T14:43:50","name":"[1/2] ld/testsuite: skip ld-elf/exclude when -shared is not supported","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221020144351.1398099-1-chigot@adacore.com/mbox/"},{"id":6230,"url":"https://patchwork.plctlab.org/api/1.2/patches/6230/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221020144351.1398099-2-chigot@adacore.com/","msgid":"<20221020144351.1398099-2-chigot@adacore.com>","list_archive_url":null,"date":"2022-10-20T14:43:51","name":"[2/2] ld/testsuite: adjust ld-arm to run shared tests only when supported","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221020144351.1398099-2-chigot@adacore.com/mbox/"},{"id":6236,"url":"https://patchwork.plctlab.org/api/1.2/patches/6236/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221020151027.GA1300@delia.home/","msgid":"<20221020151027.GA1300@delia.home>","list_archive_url":null,"date":"2022-10-20T15:10:28","name":"[RFC,top-level] Add configure test-case","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221020151027.GA1300@delia.home/mbox/"},{"id":6286,"url":"https://patchwork.plctlab.org/api/1.2/patches/6286/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221020162911.1113338-1-hjl.tools@gmail.com/","msgid":"<20221020162911.1113338-1-hjl.tools@gmail.com>","list_archive_url":null,"date":"2022-10-20T16:29:11","name":"x86: Check VEX/EVEX encoding before checking vector operands","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221020162911.1113338-1-hjl.tools@gmail.com/mbox/"},{"id":7884,"url":"https://patchwork.plctlab.org/api/1.2/patches/7884/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7e53b7980f2b3b74d2250bc87f5db94b1d888a2d.camel@espressif.com/","msgid":"<7e53b7980f2b3b74d2250bc87f5db94b1d888a2d.camel@espressif.com>","list_archive_url":null,"date":"2022-10-22T12:53:54","name":"[1/5] bfd: xtensa: move common code from ld and gas","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7e53b7980f2b3b74d2250bc87f5db94b1d888a2d.camel@espressif.com/mbox/"},{"id":7885,"url":"https://patchwork.plctlab.org/api/1.2/patches/7885/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/63f2699e6ef3e6d1ca415a6ed1187d4f64297521.camel@espressif.com/","msgid":"<63f2699e6ef3e6d1ca415a6ed1187d4f64297521.camel@espressif.com>","list_archive_url":null,"date":"2022-10-22T12:55:16","name":"[2/5] gas: xtensa: add endianness, loops, booleans options","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/63f2699e6ef3e6d1ca415a6ed1187d4f64297521.camel@espressif.com/mbox/"},{"id":7886,"url":"https://patchwork.plctlab.org/api/1.2/patches/7886/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/34d2f747237aeeda595560cfded8096d9bd1c28c.camel@espressif.com/","msgid":"<34d2f747237aeeda595560cfded8096d9bd1c28c.camel@espressif.com>","list_archive_url":null,"date":"2022-10-22T12:56:02","name":"[3/5] ld: xtensa: use default LD command line options for endianness","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/34d2f747237aeeda595560cfded8096d9bd1c28c.camel@espressif.com/mbox/"},{"id":7891,"url":"https://patchwork.plctlab.org/api/1.2/patches/7891/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/535b6208c1718b9acf3258575e1ebc0a65af9f07.camel@espressif.com/","msgid":"<535b6208c1718b9acf3258575e1ebc0a65af9f07.camel@espressif.com>","list_archive_url":null,"date":"2022-10-22T13:56:44","name":"[5/5] gdb: xtensa: add support for esp32, esp32s2, esp32s3 isa-modules","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/535b6208c1718b9acf3258575e1ebc0a65af9f07.camel@espressif.com/mbox/"},{"id":10456,"url":"https://patchwork.plctlab.org/api/1.2/patches/10456/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221025013347.68282-1-nelson@rivosinc.com/","msgid":"<20221025013347.68282-1-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-10-25T01:33:46","name":"[committed,1/2] RISC-V: Improve link time complexity.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221025013347.68282-1-nelson@rivosinc.com/mbox/"},{"id":10454,"url":"https://patchwork.plctlab.org/api/1.2/patches/10454/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221025013347.68282-2-nelson@rivosinc.com/","msgid":"<20221025013347.68282-2-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-10-25T01:33:47","name":"[committed,2/2] RISC-V: Should reset `again'\'' flag for _bfd_riscv_relax_pc.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221025013347.68282-2-nelson@rivosinc.com/mbox/"},{"id":10536,"url":"https://patchwork.plctlab.org/api/1.2/patches/10536/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/bb7b87e4-1893-5c86-4a14-92bafc818b03@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-25T07:24:56","name":"[v5,1/8] x86: constify parse_insn()'\''s input","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/bb7b87e4-1893-5c86-4a14-92bafc818b03@suse.com/mbox/"},{"id":10537,"url":"https://patchwork.plctlab.org/api/1.2/patches/10537/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b9273ae6-0218-54f8-5374-b265ed13b71a@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-25T07:25:26","name":"[v5,1/8] x86: introduce Pass2 insn attribute","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b9273ae6-0218-54f8-5374-b265ed13b71a@suse.com/mbox/"},{"id":10541,"url":"https://patchwork.plctlab.org/api/1.2/patches/10541/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7250dab9-e218-e6dd-4c74-23da9f611ab4@suse.com/","msgid":"<7250dab9-e218-e6dd-4c74-23da9f611ab4@suse.com>","list_archive_url":null,"date":"2022-10-25T07:26:11","name":"[v5,3/8] x86: re-work insn/suffix recognition","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7250dab9-e218-e6dd-4c74-23da9f611ab4@suse.com/mbox/"},{"id":10540,"url":"https://patchwork.plctlab.org/api/1.2/patches/10540/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/13fc630f-e116-0099-5c9e-2697df6519d7@suse.com/","msgid":"<13fc630f-e116-0099-5c9e-2697df6519d7@suse.com>","list_archive_url":null,"date":"2022-10-25T07:26:40","name":"[v5,4/8] ix86: don'\''t recognize/derive Q suffix in the common case","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/13fc630f-e116-0099-5c9e-2697df6519d7@suse.com/mbox/"},{"id":10543,"url":"https://patchwork.plctlab.org/api/1.2/patches/10543/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/74db429d-d203-eab8-4ae1-18b9ad416b02@suse.com/","msgid":"<74db429d-d203-eab8-4ae1-18b9ad416b02@suse.com>","list_archive_url":null,"date":"2022-10-25T07:27:11","name":"[v5,5/8] x86-64: allow HLE store of accumulator to absolute 32-bit address","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/74db429d-d203-eab8-4ae1-18b9ad416b02@suse.com/mbox/"},{"id":10542,"url":"https://patchwork.plctlab.org/api/1.2/patches/10542/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2e2f7841-de4e-b5de-e8d9-a47a6a4113c8@suse.com/","msgid":"<2e2f7841-de4e-b5de-e8d9-a47a6a4113c8@suse.com>","list_archive_url":null,"date":"2022-10-25T07:27:35","name":"[v5,6/8] x86: move bad-use-of-TLS-reloc check","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2e2f7841-de4e-b5de-e8d9-a47a6a4113c8@suse.com/mbox/"},{"id":10545,"url":"https://patchwork.plctlab.org/api/1.2/patches/10545/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/421bc96e-7591-6980-48e9-5af8c8b0775a@suse.com/","msgid":"<421bc96e-7591-6980-48e9-5af8c8b0775a@suse.com>","list_archive_url":null,"date":"2022-10-25T07:28:27","name":"[v5,7/8] x86: drop (now) stray IsString","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/421bc96e-7591-6980-48e9-5af8c8b0775a@suse.com/mbox/"},{"id":10546,"url":"https://patchwork.plctlab.org/api/1.2/patches/10546/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/06ff83d4-4633-a07b-70e5-a8e049981dd4@suse.com/","msgid":"<06ff83d4-4633-a07b-70e5-a8e049981dd4@suse.com>","list_archive_url":null,"date":"2022-10-25T07:29:18","name":"[v5,8/8] x86: further re-work insn/suffix recognition to also cover MOVSX","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/06ff83d4-4633-a07b-70e5-a8e049981dd4@suse.com/mbox/"},{"id":10777,"url":"https://patchwork.plctlab.org/api/1.2/patches/10777/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6a8e7a71acccd0efb9789dfb3edfa307e83bdaa1.1666702934.git.research_trasio@irq.a4lg.com/","msgid":"<6a8e7a71acccd0efb9789dfb3edfa307e83bdaa1.1666702934.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-25T13:04:02","name":"[RFC] RISC-V: Allocate \"various\" operand type","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6a8e7a71acccd0efb9789dfb3edfa307e83bdaa1.1666702934.git.research_trasio@irq.a4lg.com/mbox/"},{"id":11062,"url":"https://patchwork.plctlab.org/api/1.2/patches/11062/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jAhwbXhxJHL66v@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-26T05:07:19","name":"PR29720, objdump -S crashes if build-id is missing","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jAhwbXhxJHL66v@squeak.grove.modra.org/mbox/"},{"id":11063,"url":"https://patchwork.plctlab.org/api/1.2/patches/11063/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jAxD+NxpMIah6s@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-26T05:08:20","name":"som.c buffer overflow","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jAxD+NxpMIah6s@squeak.grove.modra.org/mbox/"},{"id":11064,"url":"https://patchwork.plctlab.org/api/1.2/patches/11064/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jBYw4lfRQfOZhi@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-26T05:10:59","name":"som.c reloc sanity checking","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jBYw4lfRQfOZhi@squeak.grove.modra.org/mbox/"},{"id":11080,"url":"https://patchwork.plctlab.org/api/1.2/patches/11080/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jY7hygm01PelCY@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-26T06:51:26","name":"segfault in objdump.c reloc_at","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jY7hygm01PelCY@squeak.grove.modra.org/mbox/"},{"id":11081,"url":"https://patchwork.plctlab.org/api/1.2/patches/11081/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jZWIeIvCCYm9/g@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-26T06:53:12","name":"Correct ELF reloc size sanity check","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jZWIeIvCCYm9/g@squeak.grove.modra.org/mbox/"},{"id":11082,"url":"https://patchwork.plctlab.org/api/1.2/patches/11082/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221026070009.3663574-1-ysato@users.sourceforge.jp/","msgid":"<20221026070009.3663574-1-ysato@users.sourceforge.jp>","list_archive_url":null,"date":"2022-10-26T07:00:09","name":"opcodes: RX fix invalid output.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221026070009.3663574-1-ysato@users.sourceforge.jp/mbox/"},{"id":11089,"url":"https://patchwork.plctlab.org/api/1.2/patches/11089/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jhW48kuVC8Ig2d@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-26T07:27:23","name":"buffer overflow in _bfd_XX_print_ce_compressed_pdata","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jhW48kuVC8Ig2d@squeak.grove.modra.org/mbox/"},{"id":11157,"url":"https://patchwork.plctlab.org/api/1.2/patches/11157/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c52dbd16-7e1b-c356-7a92-1ff089564ef7@suse.cz/","msgid":"","list_archive_url":null,"date":"2022-10-26T08:47:09","name":"tests: use canonical option name","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c52dbd16-7e1b-c356-7a92-1ff089564ef7@suse.cz/mbox/"},{"id":11526,"url":"https://patchwork.plctlab.org/api/1.2/patches/11526/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027031915.4013-1-lifang_xia@linux.alibaba.com/","msgid":"<20221027031915.4013-1-lifang_xia@linux.alibaba.com>","list_archive_url":null,"date":"2022-10-27T03:19:15","name":"[v2] RISC-V: Optimize relax of GP/call with max_alignment.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027031915.4013-1-lifang_xia@linux.alibaba.com/mbox/"},{"id":11619,"url":"https://patchwork.plctlab.org/api/1.2/patches/11619/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9df9d9e5bb4c7594b76c40613a349b4d2364e9c5.1666854355.git.research_trasio@irq.a4lg.com/","msgid":"<9df9d9e5bb4c7594b76c40613a349b4d2364e9c5.1666854355.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-27T07:06:01","name":"include: Define macro to ignore -Wdeprecated-declarations on GCC","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9df9d9e5bb4c7594b76c40613a349b4d2364e9c5.1666854355.git.research_trasio@irq.a4lg.com/mbox/"},{"id":11627,"url":"https://patchwork.plctlab.org/api/1.2/patches/11627/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1o06O9Pp8ncCsOw@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-27T07:36:08","name":"Fuzzed files in archives","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1o06O9Pp8ncCsOw@squeak.grove.modra.org/mbox/"},{"id":11658,"url":"https://patchwork.plctlab.org/api/1.2/patches/11658/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027084808.37252-1-nelson@rivosinc.com/","msgid":"<20221027084808.37252-1-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-10-27T08:48:08","name":"[committed] RISC-V: Fix build failures for -Werror=sign-compare.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027084808.37252-1-nelson@rivosinc.com/mbox/"},{"id":11921,"url":"https://patchwork.plctlab.org/api/1.2/patches/11921/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027190052.10536-1-mark@harmstone.com/","msgid":"<20221027190052.10536-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-27T19:00:51","name":"[1/2] ld: Add section header stream to PDB files","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027190052.10536-1-mark@harmstone.com/mbox/"},{"id":11922,"url":"https://patchwork.plctlab.org/api/1.2/patches/11922/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027190052.10536-2-mark@harmstone.com/","msgid":"<20221027190052.10536-2-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-27T19:00:52","name":"[2/2] ld: Add publics stream to PDB files","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027190052.10536-2-mark@harmstone.com/mbox/"},{"id":11965,"url":"https://patchwork.plctlab.org/api/1.2/patches/11965/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027202719.32497-1-palmer@rivosinc.com/","msgid":"<20221027202719.32497-1-palmer@rivosinc.com>","list_archive_url":null,"date":"2022-10-27T20:27:18","name":"[1/2] gas: NEWS: Add a missing newline","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027202719.32497-1-palmer@rivosinc.com/mbox/"},{"id":11966,"url":"https://patchwork.plctlab.org/api/1.2/patches/11966/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027202719.32497-2-palmer@rivosinc.com/","msgid":"<20221027202719.32497-2-palmer@rivosinc.com>","list_archive_url":null,"date":"2022-10-27T20:27:19","name":"[2/2] gas: NEWS: Note support for RISC-V Zawrs","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027202719.32497-2-palmer@rivosinc.com/mbox/"},{"id":12016,"url":"https://patchwork.plctlab.org/api/1.2/patches/12016/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/21ec9a18-fa89-0828-f625-499680022ec7@linux.ibm.com/","msgid":"<21ec9a18-fa89-0828-f625-499680022ec7@linux.ibm.com>","list_archive_url":null,"date":"2022-10-28T00:35:19","name":"[COMMITTED] PowerPC: Add support for RFC02653 - Dense Math Facility","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/21ec9a18-fa89-0828-f625-499680022ec7@linux.ibm.com/mbox/"},{"id":12017,"url":"https://patchwork.plctlab.org/api/1.2/patches/12017/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fd94047d-a070-45a6-3840-c105391718e0@linux.ibm.com/","msgid":"","list_archive_url":null,"date":"2022-10-28T00:37:18","name":"[COMMITTED] PowerPC: Add support for RFC02658 - MMA+ Outer-Product, Instructions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fd94047d-a070-45a6-3840-c105391718e0@linux.ibm.com/mbox/"},{"id":12122,"url":"https://patchwork.plctlab.org/api/1.2/patches/12122/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ac4f3f3c7115a824f73aca6935789b14d33c9a58.1666939920.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-28T06:53:02","name":"RISC-V: Fix build failure for -Werror=maybe-uninitialized","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ac4f3f3c7115a824f73aca6935789b14d33c9a58.1666939920.git.research_trasio@irq.a4lg.com/mbox/"},{"id":12181,"url":"https://patchwork.plctlab.org/api/1.2/patches/12181/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221028093840.19164-1-nelson@rivosinc.com/","msgid":"<20221028093840.19164-1-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-10-28T09:38:40","name":"RISC-V: Added SiFive custom cache control extensions.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221028093840.19164-1-nelson@rivosinc.com/mbox/"},{"id":12211,"url":"https://patchwork.plctlab.org/api/1.2/patches/12211/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4a280588-a85b-6ed3-634b-2b9cbc128f86@suse.com/","msgid":"<4a280588-a85b-6ed3-634b-2b9cbc128f86@suse.com>","list_archive_url":null,"date":"2022-10-28T10:06:35","name":"RISC-V/gas: fix build with certain gcc versions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4a280588-a85b-6ed3-634b-2b9cbc128f86@suse.com/mbox/"},{"id":12249,"url":"https://patchwork.plctlab.org/api/1.2/patches/12249/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/eb0e1bff-675e-72db-b8b1-b0f0e50b7121@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-28T12:35:35","name":"x86: minor improvements to optimize_imm() (part III)","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/eb0e1bff-675e-72db-b8b1-b0f0e50b7121@suse.com/mbox/"},{"id":12382,"url":"https://patchwork.plctlab.org/api/1.2/patches/12382/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/17f57574936af82be381a1451eac56b3709b60bb.1666968673.git.research_trasio@irq.a4lg.com/","msgid":"<17f57574936af82be381a1451eac56b3709b60bb.1666968673.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-28T14:52:12","name":"RISC-V: Emit mapping symbol with ISA string if non-default arch is used","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/17f57574936af82be381a1451eac56b3709b60bb.1666968673.git.research_trasio@irq.a4lg.com/mbox/"},{"id":12627,"url":"https://patchwork.plctlab.org/api/1.2/patches/12627/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221029034432.49859-1-nelson@rivosinc.com/","msgid":"<20221029034432.49859-1-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-10-29T03:44:32","name":"[committed] RISC-V: Always generate mapping symbols at the start of the sections.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221029034432.49859-1-nelson@rivosinc.com/mbox/"},{"id":12629,"url":"https://patchwork.plctlab.org/api/1.2/patches/12629/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1yxgzNJg5M48uPI@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-29T04:52:19","name":"NULL dereference read in som_write_object_contents","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1yxgzNJg5M48uPI@squeak.grove.modra.org/mbox/"},{"id":12630,"url":"https://patchwork.plctlab.org/api/1.2/patches/12630/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1yxnSHLY+FeB5DQ@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-29T04:52:45","name":"Fix small objcopy memory leak","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1yxnSHLY+FeB5DQ@squeak.grove.modra.org/mbox/"},{"id":12631,"url":"https://patchwork.plctlab.org/api/1.2/patches/12631/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1yxxfpJz+Jx4KTh@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-29T04:53:25","name":"pef: sanity check before malloc","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1yxxfpJz+Jx4KTh@squeak.grove.modra.org/mbox/"},{"id":12950,"url":"https://patchwork.plctlab.org/api/1.2/patches/12950/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-2-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-2-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:36","name":"[V3,01/15] sframe.h: Add SFrame format definition","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-2-indu.bhagat@oracle.com/mbox/"},{"id":12952,"url":"https://patchwork.plctlab.org/api/1.2/patches/12952/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-3-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-3-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:37","name":"[V3,02/15] gas: add new command line option --gsframe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-3-indu.bhagat@oracle.com/mbox/"},{"id":12951,"url":"https://patchwork.plctlab.org/api/1.2/patches/12951/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-4-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-4-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:38","name":"[V3,03/15] gas: generate .sframe from CFI directives","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-4-indu.bhagat@oracle.com/mbox/"},{"id":12956,"url":"https://patchwork.plctlab.org/api/1.2/patches/12956/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-5-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-5-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:39","name":"[V3,04/15] gas: testsuite: add new tests for SFrame unwind info","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-5-indu.bhagat@oracle.com/mbox/"},{"id":12955,"url":"https://patchwork.plctlab.org/api/1.2/patches/12955/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-6-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-6-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:40","name":"[V3,05/15] libsframe: add the SFrame library","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-6-indu.bhagat@oracle.com/mbox/"},{"id":12959,"url":"https://patchwork.plctlab.org/api/1.2/patches/12959/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-7-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-7-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:41","name":"[V3,06/15] bfd: linker: merge .sframe sections","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-7-indu.bhagat@oracle.com/mbox/"},{"id":12961,"url":"https://patchwork.plctlab.org/api/1.2/patches/12961/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-8-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-8-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:42","name":"[V3,07/15] readelf/objdump: support for SFrame section","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-8-indu.bhagat@oracle.com/mbox/"},{"id":12962,"url":"https://patchwork.plctlab.org/api/1.2/patches/12962/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-9-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-9-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:43","name":"[V3,08/15] unwinder: generate backtrace using SFrame format","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-9-indu.bhagat@oracle.com/mbox/"},{"id":12963,"url":"https://patchwork.plctlab.org/api/1.2/patches/12963/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-10-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-10-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:44","name":"[V3,09/15] unwinder: Add SFrame unwinder tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-10-indu.bhagat@oracle.com/mbox/"},{"id":12964,"url":"https://patchwork.plctlab.org/api/1.2/patches/12964/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-11-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-11-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:45","name":"[V3,10/15] gdb: sim: buildsystem changes to accommodate libsframe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-11-indu.bhagat@oracle.com/mbox/"},{"id":12957,"url":"https://patchwork.plctlab.org/api/1.2/patches/12957/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-12-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-12-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:46","name":"[V3,11/15] libctf: add libsframe to LDFLAGS and LIBS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-12-indu.bhagat@oracle.com/mbox/"},{"id":12960,"url":"https://patchwork.plctlab.org/api/1.2/patches/12960/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-13-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-13-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:47","name":"[V3,12/15] src-release.sh: Add libsframe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-13-indu.bhagat@oracle.com/mbox/"},{"id":12953,"url":"https://patchwork.plctlab.org/api/1.2/patches/12953/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-14-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-14-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:48","name":"[V3,13/15] binutils/NEWS: add text for SFrame support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-14-indu.bhagat@oracle.com/mbox/"},{"id":12954,"url":"https://patchwork.plctlab.org/api/1.2/patches/12954/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-15-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-15-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:49","name":"[V3,14/15] gas/NEWS: add text about new command line option and SFrame support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-15-indu.bhagat@oracle.com/mbox/"},{"id":12958,"url":"https://patchwork.plctlab.org/api/1.2/patches/12958/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-16-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-16-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:50","name":"[V3,15/15] doc: add SFrame spec file","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-16-indu.bhagat@oracle.com/mbox/"},{"id":12988,"url":"https://patchwork.plctlab.org/api/1.2/patches/12988/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y15KFY32CyFhh/+u@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-30T09:55:33","name":"Pool section entries for DWP version 1","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y15KFY32CyFhh/+u@squeak.grove.modra.org/mbox/"},{"id":13076,"url":"https://patchwork.plctlab.org/api/1.2/patches/13076/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031001554.14615-1-mark@harmstone.com/","msgid":"<20221031001554.14615-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-31T00:15:52","name":"[v2,1/3] ld: Use %E in einfo in pdb.c","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031001554.14615-1-mark@harmstone.com/mbox/"},{"id":13078,"url":"https://patchwork.plctlab.org/api/1.2/patches/13078/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031001554.14615-2-mark@harmstone.com/","msgid":"<20221031001554.14615-2-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-31T00:15:53","name":"[v2,2/3] ld: Add section header stream to PDB files","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031001554.14615-2-mark@harmstone.com/mbox/"},{"id":13077,"url":"https://patchwork.plctlab.org/api/1.2/patches/13077/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031001554.14615-3-mark@harmstone.com/","msgid":"<20221031001554.14615-3-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-31T00:15:54","name":"[v2,3/3] ld: Add publics stream to PDB files","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031001554.14615-3-mark@harmstone.com/mbox/"},{"id":13106,"url":"https://patchwork.plctlab.org/api/1.2/patches/13106/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031030507.35588-2-haochen.jiang@intel.com/","msgid":"<20221031030507.35588-2-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-31T03:05:02","name":"[1/6] Support Intel AVX-IFMA","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031030507.35588-2-haochen.jiang@intel.com/mbox/"},{"id":13105,"url":"https://patchwork.plctlab.org/api/1.2/patches/13105/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031030507.35588-3-haochen.jiang@intel.com/","msgid":"<20221031030507.35588-3-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-31T03:05:03","name":"[2/6] Support Intel AVX-VNNI-INT8","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031030507.35588-3-haochen.jiang@intel.com/mbox/"},{"id":13103,"url":"https://patchwork.plctlab.org/api/1.2/patches/13103/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031030507.35588-4-haochen.jiang@intel.com/","msgid":"<20221031030507.35588-4-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-31T03:05:04","name":"[3/6] Support Intel CMPccXADD","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031030507.35588-4-haochen.jiang@intel.com/mbox/"},{"id":13101,"url":"https://patchwork.plctlab.org/api/1.2/patches/13101/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031030507.35588-5-haochen.jiang@intel.com/","msgid":"<20221031030507.35588-5-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-31T03:05:05","name":"[4/6] Add handler for more i386_cpu_flags","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031030507.35588-5-haochen.jiang@intel.com/mbox/"},{"id":13104,"url":"https://patchwork.plctlab.org/api/1.2/patches/13104/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031030507.35588-6-haochen.jiang@intel.com/","msgid":"<20221031030507.35588-6-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-31T03:05:06","name":"[5/6] Support Intel WRMSRNS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031030507.35588-6-haochen.jiang@intel.com/mbox/"},{"id":13102,"url":"https://patchwork.plctlab.org/api/1.2/patches/13102/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031030507.35588-7-haochen.jiang@intel.com/","msgid":"<20221031030507.35588-7-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-31T03:05:07","name":"[6/6] Support Intel MSRLIST","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031030507.35588-7-haochen.jiang@intel.com/mbox/"},{"id":13120,"url":"https://patchwork.plctlab.org/api/1.2/patches/13120/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031060601.38460-2-haochen.jiang@intel.com/","msgid":"<20221031060601.38460-2-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-31T06:06:00","name":"[1/2] i386: Add and ","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031060601.38460-2-haochen.jiang@intel.com/mbox/"},{"id":13121,"url":"https://patchwork.plctlab.org/api/1.2/patches/13121/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031060601.38460-3-haochen.jiang@intel.com/","msgid":"<20221031060601.38460-3-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-31T06:06:01","name":"[2/2] Support Intel AVX-NE-CONVERT","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031060601.38460-3-haochen.jiang@intel.com/mbox/"},{"id":13188,"url":"https://patchwork.plctlab.org/api/1.2/patches/13188/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9f6f8888-4dc1-a6b0-0590-35fc8a276369@suse.com/","msgid":"<9f6f8888-4dc1-a6b0-0590-35fc8a276369@suse.com>","list_archive_url":null,"date":"2022-10-31T10:18:20","name":"x86: drop bogus Tbyte","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9f6f8888-4dc1-a6b0-0590-35fc8a276369@suse.com/mbox/"},{"id":13213,"url":"https://patchwork.plctlab.org/api/1.2/patches/13213/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4f1aac95-fea5-2279-cb18-dfcdb51a2589@arm.com/","msgid":"<4f1aac95-fea5-2279-cb18-dfcdb51a2589@arm.com>","list_archive_url":null,"date":"2022-10-31T11:14:44","name":"aarch64: Add support for Common Short Sequence Compression extension","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4f1aac95-fea5-2279-cb18-dfcdb51a2589@arm.com/mbox/"}],"public":true,"mbox":"https://patchwork.plctlab.org/bundle/patchwork-bot/binutils-gdb_2022-10/mbox/"},{"id":7,"url":"https://patchwork.plctlab.org/api/1.2/bundles/7/","web_url":"https://patchwork.plctlab.org/bundle/patchwork-bot/binutils-gdb_2022-09/","project":{"id":2,"url":"https://patchwork.plctlab.org/api/1.2/projects/2/","name":"binutils-gdb","link_name":"binutils-gdb","list_id":"binutils.sourceware.org","list_email":"binutils@sourceware.org","web_url":"https://github.com/wangliu-iscas/Patchwork-Bundles/blob/main/binutils-gdb.md","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"name":"binutils-gdb_2022-09","owner":{"id":3,"url":"https://patchwork.plctlab.org/api/1.2/users/3/","username":"patchwork-bot","first_name":"","last_name":"","email":"ouuuleilei@gmail.com"},"patches":[{"id":1573,"url":"https://patchwork.plctlab.org/api/1.2/patches/1573/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930073211.2634-1-jiawei@iscas.ac.cn/","msgid":"<20220930073211.2634-1-jiawei@iscas.ac.cn>","list_archive_url":null,"date":"2022-09-30T07:32:11","name":"[V2] RISC-V: Add Smepmp CSR '\''mseccfg'\'' define and testcases.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930073211.2634-1-jiawei@iscas.ac.cn/mbox/"},{"id":1577,"url":"https://patchwork.plctlab.org/api/1.2/patches/1577/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/76fa0c3c-2303-ebdf-a765-ac4731581517@suse.com/","msgid":"<76fa0c3c-2303-ebdf-a765-ac4731581517@suse.com>","list_archive_url":null,"date":"2022-09-30T08:54:18","name":"objcopy: avoid \"shadowing\" of remove() function name","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/76fa0c3c-2303-ebdf-a765-ac4731581517@suse.com/mbox/"},{"id":1579,"url":"https://patchwork.plctlab.org/api/1.2/patches/1579/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930085852.71213-1-nelson@rivosinc.com/","msgid":"<20220930085852.71213-1-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-09-30T08:58:51","name":"[1/2] RISC-V: Output mapping symbols with ISA string.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930085852.71213-1-nelson@rivosinc.com/mbox/"},{"id":1578,"url":"https://patchwork.plctlab.org/api/1.2/patches/1578/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930085852.71213-2-nelson@rivosinc.com/","msgid":"<20220930085852.71213-2-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-09-30T08:58:52","name":"[2/2] RISC-V: Refer mapping symbol to R_RISCV_RELAX for rvc relaxations.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930085852.71213-2-nelson@rivosinc.com/mbox/"},{"id":1581,"url":"https://patchwork.plctlab.org/api/1.2/patches/1581/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930092058.71286-1-nelson@rivosinc.com/","msgid":"<20220930092058.71286-1-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-09-30T09:20:57","name":"[1/2] RISC-V: Output mapping symbols with ISA string.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930092058.71286-1-nelson@rivosinc.com/mbox/"},{"id":1580,"url":"https://patchwork.plctlab.org/api/1.2/patches/1580/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930092058.71286-2-nelson@rivosinc.com/","msgid":"<20220930092058.71286-2-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-09-30T09:20:58","name":"[2/2] RISC-V: Refer mapping symbol to R_RISCV_RELAX for rvc relaxations.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930092058.71286-2-nelson@rivosinc.com/mbox/"},{"id":1582,"url":"https://patchwork.plctlab.org/api/1.2/patches/1582/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5874dd79-0cf5-d65c-7ea2-13adfc799c0f@suse.com/","msgid":"<5874dd79-0cf5-d65c-7ea2-13adfc799c0f@suse.com>","list_archive_url":null,"date":"2022-09-30T09:41:29","name":"RISC-V: fix build after \"Add support for arbitrary immediate encoding formats\"","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5874dd79-0cf5-d65c-7ea2-13adfc799c0f@suse.com/mbox/"},{"id":1583,"url":"https://patchwork.plctlab.org/api/1.2/patches/1583/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/57d8ac2a-5757-3776-9924-99c17ca69938@suse.com/","msgid":"<57d8ac2a-5757-3776-9924-99c17ca69938@suse.com>","list_archive_url":null,"date":"2022-09-30T09:42:08","name":"RISC-V: fallout from \"re-arrange opcode table for consistent alias handling\"","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/57d8ac2a-5757-3776-9924-99c17ca69938@suse.com/mbox/"},{"id":1584,"url":"https://patchwork.plctlab.org/api/1.2/patches/1584/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e76ef8f7-72b9-5103-cb43-9608af01d017@suse.com/","msgid":"","list_archive_url":null,"date":"2022-09-30T09:42:50","name":"RISC-V: don'\''t cast expressions'\'' X_add_number to long in diagnostics","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e76ef8f7-72b9-5103-cb43-9608af01d017@suse.com/mbox/"},{"id":1585,"url":"https://patchwork.plctlab.org/api/1.2/patches/1585/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/61355429-24b3-17d0-ab03-6fa57ee861d5@suse.cz/","msgid":"<61355429-24b3-17d0-ab03-6fa57ee861d5@suse.cz>","list_archive_url":null,"date":"2022-09-30T09:48:52","name":"[RFC] add --enable-zstd-compressed-debug-sections configure option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/61355429-24b3-17d0-ab03-6fa57ee861d5@suse.cz/mbox/"},{"id":1586,"url":"https://patchwork.plctlab.org/api/1.2/patches/1586/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930103919.323690-1-christoph.muellner@vrull.eu/","msgid":"<20220930103919.323690-1-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2022-09-30T10:39:19","name":"RISC-V: Eliminate long-casts of X_add_number in diagnostics","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930103919.323690-1-christoph.muellner@vrull.eu/mbox/"},{"id":1590,"url":"https://patchwork.plctlab.org/api/1.2/patches/1590/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/DM6PR12MB4219C943049C6D883DEA3E55E7569@DM6PR12MB4219.namprd12.prod.outlook.com/","msgid":"","list_archive_url":null,"date":"2022-09-30T11:41:37","name":"[V2] Ignore DWARF debug information for -gsplit-dwarf with dwarf-5.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/DM6PR12MB4219C943049C6D883DEA3E55E7569@DM6PR12MB4219.namprd12.prod.outlook.com/mbox/"},{"id":1591,"url":"https://patchwork.plctlab.org/api/1.2/patches/1591/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c10321f9-d289-ef84-d263-bc278fb3d31b@suse.com/","msgid":"","list_archive_url":null,"date":"2022-09-30T11:59:04","name":"[1/4] RISC-V/gas: drop riscv_subsets static variable","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c10321f9-d289-ef84-d263-bc278fb3d31b@suse.com/mbox/"},{"id":1593,"url":"https://patchwork.plctlab.org/api/1.2/patches/1593/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3244eea0-c18c-e49a-4588-d69423130226@suse.com/","msgid":"<3244eea0-c18c-e49a-4588-d69423130226@suse.com>","list_archive_url":null,"date":"2022-09-30T11:59:23","name":"[2/4] RISC-V/gas: drop stray call to install_insn()","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3244eea0-c18c-e49a-4588-d69423130226@suse.com/mbox/"},{"id":1592,"url":"https://patchwork.plctlab.org/api/1.2/patches/1592/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/385d01fd-7e57-1f3f-1bae-30aa0c313d63@suse.com/","msgid":"<385d01fd-7e57-1f3f-1bae-30aa0c313d63@suse.com>","list_archive_url":null,"date":"2022-09-30T11:59:45","name":"[3/4] RISC-V/gas: don'\''t open-code insn_length()","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/385d01fd-7e57-1f3f-1bae-30aa0c313d63@suse.com/mbox/"},{"id":1594,"url":"https://patchwork.plctlab.org/api/1.2/patches/1594/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f5757acf-7b90-a0e3-5eea-3b97cc226930@suse.com/","msgid":"","list_archive_url":null,"date":"2022-09-30T12:00:12","name":"[4/4] RISC-V/gas: allow generating up to 176-bit instructions with .insn","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f5757acf-7b90-a0e3-5eea-3b97cc226930@suse.com/mbox/"},{"id":1596,"url":"https://patchwork.plctlab.org/api/1.2/patches/1596/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930140503.38233-1-chigot@adacore.com/","msgid":"<20220930140503.38233-1-chigot@adacore.com>","list_archive_url":null,"date":"2022-09-30T14:05:03","name":"ld/testsuite: consistently add board_ldflags when linking with GCC","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930140503.38233-1-chigot@adacore.com/mbox/"}],"public":true,"mbox":"https://patchwork.plctlab.org/bundle/patchwork-bot/binutils-gdb_2022-09/mbox/"},{"id":9,"url":"https://patchwork.plctlab.org/api/1.2/bundles/9/","web_url":"https://patchwork.plctlab.org/bundle/patchwork-bot/binutils-gdb_2022-11/","project":{"id":2,"url":"https://patchwork.plctlab.org/api/1.2/projects/2/","name":"binutils-gdb","link_name":"binutils-gdb","list_id":"binutils.sourceware.org","list_email":"binutils@sourceware.org","web_url":"https://github.com/wangliu-iscas/Patchwork-Bundles/blob/main/binutils-gdb.md","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"name":"binutils-gdb_2022-11","owner":{"id":3,"url":"https://patchwork.plctlab.org/api/1.2/users/3/","username":"patchwork-bot","first_name":"","last_name":"","email":"ouuuleilei@gmail.com"},"patches":[{"id":13337,"url":"https://patchwork.plctlab.org/api/1.2/patches/13337/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031160625.684434-1-hjl.tools@gmail.com/","msgid":"<20221031160625.684434-1-hjl.tools@gmail.com>","list_archive_url":null,"date":"2022-10-31T16:06:25","name":"x86: Silence GCC 12 warning on tc-i386.c","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031160625.684434-1-hjl.tools@gmail.com/mbox/"},{"id":13350,"url":"https://patchwork.plctlab.org/api/1.2/patches/13350/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c8d25b29-37fe-9623-a799-e67e1f991743@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-31T17:00:56","name":"x86: simplify expressions in update_imm()","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c8d25b29-37fe-9623-a799-e67e1f991743@suse.com/mbox/"},{"id":13487,"url":"https://patchwork.plctlab.org/api/1.2/patches/13487/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/CAMe9rOohVjin92PTeeiu_dvAtzYJn4dGtu5E=OxYfbyteraZWw@mail.gmail.com/","msgid":"","list_archive_url":null,"date":"2022-11-01T00:08:04","name":"binutils: Run PR binutils/26160 test","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/CAMe9rOohVjin92PTeeiu_dvAtzYJn4dGtu5E=OxYfbyteraZWw@mail.gmail.com/mbox/"},{"id":13621,"url":"https://patchwork.plctlab.org/api/1.2/patches/13621/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221101105724.1527333-1-aburgess@redhat.com/","msgid":"<20221101105724.1527333-1-aburgess@redhat.com>","list_archive_url":null,"date":"2022-11-01T10:57:24","name":"[PUSHED] opcodes/arm: silence compiler warning about uninitialized variable use","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221101105724.1527333-1-aburgess@redhat.com/mbox/"},{"id":13628,"url":"https://patchwork.plctlab.org/api/1.2/patches/13628/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221101111802.1532080-1-aburgess@redhat.com/","msgid":"<20221101111802.1532080-1-aburgess@redhat.com>","list_archive_url":null,"date":"2022-11-01T11:18:02","name":"[PUSHED] opcodes/arm: don'\''t pass non-string literal to printf like function","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221101111802.1532080-1-aburgess@redhat.com/mbox/"},{"id":13747,"url":"https://patchwork.plctlab.org/api/1.2/patches/13747/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/yw8jbkpqk6vw.fsf@arm.com/","msgid":"","list_archive_url":null,"date":"2022-11-01T15:54:11","name":"[Binutils-2.39,backport,GAS] arm: Use DWARF numbering convention for pseudo-register representation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/yw8jbkpqk6vw.fsf@arm.com/mbox/"},{"id":13993,"url":"https://patchwork.plctlab.org/api/1.2/patches/13993/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221102020752.24441-1-mark@harmstone.com/","msgid":"<20221102020752.24441-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-11-02T02:07:52","name":"ld: Add module information substream to PDB files","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221102020752.24441-1-mark@harmstone.com/mbox/"},{"id":14028,"url":"https://patchwork.plctlab.org/api/1.2/patches/14028/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221102050430.1053-1-nelson@rivosinc.com/","msgid":"<20221102050430.1053-1-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-11-02T05:04:30","name":"[committed] RISC-V: Fixed the missing $x+arch when adding odd paddings for alignment.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221102050430.1053-1-nelson@rivosinc.com/mbox/"},{"id":14043,"url":"https://patchwork.plctlab.org/api/1.2/patches/14043/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221102063046.31551-1-rjiejie@linux.alibaba.com/","msgid":"<20221102063046.31551-1-rjiejie@linux.alibaba.com>","list_archive_url":null,"date":"2022-11-02T06:30:46","name":"gas/doc/internals.texi: fix typo","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221102063046.31551-1-rjiejie@linux.alibaba.com/mbox/"},{"id":14069,"url":"https://patchwork.plctlab.org/api/1.2/patches/14069/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221102080112.33378-1-rjiejie@linux.alibaba.com/","msgid":"<20221102080112.33378-1-rjiejie@linux.alibaba.com>","list_archive_url":null,"date":"2022-11-02T08:01:12","name":"[v2] Support multiple .eh_frame sections","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221102080112.33378-1-rjiejie@linux.alibaba.com/mbox/"},{"id":14409,"url":"https://patchwork.plctlab.org/api/1.2/patches/14409/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221102172923.4009281-1-christophe.lyon@arm.com/","msgid":"<20221102172923.4009281-1-christophe.lyon@arm.com>","list_archive_url":null,"date":"2022-11-02T17:29:23","name":"arm: PR 29739 Fix typo where '\''; '\'' should not have been replaced with '\''@'\''","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221102172923.4009281-1-christophe.lyon@arm.com/mbox/"},{"id":14588,"url":"https://patchwork.plctlab.org/api/1.2/patches/14588/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221103020409.37322-1-rjiejie@linux.alibaba.com/","msgid":"<20221103020409.37322-1-rjiejie@linux.alibaba.com>","list_archive_url":null,"date":"2022-11-03T02:04:09","name":"[v3] Support multiple .eh_frame sections","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221103020409.37322-1-rjiejie@linux.alibaba.com/mbox/"},{"id":14602,"url":"https://patchwork.plctlab.org/api/1.2/patches/14602/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221103024604.614-1-mark@harmstone.com/","msgid":"<20221103024604.614-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-11-03T02:46:04","name":"[v2] ld: Add module information substream to PDB files","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221103024604.614-1-mark@harmstone.com/mbox/"},{"id":14706,"url":"https://patchwork.plctlab.org/api/1.2/patches/14706/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221103071519.3510462-1-luis.machado@arm.com/","msgid":"<20221103071519.3510462-1-luis.machado@arm.com>","list_archive_url":null,"date":"2022-11-03T07:15:19","name":"[opcodes/arm] Fix potential null pointer dereferences","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221103071519.3510462-1-luis.machado@arm.com/mbox/"},{"id":14840,"url":"https://patchwork.plctlab.org/api/1.2/patches/14840/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/283a86ebf0941f0f63dc1a590ec3d547bd5d69e8.1667478033.git.research_trasio@irq.a4lg.com/","msgid":"<283a86ebf0941f0f63dc1a590ec3d547bd5d69e8.1667478033.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-03T12:26:28","name":"[REVIEW,ONLY,1/2] NEAR-RATIFICATION RISC-V: Add '\''Ssstateen'\'' extension and its CSRs","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/283a86ebf0941f0f63dc1a590ec3d547bd5d69e8.1667478033.git.research_trasio@irq.a4lg.com/mbox/"},{"id":14841,"url":"https://patchwork.plctlab.org/api/1.2/patches/14841/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8083ad9d5339afdeb7f1ba88ee6af0665dcc76d5.1667478033.git.research_trasio@irq.a4lg.com/","msgid":"<8083ad9d5339afdeb7f1ba88ee6af0665dcc76d5.1667478033.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-03T12:26:29","name":"[REVIEW,ONLY,2/2] NEAR-RATIFICATION RISC-V: Add platform property/capability extensions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8083ad9d5339afdeb7f1ba88ee6af0665dcc76d5.1667478033.git.research_trasio@irq.a4lg.com/mbox/"},{"id":14894,"url":"https://patchwork.plctlab.org/api/1.2/patches/14894/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e53fbf5025e59fe6a3481b9c1fe37e4f6cf6e03d.1667483581.git.aburgess@redhat.com/","msgid":"","list_archive_url":null,"date":"2022-11-03T13:58:12","name":"[1/2] opcodes/mips: use .word/.short for undefined instructions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e53fbf5025e59fe6a3481b9c1fe37e4f6cf6e03d.1667483581.git.aburgess@redhat.com/mbox/"},{"id":14893,"url":"https://patchwork.plctlab.org/api/1.2/patches/14893/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ca81edb86580566b1641ad140eb2bed385160ab7.1667483581.git.aburgess@redhat.com/","msgid":"","list_archive_url":null,"date":"2022-11-03T13:58:13","name":"[2/2] libopcodes/mips: add support for disassembler styling","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ca81edb86580566b1641ad140eb2bed385160ab7.1667483581.git.aburgess@redhat.com/mbox/"},{"id":15465,"url":"https://patchwork.plctlab.org/api/1.2/patches/15465/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/926e5154-b40b-9df8-d770-a8bf7d40e40e@suse.com/","msgid":"<926e5154-b40b-9df8-d770-a8bf7d40e40e@suse.com>","list_archive_url":null,"date":"2022-11-04T10:50:38","name":"[v6,1/7] x86: constify parse_insn()'\''s input","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/926e5154-b40b-9df8-d770-a8bf7d40e40e@suse.com/mbox/"},{"id":15466,"url":"https://patchwork.plctlab.org/api/1.2/patches/15466/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/07ef67fd-752c-ad1f-b8cb-4eaec1f420fc@suse.com/","msgid":"<07ef67fd-752c-ad1f-b8cb-4eaec1f420fc@suse.com>","list_archive_url":null,"date":"2022-11-04T10:51:34","name":"[v6,2/7] x86: re-work insn/suffix recognition","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/07ef67fd-752c-ad1f-b8cb-4eaec1f420fc@suse.com/mbox/"},{"id":15467,"url":"https://patchwork.plctlab.org/api/1.2/patches/15467/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ee8fd655-19a5-d944-0f5e-4351b88a59f9@suse.com/","msgid":"","list_archive_url":null,"date":"2022-11-04T10:52:02","name":"[v6,3/7] ix86: don'\''t recognize/derive Q suffix in the common case","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ee8fd655-19a5-d944-0f5e-4351b88a59f9@suse.com/mbox/"},{"id":15468,"url":"https://patchwork.plctlab.org/api/1.2/patches/15468/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/15ab2cf5-f1ac-e882-c415-6318f1bcc7f0@suse.com/","msgid":"<15ab2cf5-f1ac-e882-c415-6318f1bcc7f0@suse.com>","list_archive_url":null,"date":"2022-11-04T10:52:31","name":"[v6,4/7] x86-64: allow HLE store of accumulator to absolute 32-bit address","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/15ab2cf5-f1ac-e882-c415-6318f1bcc7f0@suse.com/mbox/"},{"id":15470,"url":"https://patchwork.plctlab.org/api/1.2/patches/15470/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/352d1e49-ac9f-ee86-7e9d-74f79744268b@suse.com/","msgid":"<352d1e49-ac9f-ee86-7e9d-74f79744268b@suse.com>","list_archive_url":null,"date":"2022-11-04T10:53:14","name":"[v6,5/7] x86: move bad-use-of-TLS-reloc check","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/352d1e49-ac9f-ee86-7e9d-74f79744268b@suse.com/mbox/"},{"id":15469,"url":"https://patchwork.plctlab.org/api/1.2/patches/15469/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c1913bf6-7328-e45f-69f1-20da1954af43@suse.com/","msgid":"","list_archive_url":null,"date":"2022-11-04T10:53:52","name":"[v6,6/7] x86: drop (now) stray IsString","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c1913bf6-7328-e45f-69f1-20da1954af43@suse.com/mbox/"},{"id":15471,"url":"https://patchwork.plctlab.org/api/1.2/patches/15471/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2baf6a9d-c1bf-660d-bbca-99b1604f5478@suse.com/","msgid":"<2baf6a9d-c1bf-660d-bbca-99b1604f5478@suse.com>","list_archive_url":null,"date":"2022-11-04T10:54:30","name":"[v6,7/7] x86: further re-work insn/suffix recognition to also cover MOVSX","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2baf6a9d-c1bf-660d-bbca-99b1604f5478@suse.com/mbox/"},{"id":15472,"url":"https://patchwork.plctlab.org/api/1.2/patches/15472/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104110132.694984-1-aburgess@redhat.com/","msgid":"<20221104110132.694984-1-aburgess@redhat.com>","list_archive_url":null,"date":"2022-11-04T11:01:32","name":"[PUSHED] opcodes/arm: silence compiler warning about uninitialized variable use","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104110132.694984-1-aburgess@redhat.com/mbox/"},{"id":15473,"url":"https://patchwork.plctlab.org/api/1.2/patches/15473/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104110214.129095-1-christophe.lyon@arm.com/","msgid":"<20221104110214.129095-1-christophe.lyon@arm.com>","list_archive_url":null,"date":"2022-11-04T11:02:14","name":"configure: require libzstd >= 1.4.0","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104110214.129095-1-christophe.lyon@arm.com/mbox/"},{"id":15485,"url":"https://patchwork.plctlab.org/api/1.2/patches/15485/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104115038.8957-1-nelson@rivosinc.com/","msgid":"<20221104115038.8957-1-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-11-04T11:50:37","name":"[1/2] RISC-V: File-level architecture shouldn'\''t be affected by section-level ones.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104115038.8957-1-nelson@rivosinc.com/mbox/"},{"id":15486,"url":"https://patchwork.plctlab.org/api/1.2/patches/15486/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104115038.8957-2-nelson@rivosinc.com/","msgid":"<20221104115038.8957-2-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-11-04T11:50:38","name":"[2/2] RISC-V: Clarify the suppress rule of mapping symbol with architecture string.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104115038.8957-2-nelson@rivosinc.com/mbox/"},{"id":15509,"url":"https://patchwork.plctlab.org/api/1.2/patches/15509/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/cc133c88-9ce9-5e3a-a8f7-ad72766862b9@suse.com/","msgid":"","list_archive_url":null,"date":"2022-11-04T13:12:07","name":"x86: adjust recently introduced testcases","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/cc133c88-9ce9-5e3a-a8f7-ad72766862b9@suse.com/mbox/"},{"id":15679,"url":"https://patchwork.plctlab.org/api/1.2/patches/15679/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104163328.2274371-1-chigot@adacore.com/","msgid":"<20221104163328.2274371-1-chigot@adacore.com>","list_archive_url":null,"date":"2022-11-04T16:33:28","name":"ld/testsuite: skip tests related to -shared when disabled","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104163328.2274371-1-chigot@adacore.com/mbox/"},{"id":15751,"url":"https://patchwork.plctlab.org/api/1.2/patches/15751/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104190216.1352855-1-indu.bhagat@oracle.com/","msgid":"<20221104190216.1352855-1-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-04T19:02:16","name":"[V3.1,11/15] libctf: add libsframe to LDFLAGS and LIBS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104190216.1352855-1-indu.bhagat@oracle.com/mbox/"},{"id":15792,"url":"https://patchwork.plctlab.org/api/1.2/patches/15792/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104205547.3728827-1-hjl.tools@gmail.com/","msgid":"<20221104205547.3728827-1-hjl.tools@gmail.com>","list_archive_url":null,"date":"2022-11-04T20:55:47","name":"i386: Check invalid (%dx) usage","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104205547.3728827-1-hjl.tools@gmail.com/mbox/"},{"id":15794,"url":"https://patchwork.plctlab.org/api/1.2/patches/15794/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104210134.1721620-1-indu.bhagat@oracle.com/","msgid":"<20221104210134.1721620-1-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-04T21:01:34","name":"[V3.2,11/15] libctf: add libsframe to LDFLAGS and LIBS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104210134.1721620-1-indu.bhagat@oracle.com/mbox/"},{"id":15959,"url":"https://patchwork.plctlab.org/api/1.2/patches/15959/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c620070e3e335df2b487d3836e20d251dac37525.1667651354.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-11-05T12:29:07","name":"[01/12] RISC-V: Remove unnecessary empty matching file","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c620070e3e335df2b487d3836e20d251dac37525.1667651354.git.research_trasio@irq.a4lg.com/mbox/"},{"id":15961,"url":"https://patchwork.plctlab.org/api/1.2/patches/15961/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4496235002a396043598ab9755bd8eda5c077b1f.1667651354.git.research_trasio@irq.a4lg.com/","msgid":"<4496235002a396043598ab9755bd8eda5c077b1f.1667651354.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-05T12:29:08","name":"[02/12] RISC-V: Tidy disassembler corner case tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4496235002a396043598ab9755bd8eda5c077b1f.1667651354.git.research_trasio@irq.a4lg.com/mbox/"},{"id":15960,"url":"https://patchwork.plctlab.org/api/1.2/patches/15960/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a9229a2798480f00bf12ac3c435b3ef57f867022.1667651354.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-11-05T12:29:09","name":"[03/12] RISC-V: Tidying related to '\''Zfinx'\'' disassembler test","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a9229a2798480f00bf12ac3c435b3ef57f867022.1667651354.git.research_trasio@irq.a4lg.com/mbox/"},{"id":15962,"url":"https://patchwork.plctlab.org/api/1.2/patches/15962/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6a020edd0e114a003edbaafe1088a040e9fa07e7.1667651354.git.research_trasio@irq.a4lg.com/","msgid":"<6a020edd0e114a003edbaafe1088a040e9fa07e7.1667651354.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-05T12:29:10","name":"[04/12] RISC-V: GAS: Add basic shared test utilities","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6a020edd0e114a003edbaafe1088a040e9fa07e7.1667651354.git.research_trasio@irq.a4lg.com/mbox/"},{"id":15966,"url":"https://patchwork.plctlab.org/api/1.2/patches/15966/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6fc2851a4161edc429089bd2bbd9c2bb4c0c118f.1667651354.git.research_trasio@irq.a4lg.com/","msgid":"<6fc2851a4161edc429089bd2bbd9c2bb4c0c118f.1667651354.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-05T12:29:11","name":"[05/12] RISC-V: Redefine \"nop\" test","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6fc2851a4161edc429089bd2bbd9c2bb4c0c118f.1667651354.git.research_trasio@irq.a4lg.com/mbox/"},{"id":15963,"url":"https://patchwork.plctlab.org/api/1.2/patches/15963/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7311ed3d2429000e18877d7af594890da170a7a3.1667651354.git.research_trasio@irq.a4lg.com/","msgid":"<7311ed3d2429000e18877d7af594890da170a7a3.1667651354.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-05T12:29:12","name":"[06/12] RISC-V: Reorganize/enhance {sign, zero}-extension instructions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7311ed3d2429000e18877d7af594890da170a7a3.1667651354.git.research_trasio@irq.a4lg.com/mbox/"},{"id":15968,"url":"https://patchwork.plctlab.org/api/1.2/patches/15968/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ac99c9696c156207f06c18f2d6bf423c96c5876b.1667651354.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-11-05T12:29:13","name":"[07/12] RISC-V: Combine complex extension error handling tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ac99c9696c156207f06c18f2d6bf423c96c5876b.1667651354.git.research_trasio@irq.a4lg.com/mbox/"},{"id":15970,"url":"https://patchwork.plctlab.org/api/1.2/patches/15970/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9378b9505e3e230e0a690c56e67d253e2a0f5864.1667651354.git.research_trasio@irq.a4lg.com/","msgid":"<9378b9505e3e230e0a690c56e67d253e2a0f5864.1667651354.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-05T12:29:14","name":"[08/12] RISC-V: Refine/enhance '\''M'\''/'\''Zmmul'\'' extension tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9378b9505e3e230e0a690c56e67d253e2a0f5864.1667651354.git.research_trasio@irq.a4lg.com/mbox/"},{"id":15964,"url":"https://patchwork.plctlab.org/api/1.2/patches/15964/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/82832a67f240d5857fd502d4b74fd7d841ee2d6e.1667651354.git.research_trasio@irq.a4lg.com/","msgid":"<82832a67f240d5857fd502d4b74fd7d841ee2d6e.1667651354.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-05T12:29:15","name":"[09/12] RISC-V: Combine/enhance '\''Zicbo[mz]'\'' extension tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/82832a67f240d5857fd502d4b74fd7d841ee2d6e.1667651354.git.research_trasio@irq.a4lg.com/mbox/"},{"id":15965,"url":"https://patchwork.plctlab.org/api/1.2/patches/15965/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9c47e59868a64b13e5a7bb487e3619d4f1497d78.1667651354.git.research_trasio@irq.a4lg.com/","msgid":"<9c47e59868a64b13e5a7bb487e3619d4f1497d78.1667651354.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-05T12:29:16","name":"[10/12] RISC-V: Enhance '\''Zicbop'\'' testcases","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9c47e59868a64b13e5a7bb487e3619d4f1497d78.1667651354.git.research_trasio@irq.a4lg.com/mbox/"},{"id":15967,"url":"https://patchwork.plctlab.org/api/1.2/patches/15967/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2d9befc5bc5eed80b6bd7da6d092a61b1162ecac.1667651354.git.research_trasio@irq.a4lg.com/","msgid":"<2d9befc5bc5eed80b6bd7da6d092a61b1162ecac.1667651354.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-05T12:29:17","name":"[11/12] RISC-V: Reorganize/enhance '\''Zb*'\'' extension tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2d9befc5bc5eed80b6bd7da6d092a61b1162ecac.1667651354.git.research_trasio@irq.a4lg.com/mbox/"},{"id":15969,"url":"https://patchwork.plctlab.org/api/1.2/patches/15969/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f1c5589ab606b74eeac98e3dafd4a7903450d3b2.1667651354.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-11-05T12:29:18","name":"[12/12] RISC-V: Combine/enhance '\''Zk*'\''/'\''Zbk*'\'' extension tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f1c5589ab606b74eeac98e3dafd4a7903450d3b2.1667651354.git.research_trasio@irq.a4lg.com/mbox/"},{"id":16066,"url":"https://patchwork.plctlab.org/api/1.2/patches/16066/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221106053640.1649752-1-indu.bhagat@oracle.com/","msgid":"<20221106053640.1649752-1-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-06T05:36:40","name":"[V3.1,03/15] gas: generate .sframe from CFI directives","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221106053640.1649752-1-indu.bhagat@oracle.com/mbox/"},{"id":16379,"url":"https://patchwork.plctlab.org/api/1.2/patches/16379/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221107112805.3332619-1-och95@yandex.ru/","msgid":"<20221107112805.3332619-1-och95@yandex.ru>","list_archive_url":null,"date":"2022-11-07T11:28:05","name":"gold/aarch64: Fix adrp distance check","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221107112805.3332619-1-och95@yandex.ru/mbox/"},{"id":16400,"url":"https://patchwork.plctlab.org/api/1.2/patches/16400/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221107124620.1271470-1-christoph.muellner@vrull.eu/","msgid":"<20221107124620.1271470-1-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2022-11-07T12:46:20","name":"RISC-V: xtheadfmemidx: Use fp register in mnemonics","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221107124620.1271470-1-christoph.muellner@vrull.eu/mbox/"},{"id":16594,"url":"https://patchwork.plctlab.org/api/1.2/patches/16594/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/CACVBkZ+kM2xcpwk5zHQ4bqDV7dbPjZ6cMU9tR-h62+tDTgi3Tw@mail.gmail.com/","msgid":"","list_archive_url":null,"date":"2022-11-07T17:53:35","name":"GAS fix section alignment for aarch64-pe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/CACVBkZ+kM2xcpwk5zHQ4bqDV7dbPjZ6cMU9tR-h62+tDTgi3Tw@mail.gmail.com/mbox/"},{"id":16744,"url":"https://patchwork.plctlab.org/api/1.2/patches/16744/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221107222809.924195-1-indu.bhagat@oracle.com/","msgid":"<20221107222809.924195-1-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-07T22:28:09","name":"[V3.3,11/15] libctf: add libsframe to LDFLAGS and LIBS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221107222809.924195-1-indu.bhagat@oracle.com/mbox/"},{"id":16797,"url":"https://patchwork.plctlab.org/api/1.2/patches/16797/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221108012556.66467-1-haochen.jiang@intel.com/","msgid":"<20221108012556.66467-1-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-11-08T01:25:56","name":"x86: Correct wrong comments in vex_w_table","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221108012556.66467-1-haochen.jiang@intel.com/mbox/"},{"id":16884,"url":"https://patchwork.plctlab.org/api/1.2/patches/16884/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221108054530.796968-1-markus.t.metzger@intel.com/","msgid":"<20221108054530.796968-1-markus.t.metzger@intel.com>","list_archive_url":null,"date":"2022-11-08T05:45:29","name":"[1/2] gprofng: make cpu identification available to others","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221108054530.796968-1-markus.t.metzger@intel.com/mbox/"},{"id":16885,"url":"https://patchwork.plctlab.org/api/1.2/patches/16885/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221108054530.796968-2-markus.t.metzger@intel.com/","msgid":"<20221108054530.796968-2-markus.t.metzger@intel.com>","list_archive_url":null,"date":"2022-11-08T05:45:30","name":"[2/2] gdb, btrace: use cpuident.h to implement btrace_this_cpu","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221108054530.796968-2-markus.t.metzger@intel.com/mbox/"},{"id":16995,"url":"https://patchwork.plctlab.org/api/1.2/patches/16995/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ea0daf08-4923-ebfa-dcfe-699c43d63822@suse.com/","msgid":"","list_archive_url":null,"date":"2022-11-08T11:29:40","name":"x86/Intel: don'\''t accept malformed EXTRQ / INSERTQ","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ea0daf08-4923-ebfa-dcfe-699c43d63822@suse.com/mbox/"},{"id":17057,"url":"https://patchwork.plctlab.org/api/1.2/patches/17057/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221108141352.6613-1-jwilk@jwilk.net/","msgid":"<20221108141352.6613-1-jwilk@jwilk.net>","list_archive_url":null,"date":"2022-11-08T14:13:52","name":"Fix typos in the list of objdump options","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221108141352.6613-1-jwilk@jwilk.net/mbox/"},{"id":17117,"url":"https://patchwork.plctlab.org/api/1.2/patches/17117/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1667924955-9218-1-git-send-email-apinski@marvell.com/","msgid":"<1667924955-9218-1-git-send-email-apinski@marvell.com>","list_archive_url":null,"date":"2022-11-08T16:29:15","name":"Use toplevel configure for GMP and MPFR for gdb","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1667924955-9218-1-git-send-email-apinski@marvell.com/mbox/"},{"id":17160,"url":"https://patchwork.plctlab.org/api/1.2/patches/17160/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/27382086-397f-060f-6cf6-c1d36ff6b812@linux.ibm.com/","msgid":"<27382086-397f-060f-6cf6-c1d36ff6b812@linux.ibm.com>","list_archive_url":null,"date":"2022-11-08T18:23:32","name":"[COMMITTED] PowerPC: Add XSP operand define","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/27382086-397f-060f-6cf6-c1d36ff6b812@linux.ibm.com/mbox/"},{"id":17202,"url":"https://patchwork.plctlab.org/api/1.2/patches/17202/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221108192248.1622627-1-indu.bhagat@oracle.com/","msgid":"<20221108192248.1622627-1-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-08T19:22:48","name":"libctf: use libtool for link test in configure","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221108192248.1622627-1-indu.bhagat@oracle.com/mbox/"},{"id":17262,"url":"https://patchwork.plctlab.org/api/1.2/patches/17262/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221108225030.371817-1-hjl.tools@gmail.com/","msgid":"<20221108225030.371817-1-hjl.tools@gmail.com>","list_archive_url":null,"date":"2022-11-08T22:50:30","name":"ld: Always output local symbol for relocatable link","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221108225030.371817-1-hjl.tools@gmail.com/mbox/"},{"id":17399,"url":"https://patchwork.plctlab.org/api/1.2/patches/17399/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-2-indu.bhagat@oracle.com/","msgid":"<20221109084244.261296-2-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-09T08:42:34","name":"[V4,01/11] sframe.h: Add SFrame format definition","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-2-indu.bhagat@oracle.com/mbox/"},{"id":17398,"url":"https://patchwork.plctlab.org/api/1.2/patches/17398/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-3-indu.bhagat@oracle.com/","msgid":"<20221109084244.261296-3-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-09T08:42:35","name":"[V4,02/11] gas: add new command line option --gsframe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-3-indu.bhagat@oracle.com/mbox/"},{"id":17400,"url":"https://patchwork.plctlab.org/api/1.2/patches/17400/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-4-indu.bhagat@oracle.com/","msgid":"<20221109084244.261296-4-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-09T08:42:36","name":"[V4,03/11] gas: generate .sframe from CFI directives","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-4-indu.bhagat@oracle.com/mbox/"},{"id":17403,"url":"https://patchwork.plctlab.org/api/1.2/patches/17403/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-5-indu.bhagat@oracle.com/","msgid":"<20221109084244.261296-5-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-09T08:42:37","name":"[V4,04/11] gas: testsuite: add new tests for SFrame unwind info","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-5-indu.bhagat@oracle.com/mbox/"},{"id":17407,"url":"https://patchwork.plctlab.org/api/1.2/patches/17407/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-6-indu.bhagat@oracle.com/","msgid":"<20221109084244.261296-6-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-09T08:42:38","name":"[V4,05/11] libsframe: add the SFrame library","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-6-indu.bhagat@oracle.com/mbox/"},{"id":17406,"url":"https://patchwork.plctlab.org/api/1.2/patches/17406/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-7-indu.bhagat@oracle.com/","msgid":"<20221109084244.261296-7-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-09T08:42:39","name":"[V4,06/11] bfd: linker: merge .sframe sections","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-7-indu.bhagat@oracle.com/mbox/"},{"id":17402,"url":"https://patchwork.plctlab.org/api/1.2/patches/17402/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-8-indu.bhagat@oracle.com/","msgid":"<20221109084244.261296-8-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-09T08:42:40","name":"[V4,07/11] readelf/objdump: support for SFrame section","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-8-indu.bhagat@oracle.com/mbox/"},{"id":17401,"url":"https://patchwork.plctlab.org/api/1.2/patches/17401/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-9-indu.bhagat@oracle.com/","msgid":"<20221109084244.261296-9-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-09T08:42:41","name":"[V4,08/11] src-release.sh: Add libsframe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-9-indu.bhagat@oracle.com/mbox/"},{"id":17404,"url":"https://patchwork.plctlab.org/api/1.2/patches/17404/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-10-indu.bhagat@oracle.com/","msgid":"<20221109084244.261296-10-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-09T08:42:42","name":"[V4,09/11] binutils/NEWS: add text for SFrame support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-10-indu.bhagat@oracle.com/mbox/"},{"id":17405,"url":"https://patchwork.plctlab.org/api/1.2/patches/17405/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-11-indu.bhagat@oracle.com/","msgid":"<20221109084244.261296-11-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-09T08:42:43","name":"[V4,10/11] gas/NEWS: add text about new command line option and SFrame support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-11-indu.bhagat@oracle.com/mbox/"},{"id":17418,"url":"https://patchwork.plctlab.org/api/1.2/patches/17418/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-12-indu.bhagat@oracle.com/","msgid":"<20221109084244.261296-12-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-09T08:42:44","name":"[V4,11/11] doc: add SFrame spec file","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-12-indu.bhagat@oracle.com/mbox/"},{"id":17662,"url":"https://patchwork.plctlab.org/api/1.2/patches/17662/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109162611.760465-1-chigot@adacore.com/","msgid":"<20221109162611.760465-1-chigot@adacore.com>","list_archive_url":null,"date":"2022-11-09T16:26:11","name":"ld/testsuite: skip ld-size when -shared is not supported","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109162611.760465-1-chigot@adacore.com/mbox/"},{"id":17804,"url":"https://patchwork.plctlab.org/api/1.2/patches/17804/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109202129.475283-1-hjl.tools@gmail.com/","msgid":"<20221109202129.475283-1-hjl.tools@gmail.com>","list_archive_url":null,"date":"2022-11-09T20:21:29","name":"[v2] i386: Check invalid (%dx) usage","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109202129.475283-1-hjl.tools@gmail.com/mbox/"},{"id":18043,"url":"https://patchwork.plctlab.org/api/1.2/patches/18043/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y2zOaxv1jkhwTIAi@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-11-10T10:11:55","name":"Sanity check reloc count in get_reloc_upper_bound","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y2zOaxv1jkhwTIAi@squeak.grove.modra.org/mbox/"},{"id":18044,"url":"https://patchwork.plctlab.org/api/1.2/patches/18044/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y2zOkpGuKAn+V2Tk@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-11-10T10:12:34","name":"mach-o reloc size overflow","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y2zOkpGuKAn+V2Tk@squeak.grove.modra.org/mbox/"},{"id":18045,"url":"https://patchwork.plctlab.org/api/1.2/patches/18045/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fddbca08-756a-4d78-b117-3e82dc40df8d@AZ-NEU-EX04.Arm.com/","msgid":"","list_archive_url":null,"date":"2022-11-10T10:17:38","name":"[BINTUILS] arm: Add support for Cortex-X1C CPU.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fddbca08-756a-4d78-b117-3e82dc40df8d@AZ-NEU-EX04.Arm.com/mbox/"},{"id":18051,"url":"https://patchwork.plctlab.org/api/1.2/patches/18051/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1518b510-2124-cbcb-9dcb-059dcfdc6cd4@suse.com/","msgid":"<1518b510-2124-cbcb-9dcb-059dcfdc6cd4@suse.com>","list_archive_url":null,"date":"2022-11-10T10:24:31","name":"x86: drop stray IsString from PadLock insns","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1518b510-2124-cbcb-9dcb-059dcfdc6cd4@suse.com/mbox/"},{"id":18088,"url":"https://patchwork.plctlab.org/api/1.2/patches/18088/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/25e8786d-289e-0521-baa2-2f2b85124dfe@suse.com/","msgid":"<25e8786d-289e-0521-baa2-2f2b85124dfe@suse.com>","list_archive_url":null,"date":"2022-11-10T12:12:46","name":"[v2] x86: drop stray IsString from PadLock insns","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/25e8786d-289e-0521-baa2-2f2b85124dfe@suse.com/mbox/"},{"id":18130,"url":"https://patchwork.plctlab.org/api/1.2/patches/18130/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9bb8ebe7-9e49-d60b-d586-e4d98242acda@suse.com/","msgid":"<9bb8ebe7-9e49-d60b-d586-e4d98242acda@suse.com>","list_archive_url":null,"date":"2022-11-10T13:36:16","name":"x86: drop duplicate sse4a entry from cpu_arch[]","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9bb8ebe7-9e49-d60b-d586-e4d98242acda@suse.com/mbox/"},{"id":18135,"url":"https://patchwork.plctlab.org/api/1.2/patches/18135/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/21665493-a9f9-3429-c9ae-ea69bc7751e2@suse.com/","msgid":"<21665493-a9f9-3429-c9ae-ea69bc7751e2@suse.com>","list_archive_url":null,"date":"2022-11-10T13:45:30","name":"x86: fold special-operand insn attributes into a single enum","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/21665493-a9f9-3429-c9ae-ea69bc7751e2@suse.com/mbox/"},{"id":18284,"url":"https://patchwork.plctlab.org/api/1.2/patches/18284/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1668107159-16961-1-git-send-email-apinski@marvell.com/","msgid":"<1668107159-16961-1-git-send-email-apinski@marvell.com>","list_archive_url":null,"date":"2022-11-10T19:05:59","name":"[PATCHv2] Use toplevel configure for GMP and MPFR for gdb","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1668107159-16961-1-git-send-email-apinski@marvell.com/mbox/"},{"id":18337,"url":"https://patchwork.plctlab.org/api/1.2/patches/18337/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221110224002.3798725-1-vladimir.mezentsev@oracle.com/","msgid":"<20221110224002.3798725-1-vladimir.mezentsev@oracle.com>","list_archive_url":null,"date":"2022-11-10T22:40:02","name":"gprofng: fix typo in configure.ac","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221110224002.3798725-1-vladimir.mezentsev@oracle.com/mbox/"},{"id":18424,"url":"https://patchwork.plctlab.org/api/1.2/patches/18424/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221111033040.23115-1-mark@harmstone.com/","msgid":"<20221111033040.23115-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-11-11T03:30:40","name":"ld: Add section contributions substream to PDB files","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221111033040.23115-1-mark@harmstone.com/mbox/"},{"id":18513,"url":"https://patchwork.plctlab.org/api/1.2/patches/18513/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/40e89395-1438-6cbe-aa37-1a04a724c8c7@suse.com/","msgid":"<40e89395-1438-6cbe-aa37-1a04a724c8c7@suse.com>","list_archive_url":null,"date":"2022-11-11T07:32:17","name":"gas: accept custom \".linefile .\"","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/40e89395-1438-6cbe-aa37-1a04a724c8c7@suse.com/mbox/"},{"id":18517,"url":"https://patchwork.plctlab.org/api/1.2/patches/18517/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y23642YK4HTWnn3X@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-11-11T07:33:55","name":"Sanity check SHT_MIPS_OPTIONS size","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y23642YK4HTWnn3X@squeak.grove.modra.org/mbox/"},{"id":18519,"url":"https://patchwork.plctlab.org/api/1.2/patches/18519/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y237HYVYLWv1R4b/@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-11-11T07:34:53","name":"PR28834, PR26946 sanity checking section size","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y237HYVYLWv1R4b/@squeak.grove.modra.org/mbox/"},{"id":18670,"url":"https://patchwork.plctlab.org/api/1.2/patches/18670/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c5ab35f0-595a-439c-b120-f93bd109ab96@AZ-NEU-EX04.Arm.com/","msgid":"","list_archive_url":null,"date":"2022-11-11T10:51:43","name":"[Binutils,gas] arm: Add support for new unwinder directive \".pacspval\".","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c5ab35f0-595a-439c-b120-f93bd109ab96@AZ-NEU-EX04.Arm.com/mbox/"},{"id":18672,"url":"https://patchwork.plctlab.org/api/1.2/patches/18672/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/33eb9aff-d813-44c5-8315-aeb3e339b3f2@AZ-NEU-EX04.Arm.com/","msgid":"<33eb9aff-d813-44c5-8315-aeb3e339b3f2@AZ-NEU-EX04.Arm.com>","list_archive_url":null,"date":"2022-11-11T10:53:55","name":"[Binutils,readelf] arm: Support for new pacbti unwind opcode 0xb5.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/33eb9aff-d813-44c5-8315-aeb3e339b3f2@AZ-NEU-EX04.Arm.com/mbox/"},{"id":19116,"url":"https://patchwork.plctlab.org/api/1.2/patches/19116/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y29EZ/ykU1Qe6AAw@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-11-12T06:59:51","name":"PowerPC64 paddi -Mraw","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y29EZ/ykU1Qe6AAw@squeak.grove.modra.org/mbox/"},{"id":19138,"url":"https://patchwork.plctlab.org/api/1.2/patches/19138/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221112091217.558020-1-dimitar@dinux.eu/","msgid":"<20221112091217.558020-1-dimitar@dinux.eu>","list_archive_url":null,"date":"2022-11-12T09:12:17","name":"pru: bfd: Correct default to no execstack","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221112091217.558020-1-dimitar@dinux.eu/mbox/"},{"id":19173,"url":"https://patchwork.plctlab.org/api/1.2/patches/19173/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221112124441.5084-1-patrick@monnerat.net/","msgid":"<20221112124441.5084-1-patrick@monnerat.net>","list_archive_url":null,"date":"2022-11-12T12:44:41","name":"binutils/objcopy: keep relocation while renaming a section with explicit flags","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221112124441.5084-1-patrick@monnerat.net/mbox/"},{"id":19377,"url":"https://patchwork.plctlab.org/api/1.2/patches/19377/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221113155921.1445808-1-christoph.muellner@vrull.eu/","msgid":"<20221113155921.1445808-1-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2022-11-13T15:59:20","name":"[1/2] RISC-V: Add T-Head Fmv vendor extension","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221113155921.1445808-1-christoph.muellner@vrull.eu/mbox/"},{"id":19378,"url":"https://patchwork.plctlab.org/api/1.2/patches/19378/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221113155921.1445808-2-christoph.muellner@vrull.eu/","msgid":"<20221113155921.1445808-2-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2022-11-13T15:59:21","name":"[2/2] RISC-V: Add T-Head Int vendor extension","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221113155921.1445808-2-christoph.muellner@vrull.eu/mbox/"},{"id":19850,"url":"https://patchwork.plctlab.org/api/1.2/patches/19850/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221114150348.112815-1-bwerl.dev@gmail.com/","msgid":"<20221114150348.112815-1-bwerl.dev@gmail.com>","list_archive_url":null,"date":"2022-11-14T15:03:48","name":"readelf: use fseeko for elf files >= 2 GiB on x86_64-mingw32","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221114150348.112815-1-bwerl.dev@gmail.com/mbox/"},{"id":19866,"url":"https://patchwork.plctlab.org/api/1.2/patches/19866/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3dd1c6f9-a773-c05f-44d7-12b7947072d2@suse.com/","msgid":"<3dd1c6f9-a773-c05f-44d7-12b7947072d2@suse.com>","list_archive_url":null,"date":"2022-11-14T16:12:26","name":"x86: infer No_*Suf from other insn attributes","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3dd1c6f9-a773-c05f-44d7-12b7947072d2@suse.com/mbox/"},{"id":19934,"url":"https://patchwork.plctlab.org/api/1.2/patches/19934/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f659dfbb-b84b-af86-bd8c-d177900af779@linaro.org/","msgid":"","list_archive_url":null,"date":"2022-11-14T17:24:23","name":"[V2] GAS fix alignment for aarch64-pe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f659dfbb-b84b-af86-bd8c-d177900af779@linaro.org/mbox/"},{"id":20111,"url":"https://patchwork.plctlab.org/api/1.2/patches/20111/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221115010409.24214-1-mark@harmstone.com/","msgid":"<20221115010409.24214-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-11-15T01:04:09","name":"gas: Add --gcodeview option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221115010409.24214-1-mark@harmstone.com/mbox/"},{"id":20174,"url":"https://patchwork.plctlab.org/api/1.2/patches/20174/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d305cd6178975195b025828561d59e505524ea45.1668486687.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-11-15T04:31:22","name":"[v3,1/8] RISC-V: Add a space at the end of pinfo","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d305cd6178975195b025828561d59e505524ea45.1668486687.git.research_trasio@irq.a4lg.com/mbox/"},{"id":20177,"url":"https://patchwork.plctlab.org/api/1.2/patches/20177/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2627dd5e18e59b6d976a8e6f1be39336e8a12cc3.1668486687.git.research_trasio@irq.a4lg.com/","msgid":"<2627dd5e18e59b6d976a8e6f1be39336e8a12cc3.1668486687.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-15T04:31:23","name":"[v3,2/8] RISC-V: Fix obvious misalignments ('\''Zbb'\''/'\''Zba'\'')","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2627dd5e18e59b6d976a8e6f1be39336e8a12cc3.1668486687.git.research_trasio@irq.a4lg.com/mbox/"},{"id":20173,"url":"https://patchwork.plctlab.org/api/1.2/patches/20173/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9d110279505cf502900a000a07e6e82b50f12adc.1668486687.git.research_trasio@irq.a4lg.com/","msgid":"<9d110279505cf502900a000a07e6e82b50f12adc.1668486687.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-15T04:31:24","name":"[v3,3/8] RISC-V: Remove spaces in opcode entries","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9d110279505cf502900a000a07e6e82b50f12adc.1668486687.git.research_trasio@irq.a4lg.com/mbox/"},{"id":20179,"url":"https://patchwork.plctlab.org/api/1.2/patches/20179/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8f77aa968ed9457ce1bce0a1f6449a287d0e6a18.1668486687.git.research_trasio@irq.a4lg.com/","msgid":"<8f77aa968ed9457ce1bce0a1f6449a287d0e6a18.1668486687.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-15T04:31:25","name":"[v3,4/8] RISC-V: Remove unused instruction macros","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8f77aa968ed9457ce1bce0a1f6449a287d0e6a18.1668486687.git.research_trasio@irq.a4lg.com/mbox/"},{"id":20176,"url":"https://patchwork.plctlab.org/api/1.2/patches/20176/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b43454773d597c1bc51741ef09aac960fecdfbd5.1668486687.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-11-15T04:31:26","name":"[v3,5/8] RISC-V: Complete tidying up with SCALL and SBREAK","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b43454773d597c1bc51741ef09aac960fecdfbd5.1668486687.git.research_trasio@irq.a4lg.com/mbox/"},{"id":20178,"url":"https://patchwork.plctlab.org/api/1.2/patches/20178/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/58cfec431ff2535aeb0c3fd9213933cf28864cb9.1668486687.git.research_trasio@irq.a4lg.com/","msgid":"<58cfec431ff2535aeb0c3fd9213933cf28864cb9.1668486687.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-15T04:31:27","name":"[v3,6/8] RISC-V: Tidying up with fmv.w.x and fmv.x.w","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/58cfec431ff2535aeb0c3fd9213933cf28864cb9.1668486687.git.research_trasio@irq.a4lg.com/mbox/"},{"id":20180,"url":"https://patchwork.plctlab.org/api/1.2/patches/20180/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/192f62be797f7c46a03acadb7d1bcdb83a7e9d6e.1668486687.git.research_trasio@irq.a4lg.com/","msgid":"<192f62be797f7c46a03acadb7d1bcdb83a7e9d6e.1668486687.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-15T04:31:28","name":"[v3,7/8] RISC-V: Make alias instructions aliases","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/192f62be797f7c46a03acadb7d1bcdb83a7e9d6e.1668486687.git.research_trasio@irq.a4lg.com/mbox/"},{"id":20175,"url":"https://patchwork.plctlab.org/api/1.2/patches/20175/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c89919c84067e1c2105b1857937df6405aec70fa.1668486687.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-11-15T04:31:29","name":"[v3,8/8] RISC-V: Use defined mask and match values","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c89919c84067e1c2105b1857937df6405aec70fa.1668486687.git.research_trasio@irq.a4lg.com/mbox/"},{"id":20185,"url":"https://patchwork.plctlab.org/api/1.2/patches/20185/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ebc1e98ae09f2c209ebaed2b81d5b418ce2c5128.1668487922.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-11-15T04:52:44","name":"[01/11] opcodes/riscv-dis.c: More tidying","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ebc1e98ae09f2c209ebaed2b81d5b418ce2c5128.1668487922.git.research_trasio@irq.a4lg.com/mbox/"},{"id":20188,"url":"https://patchwork.plctlab.org/api/1.2/patches/20188/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9795298f970f0b8a02796edc2c4249417614103b.1668487922.git.research_trasio@irq.a4lg.com/","msgid":"<9795298f970f0b8a02796edc2c4249417614103b.1668487922.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-15T04:52:45","name":"[02/11] RISC-V: Add test for '\''Zfinx'\'' register switching","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9795298f970f0b8a02796edc2c4249417614103b.1668487922.git.research_trasio@irq.a4lg.com/mbox/"},{"id":20186,"url":"https://patchwork.plctlab.org/api/1.2/patches/20186/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6c6c644515c6bc2751062543097eb14ee98e97c8.1668487922.git.research_trasio@irq.a4lg.com/","msgid":"<6c6c644515c6bc2751062543097eb14ee98e97c8.1668487922.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-15T04:52:46","name":"[03/11] RISC-V: Make mapping symbol checking consistent","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6c6c644515c6bc2751062543097eb14ee98e97c8.1668487922.git.research_trasio@irq.a4lg.com/mbox/"},{"id":20187,"url":"https://patchwork.plctlab.org/api/1.2/patches/20187/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b5b5ce7e34544c7934b775062413e0fe07dcd6e6.1668487922.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-11-15T04:52:47","name":"[04/11] RISC-V: Split riscv_get_map_state into two steps","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b5b5ce7e34544c7934b775062413e0fe07dcd6e6.1668487922.git.research_trasio@irq.a4lg.com/mbox/"},{"id":20192,"url":"https://patchwork.plctlab.org/api/1.2/patches/20192/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c143088cbaf7a19a992e008689420d95a90f3fab.1668487922.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-11-15T04:52:48","name":"[05/11] RISC-V: One time CSR hash table initialization","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c143088cbaf7a19a992e008689420d95a90f3fab.1668487922.git.research_trasio@irq.a4lg.com/mbox/"},{"id":20193,"url":"https://patchwork.plctlab.org/api/1.2/patches/20193/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9734125736efc8b63be17df87d38cf24bb14a156.1668487922.git.research_trasio@irq.a4lg.com/","msgid":"<9734125736efc8b63be17df87d38cf24bb14a156.1668487922.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-15T04:52:49","name":"[06/11] RISC-V: Use static xlen on ADDIW sequence","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9734125736efc8b63be17df87d38cf24bb14a156.1668487922.git.research_trasio@irq.a4lg.com/mbox/"},{"id":20191,"url":"https://patchwork.plctlab.org/api/1.2/patches/20191/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/34dbd0c82de0af284887a3bff649c8c53d67e752.1668487922.git.research_trasio@irq.a4lg.com/","msgid":"<34dbd0c82de0af284887a3bff649c8c53d67e752.1668487922.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-15T04:52:50","name":"[07/11] opcodes/riscv-dis.c: Add form feed for separation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/34dbd0c82de0af284887a3bff649c8c53d67e752.1668487922.git.research_trasio@irq.a4lg.com/mbox/"},{"id":20190,"url":"https://patchwork.plctlab.org/api/1.2/patches/20190/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1352fb8c63539727204df94651f371ed09bbce4c.1668487922.git.research_trasio@irq.a4lg.com/","msgid":"<1352fb8c63539727204df94651f371ed09bbce4c.1668487922.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-15T04:52:51","name":"[08/11] RISC-V: Split match/print steps on disassembler","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1352fb8c63539727204df94651f371ed09bbce4c.1668487922.git.research_trasio@irq.a4lg.com/mbox/"},{"id":20189,"url":"https://patchwork.plctlab.org/api/1.2/patches/20189/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/12cd8820841f695708875206b6461b6322c74428.1668487922.git.research_trasio@irq.a4lg.com/","msgid":"<12cd8820841f695708875206b6461b6322c74428.1668487922.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-15T04:52:52","name":"[09/11] RISC-V: Reorganize disassembler state initialization","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/12cd8820841f695708875206b6461b6322c74428.1668487922.git.research_trasio@irq.a4lg.com/mbox/"},{"id":20194,"url":"https://patchwork.plctlab.org/api/1.2/patches/20194/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6aade17e12ce2a928d044d9f148c874cf9922da8.1668487922.git.research_trasio@irq.a4lg.com/","msgid":"<6aade17e12ce2a928d044d9f148c874cf9922da8.1668487922.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-15T04:52:53","name":"[10/11] RISC-V: Reorganize arch-related initialization and management","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6aade17e12ce2a928d044d9f148c874cf9922da8.1668487922.git.research_trasio@irq.a4lg.com/mbox/"},{"id":20195,"url":"https://patchwork.plctlab.org/api/1.2/patches/20195/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a239fb0682bd24d4f1eb3014685eed78f9ea779a.1668487922.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-11-15T04:52:54","name":"[11/11] RISC-V: Move disassembler private data initialization","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a239fb0682bd24d4f1eb3014685eed78f9ea779a.1668487922.git.research_trasio@irq.a4lg.com/mbox/"},{"id":20236,"url":"https://patchwork.plctlab.org/api/1.2/patches/20236/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221115081455.2354987-2-zengxiao@eswincomputing.com/","msgid":"<20221115081455.2354987-2-zengxiao@eswincomputing.com>","list_archive_url":null,"date":"2022-11-15T08:14:55","name":"[v1,1/1] RISC-V: Make R_RISCV_SUB6 conforms to riscv abi standard","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221115081455.2354987-2-zengxiao@eswincomputing.com/mbox/"},{"id":20422,"url":"https://patchwork.plctlab.org/api/1.2/patches/20422/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221115145717.64948-1-bwerl.dev@gmail.com/","msgid":"<20221115145717.64948-1-bwerl.dev@gmail.com>","list_archive_url":null,"date":"2022-11-15T14:57:17","name":"readelf: use fseeko64 or fseeko if possible","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221115145717.64948-1-bwerl.dev@gmail.com/mbox/"},{"id":20600,"url":"https://patchwork.plctlab.org/api/1.2/patches/20600/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y3QKUwDn748CbDIs@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-11-15T21:53:23","name":"aarch64-pe can'\''t fill 16 bytes in section .text","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y3QKUwDn748CbDIs@squeak.grove.modra.org/mbox/"},{"id":20720,"url":"https://patchwork.plctlab.org/api/1.2/patches/20720/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221116053326.1337432-1-vladimir.mezentsev@oracle.com/","msgid":"<20221116053326.1337432-1-vladimir.mezentsev@oracle.com>","list_archive_url":null,"date":"2022-11-16T05:33:26","name":"PR29788, gprofng cannot display Java'\''s generated assembly code","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221116053326.1337432-1-vladimir.mezentsev@oracle.com/mbox/"},{"id":21321,"url":"https://patchwork.plctlab.org/api/1.2/patches/21321/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221116232039.1793148-1-hjl.tools@gmail.com/","msgid":"<20221116232039.1793148-1-hjl.tools@gmail.com>","list_archive_url":null,"date":"2022-11-16T23:20:39","name":"ld: Always call elf_backend_output_arch_local_syms","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221116232039.1793148-1-hjl.tools@gmail.com/mbox/"},{"id":21322,"url":"https://patchwork.plctlab.org/api/1.2/patches/21322/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221116232132.1009459-1-indu.bhagat@oracle.com/","msgid":"<20221116232132.1009459-1-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-16T23:21:32","name":"[gas,aarch64] : fix build breakage for aarch64-pe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221116232132.1009459-1-indu.bhagat@oracle.com/mbox/"},{"id":21449,"url":"https://patchwork.plctlab.org/api/1.2/patches/21449/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221117060234.1771025-1-indu.bhagat@oracle.com/","msgid":"<20221117060234.1771025-1-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-17T06:02:34","name":"[V2,gas,aarch64] : fix build breakage for aarch64-pe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221117060234.1771025-1-indu.bhagat@oracle.com/mbox/"},{"id":21662,"url":"https://patchwork.plctlab.org/api/1.2/patches/21662/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a050b8da-b978-d443-eee0-32b5a7836bb4@suse.com/","msgid":"","list_archive_url":null,"date":"2022-11-17T13:29:02","name":"[1/2] x86: instantiate i386_{op, reg}tab[] in gas instead of in libopcodes","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a050b8da-b978-d443-eee0-32b5a7836bb4@suse.com/mbox/"},{"id":21663,"url":"https://patchwork.plctlab.org/api/1.2/patches/21663/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d9b5137b-3bc0-8496-4533-03402ac00628@suse.com/","msgid":"","list_archive_url":null,"date":"2022-11-17T13:29:36","name":"[2/2] x86: break gas dependency on libopcodes","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d9b5137b-3bc0-8496-4533-03402ac00628@suse.com/mbox/"},{"id":21682,"url":"https://patchwork.plctlab.org/api/1.2/patches/21682/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221117143419.19571-1-bwerl.dev@gmail.com/","msgid":"<20221117143419.19571-1-bwerl.dev@gmail.com>","list_archive_url":null,"date":"2022-11-17T14:34:19","name":"readelf: use fseeko64 or fseeko if possible","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221117143419.19571-1-bwerl.dev@gmail.com/mbox/"},{"id":21850,"url":"https://patchwork.plctlab.org/api/1.2/patches/21850/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221117170546.1941945-1-hjl.tools@gmail.com/","msgid":"<20221117170546.1941945-1-hjl.tools@gmail.com>","list_archive_url":null,"date":"2022-11-17T17:05:46","name":"i386: Move i386_seg_prefixes to gas","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221117170546.1941945-1-hjl.tools@gmail.com/mbox/"},{"id":21858,"url":"https://patchwork.plctlab.org/api/1.2/patches/21858/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/CAPOVtOvi0D-u7MKAuO97-q241JZFojD8xppn3GdF2kH57iT+TA@mail.gmail.com/","msgid":"","list_archive_url":null,"date":"2022-11-17T17:44:00","name":"binutils: partially revert 17c6c3b99156fe82c1e637e1a5fd9f163ac788c8","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/CAPOVtOvi0D-u7MKAuO97-q241JZFojD8xppn3GdF2kH57iT+TA@mail.gmail.com/mbox/"},{"id":21992,"url":"https://patchwork.plctlab.org/api/1.2/patches/21992/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221118003212.3628771-1-christoph.muellner@vrull.eu/","msgid":"<20221118003212.3628771-1-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2022-11-18T00:32:12","name":"riscv: Add AIA extension support (Smaia, Ssaia)","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221118003212.3628771-1-christoph.muellner@vrull.eu/mbox/"},{"id":22004,"url":"https://patchwork.plctlab.org/api/1.2/patches/22004/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y3bZt50nhFXkf2WU@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-11-18T01:02:47","name":"go32 sanity check","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y3bZt50nhFXkf2WU@squeak.grove.modra.org/mbox/"},{"id":22005,"url":"https://patchwork.plctlab.org/api/1.2/patches/22005/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y3bZ0x42eeZFSqXt@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-11-18T01:03:15","name":"PR29799 heap buffer overflow in display_gdb_index dwarf.c:10548","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y3bZ0x42eeZFSqXt@squeak.grove.modra.org/mbox/"},{"id":22050,"url":"https://patchwork.plctlab.org/api/1.2/patches/22050/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4c45925619ab51261ca87d309883c9aa7cd05240.1668736896.git.research_trasio@irq.a4lg.com/","msgid":"<4c45925619ab51261ca87d309883c9aa7cd05240.1668736896.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-18T02:02:21","name":"RISC-V: Add INSN_DREF to memory read/write instructions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4c45925619ab51261ca87d309883c9aa7cd05240.1668736896.git.research_trasio@irq.a4lg.com/mbox/"},{"id":22053,"url":"https://patchwork.plctlab.org/api/1.2/patches/22053/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/13809b68ae60e912f3cb8e9bedd8eedf3899b547.1668737241.git.research_trasio@irq.a4lg.com/","msgid":"<13809b68ae60e912f3cb8e9bedd8eedf3899b547.1668737241.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-18T02:07:48","name":"[v4,1/8] RISC-V: Add a space at the end of pinfo","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/13809b68ae60e912f3cb8e9bedd8eedf3899b547.1668737241.git.research_trasio@irq.a4lg.com/mbox/"},{"id":22051,"url":"https://patchwork.plctlab.org/api/1.2/patches/22051/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9abf4696a17c5407a75d87b3c200fb9958ff227e.1668737241.git.research_trasio@irq.a4lg.com/","msgid":"<9abf4696a17c5407a75d87b3c200fb9958ff227e.1668737241.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-18T02:07:49","name":"[v4,2/8] RISC-V: Fix obvious misalignments ('\''Zbb'\''/'\''Zba'\'')","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9abf4696a17c5407a75d87b3c200fb9958ff227e.1668737241.git.research_trasio@irq.a4lg.com/mbox/"},{"id":22052,"url":"https://patchwork.plctlab.org/api/1.2/patches/22052/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/80185b54704af681ba81c6f84b6ce099cc3b5970.1668737241.git.research_trasio@irq.a4lg.com/","msgid":"<80185b54704af681ba81c6f84b6ce099cc3b5970.1668737241.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-18T02:07:50","name":"[v4,3/8] RISC-V: Remove spaces in opcode entries","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/80185b54704af681ba81c6f84b6ce099cc3b5970.1668737241.git.research_trasio@irq.a4lg.com/mbox/"},{"id":22055,"url":"https://patchwork.plctlab.org/api/1.2/patches/22055/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5d675a4132e2f6160d3294563e16f5093b5b1e20.1668737241.git.research_trasio@irq.a4lg.com/","msgid":"<5d675a4132e2f6160d3294563e16f5093b5b1e20.1668737241.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-18T02:07:51","name":"[v4,4/8] RISC-V: Remove unused instruction macros","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5d675a4132e2f6160d3294563e16f5093b5b1e20.1668737241.git.research_trasio@irq.a4lg.com/mbox/"},{"id":22056,"url":"https://patchwork.plctlab.org/api/1.2/patches/22056/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/27a4301cbae3d6788c878924f55aa9a6ae910669.1668737241.git.research_trasio@irq.a4lg.com/","msgid":"<27a4301cbae3d6788c878924f55aa9a6ae910669.1668737241.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-18T02:07:52","name":"[v4,5/8] RISC-V: Complete tidying up with SCALL and SBREAK","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/27a4301cbae3d6788c878924f55aa9a6ae910669.1668737241.git.research_trasio@irq.a4lg.com/mbox/"},{"id":22058,"url":"https://patchwork.plctlab.org/api/1.2/patches/22058/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7f0ea4bf1af541504b72791b5217253b2450071c.1668737241.git.research_trasio@irq.a4lg.com/","msgid":"<7f0ea4bf1af541504b72791b5217253b2450071c.1668737241.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-18T02:07:53","name":"[v4,6/8] RISC-V: Tidying up with fmv.w.x and fmv.x.w","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7f0ea4bf1af541504b72791b5217253b2450071c.1668737241.git.research_trasio@irq.a4lg.com/mbox/"},{"id":22057,"url":"https://patchwork.plctlab.org/api/1.2/patches/22057/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e5d45f2c8d1bb5b2d9adbfa117a3fc7d32afd6c9.1668737241.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-11-18T02:07:54","name":"[v4,7/8] RISC-V: Make alias instructions aliases","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e5d45f2c8d1bb5b2d9adbfa117a3fc7d32afd6c9.1668737241.git.research_trasio@irq.a4lg.com/mbox/"},{"id":22054,"url":"https://patchwork.plctlab.org/api/1.2/patches/22054/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3c1e28e61eb0275d0fd02a7d9ff956cc4f589104.1668737241.git.research_trasio@irq.a4lg.com/","msgid":"<3c1e28e61eb0275d0fd02a7d9ff956cc4f589104.1668737241.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-18T02:07:55","name":"[v4,8/8] RISC-V: Use defined mask and match values","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3c1e28e61eb0275d0fd02a7d9ff956cc4f589104.1668737241.git.research_trasio@irq.a4lg.com/mbox/"},{"id":22215,"url":"https://patchwork.plctlab.org/api/1.2/patches/22215/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/028280ab-56ad-2380-6bdd-3c944695ec5f@suse.com/","msgid":"<028280ab-56ad-2380-6bdd-3c944695ec5f@suse.com>","list_archive_url":null,"date":"2022-11-18T09:12:10","name":"[v2,1/4] x86: instantiate i386_{op, reg}tab[] in gas instead of in libopcodes","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/028280ab-56ad-2380-6bdd-3c944695ec5f@suse.com/mbox/"},{"id":22216,"url":"https://patchwork.plctlab.org/api/1.2/patches/22216/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b9a2ae11-6e9c-e9a8-88f6-17c686f0b844@suse.com/","msgid":"","list_archive_url":null,"date":"2022-11-18T09:13:01","name":"[v2,2/4] x86: remove i386-opc.c","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b9a2ae11-6e9c-e9a8-88f6-17c686f0b844@suse.com/mbox/"},{"id":22217,"url":"https://patchwork.plctlab.org/api/1.2/patches/22217/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fad783e7-e00a-c3c1-cb6d-89b70816a737@suse.com/","msgid":"","list_archive_url":null,"date":"2022-11-18T09:13:24","name":"[v2,3/4] x86: break gas dependency on libopcodes","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fad783e7-e00a-c3c1-cb6d-89b70816a737@suse.com/mbox/"},{"id":22218,"url":"https://patchwork.plctlab.org/api/1.2/patches/22218/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e3d67085-1385-d576-8656-30454f9e4474@suse.com/","msgid":"","list_archive_url":null,"date":"2022-11-18T09:14:05","name":"[v2,4/4] x86: drop sentinel from i386_optab[]","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e3d67085-1385-d576-8656-30454f9e4474@suse.com/mbox/"},{"id":23223,"url":"https://patchwork.plctlab.org/api/1.2/patches/23223/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2e469b6dd7d8b93ffd3cac333dd58d172a8f28d6.1668841829.git.research_trasio@irq.a4lg.com/","msgid":"<2e469b6dd7d8b93ffd3cac333dd58d172a8f28d6.1668841829.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-19T07:10:33","name":"[1/2] RISC-V: Make .insn tests stricter","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2e469b6dd7d8b93ffd3cac333dd58d172a8f28d6.1668841829.git.research_trasio@irq.a4lg.com/mbox/"},{"id":23224,"url":"https://patchwork.plctlab.org/api/1.2/patches/23224/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ed49fad6bc6aa4f59d619fd6b445582331594e08.1668841829.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-11-19T07:10:34","name":"[2/2] RISC-V: Better support for long instructions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ed49fad6bc6aa4f59d619fd6b445582331594e08.1668841829.git.research_trasio@irq.a4lg.com/mbox/"},{"id":23362,"url":"https://patchwork.plctlab.org/api/1.2/patches/23362/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7487608537fcd71f322e56d40bfb2cc605cee89a.1668906514.git.research_trasio@irq.a4lg.com/","msgid":"<7487608537fcd71f322e56d40bfb2cc605cee89a.1668906514.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-20T01:08:40","name":"[1/3] RISC-V: Use faster hash table on disassembling","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7487608537fcd71f322e56d40bfb2cc605cee89a.1668906514.git.research_trasio@irq.a4lg.com/mbox/"},{"id":23361,"url":"https://patchwork.plctlab.org/api/1.2/patches/23361/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e984efaf6c2d42891fa466338d999bf8b292dd7d.1668906514.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-11-20T01:08:41","name":"[2/3] RISC-V: Fallback on faster hash table","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e984efaf6c2d42891fa466338d999bf8b292dd7d.1668906514.git.research_trasio@irq.a4lg.com/mbox/"},{"id":23366,"url":"https://patchwork.plctlab.org/api/1.2/patches/23366/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/844db363911065a3b5f0c5e4601f89ee1d7360c5.1668906514.git.research_trasio@irq.a4lg.com/","msgid":"<844db363911065a3b5f0c5e4601f89ee1d7360c5.1668906514.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-20T01:08:42","name":"[3/3] RISC-V: Cache instruction support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/844db363911065a3b5f0c5e4601f89ee1d7360c5.1668906514.git.research_trasio@irq.a4lg.com/mbox/"},{"id":23363,"url":"https://patchwork.plctlab.org/api/1.2/patches/23363/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/88793c204c9270376959c6276fb1b63275bef3c8.1668906599.git.research_trasio@irq.a4lg.com/","msgid":"<88793c204c9270376959c6276fb1b63275bef3c8.1668906599.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-20T01:10:07","name":"[1/3] RISC-V: Easy optimization on riscv_search_mapping_symbol","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/88793c204c9270376959c6276fb1b63275bef3c8.1668906599.git.research_trasio@irq.a4lg.com/mbox/"},{"id":23365,"url":"https://patchwork.plctlab.org/api/1.2/patches/23365/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/55a36e28e1cb3983c637b3019d48717278574591.1668906599.git.research_trasio@irq.a4lg.com/","msgid":"<55a36e28e1cb3983c637b3019d48717278574591.1668906599.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-20T01:10:08","name":"[2/3] RISC-V: Per-section private data initialization","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/55a36e28e1cb3983c637b3019d48717278574591.1668906599.git.research_trasio@irq.a4lg.com/mbox/"},{"id":23364,"url":"https://patchwork.plctlab.org/api/1.2/patches/23364/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d41edfbaf150abb20fd78e8518ca5a9e7e5eb74f.1668906599.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-11-20T01:10:09","name":"[3/3] RISC-V: Optimized search on mapping symbols","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d41edfbaf150abb20fd78e8518ca5a9e7e5eb74f.1668906599.git.research_trasio@irq.a4lg.com/mbox/"},{"id":23372,"url":"https://patchwork.plctlab.org/api/1.2/patches/23372/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/94304c8d9174ae7e9cf52abc3af6ccf5e3e0ecd9.1668910970.git.research_trasio@irq.a4lg.com/","msgid":"<94304c8d9174ae7e9cf52abc3af6ccf5e3e0ecd9.1668910970.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-20T02:23:27","name":"[v3,1/3] RISC-V: Make \"priv-spec\" overridable","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/94304c8d9174ae7e9cf52abc3af6ccf5e3e0ecd9.1668910970.git.research_trasio@irq.a4lg.com/mbox/"},{"id":23371,"url":"https://patchwork.plctlab.org/api/1.2/patches/23371/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9d6008e38402c4e60ada6f3d3db14b92815177d8.1668910970.git.research_trasio@irq.a4lg.com/","msgid":"<9d6008e38402c4e60ada6f3d3db14b92815177d8.1668910970.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-20T02:23:28","name":"[v3,2/3] RISC-V: Add \"arch\" disassembler option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9d6008e38402c4e60ada6f3d3db14b92815177d8.1668910970.git.research_trasio@irq.a4lg.com/mbox/"},{"id":23370,"url":"https://patchwork.plctlab.org/api/1.2/patches/23370/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/70a4ac1ba8c12101de56c24d3a47939a2f5ee542.1668910970.git.research_trasio@irq.a4lg.com/","msgid":"<70a4ac1ba8c12101de56c24d3a47939a2f5ee542.1668910970.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-20T02:23:29","name":"[v3,3/3] gdb/testsuite: RISC-V disassembler option tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/70a4ac1ba8c12101de56c24d3a47939a2f5ee542.1668910970.git.research_trasio@irq.a4lg.com/mbox/"},{"id":23667,"url":"https://patchwork.plctlab.org/api/1.2/patches/23667/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221121110926.124434-1-aleksandar.rikalo@syrmia.com/","msgid":"<20221121110926.124434-1-aleksandar.rikalo@syrmia.com>","list_archive_url":null,"date":"2022-11-21T11:09:26","name":"[v3] Add support for nanoMIPS architecture","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221121110926.124434-1-aleksandar.rikalo@syrmia.com/mbox/"},{"id":23697,"url":"https://patchwork.plctlab.org/api/1.2/patches/23697/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221121120037.19325-1-zengxiao@eswincomputing.com/","msgid":"<20221121120037.19325-1-zengxiao@eswincomputing.com>","list_archive_url":null,"date":"2022-11-21T12:00:37","name":"[v2] RISC-V: Make R_RISCV_SUB6 conforms to riscv ABI standard","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221121120037.19325-1-zengxiao@eswincomputing.com/mbox/"},{"id":23957,"url":"https://patchwork.plctlab.org/api/1.2/patches/23957/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221121171544.3291-1-shahab@synopsys.com/","msgid":"<20221121171544.3291-1-shahab@synopsys.com>","list_archive_url":null,"date":"2022-11-21T17:15:44","name":"opcodes: Correct address for ARC'\''s \"isa_config\" aux reg","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221121171544.3291-1-shahab@synopsys.com/mbox/"},{"id":24026,"url":"https://patchwork.plctlab.org/api/1.2/patches/24026/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y3vyL3UATztRRM8v@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-11-21T21:48:31","name":"PR29807, SIGSEGV when linking fuzzed PE object","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y3vyL3UATztRRM8v@squeak.grove.modra.org/mbox/"},{"id":24269,"url":"https://patchwork.plctlab.org/api/1.2/patches/24269/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221122110927.2328582-1-christoph.muellner@vrull.eu/","msgid":"<20221122110927.2328582-1-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2022-11-22T11:09:27","name":"[v3] riscv: Add AIA extension support (Smaia, Ssaia)","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221122110927.2328582-1-christoph.muellner@vrull.eu/mbox/"},{"id":24318,"url":"https://patchwork.plctlab.org/api/1.2/patches/24318/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221122120339.23186-1-shahab@synopsys.com/","msgid":"<20221122120339.23186-1-shahab@synopsys.com>","list_archive_url":null,"date":"2022-11-22T12:03:39","name":"[PUSHED] opcodes: Correct address for ARC'\''s \"isa_config\" aux reg","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221122120339.23186-1-shahab@synopsys.com/mbox/"},{"id":24501,"url":"https://patchwork.plctlab.org/api/1.2/patches/24501/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221122181927.251937-1-hjl.tools@gmail.com/","msgid":"<20221122181927.251937-1-hjl.tools@gmail.com>","list_archive_url":null,"date":"2022-11-22T18:19:27","name":"x86: Remove libopcodes dependency","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221122181927.251937-1-hjl.tools@gmail.com/mbox/"}],"public":true,"mbox":"https://patchwork.plctlab.org/bundle/patchwork-bot/binutils-gdb_2022-11/mbox/"}]' ++ jq -rc '.[].name' ++ echo '[{"id":6,"url":"https://patchwork.plctlab.org/api/1.2/bundles/6/","web_url":"https://patchwork.plctlab.org/bundle/patchwork-bot/binutils-gdb_2022-10/","project":{"id":2,"url":"https://patchwork.plctlab.org/api/1.2/projects/2/","name":"binutils-gdb","link_name":"binutils-gdb","list_id":"binutils.sourceware.org","list_email":"binutils@sourceware.org","web_url":"https://github.com/wangliu-iscas/Patchwork-Bundles/blob/main/binutils-gdb.md","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"name":"binutils-gdb_2022-10","owner":{"id":3,"url":"https://patchwork.plctlab.org/api/1.2/users/3/","username":"patchwork-bot","first_name":"","last_name":"","email":"ouuuleilei@gmail.com"},"patches":[{"id":1592,"url":"https://patchwork.plctlab.org/api/1.2/patches/1592/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/385d01fd-7e57-1f3f-1bae-30aa0c313d63@suse.com/","msgid":"<385d01fd-7e57-1f3f-1bae-30aa0c313d63@suse.com>","list_archive_url":null,"date":"2022-09-30T11:59:45","name":"[3/4] RISC-V/gas: don'\''t open-code insn_length()","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/385d01fd-7e57-1f3f-1bae-30aa0c313d63@suse.com/mbox/"},{"id":1594,"url":"https://patchwork.plctlab.org/api/1.2/patches/1594/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f5757acf-7b90-a0e3-5eea-3b97cc226930@suse.com/","msgid":"","list_archive_url":null,"date":"2022-09-30T12:00:12","name":"[4/4] RISC-V/gas: allow generating up to 176-bit instructions with .insn","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f5757acf-7b90-a0e3-5eea-3b97cc226930@suse.com/mbox/"},{"id":1596,"url":"https://patchwork.plctlab.org/api/1.2/patches/1596/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930140503.38233-1-chigot@adacore.com/","msgid":"<20220930140503.38233-1-chigot@adacore.com>","list_archive_url":null,"date":"2022-09-30T14:05:03","name":"ld/testsuite: consistently add board_ldflags when linking with GCC","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930140503.38233-1-chigot@adacore.com/mbox/"},{"id":1619,"url":"https://patchwork.plctlab.org/api/1.2/patches/1619/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221001014451.532772-1-maskray@google.com/","msgid":"<20221001014451.532772-1-maskray@google.com>","list_archive_url":null,"date":"2022-10-01T01:44:51","name":"gold, dwp: support zstd compressed input debug sections [PR 29641]","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221001014451.532772-1-maskray@google.com/mbox/"},{"id":1620,"url":"https://patchwork.plctlab.org/api/1.2/patches/1620/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221001023846.590825-1-maskray@google.com/","msgid":"<20221001023846.590825-1-maskray@google.com>","list_archive_url":null,"date":"2022-10-01T02:38:46","name":"gold: add --compress-debug-sections=zstd [PR 29641]","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221001023846.590825-1-maskray@google.com/mbox/"},{"id":1623,"url":"https://patchwork.plctlab.org/api/1.2/patches/1623/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b4477c7f666bdeb7f8e998633c7b0cb62310b9ef.1664599545.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-01T04:45:52","name":"[RFC,1/1] RISC-V: Implement common register pair framework","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b4477c7f666bdeb7f8e998633c7b0cb62310b9ef.1664599545.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1625,"url":"https://patchwork.plctlab.org/api/1.2/patches/1625/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/53a265a1f14d17a6f7b106082f610994c5d546e0.1664602025.git.research_trasio@irq.a4lg.com/","msgid":"<53a265a1f14d17a6f7b106082f610994c5d546e0.1664602025.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-01T05:27:31","name":"[RFC,1/1] RISC-V: Implement extension variants","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/53a265a1f14d17a6f7b106082f610994c5d546e0.1664602025.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1626,"url":"https://patchwork.plctlab.org/api/1.2/patches/1626/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8db04962aba9c780f133840a8934353a58f223fe.1664602716.git.research_trasio@irq.a4lg.com/","msgid":"<8db04962aba9c780f133840a8934353a58f223fe.1664602716.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-01T05:39:26","name":"[1/1] RISC-V: Move supervisor instructions after all unprivileged ones","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8db04962aba9c780f133840a8934353a58f223fe.1664602716.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1627,"url":"https://patchwork.plctlab.org/api/1.2/patches/1627/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221001062057.681440-1-maskray@google.com/","msgid":"<20221001062057.681440-1-maskray@google.com>","list_archive_url":null,"date":"2022-10-01T06:20:57","name":"readelf: support zstd compressed debug sections [PR 29640]","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221001062057.681440-1-maskray@google.com/mbox/"},{"id":1631,"url":"https://patchwork.plctlab.org/api/1.2/patches/1631/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/619f112539c0bdecd58e25664f1250a3479a37f5.1664707612.git.aburgess@redhat.com/","msgid":"<619f112539c0bdecd58e25664f1250a3479a37f5.1664707612.git.aburgess@redhat.com>","list_archive_url":null,"date":"2022-10-02T10:47:52","name":"[PATCHv2,2/2] opcodes/arm: add disassembler styling for arm","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/619f112539c0bdecd58e25664f1250a3479a37f5.1664707612.git.aburgess@redhat.com/mbox/"},{"id":1635,"url":"https://patchwork.plctlab.org/api/1.2/patches/1635/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221002185433.gl7dvytfh5wthifx@lug-owl.de/","msgid":"<20221002185433.gl7dvytfh5wthifx@lug-owl.de>","list_archive_url":null,"date":"2022-10-02T18:54:33","name":"diagnostics.h: GCC 13 got -Wself-move, breaks GDB build","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221002185433.gl7dvytfh5wthifx@lug-owl.de/mbox/"},{"id":1637,"url":"https://patchwork.plctlab.org/api/1.2/patches/1637/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003014313.28766-1-mark@harmstone.com/","msgid":"<20221003014313.28766-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-03T01:43:12","name":"[1/2] ld: Add --pdb option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003014313.28766-1-mark@harmstone.com/mbox/"},{"id":1638,"url":"https://patchwork.plctlab.org/api/1.2/patches/1638/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003014313.28766-2-mark@harmstone.com/","msgid":"<20221003014313.28766-2-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-03T01:43:13","name":"[2/2] ld: Add minimal pdb generation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003014313.28766-2-mark@harmstone.com/mbox/"},{"id":1640,"url":"https://patchwork.plctlab.org/api/1.2/patches/1640/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/597ed978-d121-220c-b56b-2ffb94bd091c@suse.cz/","msgid":"<597ed978-d121-220c-b56b-2ffb94bd091c@suse.cz>","list_archive_url":null,"date":"2022-10-03T07:50:38","name":"[1/2] refactor usage of compressed_debug_section_type","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/597ed978-d121-220c-b56b-2ffb94bd091c@suse.cz/mbox/"},{"id":1641,"url":"https://patchwork.plctlab.org/api/1.2/patches/1641/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b8acdd83-f33a-74b8-e21a-23719a0b1a60@suse.cz/","msgid":"","list_archive_url":null,"date":"2022-10-03T07:50:44","name":"[2/2] add --enable-default-compressed-debug-sections-algorithm configure option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b8acdd83-f33a-74b8-e21a-23719a0b1a60@suse.cz/mbox/"},{"id":1642,"url":"https://patchwork.plctlab.org/api/1.2/patches/1642/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003101328.1790113-1-aburgess@redhat.com/","msgid":"<20221003101328.1790113-1-aburgess@redhat.com>","list_archive_url":null,"date":"2022-10-03T10:13:28","name":"opcodes/riscv: style csr names as registers","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003101328.1790113-1-aburgess@redhat.com/mbox/"},{"id":1643,"url":"https://patchwork.plctlab.org/api/1.2/patches/1643/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7ba14fc4472ce97d4f7a4433cad8a571e89f82f4.1664793840.git.research_trasio@irq.a4lg.com/","msgid":"<7ba14fc4472ce97d4f7a4433cad8a571e89f82f4.1664793840.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-03T10:43:59","name":"[v3,1/6] RISC-V: Fix immediates to have \"immediate\" style","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7ba14fc4472ce97d4f7a4433cad8a571e89f82f4.1664793840.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1644,"url":"https://patchwork.plctlab.org/api/1.2/patches/1644/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a498bec37c1fd1dcda57cbf95e5f8cfba09b31d3.1664793840.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-03T10:44:00","name":"[v3,2/6] RISC-V: Fix printf argument types corresponding %x","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a498bec37c1fd1dcda57cbf95e5f8cfba09b31d3.1664793840.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1647,"url":"https://patchwork.plctlab.org/api/1.2/patches/1647/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0002ea716713ace4998a33dde0b81f4f890d10bf.1664793840.git.research_trasio@irq.a4lg.com/","msgid":"<0002ea716713ace4998a33dde0b81f4f890d10bf.1664793840.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-03T10:44:01","name":"[v3,3/6] RISC-V: Optimize riscv_disassemble_data printf","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0002ea716713ace4998a33dde0b81f4f890d10bf.1664793840.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1646,"url":"https://patchwork.plctlab.org/api/1.2/patches/1646/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c65fc3e9aa58965d6768a28c9fd7467fea9897a5.1664793840.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-03T10:44:02","name":"[v3,4/6] RISC-V: Print comma and tabs as the \"text\" style","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c65fc3e9aa58965d6768a28c9fd7467fea9897a5.1664793840.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1648,"url":"https://patchwork.plctlab.org/api/1.2/patches/1648/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5abe1d8a7694417b990e11d8f6cd6789573872e5.1664793840.git.research_trasio@irq.a4lg.com/","msgid":"<5abe1d8a7694417b990e11d8f6cd6789573872e5.1664793840.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-03T10:44:03","name":"[v3,5/6] RISC-V: Fix T-Head immediate types on printing","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5abe1d8a7694417b990e11d8f6cd6789573872e5.1664793840.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1649,"url":"https://patchwork.plctlab.org/api/1.2/patches/1649/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0b68af932117258c908db62cf87c3a15d3cdec41.1664793840.git.research_trasio@irq.a4lg.com/","msgid":"<0b68af932117258c908db62cf87c3a15d3cdec41.1664793840.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-03T10:44:04","name":"[v3,6/6] RISC-V: Print XTheadMemPair literal as \"immediate\"","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0b68af932117258c908db62cf87c3a15d3cdec41.1664793840.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1656,"url":"https://patchwork.plctlab.org/api/1.2/patches/1656/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/87lepxcd6x.fsf@redhat.com/","msgid":"<87lepxcd6x.fsf@redhat.com>","list_archive_url":null,"date":"2022-10-03T12:19:02","name":"Commit: readelf: Do not load section data from offset 0","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/87lepxcd6x.fsf@redhat.com/mbox/"},{"id":1659,"url":"https://patchwork.plctlab.org/api/1.2/patches/1659/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e0d369d419da9c0441f415da7f54352aead8f655.1664707612.git.aburgess@redhat.com/","msgid":"","list_archive_url":null,"date":"2022-10-03T16:37:36","name":"[PATCHv2,1/2] opcodes/arm: use '\''@'\'' consistently for the comment character","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e0d369d419da9c0441f415da7f54352aead8f655.1664707612.git.aburgess@redhat.com/mbox/"},{"id":1660,"url":"https://patchwork.plctlab.org/api/1.2/patches/1660/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003165848.11142-1-palmer@rivosinc.com/","msgid":"<20221003165848.11142-1-palmer@rivosinc.com>","list_archive_url":null,"date":"2022-10-03T16:58:48","name":"gas: NEWS: Mention the T-Head extensions that were recently added","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003165848.11142-1-palmer@rivosinc.com/mbox/"},{"id":1671,"url":"https://patchwork.plctlab.org/api/1.2/patches/1671/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/YzvrMEdkXjIn5Lfz@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-04T08:13:36","name":"Support objcopy changing compression to or from zstd","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/YzvrMEdkXjIn5Lfz@squeak.grove.modra.org/mbox/"},{"id":1673,"url":"https://patchwork.plctlab.org/api/1.2/patches/1673/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0bc857d306bb7c8130e5328dbe6b9ed2fed3ef87.1664873933.git.research_trasio@irq.a4lg.com/","msgid":"<0bc857d306bb7c8130e5328dbe6b9ed2fed3ef87.1664873933.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-04T08:59:07","name":"[1/2] RISC-V: Fix buffer overflow on print_insn_riscv","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0bc857d306bb7c8130e5328dbe6b9ed2fed3ef87.1664873933.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1672,"url":"https://patchwork.plctlab.org/api/1.2/patches/1672/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/89612fe01d902007bf84a7dfb0df5f85d5c166e4.1664873933.git.research_trasio@irq.a4lg.com/","msgid":"<89612fe01d902007bf84a7dfb0df5f85d5c166e4.1664873933.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-04T08:59:08","name":"[2/2] gdb/riscv: Fix buffer overflow on riscv_insn::fetch_instruction","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/89612fe01d902007bf84a7dfb0df5f85d5c166e4.1664873933.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1676,"url":"https://patchwork.plctlab.org/api/1.2/patches/1676/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fc849c94f4adcac1c4ccc5508c7a145a2f13b2a9.1664876744.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-04T09:45:49","name":"[v2,1/2] RISC-V: Fix buffer overflow on print_insn_riscv","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fc849c94f4adcac1c4ccc5508c7a145a2f13b2a9.1664876744.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1677,"url":"https://patchwork.plctlab.org/api/1.2/patches/1677/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4eb6e59ae2e790dbbf2bc92477edd281648d8814.1664876744.git.research_trasio@irq.a4lg.com/","msgid":"<4eb6e59ae2e790dbbf2bc92477edd281648d8814.1664876744.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-04T09:45:50","name":"[v2,2/2] gdb/riscv: Partial support for instructions up to 176-bits","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4eb6e59ae2e790dbbf2bc92477edd281648d8814.1664876744.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1678,"url":"https://patchwork.plctlab.org/api/1.2/patches/1678/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ebf16f9e1f45115d0793952ccb4a94d4233303f9.1664882725.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-04T11:25:56","name":"[v3,1/2] RISC-V: Fix buffer overflow on print_insn_riscv","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ebf16f9e1f45115d0793952ccb4a94d4233303f9.1664882725.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1679,"url":"https://patchwork.plctlab.org/api/1.2/patches/1679/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/83464b09b8649525259c69c853dfa2c9575a204b.1664882725.git.research_trasio@irq.a4lg.com/","msgid":"<83464b09b8649525259c69c853dfa2c9575a204b.1664882725.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-04T11:25:57","name":"[v3,2/2] gdb/riscv: Partial support for instructions up to 176-bit","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/83464b09b8649525259c69c853dfa2c9575a204b.1664882725.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1681,"url":"https://patchwork.plctlab.org/api/1.2/patches/1681/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ffa9c1d7-e8c2-a62b-ef3e-b565c0ffbe5b@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-04T13:56:27","name":"RISC-V: Zicbo{m,p,z} adjustments to riscv_multi_subset_supports_ext()","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ffa9c1d7-e8c2-a62b-ef3e-b565c0ffbe5b@suse.com/mbox/"},{"id":1690,"url":"https://patchwork.plctlab.org/api/1.2/patches/1690/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221004161720.1963953-1-vladimir.mezentsev@oracle.com/","msgid":"<20221004161720.1963953-1-vladimir.mezentsev@oracle.com>","list_archive_url":null,"date":"2022-10-04T16:17:20","name":"gprofng: fix build with --enable-pgo-build=lto","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221004161720.1963953-1-vladimir.mezentsev@oracle.com/mbox/"},{"id":1691,"url":"https://patchwork.plctlab.org/api/1.2/patches/1691/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c0211bc9c57be6c79c6d878ce147f63b657f461d.camel@espressif.com/","msgid":"","list_archive_url":null,"date":"2022-10-04T16:22:05","name":"bfd: xtensa: fix __stop_SECTION literal drop,","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c0211bc9c57be6c79c6d878ce147f63b657f461d.camel@espressif.com/mbox/"},{"id":1702,"url":"https://patchwork.plctlab.org/api/1.2/patches/1702/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5f482299-6c60-b2b3-9abe-f4a55a5a26c5@univ-grenoble-alpes.fr/","msgid":"<5f482299-6c60-b2b3-9abe-f4a55a5a26c5@univ-grenoble-alpes.fr>","list_archive_url":null,"date":"2022-10-04T20:03:20","name":"[RFC] bfd: use bfd_vma for the 64-bit version of put[lb] and get[lb]","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5f482299-6c60-b2b3-9abe-f4a55a5a26c5@univ-grenoble-alpes.fr/mbox/"},{"id":1711,"url":"https://patchwork.plctlab.org/api/1.2/patches/1711/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Yz0Gsxdxe0TePbJT@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-05T04:23:15","name":"PR29647, objdump -S looping","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Yz0Gsxdxe0TePbJT@squeak.grove.modra.org/mbox/"},{"id":1712,"url":"https://patchwork.plctlab.org/api/1.2/patches/1712/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/02d747d2-f57b-0fb5-b893-842b6cc41f2f@suse.com/","msgid":"<02d747d2-f57b-0fb5-b893-842b6cc41f2f@suse.com>","list_archive_url":null,"date":"2022-10-05T07:20:47","name":"[v3,1/7] x86: constify parse_insn()'\''s input","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/02d747d2-f57b-0fb5-b893-842b6cc41f2f@suse.com/mbox/"},{"id":1713,"url":"https://patchwork.plctlab.org/api/1.2/patches/1713/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/925cb740-4e1b-abc4-8526-aaab6faae5e1@suse.com/","msgid":"<925cb740-4e1b-abc4-8526-aaab6faae5e1@suse.com>","list_archive_url":null,"date":"2022-10-05T07:22:19","name":"[v3,2/7] x86: introduce Pass2 insn attribute","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/925cb740-4e1b-abc4-8526-aaab6faae5e1@suse.com/mbox/"},{"id":1714,"url":"https://patchwork.plctlab.org/api/1.2/patches/1714/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e16d3e78-39ca-f715-508f-a4104b8ab9a9@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-05T07:23:51","name":"[v3,3/7] x86: re-work insn/suffix recognition","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e16d3e78-39ca-f715-508f-a4104b8ab9a9@suse.com/mbox/"},{"id":1715,"url":"https://patchwork.plctlab.org/api/1.2/patches/1715/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e4e4b80b-794c-7485-1997-685adab8fb27@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-05T07:24:20","name":"[v3,4/7] x86-64: further re-work insn/suffix recognition to also cover MOVSL","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e4e4b80b-794c-7485-1997-685adab8fb27@suse.com/mbox/"},{"id":1716,"url":"https://patchwork.plctlab.org/api/1.2/patches/1716/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/540678fc-8bff-ec68-c97c-478d2631998c@suse.com/","msgid":"<540678fc-8bff-ec68-c97c-478d2631998c@suse.com>","list_archive_url":null,"date":"2022-10-05T07:24:55","name":"[v3,5/7] ix86: don'\''t recognize/derive Q suffix in the common case","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/540678fc-8bff-ec68-c97c-478d2631998c@suse.com/mbox/"},{"id":1718,"url":"https://patchwork.plctlab.org/api/1.2/patches/1718/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e4692495-7d3d-074d-14f9-364d4a9a998c@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-05T07:25:25","name":"[v3,6/7] x86-64: allow HLE store of accumulator to absolute 32-bit address","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e4692495-7d3d-074d-14f9-364d4a9a998c@suse.com/mbox/"},{"id":1717,"url":"https://patchwork.plctlab.org/api/1.2/patches/1717/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e8014ebd-d16b-17a7-9f34-3700fc164136@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-05T07:25:57","name":"[v3,7/7] x86: move bad-use-of-TLS-reloc check","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e8014ebd-d16b-17a7-9f34-3700fc164136@suse.com/mbox/"},{"id":1719,"url":"https://patchwork.plctlab.org/api/1.2/patches/1719/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1266f001-4511-2662-dba9-14b4d0317c57@suse.com/","msgid":"<1266f001-4511-2662-dba9-14b4d0317c57@suse.com>","list_archive_url":null,"date":"2022-10-05T07:40:50","name":"x86: drop \"regmask\" static variable","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1266f001-4511-2662-dba9-14b4d0317c57@suse.com/mbox/"},{"id":1751,"url":"https://patchwork.plctlab.org/api/1.2/patches/1751/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/af45c5d57c221e43101c2aa38b14f4b4ac12d011.1665031170.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-06T04:40:15","name":"[v2,1/2] RISC-V: Fallback for instructions longer than 64b","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/af45c5d57c221e43101c2aa38b14f4b4ac12d011.1665031170.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1752,"url":"https://patchwork.plctlab.org/api/1.2/patches/1752/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c6e55781245dd3e8e9b8debd6130fc5449dfbd55.1665031170.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-06T04:40:16","name":"[v2,2/2] RISC-V: Improve \"bits undefined\" diagnostics","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c6e55781245dd3e8e9b8debd6130fc5449dfbd55.1665031170.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1776,"url":"https://patchwork.plctlab.org/api/1.2/patches/1776/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d52952119e15357c0e823f8a2398999359588b4d.1665050099.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-06T09:56:30","name":"[v3,1/2] RISC-V: Fallback for instructions longer than 64b","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d52952119e15357c0e823f8a2398999359588b4d.1665050099.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1777,"url":"https://patchwork.plctlab.org/api/1.2/patches/1777/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d907b1997f60ff7823c4a23e281ec9d8ddcbf3f1.1665050099.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-06T09:56:31","name":"[v3,2/2] RISC-V: Improve \"bits undefined\" diagnostics","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d907b1997f60ff7823c4a23e281ec9d8ddcbf3f1.1665050099.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1781,"url":"https://patchwork.plctlab.org/api/1.2/patches/1781/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221006114628.304185-1-chigot@adacore.com/","msgid":"<20221006114628.304185-1-chigot@adacore.com>","list_archive_url":null,"date":"2022-10-06T11:46:28","name":"RISC-V: fix linker message when relaxation deletes bytes","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221006114628.304185-1-chigot@adacore.com/mbox/"},{"id":1801,"url":"https://patchwork.plctlab.org/api/1.2/patches/1801/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Yz+Yhyg7UewC9/kp@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-07T03:09:59","name":"PR29653, objcopy/strip: fuzzed small input file induces large output file","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Yz+Yhyg7UewC9/kp@squeak.grove.modra.org/mbox/"},{"id":1803,"url":"https://patchwork.plctlab.org/api/1.2/patches/1803/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/PH1P110MB16505D9D39EC5B1DE22FE3D5EC5F9@PH1P110MB1650.NAMP110.PROD.OUTLOOK.COM/","msgid":"","list_archive_url":null,"date":"2022-10-07T04:10:07","name":"@CPP_FOR_BUILD@ problem since binutils-2.38","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/PH1P110MB16505D9D39EC5B1DE22FE3D5EC5F9@PH1P110MB1650.NAMP110.PROD.OUTLOOK.COM/mbox/"},{"id":1827,"url":"https://patchwork.plctlab.org/api/1.2/patches/1827/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8e13bce108ac10a0c1dd911e23ec572926f7ae44.1665203374.git.research_trasio@irq.a4lg.com/","msgid":"<8e13bce108ac10a0c1dd911e23ec572926f7ae44.1665203374.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-08T04:29:53","name":"[v2,1/1] RISC-V: Test DWARF register numbers for \"fp\"","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8e13bce108ac10a0c1dd911e23ec572926f7ae44.1665203374.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1828,"url":"https://patchwork.plctlab.org/api/1.2/patches/1828/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0883001b3572e54d3fba264429c7ade2adb66610.1665203441.git.research_trasio@irq.a4lg.com/","msgid":"<0883001b3572e54d3fba264429c7ade2adb66610.1665203441.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-08T04:31:15","name":"[1/1] RISC-V: Move standard hints before all instructions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0883001b3572e54d3fba264429c7ade2adb66610.1665203441.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1829,"url":"https://patchwork.plctlab.org/api/1.2/patches/1829/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/58e16a241d7376fcae2515c6bd5a2b41d275eeba.1665203531.git.research_trasio@irq.a4lg.com/","msgid":"<58e16a241d7376fcae2515c6bd5a2b41d275eeba.1665203531.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-08T04:32:18","name":"[RFC,1/1] RISC-V: Imply '\''Zicsr'\'' from privileged extensions with CSRs","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/58e16a241d7376fcae2515c6bd5a2b41d275eeba.1665203531.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1830,"url":"https://patchwork.plctlab.org/api/1.2/patches/1830/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/cb5076fc96e8f2097779a3abcde843dcdd660031.1665203660.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-08T04:34:23","name":"[1/5] opcodes/riscv-dis.c: Tidying with comments/clarity","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/cb5076fc96e8f2097779a3abcde843dcdd660031.1665203660.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1832,"url":"https://patchwork.plctlab.org/api/1.2/patches/1832/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1f1aa0838bf9c4f10a45fcfe3c682f7efc79d9ae.1665203660.git.research_trasio@irq.a4lg.com/","msgid":"<1f1aa0838bf9c4f10a45fcfe3c682f7efc79d9ae.1665203660.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-08T04:34:24","name":"[2/5] opcodes/riscv-dis.c: Tidying with spacing","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1f1aa0838bf9c4f10a45fcfe3c682f7efc79d9ae.1665203660.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1831,"url":"https://patchwork.plctlab.org/api/1.2/patches/1831/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/740bc5e2d2618d236519b39fedd1a1d7ae4e05da.1665203660.git.research_trasio@irq.a4lg.com/","msgid":"<740bc5e2d2618d236519b39fedd1a1d7ae4e05da.1665203660.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-08T04:34:25","name":"[3/5] opcodes/riscv-dis.c: Use bool type whenever possible","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/740bc5e2d2618d236519b39fedd1a1d7ae4e05da.1665203660.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1833,"url":"https://patchwork.plctlab.org/api/1.2/patches/1833/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6e3a9c235e317f441b4383b3daa68f2051bdc149.1665203660.git.research_trasio@irq.a4lg.com/","msgid":"<6e3a9c235e317f441b4383b3daa68f2051bdc149.1665203660.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-08T04:34:26","name":"[4/5] opcodes/riscv-dis.c: Make XLEN variable static","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6e3a9c235e317f441b4383b3daa68f2051bdc149.1665203660.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1834,"url":"https://patchwork.plctlab.org/api/1.2/patches/1834/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ad929233a62d887495122721340b2f9c80392963.1665203660.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-08T04:34:27","name":"[5/5] opcodes/riscv-dis.c: Remove last_map_state","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ad929233a62d887495122721340b2f9c80392963.1665203660.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1836,"url":"https://patchwork.plctlab.org/api/1.2/patches/1836/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d07e2b6f36ea2fd5830924a9bfeda941b774b687.1665290422.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-09T05:09:22","name":"RISC-V: Move certain arrays to riscv-opc.c","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d07e2b6f36ea2fd5830924a9bfeda941b774b687.1665290422.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1844,"url":"https://patchwork.plctlab.org/api/1.2/patches/1844/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010004623.16582-1-mark@harmstone.com/","msgid":"<20221010004623.16582-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-10T00:46:22","name":"[v2,1/2] ld: Add --pdb option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010004623.16582-1-mark@harmstone.com/mbox/"},{"id":1845,"url":"https://patchwork.plctlab.org/api/1.2/patches/1845/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010004623.16582-2-mark@harmstone.com/","msgid":"<20221010004623.16582-2-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-10T00:46:23","name":"[v2,2/2] ld: Add minimal pdb generation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010004623.16582-2-mark@harmstone.com/mbox/"},{"id":1890,"url":"https://patchwork.plctlab.org/api/1.2/patches/1890/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010200433.414320-1-vladimir.mezentsev@oracle.com/","msgid":"<20221010200433.414320-1-vladimir.mezentsev@oracle.com>","list_archive_url":null,"date":"2022-10-10T20:04:33","name":"gprofng: run tests without installation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010200433.414320-1-vladimir.mezentsev@oracle.com/mbox/"},{"id":1893,"url":"https://patchwork.plctlab.org/api/1.2/patches/1893/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010230426.719238-1-vladimir.mezentsev@oracle.com/","msgid":"<20221010230426.719238-1-vladimir.mezentsev@oracle.com>","list_archive_url":null,"date":"2022-10-10T23:04:26","name":"[2/2] gprofng: use the --libdir path to find libraries","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010230426.719238-1-vladimir.mezentsev@oracle.com/mbox/"},{"id":1894,"url":"https://patchwork.plctlab.org/api/1.2/patches/1894/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010235155.842469-1-vladimir.mezentsev@oracle.com/","msgid":"<20221010235155.842469-1-vladimir.mezentsev@oracle.com>","list_archive_url":null,"date":"2022-10-10T23:51:55","name":"[3/3] gprofng: no need to build version.texi","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010235155.842469-1-vladimir.mezentsev@oracle.com/mbox/"},{"id":1895,"url":"https://patchwork.plctlab.org/api/1.2/patches/1895/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011003702.4287-1-mark@harmstone.com/","msgid":"<20221011003702.4287-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-11T00:37:01","name":"[v3,1/2] ld: Add --pdb option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011003702.4287-1-mark@harmstone.com/mbox/"},{"id":1897,"url":"https://patchwork.plctlab.org/api/1.2/patches/1897/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011003702.4287-2-mark@harmstone.com/","msgid":"<20221011003702.4287-2-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-11T00:37:02","name":"[v3,2/2] ld: Add minimal pdb generation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011003702.4287-2-mark@harmstone.com/mbox/"},{"id":1928,"url":"https://patchwork.plctlab.org/api/1.2/patches/1928/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011175332.17156-1-mark@harmstone.com/","msgid":"<20221011175332.17156-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-11T17:53:31","name":"[v4,1/2] ld: Add --pdb option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011175332.17156-1-mark@harmstone.com/mbox/"},{"id":1929,"url":"https://patchwork.plctlab.org/api/1.2/patches/1929/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011175332.17156-2-mark@harmstone.com/","msgid":"<20221011175332.17156-2-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-11T17:53:32","name":"[v4,2/2] ld: Add minimal pdb generation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011175332.17156-2-mark@harmstone.com/mbox/"},{"id":1941,"url":"https://patchwork.plctlab.org/api/1.2/patches/1941/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221012031005.237446-1-simon.marchi@polymtl.ca/","msgid":"<20221012031005.237446-1-simon.marchi@polymtl.ca>","list_archive_url":null,"date":"2022-10-12T03:10:05","name":"[pushed] Re-apply \"Pass PKG_CONFIG_PATH down from top-level Makefile\"","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221012031005.237446-1-simon.marchi@polymtl.ca/mbox/"},{"id":1976,"url":"https://patchwork.plctlab.org/api/1.2/patches/1976/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1216a3f8-2273-8681-f528-9493a66891f0@suse.com/","msgid":"<1216a3f8-2273-8681-f528-9493a66891f0@suse.com>","list_archive_url":null,"date":"2022-10-13T08:16:49","name":"[v4,1/8] x86: constify parse_insn()'\''s input","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1216a3f8-2273-8681-f528-9493a66891f0@suse.com/mbox/"},{"id":1977,"url":"https://patchwork.plctlab.org/api/1.2/patches/1977/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/11599bbe-c779-aa9f-4d5d-c2243f0e69dc@suse.com/","msgid":"<11599bbe-c779-aa9f-4d5d-c2243f0e69dc@suse.com>","list_archive_url":null,"date":"2022-10-13T08:17:17","name":"[v4,2/8] x86: introduce Pass2 insn attribute","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/11599bbe-c779-aa9f-4d5d-c2243f0e69dc@suse.com/mbox/"},{"id":1978,"url":"https://patchwork.plctlab.org/api/1.2/patches/1978/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/357273a3-060c-23db-72da-3fc9d1be3d2a@suse.com/","msgid":"<357273a3-060c-23db-72da-3fc9d1be3d2a@suse.com>","list_archive_url":null,"date":"2022-10-13T08:18:09","name":"[v4,3/8] x86: re-work insn/suffix recognition","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/357273a3-060c-23db-72da-3fc9d1be3d2a@suse.com/mbox/"},{"id":1979,"url":"https://patchwork.plctlab.org/api/1.2/patches/1979/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0ec0587f-6a7b-45b6-8346-e5d774e73636@suse.com/","msgid":"<0ec0587f-6a7b-45b6-8346-e5d774e73636@suse.com>","list_archive_url":null,"date":"2022-10-13T08:18:39","name":"[v4,4/8] x86-64: further re-work insn/suffix recognition to also cover MOVSL","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0ec0587f-6a7b-45b6-8346-e5d774e73636@suse.com/mbox/"},{"id":1980,"url":"https://patchwork.plctlab.org/api/1.2/patches/1980/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fb617d0b-8759-3169-5a65-1178b7fef3d7@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-13T08:19:34","name":"[v4,5/8] ix86: don'\''t recognize/derive Q suffix in the common case","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fb617d0b-8759-3169-5a65-1178b7fef3d7@suse.com/mbox/"},{"id":1981,"url":"https://patchwork.plctlab.org/api/1.2/patches/1981/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1df3bd01-99c5-f56c-d937-970edd42b2b8@suse.com/","msgid":"<1df3bd01-99c5-f56c-d937-970edd42b2b8@suse.com>","list_archive_url":null,"date":"2022-10-13T08:20:14","name":"[v4,6/8] x86-64: allow HLE store of accumulator to absolute 32-bit address","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1df3bd01-99c5-f56c-d937-970edd42b2b8@suse.com/mbox/"},{"id":1982,"url":"https://patchwork.plctlab.org/api/1.2/patches/1982/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8486a218-39ec-16b2-5c6c-5037196b93cf@suse.com/","msgid":"<8486a218-39ec-16b2-5c6c-5037196b93cf@suse.com>","list_archive_url":null,"date":"2022-10-13T08:21:00","name":"[v4,7/8] x86: move bad-use-of-TLS-reloc check","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8486a218-39ec-16b2-5c6c-5037196b93cf@suse.com/mbox/"},{"id":1983,"url":"https://patchwork.plctlab.org/api/1.2/patches/1983/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7d82692d-93df-fbee-9efb-2f44e8a91df3@suse.com/","msgid":"<7d82692d-93df-fbee-9efb-2f44e8a91df3@suse.com>","list_archive_url":null,"date":"2022-10-13T08:22:00","name":"[v4,8/8] x86: drop (now) stray IsString","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7d82692d-93df-fbee-9efb-2f44e8a91df3@suse.com/mbox/"},{"id":2013,"url":"https://patchwork.plctlab.org/api/1.2/patches/2013/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8ab93d7a617ad480dd786210f46db0e5aa07d1ac.1665655719.git.research_trasio@irq.a4lg.com/","msgid":"<8ab93d7a617ad480dd786210f46db0e5aa07d1ac.1665655719.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-13T10:11:41","name":"include: Declare getopt function on old GNU libc","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8ab93d7a617ad480dd786210f46db0e5aa07d1ac.1665655719.git.research_trasio@irq.a4lg.com/mbox/"},{"id":2352,"url":"https://patchwork.plctlab.org/api/1.2/patches/2352/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221013201332.2747246-1-maskray@google.com/","msgid":"<20221013201332.2747246-1-maskray@google.com>","list_archive_url":null,"date":"2022-10-13T20:13:32","name":"ld: Add --undefined-version","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221013201332.2747246-1-maskray@google.com/mbox/"},{"id":2532,"url":"https://patchwork.plctlab.org/api/1.2/patches/2532/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014063520.1428330-2-zengxiao@eswincomputing.com/","msgid":"<20221014063520.1428330-2-zengxiao@eswincomputing.com>","list_archive_url":null,"date":"2022-10-14T06:35:20","name":"[1/1] RISC-V: Make R_RISCV_SUB6 conforms to riscv abi standard","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014063520.1428330-2-zengxiao@eswincomputing.com/mbox/"},{"id":2560,"url":"https://patchwork.plctlab.org/api/1.2/patches/2560/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/027ae69a-636b-6757-297a-eec42936401e@linaro.org/","msgid":"<027ae69a-636b-6757-297a-eec42936401e@linaro.org>","list_archive_url":null,"date":"2022-10-14T07:58:22","name":"[v3] aarch64-pe support for LD, GAS and BFD","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/027ae69a-636b-6757-297a-eec42936401e@linaro.org/mbox/"},{"id":2602,"url":"https://patchwork.plctlab.org/api/1.2/patches/2602/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-2-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-2-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:39","name":"[01/10] Support Intel AVX-IFMA","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-2-haochen.jiang@intel.com/mbox/"},{"id":2608,"url":"https://patchwork.plctlab.org/api/1.2/patches/2608/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-3-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-3-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:40","name":"[02/10] Support Intel AVX-VNNI-INT8","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-3-haochen.jiang@intel.com/mbox/"},{"id":2611,"url":"https://patchwork.plctlab.org/api/1.2/patches/2611/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-4-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-4-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:41","name":"[03/10] Support Intel AVX-NE-CONVERT","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-4-haochen.jiang@intel.com/mbox/"},{"id":2610,"url":"https://patchwork.plctlab.org/api/1.2/patches/2610/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-5-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-5-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:42","name":"[04/10] Support Intel CMPccXADD","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-5-haochen.jiang@intel.com/mbox/"},{"id":2601,"url":"https://patchwork.plctlab.org/api/1.2/patches/2601/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-6-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-6-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:43","name":"[05/10] Add handler for more i386_cpu_flags","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-6-haochen.jiang@intel.com/mbox/"},{"id":2606,"url":"https://patchwork.plctlab.org/api/1.2/patches/2606/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-7-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-7-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:44","name":"[06/10] Support Intel RAO-INT","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-7-haochen.jiang@intel.com/mbox/"},{"id":2609,"url":"https://patchwork.plctlab.org/api/1.2/patches/2609/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-8-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-8-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:45","name":"[07/10] Support Intel WRMSRNS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-8-haochen.jiang@intel.com/mbox/"},{"id":2605,"url":"https://patchwork.plctlab.org/api/1.2/patches/2605/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-9-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-9-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:46","name":"[08/10] Support Intel MSRLIST","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-9-haochen.jiang@intel.com/mbox/"},{"id":2607,"url":"https://patchwork.plctlab.org/api/1.2/patches/2607/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-10-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-10-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:47","name":"[09/10] Support Intel AMX-FP16","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-10-haochen.jiang@intel.com/mbox/"},{"id":2604,"url":"https://patchwork.plctlab.org/api/1.2/patches/2604/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-11-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-11-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:48","name":"[10/10] Support Intel PREFETCHI","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-11-haochen.jiang@intel.com/mbox/"},{"id":2643,"url":"https://patchwork.plctlab.org/api/1.2/patches/2643/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7bac66be-535e-9051-d674-f2f5ba180e17@suse.com/","msgid":"<7bac66be-535e-9051-d674-f2f5ba180e17@suse.com>","list_archive_url":null,"date":"2022-10-14T10:22:34","name":"x86: fold AVX512-VNNI disassembler entries with AVX-VNNI ones","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7bac66be-535e-9051-d674-f2f5ba180e17@suse.com/mbox/"},{"id":2654,"url":"https://patchwork.plctlab.org/api/1.2/patches/2654/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0lIo5+ncY/MqBEq@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-14T11:31:47","name":"PR29677, Field `the_bfd` of `asymbol` is uninitialised","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0lIo5+ncY/MqBEq@squeak.grove.modra.org/mbox/"},{"id":2656,"url":"https://patchwork.plctlab.org/api/1.2/patches/2656/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0lJksn49ZpABY89@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-14T11:35:46","name":"e200 LSP support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0lJksn49ZpABY89@squeak.grove.modra.org/mbox/"},{"id":2657,"url":"https://patchwork.plctlab.org/api/1.2/patches/2657/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0lJxxYoeD5iDYAD@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-14T11:36:39","name":"PowerPC SPE disassembly and tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0lJxxYoeD5iDYAD@squeak.grove.modra.org/mbox/"},{"id":2695,"url":"https://patchwork.plctlab.org/api/1.2/patches/2695/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/DM6PR12MB4219611F6CC2A0702884A602E7249@DM6PR12MB4219.namprd12.prod.outlook.com/","msgid":"","list_archive_url":null,"date":"2022-10-14T13:29:40","name":"Binutils: Adding new testcase for addr2line.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/DM6PR12MB4219611F6CC2A0702884A602E7249@DM6PR12MB4219.namprd12.prod.outlook.com/mbox/"},{"id":2700,"url":"https://patchwork.plctlab.org/api/1.2/patches/2700/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9fd2c88d-98b2-99a4-419f-c7235b2cf960@suse.com/","msgid":"<9fd2c88d-98b2-99a4-419f-c7235b2cf960@suse.com>","list_archive_url":null,"date":"2022-10-14T14:11:35","name":"x86: properly decode EVEX.W for AVX512_4{FMAPS,VNNIW} insns","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9fd2c88d-98b2-99a4-419f-c7235b2cf960@suse.com/mbox/"},{"id":2981,"url":"https://patchwork.plctlab.org/api/1.2/patches/2981/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0uLzalqjm4C87GN@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-16T04:42:53","name":"PowerPC se_rfmci and VLE, SPE2 and LSP insns with -many","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0uLzalqjm4C87GN@squeak.grove.modra.org/mbox/"},{"id":3152,"url":"https://patchwork.plctlab.org/api/1.2/patches/3152/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221016232419.1135-1-mark@harmstone.com/","msgid":"<20221016232419.1135-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-16T23:24:18","name":"[v5,1/2] ld: Add --pdb option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221016232419.1135-1-mark@harmstone.com/mbox/"},{"id":3151,"url":"https://patchwork.plctlab.org/api/1.2/patches/3151/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221016232419.1135-2-mark@harmstone.com/","msgid":"<20221016232419.1135-2-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-16T23:24:19","name":"[v5,2/2] ld: Add minimal pdb generation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221016232419.1135-2-mark@harmstone.com/mbox/"},{"id":3258,"url":"https://patchwork.plctlab.org/api/1.2/patches/3258/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/19c08747-fa5b-1e67-3dd2-c891a2c0c1fa@suse.com/","msgid":"<19c08747-fa5b-1e67-3dd2-c891a2c0c1fa@suse.com>","list_archive_url":null,"date":"2022-10-17T07:44:51","name":"x86: correct CPU_AMX_{BF16,INT8}_FLAGS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/19c08747-fa5b-1e67-3dd2-c891a2c0c1fa@suse.com/mbox/"},{"id":3272,"url":"https://patchwork.plctlab.org/api/1.2/patches/3272/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/85dd526c-d3a7-72dc-5444-ed5573eebec1@suse.com/","msgid":"<85dd526c-d3a7-72dc-5444-ed5573eebec1@suse.com>","list_archive_url":null,"date":"2022-10-17T08:30:12","name":"x86: generalize gas documentation for disabling of ISA extensions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/85dd526c-d3a7-72dc-5444-ed5573eebec1@suse.com/mbox/"},{"id":3759,"url":"https://patchwork.plctlab.org/api/1.2/patches/3759/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-2-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-2-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:15:58","name":"[V2,01/15] sframe.h: Add SFrame format definition","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-2-indu.bhagat@oracle.com/mbox/"},{"id":3762,"url":"https://patchwork.plctlab.org/api/1.2/patches/3762/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-3-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-3-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:15:59","name":"[V2,02/15] gas: add new command line option --gsframe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-3-indu.bhagat@oracle.com/mbox/"},{"id":3761,"url":"https://patchwork.plctlab.org/api/1.2/patches/3761/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-4-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-4-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:00","name":"[V2,03/15] gas: generate .sframe from CFI directives","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-4-indu.bhagat@oracle.com/mbox/"},{"id":3760,"url":"https://patchwork.plctlab.org/api/1.2/patches/3760/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-5-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-5-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:01","name":"[V2,04/15] gas: testsuite: add new tests for SFrame unwind info","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-5-indu.bhagat@oracle.com/mbox/"},{"id":3764,"url":"https://patchwork.plctlab.org/api/1.2/patches/3764/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-6-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-6-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:02","name":"[V2,05/15] libsframe: add the SFrame library","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-6-indu.bhagat@oracle.com/mbox/"},{"id":3766,"url":"https://patchwork.plctlab.org/api/1.2/patches/3766/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-7-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-7-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:03","name":"[V2,06/15] bfd: linker: merge .sframe sections","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-7-indu.bhagat@oracle.com/mbox/"},{"id":3763,"url":"https://patchwork.plctlab.org/api/1.2/patches/3763/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-8-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-8-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:04","name":"[V2,07/15] readelf/objdump: support for SFrame section","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-8-indu.bhagat@oracle.com/mbox/"},{"id":3765,"url":"https://patchwork.plctlab.org/api/1.2/patches/3765/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-9-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-9-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:05","name":"[V2,08/15] unwinder: generate backtrace using SFrame format","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-9-indu.bhagat@oracle.com/mbox/"},{"id":3770,"url":"https://patchwork.plctlab.org/api/1.2/patches/3770/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-10-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-10-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:06","name":"[V2,09/15] unwinder: Add SFrame unwinder tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-10-indu.bhagat@oracle.com/mbox/"},{"id":3769,"url":"https://patchwork.plctlab.org/api/1.2/patches/3769/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-11-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-11-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:07","name":"[V2,10/15] gdb: sim: buildsystem changes to accommodate libsframe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-11-indu.bhagat@oracle.com/mbox/"},{"id":3771,"url":"https://patchwork.plctlab.org/api/1.2/patches/3771/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-12-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-12-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:08","name":"[V2,11/15] libctf: add libsframe to LDFLAGS and LIBS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-12-indu.bhagat@oracle.com/mbox/"},{"id":3768,"url":"https://patchwork.plctlab.org/api/1.2/patches/3768/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-13-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-13-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:09","name":"[V2,12/15] src-release.sh: Add libsframe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-13-indu.bhagat@oracle.com/mbox/"},{"id":3767,"url":"https://patchwork.plctlab.org/api/1.2/patches/3767/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-14-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-14-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:10","name":"[V2,13/15] binutils/NEWS: add text for SFrame support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-14-indu.bhagat@oracle.com/mbox/"},{"id":3772,"url":"https://patchwork.plctlab.org/api/1.2/patches/3772/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-15-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-15-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:11","name":"[V2,14/15] gas/NEWS: add text about new command line option and SFrame support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-15-indu.bhagat@oracle.com/mbox/"},{"id":3773,"url":"https://patchwork.plctlab.org/api/1.2/patches/3773/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-16-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-16-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:12","name":"[V2,15/15] doc: add SFrame spec file","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-16-indu.bhagat@oracle.com/mbox/"},{"id":3999,"url":"https://patchwork.plctlab.org/api/1.2/patches/3999/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221018081205.17880-1-krebbel@linux.ibm.com/","msgid":"<20221018081205.17880-1-krebbel@linux.ibm.com>","list_archive_url":null,"date":"2022-10-18T08:12:05","name":"[1/1] IBM zSystems: Issue error for *DBL relocs on misaligned symbols","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221018081205.17880-1-krebbel@linux.ibm.com/mbox/"},{"id":4141,"url":"https://patchwork.plctlab.org/api/1.2/patches/4141/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/baffaf673f17692b7bcbd604b31800b189988596.camel@espressif.com/","msgid":"","list_archive_url":null,"date":"2022-10-18T12:12:07","name":"xtensa: use definitions from xtensa-config.h","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/baffaf673f17692b7bcbd604b31800b189988596.camel@espressif.com/mbox/"},{"id":4272,"url":"https://patchwork.plctlab.org/api/1.2/patches/4272/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221018174914.470062-1-hjl.tools@gmail.com/","msgid":"<20221018174914.470062-1-hjl.tools@gmail.com>","list_archive_url":null,"date":"2022-10-18T17:49:14","name":"x86: Disable AVX-VNNI when disabling AVX2","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221018174914.470062-1-hjl.tools@gmail.com/mbox/"},{"id":4998,"url":"https://patchwork.plctlab.org/api/1.2/patches/4998/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c2f76e95-09f6-1d92-7ef4-38a3c2955fcd@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-19T09:52:46","name":"x86: re-work AVX-VNNI support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c2f76e95-09f6-1d92-7ef4-38a3c2955fcd@suse.com/mbox/"},{"id":5276,"url":"https://patchwork.plctlab.org/api/1.2/patches/5276/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0/lLtlKqqsmAx0s@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-19T11:53:18","name":"Fix addr2line test for ppc64 elfv1 and mingw","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0/lLtlKqqsmAx0s@squeak.grove.modra.org/mbox/"},{"id":5424,"url":"https://patchwork.plctlab.org/api/1.2/patches/5424/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/07bfebbf3843b47e13d82d4fa16eb14fec942ef7.1666184962.git.research_trasio@irq.a4lg.com/","msgid":"<07bfebbf3843b47e13d82d4fa16eb14fec942ef7.1666184962.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:09:54","name":"binutils: Remove unused substitution PROGRAM","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/07bfebbf3843b47e13d82d4fa16eb14fec942ef7.1666184962.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5433,"url":"https://patchwork.plctlab.org/api/1.2/patches/5433/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2fa7ff719223232402e82a9c91331aea22ace1bb.1666185116.git.research_trasio@irq.a4lg.com/","msgid":"<2fa7ff719223232402e82a9c91331aea22ace1bb.1666185116.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:11:55","name":"[v2,1/8] RISC-V: Add a space at the end of pinfo","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2fa7ff719223232402e82a9c91331aea22ace1bb.1666185116.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5435,"url":"https://patchwork.plctlab.org/api/1.2/patches/5435/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1b30cce5db2cce3b8edca42ab5da114d0b8c9e93.1666185116.git.research_trasio@irq.a4lg.com/","msgid":"<1b30cce5db2cce3b8edca42ab5da114d0b8c9e93.1666185116.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:11:56","name":"[v2,2/8] RISC-V: Fix obvious misalignments ('\''Zbb'\''/'\''Zba'\'')","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1b30cce5db2cce3b8edca42ab5da114d0b8c9e93.1666185116.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5437,"url":"https://patchwork.plctlab.org/api/1.2/patches/5437/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6b0857aa1a2d15ca1cf00b4dcaae0032efbb88ff.1666185116.git.research_trasio@irq.a4lg.com/","msgid":"<6b0857aa1a2d15ca1cf00b4dcaae0032efbb88ff.1666185116.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:11:57","name":"[v2,3/8] RISC-V: Remove spaces in opcode entries","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6b0857aa1a2d15ca1cf00b4dcaae0032efbb88ff.1666185116.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5436,"url":"https://patchwork.plctlab.org/api/1.2/patches/5436/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/889d956caac0f2e95543a14afaeed97188ce384c.1666185116.git.research_trasio@irq.a4lg.com/","msgid":"<889d956caac0f2e95543a14afaeed97188ce384c.1666185116.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:11:58","name":"[v2,4/8] RISC-V: Remove unused instruction macros","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/889d956caac0f2e95543a14afaeed97188ce384c.1666185116.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5440,"url":"https://patchwork.plctlab.org/api/1.2/patches/5440/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8f226ee20d8a5ef6ad7b6c4408b44794a99d542a.1666185116.git.research_trasio@irq.a4lg.com/","msgid":"<8f226ee20d8a5ef6ad7b6c4408b44794a99d542a.1666185116.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:11:59","name":"[v2,5/8] RISC-V: Complete tidying up with SCALL and SBREAK","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8f226ee20d8a5ef6ad7b6c4408b44794a99d542a.1666185116.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5442,"url":"https://patchwork.plctlab.org/api/1.2/patches/5442/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4070184c454a05a39adf0790951e5856e6b2ecb6.1666185116.git.research_trasio@irq.a4lg.com/","msgid":"<4070184c454a05a39adf0790951e5856e6b2ecb6.1666185116.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:12:00","name":"[v2,6/8] RISC-V: Tidying up with fmv.w.x and fmv.x.w","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4070184c454a05a39adf0790951e5856e6b2ecb6.1666185116.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5438,"url":"https://patchwork.plctlab.org/api/1.2/patches/5438/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c1ccda3e7c8fb297eda46dab3936d5c5977178fc.1666185116.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-19T13:12:01","name":"[v2,7/8] RISC-V: Make alias instructions aliases","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c1ccda3e7c8fb297eda46dab3936d5c5977178fc.1666185116.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5441,"url":"https://patchwork.plctlab.org/api/1.2/patches/5441/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/413cfca82c7e8d8a2e977dfda9135903c9cb7c57.1666185116.git.research_trasio@irq.a4lg.com/","msgid":"<413cfca82c7e8d8a2e977dfda9135903c9cb7c57.1666185116.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:12:02","name":"[v2,8/8] RISC-V: Use defined mask and match values","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/413cfca82c7e8d8a2e977dfda9135903c9cb7c57.1666185116.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5439,"url":"https://patchwork.plctlab.org/api/1.2/patches/5439/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/345c5c3b3a53eab04a1e6e91197de2642095c94f.1666185237.git.research_trasio@irq.a4lg.com/","msgid":"<345c5c3b3a53eab04a1e6e91197de2642095c94f.1666185237.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:14:01","name":"RISC-V: Remove RV32EF conflict","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/345c5c3b3a53eab04a1e6e91197de2642095c94f.1666185237.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5616,"url":"https://patchwork.plctlab.org/api/1.2/patches/5616/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019145608.45213-5-haochen.jiang@intel.com/","msgid":"<20221019145608.45213-5-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T14:56:02","name":"[04/10] Support Intel CMPccXADD","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019145608.45213-5-haochen.jiang@intel.com/mbox/"},{"id":5614,"url":"https://patchwork.plctlab.org/api/1.2/patches/5614/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019145608.45213-6-haochen.jiang@intel.com/","msgid":"<20221019145608.45213-6-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T14:56:03","name":"[05/10] Add handler for more i386_cpu_flags","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019145608.45213-6-haochen.jiang@intel.com/mbox/"},{"id":5672,"url":"https://patchwork.plctlab.org/api/1.2/patches/5672/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-2-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-2-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:25","name":"[01/10] Support Intel AVX-IFMA","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-2-haochen.jiang@intel.com/mbox/"},{"id":5691,"url":"https://patchwork.plctlab.org/api/1.2/patches/5691/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-3-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-3-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:26","name":"[02/10] Support Intel AVX-VNNI-INT8","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-3-haochen.jiang@intel.com/mbox/"},{"id":5690,"url":"https://patchwork.plctlab.org/api/1.2/patches/5690/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-4-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-4-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:27","name":"[03/10] Support Intel AVX-NE-CONVERT","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-4-haochen.jiang@intel.com/mbox/"},{"id":5689,"url":"https://patchwork.plctlab.org/api/1.2/patches/5689/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-5-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-5-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:28","name":"[04/10] Support Intel CMPccXADD","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-5-haochen.jiang@intel.com/mbox/"},{"id":5676,"url":"https://patchwork.plctlab.org/api/1.2/patches/5676/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-6-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-6-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:29","name":"[05/10] Add handler for more i386_cpu_flags","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-6-haochen.jiang@intel.com/mbox/"},{"id":5677,"url":"https://patchwork.plctlab.org/api/1.2/patches/5677/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-7-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-7-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:30","name":"[06/10] Support Intel RAO-INT","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-7-haochen.jiang@intel.com/mbox/"},{"id":5681,"url":"https://patchwork.plctlab.org/api/1.2/patches/5681/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-8-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-8-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:31","name":"[07/10] Support Intel WRMSRNS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-8-haochen.jiang@intel.com/mbox/"},{"id":5682,"url":"https://patchwork.plctlab.org/api/1.2/patches/5682/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-9-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-9-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:32","name":"[08/10] Support Intel MSRLIST","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-9-haochen.jiang@intel.com/mbox/"},{"id":5673,"url":"https://patchwork.plctlab.org/api/1.2/patches/5673/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-10-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-10-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:33","name":"[09/10] Support Intel AMX-FP16","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-10-haochen.jiang@intel.com/mbox/"},{"id":5686,"url":"https://patchwork.plctlab.org/api/1.2/patches/5686/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-11-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-11-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:34","name":"[10/10] Support Intel PREFETCHI","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-11-haochen.jiang@intel.com/mbox/"},{"id":5940,"url":"https://patchwork.plctlab.org/api/1.2/patches/5940/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1CMrFUC8d9lC/NL@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-19T23:47:56","name":"Obsolete beos","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1CMrFUC8d9lC/NL@squeak.grove.modra.org/mbox/"},{"id":6080,"url":"https://patchwork.plctlab.org/api/1.2/patches/6080/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8b99d666e78ba5b9d32c7889a2161c70b3da88df.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<8b99d666e78ba5b9d32c7889a2161c70b3da88df.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:25:47","name":"[01/40] gdb/unittests: PR28413, suppress warnings generated by Gnulib","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8b99d666e78ba5b9d32c7889a2161c70b3da88df.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6081,"url":"https://patchwork.plctlab.org/api/1.2/patches/6081/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b05adb17e401d621dbdad791281bc7af7806906e.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-20T09:25:48","name":"[02/40] sim: Check known getrusage declaration existence","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b05adb17e401d621dbdad791281bc7af7806906e.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6083,"url":"https://patchwork.plctlab.org/api/1.2/patches/6083/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/796962a87e569feeafb5ef636de3c79000ae152c.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<796962a87e569feeafb5ef636de3c79000ae152c.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:25:49","name":"[03/40] sim/aarch64: Remove unused functions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/796962a87e569feeafb5ef636de3c79000ae152c.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6084,"url":"https://patchwork.plctlab.org/api/1.2/patches/6084/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/65223c79fdfd7faf132275415cd9da9852c5bec3.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<65223c79fdfd7faf132275415cd9da9852c5bec3.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:25:50","name":"[04/40] cpu/cris: Initialize some variables on CRIS CPU","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/65223c79fdfd7faf132275415cd9da9852c5bec3.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6082,"url":"https://patchwork.plctlab.org/api/1.2/patches/6082/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/24baefe92148f4b7968115ba13de9b0c863a65f6.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<24baefe92148f4b7968115ba13de9b0c863a65f6.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:25:51","name":"[05/40] cpu/cris: Add u-stall virtual unit to CRIS v32","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/24baefe92148f4b7968115ba13de9b0c863a65f6.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6087,"url":"https://patchwork.plctlab.org/api/1.2/patches/6087/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3904a5c3e80f8548150d8088a92059dd728c7ff8.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<3904a5c3e80f8548150d8088a92059dd728c7ff8.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:25:52","name":"[06/40] sim/cris: Move declarations of f_specific_init","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3904a5c3e80f8548150d8088a92059dd728c7ff8.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6091,"url":"https://patchwork.plctlab.org/api/1.2/patches/6091/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/69ef2d7dd519ed572511890a215a0f6d74e53384.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<69ef2d7dd519ed572511890a215a0f6d74e53384.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:25:53","name":"[07/40] sim/cris: Regenerate with CGEN","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/69ef2d7dd519ed572511890a215a0f6d74e53384.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6085,"url":"https://patchwork.plctlab.org/api/1.2/patches/6085/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/26a3eaf4f5d2e0db6977738ddfd65d82b36e38b2.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<26a3eaf4f5d2e0db6977738ddfd65d82b36e38b2.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:25:54","name":"[08/40] sim/erc32: Insert void parameter","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/26a3eaf4f5d2e0db6977738ddfd65d82b36e38b2.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6086,"url":"https://patchwork.plctlab.org/api/1.2/patches/6086/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/057c2f8392410494c3bc5dc98052246508e6a73e.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<057c2f8392410494c3bc5dc98052246508e6a73e.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:25:55","name":"[09/40] sim/erc32: Use int32_t as event callback argument","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/057c2f8392410494c3bc5dc98052246508e6a73e.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6090,"url":"https://patchwork.plctlab.org/api/1.2/patches/6090/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8c05aec20557191434485be347d37177a2ec5ff2.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<8c05aec20557191434485be347d37177a2ec5ff2.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:25:56","name":"[10/40] sim/erc32: Use int32_t as IRQ callback argument","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8c05aec20557191434485be347d37177a2ec5ff2.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6089,"url":"https://patchwork.plctlab.org/api/1.2/patches/6089/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/afd7757aae21743c29f2aa4135a23b31d4959e9b.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-20T09:25:57","name":"[11/40] cpu/frv: Initialize some variables","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/afd7757aae21743c29f2aa4135a23b31d4959e9b.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6088,"url":"https://patchwork.plctlab.org/api/1.2/patches/6088/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/021dbd238af5dfe74523ed229d2156a155a6bb9e.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<021dbd238af5dfe74523ed229d2156a155a6bb9e.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:25:58","name":"[12/40] sim/frv: Initialize nesr variable","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/021dbd238af5dfe74523ed229d2156a155a6bb9e.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6093,"url":"https://patchwork.plctlab.org/api/1.2/patches/6093/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/51a03f7097921cc48954210cf99e370ae8982ec8.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<51a03f7097921cc48954210cf99e370ae8982ec8.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:25:59","name":"[13/40] sim/frv: Initialize some variables","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/51a03f7097921cc48954210cf99e370ae8982ec8.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6092,"url":"https://patchwork.plctlab.org/api/1.2/patches/6092/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e1baa1be3601612266dc6ae0bdde8426ff2a42c8.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-20T09:26:00","name":"[14/40] sim/frv: Add explicit casts","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e1baa1be3601612266dc6ae0bdde8426ff2a42c8.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6095,"url":"https://patchwork.plctlab.org/api/1.2/patches/6095/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5ab303a5bdfc1da7832f8fa22f57678c9ef1a5fa.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<5ab303a5bdfc1da7832f8fa22f57678c9ef1a5fa.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:26:01","name":"[15/40] sim/h8300: Add \"+ 0x0\" to avoid self-assignments","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5ab303a5bdfc1da7832f8fa22f57678c9ef1a5fa.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6101,"url":"https://patchwork.plctlab.org/api/1.2/patches/6101/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ddff80db3328a2286fe6fbc1240d2abc1e3813eb.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-20T09:26:02","name":"[16/40] sim/lm32: fix some missing function declaration warnings","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ddff80db3328a2286fe6fbc1240d2abc1e3813eb.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6094,"url":"https://patchwork.plctlab.org/api/1.2/patches/6094/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e094b1379231d9ffb59a78cfebbcc84634c779c6.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-20T09:26:03","name":"[17/40] sim/lm32: Add explicit casts","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e094b1379231d9ffb59a78cfebbcc84634c779c6.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6141,"url":"https://patchwork.plctlab.org/api/1.2/patches/6141/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/cabebead-489b-528c-580e-933832417474@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-20T10:25:51","name":"[1/3] x86: emit {evex} prefix when disassembling ambiguous AVX512VL insns","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/cabebead-489b-528c-580e-933832417474@suse.com/mbox/"},{"id":6143,"url":"https://patchwork.plctlab.org/api/1.2/patches/6143/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a032d61c-63a0-23d1-331f-619a2b8bbde3@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-20T10:26:15","name":"[2/3] x86: consolidate VAES tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a032d61c-63a0-23d1-331f-619a2b8bbde3@suse.com/mbox/"},{"id":6142,"url":"https://patchwork.plctlab.org/api/1.2/patches/6142/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7ff09c86-2de7-dc34-3183-5187de3df5ac@suse.com/","msgid":"<7ff09c86-2de7-dc34-3183-5187de3df5ac@suse.com>","list_archive_url":null,"date":"2022-10-20T10:26:40","name":"[3/3] x86: consolidate VPCLMUL tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7ff09c86-2de7-dc34-3183-5187de3df5ac@suse.com/mbox/"},{"id":6228,"url":"https://patchwork.plctlab.org/api/1.2/patches/6228/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.LSU.2.20.2210201432170.29399@wotan.suse.de/","msgid":"","list_archive_url":null,"date":"2022-10-20T14:42:25","name":"x86-64: Use only one default max-page-size","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.LSU.2.20.2210201432170.29399@wotan.suse.de/mbox/"},{"id":6229,"url":"https://patchwork.plctlab.org/api/1.2/patches/6229/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221020144351.1398099-1-chigot@adacore.com/","msgid":"<20221020144351.1398099-1-chigot@adacore.com>","list_archive_url":null,"date":"2022-10-20T14:43:50","name":"[1/2] ld/testsuite: skip ld-elf/exclude when -shared is not supported","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221020144351.1398099-1-chigot@adacore.com/mbox/"},{"id":6230,"url":"https://patchwork.plctlab.org/api/1.2/patches/6230/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221020144351.1398099-2-chigot@adacore.com/","msgid":"<20221020144351.1398099-2-chigot@adacore.com>","list_archive_url":null,"date":"2022-10-20T14:43:51","name":"[2/2] ld/testsuite: adjust ld-arm to run shared tests only when supported","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221020144351.1398099-2-chigot@adacore.com/mbox/"},{"id":6236,"url":"https://patchwork.plctlab.org/api/1.2/patches/6236/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221020151027.GA1300@delia.home/","msgid":"<20221020151027.GA1300@delia.home>","list_archive_url":null,"date":"2022-10-20T15:10:28","name":"[RFC,top-level] Add configure test-case","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221020151027.GA1300@delia.home/mbox/"},{"id":6286,"url":"https://patchwork.plctlab.org/api/1.2/patches/6286/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221020162911.1113338-1-hjl.tools@gmail.com/","msgid":"<20221020162911.1113338-1-hjl.tools@gmail.com>","list_archive_url":null,"date":"2022-10-20T16:29:11","name":"x86: Check VEX/EVEX encoding before checking vector operands","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221020162911.1113338-1-hjl.tools@gmail.com/mbox/"},{"id":7884,"url":"https://patchwork.plctlab.org/api/1.2/patches/7884/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7e53b7980f2b3b74d2250bc87f5db94b1d888a2d.camel@espressif.com/","msgid":"<7e53b7980f2b3b74d2250bc87f5db94b1d888a2d.camel@espressif.com>","list_archive_url":null,"date":"2022-10-22T12:53:54","name":"[1/5] bfd: xtensa: move common code from ld and gas","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7e53b7980f2b3b74d2250bc87f5db94b1d888a2d.camel@espressif.com/mbox/"},{"id":7885,"url":"https://patchwork.plctlab.org/api/1.2/patches/7885/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/63f2699e6ef3e6d1ca415a6ed1187d4f64297521.camel@espressif.com/","msgid":"<63f2699e6ef3e6d1ca415a6ed1187d4f64297521.camel@espressif.com>","list_archive_url":null,"date":"2022-10-22T12:55:16","name":"[2/5] gas: xtensa: add endianness, loops, booleans options","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/63f2699e6ef3e6d1ca415a6ed1187d4f64297521.camel@espressif.com/mbox/"},{"id":7886,"url":"https://patchwork.plctlab.org/api/1.2/patches/7886/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/34d2f747237aeeda595560cfded8096d9bd1c28c.camel@espressif.com/","msgid":"<34d2f747237aeeda595560cfded8096d9bd1c28c.camel@espressif.com>","list_archive_url":null,"date":"2022-10-22T12:56:02","name":"[3/5] ld: xtensa: use default LD command line options for endianness","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/34d2f747237aeeda595560cfded8096d9bd1c28c.camel@espressif.com/mbox/"},{"id":7891,"url":"https://patchwork.plctlab.org/api/1.2/patches/7891/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/535b6208c1718b9acf3258575e1ebc0a65af9f07.camel@espressif.com/","msgid":"<535b6208c1718b9acf3258575e1ebc0a65af9f07.camel@espressif.com>","list_archive_url":null,"date":"2022-10-22T13:56:44","name":"[5/5] gdb: xtensa: add support for esp32, esp32s2, esp32s3 isa-modules","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/535b6208c1718b9acf3258575e1ebc0a65af9f07.camel@espressif.com/mbox/"},{"id":10456,"url":"https://patchwork.plctlab.org/api/1.2/patches/10456/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221025013347.68282-1-nelson@rivosinc.com/","msgid":"<20221025013347.68282-1-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-10-25T01:33:46","name":"[committed,1/2] RISC-V: Improve link time complexity.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221025013347.68282-1-nelson@rivosinc.com/mbox/"},{"id":10454,"url":"https://patchwork.plctlab.org/api/1.2/patches/10454/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221025013347.68282-2-nelson@rivosinc.com/","msgid":"<20221025013347.68282-2-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-10-25T01:33:47","name":"[committed,2/2] RISC-V: Should reset `again'\'' flag for _bfd_riscv_relax_pc.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221025013347.68282-2-nelson@rivosinc.com/mbox/"},{"id":10536,"url":"https://patchwork.plctlab.org/api/1.2/patches/10536/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/bb7b87e4-1893-5c86-4a14-92bafc818b03@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-25T07:24:56","name":"[v5,1/8] x86: constify parse_insn()'\''s input","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/bb7b87e4-1893-5c86-4a14-92bafc818b03@suse.com/mbox/"},{"id":10537,"url":"https://patchwork.plctlab.org/api/1.2/patches/10537/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b9273ae6-0218-54f8-5374-b265ed13b71a@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-25T07:25:26","name":"[v5,1/8] x86: introduce Pass2 insn attribute","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b9273ae6-0218-54f8-5374-b265ed13b71a@suse.com/mbox/"},{"id":10541,"url":"https://patchwork.plctlab.org/api/1.2/patches/10541/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7250dab9-e218-e6dd-4c74-23da9f611ab4@suse.com/","msgid":"<7250dab9-e218-e6dd-4c74-23da9f611ab4@suse.com>","list_archive_url":null,"date":"2022-10-25T07:26:11","name":"[v5,3/8] x86: re-work insn/suffix recognition","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7250dab9-e218-e6dd-4c74-23da9f611ab4@suse.com/mbox/"},{"id":10540,"url":"https://patchwork.plctlab.org/api/1.2/patches/10540/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/13fc630f-e116-0099-5c9e-2697df6519d7@suse.com/","msgid":"<13fc630f-e116-0099-5c9e-2697df6519d7@suse.com>","list_archive_url":null,"date":"2022-10-25T07:26:40","name":"[v5,4/8] ix86: don'\''t recognize/derive Q suffix in the common case","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/13fc630f-e116-0099-5c9e-2697df6519d7@suse.com/mbox/"},{"id":10543,"url":"https://patchwork.plctlab.org/api/1.2/patches/10543/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/74db429d-d203-eab8-4ae1-18b9ad416b02@suse.com/","msgid":"<74db429d-d203-eab8-4ae1-18b9ad416b02@suse.com>","list_archive_url":null,"date":"2022-10-25T07:27:11","name":"[v5,5/8] x86-64: allow HLE store of accumulator to absolute 32-bit address","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/74db429d-d203-eab8-4ae1-18b9ad416b02@suse.com/mbox/"},{"id":10542,"url":"https://patchwork.plctlab.org/api/1.2/patches/10542/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2e2f7841-de4e-b5de-e8d9-a47a6a4113c8@suse.com/","msgid":"<2e2f7841-de4e-b5de-e8d9-a47a6a4113c8@suse.com>","list_archive_url":null,"date":"2022-10-25T07:27:35","name":"[v5,6/8] x86: move bad-use-of-TLS-reloc check","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2e2f7841-de4e-b5de-e8d9-a47a6a4113c8@suse.com/mbox/"},{"id":10545,"url":"https://patchwork.plctlab.org/api/1.2/patches/10545/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/421bc96e-7591-6980-48e9-5af8c8b0775a@suse.com/","msgid":"<421bc96e-7591-6980-48e9-5af8c8b0775a@suse.com>","list_archive_url":null,"date":"2022-10-25T07:28:27","name":"[v5,7/8] x86: drop (now) stray IsString","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/421bc96e-7591-6980-48e9-5af8c8b0775a@suse.com/mbox/"},{"id":10546,"url":"https://patchwork.plctlab.org/api/1.2/patches/10546/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/06ff83d4-4633-a07b-70e5-a8e049981dd4@suse.com/","msgid":"<06ff83d4-4633-a07b-70e5-a8e049981dd4@suse.com>","list_archive_url":null,"date":"2022-10-25T07:29:18","name":"[v5,8/8] x86: further re-work insn/suffix recognition to also cover MOVSX","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/06ff83d4-4633-a07b-70e5-a8e049981dd4@suse.com/mbox/"},{"id":10777,"url":"https://patchwork.plctlab.org/api/1.2/patches/10777/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6a8e7a71acccd0efb9789dfb3edfa307e83bdaa1.1666702934.git.research_trasio@irq.a4lg.com/","msgid":"<6a8e7a71acccd0efb9789dfb3edfa307e83bdaa1.1666702934.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-25T13:04:02","name":"[RFC] RISC-V: Allocate \"various\" operand type","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6a8e7a71acccd0efb9789dfb3edfa307e83bdaa1.1666702934.git.research_trasio@irq.a4lg.com/mbox/"},{"id":11062,"url":"https://patchwork.plctlab.org/api/1.2/patches/11062/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jAhwbXhxJHL66v@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-26T05:07:19","name":"PR29720, objdump -S crashes if build-id is missing","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jAhwbXhxJHL66v@squeak.grove.modra.org/mbox/"},{"id":11063,"url":"https://patchwork.plctlab.org/api/1.2/patches/11063/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jAxD+NxpMIah6s@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-26T05:08:20","name":"som.c buffer overflow","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jAxD+NxpMIah6s@squeak.grove.modra.org/mbox/"},{"id":11064,"url":"https://patchwork.plctlab.org/api/1.2/patches/11064/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jBYw4lfRQfOZhi@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-26T05:10:59","name":"som.c reloc sanity checking","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jBYw4lfRQfOZhi@squeak.grove.modra.org/mbox/"},{"id":11080,"url":"https://patchwork.plctlab.org/api/1.2/patches/11080/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jY7hygm01PelCY@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-26T06:51:26","name":"segfault in objdump.c reloc_at","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jY7hygm01PelCY@squeak.grove.modra.org/mbox/"},{"id":11081,"url":"https://patchwork.plctlab.org/api/1.2/patches/11081/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jZWIeIvCCYm9/g@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-26T06:53:12","name":"Correct ELF reloc size sanity check","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jZWIeIvCCYm9/g@squeak.grove.modra.org/mbox/"},{"id":11082,"url":"https://patchwork.plctlab.org/api/1.2/patches/11082/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221026070009.3663574-1-ysato@users.sourceforge.jp/","msgid":"<20221026070009.3663574-1-ysato@users.sourceforge.jp>","list_archive_url":null,"date":"2022-10-26T07:00:09","name":"opcodes: RX fix invalid output.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221026070009.3663574-1-ysato@users.sourceforge.jp/mbox/"},{"id":11089,"url":"https://patchwork.plctlab.org/api/1.2/patches/11089/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jhW48kuVC8Ig2d@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-26T07:27:23","name":"buffer overflow in _bfd_XX_print_ce_compressed_pdata","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jhW48kuVC8Ig2d@squeak.grove.modra.org/mbox/"},{"id":11157,"url":"https://patchwork.plctlab.org/api/1.2/patches/11157/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c52dbd16-7e1b-c356-7a92-1ff089564ef7@suse.cz/","msgid":"","list_archive_url":null,"date":"2022-10-26T08:47:09","name":"tests: use canonical option name","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c52dbd16-7e1b-c356-7a92-1ff089564ef7@suse.cz/mbox/"},{"id":11526,"url":"https://patchwork.plctlab.org/api/1.2/patches/11526/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027031915.4013-1-lifang_xia@linux.alibaba.com/","msgid":"<20221027031915.4013-1-lifang_xia@linux.alibaba.com>","list_archive_url":null,"date":"2022-10-27T03:19:15","name":"[v2] RISC-V: Optimize relax of GP/call with max_alignment.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027031915.4013-1-lifang_xia@linux.alibaba.com/mbox/"},{"id":11619,"url":"https://patchwork.plctlab.org/api/1.2/patches/11619/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9df9d9e5bb4c7594b76c40613a349b4d2364e9c5.1666854355.git.research_trasio@irq.a4lg.com/","msgid":"<9df9d9e5bb4c7594b76c40613a349b4d2364e9c5.1666854355.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-27T07:06:01","name":"include: Define macro to ignore -Wdeprecated-declarations on GCC","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9df9d9e5bb4c7594b76c40613a349b4d2364e9c5.1666854355.git.research_trasio@irq.a4lg.com/mbox/"},{"id":11627,"url":"https://patchwork.plctlab.org/api/1.2/patches/11627/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1o06O9Pp8ncCsOw@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-27T07:36:08","name":"Fuzzed files in archives","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1o06O9Pp8ncCsOw@squeak.grove.modra.org/mbox/"},{"id":11658,"url":"https://patchwork.plctlab.org/api/1.2/patches/11658/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027084808.37252-1-nelson@rivosinc.com/","msgid":"<20221027084808.37252-1-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-10-27T08:48:08","name":"[committed] RISC-V: Fix build failures for -Werror=sign-compare.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027084808.37252-1-nelson@rivosinc.com/mbox/"},{"id":11921,"url":"https://patchwork.plctlab.org/api/1.2/patches/11921/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027190052.10536-1-mark@harmstone.com/","msgid":"<20221027190052.10536-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-27T19:00:51","name":"[1/2] ld: Add section header stream to PDB files","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027190052.10536-1-mark@harmstone.com/mbox/"},{"id":11922,"url":"https://patchwork.plctlab.org/api/1.2/patches/11922/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027190052.10536-2-mark@harmstone.com/","msgid":"<20221027190052.10536-2-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-27T19:00:52","name":"[2/2] ld: Add publics stream to PDB files","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027190052.10536-2-mark@harmstone.com/mbox/"},{"id":11965,"url":"https://patchwork.plctlab.org/api/1.2/patches/11965/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027202719.32497-1-palmer@rivosinc.com/","msgid":"<20221027202719.32497-1-palmer@rivosinc.com>","list_archive_url":null,"date":"2022-10-27T20:27:18","name":"[1/2] gas: NEWS: Add a missing newline","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027202719.32497-1-palmer@rivosinc.com/mbox/"},{"id":11966,"url":"https://patchwork.plctlab.org/api/1.2/patches/11966/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027202719.32497-2-palmer@rivosinc.com/","msgid":"<20221027202719.32497-2-palmer@rivosinc.com>","list_archive_url":null,"date":"2022-10-27T20:27:19","name":"[2/2] gas: NEWS: Note support for RISC-V Zawrs","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027202719.32497-2-palmer@rivosinc.com/mbox/"},{"id":12016,"url":"https://patchwork.plctlab.org/api/1.2/patches/12016/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/21ec9a18-fa89-0828-f625-499680022ec7@linux.ibm.com/","msgid":"<21ec9a18-fa89-0828-f625-499680022ec7@linux.ibm.com>","list_archive_url":null,"date":"2022-10-28T00:35:19","name":"[COMMITTED] PowerPC: Add support for RFC02653 - Dense Math Facility","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/21ec9a18-fa89-0828-f625-499680022ec7@linux.ibm.com/mbox/"},{"id":12017,"url":"https://patchwork.plctlab.org/api/1.2/patches/12017/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fd94047d-a070-45a6-3840-c105391718e0@linux.ibm.com/","msgid":"","list_archive_url":null,"date":"2022-10-28T00:37:18","name":"[COMMITTED] PowerPC: Add support for RFC02658 - MMA+ Outer-Product, Instructions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fd94047d-a070-45a6-3840-c105391718e0@linux.ibm.com/mbox/"},{"id":12122,"url":"https://patchwork.plctlab.org/api/1.2/patches/12122/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ac4f3f3c7115a824f73aca6935789b14d33c9a58.1666939920.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-28T06:53:02","name":"RISC-V: Fix build failure for -Werror=maybe-uninitialized","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ac4f3f3c7115a824f73aca6935789b14d33c9a58.1666939920.git.research_trasio@irq.a4lg.com/mbox/"},{"id":12181,"url":"https://patchwork.plctlab.org/api/1.2/patches/12181/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221028093840.19164-1-nelson@rivosinc.com/","msgid":"<20221028093840.19164-1-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-10-28T09:38:40","name":"RISC-V: Added SiFive custom cache control extensions.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221028093840.19164-1-nelson@rivosinc.com/mbox/"},{"id":12211,"url":"https://patchwork.plctlab.org/api/1.2/patches/12211/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4a280588-a85b-6ed3-634b-2b9cbc128f86@suse.com/","msgid":"<4a280588-a85b-6ed3-634b-2b9cbc128f86@suse.com>","list_archive_url":null,"date":"2022-10-28T10:06:35","name":"RISC-V/gas: fix build with certain gcc versions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4a280588-a85b-6ed3-634b-2b9cbc128f86@suse.com/mbox/"},{"id":12249,"url":"https://patchwork.plctlab.org/api/1.2/patches/12249/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/eb0e1bff-675e-72db-b8b1-b0f0e50b7121@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-28T12:35:35","name":"x86: minor improvements to optimize_imm() (part III)","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/eb0e1bff-675e-72db-b8b1-b0f0e50b7121@suse.com/mbox/"},{"id":12382,"url":"https://patchwork.plctlab.org/api/1.2/patches/12382/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/17f57574936af82be381a1451eac56b3709b60bb.1666968673.git.research_trasio@irq.a4lg.com/","msgid":"<17f57574936af82be381a1451eac56b3709b60bb.1666968673.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-28T14:52:12","name":"RISC-V: Emit mapping symbol with ISA string if non-default arch is used","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/17f57574936af82be381a1451eac56b3709b60bb.1666968673.git.research_trasio@irq.a4lg.com/mbox/"},{"id":12627,"url":"https://patchwork.plctlab.org/api/1.2/patches/12627/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221029034432.49859-1-nelson@rivosinc.com/","msgid":"<20221029034432.49859-1-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-10-29T03:44:32","name":"[committed] RISC-V: Always generate mapping symbols at the start of the sections.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221029034432.49859-1-nelson@rivosinc.com/mbox/"},{"id":12629,"url":"https://patchwork.plctlab.org/api/1.2/patches/12629/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1yxgzNJg5M48uPI@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-29T04:52:19","name":"NULL dereference read in som_write_object_contents","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1yxgzNJg5M48uPI@squeak.grove.modra.org/mbox/"},{"id":12630,"url":"https://patchwork.plctlab.org/api/1.2/patches/12630/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1yxnSHLY+FeB5DQ@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-29T04:52:45","name":"Fix small objcopy memory leak","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1yxnSHLY+FeB5DQ@squeak.grove.modra.org/mbox/"},{"id":12631,"url":"https://patchwork.plctlab.org/api/1.2/patches/12631/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1yxxfpJz+Jx4KTh@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-29T04:53:25","name":"pef: sanity check before malloc","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1yxxfpJz+Jx4KTh@squeak.grove.modra.org/mbox/"},{"id":12950,"url":"https://patchwork.plctlab.org/api/1.2/patches/12950/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-2-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-2-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:36","name":"[V3,01/15] sframe.h: Add SFrame format definition","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-2-indu.bhagat@oracle.com/mbox/"},{"id":12952,"url":"https://patchwork.plctlab.org/api/1.2/patches/12952/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-3-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-3-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:37","name":"[V3,02/15] gas: add new command line option --gsframe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-3-indu.bhagat@oracle.com/mbox/"},{"id":12951,"url":"https://patchwork.plctlab.org/api/1.2/patches/12951/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-4-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-4-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:38","name":"[V3,03/15] gas: generate .sframe from CFI directives","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-4-indu.bhagat@oracle.com/mbox/"},{"id":12956,"url":"https://patchwork.plctlab.org/api/1.2/patches/12956/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-5-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-5-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:39","name":"[V3,04/15] gas: testsuite: add new tests for SFrame unwind info","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-5-indu.bhagat@oracle.com/mbox/"},{"id":12955,"url":"https://patchwork.plctlab.org/api/1.2/patches/12955/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-6-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-6-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:40","name":"[V3,05/15] libsframe: add the SFrame library","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-6-indu.bhagat@oracle.com/mbox/"},{"id":12959,"url":"https://patchwork.plctlab.org/api/1.2/patches/12959/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-7-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-7-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:41","name":"[V3,06/15] bfd: linker: merge .sframe sections","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-7-indu.bhagat@oracle.com/mbox/"},{"id":12961,"url":"https://patchwork.plctlab.org/api/1.2/patches/12961/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-8-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-8-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:42","name":"[V3,07/15] readelf/objdump: support for SFrame section","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-8-indu.bhagat@oracle.com/mbox/"},{"id":12962,"url":"https://patchwork.plctlab.org/api/1.2/patches/12962/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-9-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-9-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:43","name":"[V3,08/15] unwinder: generate backtrace using SFrame format","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-9-indu.bhagat@oracle.com/mbox/"},{"id":12963,"url":"https://patchwork.plctlab.org/api/1.2/patches/12963/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-10-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-10-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:44","name":"[V3,09/15] unwinder: Add SFrame unwinder tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-10-indu.bhagat@oracle.com/mbox/"},{"id":12964,"url":"https://patchwork.plctlab.org/api/1.2/patches/12964/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-11-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-11-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:45","name":"[V3,10/15] gdb: sim: buildsystem changes to accommodate libsframe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-11-indu.bhagat@oracle.com/mbox/"},{"id":12957,"url":"https://patchwork.plctlab.org/api/1.2/patches/12957/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-12-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-12-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:46","name":"[V3,11/15] libctf: add libsframe to LDFLAGS and LIBS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-12-indu.bhagat@oracle.com/mbox/"},{"id":12960,"url":"https://patchwork.plctlab.org/api/1.2/patches/12960/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-13-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-13-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:47","name":"[V3,12/15] src-release.sh: Add libsframe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-13-indu.bhagat@oracle.com/mbox/"},{"id":12953,"url":"https://patchwork.plctlab.org/api/1.2/patches/12953/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-14-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-14-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:48","name":"[V3,13/15] binutils/NEWS: add text for SFrame support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-14-indu.bhagat@oracle.com/mbox/"},{"id":12954,"url":"https://patchwork.plctlab.org/api/1.2/patches/12954/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-15-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-15-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:49","name":"[V3,14/15] gas/NEWS: add text about new command line option and SFrame support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-15-indu.bhagat@oracle.com/mbox/"},{"id":12958,"url":"https://patchwork.plctlab.org/api/1.2/patches/12958/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-16-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-16-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:50","name":"[V3,15/15] doc: add SFrame spec file","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-16-indu.bhagat@oracle.com/mbox/"},{"id":12988,"url":"https://patchwork.plctlab.org/api/1.2/patches/12988/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y15KFY32CyFhh/+u@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-30T09:55:33","name":"Pool section entries for DWP version 1","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y15KFY32CyFhh/+u@squeak.grove.modra.org/mbox/"},{"id":13076,"url":"https://patchwork.plctlab.org/api/1.2/patches/13076/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031001554.14615-1-mark@harmstone.com/","msgid":"<20221031001554.14615-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-31T00:15:52","name":"[v2,1/3] ld: Use %E in einfo in pdb.c","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031001554.14615-1-mark@harmstone.com/mbox/"},{"id":13078,"url":"https://patchwork.plctlab.org/api/1.2/patches/13078/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031001554.14615-2-mark@harmstone.com/","msgid":"<20221031001554.14615-2-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-31T00:15:53","name":"[v2,2/3] ld: Add section header stream to PDB files","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031001554.14615-2-mark@harmstone.com/mbox/"},{"id":13077,"url":"https://patchwork.plctlab.org/api/1.2/patches/13077/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031001554.14615-3-mark@harmstone.com/","msgid":"<20221031001554.14615-3-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-31T00:15:54","name":"[v2,3/3] ld: Add publics stream to PDB files","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031001554.14615-3-mark@harmstone.com/mbox/"},{"id":13106,"url":"https://patchwork.plctlab.org/api/1.2/patches/13106/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031030507.35588-2-haochen.jiang@intel.com/","msgid":"<20221031030507.35588-2-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-31T03:05:02","name":"[1/6] Support Intel AVX-IFMA","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031030507.35588-2-haochen.jiang@intel.com/mbox/"},{"id":13105,"url":"https://patchwork.plctlab.org/api/1.2/patches/13105/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031030507.35588-3-haochen.jiang@intel.com/","msgid":"<20221031030507.35588-3-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-31T03:05:03","name":"[2/6] Support Intel AVX-VNNI-INT8","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031030507.35588-3-haochen.jiang@intel.com/mbox/"},{"id":13103,"url":"https://patchwork.plctlab.org/api/1.2/patches/13103/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031030507.35588-4-haochen.jiang@intel.com/","msgid":"<20221031030507.35588-4-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-31T03:05:04","name":"[3/6] Support Intel CMPccXADD","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031030507.35588-4-haochen.jiang@intel.com/mbox/"},{"id":13101,"url":"https://patchwork.plctlab.org/api/1.2/patches/13101/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031030507.35588-5-haochen.jiang@intel.com/","msgid":"<20221031030507.35588-5-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-31T03:05:05","name":"[4/6] Add handler for more i386_cpu_flags","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031030507.35588-5-haochen.jiang@intel.com/mbox/"},{"id":13104,"url":"https://patchwork.plctlab.org/api/1.2/patches/13104/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031030507.35588-6-haochen.jiang@intel.com/","msgid":"<20221031030507.35588-6-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-31T03:05:06","name":"[5/6] Support Intel WRMSRNS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031030507.35588-6-haochen.jiang@intel.com/mbox/"},{"id":13102,"url":"https://patchwork.plctlab.org/api/1.2/patches/13102/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031030507.35588-7-haochen.jiang@intel.com/","msgid":"<20221031030507.35588-7-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-31T03:05:07","name":"[6/6] Support Intel MSRLIST","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031030507.35588-7-haochen.jiang@intel.com/mbox/"},{"id":13120,"url":"https://patchwork.plctlab.org/api/1.2/patches/13120/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031060601.38460-2-haochen.jiang@intel.com/","msgid":"<20221031060601.38460-2-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-31T06:06:00","name":"[1/2] i386: Add and ","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031060601.38460-2-haochen.jiang@intel.com/mbox/"},{"id":13121,"url":"https://patchwork.plctlab.org/api/1.2/patches/13121/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031060601.38460-3-haochen.jiang@intel.com/","msgid":"<20221031060601.38460-3-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-31T06:06:01","name":"[2/2] Support Intel AVX-NE-CONVERT","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031060601.38460-3-haochen.jiang@intel.com/mbox/"},{"id":13188,"url":"https://patchwork.plctlab.org/api/1.2/patches/13188/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9f6f8888-4dc1-a6b0-0590-35fc8a276369@suse.com/","msgid":"<9f6f8888-4dc1-a6b0-0590-35fc8a276369@suse.com>","list_archive_url":null,"date":"2022-10-31T10:18:20","name":"x86: drop bogus Tbyte","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9f6f8888-4dc1-a6b0-0590-35fc8a276369@suse.com/mbox/"},{"id":13213,"url":"https://patchwork.plctlab.org/api/1.2/patches/13213/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4f1aac95-fea5-2279-cb18-dfcdb51a2589@arm.com/","msgid":"<4f1aac95-fea5-2279-cb18-dfcdb51a2589@arm.com>","list_archive_url":null,"date":"2022-10-31T11:14:44","name":"aarch64: Add support for Common Short Sequence Compression extension","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4f1aac95-fea5-2279-cb18-dfcdb51a2589@arm.com/mbox/"}],"public":true,"mbox":"https://patchwork.plctlab.org/bundle/patchwork-bot/binutils-gdb_2022-10/mbox/"},{"id":7,"url":"https://patchwork.plctlab.org/api/1.2/bundles/7/","web_url":"https://patchwork.plctlab.org/bundle/patchwork-bot/binutils-gdb_2022-09/","project":{"id":2,"url":"https://patchwork.plctlab.org/api/1.2/projects/2/","name":"binutils-gdb","link_name":"binutils-gdb","list_id":"binutils.sourceware.org","list_email":"binutils@sourceware.org","web_url":"https://github.com/wangliu-iscas/Patchwork-Bundles/blob/main/binutils-gdb.md","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"name":"binutils-gdb_2022-09","owner":{"id":3,"url":"https://patchwork.plctlab.org/api/1.2/users/3/","username":"patchwork-bot","first_name":"","last_name":"","email":"ouuuleilei@gmail.com"},"patches":[{"id":1573,"url":"https://patchwork.plctlab.org/api/1.2/patches/1573/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930073211.2634-1-jiawei@iscas.ac.cn/","msgid":"<20220930073211.2634-1-jiawei@iscas.ac.cn>","list_archive_url":null,"date":"2022-09-30T07:32:11","name":"[V2] RISC-V: Add Smepmp CSR '\''mseccfg'\'' define and testcases.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930073211.2634-1-jiawei@iscas.ac.cn/mbox/"},{"id":1577,"url":"https://patchwork.plctlab.org/api/1.2/patches/1577/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/76fa0c3c-2303-ebdf-a765-ac4731581517@suse.com/","msgid":"<76fa0c3c-2303-ebdf-a765-ac4731581517@suse.com>","list_archive_url":null,"date":"2022-09-30T08:54:18","name":"objcopy: avoid \"shadowing\" of remove() function name","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/76fa0c3c-2303-ebdf-a765-ac4731581517@suse.com/mbox/"},{"id":1579,"url":"https://patchwork.plctlab.org/api/1.2/patches/1579/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930085852.71213-1-nelson@rivosinc.com/","msgid":"<20220930085852.71213-1-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-09-30T08:58:51","name":"[1/2] RISC-V: Output mapping symbols with ISA string.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930085852.71213-1-nelson@rivosinc.com/mbox/"},{"id":1578,"url":"https://patchwork.plctlab.org/api/1.2/patches/1578/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930085852.71213-2-nelson@rivosinc.com/","msgid":"<20220930085852.71213-2-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-09-30T08:58:52","name":"[2/2] RISC-V: Refer mapping symbol to R_RISCV_RELAX for rvc relaxations.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930085852.71213-2-nelson@rivosinc.com/mbox/"},{"id":1581,"url":"https://patchwork.plctlab.org/api/1.2/patches/1581/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930092058.71286-1-nelson@rivosinc.com/","msgid":"<20220930092058.71286-1-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-09-30T09:20:57","name":"[1/2] RISC-V: Output mapping symbols with ISA string.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930092058.71286-1-nelson@rivosinc.com/mbox/"},{"id":1580,"url":"https://patchwork.plctlab.org/api/1.2/patches/1580/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930092058.71286-2-nelson@rivosinc.com/","msgid":"<20220930092058.71286-2-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-09-30T09:20:58","name":"[2/2] RISC-V: Refer mapping symbol to R_RISCV_RELAX for rvc relaxations.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930092058.71286-2-nelson@rivosinc.com/mbox/"},{"id":1582,"url":"https://patchwork.plctlab.org/api/1.2/patches/1582/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5874dd79-0cf5-d65c-7ea2-13adfc799c0f@suse.com/","msgid":"<5874dd79-0cf5-d65c-7ea2-13adfc799c0f@suse.com>","list_archive_url":null,"date":"2022-09-30T09:41:29","name":"RISC-V: fix build after \"Add support for arbitrary immediate encoding formats\"","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5874dd79-0cf5-d65c-7ea2-13adfc799c0f@suse.com/mbox/"},{"id":1583,"url":"https://patchwork.plctlab.org/api/1.2/patches/1583/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/57d8ac2a-5757-3776-9924-99c17ca69938@suse.com/","msgid":"<57d8ac2a-5757-3776-9924-99c17ca69938@suse.com>","list_archive_url":null,"date":"2022-09-30T09:42:08","name":"RISC-V: fallout from \"re-arrange opcode table for consistent alias handling\"","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/57d8ac2a-5757-3776-9924-99c17ca69938@suse.com/mbox/"},{"id":1584,"url":"https://patchwork.plctlab.org/api/1.2/patches/1584/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e76ef8f7-72b9-5103-cb43-9608af01d017@suse.com/","msgid":"","list_archive_url":null,"date":"2022-09-30T09:42:50","name":"RISC-V: don'\''t cast expressions'\'' X_add_number to long in diagnostics","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e76ef8f7-72b9-5103-cb43-9608af01d017@suse.com/mbox/"},{"id":1585,"url":"https://patchwork.plctlab.org/api/1.2/patches/1585/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/61355429-24b3-17d0-ab03-6fa57ee861d5@suse.cz/","msgid":"<61355429-24b3-17d0-ab03-6fa57ee861d5@suse.cz>","list_archive_url":null,"date":"2022-09-30T09:48:52","name":"[RFC] add --enable-zstd-compressed-debug-sections configure option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/61355429-24b3-17d0-ab03-6fa57ee861d5@suse.cz/mbox/"},{"id":1586,"url":"https://patchwork.plctlab.org/api/1.2/patches/1586/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930103919.323690-1-christoph.muellner@vrull.eu/","msgid":"<20220930103919.323690-1-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2022-09-30T10:39:19","name":"RISC-V: Eliminate long-casts of X_add_number in diagnostics","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930103919.323690-1-christoph.muellner@vrull.eu/mbox/"},{"id":1590,"url":"https://patchwork.plctlab.org/api/1.2/patches/1590/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/DM6PR12MB4219C943049C6D883DEA3E55E7569@DM6PR12MB4219.namprd12.prod.outlook.com/","msgid":"","list_archive_url":null,"date":"2022-09-30T11:41:37","name":"[V2] Ignore DWARF debug information for -gsplit-dwarf with dwarf-5.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/DM6PR12MB4219C943049C6D883DEA3E55E7569@DM6PR12MB4219.namprd12.prod.outlook.com/mbox/"},{"id":1591,"url":"https://patchwork.plctlab.org/api/1.2/patches/1591/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c10321f9-d289-ef84-d263-bc278fb3d31b@suse.com/","msgid":"","list_archive_url":null,"date":"2022-09-30T11:59:04","name":"[1/4] RISC-V/gas: drop riscv_subsets static variable","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c10321f9-d289-ef84-d263-bc278fb3d31b@suse.com/mbox/"},{"id":1593,"url":"https://patchwork.plctlab.org/api/1.2/patches/1593/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3244eea0-c18c-e49a-4588-d69423130226@suse.com/","msgid":"<3244eea0-c18c-e49a-4588-d69423130226@suse.com>","list_archive_url":null,"date":"2022-09-30T11:59:23","name":"[2/4] RISC-V/gas: drop stray call to install_insn()","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3244eea0-c18c-e49a-4588-d69423130226@suse.com/mbox/"},{"id":1592,"url":"https://patchwork.plctlab.org/api/1.2/patches/1592/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/385d01fd-7e57-1f3f-1bae-30aa0c313d63@suse.com/","msgid":"<385d01fd-7e57-1f3f-1bae-30aa0c313d63@suse.com>","list_archive_url":null,"date":"2022-09-30T11:59:45","name":"[3/4] RISC-V/gas: don'\''t open-code insn_length()","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/385d01fd-7e57-1f3f-1bae-30aa0c313d63@suse.com/mbox/"},{"id":1594,"url":"https://patchwork.plctlab.org/api/1.2/patches/1594/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f5757acf-7b90-a0e3-5eea-3b97cc226930@suse.com/","msgid":"","list_archive_url":null,"date":"2022-09-30T12:00:12","name":"[4/4] RISC-V/gas: allow generating up to 176-bit instructions with .insn","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f5757acf-7b90-a0e3-5eea-3b97cc226930@suse.com/mbox/"},{"id":1596,"url":"https://patchwork.plctlab.org/api/1.2/patches/1596/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930140503.38233-1-chigot@adacore.com/","msgid":"<20220930140503.38233-1-chigot@adacore.com>","list_archive_url":null,"date":"2022-09-30T14:05:03","name":"ld/testsuite: consistently add board_ldflags when linking with GCC","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930140503.38233-1-chigot@adacore.com/mbox/"}],"public":true,"mbox":"https://patchwork.plctlab.org/bundle/patchwork-bot/binutils-gdb_2022-09/mbox/"},{"id":9,"url":"https://patchwork.plctlab.org/api/1.2/bundles/9/","web_url":"https://patchwork.plctlab.org/bundle/patchwork-bot/binutils-gdb_2022-11/","project":{"id":2,"url":"https://patchwork.plctlab.org/api/1.2/projects/2/","name":"binutils-gdb","link_name":"binutils-gdb","list_id":"binutils.sourceware.org","list_email":"binutils@sourceware.org","web_url":"https://github.com/wangliu-iscas/Patchwork-Bundles/blob/main/binutils-gdb.md","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"name":"binutils-gdb_2022-11","owner":{"id":3,"url":"https://patchwork.plctlab.org/api/1.2/users/3/","username":"patchwork-bot","first_name":"","last_name":"","email":"ouuuleilei@gmail.com"},"patches":[{"id":13337,"url":"https://patchwork.plctlab.org/api/1.2/patches/13337/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031160625.684434-1-hjl.tools@gmail.com/","msgid":"<20221031160625.684434-1-hjl.tools@gmail.com>","list_archive_url":null,"date":"2022-10-31T16:06:25","name":"x86: Silence GCC 12 warning on tc-i386.c","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031160625.684434-1-hjl.tools@gmail.com/mbox/"},{"id":13350,"url":"https://patchwork.plctlab.org/api/1.2/patches/13350/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c8d25b29-37fe-9623-a799-e67e1f991743@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-31T17:00:56","name":"x86: simplify expressions in update_imm()","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c8d25b29-37fe-9623-a799-e67e1f991743@suse.com/mbox/"},{"id":13487,"url":"https://patchwork.plctlab.org/api/1.2/patches/13487/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/CAMe9rOohVjin92PTeeiu_dvAtzYJn4dGtu5E=OxYfbyteraZWw@mail.gmail.com/","msgid":"","list_archive_url":null,"date":"2022-11-01T00:08:04","name":"binutils: Run PR binutils/26160 test","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/CAMe9rOohVjin92PTeeiu_dvAtzYJn4dGtu5E=OxYfbyteraZWw@mail.gmail.com/mbox/"},{"id":13621,"url":"https://patchwork.plctlab.org/api/1.2/patches/13621/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221101105724.1527333-1-aburgess@redhat.com/","msgid":"<20221101105724.1527333-1-aburgess@redhat.com>","list_archive_url":null,"date":"2022-11-01T10:57:24","name":"[PUSHED] opcodes/arm: silence compiler warning about uninitialized variable use","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221101105724.1527333-1-aburgess@redhat.com/mbox/"},{"id":13628,"url":"https://patchwork.plctlab.org/api/1.2/patches/13628/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221101111802.1532080-1-aburgess@redhat.com/","msgid":"<20221101111802.1532080-1-aburgess@redhat.com>","list_archive_url":null,"date":"2022-11-01T11:18:02","name":"[PUSHED] opcodes/arm: don'\''t pass non-string literal to printf like function","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221101111802.1532080-1-aburgess@redhat.com/mbox/"},{"id":13747,"url":"https://patchwork.plctlab.org/api/1.2/patches/13747/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/yw8jbkpqk6vw.fsf@arm.com/","msgid":"","list_archive_url":null,"date":"2022-11-01T15:54:11","name":"[Binutils-2.39,backport,GAS] arm: Use DWARF numbering convention for pseudo-register representation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/yw8jbkpqk6vw.fsf@arm.com/mbox/"},{"id":13993,"url":"https://patchwork.plctlab.org/api/1.2/patches/13993/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221102020752.24441-1-mark@harmstone.com/","msgid":"<20221102020752.24441-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-11-02T02:07:52","name":"ld: Add module information substream to PDB files","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221102020752.24441-1-mark@harmstone.com/mbox/"},{"id":14028,"url":"https://patchwork.plctlab.org/api/1.2/patches/14028/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221102050430.1053-1-nelson@rivosinc.com/","msgid":"<20221102050430.1053-1-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-11-02T05:04:30","name":"[committed] RISC-V: Fixed the missing $x+arch when adding odd paddings for alignment.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221102050430.1053-1-nelson@rivosinc.com/mbox/"},{"id":14043,"url":"https://patchwork.plctlab.org/api/1.2/patches/14043/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221102063046.31551-1-rjiejie@linux.alibaba.com/","msgid":"<20221102063046.31551-1-rjiejie@linux.alibaba.com>","list_archive_url":null,"date":"2022-11-02T06:30:46","name":"gas/doc/internals.texi: fix typo","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221102063046.31551-1-rjiejie@linux.alibaba.com/mbox/"},{"id":14069,"url":"https://patchwork.plctlab.org/api/1.2/patches/14069/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221102080112.33378-1-rjiejie@linux.alibaba.com/","msgid":"<20221102080112.33378-1-rjiejie@linux.alibaba.com>","list_archive_url":null,"date":"2022-11-02T08:01:12","name":"[v2] Support multiple .eh_frame sections","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221102080112.33378-1-rjiejie@linux.alibaba.com/mbox/"},{"id":14409,"url":"https://patchwork.plctlab.org/api/1.2/patches/14409/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221102172923.4009281-1-christophe.lyon@arm.com/","msgid":"<20221102172923.4009281-1-christophe.lyon@arm.com>","list_archive_url":null,"date":"2022-11-02T17:29:23","name":"arm: PR 29739 Fix typo where '\''; '\'' should not have been replaced with '\''@'\''","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221102172923.4009281-1-christophe.lyon@arm.com/mbox/"},{"id":14588,"url":"https://patchwork.plctlab.org/api/1.2/patches/14588/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221103020409.37322-1-rjiejie@linux.alibaba.com/","msgid":"<20221103020409.37322-1-rjiejie@linux.alibaba.com>","list_archive_url":null,"date":"2022-11-03T02:04:09","name":"[v3] Support multiple .eh_frame sections","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221103020409.37322-1-rjiejie@linux.alibaba.com/mbox/"},{"id":14602,"url":"https://patchwork.plctlab.org/api/1.2/patches/14602/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221103024604.614-1-mark@harmstone.com/","msgid":"<20221103024604.614-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-11-03T02:46:04","name":"[v2] ld: Add module information substream to PDB files","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221103024604.614-1-mark@harmstone.com/mbox/"},{"id":14706,"url":"https://patchwork.plctlab.org/api/1.2/patches/14706/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221103071519.3510462-1-luis.machado@arm.com/","msgid":"<20221103071519.3510462-1-luis.machado@arm.com>","list_archive_url":null,"date":"2022-11-03T07:15:19","name":"[opcodes/arm] Fix potential null pointer dereferences","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221103071519.3510462-1-luis.machado@arm.com/mbox/"},{"id":14840,"url":"https://patchwork.plctlab.org/api/1.2/patches/14840/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/283a86ebf0941f0f63dc1a590ec3d547bd5d69e8.1667478033.git.research_trasio@irq.a4lg.com/","msgid":"<283a86ebf0941f0f63dc1a590ec3d547bd5d69e8.1667478033.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-03T12:26:28","name":"[REVIEW,ONLY,1/2] NEAR-RATIFICATION RISC-V: Add '\''Ssstateen'\'' extension and its CSRs","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/283a86ebf0941f0f63dc1a590ec3d547bd5d69e8.1667478033.git.research_trasio@irq.a4lg.com/mbox/"},{"id":14841,"url":"https://patchwork.plctlab.org/api/1.2/patches/14841/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8083ad9d5339afdeb7f1ba88ee6af0665dcc76d5.1667478033.git.research_trasio@irq.a4lg.com/","msgid":"<8083ad9d5339afdeb7f1ba88ee6af0665dcc76d5.1667478033.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-03T12:26:29","name":"[REVIEW,ONLY,2/2] NEAR-RATIFICATION RISC-V: Add platform property/capability extensions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8083ad9d5339afdeb7f1ba88ee6af0665dcc76d5.1667478033.git.research_trasio@irq.a4lg.com/mbox/"},{"id":14894,"url":"https://patchwork.plctlab.org/api/1.2/patches/14894/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e53fbf5025e59fe6a3481b9c1fe37e4f6cf6e03d.1667483581.git.aburgess@redhat.com/","msgid":"","list_archive_url":null,"date":"2022-11-03T13:58:12","name":"[1/2] opcodes/mips: use .word/.short for undefined instructions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e53fbf5025e59fe6a3481b9c1fe37e4f6cf6e03d.1667483581.git.aburgess@redhat.com/mbox/"},{"id":14893,"url":"https://patchwork.plctlab.org/api/1.2/patches/14893/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ca81edb86580566b1641ad140eb2bed385160ab7.1667483581.git.aburgess@redhat.com/","msgid":"","list_archive_url":null,"date":"2022-11-03T13:58:13","name":"[2/2] libopcodes/mips: add support for disassembler styling","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ca81edb86580566b1641ad140eb2bed385160ab7.1667483581.git.aburgess@redhat.com/mbox/"},{"id":15465,"url":"https://patchwork.plctlab.org/api/1.2/patches/15465/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/926e5154-b40b-9df8-d770-a8bf7d40e40e@suse.com/","msgid":"<926e5154-b40b-9df8-d770-a8bf7d40e40e@suse.com>","list_archive_url":null,"date":"2022-11-04T10:50:38","name":"[v6,1/7] x86: constify parse_insn()'\''s input","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/926e5154-b40b-9df8-d770-a8bf7d40e40e@suse.com/mbox/"},{"id":15466,"url":"https://patchwork.plctlab.org/api/1.2/patches/15466/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/07ef67fd-752c-ad1f-b8cb-4eaec1f420fc@suse.com/","msgid":"<07ef67fd-752c-ad1f-b8cb-4eaec1f420fc@suse.com>","list_archive_url":null,"date":"2022-11-04T10:51:34","name":"[v6,2/7] x86: re-work insn/suffix recognition","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/07ef67fd-752c-ad1f-b8cb-4eaec1f420fc@suse.com/mbox/"},{"id":15467,"url":"https://patchwork.plctlab.org/api/1.2/patches/15467/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ee8fd655-19a5-d944-0f5e-4351b88a59f9@suse.com/","msgid":"","list_archive_url":null,"date":"2022-11-04T10:52:02","name":"[v6,3/7] ix86: don'\''t recognize/derive Q suffix in the common case","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ee8fd655-19a5-d944-0f5e-4351b88a59f9@suse.com/mbox/"},{"id":15468,"url":"https://patchwork.plctlab.org/api/1.2/patches/15468/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/15ab2cf5-f1ac-e882-c415-6318f1bcc7f0@suse.com/","msgid":"<15ab2cf5-f1ac-e882-c415-6318f1bcc7f0@suse.com>","list_archive_url":null,"date":"2022-11-04T10:52:31","name":"[v6,4/7] x86-64: allow HLE store of accumulator to absolute 32-bit address","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/15ab2cf5-f1ac-e882-c415-6318f1bcc7f0@suse.com/mbox/"},{"id":15470,"url":"https://patchwork.plctlab.org/api/1.2/patches/15470/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/352d1e49-ac9f-ee86-7e9d-74f79744268b@suse.com/","msgid":"<352d1e49-ac9f-ee86-7e9d-74f79744268b@suse.com>","list_archive_url":null,"date":"2022-11-04T10:53:14","name":"[v6,5/7] x86: move bad-use-of-TLS-reloc check","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/352d1e49-ac9f-ee86-7e9d-74f79744268b@suse.com/mbox/"},{"id":15469,"url":"https://patchwork.plctlab.org/api/1.2/patches/15469/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c1913bf6-7328-e45f-69f1-20da1954af43@suse.com/","msgid":"","list_archive_url":null,"date":"2022-11-04T10:53:52","name":"[v6,6/7] x86: drop (now) stray IsString","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c1913bf6-7328-e45f-69f1-20da1954af43@suse.com/mbox/"},{"id":15471,"url":"https://patchwork.plctlab.org/api/1.2/patches/15471/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2baf6a9d-c1bf-660d-bbca-99b1604f5478@suse.com/","msgid":"<2baf6a9d-c1bf-660d-bbca-99b1604f5478@suse.com>","list_archive_url":null,"date":"2022-11-04T10:54:30","name":"[v6,7/7] x86: further re-work insn/suffix recognition to also cover MOVSX","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2baf6a9d-c1bf-660d-bbca-99b1604f5478@suse.com/mbox/"},{"id":15472,"url":"https://patchwork.plctlab.org/api/1.2/patches/15472/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104110132.694984-1-aburgess@redhat.com/","msgid":"<20221104110132.694984-1-aburgess@redhat.com>","list_archive_url":null,"date":"2022-11-04T11:01:32","name":"[PUSHED] opcodes/arm: silence compiler warning about uninitialized variable use","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104110132.694984-1-aburgess@redhat.com/mbox/"},{"id":15473,"url":"https://patchwork.plctlab.org/api/1.2/patches/15473/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104110214.129095-1-christophe.lyon@arm.com/","msgid":"<20221104110214.129095-1-christophe.lyon@arm.com>","list_archive_url":null,"date":"2022-11-04T11:02:14","name":"configure: require libzstd >= 1.4.0","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104110214.129095-1-christophe.lyon@arm.com/mbox/"},{"id":15485,"url":"https://patchwork.plctlab.org/api/1.2/patches/15485/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104115038.8957-1-nelson@rivosinc.com/","msgid":"<20221104115038.8957-1-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-11-04T11:50:37","name":"[1/2] RISC-V: File-level architecture shouldn'\''t be affected by section-level ones.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104115038.8957-1-nelson@rivosinc.com/mbox/"},{"id":15486,"url":"https://patchwork.plctlab.org/api/1.2/patches/15486/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104115038.8957-2-nelson@rivosinc.com/","msgid":"<20221104115038.8957-2-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-11-04T11:50:38","name":"[2/2] RISC-V: Clarify the suppress rule of mapping symbol with architecture string.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104115038.8957-2-nelson@rivosinc.com/mbox/"},{"id":15509,"url":"https://patchwork.plctlab.org/api/1.2/patches/15509/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/cc133c88-9ce9-5e3a-a8f7-ad72766862b9@suse.com/","msgid":"","list_archive_url":null,"date":"2022-11-04T13:12:07","name":"x86: adjust recently introduced testcases","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/cc133c88-9ce9-5e3a-a8f7-ad72766862b9@suse.com/mbox/"},{"id":15679,"url":"https://patchwork.plctlab.org/api/1.2/patches/15679/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104163328.2274371-1-chigot@adacore.com/","msgid":"<20221104163328.2274371-1-chigot@adacore.com>","list_archive_url":null,"date":"2022-11-04T16:33:28","name":"ld/testsuite: skip tests related to -shared when disabled","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104163328.2274371-1-chigot@adacore.com/mbox/"},{"id":15751,"url":"https://patchwork.plctlab.org/api/1.2/patches/15751/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104190216.1352855-1-indu.bhagat@oracle.com/","msgid":"<20221104190216.1352855-1-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-04T19:02:16","name":"[V3.1,11/15] libctf: add libsframe to LDFLAGS and LIBS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104190216.1352855-1-indu.bhagat@oracle.com/mbox/"},{"id":15792,"url":"https://patchwork.plctlab.org/api/1.2/patches/15792/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104205547.3728827-1-hjl.tools@gmail.com/","msgid":"<20221104205547.3728827-1-hjl.tools@gmail.com>","list_archive_url":null,"date":"2022-11-04T20:55:47","name":"i386: Check invalid (%dx) usage","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104205547.3728827-1-hjl.tools@gmail.com/mbox/"},{"id":15794,"url":"https://patchwork.plctlab.org/api/1.2/patches/15794/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104210134.1721620-1-indu.bhagat@oracle.com/","msgid":"<20221104210134.1721620-1-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-04T21:01:34","name":"[V3.2,11/15] libctf: add libsframe to LDFLAGS and LIBS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104210134.1721620-1-indu.bhagat@oracle.com/mbox/"},{"id":15959,"url":"https://patchwork.plctlab.org/api/1.2/patches/15959/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c620070e3e335df2b487d3836e20d251dac37525.1667651354.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-11-05T12:29:07","name":"[01/12] RISC-V: Remove unnecessary empty matching file","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c620070e3e335df2b487d3836e20d251dac37525.1667651354.git.research_trasio@irq.a4lg.com/mbox/"},{"id":15961,"url":"https://patchwork.plctlab.org/api/1.2/patches/15961/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4496235002a396043598ab9755bd8eda5c077b1f.1667651354.git.research_trasio@irq.a4lg.com/","msgid":"<4496235002a396043598ab9755bd8eda5c077b1f.1667651354.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-05T12:29:08","name":"[02/12] RISC-V: Tidy disassembler corner case tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4496235002a396043598ab9755bd8eda5c077b1f.1667651354.git.research_trasio@irq.a4lg.com/mbox/"},{"id":15960,"url":"https://patchwork.plctlab.org/api/1.2/patches/15960/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a9229a2798480f00bf12ac3c435b3ef57f867022.1667651354.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-11-05T12:29:09","name":"[03/12] RISC-V: Tidying related to '\''Zfinx'\'' disassembler test","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a9229a2798480f00bf12ac3c435b3ef57f867022.1667651354.git.research_trasio@irq.a4lg.com/mbox/"},{"id":15962,"url":"https://patchwork.plctlab.org/api/1.2/patches/15962/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6a020edd0e114a003edbaafe1088a040e9fa07e7.1667651354.git.research_trasio@irq.a4lg.com/","msgid":"<6a020edd0e114a003edbaafe1088a040e9fa07e7.1667651354.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-05T12:29:10","name":"[04/12] RISC-V: GAS: Add basic shared test utilities","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6a020edd0e114a003edbaafe1088a040e9fa07e7.1667651354.git.research_trasio@irq.a4lg.com/mbox/"},{"id":15966,"url":"https://patchwork.plctlab.org/api/1.2/patches/15966/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6fc2851a4161edc429089bd2bbd9c2bb4c0c118f.1667651354.git.research_trasio@irq.a4lg.com/","msgid":"<6fc2851a4161edc429089bd2bbd9c2bb4c0c118f.1667651354.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-05T12:29:11","name":"[05/12] RISC-V: Redefine \"nop\" test","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6fc2851a4161edc429089bd2bbd9c2bb4c0c118f.1667651354.git.research_trasio@irq.a4lg.com/mbox/"},{"id":15963,"url":"https://patchwork.plctlab.org/api/1.2/patches/15963/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7311ed3d2429000e18877d7af594890da170a7a3.1667651354.git.research_trasio@irq.a4lg.com/","msgid":"<7311ed3d2429000e18877d7af594890da170a7a3.1667651354.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-05T12:29:12","name":"[06/12] RISC-V: Reorganize/enhance {sign, zero}-extension instructions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7311ed3d2429000e18877d7af594890da170a7a3.1667651354.git.research_trasio@irq.a4lg.com/mbox/"},{"id":15968,"url":"https://patchwork.plctlab.org/api/1.2/patches/15968/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ac99c9696c156207f06c18f2d6bf423c96c5876b.1667651354.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-11-05T12:29:13","name":"[07/12] RISC-V: Combine complex extension error handling tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ac99c9696c156207f06c18f2d6bf423c96c5876b.1667651354.git.research_trasio@irq.a4lg.com/mbox/"},{"id":15970,"url":"https://patchwork.plctlab.org/api/1.2/patches/15970/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9378b9505e3e230e0a690c56e67d253e2a0f5864.1667651354.git.research_trasio@irq.a4lg.com/","msgid":"<9378b9505e3e230e0a690c56e67d253e2a0f5864.1667651354.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-05T12:29:14","name":"[08/12] RISC-V: Refine/enhance '\''M'\''/'\''Zmmul'\'' extension tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9378b9505e3e230e0a690c56e67d253e2a0f5864.1667651354.git.research_trasio@irq.a4lg.com/mbox/"},{"id":15964,"url":"https://patchwork.plctlab.org/api/1.2/patches/15964/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/82832a67f240d5857fd502d4b74fd7d841ee2d6e.1667651354.git.research_trasio@irq.a4lg.com/","msgid":"<82832a67f240d5857fd502d4b74fd7d841ee2d6e.1667651354.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-05T12:29:15","name":"[09/12] RISC-V: Combine/enhance '\''Zicbo[mz]'\'' extension tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/82832a67f240d5857fd502d4b74fd7d841ee2d6e.1667651354.git.research_trasio@irq.a4lg.com/mbox/"},{"id":15965,"url":"https://patchwork.plctlab.org/api/1.2/patches/15965/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9c47e59868a64b13e5a7bb487e3619d4f1497d78.1667651354.git.research_trasio@irq.a4lg.com/","msgid":"<9c47e59868a64b13e5a7bb487e3619d4f1497d78.1667651354.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-05T12:29:16","name":"[10/12] RISC-V: Enhance '\''Zicbop'\'' testcases","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9c47e59868a64b13e5a7bb487e3619d4f1497d78.1667651354.git.research_trasio@irq.a4lg.com/mbox/"},{"id":15967,"url":"https://patchwork.plctlab.org/api/1.2/patches/15967/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2d9befc5bc5eed80b6bd7da6d092a61b1162ecac.1667651354.git.research_trasio@irq.a4lg.com/","msgid":"<2d9befc5bc5eed80b6bd7da6d092a61b1162ecac.1667651354.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-05T12:29:17","name":"[11/12] RISC-V: Reorganize/enhance '\''Zb*'\'' extension tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2d9befc5bc5eed80b6bd7da6d092a61b1162ecac.1667651354.git.research_trasio@irq.a4lg.com/mbox/"},{"id":15969,"url":"https://patchwork.plctlab.org/api/1.2/patches/15969/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f1c5589ab606b74eeac98e3dafd4a7903450d3b2.1667651354.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-11-05T12:29:18","name":"[12/12] RISC-V: Combine/enhance '\''Zk*'\''/'\''Zbk*'\'' extension tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f1c5589ab606b74eeac98e3dafd4a7903450d3b2.1667651354.git.research_trasio@irq.a4lg.com/mbox/"},{"id":16066,"url":"https://patchwork.plctlab.org/api/1.2/patches/16066/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221106053640.1649752-1-indu.bhagat@oracle.com/","msgid":"<20221106053640.1649752-1-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-06T05:36:40","name":"[V3.1,03/15] gas: generate .sframe from CFI directives","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221106053640.1649752-1-indu.bhagat@oracle.com/mbox/"},{"id":16379,"url":"https://patchwork.plctlab.org/api/1.2/patches/16379/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221107112805.3332619-1-och95@yandex.ru/","msgid":"<20221107112805.3332619-1-och95@yandex.ru>","list_archive_url":null,"date":"2022-11-07T11:28:05","name":"gold/aarch64: Fix adrp distance check","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221107112805.3332619-1-och95@yandex.ru/mbox/"},{"id":16400,"url":"https://patchwork.plctlab.org/api/1.2/patches/16400/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221107124620.1271470-1-christoph.muellner@vrull.eu/","msgid":"<20221107124620.1271470-1-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2022-11-07T12:46:20","name":"RISC-V: xtheadfmemidx: Use fp register in mnemonics","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221107124620.1271470-1-christoph.muellner@vrull.eu/mbox/"},{"id":16594,"url":"https://patchwork.plctlab.org/api/1.2/patches/16594/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/CACVBkZ+kM2xcpwk5zHQ4bqDV7dbPjZ6cMU9tR-h62+tDTgi3Tw@mail.gmail.com/","msgid":"","list_archive_url":null,"date":"2022-11-07T17:53:35","name":"GAS fix section alignment for aarch64-pe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/CACVBkZ+kM2xcpwk5zHQ4bqDV7dbPjZ6cMU9tR-h62+tDTgi3Tw@mail.gmail.com/mbox/"},{"id":16744,"url":"https://patchwork.plctlab.org/api/1.2/patches/16744/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221107222809.924195-1-indu.bhagat@oracle.com/","msgid":"<20221107222809.924195-1-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-07T22:28:09","name":"[V3.3,11/15] libctf: add libsframe to LDFLAGS and LIBS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221107222809.924195-1-indu.bhagat@oracle.com/mbox/"},{"id":16797,"url":"https://patchwork.plctlab.org/api/1.2/patches/16797/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221108012556.66467-1-haochen.jiang@intel.com/","msgid":"<20221108012556.66467-1-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-11-08T01:25:56","name":"x86: Correct wrong comments in vex_w_table","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221108012556.66467-1-haochen.jiang@intel.com/mbox/"},{"id":16884,"url":"https://patchwork.plctlab.org/api/1.2/patches/16884/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221108054530.796968-1-markus.t.metzger@intel.com/","msgid":"<20221108054530.796968-1-markus.t.metzger@intel.com>","list_archive_url":null,"date":"2022-11-08T05:45:29","name":"[1/2] gprofng: make cpu identification available to others","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221108054530.796968-1-markus.t.metzger@intel.com/mbox/"},{"id":16885,"url":"https://patchwork.plctlab.org/api/1.2/patches/16885/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221108054530.796968-2-markus.t.metzger@intel.com/","msgid":"<20221108054530.796968-2-markus.t.metzger@intel.com>","list_archive_url":null,"date":"2022-11-08T05:45:30","name":"[2/2] gdb, btrace: use cpuident.h to implement btrace_this_cpu","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221108054530.796968-2-markus.t.metzger@intel.com/mbox/"},{"id":16995,"url":"https://patchwork.plctlab.org/api/1.2/patches/16995/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ea0daf08-4923-ebfa-dcfe-699c43d63822@suse.com/","msgid":"","list_archive_url":null,"date":"2022-11-08T11:29:40","name":"x86/Intel: don'\''t accept malformed EXTRQ / INSERTQ","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ea0daf08-4923-ebfa-dcfe-699c43d63822@suse.com/mbox/"},{"id":17057,"url":"https://patchwork.plctlab.org/api/1.2/patches/17057/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221108141352.6613-1-jwilk@jwilk.net/","msgid":"<20221108141352.6613-1-jwilk@jwilk.net>","list_archive_url":null,"date":"2022-11-08T14:13:52","name":"Fix typos in the list of objdump options","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221108141352.6613-1-jwilk@jwilk.net/mbox/"},{"id":17117,"url":"https://patchwork.plctlab.org/api/1.2/patches/17117/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1667924955-9218-1-git-send-email-apinski@marvell.com/","msgid":"<1667924955-9218-1-git-send-email-apinski@marvell.com>","list_archive_url":null,"date":"2022-11-08T16:29:15","name":"Use toplevel configure for GMP and MPFR for gdb","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1667924955-9218-1-git-send-email-apinski@marvell.com/mbox/"},{"id":17160,"url":"https://patchwork.plctlab.org/api/1.2/patches/17160/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/27382086-397f-060f-6cf6-c1d36ff6b812@linux.ibm.com/","msgid":"<27382086-397f-060f-6cf6-c1d36ff6b812@linux.ibm.com>","list_archive_url":null,"date":"2022-11-08T18:23:32","name":"[COMMITTED] PowerPC: Add XSP operand define","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/27382086-397f-060f-6cf6-c1d36ff6b812@linux.ibm.com/mbox/"},{"id":17202,"url":"https://patchwork.plctlab.org/api/1.2/patches/17202/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221108192248.1622627-1-indu.bhagat@oracle.com/","msgid":"<20221108192248.1622627-1-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-08T19:22:48","name":"libctf: use libtool for link test in configure","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221108192248.1622627-1-indu.bhagat@oracle.com/mbox/"},{"id":17262,"url":"https://patchwork.plctlab.org/api/1.2/patches/17262/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221108225030.371817-1-hjl.tools@gmail.com/","msgid":"<20221108225030.371817-1-hjl.tools@gmail.com>","list_archive_url":null,"date":"2022-11-08T22:50:30","name":"ld: Always output local symbol for relocatable link","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221108225030.371817-1-hjl.tools@gmail.com/mbox/"},{"id":17399,"url":"https://patchwork.plctlab.org/api/1.2/patches/17399/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-2-indu.bhagat@oracle.com/","msgid":"<20221109084244.261296-2-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-09T08:42:34","name":"[V4,01/11] sframe.h: Add SFrame format definition","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-2-indu.bhagat@oracle.com/mbox/"},{"id":17398,"url":"https://patchwork.plctlab.org/api/1.2/patches/17398/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-3-indu.bhagat@oracle.com/","msgid":"<20221109084244.261296-3-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-09T08:42:35","name":"[V4,02/11] gas: add new command line option --gsframe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-3-indu.bhagat@oracle.com/mbox/"},{"id":17400,"url":"https://patchwork.plctlab.org/api/1.2/patches/17400/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-4-indu.bhagat@oracle.com/","msgid":"<20221109084244.261296-4-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-09T08:42:36","name":"[V4,03/11] gas: generate .sframe from CFI directives","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-4-indu.bhagat@oracle.com/mbox/"},{"id":17403,"url":"https://patchwork.plctlab.org/api/1.2/patches/17403/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-5-indu.bhagat@oracle.com/","msgid":"<20221109084244.261296-5-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-09T08:42:37","name":"[V4,04/11] gas: testsuite: add new tests for SFrame unwind info","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-5-indu.bhagat@oracle.com/mbox/"},{"id":17407,"url":"https://patchwork.plctlab.org/api/1.2/patches/17407/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-6-indu.bhagat@oracle.com/","msgid":"<20221109084244.261296-6-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-09T08:42:38","name":"[V4,05/11] libsframe: add the SFrame library","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-6-indu.bhagat@oracle.com/mbox/"},{"id":17406,"url":"https://patchwork.plctlab.org/api/1.2/patches/17406/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-7-indu.bhagat@oracle.com/","msgid":"<20221109084244.261296-7-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-09T08:42:39","name":"[V4,06/11] bfd: linker: merge .sframe sections","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-7-indu.bhagat@oracle.com/mbox/"},{"id":17402,"url":"https://patchwork.plctlab.org/api/1.2/patches/17402/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-8-indu.bhagat@oracle.com/","msgid":"<20221109084244.261296-8-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-09T08:42:40","name":"[V4,07/11] readelf/objdump: support for SFrame section","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-8-indu.bhagat@oracle.com/mbox/"},{"id":17401,"url":"https://patchwork.plctlab.org/api/1.2/patches/17401/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-9-indu.bhagat@oracle.com/","msgid":"<20221109084244.261296-9-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-09T08:42:41","name":"[V4,08/11] src-release.sh: Add libsframe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-9-indu.bhagat@oracle.com/mbox/"},{"id":17404,"url":"https://patchwork.plctlab.org/api/1.2/patches/17404/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-10-indu.bhagat@oracle.com/","msgid":"<20221109084244.261296-10-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-09T08:42:42","name":"[V4,09/11] binutils/NEWS: add text for SFrame support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-10-indu.bhagat@oracle.com/mbox/"},{"id":17405,"url":"https://patchwork.plctlab.org/api/1.2/patches/17405/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-11-indu.bhagat@oracle.com/","msgid":"<20221109084244.261296-11-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-09T08:42:43","name":"[V4,10/11] gas/NEWS: add text about new command line option and SFrame support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-11-indu.bhagat@oracle.com/mbox/"},{"id":17418,"url":"https://patchwork.plctlab.org/api/1.2/patches/17418/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-12-indu.bhagat@oracle.com/","msgid":"<20221109084244.261296-12-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-09T08:42:44","name":"[V4,11/11] doc: add SFrame spec file","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-12-indu.bhagat@oracle.com/mbox/"},{"id":17662,"url":"https://patchwork.plctlab.org/api/1.2/patches/17662/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109162611.760465-1-chigot@adacore.com/","msgid":"<20221109162611.760465-1-chigot@adacore.com>","list_archive_url":null,"date":"2022-11-09T16:26:11","name":"ld/testsuite: skip ld-size when -shared is not supported","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109162611.760465-1-chigot@adacore.com/mbox/"},{"id":17804,"url":"https://patchwork.plctlab.org/api/1.2/patches/17804/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109202129.475283-1-hjl.tools@gmail.com/","msgid":"<20221109202129.475283-1-hjl.tools@gmail.com>","list_archive_url":null,"date":"2022-11-09T20:21:29","name":"[v2] i386: Check invalid (%dx) usage","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109202129.475283-1-hjl.tools@gmail.com/mbox/"},{"id":18043,"url":"https://patchwork.plctlab.org/api/1.2/patches/18043/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y2zOaxv1jkhwTIAi@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-11-10T10:11:55","name":"Sanity check reloc count in get_reloc_upper_bound","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y2zOaxv1jkhwTIAi@squeak.grove.modra.org/mbox/"},{"id":18044,"url":"https://patchwork.plctlab.org/api/1.2/patches/18044/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y2zOkpGuKAn+V2Tk@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-11-10T10:12:34","name":"mach-o reloc size overflow","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y2zOkpGuKAn+V2Tk@squeak.grove.modra.org/mbox/"},{"id":18045,"url":"https://patchwork.plctlab.org/api/1.2/patches/18045/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fddbca08-756a-4d78-b117-3e82dc40df8d@AZ-NEU-EX04.Arm.com/","msgid":"","list_archive_url":null,"date":"2022-11-10T10:17:38","name":"[BINTUILS] arm: Add support for Cortex-X1C CPU.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fddbca08-756a-4d78-b117-3e82dc40df8d@AZ-NEU-EX04.Arm.com/mbox/"},{"id":18051,"url":"https://patchwork.plctlab.org/api/1.2/patches/18051/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1518b510-2124-cbcb-9dcb-059dcfdc6cd4@suse.com/","msgid":"<1518b510-2124-cbcb-9dcb-059dcfdc6cd4@suse.com>","list_archive_url":null,"date":"2022-11-10T10:24:31","name":"x86: drop stray IsString from PadLock insns","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1518b510-2124-cbcb-9dcb-059dcfdc6cd4@suse.com/mbox/"},{"id":18088,"url":"https://patchwork.plctlab.org/api/1.2/patches/18088/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/25e8786d-289e-0521-baa2-2f2b85124dfe@suse.com/","msgid":"<25e8786d-289e-0521-baa2-2f2b85124dfe@suse.com>","list_archive_url":null,"date":"2022-11-10T12:12:46","name":"[v2] x86: drop stray IsString from PadLock insns","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/25e8786d-289e-0521-baa2-2f2b85124dfe@suse.com/mbox/"},{"id":18130,"url":"https://patchwork.plctlab.org/api/1.2/patches/18130/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9bb8ebe7-9e49-d60b-d586-e4d98242acda@suse.com/","msgid":"<9bb8ebe7-9e49-d60b-d586-e4d98242acda@suse.com>","list_archive_url":null,"date":"2022-11-10T13:36:16","name":"x86: drop duplicate sse4a entry from cpu_arch[]","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9bb8ebe7-9e49-d60b-d586-e4d98242acda@suse.com/mbox/"},{"id":18135,"url":"https://patchwork.plctlab.org/api/1.2/patches/18135/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/21665493-a9f9-3429-c9ae-ea69bc7751e2@suse.com/","msgid":"<21665493-a9f9-3429-c9ae-ea69bc7751e2@suse.com>","list_archive_url":null,"date":"2022-11-10T13:45:30","name":"x86: fold special-operand insn attributes into a single enum","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/21665493-a9f9-3429-c9ae-ea69bc7751e2@suse.com/mbox/"},{"id":18284,"url":"https://patchwork.plctlab.org/api/1.2/patches/18284/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1668107159-16961-1-git-send-email-apinski@marvell.com/","msgid":"<1668107159-16961-1-git-send-email-apinski@marvell.com>","list_archive_url":null,"date":"2022-11-10T19:05:59","name":"[PATCHv2] Use toplevel configure for GMP and MPFR for gdb","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1668107159-16961-1-git-send-email-apinski@marvell.com/mbox/"},{"id":18337,"url":"https://patchwork.plctlab.org/api/1.2/patches/18337/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221110224002.3798725-1-vladimir.mezentsev@oracle.com/","msgid":"<20221110224002.3798725-1-vladimir.mezentsev@oracle.com>","list_archive_url":null,"date":"2022-11-10T22:40:02","name":"gprofng: fix typo in configure.ac","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221110224002.3798725-1-vladimir.mezentsev@oracle.com/mbox/"},{"id":18424,"url":"https://patchwork.plctlab.org/api/1.2/patches/18424/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221111033040.23115-1-mark@harmstone.com/","msgid":"<20221111033040.23115-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-11-11T03:30:40","name":"ld: Add section contributions substream to PDB files","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221111033040.23115-1-mark@harmstone.com/mbox/"},{"id":18513,"url":"https://patchwork.plctlab.org/api/1.2/patches/18513/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/40e89395-1438-6cbe-aa37-1a04a724c8c7@suse.com/","msgid":"<40e89395-1438-6cbe-aa37-1a04a724c8c7@suse.com>","list_archive_url":null,"date":"2022-11-11T07:32:17","name":"gas: accept custom \".linefile .\"","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/40e89395-1438-6cbe-aa37-1a04a724c8c7@suse.com/mbox/"},{"id":18517,"url":"https://patchwork.plctlab.org/api/1.2/patches/18517/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y23642YK4HTWnn3X@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-11-11T07:33:55","name":"Sanity check SHT_MIPS_OPTIONS size","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y23642YK4HTWnn3X@squeak.grove.modra.org/mbox/"},{"id":18519,"url":"https://patchwork.plctlab.org/api/1.2/patches/18519/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y237HYVYLWv1R4b/@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-11-11T07:34:53","name":"PR28834, PR26946 sanity checking section size","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y237HYVYLWv1R4b/@squeak.grove.modra.org/mbox/"},{"id":18670,"url":"https://patchwork.plctlab.org/api/1.2/patches/18670/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c5ab35f0-595a-439c-b120-f93bd109ab96@AZ-NEU-EX04.Arm.com/","msgid":"","list_archive_url":null,"date":"2022-11-11T10:51:43","name":"[Binutils,gas] arm: Add support for new unwinder directive \".pacspval\".","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c5ab35f0-595a-439c-b120-f93bd109ab96@AZ-NEU-EX04.Arm.com/mbox/"},{"id":18672,"url":"https://patchwork.plctlab.org/api/1.2/patches/18672/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/33eb9aff-d813-44c5-8315-aeb3e339b3f2@AZ-NEU-EX04.Arm.com/","msgid":"<33eb9aff-d813-44c5-8315-aeb3e339b3f2@AZ-NEU-EX04.Arm.com>","list_archive_url":null,"date":"2022-11-11T10:53:55","name":"[Binutils,readelf] arm: Support for new pacbti unwind opcode 0xb5.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/33eb9aff-d813-44c5-8315-aeb3e339b3f2@AZ-NEU-EX04.Arm.com/mbox/"},{"id":19116,"url":"https://patchwork.plctlab.org/api/1.2/patches/19116/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y29EZ/ykU1Qe6AAw@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-11-12T06:59:51","name":"PowerPC64 paddi -Mraw","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y29EZ/ykU1Qe6AAw@squeak.grove.modra.org/mbox/"},{"id":19138,"url":"https://patchwork.plctlab.org/api/1.2/patches/19138/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221112091217.558020-1-dimitar@dinux.eu/","msgid":"<20221112091217.558020-1-dimitar@dinux.eu>","list_archive_url":null,"date":"2022-11-12T09:12:17","name":"pru: bfd: Correct default to no execstack","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221112091217.558020-1-dimitar@dinux.eu/mbox/"},{"id":19173,"url":"https://patchwork.plctlab.org/api/1.2/patches/19173/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221112124441.5084-1-patrick@monnerat.net/","msgid":"<20221112124441.5084-1-patrick@monnerat.net>","list_archive_url":null,"date":"2022-11-12T12:44:41","name":"binutils/objcopy: keep relocation while renaming a section with explicit flags","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221112124441.5084-1-patrick@monnerat.net/mbox/"},{"id":19377,"url":"https://patchwork.plctlab.org/api/1.2/patches/19377/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221113155921.1445808-1-christoph.muellner@vrull.eu/","msgid":"<20221113155921.1445808-1-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2022-11-13T15:59:20","name":"[1/2] RISC-V: Add T-Head Fmv vendor extension","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221113155921.1445808-1-christoph.muellner@vrull.eu/mbox/"},{"id":19378,"url":"https://patchwork.plctlab.org/api/1.2/patches/19378/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221113155921.1445808-2-christoph.muellner@vrull.eu/","msgid":"<20221113155921.1445808-2-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2022-11-13T15:59:21","name":"[2/2] RISC-V: Add T-Head Int vendor extension","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221113155921.1445808-2-christoph.muellner@vrull.eu/mbox/"},{"id":19850,"url":"https://patchwork.plctlab.org/api/1.2/patches/19850/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221114150348.112815-1-bwerl.dev@gmail.com/","msgid":"<20221114150348.112815-1-bwerl.dev@gmail.com>","list_archive_url":null,"date":"2022-11-14T15:03:48","name":"readelf: use fseeko for elf files >= 2 GiB on x86_64-mingw32","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221114150348.112815-1-bwerl.dev@gmail.com/mbox/"},{"id":19866,"url":"https://patchwork.plctlab.org/api/1.2/patches/19866/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3dd1c6f9-a773-c05f-44d7-12b7947072d2@suse.com/","msgid":"<3dd1c6f9-a773-c05f-44d7-12b7947072d2@suse.com>","list_archive_url":null,"date":"2022-11-14T16:12:26","name":"x86: infer No_*Suf from other insn attributes","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3dd1c6f9-a773-c05f-44d7-12b7947072d2@suse.com/mbox/"},{"id":19934,"url":"https://patchwork.plctlab.org/api/1.2/patches/19934/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f659dfbb-b84b-af86-bd8c-d177900af779@linaro.org/","msgid":"","list_archive_url":null,"date":"2022-11-14T17:24:23","name":"[V2] GAS fix alignment for aarch64-pe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f659dfbb-b84b-af86-bd8c-d177900af779@linaro.org/mbox/"},{"id":20111,"url":"https://patchwork.plctlab.org/api/1.2/patches/20111/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221115010409.24214-1-mark@harmstone.com/","msgid":"<20221115010409.24214-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-11-15T01:04:09","name":"gas: Add --gcodeview option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221115010409.24214-1-mark@harmstone.com/mbox/"},{"id":20174,"url":"https://patchwork.plctlab.org/api/1.2/patches/20174/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d305cd6178975195b025828561d59e505524ea45.1668486687.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-11-15T04:31:22","name":"[v3,1/8] RISC-V: Add a space at the end of pinfo","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d305cd6178975195b025828561d59e505524ea45.1668486687.git.research_trasio@irq.a4lg.com/mbox/"},{"id":20177,"url":"https://patchwork.plctlab.org/api/1.2/patches/20177/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2627dd5e18e59b6d976a8e6f1be39336e8a12cc3.1668486687.git.research_trasio@irq.a4lg.com/","msgid":"<2627dd5e18e59b6d976a8e6f1be39336e8a12cc3.1668486687.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-15T04:31:23","name":"[v3,2/8] RISC-V: Fix obvious misalignments ('\''Zbb'\''/'\''Zba'\'')","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2627dd5e18e59b6d976a8e6f1be39336e8a12cc3.1668486687.git.research_trasio@irq.a4lg.com/mbox/"},{"id":20173,"url":"https://patchwork.plctlab.org/api/1.2/patches/20173/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9d110279505cf502900a000a07e6e82b50f12adc.1668486687.git.research_trasio@irq.a4lg.com/","msgid":"<9d110279505cf502900a000a07e6e82b50f12adc.1668486687.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-15T04:31:24","name":"[v3,3/8] RISC-V: Remove spaces in opcode entries","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9d110279505cf502900a000a07e6e82b50f12adc.1668486687.git.research_trasio@irq.a4lg.com/mbox/"},{"id":20179,"url":"https://patchwork.plctlab.org/api/1.2/patches/20179/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8f77aa968ed9457ce1bce0a1f6449a287d0e6a18.1668486687.git.research_trasio@irq.a4lg.com/","msgid":"<8f77aa968ed9457ce1bce0a1f6449a287d0e6a18.1668486687.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-15T04:31:25","name":"[v3,4/8] RISC-V: Remove unused instruction macros","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8f77aa968ed9457ce1bce0a1f6449a287d0e6a18.1668486687.git.research_trasio@irq.a4lg.com/mbox/"},{"id":20176,"url":"https://patchwork.plctlab.org/api/1.2/patches/20176/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b43454773d597c1bc51741ef09aac960fecdfbd5.1668486687.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-11-15T04:31:26","name":"[v3,5/8] RISC-V: Complete tidying up with SCALL and SBREAK","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b43454773d597c1bc51741ef09aac960fecdfbd5.1668486687.git.research_trasio@irq.a4lg.com/mbox/"},{"id":20178,"url":"https://patchwork.plctlab.org/api/1.2/patches/20178/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/58cfec431ff2535aeb0c3fd9213933cf28864cb9.1668486687.git.research_trasio@irq.a4lg.com/","msgid":"<58cfec431ff2535aeb0c3fd9213933cf28864cb9.1668486687.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-15T04:31:27","name":"[v3,6/8] RISC-V: Tidying up with fmv.w.x and fmv.x.w","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/58cfec431ff2535aeb0c3fd9213933cf28864cb9.1668486687.git.research_trasio@irq.a4lg.com/mbox/"},{"id":20180,"url":"https://patchwork.plctlab.org/api/1.2/patches/20180/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/192f62be797f7c46a03acadb7d1bcdb83a7e9d6e.1668486687.git.research_trasio@irq.a4lg.com/","msgid":"<192f62be797f7c46a03acadb7d1bcdb83a7e9d6e.1668486687.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-15T04:31:28","name":"[v3,7/8] RISC-V: Make alias instructions aliases","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/192f62be797f7c46a03acadb7d1bcdb83a7e9d6e.1668486687.git.research_trasio@irq.a4lg.com/mbox/"},{"id":20175,"url":"https://patchwork.plctlab.org/api/1.2/patches/20175/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c89919c84067e1c2105b1857937df6405aec70fa.1668486687.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-11-15T04:31:29","name":"[v3,8/8] RISC-V: Use defined mask and match values","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c89919c84067e1c2105b1857937df6405aec70fa.1668486687.git.research_trasio@irq.a4lg.com/mbox/"},{"id":20185,"url":"https://patchwork.plctlab.org/api/1.2/patches/20185/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ebc1e98ae09f2c209ebaed2b81d5b418ce2c5128.1668487922.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-11-15T04:52:44","name":"[01/11] opcodes/riscv-dis.c: More tidying","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ebc1e98ae09f2c209ebaed2b81d5b418ce2c5128.1668487922.git.research_trasio@irq.a4lg.com/mbox/"},{"id":20188,"url":"https://patchwork.plctlab.org/api/1.2/patches/20188/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9795298f970f0b8a02796edc2c4249417614103b.1668487922.git.research_trasio@irq.a4lg.com/","msgid":"<9795298f970f0b8a02796edc2c4249417614103b.1668487922.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-15T04:52:45","name":"[02/11] RISC-V: Add test for '\''Zfinx'\'' register switching","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9795298f970f0b8a02796edc2c4249417614103b.1668487922.git.research_trasio@irq.a4lg.com/mbox/"},{"id":20186,"url":"https://patchwork.plctlab.org/api/1.2/patches/20186/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6c6c644515c6bc2751062543097eb14ee98e97c8.1668487922.git.research_trasio@irq.a4lg.com/","msgid":"<6c6c644515c6bc2751062543097eb14ee98e97c8.1668487922.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-15T04:52:46","name":"[03/11] RISC-V: Make mapping symbol checking consistent","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6c6c644515c6bc2751062543097eb14ee98e97c8.1668487922.git.research_trasio@irq.a4lg.com/mbox/"},{"id":20187,"url":"https://patchwork.plctlab.org/api/1.2/patches/20187/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b5b5ce7e34544c7934b775062413e0fe07dcd6e6.1668487922.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-11-15T04:52:47","name":"[04/11] RISC-V: Split riscv_get_map_state into two steps","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b5b5ce7e34544c7934b775062413e0fe07dcd6e6.1668487922.git.research_trasio@irq.a4lg.com/mbox/"},{"id":20192,"url":"https://patchwork.plctlab.org/api/1.2/patches/20192/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c143088cbaf7a19a992e008689420d95a90f3fab.1668487922.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-11-15T04:52:48","name":"[05/11] RISC-V: One time CSR hash table initialization","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c143088cbaf7a19a992e008689420d95a90f3fab.1668487922.git.research_trasio@irq.a4lg.com/mbox/"},{"id":20193,"url":"https://patchwork.plctlab.org/api/1.2/patches/20193/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9734125736efc8b63be17df87d38cf24bb14a156.1668487922.git.research_trasio@irq.a4lg.com/","msgid":"<9734125736efc8b63be17df87d38cf24bb14a156.1668487922.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-15T04:52:49","name":"[06/11] RISC-V: Use static xlen on ADDIW sequence","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9734125736efc8b63be17df87d38cf24bb14a156.1668487922.git.research_trasio@irq.a4lg.com/mbox/"},{"id":20191,"url":"https://patchwork.plctlab.org/api/1.2/patches/20191/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/34dbd0c82de0af284887a3bff649c8c53d67e752.1668487922.git.research_trasio@irq.a4lg.com/","msgid":"<34dbd0c82de0af284887a3bff649c8c53d67e752.1668487922.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-15T04:52:50","name":"[07/11] opcodes/riscv-dis.c: Add form feed for separation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/34dbd0c82de0af284887a3bff649c8c53d67e752.1668487922.git.research_trasio@irq.a4lg.com/mbox/"},{"id":20190,"url":"https://patchwork.plctlab.org/api/1.2/patches/20190/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1352fb8c63539727204df94651f371ed09bbce4c.1668487922.git.research_trasio@irq.a4lg.com/","msgid":"<1352fb8c63539727204df94651f371ed09bbce4c.1668487922.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-15T04:52:51","name":"[08/11] RISC-V: Split match/print steps on disassembler","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1352fb8c63539727204df94651f371ed09bbce4c.1668487922.git.research_trasio@irq.a4lg.com/mbox/"},{"id":20189,"url":"https://patchwork.plctlab.org/api/1.2/patches/20189/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/12cd8820841f695708875206b6461b6322c74428.1668487922.git.research_trasio@irq.a4lg.com/","msgid":"<12cd8820841f695708875206b6461b6322c74428.1668487922.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-15T04:52:52","name":"[09/11] RISC-V: Reorganize disassembler state initialization","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/12cd8820841f695708875206b6461b6322c74428.1668487922.git.research_trasio@irq.a4lg.com/mbox/"},{"id":20194,"url":"https://patchwork.plctlab.org/api/1.2/patches/20194/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6aade17e12ce2a928d044d9f148c874cf9922da8.1668487922.git.research_trasio@irq.a4lg.com/","msgid":"<6aade17e12ce2a928d044d9f148c874cf9922da8.1668487922.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-15T04:52:53","name":"[10/11] RISC-V: Reorganize arch-related initialization and management","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6aade17e12ce2a928d044d9f148c874cf9922da8.1668487922.git.research_trasio@irq.a4lg.com/mbox/"},{"id":20195,"url":"https://patchwork.plctlab.org/api/1.2/patches/20195/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a239fb0682bd24d4f1eb3014685eed78f9ea779a.1668487922.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-11-15T04:52:54","name":"[11/11] RISC-V: Move disassembler private data initialization","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a239fb0682bd24d4f1eb3014685eed78f9ea779a.1668487922.git.research_trasio@irq.a4lg.com/mbox/"},{"id":20236,"url":"https://patchwork.plctlab.org/api/1.2/patches/20236/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221115081455.2354987-2-zengxiao@eswincomputing.com/","msgid":"<20221115081455.2354987-2-zengxiao@eswincomputing.com>","list_archive_url":null,"date":"2022-11-15T08:14:55","name":"[v1,1/1] RISC-V: Make R_RISCV_SUB6 conforms to riscv abi standard","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221115081455.2354987-2-zengxiao@eswincomputing.com/mbox/"},{"id":20422,"url":"https://patchwork.plctlab.org/api/1.2/patches/20422/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221115145717.64948-1-bwerl.dev@gmail.com/","msgid":"<20221115145717.64948-1-bwerl.dev@gmail.com>","list_archive_url":null,"date":"2022-11-15T14:57:17","name":"readelf: use fseeko64 or fseeko if possible","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221115145717.64948-1-bwerl.dev@gmail.com/mbox/"},{"id":20600,"url":"https://patchwork.plctlab.org/api/1.2/patches/20600/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y3QKUwDn748CbDIs@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-11-15T21:53:23","name":"aarch64-pe can'\''t fill 16 bytes in section .text","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y3QKUwDn748CbDIs@squeak.grove.modra.org/mbox/"},{"id":20720,"url":"https://patchwork.plctlab.org/api/1.2/patches/20720/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221116053326.1337432-1-vladimir.mezentsev@oracle.com/","msgid":"<20221116053326.1337432-1-vladimir.mezentsev@oracle.com>","list_archive_url":null,"date":"2022-11-16T05:33:26","name":"PR29788, gprofng cannot display Java'\''s generated assembly code","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221116053326.1337432-1-vladimir.mezentsev@oracle.com/mbox/"},{"id":21321,"url":"https://patchwork.plctlab.org/api/1.2/patches/21321/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221116232039.1793148-1-hjl.tools@gmail.com/","msgid":"<20221116232039.1793148-1-hjl.tools@gmail.com>","list_archive_url":null,"date":"2022-11-16T23:20:39","name":"ld: Always call elf_backend_output_arch_local_syms","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221116232039.1793148-1-hjl.tools@gmail.com/mbox/"},{"id":21322,"url":"https://patchwork.plctlab.org/api/1.2/patches/21322/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221116232132.1009459-1-indu.bhagat@oracle.com/","msgid":"<20221116232132.1009459-1-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-16T23:21:32","name":"[gas,aarch64] : fix build breakage for aarch64-pe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221116232132.1009459-1-indu.bhagat@oracle.com/mbox/"},{"id":21449,"url":"https://patchwork.plctlab.org/api/1.2/patches/21449/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221117060234.1771025-1-indu.bhagat@oracle.com/","msgid":"<20221117060234.1771025-1-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-17T06:02:34","name":"[V2,gas,aarch64] : fix build breakage for aarch64-pe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221117060234.1771025-1-indu.bhagat@oracle.com/mbox/"},{"id":21662,"url":"https://patchwork.plctlab.org/api/1.2/patches/21662/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a050b8da-b978-d443-eee0-32b5a7836bb4@suse.com/","msgid":"","list_archive_url":null,"date":"2022-11-17T13:29:02","name":"[1/2] x86: instantiate i386_{op, reg}tab[] in gas instead of in libopcodes","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a050b8da-b978-d443-eee0-32b5a7836bb4@suse.com/mbox/"},{"id":21663,"url":"https://patchwork.plctlab.org/api/1.2/patches/21663/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d9b5137b-3bc0-8496-4533-03402ac00628@suse.com/","msgid":"","list_archive_url":null,"date":"2022-11-17T13:29:36","name":"[2/2] x86: break gas dependency on libopcodes","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d9b5137b-3bc0-8496-4533-03402ac00628@suse.com/mbox/"},{"id":21682,"url":"https://patchwork.plctlab.org/api/1.2/patches/21682/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221117143419.19571-1-bwerl.dev@gmail.com/","msgid":"<20221117143419.19571-1-bwerl.dev@gmail.com>","list_archive_url":null,"date":"2022-11-17T14:34:19","name":"readelf: use fseeko64 or fseeko if possible","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221117143419.19571-1-bwerl.dev@gmail.com/mbox/"},{"id":21850,"url":"https://patchwork.plctlab.org/api/1.2/patches/21850/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221117170546.1941945-1-hjl.tools@gmail.com/","msgid":"<20221117170546.1941945-1-hjl.tools@gmail.com>","list_archive_url":null,"date":"2022-11-17T17:05:46","name":"i386: Move i386_seg_prefixes to gas","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221117170546.1941945-1-hjl.tools@gmail.com/mbox/"},{"id":21858,"url":"https://patchwork.plctlab.org/api/1.2/patches/21858/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/CAPOVtOvi0D-u7MKAuO97-q241JZFojD8xppn3GdF2kH57iT+TA@mail.gmail.com/","msgid":"","list_archive_url":null,"date":"2022-11-17T17:44:00","name":"binutils: partially revert 17c6c3b99156fe82c1e637e1a5fd9f163ac788c8","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/CAPOVtOvi0D-u7MKAuO97-q241JZFojD8xppn3GdF2kH57iT+TA@mail.gmail.com/mbox/"},{"id":21992,"url":"https://patchwork.plctlab.org/api/1.2/patches/21992/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221118003212.3628771-1-christoph.muellner@vrull.eu/","msgid":"<20221118003212.3628771-1-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2022-11-18T00:32:12","name":"riscv: Add AIA extension support (Smaia, Ssaia)","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221118003212.3628771-1-christoph.muellner@vrull.eu/mbox/"},{"id":22004,"url":"https://patchwork.plctlab.org/api/1.2/patches/22004/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y3bZt50nhFXkf2WU@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-11-18T01:02:47","name":"go32 sanity check","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y3bZt50nhFXkf2WU@squeak.grove.modra.org/mbox/"},{"id":22005,"url":"https://patchwork.plctlab.org/api/1.2/patches/22005/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y3bZ0x42eeZFSqXt@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-11-18T01:03:15","name":"PR29799 heap buffer overflow in display_gdb_index dwarf.c:10548","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y3bZ0x42eeZFSqXt@squeak.grove.modra.org/mbox/"},{"id":22050,"url":"https://patchwork.plctlab.org/api/1.2/patches/22050/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4c45925619ab51261ca87d309883c9aa7cd05240.1668736896.git.research_trasio@irq.a4lg.com/","msgid":"<4c45925619ab51261ca87d309883c9aa7cd05240.1668736896.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-18T02:02:21","name":"RISC-V: Add INSN_DREF to memory read/write instructions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4c45925619ab51261ca87d309883c9aa7cd05240.1668736896.git.research_trasio@irq.a4lg.com/mbox/"},{"id":22053,"url":"https://patchwork.plctlab.org/api/1.2/patches/22053/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/13809b68ae60e912f3cb8e9bedd8eedf3899b547.1668737241.git.research_trasio@irq.a4lg.com/","msgid":"<13809b68ae60e912f3cb8e9bedd8eedf3899b547.1668737241.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-18T02:07:48","name":"[v4,1/8] RISC-V: Add a space at the end of pinfo","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/13809b68ae60e912f3cb8e9bedd8eedf3899b547.1668737241.git.research_trasio@irq.a4lg.com/mbox/"},{"id":22051,"url":"https://patchwork.plctlab.org/api/1.2/patches/22051/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9abf4696a17c5407a75d87b3c200fb9958ff227e.1668737241.git.research_trasio@irq.a4lg.com/","msgid":"<9abf4696a17c5407a75d87b3c200fb9958ff227e.1668737241.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-18T02:07:49","name":"[v4,2/8] RISC-V: Fix obvious misalignments ('\''Zbb'\''/'\''Zba'\'')","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9abf4696a17c5407a75d87b3c200fb9958ff227e.1668737241.git.research_trasio@irq.a4lg.com/mbox/"},{"id":22052,"url":"https://patchwork.plctlab.org/api/1.2/patches/22052/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/80185b54704af681ba81c6f84b6ce099cc3b5970.1668737241.git.research_trasio@irq.a4lg.com/","msgid":"<80185b54704af681ba81c6f84b6ce099cc3b5970.1668737241.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-18T02:07:50","name":"[v4,3/8] RISC-V: Remove spaces in opcode entries","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/80185b54704af681ba81c6f84b6ce099cc3b5970.1668737241.git.research_trasio@irq.a4lg.com/mbox/"},{"id":22055,"url":"https://patchwork.plctlab.org/api/1.2/patches/22055/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5d675a4132e2f6160d3294563e16f5093b5b1e20.1668737241.git.research_trasio@irq.a4lg.com/","msgid":"<5d675a4132e2f6160d3294563e16f5093b5b1e20.1668737241.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-18T02:07:51","name":"[v4,4/8] RISC-V: Remove unused instruction macros","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5d675a4132e2f6160d3294563e16f5093b5b1e20.1668737241.git.research_trasio@irq.a4lg.com/mbox/"},{"id":22056,"url":"https://patchwork.plctlab.org/api/1.2/patches/22056/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/27a4301cbae3d6788c878924f55aa9a6ae910669.1668737241.git.research_trasio@irq.a4lg.com/","msgid":"<27a4301cbae3d6788c878924f55aa9a6ae910669.1668737241.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-18T02:07:52","name":"[v4,5/8] RISC-V: Complete tidying up with SCALL and SBREAK","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/27a4301cbae3d6788c878924f55aa9a6ae910669.1668737241.git.research_trasio@irq.a4lg.com/mbox/"},{"id":22058,"url":"https://patchwork.plctlab.org/api/1.2/patches/22058/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7f0ea4bf1af541504b72791b5217253b2450071c.1668737241.git.research_trasio@irq.a4lg.com/","msgid":"<7f0ea4bf1af541504b72791b5217253b2450071c.1668737241.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-18T02:07:53","name":"[v4,6/8] RISC-V: Tidying up with fmv.w.x and fmv.x.w","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7f0ea4bf1af541504b72791b5217253b2450071c.1668737241.git.research_trasio@irq.a4lg.com/mbox/"},{"id":22057,"url":"https://patchwork.plctlab.org/api/1.2/patches/22057/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e5d45f2c8d1bb5b2d9adbfa117a3fc7d32afd6c9.1668737241.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-11-18T02:07:54","name":"[v4,7/8] RISC-V: Make alias instructions aliases","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e5d45f2c8d1bb5b2d9adbfa117a3fc7d32afd6c9.1668737241.git.research_trasio@irq.a4lg.com/mbox/"},{"id":22054,"url":"https://patchwork.plctlab.org/api/1.2/patches/22054/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3c1e28e61eb0275d0fd02a7d9ff956cc4f589104.1668737241.git.research_trasio@irq.a4lg.com/","msgid":"<3c1e28e61eb0275d0fd02a7d9ff956cc4f589104.1668737241.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-18T02:07:55","name":"[v4,8/8] RISC-V: Use defined mask and match values","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3c1e28e61eb0275d0fd02a7d9ff956cc4f589104.1668737241.git.research_trasio@irq.a4lg.com/mbox/"},{"id":22215,"url":"https://patchwork.plctlab.org/api/1.2/patches/22215/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/028280ab-56ad-2380-6bdd-3c944695ec5f@suse.com/","msgid":"<028280ab-56ad-2380-6bdd-3c944695ec5f@suse.com>","list_archive_url":null,"date":"2022-11-18T09:12:10","name":"[v2,1/4] x86: instantiate i386_{op, reg}tab[] in gas instead of in libopcodes","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/028280ab-56ad-2380-6bdd-3c944695ec5f@suse.com/mbox/"},{"id":22216,"url":"https://patchwork.plctlab.org/api/1.2/patches/22216/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b9a2ae11-6e9c-e9a8-88f6-17c686f0b844@suse.com/","msgid":"","list_archive_url":null,"date":"2022-11-18T09:13:01","name":"[v2,2/4] x86: remove i386-opc.c","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b9a2ae11-6e9c-e9a8-88f6-17c686f0b844@suse.com/mbox/"},{"id":22217,"url":"https://patchwork.plctlab.org/api/1.2/patches/22217/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fad783e7-e00a-c3c1-cb6d-89b70816a737@suse.com/","msgid":"","list_archive_url":null,"date":"2022-11-18T09:13:24","name":"[v2,3/4] x86: break gas dependency on libopcodes","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fad783e7-e00a-c3c1-cb6d-89b70816a737@suse.com/mbox/"},{"id":22218,"url":"https://patchwork.plctlab.org/api/1.2/patches/22218/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e3d67085-1385-d576-8656-30454f9e4474@suse.com/","msgid":"","list_archive_url":null,"date":"2022-11-18T09:14:05","name":"[v2,4/4] x86: drop sentinel from i386_optab[]","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e3d67085-1385-d576-8656-30454f9e4474@suse.com/mbox/"},{"id":23223,"url":"https://patchwork.plctlab.org/api/1.2/patches/23223/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2e469b6dd7d8b93ffd3cac333dd58d172a8f28d6.1668841829.git.research_trasio@irq.a4lg.com/","msgid":"<2e469b6dd7d8b93ffd3cac333dd58d172a8f28d6.1668841829.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-19T07:10:33","name":"[1/2] RISC-V: Make .insn tests stricter","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2e469b6dd7d8b93ffd3cac333dd58d172a8f28d6.1668841829.git.research_trasio@irq.a4lg.com/mbox/"},{"id":23224,"url":"https://patchwork.plctlab.org/api/1.2/patches/23224/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ed49fad6bc6aa4f59d619fd6b445582331594e08.1668841829.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-11-19T07:10:34","name":"[2/2] RISC-V: Better support for long instructions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ed49fad6bc6aa4f59d619fd6b445582331594e08.1668841829.git.research_trasio@irq.a4lg.com/mbox/"},{"id":23362,"url":"https://patchwork.plctlab.org/api/1.2/patches/23362/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7487608537fcd71f322e56d40bfb2cc605cee89a.1668906514.git.research_trasio@irq.a4lg.com/","msgid":"<7487608537fcd71f322e56d40bfb2cc605cee89a.1668906514.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-20T01:08:40","name":"[1/3] RISC-V: Use faster hash table on disassembling","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7487608537fcd71f322e56d40bfb2cc605cee89a.1668906514.git.research_trasio@irq.a4lg.com/mbox/"},{"id":23361,"url":"https://patchwork.plctlab.org/api/1.2/patches/23361/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e984efaf6c2d42891fa466338d999bf8b292dd7d.1668906514.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-11-20T01:08:41","name":"[2/3] RISC-V: Fallback on faster hash table","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e984efaf6c2d42891fa466338d999bf8b292dd7d.1668906514.git.research_trasio@irq.a4lg.com/mbox/"},{"id":23366,"url":"https://patchwork.plctlab.org/api/1.2/patches/23366/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/844db363911065a3b5f0c5e4601f89ee1d7360c5.1668906514.git.research_trasio@irq.a4lg.com/","msgid":"<844db363911065a3b5f0c5e4601f89ee1d7360c5.1668906514.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-20T01:08:42","name":"[3/3] RISC-V: Cache instruction support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/844db363911065a3b5f0c5e4601f89ee1d7360c5.1668906514.git.research_trasio@irq.a4lg.com/mbox/"},{"id":23363,"url":"https://patchwork.plctlab.org/api/1.2/patches/23363/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/88793c204c9270376959c6276fb1b63275bef3c8.1668906599.git.research_trasio@irq.a4lg.com/","msgid":"<88793c204c9270376959c6276fb1b63275bef3c8.1668906599.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-20T01:10:07","name":"[1/3] RISC-V: Easy optimization on riscv_search_mapping_symbol","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/88793c204c9270376959c6276fb1b63275bef3c8.1668906599.git.research_trasio@irq.a4lg.com/mbox/"},{"id":23365,"url":"https://patchwork.plctlab.org/api/1.2/patches/23365/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/55a36e28e1cb3983c637b3019d48717278574591.1668906599.git.research_trasio@irq.a4lg.com/","msgid":"<55a36e28e1cb3983c637b3019d48717278574591.1668906599.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-20T01:10:08","name":"[2/3] RISC-V: Per-section private data initialization","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/55a36e28e1cb3983c637b3019d48717278574591.1668906599.git.research_trasio@irq.a4lg.com/mbox/"},{"id":23364,"url":"https://patchwork.plctlab.org/api/1.2/patches/23364/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d41edfbaf150abb20fd78e8518ca5a9e7e5eb74f.1668906599.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-11-20T01:10:09","name":"[3/3] RISC-V: Optimized search on mapping symbols","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d41edfbaf150abb20fd78e8518ca5a9e7e5eb74f.1668906599.git.research_trasio@irq.a4lg.com/mbox/"},{"id":23372,"url":"https://patchwork.plctlab.org/api/1.2/patches/23372/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/94304c8d9174ae7e9cf52abc3af6ccf5e3e0ecd9.1668910970.git.research_trasio@irq.a4lg.com/","msgid":"<94304c8d9174ae7e9cf52abc3af6ccf5e3e0ecd9.1668910970.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-20T02:23:27","name":"[v3,1/3] RISC-V: Make \"priv-spec\" overridable","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/94304c8d9174ae7e9cf52abc3af6ccf5e3e0ecd9.1668910970.git.research_trasio@irq.a4lg.com/mbox/"},{"id":23371,"url":"https://patchwork.plctlab.org/api/1.2/patches/23371/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9d6008e38402c4e60ada6f3d3db14b92815177d8.1668910970.git.research_trasio@irq.a4lg.com/","msgid":"<9d6008e38402c4e60ada6f3d3db14b92815177d8.1668910970.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-20T02:23:28","name":"[v3,2/3] RISC-V: Add \"arch\" disassembler option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9d6008e38402c4e60ada6f3d3db14b92815177d8.1668910970.git.research_trasio@irq.a4lg.com/mbox/"},{"id":23370,"url":"https://patchwork.plctlab.org/api/1.2/patches/23370/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/70a4ac1ba8c12101de56c24d3a47939a2f5ee542.1668910970.git.research_trasio@irq.a4lg.com/","msgid":"<70a4ac1ba8c12101de56c24d3a47939a2f5ee542.1668910970.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-20T02:23:29","name":"[v3,3/3] gdb/testsuite: RISC-V disassembler option tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/70a4ac1ba8c12101de56c24d3a47939a2f5ee542.1668910970.git.research_trasio@irq.a4lg.com/mbox/"},{"id":23667,"url":"https://patchwork.plctlab.org/api/1.2/patches/23667/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221121110926.124434-1-aleksandar.rikalo@syrmia.com/","msgid":"<20221121110926.124434-1-aleksandar.rikalo@syrmia.com>","list_archive_url":null,"date":"2022-11-21T11:09:26","name":"[v3] Add support for nanoMIPS architecture","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221121110926.124434-1-aleksandar.rikalo@syrmia.com/mbox/"},{"id":23697,"url":"https://patchwork.plctlab.org/api/1.2/patches/23697/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221121120037.19325-1-zengxiao@eswincomputing.com/","msgid":"<20221121120037.19325-1-zengxiao@eswincomputing.com>","list_archive_url":null,"date":"2022-11-21T12:00:37","name":"[v2] RISC-V: Make R_RISCV_SUB6 conforms to riscv ABI standard","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221121120037.19325-1-zengxiao@eswincomputing.com/mbox/"},{"id":23957,"url":"https://patchwork.plctlab.org/api/1.2/patches/23957/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221121171544.3291-1-shahab@synopsys.com/","msgid":"<20221121171544.3291-1-shahab@synopsys.com>","list_archive_url":null,"date":"2022-11-21T17:15:44","name":"opcodes: Correct address for ARC'\''s \"isa_config\" aux reg","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221121171544.3291-1-shahab@synopsys.com/mbox/"},{"id":24026,"url":"https://patchwork.plctlab.org/api/1.2/patches/24026/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y3vyL3UATztRRM8v@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-11-21T21:48:31","name":"PR29807, SIGSEGV when linking fuzzed PE object","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y3vyL3UATztRRM8v@squeak.grove.modra.org/mbox/"},{"id":24269,"url":"https://patchwork.plctlab.org/api/1.2/patches/24269/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221122110927.2328582-1-christoph.muellner@vrull.eu/","msgid":"<20221122110927.2328582-1-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2022-11-22T11:09:27","name":"[v3] riscv: Add AIA extension support (Smaia, Ssaia)","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221122110927.2328582-1-christoph.muellner@vrull.eu/mbox/"},{"id":24318,"url":"https://patchwork.plctlab.org/api/1.2/patches/24318/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221122120339.23186-1-shahab@synopsys.com/","msgid":"<20221122120339.23186-1-shahab@synopsys.com>","list_archive_url":null,"date":"2022-11-22T12:03:39","name":"[PUSHED] opcodes: Correct address for ARC'\''s \"isa_config\" aux reg","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221122120339.23186-1-shahab@synopsys.com/mbox/"},{"id":24501,"url":"https://patchwork.plctlab.org/api/1.2/patches/24501/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221122181927.251937-1-hjl.tools@gmail.com/","msgid":"<20221122181927.251937-1-hjl.tools@gmail.com>","list_archive_url":null,"date":"2022-11-22T18:19:27","name":"x86: Remove libopcodes dependency","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221122181927.251937-1-hjl.tools@gmail.com/mbox/"}],"public":true,"mbox":"https://patchwork.plctlab.org/bundle/patchwork-bot/binutils-gdb_2022-11/mbox/"}]' + bundle_name_list='binutils-gdb_2022-10 binutils-gdb_2022-09 binutils-gdb_2022-11' + [[ binutils-gdb_2022-10 binutils-gdb_2022-09 binutils-gdb_2022-11 =~ 2022-11 ]] ++ jq -rc --arg bundle_name binutils-gdb_2022-11 '.[] | select(.name==$bundle_name) | (.id|tostring)' ++ echo '[{"id":6,"url":"https://patchwork.plctlab.org/api/1.2/bundles/6/","web_url":"https://patchwork.plctlab.org/bundle/patchwork-bot/binutils-gdb_2022-10/","project":{"id":2,"url":"https://patchwork.plctlab.org/api/1.2/projects/2/","name":"binutils-gdb","link_name":"binutils-gdb","list_id":"binutils.sourceware.org","list_email":"binutils@sourceware.org","web_url":"https://github.com/wangliu-iscas/Patchwork-Bundles/blob/main/binutils-gdb.md","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"name":"binutils-gdb_2022-10","owner":{"id":3,"url":"https://patchwork.plctlab.org/api/1.2/users/3/","username":"patchwork-bot","first_name":"","last_name":"","email":"ouuuleilei@gmail.com"},"patches":[{"id":1592,"url":"https://patchwork.plctlab.org/api/1.2/patches/1592/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/385d01fd-7e57-1f3f-1bae-30aa0c313d63@suse.com/","msgid":"<385d01fd-7e57-1f3f-1bae-30aa0c313d63@suse.com>","list_archive_url":null,"date":"2022-09-30T11:59:45","name":"[3/4] RISC-V/gas: don'\''t open-code insn_length()","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/385d01fd-7e57-1f3f-1bae-30aa0c313d63@suse.com/mbox/"},{"id":1594,"url":"https://patchwork.plctlab.org/api/1.2/patches/1594/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f5757acf-7b90-a0e3-5eea-3b97cc226930@suse.com/","msgid":"","list_archive_url":null,"date":"2022-09-30T12:00:12","name":"[4/4] RISC-V/gas: allow generating up to 176-bit instructions with .insn","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f5757acf-7b90-a0e3-5eea-3b97cc226930@suse.com/mbox/"},{"id":1596,"url":"https://patchwork.plctlab.org/api/1.2/patches/1596/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930140503.38233-1-chigot@adacore.com/","msgid":"<20220930140503.38233-1-chigot@adacore.com>","list_archive_url":null,"date":"2022-09-30T14:05:03","name":"ld/testsuite: consistently add board_ldflags when linking with GCC","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930140503.38233-1-chigot@adacore.com/mbox/"},{"id":1619,"url":"https://patchwork.plctlab.org/api/1.2/patches/1619/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221001014451.532772-1-maskray@google.com/","msgid":"<20221001014451.532772-1-maskray@google.com>","list_archive_url":null,"date":"2022-10-01T01:44:51","name":"gold, dwp: support zstd compressed input debug sections [PR 29641]","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221001014451.532772-1-maskray@google.com/mbox/"},{"id":1620,"url":"https://patchwork.plctlab.org/api/1.2/patches/1620/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221001023846.590825-1-maskray@google.com/","msgid":"<20221001023846.590825-1-maskray@google.com>","list_archive_url":null,"date":"2022-10-01T02:38:46","name":"gold: add --compress-debug-sections=zstd [PR 29641]","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221001023846.590825-1-maskray@google.com/mbox/"},{"id":1623,"url":"https://patchwork.plctlab.org/api/1.2/patches/1623/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b4477c7f666bdeb7f8e998633c7b0cb62310b9ef.1664599545.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-01T04:45:52","name":"[RFC,1/1] RISC-V: Implement common register pair framework","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b4477c7f666bdeb7f8e998633c7b0cb62310b9ef.1664599545.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1625,"url":"https://patchwork.plctlab.org/api/1.2/patches/1625/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/53a265a1f14d17a6f7b106082f610994c5d546e0.1664602025.git.research_trasio@irq.a4lg.com/","msgid":"<53a265a1f14d17a6f7b106082f610994c5d546e0.1664602025.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-01T05:27:31","name":"[RFC,1/1] RISC-V: Implement extension variants","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/53a265a1f14d17a6f7b106082f610994c5d546e0.1664602025.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1626,"url":"https://patchwork.plctlab.org/api/1.2/patches/1626/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8db04962aba9c780f133840a8934353a58f223fe.1664602716.git.research_trasio@irq.a4lg.com/","msgid":"<8db04962aba9c780f133840a8934353a58f223fe.1664602716.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-01T05:39:26","name":"[1/1] RISC-V: Move supervisor instructions after all unprivileged ones","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8db04962aba9c780f133840a8934353a58f223fe.1664602716.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1627,"url":"https://patchwork.plctlab.org/api/1.2/patches/1627/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221001062057.681440-1-maskray@google.com/","msgid":"<20221001062057.681440-1-maskray@google.com>","list_archive_url":null,"date":"2022-10-01T06:20:57","name":"readelf: support zstd compressed debug sections [PR 29640]","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221001062057.681440-1-maskray@google.com/mbox/"},{"id":1631,"url":"https://patchwork.plctlab.org/api/1.2/patches/1631/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/619f112539c0bdecd58e25664f1250a3479a37f5.1664707612.git.aburgess@redhat.com/","msgid":"<619f112539c0bdecd58e25664f1250a3479a37f5.1664707612.git.aburgess@redhat.com>","list_archive_url":null,"date":"2022-10-02T10:47:52","name":"[PATCHv2,2/2] opcodes/arm: add disassembler styling for arm","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/619f112539c0bdecd58e25664f1250a3479a37f5.1664707612.git.aburgess@redhat.com/mbox/"},{"id":1635,"url":"https://patchwork.plctlab.org/api/1.2/patches/1635/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221002185433.gl7dvytfh5wthifx@lug-owl.de/","msgid":"<20221002185433.gl7dvytfh5wthifx@lug-owl.de>","list_archive_url":null,"date":"2022-10-02T18:54:33","name":"diagnostics.h: GCC 13 got -Wself-move, breaks GDB build","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221002185433.gl7dvytfh5wthifx@lug-owl.de/mbox/"},{"id":1637,"url":"https://patchwork.plctlab.org/api/1.2/patches/1637/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003014313.28766-1-mark@harmstone.com/","msgid":"<20221003014313.28766-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-03T01:43:12","name":"[1/2] ld: Add --pdb option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003014313.28766-1-mark@harmstone.com/mbox/"},{"id":1638,"url":"https://patchwork.plctlab.org/api/1.2/patches/1638/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003014313.28766-2-mark@harmstone.com/","msgid":"<20221003014313.28766-2-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-03T01:43:13","name":"[2/2] ld: Add minimal pdb generation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003014313.28766-2-mark@harmstone.com/mbox/"},{"id":1640,"url":"https://patchwork.plctlab.org/api/1.2/patches/1640/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/597ed978-d121-220c-b56b-2ffb94bd091c@suse.cz/","msgid":"<597ed978-d121-220c-b56b-2ffb94bd091c@suse.cz>","list_archive_url":null,"date":"2022-10-03T07:50:38","name":"[1/2] refactor usage of compressed_debug_section_type","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/597ed978-d121-220c-b56b-2ffb94bd091c@suse.cz/mbox/"},{"id":1641,"url":"https://patchwork.plctlab.org/api/1.2/patches/1641/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b8acdd83-f33a-74b8-e21a-23719a0b1a60@suse.cz/","msgid":"","list_archive_url":null,"date":"2022-10-03T07:50:44","name":"[2/2] add --enable-default-compressed-debug-sections-algorithm configure option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b8acdd83-f33a-74b8-e21a-23719a0b1a60@suse.cz/mbox/"},{"id":1642,"url":"https://patchwork.plctlab.org/api/1.2/patches/1642/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003101328.1790113-1-aburgess@redhat.com/","msgid":"<20221003101328.1790113-1-aburgess@redhat.com>","list_archive_url":null,"date":"2022-10-03T10:13:28","name":"opcodes/riscv: style csr names as registers","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003101328.1790113-1-aburgess@redhat.com/mbox/"},{"id":1643,"url":"https://patchwork.plctlab.org/api/1.2/patches/1643/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7ba14fc4472ce97d4f7a4433cad8a571e89f82f4.1664793840.git.research_trasio@irq.a4lg.com/","msgid":"<7ba14fc4472ce97d4f7a4433cad8a571e89f82f4.1664793840.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-03T10:43:59","name":"[v3,1/6] RISC-V: Fix immediates to have \"immediate\" style","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7ba14fc4472ce97d4f7a4433cad8a571e89f82f4.1664793840.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1644,"url":"https://patchwork.plctlab.org/api/1.2/patches/1644/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a498bec37c1fd1dcda57cbf95e5f8cfba09b31d3.1664793840.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-03T10:44:00","name":"[v3,2/6] RISC-V: Fix printf argument types corresponding %x","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a498bec37c1fd1dcda57cbf95e5f8cfba09b31d3.1664793840.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1647,"url":"https://patchwork.plctlab.org/api/1.2/patches/1647/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0002ea716713ace4998a33dde0b81f4f890d10bf.1664793840.git.research_trasio@irq.a4lg.com/","msgid":"<0002ea716713ace4998a33dde0b81f4f890d10bf.1664793840.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-03T10:44:01","name":"[v3,3/6] RISC-V: Optimize riscv_disassemble_data printf","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0002ea716713ace4998a33dde0b81f4f890d10bf.1664793840.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1646,"url":"https://patchwork.plctlab.org/api/1.2/patches/1646/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c65fc3e9aa58965d6768a28c9fd7467fea9897a5.1664793840.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-03T10:44:02","name":"[v3,4/6] RISC-V: Print comma and tabs as the \"text\" style","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c65fc3e9aa58965d6768a28c9fd7467fea9897a5.1664793840.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1648,"url":"https://patchwork.plctlab.org/api/1.2/patches/1648/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5abe1d8a7694417b990e11d8f6cd6789573872e5.1664793840.git.research_trasio@irq.a4lg.com/","msgid":"<5abe1d8a7694417b990e11d8f6cd6789573872e5.1664793840.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-03T10:44:03","name":"[v3,5/6] RISC-V: Fix T-Head immediate types on printing","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5abe1d8a7694417b990e11d8f6cd6789573872e5.1664793840.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1649,"url":"https://patchwork.plctlab.org/api/1.2/patches/1649/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0b68af932117258c908db62cf87c3a15d3cdec41.1664793840.git.research_trasio@irq.a4lg.com/","msgid":"<0b68af932117258c908db62cf87c3a15d3cdec41.1664793840.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-03T10:44:04","name":"[v3,6/6] RISC-V: Print XTheadMemPair literal as \"immediate\"","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0b68af932117258c908db62cf87c3a15d3cdec41.1664793840.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1656,"url":"https://patchwork.plctlab.org/api/1.2/patches/1656/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/87lepxcd6x.fsf@redhat.com/","msgid":"<87lepxcd6x.fsf@redhat.com>","list_archive_url":null,"date":"2022-10-03T12:19:02","name":"Commit: readelf: Do not load section data from offset 0","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/87lepxcd6x.fsf@redhat.com/mbox/"},{"id":1659,"url":"https://patchwork.plctlab.org/api/1.2/patches/1659/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e0d369d419da9c0441f415da7f54352aead8f655.1664707612.git.aburgess@redhat.com/","msgid":"","list_archive_url":null,"date":"2022-10-03T16:37:36","name":"[PATCHv2,1/2] opcodes/arm: use '\''@'\'' consistently for the comment character","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e0d369d419da9c0441f415da7f54352aead8f655.1664707612.git.aburgess@redhat.com/mbox/"},{"id":1660,"url":"https://patchwork.plctlab.org/api/1.2/patches/1660/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003165848.11142-1-palmer@rivosinc.com/","msgid":"<20221003165848.11142-1-palmer@rivosinc.com>","list_archive_url":null,"date":"2022-10-03T16:58:48","name":"gas: NEWS: Mention the T-Head extensions that were recently added","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003165848.11142-1-palmer@rivosinc.com/mbox/"},{"id":1671,"url":"https://patchwork.plctlab.org/api/1.2/patches/1671/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/YzvrMEdkXjIn5Lfz@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-04T08:13:36","name":"Support objcopy changing compression to or from zstd","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/YzvrMEdkXjIn5Lfz@squeak.grove.modra.org/mbox/"},{"id":1673,"url":"https://patchwork.plctlab.org/api/1.2/patches/1673/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0bc857d306bb7c8130e5328dbe6b9ed2fed3ef87.1664873933.git.research_trasio@irq.a4lg.com/","msgid":"<0bc857d306bb7c8130e5328dbe6b9ed2fed3ef87.1664873933.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-04T08:59:07","name":"[1/2] RISC-V: Fix buffer overflow on print_insn_riscv","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0bc857d306bb7c8130e5328dbe6b9ed2fed3ef87.1664873933.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1672,"url":"https://patchwork.plctlab.org/api/1.2/patches/1672/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/89612fe01d902007bf84a7dfb0df5f85d5c166e4.1664873933.git.research_trasio@irq.a4lg.com/","msgid":"<89612fe01d902007bf84a7dfb0df5f85d5c166e4.1664873933.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-04T08:59:08","name":"[2/2] gdb/riscv: Fix buffer overflow on riscv_insn::fetch_instruction","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/89612fe01d902007bf84a7dfb0df5f85d5c166e4.1664873933.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1676,"url":"https://patchwork.plctlab.org/api/1.2/patches/1676/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fc849c94f4adcac1c4ccc5508c7a145a2f13b2a9.1664876744.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-04T09:45:49","name":"[v2,1/2] RISC-V: Fix buffer overflow on print_insn_riscv","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fc849c94f4adcac1c4ccc5508c7a145a2f13b2a9.1664876744.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1677,"url":"https://patchwork.plctlab.org/api/1.2/patches/1677/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4eb6e59ae2e790dbbf2bc92477edd281648d8814.1664876744.git.research_trasio@irq.a4lg.com/","msgid":"<4eb6e59ae2e790dbbf2bc92477edd281648d8814.1664876744.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-04T09:45:50","name":"[v2,2/2] gdb/riscv: Partial support for instructions up to 176-bits","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4eb6e59ae2e790dbbf2bc92477edd281648d8814.1664876744.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1678,"url":"https://patchwork.plctlab.org/api/1.2/patches/1678/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ebf16f9e1f45115d0793952ccb4a94d4233303f9.1664882725.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-04T11:25:56","name":"[v3,1/2] RISC-V: Fix buffer overflow on print_insn_riscv","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ebf16f9e1f45115d0793952ccb4a94d4233303f9.1664882725.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1679,"url":"https://patchwork.plctlab.org/api/1.2/patches/1679/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/83464b09b8649525259c69c853dfa2c9575a204b.1664882725.git.research_trasio@irq.a4lg.com/","msgid":"<83464b09b8649525259c69c853dfa2c9575a204b.1664882725.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-04T11:25:57","name":"[v3,2/2] gdb/riscv: Partial support for instructions up to 176-bit","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/83464b09b8649525259c69c853dfa2c9575a204b.1664882725.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1681,"url":"https://patchwork.plctlab.org/api/1.2/patches/1681/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ffa9c1d7-e8c2-a62b-ef3e-b565c0ffbe5b@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-04T13:56:27","name":"RISC-V: Zicbo{m,p,z} adjustments to riscv_multi_subset_supports_ext()","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ffa9c1d7-e8c2-a62b-ef3e-b565c0ffbe5b@suse.com/mbox/"},{"id":1690,"url":"https://patchwork.plctlab.org/api/1.2/patches/1690/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221004161720.1963953-1-vladimir.mezentsev@oracle.com/","msgid":"<20221004161720.1963953-1-vladimir.mezentsev@oracle.com>","list_archive_url":null,"date":"2022-10-04T16:17:20","name":"gprofng: fix build with --enable-pgo-build=lto","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221004161720.1963953-1-vladimir.mezentsev@oracle.com/mbox/"},{"id":1691,"url":"https://patchwork.plctlab.org/api/1.2/patches/1691/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c0211bc9c57be6c79c6d878ce147f63b657f461d.camel@espressif.com/","msgid":"","list_archive_url":null,"date":"2022-10-04T16:22:05","name":"bfd: xtensa: fix __stop_SECTION literal drop,","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c0211bc9c57be6c79c6d878ce147f63b657f461d.camel@espressif.com/mbox/"},{"id":1702,"url":"https://patchwork.plctlab.org/api/1.2/patches/1702/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5f482299-6c60-b2b3-9abe-f4a55a5a26c5@univ-grenoble-alpes.fr/","msgid":"<5f482299-6c60-b2b3-9abe-f4a55a5a26c5@univ-grenoble-alpes.fr>","list_archive_url":null,"date":"2022-10-04T20:03:20","name":"[RFC] bfd: use bfd_vma for the 64-bit version of put[lb] and get[lb]","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5f482299-6c60-b2b3-9abe-f4a55a5a26c5@univ-grenoble-alpes.fr/mbox/"},{"id":1711,"url":"https://patchwork.plctlab.org/api/1.2/patches/1711/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Yz0Gsxdxe0TePbJT@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-05T04:23:15","name":"PR29647, objdump -S looping","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Yz0Gsxdxe0TePbJT@squeak.grove.modra.org/mbox/"},{"id":1712,"url":"https://patchwork.plctlab.org/api/1.2/patches/1712/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/02d747d2-f57b-0fb5-b893-842b6cc41f2f@suse.com/","msgid":"<02d747d2-f57b-0fb5-b893-842b6cc41f2f@suse.com>","list_archive_url":null,"date":"2022-10-05T07:20:47","name":"[v3,1/7] x86: constify parse_insn()'\''s input","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/02d747d2-f57b-0fb5-b893-842b6cc41f2f@suse.com/mbox/"},{"id":1713,"url":"https://patchwork.plctlab.org/api/1.2/patches/1713/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/925cb740-4e1b-abc4-8526-aaab6faae5e1@suse.com/","msgid":"<925cb740-4e1b-abc4-8526-aaab6faae5e1@suse.com>","list_archive_url":null,"date":"2022-10-05T07:22:19","name":"[v3,2/7] x86: introduce Pass2 insn attribute","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/925cb740-4e1b-abc4-8526-aaab6faae5e1@suse.com/mbox/"},{"id":1714,"url":"https://patchwork.plctlab.org/api/1.2/patches/1714/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e16d3e78-39ca-f715-508f-a4104b8ab9a9@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-05T07:23:51","name":"[v3,3/7] x86: re-work insn/suffix recognition","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e16d3e78-39ca-f715-508f-a4104b8ab9a9@suse.com/mbox/"},{"id":1715,"url":"https://patchwork.plctlab.org/api/1.2/patches/1715/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e4e4b80b-794c-7485-1997-685adab8fb27@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-05T07:24:20","name":"[v3,4/7] x86-64: further re-work insn/suffix recognition to also cover MOVSL","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e4e4b80b-794c-7485-1997-685adab8fb27@suse.com/mbox/"},{"id":1716,"url":"https://patchwork.plctlab.org/api/1.2/patches/1716/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/540678fc-8bff-ec68-c97c-478d2631998c@suse.com/","msgid":"<540678fc-8bff-ec68-c97c-478d2631998c@suse.com>","list_archive_url":null,"date":"2022-10-05T07:24:55","name":"[v3,5/7] ix86: don'\''t recognize/derive Q suffix in the common case","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/540678fc-8bff-ec68-c97c-478d2631998c@suse.com/mbox/"},{"id":1718,"url":"https://patchwork.plctlab.org/api/1.2/patches/1718/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e4692495-7d3d-074d-14f9-364d4a9a998c@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-05T07:25:25","name":"[v3,6/7] x86-64: allow HLE store of accumulator to absolute 32-bit address","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e4692495-7d3d-074d-14f9-364d4a9a998c@suse.com/mbox/"},{"id":1717,"url":"https://patchwork.plctlab.org/api/1.2/patches/1717/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e8014ebd-d16b-17a7-9f34-3700fc164136@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-05T07:25:57","name":"[v3,7/7] x86: move bad-use-of-TLS-reloc check","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e8014ebd-d16b-17a7-9f34-3700fc164136@suse.com/mbox/"},{"id":1719,"url":"https://patchwork.plctlab.org/api/1.2/patches/1719/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1266f001-4511-2662-dba9-14b4d0317c57@suse.com/","msgid":"<1266f001-4511-2662-dba9-14b4d0317c57@suse.com>","list_archive_url":null,"date":"2022-10-05T07:40:50","name":"x86: drop \"regmask\" static variable","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1266f001-4511-2662-dba9-14b4d0317c57@suse.com/mbox/"},{"id":1751,"url":"https://patchwork.plctlab.org/api/1.2/patches/1751/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/af45c5d57c221e43101c2aa38b14f4b4ac12d011.1665031170.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-06T04:40:15","name":"[v2,1/2] RISC-V: Fallback for instructions longer than 64b","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/af45c5d57c221e43101c2aa38b14f4b4ac12d011.1665031170.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1752,"url":"https://patchwork.plctlab.org/api/1.2/patches/1752/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c6e55781245dd3e8e9b8debd6130fc5449dfbd55.1665031170.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-06T04:40:16","name":"[v2,2/2] RISC-V: Improve \"bits undefined\" diagnostics","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c6e55781245dd3e8e9b8debd6130fc5449dfbd55.1665031170.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1776,"url":"https://patchwork.plctlab.org/api/1.2/patches/1776/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d52952119e15357c0e823f8a2398999359588b4d.1665050099.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-06T09:56:30","name":"[v3,1/2] RISC-V: Fallback for instructions longer than 64b","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d52952119e15357c0e823f8a2398999359588b4d.1665050099.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1777,"url":"https://patchwork.plctlab.org/api/1.2/patches/1777/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d907b1997f60ff7823c4a23e281ec9d8ddcbf3f1.1665050099.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-06T09:56:31","name":"[v3,2/2] RISC-V: Improve \"bits undefined\" diagnostics","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d907b1997f60ff7823c4a23e281ec9d8ddcbf3f1.1665050099.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1781,"url":"https://patchwork.plctlab.org/api/1.2/patches/1781/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221006114628.304185-1-chigot@adacore.com/","msgid":"<20221006114628.304185-1-chigot@adacore.com>","list_archive_url":null,"date":"2022-10-06T11:46:28","name":"RISC-V: fix linker message when relaxation deletes bytes","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221006114628.304185-1-chigot@adacore.com/mbox/"},{"id":1801,"url":"https://patchwork.plctlab.org/api/1.2/patches/1801/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Yz+Yhyg7UewC9/kp@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-07T03:09:59","name":"PR29653, objcopy/strip: fuzzed small input file induces large output file","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Yz+Yhyg7UewC9/kp@squeak.grove.modra.org/mbox/"},{"id":1803,"url":"https://patchwork.plctlab.org/api/1.2/patches/1803/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/PH1P110MB16505D9D39EC5B1DE22FE3D5EC5F9@PH1P110MB1650.NAMP110.PROD.OUTLOOK.COM/","msgid":"","list_archive_url":null,"date":"2022-10-07T04:10:07","name":"@CPP_FOR_BUILD@ problem since binutils-2.38","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/PH1P110MB16505D9D39EC5B1DE22FE3D5EC5F9@PH1P110MB1650.NAMP110.PROD.OUTLOOK.COM/mbox/"},{"id":1827,"url":"https://patchwork.plctlab.org/api/1.2/patches/1827/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8e13bce108ac10a0c1dd911e23ec572926f7ae44.1665203374.git.research_trasio@irq.a4lg.com/","msgid":"<8e13bce108ac10a0c1dd911e23ec572926f7ae44.1665203374.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-08T04:29:53","name":"[v2,1/1] RISC-V: Test DWARF register numbers for \"fp\"","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8e13bce108ac10a0c1dd911e23ec572926f7ae44.1665203374.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1828,"url":"https://patchwork.plctlab.org/api/1.2/patches/1828/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0883001b3572e54d3fba264429c7ade2adb66610.1665203441.git.research_trasio@irq.a4lg.com/","msgid":"<0883001b3572e54d3fba264429c7ade2adb66610.1665203441.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-08T04:31:15","name":"[1/1] RISC-V: Move standard hints before all instructions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0883001b3572e54d3fba264429c7ade2adb66610.1665203441.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1829,"url":"https://patchwork.plctlab.org/api/1.2/patches/1829/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/58e16a241d7376fcae2515c6bd5a2b41d275eeba.1665203531.git.research_trasio@irq.a4lg.com/","msgid":"<58e16a241d7376fcae2515c6bd5a2b41d275eeba.1665203531.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-08T04:32:18","name":"[RFC,1/1] RISC-V: Imply '\''Zicsr'\'' from privileged extensions with CSRs","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/58e16a241d7376fcae2515c6bd5a2b41d275eeba.1665203531.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1830,"url":"https://patchwork.plctlab.org/api/1.2/patches/1830/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/cb5076fc96e8f2097779a3abcde843dcdd660031.1665203660.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-08T04:34:23","name":"[1/5] opcodes/riscv-dis.c: Tidying with comments/clarity","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/cb5076fc96e8f2097779a3abcde843dcdd660031.1665203660.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1832,"url":"https://patchwork.plctlab.org/api/1.2/patches/1832/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1f1aa0838bf9c4f10a45fcfe3c682f7efc79d9ae.1665203660.git.research_trasio@irq.a4lg.com/","msgid":"<1f1aa0838bf9c4f10a45fcfe3c682f7efc79d9ae.1665203660.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-08T04:34:24","name":"[2/5] opcodes/riscv-dis.c: Tidying with spacing","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1f1aa0838bf9c4f10a45fcfe3c682f7efc79d9ae.1665203660.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1831,"url":"https://patchwork.plctlab.org/api/1.2/patches/1831/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/740bc5e2d2618d236519b39fedd1a1d7ae4e05da.1665203660.git.research_trasio@irq.a4lg.com/","msgid":"<740bc5e2d2618d236519b39fedd1a1d7ae4e05da.1665203660.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-08T04:34:25","name":"[3/5] opcodes/riscv-dis.c: Use bool type whenever possible","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/740bc5e2d2618d236519b39fedd1a1d7ae4e05da.1665203660.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1833,"url":"https://patchwork.plctlab.org/api/1.2/patches/1833/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6e3a9c235e317f441b4383b3daa68f2051bdc149.1665203660.git.research_trasio@irq.a4lg.com/","msgid":"<6e3a9c235e317f441b4383b3daa68f2051bdc149.1665203660.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-08T04:34:26","name":"[4/5] opcodes/riscv-dis.c: Make XLEN variable static","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6e3a9c235e317f441b4383b3daa68f2051bdc149.1665203660.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1834,"url":"https://patchwork.plctlab.org/api/1.2/patches/1834/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ad929233a62d887495122721340b2f9c80392963.1665203660.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-08T04:34:27","name":"[5/5] opcodes/riscv-dis.c: Remove last_map_state","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ad929233a62d887495122721340b2f9c80392963.1665203660.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1836,"url":"https://patchwork.plctlab.org/api/1.2/patches/1836/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d07e2b6f36ea2fd5830924a9bfeda941b774b687.1665290422.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-09T05:09:22","name":"RISC-V: Move certain arrays to riscv-opc.c","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d07e2b6f36ea2fd5830924a9bfeda941b774b687.1665290422.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1844,"url":"https://patchwork.plctlab.org/api/1.2/patches/1844/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010004623.16582-1-mark@harmstone.com/","msgid":"<20221010004623.16582-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-10T00:46:22","name":"[v2,1/2] ld: Add --pdb option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010004623.16582-1-mark@harmstone.com/mbox/"},{"id":1845,"url":"https://patchwork.plctlab.org/api/1.2/patches/1845/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010004623.16582-2-mark@harmstone.com/","msgid":"<20221010004623.16582-2-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-10T00:46:23","name":"[v2,2/2] ld: Add minimal pdb generation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010004623.16582-2-mark@harmstone.com/mbox/"},{"id":1890,"url":"https://patchwork.plctlab.org/api/1.2/patches/1890/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010200433.414320-1-vladimir.mezentsev@oracle.com/","msgid":"<20221010200433.414320-1-vladimir.mezentsev@oracle.com>","list_archive_url":null,"date":"2022-10-10T20:04:33","name":"gprofng: run tests without installation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010200433.414320-1-vladimir.mezentsev@oracle.com/mbox/"},{"id":1893,"url":"https://patchwork.plctlab.org/api/1.2/patches/1893/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010230426.719238-1-vladimir.mezentsev@oracle.com/","msgid":"<20221010230426.719238-1-vladimir.mezentsev@oracle.com>","list_archive_url":null,"date":"2022-10-10T23:04:26","name":"[2/2] gprofng: use the --libdir path to find libraries","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010230426.719238-1-vladimir.mezentsev@oracle.com/mbox/"},{"id":1894,"url":"https://patchwork.plctlab.org/api/1.2/patches/1894/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010235155.842469-1-vladimir.mezentsev@oracle.com/","msgid":"<20221010235155.842469-1-vladimir.mezentsev@oracle.com>","list_archive_url":null,"date":"2022-10-10T23:51:55","name":"[3/3] gprofng: no need to build version.texi","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010235155.842469-1-vladimir.mezentsev@oracle.com/mbox/"},{"id":1895,"url":"https://patchwork.plctlab.org/api/1.2/patches/1895/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011003702.4287-1-mark@harmstone.com/","msgid":"<20221011003702.4287-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-11T00:37:01","name":"[v3,1/2] ld: Add --pdb option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011003702.4287-1-mark@harmstone.com/mbox/"},{"id":1897,"url":"https://patchwork.plctlab.org/api/1.2/patches/1897/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011003702.4287-2-mark@harmstone.com/","msgid":"<20221011003702.4287-2-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-11T00:37:02","name":"[v3,2/2] ld: Add minimal pdb generation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011003702.4287-2-mark@harmstone.com/mbox/"},{"id":1928,"url":"https://patchwork.plctlab.org/api/1.2/patches/1928/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011175332.17156-1-mark@harmstone.com/","msgid":"<20221011175332.17156-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-11T17:53:31","name":"[v4,1/2] ld: Add --pdb option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011175332.17156-1-mark@harmstone.com/mbox/"},{"id":1929,"url":"https://patchwork.plctlab.org/api/1.2/patches/1929/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011175332.17156-2-mark@harmstone.com/","msgid":"<20221011175332.17156-2-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-11T17:53:32","name":"[v4,2/2] ld: Add minimal pdb generation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011175332.17156-2-mark@harmstone.com/mbox/"},{"id":1941,"url":"https://patchwork.plctlab.org/api/1.2/patches/1941/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221012031005.237446-1-simon.marchi@polymtl.ca/","msgid":"<20221012031005.237446-1-simon.marchi@polymtl.ca>","list_archive_url":null,"date":"2022-10-12T03:10:05","name":"[pushed] Re-apply \"Pass PKG_CONFIG_PATH down from top-level Makefile\"","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221012031005.237446-1-simon.marchi@polymtl.ca/mbox/"},{"id":1976,"url":"https://patchwork.plctlab.org/api/1.2/patches/1976/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1216a3f8-2273-8681-f528-9493a66891f0@suse.com/","msgid":"<1216a3f8-2273-8681-f528-9493a66891f0@suse.com>","list_archive_url":null,"date":"2022-10-13T08:16:49","name":"[v4,1/8] x86: constify parse_insn()'\''s input","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1216a3f8-2273-8681-f528-9493a66891f0@suse.com/mbox/"},{"id":1977,"url":"https://patchwork.plctlab.org/api/1.2/patches/1977/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/11599bbe-c779-aa9f-4d5d-c2243f0e69dc@suse.com/","msgid":"<11599bbe-c779-aa9f-4d5d-c2243f0e69dc@suse.com>","list_archive_url":null,"date":"2022-10-13T08:17:17","name":"[v4,2/8] x86: introduce Pass2 insn attribute","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/11599bbe-c779-aa9f-4d5d-c2243f0e69dc@suse.com/mbox/"},{"id":1978,"url":"https://patchwork.plctlab.org/api/1.2/patches/1978/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/357273a3-060c-23db-72da-3fc9d1be3d2a@suse.com/","msgid":"<357273a3-060c-23db-72da-3fc9d1be3d2a@suse.com>","list_archive_url":null,"date":"2022-10-13T08:18:09","name":"[v4,3/8] x86: re-work insn/suffix recognition","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/357273a3-060c-23db-72da-3fc9d1be3d2a@suse.com/mbox/"},{"id":1979,"url":"https://patchwork.plctlab.org/api/1.2/patches/1979/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0ec0587f-6a7b-45b6-8346-e5d774e73636@suse.com/","msgid":"<0ec0587f-6a7b-45b6-8346-e5d774e73636@suse.com>","list_archive_url":null,"date":"2022-10-13T08:18:39","name":"[v4,4/8] x86-64: further re-work insn/suffix recognition to also cover MOVSL","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0ec0587f-6a7b-45b6-8346-e5d774e73636@suse.com/mbox/"},{"id":1980,"url":"https://patchwork.plctlab.org/api/1.2/patches/1980/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fb617d0b-8759-3169-5a65-1178b7fef3d7@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-13T08:19:34","name":"[v4,5/8] ix86: don'\''t recognize/derive Q suffix in the common case","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fb617d0b-8759-3169-5a65-1178b7fef3d7@suse.com/mbox/"},{"id":1981,"url":"https://patchwork.plctlab.org/api/1.2/patches/1981/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1df3bd01-99c5-f56c-d937-970edd42b2b8@suse.com/","msgid":"<1df3bd01-99c5-f56c-d937-970edd42b2b8@suse.com>","list_archive_url":null,"date":"2022-10-13T08:20:14","name":"[v4,6/8] x86-64: allow HLE store of accumulator to absolute 32-bit address","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1df3bd01-99c5-f56c-d937-970edd42b2b8@suse.com/mbox/"},{"id":1982,"url":"https://patchwork.plctlab.org/api/1.2/patches/1982/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8486a218-39ec-16b2-5c6c-5037196b93cf@suse.com/","msgid":"<8486a218-39ec-16b2-5c6c-5037196b93cf@suse.com>","list_archive_url":null,"date":"2022-10-13T08:21:00","name":"[v4,7/8] x86: move bad-use-of-TLS-reloc check","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8486a218-39ec-16b2-5c6c-5037196b93cf@suse.com/mbox/"},{"id":1983,"url":"https://patchwork.plctlab.org/api/1.2/patches/1983/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7d82692d-93df-fbee-9efb-2f44e8a91df3@suse.com/","msgid":"<7d82692d-93df-fbee-9efb-2f44e8a91df3@suse.com>","list_archive_url":null,"date":"2022-10-13T08:22:00","name":"[v4,8/8] x86: drop (now) stray IsString","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7d82692d-93df-fbee-9efb-2f44e8a91df3@suse.com/mbox/"},{"id":2013,"url":"https://patchwork.plctlab.org/api/1.2/patches/2013/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8ab93d7a617ad480dd786210f46db0e5aa07d1ac.1665655719.git.research_trasio@irq.a4lg.com/","msgid":"<8ab93d7a617ad480dd786210f46db0e5aa07d1ac.1665655719.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-13T10:11:41","name":"include: Declare getopt function on old GNU libc","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8ab93d7a617ad480dd786210f46db0e5aa07d1ac.1665655719.git.research_trasio@irq.a4lg.com/mbox/"},{"id":2352,"url":"https://patchwork.plctlab.org/api/1.2/patches/2352/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221013201332.2747246-1-maskray@google.com/","msgid":"<20221013201332.2747246-1-maskray@google.com>","list_archive_url":null,"date":"2022-10-13T20:13:32","name":"ld: Add --undefined-version","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221013201332.2747246-1-maskray@google.com/mbox/"},{"id":2532,"url":"https://patchwork.plctlab.org/api/1.2/patches/2532/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014063520.1428330-2-zengxiao@eswincomputing.com/","msgid":"<20221014063520.1428330-2-zengxiao@eswincomputing.com>","list_archive_url":null,"date":"2022-10-14T06:35:20","name":"[1/1] RISC-V: Make R_RISCV_SUB6 conforms to riscv abi standard","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014063520.1428330-2-zengxiao@eswincomputing.com/mbox/"},{"id":2560,"url":"https://patchwork.plctlab.org/api/1.2/patches/2560/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/027ae69a-636b-6757-297a-eec42936401e@linaro.org/","msgid":"<027ae69a-636b-6757-297a-eec42936401e@linaro.org>","list_archive_url":null,"date":"2022-10-14T07:58:22","name":"[v3] aarch64-pe support for LD, GAS and BFD","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/027ae69a-636b-6757-297a-eec42936401e@linaro.org/mbox/"},{"id":2602,"url":"https://patchwork.plctlab.org/api/1.2/patches/2602/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-2-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-2-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:39","name":"[01/10] Support Intel AVX-IFMA","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-2-haochen.jiang@intel.com/mbox/"},{"id":2608,"url":"https://patchwork.plctlab.org/api/1.2/patches/2608/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-3-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-3-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:40","name":"[02/10] Support Intel AVX-VNNI-INT8","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-3-haochen.jiang@intel.com/mbox/"},{"id":2611,"url":"https://patchwork.plctlab.org/api/1.2/patches/2611/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-4-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-4-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:41","name":"[03/10] Support Intel AVX-NE-CONVERT","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-4-haochen.jiang@intel.com/mbox/"},{"id":2610,"url":"https://patchwork.plctlab.org/api/1.2/patches/2610/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-5-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-5-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:42","name":"[04/10] Support Intel CMPccXADD","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-5-haochen.jiang@intel.com/mbox/"},{"id":2601,"url":"https://patchwork.plctlab.org/api/1.2/patches/2601/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-6-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-6-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:43","name":"[05/10] Add handler for more i386_cpu_flags","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-6-haochen.jiang@intel.com/mbox/"},{"id":2606,"url":"https://patchwork.plctlab.org/api/1.2/patches/2606/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-7-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-7-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:44","name":"[06/10] Support Intel RAO-INT","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-7-haochen.jiang@intel.com/mbox/"},{"id":2609,"url":"https://patchwork.plctlab.org/api/1.2/patches/2609/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-8-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-8-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:45","name":"[07/10] Support Intel WRMSRNS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-8-haochen.jiang@intel.com/mbox/"},{"id":2605,"url":"https://patchwork.plctlab.org/api/1.2/patches/2605/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-9-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-9-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:46","name":"[08/10] Support Intel MSRLIST","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-9-haochen.jiang@intel.com/mbox/"},{"id":2607,"url":"https://patchwork.plctlab.org/api/1.2/patches/2607/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-10-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-10-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:47","name":"[09/10] Support Intel AMX-FP16","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-10-haochen.jiang@intel.com/mbox/"},{"id":2604,"url":"https://patchwork.plctlab.org/api/1.2/patches/2604/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-11-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-11-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:48","name":"[10/10] Support Intel PREFETCHI","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-11-haochen.jiang@intel.com/mbox/"},{"id":2643,"url":"https://patchwork.plctlab.org/api/1.2/patches/2643/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7bac66be-535e-9051-d674-f2f5ba180e17@suse.com/","msgid":"<7bac66be-535e-9051-d674-f2f5ba180e17@suse.com>","list_archive_url":null,"date":"2022-10-14T10:22:34","name":"x86: fold AVX512-VNNI disassembler entries with AVX-VNNI ones","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7bac66be-535e-9051-d674-f2f5ba180e17@suse.com/mbox/"},{"id":2654,"url":"https://patchwork.plctlab.org/api/1.2/patches/2654/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0lIo5+ncY/MqBEq@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-14T11:31:47","name":"PR29677, Field `the_bfd` of `asymbol` is uninitialised","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0lIo5+ncY/MqBEq@squeak.grove.modra.org/mbox/"},{"id":2656,"url":"https://patchwork.plctlab.org/api/1.2/patches/2656/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0lJksn49ZpABY89@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-14T11:35:46","name":"e200 LSP support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0lJksn49ZpABY89@squeak.grove.modra.org/mbox/"},{"id":2657,"url":"https://patchwork.plctlab.org/api/1.2/patches/2657/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0lJxxYoeD5iDYAD@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-14T11:36:39","name":"PowerPC SPE disassembly and tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0lJxxYoeD5iDYAD@squeak.grove.modra.org/mbox/"},{"id":2695,"url":"https://patchwork.plctlab.org/api/1.2/patches/2695/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/DM6PR12MB4219611F6CC2A0702884A602E7249@DM6PR12MB4219.namprd12.prod.outlook.com/","msgid":"","list_archive_url":null,"date":"2022-10-14T13:29:40","name":"Binutils: Adding new testcase for addr2line.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/DM6PR12MB4219611F6CC2A0702884A602E7249@DM6PR12MB4219.namprd12.prod.outlook.com/mbox/"},{"id":2700,"url":"https://patchwork.plctlab.org/api/1.2/patches/2700/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9fd2c88d-98b2-99a4-419f-c7235b2cf960@suse.com/","msgid":"<9fd2c88d-98b2-99a4-419f-c7235b2cf960@suse.com>","list_archive_url":null,"date":"2022-10-14T14:11:35","name":"x86: properly decode EVEX.W for AVX512_4{FMAPS,VNNIW} insns","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9fd2c88d-98b2-99a4-419f-c7235b2cf960@suse.com/mbox/"},{"id":2981,"url":"https://patchwork.plctlab.org/api/1.2/patches/2981/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0uLzalqjm4C87GN@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-16T04:42:53","name":"PowerPC se_rfmci and VLE, SPE2 and LSP insns with -many","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0uLzalqjm4C87GN@squeak.grove.modra.org/mbox/"},{"id":3152,"url":"https://patchwork.plctlab.org/api/1.2/patches/3152/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221016232419.1135-1-mark@harmstone.com/","msgid":"<20221016232419.1135-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-16T23:24:18","name":"[v5,1/2] ld: Add --pdb option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221016232419.1135-1-mark@harmstone.com/mbox/"},{"id":3151,"url":"https://patchwork.plctlab.org/api/1.2/patches/3151/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221016232419.1135-2-mark@harmstone.com/","msgid":"<20221016232419.1135-2-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-16T23:24:19","name":"[v5,2/2] ld: Add minimal pdb generation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221016232419.1135-2-mark@harmstone.com/mbox/"},{"id":3258,"url":"https://patchwork.plctlab.org/api/1.2/patches/3258/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/19c08747-fa5b-1e67-3dd2-c891a2c0c1fa@suse.com/","msgid":"<19c08747-fa5b-1e67-3dd2-c891a2c0c1fa@suse.com>","list_archive_url":null,"date":"2022-10-17T07:44:51","name":"x86: correct CPU_AMX_{BF16,INT8}_FLAGS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/19c08747-fa5b-1e67-3dd2-c891a2c0c1fa@suse.com/mbox/"},{"id":3272,"url":"https://patchwork.plctlab.org/api/1.2/patches/3272/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/85dd526c-d3a7-72dc-5444-ed5573eebec1@suse.com/","msgid":"<85dd526c-d3a7-72dc-5444-ed5573eebec1@suse.com>","list_archive_url":null,"date":"2022-10-17T08:30:12","name":"x86: generalize gas documentation for disabling of ISA extensions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/85dd526c-d3a7-72dc-5444-ed5573eebec1@suse.com/mbox/"},{"id":3759,"url":"https://patchwork.plctlab.org/api/1.2/patches/3759/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-2-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-2-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:15:58","name":"[V2,01/15] sframe.h: Add SFrame format definition","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-2-indu.bhagat@oracle.com/mbox/"},{"id":3762,"url":"https://patchwork.plctlab.org/api/1.2/patches/3762/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-3-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-3-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:15:59","name":"[V2,02/15] gas: add new command line option --gsframe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-3-indu.bhagat@oracle.com/mbox/"},{"id":3761,"url":"https://patchwork.plctlab.org/api/1.2/patches/3761/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-4-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-4-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:00","name":"[V2,03/15] gas: generate .sframe from CFI directives","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-4-indu.bhagat@oracle.com/mbox/"},{"id":3760,"url":"https://patchwork.plctlab.org/api/1.2/patches/3760/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-5-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-5-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:01","name":"[V2,04/15] gas: testsuite: add new tests for SFrame unwind info","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-5-indu.bhagat@oracle.com/mbox/"},{"id":3764,"url":"https://patchwork.plctlab.org/api/1.2/patches/3764/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-6-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-6-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:02","name":"[V2,05/15] libsframe: add the SFrame library","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-6-indu.bhagat@oracle.com/mbox/"},{"id":3766,"url":"https://patchwork.plctlab.org/api/1.2/patches/3766/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-7-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-7-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:03","name":"[V2,06/15] bfd: linker: merge .sframe sections","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-7-indu.bhagat@oracle.com/mbox/"},{"id":3763,"url":"https://patchwork.plctlab.org/api/1.2/patches/3763/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-8-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-8-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:04","name":"[V2,07/15] readelf/objdump: support for SFrame section","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-8-indu.bhagat@oracle.com/mbox/"},{"id":3765,"url":"https://patchwork.plctlab.org/api/1.2/patches/3765/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-9-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-9-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:05","name":"[V2,08/15] unwinder: generate backtrace using SFrame format","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-9-indu.bhagat@oracle.com/mbox/"},{"id":3770,"url":"https://patchwork.plctlab.org/api/1.2/patches/3770/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-10-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-10-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:06","name":"[V2,09/15] unwinder: Add SFrame unwinder tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-10-indu.bhagat@oracle.com/mbox/"},{"id":3769,"url":"https://patchwork.plctlab.org/api/1.2/patches/3769/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-11-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-11-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:07","name":"[V2,10/15] gdb: sim: buildsystem changes to accommodate libsframe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-11-indu.bhagat@oracle.com/mbox/"},{"id":3771,"url":"https://patchwork.plctlab.org/api/1.2/patches/3771/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-12-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-12-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:08","name":"[V2,11/15] libctf: add libsframe to LDFLAGS and LIBS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-12-indu.bhagat@oracle.com/mbox/"},{"id":3768,"url":"https://patchwork.plctlab.org/api/1.2/patches/3768/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-13-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-13-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:09","name":"[V2,12/15] src-release.sh: Add libsframe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-13-indu.bhagat@oracle.com/mbox/"},{"id":3767,"url":"https://patchwork.plctlab.org/api/1.2/patches/3767/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-14-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-14-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:10","name":"[V2,13/15] binutils/NEWS: add text for SFrame support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-14-indu.bhagat@oracle.com/mbox/"},{"id":3772,"url":"https://patchwork.plctlab.org/api/1.2/patches/3772/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-15-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-15-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:11","name":"[V2,14/15] gas/NEWS: add text about new command line option and SFrame support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-15-indu.bhagat@oracle.com/mbox/"},{"id":3773,"url":"https://patchwork.plctlab.org/api/1.2/patches/3773/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-16-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-16-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:12","name":"[V2,15/15] doc: add SFrame spec file","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-16-indu.bhagat@oracle.com/mbox/"},{"id":3999,"url":"https://patchwork.plctlab.org/api/1.2/patches/3999/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221018081205.17880-1-krebbel@linux.ibm.com/","msgid":"<20221018081205.17880-1-krebbel@linux.ibm.com>","list_archive_url":null,"date":"2022-10-18T08:12:05","name":"[1/1] IBM zSystems: Issue error for *DBL relocs on misaligned symbols","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221018081205.17880-1-krebbel@linux.ibm.com/mbox/"},{"id":4141,"url":"https://patchwork.plctlab.org/api/1.2/patches/4141/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/baffaf673f17692b7bcbd604b31800b189988596.camel@espressif.com/","msgid":"","list_archive_url":null,"date":"2022-10-18T12:12:07","name":"xtensa: use definitions from xtensa-config.h","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/baffaf673f17692b7bcbd604b31800b189988596.camel@espressif.com/mbox/"},{"id":4272,"url":"https://patchwork.plctlab.org/api/1.2/patches/4272/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221018174914.470062-1-hjl.tools@gmail.com/","msgid":"<20221018174914.470062-1-hjl.tools@gmail.com>","list_archive_url":null,"date":"2022-10-18T17:49:14","name":"x86: Disable AVX-VNNI when disabling AVX2","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221018174914.470062-1-hjl.tools@gmail.com/mbox/"},{"id":4998,"url":"https://patchwork.plctlab.org/api/1.2/patches/4998/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c2f76e95-09f6-1d92-7ef4-38a3c2955fcd@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-19T09:52:46","name":"x86: re-work AVX-VNNI support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c2f76e95-09f6-1d92-7ef4-38a3c2955fcd@suse.com/mbox/"},{"id":5276,"url":"https://patchwork.plctlab.org/api/1.2/patches/5276/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0/lLtlKqqsmAx0s@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-19T11:53:18","name":"Fix addr2line test for ppc64 elfv1 and mingw","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0/lLtlKqqsmAx0s@squeak.grove.modra.org/mbox/"},{"id":5424,"url":"https://patchwork.plctlab.org/api/1.2/patches/5424/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/07bfebbf3843b47e13d82d4fa16eb14fec942ef7.1666184962.git.research_trasio@irq.a4lg.com/","msgid":"<07bfebbf3843b47e13d82d4fa16eb14fec942ef7.1666184962.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:09:54","name":"binutils: Remove unused substitution PROGRAM","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/07bfebbf3843b47e13d82d4fa16eb14fec942ef7.1666184962.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5433,"url":"https://patchwork.plctlab.org/api/1.2/patches/5433/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2fa7ff719223232402e82a9c91331aea22ace1bb.1666185116.git.research_trasio@irq.a4lg.com/","msgid":"<2fa7ff719223232402e82a9c91331aea22ace1bb.1666185116.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:11:55","name":"[v2,1/8] RISC-V: Add a space at the end of pinfo","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2fa7ff719223232402e82a9c91331aea22ace1bb.1666185116.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5435,"url":"https://patchwork.plctlab.org/api/1.2/patches/5435/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1b30cce5db2cce3b8edca42ab5da114d0b8c9e93.1666185116.git.research_trasio@irq.a4lg.com/","msgid":"<1b30cce5db2cce3b8edca42ab5da114d0b8c9e93.1666185116.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:11:56","name":"[v2,2/8] RISC-V: Fix obvious misalignments ('\''Zbb'\''/'\''Zba'\'')","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1b30cce5db2cce3b8edca42ab5da114d0b8c9e93.1666185116.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5437,"url":"https://patchwork.plctlab.org/api/1.2/patches/5437/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6b0857aa1a2d15ca1cf00b4dcaae0032efbb88ff.1666185116.git.research_trasio@irq.a4lg.com/","msgid":"<6b0857aa1a2d15ca1cf00b4dcaae0032efbb88ff.1666185116.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:11:57","name":"[v2,3/8] RISC-V: Remove spaces in opcode entries","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6b0857aa1a2d15ca1cf00b4dcaae0032efbb88ff.1666185116.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5436,"url":"https://patchwork.plctlab.org/api/1.2/patches/5436/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/889d956caac0f2e95543a14afaeed97188ce384c.1666185116.git.research_trasio@irq.a4lg.com/","msgid":"<889d956caac0f2e95543a14afaeed97188ce384c.1666185116.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:11:58","name":"[v2,4/8] RISC-V: Remove unused instruction macros","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/889d956caac0f2e95543a14afaeed97188ce384c.1666185116.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5440,"url":"https://patchwork.plctlab.org/api/1.2/patches/5440/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8f226ee20d8a5ef6ad7b6c4408b44794a99d542a.1666185116.git.research_trasio@irq.a4lg.com/","msgid":"<8f226ee20d8a5ef6ad7b6c4408b44794a99d542a.1666185116.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:11:59","name":"[v2,5/8] RISC-V: Complete tidying up with SCALL and SBREAK","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8f226ee20d8a5ef6ad7b6c4408b44794a99d542a.1666185116.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5442,"url":"https://patchwork.plctlab.org/api/1.2/patches/5442/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4070184c454a05a39adf0790951e5856e6b2ecb6.1666185116.git.research_trasio@irq.a4lg.com/","msgid":"<4070184c454a05a39adf0790951e5856e6b2ecb6.1666185116.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:12:00","name":"[v2,6/8] RISC-V: Tidying up with fmv.w.x and fmv.x.w","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4070184c454a05a39adf0790951e5856e6b2ecb6.1666185116.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5438,"url":"https://patchwork.plctlab.org/api/1.2/patches/5438/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c1ccda3e7c8fb297eda46dab3936d5c5977178fc.1666185116.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-19T13:12:01","name":"[v2,7/8] RISC-V: Make alias instructions aliases","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c1ccda3e7c8fb297eda46dab3936d5c5977178fc.1666185116.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5441,"url":"https://patchwork.plctlab.org/api/1.2/patches/5441/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/413cfca82c7e8d8a2e977dfda9135903c9cb7c57.1666185116.git.research_trasio@irq.a4lg.com/","msgid":"<413cfca82c7e8d8a2e977dfda9135903c9cb7c57.1666185116.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:12:02","name":"[v2,8/8] RISC-V: Use defined mask and match values","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/413cfca82c7e8d8a2e977dfda9135903c9cb7c57.1666185116.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5439,"url":"https://patchwork.plctlab.org/api/1.2/patches/5439/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/345c5c3b3a53eab04a1e6e91197de2642095c94f.1666185237.git.research_trasio@irq.a4lg.com/","msgid":"<345c5c3b3a53eab04a1e6e91197de2642095c94f.1666185237.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:14:01","name":"RISC-V: Remove RV32EF conflict","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/345c5c3b3a53eab04a1e6e91197de2642095c94f.1666185237.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5616,"url":"https://patchwork.plctlab.org/api/1.2/patches/5616/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019145608.45213-5-haochen.jiang@intel.com/","msgid":"<20221019145608.45213-5-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T14:56:02","name":"[04/10] Support Intel CMPccXADD","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019145608.45213-5-haochen.jiang@intel.com/mbox/"},{"id":5614,"url":"https://patchwork.plctlab.org/api/1.2/patches/5614/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019145608.45213-6-haochen.jiang@intel.com/","msgid":"<20221019145608.45213-6-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T14:56:03","name":"[05/10] Add handler for more i386_cpu_flags","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019145608.45213-6-haochen.jiang@intel.com/mbox/"},{"id":5672,"url":"https://patchwork.plctlab.org/api/1.2/patches/5672/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-2-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-2-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:25","name":"[01/10] Support Intel AVX-IFMA","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-2-haochen.jiang@intel.com/mbox/"},{"id":5691,"url":"https://patchwork.plctlab.org/api/1.2/patches/5691/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-3-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-3-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:26","name":"[02/10] Support Intel AVX-VNNI-INT8","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-3-haochen.jiang@intel.com/mbox/"},{"id":5690,"url":"https://patchwork.plctlab.org/api/1.2/patches/5690/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-4-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-4-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:27","name":"[03/10] Support Intel AVX-NE-CONVERT","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-4-haochen.jiang@intel.com/mbox/"},{"id":5689,"url":"https://patchwork.plctlab.org/api/1.2/patches/5689/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-5-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-5-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:28","name":"[04/10] Support Intel CMPccXADD","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-5-haochen.jiang@intel.com/mbox/"},{"id":5676,"url":"https://patchwork.plctlab.org/api/1.2/patches/5676/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-6-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-6-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:29","name":"[05/10] Add handler for more i386_cpu_flags","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-6-haochen.jiang@intel.com/mbox/"},{"id":5677,"url":"https://patchwork.plctlab.org/api/1.2/patches/5677/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-7-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-7-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:30","name":"[06/10] Support Intel RAO-INT","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-7-haochen.jiang@intel.com/mbox/"},{"id":5681,"url":"https://patchwork.plctlab.org/api/1.2/patches/5681/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-8-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-8-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:31","name":"[07/10] Support Intel WRMSRNS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-8-haochen.jiang@intel.com/mbox/"},{"id":5682,"url":"https://patchwork.plctlab.org/api/1.2/patches/5682/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-9-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-9-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:32","name":"[08/10] Support Intel MSRLIST","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-9-haochen.jiang@intel.com/mbox/"},{"id":5673,"url":"https://patchwork.plctlab.org/api/1.2/patches/5673/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-10-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-10-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:33","name":"[09/10] Support Intel AMX-FP16","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-10-haochen.jiang@intel.com/mbox/"},{"id":5686,"url":"https://patchwork.plctlab.org/api/1.2/patches/5686/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-11-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-11-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:34","name":"[10/10] Support Intel PREFETCHI","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-11-haochen.jiang@intel.com/mbox/"},{"id":5940,"url":"https://patchwork.plctlab.org/api/1.2/patches/5940/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1CMrFUC8d9lC/NL@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-19T23:47:56","name":"Obsolete beos","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1CMrFUC8d9lC/NL@squeak.grove.modra.org/mbox/"},{"id":6080,"url":"https://patchwork.plctlab.org/api/1.2/patches/6080/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8b99d666e78ba5b9d32c7889a2161c70b3da88df.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<8b99d666e78ba5b9d32c7889a2161c70b3da88df.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:25:47","name":"[01/40] gdb/unittests: PR28413, suppress warnings generated by Gnulib","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8b99d666e78ba5b9d32c7889a2161c70b3da88df.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6081,"url":"https://patchwork.plctlab.org/api/1.2/patches/6081/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b05adb17e401d621dbdad791281bc7af7806906e.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-20T09:25:48","name":"[02/40] sim: Check known getrusage declaration existence","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b05adb17e401d621dbdad791281bc7af7806906e.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6083,"url":"https://patchwork.plctlab.org/api/1.2/patches/6083/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/796962a87e569feeafb5ef636de3c79000ae152c.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<796962a87e569feeafb5ef636de3c79000ae152c.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:25:49","name":"[03/40] sim/aarch64: Remove unused functions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/796962a87e569feeafb5ef636de3c79000ae152c.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6084,"url":"https://patchwork.plctlab.org/api/1.2/patches/6084/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/65223c79fdfd7faf132275415cd9da9852c5bec3.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<65223c79fdfd7faf132275415cd9da9852c5bec3.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:25:50","name":"[04/40] cpu/cris: Initialize some variables on CRIS CPU","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/65223c79fdfd7faf132275415cd9da9852c5bec3.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6082,"url":"https://patchwork.plctlab.org/api/1.2/patches/6082/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/24baefe92148f4b7968115ba13de9b0c863a65f6.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<24baefe92148f4b7968115ba13de9b0c863a65f6.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:25:51","name":"[05/40] cpu/cris: Add u-stall virtual unit to CRIS v32","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/24baefe92148f4b7968115ba13de9b0c863a65f6.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6087,"url":"https://patchwork.plctlab.org/api/1.2/patches/6087/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3904a5c3e80f8548150d8088a92059dd728c7ff8.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<3904a5c3e80f8548150d8088a92059dd728c7ff8.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:25:52","name":"[06/40] sim/cris: Move declarations of f_specific_init","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3904a5c3e80f8548150d8088a92059dd728c7ff8.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6091,"url":"https://patchwork.plctlab.org/api/1.2/patches/6091/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/69ef2d7dd519ed572511890a215a0f6d74e53384.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<69ef2d7dd519ed572511890a215a0f6d74e53384.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:25:53","name":"[07/40] sim/cris: Regenerate with CGEN","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/69ef2d7dd519ed572511890a215a0f6d74e53384.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6085,"url":"https://patchwork.plctlab.org/api/1.2/patches/6085/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/26a3eaf4f5d2e0db6977738ddfd65d82b36e38b2.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<26a3eaf4f5d2e0db6977738ddfd65d82b36e38b2.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:25:54","name":"[08/40] sim/erc32: Insert void parameter","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/26a3eaf4f5d2e0db6977738ddfd65d82b36e38b2.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6086,"url":"https://patchwork.plctlab.org/api/1.2/patches/6086/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/057c2f8392410494c3bc5dc98052246508e6a73e.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<057c2f8392410494c3bc5dc98052246508e6a73e.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:25:55","name":"[09/40] sim/erc32: Use int32_t as event callback argument","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/057c2f8392410494c3bc5dc98052246508e6a73e.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6090,"url":"https://patchwork.plctlab.org/api/1.2/patches/6090/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8c05aec20557191434485be347d37177a2ec5ff2.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<8c05aec20557191434485be347d37177a2ec5ff2.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:25:56","name":"[10/40] sim/erc32: Use int32_t as IRQ callback argument","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8c05aec20557191434485be347d37177a2ec5ff2.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6089,"url":"https://patchwork.plctlab.org/api/1.2/patches/6089/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/afd7757aae21743c29f2aa4135a23b31d4959e9b.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-20T09:25:57","name":"[11/40] cpu/frv: Initialize some variables","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/afd7757aae21743c29f2aa4135a23b31d4959e9b.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6088,"url":"https://patchwork.plctlab.org/api/1.2/patches/6088/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/021dbd238af5dfe74523ed229d2156a155a6bb9e.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<021dbd238af5dfe74523ed229d2156a155a6bb9e.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:25:58","name":"[12/40] sim/frv: Initialize nesr variable","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/021dbd238af5dfe74523ed229d2156a155a6bb9e.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6093,"url":"https://patchwork.plctlab.org/api/1.2/patches/6093/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/51a03f7097921cc48954210cf99e370ae8982ec8.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<51a03f7097921cc48954210cf99e370ae8982ec8.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:25:59","name":"[13/40] sim/frv: Initialize some variables","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/51a03f7097921cc48954210cf99e370ae8982ec8.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6092,"url":"https://patchwork.plctlab.org/api/1.2/patches/6092/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e1baa1be3601612266dc6ae0bdde8426ff2a42c8.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-20T09:26:00","name":"[14/40] sim/frv: Add explicit casts","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e1baa1be3601612266dc6ae0bdde8426ff2a42c8.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6095,"url":"https://patchwork.plctlab.org/api/1.2/patches/6095/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5ab303a5bdfc1da7832f8fa22f57678c9ef1a5fa.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<5ab303a5bdfc1da7832f8fa22f57678c9ef1a5fa.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:26:01","name":"[15/40] sim/h8300: Add \"+ 0x0\" to avoid self-assignments","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5ab303a5bdfc1da7832f8fa22f57678c9ef1a5fa.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6101,"url":"https://patchwork.plctlab.org/api/1.2/patches/6101/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ddff80db3328a2286fe6fbc1240d2abc1e3813eb.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-20T09:26:02","name":"[16/40] sim/lm32: fix some missing function declaration warnings","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ddff80db3328a2286fe6fbc1240d2abc1e3813eb.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6094,"url":"https://patchwork.plctlab.org/api/1.2/patches/6094/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e094b1379231d9ffb59a78cfebbcc84634c779c6.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-20T09:26:03","name":"[17/40] sim/lm32: Add explicit casts","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e094b1379231d9ffb59a78cfebbcc84634c779c6.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6141,"url":"https://patchwork.plctlab.org/api/1.2/patches/6141/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/cabebead-489b-528c-580e-933832417474@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-20T10:25:51","name":"[1/3] x86: emit {evex} prefix when disassembling ambiguous AVX512VL insns","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/cabebead-489b-528c-580e-933832417474@suse.com/mbox/"},{"id":6143,"url":"https://patchwork.plctlab.org/api/1.2/patches/6143/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a032d61c-63a0-23d1-331f-619a2b8bbde3@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-20T10:26:15","name":"[2/3] x86: consolidate VAES tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a032d61c-63a0-23d1-331f-619a2b8bbde3@suse.com/mbox/"},{"id":6142,"url":"https://patchwork.plctlab.org/api/1.2/patches/6142/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7ff09c86-2de7-dc34-3183-5187de3df5ac@suse.com/","msgid":"<7ff09c86-2de7-dc34-3183-5187de3df5ac@suse.com>","list_archive_url":null,"date":"2022-10-20T10:26:40","name":"[3/3] x86: consolidate VPCLMUL tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7ff09c86-2de7-dc34-3183-5187de3df5ac@suse.com/mbox/"},{"id":6228,"url":"https://patchwork.plctlab.org/api/1.2/patches/6228/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.LSU.2.20.2210201432170.29399@wotan.suse.de/","msgid":"","list_archive_url":null,"date":"2022-10-20T14:42:25","name":"x86-64: Use only one default max-page-size","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.LSU.2.20.2210201432170.29399@wotan.suse.de/mbox/"},{"id":6229,"url":"https://patchwork.plctlab.org/api/1.2/patches/6229/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221020144351.1398099-1-chigot@adacore.com/","msgid":"<20221020144351.1398099-1-chigot@adacore.com>","list_archive_url":null,"date":"2022-10-20T14:43:50","name":"[1/2] ld/testsuite: skip ld-elf/exclude when -shared is not supported","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221020144351.1398099-1-chigot@adacore.com/mbox/"},{"id":6230,"url":"https://patchwork.plctlab.org/api/1.2/patches/6230/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221020144351.1398099-2-chigot@adacore.com/","msgid":"<20221020144351.1398099-2-chigot@adacore.com>","list_archive_url":null,"date":"2022-10-20T14:43:51","name":"[2/2] ld/testsuite: adjust ld-arm to run shared tests only when supported","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221020144351.1398099-2-chigot@adacore.com/mbox/"},{"id":6236,"url":"https://patchwork.plctlab.org/api/1.2/patches/6236/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221020151027.GA1300@delia.home/","msgid":"<20221020151027.GA1300@delia.home>","list_archive_url":null,"date":"2022-10-20T15:10:28","name":"[RFC,top-level] Add configure test-case","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221020151027.GA1300@delia.home/mbox/"},{"id":6286,"url":"https://patchwork.plctlab.org/api/1.2/patches/6286/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221020162911.1113338-1-hjl.tools@gmail.com/","msgid":"<20221020162911.1113338-1-hjl.tools@gmail.com>","list_archive_url":null,"date":"2022-10-20T16:29:11","name":"x86: Check VEX/EVEX encoding before checking vector operands","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221020162911.1113338-1-hjl.tools@gmail.com/mbox/"},{"id":7884,"url":"https://patchwork.plctlab.org/api/1.2/patches/7884/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7e53b7980f2b3b74d2250bc87f5db94b1d888a2d.camel@espressif.com/","msgid":"<7e53b7980f2b3b74d2250bc87f5db94b1d888a2d.camel@espressif.com>","list_archive_url":null,"date":"2022-10-22T12:53:54","name":"[1/5] bfd: xtensa: move common code from ld and gas","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7e53b7980f2b3b74d2250bc87f5db94b1d888a2d.camel@espressif.com/mbox/"},{"id":7885,"url":"https://patchwork.plctlab.org/api/1.2/patches/7885/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/63f2699e6ef3e6d1ca415a6ed1187d4f64297521.camel@espressif.com/","msgid":"<63f2699e6ef3e6d1ca415a6ed1187d4f64297521.camel@espressif.com>","list_archive_url":null,"date":"2022-10-22T12:55:16","name":"[2/5] gas: xtensa: add endianness, loops, booleans options","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/63f2699e6ef3e6d1ca415a6ed1187d4f64297521.camel@espressif.com/mbox/"},{"id":7886,"url":"https://patchwork.plctlab.org/api/1.2/patches/7886/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/34d2f747237aeeda595560cfded8096d9bd1c28c.camel@espressif.com/","msgid":"<34d2f747237aeeda595560cfded8096d9bd1c28c.camel@espressif.com>","list_archive_url":null,"date":"2022-10-22T12:56:02","name":"[3/5] ld: xtensa: use default LD command line options for endianness","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/34d2f747237aeeda595560cfded8096d9bd1c28c.camel@espressif.com/mbox/"},{"id":7891,"url":"https://patchwork.plctlab.org/api/1.2/patches/7891/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/535b6208c1718b9acf3258575e1ebc0a65af9f07.camel@espressif.com/","msgid":"<535b6208c1718b9acf3258575e1ebc0a65af9f07.camel@espressif.com>","list_archive_url":null,"date":"2022-10-22T13:56:44","name":"[5/5] gdb: xtensa: add support for esp32, esp32s2, esp32s3 isa-modules","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/535b6208c1718b9acf3258575e1ebc0a65af9f07.camel@espressif.com/mbox/"},{"id":10456,"url":"https://patchwork.plctlab.org/api/1.2/patches/10456/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221025013347.68282-1-nelson@rivosinc.com/","msgid":"<20221025013347.68282-1-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-10-25T01:33:46","name":"[committed,1/2] RISC-V: Improve link time complexity.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221025013347.68282-1-nelson@rivosinc.com/mbox/"},{"id":10454,"url":"https://patchwork.plctlab.org/api/1.2/patches/10454/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221025013347.68282-2-nelson@rivosinc.com/","msgid":"<20221025013347.68282-2-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-10-25T01:33:47","name":"[committed,2/2] RISC-V: Should reset `again'\'' flag for _bfd_riscv_relax_pc.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221025013347.68282-2-nelson@rivosinc.com/mbox/"},{"id":10536,"url":"https://patchwork.plctlab.org/api/1.2/patches/10536/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/bb7b87e4-1893-5c86-4a14-92bafc818b03@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-25T07:24:56","name":"[v5,1/8] x86: constify parse_insn()'\''s input","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/bb7b87e4-1893-5c86-4a14-92bafc818b03@suse.com/mbox/"},{"id":10537,"url":"https://patchwork.plctlab.org/api/1.2/patches/10537/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b9273ae6-0218-54f8-5374-b265ed13b71a@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-25T07:25:26","name":"[v5,1/8] x86: introduce Pass2 insn attribute","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b9273ae6-0218-54f8-5374-b265ed13b71a@suse.com/mbox/"},{"id":10541,"url":"https://patchwork.plctlab.org/api/1.2/patches/10541/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7250dab9-e218-e6dd-4c74-23da9f611ab4@suse.com/","msgid":"<7250dab9-e218-e6dd-4c74-23da9f611ab4@suse.com>","list_archive_url":null,"date":"2022-10-25T07:26:11","name":"[v5,3/8] x86: re-work insn/suffix recognition","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7250dab9-e218-e6dd-4c74-23da9f611ab4@suse.com/mbox/"},{"id":10540,"url":"https://patchwork.plctlab.org/api/1.2/patches/10540/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/13fc630f-e116-0099-5c9e-2697df6519d7@suse.com/","msgid":"<13fc630f-e116-0099-5c9e-2697df6519d7@suse.com>","list_archive_url":null,"date":"2022-10-25T07:26:40","name":"[v5,4/8] ix86: don'\''t recognize/derive Q suffix in the common case","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/13fc630f-e116-0099-5c9e-2697df6519d7@suse.com/mbox/"},{"id":10543,"url":"https://patchwork.plctlab.org/api/1.2/patches/10543/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/74db429d-d203-eab8-4ae1-18b9ad416b02@suse.com/","msgid":"<74db429d-d203-eab8-4ae1-18b9ad416b02@suse.com>","list_archive_url":null,"date":"2022-10-25T07:27:11","name":"[v5,5/8] x86-64: allow HLE store of accumulator to absolute 32-bit address","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/74db429d-d203-eab8-4ae1-18b9ad416b02@suse.com/mbox/"},{"id":10542,"url":"https://patchwork.plctlab.org/api/1.2/patches/10542/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2e2f7841-de4e-b5de-e8d9-a47a6a4113c8@suse.com/","msgid":"<2e2f7841-de4e-b5de-e8d9-a47a6a4113c8@suse.com>","list_archive_url":null,"date":"2022-10-25T07:27:35","name":"[v5,6/8] x86: move bad-use-of-TLS-reloc check","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2e2f7841-de4e-b5de-e8d9-a47a6a4113c8@suse.com/mbox/"},{"id":10545,"url":"https://patchwork.plctlab.org/api/1.2/patches/10545/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/421bc96e-7591-6980-48e9-5af8c8b0775a@suse.com/","msgid":"<421bc96e-7591-6980-48e9-5af8c8b0775a@suse.com>","list_archive_url":null,"date":"2022-10-25T07:28:27","name":"[v5,7/8] x86: drop (now) stray IsString","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/421bc96e-7591-6980-48e9-5af8c8b0775a@suse.com/mbox/"},{"id":10546,"url":"https://patchwork.plctlab.org/api/1.2/patches/10546/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/06ff83d4-4633-a07b-70e5-a8e049981dd4@suse.com/","msgid":"<06ff83d4-4633-a07b-70e5-a8e049981dd4@suse.com>","list_archive_url":null,"date":"2022-10-25T07:29:18","name":"[v5,8/8] x86: further re-work insn/suffix recognition to also cover MOVSX","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/06ff83d4-4633-a07b-70e5-a8e049981dd4@suse.com/mbox/"},{"id":10777,"url":"https://patchwork.plctlab.org/api/1.2/patches/10777/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6a8e7a71acccd0efb9789dfb3edfa307e83bdaa1.1666702934.git.research_trasio@irq.a4lg.com/","msgid":"<6a8e7a71acccd0efb9789dfb3edfa307e83bdaa1.1666702934.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-25T13:04:02","name":"[RFC] RISC-V: Allocate \"various\" operand type","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6a8e7a71acccd0efb9789dfb3edfa307e83bdaa1.1666702934.git.research_trasio@irq.a4lg.com/mbox/"},{"id":11062,"url":"https://patchwork.plctlab.org/api/1.2/patches/11062/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jAhwbXhxJHL66v@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-26T05:07:19","name":"PR29720, objdump -S crashes if build-id is missing","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jAhwbXhxJHL66v@squeak.grove.modra.org/mbox/"},{"id":11063,"url":"https://patchwork.plctlab.org/api/1.2/patches/11063/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jAxD+NxpMIah6s@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-26T05:08:20","name":"som.c buffer overflow","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jAxD+NxpMIah6s@squeak.grove.modra.org/mbox/"},{"id":11064,"url":"https://patchwork.plctlab.org/api/1.2/patches/11064/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jBYw4lfRQfOZhi@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-26T05:10:59","name":"som.c reloc sanity checking","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jBYw4lfRQfOZhi@squeak.grove.modra.org/mbox/"},{"id":11080,"url":"https://patchwork.plctlab.org/api/1.2/patches/11080/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jY7hygm01PelCY@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-26T06:51:26","name":"segfault in objdump.c reloc_at","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jY7hygm01PelCY@squeak.grove.modra.org/mbox/"},{"id":11081,"url":"https://patchwork.plctlab.org/api/1.2/patches/11081/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jZWIeIvCCYm9/g@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-26T06:53:12","name":"Correct ELF reloc size sanity check","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jZWIeIvCCYm9/g@squeak.grove.modra.org/mbox/"},{"id":11082,"url":"https://patchwork.plctlab.org/api/1.2/patches/11082/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221026070009.3663574-1-ysato@users.sourceforge.jp/","msgid":"<20221026070009.3663574-1-ysato@users.sourceforge.jp>","list_archive_url":null,"date":"2022-10-26T07:00:09","name":"opcodes: RX fix invalid output.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221026070009.3663574-1-ysato@users.sourceforge.jp/mbox/"},{"id":11089,"url":"https://patchwork.plctlab.org/api/1.2/patches/11089/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jhW48kuVC8Ig2d@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-26T07:27:23","name":"buffer overflow in _bfd_XX_print_ce_compressed_pdata","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jhW48kuVC8Ig2d@squeak.grove.modra.org/mbox/"},{"id":11157,"url":"https://patchwork.plctlab.org/api/1.2/patches/11157/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c52dbd16-7e1b-c356-7a92-1ff089564ef7@suse.cz/","msgid":"","list_archive_url":null,"date":"2022-10-26T08:47:09","name":"tests: use canonical option name","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c52dbd16-7e1b-c356-7a92-1ff089564ef7@suse.cz/mbox/"},{"id":11526,"url":"https://patchwork.plctlab.org/api/1.2/patches/11526/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027031915.4013-1-lifang_xia@linux.alibaba.com/","msgid":"<20221027031915.4013-1-lifang_xia@linux.alibaba.com>","list_archive_url":null,"date":"2022-10-27T03:19:15","name":"[v2] RISC-V: Optimize relax of GP/call with max_alignment.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027031915.4013-1-lifang_xia@linux.alibaba.com/mbox/"},{"id":11619,"url":"https://patchwork.plctlab.org/api/1.2/patches/11619/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9df9d9e5bb4c7594b76c40613a349b4d2364e9c5.1666854355.git.research_trasio@irq.a4lg.com/","msgid":"<9df9d9e5bb4c7594b76c40613a349b4d2364e9c5.1666854355.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-27T07:06:01","name":"include: Define macro to ignore -Wdeprecated-declarations on GCC","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9df9d9e5bb4c7594b76c40613a349b4d2364e9c5.1666854355.git.research_trasio@irq.a4lg.com/mbox/"},{"id":11627,"url":"https://patchwork.plctlab.org/api/1.2/patches/11627/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1o06O9Pp8ncCsOw@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-27T07:36:08","name":"Fuzzed files in archives","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1o06O9Pp8ncCsOw@squeak.grove.modra.org/mbox/"},{"id":11658,"url":"https://patchwork.plctlab.org/api/1.2/patches/11658/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027084808.37252-1-nelson@rivosinc.com/","msgid":"<20221027084808.37252-1-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-10-27T08:48:08","name":"[committed] RISC-V: Fix build failures for -Werror=sign-compare.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027084808.37252-1-nelson@rivosinc.com/mbox/"},{"id":11921,"url":"https://patchwork.plctlab.org/api/1.2/patches/11921/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027190052.10536-1-mark@harmstone.com/","msgid":"<20221027190052.10536-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-27T19:00:51","name":"[1/2] ld: Add section header stream to PDB files","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027190052.10536-1-mark@harmstone.com/mbox/"},{"id":11922,"url":"https://patchwork.plctlab.org/api/1.2/patches/11922/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027190052.10536-2-mark@harmstone.com/","msgid":"<20221027190052.10536-2-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-27T19:00:52","name":"[2/2] ld: Add publics stream to PDB files","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027190052.10536-2-mark@harmstone.com/mbox/"},{"id":11965,"url":"https://patchwork.plctlab.org/api/1.2/patches/11965/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027202719.32497-1-palmer@rivosinc.com/","msgid":"<20221027202719.32497-1-palmer@rivosinc.com>","list_archive_url":null,"date":"2022-10-27T20:27:18","name":"[1/2] gas: NEWS: Add a missing newline","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027202719.32497-1-palmer@rivosinc.com/mbox/"},{"id":11966,"url":"https://patchwork.plctlab.org/api/1.2/patches/11966/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027202719.32497-2-palmer@rivosinc.com/","msgid":"<20221027202719.32497-2-palmer@rivosinc.com>","list_archive_url":null,"date":"2022-10-27T20:27:19","name":"[2/2] gas: NEWS: Note support for RISC-V Zawrs","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027202719.32497-2-palmer@rivosinc.com/mbox/"},{"id":12016,"url":"https://patchwork.plctlab.org/api/1.2/patches/12016/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/21ec9a18-fa89-0828-f625-499680022ec7@linux.ibm.com/","msgid":"<21ec9a18-fa89-0828-f625-499680022ec7@linux.ibm.com>","list_archive_url":null,"date":"2022-10-28T00:35:19","name":"[COMMITTED] PowerPC: Add support for RFC02653 - Dense Math Facility","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/21ec9a18-fa89-0828-f625-499680022ec7@linux.ibm.com/mbox/"},{"id":12017,"url":"https://patchwork.plctlab.org/api/1.2/patches/12017/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fd94047d-a070-45a6-3840-c105391718e0@linux.ibm.com/","msgid":"","list_archive_url":null,"date":"2022-10-28T00:37:18","name":"[COMMITTED] PowerPC: Add support for RFC02658 - MMA+ Outer-Product, Instructions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fd94047d-a070-45a6-3840-c105391718e0@linux.ibm.com/mbox/"},{"id":12122,"url":"https://patchwork.plctlab.org/api/1.2/patches/12122/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ac4f3f3c7115a824f73aca6935789b14d33c9a58.1666939920.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-28T06:53:02","name":"RISC-V: Fix build failure for -Werror=maybe-uninitialized","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ac4f3f3c7115a824f73aca6935789b14d33c9a58.1666939920.git.research_trasio@irq.a4lg.com/mbox/"},{"id":12181,"url":"https://patchwork.plctlab.org/api/1.2/patches/12181/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221028093840.19164-1-nelson@rivosinc.com/","msgid":"<20221028093840.19164-1-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-10-28T09:38:40","name":"RISC-V: Added SiFive custom cache control extensions.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221028093840.19164-1-nelson@rivosinc.com/mbox/"},{"id":12211,"url":"https://patchwork.plctlab.org/api/1.2/patches/12211/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4a280588-a85b-6ed3-634b-2b9cbc128f86@suse.com/","msgid":"<4a280588-a85b-6ed3-634b-2b9cbc128f86@suse.com>","list_archive_url":null,"date":"2022-10-28T10:06:35","name":"RISC-V/gas: fix build with certain gcc versions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4a280588-a85b-6ed3-634b-2b9cbc128f86@suse.com/mbox/"},{"id":12249,"url":"https://patchwork.plctlab.org/api/1.2/patches/12249/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/eb0e1bff-675e-72db-b8b1-b0f0e50b7121@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-28T12:35:35","name":"x86: minor improvements to optimize_imm() (part III)","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/eb0e1bff-675e-72db-b8b1-b0f0e50b7121@suse.com/mbox/"},{"id":12382,"url":"https://patchwork.plctlab.org/api/1.2/patches/12382/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/17f57574936af82be381a1451eac56b3709b60bb.1666968673.git.research_trasio@irq.a4lg.com/","msgid":"<17f57574936af82be381a1451eac56b3709b60bb.1666968673.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-28T14:52:12","name":"RISC-V: Emit mapping symbol with ISA string if non-default arch is used","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/17f57574936af82be381a1451eac56b3709b60bb.1666968673.git.research_trasio@irq.a4lg.com/mbox/"},{"id":12627,"url":"https://patchwork.plctlab.org/api/1.2/patches/12627/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221029034432.49859-1-nelson@rivosinc.com/","msgid":"<20221029034432.49859-1-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-10-29T03:44:32","name":"[committed] RISC-V: Always generate mapping symbols at the start of the sections.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221029034432.49859-1-nelson@rivosinc.com/mbox/"},{"id":12629,"url":"https://patchwork.plctlab.org/api/1.2/patches/12629/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1yxgzNJg5M48uPI@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-29T04:52:19","name":"NULL dereference read in som_write_object_contents","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1yxgzNJg5M48uPI@squeak.grove.modra.org/mbox/"},{"id":12630,"url":"https://patchwork.plctlab.org/api/1.2/patches/12630/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1yxnSHLY+FeB5DQ@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-29T04:52:45","name":"Fix small objcopy memory leak","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1yxnSHLY+FeB5DQ@squeak.grove.modra.org/mbox/"},{"id":12631,"url":"https://patchwork.plctlab.org/api/1.2/patches/12631/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1yxxfpJz+Jx4KTh@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-29T04:53:25","name":"pef: sanity check before malloc","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1yxxfpJz+Jx4KTh@squeak.grove.modra.org/mbox/"},{"id":12950,"url":"https://patchwork.plctlab.org/api/1.2/patches/12950/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-2-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-2-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:36","name":"[V3,01/15] sframe.h: Add SFrame format definition","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-2-indu.bhagat@oracle.com/mbox/"},{"id":12952,"url":"https://patchwork.plctlab.org/api/1.2/patches/12952/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-3-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-3-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:37","name":"[V3,02/15] gas: add new command line option --gsframe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-3-indu.bhagat@oracle.com/mbox/"},{"id":12951,"url":"https://patchwork.plctlab.org/api/1.2/patches/12951/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-4-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-4-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:38","name":"[V3,03/15] gas: generate .sframe from CFI directives","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-4-indu.bhagat@oracle.com/mbox/"},{"id":12956,"url":"https://patchwork.plctlab.org/api/1.2/patches/12956/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-5-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-5-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:39","name":"[V3,04/15] gas: testsuite: add new tests for SFrame unwind info","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-5-indu.bhagat@oracle.com/mbox/"},{"id":12955,"url":"https://patchwork.plctlab.org/api/1.2/patches/12955/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-6-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-6-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:40","name":"[V3,05/15] libsframe: add the SFrame library","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-6-indu.bhagat@oracle.com/mbox/"},{"id":12959,"url":"https://patchwork.plctlab.org/api/1.2/patches/12959/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-7-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-7-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:41","name":"[V3,06/15] bfd: linker: merge .sframe sections","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-7-indu.bhagat@oracle.com/mbox/"},{"id":12961,"url":"https://patchwork.plctlab.org/api/1.2/patches/12961/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-8-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-8-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:42","name":"[V3,07/15] readelf/objdump: support for SFrame section","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-8-indu.bhagat@oracle.com/mbox/"},{"id":12962,"url":"https://patchwork.plctlab.org/api/1.2/patches/12962/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-9-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-9-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:43","name":"[V3,08/15] unwinder: generate backtrace using SFrame format","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-9-indu.bhagat@oracle.com/mbox/"},{"id":12963,"url":"https://patchwork.plctlab.org/api/1.2/patches/12963/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-10-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-10-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:44","name":"[V3,09/15] unwinder: Add SFrame unwinder tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-10-indu.bhagat@oracle.com/mbox/"},{"id":12964,"url":"https://patchwork.plctlab.org/api/1.2/patches/12964/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-11-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-11-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:45","name":"[V3,10/15] gdb: sim: buildsystem changes to accommodate libsframe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-11-indu.bhagat@oracle.com/mbox/"},{"id":12957,"url":"https://patchwork.plctlab.org/api/1.2/patches/12957/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-12-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-12-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:46","name":"[V3,11/15] libctf: add libsframe to LDFLAGS and LIBS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-12-indu.bhagat@oracle.com/mbox/"},{"id":12960,"url":"https://patchwork.plctlab.org/api/1.2/patches/12960/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-13-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-13-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:47","name":"[V3,12/15] src-release.sh: Add libsframe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-13-indu.bhagat@oracle.com/mbox/"},{"id":12953,"url":"https://patchwork.plctlab.org/api/1.2/patches/12953/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-14-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-14-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:48","name":"[V3,13/15] binutils/NEWS: add text for SFrame support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-14-indu.bhagat@oracle.com/mbox/"},{"id":12954,"url":"https://patchwork.plctlab.org/api/1.2/patches/12954/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-15-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-15-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:49","name":"[V3,14/15] gas/NEWS: add text about new command line option and SFrame support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-15-indu.bhagat@oracle.com/mbox/"},{"id":12958,"url":"https://patchwork.plctlab.org/api/1.2/patches/12958/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-16-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-16-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:50","name":"[V3,15/15] doc: add SFrame spec file","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-16-indu.bhagat@oracle.com/mbox/"},{"id":12988,"url":"https://patchwork.plctlab.org/api/1.2/patches/12988/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y15KFY32CyFhh/+u@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-30T09:55:33","name":"Pool section entries for DWP version 1","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y15KFY32CyFhh/+u@squeak.grove.modra.org/mbox/"},{"id":13076,"url":"https://patchwork.plctlab.org/api/1.2/patches/13076/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031001554.14615-1-mark@harmstone.com/","msgid":"<20221031001554.14615-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-31T00:15:52","name":"[v2,1/3] ld: Use %E in einfo in pdb.c","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031001554.14615-1-mark@harmstone.com/mbox/"},{"id":13078,"url":"https://patchwork.plctlab.org/api/1.2/patches/13078/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031001554.14615-2-mark@harmstone.com/","msgid":"<20221031001554.14615-2-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-31T00:15:53","name":"[v2,2/3] ld: Add section header stream to PDB files","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031001554.14615-2-mark@harmstone.com/mbox/"},{"id":13077,"url":"https://patchwork.plctlab.org/api/1.2/patches/13077/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031001554.14615-3-mark@harmstone.com/","msgid":"<20221031001554.14615-3-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-31T00:15:54","name":"[v2,3/3] ld: Add publics stream to PDB files","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031001554.14615-3-mark@harmstone.com/mbox/"},{"id":13106,"url":"https://patchwork.plctlab.org/api/1.2/patches/13106/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031030507.35588-2-haochen.jiang@intel.com/","msgid":"<20221031030507.35588-2-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-31T03:05:02","name":"[1/6] Support Intel AVX-IFMA","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031030507.35588-2-haochen.jiang@intel.com/mbox/"},{"id":13105,"url":"https://patchwork.plctlab.org/api/1.2/patches/13105/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031030507.35588-3-haochen.jiang@intel.com/","msgid":"<20221031030507.35588-3-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-31T03:05:03","name":"[2/6] Support Intel AVX-VNNI-INT8","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031030507.35588-3-haochen.jiang@intel.com/mbox/"},{"id":13103,"url":"https://patchwork.plctlab.org/api/1.2/patches/13103/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031030507.35588-4-haochen.jiang@intel.com/","msgid":"<20221031030507.35588-4-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-31T03:05:04","name":"[3/6] Support Intel CMPccXADD","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031030507.35588-4-haochen.jiang@intel.com/mbox/"},{"id":13101,"url":"https://patchwork.plctlab.org/api/1.2/patches/13101/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031030507.35588-5-haochen.jiang@intel.com/","msgid":"<20221031030507.35588-5-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-31T03:05:05","name":"[4/6] Add handler for more i386_cpu_flags","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031030507.35588-5-haochen.jiang@intel.com/mbox/"},{"id":13104,"url":"https://patchwork.plctlab.org/api/1.2/patches/13104/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031030507.35588-6-haochen.jiang@intel.com/","msgid":"<20221031030507.35588-6-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-31T03:05:06","name":"[5/6] Support Intel WRMSRNS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031030507.35588-6-haochen.jiang@intel.com/mbox/"},{"id":13102,"url":"https://patchwork.plctlab.org/api/1.2/patches/13102/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031030507.35588-7-haochen.jiang@intel.com/","msgid":"<20221031030507.35588-7-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-31T03:05:07","name":"[6/6] Support Intel MSRLIST","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031030507.35588-7-haochen.jiang@intel.com/mbox/"},{"id":13120,"url":"https://patchwork.plctlab.org/api/1.2/patches/13120/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031060601.38460-2-haochen.jiang@intel.com/","msgid":"<20221031060601.38460-2-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-31T06:06:00","name":"[1/2] i386: Add and ","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031060601.38460-2-haochen.jiang@intel.com/mbox/"},{"id":13121,"url":"https://patchwork.plctlab.org/api/1.2/patches/13121/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031060601.38460-3-haochen.jiang@intel.com/","msgid":"<20221031060601.38460-3-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-31T06:06:01","name":"[2/2] Support Intel AVX-NE-CONVERT","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031060601.38460-3-haochen.jiang@intel.com/mbox/"},{"id":13188,"url":"https://patchwork.plctlab.org/api/1.2/patches/13188/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9f6f8888-4dc1-a6b0-0590-35fc8a276369@suse.com/","msgid":"<9f6f8888-4dc1-a6b0-0590-35fc8a276369@suse.com>","list_archive_url":null,"date":"2022-10-31T10:18:20","name":"x86: drop bogus Tbyte","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9f6f8888-4dc1-a6b0-0590-35fc8a276369@suse.com/mbox/"},{"id":13213,"url":"https://patchwork.plctlab.org/api/1.2/patches/13213/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4f1aac95-fea5-2279-cb18-dfcdb51a2589@arm.com/","msgid":"<4f1aac95-fea5-2279-cb18-dfcdb51a2589@arm.com>","list_archive_url":null,"date":"2022-10-31T11:14:44","name":"aarch64: Add support for Common Short Sequence Compression extension","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4f1aac95-fea5-2279-cb18-dfcdb51a2589@arm.com/mbox/"}],"public":true,"mbox":"https://patchwork.plctlab.org/bundle/patchwork-bot/binutils-gdb_2022-10/mbox/"},{"id":7,"url":"https://patchwork.plctlab.org/api/1.2/bundles/7/","web_url":"https://patchwork.plctlab.org/bundle/patchwork-bot/binutils-gdb_2022-09/","project":{"id":2,"url":"https://patchwork.plctlab.org/api/1.2/projects/2/","name":"binutils-gdb","link_name":"binutils-gdb","list_id":"binutils.sourceware.org","list_email":"binutils@sourceware.org","web_url":"https://github.com/wangliu-iscas/Patchwork-Bundles/blob/main/binutils-gdb.md","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"name":"binutils-gdb_2022-09","owner":{"id":3,"url":"https://patchwork.plctlab.org/api/1.2/users/3/","username":"patchwork-bot","first_name":"","last_name":"","email":"ouuuleilei@gmail.com"},"patches":[{"id":1573,"url":"https://patchwork.plctlab.org/api/1.2/patches/1573/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930073211.2634-1-jiawei@iscas.ac.cn/","msgid":"<20220930073211.2634-1-jiawei@iscas.ac.cn>","list_archive_url":null,"date":"2022-09-30T07:32:11","name":"[V2] RISC-V: Add Smepmp CSR '\''mseccfg'\'' define and testcases.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930073211.2634-1-jiawei@iscas.ac.cn/mbox/"},{"id":1577,"url":"https://patchwork.plctlab.org/api/1.2/patches/1577/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/76fa0c3c-2303-ebdf-a765-ac4731581517@suse.com/","msgid":"<76fa0c3c-2303-ebdf-a765-ac4731581517@suse.com>","list_archive_url":null,"date":"2022-09-30T08:54:18","name":"objcopy: avoid \"shadowing\" of remove() function name","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/76fa0c3c-2303-ebdf-a765-ac4731581517@suse.com/mbox/"},{"id":1579,"url":"https://patchwork.plctlab.org/api/1.2/patches/1579/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930085852.71213-1-nelson@rivosinc.com/","msgid":"<20220930085852.71213-1-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-09-30T08:58:51","name":"[1/2] RISC-V: Output mapping symbols with ISA string.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930085852.71213-1-nelson@rivosinc.com/mbox/"},{"id":1578,"url":"https://patchwork.plctlab.org/api/1.2/patches/1578/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930085852.71213-2-nelson@rivosinc.com/","msgid":"<20220930085852.71213-2-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-09-30T08:58:52","name":"[2/2] RISC-V: Refer mapping symbol to R_RISCV_RELAX for rvc relaxations.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930085852.71213-2-nelson@rivosinc.com/mbox/"},{"id":1581,"url":"https://patchwork.plctlab.org/api/1.2/patches/1581/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930092058.71286-1-nelson@rivosinc.com/","msgid":"<20220930092058.71286-1-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-09-30T09:20:57","name":"[1/2] RISC-V: Output mapping symbols with ISA string.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930092058.71286-1-nelson@rivosinc.com/mbox/"},{"id":1580,"url":"https://patchwork.plctlab.org/api/1.2/patches/1580/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930092058.71286-2-nelson@rivosinc.com/","msgid":"<20220930092058.71286-2-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-09-30T09:20:58","name":"[2/2] RISC-V: Refer mapping symbol to R_RISCV_RELAX for rvc relaxations.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930092058.71286-2-nelson@rivosinc.com/mbox/"},{"id":1582,"url":"https://patchwork.plctlab.org/api/1.2/patches/1582/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5874dd79-0cf5-d65c-7ea2-13adfc799c0f@suse.com/","msgid":"<5874dd79-0cf5-d65c-7ea2-13adfc799c0f@suse.com>","list_archive_url":null,"date":"2022-09-30T09:41:29","name":"RISC-V: fix build after \"Add support for arbitrary immediate encoding formats\"","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5874dd79-0cf5-d65c-7ea2-13adfc799c0f@suse.com/mbox/"},{"id":1583,"url":"https://patchwork.plctlab.org/api/1.2/patches/1583/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/57d8ac2a-5757-3776-9924-99c17ca69938@suse.com/","msgid":"<57d8ac2a-5757-3776-9924-99c17ca69938@suse.com>","list_archive_url":null,"date":"2022-09-30T09:42:08","name":"RISC-V: fallout from \"re-arrange opcode table for consistent alias handling\"","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/57d8ac2a-5757-3776-9924-99c17ca69938@suse.com/mbox/"},{"id":1584,"url":"https://patchwork.plctlab.org/api/1.2/patches/1584/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e76ef8f7-72b9-5103-cb43-9608af01d017@suse.com/","msgid":"","list_archive_url":null,"date":"2022-09-30T09:42:50","name":"RISC-V: don'\''t cast expressions'\'' X_add_number to long in diagnostics","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e76ef8f7-72b9-5103-cb43-9608af01d017@suse.com/mbox/"},{"id":1585,"url":"https://patchwork.plctlab.org/api/1.2/patches/1585/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/61355429-24b3-17d0-ab03-6fa57ee861d5@suse.cz/","msgid":"<61355429-24b3-17d0-ab03-6fa57ee861d5@suse.cz>","list_archive_url":null,"date":"2022-09-30T09:48:52","name":"[RFC] add --enable-zstd-compressed-debug-sections configure option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/61355429-24b3-17d0-ab03-6fa57ee861d5@suse.cz/mbox/"},{"id":1586,"url":"https://patchwork.plctlab.org/api/1.2/patches/1586/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930103919.323690-1-christoph.muellner@vrull.eu/","msgid":"<20220930103919.323690-1-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2022-09-30T10:39:19","name":"RISC-V: Eliminate long-casts of X_add_number in diagnostics","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930103919.323690-1-christoph.muellner@vrull.eu/mbox/"},{"id":1590,"url":"https://patchwork.plctlab.org/api/1.2/patches/1590/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/DM6PR12MB4219C943049C6D883DEA3E55E7569@DM6PR12MB4219.namprd12.prod.outlook.com/","msgid":"","list_archive_url":null,"date":"2022-09-30T11:41:37","name":"[V2] Ignore DWARF debug information for -gsplit-dwarf with dwarf-5.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/DM6PR12MB4219C943049C6D883DEA3E55E7569@DM6PR12MB4219.namprd12.prod.outlook.com/mbox/"},{"id":1591,"url":"https://patchwork.plctlab.org/api/1.2/patches/1591/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c10321f9-d289-ef84-d263-bc278fb3d31b@suse.com/","msgid":"","list_archive_url":null,"date":"2022-09-30T11:59:04","name":"[1/4] RISC-V/gas: drop riscv_subsets static variable","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c10321f9-d289-ef84-d263-bc278fb3d31b@suse.com/mbox/"},{"id":1593,"url":"https://patchwork.plctlab.org/api/1.2/patches/1593/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3244eea0-c18c-e49a-4588-d69423130226@suse.com/","msgid":"<3244eea0-c18c-e49a-4588-d69423130226@suse.com>","list_archive_url":null,"date":"2022-09-30T11:59:23","name":"[2/4] RISC-V/gas: drop stray call to install_insn()","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3244eea0-c18c-e49a-4588-d69423130226@suse.com/mbox/"},{"id":1592,"url":"https://patchwork.plctlab.org/api/1.2/patches/1592/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/385d01fd-7e57-1f3f-1bae-30aa0c313d63@suse.com/","msgid":"<385d01fd-7e57-1f3f-1bae-30aa0c313d63@suse.com>","list_archive_url":null,"date":"2022-09-30T11:59:45","name":"[3/4] RISC-V/gas: don'\''t open-code insn_length()","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/385d01fd-7e57-1f3f-1bae-30aa0c313d63@suse.com/mbox/"},{"id":1594,"url":"https://patchwork.plctlab.org/api/1.2/patches/1594/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f5757acf-7b90-a0e3-5eea-3b97cc226930@suse.com/","msgid":"","list_archive_url":null,"date":"2022-09-30T12:00:12","name":"[4/4] RISC-V/gas: allow generating up to 176-bit instructions with .insn","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f5757acf-7b90-a0e3-5eea-3b97cc226930@suse.com/mbox/"},{"id":1596,"url":"https://patchwork.plctlab.org/api/1.2/patches/1596/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930140503.38233-1-chigot@adacore.com/","msgid":"<20220930140503.38233-1-chigot@adacore.com>","list_archive_url":null,"date":"2022-09-30T14:05:03","name":"ld/testsuite: consistently add board_ldflags when linking with GCC","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930140503.38233-1-chigot@adacore.com/mbox/"}],"public":true,"mbox":"https://patchwork.plctlab.org/bundle/patchwork-bot/binutils-gdb_2022-09/mbox/"},{"id":9,"url":"https://patchwork.plctlab.org/api/1.2/bundles/9/","web_url":"https://patchwork.plctlab.org/bundle/patchwork-bot/binutils-gdb_2022-11/","project":{"id":2,"url":"https://patchwork.plctlab.org/api/1.2/projects/2/","name":"binutils-gdb","link_name":"binutils-gdb","list_id":"binutils.sourceware.org","list_email":"binutils@sourceware.org","web_url":"https://github.com/wangliu-iscas/Patchwork-Bundles/blob/main/binutils-gdb.md","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"name":"binutils-gdb_2022-11","owner":{"id":3,"url":"https://patchwork.plctlab.org/api/1.2/users/3/","username":"patchwork-bot","first_name":"","last_name":"","email":"ouuuleilei@gmail.com"},"patches":[{"id":13337,"url":"https://patchwork.plctlab.org/api/1.2/patches/13337/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031160625.684434-1-hjl.tools@gmail.com/","msgid":"<20221031160625.684434-1-hjl.tools@gmail.com>","list_archive_url":null,"date":"2022-10-31T16:06:25","name":"x86: Silence GCC 12 warning on tc-i386.c","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031160625.684434-1-hjl.tools@gmail.com/mbox/"},{"id":13350,"url":"https://patchwork.plctlab.org/api/1.2/patches/13350/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c8d25b29-37fe-9623-a799-e67e1f991743@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-31T17:00:56","name":"x86: simplify expressions in update_imm()","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c8d25b29-37fe-9623-a799-e67e1f991743@suse.com/mbox/"},{"id":13487,"url":"https://patchwork.plctlab.org/api/1.2/patches/13487/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/CAMe9rOohVjin92PTeeiu_dvAtzYJn4dGtu5E=OxYfbyteraZWw@mail.gmail.com/","msgid":"","list_archive_url":null,"date":"2022-11-01T00:08:04","name":"binutils: Run PR binutils/26160 test","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/CAMe9rOohVjin92PTeeiu_dvAtzYJn4dGtu5E=OxYfbyteraZWw@mail.gmail.com/mbox/"},{"id":13621,"url":"https://patchwork.plctlab.org/api/1.2/patches/13621/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221101105724.1527333-1-aburgess@redhat.com/","msgid":"<20221101105724.1527333-1-aburgess@redhat.com>","list_archive_url":null,"date":"2022-11-01T10:57:24","name":"[PUSHED] opcodes/arm: silence compiler warning about uninitialized variable use","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221101105724.1527333-1-aburgess@redhat.com/mbox/"},{"id":13628,"url":"https://patchwork.plctlab.org/api/1.2/patches/13628/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221101111802.1532080-1-aburgess@redhat.com/","msgid":"<20221101111802.1532080-1-aburgess@redhat.com>","list_archive_url":null,"date":"2022-11-01T11:18:02","name":"[PUSHED] opcodes/arm: don'\''t pass non-string literal to printf like function","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221101111802.1532080-1-aburgess@redhat.com/mbox/"},{"id":13747,"url":"https://patchwork.plctlab.org/api/1.2/patches/13747/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/yw8jbkpqk6vw.fsf@arm.com/","msgid":"","list_archive_url":null,"date":"2022-11-01T15:54:11","name":"[Binutils-2.39,backport,GAS] arm: Use DWARF numbering convention for pseudo-register representation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/yw8jbkpqk6vw.fsf@arm.com/mbox/"},{"id":13993,"url":"https://patchwork.plctlab.org/api/1.2/patches/13993/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221102020752.24441-1-mark@harmstone.com/","msgid":"<20221102020752.24441-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-11-02T02:07:52","name":"ld: Add module information substream to PDB files","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221102020752.24441-1-mark@harmstone.com/mbox/"},{"id":14028,"url":"https://patchwork.plctlab.org/api/1.2/patches/14028/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221102050430.1053-1-nelson@rivosinc.com/","msgid":"<20221102050430.1053-1-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-11-02T05:04:30","name":"[committed] RISC-V: Fixed the missing $x+arch when adding odd paddings for alignment.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221102050430.1053-1-nelson@rivosinc.com/mbox/"},{"id":14043,"url":"https://patchwork.plctlab.org/api/1.2/patches/14043/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221102063046.31551-1-rjiejie@linux.alibaba.com/","msgid":"<20221102063046.31551-1-rjiejie@linux.alibaba.com>","list_archive_url":null,"date":"2022-11-02T06:30:46","name":"gas/doc/internals.texi: fix typo","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221102063046.31551-1-rjiejie@linux.alibaba.com/mbox/"},{"id":14069,"url":"https://patchwork.plctlab.org/api/1.2/patches/14069/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221102080112.33378-1-rjiejie@linux.alibaba.com/","msgid":"<20221102080112.33378-1-rjiejie@linux.alibaba.com>","list_archive_url":null,"date":"2022-11-02T08:01:12","name":"[v2] Support multiple .eh_frame sections","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221102080112.33378-1-rjiejie@linux.alibaba.com/mbox/"},{"id":14409,"url":"https://patchwork.plctlab.org/api/1.2/patches/14409/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221102172923.4009281-1-christophe.lyon@arm.com/","msgid":"<20221102172923.4009281-1-christophe.lyon@arm.com>","list_archive_url":null,"date":"2022-11-02T17:29:23","name":"arm: PR 29739 Fix typo where '\''; '\'' should not have been replaced with '\''@'\''","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221102172923.4009281-1-christophe.lyon@arm.com/mbox/"},{"id":14588,"url":"https://patchwork.plctlab.org/api/1.2/patches/14588/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221103020409.37322-1-rjiejie@linux.alibaba.com/","msgid":"<20221103020409.37322-1-rjiejie@linux.alibaba.com>","list_archive_url":null,"date":"2022-11-03T02:04:09","name":"[v3] Support multiple .eh_frame sections","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221103020409.37322-1-rjiejie@linux.alibaba.com/mbox/"},{"id":14602,"url":"https://patchwork.plctlab.org/api/1.2/patches/14602/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221103024604.614-1-mark@harmstone.com/","msgid":"<20221103024604.614-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-11-03T02:46:04","name":"[v2] ld: Add module information substream to PDB files","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221103024604.614-1-mark@harmstone.com/mbox/"},{"id":14706,"url":"https://patchwork.plctlab.org/api/1.2/patches/14706/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221103071519.3510462-1-luis.machado@arm.com/","msgid":"<20221103071519.3510462-1-luis.machado@arm.com>","list_archive_url":null,"date":"2022-11-03T07:15:19","name":"[opcodes/arm] Fix potential null pointer dereferences","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221103071519.3510462-1-luis.machado@arm.com/mbox/"},{"id":14840,"url":"https://patchwork.plctlab.org/api/1.2/patches/14840/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/283a86ebf0941f0f63dc1a590ec3d547bd5d69e8.1667478033.git.research_trasio@irq.a4lg.com/","msgid":"<283a86ebf0941f0f63dc1a590ec3d547bd5d69e8.1667478033.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-03T12:26:28","name":"[REVIEW,ONLY,1/2] NEAR-RATIFICATION RISC-V: Add '\''Ssstateen'\'' extension and its CSRs","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/283a86ebf0941f0f63dc1a590ec3d547bd5d69e8.1667478033.git.research_trasio@irq.a4lg.com/mbox/"},{"id":14841,"url":"https://patchwork.plctlab.org/api/1.2/patches/14841/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8083ad9d5339afdeb7f1ba88ee6af0665dcc76d5.1667478033.git.research_trasio@irq.a4lg.com/","msgid":"<8083ad9d5339afdeb7f1ba88ee6af0665dcc76d5.1667478033.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-03T12:26:29","name":"[REVIEW,ONLY,2/2] NEAR-RATIFICATION RISC-V: Add platform property/capability extensions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8083ad9d5339afdeb7f1ba88ee6af0665dcc76d5.1667478033.git.research_trasio@irq.a4lg.com/mbox/"},{"id":14894,"url":"https://patchwork.plctlab.org/api/1.2/patches/14894/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e53fbf5025e59fe6a3481b9c1fe37e4f6cf6e03d.1667483581.git.aburgess@redhat.com/","msgid":"","list_archive_url":null,"date":"2022-11-03T13:58:12","name":"[1/2] opcodes/mips: use .word/.short for undefined instructions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e53fbf5025e59fe6a3481b9c1fe37e4f6cf6e03d.1667483581.git.aburgess@redhat.com/mbox/"},{"id":14893,"url":"https://patchwork.plctlab.org/api/1.2/patches/14893/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ca81edb86580566b1641ad140eb2bed385160ab7.1667483581.git.aburgess@redhat.com/","msgid":"","list_archive_url":null,"date":"2022-11-03T13:58:13","name":"[2/2] libopcodes/mips: add support for disassembler styling","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ca81edb86580566b1641ad140eb2bed385160ab7.1667483581.git.aburgess@redhat.com/mbox/"},{"id":15465,"url":"https://patchwork.plctlab.org/api/1.2/patches/15465/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/926e5154-b40b-9df8-d770-a8bf7d40e40e@suse.com/","msgid":"<926e5154-b40b-9df8-d770-a8bf7d40e40e@suse.com>","list_archive_url":null,"date":"2022-11-04T10:50:38","name":"[v6,1/7] x86: constify parse_insn()'\''s input","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/926e5154-b40b-9df8-d770-a8bf7d40e40e@suse.com/mbox/"},{"id":15466,"url":"https://patchwork.plctlab.org/api/1.2/patches/15466/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/07ef67fd-752c-ad1f-b8cb-4eaec1f420fc@suse.com/","msgid":"<07ef67fd-752c-ad1f-b8cb-4eaec1f420fc@suse.com>","list_archive_url":null,"date":"2022-11-04T10:51:34","name":"[v6,2/7] x86: re-work insn/suffix recognition","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/07ef67fd-752c-ad1f-b8cb-4eaec1f420fc@suse.com/mbox/"},{"id":15467,"url":"https://patchwork.plctlab.org/api/1.2/patches/15467/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ee8fd655-19a5-d944-0f5e-4351b88a59f9@suse.com/","msgid":"","list_archive_url":null,"date":"2022-11-04T10:52:02","name":"[v6,3/7] ix86: don'\''t recognize/derive Q suffix in the common case","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ee8fd655-19a5-d944-0f5e-4351b88a59f9@suse.com/mbox/"},{"id":15468,"url":"https://patchwork.plctlab.org/api/1.2/patches/15468/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/15ab2cf5-f1ac-e882-c415-6318f1bcc7f0@suse.com/","msgid":"<15ab2cf5-f1ac-e882-c415-6318f1bcc7f0@suse.com>","list_archive_url":null,"date":"2022-11-04T10:52:31","name":"[v6,4/7] x86-64: allow HLE store of accumulator to absolute 32-bit address","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/15ab2cf5-f1ac-e882-c415-6318f1bcc7f0@suse.com/mbox/"},{"id":15470,"url":"https://patchwork.plctlab.org/api/1.2/patches/15470/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/352d1e49-ac9f-ee86-7e9d-74f79744268b@suse.com/","msgid":"<352d1e49-ac9f-ee86-7e9d-74f79744268b@suse.com>","list_archive_url":null,"date":"2022-11-04T10:53:14","name":"[v6,5/7] x86: move bad-use-of-TLS-reloc check","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/352d1e49-ac9f-ee86-7e9d-74f79744268b@suse.com/mbox/"},{"id":15469,"url":"https://patchwork.plctlab.org/api/1.2/patches/15469/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c1913bf6-7328-e45f-69f1-20da1954af43@suse.com/","msgid":"","list_archive_url":null,"date":"2022-11-04T10:53:52","name":"[v6,6/7] x86: drop (now) stray IsString","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c1913bf6-7328-e45f-69f1-20da1954af43@suse.com/mbox/"},{"id":15471,"url":"https://patchwork.plctlab.org/api/1.2/patches/15471/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2baf6a9d-c1bf-660d-bbca-99b1604f5478@suse.com/","msgid":"<2baf6a9d-c1bf-660d-bbca-99b1604f5478@suse.com>","list_archive_url":null,"date":"2022-11-04T10:54:30","name":"[v6,7/7] x86: further re-work insn/suffix recognition to also cover MOVSX","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2baf6a9d-c1bf-660d-bbca-99b1604f5478@suse.com/mbox/"},{"id":15472,"url":"https://patchwork.plctlab.org/api/1.2/patches/15472/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104110132.694984-1-aburgess@redhat.com/","msgid":"<20221104110132.694984-1-aburgess@redhat.com>","list_archive_url":null,"date":"2022-11-04T11:01:32","name":"[PUSHED] opcodes/arm: silence compiler warning about uninitialized variable use","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104110132.694984-1-aburgess@redhat.com/mbox/"},{"id":15473,"url":"https://patchwork.plctlab.org/api/1.2/patches/15473/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104110214.129095-1-christophe.lyon@arm.com/","msgid":"<20221104110214.129095-1-christophe.lyon@arm.com>","list_archive_url":null,"date":"2022-11-04T11:02:14","name":"configure: require libzstd >= 1.4.0","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104110214.129095-1-christophe.lyon@arm.com/mbox/"},{"id":15485,"url":"https://patchwork.plctlab.org/api/1.2/patches/15485/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104115038.8957-1-nelson@rivosinc.com/","msgid":"<20221104115038.8957-1-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-11-04T11:50:37","name":"[1/2] RISC-V: File-level architecture shouldn'\''t be affected by section-level ones.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104115038.8957-1-nelson@rivosinc.com/mbox/"},{"id":15486,"url":"https://patchwork.plctlab.org/api/1.2/patches/15486/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104115038.8957-2-nelson@rivosinc.com/","msgid":"<20221104115038.8957-2-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-11-04T11:50:38","name":"[2/2] RISC-V: Clarify the suppress rule of mapping symbol with architecture string.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104115038.8957-2-nelson@rivosinc.com/mbox/"},{"id":15509,"url":"https://patchwork.plctlab.org/api/1.2/patches/15509/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/cc133c88-9ce9-5e3a-a8f7-ad72766862b9@suse.com/","msgid":"","list_archive_url":null,"date":"2022-11-04T13:12:07","name":"x86: adjust recently introduced testcases","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/cc133c88-9ce9-5e3a-a8f7-ad72766862b9@suse.com/mbox/"},{"id":15679,"url":"https://patchwork.plctlab.org/api/1.2/patches/15679/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104163328.2274371-1-chigot@adacore.com/","msgid":"<20221104163328.2274371-1-chigot@adacore.com>","list_archive_url":null,"date":"2022-11-04T16:33:28","name":"ld/testsuite: skip tests related to -shared when disabled","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104163328.2274371-1-chigot@adacore.com/mbox/"},{"id":15751,"url":"https://patchwork.plctlab.org/api/1.2/patches/15751/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104190216.1352855-1-indu.bhagat@oracle.com/","msgid":"<20221104190216.1352855-1-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-04T19:02:16","name":"[V3.1,11/15] libctf: add libsframe to LDFLAGS and LIBS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104190216.1352855-1-indu.bhagat@oracle.com/mbox/"},{"id":15792,"url":"https://patchwork.plctlab.org/api/1.2/patches/15792/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104205547.3728827-1-hjl.tools@gmail.com/","msgid":"<20221104205547.3728827-1-hjl.tools@gmail.com>","list_archive_url":null,"date":"2022-11-04T20:55:47","name":"i386: Check invalid (%dx) usage","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104205547.3728827-1-hjl.tools@gmail.com/mbox/"},{"id":15794,"url":"https://patchwork.plctlab.org/api/1.2/patches/15794/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104210134.1721620-1-indu.bhagat@oracle.com/","msgid":"<20221104210134.1721620-1-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-04T21:01:34","name":"[V3.2,11/15] libctf: add libsframe to LDFLAGS and LIBS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104210134.1721620-1-indu.bhagat@oracle.com/mbox/"},{"id":15959,"url":"https://patchwork.plctlab.org/api/1.2/patches/15959/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c620070e3e335df2b487d3836e20d251dac37525.1667651354.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-11-05T12:29:07","name":"[01/12] RISC-V: Remove unnecessary empty matching file","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c620070e3e335df2b487d3836e20d251dac37525.1667651354.git.research_trasio@irq.a4lg.com/mbox/"},{"id":15961,"url":"https://patchwork.plctlab.org/api/1.2/patches/15961/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4496235002a396043598ab9755bd8eda5c077b1f.1667651354.git.research_trasio@irq.a4lg.com/","msgid":"<4496235002a396043598ab9755bd8eda5c077b1f.1667651354.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-05T12:29:08","name":"[02/12] RISC-V: Tidy disassembler corner case tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4496235002a396043598ab9755bd8eda5c077b1f.1667651354.git.research_trasio@irq.a4lg.com/mbox/"},{"id":15960,"url":"https://patchwork.plctlab.org/api/1.2/patches/15960/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a9229a2798480f00bf12ac3c435b3ef57f867022.1667651354.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-11-05T12:29:09","name":"[03/12] RISC-V: Tidying related to '\''Zfinx'\'' disassembler test","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a9229a2798480f00bf12ac3c435b3ef57f867022.1667651354.git.research_trasio@irq.a4lg.com/mbox/"},{"id":15962,"url":"https://patchwork.plctlab.org/api/1.2/patches/15962/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6a020edd0e114a003edbaafe1088a040e9fa07e7.1667651354.git.research_trasio@irq.a4lg.com/","msgid":"<6a020edd0e114a003edbaafe1088a040e9fa07e7.1667651354.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-05T12:29:10","name":"[04/12] RISC-V: GAS: Add basic shared test utilities","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6a020edd0e114a003edbaafe1088a040e9fa07e7.1667651354.git.research_trasio@irq.a4lg.com/mbox/"},{"id":15966,"url":"https://patchwork.plctlab.org/api/1.2/patches/15966/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6fc2851a4161edc429089bd2bbd9c2bb4c0c118f.1667651354.git.research_trasio@irq.a4lg.com/","msgid":"<6fc2851a4161edc429089bd2bbd9c2bb4c0c118f.1667651354.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-05T12:29:11","name":"[05/12] RISC-V: Redefine \"nop\" test","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6fc2851a4161edc429089bd2bbd9c2bb4c0c118f.1667651354.git.research_trasio@irq.a4lg.com/mbox/"},{"id":15963,"url":"https://patchwork.plctlab.org/api/1.2/patches/15963/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7311ed3d2429000e18877d7af594890da170a7a3.1667651354.git.research_trasio@irq.a4lg.com/","msgid":"<7311ed3d2429000e18877d7af594890da170a7a3.1667651354.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-05T12:29:12","name":"[06/12] RISC-V: Reorganize/enhance {sign, zero}-extension instructions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7311ed3d2429000e18877d7af594890da170a7a3.1667651354.git.research_trasio@irq.a4lg.com/mbox/"},{"id":15968,"url":"https://patchwork.plctlab.org/api/1.2/patches/15968/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ac99c9696c156207f06c18f2d6bf423c96c5876b.1667651354.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-11-05T12:29:13","name":"[07/12] RISC-V: Combine complex extension error handling tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ac99c9696c156207f06c18f2d6bf423c96c5876b.1667651354.git.research_trasio@irq.a4lg.com/mbox/"},{"id":15970,"url":"https://patchwork.plctlab.org/api/1.2/patches/15970/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9378b9505e3e230e0a690c56e67d253e2a0f5864.1667651354.git.research_trasio@irq.a4lg.com/","msgid":"<9378b9505e3e230e0a690c56e67d253e2a0f5864.1667651354.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-05T12:29:14","name":"[08/12] RISC-V: Refine/enhance '\''M'\''/'\''Zmmul'\'' extension tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9378b9505e3e230e0a690c56e67d253e2a0f5864.1667651354.git.research_trasio@irq.a4lg.com/mbox/"},{"id":15964,"url":"https://patchwork.plctlab.org/api/1.2/patches/15964/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/82832a67f240d5857fd502d4b74fd7d841ee2d6e.1667651354.git.research_trasio@irq.a4lg.com/","msgid":"<82832a67f240d5857fd502d4b74fd7d841ee2d6e.1667651354.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-05T12:29:15","name":"[09/12] RISC-V: Combine/enhance '\''Zicbo[mz]'\'' extension tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/82832a67f240d5857fd502d4b74fd7d841ee2d6e.1667651354.git.research_trasio@irq.a4lg.com/mbox/"},{"id":15965,"url":"https://patchwork.plctlab.org/api/1.2/patches/15965/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9c47e59868a64b13e5a7bb487e3619d4f1497d78.1667651354.git.research_trasio@irq.a4lg.com/","msgid":"<9c47e59868a64b13e5a7bb487e3619d4f1497d78.1667651354.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-05T12:29:16","name":"[10/12] RISC-V: Enhance '\''Zicbop'\'' testcases","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9c47e59868a64b13e5a7bb487e3619d4f1497d78.1667651354.git.research_trasio@irq.a4lg.com/mbox/"},{"id":15967,"url":"https://patchwork.plctlab.org/api/1.2/patches/15967/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2d9befc5bc5eed80b6bd7da6d092a61b1162ecac.1667651354.git.research_trasio@irq.a4lg.com/","msgid":"<2d9befc5bc5eed80b6bd7da6d092a61b1162ecac.1667651354.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-05T12:29:17","name":"[11/12] RISC-V: Reorganize/enhance '\''Zb*'\'' extension tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2d9befc5bc5eed80b6bd7da6d092a61b1162ecac.1667651354.git.research_trasio@irq.a4lg.com/mbox/"},{"id":15969,"url":"https://patchwork.plctlab.org/api/1.2/patches/15969/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f1c5589ab606b74eeac98e3dafd4a7903450d3b2.1667651354.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-11-05T12:29:18","name":"[12/12] RISC-V: Combine/enhance '\''Zk*'\''/'\''Zbk*'\'' extension tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f1c5589ab606b74eeac98e3dafd4a7903450d3b2.1667651354.git.research_trasio@irq.a4lg.com/mbox/"},{"id":16066,"url":"https://patchwork.plctlab.org/api/1.2/patches/16066/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221106053640.1649752-1-indu.bhagat@oracle.com/","msgid":"<20221106053640.1649752-1-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-06T05:36:40","name":"[V3.1,03/15] gas: generate .sframe from CFI directives","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221106053640.1649752-1-indu.bhagat@oracle.com/mbox/"},{"id":16379,"url":"https://patchwork.plctlab.org/api/1.2/patches/16379/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221107112805.3332619-1-och95@yandex.ru/","msgid":"<20221107112805.3332619-1-och95@yandex.ru>","list_archive_url":null,"date":"2022-11-07T11:28:05","name":"gold/aarch64: Fix adrp distance check","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221107112805.3332619-1-och95@yandex.ru/mbox/"},{"id":16400,"url":"https://patchwork.plctlab.org/api/1.2/patches/16400/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221107124620.1271470-1-christoph.muellner@vrull.eu/","msgid":"<20221107124620.1271470-1-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2022-11-07T12:46:20","name":"RISC-V: xtheadfmemidx: Use fp register in mnemonics","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221107124620.1271470-1-christoph.muellner@vrull.eu/mbox/"},{"id":16594,"url":"https://patchwork.plctlab.org/api/1.2/patches/16594/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/CACVBkZ+kM2xcpwk5zHQ4bqDV7dbPjZ6cMU9tR-h62+tDTgi3Tw@mail.gmail.com/","msgid":"","list_archive_url":null,"date":"2022-11-07T17:53:35","name":"GAS fix section alignment for aarch64-pe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/CACVBkZ+kM2xcpwk5zHQ4bqDV7dbPjZ6cMU9tR-h62+tDTgi3Tw@mail.gmail.com/mbox/"},{"id":16744,"url":"https://patchwork.plctlab.org/api/1.2/patches/16744/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221107222809.924195-1-indu.bhagat@oracle.com/","msgid":"<20221107222809.924195-1-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-07T22:28:09","name":"[V3.3,11/15] libctf: add libsframe to LDFLAGS and LIBS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221107222809.924195-1-indu.bhagat@oracle.com/mbox/"},{"id":16797,"url":"https://patchwork.plctlab.org/api/1.2/patches/16797/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221108012556.66467-1-haochen.jiang@intel.com/","msgid":"<20221108012556.66467-1-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-11-08T01:25:56","name":"x86: Correct wrong comments in vex_w_table","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221108012556.66467-1-haochen.jiang@intel.com/mbox/"},{"id":16884,"url":"https://patchwork.plctlab.org/api/1.2/patches/16884/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221108054530.796968-1-markus.t.metzger@intel.com/","msgid":"<20221108054530.796968-1-markus.t.metzger@intel.com>","list_archive_url":null,"date":"2022-11-08T05:45:29","name":"[1/2] gprofng: make cpu identification available to others","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221108054530.796968-1-markus.t.metzger@intel.com/mbox/"},{"id":16885,"url":"https://patchwork.plctlab.org/api/1.2/patches/16885/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221108054530.796968-2-markus.t.metzger@intel.com/","msgid":"<20221108054530.796968-2-markus.t.metzger@intel.com>","list_archive_url":null,"date":"2022-11-08T05:45:30","name":"[2/2] gdb, btrace: use cpuident.h to implement btrace_this_cpu","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221108054530.796968-2-markus.t.metzger@intel.com/mbox/"},{"id":16995,"url":"https://patchwork.plctlab.org/api/1.2/patches/16995/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ea0daf08-4923-ebfa-dcfe-699c43d63822@suse.com/","msgid":"","list_archive_url":null,"date":"2022-11-08T11:29:40","name":"x86/Intel: don'\''t accept malformed EXTRQ / INSERTQ","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ea0daf08-4923-ebfa-dcfe-699c43d63822@suse.com/mbox/"},{"id":17057,"url":"https://patchwork.plctlab.org/api/1.2/patches/17057/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221108141352.6613-1-jwilk@jwilk.net/","msgid":"<20221108141352.6613-1-jwilk@jwilk.net>","list_archive_url":null,"date":"2022-11-08T14:13:52","name":"Fix typos in the list of objdump options","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221108141352.6613-1-jwilk@jwilk.net/mbox/"},{"id":17117,"url":"https://patchwork.plctlab.org/api/1.2/patches/17117/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1667924955-9218-1-git-send-email-apinski@marvell.com/","msgid":"<1667924955-9218-1-git-send-email-apinski@marvell.com>","list_archive_url":null,"date":"2022-11-08T16:29:15","name":"Use toplevel configure for GMP and MPFR for gdb","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1667924955-9218-1-git-send-email-apinski@marvell.com/mbox/"},{"id":17160,"url":"https://patchwork.plctlab.org/api/1.2/patches/17160/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/27382086-397f-060f-6cf6-c1d36ff6b812@linux.ibm.com/","msgid":"<27382086-397f-060f-6cf6-c1d36ff6b812@linux.ibm.com>","list_archive_url":null,"date":"2022-11-08T18:23:32","name":"[COMMITTED] PowerPC: Add XSP operand define","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/27382086-397f-060f-6cf6-c1d36ff6b812@linux.ibm.com/mbox/"},{"id":17202,"url":"https://patchwork.plctlab.org/api/1.2/patches/17202/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221108192248.1622627-1-indu.bhagat@oracle.com/","msgid":"<20221108192248.1622627-1-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-08T19:22:48","name":"libctf: use libtool for link test in configure","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221108192248.1622627-1-indu.bhagat@oracle.com/mbox/"},{"id":17262,"url":"https://patchwork.plctlab.org/api/1.2/patches/17262/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221108225030.371817-1-hjl.tools@gmail.com/","msgid":"<20221108225030.371817-1-hjl.tools@gmail.com>","list_archive_url":null,"date":"2022-11-08T22:50:30","name":"ld: Always output local symbol for relocatable link","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221108225030.371817-1-hjl.tools@gmail.com/mbox/"},{"id":17399,"url":"https://patchwork.plctlab.org/api/1.2/patches/17399/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-2-indu.bhagat@oracle.com/","msgid":"<20221109084244.261296-2-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-09T08:42:34","name":"[V4,01/11] sframe.h: Add SFrame format definition","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-2-indu.bhagat@oracle.com/mbox/"},{"id":17398,"url":"https://patchwork.plctlab.org/api/1.2/patches/17398/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-3-indu.bhagat@oracle.com/","msgid":"<20221109084244.261296-3-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-09T08:42:35","name":"[V4,02/11] gas: add new command line option --gsframe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-3-indu.bhagat@oracle.com/mbox/"},{"id":17400,"url":"https://patchwork.plctlab.org/api/1.2/patches/17400/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-4-indu.bhagat@oracle.com/","msgid":"<20221109084244.261296-4-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-09T08:42:36","name":"[V4,03/11] gas: generate .sframe from CFI directives","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-4-indu.bhagat@oracle.com/mbox/"},{"id":17403,"url":"https://patchwork.plctlab.org/api/1.2/patches/17403/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-5-indu.bhagat@oracle.com/","msgid":"<20221109084244.261296-5-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-09T08:42:37","name":"[V4,04/11] gas: testsuite: add new tests for SFrame unwind info","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-5-indu.bhagat@oracle.com/mbox/"},{"id":17407,"url":"https://patchwork.plctlab.org/api/1.2/patches/17407/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-6-indu.bhagat@oracle.com/","msgid":"<20221109084244.261296-6-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-09T08:42:38","name":"[V4,05/11] libsframe: add the SFrame library","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-6-indu.bhagat@oracle.com/mbox/"},{"id":17406,"url":"https://patchwork.plctlab.org/api/1.2/patches/17406/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-7-indu.bhagat@oracle.com/","msgid":"<20221109084244.261296-7-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-09T08:42:39","name":"[V4,06/11] bfd: linker: merge .sframe sections","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-7-indu.bhagat@oracle.com/mbox/"},{"id":17402,"url":"https://patchwork.plctlab.org/api/1.2/patches/17402/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-8-indu.bhagat@oracle.com/","msgid":"<20221109084244.261296-8-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-09T08:42:40","name":"[V4,07/11] readelf/objdump: support for SFrame section","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-8-indu.bhagat@oracle.com/mbox/"},{"id":17401,"url":"https://patchwork.plctlab.org/api/1.2/patches/17401/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-9-indu.bhagat@oracle.com/","msgid":"<20221109084244.261296-9-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-09T08:42:41","name":"[V4,08/11] src-release.sh: Add libsframe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-9-indu.bhagat@oracle.com/mbox/"},{"id":17404,"url":"https://patchwork.plctlab.org/api/1.2/patches/17404/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-10-indu.bhagat@oracle.com/","msgid":"<20221109084244.261296-10-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-09T08:42:42","name":"[V4,09/11] binutils/NEWS: add text for SFrame support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-10-indu.bhagat@oracle.com/mbox/"},{"id":17405,"url":"https://patchwork.plctlab.org/api/1.2/patches/17405/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-11-indu.bhagat@oracle.com/","msgid":"<20221109084244.261296-11-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-09T08:42:43","name":"[V4,10/11] gas/NEWS: add text about new command line option and SFrame support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-11-indu.bhagat@oracle.com/mbox/"},{"id":17418,"url":"https://patchwork.plctlab.org/api/1.2/patches/17418/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-12-indu.bhagat@oracle.com/","msgid":"<20221109084244.261296-12-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-09T08:42:44","name":"[V4,11/11] doc: add SFrame spec file","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-12-indu.bhagat@oracle.com/mbox/"},{"id":17662,"url":"https://patchwork.plctlab.org/api/1.2/patches/17662/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109162611.760465-1-chigot@adacore.com/","msgid":"<20221109162611.760465-1-chigot@adacore.com>","list_archive_url":null,"date":"2022-11-09T16:26:11","name":"ld/testsuite: skip ld-size when -shared is not supported","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109162611.760465-1-chigot@adacore.com/mbox/"},{"id":17804,"url":"https://patchwork.plctlab.org/api/1.2/patches/17804/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109202129.475283-1-hjl.tools@gmail.com/","msgid":"<20221109202129.475283-1-hjl.tools@gmail.com>","list_archive_url":null,"date":"2022-11-09T20:21:29","name":"[v2] i386: Check invalid (%dx) usage","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109202129.475283-1-hjl.tools@gmail.com/mbox/"},{"id":18043,"url":"https://patchwork.plctlab.org/api/1.2/patches/18043/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y2zOaxv1jkhwTIAi@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-11-10T10:11:55","name":"Sanity check reloc count in get_reloc_upper_bound","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y2zOaxv1jkhwTIAi@squeak.grove.modra.org/mbox/"},{"id":18044,"url":"https://patchwork.plctlab.org/api/1.2/patches/18044/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y2zOkpGuKAn+V2Tk@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-11-10T10:12:34","name":"mach-o reloc size overflow","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y2zOkpGuKAn+V2Tk@squeak.grove.modra.org/mbox/"},{"id":18045,"url":"https://patchwork.plctlab.org/api/1.2/patches/18045/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fddbca08-756a-4d78-b117-3e82dc40df8d@AZ-NEU-EX04.Arm.com/","msgid":"","list_archive_url":null,"date":"2022-11-10T10:17:38","name":"[BINTUILS] arm: Add support for Cortex-X1C CPU.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fddbca08-756a-4d78-b117-3e82dc40df8d@AZ-NEU-EX04.Arm.com/mbox/"},{"id":18051,"url":"https://patchwork.plctlab.org/api/1.2/patches/18051/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1518b510-2124-cbcb-9dcb-059dcfdc6cd4@suse.com/","msgid":"<1518b510-2124-cbcb-9dcb-059dcfdc6cd4@suse.com>","list_archive_url":null,"date":"2022-11-10T10:24:31","name":"x86: drop stray IsString from PadLock insns","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1518b510-2124-cbcb-9dcb-059dcfdc6cd4@suse.com/mbox/"},{"id":18088,"url":"https://patchwork.plctlab.org/api/1.2/patches/18088/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/25e8786d-289e-0521-baa2-2f2b85124dfe@suse.com/","msgid":"<25e8786d-289e-0521-baa2-2f2b85124dfe@suse.com>","list_archive_url":null,"date":"2022-11-10T12:12:46","name":"[v2] x86: drop stray IsString from PadLock insns","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/25e8786d-289e-0521-baa2-2f2b85124dfe@suse.com/mbox/"},{"id":18130,"url":"https://patchwork.plctlab.org/api/1.2/patches/18130/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9bb8ebe7-9e49-d60b-d586-e4d98242acda@suse.com/","msgid":"<9bb8ebe7-9e49-d60b-d586-e4d98242acda@suse.com>","list_archive_url":null,"date":"2022-11-10T13:36:16","name":"x86: drop duplicate sse4a entry from cpu_arch[]","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9bb8ebe7-9e49-d60b-d586-e4d98242acda@suse.com/mbox/"},{"id":18135,"url":"https://patchwork.plctlab.org/api/1.2/patches/18135/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/21665493-a9f9-3429-c9ae-ea69bc7751e2@suse.com/","msgid":"<21665493-a9f9-3429-c9ae-ea69bc7751e2@suse.com>","list_archive_url":null,"date":"2022-11-10T13:45:30","name":"x86: fold special-operand insn attributes into a single enum","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/21665493-a9f9-3429-c9ae-ea69bc7751e2@suse.com/mbox/"},{"id":18284,"url":"https://patchwork.plctlab.org/api/1.2/patches/18284/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1668107159-16961-1-git-send-email-apinski@marvell.com/","msgid":"<1668107159-16961-1-git-send-email-apinski@marvell.com>","list_archive_url":null,"date":"2022-11-10T19:05:59","name":"[PATCHv2] Use toplevel configure for GMP and MPFR for gdb","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1668107159-16961-1-git-send-email-apinski@marvell.com/mbox/"},{"id":18337,"url":"https://patchwork.plctlab.org/api/1.2/patches/18337/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221110224002.3798725-1-vladimir.mezentsev@oracle.com/","msgid":"<20221110224002.3798725-1-vladimir.mezentsev@oracle.com>","list_archive_url":null,"date":"2022-11-10T22:40:02","name":"gprofng: fix typo in configure.ac","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221110224002.3798725-1-vladimir.mezentsev@oracle.com/mbox/"},{"id":18424,"url":"https://patchwork.plctlab.org/api/1.2/patches/18424/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221111033040.23115-1-mark@harmstone.com/","msgid":"<20221111033040.23115-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-11-11T03:30:40","name":"ld: Add section contributions substream to PDB files","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221111033040.23115-1-mark@harmstone.com/mbox/"},{"id":18513,"url":"https://patchwork.plctlab.org/api/1.2/patches/18513/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/40e89395-1438-6cbe-aa37-1a04a724c8c7@suse.com/","msgid":"<40e89395-1438-6cbe-aa37-1a04a724c8c7@suse.com>","list_archive_url":null,"date":"2022-11-11T07:32:17","name":"gas: accept custom \".linefile .\"","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/40e89395-1438-6cbe-aa37-1a04a724c8c7@suse.com/mbox/"},{"id":18517,"url":"https://patchwork.plctlab.org/api/1.2/patches/18517/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y23642YK4HTWnn3X@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-11-11T07:33:55","name":"Sanity check SHT_MIPS_OPTIONS size","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y23642YK4HTWnn3X@squeak.grove.modra.org/mbox/"},{"id":18519,"url":"https://patchwork.plctlab.org/api/1.2/patches/18519/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y237HYVYLWv1R4b/@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-11-11T07:34:53","name":"PR28834, PR26946 sanity checking section size","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y237HYVYLWv1R4b/@squeak.grove.modra.org/mbox/"},{"id":18670,"url":"https://patchwork.plctlab.org/api/1.2/patches/18670/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c5ab35f0-595a-439c-b120-f93bd109ab96@AZ-NEU-EX04.Arm.com/","msgid":"","list_archive_url":null,"date":"2022-11-11T10:51:43","name":"[Binutils,gas] arm: Add support for new unwinder directive \".pacspval\".","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c5ab35f0-595a-439c-b120-f93bd109ab96@AZ-NEU-EX04.Arm.com/mbox/"},{"id":18672,"url":"https://patchwork.plctlab.org/api/1.2/patches/18672/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/33eb9aff-d813-44c5-8315-aeb3e339b3f2@AZ-NEU-EX04.Arm.com/","msgid":"<33eb9aff-d813-44c5-8315-aeb3e339b3f2@AZ-NEU-EX04.Arm.com>","list_archive_url":null,"date":"2022-11-11T10:53:55","name":"[Binutils,readelf] arm: Support for new pacbti unwind opcode 0xb5.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/33eb9aff-d813-44c5-8315-aeb3e339b3f2@AZ-NEU-EX04.Arm.com/mbox/"},{"id":19116,"url":"https://patchwork.plctlab.org/api/1.2/patches/19116/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y29EZ/ykU1Qe6AAw@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-11-12T06:59:51","name":"PowerPC64 paddi -Mraw","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y29EZ/ykU1Qe6AAw@squeak.grove.modra.org/mbox/"},{"id":19138,"url":"https://patchwork.plctlab.org/api/1.2/patches/19138/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221112091217.558020-1-dimitar@dinux.eu/","msgid":"<20221112091217.558020-1-dimitar@dinux.eu>","list_archive_url":null,"date":"2022-11-12T09:12:17","name":"pru: bfd: Correct default to no execstack","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221112091217.558020-1-dimitar@dinux.eu/mbox/"},{"id":19173,"url":"https://patchwork.plctlab.org/api/1.2/patches/19173/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221112124441.5084-1-patrick@monnerat.net/","msgid":"<20221112124441.5084-1-patrick@monnerat.net>","list_archive_url":null,"date":"2022-11-12T12:44:41","name":"binutils/objcopy: keep relocation while renaming a section with explicit flags","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221112124441.5084-1-patrick@monnerat.net/mbox/"},{"id":19377,"url":"https://patchwork.plctlab.org/api/1.2/patches/19377/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221113155921.1445808-1-christoph.muellner@vrull.eu/","msgid":"<20221113155921.1445808-1-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2022-11-13T15:59:20","name":"[1/2] RISC-V: Add T-Head Fmv vendor extension","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221113155921.1445808-1-christoph.muellner@vrull.eu/mbox/"},{"id":19378,"url":"https://patchwork.plctlab.org/api/1.2/patches/19378/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221113155921.1445808-2-christoph.muellner@vrull.eu/","msgid":"<20221113155921.1445808-2-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2022-11-13T15:59:21","name":"[2/2] RISC-V: Add T-Head Int vendor extension","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221113155921.1445808-2-christoph.muellner@vrull.eu/mbox/"},{"id":19850,"url":"https://patchwork.plctlab.org/api/1.2/patches/19850/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221114150348.112815-1-bwerl.dev@gmail.com/","msgid":"<20221114150348.112815-1-bwerl.dev@gmail.com>","list_archive_url":null,"date":"2022-11-14T15:03:48","name":"readelf: use fseeko for elf files >= 2 GiB on x86_64-mingw32","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221114150348.112815-1-bwerl.dev@gmail.com/mbox/"},{"id":19866,"url":"https://patchwork.plctlab.org/api/1.2/patches/19866/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3dd1c6f9-a773-c05f-44d7-12b7947072d2@suse.com/","msgid":"<3dd1c6f9-a773-c05f-44d7-12b7947072d2@suse.com>","list_archive_url":null,"date":"2022-11-14T16:12:26","name":"x86: infer No_*Suf from other insn attributes","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3dd1c6f9-a773-c05f-44d7-12b7947072d2@suse.com/mbox/"},{"id":19934,"url":"https://patchwork.plctlab.org/api/1.2/patches/19934/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f659dfbb-b84b-af86-bd8c-d177900af779@linaro.org/","msgid":"","list_archive_url":null,"date":"2022-11-14T17:24:23","name":"[V2] GAS fix alignment for aarch64-pe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f659dfbb-b84b-af86-bd8c-d177900af779@linaro.org/mbox/"},{"id":20111,"url":"https://patchwork.plctlab.org/api/1.2/patches/20111/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221115010409.24214-1-mark@harmstone.com/","msgid":"<20221115010409.24214-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-11-15T01:04:09","name":"gas: Add --gcodeview option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221115010409.24214-1-mark@harmstone.com/mbox/"},{"id":20174,"url":"https://patchwork.plctlab.org/api/1.2/patches/20174/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d305cd6178975195b025828561d59e505524ea45.1668486687.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-11-15T04:31:22","name":"[v3,1/8] RISC-V: Add a space at the end of pinfo","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d305cd6178975195b025828561d59e505524ea45.1668486687.git.research_trasio@irq.a4lg.com/mbox/"},{"id":20177,"url":"https://patchwork.plctlab.org/api/1.2/patches/20177/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2627dd5e18e59b6d976a8e6f1be39336e8a12cc3.1668486687.git.research_trasio@irq.a4lg.com/","msgid":"<2627dd5e18e59b6d976a8e6f1be39336e8a12cc3.1668486687.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-15T04:31:23","name":"[v3,2/8] RISC-V: Fix obvious misalignments ('\''Zbb'\''/'\''Zba'\'')","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2627dd5e18e59b6d976a8e6f1be39336e8a12cc3.1668486687.git.research_trasio@irq.a4lg.com/mbox/"},{"id":20173,"url":"https://patchwork.plctlab.org/api/1.2/patches/20173/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9d110279505cf502900a000a07e6e82b50f12adc.1668486687.git.research_trasio@irq.a4lg.com/","msgid":"<9d110279505cf502900a000a07e6e82b50f12adc.1668486687.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-15T04:31:24","name":"[v3,3/8] RISC-V: Remove spaces in opcode entries","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9d110279505cf502900a000a07e6e82b50f12adc.1668486687.git.research_trasio@irq.a4lg.com/mbox/"},{"id":20179,"url":"https://patchwork.plctlab.org/api/1.2/patches/20179/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8f77aa968ed9457ce1bce0a1f6449a287d0e6a18.1668486687.git.research_trasio@irq.a4lg.com/","msgid":"<8f77aa968ed9457ce1bce0a1f6449a287d0e6a18.1668486687.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-15T04:31:25","name":"[v3,4/8] RISC-V: Remove unused instruction macros","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8f77aa968ed9457ce1bce0a1f6449a287d0e6a18.1668486687.git.research_trasio@irq.a4lg.com/mbox/"},{"id":20176,"url":"https://patchwork.plctlab.org/api/1.2/patches/20176/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b43454773d597c1bc51741ef09aac960fecdfbd5.1668486687.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-11-15T04:31:26","name":"[v3,5/8] RISC-V: Complete tidying up with SCALL and SBREAK","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b43454773d597c1bc51741ef09aac960fecdfbd5.1668486687.git.research_trasio@irq.a4lg.com/mbox/"},{"id":20178,"url":"https://patchwork.plctlab.org/api/1.2/patches/20178/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/58cfec431ff2535aeb0c3fd9213933cf28864cb9.1668486687.git.research_trasio@irq.a4lg.com/","msgid":"<58cfec431ff2535aeb0c3fd9213933cf28864cb9.1668486687.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-15T04:31:27","name":"[v3,6/8] RISC-V: Tidying up with fmv.w.x and fmv.x.w","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/58cfec431ff2535aeb0c3fd9213933cf28864cb9.1668486687.git.research_trasio@irq.a4lg.com/mbox/"},{"id":20180,"url":"https://patchwork.plctlab.org/api/1.2/patches/20180/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/192f62be797f7c46a03acadb7d1bcdb83a7e9d6e.1668486687.git.research_trasio@irq.a4lg.com/","msgid":"<192f62be797f7c46a03acadb7d1bcdb83a7e9d6e.1668486687.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-15T04:31:28","name":"[v3,7/8] RISC-V: Make alias instructions aliases","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/192f62be797f7c46a03acadb7d1bcdb83a7e9d6e.1668486687.git.research_trasio@irq.a4lg.com/mbox/"},{"id":20175,"url":"https://patchwork.plctlab.org/api/1.2/patches/20175/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c89919c84067e1c2105b1857937df6405aec70fa.1668486687.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-11-15T04:31:29","name":"[v3,8/8] RISC-V: Use defined mask and match values","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c89919c84067e1c2105b1857937df6405aec70fa.1668486687.git.research_trasio@irq.a4lg.com/mbox/"},{"id":20185,"url":"https://patchwork.plctlab.org/api/1.2/patches/20185/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ebc1e98ae09f2c209ebaed2b81d5b418ce2c5128.1668487922.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-11-15T04:52:44","name":"[01/11] opcodes/riscv-dis.c: More tidying","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ebc1e98ae09f2c209ebaed2b81d5b418ce2c5128.1668487922.git.research_trasio@irq.a4lg.com/mbox/"},{"id":20188,"url":"https://patchwork.plctlab.org/api/1.2/patches/20188/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9795298f970f0b8a02796edc2c4249417614103b.1668487922.git.research_trasio@irq.a4lg.com/","msgid":"<9795298f970f0b8a02796edc2c4249417614103b.1668487922.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-15T04:52:45","name":"[02/11] RISC-V: Add test for '\''Zfinx'\'' register switching","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9795298f970f0b8a02796edc2c4249417614103b.1668487922.git.research_trasio@irq.a4lg.com/mbox/"},{"id":20186,"url":"https://patchwork.plctlab.org/api/1.2/patches/20186/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6c6c644515c6bc2751062543097eb14ee98e97c8.1668487922.git.research_trasio@irq.a4lg.com/","msgid":"<6c6c644515c6bc2751062543097eb14ee98e97c8.1668487922.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-15T04:52:46","name":"[03/11] RISC-V: Make mapping symbol checking consistent","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6c6c644515c6bc2751062543097eb14ee98e97c8.1668487922.git.research_trasio@irq.a4lg.com/mbox/"},{"id":20187,"url":"https://patchwork.plctlab.org/api/1.2/patches/20187/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b5b5ce7e34544c7934b775062413e0fe07dcd6e6.1668487922.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-11-15T04:52:47","name":"[04/11] RISC-V: Split riscv_get_map_state into two steps","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b5b5ce7e34544c7934b775062413e0fe07dcd6e6.1668487922.git.research_trasio@irq.a4lg.com/mbox/"},{"id":20192,"url":"https://patchwork.plctlab.org/api/1.2/patches/20192/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c143088cbaf7a19a992e008689420d95a90f3fab.1668487922.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-11-15T04:52:48","name":"[05/11] RISC-V: One time CSR hash table initialization","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c143088cbaf7a19a992e008689420d95a90f3fab.1668487922.git.research_trasio@irq.a4lg.com/mbox/"},{"id":20193,"url":"https://patchwork.plctlab.org/api/1.2/patches/20193/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9734125736efc8b63be17df87d38cf24bb14a156.1668487922.git.research_trasio@irq.a4lg.com/","msgid":"<9734125736efc8b63be17df87d38cf24bb14a156.1668487922.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-15T04:52:49","name":"[06/11] RISC-V: Use static xlen on ADDIW sequence","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9734125736efc8b63be17df87d38cf24bb14a156.1668487922.git.research_trasio@irq.a4lg.com/mbox/"},{"id":20191,"url":"https://patchwork.plctlab.org/api/1.2/patches/20191/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/34dbd0c82de0af284887a3bff649c8c53d67e752.1668487922.git.research_trasio@irq.a4lg.com/","msgid":"<34dbd0c82de0af284887a3bff649c8c53d67e752.1668487922.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-15T04:52:50","name":"[07/11] opcodes/riscv-dis.c: Add form feed for separation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/34dbd0c82de0af284887a3bff649c8c53d67e752.1668487922.git.research_trasio@irq.a4lg.com/mbox/"},{"id":20190,"url":"https://patchwork.plctlab.org/api/1.2/patches/20190/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1352fb8c63539727204df94651f371ed09bbce4c.1668487922.git.research_trasio@irq.a4lg.com/","msgid":"<1352fb8c63539727204df94651f371ed09bbce4c.1668487922.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-15T04:52:51","name":"[08/11] RISC-V: Split match/print steps on disassembler","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1352fb8c63539727204df94651f371ed09bbce4c.1668487922.git.research_trasio@irq.a4lg.com/mbox/"},{"id":20189,"url":"https://patchwork.plctlab.org/api/1.2/patches/20189/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/12cd8820841f695708875206b6461b6322c74428.1668487922.git.research_trasio@irq.a4lg.com/","msgid":"<12cd8820841f695708875206b6461b6322c74428.1668487922.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-15T04:52:52","name":"[09/11] RISC-V: Reorganize disassembler state initialization","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/12cd8820841f695708875206b6461b6322c74428.1668487922.git.research_trasio@irq.a4lg.com/mbox/"},{"id":20194,"url":"https://patchwork.plctlab.org/api/1.2/patches/20194/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6aade17e12ce2a928d044d9f148c874cf9922da8.1668487922.git.research_trasio@irq.a4lg.com/","msgid":"<6aade17e12ce2a928d044d9f148c874cf9922da8.1668487922.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-15T04:52:53","name":"[10/11] RISC-V: Reorganize arch-related initialization and management","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6aade17e12ce2a928d044d9f148c874cf9922da8.1668487922.git.research_trasio@irq.a4lg.com/mbox/"},{"id":20195,"url":"https://patchwork.plctlab.org/api/1.2/patches/20195/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a239fb0682bd24d4f1eb3014685eed78f9ea779a.1668487922.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-11-15T04:52:54","name":"[11/11] RISC-V: Move disassembler private data initialization","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a239fb0682bd24d4f1eb3014685eed78f9ea779a.1668487922.git.research_trasio@irq.a4lg.com/mbox/"},{"id":20236,"url":"https://patchwork.plctlab.org/api/1.2/patches/20236/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221115081455.2354987-2-zengxiao@eswincomputing.com/","msgid":"<20221115081455.2354987-2-zengxiao@eswincomputing.com>","list_archive_url":null,"date":"2022-11-15T08:14:55","name":"[v1,1/1] RISC-V: Make R_RISCV_SUB6 conforms to riscv abi standard","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221115081455.2354987-2-zengxiao@eswincomputing.com/mbox/"},{"id":20422,"url":"https://patchwork.plctlab.org/api/1.2/patches/20422/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221115145717.64948-1-bwerl.dev@gmail.com/","msgid":"<20221115145717.64948-1-bwerl.dev@gmail.com>","list_archive_url":null,"date":"2022-11-15T14:57:17","name":"readelf: use fseeko64 or fseeko if possible","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221115145717.64948-1-bwerl.dev@gmail.com/mbox/"},{"id":20600,"url":"https://patchwork.plctlab.org/api/1.2/patches/20600/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y3QKUwDn748CbDIs@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-11-15T21:53:23","name":"aarch64-pe can'\''t fill 16 bytes in section .text","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y3QKUwDn748CbDIs@squeak.grove.modra.org/mbox/"},{"id":20720,"url":"https://patchwork.plctlab.org/api/1.2/patches/20720/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221116053326.1337432-1-vladimir.mezentsev@oracle.com/","msgid":"<20221116053326.1337432-1-vladimir.mezentsev@oracle.com>","list_archive_url":null,"date":"2022-11-16T05:33:26","name":"PR29788, gprofng cannot display Java'\''s generated assembly code","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221116053326.1337432-1-vladimir.mezentsev@oracle.com/mbox/"},{"id":21321,"url":"https://patchwork.plctlab.org/api/1.2/patches/21321/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221116232039.1793148-1-hjl.tools@gmail.com/","msgid":"<20221116232039.1793148-1-hjl.tools@gmail.com>","list_archive_url":null,"date":"2022-11-16T23:20:39","name":"ld: Always call elf_backend_output_arch_local_syms","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221116232039.1793148-1-hjl.tools@gmail.com/mbox/"},{"id":21322,"url":"https://patchwork.plctlab.org/api/1.2/patches/21322/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221116232132.1009459-1-indu.bhagat@oracle.com/","msgid":"<20221116232132.1009459-1-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-16T23:21:32","name":"[gas,aarch64] : fix build breakage for aarch64-pe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221116232132.1009459-1-indu.bhagat@oracle.com/mbox/"},{"id":21449,"url":"https://patchwork.plctlab.org/api/1.2/patches/21449/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221117060234.1771025-1-indu.bhagat@oracle.com/","msgid":"<20221117060234.1771025-1-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-17T06:02:34","name":"[V2,gas,aarch64] : fix build breakage for aarch64-pe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221117060234.1771025-1-indu.bhagat@oracle.com/mbox/"},{"id":21662,"url":"https://patchwork.plctlab.org/api/1.2/patches/21662/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a050b8da-b978-d443-eee0-32b5a7836bb4@suse.com/","msgid":"","list_archive_url":null,"date":"2022-11-17T13:29:02","name":"[1/2] x86: instantiate i386_{op, reg}tab[] in gas instead of in libopcodes","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a050b8da-b978-d443-eee0-32b5a7836bb4@suse.com/mbox/"},{"id":21663,"url":"https://patchwork.plctlab.org/api/1.2/patches/21663/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d9b5137b-3bc0-8496-4533-03402ac00628@suse.com/","msgid":"","list_archive_url":null,"date":"2022-11-17T13:29:36","name":"[2/2] x86: break gas dependency on libopcodes","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d9b5137b-3bc0-8496-4533-03402ac00628@suse.com/mbox/"},{"id":21682,"url":"https://patchwork.plctlab.org/api/1.2/patches/21682/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221117143419.19571-1-bwerl.dev@gmail.com/","msgid":"<20221117143419.19571-1-bwerl.dev@gmail.com>","list_archive_url":null,"date":"2022-11-17T14:34:19","name":"readelf: use fseeko64 or fseeko if possible","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221117143419.19571-1-bwerl.dev@gmail.com/mbox/"},{"id":21850,"url":"https://patchwork.plctlab.org/api/1.2/patches/21850/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221117170546.1941945-1-hjl.tools@gmail.com/","msgid":"<20221117170546.1941945-1-hjl.tools@gmail.com>","list_archive_url":null,"date":"2022-11-17T17:05:46","name":"i386: Move i386_seg_prefixes to gas","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221117170546.1941945-1-hjl.tools@gmail.com/mbox/"},{"id":21858,"url":"https://patchwork.plctlab.org/api/1.2/patches/21858/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/CAPOVtOvi0D-u7MKAuO97-q241JZFojD8xppn3GdF2kH57iT+TA@mail.gmail.com/","msgid":"","list_archive_url":null,"date":"2022-11-17T17:44:00","name":"binutils: partially revert 17c6c3b99156fe82c1e637e1a5fd9f163ac788c8","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/CAPOVtOvi0D-u7MKAuO97-q241JZFojD8xppn3GdF2kH57iT+TA@mail.gmail.com/mbox/"},{"id":21992,"url":"https://patchwork.plctlab.org/api/1.2/patches/21992/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221118003212.3628771-1-christoph.muellner@vrull.eu/","msgid":"<20221118003212.3628771-1-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2022-11-18T00:32:12","name":"riscv: Add AIA extension support (Smaia, Ssaia)","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221118003212.3628771-1-christoph.muellner@vrull.eu/mbox/"},{"id":22004,"url":"https://patchwork.plctlab.org/api/1.2/patches/22004/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y3bZt50nhFXkf2WU@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-11-18T01:02:47","name":"go32 sanity check","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y3bZt50nhFXkf2WU@squeak.grove.modra.org/mbox/"},{"id":22005,"url":"https://patchwork.plctlab.org/api/1.2/patches/22005/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y3bZ0x42eeZFSqXt@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-11-18T01:03:15","name":"PR29799 heap buffer overflow in display_gdb_index dwarf.c:10548","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y3bZ0x42eeZFSqXt@squeak.grove.modra.org/mbox/"},{"id":22050,"url":"https://patchwork.plctlab.org/api/1.2/patches/22050/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4c45925619ab51261ca87d309883c9aa7cd05240.1668736896.git.research_trasio@irq.a4lg.com/","msgid":"<4c45925619ab51261ca87d309883c9aa7cd05240.1668736896.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-18T02:02:21","name":"RISC-V: Add INSN_DREF to memory read/write instructions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4c45925619ab51261ca87d309883c9aa7cd05240.1668736896.git.research_trasio@irq.a4lg.com/mbox/"},{"id":22053,"url":"https://patchwork.plctlab.org/api/1.2/patches/22053/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/13809b68ae60e912f3cb8e9bedd8eedf3899b547.1668737241.git.research_trasio@irq.a4lg.com/","msgid":"<13809b68ae60e912f3cb8e9bedd8eedf3899b547.1668737241.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-18T02:07:48","name":"[v4,1/8] RISC-V: Add a space at the end of pinfo","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/13809b68ae60e912f3cb8e9bedd8eedf3899b547.1668737241.git.research_trasio@irq.a4lg.com/mbox/"},{"id":22051,"url":"https://patchwork.plctlab.org/api/1.2/patches/22051/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9abf4696a17c5407a75d87b3c200fb9958ff227e.1668737241.git.research_trasio@irq.a4lg.com/","msgid":"<9abf4696a17c5407a75d87b3c200fb9958ff227e.1668737241.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-18T02:07:49","name":"[v4,2/8] RISC-V: Fix obvious misalignments ('\''Zbb'\''/'\''Zba'\'')","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9abf4696a17c5407a75d87b3c200fb9958ff227e.1668737241.git.research_trasio@irq.a4lg.com/mbox/"},{"id":22052,"url":"https://patchwork.plctlab.org/api/1.2/patches/22052/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/80185b54704af681ba81c6f84b6ce099cc3b5970.1668737241.git.research_trasio@irq.a4lg.com/","msgid":"<80185b54704af681ba81c6f84b6ce099cc3b5970.1668737241.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-18T02:07:50","name":"[v4,3/8] RISC-V: Remove spaces in opcode entries","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/80185b54704af681ba81c6f84b6ce099cc3b5970.1668737241.git.research_trasio@irq.a4lg.com/mbox/"},{"id":22055,"url":"https://patchwork.plctlab.org/api/1.2/patches/22055/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5d675a4132e2f6160d3294563e16f5093b5b1e20.1668737241.git.research_trasio@irq.a4lg.com/","msgid":"<5d675a4132e2f6160d3294563e16f5093b5b1e20.1668737241.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-18T02:07:51","name":"[v4,4/8] RISC-V: Remove unused instruction macros","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5d675a4132e2f6160d3294563e16f5093b5b1e20.1668737241.git.research_trasio@irq.a4lg.com/mbox/"},{"id":22056,"url":"https://patchwork.plctlab.org/api/1.2/patches/22056/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/27a4301cbae3d6788c878924f55aa9a6ae910669.1668737241.git.research_trasio@irq.a4lg.com/","msgid":"<27a4301cbae3d6788c878924f55aa9a6ae910669.1668737241.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-18T02:07:52","name":"[v4,5/8] RISC-V: Complete tidying up with SCALL and SBREAK","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/27a4301cbae3d6788c878924f55aa9a6ae910669.1668737241.git.research_trasio@irq.a4lg.com/mbox/"},{"id":22058,"url":"https://patchwork.plctlab.org/api/1.2/patches/22058/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7f0ea4bf1af541504b72791b5217253b2450071c.1668737241.git.research_trasio@irq.a4lg.com/","msgid":"<7f0ea4bf1af541504b72791b5217253b2450071c.1668737241.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-18T02:07:53","name":"[v4,6/8] RISC-V: Tidying up with fmv.w.x and fmv.x.w","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7f0ea4bf1af541504b72791b5217253b2450071c.1668737241.git.research_trasio@irq.a4lg.com/mbox/"},{"id":22057,"url":"https://patchwork.plctlab.org/api/1.2/patches/22057/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e5d45f2c8d1bb5b2d9adbfa117a3fc7d32afd6c9.1668737241.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-11-18T02:07:54","name":"[v4,7/8] RISC-V: Make alias instructions aliases","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e5d45f2c8d1bb5b2d9adbfa117a3fc7d32afd6c9.1668737241.git.research_trasio@irq.a4lg.com/mbox/"},{"id":22054,"url":"https://patchwork.plctlab.org/api/1.2/patches/22054/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3c1e28e61eb0275d0fd02a7d9ff956cc4f589104.1668737241.git.research_trasio@irq.a4lg.com/","msgid":"<3c1e28e61eb0275d0fd02a7d9ff956cc4f589104.1668737241.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-18T02:07:55","name":"[v4,8/8] RISC-V: Use defined mask and match values","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3c1e28e61eb0275d0fd02a7d9ff956cc4f589104.1668737241.git.research_trasio@irq.a4lg.com/mbox/"},{"id":22215,"url":"https://patchwork.plctlab.org/api/1.2/patches/22215/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/028280ab-56ad-2380-6bdd-3c944695ec5f@suse.com/","msgid":"<028280ab-56ad-2380-6bdd-3c944695ec5f@suse.com>","list_archive_url":null,"date":"2022-11-18T09:12:10","name":"[v2,1/4] x86: instantiate i386_{op, reg}tab[] in gas instead of in libopcodes","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/028280ab-56ad-2380-6bdd-3c944695ec5f@suse.com/mbox/"},{"id":22216,"url":"https://patchwork.plctlab.org/api/1.2/patches/22216/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b9a2ae11-6e9c-e9a8-88f6-17c686f0b844@suse.com/","msgid":"","list_archive_url":null,"date":"2022-11-18T09:13:01","name":"[v2,2/4] x86: remove i386-opc.c","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b9a2ae11-6e9c-e9a8-88f6-17c686f0b844@suse.com/mbox/"},{"id":22217,"url":"https://patchwork.plctlab.org/api/1.2/patches/22217/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fad783e7-e00a-c3c1-cb6d-89b70816a737@suse.com/","msgid":"","list_archive_url":null,"date":"2022-11-18T09:13:24","name":"[v2,3/4] x86: break gas dependency on libopcodes","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fad783e7-e00a-c3c1-cb6d-89b70816a737@suse.com/mbox/"},{"id":22218,"url":"https://patchwork.plctlab.org/api/1.2/patches/22218/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e3d67085-1385-d576-8656-30454f9e4474@suse.com/","msgid":"","list_archive_url":null,"date":"2022-11-18T09:14:05","name":"[v2,4/4] x86: drop sentinel from i386_optab[]","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e3d67085-1385-d576-8656-30454f9e4474@suse.com/mbox/"},{"id":23223,"url":"https://patchwork.plctlab.org/api/1.2/patches/23223/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2e469b6dd7d8b93ffd3cac333dd58d172a8f28d6.1668841829.git.research_trasio@irq.a4lg.com/","msgid":"<2e469b6dd7d8b93ffd3cac333dd58d172a8f28d6.1668841829.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-19T07:10:33","name":"[1/2] RISC-V: Make .insn tests stricter","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2e469b6dd7d8b93ffd3cac333dd58d172a8f28d6.1668841829.git.research_trasio@irq.a4lg.com/mbox/"},{"id":23224,"url":"https://patchwork.plctlab.org/api/1.2/patches/23224/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ed49fad6bc6aa4f59d619fd6b445582331594e08.1668841829.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-11-19T07:10:34","name":"[2/2] RISC-V: Better support for long instructions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ed49fad6bc6aa4f59d619fd6b445582331594e08.1668841829.git.research_trasio@irq.a4lg.com/mbox/"},{"id":23362,"url":"https://patchwork.plctlab.org/api/1.2/patches/23362/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7487608537fcd71f322e56d40bfb2cc605cee89a.1668906514.git.research_trasio@irq.a4lg.com/","msgid":"<7487608537fcd71f322e56d40bfb2cc605cee89a.1668906514.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-20T01:08:40","name":"[1/3] RISC-V: Use faster hash table on disassembling","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7487608537fcd71f322e56d40bfb2cc605cee89a.1668906514.git.research_trasio@irq.a4lg.com/mbox/"},{"id":23361,"url":"https://patchwork.plctlab.org/api/1.2/patches/23361/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e984efaf6c2d42891fa466338d999bf8b292dd7d.1668906514.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-11-20T01:08:41","name":"[2/3] RISC-V: Fallback on faster hash table","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e984efaf6c2d42891fa466338d999bf8b292dd7d.1668906514.git.research_trasio@irq.a4lg.com/mbox/"},{"id":23366,"url":"https://patchwork.plctlab.org/api/1.2/patches/23366/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/844db363911065a3b5f0c5e4601f89ee1d7360c5.1668906514.git.research_trasio@irq.a4lg.com/","msgid":"<844db363911065a3b5f0c5e4601f89ee1d7360c5.1668906514.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-20T01:08:42","name":"[3/3] RISC-V: Cache instruction support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/844db363911065a3b5f0c5e4601f89ee1d7360c5.1668906514.git.research_trasio@irq.a4lg.com/mbox/"},{"id":23363,"url":"https://patchwork.plctlab.org/api/1.2/patches/23363/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/88793c204c9270376959c6276fb1b63275bef3c8.1668906599.git.research_trasio@irq.a4lg.com/","msgid":"<88793c204c9270376959c6276fb1b63275bef3c8.1668906599.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-20T01:10:07","name":"[1/3] RISC-V: Easy optimization on riscv_search_mapping_symbol","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/88793c204c9270376959c6276fb1b63275bef3c8.1668906599.git.research_trasio@irq.a4lg.com/mbox/"},{"id":23365,"url":"https://patchwork.plctlab.org/api/1.2/patches/23365/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/55a36e28e1cb3983c637b3019d48717278574591.1668906599.git.research_trasio@irq.a4lg.com/","msgid":"<55a36e28e1cb3983c637b3019d48717278574591.1668906599.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-20T01:10:08","name":"[2/3] RISC-V: Per-section private data initialization","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/55a36e28e1cb3983c637b3019d48717278574591.1668906599.git.research_trasio@irq.a4lg.com/mbox/"},{"id":23364,"url":"https://patchwork.plctlab.org/api/1.2/patches/23364/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d41edfbaf150abb20fd78e8518ca5a9e7e5eb74f.1668906599.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-11-20T01:10:09","name":"[3/3] RISC-V: Optimized search on mapping symbols","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d41edfbaf150abb20fd78e8518ca5a9e7e5eb74f.1668906599.git.research_trasio@irq.a4lg.com/mbox/"},{"id":23372,"url":"https://patchwork.plctlab.org/api/1.2/patches/23372/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/94304c8d9174ae7e9cf52abc3af6ccf5e3e0ecd9.1668910970.git.research_trasio@irq.a4lg.com/","msgid":"<94304c8d9174ae7e9cf52abc3af6ccf5e3e0ecd9.1668910970.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-20T02:23:27","name":"[v3,1/3] RISC-V: Make \"priv-spec\" overridable","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/94304c8d9174ae7e9cf52abc3af6ccf5e3e0ecd9.1668910970.git.research_trasio@irq.a4lg.com/mbox/"},{"id":23371,"url":"https://patchwork.plctlab.org/api/1.2/patches/23371/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9d6008e38402c4e60ada6f3d3db14b92815177d8.1668910970.git.research_trasio@irq.a4lg.com/","msgid":"<9d6008e38402c4e60ada6f3d3db14b92815177d8.1668910970.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-20T02:23:28","name":"[v3,2/3] RISC-V: Add \"arch\" disassembler option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9d6008e38402c4e60ada6f3d3db14b92815177d8.1668910970.git.research_trasio@irq.a4lg.com/mbox/"},{"id":23370,"url":"https://patchwork.plctlab.org/api/1.2/patches/23370/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/70a4ac1ba8c12101de56c24d3a47939a2f5ee542.1668910970.git.research_trasio@irq.a4lg.com/","msgid":"<70a4ac1ba8c12101de56c24d3a47939a2f5ee542.1668910970.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-20T02:23:29","name":"[v3,3/3] gdb/testsuite: RISC-V disassembler option tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/70a4ac1ba8c12101de56c24d3a47939a2f5ee542.1668910970.git.research_trasio@irq.a4lg.com/mbox/"},{"id":23667,"url":"https://patchwork.plctlab.org/api/1.2/patches/23667/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221121110926.124434-1-aleksandar.rikalo@syrmia.com/","msgid":"<20221121110926.124434-1-aleksandar.rikalo@syrmia.com>","list_archive_url":null,"date":"2022-11-21T11:09:26","name":"[v3] Add support for nanoMIPS architecture","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221121110926.124434-1-aleksandar.rikalo@syrmia.com/mbox/"},{"id":23697,"url":"https://patchwork.plctlab.org/api/1.2/patches/23697/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221121120037.19325-1-zengxiao@eswincomputing.com/","msgid":"<20221121120037.19325-1-zengxiao@eswincomputing.com>","list_archive_url":null,"date":"2022-11-21T12:00:37","name":"[v2] RISC-V: Make R_RISCV_SUB6 conforms to riscv ABI standard","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221121120037.19325-1-zengxiao@eswincomputing.com/mbox/"},{"id":23957,"url":"https://patchwork.plctlab.org/api/1.2/patches/23957/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221121171544.3291-1-shahab@synopsys.com/","msgid":"<20221121171544.3291-1-shahab@synopsys.com>","list_archive_url":null,"date":"2022-11-21T17:15:44","name":"opcodes: Correct address for ARC'\''s \"isa_config\" aux reg","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221121171544.3291-1-shahab@synopsys.com/mbox/"},{"id":24026,"url":"https://patchwork.plctlab.org/api/1.2/patches/24026/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y3vyL3UATztRRM8v@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-11-21T21:48:31","name":"PR29807, SIGSEGV when linking fuzzed PE object","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y3vyL3UATztRRM8v@squeak.grove.modra.org/mbox/"},{"id":24269,"url":"https://patchwork.plctlab.org/api/1.2/patches/24269/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221122110927.2328582-1-christoph.muellner@vrull.eu/","msgid":"<20221122110927.2328582-1-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2022-11-22T11:09:27","name":"[v3] riscv: Add AIA extension support (Smaia, Ssaia)","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221122110927.2328582-1-christoph.muellner@vrull.eu/mbox/"},{"id":24318,"url":"https://patchwork.plctlab.org/api/1.2/patches/24318/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221122120339.23186-1-shahab@synopsys.com/","msgid":"<20221122120339.23186-1-shahab@synopsys.com>","list_archive_url":null,"date":"2022-11-22T12:03:39","name":"[PUSHED] opcodes: Correct address for ARC'\''s \"isa_config\" aux reg","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221122120339.23186-1-shahab@synopsys.com/mbox/"},{"id":24501,"url":"https://patchwork.plctlab.org/api/1.2/patches/24501/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221122181927.251937-1-hjl.tools@gmail.com/","msgid":"<20221122181927.251937-1-hjl.tools@gmail.com>","list_archive_url":null,"date":"2022-11-22T18:19:27","name":"x86: Remove libopcodes dependency","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221122181927.251937-1-hjl.tools@gmail.com/mbox/"}],"public":true,"mbox":"https://patchwork.plctlab.org/bundle/patchwork-bot/binutils-gdb_2022-11/mbox/"}]' + bundle_id=9 + git-pw bundle add 9 24599 +------------+-----------------------------------------------------------------------------------------------------------+ | Property | Value | |------------+-----------------------------------------------------------------------------------------------------------| | ID | 9 | | Name | binutils-gdb_2022-11 | | URL | https://patchwork.plctlab.org/bundle/patchwork-bot/binutils-gdb_2022-11/ | | Owner | patchwork-bot | | Project | binutils-gdb | | Public | True | | Patches | 13337 x86: Silence GCC 12 warning on tc-i386.c | | | 13350 x86: simplify expressions in update_imm() | | | 13487 binutils: Run PR binutils/26160 test | | | 13621 [PUSHED] opcodes/arm: silence compiler warning about uninitialized variable use | | | 13628 [PUSHED] opcodes/arm: don't pass non-string literal to printf like function | | | 13747 [Binutils-2.39,backport,GAS] arm: Use DWARF numbering convention for pseudo-register representation | | | 13993 ld: Add module information substream to PDB files | | | 14028 [committed] RISC-V: Fixed the missing $x+arch when adding odd paddings for alignment. | | | 14043 gas/doc/internals.texi: fix typo | | | 14069 [v2] Support multiple .eh_frame sections | | | 14409 arm: PR 29739 Fix typo where '; ' should not have been replaced with '@' | | | 14588 [v3] Support multiple .eh_frame sections | | | 14602 [v2] ld: Add module information substream to PDB files | | | 14706 [opcodes/arm] Fix potential null pointer dereferences | | | 14840 [REVIEW,ONLY,1/2] NEAR-RATIFICATION RISC-V: Add 'Ssstateen' extension and its CSRs | | | 14841 [REVIEW,ONLY,2/2] NEAR-RATIFICATION RISC-V: Add platform property/capability extensions | | | 14894 [1/2] opcodes/mips: use .word/.short for undefined instructions | | | 14893 [2/2] libopcodes/mips: add support for disassembler styling | | | 15465 [v6,1/7] x86: constify parse_insn()'s input | | | 15466 [v6,2/7] x86: re-work insn/suffix recognition | | | 15467 [v6,3/7] ix86: don't recognize/derive Q suffix in the common case | | | 15468 [v6,4/7] x86-64: allow HLE store of accumulator to absolute 32-bit address | | | 15470 [v6,5/7] x86: move bad-use-of-TLS-reloc check | | | 15469 [v6,6/7] x86: drop (now) stray IsString | | | 15471 [v6,7/7] x86: further re-work insn/suffix recognition to also cover MOVSX | | | 15472 [PUSHED] opcodes/arm: silence compiler warning about uninitialized variable use | | | 15473 configure: require libzstd >= 1.4.0 | | | 15485 [1/2] RISC-V: File-level architecture shouldn't be affected by section-level ones. | | | 15486 [2/2] RISC-V: Clarify the suppress rule of mapping symbol with architecture string. | | | 15509 x86: adjust recently introduced testcases | | | 15679 ld/testsuite: skip tests related to -shared when disabled | | | 15751 [V3.1,11/15] libctf: add libsframe to LDFLAGS and LIBS | | | 15792 i386: Check invalid (%dx) usage | | | 15794 [V3.2,11/15] libctf: add libsframe to LDFLAGS and LIBS | | | 15959 [01/12] RISC-V: Remove unnecessary empty matching file | | | 15961 [02/12] RISC-V: Tidy disassembler corner case tests | | | 15960 [03/12] RISC-V: Tidying related to 'Zfinx' disassembler test | | | 15962 [04/12] RISC-V: GAS: Add basic shared test utilities | | | 15966 [05/12] RISC-V: Redefine "nop" test | | | 15963 [06/12] RISC-V: Reorganize/enhance {sign, zero}-extension instructions | | | 15968 [07/12] RISC-V: Combine complex extension error handling tests | | | 15970 [08/12] RISC-V: Refine/enhance 'M'/'Zmmul' extension tests | | | 15964 [09/12] RISC-V: Combine/enhance 'Zicbo[mz]' extension tests | | | 15965 [10/12] RISC-V: Enhance 'Zicbop' testcases | | | 15967 [11/12] RISC-V: Reorganize/enhance 'Zb*' extension tests | | | 15969 [12/12] RISC-V: Combine/enhance 'Zk*'/'Zbk*' extension tests | | | 16066 [V3.1,03/15] gas: generate .sframe from CFI directives | | | 16379 gold/aarch64: Fix adrp distance check | | | 16400 RISC-V: xtheadfmemidx: Use fp register in mnemonics | | | 16594 GAS fix section alignment for aarch64-pe | | | 16744 [V3.3,11/15] libctf: add libsframe to LDFLAGS and LIBS | | | 16797 x86: Correct wrong comments in vex_w_table | | | 16884 [1/2] gprofng: make cpu identification available to others | | | 16885 [2/2] gdb, btrace: use cpuident.h to implement btrace_this_cpu | | | 16995 x86/Intel: don't accept malformed EXTRQ / INSERTQ | | | 17057 Fix typos in the list of objdump options | | | 17117 Use toplevel configure for GMP and MPFR for gdb | | | 17160 [COMMITTED] PowerPC: Add XSP operand define | | | 17202 libctf: use libtool for link test in configure | | | 17262 ld: Always output local symbol for relocatable link | | | 17399 [V4,01/11] sframe.h: Add SFrame format definition | | | 17398 [V4,02/11] gas: add new command line option --gsframe | | | 17400 [V4,03/11] gas: generate .sframe from CFI directives | | | 17403 [V4,04/11] gas: testsuite: add new tests for SFrame unwind info | | | 17407 [V4,05/11] libsframe: add the SFrame library | | | 17406 [V4,06/11] bfd: linker: merge .sframe sections | | | 17402 [V4,07/11] readelf/objdump: support for SFrame section | | | 17401 [V4,08/11] src-release.sh: Add libsframe | | | 17404 [V4,09/11] binutils/NEWS: add text for SFrame support | | | 17405 [V4,10/11] gas/NEWS: add text about new command line option and SFrame support | | | 17418 [V4,11/11] doc: add SFrame spec file | | | 17662 ld/testsuite: skip ld-size when -shared is not supported | | | 17804 [v2] i386: Check invalid (%dx) usage | | | 18043 Sanity check reloc count in get_reloc_upper_bound | | | 18044 mach-o reloc size overflow | | | 18045 [BINTUILS] arm: Add support for Cortex-X1C CPU. | | | 18051 x86: drop stray IsString from PadLock insns | | | 18088 [v2] x86: drop stray IsString from PadLock insns | | | 18130 x86: drop duplicate sse4a entry from cpu_arch[] | | | 18135 x86: fold special-operand insn attributes into a single enum | | | 18284 [PATCHv2] Use toplevel configure for GMP and MPFR for gdb | | | 18337 gprofng: fix typo in configure.ac | | | 18424 ld: Add section contributions substream to PDB files | | | 18513 gas: accept custom ".linefile ." | | | 18517 Sanity check SHT_MIPS_OPTIONS size | | | 18519 PR28834, PR26946 sanity checking section size | | | 18670 [Binutils,gas] arm: Add support for new unwinder directive ".pacspval". | | | 18672 [Binutils,readelf] arm: Support for new pacbti unwind opcode 0xb5. | | | 19116 PowerPC64 paddi -Mraw | | | 19138 pru: bfd: Correct default to no execstack | | | 19173 binutils/objcopy: keep relocation while renaming a section with explicit flags | | | 19377 [1/2] RISC-V: Add T-Head Fmv vendor extension | | | 19378 [2/2] RISC-V: Add T-Head Int vendor extension | | | 19850 readelf: use fseeko for elf files >= 2 GiB on x86_64-mingw32 | | | 19866 x86: infer No_*Suf from other insn attributes | | | 19934 [V2] GAS fix alignment for aarch64-pe | | | 20111 gas: Add --gcodeview option | | | 20174 [v3,1/8] RISC-V: Add a space at the end of pinfo | | | 20177 [v3,2/8] RISC-V: Fix obvious misalignments ('Zbb'/'Zba') | | | 20173 [v3,3/8] RISC-V: Remove spaces in opcode entries | | | 20179 [v3,4/8] RISC-V: Remove unused instruction macros | | | 20176 [v3,5/8] RISC-V: Complete tidying up with SCALL and SBREAK | | | 20178 [v3,6/8] RISC-V: Tidying up with fmv.w.x and fmv.x.w | | | 20180 [v3,7/8] RISC-V: Make alias instructions aliases | | | 20175 [v3,8/8] RISC-V: Use defined mask and match values | | | 20185 [01/11] opcodes/riscv-dis.c: More tidying | | | 20188 [02/11] RISC-V: Add test for 'Zfinx' register switching | | | 20186 [03/11] RISC-V: Make mapping symbol checking consistent | | | 20187 [04/11] RISC-V: Split riscv_get_map_state into two steps | | | 20192 [05/11] RISC-V: One time CSR hash table initialization | | | 20193 [06/11] RISC-V: Use static xlen on ADDIW sequence | | | 20191 [07/11] opcodes/riscv-dis.c: Add form feed for separation | | | 20190 [08/11] RISC-V: Split match/print steps on disassembler | | | 20189 [09/11] RISC-V: Reorganize disassembler state initialization | | | 20194 [10/11] RISC-V: Reorganize arch-related initialization and management | | | 20195 [11/11] RISC-V: Move disassembler private data initialization | | | 20236 [v1,1/1] RISC-V: Make R_RISCV_SUB6 conforms to riscv abi standard | | | 20422 readelf: use fseeko64 or fseeko if possible | | | 20600 aarch64-pe can't fill 16 bytes in section .text | | | 20720 PR29788, gprofng cannot display Java's generated assembly code | | | 21321 ld: Always call elf_backend_output_arch_local_syms | | | 21322 [gas,aarch64] : fix build breakage for aarch64-pe | | | 21449 [V2,gas,aarch64] : fix build breakage for aarch64-pe | | | 21662 [1/2] x86: instantiate i386_{op, reg}tab[] in gas instead of in libopcodes | | | 21663 [2/2] x86: break gas dependency on libopcodes | | | 21682 readelf: use fseeko64 or fseeko if possible | | | 21850 i386: Move i386_seg_prefixes to gas | | | 21858 binutils: partially revert 17c6c3b99156fe82c1e637e1a5fd9f163ac788c8 | | | 21992 riscv: Add AIA extension support (Smaia, Ssaia) | | | 22004 go32 sanity check | | | 22005 PR29799 heap buffer overflow in display_gdb_index dwarf.c:10548 | | | 22050 RISC-V: Add INSN_DREF to memory read/write instructions | | | 22053 [v4,1/8] RISC-V: Add a space at the end of pinfo | | | 22051 [v4,2/8] RISC-V: Fix obvious misalignments ('Zbb'/'Zba') | | | 22052 [v4,3/8] RISC-V: Remove spaces in opcode entries | | | 22055 [v4,4/8] RISC-V: Remove unused instruction macros | | | 22056 [v4,5/8] RISC-V: Complete tidying up with SCALL and SBREAK | | | 22058 [v4,6/8] RISC-V: Tidying up with fmv.w.x and fmv.x.w | | | 22057 [v4,7/8] RISC-V: Make alias instructions aliases | | | 22054 [v4,8/8] RISC-V: Use defined mask and match values | | | 22215 [v2,1/4] x86: instantiate i386_{op, reg}tab[] in gas instead of in libopcodes | | | 22216 [v2,2/4] x86: remove i386-opc.c | | | 22217 [v2,3/4] x86: break gas dependency on libopcodes | | | 22218 [v2,4/4] x86: drop sentinel from i386_optab[] | | | 23223 [1/2] RISC-V: Make .insn tests stricter | | | 23224 [2/2] RISC-V: Better support for long instructions | | | 23362 [1/3] RISC-V: Use faster hash table on disassembling | | | 23361 [2/3] RISC-V: Fallback on faster hash table | | | 23366 [3/3] RISC-V: Cache instruction support | | | 23363 [1/3] RISC-V: Easy optimization on riscv_search_mapping_symbol | | | 23365 [2/3] RISC-V: Per-section private data initialization | | | 23364 [3/3] RISC-V: Optimized search on mapping symbols | | | 23372 [v3,1/3] RISC-V: Make "priv-spec" overridable | | | 23371 [v3,2/3] RISC-V: Add "arch" disassembler option | | | 23370 [v3,3/3] gdb/testsuite: RISC-V disassembler option tests | | | 23667 [v3] Add support for nanoMIPS architecture | | | 23697 [v2] RISC-V: Make R_RISCV_SUB6 conforms to riscv ABI standard | | | 23957 opcodes: Correct address for ARC's "isa_config" aux reg | | | 24026 PR29807, SIGSEGV when linking fuzzed PE object | | | 24269 [v3] riscv: Add AIA extension support (Smaia, Ssaia) | | | 24318 [PUSHED] opcodes: Correct address for ARC's "isa_config" aux reg | | | 24501 x86: Remove libopcodes dependency | | | 24599 Don't use "long" in readelf for file offsets | +------------+-----------------------------------------------------------------------------------------------------------+ + git config pull.rebase false + git fetch origin master From github.com:plctlab/patchwork-binutils-gdb * branch master -> FETCH_HEAD + git checkout master Switched to a new branch 'master' branch 'master' set up to track 'origin/master'. + git pull origin master From github.com:plctlab/patchwork-binutils-gdb * branch master -> FETCH_HEAD Already up to date. + git fetch origin upstream-master From github.com:plctlab/patchwork-binutils-gdb * branch upstream-master -> FETCH_HEAD + git checkout upstream-master Switched to a new branch 'upstream-master' branch 'upstream-master' set up to track 'origin/upstream-master'. + git remote add upstream https://sourceware.org/git/binutils-gdb.git + git pull upstream master From https://sourceware.org/git/binutils-gdb * branch master -> FETCH_HEAD * [new branch] master -> upstream/master Updating f3f7ecc9..04ad7193 Fast-forward bfd/elfxx-x86.c | 2 +- binutils/dwarf.c | 14 +- binutils/dwarf.h | 10 +- binutils/elfcomm.c | 4 +- binutils/elfcomm.h | 26 +- binutils/readelf.c | 1102 +++++++++++++++++++------------------ ld/testsuite/ld-x86-64/pr29820.d | 6 + ld/testsuite/ld-x86-64/pr29820.s | 12 + ld/testsuite/ld-x86-64/x86-64.exp | 1 + 9 files changed, 626 insertions(+), 551 deletions(-) create mode 100644 ld/testsuite/ld-x86-64/pr29820.d create mode 100644 ld/testsuite/ld-x86-64/pr29820.s + git push -u origin upstream-master To github.com:plctlab/patchwork-binutils-gdb.git f3f7ecc9..04ad7193 upstream-master -> upstream-master branch 'upstream-master' set up to track 'origin/upstream-master'. + git checkout master Switched to branch 'master' Your branch is up to date with 'origin/master'. + git merge upstream-master Updating f3f7ecc9..04ad7193 Fast-forward bfd/elfxx-x86.c | 2 +- binutils/dwarf.c | 14 +- binutils/dwarf.h | 10 +- binutils/elfcomm.c | 4 +- binutils/elfcomm.h | 26 +- binutils/readelf.c | 1102 +++++++++++++++++++------------------ ld/testsuite/ld-x86-64/pr29820.d | 6 + ld/testsuite/ld-x86-64/pr29820.s | 12 + ld/testsuite/ld-x86-64/x86-64.exp | 1 + 9 files changed, 626 insertions(+), 551 deletions(-) create mode 100644 ld/testsuite/ld-x86-64/pr29820.d create mode 100644 ld/testsuite/ld-x86-64/pr29820.s + git push -u origin master To github.com:plctlab/patchwork-binutils-gdb.git f3f7ecc9..04ad7193 master -> master branch 'master' set up to track 'origin/master'. + branchname=series9673-patch24599 ++ git branch -a ++ grep 'series9673-patch24599$' + checkbranch= + checkbranchresult=null + '[' null = series9673-patch24599 ']' + git checkout -b series9673-patch24599 Switched to a new branch 'series9673-patch24599' ++ curl https://patchwork.plctlab.org/api/1.2/series/9673/ % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 1364 100 1364 0 0 35894 0 --:--:-- --:--:-- --:--:-- 35894 + series_response='{"id":9673,"url":"https://patchwork.plctlab.org/api/1.2/series/9673/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/list/?series=9673","project":{"id":2,"url":"https://patchwork.plctlab.org/api/1.2/projects/2/","name":"binutils-gdb","link_name":"binutils-gdb","list_id":"binutils.sourceware.org","list_email":"binutils@sourceware.org","web_url":"https://github.com/wangliu-iscas/Patchwork-Bundles/blob/main/binutils-gdb.md","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"name":"Don'\''t use \"long\" in readelf for file offsets","date":"2022-11-22T21:59:00","submitter":{"id":207,"url":"https://patchwork.plctlab.org/api/1.2/people/207/","name":"Alan Modra","email":"amodra@gmail.com"},"version":1,"total":1,"received_total":1,"received_all":true,"mbox":"https://patchwork.plctlab.org/series/9673/mbox/","cover_letter":null,"patches":[{"id":24599,"url":"https://patchwork.plctlab.org/api/1.2/patches/24599/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y31GJLbFpb5DCn2F@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-11-22T21:59:00","name":"Don'\''t use \"long\" in readelf for file offsets","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y31GJLbFpb5DCn2F@squeak.grove.modra.org/mbox/"}]}' ++ jq '.patches[] | (.id|tostring) + "," + .mbox' ++ echo '{"id":9673,"url":"https://patchwork.plctlab.org/api/1.2/series/9673/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/list/?series=9673","project":{"id":2,"url":"https://patchwork.plctlab.org/api/1.2/projects/2/","name":"binutils-gdb","link_name":"binutils-gdb","list_id":"binutils.sourceware.org","list_email":"binutils@sourceware.org","web_url":"https://github.com/wangliu-iscas/Patchwork-Bundles/blob/main/binutils-gdb.md","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"name":"Don'\''t use \"long\" in readelf for file offsets","date":"2022-11-22T21:59:00","submitter":{"id":207,"url":"https://patchwork.plctlab.org/api/1.2/people/207/","name":"Alan Modra","email":"amodra@gmail.com"},"version":1,"total":1,"received_total":1,"received_all":true,"mbox":"https://patchwork.plctlab.org/series/9673/mbox/","cover_letter":null,"patches":[{"id":24599,"url":"https://patchwork.plctlab.org/api/1.2/patches/24599/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y31GJLbFpb5DCn2F@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-11-22T21:59:00","name":"Don'\''t use \"long\" in readelf for file offsets","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y31GJLbFpb5DCn2F@squeak.grove.modra.org/mbox/"}]}' + patchid_patchurl='"24599,https://patchwork.plctlab.org/project/binutils-gdb/patch/Y31GJLbFpb5DCn2F@squeak.grove.modra.org/mbox/"' + echo '"24599,https://patchwork.plctlab.org/project/binutils-gdb/patch/Y31GJLbFpb5DCn2F@squeak.grove.modra.org/mbox/"' + IFS=, + read -r series_patch_id series_patch_url ++ echo '"24599' ++ sed 's/"//g' + series_patch_id=24599 ++ echo 'https://patchwork.plctlab.org/project/binutils-gdb/patch/Y31GJLbFpb5DCn2F@squeak.grove.modra.org/mbox/"' ++ sed 's/"//g' + series_patch_url=https://patchwork.plctlab.org/project/binutils-gdb/patch/Y31GJLbFpb5DCn2F@squeak.grove.modra.org/mbox/ ++ git rev-parse HEAD + commitid_before=04ad71937f28561ad5a2bbbc7e8f0af21e1019f8 + eval '+++ declare -p bout bret declare -- bout="Applying: Don'\''t use \"long\" in readelf for file offsets .git/rebase-apply/patch:2052: indent with spaces. size_t j; .git/rebase-apply/patch:2734: indent with spaces. warn (_(\"corrupt namesz found in note at offset %#zx\\n\"), .git/rebase-apply/patch:2735: indent with spaces. (char *) external - (char *) pnotes); .git/rebase-apply/patch:2736: indent with spaces. warn (_(\" type: %#lx, namesize: %#lx, descsize: %#lx\\n\"), warning: 4 lines add whitespace errors. Using index info to reconstruct a base tree... M binutils/dwarf.c M binutils/dwarf.h M binutils/elfcomm.c M binutils/elfcomm.h M binutils/readelf.c Falling back to patching base and 3-way merge... No changes -- Patch already applied." declare -- bret="0" ++ berr='\''++++ git_am https://patchwork.plctlab.org/project/binutils-gdb/patch/Y31GJLbFpb5DCn2F@squeak.grove.modra.org/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/binutils-gdb/patch/Y31GJLbFpb5DCn2F@squeak.grove.modra.org/mbox/ ++++ curl https://patchwork.plctlab.org/project/binutils-gdb/patch/Y31GJLbFpb5DCn2F@squeak.grove.modra.org/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 107k 100 107k 0 0 1448k 0 --:--:-- --:--:-- --:--:-- 1448k +++ bout='\''\'\'''\''Applying: Don'\''\'\'''\''\'\''\'\'''\'''\''\'\'''\''t use "long" in readelf for file offsets .git/rebase-apply/patch:2052: indent with spaces. size_t j; .git/rebase-apply/patch:2734: indent with spaces. warn (_("corrupt namesz found in note at offset %#zx\n"), .git/rebase-apply/patch:2735: indent with spaces. (char *) external - (char *) pnotes); .git/rebase-apply/patch:2736: indent with spaces. warn (_(" type: %#lx, namesize: %#lx, descsize: %#lx\n"), warning: 4 lines add whitespace errors. Using index info to reconstruct a base tree... M binutils/dwarf.c M binutils/dwarf.h M binutils/elfcomm.c M binutils/elfcomm.h M binutils/readelf.c Falling back to patching base and 3-way merge... No changes -- Patch already applied.'\''\'\'''\'' +++ bret=0'\'' ++ declare -p berr declare -- berr="++++ git_am https://patchwork.plctlab.org/project/binutils-gdb/patch/Y31GJLbFpb5DCn2F@squeak.grove.modra.org/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/binutils-gdb/patch/Y31GJLbFpb5DCn2F@squeak.grove.modra.org/mbox/ ++++ curl https://patchwork.plctlab.org/project/binutils-gdb/patch/Y31GJLbFpb5DCn2F@squeak.grove.modra.org/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 107k 100 107k 0 0 1448k 0 --:--:-- --:--:-- --:--:-- 1448k +++ bout='\''Applying: Don'\''\\'\'''\''t use \"long\" in readelf for file offsets .git/rebase-apply/patch:2052: indent with spaces. size_t j; .git/rebase-apply/patch:2734: indent with spaces. warn (_(\"corrupt namesz found in note at offset %#zx\\n\"), .git/rebase-apply/patch:2735: indent with spaces. (char *) external - (char *) pnotes); .git/rebase-apply/patch:2736: indent with spaces. warn (_(\" type: %#lx, namesize: %#lx, descsize: %#lx\\n\"), warning: 4 lines add whitespace errors. Using index info to reconstruct a base tree... M binutils/dwarf.c M binutils/dwarf.h M binutils/elfcomm.c M binutils/elfcomm.h M binutils/readelf.c Falling back to patching base and 3-way merge... No changes -- Patch already applied.'\'' +++ bret=0"' ++ +++ declare -p bout bret /tmp/jenkins18048627011076444890.sh: line 124: +++: command not found ++ declare -- 'bout=Applying: Don'\''t use "long" in readelf for file offsets .git/rebase-apply/patch:2052: indent with spaces. size_t j; .git/rebase-apply/patch:2734: indent with spaces. warn (_("corrupt namesz found in note at offset %#zx\n"), .git/rebase-apply/patch:2735: indent with spaces. (char *) external - (char *) pnotes); .git/rebase-apply/patch:2736: indent with spaces. warn (_(" type: %#lx, namesize: %#lx, descsize: %#lx\n"), warning: 4 lines add whitespace errors. Using index info to reconstruct a base tree... M binutils/dwarf.c M binutils/dwarf.h M binutils/elfcomm.c M binutils/elfcomm.h M binutils/readelf.c Falling back to patching base and 3-way merge... No changes -- Patch already applied.' ++ declare -- bret=0 ++ ++ 'berr=++++ git_am https://patchwork.plctlab.org/project/binutils-gdb/patch/Y31GJLbFpb5DCn2F@squeak.grove.modra.org/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/binutils-gdb/patch/Y31GJLbFpb5DCn2F@squeak.grove.modra.org/mbox/ ++++ curl https://patchwork.plctlab.org/project/binutils-gdb/patch/Y31GJLbFpb5DCn2F@squeak.grove.modra.org/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 107k 100 107k 0 0 1448k 0 --:--:-- --:--:-- --:--:-- 1448k +++ bout='\''Applying: Don'\''\'\'''\''t use "long" in readelf for file offsets .git/rebase-apply/patch:2052: indent with spaces. size_t j; .git/rebase-apply/patch:2734: indent with spaces. warn (_("corrupt namesz found in note at offset %#zx\n"), .git/rebase-apply/patch:2735: indent with spaces. (char *) external - (char *) pnotes); .git/rebase-apply/patch:2736: indent with spaces. warn (_(" type: %#lx, namesize: %#lx, descsize: %#lx\n"), warning: 4 lines add whitespace errors. Using index info to reconstruct a base tree... M binutils/dwarf.c M binutils/dwarf.h M binutils/elfcomm.c M binutils/elfcomm.h M binutils/readelf.c Falling back to patching base and 3-way merge... No changes -- Patch already applied.'\'' +++ bret=0' /tmp/jenkins18048627011076444890.sh: line 169: ++: command not found ++ ++ declare -p berr /tmp/jenkins18048627011076444890.sh: line 170: ++: command not found ++ declare -- 'berr=++++ git_am https://patchwork.plctlab.org/project/binutils-gdb/patch/Y31GJLbFpb5DCn2F@squeak.grove.modra.org/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/binutils-gdb/patch/Y31GJLbFpb5DCn2F@squeak.grove.modra.org/mbox/ ++++ curl https://patchwork.plctlab.org/project/binutils-gdb/patch/Y31GJLbFpb5DCn2F@squeak.grove.modra.org/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 107k 100 107k 0 0 1448k 0 --:--:-- --:--:-- --:--:-- 1448k +++ bout='\''Applying: Don'\''\'\'''\''t use "long" in readelf for file offsets .git/rebase-apply/patch:2052: indent with spaces. size_t j; .git/rebase-apply/patch:2734: indent with spaces. warn (_("corrupt namesz found in note at offset %#zx\n"), .git/rebase-apply/patch:2735: indent with spaces. (char *) external - (char *) pnotes); .git/rebase-apply/patch:2736: indent with spaces. warn (_(" type: %#lx, namesize: %#lx, descsize: %#lx\n"), warning: 4 lines add whitespace errors. Using index info to reconstruct a base tree... M binutils/dwarf.c M binutils/dwarf.h M binutils/elfcomm.c M binutils/elfcomm.h M binutils/readelf.c Falling back to patching base and 3-way merge... No changes -- Patch already applied.'\'' +++ bret=0' ++ git rev-parse HEAD + commitid_after=04ad71937f28561ad5a2bbbc7e8f0af21e1019f8 + '[' 0 = 0 ']' + '[' 04ad71937f28561ad5a2bbbc7e8f0af21e1019f8 = 04ad71937f28561ad5a2bbbc7e8f0af21e1019f8 ']' + submit_check warning 'Repeat Merge' https://patchwork.plctlab.org/jenkins/job/binutils-gdb/432/consoleText 'Git am fail log' + check_state=warning + patch_state='Repeat Merge' + repo_url=https://patchwork.plctlab.org/jenkins/job/binutils-gdb/432/consoleText + DESCRIPTION='Git am fail log' + curl -X POST -H 'Authorization: Token [*******]' -F state=warning -F target_url=https://patchwork.plctlab.org/jenkins/job/binutils-gdb/432/consoleText -F context=binutils-gdb-check -F 'description=Git am fail log' https://patchwork.plctlab.org/api/patches/24599/checks/ % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 975 100 430 100 545 16538 20961 --:--:-- --:--:-- --:--:-- 37500 {"id":2567,"url":"https://patchwork.plctlab.org/api/patches/24599/checks/2567/","user":{"id":1,"url":"https://patchwork.plctlab.org/api/users/1/","username":"snail","first_name":"","last_name":"","email":"wangliu@iscas.ac.cn"},"date":"2022-11-22T22:15:43.198558","state":"warning","target_url":"https://patchwork.plctlab.org/jenkins/job/binutils-gdb/432/consoleText","context":"binutils-gdb-check","description":"Git am fail log"}+ curl -X PATCH -H 'Authorization: Token [*******]' -F 'state=Repeat Merge' https://patchwork.plctlab.org/api/1.2/patches/24599/ % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0{"id":24599,"url":"https://patchwork.plctlab.org/api/1.2/patches/24599/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y31GJLbFpb5DCn2F@squeak.grove.modra.org/","project":{"id":2,"url":"https://patchwork.plctlab.org/api/1.2/projects/2/","name":"binutils-gdb","link_name":"binutils-gdb","list_id":"binutils.sourceware.org","list_email":"binutils@sourceware.org","web_url":"https://github.com/wangliu-iscas/Patchwork-Bundles/blob/main/binutils-gdb.md","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"","list_archive_url":null,"date":"2022-11-22T21:59:00","name":"Don't use \"long\" in readelf for file offsets","commit_ref":null,"pull_url":null,"state":"repeat-merge","archived":false,"hash":"b16c4fb50e059abbd1074f17951813050c4e7a3c","submitter":{"id":207,"url":"https://patchwork.plctlab.org/api/1.2/people/207/","name":"Alan Modra","email":"amodra@gmail.com"},"delegate":null,"mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y31GJLbFpb5DCn2F@squeak.grove.modra.org/mbox/","series":[{"id":9673,"url":"https://patchwork.plctlab.org/api/1.2/series/9673/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/list/?series=9673","date":"2022-11-22T21:59:00","name":"Don't use \"long\" in readelf for file offsets","version":1,"mbox":"https://patchwork.plctlab.org/series/9673/mbox/"}],"comments":"https://patchwork.plctlab.org/api/patches/24599/comments/","check":"warning","checks":"https://patchwork.plctlab.org/api/patches/24599/checks/","tags":{},"headers":{"Return-Path":"","Delivered-To":["ouuuleilei@gmail.com","binutils@sourceware.org"],"Received":["by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp2457568wrr;\n Tue, 22 Nov 2022 13:59:23 -0800 (PST)","from sourceware.org (server2.sourceware.org. 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charset=us-ascii","Content-Disposition":"inline","In-Reply-To":"","X-Spam-Status":"No, score=-3035.5 required=5.0 tests=BAYES_00, DKIM_SIGNED,\n DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0,\n RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS,\n TXREP autolearn=ham autolearn_force=no version=3.4.6","X-Spam-Checker-Version":"SpamAssassin 3.4.6 (2021-04-09) on\n server2.sourceware.org","X-BeenThere":"binutils@sourceware.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"Binutils mailing list ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","From":"Alan Modra via Binutils ","Reply-To":"Alan Modra ","Errors-To":"binutils-bounces+ouuuleilei=gmail.com@sourceware.org","Sender":"\"Binutils\" ","X-getmail-retrieved-from-mailbox":"=?utf-8?q?INBOX?=","X-GMAIL-THRID":"=?utf-8?q?1750235205912119726?=","X-GMAIL-MSGID":"=?utf-8?q?1750235205912119726?="},"content":"The aim here is to improve readelf handling of large 64-bit object\nfiles on LLP64 hosts (Windows) where long is only 32 bits. The patch\nchanges more than just file offsets. Addresses and sizes are also\nchanged to avoid \"long\". Most places get to use uint64_t even where\nsize_t may be more appropriate, because that allows some overflow\nchecks to be implemented easily (*alloc changes).\n\n\t* dwarf.c (cmalloc, xcmalloc, xcrealloc, xcalloc2): Make nmemb\n\tparameter uint64_t.\n\t* dwarf.h: Update prototypes.\n\t(struct dwarf_section): Make num_relocs uint64_t.\n\t* elfcomm.c (setup_archive): Update error format.\n\t* elfcomm.h (struct archive_info): Make sym_size, longnames_size,\n\tnested_member_origin, next_arhdr_offset uint64_t.\n\t* readelf.c (struct filedata): Make archive_file_offset,\n\tarchive_file_size, string_table_length, dynamic_addr,\n\tdynamic_nent, dynamic_strings_length, num_dynamic_syms,\n\tdynamic_syminfo_offset uint64_t.\n\t(many functions): Replace uses of \"unsigned long\" with\n\t\"uint64_t\" or \"size_t\".","diff":"diff --git a/binutils/dwarf.c b/binutils/dwarf.c\nindex 4bba8dfb81a..404a0bdbac6 100644\n--- a/binutils/dwarf.c\n+++ b/binutils/dwarf.c\n@@ -11082,7 +11082,7 @@ display_debug_not_supported (struct dwarf_section *section,\n Note: does *not* initialise the allocated memory to zero. */\n \n void *\n-cmalloc (size_t nmemb, size_t size)\n+cmalloc (uint64_t nmemb, size_t size)\n {\n /* Check for overflow. */\n if (nmemb >= ~(size_t) 0 / size)\n@@ -11096,13 +11096,13 @@ cmalloc (size_t nmemb, size_t size)\n Note: does *not* initialise the allocated memory to zero. */\n \n void *\n-xcmalloc (size_t nmemb, size_t size)\n+xcmalloc (uint64_t nmemb, size_t size)\n {\n /* Check for overflow. */\n if (nmemb >= ~(size_t) 0 / size)\n {\n fprintf (stderr,\n-\t _(\"Attempt to allocate an array with an excessive number of elements: %#zx\\n\"),\n+\t _(\"Attempt to allocate an array with an excessive number of elements: %#\" PRIx64 \"\\n\"),\n \t nmemb);\n xexit (1);\n }\n@@ -11115,12 +11115,12 @@ xcmalloc (size_t nmemb, size_t size)\n Note: does *not* initialise any new memory to zero. */\n \n void *\n-xcrealloc (void *ptr, size_t nmemb, size_t size)\n+xcrealloc (void *ptr, uint64_t nmemb, size_t size)\n {\n /* Check for overflow. */\n if (nmemb >= ~(size_t) 0 / size)\n {\n- error (_(\"Attempt to re-allocate an array with an excessive number of elements: %#zx\\n\"),\n+ error (_(\"Attempt to re-allocate an array with an excessive number of elements: %#\" PRIx64 \"\\n\"),\n \t nmemb);\n xexit (1);\n }\n@@ -11131,12 +11131,12 @@ xcrealloc (void *ptr, size_t nmemb, size_t size)\n /* Like xcalloc, but verifies that the first parameter is not too large. */\n \n void *\n-xcalloc2 (size_t nmemb, size_t size)\n+xcalloc2 (uint64_t nmemb, size_t size)\n {\n /* Check for overflow. */\n if (nmemb >= ~(size_t) 0 / size)\n {\n- error (_(\"Attempt to allocate a zero'ed array with an excessive number of elements: %#zx\\n\"),\n+ error (_(\"Attempt to allocate a zero'ed array with an excessive number of elements: %#\" PRIx64 \"\\n\"),\n \t nmemb);\n xexit (1);\n }\ndiff --git a/binutils/dwarf.h b/binutils/dwarf.h\nindex bb6128e3b5b..9c0031355d2 100644\n--- a/binutils/dwarf.h\n+++ b/binutils/dwarf.h\n@@ -144,7 +144,7 @@ struct dwarf_section\n enum dwarf_section_display_enum abbrev_sec;\n /* Used by clients to help them implement the reloc_at callback. */\n void * reloc_info;\n- unsigned long num_relocs;\n+ uint64_t num_relocs;\n };\n \n /* A structure containing the name of a debug section\n@@ -256,10 +256,10 @@ extern void dwarf_select_sections_all (void);\n \n extern unsigned int * find_cu_tu_set (void *, unsigned int);\n \n-extern void * cmalloc (size_t, size_t);\n-extern void * xcalloc2 (size_t, size_t);\n-extern void * xcmalloc (size_t, size_t);\n-extern void * xcrealloc (void *, size_t, size_t);\n+extern void * cmalloc (uint64_t, size_t);\n+extern void * xcalloc2 (uint64_t, size_t);\n+extern void * xcmalloc (uint64_t, size_t);\n+extern void * xcrealloc (void *, uint64_t, size_t);\n \n /* A callback into the client. Returns TRUE if there is a\n relocation against the given debug section at the given\ndiff --git a/binutils/elfcomm.c b/binutils/elfcomm.c\nindex 0e7d0b57ac6..6070b6ee8d9 100644\n--- a/binutils/elfcomm.c\n+++ b/binutils/elfcomm.c\n@@ -530,7 +530,7 @@ setup_archive (struct archive_info *arch, const char *file_name,\n /* PR 17531: file: 01068045. */\n if (arch->longnames_size < 8)\n \t{\n-\t error (_(\"%s: long name table is too small, (size = %ld)\\n\"),\n+\t error (_(\"%s: long name table is too small, (size = %\" PRId64 \")\\n\"),\n \t\t file_name, arch->longnames_size);\n \t return 1;\n \t}\n@@ -538,7 +538,7 @@ setup_archive (struct archive_info *arch, const char *file_name,\n if ((off_t) arch->longnames_size > file_size\n \t || (signed long) arch->longnames_size < 0)\n \t{\n-\t error (_(\"%s: long name table is too big, (size = 0x%lx)\\n\"),\n+\t error (_(\"%s: long name table is too big, (size = %#\" PRIx64 \")\\n\"),\n \t\t file_name, arch->longnames_size);\n \t return 1;\n \t}\ndiff --git a/binutils/elfcomm.h b/binutils/elfcomm.h\nindex bab46b03451..54ac4b36811 100644\n--- a/binutils/elfcomm.h\n+++ b/binutils/elfcomm.h\n@@ -49,19 +49,19 @@ extern uint64_t byte_get_big_endian (const unsigned char *, unsigned int);\n \n struct archive_info\n {\n- char * file_name; /* Archive file name. */\n- FILE * file; /* Open file descriptor. */\n- uint64_t index_num; /* Number of symbols in table. */\n- uint64_t * index_array; /* The array of member offsets. */\n- char * sym_table; /* The symbol table. */\n- unsigned long sym_size; /* Size of the symbol table. */\n- char * longnames; /* The long file names table. */\n- unsigned long longnames_size; /* Size of the long file names table. */\n- unsigned long nested_member_origin; /* Origin in the nested archive of the current member. */\n- unsigned long next_arhdr_offset; /* Offset of the next archive header. */\n- int is_thin_archive; /* 1 if this is a thin archive. */\n- int uses_64bit_indices; /* 1 if the index table uses 64bit entries. */\n- struct ar_hdr arhdr; /* Current archive header. */\n+ char *file_name; /* Archive file name. */\n+ FILE *file; /* Open file descriptor. */\n+ uint64_t index_num; /* Number of symbols in table. */\n+ uint64_t *index_array; /* The array of member offsets. */\n+ char *sym_table; /* The symbol table. */\n+ uint64_t sym_size; /* Size of the symbol table. */\n+ char *longnames; /* The long file names table. */\n+ uint64_t longnames_size; /* Size of the long file names table. */\n+ uint64_t nested_member_origin; /* Origin in the nested archive of the current member. */\n+ uint64_t next_arhdr_offset; /* Offset of the next archive header. */\n+ int is_thin_archive; /* 1 if this is a thin archive. */\n+ int uses_64bit_indices; /* 1 if the index table uses 64bit entries. */\n+ struct ar_hdr arhdr; /* Current archive header. */\n };\n \n /* Return the path name for a proxy entry in a thin archive. */\ndiff --git a/binutils/readelf.c b/binutils/readelf.c\nindex 291bc13e0d0..1bd6df9448a 100644\n--- a/binutils/readelf.c\n+++ b/binutils/readelf.c\n@@ -272,27 +272,27 @@ typedef struct filedata\n FILE * handle;\n uint64_t file_size;\n Elf_Internal_Ehdr file_header;\n- unsigned long archive_file_offset;\n- unsigned long archive_file_size;\n+ uint64_t archive_file_offset;\n+ uint64_t archive_file_size;\n /* Everything below this point is cleared out by free_filedata. */\n Elf_Internal_Shdr * section_headers;\n Elf_Internal_Phdr * program_headers;\n char * string_table;\n- unsigned long string_table_length;\n- unsigned long dynamic_addr;\n+ uint64_t string_table_length;\n+ uint64_t dynamic_addr;\n uint64_t dynamic_size;\n- size_t dynamic_nent;\n+ uint64_t dynamic_nent;\n Elf_Internal_Dyn * dynamic_section;\n Elf_Internal_Shdr * dynamic_strtab_section;\n char * dynamic_strings;\n- unsigned long dynamic_strings_length;\n+ uint64_t dynamic_strings_length;\n Elf_Internal_Shdr * dynamic_symtab_section;\n- unsigned long num_dynamic_syms;\n+ uint64_t num_dynamic_syms;\n Elf_Internal_Sym * dynamic_symbols;\n- uint64_t version_info[16];\n+ uint64_t version_info[16];\n unsigned int dynamic_syminfo_nent;\n Elf_Internal_Syminfo * dynamic_syminfo;\n- unsigned long dynamic_syminfo_offset;\n+ uint64_t dynamic_syminfo_offset;\n uint64_t nbuckets;\n uint64_t nchains;\n uint64_t * buckets;\n@@ -396,7 +396,7 @@ fseek64 (FILE *stream, int64_t offset, int whence)\n }\n \n static const char * get_symbol_version_string\n- (Filedata *, bool, const char *, unsigned long, unsigned,\n+ (Filedata *, bool, const char *, size_t, unsigned,\n Elf_Internal_Sym *, enum versioned_symbol_info *, unsigned short *);\n \n #define UNKNOWN -1\n@@ -473,7 +473,7 @@ get_dynamic_name (const Filedata *filedata, size_t offset)\n static void *\n get_data (void *var,\n \t Filedata *filedata,\n-\t unsigned long offset,\n+\t uint64_t offset,\n \t uint64_t size,\n \t uint64_t nmemb,\n \t const char *reason)\n@@ -516,7 +516,7 @@ get_data (void *var,\n \t SEEK_SET))\n {\n if (reason)\n-\terror (_(\"Unable to seek to 0x%lx for %s\\n\"),\n+\terror (_(\"Unable to seek to %#\" PRIx64 \" for %s\\n\"),\n \t filedata->archive_file_offset + offset, reason);\n return NULL;\n }\n@@ -919,7 +919,7 @@ printable_section_name (Filedata * filedata, const Elf_Internal_Shdr * sec)\n }\n \n static const char *\n-printable_section_name_from_index (Filedata * filedata, unsigned long ndx)\n+printable_section_name_from_index (Filedata *filedata, size_t ndx)\n {\n if (ndx >= filedata->file_header.e_shnum)\n return _(\"\");\n@@ -1162,14 +1162,14 @@ guess_is_rela (unsigned int e_machine)\n responsibility to free the allocated buffer. */\n \n static bool\n-slurp_rela_relocs (Filedata * filedata,\n-\t\t unsigned long rel_offset,\n-\t\t unsigned long rel_size,\n-\t\t Elf_Internal_Rela ** relasp,\n-\t\t unsigned long * nrelasp)\n+slurp_rela_relocs (Filedata *filedata,\n+\t\t uint64_t rel_offset,\n+\t\t uint64_t rel_size,\n+\t\t Elf_Internal_Rela **relasp,\n+\t\t uint64_t *nrelasp)\n {\n Elf_Internal_Rela * relas;\n- size_t nrelas;\n+ uint64_t nrelas;\n unsigned int i;\n \n if (is_32bit_elf)\n@@ -1262,14 +1262,14 @@ slurp_rela_relocs (Filedata * filedata,\n responsibility to free the allocated buffer. */\n \n static bool\n-slurp_rel_relocs (Filedata * filedata,\n-\t\t unsigned long rel_offset,\n-\t\t unsigned long rel_size,\n-\t\t Elf_Internal_Rela ** relsp,\n-\t\t unsigned long * nrelsp)\n+slurp_rel_relocs (Filedata *filedata,\n+\t\t uint64_t rel_offset,\n+\t\t uint64_t rel_size,\n+\t\t Elf_Internal_Rela **relsp,\n+\t\t uint64_t *nrelsp)\n {\n Elf_Internal_Rela * rels;\n- size_t nrels;\n+ uint64_t nrels;\n unsigned int i;\n \n if (is_32bit_elf)\n@@ -1354,11 +1354,11 @@ slurp_rel_relocs (Filedata * filedata,\n }\n \n static bool\n-slurp_relr_relocs (Filedata * filedata,\n-\t\t unsigned long relr_offset,\n-\t\t unsigned long relr_size,\n-\t\t uint64_t ** relrsp,\n-\t\t unsigned long * nrelrsp)\n+slurp_relr_relocs (Filedata *filedata,\n+\t\t uint64_t relr_offset,\n+\t\t uint64_t relr_size,\n+\t\t uint64_t **relrsp,\n+\t\t uint64_t *nrelrsp)\n {\n void *relrs;\n size_t size = 0, nentries, i;\n@@ -1468,17 +1468,17 @@ uses_msp430x_relocs (Filedata * filedata)\n offset. */\n \n static bool\n-dump_relocations (Filedata * filedata,\n-\t\t unsigned long rel_offset,\n-\t\t unsigned long rel_size,\n-\t\t Elf_Internal_Sym * symtab,\n-\t\t unsigned long nsyms,\n-\t\t char * strtab,\n-\t\t unsigned long strtablen,\n-\t\t relocation_type rel_type,\n-\t\t bool is_dynsym)\n-{\n- unsigned long i;\n+dump_relocations (Filedata *filedata,\n+\t\t uint64_t rel_offset,\n+\t\t uint64_t rel_size,\n+\t\t Elf_Internal_Sym *symtab,\n+\t\t uint64_t nsyms,\n+\t\t char *strtab,\n+\t\t uint64_t strtablen,\n+\t\t relocation_type rel_type,\n+\t\t bool is_dynsym)\n+{\n+ size_t i;\n Elf_Internal_Rela * rels;\n bool res = true;\n \n@@ -1505,7 +1505,8 @@ dump_relocations (Filedata * filedata,\n \t\t\t &rel_size))\n \treturn false;\n \n- printf (ngettext (\" %lu offset\\n\", \" %lu offsets\\n\", rel_size),\n+ printf (ngettext (\" %\" PRIu64 \" offset\\n\",\n+\t\t\t\" %\" PRIu64 \" offsets\\n\", rel_size),\n \t rel_size);\n for (i = 0; i < rel_size; i++)\n \tprintf (format, relrs[i]);\n@@ -1944,8 +1945,8 @@ dump_relocations (Filedata * filedata,\n \t else\n \t {\n \t putchar (' ');\n-\t printf (_(\"\"),\n-\t\t (unsigned long) rels[i].r_addend);\n+\t printf (_(\"\"),\n+\t\t rels[i].r_addend);\n \t res = false;\n \t }\n \t}\n@@ -2098,7 +2099,7 @@ dump_relocations (Filedata * filedata,\n if (filedata->file_header.e_machine == EM_SPARCV9\n \t && rtype != NULL\n \t && streq (rtype, \"R_SPARC_OLO10\"))\n-\tprintf (\" + %lx\", (unsigned long) ELF64_R_TYPE_DATA (inf));\n+\tprintf (\" + %\" PRIx64, ELF64_R_TYPE_DATA (inf));\n \n putchar ('\\n');\n \n@@ -2624,7 +2625,7 @@ static bool get_dynamic_section (Filedata *);\n static void\n locate_dynamic_section (Filedata *filedata)\n {\n- unsigned long dynamic_addr = 0;\n+ uint64_t dynamic_addr = 0;\n uint64_t dynamic_size = 0;\n \n if (filedata->file_header.e_phnum != 0\n@@ -6126,7 +6127,7 @@ process_program_headers (Filedata * filedata)\n \t}\n }\n \n- unsigned long dynamic_addr = 0;\n+ uint64_t dynamic_addr = 0;\n uint64_t dynamic_size = 0;\n for (i = 0, segment = filedata->program_headers;\n i < filedata->file_header.e_phnum;\n@@ -6374,7 +6375,7 @@ the .dynamic section is not the same as the dynamic segment\\n\"));\n \n /* Find the file offset corresponding to VMA by using the program headers. */\n \n-static long\n+static int64_t\n offset_from_vma (Filedata * filedata, uint64_t vma, uint64_t size)\n {\n Elf_Internal_Phdr * seg;\n@@ -6397,9 +6398,9 @@ offset_from_vma (Filedata * filedata, uint64_t vma, uint64_t size)\n \treturn vma - seg->p_vaddr + seg->p_offset;\n }\n \n- warn (_(\"Virtual address 0x%lx not located in any PT_LOAD segment.\\n\"),\n-\t(unsigned long) vma);\n- return (long) vma;\n+ warn (_(\"Virtual address %#\" PRIx64\n+\t \" not located in any PT_LOAD segment.\\n\"), vma);\n+ return vma;\n }\n \n \n@@ -6560,11 +6561,11 @@ get_section_headers (Filedata *filedata, bool probe)\n }\n \n static Elf_Internal_Sym *\n-get_32bit_elf_symbols (Filedata * filedata,\n-\t\t Elf_Internal_Shdr * section,\n-\t\t unsigned long * num_syms_return)\n+get_32bit_elf_symbols (Filedata *filedata,\n+\t\t Elf_Internal_Shdr *section,\n+\t\t uint64_t *num_syms_return)\n {\n- unsigned long number = 0;\n+ uint64_t number = 0;\n Elf32_External_Sym * esyms = NULL;\n Elf_External_Sym_Shndx * shndx = NULL;\n Elf_Internal_Sym * isyms = NULL;\n@@ -6582,17 +6583,17 @@ get_32bit_elf_symbols (Filedata * filedata,\n /* Run some sanity checks first. */\n if (section->sh_entsize == 0 || section->sh_entsize > section->sh_size)\n {\n- error (_(\"Section %s has an invalid sh_entsize of 0x%lx\\n\"),\n+ error (_(\"Section %s has an invalid sh_entsize of %#\" PRIx64 \"\\n\"),\n \t printable_section_name (filedata, section),\n-\t (unsigned long) section->sh_entsize);\n+\t section->sh_entsize);\n goto exit_point;\n }\n \n if (section->sh_size > filedata->file_size)\n {\n- error (_(\"Section %s has an invalid sh_size of 0x%lx\\n\"),\n+ error (_(\"Section %s has an invalid sh_size of %#\" PRIx64 \"\\n\"),\n \t printable_section_name (filedata, section),\n-\t (unsigned long) section->sh_size);\n+\t section->sh_size);\n goto exit_point;\n }\n \n@@ -6600,10 +6601,11 @@ get_32bit_elf_symbols (Filedata * filedata,\n \n if (number * sizeof (Elf32_External_Sym) > section->sh_size + 1)\n {\n- error (_(\"Size (0x%lx) of section %s is not a multiple of its sh_entsize (0x%lx)\\n\"),\n-\t (unsigned long) section->sh_size,\n+ error (_(\"Size (%#\" PRIx64 \") of section %s \"\n+\t \"is not a multiple of its sh_entsize (%#\" PRIx64 \")\\n\"),\n+\t section->sh_size,\n \t printable_section_name (filedata, section),\n-\t (unsigned long) section->sh_entsize);\n+\t section->sh_entsize);\n goto exit_point;\n }\n \n@@ -6615,7 +6617,7 @@ get_32bit_elf_symbols (Filedata * filedata,\n shndx = NULL;\n for (entry = filedata->symtab_shndx_list; entry != NULL; entry = entry->next)\n {\n- if (entry->hdr->sh_link != (unsigned long) (section - filedata->section_headers))\n+ if (entry->hdr->sh_link != (size_t) (section - filedata->section_headers))\n \tcontinue;\n \n if (shndx != NULL)\n@@ -6634,10 +6636,10 @@ get_32bit_elf_symbols (Filedata * filedata,\n /* PR17531: file: heap-buffer-overflow */\n if (entry->hdr->sh_size / sizeof (Elf_External_Sym_Shndx) < number)\n \t{\n-\t error (_(\"Index section %s has an sh_size of 0x%lx - expected 0x%lx\\n\"),\n+\t error (_(\"Index section %s has an sh_size of %#\" PRIx64 \" - expected %#\" PRIx64 \"\\n\"),\n \t\t printable_section_name (filedata, entry->hdr),\n-\t\t (unsigned long) entry->hdr->sh_size,\n-\t\t (unsigned long) section->sh_size);\n+\t\t entry->hdr->sh_size,\n+\t\t section->sh_size);\n \t goto exit_point;\n \t}\n }\n@@ -6646,8 +6648,7 @@ get_32bit_elf_symbols (Filedata * filedata,\n \n if (isyms == NULL)\n {\n- error (_(\"Out of memory reading %lu symbols\\n\"),\n-\t (unsigned long) number);\n+ error (_(\"Out of memory reading %\" PRIu64 \" symbols\\n\"), number);\n goto exit_point;\n }\n \n@@ -6677,11 +6678,11 @@ get_32bit_elf_symbols (Filedata * filedata,\n }\n \n static Elf_Internal_Sym *\n-get_64bit_elf_symbols (Filedata * filedata,\n-\t\t Elf_Internal_Shdr * section,\n-\t\t unsigned long * num_syms_return)\n+get_64bit_elf_symbols (Filedata *filedata,\n+\t\t Elf_Internal_Shdr *section,\n+\t\t uint64_t *num_syms_return)\n {\n- unsigned long number = 0;\n+ uint64_t number = 0;\n Elf64_External_Sym * esyms = NULL;\n Elf_External_Sym_Shndx * shndx = NULL;\n Elf_Internal_Sym * isyms = NULL;\n@@ -6699,17 +6700,17 @@ get_64bit_elf_symbols (Filedata * filedata,\n /* Run some sanity checks first. */\n if (section->sh_entsize == 0 || section->sh_entsize > section->sh_size)\n {\n- error (_(\"Section %s has an invalid sh_entsize of 0x%lx\\n\"),\n+ error (_(\"Section %s has an invalid sh_entsize of %#\" PRIx64 \"\\n\"),\n \t printable_section_name (filedata, section),\n-\t (unsigned long) section->sh_entsize);\n+\t section->sh_entsize);\n goto exit_point;\n }\n \n if (section->sh_size > filedata->file_size)\n {\n- error (_(\"Section %s has an invalid sh_size of 0x%lx\\n\"),\n+ error (_(\"Section %s has an invalid sh_size of %#\" PRIx64 \"\\n\"),\n \t printable_section_name (filedata, section),\n-\t (unsigned long) section->sh_size);\n+\t section->sh_size);\n goto exit_point;\n }\n \n@@ -6717,10 +6718,11 @@ get_64bit_elf_symbols (Filedata * filedata,\n \n if (number * sizeof (Elf64_External_Sym) > section->sh_size + 1)\n {\n- error (_(\"Size (0x%lx) of section %s is not a multiple of its sh_entsize (0x%lx)\\n\"),\n-\t (unsigned long) section->sh_size,\n+ error (_(\"Size (%#\" PRIx64 \") of section %s \"\n+\t \"is not a multiple of its sh_entsize (%#\" PRIx64 \")\\n\"),\n+\t section->sh_size,\n \t printable_section_name (filedata, section),\n-\t (unsigned long) section->sh_entsize);\n+\t section->sh_entsize);\n goto exit_point;\n }\n \n@@ -6732,7 +6734,7 @@ get_64bit_elf_symbols (Filedata * filedata,\n shndx = NULL;\n for (entry = filedata->symtab_shndx_list; entry != NULL; entry = entry->next)\n {\n- if (entry->hdr->sh_link != (unsigned long) (section - filedata->section_headers))\n+ if (entry->hdr->sh_link != (size_t) (section - filedata->section_headers))\n \tcontinue;\n \n if (shndx != NULL)\n@@ -6751,10 +6753,10 @@ get_64bit_elf_symbols (Filedata * filedata,\n /* PR17531: file: heap-buffer-overflow */\n if (entry->hdr->sh_size / sizeof (Elf_External_Sym_Shndx) < number)\n \t{\n-\t error (_(\"Index section %s has an sh_size of 0x%lx - expected 0x%lx\\n\"),\n+\t error (_(\"Index section %s has an sh_size of %#\" PRIx64 \" - expected %#\" PRIx64 \"\\n\"),\n \t\t printable_section_name (filedata, entry->hdr),\n-\t\t (unsigned long) entry->hdr->sh_size,\n-\t\t (unsigned long) section->sh_size);\n+\t\t entry->hdr->sh_size,\n+\t\t section->sh_size);\n \t goto exit_point;\n \t}\n }\n@@ -6763,8 +6765,7 @@ get_64bit_elf_symbols (Filedata * filedata,\n \n if (isyms == NULL)\n {\n- error (_(\"Out of memory reading %lu symbols\\n\"),\n-\t (unsigned long) number);\n+ error (_(\"Out of memory reading %\" PRIu64 \" symbols\\n\"), number);\n goto exit_point;\n }\n \n@@ -6798,7 +6799,7 @@ get_64bit_elf_symbols (Filedata * filedata,\n static Elf_Internal_Sym *\n get_elf_symbols (Filedata *filedata,\n \t\t Elf_Internal_Shdr *section,\n-\t\t unsigned long *num_syms_return)\n+\t\t uint64_t *num_syms_return)\n {\n if (is_32bit_elf)\n return get_32bit_elf_symbols (filedata, section, num_syms_return);\n@@ -7183,12 +7184,12 @@ process_section_headers (Filedata * filedata)\n \tprintf (_(\"In linked file '%s': \"), filedata->file_name);\n if (! filedata->is_separate || process_links)\n \tprintf (ngettext (\"There is %d section header, \"\n-\t\t\t \"starting at offset 0x%lx:\\n\",\n+\t\t\t \"starting at offset %#\" PRIx64 \":\\n\",\n \t\t\t \"There are %d section headers, \"\n-\t\t\t \"starting at offset 0x%lx:\\n\",\n+\t\t\t \"starting at offset %#\" PRIx64 \":\\n\",\n \t\t\t filedata->file_header.e_shnum),\n \t\tfiledata->file_header.e_shnum,\n-\t\t(unsigned long) filedata->file_header.e_shoff);\n+\t\tfiledata->file_header.e_shoff);\n }\n \n if (!get_section_headers (filedata, false))\n@@ -7854,8 +7855,8 @@ process_section_headers (Filedata * filedata)\n \n static bool\n get_symtab (Filedata *filedata, Elf_Internal_Shdr *symsec,\n-\t Elf_Internal_Sym **symtab, unsigned long *nsyms,\n-\t char **strtab, unsigned long *strtablen)\n+\t Elf_Internal_Sym **symtab, uint64_t *nsyms,\n+\t char **strtab, uint64_t *strtablen)\n {\n *strtab = NULL;\n *strtablen = 0;\n@@ -7922,7 +7923,7 @@ process_section_groups (Filedata * filedata)\n Elf_Internal_Shdr * symtab_sec;\n Elf_Internal_Shdr * strtab_sec;\n Elf_Internal_Sym * symtab;\n- unsigned long num_syms;\n+ uint64_t num_syms;\n char * strtab;\n size_t strtab_size;\n \n@@ -7988,8 +7989,7 @@ process_section_groups (Filedata * filedata)\n \n if (filedata->section_groups == NULL)\n {\n- error (_(\"Out of memory reading %lu groups\\n\"),\n-\t (unsigned long) filedata->group_count);\n+ error (_(\"Out of memory reading %zu groups\\n\"), filedata->group_count);\n return false;\n }\n \n@@ -8092,10 +8092,11 @@ process_section_groups (Filedata * filedata)\n \t /* PR 17531: file: loop. */\n \t if (section->sh_entsize > section->sh_size)\n \t {\n-\t error (_(\"Section %s has sh_entsize (0x%lx) which is larger than its size (0x%lx)\\n\"),\n+\t error (_(\"Section %s has sh_entsize (%#\" PRIx64 \")\"\n+\t\t \" which is larger than its size (%#\" PRIx64 \")\\n\"),\n \t\t printable_section_name (filedata, section),\n-\t\t (unsigned long) section->sh_entsize,\n-\t\t (unsigned long) section->sh_size);\n+\t\t section->sh_entsize,\n+\t\t section->sh_size);\n \t continue;\n \t }\n \n@@ -8226,7 +8227,7 @@ dump_ia64_vms_dynamic_fixups (Filedata * filedata,\n \t\t\t unsigned int strtab_sz)\n {\n Elf64_External_VMS_IMAGE_FIXUP * imfs;\n- long i;\n+ size_t i;\n const char * lib_name;\n \n imfs = get_data (NULL, filedata,\n@@ -8240,17 +8241,18 @@ dump_ia64_vms_dynamic_fixups (Filedata * filedata,\n lib_name = strtab + fixup->needed;\n else\n {\n- warn (_(\"corrupt library name index of 0x%lx found in dynamic entry\"),\n- (unsigned long) fixup->needed);\n+ warn (_(\"corrupt library name index of %#\" PRIx64\n+\t \" found in dynamic entry\"), fixup->needed);\n lib_name = \"???\";\n }\n \n- printf (_(\"\\nImage fixups for needed library #%d: %s - ident: %lx\\n\"),\n-\t (int) fixup->fixup_needed, lib_name, (long) fixup->needed_ident);\n+ printf (_(\"\\nImage fixups for needed library #%\" PRId64\n+\t \": %s - ident: %\" PRIx64 \"\\n\"),\n+\t fixup->fixup_needed, lib_name, fixup->needed_ident);\n printf\n (_(\"Seg Offset Type SymVec DataType\\n\"));\n \n- for (i = 0; i < (long) fixup->fixup_rela_cnt; i++)\n+ for (i = 0; i < (size_t) fixup->fixup_rela_cnt; i++)\n {\n unsigned int type;\n const char *rtype;\n@@ -8277,7 +8279,7 @@ static bool\n dump_ia64_vms_dynamic_relocs (Filedata * filedata, struct ia64_vms_dynimgrela *imgrela)\n {\n Elf64_External_VMS_IMAGE_RELA *imrs;\n- long i;\n+ size_t i;\n \n imrs = get_data (NULL, filedata,\n \t\t filedata->dynamic_addr + imgrela->img_rela_off,\n@@ -8290,7 +8292,7 @@ dump_ia64_vms_dynamic_relocs (Filedata * filedata, struct ia64_vms_dynimgrela *i\n printf\n (_(\"Seg Offset Type Addend Seg Sym Off\\n\"));\n \n- for (i = 0; i < (long) imgrela->img_rela_cnt; i++)\n+ for (i = 0; i < (size_t) imgrela->img_rela_cnt; i++)\n {\n unsigned int type;\n const char *rtype;\n@@ -8404,8 +8406,8 @@ static struct\n static bool\n process_relocs (Filedata * filedata)\n {\n- unsigned long rel_size;\n- unsigned long rel_offset;\n+ uint64_t rel_size;\n+ uint64_t rel_offset;\n \n if (!do_reloc)\n return true;\n@@ -8447,11 +8449,13 @@ process_relocs (Filedata * filedata)\n \t {\n \t if (filedata->is_separate)\n \t\tprintf\n-\t\t (_(\"\\nIn linked file '%s' section '%s' at offset 0x%lx contains %ld bytes:\\n\"),\n+\t\t (_(\"\\nIn linked file '%s' section '%s' at offset %#\" PRIx64\n+\t\t \" contains %\" PRId64 \" bytes:\\n\"),\n \t\t filedata->file_name, name, rel_offset, rel_size);\n \t else\n \t\tprintf\n-\t\t (_(\"\\n'%s' relocation section at offset 0x%lx contains %ld bytes:\\n\"),\n+\t\t (_(\"\\n'%s' relocation section at offset %#\" PRIx64\n+\t\t \" contains %\" PRId64 \" bytes:\\n\"),\n \t\t name, rel_offset, rel_size);\n \n \t dump_relocations (filedata,\n@@ -8481,7 +8485,7 @@ process_relocs (Filedata * filedata)\n else\n {\n Elf_Internal_Shdr * section;\n- unsigned long i;\n+ size_t i;\n bool found = false;\n \n for (i = 0, section = filedata->section_headers;\n@@ -8499,7 +8503,7 @@ process_relocs (Filedata * filedata)\n \t if (rel_size)\n \t {\n \t relocation_type rel_type;\n-\t unsigned long num_rela;\n+\t uint64_t num_rela;\n \n \t if (filedata->is_separate)\n \t\tprintf (_(\"\\nIn linked file '%s' relocation section \"),\n@@ -8513,8 +8517,10 @@ process_relocs (Filedata * filedata)\n \t\tprintf (\"'%s'\", printable_section_name (filedata, section));\n \n \t num_rela = rel_size / section->sh_entsize;\n-\t printf (ngettext (\" at offset 0x%lx contains %lu entry:\\n\",\n-\t\t\t\t\" at offset 0x%lx contains %lu entries:\\n\",\n+\t printf (ngettext (\" at offset %#\" PRIx64\n+\t\t\t\t\" contains %\" PRIu64 \" entry:\\n\",\n+\t\t\t\t\" at offset %#\" PRIx64\n+\t\t\t\t\" contains %\" PRId64 \" entries:\\n\",\n \t\t\t\tnum_rela),\n \t\t rel_offset, num_rela);\n \n@@ -8524,11 +8530,11 @@ process_relocs (Filedata * filedata)\n \t if (section->sh_link != 0\n \t\t && section->sh_link < filedata->file_header.e_shnum)\n \t\t{\n-\t\t Elf_Internal_Shdr * symsec;\n-\t\t Elf_Internal_Sym * symtab;\n-\t\t unsigned long nsyms;\n-\t\t unsigned long strtablen = 0;\n-\t\t char * strtab = NULL;\n+\t\t Elf_Internal_Shdr *symsec;\n+\t\t Elf_Internal_Sym *symtab;\n+\t\t uint64_t nsyms;\n+\t\t uint64_t strtablen = 0;\n+\t\t char *strtab = NULL;\n \n \t\t symsec = filedata->section_headers + section->sh_link;\n \t\t if (symsec->sh_type != SHT_SYMTAB\n@@ -8599,14 +8605,14 @@ struct absaddr\n name, if found, and the offset from the symbol to ADDR. */\n \n static void\n-find_symbol_for_address (Filedata * filedata,\n-\t\t\t Elf_Internal_Sym * symtab,\n-\t\t\t unsigned long nsyms,\n-\t\t\t const char * strtab,\n-\t\t\t unsigned long strtab_size,\n-\t\t\t struct absaddr addr,\n-\t\t\t const char ** symname,\n-\t\t\t uint64_t * offset)\n+find_symbol_for_address (Filedata *filedata,\n+\t\t\t Elf_Internal_Sym *symtab,\n+\t\t\t uint64_t nsyms,\n+\t\t\t const char *strtab,\n+\t\t\t uint64_t strtab_size,\n+\t\t\t struct absaddr addr,\n+\t\t\t const char **symname,\n+\t\t\t uint64_t *offset)\n {\n uint64_t dist = 0x100000;\n Elf_Internal_Sym * sym;\n@@ -8679,24 +8685,24 @@ struct ia64_unw_table_entry\n struct ia64_unw_aux_info\n {\n struct ia64_unw_table_entry * table;\t\t/* Unwind table. */\n- unsigned long table_len;\t/* Length of unwind table. */\n+ uint64_t table_len;\t/* Length of unwind table. */\n unsigned char * info;\t\t/* Unwind info. */\n- unsigned long info_size;\t/* Size of unwind info. */\n+ uint64_t info_size;\t/* Size of unwind info. */\n uint64_t info_addr;\t/* Starting address of unwind info. */\n uint64_t seg_base;\t/* Starting address of segment. */\n Elf_Internal_Sym * symtab;\t\t/* The symbol table. */\n- unsigned long nsyms;\t\t/* Number of symbols. */\n+ uint64_t nsyms;\t\t/* Number of symbols. */\n Elf_Internal_Sym * funtab;\t\t/* Sorted table of STT_FUNC symbols. */\n- unsigned long nfuns;\t\t/* Number of entries in funtab. */\n+ uint64_t nfuns;\t\t/* Number of entries in funtab. */\n char * strtab;\t\t/* The string table. */\n- unsigned long strtab_size;\t/* Size of string table. */\n+ uint64_t strtab_size;\t/* Size of string table. */\n };\n \n static bool\n dump_ia64_unwind (Filedata * filedata, struct ia64_unw_aux_info * aux)\n {\n struct ia64_unw_table_entry * tp;\n- unsigned long j, nfuns;\n+ size_t j, nfuns;\n int in_body;\n bool res = true;\n \n@@ -8726,15 +8732,15 @@ dump_ia64_unwind (Filedata * filedata, struct ia64_unw_aux_info * aux)\n \t fputs (procname, stdout);\n \n \t if (offset)\n-\t printf (\"+%lx\", (unsigned long) offset);\n+\t printf (\"+%\" PRIx64, offset);\n \t}\n \n fputs (\">: [\", stdout);\n print_vma (tp->start.offset, PREFIX_HEX);\n fputc ('-', stdout);\n print_vma (tp->end.offset, PREFIX_HEX);\n- printf (\"], info at +0x%lx\\n\",\n-\t (unsigned long) (tp->info.offset - aux->seg_base));\n+ printf (\"], info at +0x%\" PRIx64 \"\\n\",\n+\t tp->info.offset - aux->seg_base);\n \n /* PR 17531: file: 86232b32. */\n if (aux->info == NULL)\n@@ -8745,8 +8751,8 @@ dump_ia64_unwind (Filedata * filedata, struct ia64_unw_aux_info * aux)\n \t{\n \t if (tp->info.section >= filedata->file_header.e_shnum)\n \t {\n-\t warn (_(\"Invalid section %u in table entry %ld\\n\"),\n-\t\t tp->info.section, (long) (tp - aux->table));\n+\t warn (_(\"Invalid section %u in table entry %td\\n\"),\n+\t\t tp->info.section, tp - aux->table);\n \t res = false;\n \t continue;\n \t }\n@@ -8757,8 +8763,8 @@ dump_ia64_unwind (Filedata * filedata, struct ia64_unw_aux_info * aux)\n if (offset >= aux->info_size\n \t || aux->info_size - offset < 8)\n \t{\n-\t warn (_(\"Invalid offset %lx in table entry %ld\\n\"),\n-\t\t(long) tp->info.offset, (long) (tp - aux->table));\n+\t warn (_(\"Invalid offset %\" PRIx64 \" in table entry %td\\n\"),\n+\t\ttp->info.offset, tp - aux->table);\n \t res = false;\n \t continue;\n \t}\n@@ -8798,7 +8804,7 @@ slurp_ia64_unwind_table (Filedata * filedata,\n \t\t\t struct ia64_unw_aux_info * aux,\n \t\t\t Elf_Internal_Shdr * sec)\n {\n- unsigned long size, nrelas, i;\n+ uint64_t size, nrelas, i;\n Elf_Internal_Phdr * seg;\n struct ia64_unw_table_entry * tep;\n Elf_Internal_Shdr * relsec;\n@@ -8904,7 +8910,8 @@ slurp_ia64_unwind_table (Filedata * filedata,\n \t /* PR 17531: file: 5bc8d9bf. */\n \t if (i >= aux->table_len)\n \t {\n-\t warn (_(\"Skipping reloc with overlarge offset: %lx\\n\"), i);\n+\t warn (_(\"Skipping reloc with overlarge offset: %#\" PRIx64 \"\\n\"),\n+\t\t i);\n \t continue;\n \t }\n \n@@ -8947,7 +8954,7 @@ ia64_process_unwind (Filedata * filedata)\n {\n Elf_Internal_Shdr * sec;\n Elf_Internal_Shdr * unwsec = NULL;\n- unsigned long i, unwcount = 0, unwstart = 0;\n+ uint64_t i, unwcount = 0, unwstart = 0;\n struct ia64_unw_aux_info aux;\n bool res = true;\n \n@@ -9082,9 +9089,9 @@ ia64_process_unwind (Filedata * filedata)\n \t else\n \t printf (\"'%s'\", printable_section_name (filedata, unwsec));\n \n-\t printf (_(\" at offset 0x%lx contains %lu entries:\\n\"),\n-\t\t (unsigned long) unwsec->sh_offset,\n-\t\t (unsigned long) (unwsec->sh_size / (3 * eh_addr_size)));\n+\t printf (_(\" at offset %#\" PRIx64 \" contains %\" PRIu64 \" entries:\\n\"),\n+\t\t unwsec->sh_offset,\n+\t\t unwsec->sh_size / (3 * eh_addr_size));\n \n \t if (slurp_ia64_unwind_table (filedata, & aux, unwsec)\n \t && aux.table_len > 0)\n@@ -9143,21 +9150,21 @@ struct hppa_unw_table_entry\n struct hppa_unw_aux_info\n {\n struct hppa_unw_table_entry * table;\t\t/* Unwind table. */\n- unsigned long table_len;\t/* Length of unwind table. */\n+ uint64_t table_len;\t/* Length of unwind table. */\n uint64_t seg_base;\t/* Starting address of segment. */\n Elf_Internal_Sym * symtab;\t/* The symbol table. */\n- unsigned long nsyms;\t\t/* Number of symbols. */\n+ uint64_t nsyms;\t\t/* Number of symbols. */\n Elf_Internal_Sym * funtab;\t/* Sorted table of STT_FUNC symbols. */\n- unsigned long nfuns;\t\t/* Number of entries in funtab. */\n+ uint64_t nfuns;\t\t/* Number of entries in funtab. */\n char * strtab;\t/* The string table. */\n- unsigned long strtab_size;\t/* Size of string table. */\n+ uint64_t strtab_size;\t/* Size of string table. */\n };\n \n static bool\n dump_hppa_unwind (Filedata * filedata, struct hppa_unw_aux_info * aux)\n {\n struct hppa_unw_table_entry * tp;\n- unsigned long j, nfuns;\n+ uint64_t j, nfuns;\n bool res = true;\n \n aux->funtab = xmalloc (aux->nsyms * sizeof (Elf_Internal_Sym));\n@@ -9183,7 +9190,7 @@ dump_hppa_unwind (Filedata * filedata, struct hppa_unw_aux_info * aux)\n \t fputs (procname, stdout);\n \n \t if (offset)\n-\t printf (\"+%lx\", (unsigned long) offset);\n+\t printf (\"+%\" PRIx64, offset);\n \t}\n \n fputs (\">: [\", stdout);\n@@ -9237,7 +9244,7 @@ slurp_hppa_unwind_table (Filedata * filedata,\n \t\t\t struct hppa_unw_aux_info * aux,\n \t\t\t Elf_Internal_Shdr * sec)\n {\n- unsigned long size, unw_ent_size, nentries, nrelas, i;\n+ uint64_t size, unw_ent_size, nentries, nrelas, i;\n Elf_Internal_Phdr * seg;\n struct hppa_unw_table_entry * tep;\n Elf_Internal_Shdr * relsec;\n@@ -9372,7 +9379,8 @@ slurp_hppa_unwind_table (Filedata * filedata,\n \t i = rp->r_offset / unw_ent_size;\n \t if (i >= aux->table_len)\n \t {\n-\t warn (_(\"Skipping reloc with overlarge offset: %lx\\n\"), i);\n+\t warn (_(\"Skipping reloc with overlarge offset: %#\" PRIx64 \"\\n\"),\n+\t\t i);\n \t continue;\n \t }\n \n@@ -9412,7 +9420,7 @@ hppa_process_unwind (Filedata * filedata)\n struct hppa_unw_aux_info aux;\n Elf_Internal_Shdr * unwsec = NULL;\n Elf_Internal_Shdr * sec;\n- unsigned long i;\n+ size_t i;\n bool res = true;\n \n if (filedata->string_table == NULL)\n@@ -9449,15 +9457,15 @@ hppa_process_unwind (Filedata * filedata)\n if (section_name_valid (filedata, sec)\n \t && streq (section_name (filedata, sec), \".PARISC.unwind\"))\n \t{\n-\t unsigned long num_unwind = sec->sh_size / 16;\n+\t uint64_t num_unwind = sec->sh_size / 16;\n \n-\t printf (ngettext (\"\\nUnwind section '%s' at offset 0x%lx \"\n-\t\t\t \"contains %lu entry:\\n\",\n-\t\t\t \"\\nUnwind section '%s' at offset 0x%lx \"\n-\t\t\t \"contains %lu entries:\\n\",\n+\t printf (ngettext (\"\\nUnwind section '%s' at offset %#\" PRIx64 \" \"\n+\t\t\t \"contains %\" PRIu64 \" entry:\\n\",\n+\t\t\t \"\\nUnwind section '%s' at offset %#\" PRIx64 \" \"\n+\t\t\t \"contains %\" PRIu64 \" entries:\\n\",\n \t\t\t num_unwind),\n \t\t printable_section_name (filedata, sec),\n-\t\t (unsigned long) sec->sh_offset,\n+\t\t sec->sh_offset,\n \t\t num_unwind);\n \n if (! slurp_hppa_unwind_table (filedata, &aux, sec))\n@@ -9485,7 +9493,7 @@ struct arm_section\n unsigned char * data;\t\t/* The unwind data. */\n Elf_Internal_Shdr * sec;\t\t/* The cached unwind section header. */\n Elf_Internal_Rela * rela;\t\t/* The cached relocations for this section. */\n- unsigned long nrelas;\t\t/* The number of relocations. */\n+ uint64_t nrelas;\t\t/* The number of relocations. */\n unsigned int rel_type;\t/* REL or RELA ? */\n Elf_Internal_Rela * next_rela;\t/* Cyclic pointer to the next reloc to process. */\n };\n@@ -9494,11 +9502,11 @@ struct arm_unw_aux_info\n {\n Filedata * filedata;\t\t/* The file containing the unwind sections. */\n Elf_Internal_Sym * symtab;\t\t/* The file's symbol table. */\n- unsigned long nsyms;\t\t/* Number of symbols. */\n+ uint64_t nsyms;\t\t/* Number of symbols. */\n Elf_Internal_Sym * funtab;\t\t/* Sorted table of STT_FUNC symbols. */\n- unsigned long nfuns;\t\t/* Number of these symbols. */\n+ uint64_t nfuns;\t\t/* Number of these symbols. */\n char * strtab;\t\t/* The file's string table. */\n- unsigned long strtab_size;\t/* Size of string table. */\n+ uint64_t strtab_size;\t/* Size of string table. */\n };\n \n static const char *\n@@ -9525,7 +9533,7 @@ arm_print_vma_and_name (Filedata * filedata,\n fputs (procname, stdout);\n \n if (sym_offset)\n-\tprintf (\"+0x%lx\", (unsigned long) sym_offset);\n+\tprintf (\"+0x%\" PRIx64, sym_offset);\n fputc ('>', stdout);\n }\n \n@@ -9656,8 +9664,8 @@ get_unwind_section_word (Filedata * filedata,\n \n if (rp->r_offset & 3)\n \t{\n-\t warn (_(\"Skipping unexpected relocation at offset 0x%lx\\n\"),\n-\t\t(unsigned long) rp->r_offset);\n+\t warn (_(\"Skipping unexpected relocation at offset %#\" PRIx64 \"\\n\"),\n+\t\trp->r_offset);\n \t continue;\n \t}\n \n@@ -9686,8 +9694,9 @@ get_unwind_section_word (Filedata * filedata,\n /* PR 17531 file: 027-1241568-0.004. */\n if (ELF32_R_SYM (rp->r_info) >= aux->nsyms)\n \t{\n-\t error (_(\"Bad symbol index in unwind relocation (%lu > %lu)\\n\"),\n-\t\t (unsigned long) ELF32_R_SYM (rp->r_info), aux->nsyms);\n+\t error (_(\"Bad symbol index in unwind relocation \"\n+\t\t \"(%\" PRIu64 \" > %\" PRIu64 \")\\n\"),\n+\t\t ELF32_R_SYM (rp->r_info), aux->nsyms);\n \t break;\n \t}\n \n@@ -9930,7 +9939,7 @@ decode_arm_unwind_bytecode (Filedata * filedata,\n \t{\n \t unsigned char buf[9];\n \t unsigned int i, len;\n-\t unsigned long offset;\n+\t uint64_t offset;\n \n \t for (i = 0; i < sizeof (buf); i++)\n \t {\n@@ -9948,7 +9957,7 @@ decode_arm_unwind_bytecode (Filedata * filedata,\n \t offset = read_leb128 (buf, buf + i + 1, false, &len, NULL);\n \t assert (len == i + 1);\n \t offset = offset * 4 + 0x204;\n-\t printf (\"vsp = vsp + %ld\", offset);\n+\t printf (\"vsp = vsp + %\" PRId64, offset);\n \t }\n \t}\n else if (op == 0xb3 || op == 0xc8 || op == 0xc9)\n@@ -10153,7 +10162,7 @@ decode_tic6x_unwind_bytecode (Filedata * filedata,\n \t{\n \t unsigned char buf[9];\n \t unsigned int i, len;\n-\t unsigned long offset;\n+\t uint64_t offset;\n \n \t for (i = 0; i < sizeof (buf); i++)\n \t {\n@@ -10171,7 +10180,7 @@ decode_tic6x_unwind_bytecode (Filedata * filedata,\n \t offset = read_leb128 (buf, buf + i + 1, false, &len, NULL);\n \t assert (len == i + 1);\n \t offset = offset * 8 + 0x408;\n-\t printf (_(\"sp = sp + %ld\"), offset);\n+\t printf (_(\"sp = sp + %\" PRId64), offset);\n \t}\n else if ((op & 0xf0) == 0xe0)\n \t{\n@@ -10382,7 +10391,7 @@ dump_arm_unwind (Filedata * filedata,\n {\n struct arm_section exidx_arm_sec, extab_arm_sec;\n unsigned int i, exidx_len;\n- unsigned long j, nfuns;\n+ uint64_t j, nfuns;\n bool res = true;\n \n memset (&exidx_arm_sec, 0, sizeof (exidx_arm_sec));\n@@ -10459,8 +10468,8 @@ dump_arm_unwind (Filedata * filedata,\n \t /* PR 18879 */\n \t if (table_offset > table_sec->sh_size)\n \t\t{\n-\t\t warn (_(\"Unwind entry contains corrupt offset (0x%lx) into section %s\\n\"),\n-\t\t\t(unsigned long) table_offset,\n+\t\t warn (_(\"Unwind entry contains corrupt offset (%#\" PRIx64 \") into section %s\\n\"),\n+\t\t\ttable_offset,\n \t\t\tprintable_section_name (filedata, table_sec));\n \t\t res = false;\n \t\t continue;\n@@ -10475,8 +10484,8 @@ dump_arm_unwind (Filedata * filedata,\n \n \t if (table_sec == NULL)\n \t {\n-\t warn (_(\"Could not locate .ARM.extab section containing 0x%lx.\\n\"),\n-\t\t (unsigned long) table);\n+\t warn (_(\"Could not locate .ARM.extab section containing %#\" PRIx64 \".\\n\"),\n+\t\t table);\n \t res = false;\n \t continue;\n \t }\n@@ -10504,7 +10513,7 @@ arm_process_unwind (Filedata * filedata)\n struct arm_unw_aux_info aux;\n Elf_Internal_Shdr *unwsec = NULL;\n Elf_Internal_Shdr *sec;\n- unsigned long i;\n+ size_t i;\n unsigned int sec_type;\n bool res = true;\n \n@@ -10557,14 +10566,14 @@ arm_process_unwind (Filedata * filedata)\n {\n \tif (sec->sh_type == sec_type)\n \t {\n-\t unsigned long num_unwind = sec->sh_size / (2 * eh_addr_size);\n-\t printf (ngettext (\"\\nUnwind section '%s' at offset 0x%lx \"\n-\t\t\t \"contains %lu entry:\\n\",\n-\t\t\t \"\\nUnwind section '%s' at offset 0x%lx \"\n-\t\t\t \"contains %lu entries:\\n\",\n+\t uint64_t num_unwind = sec->sh_size / (2 * eh_addr_size);\n+\t printf (ngettext (\"\\nUnwind section '%s' at offset %#\" PRIx64 \" \"\n+\t\t\t \"contains %\" PRIu64 \" entry:\\n\",\n+\t\t\t \"\\nUnwind section '%s' at offset %#\" PRIx64 \" \"\n+\t\t\t \"contains %\" PRIu64 \" entries:\\n\",\n \t\t\t num_unwind),\n \t\t printable_section_name (filedata, sec),\n-\t\t (unsigned long) sec->sh_offset,\n+\t\t sec->sh_offset,\n \t\t num_unwind);\n \n \t if (! dump_arm_unwind (filedata, &aux, sec))\n@@ -10724,7 +10733,7 @@ dynamic_section_parisc_val (Elf_Internal_Dyn * entry)\n {\n \tstatic struct\n \t{\n-\t long int bit;\n+\t unsigned int bit;\n \t const char * str;\n \t}\n \tflags[] =\n@@ -10893,8 +10902,8 @@ get_32bit_dynamic_section (Filedata * filedata)\n = (Elf_Internal_Dyn *) cmalloc (filedata->dynamic_nent, sizeof (* entry));\n if (filedata->dynamic_section == NULL)\n {\n- error (_(\"Out of memory allocating space for %lu dynamic entries\\n\"),\n-\t (unsigned long) filedata->dynamic_nent);\n+ error (_(\"Out of memory allocating space for %\" PRIu64 \" dynamic entries\\n\"),\n+\t filedata->dynamic_nent);\n free (edyn);\n return false;\n }\n@@ -10944,8 +10953,8 @@ get_64bit_dynamic_section (Filedata * filedata)\n = (Elf_Internal_Dyn *) cmalloc (filedata->dynamic_nent, sizeof (* entry));\n if (filedata->dynamic_section == NULL)\n {\n- error (_(\"Out of memory allocating space for %lu dynamic entries\\n\"),\n-\t (unsigned long) filedata->dynamic_nent);\n+ error (_(\"Out of memory allocating space for %\" PRIu64 \" dynamic entries\\n\"),\n+\t filedata->dynamic_nent);\n free (edyn);\n return false;\n }\n@@ -11066,10 +11075,10 @@ get_dynamic_data (Filedata * filedata, uint64_t number, unsigned int ent_size)\n return i_data;\n }\n \n-static unsigned long\n+static uint64_t\n get_num_dynamic_syms (Filedata * filedata)\n {\n- unsigned long num_of_syms = 0;\n+ uint64_t num_of_syms = 0;\n \n if (!do_histogram && (!do_using_dynamic || do_dyn_syms))\n return num_of_syms;\n@@ -11138,7 +11147,7 @@ get_num_dynamic_syms (Filedata * filedata)\n unsigned char nb[16];\n uint64_t i, maxchain = 0xffffffff, bitmaskwords;\n uint64_t buckets_vma;\n- unsigned long hn;\n+ uint64_t hn;\n \n if (fseek64 (filedata->handle,\n \t\t (filedata->archive_file_offset\n@@ -11327,7 +11336,7 @@ process_dynamic_section (Filedata * filedata)\n /* Find the appropriate symbol table. */\n if (filedata->dynamic_symbols == NULL || do_histogram)\n {\n- unsigned long num_of_syms;\n+ uint64_t num_of_syms;\n \n for (entry = filedata->dynamic_section;\n \t entry < filedata->dynamic_section + filedata->dynamic_nent;\n@@ -11435,7 +11444,7 @@ the .dynsym section doesn't match the DT_SYMTAB and DT_SYMENT tags\\n\"));\n \tif (filedata->dynamic_info[DT_STRTAB]\n \t && filedata->dynamic_info[DT_STRSZ])\n \t {\n-\t unsigned long offset;\n+\t uint64_t offset;\n \t uint64_t str_tab_len = filedata->dynamic_info[DT_STRSZ];\n \n \t offset = offset_from_vma (filedata,\n@@ -11467,7 +11476,7 @@ the .dynstr section doesn't match the DT_STRTAB and DT_STRSZ tags\\n\"));\n /* And find the syminfo section if available. */\n if (filedata->dynamic_syminfo == NULL)\n {\n- unsigned long syminsz = 0;\n+ uint64_t syminsz = 0;\n \n for (entry = filedata->dynamic_section;\n \t entry < filedata->dynamic_section + filedata->dynamic_nent;\n@@ -11511,9 +11520,9 @@ the .dynstr section doesn't match the DT_STRTAB and DT_STRSZ tags\\n\"));\n \t filedata->dynamic_syminfo = (Elf_Internal_Syminfo *) malloc (syminsz);\n \t if (filedata->dynamic_syminfo == NULL)\n \t {\n-\t error (_(\"Out of memory allocating %lu bytes \"\n-\t\t \"for dynamic symbol info\\n\"),\n-\t\t (unsigned long) syminsz);\n+\t error (_(\"Out of memory allocating %\" PRIu64\n+\t\t \" bytes for dynamic symbol info\\n\"),\n+\t\t syminsz);\n \t return false;\n \t }\n \n@@ -11535,18 +11544,18 @@ the .dynstr section doesn't match the DT_STRTAB and DT_STRSZ tags\\n\"));\n if (do_dynamic && filedata->dynamic_addr)\n {\n if (filedata->is_separate)\n-\tprintf (ngettext (\"\\nIn linked file '%s' the dynamic section at offset 0x%lx contains %lu entry:\\n\",\n-\t\t\t \"\\nIn linked file '%s' the dynamic section at offset 0x%lx contains %lu entries:\\n\",\n-\t\t\t (unsigned long) filedata->dynamic_nent),\n+\tprintf (ngettext (\"\\nIn linked file '%s' the dynamic section at offset %#\" PRIx64 \" contains %\" PRIu64 \" entry:\\n\",\n+\t\t\t \"\\nIn linked file '%s' the dynamic section at offset %#\" PRIx64 \" contains %\" PRIu64 \" entries:\\n\",\n+\t\t\t filedata->dynamic_nent),\n \t\tfiledata->file_name,\n \t\tfiledata->dynamic_addr,\n-\t\t(unsigned long) filedata->dynamic_nent);\n+\t\tfiledata->dynamic_nent);\n else\n-\tprintf (ngettext (\"\\nDynamic section at offset 0x%lx contains %lu entry:\\n\",\n-\t\t\t \"\\nDynamic section at offset 0x%lx contains %lu entries:\\n\",\n-\t\t\t (unsigned long) filedata->dynamic_nent),\n+\tprintf (ngettext (\"\\nDynamic section at offset %#\" PRIx64 \" contains %\" PRId64 \" entry:\\n\",\n+\t\t\t \"\\nDynamic section at offset %#\" PRIx64 \" contains %\" PRIu64 \" entries:\\n\",\n+\t\t\t filedata->dynamic_nent),\n \t\tfiledata->dynamic_addr,\n-\t\t(unsigned long) filedata->dynamic_nent);\n+\t\tfiledata->dynamic_nent);\n }\n if (do_dynamic)\n printf (_(\" Tag Type Name/Value\\n\"));\n@@ -11624,7 +11633,7 @@ the .dynstr section doesn't match the DT_STRTAB and DT_STRSZ tags\\n\"));\n \t\tprintf (_(\" None\\n\"));\n \t else\n \t\t{\n-\t\t unsigned long int val = entry->d_un.d_val;\n+\t\t uint64_t val = entry->d_un.d_val;\n \n \t\t if (val & DTF_1_PARINIT)\n \t\t {\n@@ -11637,7 +11646,7 @@ the .dynstr section doesn't match the DT_STRTAB and DT_STRSZ tags\\n\"));\n \t\t val ^= DTF_1_CONFEXP;\n \t\t }\n \t\t if (val != 0)\n-\t\t printf (\" %lx\", val);\n+\t\t printf (\" %\" PRIx64, val);\n \t\t puts (\"\");\n \t\t}\n \t }\n@@ -11652,7 +11661,7 @@ the .dynstr section doesn't match the DT_STRTAB and DT_STRSZ tags\\n\"));\n \t\tprintf (_(\" None\\n\"));\n \t else\n \t\t{\n-\t\t unsigned long int val = entry->d_un.d_val;\n+\t\t uint64_t val = entry->d_un.d_val;\n \n \t\t if (val & DF_P1_LAZYLOAD)\n \t\t {\n@@ -11665,7 +11674,7 @@ the .dynstr section doesn't match the DT_STRTAB and DT_STRSZ tags\\n\"));\n \t\t val ^= DF_P1_GROUPPERM;\n \t\t }\n \t\t if (val != 0)\n-\t\t printf (\" %lx\", val);\n+\t\t printf (\" %\" PRIx64, val);\n \t\t puts (\"\");\n \t\t}\n \t }\n@@ -11679,7 +11688,7 @@ the .dynstr section doesn't match the DT_STRTAB and DT_STRSZ tags\\n\"));\n \t\tprintf (_(\" None\\n\"));\n \t else\n \t\t{\n-\t\t unsigned long int val = entry->d_un.d_val;\n+\t\t uint64_t val = entry->d_un.d_val;\n \n \t\t if (val & DF_1_NOW)\n \t\t {\n@@ -11837,7 +11846,7 @@ the .dynstr section doesn't match the DT_STRTAB and DT_STRSZ tags\\n\"));\n \t\t val ^= DF_1_NOCOMMON;\n \t\t }\n \t\t if (val != 0)\n-\t\t printf (\" %lx\", val);\n+\t\t printf (\" %\" PRIx64, val);\n \t\t puts (\"\");\n \t\t}\n \t }\n@@ -11992,8 +12001,8 @@ the .dynstr section doesn't match the DT_STRTAB and DT_STRSZ tags\\n\"));\n \t tmp = gmtime (&atime);\n \t /* PR 17533 file: 041-1244816-0.004. */\n \t if (tmp == NULL)\n-\t\tprintf (_(\"tm_year + 1900, tmp->tm_mon + 1, tmp->tm_mday,\n@@ -12019,7 +12028,7 @@ the .dynstr section doesn't match the DT_STRTAB and DT_STRSZ tags\\n\"));\n \t\tprintf (_(\" None\\n\"));\n \t else\n \t\t{\n-\t\t unsigned long int val = entry->d_un.d_val;\n+\t\t uint64_t val = entry->d_un.d_val;\n \n \t\t if (val & DF_GNU_1_UNIQUE)\n \t\t {\n@@ -12027,7 +12036,7 @@ the .dynstr section doesn't match the DT_STRTAB and DT_STRSZ tags\\n\"));\n \t\t val ^= DF_GNU_1_UNIQUE;\n \t\t }\n \t\t if (val != 0)\n-\t\t printf (\" %lx\", val);\n+\t\t printf (\" %\" PRIx64, val);\n \t\t puts (\"\");\n \t\t}\n \t }\n@@ -12128,8 +12137,8 @@ process_version_sections (Filedata * filedata)\n \tcase SHT_GNU_verdef:\n \t {\n \t Elf_External_Verdef * edefs;\n-\t unsigned long idx;\n-\t unsigned long cnt;\n+\t size_t idx;\n+\t size_t cnt;\n \t char * endbuf;\n \n \t found = true;\n@@ -12151,8 +12160,8 @@ process_version_sections (Filedata * filedata)\n \t\t section->sh_info);\n \n \t printf (_(\" Addr: 0x%016\" PRIx64), section->sh_addr);\n-\t printf (_(\" Offset: %#08lx Link: %u (%s)\\n\"),\n-\t\t (unsigned long) section->sh_offset, section->sh_link,\n+\t printf (_(\" Offset: 0x%08\" PRIx64 \" Link: %u (%s)\\n\"),\n+\t\t section->sh_offset, section->sh_link,\n \t\t printable_section_name_from_index (filedata, section->sh_link));\n \n \t edefs = (Elf_External_Verdef *)\n@@ -12169,7 +12178,7 @@ process_version_sections (Filedata * filedata)\n \t\tElf_Internal_Verdef ent;\n \t\tElf_External_Verdaux * eaux;\n \t\tElf_Internal_Verdaux aux;\n-\t\tunsigned long isum;\n+\t\tsize_t isum;\n \t\tint j;\n \n \t\tvstart = ((char *) edefs) + idx;\n@@ -12186,7 +12195,7 @@ process_version_sections (Filedata * filedata)\n \t\tent.vd_aux = BYTE_GET (edef->vd_aux);\n \t\tent.vd_next = BYTE_GET (edef->vd_next);\n \n-\t\tprintf (_(\" %#06lx: Rev: %d Flags: %s\"),\n+\t\tprintf (_(\" %#06zx: Rev: %d Flags: %s\"),\n \t\t\tidx, ent.vd_version, get_ver_flags (ent.vd_flags));\n \n \t\tprintf (_(\" Index: %d Cnt: %d \"),\n@@ -12238,11 +12247,11 @@ process_version_sections (Filedata * filedata)\n \t\t aux.vda_next = BYTE_GET (eaux->vda_next);\n \n \t\t if (valid_dynamic_name (filedata, aux.vda_name))\n-\t\t printf (_(\" %#06lx: Parent %d: %s\\n\"),\n+\t\t printf (_(\" %#06zx: Parent %d: %s\\n\"),\n \t\t\t isum, j,\n \t\t\t get_dynamic_name (filedata, aux.vda_name));\n \t\t else\n-\t\t printf (_(\" %#06lx: Parent %d, name index: %ld\\n\"),\n+\t\t printf (_(\" %#06zx: Parent %d, name index: %ld\\n\"),\n \t\t\t isum, j, aux.vda_name);\n \t\t }\n \n@@ -12274,8 +12283,8 @@ process_version_sections (Filedata * filedata)\n \tcase SHT_GNU_verneed:\n \t {\n \t Elf_External_Verneed * eneed;\n-\t unsigned long idx;\n-\t unsigned long cnt;\n+\t size_t idx;\n+\t size_t cnt;\n \t char * endbuf;\n \n \t found = true;\n@@ -12297,8 +12306,8 @@ process_version_sections (Filedata * filedata)\n \t\t section->sh_info);\n \n \t printf (_(\" Addr: 0x%016\" PRIx64), section->sh_addr);\n-\t printf (_(\" Offset: %#08lx Link: %u (%s)\\n\"),\n-\t\t (unsigned long) section->sh_offset, section->sh_link,\n+\t printf (_(\" Offset: 0x%08\" PRIx64 \" Link: %u (%s)\\n\"),\n+\t\t section->sh_offset, section->sh_link,\n \t\t printable_section_name_from_index (filedata, section->sh_link));\n \n \t eneed = (Elf_External_Verneed *) get_data (NULL, filedata,\n@@ -12313,7 +12322,7 @@ process_version_sections (Filedata * filedata)\n \t {\n \t\tElf_External_Verneed * entry;\n \t\tElf_Internal_Verneed ent;\n-\t\tunsigned long isum;\n+\t\tsize_t isum;\n \t\tint j;\n \t\tchar * vstart;\n \n@@ -12329,7 +12338,7 @@ process_version_sections (Filedata * filedata)\n \t\tent.vn_aux = BYTE_GET (entry->vn_aux);\n \t\tent.vn_next = BYTE_GET (entry->vn_next);\n \n-\t\tprintf (_(\" %#06lx: Version: %d\"), idx, ent.vn_version);\n+\t\tprintf (_(\" %#06zx: Version: %d\"), idx, ent.vn_version);\n \n \t\tif (valid_dynamic_name (filedata, ent.vn_file))\n \t\t printf (_(\" File: %s\"),\n@@ -12360,10 +12369,10 @@ process_version_sections (Filedata * filedata)\n \t\t aux.vna_next = BYTE_GET (eaux->vna_next);\n \n \t\t if (valid_dynamic_name (filedata, aux.vna_name))\n-\t\t printf (_(\" %#06lx: Name: %s\"),\n+\t\t printf (_(\" %#06zx: Name: %s\"),\n \t\t\t isum, get_dynamic_name (filedata, aux.vna_name));\n \t\t else\n-\t\t printf (_(\" %#06lx: Name index: %lx\"),\n+\t\t printf (_(\" %#06zx: Name index: %lx\"),\n \t\t\t isum, aux.vna_name);\n \n \t\t printf (_(\" Flags: %s Version: %d\\n\"),\n@@ -12409,15 +12418,15 @@ process_version_sections (Filedata * filedata)\n \tcase SHT_GNU_versym:\n \t {\n \t Elf_Internal_Shdr * link_section;\n-\t size_t total;\n+\t uint64_t total;\n \t unsigned int cnt;\n \t unsigned char * edata;\n \t unsigned short * data;\n \t char * strtab;\n \t Elf_Internal_Sym * symbols;\n \t Elf_Internal_Shdr * string_sec;\n-\t unsigned long num_syms;\n-\t long off;\n+\t uint64_t num_syms;\n+\t uint64_t off;\n \n \t if (section->sh_link >= filedata->file_header.e_shnum)\n \t break;\n@@ -12446,24 +12455,24 @@ process_version_sections (Filedata * filedata)\n \t }\n \n \t if (filedata->is_separate)\n-\t printf (ngettext (\"\\nIn linked file '%s' the version symbols section '%s' contains %lu entry:\\n\",\n-\t\t\t\t\"\\nIn linked file '%s' the version symbols section '%s' contains %lu entries:\\n\",\n+\t printf (ngettext (\"\\nIn linked file '%s' the version symbols section '%s' contains %\" PRIu64 \" entry:\\n\",\n+\t\t\t\t\"\\nIn linked file '%s' the version symbols section '%s' contains %\" PRIu64 \" entries:\\n\",\n \t\t\t\ttotal),\n \t\t filedata->file_name,\n \t\t printable_section_name (filedata, section),\n-\t\t (unsigned long) total);\n+\t\t total);\n \t else\n \t printf (ngettext (\"\\nVersion symbols section '%s' \"\n-\t\t\t\t\"contains %lu entry:\\n\",\n+\t\t\t\t\"contains %\" PRIu64 \" entry:\\n\",\n \t\t\t\t\"\\nVersion symbols section '%s' \"\n-\t\t\t\t\"contains %lu entries:\\n\",\n+\t\t\t\t\"contains %\" PRIu64 \" entries:\\n\",\n \t\t\t\ttotal),\n \t\t printable_section_name (filedata, section),\n-\t\t (unsigned long) total);\n+\t\t total);\n \n \t printf (_(\" Addr: 0x%016\" PRIx64), section->sh_addr);\n-\t printf (_(\" Offset: %#08lx Link: %u (%s)\\n\"),\n-\t\t (unsigned long) section->sh_offset, section->sh_link,\n+\t printf (_(\" Offset: 0x%08\" PRIx64 \" Link: %u (%s)\\n\"),\n+\t\t section->sh_offset, section->sh_link,\n \t\t printable_section_name (filedata, link_section));\n \n \t off = offset_from_vma (filedata,\n@@ -12512,7 +12521,7 @@ process_version_sections (Filedata * filedata)\n \n \t\t /* If this index value is greater than the size of the symbols\n \t\t array, break to avoid an out-of-bounds read. */\n-\t\t if ((unsigned long)(cnt + j) >= num_syms)\n+\t\t if (cnt + j >= num_syms)\n \t\t {\n \t\t warn (_(\"invalid index into symbol array\\n\"));\n \t\t break;\n@@ -12522,7 +12531,7 @@ process_version_sections (Filedata * filedata)\n \t\t if (filedata->version_info[DT_VERSIONTAGIDX (DT_VERNEED)])\n \t\t\t{\n \t\t\t Elf_Internal_Verneed ivn;\n-\t\t\t unsigned long offset;\n+\t\t\t uint64_t offset;\n \n \t\t\t offset = offset_from_vma\n \t\t\t (filedata,\n@@ -12534,7 +12543,7 @@ process_version_sections (Filedata * filedata)\n \t\t\t Elf_Internal_Vernaux ivna;\n \t\t\t Elf_External_Verneed evn;\n \t\t\t Elf_External_Vernaux evna;\n-\t\t\t unsigned long a_off;\n+\t\t\t uint64_t a_off;\n \n \t\t\t if (get_data (&evn, filedata, offset, sizeof (evn), 1,\n \t\t\t\t\t _(\"version need\")) == NULL)\n@@ -12585,7 +12594,7 @@ process_version_sections (Filedata * filedata)\n \t\t\t{\n \t\t\t Elf_Internal_Verdef ivd;\n \t\t\t Elf_External_Verdef evd;\n-\t\t\t unsigned long offset;\n+\t\t\t uint64_t offset;\n \n \t\t\t offset = offset_from_vma\n \t\t\t (filedata,\n@@ -13017,18 +13026,18 @@ get_symbol_index_type (Filedata * filedata, unsigned int type)\n }\n \n static const char *\n-get_symbol_version_string (Filedata * filedata,\n-\t\t\t bool is_dynsym,\n-\t\t\t const char * strtab,\n-\t\t\t unsigned long int strtab_size,\n-\t\t\t unsigned int si,\n-\t\t\t Elf_Internal_Sym * psym,\n-\t\t\t enum versioned_symbol_info * sym_info,\n-\t\t\t unsigned short * vna_other)\n+get_symbol_version_string (Filedata *filedata,\n+\t\t\t bool is_dynsym,\n+\t\t\t const char *strtab,\n+\t\t\t size_t strtab_size,\n+\t\t\t unsigned int si,\n+\t\t\t Elf_Internal_Sym *psym,\n+\t\t\t enum versioned_symbol_info *sym_info,\n+\t\t\t unsigned short *vna_other)\n {\n unsigned char data[2];\n unsigned short vers_data;\n- unsigned long offset;\n+ uint64_t offset;\n unsigned short max_vd_ndx;\n \n if (!is_dynsym\n@@ -13067,7 +13076,7 @@ get_symbol_version_string (Filedata * filedata,\n Elf_Internal_Verdef ivd;\n Elf_Internal_Verdaux ivda;\n Elf_External_Verdaux evda;\n- unsigned long off;\n+ uint64_t off;\n \n off = offset_from_vma (filedata,\n \t\t\t filedata->version_info[DT_VERSIONTAGIDX (DT_VERDEF)],\n@@ -13131,7 +13140,7 @@ get_symbol_version_string (Filedata * filedata,\n \t\t\t\tsizeof evn);\n do\n \t{\n-\t unsigned long vna_off;\n+\t uint64_t vna_off;\n \n \t if (get_data (&evn, filedata, offset, sizeof (evn), 1,\n \t\t\t_(\"version need\")) == NULL)\n@@ -13213,7 +13222,7 @@ print_dynamic_symbol_size (uint64_t vma, int base)\n }\n \n static void\n-print_dynamic_symbol (Filedata *filedata, unsigned long si,\n+print_dynamic_symbol (Filedata *filedata, uint64_t si,\n \t\t Elf_Internal_Sym *symtab,\n \t\t Elf_Internal_Shdr *section,\n \t\t char *strtab, size_t strtab_size)\n@@ -13225,7 +13234,7 @@ print_dynamic_symbol (Filedata *filedata, unsigned long si,\n const char * sstr;\n Elf_Internal_Sym *psym = symtab + si;\n \n- printf (\"%6ld: \", si);\n+ printf (\"%6\" PRId64 \": \", si);\n print_vma (psym->st_value, LONG_HEX);\n putchar (' ');\n print_dynamic_symbol_size (psym->st_size, sym_base);\n@@ -13306,7 +13315,7 @@ print_dynamic_symbol (Filedata *filedata, unsigned long si,\n /* Solaris binaries have been found to violate this requirement as\n \t well. Not sure if this is a bug or an ABI requirement. */\n && filedata->file_header.e_ident[EI_OSABI] != ELFOSABI_SOLARIS)\n- warn (_(\"local symbol %lu found at index >= %s's sh_info value of %u\\n\"),\n+ warn (_(\"local symbol %\" PRIu64 \" found at index >= %s's sh_info value of %u\\n\"),\n \t si, printable_section_name (filedata, section), section->sh_info);\n }\n \n@@ -13390,9 +13399,9 @@ display_lto_symtab (Filedata * filedata,\n \n if (section->sh_size > filedata->file_size)\n {\n- error (_(\"Section %s has an invalid sh_size of 0x%lx\\n\"),\n+ error (_(\"Section %s has an invalid sh_size of %#\" PRIx64 \"\\n\"),\n \t printable_section_name (filedata, section),\n-\t (unsigned long) section->sh_size);\n+\t section->sh_size);\n return false;\n }\n \n@@ -13586,20 +13595,24 @@ process_symbol_table (Filedata * filedata)\n && filedata->dynamic_strings != NULL\n && filedata->dynamic_symbols != NULL)\n {\n- unsigned long si;\n+ uint64_t si;\n \n if (filedata->is_separate)\n \t{\n-\t printf (ngettext (\"\\nIn linked file '%s' the dynamic symbol table contains %lu entry:\\n\",\n-\t\t\t \"\\nIn linked file '%s' the dynamic symbol table contains %lu entries:\\n\",\n+\t printf (ngettext (\"\\nIn linked file '%s' the dynamic symbol table\"\n+\t\t\t \" contains %\" PRIu64 \" entry:\\n\",\n+\t\t\t \"\\nIn linked file '%s' the dynamic symbol table\"\n+\t\t\t \" contains %\" PRIu64 \" entries:\\n\",\n \t\t\t filedata->num_dynamic_syms),\n \t\t filedata->file_name,\n \t\t filedata->num_dynamic_syms);\n \t}\n else\n \t{\n-\t printf (ngettext (\"\\nSymbol table for image contains %lu entry:\\n\",\n-\t\t\t \"\\nSymbol table for image contains %lu entries:\\n\",\n+\t printf (ngettext (\"\\nSymbol table for image contains %\" PRIu64\n+\t\t\t \" entry:\\n\",\n+\t\t\t \"\\nSymbol table for image contains %\" PRIu64\n+\t\t\t \" entries:\\n\",\n \t\t\t filedata->num_dynamic_syms),\n \t\t filedata->num_dynamic_syms);\n \t}\n@@ -13623,9 +13636,9 @@ process_symbol_table (Filedata * filedata)\n \t i++, section++)\n \t{\n \t char * strtab = NULL;\n-\t unsigned long int strtab_size = 0;\n+\t uint64_t strtab_size = 0;\n \t Elf_Internal_Sym * symtab;\n-\t unsigned long si, num_syms;\n+\t uint64_t si, num_syms;\n \n \t if ((section->sh_type != SHT_SYMTAB\n \t && section->sh_type != SHT_DYNSYM)\n@@ -13643,15 +13656,19 @@ process_symbol_table (Filedata * filedata)\n \t num_syms = section->sh_size / section->sh_entsize;\n \n \t if (filedata->is_separate)\n-\t printf (ngettext (\"\\nIn linked file '%s' symbol section '%s' contains %lu entry:\\n\",\n-\t\t\t \"\\nIn linked file '%s' symbol section '%s' contains %lu entries:\\n\",\n+\t printf (ngettext (\"\\nIn linked file '%s' symbol section '%s'\"\n+\t\t\t \" contains %\" PRIu64 \" entry:\\n\",\n+\t\t\t \"\\nIn linked file '%s' symbol section '%s'\"\n+\t\t\t \" contains %\" PRIu64 \" entries:\\n\",\n \t\t\t num_syms),\n \t\t filedata->file_name,\n \t\t printable_section_name (filedata, section),\n \t\t num_syms);\n \t else\n-\t printf (ngettext (\"\\nSymbol table '%s' contains %lu entry:\\n\",\n-\t\t\t \"\\nSymbol table '%s' contains %lu entries:\\n\",\n+\t printf (ngettext (\"\\nSymbol table '%s' contains %\" PRIu64\n+\t\t\t \" entry:\\n\",\n+\t\t\t \"\\nSymbol table '%s' contains %\" PRIu64\n+\t\t\t \" entries:\\n\",\n \t\t\t num_syms),\n \t\t printable_section_name (filedata, section),\n \t\t num_syms);\n@@ -13697,24 +13714,23 @@ process_symbol_table (Filedata * filedata)\n \n if (do_histogram && filedata->buckets != NULL)\n {\n- unsigned long * lengths;\n- unsigned long * counts;\n- unsigned long hn;\n+ uint64_t *lengths;\n+ uint64_t *counts;\n+ uint64_t hn;\n uint64_t si;\n- unsigned long maxlength = 0;\n- unsigned long nzero_counts = 0;\n- unsigned long nsyms = 0;\n+ uint64_t maxlength = 0;\n+ uint64_t nzero_counts = 0;\n+ uint64_t nsyms = 0;\n char *visited;\n \n printf (ngettext (\"\\nHistogram for bucket list length \"\n-\t\t\t\"(total of %lu bucket):\\n\",\n+\t\t\t\"(total of %\" PRIu64 \" bucket):\\n\",\n \t\t\t\"\\nHistogram for bucket list length \"\n-\t\t\t\"(total of %lu buckets):\\n\",\n-\t\t\t(unsigned long) filedata->nbuckets),\n-\t (unsigned long) filedata->nbuckets);\n+\t\t\t\"(total of %\" PRIu64 \" buckets):\\n\",\n+\t\t\tfiledata->nbuckets),\n+\t filedata->nbuckets);\n \n- lengths = (unsigned long *) calloc (filedata->nbuckets,\n-\t\t\t\t\t sizeof (*lengths));\n+ lengths = calloc (filedata->nbuckets, sizeof (*lengths));\n if (lengths == NULL)\n \t{\n \t error (_(\"Out of memory allocating space for histogram buckets\\n\"));\n@@ -13741,7 +13757,7 @@ process_symbol_table (Filedata * filedata)\n \t}\n free (visited);\n \n- counts = (unsigned long *) calloc (maxlength + 1, sizeof (*counts));\n+ counts = calloc (maxlength + 1, sizeof (*counts));\n if (counts == NULL)\n \t{\n \t free (lengths);\n@@ -13754,13 +13770,13 @@ process_symbol_table (Filedata * filedata)\n \n if (filedata->nbuckets > 0)\n \t{\n-\t unsigned long i;\n-\t printf (\" 0 %-10lu (%5.1f%%)\\n\",\n+\t uint64_t i;\n+\t printf (\" 0 %-10\" PRIu64 \" (%5.1f%%)\\n\",\n \t\t counts[0], (counts[0] * 100.0) / filedata->nbuckets);\n \t for (i = 1; i <= maxlength; ++i)\n \t {\n \t nzero_counts += counts[i] * i;\n-\t printf (\"%7lu %-10lu (%5.1f%%) %5.1f%%\\n\",\n+\t printf (\"%7\" PRIu64 \" %-10\" PRIu64 \" (%5.1f%%) %5.1f%%\\n\",\n \t\t i, counts[i], (counts[i] * 100.0) / filedata->nbuckets,\n \t\t (nzero_counts * 100.0) / nsyms);\n \t }\n@@ -13778,23 +13794,22 @@ process_symbol_table (Filedata * filedata)\n \n if (do_histogram && filedata->gnubuckets != NULL)\n {\n- unsigned long * lengths;\n- unsigned long * counts;\n- unsigned long hn;\n- unsigned long maxlength = 0;\n- unsigned long nzero_counts = 0;\n- unsigned long nsyms = 0;\n+ uint64_t *lengths;\n+ uint64_t *counts;\n+ uint64_t hn;\n+ uint64_t maxlength = 0;\n+ uint64_t nzero_counts = 0;\n+ uint64_t nsyms = 0;\n \n printf (ngettext (\"\\nHistogram for `%s' bucket list length \"\n-\t\t\t\"(total of %lu bucket):\\n\",\n+\t\t\t\"(total of %\" PRIu64 \" bucket):\\n\",\n \t\t\t\"\\nHistogram for `%s' bucket list length \"\n-\t\t\t\"(total of %lu buckets):\\n\",\n-\t\t\t(unsigned long) filedata->ngnubuckets),\n+\t\t\t\"(total of %\" PRIu64 \" buckets):\\n\",\n+\t\t\tfiledata->ngnubuckets),\n \t GNU_HASH_SECTION_NAME (filedata),\n-\t (unsigned long) filedata->ngnubuckets);\n+\t filedata->ngnubuckets);\n \n- lengths = (unsigned long *) calloc (filedata->ngnubuckets,\n-\t\t\t\t\t sizeof (*lengths));\n+ lengths = calloc (filedata->ngnubuckets, sizeof (*lengths));\n if (lengths == NULL)\n \t{\n \t error (_(\"Out of memory allocating space for gnu histogram buckets\\n\"));\n@@ -13820,7 +13835,7 @@ process_symbol_table (Filedata * filedata)\n \t nsyms += length;\n \t }\n \n- counts = (unsigned long *) calloc (maxlength + 1, sizeof (*counts));\n+ counts = calloc (maxlength + 1, sizeof (*counts));\n if (counts == NULL)\n \t{\n \t free (lengths);\n@@ -13833,13 +13848,13 @@ process_symbol_table (Filedata * filedata)\n \n if (filedata->ngnubuckets > 0)\n \t{\n-\t unsigned long j;\n-\t printf (\" 0 %-10lu (%5.1f%%)\\n\",\n+\t uint64_t j;\n+\t printf (\" 0 %-10\" PRIu64 \" (%5.1f%%)\\n\",\n \t\t counts[0], (counts[0] * 100.0) / filedata->ngnubuckets);\n \t for (j = 1; j <= maxlength; ++j)\n \t {\n \t nzero_counts += counts[j] * j;\n-\t printf (\"%7lu %-10lu (%5.1f%%) %5.1f%%\\n\",\n+\t printf (\"%7\" PRIu64 \" %-10\" PRIu64 \" (%5.1f%%) %5.1f%%\\n\",\n \t\t j, counts[j], (counts[j] * 100.0) / filedata->ngnubuckets,\n \t\t (nzero_counts * 100.0) / nsyms);\n \t }\n@@ -13890,17 +13905,17 @@ process_syminfo (Filedata * filedata)\n return false;\n \n if (filedata->is_separate)\n- printf (ngettext (\"\\nIn linked file '%s: the dynamic info segment at offset 0x%lx contains %d entry:\\n\",\n-\t\t \"\\nIn linked file '%s: the dynamic info segment at offset 0x%lx contains %d entries:\\n\",\n+ printf (ngettext (\"\\nIn linked file '%s: the dynamic info segment at offset %#\" PRIx64 \" contains %d entry:\\n\",\n+\t\t \"\\nIn linked file '%s: the dynamic info segment at offset %#\" PRIx64 \" contains %d entries:\\n\",\n \t\t filedata->dynamic_syminfo_nent),\n \t filedata->file_name,\n \t filedata->dynamic_syminfo_offset,\n \t filedata->dynamic_syminfo_nent);\n else\n- printf (ngettext (\"\\nDynamic info segment at offset 0x%lx \"\n-\t\t \"contains %d entry:\\n\",\n-\t\t \"\\nDynamic info segment at offset 0x%lx \"\n-\t\t \"contains %d entries:\\n\",\n+ printf (ngettext (\"\\nDynamic info segment at offset %#\" PRIx64\n+\t\t \" contains %d entry:\\n\",\n+\t\t \"\\nDynamic info segment at offset %#\" PRIx64\n+\t\t \" contains %d entries:\\n\",\n \t\t filedata->dynamic_syminfo_nent),\n \t filedata->dynamic_syminfo_offset,\n \t filedata->dynamic_syminfo_nent);\n@@ -13974,15 +13989,15 @@ process_syminfo (Filedata * filedata)\n discarded. */\n \n static bool\n-target_specific_reloc_handling (Filedata * filedata,\n-\t\t\t\tElf_Internal_Rela * reloc,\n-\t\t\t\tunsigned char * start,\n-\t\t\t\tunsigned char * end,\n-\t\t\t\tElf_Internal_Sym * symtab,\n-\t\t\t\tunsigned long num_syms)\n+target_specific_reloc_handling (Filedata *filedata,\n+\t\t\t\tElf_Internal_Rela *reloc,\n+\t\t\t\tunsigned char *start,\n+\t\t\t\tunsigned char *end,\n+\t\t\t\tElf_Internal_Sym *symtab,\n+\t\t\t\tuint64_t num_syms)\n {\n unsigned int reloc_type = 0;\n- unsigned long sym_index = 0;\n+ uint64_t sym_index = 0;\n \n if (reloc)\n {\n@@ -14014,8 +14029,8 @@ target_specific_reloc_handling (Filedata * filedata,\n \t case 23: /* R_MSP430X_GNU_SUB_ULEB128 */\n \t /* PR 21139. */\n \t if (sym_index >= num_syms)\n-\t error (_(\"MSP430 SYM_DIFF reloc contains invalid symbol index %lu\\n\"),\n-\t\t sym_index);\n+\t error (_(\"MSP430 SYM_DIFF reloc contains invalid symbol index\"\n+\t\t \" %\" PRIu64 \"\\n\"), sym_index);\n \t else\n \t saved_sym = symtab + sym_index;\n \t return true;\n@@ -14061,11 +14076,12 @@ target_specific_reloc_handling (Filedata * filedata,\n \t\t }\n \n \t\tif (leb_ret != 0 || reloc_size == 0 || reloc_size > 8)\n-\t\t error (_(\"MSP430 ULEB128 field at 0x%lx contains invalid \"\n-\t\t\t \"ULEB128 value\\n\"),\n-\t\t\t (long) reloc->r_offset);\n+\t\t error (_(\"MSP430 ULEB128 field at %#\" PRIx64\n+\t\t\t \" contains invalid ULEB128 value\\n\"),\n+\t\t\t reloc->r_offset);\n \t\telse if (sym_index >= num_syms)\n-\t\t error (_(\"MSP430 reloc contains invalid symbol index %lu\\n\"),\n+\t\t error (_(\"MSP430 reloc contains invalid symbol index \"\n+\t\t\t \"%\" PRIu64 \"\\n\"),\n \t\t\t sym_index);\n \t\telse\n \t\t {\n@@ -14076,8 +14092,9 @@ target_specific_reloc_handling (Filedata * filedata,\n \t\t byte_put (start + reloc->r_offset, value, reloc_size);\n \t\t else\n \t\t /* PR 21137 */\n-\t\t error (_(\"MSP430 sym diff reloc contains invalid offset: 0x%lx\\n\"),\n-\t\t\t (long) reloc->r_offset);\n+\t\t error (_(\"MSP430 sym diff reloc contains invalid offset: \"\n+\t\t\t \"%#\" PRIx64 \"\\n\"),\n+\t\t\t reloc->r_offset);\n \t\t }\n \n \t\tsaved_sym = NULL;\n@@ -14110,7 +14127,8 @@ target_specific_reloc_handling (Filedata * filedata,\n \t return true;\n \t case 33: /* R_MN10300_SYM_DIFF */\n \t if (sym_index >= num_syms)\n-\t error (_(\"MN10300_SYM_DIFF reloc contains invalid symbol index %lu\\n\"),\n+\t error (_(\"MN10300_SYM_DIFF reloc contains invalid symbol index \"\n+\t\t \"%\" PRIu64 \"\\n\"),\n \t\t sym_index);\n \t else\n \t saved_sym = symtab + sym_index;\n@@ -14124,7 +14142,8 @@ target_specific_reloc_handling (Filedata * filedata,\n \t\tuint64_t value;\n \n \t\tif (sym_index >= num_syms)\n-\t\t error (_(\"MN10300 reloc contains invalid symbol index %lu\\n\"),\n+\t\t error (_(\"MN10300 reloc contains invalid symbol index \"\n+\t\t\t \"%\" PRIu64 \"\\n\"),\n \t\t\t sym_index);\n \t\telse\n \t\t {\n@@ -14134,8 +14153,9 @@ target_specific_reloc_handling (Filedata * filedata,\n \t\t if (IN_RANGE (start, end, start + reloc->r_offset, reloc_size))\n \t\t byte_put (start + reloc->r_offset, value, reloc_size);\n \t\t else\n-\t\t error (_(\"MN10300 sym diff reloc contains invalid offset: 0x%lx\\n\"),\n-\t\t\t (long) reloc->r_offset);\n+\t\t error (_(\"MN10300 sym diff reloc contains invalid offset:\"\n+\t\t\t \" %#\" PRIx64 \"\\n\"),\n+\t\t\t reloc->r_offset);\n \t\t }\n \n \t\tsaved_sym = NULL;\n@@ -14167,8 +14187,8 @@ target_specific_reloc_handling (Filedata * filedata,\n \t case 0x80: /* R_RL78_SYM. */\n \t saved_sym1 = saved_sym2;\n \t if (sym_index >= num_syms)\n-\t error (_(\"RL78_SYM reloc contains invalid symbol index %lu\\n\"),\n-\t\t sym_index);\n+\t error (_(\"RL78_SYM reloc contains invalid symbol index \"\n+\t\t \"%\" PRIu64 \"\\n\"), sym_index);\n \t else\n \t {\n \t\tsaved_sym2 = symtab[sym_index].st_value;\n@@ -14186,8 +14206,9 @@ target_specific_reloc_handling (Filedata * filedata,\n \t if (IN_RANGE (start, end, start + reloc->r_offset, 4))\n \t byte_put (start + reloc->r_offset, value, 4);\n \t else\n-\t error (_(\"RL78 sym diff reloc contains invalid offset: 0x%lx\\n\"),\n-\t\t (long) reloc->r_offset);\n+\t error (_(\"RL78 sym diff reloc contains invalid offset: \"\n+\t\t \"%#\" PRIx64 \"\\n\"),\n+\t\t reloc->r_offset);\n \t value = 0;\n \t return true;\n \n@@ -14195,8 +14216,9 @@ target_specific_reloc_handling (Filedata * filedata,\n \t if (IN_RANGE (start, end, start + reloc->r_offset, 2))\n \t byte_put (start + reloc->r_offset, value, 2);\n \t else\n-\t error (_(\"RL78 sym diff reloc contains invalid offset: 0x%lx\\n\"),\n-\t\t (long) reloc->r_offset);\n+\t error (_(\"RL78 sym diff reloc contains invalid offset: \"\n+\t\t \"%#\" PRIx64 \"\\n\"),\n+\t\t reloc->r_offset);\n \t value = 0;\n \t return true;\n \n@@ -14965,7 +14987,7 @@ apply_relocations (Filedata *filedata,\n \t\t unsigned char *start,\n \t\t size_t size,\n \t\t void **relocs_return,\n-\t\t unsigned long *num_relocs_return)\n+\t\t uint64_t *num_relocs_return)\n {\n Elf_Internal_Shdr * relsec;\n unsigned char * end = start + size;\n@@ -14986,12 +15008,12 @@ apply_relocations (Filedata *filedata,\n ++relsec)\n {\n bool is_rela;\n- unsigned long num_relocs;\n+ uint64_t num_relocs;\n Elf_Internal_Rela * relocs;\n Elf_Internal_Rela * rp;\n Elf_Internal_Shdr * symsec;\n Elf_Internal_Sym * symtab;\n- unsigned long num_syms;\n+ uint64_t num_syms;\n Elf_Internal_Sym * sym;\n \n if ((relsec->sh_type != SHT_RELA && relsec->sh_type != SHT_REL)\n@@ -15035,7 +15057,7 @@ apply_relocations (Filedata *filedata,\n \t bool reloc_inplace = false;\n \t bool reloc_subtract = false;\n \t unsigned char *rloc;\n-\t unsigned long sym_index;\n+\t uint64_t sym_index;\n \n \t reloc_type = get_reloc_type (filedata, rp->r_info);\n \n@@ -15104,16 +15126,18 @@ apply_relocations (Filedata *filedata,\n \t rloc = start + rp->r_offset;\n \t if (!IN_RANGE (start, end, rloc, reloc_size))\n \t {\n-\t warn (_(\"skipping invalid relocation offset 0x%lx in section %s\\n\"),\n-\t\t (unsigned long) rp->r_offset,\n+\t warn (_(\"skipping invalid relocation offset %#\" PRIx64\n+\t\t \" in section %s\\n\"),\n+\t\t rp->r_offset,\n \t\t printable_section_name (filedata, section));\n \t continue;\n \t }\n \n-\t sym_index = (unsigned long) get_reloc_symindex (rp->r_info);\n+\t sym_index = get_reloc_symindex (rp->r_info);\n \t if (sym_index >= num_syms)\n \t {\n-\t warn (_(\"skipping invalid relocation symbol index 0x%lx in section %s\\n\"),\n+\t warn (_(\"skipping invalid relocation symbol index %#\" PRIx64\n+\t\t \" in section %s\\n\"),\n \t\t sym_index, printable_section_name (filedata, section));\n \t continue;\n \t }\n@@ -15136,10 +15160,10 @@ apply_relocations (Filedata *filedata,\n \t && ELF_ST_TYPE (sym->st_info) != STT_COMMON\n \t && ELF_ST_TYPE (sym->st_info) > STT_SECTION)\n \t {\n-\t warn (_(\"skipping unexpected symbol type %s in section %s relocation %ld\\n\"),\n+\t warn (_(\"skipping unexpected symbol type %s in section %s relocation %tu\\n\"),\n \t\t get_symbol_type (filedata, ELF_ST_TYPE (sym->st_info)),\n \t\t printable_section_name (filedata, relsec),\n-\t\t (long int)(rp - relocs));\n+\t\t rp - relocs);\n \t continue;\n \t }\n \n@@ -15443,7 +15467,7 @@ dump_section_as_strings (Elf_Internal_Shdr * section, Filedata * filedata)\n \t }\n \t else\n \t {\n-\t printf (\" [%6lx] \", (unsigned long) (data - start));\n+\t printf (\" [%6tx] \", data - start);\n \t }\n \n \t if (maxlen > 0)\n@@ -15660,7 +15684,7 @@ dump_section_as_bytes (Elf_Internal_Shdr *section,\n \n lbytes = (bytes > 16 ? 16 : bytes);\n \n- printf (\" 0x%8.8lx \", (unsigned long) addr);\n+ printf (\" 0x%8.8\" PRIx64 \" \", addr);\n \n for (j = 0; j < 16; j++)\n \t{\n@@ -16079,7 +16103,7 @@ get_build_id (void * data)\n {\n Filedata * filedata = (Filedata *) data;\n Elf_Internal_Shdr * shdr;\n- unsigned long i;\n+ size_t i;\n \n /* Iterate through notes to find note.gnu.build-id.\n FIXME: Only the first note in any note section is examined. */\n@@ -16186,7 +16210,7 @@ malformed note encountered in section %s whilst scanning for build-id note\\n\"),\n && startswith (inote.namedata, \"GNU\")\n && inote.type == NT_GNU_BUILD_ID)\n {\n- unsigned long j;\n+ size_t j;\n char * build_id;\n \n build_id = malloc (inote.descsz * 2 + 1);\n@@ -16517,7 +16541,7 @@ display_tag_value (signed int tag,\n \t\t unsigned char * p,\n \t\t const unsigned char * const end)\n {\n- unsigned long val;\n+ uint64_t val;\n \n if (tag > 0)\n printf (\" Tag_unknown_%d: \", tag);\n@@ -16547,7 +16571,7 @@ display_tag_value (signed int tag,\n else\n {\n READ_ULEB (val, p, end);\n- printf (\"%ld (0x%lx)\\n\", val, val);\n+ printf (\"%\" PRId64 \" (0x%\" PRIx64 \")\\n\", val, val);\n }\n \n assert (p <= end);\n@@ -17679,7 +17703,7 @@ display_tic6x_attribute (unsigned char * p,\n static void\n display_raw_attribute (unsigned char * p, unsigned char const * const end)\n {\n- unsigned long addr = 0;\n+ uint64_t addr = 0;\n size_t bytes = end - p;\n \n assert (end >= p);\n@@ -17689,7 +17713,7 @@ display_raw_attribute (unsigned char * p, unsigned char const * const end)\n int k;\n int lbytes = (bytes > 16 ? 16 : bytes);\n \n- printf (\" 0x%8.8lx \", addr);\n+ printf (\" 0x%8.8\" PRIx64 \" \", addr);\n \n for (j = 0; j < 16; j++)\n \t{\n@@ -17723,10 +17747,10 @@ display_raw_attribute (unsigned char * p, unsigned char const * const end)\n \n static unsigned char *\n display_msp430_attribute (unsigned char * p,\n-\t\t\t const unsigned char * const end)\n+\t\t\t const unsigned char * const end)\n {\n- unsigned int val;\n- unsigned int tag;\n+ uint64_t val;\n+ uint64_t tag;\n \n READ_ULEB (tag, p, end);\n \n@@ -17740,7 +17764,7 @@ display_msp430_attribute (unsigned char * p,\n \tcase 0: printf (_(\"None\\n\")); break;\n \tcase 1: printf (_(\"MSP430\\n\")); break;\n \tcase 2: printf (_(\"MSP430X\\n\")); break;\n-\tdefault: printf (\"??? (%d)\\n\", val); break;\n+\tdefault: printf (\"??? (%\" PRId64 \")\\n\", val); break;\n \t}\n break;\n \n@@ -17752,7 +17776,7 @@ display_msp430_attribute (unsigned char * p,\n \tcase 0: printf (_(\"None\\n\")); break;\n \tcase 1: printf (_(\"Small\\n\")); break;\n \tcase 2: printf (_(\"Large\\n\")); break;\n-\tdefault: printf (\"??? (%d)\\n\", val); break;\n+\tdefault: printf (\"??? (%\" PRId64 \")\\n\", val); break;\n \t}\n break;\n \n@@ -17765,12 +17789,12 @@ display_msp430_attribute (unsigned char * p,\n \tcase 1: printf (_(\"Small\\n\")); break;\n \tcase 2: printf (_(\"Large\\n\")); break;\n \tcase 3: printf (_(\"Restricted Large\\n\")); break;\n-\tdefault: printf (\"??? (%d)\\n\", val); break;\n+\tdefault: printf (\"??? (%\" PRId64 \")\\n\", val); break;\n \t}\n break;\n \n default:\n- printf (_(\" : \"), tag);\n+ printf (_(\" : \"), tag);\n \n if (tag & 1)\n \t{\n@@ -17792,7 +17816,7 @@ display_msp430_attribute (unsigned char * p,\n else\n \t{\n \t READ_ULEB (val, p, end);\n-\t printf (\"%d (0x%x)\\n\", val, val);\n+\t printf (\"%\" PRId64 \" (0x%\" PRIx64 \")\\n\", val, val);\n \t}\n break;\n }\n@@ -17808,7 +17832,7 @@ display_msp430_gnu_attribute (unsigned char * p,\n {\n if (tag == Tag_GNU_MSP430_Data_Region)\n {\n- unsigned int val;\n+ uint64_t val;\n \n printf (\" Tag_GNU_MSP430_Data_Region: \");\n READ_ULEB (val, p, end);\n@@ -17822,7 +17846,7 @@ display_msp430_gnu_attribute (unsigned char * p,\n \t printf (_(\"Lower Region Only\\n\"));\n \t break;\n \tdefault:\n-\t printf (\"??? (%u)\\n\", val);\n+\t printf (\"??? (%\" PRIu64 \")\\n\", val);\n \t}\n return p;\n }\n@@ -17850,8 +17874,8 @@ static unsigned char *\n display_riscv_attribute (unsigned char *p,\n \t\t\t const unsigned char * const end)\n {\n- unsigned int val;\n- unsigned int tag;\n+ uint64_t val;\n+ uint64_t tag;\n struct riscv_attr_tag_t *attr = NULL;\n unsigned i;\n \n@@ -17878,7 +17902,7 @@ display_riscv_attribute (unsigned char *p,\n case Tag_RISCV_priv_spec_minor:\n case Tag_RISCV_priv_spec_revision:\n READ_ULEB (val, p, end);\n- printf (_(\"%u\\n\"), val);\n+ printf (\"%\" PRIu64 \"\\n\", val);\n break;\n case Tag_RISCV_unaligned_access:\n READ_ULEB (val, p, end);\n@@ -17894,7 +17918,7 @@ display_riscv_attribute (unsigned char *p,\n break;\n case Tag_RISCV_stack_align:\n READ_ULEB (val, p, end);\n- printf (_(\"%u-bytes\\n\"), val);\n+ printf (_(\"%\" PRIu64 \"-bytes\\n\"), val);\n break;\n case Tag_RISCV_arch:\n p = display_tag_value (-1, p, end);\n@@ -17910,8 +17934,8 @@ static unsigned char *\n display_csky_attribute (unsigned char * p,\n \t\t\tconst unsigned char * const end)\n {\n- unsigned int tag;\n- unsigned int val;\n+ uint64_t tag;\n+ uint64_t val;\n READ_ULEB (tag, p, end);\n \n if (tag >= Tag_CSKY_MAX)\n@@ -17947,7 +17971,7 @@ display_csky_attribute (unsigned char * p,\n case Tag_CSKY_VDSP_VERSION:\n printf (\" Tag_CSKY_VDSP_VERSION:\\t\");\n READ_ULEB (val, p, end);\n- printf (\"VDSP Version %d\\n\", val);\n+ printf (\"VDSP Version %\" PRId64 \"\\n\", val);\n break;\n \n case Tag_CSKY_FPU_VERSION:\n@@ -18640,10 +18664,10 @@ process_mips_specific (Filedata * filedata)\n \t\t\t\t\t _(\"liblist section data\"));\n if (elib)\n \t{\n-\t printf (ngettext (\"\\nSection '.liblist' contains %lu entry:\\n\",\n-\t\t\t \"\\nSection '.liblist' contains %lu entries:\\n\",\n-\t\t\t (unsigned long) liblistno),\n-\t\t (unsigned long) liblistno);\n+\t printf (ngettext (\"\\nSection '.liblist' contains %zu entry:\\n\",\n+\t\t\t \"\\nSection '.liblist' contains %zu entries:\\n\",\n+\t\t\t liblistno),\n+\t\t liblistno);\n \t fputs (_(\" Library Time Stamp Checksum Version Flags\\n\"),\n \t\t stdout);\n \n@@ -18666,7 +18690,7 @@ process_mips_specific (Filedata * filedata)\n \t\t\ttmp->tm_year + 1900, tmp->tm_mon + 1, tmp->tm_mday,\n \t\t\ttmp->tm_hour, tmp->tm_min, tmp->tm_sec);\n \n-\t printf (\"%3lu: \", (unsigned long) cnt);\n+\t printf (\"%3zu: \", cnt);\n \t if (valid_dynamic_name (filedata, liblist.l_name))\n \t\tprint_symbol (20, get_dynamic_name (filedata, liblist.l_name));\n \t else\n@@ -18978,8 +19002,8 @@ process_mips_specific (Filedata * filedata)\n \t if we are sure that the cmalloc will fail. */\n if (conflictsno > filedata->file_size / sizeof (* iconf))\n \t{\n-\t error (_(\"Overlarge number of conflicts detected: %lx\\n\"),\n-\t\t (long) conflictsno);\n+\t error (_(\"Overlarge number of conflicts detected: %zx\\n\"),\n+\t\t conflictsno);\n \t return false;\n \t}\n \n@@ -19027,15 +19051,15 @@ process_mips_specific (Filedata * filedata)\n \t free (econf64);\n \t}\n \n- printf (ngettext (\"\\nSection '.conflict' contains %lu entry:\\n\",\n-\t\t\t\"\\nSection '.conflict' contains %lu entries:\\n\",\n-\t\t\t(unsigned long) conflictsno),\n-\t (unsigned long) conflictsno);\n+ printf (ngettext (\"\\nSection '.conflict' contains %zu entry:\\n\",\n+\t\t\t\"\\nSection '.conflict' contains %zu entries:\\n\",\n+\t\t\tconflictsno),\n+\t conflictsno);\n puts (_(\" Num: Index Value Name\"));\n \n for (cnt = 0; cnt < conflictsno; ++cnt)\n \t{\n-\t printf (\"%5lu: %8lu \", (unsigned long) cnt, iconf[cnt]);\n+\t printf (\"%5zu: %8lu \", cnt, iconf[cnt]);\n \n \t if (iconf[cnt] >= filedata->num_dynamic_syms)\n \t printf (_(\"\"));\n@@ -19072,8 +19096,9 @@ process_mips_specific (Filedata * filedata)\n /* PR binutils/17533 file: 012-111227-0.004 */\n if (symtabno < gotsym)\n \t{\n-\t error (_(\"The GOT symbol offset (%lu) is greater than the symbol table size (%lu)\\n\"),\n-\t\t (unsigned long) gotsym, (unsigned long) symtabno);\n+\t error (_(\"The GOT symbol offset (%\" PRIu64\n+\t\t \") is greater than the symbol table size (%\" PRIu64 \")\\n\"),\n+\t\t gotsym, symtabno);\n \t return false;\n \t}\n \n@@ -19081,7 +19106,7 @@ process_mips_specific (Filedata * filedata)\n /* PR 17531: file: 54c91a34. */\n if (global_end < local_end)\n \t{\n-\t error (_(\"Too many GOT symbols: %lu\\n\"), (unsigned long) symtabno);\n+\t error (_(\"Too many GOT symbols: %\" PRIu64 \"\\n\"), symtabno);\n \t return false;\n \t}\n \n@@ -19178,8 +19203,8 @@ process_mips_specific (Filedata * filedata)\n \t\t printf (_(\"\"), psym->st_name);\n \t\t}\n \t else\n-\t\tprintf (_(\"\"),\n-\t\t\t(unsigned long) i);\n+\t\tprintf (_(\"\"),\n+\t\t\ti);\n \n \t printf (\"\\n\");\n \t if (ent == (uint64_t) -1)\n@@ -19195,8 +19220,8 @@ process_mips_specific (Filedata * filedata)\n if (mips_pltgot != 0 && jmprel != 0 && pltrel != 0 && pltrelsz != 0)\n {\n uint64_t ent, end;\n- size_t offset, rel_offset;\n- unsigned long count, i;\n+ uint64_t offset, rel_offset;\n+ uint64_t count, i;\n unsigned char * data;\n int addr_size, sym_width;\n Elf_Internal_Rela * rels;\n@@ -19244,13 +19269,13 @@ process_mips_specific (Filedata * filedata)\n sym_width = (is_32bit_elf ? 80 : 160) - 17 - addr_size * 6 - 1;\n for (i = 0; i < count; i++)\n \t{\n-\t unsigned long idx = get_reloc_symindex (rels[i].r_info);\n+\t uint64_t idx = get_reloc_symindex (rels[i].r_info);\n \n \t ent = print_mips_pltgot_entry (data, mips_pltgot, ent);\n \t printf (\" \");\n \n \t if (idx >= filedata->num_dynamic_syms)\n-\t printf (_(\"\"), idx);\n+\t printf (_(\"\"), idx);\n \t else\n \t {\n \t Elf_Internal_Sym * psym = filedata->dynamic_symbols + idx;\n@@ -19325,7 +19350,7 @@ process_gnu_liblist (Filedata * filedata)\n char * strtab;\n size_t strtab_size;\n size_t cnt;\n- unsigned long num_liblist;\n+ uint64_t num_liblist;\n unsigned i;\n bool res = true;\n \n@@ -19367,8 +19392,10 @@ process_gnu_liblist (Filedata * filedata)\n \t strtab_size = string_sec->sh_size;\n \n \t num_liblist = section->sh_size / sizeof (Elf32_External_Lib);\n-\t printf (ngettext (\"\\nLibrary list section '%s' contains %lu entries:\\n\",\n-\t\t\t \"\\nLibrary list section '%s' contains %lu entries:\\n\",\n+\t printf (ngettext (\"\\nLibrary list section '%s' contains %\" PRIu64\n+\t\t\t \" entries:\\n\",\n+\t\t\t \"\\nLibrary list section '%s' contains %\" PRIu64\n+\t\t\t \" entries:\\n\",\n \t\t\t num_liblist),\n \t\t printable_section_name (filedata, section),\n \t\t num_liblist);\n@@ -19395,7 +19422,7 @@ process_gnu_liblist (Filedata * filedata)\n \t\t\ttmp->tm_year + 1900, tmp->tm_mon + 1, tmp->tm_mday,\n \t\t\ttmp->tm_hour, tmp->tm_min, tmp->tm_sec);\n \n-\t printf (\"%3lu: \", (unsigned long) cnt);\n+\t printf (\"%3zu: \", cnt);\n \t if (do_wide)\n \t\tprintf (\"%-20s\", liblist.l_name < strtab_size\n \t\t\t? strtab + liblist.l_name : _(\"\"));\n@@ -20232,7 +20259,7 @@ print_gnu_property_note (Filedata * filedata, Elf_Internal_Note * pnote)\n \t if (datasz != size)\n \t\tprintf (_(\" \"), datasz);\n \t else\n-\t\tprintf (\"%#lx\", (unsigned long) byte_get (ptr, size));\n+\t\tprintf (\"%#\" PRIx64, byte_get (ptr, size));\n \t goto next;\n \n \t case GNU_PROPERTY_NO_COPY_ON_PROTECTED:\n@@ -20310,7 +20337,7 @@ print_gnu_note (Filedata * filedata, Elf_Internal_Note *pnote)\n {\n case NT_GNU_BUILD_ID:\n {\n-\tunsigned long i;\n+\tsize_t i;\n \n \tprintf (_(\" Build ID: \"));\n \tfor (i = 0; i < pnote->descsz; ++i)\n@@ -20321,7 +20348,7 @@ print_gnu_note (Filedata * filedata, Elf_Internal_Note *pnote)\n \n case NT_GNU_ABI_TAG:\n {\n-\tunsigned long os, major, minor, subminor;\n+\tunsigned int os, major, minor, subminor;\n \tconst char *osname;\n \n \t/* PR 17531: file: 030-599401-0.004. */\n@@ -20364,14 +20391,14 @@ print_gnu_note (Filedata * filedata, Elf_Internal_Note *pnote)\n \t break;\n \t }\n \n-\tprintf (_(\" OS: %s, ABI: %ld.%ld.%ld\\n\"), osname,\n+\tprintf (_(\" OS: %s, ABI: %d.%d.%d\\n\"), osname,\n \t\tmajor, minor, subminor);\n }\n break;\n \n case NT_GNU_GOLD_VERSION:\n {\n-\tunsigned long i;\n+\tsize_t i;\n \n \tprintf (_(\" Version: \"));\n \tfor (i = 0; i < pnote->descsz && pnote->descdata[i] != '\\0'; ++i)\n@@ -20382,7 +20409,7 @@ print_gnu_note (Filedata * filedata, Elf_Internal_Note *pnote)\n \n case NT_GNU_HWCAP:\n {\n-\tunsigned long num_entries, mask;\n+\tunsigned int num_entries, mask;\n \n \t/* Hardware capabilities information. Word 0 is the number of entries.\n \t Word 1 is a bitmask of enabled entries. The rest of the descriptor\n@@ -20397,7 +20424,7 @@ print_gnu_note (Filedata * filedata, Elf_Internal_Note *pnote)\n \t }\n \tnum_entries = byte_get ((unsigned char *) pnote->descdata, 4);\n \tmask = byte_get ((unsigned char *) pnote->descdata + 4, 4);\n-\tprintf (_(\"num entries: %ld, enabled mask: %lx\\n\"), num_entries, mask);\n+\tprintf (_(\"num entries: %d, enabled mask: %x\\n\"), num_entries, mask);\n \t/* FIXME: Add code to display the entries... */\n }\n break;\n@@ -20411,7 +20438,7 @@ print_gnu_note (Filedata * filedata, Elf_Internal_Note *pnote)\n \t created by get_gnu_elf_note_type(), so all that we need to do is to\n \t display the data. */\n {\n-\tunsigned long i;\n+\tsize_t i;\n \n \tprintf (_(\" Description data: \"));\n \tfor (i = 0; i < pnote->descsz; ++i)\n@@ -20713,7 +20740,7 @@ static bool\n print_stapsdt_note (Elf_Internal_Note *pnote)\n {\n size_t len, maxlen;\n- unsigned long addr_size = is_32bit_elf ? 4 : 8;\n+ size_t addr_size = is_32bit_elf ? 4 : 8;\n char *data = pnote->descdata;\n char *data_end = pnote->descdata + pnote->descsz;\n uint64_t pc, base_addr, semaphore;\n@@ -20841,9 +20868,9 @@ get_ia64_vms_note_type (unsigned e_type)\n static bool\n print_ia64_vms_note (Elf_Internal_Note * pnote)\n {\n- int maxlen = pnote->descsz;\n+ unsigned int maxlen = pnote->descsz;\n \n- if (maxlen < 2 || (unsigned long) maxlen != pnote->descsz)\n+ if (maxlen < 2 || maxlen != pnote->descsz)\n goto desc_size_fail;\n \n switch (pnote->type)\n@@ -20852,7 +20879,7 @@ print_ia64_vms_note (Elf_Internal_Note * pnote)\n if (maxlen <= 36)\n \tgoto desc_size_fail;\n \n- int l = (int) strnlen (pnote->descdata + 34, maxlen - 34);\n+ size_t l = strnlen (pnote->descdata + 34, maxlen - 34);\n \n printf (_(\" Creation date : %.17s\\n\"), pnote->descdata);\n printf (_(\" Last patch date: %.17s\\n\"), pnote->descdata + 17);\n@@ -20953,9 +20980,9 @@ print_ia64_vms_note (Elf_Internal_Note * pnote)\n struct build_attr_cache {\n Filedata *filedata;\n char *strtab;\n- unsigned long strtablen;\n+ uint64_t strtablen;\n Elf_Internal_Sym *symtab;\n- unsigned long nsyms;\n+ uint64_t nsyms;\n } ba_cache;\n \n /* Find the symbol associated with a build attribute that is attached\n@@ -20965,7 +20992,7 @@ struct build_attr_cache {\n \n static Elf_Internal_Sym *\n get_symbol_for_build_attribute (Filedata *filedata,\n-\t\t\t\tunsigned long offset,\n+\t\t\t\tuint64_t offset,\n \t\t\t\tbool is_open_attr,\n \t\t\t\tconst char **pname)\n {\n@@ -21079,7 +21106,7 @@ get_symbol_for_build_attribute (Filedata *filedata,\n /* Returns true iff addr1 and addr2 are in the same section. */\n \n static bool\n-same_section (Filedata * filedata, unsigned long addr1, unsigned long addr2)\n+same_section (Filedata * filedata, uint64_t addr1, uint64_t addr2)\n {\n Elf_Internal_Shdr * a1;\n Elf_Internal_Shdr * a2;\n@@ -21094,15 +21121,15 @@ static bool\n print_gnu_build_attribute_description (Elf_Internal_Note * pnote,\n \t\t\t\t Filedata * filedata)\n {\n- static unsigned long global_offset = 0;\n- static unsigned long global_end = 0;\n- static unsigned long func_offset = 0;\n- static unsigned long func_end = 0;\n+ static uint64_t global_offset = 0;\n+ static uint64_t global_end = 0;\n+ static uint64_t func_offset = 0;\n+ static uint64_t func_end = 0;\n \n Elf_Internal_Sym *sym;\n const char *name;\n- unsigned long start;\n- unsigned long end;\n+ uint64_t start;\n+ uint64_t end;\n bool is_open_attr = pnote->type == NT_GNU_BUILD_ATTRIBUTE_OPEN;\n \n switch (pnote->descsz)\n@@ -21113,17 +21140,20 @@ print_gnu_build_attribute_description (Elf_Internal_Note * pnote,\n if (is_open_attr)\n \t{\n \t if (global_end > global_offset)\n-\t printf (_(\" Applies to region from %#lx to %#lx\\n\"),\n-\t\t global_offset, global_end);\n+\t printf (_(\" Applies to region from %#\" PRIx64\n+\t\t \" to %#\" PRIx64 \"\\n\"), global_offset, global_end);\n \t else\n-\t printf (_(\" Applies to region from %#lx\\n\"), global_offset);\n+\t printf (_(\" Applies to region from %#\" PRIx64\n+\t\t \"\\n\"), global_offset);\n \t}\n else\n \t{\n \t if (func_end > func_offset)\n-\t printf (_(\" Applies to region from %#lx to %#lx\\n\"), func_offset, func_end);\n+\t printf (_(\" Applies to region from %#\" PRIx64\n+\t\t \" to %#\" PRIx64 \"\\n\"), func_offset, func_end);\n \t else\n-\t printf (_(\" Applies to region from %#lx\\n\"), func_offset);\n+\t printf (_(\" Applies to region from %#\" PRIx64\n+\t\t \"\\n\"), func_offset);\n \t}\n return true;\n \n@@ -21170,26 +21200,27 @@ print_gnu_build_attribute_description (Elf_Internal_Note * pnote,\n \t increasing address, but we should find the all of the notes\n \t for one section in the same place. */\n \t && same_section (filedata, start, global_end))\n-\twarn (_(\"Gap in build notes detected from %#lx to %#lx\\n\"),\n+\twarn (_(\"Gap in build notes detected from %#\" PRIx64\n+\t\t\" to %#\" PRIx64 \"\\n\"),\n \t global_end + 1, start - 1);\n \n- printf (_(\" Applies to region from %#lx\"), start);\n+ printf (_(\" Applies to region from %#\" PRIx64), start);\n global_offset = start;\n \n if (end)\n \t{\n-\t printf (_(\" to %#lx\"), end);\n+\t printf (_(\" to %#\" PRIx64), end);\n \t global_end = end;\n \t}\n }\n else\n {\n- printf (_(\" Applies to region from %#lx\"), start);\n+ printf (_(\" Applies to region from %#\" PRIx64), start);\n func_offset = start;\n \n if (end)\n \t{\n-\t printf (_(\" to %#lx\"), end);\n+\t printf (_(\" to %#\" PRIx64), end);\n \t func_end = end;\n \t}\n }\n@@ -21331,11 +21362,11 @@ print_gnu_build_attribute_name (Elf_Internal_Note * pnote)\n if (strchr (expected_types, name_type) == NULL)\n warn (_(\"attribute does not have an expected type (%c)\\n\"), name_type);\n \n- if ((unsigned long)(name - pnote->namedata) > pnote->namesz)\n+ if ((size_t) (name - pnote->namedata) > pnote->namesz)\n {\n- error (_(\"corrupt name field: namesz: %lu but parsing gets to %ld\\n\"),\n-\t (unsigned long) pnote->namesz,\n-\t (long) (name - pnote->namedata));\n+ error (_(\"corrupt name field: namesz: %lu but parsing gets to %td\\n\"),\n+\t pnote->namesz,\n+\t name - pnote->namedata);\n return false;\n }\n \n@@ -21346,10 +21377,10 @@ print_gnu_build_attribute_name (Elf_Internal_Note * pnote)\n {\n case GNU_BUILD_ATTRIBUTE_TYPE_NUMERIC:\n {\n-\tunsigned int bytes;\n-\tunsigned long long val = 0;\n-\tunsigned int shift = 0;\n-\tchar * decoded = NULL;\n+\tunsigned int bytes;\n+\tuint64_t val = 0;\n+\tunsigned int shift = 0;\n+\tchar *decoded = NULL;\n \n \tbytes = pnote->namesz - (name - pnote->namedata);\n \tif (bytes > 0)\n@@ -21369,7 +21400,7 @@ print_gnu_build_attribute_name (Elf_Internal_Note * pnote)\n \n \twhile (bytes --)\n \t {\n-\t unsigned long long byte = *name++ & 0xff;\n+\t uint64_t byte = *name++ & 0xff;\n \n \t val |= byte << shift;\n \t shift += 8;\n@@ -21417,9 +21448,9 @@ print_gnu_build_attribute_name (Elf_Internal_Note * pnote)\n \telse\n \t {\n \t if (do_wide)\n-\t left -= printf (\"0x%llx\", val);\n+\t left -= printf (\"0x%\" PRIx64, val);\n \t else\n-\t left -= printf (\"0x%-.*llx\", left, val);\n+\t left -= printf (\"0x%-.*\" PRIx64, left, val);\n \t }\n }\n break;\n@@ -21447,7 +21478,7 @@ print_note_contents_hex (Elf_Internal_Note *pnote)\n {\n if (pnote->descsz)\n {\n- unsigned long i;\n+ size_t i;\n \n printf (_(\" description data: \"));\n for (i = 0; i < pnote->descsz; i++)\n@@ -21759,8 +21790,9 @@ process_notes_at (Filedata * filedata,\n if (section)\n printf (_(\"Displaying notes found in: %s\\n\"), printable_section_name (filedata, section));\n else\n- printf (_(\"Displaying notes found at file offset 0x%08lx with length 0x%08lx:\\n\"),\n-\t (unsigned long) offset, (unsigned long) length);\n+ printf (_(\"Displaying notes found at file offset 0x%08\" PRIx64\n+\t \" with length 0x%08\" PRIx64 \":\\n\"),\n+\t offset, length);\n \n /* NB: Some note sections may have alignment value of 0 or 1. gABI\n specifies that notes should be aligned to 4 bytes in 32-bit\n@@ -21771,8 +21803,8 @@ process_notes_at (Filedata * filedata,\n align = 4;\n else if (align != 4 && align != 8)\n {\n- warn (_(\"Corrupt note: alignment %ld, expecting 4 or 8\\n\"),\n-\t (long) align);\n+ warn (_(\"Corrupt note: alignment %\" PRId64 \", expecting 4 or 8\\n\"),\n+\t align);\n free (pnotes);\n return false;\n }\n@@ -21795,12 +21827,12 @@ process_notes_at (Filedata * filedata,\n \t min_notesz = offsetof (Elf_External_Note, name);\n \t if (data_remaining < min_notesz)\n \t {\n-\t warn (ngettext (\"Corrupt note: only %ld byte remains, \"\n+\t warn (ngettext (\"Corrupt note: only %zd byte remains, \"\n \t\t\t \"not enough for a full note\\n\",\n-\t\t\t \"Corrupt note: only %ld bytes remain, \"\n+\t\t\t \"Corrupt note: only %zd bytes remain, \"\n \t\t\t \"not enough for a full note\\n\",\n \t\t\t data_remaining),\n-\t\t (long) data_remaining);\n+\t\t data_remaining);\n \t break;\n \t }\n \t data_remaining -= min_notesz;\n@@ -21824,12 +21856,12 @@ process_notes_at (Filedata * filedata,\n \t min_notesz = offsetof (Elf64_External_VMS_Note, name);\n \t if (data_remaining < min_notesz)\n \t {\n-\t warn (ngettext (\"Corrupt note: only %ld byte remains, \"\n+\t warn (ngettext (\"Corrupt note: only %zd byte remains, \"\n \t\t\t \"not enough for a full note\\n\",\n-\t\t\t \"Corrupt note: only %ld bytes remain, \"\n+\t\t\t \"Corrupt note: only %zd bytes remain, \"\n \t\t\t \"not enough for a full note\\n\",\n \t\t\t data_remaining),\n-\t\t (long) data_remaining);\n+\t\t data_remaining);\n \t break;\n \t }\n \t data_remaining -= min_notesz;\n@@ -21852,9 +21884,9 @@ process_notes_at (Filedata * filedata,\n \t || ((size_t) (next - inote.descdata)\n \t > data_remaining - (size_t) (inote.descdata - inote.namedata)))\n \t{\n-\t warn (_(\"note with invalid namesz and/or descsz found at offset 0x%lx\\n\"),\n-\t\t(unsigned long) ((char *) external - (char *) pnotes));\n-\t warn (_(\" type: 0x%lx, namesize: 0x%08lx, descsize: 0x%08lx, alignment: %u\\n\"),\n+\t warn (_(\"note with invalid namesz and/or descsz found at offset %#tx\\n\"),\n+\t\t(char *) external - (char *) pnotes);\n+\t warn (_(\" type: %#lx, namesize: %#lx, descsize: %#lx, alignment: %u\\n\"),\n \t\tinote.type, inote.namesz, inote.descsz, (int) align);\n \t break;\n \t}\n@@ -21937,8 +21969,9 @@ process_v850_notes (Filedata * filedata, uint64_t offset, uint64_t length)\n external = pnotes;\n end = (char*) pnotes + length;\n \n- printf (_(\"\\nDisplaying contents of Renesas V850 notes section at offset 0x%lx with length 0x%lx:\\n\"),\n-\t (unsigned long) offset, (unsigned long) length);\n+ printf (_(\"\\nDisplaying contents of Renesas V850 notes section at offset\"\n+\t \" %#\" PRIx64 \" with length %#\" 100 115k 100 115k 100 152 2022k 2666 --:--:-- --:--:-- --:--:-- 2025k PRIx64 \":\\n\"),\n+\t offset, length);\n \n while ((char *) external + sizeof (Elf_External_Note) < end)\n {\n@@ -21964,9 +21997,9 @@ process_v850_notes (Filedata * filedata, uint64_t offset, uint64_t length)\n if ( ((char *) next > end)\n \t || ((char *) next < (char *) pnotes))\n \t{\n-\t warn (_(\"corrupt descsz found in note at offset 0x%lx\\n\"),\n-\t\t(unsigned long) ((char *) external - (char *) pnotes));\n-\t warn (_(\" type: 0x%lx, namesize: 0x%lx, descsize: 0x%lx\\n\"),\n+\t warn (_(\"corrupt descsz found in note at offset %#tx\\n\"),\n+\t\t(char *) external - (char *) pnotes);\n+\t warn (_(\" type: %#lx, namesize: %#lx, descsize: %#lx\\n\"),\n \t\tinote.type, inote.namesz, inote.descsz);\n \t break;\n \t}\n@@ -21977,9 +22010,9 @@ process_v850_notes (Filedata * filedata, uint64_t offset, uint64_t length)\n if ( inote.namedata + inote.namesz > end\n \t || inote.namedata + inote.namesz < inote.namedata)\n {\n- warn (_(\"corrupt namesz found in note at offset 0x%lx\\n\"),\n- (unsigned long) ((char *) external - (char *) pnotes));\n- warn (_(\" type: 0x%lx, namesize: 0x%lx, descsize: 0x%lx\\n\"),\n+ warn (_(\"corrupt namesz found in note at offset %#zx\\n\"),\n+ (char *) external - (char *) pnotes);\n+ warn (_(\" type: %#lx, namesize: %#lx, descsize: %#lx\\n\"),\n inote.type, inote.namesz, inote.descsz);\n break;\n }\n@@ -21989,7 +22022,7 @@ process_v850_notes (Filedata * filedata, uint64_t offset, uint64_t length)\n if (! print_v850_note (& inote))\n \t{\n \t res = false;\n-\t printf (\"\\n\",\n+\t printf (\"\\n\",\n \t\t inote.namesz, inote.descsz);\n \t}\n }\n@@ -22003,7 +22036,7 @@ static bool\n process_note_sections (Filedata * filedata)\n {\n Elf_Internal_Shdr *section;\n- unsigned long i;\n+ size_t i;\n unsigned int n = 0;\n bool res = true;\n \n@@ -22572,12 +22605,12 @@ process_archive (Filedata * filedata, bool is_thin_archive)\n \t filedata->file_name);\n else\n \t{\n-\t unsigned long i, l;\n-\t unsigned long current_pos;\n+\t uint64_t i, l;\n+\t uint64_t current_pos;\n \n-\t printf (_(\"Index of archive %s: (%lu entries, 0x%lx bytes \"\n-\t\t \"in the symbol table)\\n\"),\n-\t\t filedata->file_name, (unsigned long) arch.index_num,\n+\t printf (_(\"Index of archive %s: (%\" PRIu64 \" entries,\"\n+\t\t \" %#\" PRIx64 \" bytes in the symbol table)\\n\"),\n+\t\t filedata->file_name, arch.index_num,\n \t\t arch.sym_size);\n \n \t current_pos = ftell (filedata->handle);\n@@ -22630,10 +22663,10 @@ process_archive (Filedata * filedata, bool is_thin_archive)\n \n \t if (l < arch.sym_size)\n \t {\n-\t error (ngettext (\"%s: %ld byte remains in the symbol table, \"\n+\t error (ngettext (\"%s: %\" PRId64 \" byte remains in the symbol table, \"\n \t\t\t \"but without corresponding entries in \"\n \t\t\t \"the index table\\n\",\n-\t\t\t \"%s: %ld bytes remain in the symbol table, \"\n+\t\t\t \"%s: %\" PRId64 \" bytes remain in the symbol table, \"\n \t\t\t \"but without corresponding entries in \"\n \t\t\t \"the index table\\n\",\n \t\t\t arch.sym_size - l),\n","prefixes":[]}+ exit 1 Build step 'Execute shell' marked build as failure Finished: FAILURE