Started by user snail Running as SYSTEM [EnvInject] - Loading node environment variables. Building remotely on docker-jenkins-agent in workspace /home/jenkins/agent/workspace/binutils-gdb [WS-CLEANUP] Deleting project workspace... [WS-CLEANUP] Deferred wipeout is used... [WS-CLEANUP] Done The recommended git tool is: NONE using credential 0adb5fc7-caa2-429d-97d2-c7fa2fa1d884 Cloning the remote Git repository Using shallow clone with depth 1 Avoid fetching tags Cloning repository git@github.com:plctlab/patchwork-binutils-gdb.git > git init /home/jenkins/agent/workspace/binutils-gdb # timeout=10 Fetching upstream changes from git@github.com:plctlab/patchwork-binutils-gdb.git > git --version # timeout=10 > git --version # 'git version 2.37.2' using GIT_SSH to set credentials patchwork github wangliu-iscas git ssh key Verifying host key using known hosts file, will automatically accept unseen keys > git fetch --no-tags --force --progress --depth=1 -- git@github.com:plctlab/patchwork-binutils-gdb.git +refs/heads/*:refs/remotes/origin/* # timeout=10 > git config remote.origin.url git@github.com:plctlab/patchwork-binutils-gdb.git # timeout=10 > git config --add remote.origin.fetch +refs/heads/*:refs/remotes/origin/* # timeout=10 Avoid second fetch > git rev-parse refs/remotes/origin/master^{commit} # timeout=10 Checking out Revision 2d4989e98ee5e63b76ce3e35b0e02baaee2f50cb (refs/remotes/origin/master) > git config core.sparsecheckout # timeout=10 > git checkout -f 2d4989e98ee5e63b76ce3e35b0e02baaee2f50cb # timeout=10 Commit message: "Re: Fuzzed files in archives" > git rev-list --no-walk 2d4989e98ee5e63b76ce3e35b0e02baaee2f50cb # timeout=10 [EnvInject] - Mask passwords that will be passed as build parameters. [EnvInject] - Executing scripts and injecting environment variables after the SCM step. [EnvInject] - Injecting as environment variables the properties content GITHUB_REPO=https://github.com/plctlab/patchwork-binutils-gdb PATCHWORK_URL=https://patchwork.plctlab.org [EnvInject] - Variables injected successfully. [binutils-gdb] $ /usr/bin/env bash /tmp/jenkins9340818698266593740.sh + git config pw.server https://patchwork.plctlab.org/api/1.2/ + git config pw.project binutils-gdb + git config pw.token [*******] ++ date +%Y-%m + now_date=2022-11 ++ date +%Y + now_date_year=2022 + bundle_name=binutils-gdb_2022-11 ++ curl -s -H 'Authorization: Token [*******]' 'https://patchwork.plctlab.org/api/1.2/bundles/?project=binutils-gdb&per_page=999' + bundle_response='[{"id":6,"url":"https://patchwork.plctlab.org/api/1.2/bundles/6/","web_url":"https://patchwork.plctlab.org/bundle/patchwork-bot/binutils-gdb_2022-10/","project":{"id":2,"url":"https://patchwork.plctlab.org/api/1.2/projects/2/","name":"binutils-gdb","link_name":"binutils-gdb","list_id":"binutils.sourceware.org","list_email":"binutils@sourceware.org","web_url":"https://github.com/wangliu-iscas/Patchwork-Bundles/blob/main/binutils-gdb.md","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"name":"binutils-gdb_2022-10","owner":{"id":3,"url":"https://patchwork.plctlab.org/api/1.2/users/3/","username":"patchwork-bot","first_name":"","last_name":"","email":"ouuuleilei@gmail.com"},"patches":[{"id":1592,"url":"https://patchwork.plctlab.org/api/1.2/patches/1592/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/385d01fd-7e57-1f3f-1bae-30aa0c313d63@suse.com/","msgid":"<385d01fd-7e57-1f3f-1bae-30aa0c313d63@suse.com>","list_archive_url":null,"date":"2022-09-30T11:59:45","name":"[3/4] RISC-V/gas: don'\''t open-code insn_length()","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/385d01fd-7e57-1f3f-1bae-30aa0c313d63@suse.com/mbox/"},{"id":1594,"url":"https://patchwork.plctlab.org/api/1.2/patches/1594/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f5757acf-7b90-a0e3-5eea-3b97cc226930@suse.com/","msgid":"","list_archive_url":null,"date":"2022-09-30T12:00:12","name":"[4/4] RISC-V/gas: allow generating up to 176-bit instructions with .insn","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f5757acf-7b90-a0e3-5eea-3b97cc226930@suse.com/mbox/"},{"id":1596,"url":"https://patchwork.plctlab.org/api/1.2/patches/1596/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930140503.38233-1-chigot@adacore.com/","msgid":"<20220930140503.38233-1-chigot@adacore.com>","list_archive_url":null,"date":"2022-09-30T14:05:03","name":"ld/testsuite: consistently add board_ldflags when linking with GCC","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930140503.38233-1-chigot@adacore.com/mbox/"},{"id":1619,"url":"https://patchwork.plctlab.org/api/1.2/patches/1619/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221001014451.532772-1-maskray@google.com/","msgid":"<20221001014451.532772-1-maskray@google.com>","list_archive_url":null,"date":"2022-10-01T01:44:51","name":"gold, dwp: support zstd compressed input debug sections [PR 29641]","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221001014451.532772-1-maskray@google.com/mbox/"},{"id":1620,"url":"https://patchwork.plctlab.org/api/1.2/patches/1620/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221001023846.590825-1-maskray@google.com/","msgid":"<20221001023846.590825-1-maskray@google.com>","list_archive_url":null,"date":"2022-10-01T02:38:46","name":"gold: add --compress-debug-sections=zstd [PR 29641]","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221001023846.590825-1-maskray@google.com/mbox/"},{"id":1623,"url":"https://patchwork.plctlab.org/api/1.2/patches/1623/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b4477c7f666bdeb7f8e998633c7b0cb62310b9ef.1664599545.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-01T04:45:52","name":"[RFC,1/1] RISC-V: Implement common register pair framework","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b4477c7f666bdeb7f8e998633c7b0cb62310b9ef.1664599545.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1625,"url":"https://patchwork.plctlab.org/api/1.2/patches/1625/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/53a265a1f14d17a6f7b106082f610994c5d546e0.1664602025.git.research_trasio@irq.a4lg.com/","msgid":"<53a265a1f14d17a6f7b106082f610994c5d546e0.1664602025.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-01T05:27:31","name":"[RFC,1/1] RISC-V: Implement extension variants","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/53a265a1f14d17a6f7b106082f610994c5d546e0.1664602025.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1626,"url":"https://patchwork.plctlab.org/api/1.2/patches/1626/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8db04962aba9c780f133840a8934353a58f223fe.1664602716.git.research_trasio@irq.a4lg.com/","msgid":"<8db04962aba9c780f133840a8934353a58f223fe.1664602716.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-01T05:39:26","name":"[1/1] RISC-V: Move supervisor instructions after all unprivileged ones","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8db04962aba9c780f133840a8934353a58f223fe.1664602716.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1627,"url":"https://patchwork.plctlab.org/api/1.2/patches/1627/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221001062057.681440-1-maskray@google.com/","msgid":"<20221001062057.681440-1-maskray@google.com>","list_archive_url":null,"date":"2022-10-01T06:20:57","name":"readelf: support zstd compressed debug sections [PR 29640]","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221001062057.681440-1-maskray@google.com/mbox/"},{"id":1631,"url":"https://patchwork.plctlab.org/api/1.2/patches/1631/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/619f112539c0bdecd58e25664f1250a3479a37f5.1664707612.git.aburgess@redhat.com/","msgid":"<619f112539c0bdecd58e25664f1250a3479a37f5.1664707612.git.aburgess@redhat.com>","list_archive_url":null,"date":"2022-10-02T10:47:52","name":"[PATCHv2,2/2] opcodes/arm: add disassembler styling for arm","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/619f112539c0bdecd58e25664f1250a3479a37f5.1664707612.git.aburgess@redhat.com/mbox/"},{"id":1635,"url":"https://patchwork.plctlab.org/api/1.2/patches/1635/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221002185433.gl7dvytfh5wthifx@lug-owl.de/","msgid":"<20221002185433.gl7dvytfh5wthifx@lug-owl.de>","list_archive_url":null,"date":"2022-10-02T18:54:33","name":"diagnostics.h: GCC 13 got -Wself-move, breaks GDB build","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221002185433.gl7dvytfh5wthifx@lug-owl.de/mbox/"},{"id":1637,"url":"https://patchwork.plctlab.org/api/1.2/patches/1637/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003014313.28766-1-mark@harmstone.com/","msgid":"<20221003014313.28766-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-03T01:43:12","name":"[1/2] ld: Add --pdb option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003014313.28766-1-mark@harmstone.com/mbox/"},{"id":1638,"url":"https://patchwork.plctlab.org/api/1.2/patches/1638/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003014313.28766-2-mark@harmstone.com/","msgid":"<20221003014313.28766-2-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-03T01:43:13","name":"[2/2] ld: Add minimal pdb generation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003014313.28766-2-mark@harmstone.com/mbox/"},{"id":1640,"url":"https://patchwork.plctlab.org/api/1.2/patches/1640/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/597ed978-d121-220c-b56b-2ffb94bd091c@suse.cz/","msgid":"<597ed978-d121-220c-b56b-2ffb94bd091c@suse.cz>","list_archive_url":null,"date":"2022-10-03T07:50:38","name":"[1/2] refactor usage of compressed_debug_section_type","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/597ed978-d121-220c-b56b-2ffb94bd091c@suse.cz/mbox/"},{"id":1641,"url":"https://patchwork.plctlab.org/api/1.2/patches/1641/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b8acdd83-f33a-74b8-e21a-23719a0b1a60@suse.cz/","msgid":"","list_archive_url":null,"date":"2022-10-03T07:50:44","name":"[2/2] add --enable-default-compressed-debug-sections-algorithm configure option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b8acdd83-f33a-74b8-e21a-23719a0b1a60@suse.cz/mbox/"},{"id":1642,"url":"https://patchwork.plctlab.org/api/1.2/patches/1642/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003101328.1790113-1-aburgess@redhat.com/","msgid":"<20221003101328.1790113-1-aburgess@redhat.com>","list_archive_url":null,"date":"2022-10-03T10:13:28","name":"opcodes/riscv: style csr names as registers","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003101328.1790113-1-aburgess@redhat.com/mbox/"},{"id":1643,"url":"https://patchwork.plctlab.org/api/1.2/patches/1643/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7ba14fc4472ce97d4f7a4433cad8a571e89f82f4.1664793840.git.research_trasio@irq.a4lg.com/","msgid":"<7ba14fc4472ce97d4f7a4433cad8a571e89f82f4.1664793840.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-03T10:43:59","name":"[v3,1/6] RISC-V: Fix immediates to have \"immediate\" style","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7ba14fc4472ce97d4f7a4433cad8a571e89f82f4.1664793840.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1644,"url":"https://patchwork.plctlab.org/api/1.2/patches/1644/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a498bec37c1fd1dcda57cbf95e5f8cfba09b31d3.1664793840.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-03T10:44:00","name":"[v3,2/6] RISC-V: Fix printf argument types corresponding %x","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a498bec37c1fd1dcda57cbf95e5f8cfba09b31d3.1664793840.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1647,"url":"https://patchwork.plctlab.org/api/1.2/patches/1647/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0002ea716713ace4998a33dde0b81f4f890d10bf.1664793840.git.research_trasio@irq.a4lg.com/","msgid":"<0002ea716713ace4998a33dde0b81f4f890d10bf.1664793840.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-03T10:44:01","name":"[v3,3/6] RISC-V: Optimize riscv_disassemble_data printf","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0002ea716713ace4998a33dde0b81f4f890d10bf.1664793840.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1646,"url":"https://patchwork.plctlab.org/api/1.2/patches/1646/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c65fc3e9aa58965d6768a28c9fd7467fea9897a5.1664793840.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-03T10:44:02","name":"[v3,4/6] RISC-V: Print comma and tabs as the \"text\" style","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c65fc3e9aa58965d6768a28c9fd7467fea9897a5.1664793840.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1648,"url":"https://patchwork.plctlab.org/api/1.2/patches/1648/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5abe1d8a7694417b990e11d8f6cd6789573872e5.1664793840.git.research_trasio@irq.a4lg.com/","msgid":"<5abe1d8a7694417b990e11d8f6cd6789573872e5.1664793840.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-03T10:44:03","name":"[v3,5/6] RISC-V: Fix T-Head immediate types on printing","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5abe1d8a7694417b990e11d8f6cd6789573872e5.1664793840.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1649,"url":"https://patchwork.plctlab.org/api/1.2/patches/1649/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0b68af932117258c908db62cf87c3a15d3cdec41.1664793840.git.research_trasio@irq.a4lg.com/","msgid":"<0b68af932117258c908db62cf87c3a15d3cdec41.1664793840.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-03T10:44:04","name":"[v3,6/6] RISC-V: Print XTheadMemPair literal as \"immediate\"","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0b68af932117258c908db62cf87c3a15d3cdec41.1664793840.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1656,"url":"https://patchwork.plctlab.org/api/1.2/patches/1656/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/87lepxcd6x.fsf@redhat.com/","msgid":"<87lepxcd6x.fsf@redhat.com>","list_archive_url":null,"date":"2022-10-03T12:19:02","name":"Commit: readelf: Do not load section data from offset 0","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/87lepxcd6x.fsf@redhat.com/mbox/"},{"id":1659,"url":"https://patchwork.plctlab.org/api/1.2/patches/1659/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e0d369d419da9c0441f415da7f54352aead8f655.1664707612.git.aburgess@redhat.com/","msgid":"","list_archive_url":null,"date":"2022-10-03T16:37:36","name":"[PATCHv2,1/2] opcodes/arm: use '\''@'\'' consistently for the comment character","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e0d369d419da9c0441f415da7f54352aead8f655.1664707612.git.aburgess@redhat.com/mbox/"},{"id":1660,"url":"https://patchwork.plctlab.org/api/1.2/patches/1660/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003165848.11142-1-palmer@rivosinc.com/","msgid":"<20221003165848.11142-1-palmer@rivosinc.com>","list_archive_url":null,"date":"2022-10-03T16:58:48","name":"gas: NEWS: Mention the T-Head extensions that were recently added","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003165848.11142-1-palmer@rivosinc.com/mbox/"},{"id":1671,"url":"https://patchwork.plctlab.org/api/1.2/patches/1671/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/YzvrMEdkXjIn5Lfz@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-04T08:13:36","name":"Support objcopy changing compression to or from zstd","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/YzvrMEdkXjIn5Lfz@squeak.grove.modra.org/mbox/"},{"id":1673,"url":"https://patchwork.plctlab.org/api/1.2/patches/1673/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0bc857d306bb7c8130e5328dbe6b9ed2fed3ef87.1664873933.git.research_trasio@irq.a4lg.com/","msgid":"<0bc857d306bb7c8130e5328dbe6b9ed2fed3ef87.1664873933.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-04T08:59:07","name":"[1/2] RISC-V: Fix buffer overflow on print_insn_riscv","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0bc857d306bb7c8130e5328dbe6b9ed2fed3ef87.1664873933.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1672,"url":"https://patchwork.plctlab.org/api/1.2/patches/1672/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/89612fe01d902007bf84a7dfb0df5f85d5c166e4.1664873933.git.research_trasio@irq.a4lg.com/","msgid":"<89612fe01d902007bf84a7dfb0df5f85d5c166e4.1664873933.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-04T08:59:08","name":"[2/2] gdb/riscv: Fix buffer overflow on riscv_insn::fetch_instruction","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/89612fe01d902007bf84a7dfb0df5f85d5c166e4.1664873933.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1676,"url":"https://patchwork.plctlab.org/api/1.2/patches/1676/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fc849c94f4adcac1c4ccc5508c7a145a2f13b2a9.1664876744.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-04T09:45:49","name":"[v2,1/2] RISC-V: Fix buffer overflow on print_insn_riscv","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fc849c94f4adcac1c4ccc5508c7a145a2f13b2a9.1664876744.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1677,"url":"https://patchwork.plctlab.org/api/1.2/patches/1677/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4eb6e59ae2e790dbbf2bc92477edd281648d8814.1664876744.git.research_trasio@irq.a4lg.com/","msgid":"<4eb6e59ae2e790dbbf2bc92477edd281648d8814.1664876744.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-04T09:45:50","name":"[v2,2/2] gdb/riscv: Partial support for instructions up to 176-bits","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4eb6e59ae2e790dbbf2bc92477edd281648d8814.1664876744.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1678,"url":"https://patchwork.plctlab.org/api/1.2/patches/1678/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ebf16f9e1f45115d0793952ccb4a94d4233303f9.1664882725.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-04T11:25:56","name":"[v3,1/2] RISC-V: Fix buffer overflow on print_insn_riscv","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ebf16f9e1f45115d0793952ccb4a94d4233303f9.1664882725.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1679,"url":"https://patchwork.plctlab.org/api/1.2/patches/1679/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/83464b09b8649525259c69c853dfa2c9575a204b.1664882725.git.research_trasio@irq.a4lg.com/","msgid":"<83464b09b8649525259c69c853dfa2c9575a204b.1664882725.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-04T11:25:57","name":"[v3,2/2] gdb/riscv: Partial support for instructions up to 176-bit","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/83464b09b8649525259c69c853dfa2c9575a204b.1664882725.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1681,"url":"https://patchwork.plctlab.org/api/1.2/patches/1681/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ffa9c1d7-e8c2-a62b-ef3e-b565c0ffbe5b@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-04T13:56:27","name":"RISC-V: Zicbo{m,p,z} adjustments to riscv_multi_subset_supports_ext()","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ffa9c1d7-e8c2-a62b-ef3e-b565c0ffbe5b@suse.com/mbox/"},{"id":1690,"url":"https://patchwork.plctlab.org/api/1.2/patches/1690/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221004161720.1963953-1-vladimir.mezentsev@oracle.com/","msgid":"<20221004161720.1963953-1-vladimir.mezentsev@oracle.com>","list_archive_url":null,"date":"2022-10-04T16:17:20","name":"gprofng: fix build with --enable-pgo-build=lto","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221004161720.1963953-1-vladimir.mezentsev@oracle.com/mbox/"},{"id":1691,"url":"https://patchwork.plctlab.org/api/1.2/patches/1691/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c0211bc9c57be6c79c6d878ce147f63b657f461d.camel@espressif.com/","msgid":"","list_archive_url":null,"date":"2022-10-04T16:22:05","name":"bfd: xtensa: fix __stop_SECTION literal drop,","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c0211bc9c57be6c79c6d878ce147f63b657f461d.camel@espressif.com/mbox/"},{"id":1702,"url":"https://patchwork.plctlab.org/api/1.2/patches/1702/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5f482299-6c60-b2b3-9abe-f4a55a5a26c5@univ-grenoble-alpes.fr/","msgid":"<5f482299-6c60-b2b3-9abe-f4a55a5a26c5@univ-grenoble-alpes.fr>","list_archive_url":null,"date":"2022-10-04T20:03:20","name":"[RFC] bfd: use bfd_vma for the 64-bit version of put[lb] and get[lb]","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5f482299-6c60-b2b3-9abe-f4a55a5a26c5@univ-grenoble-alpes.fr/mbox/"},{"id":1711,"url":"https://patchwork.plctlab.org/api/1.2/patches/1711/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Yz0Gsxdxe0TePbJT@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-05T04:23:15","name":"PR29647, objdump -S looping","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Yz0Gsxdxe0TePbJT@squeak.grove.modra.org/mbox/"},{"id":1712,"url":"https://patchwork.plctlab.org/api/1.2/patches/1712/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/02d747d2-f57b-0fb5-b893-842b6cc41f2f@suse.com/","msgid":"<02d747d2-f57b-0fb5-b893-842b6cc41f2f@suse.com>","list_archive_url":null,"date":"2022-10-05T07:20:47","name":"[v3,1/7] x86: constify parse_insn()'\''s input","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/02d747d2-f57b-0fb5-b893-842b6cc41f2f@suse.com/mbox/"},{"id":1713,"url":"https://patchwork.plctlab.org/api/1.2/patches/1713/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/925cb740-4e1b-abc4-8526-aaab6faae5e1@suse.com/","msgid":"<925cb740-4e1b-abc4-8526-aaab6faae5e1@suse.com>","list_archive_url":null,"date":"2022-10-05T07:22:19","name":"[v3,2/7] x86: introduce Pass2 insn attribute","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/925cb740-4e1b-abc4-8526-aaab6faae5e1@suse.com/mbox/"},{"id":1714,"url":"https://patchwork.plctlab.org/api/1.2/patches/1714/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e16d3e78-39ca-f715-508f-a4104b8ab9a9@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-05T07:23:51","name":"[v3,3/7] x86: re-work insn/suffix recognition","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e16d3e78-39ca-f715-508f-a4104b8ab9a9@suse.com/mbox/"},{"id":1715,"url":"https://patchwork.plctlab.org/api/1.2/patches/1715/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e4e4b80b-794c-7485-1997-685adab8fb27@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-05T07:24:20","name":"[v3,4/7] x86-64: further re-work insn/suffix recognition to also cover MOVSL","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e4e4b80b-794c-7485-1997-685adab8fb27@suse.com/mbox/"},{"id":1716,"url":"https://patchwork.plctlab.org/api/1.2/patches/1716/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/540678fc-8bff-ec68-c97c-478d2631998c@suse.com/","msgid":"<540678fc-8bff-ec68-c97c-478d2631998c@suse.com>","list_archive_url":null,"date":"2022-10-05T07:24:55","name":"[v3,5/7] ix86: don'\''t recognize/derive Q suffix in the common case","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/540678fc-8bff-ec68-c97c-478d2631998c@suse.com/mbox/"},{"id":1718,"url":"https://patchwork.plctlab.org/api/1.2/patches/1718/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e4692495-7d3d-074d-14f9-364d4a9a998c@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-05T07:25:25","name":"[v3,6/7] x86-64: allow HLE store of accumulator to absolute 32-bit address","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e4692495-7d3d-074d-14f9-364d4a9a998c@suse.com/mbox/"},{"id":1717,"url":"https://patchwork.plctlab.org/api/1.2/patches/1717/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e8014ebd-d16b-17a7-9f34-3700fc164136@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-05T07:25:57","name":"[v3,7/7] x86: move bad-use-of-TLS-reloc check","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e8014ebd-d16b-17a7-9f34-3700fc164136@suse.com/mbox/"},{"id":1719,"url":"https://patchwork.plctlab.org/api/1.2/patches/1719/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1266f001-4511-2662-dba9-14b4d0317c57@suse.com/","msgid":"<1266f001-4511-2662-dba9-14b4d0317c57@suse.com>","list_archive_url":null,"date":"2022-10-05T07:40:50","name":"x86: drop \"regmask\" static variable","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1266f001-4511-2662-dba9-14b4d0317c57@suse.com/mbox/"},{"id":1751,"url":"https://patchwork.plctlab.org/api/1.2/patches/1751/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/af45c5d57c221e43101c2aa38b14f4b4ac12d011.1665031170.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-06T04:40:15","name":"[v2,1/2] RISC-V: Fallback for instructions longer than 64b","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/af45c5d57c221e43101c2aa38b14f4b4ac12d011.1665031170.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1752,"url":"https://patchwork.plctlab.org/api/1.2/patches/1752/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c6e55781245dd3e8e9b8debd6130fc5449dfbd55.1665031170.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-06T04:40:16","name":"[v2,2/2] RISC-V: Improve \"bits undefined\" diagnostics","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c6e55781245dd3e8e9b8debd6130fc5449dfbd55.1665031170.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1776,"url":"https://patchwork.plctlab.org/api/1.2/patches/1776/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d52952119e15357c0e823f8a2398999359588b4d.1665050099.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-06T09:56:30","name":"[v3,1/2] RISC-V: Fallback for instructions longer than 64b","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d52952119e15357c0e823f8a2398999359588b4d.1665050099.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1777,"url":"https://patchwork.plctlab.org/api/1.2/patches/1777/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d907b1997f60ff7823c4a23e281ec9d8ddcbf3f1.1665050099.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-06T09:56:31","name":"[v3,2/2] RISC-V: Improve \"bits undefined\" diagnostics","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d907b1997f60ff7823c4a23e281ec9d8ddcbf3f1.1665050099.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1781,"url":"https://patchwork.plctlab.org/api/1.2/patches/1781/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221006114628.304185-1-chigot@adacore.com/","msgid":"<20221006114628.304185-1-chigot@adacore.com>","list_archive_url":null,"date":"2022-10-06T11:46:28","name":"RISC-V: fix linker message when relaxation deletes bytes","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221006114628.304185-1-chigot@adacore.com/mbox/"},{"id":1801,"url":"https://patchwork.plctlab.org/api/1.2/patches/1801/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Yz+Yhyg7UewC9/kp@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-07T03:09:59","name":"PR29653, objcopy/strip: fuzzed small input file induces large output file","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Yz+Yhyg7UewC9/kp@squeak.grove.modra.org/mbox/"},{"id":1803,"url":"https://patchwork.plctlab.org/api/1.2/patches/1803/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/PH1P110MB16505D9D39EC5B1DE22FE3D5EC5F9@PH1P110MB1650.NAMP110.PROD.OUTLOOK.COM/","msgid":"","list_archive_url":null,"date":"2022-10-07T04:10:07","name":"@CPP_FOR_BUILD@ problem since binutils-2.38","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/PH1P110MB16505D9D39EC5B1DE22FE3D5EC5F9@PH1P110MB1650.NAMP110.PROD.OUTLOOK.COM/mbox/"},{"id":1827,"url":"https://patchwork.plctlab.org/api/1.2/patches/1827/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8e13bce108ac10a0c1dd911e23ec572926f7ae44.1665203374.git.research_trasio@irq.a4lg.com/","msgid":"<8e13bce108ac10a0c1dd911e23ec572926f7ae44.1665203374.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-08T04:29:53","name":"[v2,1/1] RISC-V: Test DWARF register numbers for \"fp\"","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8e13bce108ac10a0c1dd911e23ec572926f7ae44.1665203374.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1828,"url":"https://patchwork.plctlab.org/api/1.2/patches/1828/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0883001b3572e54d3fba264429c7ade2adb66610.1665203441.git.research_trasio@irq.a4lg.com/","msgid":"<0883001b3572e54d3fba264429c7ade2adb66610.1665203441.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-08T04:31:15","name":"[1/1] RISC-V: Move standard hints before all instructions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0883001b3572e54d3fba264429c7ade2adb66610.1665203441.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1829,"url":"https://patchwork.plctlab.org/api/1.2/patches/1829/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/58e16a241d7376fcae2515c6bd5a2b41d275eeba.1665203531.git.research_trasio@irq.a4lg.com/","msgid":"<58e16a241d7376fcae2515c6bd5a2b41d275eeba.1665203531.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-08T04:32:18","name":"[RFC,1/1] RISC-V: Imply '\''Zicsr'\'' from privileged extensions with CSRs","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/58e16a241d7376fcae2515c6bd5a2b41d275eeba.1665203531.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1830,"url":"https://patchwork.plctlab.org/api/1.2/patches/1830/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/cb5076fc96e8f2097779a3abcde843dcdd660031.1665203660.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-08T04:34:23","name":"[1/5] opcodes/riscv-dis.c: Tidying with comments/clarity","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/cb5076fc96e8f2097779a3abcde843dcdd660031.1665203660.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1832,"url":"https://patchwork.plctlab.org/api/1.2/patches/1832/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1f1aa0838bf9c4f10a45fcfe3c682f7efc79d9ae.1665203660.git.research_trasio@irq.a4lg.com/","msgid":"<1f1aa0838bf9c4f10a45fcfe3c682f7efc79d9ae.1665203660.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-08T04:34:24","name":"[2/5] opcodes/riscv-dis.c: Tidying with spacing","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1f1aa0838bf9c4f10a45fcfe3c682f7efc79d9ae.1665203660.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1831,"url":"https://patchwork.plctlab.org/api/1.2/patches/1831/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/740bc5e2d2618d236519b39fedd1a1d7ae4e05da.1665203660.git.research_trasio@irq.a4lg.com/","msgid":"<740bc5e2d2618d236519b39fedd1a1d7ae4e05da.1665203660.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-08T04:34:25","name":"[3/5] opcodes/riscv-dis.c: Use bool type whenever possible","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/740bc5e2d2618d236519b39fedd1a1d7ae4e05da.1665203660.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1833,"url":"https://patchwork.plctlab.org/api/1.2/patches/1833/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6e3a9c235e317f441b4383b3daa68f2051bdc149.1665203660.git.research_trasio@irq.a4lg.com/","msgid":"<6e3a9c235e317f441b4383b3daa68f2051bdc149.1665203660.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-08T04:34:26","name":"[4/5] opcodes/riscv-dis.c: Make XLEN variable static","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6e3a9c235e317f441b4383b3daa68f2051bdc149.1665203660.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1834,"url":"https://patchwork.plctlab.org/api/1.2/patches/1834/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ad929233a62d887495122721340b2f9c80392963.1665203660.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-08T04:34:27","name":"[5/5] opcodes/riscv-dis.c: Remove last_map_state","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ad929233a62d887495122721340b2f9c80392963.1665203660.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1836,"url":"https://patchwork.plctlab.org/api/1.2/patches/1836/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d07e2b6f36ea2fd5830924a9bfeda941b774b687.1665290422.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-09T05:09:22","name":"RISC-V: Move certain arrays to riscv-opc.c","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d07e2b6f36ea2fd5830924a9bfeda941b774b687.1665290422.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1844,"url":"https://patchwork.plctlab.org/api/1.2/patches/1844/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010004623.16582-1-mark@harmstone.com/","msgid":"<20221010004623.16582-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-10T00:46:22","name":"[v2,1/2] ld: Add --pdb option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010004623.16582-1-mark@harmstone.com/mbox/"},{"id":1845,"url":"https://patchwork.plctlab.org/api/1.2/patches/1845/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010004623.16582-2-mark@harmstone.com/","msgid":"<20221010004623.16582-2-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-10T00:46:23","name":"[v2,2/2] ld: Add minimal pdb generation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010004623.16582-2-mark@harmstone.com/mbox/"},{"id":1890,"url":"https://patchwork.plctlab.org/api/1.2/patches/1890/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010200433.414320-1-vladimir.mezentsev@oracle.com/","msgid":"<20221010200433.414320-1-vladimir.mezentsev@oracle.com>","list_archive_url":null,"date":"2022-10-10T20:04:33","name":"gprofng: run tests without installation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010200433.414320-1-vladimir.mezentsev@oracle.com/mbox/"},{"id":1893,"url":"https://patchwork.plctlab.org/api/1.2/patches/1893/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010230426.719238-1-vladimir.mezentsev@oracle.com/","msgid":"<20221010230426.719238-1-vladimir.mezentsev@oracle.com>","list_archive_url":null,"date":"2022-10-10T23:04:26","name":"[2/2] gprofng: use the --libdir path to find libraries","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010230426.719238-1-vladimir.mezentsev@oracle.com/mbox/"},{"id":1894,"url":"https://patchwork.plctlab.org/api/1.2/patches/1894/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010235155.842469-1-vladimir.mezentsev@oracle.com/","msgid":"<20221010235155.842469-1-vladimir.mezentsev@oracle.com>","list_archive_url":null,"date":"2022-10-10T23:51:55","name":"[3/3] gprofng: no need to build version.texi","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010235155.842469-1-vladimir.mezentsev@oracle.com/mbox/"},{"id":1895,"url":"https://patchwork.plctlab.org/api/1.2/patches/1895/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011003702.4287-1-mark@harmstone.com/","msgid":"<20221011003702.4287-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-11T00:37:01","name":"[v3,1/2] ld: Add --pdb option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011003702.4287-1-mark@harmstone.com/mbox/"},{"id":1897,"url":"https://patchwork.plctlab.org/api/1.2/patches/1897/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011003702.4287-2-mark@harmstone.com/","msgid":"<20221011003702.4287-2-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-11T00:37:02","name":"[v3,2/2] ld: Add minimal pdb generation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011003702.4287-2-mark@harmstone.com/mbox/"},{"id":1928,"url":"https://patchwork.plctlab.org/api/1.2/patches/1928/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011175332.17156-1-mark@harmstone.com/","msgid":"<20221011175332.17156-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-11T17:53:31","name":"[v4,1/2] ld: Add --pdb option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011175332.17156-1-mark@harmstone.com/mbox/"},{"id":1929,"url":"https://patchwork.plctlab.org/api/1.2/patches/1929/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011175332.17156-2-mark@harmstone.com/","msgid":"<20221011175332.17156-2-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-11T17:53:32","name":"[v4,2/2] ld: Add minimal pdb generation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011175332.17156-2-mark@harmstone.com/mbox/"},{"id":1941,"url":"https://patchwork.plctlab.org/api/1.2/patches/1941/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221012031005.237446-1-simon.marchi@polymtl.ca/","msgid":"<20221012031005.237446-1-simon.marchi@polymtl.ca>","list_archive_url":null,"date":"2022-10-12T03:10:05","name":"[pushed] Re-apply \"Pass PKG_CONFIG_PATH down from top-level Makefile\"","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221012031005.237446-1-simon.marchi@polymtl.ca/mbox/"},{"id":1976,"url":"https://patchwork.plctlab.org/api/1.2/patches/1976/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1216a3f8-2273-8681-f528-9493a66891f0@suse.com/","msgid":"<1216a3f8-2273-8681-f528-9493a66891f0@suse.com>","list_archive_url":null,"date":"2022-10-13T08:16:49","name":"[v4,1/8] x86: constify parse_insn()'\''s input","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1216a3f8-2273-8681-f528-9493a66891f0@suse.com/mbox/"},{"id":1977,"url":"https://patchwork.plctlab.org/api/1.2/patches/1977/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/11599bbe-c779-aa9f-4d5d-c2243f0e69dc@suse.com/","msgid":"<11599bbe-c779-aa9f-4d5d-c2243f0e69dc@suse.com>","list_archive_url":null,"date":"2022-10-13T08:17:17","name":"[v4,2/8] x86: introduce Pass2 insn attribute","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/11599bbe-c779-aa9f-4d5d-c2243f0e69dc@suse.com/mbox/"},{"id":1978,"url":"https://patchwork.plctlab.org/api/1.2/patches/1978/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/357273a3-060c-23db-72da-3fc9d1be3d2a@suse.com/","msgid":"<357273a3-060c-23db-72da-3fc9d1be3d2a@suse.com>","list_archive_url":null,"date":"2022-10-13T08:18:09","name":"[v4,3/8] x86: re-work insn/suffix recognition","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/357273a3-060c-23db-72da-3fc9d1be3d2a@suse.com/mbox/"},{"id":1979,"url":"https://patchwork.plctlab.org/api/1.2/patches/1979/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0ec0587f-6a7b-45b6-8346-e5d774e73636@suse.com/","msgid":"<0ec0587f-6a7b-45b6-8346-e5d774e73636@suse.com>","list_archive_url":null,"date":"2022-10-13T08:18:39","name":"[v4,4/8] x86-64: further re-work insn/suffix recognition to also cover MOVSL","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0ec0587f-6a7b-45b6-8346-e5d774e73636@suse.com/mbox/"},{"id":1980,"url":"https://patchwork.plctlab.org/api/1.2/patches/1980/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fb617d0b-8759-3169-5a65-1178b7fef3d7@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-13T08:19:34","name":"[v4,5/8] ix86: don'\''t recognize/derive Q suffix in the common case","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fb617d0b-8759-3169-5a65-1178b7fef3d7@suse.com/mbox/"},{"id":1981,"url":"https://patchwork.plctlab.org/api/1.2/patches/1981/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1df3bd01-99c5-f56c-d937-970edd42b2b8@suse.com/","msgid":"<1df3bd01-99c5-f56c-d937-970edd42b2b8@suse.com>","list_archive_url":null,"date":"2022-10-13T08:20:14","name":"[v4,6/8] x86-64: allow HLE store of accumulator to absolute 32-bit address","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1df3bd01-99c5-f56c-d937-970edd42b2b8@suse.com/mbox/"},{"id":1982,"url":"https://patchwork.plctlab.org/api/1.2/patches/1982/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8486a218-39ec-16b2-5c6c-5037196b93cf@suse.com/","msgid":"<8486a218-39ec-16b2-5c6c-5037196b93cf@suse.com>","list_archive_url":null,"date":"2022-10-13T08:21:00","name":"[v4,7/8] x86: move bad-use-of-TLS-reloc check","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8486a218-39ec-16b2-5c6c-5037196b93cf@suse.com/mbox/"},{"id":1983,"url":"https://patchwork.plctlab.org/api/1.2/patches/1983/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7d82692d-93df-fbee-9efb-2f44e8a91df3@suse.com/","msgid":"<7d82692d-93df-fbee-9efb-2f44e8a91df3@suse.com>","list_archive_url":null,"date":"2022-10-13T08:22:00","name":"[v4,8/8] x86: drop (now) stray IsString","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7d82692d-93df-fbee-9efb-2f44e8a91df3@suse.com/mbox/"},{"id":2013,"url":"https://patchwork.plctlab.org/api/1.2/patches/2013/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8ab93d7a617ad480dd786210f46db0e5aa07d1ac.1665655719.git.research_trasio@irq.a4lg.com/","msgid":"<8ab93d7a617ad480dd786210f46db0e5aa07d1ac.1665655719.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-13T10:11:41","name":"include: Declare getopt function on old GNU libc","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8ab93d7a617ad480dd786210f46db0e5aa07d1ac.1665655719.git.research_trasio@irq.a4lg.com/mbox/"},{"id":2352,"url":"https://patchwork.plctlab.org/api/1.2/patches/2352/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221013201332.2747246-1-maskray@google.com/","msgid":"<20221013201332.2747246-1-maskray@google.com>","list_archive_url":null,"date":"2022-10-13T20:13:32","name":"ld: Add --undefined-version","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221013201332.2747246-1-maskray@google.com/mbox/"},{"id":2532,"url":"https://patchwork.plctlab.org/api/1.2/patches/2532/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014063520.1428330-2-zengxiao@eswincomputing.com/","msgid":"<20221014063520.1428330-2-zengxiao@eswincomputing.com>","list_archive_url":null,"date":"2022-10-14T06:35:20","name":"[1/1] RISC-V: Make R_RISCV_SUB6 conforms to riscv abi standard","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014063520.1428330-2-zengxiao@eswincomputing.com/mbox/"},{"id":2560,"url":"https://patchwork.plctlab.org/api/1.2/patches/2560/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/027ae69a-636b-6757-297a-eec42936401e@linaro.org/","msgid":"<027ae69a-636b-6757-297a-eec42936401e@linaro.org>","list_archive_url":null,"date":"2022-10-14T07:58:22","name":"[v3] aarch64-pe support for LD, GAS and BFD","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/027ae69a-636b-6757-297a-eec42936401e@linaro.org/mbox/"},{"id":2602,"url":"https://patchwork.plctlab.org/api/1.2/patches/2602/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-2-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-2-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:39","name":"[01/10] Support Intel AVX-IFMA","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-2-haochen.jiang@intel.com/mbox/"},{"id":2608,"url":"https://patchwork.plctlab.org/api/1.2/patches/2608/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-3-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-3-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:40","name":"[02/10] Support Intel AVX-VNNI-INT8","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-3-haochen.jiang@intel.com/mbox/"},{"id":2611,"url":"https://patchwork.plctlab.org/api/1.2/patches/2611/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-4-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-4-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:41","name":"[03/10] Support Intel AVX-NE-CONVERT","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-4-haochen.jiang@intel.com/mbox/"},{"id":2610,"url":"https://patchwork.plctlab.org/api/1.2/patches/2610/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-5-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-5-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:42","name":"[04/10] Support Intel CMPccXADD","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-5-haochen.jiang@intel.com/mbox/"},{"id":2601,"url":"https://patchwork.plctlab.org/api/1.2/patches/2601/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-6-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-6-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:43","name":"[05/10] Add handler for more i386_cpu_flags","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-6-haochen.jiang@intel.com/mbox/"},{"id":2606,"url":"https://patchwork.plctlab.org/api/1.2/patches/2606/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-7-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-7-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:44","name":"[06/10] Support Intel RAO-INT","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-7-haochen.jiang@intel.com/mbox/"},{"id":2609,"url":"https://patchwork.plctlab.org/api/1.2/patches/2609/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-8-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-8-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:45","name":"[07/10] Support Intel WRMSRNS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-8-haochen.jiang@intel.com/mbox/"},{"id":2605,"url":"https://patchwork.plctlab.org/api/1.2/patches/2605/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-9-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-9-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:46","name":"[08/10] Support Intel MSRLIST","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-9-haochen.jiang@intel.com/mbox/"},{"id":2607,"url":"https://patchwork.plctlab.org/api/1.2/patches/2607/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-10-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-10-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:47","name":"[09/10] Support Intel AMX-FP16","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-10-haochen.jiang@intel.com/mbox/"},{"id":2604,"url":"https://patchwork.plctlab.org/api/1.2/patches/2604/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-11-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-11-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:48","name":"[10/10] Support Intel PREFETCHI","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-11-haochen.jiang@intel.com/mbox/"},{"id":2643,"url":"https://patchwork.plctlab.org/api/1.2/patches/2643/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7bac66be-535e-9051-d674-f2f5ba180e17@suse.com/","msgid":"<7bac66be-535e-9051-d674-f2f5ba180e17@suse.com>","list_archive_url":null,"date":"2022-10-14T10:22:34","name":"x86: fold AVX512-VNNI disassembler entries with AVX-VNNI ones","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7bac66be-535e-9051-d674-f2f5ba180e17@suse.com/mbox/"},{"id":2654,"url":"https://patchwork.plctlab.org/api/1.2/patches/2654/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0lIo5+ncY/MqBEq@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-14T11:31:47","name":"PR29677, Field `the_bfd` of `asymbol` is uninitialised","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0lIo5+ncY/MqBEq@squeak.grove.modra.org/mbox/"},{"id":2656,"url":"https://patchwork.plctlab.org/api/1.2/patches/2656/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0lJksn49ZpABY89@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-14T11:35:46","name":"e200 LSP support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0lJksn49ZpABY89@squeak.grove.modra.org/mbox/"},{"id":2657,"url":"https://patchwork.plctlab.org/api/1.2/patches/2657/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0lJxxYoeD5iDYAD@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-14T11:36:39","name":"PowerPC SPE disassembly and tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0lJxxYoeD5iDYAD@squeak.grove.modra.org/mbox/"},{"id":2695,"url":"https://patchwork.plctlab.org/api/1.2/patches/2695/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/DM6PR12MB4219611F6CC2A0702884A602E7249@DM6PR12MB4219.namprd12.prod.outlook.com/","msgid":"","list_archive_url":null,"date":"2022-10-14T13:29:40","name":"Binutils: Adding new testcase for addr2line.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/DM6PR12MB4219611F6CC2A0702884A602E7249@DM6PR12MB4219.namprd12.prod.outlook.com/mbox/"},{"id":2700,"url":"https://patchwork.plctlab.org/api/1.2/patches/2700/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9fd2c88d-98b2-99a4-419f-c7235b2cf960@suse.com/","msgid":"<9fd2c88d-98b2-99a4-419f-c7235b2cf960@suse.com>","list_archive_url":null,"date":"2022-10-14T14:11:35","name":"x86: properly decode EVEX.W for AVX512_4{FMAPS,VNNIW} insns","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9fd2c88d-98b2-99a4-419f-c7235b2cf960@suse.com/mbox/"},{"id":2981,"url":"https://patchwork.plctlab.org/api/1.2/patches/2981/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0uLzalqjm4C87GN@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-16T04:42:53","name":"PowerPC se_rfmci and VLE, SPE2 and LSP insns with -many","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0uLzalqjm4C87GN@squeak.grove.modra.org/mbox/"},{"id":3152,"url":"https://patchwork.plctlab.org/api/1.2/patches/3152/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221016232419.1135-1-mark@harmstone.com/","msgid":"<20221016232419.1135-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-16T23:24:18","name":"[v5,1/2] ld: Add --pdb option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221016232419.1135-1-mark@harmstone.com/mbox/"},{"id":3151,"url":"https://patchwork.plctlab.org/api/1.2/patches/3151/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221016232419.1135-2-mark@harmstone.com/","msgid":"<20221016232419.1135-2-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-16T23:24:19","name":"[v5,2/2] ld: Add minimal pdb generation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221016232419.1135-2-mark@harmstone.com/mbox/"},{"id":3258,"url":"https://patchwork.plctlab.org/api/1.2/patches/3258/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/19c08747-fa5b-1e67-3dd2-c891a2c0c1fa@suse.com/","msgid":"<19c08747-fa5b-1e67-3dd2-c891a2c0c1fa@suse.com>","list_archive_url":null,"date":"2022-10-17T07:44:51","name":"x86: correct CPU_AMX_{BF16,INT8}_FLAGS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/19c08747-fa5b-1e67-3dd2-c891a2c0c1fa@suse.com/mbox/"},{"id":3272,"url":"https://patchwork.plctlab.org/api/1.2/patches/3272/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/85dd526c-d3a7-72dc-5444-ed5573eebec1@suse.com/","msgid":"<85dd526c-d3a7-72dc-5444-ed5573eebec1@suse.com>","list_archive_url":null,"date":"2022-10-17T08:30:12","name":"x86: generalize gas documentation for disabling of ISA extensions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/85dd526c-d3a7-72dc-5444-ed5573eebec1@suse.com/mbox/"},{"id":3759,"url":"https://patchwork.plctlab.org/api/1.2/patches/3759/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-2-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-2-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:15:58","name":"[V2,01/15] sframe.h: Add SFrame format definition","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-2-indu.bhagat@oracle.com/mbox/"},{"id":3762,"url":"https://patchwork.plctlab.org/api/1.2/patches/3762/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-3-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-3-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:15:59","name":"[V2,02/15] gas: add new command line option --gsframe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-3-indu.bhagat@oracle.com/mbox/"},{"id":3761,"url":"https://patchwork.plctlab.org/api/1.2/patches/3761/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-4-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-4-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:00","name":"[V2,03/15] gas: generate .sframe from CFI directives","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-4-indu.bhagat@oracle.com/mbox/"},{"id":3760,"url":"https://patchwork.plctlab.org/api/1.2/patches/3760/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-5-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-5-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:01","name":"[V2,04/15] gas: testsuite: add new tests for SFrame unwind info","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-5-indu.bhagat@oracle.com/mbox/"},{"id":3764,"url":"https://patchwork.plctlab.org/api/1.2/patches/3764/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-6-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-6-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:02","name":"[V2,05/15] libsframe: add the SFrame library","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-6-indu.bhagat@oracle.com/mbox/"},{"id":3766,"url":"https://patchwork.plctlab.org/api/1.2/patches/3766/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-7-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-7-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:03","name":"[V2,06/15] bfd: linker: merge .sframe sections","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-7-indu.bhagat@oracle.com/mbox/"},{"id":3763,"url":"https://patchwork.plctlab.org/api/1.2/patches/3763/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-8-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-8-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:04","name":"[V2,07/15] readelf/objdump: support for SFrame section","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-8-indu.bhagat@oracle.com/mbox/"},{"id":3765,"url":"https://patchwork.plctlab.org/api/1.2/patches/3765/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-9-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-9-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:05","name":"[V2,08/15] unwinder: generate backtrace using SFrame format","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-9-indu.bhagat@oracle.com/mbox/"},{"id":3770,"url":"https://patchwork.plctlab.org/api/1.2/patches/3770/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-10-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-10-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:06","name":"[V2,09/15] unwinder: Add SFrame unwinder tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-10-indu.bhagat@oracle.com/mbox/"},{"id":3769,"url":"https://patchwork.plctlab.org/api/1.2/patches/3769/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-11-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-11-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:07","name":"[V2,10/15] gdb: sim: buildsystem changes to accommodate libsframe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-11-indu.bhagat@oracle.com/mbox/"},{"id":3771,"url":"https://patchwork.plctlab.org/api/1.2/patches/3771/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-12-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-12-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:08","name":"[V2,11/15] libctf: add libsframe to LDFLAGS and LIBS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-12-indu.bhagat@oracle.com/mbox/"},{"id":3768,"url":"https://patchwork.plctlab.org/api/1.2/patches/3768/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-13-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-13-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:09","name":"[V2,12/15] src-release.sh: Add libsframe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-13-indu.bhagat@oracle.com/mbox/"},{"id":3767,"url":"https://patchwork.plctlab.org/api/1.2/patches/3767/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-14-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-14-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:10","name":"[V2,13/15] binutils/NEWS: add text for SFrame support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-14-indu.bhagat@oracle.com/mbox/"},{"id":3772,"url":"https://patchwork.plctlab.org/api/1.2/patches/3772/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-15-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-15-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:11","name":"[V2,14/15] gas/NEWS: add text about new command line option and SFrame support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-15-indu.bhagat@oracle.com/mbox/"},{"id":3773,"url":"https://patchwork.plctlab.org/api/1.2/patches/3773/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-16-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-16-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:12","name":"[V2,15/15] doc: add SFrame spec file","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-16-indu.bhagat@oracle.com/mbox/"},{"id":3999,"url":"https://patchwork.plctlab.org/api/1.2/patches/3999/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221018081205.17880-1-krebbel@linux.ibm.com/","msgid":"<20221018081205.17880-1-krebbel@linux.ibm.com>","list_archive_url":null,"date":"2022-10-18T08:12:05","name":"[1/1] IBM zSystems: Issue error for *DBL relocs on misaligned symbols","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221018081205.17880-1-krebbel@linux.ibm.com/mbox/"},{"id":4141,"url":"https://patchwork.plctlab.org/api/1.2/patches/4141/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/baffaf673f17692b7bcbd604b31800b189988596.camel@espressif.com/","msgid":"","list_archive_url":null,"date":"2022-10-18T12:12:07","name":"xtensa: use definitions from xtensa-config.h","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/baffaf673f17692b7bcbd604b31800b189988596.camel@espressif.com/mbox/"},{"id":4272,"url":"https://patchwork.plctlab.org/api/1.2/patches/4272/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221018174914.470062-1-hjl.tools@gmail.com/","msgid":"<20221018174914.470062-1-hjl.tools@gmail.com>","list_archive_url":null,"date":"2022-10-18T17:49:14","name":"x86: Disable AVX-VNNI when disabling AVX2","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221018174914.470062-1-hjl.tools@gmail.com/mbox/"},{"id":4998,"url":"https://patchwork.plctlab.org/api/1.2/patches/4998/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c2f76e95-09f6-1d92-7ef4-38a3c2955fcd@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-19T09:52:46","name":"x86: re-work AVX-VNNI support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c2f76e95-09f6-1d92-7ef4-38a3c2955fcd@suse.com/mbox/"},{"id":5276,"url":"https://patchwork.plctlab.org/api/1.2/patches/5276/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0/lLtlKqqsmAx0s@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-19T11:53:18","name":"Fix addr2line test for ppc64 elfv1 and mingw","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0/lLtlKqqsmAx0s@squeak.grove.modra.org/mbox/"},{"id":5424,"url":"https://patchwork.plctlab.org/api/1.2/patches/5424/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/07bfebbf3843b47e13d82d4fa16eb14fec942ef7.1666184962.git.research_trasio@irq.a4lg.com/","msgid":"<07bfebbf3843b47e13d82d4fa16eb14fec942ef7.1666184962.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:09:54","name":"binutils: Remove unused substitution PROGRAM","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/07bfebbf3843b47e13d82d4fa16eb14fec942ef7.1666184962.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5433,"url":"https://patchwork.plctlab.org/api/1.2/patches/5433/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2fa7ff719223232402e82a9c91331aea22ace1bb.1666185116.git.research_trasio@irq.a4lg.com/","msgid":"<2fa7ff719223232402e82a9c91331aea22ace1bb.1666185116.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:11:55","name":"[v2,1/8] RISC-V: Add a space at the end of pinfo","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2fa7ff719223232402e82a9c91331aea22ace1bb.1666185116.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5435,"url":"https://patchwork.plctlab.org/api/1.2/patches/5435/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1b30cce5db2cce3b8edca42ab5da114d0b8c9e93.1666185116.git.research_trasio@irq.a4lg.com/","msgid":"<1b30cce5db2cce3b8edca42ab5da114d0b8c9e93.1666185116.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:11:56","name":"[v2,2/8] RISC-V: Fix obvious misalignments ('\''Zbb'\''/'\''Zba'\'')","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1b30cce5db2cce3b8edca42ab5da114d0b8c9e93.1666185116.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5437,"url":"https://patchwork.plctlab.org/api/1.2/patches/5437/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6b0857aa1a2d15ca1cf00b4dcaae0032efbb88ff.1666185116.git.research_trasio@irq.a4lg.com/","msgid":"<6b0857aa1a2d15ca1cf00b4dcaae0032efbb88ff.1666185116.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:11:57","name":"[v2,3/8] RISC-V: Remove spaces in opcode entries","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6b0857aa1a2d15ca1cf00b4dcaae0032efbb88ff.1666185116.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5436,"url":"https://patchwork.plctlab.org/api/1.2/patches/5436/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/889d956caac0f2e95543a14afaeed97188ce384c.1666185116.git.research_trasio@irq.a4lg.com/","msgid":"<889d956caac0f2e95543a14afaeed97188ce384c.1666185116.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:11:58","name":"[v2,4/8] RISC-V: Remove unused instruction macros","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/889d956caac0f2e95543a14afaeed97188ce384c.1666185116.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5440,"url":"https://patchwork.plctlab.org/api/1.2/patches/5440/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8f226ee20d8a5ef6ad7b6c4408b44794a99d542a.1666185116.git.research_trasio@irq.a4lg.com/","msgid":"<8f226ee20d8a5ef6ad7b6c4408b44794a99d542a.1666185116.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:11:59","name":"[v2,5/8] RISC-V: Complete tidying up with SCALL and SBREAK","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8f226ee20d8a5ef6ad7b6c4408b44794a99d542a.1666185116.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5442,"url":"https://patchwork.plctlab.org/api/1.2/patches/5442/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4070184c454a05a39adf0790951e5856e6b2ecb6.1666185116.git.research_trasio@irq.a4lg.com/","msgid":"<4070184c454a05a39adf0790951e5856e6b2ecb6.1666185116.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:12:00","name":"[v2,6/8] RISC-V: Tidying up with fmv.w.x and fmv.x.w","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4070184c454a05a39adf0790951e5856e6b2ecb6.1666185116.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5438,"url":"https://patchwork.plctlab.org/api/1.2/patches/5438/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c1ccda3e7c8fb297eda46dab3936d5c5977178fc.1666185116.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-19T13:12:01","name":"[v2,7/8] RISC-V: Make alias instructions aliases","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c1ccda3e7c8fb297eda46dab3936d5c5977178fc.1666185116.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5441,"url":"https://patchwork.plctlab.org/api/1.2/patches/5441/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/413cfca82c7e8d8a2e977dfda9135903c9cb7c57.1666185116.git.research_trasio@irq.a4lg.com/","msgid":"<413cfca82c7e8d8a2e977dfda9135903c9cb7c57.1666185116.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:12:02","name":"[v2,8/8] RISC-V: Use defined mask and match values","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/413cfca82c7e8d8a2e977dfda9135903c9cb7c57.1666185116.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5439,"url":"https://patchwork.plctlab.org/api/1.2/patches/5439/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/345c5c3b3a53eab04a1e6e91197de2642095c94f.1666185237.git.research_trasio@irq.a4lg.com/","msgid":"<345c5c3b3a53eab04a1e6e91197de2642095c94f.1666185237.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:14:01","name":"RISC-V: Remove RV32EF conflict","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/345c5c3b3a53eab04a1e6e91197de2642095c94f.1666185237.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5616,"url":"https://patchwork.plctlab.org/api/1.2/patches/5616/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019145608.45213-5-haochen.jiang@intel.com/","msgid":"<20221019145608.45213-5-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T14:56:02","name":"[04/10] Support Intel CMPccXADD","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019145608.45213-5-haochen.jiang@intel.com/mbox/"},{"id":5614,"url":"https://patchwork.plctlab.org/api/1.2/patches/5614/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019145608.45213-6-haochen.jiang@intel.com/","msgid":"<20221019145608.45213-6-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T14:56:03","name":"[05/10] Add handler for more i386_cpu_flags","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019145608.45213-6-haochen.jiang@intel.com/mbox/"},{"id":5672,"url":"https://patchwork.plctlab.org/api/1.2/patches/5672/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-2-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-2-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:25","name":"[01/10] Support Intel AVX-IFMA","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-2-haochen.jiang@intel.com/mbox/"},{"id":5691,"url":"https://patchwork.plctlab.org/api/1.2/patches/5691/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-3-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-3-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:26","name":"[02/10] Support Intel AVX-VNNI-INT8","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-3-haochen.jiang@intel.com/mbox/"},{"id":5690,"url":"https://patchwork.plctlab.org/api/1.2/patches/5690/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-4-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-4-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:27","name":"[03/10] Support Intel AVX-NE-CONVERT","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-4-haochen.jiang@intel.com/mbox/"},{"id":5689,"url":"https://patchwork.plctlab.org/api/1.2/patches/5689/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-5-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-5-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:28","name":"[04/10] Support Intel CMPccXADD","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-5-haochen.jiang@intel.com/mbox/"},{"id":5676,"url":"https://patchwork.plctlab.org/api/1.2/patches/5676/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-6-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-6-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:29","name":"[05/10] Add handler for more i386_cpu_flags","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-6-haochen.jiang@intel.com/mbox/"},{"id":5677,"url":"https://patchwork.plctlab.org/api/1.2/patches/5677/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-7-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-7-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:30","name":"[06/10] Support Intel RAO-INT","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-7-haochen.jiang@intel.com/mbox/"},{"id":5681,"url":"https://patchwork.plctlab.org/api/1.2/patches/5681/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-8-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-8-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:31","name":"[07/10] Support Intel WRMSRNS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-8-haochen.jiang@intel.com/mbox/"},{"id":5682,"url":"https://patchwork.plctlab.org/api/1.2/patches/5682/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-9-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-9-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:32","name":"[08/10] Support Intel MSRLIST","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-9-haochen.jiang@intel.com/mbox/"},{"id":5673,"url":"https://patchwork.plctlab.org/api/1.2/patches/5673/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-10-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-10-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:33","name":"[09/10] Support Intel AMX-FP16","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-10-haochen.jiang@intel.com/mbox/"},{"id":5686,"url":"https://patchwork.plctlab.org/api/1.2/patches/5686/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-11-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-11-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:34","name":"[10/10] Support Intel PREFETCHI","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-11-haochen.jiang@intel.com/mbox/"},{"id":5940,"url":"https://patchwork.plctlab.org/api/1.2/patches/5940/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1CMrFUC8d9lC/NL@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-19T23:47:56","name":"Obsolete beos","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1CMrFUC8d9lC/NL@squeak.grove.modra.org/mbox/"},{"id":6080,"url":"https://patchwork.plctlab.org/api/1.2/patches/6080/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8b99d666e78ba5b9d32c7889a2161c70b3da88df.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<8b99d666e78ba5b9d32c7889a2161c70b3da88df.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:25:47","name":"[01/40] gdb/unittests: PR28413, suppress warnings generated by Gnulib","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8b99d666e78ba5b9d32c7889a2161c70b3da88df.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6081,"url":"https://patchwork.plctlab.org/api/1.2/patches/6081/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b05adb17e401d621dbdad791281bc7af7806906e.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-20T09:25:48","name":"[02/40] sim: Check known getrusage declaration existence","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b05adb17e401d621dbdad791281bc7af7806906e.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6083,"url":"https://patchwork.plctlab.org/api/1.2/patches/6083/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/796962a87e569feeafb5ef636de3c79000ae152c.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<796962a87e569feeafb5ef636de3c79000ae152c.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:25:49","name":"[03/40] sim/aarch64: Remove unused functions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/796962a87e569feeafb5ef636de3c79000ae152c.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6084,"url":"https://patchwork.plctlab.org/api/1.2/patches/6084/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/65223c79fdfd7faf132275415cd9da9852c5bec3.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<65223c79fdfd7faf132275415cd9da9852c5bec3.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:25:50","name":"[04/40] cpu/cris: Initialize some variables on CRIS CPU","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/65223c79fdfd7faf132275415cd9da9852c5bec3.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6082,"url":"https://patchwork.plctlab.org/api/1.2/patches/6082/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/24baefe92148f4b7968115ba13de9b0c863a65f6.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<24baefe92148f4b7968115ba13de9b0c863a65f6.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:25:51","name":"[05/40] cpu/cris: Add u-stall virtual unit to CRIS v32","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/24baefe92148f4b7968115ba13de9b0c863a65f6.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6087,"url":"https://patchwork.plctlab.org/api/1.2/patches/6087/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3904a5c3e80f8548150d8088a92059dd728c7ff8.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<3904a5c3e80f8548150d8088a92059dd728c7ff8.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:25:52","name":"[06/40] sim/cris: Move declarations of f_specific_init","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3904a5c3e80f8548150d8088a92059dd728c7ff8.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6091,"url":"https://patchwork.plctlab.org/api/1.2/patches/6091/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/69ef2d7dd519ed572511890a215a0f6d74e53384.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<69ef2d7dd519ed572511890a215a0f6d74e53384.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:25:53","name":"[07/40] sim/cris: Regenerate with CGEN","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/69ef2d7dd519ed572511890a215a0f6d74e53384.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6085,"url":"https://patchwork.plctlab.org/api/1.2/patches/6085/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/26a3eaf4f5d2e0db6977738ddfd65d82b36e38b2.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<26a3eaf4f5d2e0db6977738ddfd65d82b36e38b2.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:25:54","name":"[08/40] sim/erc32: Insert void parameter","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/26a3eaf4f5d2e0db6977738ddfd65d82b36e38b2.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6086,"url":"https://patchwork.plctlab.org/api/1.2/patches/6086/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/057c2f8392410494c3bc5dc98052246508e6a73e.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<057c2f8392410494c3bc5dc98052246508e6a73e.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:25:55","name":"[09/40] sim/erc32: Use int32_t as event callback argument","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/057c2f8392410494c3bc5dc98052246508e6a73e.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6090,"url":"https://patchwork.plctlab.org/api/1.2/patches/6090/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8c05aec20557191434485be347d37177a2ec5ff2.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<8c05aec20557191434485be347d37177a2ec5ff2.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:25:56","name":"[10/40] sim/erc32: Use int32_t as IRQ callback argument","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8c05aec20557191434485be347d37177a2ec5ff2.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6089,"url":"https://patchwork.plctlab.org/api/1.2/patches/6089/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/afd7757aae21743c29f2aa4135a23b31d4959e9b.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-20T09:25:57","name":"[11/40] cpu/frv: Initialize some variables","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/afd7757aae21743c29f2aa4135a23b31d4959e9b.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6088,"url":"https://patchwork.plctlab.org/api/1.2/patches/6088/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/021dbd238af5dfe74523ed229d2156a155a6bb9e.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<021dbd238af5dfe74523ed229d2156a155a6bb9e.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:25:58","name":"[12/40] sim/frv: Initialize nesr variable","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/021dbd238af5dfe74523ed229d2156a155a6bb9e.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6093,"url":"https://patchwork.plctlab.org/api/1.2/patches/6093/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/51a03f7097921cc48954210cf99e370ae8982ec8.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<51a03f7097921cc48954210cf99e370ae8982ec8.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:25:59","name":"[13/40] sim/frv: Initialize some variables","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/51a03f7097921cc48954210cf99e370ae8982ec8.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6092,"url":"https://patchwork.plctlab.org/api/1.2/patches/6092/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e1baa1be3601612266dc6ae0bdde8426ff2a42c8.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-20T09:26:00","name":"[14/40] sim/frv: Add explicit casts","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e1baa1be3601612266dc6ae0bdde8426ff2a42c8.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6095,"url":"https://patchwork.plctlab.org/api/1.2/patches/6095/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5ab303a5bdfc1da7832f8fa22f57678c9ef1a5fa.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<5ab303a5bdfc1da7832f8fa22f57678c9ef1a5fa.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:26:01","name":"[15/40] sim/h8300: Add \"+ 0x0\" to avoid self-assignments","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5ab303a5bdfc1da7832f8fa22f57678c9ef1a5fa.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6101,"url":"https://patchwork.plctlab.org/api/1.2/patches/6101/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ddff80db3328a2286fe6fbc1240d2abc1e3813eb.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-20T09:26:02","name":"[16/40] sim/lm32: fix some missing function declaration warnings","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ddff80db3328a2286fe6fbc1240d2abc1e3813eb.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6094,"url":"https://patchwork.plctlab.org/api/1.2/patches/6094/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e094b1379231d9ffb59a78cfebbcc84634c779c6.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-20T09:26:03","name":"[17/40] sim/lm32: Add explicit casts","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e094b1379231d9ffb59a78cfebbcc84634c779c6.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6141,"url":"https://patchwork.plctlab.org/api/1.2/patches/6141/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/cabebead-489b-528c-580e-933832417474@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-20T10:25:51","name":"[1/3] x86: emit {evex} prefix when disassembling ambiguous AVX512VL insns","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/cabebead-489b-528c-580e-933832417474@suse.com/mbox/"},{"id":6143,"url":"https://patchwork.plctlab.org/api/1.2/patches/6143/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a032d61c-63a0-23d1-331f-619a2b8bbde3@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-20T10:26:15","name":"[2/3] x86: consolidate VAES tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a032d61c-63a0-23d1-331f-619a2b8bbde3@suse.com/mbox/"},{"id":6142,"url":"https://patchwork.plctlab.org/api/1.2/patches/6142/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7ff09c86-2de7-dc34-3183-5187de3df5ac@suse.com/","msgid":"<7ff09c86-2de7-dc34-3183-5187de3df5ac@suse.com>","list_archive_url":null,"date":"2022-10-20T10:26:40","name":"[3/3] x86: consolidate VPCLMUL tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7ff09c86-2de7-dc34-3183-5187de3df5ac@suse.com/mbox/"},{"id":6228,"url":"https://patchwork.plctlab.org/api/1.2/patches/6228/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.LSU.2.20.2210201432170.29399@wotan.suse.de/","msgid":"","list_archive_url":null,"date":"2022-10-20T14:42:25","name":"x86-64: Use only one default max-page-size","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.LSU.2.20.2210201432170.29399@wotan.suse.de/mbox/"},{"id":6229,"url":"https://patchwork.plctlab.org/api/1.2/patches/6229/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221020144351.1398099-1-chigot@adacore.com/","msgid":"<20221020144351.1398099-1-chigot@adacore.com>","list_archive_url":null,"date":"2022-10-20T14:43:50","name":"[1/2] ld/testsuite: skip ld-elf/exclude when -shared is not supported","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221020144351.1398099-1-chigot@adacore.com/mbox/"},{"id":6230,"url":"https://patchwork.plctlab.org/api/1.2/patches/6230/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221020144351.1398099-2-chigot@adacore.com/","msgid":"<20221020144351.1398099-2-chigot@adacore.com>","list_archive_url":null,"date":"2022-10-20T14:43:51","name":"[2/2] ld/testsuite: adjust ld-arm to run shared tests only when supported","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221020144351.1398099-2-chigot@adacore.com/mbox/"},{"id":6236,"url":"https://patchwork.plctlab.org/api/1.2/patches/6236/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221020151027.GA1300@delia.home/","msgid":"<20221020151027.GA1300@delia.home>","list_archive_url":null,"date":"2022-10-20T15:10:28","name":"[RFC,top-level] Add configure test-case","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221020151027.GA1300@delia.home/mbox/"},{"id":6286,"url":"https://patchwork.plctlab.org/api/1.2/patches/6286/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221020162911.1113338-1-hjl.tools@gmail.com/","msgid":"<20221020162911.1113338-1-hjl.tools@gmail.com>","list_archive_url":null,"date":"2022-10-20T16:29:11","name":"x86: Check VEX/EVEX encoding before checking vector operands","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221020162911.1113338-1-hjl.tools@gmail.com/mbox/"},{"id":7884,"url":"https://patchwork.plctlab.org/api/1.2/patches/7884/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7e53b7980f2b3b74d2250bc87f5db94b1d888a2d.camel@espressif.com/","msgid":"<7e53b7980f2b3b74d2250bc87f5db94b1d888a2d.camel@espressif.com>","list_archive_url":null,"date":"2022-10-22T12:53:54","name":"[1/5] bfd: xtensa: move common code from ld and gas","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7e53b7980f2b3b74d2250bc87f5db94b1d888a2d.camel@espressif.com/mbox/"},{"id":7885,"url":"https://patchwork.plctlab.org/api/1.2/patches/7885/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/63f2699e6ef3e6d1ca415a6ed1187d4f64297521.camel@espressif.com/","msgid":"<63f2699e6ef3e6d1ca415a6ed1187d4f64297521.camel@espressif.com>","list_archive_url":null,"date":"2022-10-22T12:55:16","name":"[2/5] gas: xtensa: add endianness, loops, booleans options","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/63f2699e6ef3e6d1ca415a6ed1187d4f64297521.camel@espressif.com/mbox/"},{"id":7886,"url":"https://patchwork.plctlab.org/api/1.2/patches/7886/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/34d2f747237aeeda595560cfded8096d9bd1c28c.camel@espressif.com/","msgid":"<34d2f747237aeeda595560cfded8096d9bd1c28c.camel@espressif.com>","list_archive_url":null,"date":"2022-10-22T12:56:02","name":"[3/5] ld: xtensa: use default LD command line options for endianness","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/34d2f747237aeeda595560cfded8096d9bd1c28c.camel@espressif.com/mbox/"},{"id":7891,"url":"https://patchwork.plctlab.org/api/1.2/patches/7891/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/535b6208c1718b9acf3258575e1ebc0a65af9f07.camel@espressif.com/","msgid":"<535b6208c1718b9acf3258575e1ebc0a65af9f07.camel@espressif.com>","list_archive_url":null,"date":"2022-10-22T13:56:44","name":"[5/5] gdb: xtensa: add support for esp32, esp32s2, esp32s3 isa-modules","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/535b6208c1718b9acf3258575e1ebc0a65af9f07.camel@espressif.com/mbox/"},{"id":10456,"url":"https://patchwork.plctlab.org/api/1.2/patches/10456/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221025013347.68282-1-nelson@rivosinc.com/","msgid":"<20221025013347.68282-1-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-10-25T01:33:46","name":"[committed,1/2] RISC-V: Improve link time complexity.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221025013347.68282-1-nelson@rivosinc.com/mbox/"},{"id":10454,"url":"https://patchwork.plctlab.org/api/1.2/patches/10454/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221025013347.68282-2-nelson@rivosinc.com/","msgid":"<20221025013347.68282-2-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-10-25T01:33:47","name":"[committed,2/2] RISC-V: Should reset `again'\'' flag for _bfd_riscv_relax_pc.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221025013347.68282-2-nelson@rivosinc.com/mbox/"},{"id":10536,"url":"https://patchwork.plctlab.org/api/1.2/patches/10536/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/bb7b87e4-1893-5c86-4a14-92bafc818b03@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-25T07:24:56","name":"[v5,1/8] x86: constify parse_insn()'\''s input","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/bb7b87e4-1893-5c86-4a14-92bafc818b03@suse.com/mbox/"},{"id":10537,"url":"https://patchwork.plctlab.org/api/1.2/patches/10537/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b9273ae6-0218-54f8-5374-b265ed13b71a@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-25T07:25:26","name":"[v5,1/8] x86: introduce Pass2 insn attribute","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b9273ae6-0218-54f8-5374-b265ed13b71a@suse.com/mbox/"},{"id":10541,"url":"https://patchwork.plctlab.org/api/1.2/patches/10541/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7250dab9-e218-e6dd-4c74-23da9f611ab4@suse.com/","msgid":"<7250dab9-e218-e6dd-4c74-23da9f611ab4@suse.com>","list_archive_url":null,"date":"2022-10-25T07:26:11","name":"[v5,3/8] x86: re-work insn/suffix recognition","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7250dab9-e218-e6dd-4c74-23da9f611ab4@suse.com/mbox/"},{"id":10540,"url":"https://patchwork.plctlab.org/api/1.2/patches/10540/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/13fc630f-e116-0099-5c9e-2697df6519d7@suse.com/","msgid":"<13fc630f-e116-0099-5c9e-2697df6519d7@suse.com>","list_archive_url":null,"date":"2022-10-25T07:26:40","name":"[v5,4/8] ix86: don'\''t recognize/derive Q suffix in the common case","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/13fc630f-e116-0099-5c9e-2697df6519d7@suse.com/mbox/"},{"id":10543,"url":"https://patchwork.plctlab.org/api/1.2/patches/10543/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/74db429d-d203-eab8-4ae1-18b9ad416b02@suse.com/","msgid":"<74db429d-d203-eab8-4ae1-18b9ad416b02@suse.com>","list_archive_url":null,"date":"2022-10-25T07:27:11","name":"[v5,5/8] x86-64: allow HLE store of accumulator to absolute 32-bit address","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/74db429d-d203-eab8-4ae1-18b9ad416b02@suse.com/mbox/"},{"id":10542,"url":"https://patchwork.plctlab.org/api/1.2/patches/10542/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2e2f7841-de4e-b5de-e8d9-a47a6a4113c8@suse.com/","msgid":"<2e2f7841-de4e-b5de-e8d9-a47a6a4113c8@suse.com>","list_archive_url":null,"date":"2022-10-25T07:27:35","name":"[v5,6/8] x86: move bad-use-of-TLS-reloc check","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2e2f7841-de4e-b5de-e8d9-a47a6a4113c8@suse.com/mbox/"},{"id":10545,"url":"https://patchwork.plctlab.org/api/1.2/patches/10545/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/421bc96e-7591-6980-48e9-5af8c8b0775a@suse.com/","msgid":"<421bc96e-7591-6980-48e9-5af8c8b0775a@suse.com>","list_archive_url":null,"date":"2022-10-25T07:28:27","name":"[v5,7/8] x86: drop (now) stray IsString","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/421bc96e-7591-6980-48e9-5af8c8b0775a@suse.com/mbox/"},{"id":10546,"url":"https://patchwork.plctlab.org/api/1.2/patches/10546/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/06ff83d4-4633-a07b-70e5-a8e049981dd4@suse.com/","msgid":"<06ff83d4-4633-a07b-70e5-a8e049981dd4@suse.com>","list_archive_url":null,"date":"2022-10-25T07:29:18","name":"[v5,8/8] x86: further re-work insn/suffix recognition to also cover MOVSX","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/06ff83d4-4633-a07b-70e5-a8e049981dd4@suse.com/mbox/"},{"id":10777,"url":"https://patchwork.plctlab.org/api/1.2/patches/10777/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6a8e7a71acccd0efb9789dfb3edfa307e83bdaa1.1666702934.git.research_trasio@irq.a4lg.com/","msgid":"<6a8e7a71acccd0efb9789dfb3edfa307e83bdaa1.1666702934.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-25T13:04:02","name":"[RFC] RISC-V: Allocate \"various\" operand type","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6a8e7a71acccd0efb9789dfb3edfa307e83bdaa1.1666702934.git.research_trasio@irq.a4lg.com/mbox/"},{"id":11062,"url":"https://patchwork.plctlab.org/api/1.2/patches/11062/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jAhwbXhxJHL66v@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-26T05:07:19","name":"PR29720, objdump -S crashes if build-id is missing","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jAhwbXhxJHL66v@squeak.grove.modra.org/mbox/"},{"id":11063,"url":"https://patchwork.plctlab.org/api/1.2/patches/11063/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jAxD+NxpMIah6s@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-26T05:08:20","name":"som.c buffer overflow","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jAxD+NxpMIah6s@squeak.grove.modra.org/mbox/"},{"id":11064,"url":"https://patchwork.plctlab.org/api/1.2/patches/11064/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jBYw4lfRQfOZhi@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-26T05:10:59","name":"som.c reloc sanity checking","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jBYw4lfRQfOZhi@squeak.grove.modra.org/mbox/"},{"id":11080,"url":"https://patchwork.plctlab.org/api/1.2/patches/11080/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jY7hygm01PelCY@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-26T06:51:26","name":"segfault in objdump.c reloc_at","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jY7hygm01PelCY@squeak.grove.modra.org/mbox/"},{"id":11081,"url":"https://patchwork.plctlab.org/api/1.2/patches/11081/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jZWIeIvCCYm9/g@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-26T06:53:12","name":"Correct ELF reloc size sanity check","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jZWIeIvCCYm9/g@squeak.grove.modra.org/mbox/"},{"id":11082,"url":"https://patchwork.plctlab.org/api/1.2/patches/11082/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221026070009.3663574-1-ysato@users.sourceforge.jp/","msgid":"<20221026070009.3663574-1-ysato@users.sourceforge.jp>","list_archive_url":null,"date":"2022-10-26T07:00:09","name":"opcodes: RX fix invalid output.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221026070009.3663574-1-ysato@users.sourceforge.jp/mbox/"},{"id":11089,"url":"https://patchwork.plctlab.org/api/1.2/patches/11089/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jhW48kuVC8Ig2d@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-26T07:27:23","name":"buffer overflow in _bfd_XX_print_ce_compressed_pdata","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jhW48kuVC8Ig2d@squeak.grove.modra.org/mbox/"},{"id":11157,"url":"https://patchwork.plctlab.org/api/1.2/patches/11157/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c52dbd16-7e1b-c356-7a92-1ff089564ef7@suse.cz/","msgid":"","list_archive_url":null,"date":"2022-10-26T08:47:09","name":"tests: use canonical option name","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c52dbd16-7e1b-c356-7a92-1ff089564ef7@suse.cz/mbox/"},{"id":11526,"url":"https://patchwork.plctlab.org/api/1.2/patches/11526/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027031915.4013-1-lifang_xia@linux.alibaba.com/","msgid":"<20221027031915.4013-1-lifang_xia@linux.alibaba.com>","list_archive_url":null,"date":"2022-10-27T03:19:15","name":"[v2] RISC-V: Optimize relax of GP/call with max_alignment.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027031915.4013-1-lifang_xia@linux.alibaba.com/mbox/"},{"id":11619,"url":"https://patchwork.plctlab.org/api/1.2/patches/11619/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9df9d9e5bb4c7594b76c40613a349b4d2364e9c5.1666854355.git.research_trasio@irq.a4lg.com/","msgid":"<9df9d9e5bb4c7594b76c40613a349b4d2364e9c5.1666854355.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-27T07:06:01","name":"include: Define macro to ignore -Wdeprecated-declarations on GCC","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9df9d9e5bb4c7594b76c40613a349b4d2364e9c5.1666854355.git.research_trasio@irq.a4lg.com/mbox/"},{"id":11627,"url":"https://patchwork.plctlab.org/api/1.2/patches/11627/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1o06O9Pp8ncCsOw@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-27T07:36:08","name":"Fuzzed files in archives","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1o06O9Pp8ncCsOw@squeak.grove.modra.org/mbox/"},{"id":11658,"url":"https://patchwork.plctlab.org/api/1.2/patches/11658/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027084808.37252-1-nelson@rivosinc.com/","msgid":"<20221027084808.37252-1-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-10-27T08:48:08","name":"[committed] RISC-V: Fix build failures for -Werror=sign-compare.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027084808.37252-1-nelson@rivosinc.com/mbox/"},{"id":11921,"url":"https://patchwork.plctlab.org/api/1.2/patches/11921/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027190052.10536-1-mark@harmstone.com/","msgid":"<20221027190052.10536-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-27T19:00:51","name":"[1/2] ld: Add section header stream to PDB files","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027190052.10536-1-mark@harmstone.com/mbox/"},{"id":11922,"url":"https://patchwork.plctlab.org/api/1.2/patches/11922/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027190052.10536-2-mark@harmstone.com/","msgid":"<20221027190052.10536-2-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-27T19:00:52","name":"[2/2] ld: Add publics stream to PDB files","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027190052.10536-2-mark@harmstone.com/mbox/"},{"id":11965,"url":"https://patchwork.plctlab.org/api/1.2/patches/11965/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027202719.32497-1-palmer@rivosinc.com/","msgid":"<20221027202719.32497-1-palmer@rivosinc.com>","list_archive_url":null,"date":"2022-10-27T20:27:18","name":"[1/2] gas: NEWS: Add a missing newline","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027202719.32497-1-palmer@rivosinc.com/mbox/"},{"id":11966,"url":"https://patchwork.plctlab.org/api/1.2/patches/11966/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027202719.32497-2-palmer@rivosinc.com/","msgid":"<20221027202719.32497-2-palmer@rivosinc.com>","list_archive_url":null,"date":"2022-10-27T20:27:19","name":"[2/2] gas: NEWS: Note support for RISC-V Zawrs","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027202719.32497-2-palmer@rivosinc.com/mbox/"},{"id":12016,"url":"https://patchwork.plctlab.org/api/1.2/patches/12016/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/21ec9a18-fa89-0828-f625-499680022ec7@linux.ibm.com/","msgid":"<21ec9a18-fa89-0828-f625-499680022ec7@linux.ibm.com>","list_archive_url":null,"date":"2022-10-28T00:35:19","name":"[COMMITTED] PowerPC: Add support for RFC02653 - Dense Math Facility","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/21ec9a18-fa89-0828-f625-499680022ec7@linux.ibm.com/mbox/"},{"id":12017,"url":"https://patchwork.plctlab.org/api/1.2/patches/12017/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fd94047d-a070-45a6-3840-c105391718e0@linux.ibm.com/","msgid":"","list_archive_url":null,"date":"2022-10-28T00:37:18","name":"[COMMITTED] PowerPC: Add support for RFC02658 - MMA+ Outer-Product, Instructions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fd94047d-a070-45a6-3840-c105391718e0@linux.ibm.com/mbox/"},{"id":12122,"url":"https://patchwork.plctlab.org/api/1.2/patches/12122/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ac4f3f3c7115a824f73aca6935789b14d33c9a58.1666939920.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-28T06:53:02","name":"RISC-V: Fix build failure for -Werror=maybe-uninitialized","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ac4f3f3c7115a824f73aca6935789b14d33c9a58.1666939920.git.research_trasio@irq.a4lg.com/mbox/"},{"id":12181,"url":"https://patchwork.plctlab.org/api/1.2/patches/12181/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221028093840.19164-1-nelson@rivosinc.com/","msgid":"<20221028093840.19164-1-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-10-28T09:38:40","name":"RISC-V: Added SiFive custom cache control extensions.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221028093840.19164-1-nelson@rivosinc.com/mbox/"},{"id":12211,"url":"https://patchwork.plctlab.org/api/1.2/patches/12211/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4a280588-a85b-6ed3-634b-2b9cbc128f86@suse.com/","msgid":"<4a280588-a85b-6ed3-634b-2b9cbc128f86@suse.com>","list_archive_url":null,"date":"2022-10-28T10:06:35","name":"RISC-V/gas: fix build with certain gcc versions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4a280588-a85b-6ed3-634b-2b9cbc128f86@suse.com/mbox/"},{"id":12249,"url":"https://patchwork.plctlab.org/api/1.2/patches/12249/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/eb0e1bff-675e-72db-b8b1-b0f0e50b7121@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-28T12:35:35","name":"x86: minor improvements to optimize_imm() (part III)","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/eb0e1bff-675e-72db-b8b1-b0f0e50b7121@suse.com/mbox/"},{"id":12382,"url":"https://patchwork.plctlab.org/api/1.2/patches/12382/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/17f57574936af82be381a1451eac56b3709b60bb.1666968673.git.research_trasio@irq.a4lg.com/","msgid":"<17f57574936af82be381a1451eac56b3709b60bb.1666968673.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-28T14:52:12","name":"RISC-V: Emit mapping symbol with ISA string if non-default arch is used","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/17f57574936af82be381a1451eac56b3709b60bb.1666968673.git.research_trasio@irq.a4lg.com/mbox/"},{"id":12627,"url":"https://patchwork.plctlab.org/api/1.2/patches/12627/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221029034432.49859-1-nelson@rivosinc.com/","msgid":"<20221029034432.49859-1-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-10-29T03:44:32","name":"[committed] RISC-V: Always generate mapping symbols at the start of the sections.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221029034432.49859-1-nelson@rivosinc.com/mbox/"},{"id":12629,"url":"https://patchwork.plctlab.org/api/1.2/patches/12629/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1yxgzNJg5M48uPI@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-29T04:52:19","name":"NULL dereference read in som_write_object_contents","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1yxgzNJg5M48uPI@squeak.grove.modra.org/mbox/"},{"id":12630,"url":"https://patchwork.plctlab.org/api/1.2/patches/12630/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1yxnSHLY+FeB5DQ@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-29T04:52:45","name":"Fix small objcopy memory leak","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1yxnSHLY+FeB5DQ@squeak.grove.modra.org/mbox/"},{"id":12631,"url":"https://patchwork.plctlab.org/api/1.2/patches/12631/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1yxxfpJz+Jx4KTh@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-29T04:53:25","name":"pef: sanity check before malloc","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1yxxfpJz+Jx4KTh@squeak.grove.modra.org/mbox/"},{"id":12950,"url":"https://patchwork.plctlab.org/api/1.2/patches/12950/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-2-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-2-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:36","name":"[V3,01/15] sframe.h: Add SFrame format definition","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-2-indu.bhagat@oracle.com/mbox/"},{"id":12952,"url":"https://patchwork.plctlab.org/api/1.2/patches/12952/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-3-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-3-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:37","name":"[V3,02/15] gas: add new command line option --gsframe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-3-indu.bhagat@oracle.com/mbox/"},{"id":12951,"url":"https://patchwork.plctlab.org/api/1.2/patches/12951/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-4-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-4-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:38","name":"[V3,03/15] gas: generate .sframe from CFI directives","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-4-indu.bhagat@oracle.com/mbox/"},{"id":12956,"url":"https://patchwork.plctlab.org/api/1.2/patches/12956/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-5-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-5-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:39","name":"[V3,04/15] gas: testsuite: add new tests for SFrame unwind info","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-5-indu.bhagat@oracle.com/mbox/"},{"id":12955,"url":"https://patchwork.plctlab.org/api/1.2/patches/12955/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-6-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-6-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:40","name":"[V3,05/15] libsframe: add the SFrame library","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-6-indu.bhagat@oracle.com/mbox/"},{"id":12959,"url":"https://patchwork.plctlab.org/api/1.2/patches/12959/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-7-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-7-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:41","name":"[V3,06/15] bfd: linker: merge .sframe sections","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-7-indu.bhagat@oracle.com/mbox/"},{"id":12961,"url":"https://patchwork.plctlab.org/api/1.2/patches/12961/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-8-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-8-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:42","name":"[V3,07/15] readelf/objdump: support for SFrame section","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-8-indu.bhagat@oracle.com/mbox/"},{"id":12962,"url":"https://patchwork.plctlab.org/api/1.2/patches/12962/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-9-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-9-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:43","name":"[V3,08/15] unwinder: generate backtrace using SFrame format","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-9-indu.bhagat@oracle.com/mbox/"},{"id":12963,"url":"https://patchwork.plctlab.org/api/1.2/patches/12963/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-10-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-10-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:44","name":"[V3,09/15] unwinder: Add SFrame unwinder tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-10-indu.bhagat@oracle.com/mbox/"},{"id":12964,"url":"https://patchwork.plctlab.org/api/1.2/patches/12964/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-11-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-11-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:45","name":"[V3,10/15] gdb: sim: buildsystem changes to accommodate libsframe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-11-indu.bhagat@oracle.com/mbox/"},{"id":12957,"url":"https://patchwork.plctlab.org/api/1.2/patches/12957/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-12-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-12-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:46","name":"[V3,11/15] libctf: add libsframe to LDFLAGS and LIBS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-12-indu.bhagat@oracle.com/mbox/"},{"id":12960,"url":"https://patchwork.plctlab.org/api/1.2/patches/12960/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-13-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-13-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:47","name":"[V3,12/15] src-release.sh: Add libsframe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-13-indu.bhagat@oracle.com/mbox/"},{"id":12953,"url":"https://patchwork.plctlab.org/api/1.2/patches/12953/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-14-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-14-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:48","name":"[V3,13/15] binutils/NEWS: add text for SFrame support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-14-indu.bhagat@oracle.com/mbox/"},{"id":12954,"url":"https://patchwork.plctlab.org/api/1.2/patches/12954/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-15-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-15-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:49","name":"[V3,14/15] gas/NEWS: add text about new command line option and SFrame support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-15-indu.bhagat@oracle.com/mbox/"},{"id":12958,"url":"https://patchwork.plctlab.org/api/1.2/patches/12958/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-16-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-16-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:50","name":"[V3,15/15] doc: add SFrame spec file","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-16-indu.bhagat@oracle.com/mbox/"},{"id":12988,"url":"https://patchwork.plctlab.org/api/1.2/patches/12988/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y15KFY32CyFhh/+u@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-30T09:55:33","name":"Pool section entries for DWP version 1","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y15KFY32CyFhh/+u@squeak.grove.modra.org/mbox/"},{"id":13076,"url":"https://patchwork.plctlab.org/api/1.2/patches/13076/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031001554.14615-1-mark@harmstone.com/","msgid":"<20221031001554.14615-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-31T00:15:52","name":"[v2,1/3] ld: Use %E in einfo in pdb.c","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031001554.14615-1-mark@harmstone.com/mbox/"},{"id":13078,"url":"https://patchwork.plctlab.org/api/1.2/patches/13078/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031001554.14615-2-mark@harmstone.com/","msgid":"<20221031001554.14615-2-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-31T00:15:53","name":"[v2,2/3] ld: Add section header stream to PDB files","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031001554.14615-2-mark@harmstone.com/mbox/"},{"id":13077,"url":"https://patchwork.plctlab.org/api/1.2/patches/13077/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031001554.14615-3-mark@harmstone.com/","msgid":"<20221031001554.14615-3-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-31T00:15:54","name":"[v2,3/3] ld: Add publics stream to PDB files","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031001554.14615-3-mark@harmstone.com/mbox/"},{"id":13106,"url":"https://patchwork.plctlab.org/api/1.2/patches/13106/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031030507.35588-2-haochen.jiang@intel.com/","msgid":"<20221031030507.35588-2-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-31T03:05:02","name":"[1/6] Support Intel AVX-IFMA","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031030507.35588-2-haochen.jiang@intel.com/mbox/"},{"id":13105,"url":"https://patchwork.plctlab.org/api/1.2/patches/13105/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031030507.35588-3-haochen.jiang@intel.com/","msgid":"<20221031030507.35588-3-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-31T03:05:03","name":"[2/6] Support Intel AVX-VNNI-INT8","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031030507.35588-3-haochen.jiang@intel.com/mbox/"},{"id":13103,"url":"https://patchwork.plctlab.org/api/1.2/patches/13103/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031030507.35588-4-haochen.jiang@intel.com/","msgid":"<20221031030507.35588-4-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-31T03:05:04","name":"[3/6] Support Intel CMPccXADD","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031030507.35588-4-haochen.jiang@intel.com/mbox/"},{"id":13101,"url":"https://patchwork.plctlab.org/api/1.2/patches/13101/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031030507.35588-5-haochen.jiang@intel.com/","msgid":"<20221031030507.35588-5-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-31T03:05:05","name":"[4/6] Add handler for more i386_cpu_flags","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031030507.35588-5-haochen.jiang@intel.com/mbox/"},{"id":13104,"url":"https://patchwork.plctlab.org/api/1.2/patches/13104/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031030507.35588-6-haochen.jiang@intel.com/","msgid":"<20221031030507.35588-6-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-31T03:05:06","name":"[5/6] Support Intel WRMSRNS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031030507.35588-6-haochen.jiang@intel.com/mbox/"},{"id":13102,"url":"https://patchwork.plctlab.org/api/1.2/patches/13102/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031030507.35588-7-haochen.jiang@intel.com/","msgid":"<20221031030507.35588-7-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-31T03:05:07","name":"[6/6] Support Intel MSRLIST","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031030507.35588-7-haochen.jiang@intel.com/mbox/"},{"id":13120,"url":"https://patchwork.plctlab.org/api/1.2/patches/13120/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031060601.38460-2-haochen.jiang@intel.com/","msgid":"<20221031060601.38460-2-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-31T06:06:00","name":"[1/2] i386: Add and ","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031060601.38460-2-haochen.jiang@intel.com/mbox/"},{"id":13121,"url":"https://patchwork.plctlab.org/api/1.2/patches/13121/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031060601.38460-3-haochen.jiang@intel.com/","msgid":"<20221031060601.38460-3-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-31T06:06:01","name":"[2/2] Support Intel AVX-NE-CONVERT","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031060601.38460-3-haochen.jiang@intel.com/mbox/"},{"id":13188,"url":"https://patchwork.plctlab.org/api/1.2/patches/13188/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9f6f8888-4dc1-a6b0-0590-35fc8a276369@suse.com/","msgid":"<9f6f8888-4dc1-a6b0-0590-35fc8a276369@suse.com>","list_archive_url":null,"date":"2022-10-31T10:18:20","name":"x86: drop bogus Tbyte","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9f6f8888-4dc1-a6b0-0590-35fc8a276369@suse.com/mbox/"},{"id":13213,"url":"https://patchwork.plctlab.org/api/1.2/patches/13213/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4f1aac95-fea5-2279-cb18-dfcdb51a2589@arm.com/","msgid":"<4f1aac95-fea5-2279-cb18-dfcdb51a2589@arm.com>","list_archive_url":null,"date":"2022-10-31T11:14:44","name":"aarch64: Add support for Common Short Sequence Compression extension","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4f1aac95-fea5-2279-cb18-dfcdb51a2589@arm.com/mbox/"}],"public":true,"mbox":"https://patchwork.plctlab.org/bundle/patchwork-bot/binutils-gdb_2022-10/mbox/"},{"id":7,"url":"https://patchwork.plctlab.org/api/1.2/bundles/7/","web_url":"https://patchwork.plctlab.org/bundle/patchwork-bot/binutils-gdb_2022-09/","project":{"id":2,"url":"https://patchwork.plctlab.org/api/1.2/projects/2/","name":"binutils-gdb","link_name":"binutils-gdb","list_id":"binutils.sourceware.org","list_email":"binutils@sourceware.org","web_url":"https://github.com/wangliu-iscas/Patchwork-Bundles/blob/main/binutils-gdb.md","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"name":"binutils-gdb_2022-09","owner":{"id":3,"url":"https://patchwork.plctlab.org/api/1.2/users/3/","username":"patchwork-bot","first_name":"","last_name":"","email":"ouuuleilei@gmail.com"},"patches":[{"id":1573,"url":"https://patchwork.plctlab.org/api/1.2/patches/1573/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930073211.2634-1-jiawei@iscas.ac.cn/","msgid":"<20220930073211.2634-1-jiawei@iscas.ac.cn>","list_archive_url":null,"date":"2022-09-30T07:32:11","name":"[V2] RISC-V: Add Smepmp CSR '\''mseccfg'\'' define and testcases.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930073211.2634-1-jiawei@iscas.ac.cn/mbox/"},{"id":1577,"url":"https://patchwork.plctlab.org/api/1.2/patches/1577/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/76fa0c3c-2303-ebdf-a765-ac4731581517@suse.com/","msgid":"<76fa0c3c-2303-ebdf-a765-ac4731581517@suse.com>","list_archive_url":null,"date":"2022-09-30T08:54:18","name":"objcopy: avoid \"shadowing\" of remove() function name","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/76fa0c3c-2303-ebdf-a765-ac4731581517@suse.com/mbox/"},{"id":1579,"url":"https://patchwork.plctlab.org/api/1.2/patches/1579/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930085852.71213-1-nelson@rivosinc.com/","msgid":"<20220930085852.71213-1-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-09-30T08:58:51","name":"[1/2] RISC-V: Output mapping symbols with ISA string.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930085852.71213-1-nelson@rivosinc.com/mbox/"},{"id":1578,"url":"https://patchwork.plctlab.org/api/1.2/patches/1578/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930085852.71213-2-nelson@rivosinc.com/","msgid":"<20220930085852.71213-2-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-09-30T08:58:52","name":"[2/2] RISC-V: Refer mapping symbol to R_RISCV_RELAX for rvc relaxations.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930085852.71213-2-nelson@rivosinc.com/mbox/"},{"id":1581,"url":"https://patchwork.plctlab.org/api/1.2/patches/1581/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930092058.71286-1-nelson@rivosinc.com/","msgid":"<20220930092058.71286-1-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-09-30T09:20:57","name":"[1/2] RISC-V: Output mapping symbols with ISA string.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930092058.71286-1-nelson@rivosinc.com/mbox/"},{"id":1580,"url":"https://patchwork.plctlab.org/api/1.2/patches/1580/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930092058.71286-2-nelson@rivosinc.com/","msgid":"<20220930092058.71286-2-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-09-30T09:20:58","name":"[2/2] RISC-V: Refer mapping symbol to R_RISCV_RELAX for rvc relaxations.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930092058.71286-2-nelson@rivosinc.com/mbox/"},{"id":1582,"url":"https://patchwork.plctlab.org/api/1.2/patches/1582/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5874dd79-0cf5-d65c-7ea2-13adfc799c0f@suse.com/","msgid":"<5874dd79-0cf5-d65c-7ea2-13adfc799c0f@suse.com>","list_archive_url":null,"date":"2022-09-30T09:41:29","name":"RISC-V: fix build after \"Add support for arbitrary immediate encoding formats\"","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5874dd79-0cf5-d65c-7ea2-13adfc799c0f@suse.com/mbox/"},{"id":1583,"url":"https://patchwork.plctlab.org/api/1.2/patches/1583/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/57d8ac2a-5757-3776-9924-99c17ca69938@suse.com/","msgid":"<57d8ac2a-5757-3776-9924-99c17ca69938@suse.com>","list_archive_url":null,"date":"2022-09-30T09:42:08","name":"RISC-V: fallout from \"re-arrange opcode table for consistent alias handling\"","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/57d8ac2a-5757-3776-9924-99c17ca69938@suse.com/mbox/"},{"id":1584,"url":"https://patchwork.plctlab.org/api/1.2/patches/1584/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e76ef8f7-72b9-5103-cb43-9608af01d017@suse.com/","msgid":"","list_archive_url":null,"date":"2022-09-30T09:42:50","name":"RISC-V: don'\''t cast expressions'\'' X_add_number to long in diagnostics","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e76ef8f7-72b9-5103-cb43-9608af01d017@suse.com/mbox/"},{"id":1585,"url":"https://patchwork.plctlab.org/api/1.2/patches/1585/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/61355429-24b3-17d0-ab03-6fa57ee861d5@suse.cz/","msgid":"<61355429-24b3-17d0-ab03-6fa57ee861d5@suse.cz>","list_archive_url":null,"date":"2022-09-30T09:48:52","name":"[RFC] add --enable-zstd-compressed-debug-sections configure option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/61355429-24b3-17d0-ab03-6fa57ee861d5@suse.cz/mbox/"},{"id":1586,"url":"https://patchwork.plctlab.org/api/1.2/patches/1586/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930103919.323690-1-christoph.muellner@vrull.eu/","msgid":"<20220930103919.323690-1-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2022-09-30T10:39:19","name":"RISC-V: Eliminate long-casts of X_add_number in diagnostics","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930103919.323690-1-christoph.muellner@vrull.eu/mbox/"},{"id":1590,"url":"https://patchwork.plctlab.org/api/1.2/patches/1590/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/DM6PR12MB4219C943049C6D883DEA3E55E7569@DM6PR12MB4219.namprd12.prod.outlook.com/","msgid":"","list_archive_url":null,"date":"2022-09-30T11:41:37","name":"[V2] Ignore DWARF debug information for -gsplit-dwarf with dwarf-5.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/DM6PR12MB4219C943049C6D883DEA3E55E7569@DM6PR12MB4219.namprd12.prod.outlook.com/mbox/"},{"id":1591,"url":"https://patchwork.plctlab.org/api/1.2/patches/1591/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c10321f9-d289-ef84-d263-bc278fb3d31b@suse.com/","msgid":"","list_archive_url":null,"date":"2022-09-30T11:59:04","name":"[1/4] RISC-V/gas: drop riscv_subsets static variable","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c10321f9-d289-ef84-d263-bc278fb3d31b@suse.com/mbox/"},{"id":1593,"url":"https://patchwork.plctlab.org/api/1.2/patches/1593/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3244eea0-c18c-e49a-4588-d69423130226@suse.com/","msgid":"<3244eea0-c18c-e49a-4588-d69423130226@suse.com>","list_archive_url":null,"date":"2022-09-30T11:59:23","name":"[2/4] RISC-V/gas: drop stray call to install_insn()","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3244eea0-c18c-e49a-4588-d69423130226@suse.com/mbox/"},{"id":1592,"url":"https://patchwork.plctlab.org/api/1.2/patches/1592/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/385d01fd-7e57-1f3f-1bae-30aa0c313d63@suse.com/","msgid":"<385d01fd-7e57-1f3f-1bae-30aa0c313d63@suse.com>","list_archive_url":null,"date":"2022-09-30T11:59:45","name":"[3/4] RISC-V/gas: don'\''t open-code insn_length()","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/385d01fd-7e57-1f3f-1bae-30aa0c313d63@suse.com/mbox/"},{"id":1594,"url":"https://patchwork.plctlab.org/api/1.2/patches/1594/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f5757acf-7b90-a0e3-5eea-3b97cc226930@suse.com/","msgid":"","list_archive_url":null,"date":"2022-09-30T12:00:12","name":"[4/4] RISC-V/gas: allow generating up to 176-bit instructions with .insn","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f5757acf-7b90-a0e3-5eea-3b97cc226930@suse.com/mbox/"},{"id":1596,"url":"https://patchwork.plctlab.org/api/1.2/patches/1596/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930140503.38233-1-chigot@adacore.com/","msgid":"<20220930140503.38233-1-chigot@adacore.com>","list_archive_url":null,"date":"2022-09-30T14:05:03","name":"ld/testsuite: consistently add board_ldflags when linking with GCC","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930140503.38233-1-chigot@adacore.com/mbox/"}],"public":true,"mbox":"https://patchwork.plctlab.org/bundle/patchwork-bot/binutils-gdb_2022-09/mbox/"},{"id":9,"url":"https://patchwork.plctlab.org/api/1.2/bundles/9/","web_url":"https://patchwork.plctlab.org/bundle/patchwork-bot/binutils-gdb_2022-11/","project":{"id":2,"url":"https://patchwork.plctlab.org/api/1.2/projects/2/","name":"binutils-gdb","link_name":"binutils-gdb","list_id":"binutils.sourceware.org","list_email":"binutils@sourceware.org","web_url":"https://github.com/wangliu-iscas/Patchwork-Bundles/blob/main/binutils-gdb.md","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"name":"binutils-gdb_2022-11","owner":{"id":3,"url":"https://patchwork.plctlab.org/api/1.2/users/3/","username":"patchwork-bot","first_name":"","last_name":"","email":"ouuuleilei@gmail.com"},"patches":[{"id":13337,"url":"https://patchwork.plctlab.org/api/1.2/patches/13337/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031160625.684434-1-hjl.tools@gmail.com/","msgid":"<20221031160625.684434-1-hjl.tools@gmail.com>","list_archive_url":null,"date":"2022-10-31T16:06:25","name":"x86: Silence GCC 12 warning on tc-i386.c","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031160625.684434-1-hjl.tools@gmail.com/mbox/"},{"id":13350,"url":"https://patchwork.plctlab.org/api/1.2/patches/13350/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c8d25b29-37fe-9623-a799-e67e1f991743@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-31T17:00:56","name":"x86: simplify expressions in update_imm()","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c8d25b29-37fe-9623-a799-e67e1f991743@suse.com/mbox/"},{"id":13487,"url":"https://patchwork.plctlab.org/api/1.2/patches/13487/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/CAMe9rOohVjin92PTeeiu_dvAtzYJn4dGtu5E=OxYfbyteraZWw@mail.gmail.com/","msgid":"","list_archive_url":null,"date":"2022-11-01T00:08:04","name":"binutils: Run PR binutils/26160 test","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/CAMe9rOohVjin92PTeeiu_dvAtzYJn4dGtu5E=OxYfbyteraZWw@mail.gmail.com/mbox/"},{"id":13621,"url":"https://patchwork.plctlab.org/api/1.2/patches/13621/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221101105724.1527333-1-aburgess@redhat.com/","msgid":"<20221101105724.1527333-1-aburgess@redhat.com>","list_archive_url":null,"date":"2022-11-01T10:57:24","name":"[PUSHED] opcodes/arm: silence compiler warning about uninitialized variable use","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221101105724.1527333-1-aburgess@redhat.com/mbox/"},{"id":13628,"url":"https://patchwork.plctlab.org/api/1.2/patches/13628/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221101111802.1532080-1-aburgess@redhat.com/","msgid":"<20221101111802.1532080-1-aburgess@redhat.com>","list_archive_url":null,"date":"2022-11-01T11:18:02","name":"[PUSHED] opcodes/arm: don'\''t pass non-string literal to printf like function","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221101111802.1532080-1-aburgess@redhat.com/mbox/"},{"id":13747,"url":"https://patchwork.plctlab.org/api/1.2/patches/13747/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/yw8jbkpqk6vw.fsf@arm.com/","msgid":"","list_archive_url":null,"date":"2022-11-01T15:54:11","name":"[Binutils-2.39,backport,GAS] arm: Use DWARF numbering convention for pseudo-register representation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/yw8jbkpqk6vw.fsf@arm.com/mbox/"},{"id":13993,"url":"https://patchwork.plctlab.org/api/1.2/patches/13993/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221102020752.24441-1-mark@harmstone.com/","msgid":"<20221102020752.24441-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-11-02T02:07:52","name":"ld: Add module information substream to PDB files","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221102020752.24441-1-mark@harmstone.com/mbox/"},{"id":14028,"url":"https://patchwork.plctlab.org/api/1.2/patches/14028/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221102050430.1053-1-nelson@rivosinc.com/","msgid":"<20221102050430.1053-1-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-11-02T05:04:30","name":"[committed] RISC-V: Fixed the missing $x+arch when adding odd paddings for alignment.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221102050430.1053-1-nelson@rivosinc.com/mbox/"},{"id":14043,"url":"https://patchwork.plctlab.org/api/1.2/patches/14043/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221102063046.31551-1-rjiejie@linux.alibaba.com/","msgid":"<20221102063046.31551-1-rjiejie@linux.alibaba.com>","list_archive_url":null,"date":"2022-11-02T06:30:46","name":"gas/doc/internals.texi: fix typo","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221102063046.31551-1-rjiejie@linux.alibaba.com/mbox/"},{"id":14069,"url":"https://patchwork.plctlab.org/api/1.2/patches/14069/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221102080112.33378-1-rjiejie@linux.alibaba.com/","msgid":"<20221102080112.33378-1-rjiejie@linux.alibaba.com>","list_archive_url":null,"date":"2022-11-02T08:01:12","name":"[v2] Support multiple .eh_frame sections","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221102080112.33378-1-rjiejie@linux.alibaba.com/mbox/"},{"id":14409,"url":"https://patchwork.plctlab.org/api/1.2/patches/14409/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221102172923.4009281-1-christophe.lyon@arm.com/","msgid":"<20221102172923.4009281-1-christophe.lyon@arm.com>","list_archive_url":null,"date":"2022-11-02T17:29:23","name":"arm: PR 29739 Fix typo where '\''; '\'' should not have been replaced with '\''@'\''","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221102172923.4009281-1-christophe.lyon@arm.com/mbox/"},{"id":14588,"url":"https://patchwork.plctlab.org/api/1.2/patches/14588/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221103020409.37322-1-rjiejie@linux.alibaba.com/","msgid":"<20221103020409.37322-1-rjiejie@linux.alibaba.com>","list_archive_url":null,"date":"2022-11-03T02:04:09","name":"[v3] Support multiple .eh_frame sections","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221103020409.37322-1-rjiejie@linux.alibaba.com/mbox/"},{"id":14602,"url":"https://patchwork.plctlab.org/api/1.2/patches/14602/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221103024604.614-1-mark@harmstone.com/","msgid":"<20221103024604.614-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-11-03T02:46:04","name":"[v2] ld: Add module information substream to PDB files","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221103024604.614-1-mark@harmstone.com/mbox/"},{"id":14706,"url":"https://patchwork.plctlab.org/api/1.2/patches/14706/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221103071519.3510462-1-luis.machado@arm.com/","msgid":"<20221103071519.3510462-1-luis.machado@arm.com>","list_archive_url":null,"date":"2022-11-03T07:15:19","name":"[opcodes/arm] Fix potential null pointer dereferences","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221103071519.3510462-1-luis.machado@arm.com/mbox/"},{"id":14840,"url":"https://patchwork.plctlab.org/api/1.2/patches/14840/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/283a86ebf0941f0f63dc1a590ec3d547bd5d69e8.1667478033.git.research_trasio@irq.a4lg.com/","msgid":"<283a86ebf0941f0f63dc1a590ec3d547bd5d69e8.1667478033.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-03T12:26:28","name":"[REVIEW,ONLY,1/2] NEAR-RATIFICATION RISC-V: Add '\''Ssstateen'\'' extension and its CSRs","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/283a86ebf0941f0f63dc1a590ec3d547bd5d69e8.1667478033.git.research_trasio@irq.a4lg.com/mbox/"},{"id":14841,"url":"https://patchwork.plctlab.org/api/1.2/patches/14841/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8083ad9d5339afdeb7f1ba88ee6af0665dcc76d5.1667478033.git.research_trasio@irq.a4lg.com/","msgid":"<8083ad9d5339afdeb7f1ba88ee6af0665dcc76d5.1667478033.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-03T12:26:29","name":"[REVIEW,ONLY,2/2] NEAR-RATIFICATION RISC-V: Add platform property/capability extensions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8083ad9d5339afdeb7f1ba88ee6af0665dcc76d5.1667478033.git.research_trasio@irq.a4lg.com/mbox/"},{"id":14894,"url":"https://patchwork.plctlab.org/api/1.2/patches/14894/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e53fbf5025e59fe6a3481b9c1fe37e4f6cf6e03d.1667483581.git.aburgess@redhat.com/","msgid":"","list_archive_url":null,"date":"2022-11-03T13:58:12","name":"[1/2] opcodes/mips: use .word/.short for undefined instructions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e53fbf5025e59fe6a3481b9c1fe37e4f6cf6e03d.1667483581.git.aburgess@redhat.com/mbox/"},{"id":14893,"url":"https://patchwork.plctlab.org/api/1.2/patches/14893/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ca81edb86580566b1641ad140eb2bed385160ab7.1667483581.git.aburgess@redhat.com/","msgid":"","list_archive_url":null,"date":"2022-11-03T13:58:13","name":"[2/2] libopcodes/mips: add support for disassembler styling","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ca81edb86580566b1641ad140eb2bed385160ab7.1667483581.git.aburgess@redhat.com/mbox/"},{"id":15465,"url":"https://patchwork.plctlab.org/api/1.2/patches/15465/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/926e5154-b40b-9df8-d770-a8bf7d40e40e@suse.com/","msgid":"<926e5154-b40b-9df8-d770-a8bf7d40e40e@suse.com>","list_archive_url":null,"date":"2022-11-04T10:50:38","name":"[v6,1/7] x86: constify parse_insn()'\''s input","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/926e5154-b40b-9df8-d770-a8bf7d40e40e@suse.com/mbox/"},{"id":15466,"url":"https://patchwork.plctlab.org/api/1.2/patches/15466/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/07ef67fd-752c-ad1f-b8cb-4eaec1f420fc@suse.com/","msgid":"<07ef67fd-752c-ad1f-b8cb-4eaec1f420fc@suse.com>","list_archive_url":null,"date":"2022-11-04T10:51:34","name":"[v6,2/7] x86: re-work insn/suffix recognition","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/07ef67fd-752c-ad1f-b8cb-4eaec1f420fc@suse.com/mbox/"},{"id":15467,"url":"https://patchwork.plctlab.org/api/1.2/patches/15467/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ee8fd655-19a5-d944-0f5e-4351b88a59f9@suse.com/","msgid":"","list_archive_url":null,"date":"2022-11-04T10:52:02","name":"[v6,3/7] ix86: don'\''t recognize/derive Q suffix in the common case","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ee8fd655-19a5-d944-0f5e-4351b88a59f9@suse.com/mbox/"},{"id":15468,"url":"https://patchwork.plctlab.org/api/1.2/patches/15468/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/15ab2cf5-f1ac-e882-c415-6318f1bcc7f0@suse.com/","msgid":"<15ab2cf5-f1ac-e882-c415-6318f1bcc7f0@suse.com>","list_archive_url":null,"date":"2022-11-04T10:52:31","name":"[v6,4/7] x86-64: allow HLE store of accumulator to absolute 32-bit address","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/15ab2cf5-f1ac-e882-c415-6318f1bcc7f0@suse.com/mbox/"},{"id":15470,"url":"https://patchwork.plctlab.org/api/1.2/patches/15470/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/352d1e49-ac9f-ee86-7e9d-74f79744268b@suse.com/","msgid":"<352d1e49-ac9f-ee86-7e9d-74f79744268b@suse.com>","list_archive_url":null,"date":"2022-11-04T10:53:14","name":"[v6,5/7] x86: move bad-use-of-TLS-reloc check","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/352d1e49-ac9f-ee86-7e9d-74f79744268b@suse.com/mbox/"},{"id":15469,"url":"https://patchwork.plctlab.org/api/1.2/patches/15469/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c1913bf6-7328-e45f-69f1-20da1954af43@suse.com/","msgid":"","list_archive_url":null,"date":"2022-11-04T10:53:52","name":"[v6,6/7] x86: drop (now) stray IsString","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c1913bf6-7328-e45f-69f1-20da1954af43@suse.com/mbox/"},{"id":15471,"url":"https://patchwork.plctlab.org/api/1.2/patches/15471/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2baf6a9d-c1bf-660d-bbca-99b1604f5478@suse.com/","msgid":"<2baf6a9d-c1bf-660d-bbca-99b1604f5478@suse.com>","list_archive_url":null,"date":"2022-11-04T10:54:30","name":"[v6,7/7] x86: further re-work insn/suffix recognition to also cover MOVSX","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2baf6a9d-c1bf-660d-bbca-99b1604f5478@suse.com/mbox/"},{"id":15472,"url":"https://patchwork.plctlab.org/api/1.2/patches/15472/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104110132.694984-1-aburgess@redhat.com/","msgid":"<20221104110132.694984-1-aburgess@redhat.com>","list_archive_url":null,"date":"2022-11-04T11:01:32","name":"[PUSHED] opcodes/arm: silence compiler warning about uninitialized variable use","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104110132.694984-1-aburgess@redhat.com/mbox/"},{"id":15473,"url":"https://patchwork.plctlab.org/api/1.2/patches/15473/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104110214.129095-1-christophe.lyon@arm.com/","msgid":"<20221104110214.129095-1-christophe.lyon@arm.com>","list_archive_url":null,"date":"2022-11-04T11:02:14","name":"configure: require libzstd >= 1.4.0","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104110214.129095-1-christophe.lyon@arm.com/mbox/"},{"id":15485,"url":"https://patchwork.plctlab.org/api/1.2/patches/15485/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104115038.8957-1-nelson@rivosinc.com/","msgid":"<20221104115038.8957-1-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-11-04T11:50:37","name":"[1/2] RISC-V: File-level architecture shouldn'\''t be affected by section-level ones.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104115038.8957-1-nelson@rivosinc.com/mbox/"},{"id":15486,"url":"https://patchwork.plctlab.org/api/1.2/patches/15486/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104115038.8957-2-nelson@rivosinc.com/","msgid":"<20221104115038.8957-2-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-11-04T11:50:38","name":"[2/2] RISC-V: Clarify the suppress rule of mapping symbol with architecture string.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104115038.8957-2-nelson@rivosinc.com/mbox/"},{"id":15509,"url":"https://patchwork.plctlab.org/api/1.2/patches/15509/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/cc133c88-9ce9-5e3a-a8f7-ad72766862b9@suse.com/","msgid":"","list_archive_url":null,"date":"2022-11-04T13:12:07","name":"x86: adjust recently introduced testcases","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/cc133c88-9ce9-5e3a-a8f7-ad72766862b9@suse.com/mbox/"},{"id":15679,"url":"https://patchwork.plctlab.org/api/1.2/patches/15679/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104163328.2274371-1-chigot@adacore.com/","msgid":"<20221104163328.2274371-1-chigot@adacore.com>","list_archive_url":null,"date":"2022-11-04T16:33:28","name":"ld/testsuite: skip tests related to -shared when disabled","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104163328.2274371-1-chigot@adacore.com/mbox/"},{"id":15751,"url":"https://patchwork.plctlab.org/api/1.2/patches/15751/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104190216.1352855-1-indu.bhagat@oracle.com/","msgid":"<20221104190216.1352855-1-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-04T19:02:16","name":"[V3.1,11/15] libctf: add libsframe to LDFLAGS and LIBS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104190216.1352855-1-indu.bhagat@oracle.com/mbox/"},{"id":15792,"url":"https://patchwork.plctlab.org/api/1.2/patches/15792/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104205547.3728827-1-hjl.tools@gmail.com/","msgid":"<20221104205547.3728827-1-hjl.tools@gmail.com>","list_archive_url":null,"date":"2022-11-04T20:55:47","name":"i386: Check invalid (%dx) usage","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104205547.3728827-1-hjl.tools@gmail.com/mbox/"},{"id":15794,"url":"https://patchwork.plctlab.org/api/1.2/patches/15794/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104210134.1721620-1-indu.bhagat@oracle.com/","msgid":"<20221104210134.1721620-1-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-04T21:01:34","name":"[V3.2,11/15] libctf: add libsframe to LDFLAGS and LIBS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104210134.1721620-1-indu.bhagat@oracle.com/mbox/"},{"id":15959,"url":"https://patchwork.plctlab.org/api/1.2/patches/15959/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c620070e3e335df2b487d3836e20d251dac37525.1667651354.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-11-05T12:29:07","name":"[01/12] RISC-V: Remove unnecessary empty matching file","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c620070e3e335df2b487d3836e20d251dac37525.1667651354.git.research_trasio@irq.a4lg.com/mbox/"},{"id":15961,"url":"https://patchwork.plctlab.org/api/1.2/patches/15961/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4496235002a396043598ab9755bd8eda5c077b1f.1667651354.git.research_trasio@irq.a4lg.com/","msgid":"<4496235002a396043598ab9755bd8eda5c077b1f.1667651354.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-05T12:29:08","name":"[02/12] RISC-V: Tidy disassembler corner case tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4496235002a396043598ab9755bd8eda5c077b1f.1667651354.git.research_trasio@irq.a4lg.com/mbox/"},{"id":15960,"url":"https://patchwork.plctlab.org/api/1.2/patches/15960/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a9229a2798480f00bf12ac3c435b3ef57f867022.1667651354.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-11-05T12:29:09","name":"[03/12] RISC-V: Tidying related to '\''Zfinx'\'' disassembler test","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a9229a2798480f00bf12ac3c435b3ef57f867022.1667651354.git.research_trasio@irq.a4lg.com/mbox/"},{"id":15962,"url":"https://patchwork.plctlab.org/api/1.2/patches/15962/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6a020edd0e114a003edbaafe1088a040e9fa07e7.1667651354.git.research_trasio@irq.a4lg.com/","msgid":"<6a020edd0e114a003edbaafe1088a040e9fa07e7.1667651354.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-05T12:29:10","name":"[04/12] RISC-V: GAS: Add basic shared test utilities","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6a020edd0e114a003edbaafe1088a040e9fa07e7.1667651354.git.research_trasio@irq.a4lg.com/mbox/"},{"id":15966,"url":"https://patchwork.plctlab.org/api/1.2/patches/15966/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6fc2851a4161edc429089bd2bbd9c2bb4c0c118f.1667651354.git.research_trasio@irq.a4lg.com/","msgid":"<6fc2851a4161edc429089bd2bbd9c2bb4c0c118f.1667651354.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-05T12:29:11","name":"[05/12] RISC-V: Redefine \"nop\" test","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6fc2851a4161edc429089bd2bbd9c2bb4c0c118f.1667651354.git.research_trasio@irq.a4lg.com/mbox/"},{"id":15963,"url":"https://patchwork.plctlab.org/api/1.2/patches/15963/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7311ed3d2429000e18877d7af594890da170a7a3.1667651354.git.research_trasio@irq.a4lg.com/","msgid":"<7311ed3d2429000e18877d7af594890da170a7a3.1667651354.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-05T12:29:12","name":"[06/12] RISC-V: Reorganize/enhance {sign, zero}-extension instructions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7311ed3d2429000e18877d7af594890da170a7a3.1667651354.git.research_trasio@irq.a4lg.com/mbox/"},{"id":15968,"url":"https://patchwork.plctlab.org/api/1.2/patches/15968/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ac99c9696c156207f06c18f2d6bf423c96c5876b.1667651354.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-11-05T12:29:13","name":"[07/12] RISC-V: Combine complex extension error handling tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ac99c9696c156207f06c18f2d6bf423c96c5876b.1667651354.git.research_trasio@irq.a4lg.com/mbox/"},{"id":15970,"url":"https://patchwork.plctlab.org/api/1.2/patches/15970/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9378b9505e3e230e0a690c56e67d253e2a0f5864.1667651354.git.research_trasio@irq.a4lg.com/","msgid":"<9378b9505e3e230e0a690c56e67d253e2a0f5864.1667651354.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-05T12:29:14","name":"[08/12] RISC-V: Refine/enhance '\''M'\''/'\''Zmmul'\'' extension tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9378b9505e3e230e0a690c56e67d253e2a0f5864.1667651354.git.research_trasio@irq.a4lg.com/mbox/"},{"id":15964,"url":"https://patchwork.plctlab.org/api/1.2/patches/15964/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/82832a67f240d5857fd502d4b74fd7d841ee2d6e.1667651354.git.research_trasio@irq.a4lg.com/","msgid":"<82832a67f240d5857fd502d4b74fd7d841ee2d6e.1667651354.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-05T12:29:15","name":"[09/12] RISC-V: Combine/enhance '\''Zicbo[mz]'\'' extension tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/82832a67f240d5857fd502d4b74fd7d841ee2d6e.1667651354.git.research_trasio@irq.a4lg.com/mbox/"},{"id":15965,"url":"https://patchwork.plctlab.org/api/1.2/patches/15965/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9c47e59868a64b13e5a7bb487e3619d4f1497d78.1667651354.git.research_trasio@irq.a4lg.com/","msgid":"<9c47e59868a64b13e5a7bb487e3619d4f1497d78.1667651354.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-05T12:29:16","name":"[10/12] RISC-V: Enhance '\''Zicbop'\'' testcases","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9c47e59868a64b13e5a7bb487e3619d4f1497d78.1667651354.git.research_trasio@irq.a4lg.com/mbox/"},{"id":15967,"url":"https://patchwork.plctlab.org/api/1.2/patches/15967/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2d9befc5bc5eed80b6bd7da6d092a61b1162ecac.1667651354.git.research_trasio@irq.a4lg.com/","msgid":"<2d9befc5bc5eed80b6bd7da6d092a61b1162ecac.1667651354.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-05T12:29:17","name":"[11/12] RISC-V: Reorganize/enhance '\''Zb*'\'' extension tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2d9befc5bc5eed80b6bd7da6d092a61b1162ecac.1667651354.git.research_trasio@irq.a4lg.com/mbox/"},{"id":15969,"url":"https://patchwork.plctlab.org/api/1.2/patches/15969/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f1c5589ab606b74eeac98e3dafd4a7903450d3b2.1667651354.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-11-05T12:29:18","name":"[12/12] RISC-V: Combine/enhance '\''Zk*'\''/'\''Zbk*'\'' extension tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f1c5589ab606b74eeac98e3dafd4a7903450d3b2.1667651354.git.research_trasio@irq.a4lg.com/mbox/"},{"id":16066,"url":"https://patchwork.plctlab.org/api/1.2/patches/16066/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221106053640.1649752-1-indu.bhagat@oracle.com/","msgid":"<20221106053640.1649752-1-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-06T05:36:40","name":"[V3.1,03/15] gas: generate .sframe from CFI directives","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221106053640.1649752-1-indu.bhagat@oracle.com/mbox/"},{"id":16379,"url":"https://patchwork.plctlab.org/api/1.2/patches/16379/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221107112805.3332619-1-och95@yandex.ru/","msgid":"<20221107112805.3332619-1-och95@yandex.ru>","list_archive_url":null,"date":"2022-11-07T11:28:05","name":"gold/aarch64: Fix adrp distance check","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221107112805.3332619-1-och95@yandex.ru/mbox/"},{"id":16400,"url":"https://patchwork.plctlab.org/api/1.2/patches/16400/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221107124620.1271470-1-christoph.muellner@vrull.eu/","msgid":"<20221107124620.1271470-1-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2022-11-07T12:46:20","name":"RISC-V: xtheadfmemidx: Use fp register in mnemonics","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221107124620.1271470-1-christoph.muellner@vrull.eu/mbox/"},{"id":16594,"url":"https://patchwork.plctlab.org/api/1.2/patches/16594/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/CACVBkZ+kM2xcpwk5zHQ4bqDV7dbPjZ6cMU9tR-h62+tDTgi3Tw@mail.gmail.com/","msgid":"","list_archive_url":null,"date":"2022-11-07T17:53:35","name":"GAS fix section alignment for aarch64-pe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/CACVBkZ+kM2xcpwk5zHQ4bqDV7dbPjZ6cMU9tR-h62+tDTgi3Tw@mail.gmail.com/mbox/"},{"id":16744,"url":"https://patchwork.plctlab.org/api/1.2/patches/16744/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221107222809.924195-1-indu.bhagat@oracle.com/","msgid":"<20221107222809.924195-1-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-07T22:28:09","name":"[V3.3,11/15] libctf: add libsframe to LDFLAGS and LIBS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221107222809.924195-1-indu.bhagat@oracle.com/mbox/"},{"id":16797,"url":"https://patchwork.plctlab.org/api/1.2/patches/16797/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221108012556.66467-1-haochen.jiang@intel.com/","msgid":"<20221108012556.66467-1-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-11-08T01:25:56","name":"x86: Correct wrong comments in vex_w_table","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221108012556.66467-1-haochen.jiang@intel.com/mbox/"},{"id":16884,"url":"https://patchwork.plctlab.org/api/1.2/patches/16884/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221108054530.796968-1-markus.t.metzger@intel.com/","msgid":"<20221108054530.796968-1-markus.t.metzger@intel.com>","list_archive_url":null,"date":"2022-11-08T05:45:29","name":"[1/2] gprofng: make cpu identification available to others","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221108054530.796968-1-markus.t.metzger@intel.com/mbox/"},{"id":16885,"url":"https://patchwork.plctlab.org/api/1.2/patches/16885/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221108054530.796968-2-markus.t.metzger@intel.com/","msgid":"<20221108054530.796968-2-markus.t.metzger@intel.com>","list_archive_url":null,"date":"2022-11-08T05:45:30","name":"[2/2] gdb, btrace: use cpuident.h to implement btrace_this_cpu","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221108054530.796968-2-markus.t.metzger@intel.com/mbox/"},{"id":16995,"url":"https://patchwork.plctlab.org/api/1.2/patches/16995/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ea0daf08-4923-ebfa-dcfe-699c43d63822@suse.com/","msgid":"","list_archive_url":null,"date":"2022-11-08T11:29:40","name":"x86/Intel: don'\''t accept malformed EXTRQ / INSERTQ","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ea0daf08-4923-ebfa-dcfe-699c43d63822@suse.com/mbox/"},{"id":17057,"url":"https://patchwork.plctlab.org/api/1.2/patches/17057/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221108141352.6613-1-jwilk@jwilk.net/","msgid":"<20221108141352.6613-1-jwilk@jwilk.net>","list_archive_url":null,"date":"2022-11-08T14:13:52","name":"Fix typos in the list of objdump options","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221108141352.6613-1-jwilk@jwilk.net/mbox/"},{"id":17117,"url":"https://patchwork.plctlab.org/api/1.2/patches/17117/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1667924955-9218-1-git-send-email-apinski@marvell.com/","msgid":"<1667924955-9218-1-git-send-email-apinski@marvell.com>","list_archive_url":null,"date":"2022-11-08T16:29:15","name":"Use toplevel configure for GMP and MPFR for gdb","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1667924955-9218-1-git-send-email-apinski@marvell.com/mbox/"},{"id":17160,"url":"https://patchwork.plctlab.org/api/1.2/patches/17160/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/27382086-397f-060f-6cf6-c1d36ff6b812@linux.ibm.com/","msgid":"<27382086-397f-060f-6cf6-c1d36ff6b812@linux.ibm.com>","list_archive_url":null,"date":"2022-11-08T18:23:32","name":"[COMMITTED] PowerPC: Add XSP operand define","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/27382086-397f-060f-6cf6-c1d36ff6b812@linux.ibm.com/mbox/"},{"id":17202,"url":"https://patchwork.plctlab.org/api/1.2/patches/17202/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221108192248.1622627-1-indu.bhagat@oracle.com/","msgid":"<20221108192248.1622627-1-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-08T19:22:48","name":"libctf: use libtool for link test in configure","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221108192248.1622627-1-indu.bhagat@oracle.com/mbox/"},{"id":17262,"url":"https://patchwork.plctlab.org/api/1.2/patches/17262/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221108225030.371817-1-hjl.tools@gmail.com/","msgid":"<20221108225030.371817-1-hjl.tools@gmail.com>","list_archive_url":null,"date":"2022-11-08T22:50:30","name":"ld: Always output local symbol for relocatable link","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221108225030.371817-1-hjl.tools@gmail.com/mbox/"},{"id":17399,"url":"https://patchwork.plctlab.org/api/1.2/patches/17399/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-2-indu.bhagat@oracle.com/","msgid":"<20221109084244.261296-2-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-09T08:42:34","name":"[V4,01/11] sframe.h: Add SFrame format definition","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-2-indu.bhagat@oracle.com/mbox/"},{"id":17398,"url":"https://patchwork.plctlab.org/api/1.2/patches/17398/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-3-indu.bhagat@oracle.com/","msgid":"<20221109084244.261296-3-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-09T08:42:35","name":"[V4,02/11] gas: add new command line option --gsframe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-3-indu.bhagat@oracle.com/mbox/"},{"id":17400,"url":"https://patchwork.plctlab.org/api/1.2/patches/17400/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-4-indu.bhagat@oracle.com/","msgid":"<20221109084244.261296-4-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-09T08:42:36","name":"[V4,03/11] gas: generate .sframe from CFI directives","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-4-indu.bhagat@oracle.com/mbox/"},{"id":17403,"url":"https://patchwork.plctlab.org/api/1.2/patches/17403/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-5-indu.bhagat@oracle.com/","msgid":"<20221109084244.261296-5-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-09T08:42:37","name":"[V4,04/11] gas: testsuite: add new tests for SFrame unwind info","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-5-indu.bhagat@oracle.com/mbox/"},{"id":17407,"url":"https://patchwork.plctlab.org/api/1.2/patches/17407/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-6-indu.bhagat@oracle.com/","msgid":"<20221109084244.261296-6-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-09T08:42:38","name":"[V4,05/11] libsframe: add the SFrame library","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-6-indu.bhagat@oracle.com/mbox/"},{"id":17406,"url":"https://patchwork.plctlab.org/api/1.2/patches/17406/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-7-indu.bhagat@oracle.com/","msgid":"<20221109084244.261296-7-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-09T08:42:39","name":"[V4,06/11] bfd: linker: merge .sframe sections","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-7-indu.bhagat@oracle.com/mbox/"},{"id":17402,"url":"https://patchwork.plctlab.org/api/1.2/patches/17402/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-8-indu.bhagat@oracle.com/","msgid":"<20221109084244.261296-8-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-09T08:42:40","name":"[V4,07/11] readelf/objdump: support for SFrame section","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-8-indu.bhagat@oracle.com/mbox/"},{"id":17401,"url":"https://patchwork.plctlab.org/api/1.2/patches/17401/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-9-indu.bhagat@oracle.com/","msgid":"<20221109084244.261296-9-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-09T08:42:41","name":"[V4,08/11] src-release.sh: Add libsframe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-9-indu.bhagat@oracle.com/mbox/"},{"id":17404,"url":"https://patchwork.plctlab.org/api/1.2/patches/17404/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-10-indu.bhagat@oracle.com/","msgid":"<20221109084244.261296-10-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-09T08:42:42","name":"[V4,09/11] binutils/NEWS: add text for SFrame support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-10-indu.bhagat@oracle.com/mbox/"},{"id":17405,"url":"https://patchwork.plctlab.org/api/1.2/patches/17405/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-11-indu.bhagat@oracle.com/","msgid":"<20221109084244.261296-11-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-09T08:42:43","name":"[V4,10/11] gas/NEWS: add text about new command line option and SFrame support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-11-indu.bhagat@oracle.com/mbox/"}],"public":true,"mbox":"https://patchwork.plctlab.org/bundle/patchwork-bot/binutils-gdb_2022-11/mbox/"}]' ++ jq -rc '.[].name' ++ echo '[{"id":6,"url":"https://patchwork.plctlab.org/api/1.2/bundles/6/","web_url":"https://patchwork.plctlab.org/bundle/patchwork-bot/binutils-gdb_2022-10/","project":{"id":2,"url":"https://patchwork.plctlab.org/api/1.2/projects/2/","name":"binutils-gdb","link_name":"binutils-gdb","list_id":"binutils.sourceware.org","list_email":"binutils@sourceware.org","web_url":"https://github.com/wangliu-iscas/Patchwork-Bundles/blob/main/binutils-gdb.md","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"name":"binutils-gdb_2022-10","owner":{"id":3,"url":"https://patchwork.plctlab.org/api/1.2/users/3/","username":"patchwork-bot","first_name":"","last_name":"","email":"ouuuleilei@gmail.com"},"patches":[{"id":1592,"url":"https://patchwork.plctlab.org/api/1.2/patches/1592/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/385d01fd-7e57-1f3f-1bae-30aa0c313d63@suse.com/","msgid":"<385d01fd-7e57-1f3f-1bae-30aa0c313d63@suse.com>","list_archive_url":null,"date":"2022-09-30T11:59:45","name":"[3/4] RISC-V/gas: don'\''t open-code insn_length()","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/385d01fd-7e57-1f3f-1bae-30aa0c313d63@suse.com/mbox/"},{"id":1594,"url":"https://patchwork.plctlab.org/api/1.2/patches/1594/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f5757acf-7b90-a0e3-5eea-3b97cc226930@suse.com/","msgid":"","list_archive_url":null,"date":"2022-09-30T12:00:12","name":"[4/4] RISC-V/gas: allow generating up to 176-bit instructions with .insn","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f5757acf-7b90-a0e3-5eea-3b97cc226930@suse.com/mbox/"},{"id":1596,"url":"https://patchwork.plctlab.org/api/1.2/patches/1596/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930140503.38233-1-chigot@adacore.com/","msgid":"<20220930140503.38233-1-chigot@adacore.com>","list_archive_url":null,"date":"2022-09-30T14:05:03","name":"ld/testsuite: consistently add board_ldflags when linking with GCC","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930140503.38233-1-chigot@adacore.com/mbox/"},{"id":1619,"url":"https://patchwork.plctlab.org/api/1.2/patches/1619/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221001014451.532772-1-maskray@google.com/","msgid":"<20221001014451.532772-1-maskray@google.com>","list_archive_url":null,"date":"2022-10-01T01:44:51","name":"gold, dwp: support zstd compressed input debug sections [PR 29641]","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221001014451.532772-1-maskray@google.com/mbox/"},{"id":1620,"url":"https://patchwork.plctlab.org/api/1.2/patches/1620/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221001023846.590825-1-maskray@google.com/","msgid":"<20221001023846.590825-1-maskray@google.com>","list_archive_url":null,"date":"2022-10-01T02:38:46","name":"gold: add --compress-debug-sections=zstd [PR 29641]","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221001023846.590825-1-maskray@google.com/mbox/"},{"id":1623,"url":"https://patchwork.plctlab.org/api/1.2/patches/1623/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b4477c7f666bdeb7f8e998633c7b0cb62310b9ef.1664599545.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-01T04:45:52","name":"[RFC,1/1] RISC-V: Implement common register pair framework","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b4477c7f666bdeb7f8e998633c7b0cb62310b9ef.1664599545.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1625,"url":"https://patchwork.plctlab.org/api/1.2/patches/1625/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/53a265a1f14d17a6f7b106082f610994c5d546e0.1664602025.git.research_trasio@irq.a4lg.com/","msgid":"<53a265a1f14d17a6f7b106082f610994c5d546e0.1664602025.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-01T05:27:31","name":"[RFC,1/1] RISC-V: Implement extension variants","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/53a265a1f14d17a6f7b106082f610994c5d546e0.1664602025.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1626,"url":"https://patchwork.plctlab.org/api/1.2/patches/1626/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8db04962aba9c780f133840a8934353a58f223fe.1664602716.git.research_trasio@irq.a4lg.com/","msgid":"<8db04962aba9c780f133840a8934353a58f223fe.1664602716.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-01T05:39:26","name":"[1/1] RISC-V: Move supervisor instructions after all unprivileged ones","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8db04962aba9c780f133840a8934353a58f223fe.1664602716.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1627,"url":"https://patchwork.plctlab.org/api/1.2/patches/1627/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221001062057.681440-1-maskray@google.com/","msgid":"<20221001062057.681440-1-maskray@google.com>","list_archive_url":null,"date":"2022-10-01T06:20:57","name":"readelf: support zstd compressed debug sections [PR 29640]","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221001062057.681440-1-maskray@google.com/mbox/"},{"id":1631,"url":"https://patchwork.plctlab.org/api/1.2/patches/1631/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/619f112539c0bdecd58e25664f1250a3479a37f5.1664707612.git.aburgess@redhat.com/","msgid":"<619f112539c0bdecd58e25664f1250a3479a37f5.1664707612.git.aburgess@redhat.com>","list_archive_url":null,"date":"2022-10-02T10:47:52","name":"[PATCHv2,2/2] opcodes/arm: add disassembler styling for arm","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/619f112539c0bdecd58e25664f1250a3479a37f5.1664707612.git.aburgess@redhat.com/mbox/"},{"id":1635,"url":"https://patchwork.plctlab.org/api/1.2/patches/1635/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221002185433.gl7dvytfh5wthifx@lug-owl.de/","msgid":"<20221002185433.gl7dvytfh5wthifx@lug-owl.de>","list_archive_url":null,"date":"2022-10-02T18:54:33","name":"diagnostics.h: GCC 13 got -Wself-move, breaks GDB build","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221002185433.gl7dvytfh5wthifx@lug-owl.de/mbox/"},{"id":1637,"url":"https://patchwork.plctlab.org/api/1.2/patches/1637/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003014313.28766-1-mark@harmstone.com/","msgid":"<20221003014313.28766-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-03T01:43:12","name":"[1/2] ld: Add --pdb option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003014313.28766-1-mark@harmstone.com/mbox/"},{"id":1638,"url":"https://patchwork.plctlab.org/api/1.2/patches/1638/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003014313.28766-2-mark@harmstone.com/","msgid":"<20221003014313.28766-2-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-03T01:43:13","name":"[2/2] ld: Add minimal pdb generation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003014313.28766-2-mark@harmstone.com/mbox/"},{"id":1640,"url":"https://patchwork.plctlab.org/api/1.2/patches/1640/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/597ed978-d121-220c-b56b-2ffb94bd091c@suse.cz/","msgid":"<597ed978-d121-220c-b56b-2ffb94bd091c@suse.cz>","list_archive_url":null,"date":"2022-10-03T07:50:38","name":"[1/2] refactor usage of compressed_debug_section_type","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/597ed978-d121-220c-b56b-2ffb94bd091c@suse.cz/mbox/"},{"id":1641,"url":"https://patchwork.plctlab.org/api/1.2/patches/1641/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b8acdd83-f33a-74b8-e21a-23719a0b1a60@suse.cz/","msgid":"","list_archive_url":null,"date":"2022-10-03T07:50:44","name":"[2/2] add --enable-default-compressed-debug-sections-algorithm configure option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b8acdd83-f33a-74b8-e21a-23719a0b1a60@suse.cz/mbox/"},{"id":1642,"url":"https://patchwork.plctlab.org/api/1.2/patches/1642/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003101328.1790113-1-aburgess@redhat.com/","msgid":"<20221003101328.1790113-1-aburgess@redhat.com>","list_archive_url":null,"date":"2022-10-03T10:13:28","name":"opcodes/riscv: style csr names as registers","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003101328.1790113-1-aburgess@redhat.com/mbox/"},{"id":1643,"url":"https://patchwork.plctlab.org/api/1.2/patches/1643/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7ba14fc4472ce97d4f7a4433cad8a571e89f82f4.1664793840.git.research_trasio@irq.a4lg.com/","msgid":"<7ba14fc4472ce97d4f7a4433cad8a571e89f82f4.1664793840.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-03T10:43:59","name":"[v3,1/6] RISC-V: Fix immediates to have \"immediate\" style","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7ba14fc4472ce97d4f7a4433cad8a571e89f82f4.1664793840.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1644,"url":"https://patchwork.plctlab.org/api/1.2/patches/1644/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a498bec37c1fd1dcda57cbf95e5f8cfba09b31d3.1664793840.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-03T10:44:00","name":"[v3,2/6] RISC-V: Fix printf argument types corresponding %x","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a498bec37c1fd1dcda57cbf95e5f8cfba09b31d3.1664793840.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1647,"url":"https://patchwork.plctlab.org/api/1.2/patches/1647/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0002ea716713ace4998a33dde0b81f4f890d10bf.1664793840.git.research_trasio@irq.a4lg.com/","msgid":"<0002ea716713ace4998a33dde0b81f4f890d10bf.1664793840.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-03T10:44:01","name":"[v3,3/6] RISC-V: Optimize riscv_disassemble_data printf","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0002ea716713ace4998a33dde0b81f4f890d10bf.1664793840.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1646,"url":"https://patchwork.plctlab.org/api/1.2/patches/1646/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c65fc3e9aa58965d6768a28c9fd7467fea9897a5.1664793840.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-03T10:44:02","name":"[v3,4/6] RISC-V: Print comma and tabs as the \"text\" style","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c65fc3e9aa58965d6768a28c9fd7467fea9897a5.1664793840.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1648,"url":"https://patchwork.plctlab.org/api/1.2/patches/1648/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5abe1d8a7694417b990e11d8f6cd6789573872e5.1664793840.git.research_trasio@irq.a4lg.com/","msgid":"<5abe1d8a7694417b990e11d8f6cd6789573872e5.1664793840.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-03T10:44:03","name":"[v3,5/6] RISC-V: Fix T-Head immediate types on printing","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5abe1d8a7694417b990e11d8f6cd6789573872e5.1664793840.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1649,"url":"https://patchwork.plctlab.org/api/1.2/patches/1649/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0b68af932117258c908db62cf87c3a15d3cdec41.1664793840.git.research_trasio@irq.a4lg.com/","msgid":"<0b68af932117258c908db62cf87c3a15d3cdec41.1664793840.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-03T10:44:04","name":"[v3,6/6] RISC-V: Print XTheadMemPair literal as \"immediate\"","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0b68af932117258c908db62cf87c3a15d3cdec41.1664793840.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1656,"url":"https://patchwork.plctlab.org/api/1.2/patches/1656/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/87lepxcd6x.fsf@redhat.com/","msgid":"<87lepxcd6x.fsf@redhat.com>","list_archive_url":null,"date":"2022-10-03T12:19:02","name":"Commit: readelf: Do not load section data from offset 0","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/87lepxcd6x.fsf@redhat.com/mbox/"},{"id":1659,"url":"https://patchwork.plctlab.org/api/1.2/patches/1659/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e0d369d419da9c0441f415da7f54352aead8f655.1664707612.git.aburgess@redhat.com/","msgid":"","list_archive_url":null,"date":"2022-10-03T16:37:36","name":"[PATCHv2,1/2] opcodes/arm: use '\''@'\'' consistently for the comment character","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e0d369d419da9c0441f415da7f54352aead8f655.1664707612.git.aburgess@redhat.com/mbox/"},{"id":1660,"url":"https://patchwork.plctlab.org/api/1.2/patches/1660/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003165848.11142-1-palmer@rivosinc.com/","msgid":"<20221003165848.11142-1-palmer@rivosinc.com>","list_archive_url":null,"date":"2022-10-03T16:58:48","name":"gas: NEWS: Mention the T-Head extensions that were recently added","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003165848.11142-1-palmer@rivosinc.com/mbox/"},{"id":1671,"url":"https://patchwork.plctlab.org/api/1.2/patches/1671/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/YzvrMEdkXjIn5Lfz@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-04T08:13:36","name":"Support objcopy changing compression to or from zstd","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/YzvrMEdkXjIn5Lfz@squeak.grove.modra.org/mbox/"},{"id":1673,"url":"https://patchwork.plctlab.org/api/1.2/patches/1673/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0bc857d306bb7c8130e5328dbe6b9ed2fed3ef87.1664873933.git.research_trasio@irq.a4lg.com/","msgid":"<0bc857d306bb7c8130e5328dbe6b9ed2fed3ef87.1664873933.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-04T08:59:07","name":"[1/2] RISC-V: Fix buffer overflow on print_insn_riscv","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0bc857d306bb7c8130e5328dbe6b9ed2fed3ef87.1664873933.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1672,"url":"https://patchwork.plctlab.org/api/1.2/patches/1672/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/89612fe01d902007bf84a7dfb0df5f85d5c166e4.1664873933.git.research_trasio@irq.a4lg.com/","msgid":"<89612fe01d902007bf84a7dfb0df5f85d5c166e4.1664873933.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-04T08:59:08","name":"[2/2] gdb/riscv: Fix buffer overflow on riscv_insn::fetch_instruction","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/89612fe01d902007bf84a7dfb0df5f85d5c166e4.1664873933.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1676,"url":"https://patchwork.plctlab.org/api/1.2/patches/1676/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fc849c94f4adcac1c4ccc5508c7a145a2f13b2a9.1664876744.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-04T09:45:49","name":"[v2,1/2] RISC-V: Fix buffer overflow on print_insn_riscv","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fc849c94f4adcac1c4ccc5508c7a145a2f13b2a9.1664876744.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1677,"url":"https://patchwork.plctlab.org/api/1.2/patches/1677/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4eb6e59ae2e790dbbf2bc92477edd281648d8814.1664876744.git.research_trasio@irq.a4lg.com/","msgid":"<4eb6e59ae2e790dbbf2bc92477edd281648d8814.1664876744.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-04T09:45:50","name":"[v2,2/2] gdb/riscv: Partial support for instructions up to 176-bits","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4eb6e59ae2e790dbbf2bc92477edd281648d8814.1664876744.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1678,"url":"https://patchwork.plctlab.org/api/1.2/patches/1678/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ebf16f9e1f45115d0793952ccb4a94d4233303f9.1664882725.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-04T11:25:56","name":"[v3,1/2] RISC-V: Fix buffer overflow on print_insn_riscv","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ebf16f9e1f45115d0793952ccb4a94d4233303f9.1664882725.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1679,"url":"https://patchwork.plctlab.org/api/1.2/patches/1679/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/83464b09b8649525259c69c853dfa2c9575a204b.1664882725.git.research_trasio@irq.a4lg.com/","msgid":"<83464b09b8649525259c69c853dfa2c9575a204b.1664882725.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-04T11:25:57","name":"[v3,2/2] gdb/riscv: Partial support for instructions up to 176-bit","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/83464b09b8649525259c69c853dfa2c9575a204b.1664882725.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1681,"url":"https://patchwork.plctlab.org/api/1.2/patches/1681/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ffa9c1d7-e8c2-a62b-ef3e-b565c0ffbe5b@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-04T13:56:27","name":"RISC-V: Zicbo{m,p,z} adjustments to riscv_multi_subset_supports_ext()","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ffa9c1d7-e8c2-a62b-ef3e-b565c0ffbe5b@suse.com/mbox/"},{"id":1690,"url":"https://patchwork.plctlab.org/api/1.2/patches/1690/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221004161720.1963953-1-vladimir.mezentsev@oracle.com/","msgid":"<20221004161720.1963953-1-vladimir.mezentsev@oracle.com>","list_archive_url":null,"date":"2022-10-04T16:17:20","name":"gprofng: fix build with --enable-pgo-build=lto","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221004161720.1963953-1-vladimir.mezentsev@oracle.com/mbox/"},{"id":1691,"url":"https://patchwork.plctlab.org/api/1.2/patches/1691/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c0211bc9c57be6c79c6d878ce147f63b657f461d.camel@espressif.com/","msgid":"","list_archive_url":null,"date":"2022-10-04T16:22:05","name":"bfd: xtensa: fix __stop_SECTION literal drop,","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c0211bc9c57be6c79c6d878ce147f63b657f461d.camel@espressif.com/mbox/"},{"id":1702,"url":"https://patchwork.plctlab.org/api/1.2/patches/1702/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5f482299-6c60-b2b3-9abe-f4a55a5a26c5@univ-grenoble-alpes.fr/","msgid":"<5f482299-6c60-b2b3-9abe-f4a55a5a26c5@univ-grenoble-alpes.fr>","list_archive_url":null,"date":"2022-10-04T20:03:20","name":"[RFC] bfd: use bfd_vma for the 64-bit version of put[lb] and get[lb]","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5f482299-6c60-b2b3-9abe-f4a55a5a26c5@univ-grenoble-alpes.fr/mbox/"},{"id":1711,"url":"https://patchwork.plctlab.org/api/1.2/patches/1711/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Yz0Gsxdxe0TePbJT@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-05T04:23:15","name":"PR29647, objdump -S looping","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Yz0Gsxdxe0TePbJT@squeak.grove.modra.org/mbox/"},{"id":1712,"url":"https://patchwork.plctlab.org/api/1.2/patches/1712/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/02d747d2-f57b-0fb5-b893-842b6cc41f2f@suse.com/","msgid":"<02d747d2-f57b-0fb5-b893-842b6cc41f2f@suse.com>","list_archive_url":null,"date":"2022-10-05T07:20:47","name":"[v3,1/7] x86: constify parse_insn()'\''s input","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/02d747d2-f57b-0fb5-b893-842b6cc41f2f@suse.com/mbox/"},{"id":1713,"url":"https://patchwork.plctlab.org/api/1.2/patches/1713/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/925cb740-4e1b-abc4-8526-aaab6faae5e1@suse.com/","msgid":"<925cb740-4e1b-abc4-8526-aaab6faae5e1@suse.com>","list_archive_url":null,"date":"2022-10-05T07:22:19","name":"[v3,2/7] x86: introduce Pass2 insn attribute","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/925cb740-4e1b-abc4-8526-aaab6faae5e1@suse.com/mbox/"},{"id":1714,"url":"https://patchwork.plctlab.org/api/1.2/patches/1714/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e16d3e78-39ca-f715-508f-a4104b8ab9a9@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-05T07:23:51","name":"[v3,3/7] x86: re-work insn/suffix recognition","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e16d3e78-39ca-f715-508f-a4104b8ab9a9@suse.com/mbox/"},{"id":1715,"url":"https://patchwork.plctlab.org/api/1.2/patches/1715/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e4e4b80b-794c-7485-1997-685adab8fb27@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-05T07:24:20","name":"[v3,4/7] x86-64: further re-work insn/suffix recognition to also cover MOVSL","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e4e4b80b-794c-7485-1997-685adab8fb27@suse.com/mbox/"},{"id":1716,"url":"https://patchwork.plctlab.org/api/1.2/patches/1716/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/540678fc-8bff-ec68-c97c-478d2631998c@suse.com/","msgid":"<540678fc-8bff-ec68-c97c-478d2631998c@suse.com>","list_archive_url":null,"date":"2022-10-05T07:24:55","name":"[v3,5/7] ix86: don'\''t recognize/derive Q suffix in the common case","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/540678fc-8bff-ec68-c97c-478d2631998c@suse.com/mbox/"},{"id":1718,"url":"https://patchwork.plctlab.org/api/1.2/patches/1718/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e4692495-7d3d-074d-14f9-364d4a9a998c@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-05T07:25:25","name":"[v3,6/7] x86-64: allow HLE store of accumulator to absolute 32-bit address","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e4692495-7d3d-074d-14f9-364d4a9a998c@suse.com/mbox/"},{"id":1717,"url":"https://patchwork.plctlab.org/api/1.2/patches/1717/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e8014ebd-d16b-17a7-9f34-3700fc164136@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-05T07:25:57","name":"[v3,7/7] x86: move bad-use-of-TLS-reloc check","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e8014ebd-d16b-17a7-9f34-3700fc164136@suse.com/mbox/"},{"id":1719,"url":"https://patchwork.plctlab.org/api/1.2/patches/1719/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1266f001-4511-2662-dba9-14b4d0317c57@suse.com/","msgid":"<1266f001-4511-2662-dba9-14b4d0317c57@suse.com>","list_archive_url":null,"date":"2022-10-05T07:40:50","name":"x86: drop \"regmask\" static variable","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1266f001-4511-2662-dba9-14b4d0317c57@suse.com/mbox/"},{"id":1751,"url":"https://patchwork.plctlab.org/api/1.2/patches/1751/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/af45c5d57c221e43101c2aa38b14f4b4ac12d011.1665031170.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-06T04:40:15","name":"[v2,1/2] RISC-V: Fallback for instructions longer than 64b","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/af45c5d57c221e43101c2aa38b14f4b4ac12d011.1665031170.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1752,"url":"https://patchwork.plctlab.org/api/1.2/patches/1752/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c6e55781245dd3e8e9b8debd6130fc5449dfbd55.1665031170.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-06T04:40:16","name":"[v2,2/2] RISC-V: Improve \"bits undefined\" diagnostics","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c6e55781245dd3e8e9b8debd6130fc5449dfbd55.1665031170.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1776,"url":"https://patchwork.plctlab.org/api/1.2/patches/1776/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d52952119e15357c0e823f8a2398999359588b4d.1665050099.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-06T09:56:30","name":"[v3,1/2] RISC-V: Fallback for instructions longer than 64b","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d52952119e15357c0e823f8a2398999359588b4d.1665050099.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1777,"url":"https://patchwork.plctlab.org/api/1.2/patches/1777/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d907b1997f60ff7823c4a23e281ec9d8ddcbf3f1.1665050099.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-06T09:56:31","name":"[v3,2/2] RISC-V: Improve \"bits undefined\" diagnostics","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d907b1997f60ff7823c4a23e281ec9d8ddcbf3f1.1665050099.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1781,"url":"https://patchwork.plctlab.org/api/1.2/patches/1781/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221006114628.304185-1-chigot@adacore.com/","msgid":"<20221006114628.304185-1-chigot@adacore.com>","list_archive_url":null,"date":"2022-10-06T11:46:28","name":"RISC-V: fix linker message when relaxation deletes bytes","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221006114628.304185-1-chigot@adacore.com/mbox/"},{"id":1801,"url":"https://patchwork.plctlab.org/api/1.2/patches/1801/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Yz+Yhyg7UewC9/kp@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-07T03:09:59","name":"PR29653, objcopy/strip: fuzzed small input file induces large output file","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Yz+Yhyg7UewC9/kp@squeak.grove.modra.org/mbox/"},{"id":1803,"url":"https://patchwork.plctlab.org/api/1.2/patches/1803/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/PH1P110MB16505D9D39EC5B1DE22FE3D5EC5F9@PH1P110MB1650.NAMP110.PROD.OUTLOOK.COM/","msgid":"","list_archive_url":null,"date":"2022-10-07T04:10:07","name":"@CPP_FOR_BUILD@ problem since binutils-2.38","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/PH1P110MB16505D9D39EC5B1DE22FE3D5EC5F9@PH1P110MB1650.NAMP110.PROD.OUTLOOK.COM/mbox/"},{"id":1827,"url":"https://patchwork.plctlab.org/api/1.2/patches/1827/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8e13bce108ac10a0c1dd911e23ec572926f7ae44.1665203374.git.research_trasio@irq.a4lg.com/","msgid":"<8e13bce108ac10a0c1dd911e23ec572926f7ae44.1665203374.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-08T04:29:53","name":"[v2,1/1] RISC-V: Test DWARF register numbers for \"fp\"","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8e13bce108ac10a0c1dd911e23ec572926f7ae44.1665203374.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1828,"url":"https://patchwork.plctlab.org/api/1.2/patches/1828/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0883001b3572e54d3fba264429c7ade2adb66610.1665203441.git.research_trasio@irq.a4lg.com/","msgid":"<0883001b3572e54d3fba264429c7ade2adb66610.1665203441.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-08T04:31:15","name":"[1/1] RISC-V: Move standard hints before all instructions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0883001b3572e54d3fba264429c7ade2adb66610.1665203441.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1829,"url":"https://patchwork.plctlab.org/api/1.2/patches/1829/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/58e16a241d7376fcae2515c6bd5a2b41d275eeba.1665203531.git.research_trasio@irq.a4lg.com/","msgid":"<58e16a241d7376fcae2515c6bd5a2b41d275eeba.1665203531.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-08T04:32:18","name":"[RFC,1/1] RISC-V: Imply '\''Zicsr'\'' from privileged extensions with CSRs","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/58e16a241d7376fcae2515c6bd5a2b41d275eeba.1665203531.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1830,"url":"https://patchwork.plctlab.org/api/1.2/patches/1830/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/cb5076fc96e8f2097779a3abcde843dcdd660031.1665203660.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-08T04:34:23","name":"[1/5] opcodes/riscv-dis.c: Tidying with comments/clarity","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/cb5076fc96e8f2097779a3abcde843dcdd660031.1665203660.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1832,"url":"https://patchwork.plctlab.org/api/1.2/patches/1832/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1f1aa0838bf9c4f10a45fcfe3c682f7efc79d9ae.1665203660.git.research_trasio@irq.a4lg.com/","msgid":"<1f1aa0838bf9c4f10a45fcfe3c682f7efc79d9ae.1665203660.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-08T04:34:24","name":"[2/5] opcodes/riscv-dis.c: Tidying with spacing","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1f1aa0838bf9c4f10a45fcfe3c682f7efc79d9ae.1665203660.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1831,"url":"https://patchwork.plctlab.org/api/1.2/patches/1831/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/740bc5e2d2618d236519b39fedd1a1d7ae4e05da.1665203660.git.research_trasio@irq.a4lg.com/","msgid":"<740bc5e2d2618d236519b39fedd1a1d7ae4e05da.1665203660.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-08T04:34:25","name":"[3/5] opcodes/riscv-dis.c: Use bool type whenever possible","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/740bc5e2d2618d236519b39fedd1a1d7ae4e05da.1665203660.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1833,"url":"https://patchwork.plctlab.org/api/1.2/patches/1833/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6e3a9c235e317f441b4383b3daa68f2051bdc149.1665203660.git.research_trasio@irq.a4lg.com/","msgid":"<6e3a9c235e317f441b4383b3daa68f2051bdc149.1665203660.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-08T04:34:26","name":"[4/5] opcodes/riscv-dis.c: Make XLEN variable static","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6e3a9c235e317f441b4383b3daa68f2051bdc149.1665203660.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1834,"url":"https://patchwork.plctlab.org/api/1.2/patches/1834/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ad929233a62d887495122721340b2f9c80392963.1665203660.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-08T04:34:27","name":"[5/5] opcodes/riscv-dis.c: Remove last_map_state","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ad929233a62d887495122721340b2f9c80392963.1665203660.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1836,"url":"https://patchwork.plctlab.org/api/1.2/patches/1836/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d07e2b6f36ea2fd5830924a9bfeda941b774b687.1665290422.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-09T05:09:22","name":"RISC-V: Move certain arrays to riscv-opc.c","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d07e2b6f36ea2fd5830924a9bfeda941b774b687.1665290422.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1844,"url":"https://patchwork.plctlab.org/api/1.2/patches/1844/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010004623.16582-1-mark@harmstone.com/","msgid":"<20221010004623.16582-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-10T00:46:22","name":"[v2,1/2] ld: Add --pdb option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010004623.16582-1-mark@harmstone.com/mbox/"},{"id":1845,"url":"https://patchwork.plctlab.org/api/1.2/patches/1845/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010004623.16582-2-mark@harmstone.com/","msgid":"<20221010004623.16582-2-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-10T00:46:23","name":"[v2,2/2] ld: Add minimal pdb generation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010004623.16582-2-mark@harmstone.com/mbox/"},{"id":1890,"url":"https://patchwork.plctlab.org/api/1.2/patches/1890/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010200433.414320-1-vladimir.mezentsev@oracle.com/","msgid":"<20221010200433.414320-1-vladimir.mezentsev@oracle.com>","list_archive_url":null,"date":"2022-10-10T20:04:33","name":"gprofng: run tests without installation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010200433.414320-1-vladimir.mezentsev@oracle.com/mbox/"},{"id":1893,"url":"https://patchwork.plctlab.org/api/1.2/patches/1893/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010230426.719238-1-vladimir.mezentsev@oracle.com/","msgid":"<20221010230426.719238-1-vladimir.mezentsev@oracle.com>","list_archive_url":null,"date":"2022-10-10T23:04:26","name":"[2/2] gprofng: use the --libdir path to find libraries","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010230426.719238-1-vladimir.mezentsev@oracle.com/mbox/"},{"id":1894,"url":"https://patchwork.plctlab.org/api/1.2/patches/1894/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010235155.842469-1-vladimir.mezentsev@oracle.com/","msgid":"<20221010235155.842469-1-vladimir.mezentsev@oracle.com>","list_archive_url":null,"date":"2022-10-10T23:51:55","name":"[3/3] gprofng: no need to build version.texi","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010235155.842469-1-vladimir.mezentsev@oracle.com/mbox/"},{"id":1895,"url":"https://patchwork.plctlab.org/api/1.2/patches/1895/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011003702.4287-1-mark@harmstone.com/","msgid":"<20221011003702.4287-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-11T00:37:01","name":"[v3,1/2] ld: Add --pdb option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011003702.4287-1-mark@harmstone.com/mbox/"},{"id":1897,"url":"https://patchwork.plctlab.org/api/1.2/patches/1897/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011003702.4287-2-mark@harmstone.com/","msgid":"<20221011003702.4287-2-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-11T00:37:02","name":"[v3,2/2] ld: Add minimal pdb generation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011003702.4287-2-mark@harmstone.com/mbox/"},{"id":1928,"url":"https://patchwork.plctlab.org/api/1.2/patches/1928/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011175332.17156-1-mark@harmstone.com/","msgid":"<20221011175332.17156-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-11T17:53:31","name":"[v4,1/2] ld: Add --pdb option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011175332.17156-1-mark@harmstone.com/mbox/"},{"id":1929,"url":"https://patchwork.plctlab.org/api/1.2/patches/1929/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011175332.17156-2-mark@harmstone.com/","msgid":"<20221011175332.17156-2-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-11T17:53:32","name":"[v4,2/2] ld: Add minimal pdb generation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011175332.17156-2-mark@harmstone.com/mbox/"},{"id":1941,"url":"https://patchwork.plctlab.org/api/1.2/patches/1941/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221012031005.237446-1-simon.marchi@polymtl.ca/","msgid":"<20221012031005.237446-1-simon.marchi@polymtl.ca>","list_archive_url":null,"date":"2022-10-12T03:10:05","name":"[pushed] Re-apply \"Pass PKG_CONFIG_PATH down from top-level Makefile\"","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221012031005.237446-1-simon.marchi@polymtl.ca/mbox/"},{"id":1976,"url":"https://patchwork.plctlab.org/api/1.2/patches/1976/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1216a3f8-2273-8681-f528-9493a66891f0@suse.com/","msgid":"<1216a3f8-2273-8681-f528-9493a66891f0@suse.com>","list_archive_url":null,"date":"2022-10-13T08:16:49","name":"[v4,1/8] x86: constify parse_insn()'\''s input","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1216a3f8-2273-8681-f528-9493a66891f0@suse.com/mbox/"},{"id":1977,"url":"https://patchwork.plctlab.org/api/1.2/patches/1977/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/11599bbe-c779-aa9f-4d5d-c2243f0e69dc@suse.com/","msgid":"<11599bbe-c779-aa9f-4d5d-c2243f0e69dc@suse.com>","list_archive_url":null,"date":"2022-10-13T08:17:17","name":"[v4,2/8] x86: introduce Pass2 insn attribute","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/11599bbe-c779-aa9f-4d5d-c2243f0e69dc@suse.com/mbox/"},{"id":1978,"url":"https://patchwork.plctlab.org/api/1.2/patches/1978/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/357273a3-060c-23db-72da-3fc9d1be3d2a@suse.com/","msgid":"<357273a3-060c-23db-72da-3fc9d1be3d2a@suse.com>","list_archive_url":null,"date":"2022-10-13T08:18:09","name":"[v4,3/8] x86: re-work insn/suffix recognition","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/357273a3-060c-23db-72da-3fc9d1be3d2a@suse.com/mbox/"},{"id":1979,"url":"https://patchwork.plctlab.org/api/1.2/patches/1979/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0ec0587f-6a7b-45b6-8346-e5d774e73636@suse.com/","msgid":"<0ec0587f-6a7b-45b6-8346-e5d774e73636@suse.com>","list_archive_url":null,"date":"2022-10-13T08:18:39","name":"[v4,4/8] x86-64: further re-work insn/suffix recognition to also cover MOVSL","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0ec0587f-6a7b-45b6-8346-e5d774e73636@suse.com/mbox/"},{"id":1980,"url":"https://patchwork.plctlab.org/api/1.2/patches/1980/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fb617d0b-8759-3169-5a65-1178b7fef3d7@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-13T08:19:34","name":"[v4,5/8] ix86: don'\''t recognize/derive Q suffix in the common case","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fb617d0b-8759-3169-5a65-1178b7fef3d7@suse.com/mbox/"},{"id":1981,"url":"https://patchwork.plctlab.org/api/1.2/patches/1981/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1df3bd01-99c5-f56c-d937-970edd42b2b8@suse.com/","msgid":"<1df3bd01-99c5-f56c-d937-970edd42b2b8@suse.com>","list_archive_url":null,"date":"2022-10-13T08:20:14","name":"[v4,6/8] x86-64: allow HLE store of accumulator to absolute 32-bit address","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1df3bd01-99c5-f56c-d937-970edd42b2b8@suse.com/mbox/"},{"id":1982,"url":"https://patchwork.plctlab.org/api/1.2/patches/1982/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8486a218-39ec-16b2-5c6c-5037196b93cf@suse.com/","msgid":"<8486a218-39ec-16b2-5c6c-5037196b93cf@suse.com>","list_archive_url":null,"date":"2022-10-13T08:21:00","name":"[v4,7/8] x86: move bad-use-of-TLS-reloc check","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8486a218-39ec-16b2-5c6c-5037196b93cf@suse.com/mbox/"},{"id":1983,"url":"https://patchwork.plctlab.org/api/1.2/patches/1983/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7d82692d-93df-fbee-9efb-2f44e8a91df3@suse.com/","msgid":"<7d82692d-93df-fbee-9efb-2f44e8a91df3@suse.com>","list_archive_url":null,"date":"2022-10-13T08:22:00","name":"[v4,8/8] x86: drop (now) stray IsString","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7d82692d-93df-fbee-9efb-2f44e8a91df3@suse.com/mbox/"},{"id":2013,"url":"https://patchwork.plctlab.org/api/1.2/patches/2013/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8ab93d7a617ad480dd786210f46db0e5aa07d1ac.1665655719.git.research_trasio@irq.a4lg.com/","msgid":"<8ab93d7a617ad480dd786210f46db0e5aa07d1ac.1665655719.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-13T10:11:41","name":"include: Declare getopt function on old GNU libc","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8ab93d7a617ad480dd786210f46db0e5aa07d1ac.1665655719.git.research_trasio@irq.a4lg.com/mbox/"},{"id":2352,"url":"https://patchwork.plctlab.org/api/1.2/patches/2352/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221013201332.2747246-1-maskray@google.com/","msgid":"<20221013201332.2747246-1-maskray@google.com>","list_archive_url":null,"date":"2022-10-13T20:13:32","name":"ld: Add --undefined-version","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221013201332.2747246-1-maskray@google.com/mbox/"},{"id":2532,"url":"https://patchwork.plctlab.org/api/1.2/patches/2532/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014063520.1428330-2-zengxiao@eswincomputing.com/","msgid":"<20221014063520.1428330-2-zengxiao@eswincomputing.com>","list_archive_url":null,"date":"2022-10-14T06:35:20","name":"[1/1] RISC-V: Make R_RISCV_SUB6 conforms to riscv abi standard","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014063520.1428330-2-zengxiao@eswincomputing.com/mbox/"},{"id":2560,"url":"https://patchwork.plctlab.org/api/1.2/patches/2560/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/027ae69a-636b-6757-297a-eec42936401e@linaro.org/","msgid":"<027ae69a-636b-6757-297a-eec42936401e@linaro.org>","list_archive_url":null,"date":"2022-10-14T07:58:22","name":"[v3] aarch64-pe support for LD, GAS and BFD","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/027ae69a-636b-6757-297a-eec42936401e@linaro.org/mbox/"},{"id":2602,"url":"https://patchwork.plctlab.org/api/1.2/patches/2602/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-2-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-2-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:39","name":"[01/10] Support Intel AVX-IFMA","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-2-haochen.jiang@intel.com/mbox/"},{"id":2608,"url":"https://patchwork.plctlab.org/api/1.2/patches/2608/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-3-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-3-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:40","name":"[02/10] Support Intel AVX-VNNI-INT8","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-3-haochen.jiang@intel.com/mbox/"},{"id":2611,"url":"https://patchwork.plctlab.org/api/1.2/patches/2611/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-4-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-4-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:41","name":"[03/10] Support Intel AVX-NE-CONVERT","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-4-haochen.jiang@intel.com/mbox/"},{"id":2610,"url":"https://patchwork.plctlab.org/api/1.2/patches/2610/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-5-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-5-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:42","name":"[04/10] Support Intel CMPccXADD","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-5-haochen.jiang@intel.com/mbox/"},{"id":2601,"url":"https://patchwork.plctlab.org/api/1.2/patches/2601/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-6-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-6-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:43","name":"[05/10] Add handler for more i386_cpu_flags","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-6-haochen.jiang@intel.com/mbox/"},{"id":2606,"url":"https://patchwork.plctlab.org/api/1.2/patches/2606/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-7-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-7-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:44","name":"[06/10] Support Intel RAO-INT","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-7-haochen.jiang@intel.com/mbox/"},{"id":2609,"url":"https://patchwork.plctlab.org/api/1.2/patches/2609/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-8-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-8-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:45","name":"[07/10] Support Intel WRMSRNS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-8-haochen.jiang@intel.com/mbox/"},{"id":2605,"url":"https://patchwork.plctlab.org/api/1.2/patches/2605/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-9-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-9-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:46","name":"[08/10] Support Intel MSRLIST","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-9-haochen.jiang@intel.com/mbox/"},{"id":2607,"url":"https://patchwork.plctlab.org/api/1.2/patches/2607/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-10-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-10-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:47","name":"[09/10] Support Intel AMX-FP16","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-10-haochen.jiang@intel.com/mbox/"},{"id":2604,"url":"https://patchwork.plctlab.org/api/1.2/patches/2604/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-11-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-11-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:48","name":"[10/10] Support Intel PREFETCHI","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-11-haochen.jiang@intel.com/mbox/"},{"id":2643,"url":"https://patchwork.plctlab.org/api/1.2/patches/2643/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7bac66be-535e-9051-d674-f2f5ba180e17@suse.com/","msgid":"<7bac66be-535e-9051-d674-f2f5ba180e17@suse.com>","list_archive_url":null,"date":"2022-10-14T10:22:34","name":"x86: fold AVX512-VNNI disassembler entries with AVX-VNNI ones","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7bac66be-535e-9051-d674-f2f5ba180e17@suse.com/mbox/"},{"id":2654,"url":"https://patchwork.plctlab.org/api/1.2/patches/2654/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0lIo5+ncY/MqBEq@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-14T11:31:47","name":"PR29677, Field `the_bfd` of `asymbol` is uninitialised","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0lIo5+ncY/MqBEq@squeak.grove.modra.org/mbox/"},{"id":2656,"url":"https://patchwork.plctlab.org/api/1.2/patches/2656/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0lJksn49ZpABY89@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-14T11:35:46","name":"e200 LSP support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0lJksn49ZpABY89@squeak.grove.modra.org/mbox/"},{"id":2657,"url":"https://patchwork.plctlab.org/api/1.2/patches/2657/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0lJxxYoeD5iDYAD@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-14T11:36:39","name":"PowerPC SPE disassembly and tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0lJxxYoeD5iDYAD@squeak.grove.modra.org/mbox/"},{"id":2695,"url":"https://patchwork.plctlab.org/api/1.2/patches/2695/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/DM6PR12MB4219611F6CC2A0702884A602E7249@DM6PR12MB4219.namprd12.prod.outlook.com/","msgid":"","list_archive_url":null,"date":"2022-10-14T13:29:40","name":"Binutils: Adding new testcase for addr2line.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/DM6PR12MB4219611F6CC2A0702884A602E7249@DM6PR12MB4219.namprd12.prod.outlook.com/mbox/"},{"id":2700,"url":"https://patchwork.plctlab.org/api/1.2/patches/2700/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9fd2c88d-98b2-99a4-419f-c7235b2cf960@suse.com/","msgid":"<9fd2c88d-98b2-99a4-419f-c7235b2cf960@suse.com>","list_archive_url":null,"date":"2022-10-14T14:11:35","name":"x86: properly decode EVEX.W for AVX512_4{FMAPS,VNNIW} insns","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9fd2c88d-98b2-99a4-419f-c7235b2cf960@suse.com/mbox/"},{"id":2981,"url":"https://patchwork.plctlab.org/api/1.2/patches/2981/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0uLzalqjm4C87GN@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-16T04:42:53","name":"PowerPC se_rfmci and VLE, SPE2 and LSP insns with -many","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0uLzalqjm4C87GN@squeak.grove.modra.org/mbox/"},{"id":3152,"url":"https://patchwork.plctlab.org/api/1.2/patches/3152/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221016232419.1135-1-mark@harmstone.com/","msgid":"<20221016232419.1135-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-16T23:24:18","name":"[v5,1/2] ld: Add --pdb option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221016232419.1135-1-mark@harmstone.com/mbox/"},{"id":3151,"url":"https://patchwork.plctlab.org/api/1.2/patches/3151/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221016232419.1135-2-mark@harmstone.com/","msgid":"<20221016232419.1135-2-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-16T23:24:19","name":"[v5,2/2] ld: Add minimal pdb generation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221016232419.1135-2-mark@harmstone.com/mbox/"},{"id":3258,"url":"https://patchwork.plctlab.org/api/1.2/patches/3258/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/19c08747-fa5b-1e67-3dd2-c891a2c0c1fa@suse.com/","msgid":"<19c08747-fa5b-1e67-3dd2-c891a2c0c1fa@suse.com>","list_archive_url":null,"date":"2022-10-17T07:44:51","name":"x86: correct CPU_AMX_{BF16,INT8}_FLAGS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/19c08747-fa5b-1e67-3dd2-c891a2c0c1fa@suse.com/mbox/"},{"id":3272,"url":"https://patchwork.plctlab.org/api/1.2/patches/3272/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/85dd526c-d3a7-72dc-5444-ed5573eebec1@suse.com/","msgid":"<85dd526c-d3a7-72dc-5444-ed5573eebec1@suse.com>","list_archive_url":null,"date":"2022-10-17T08:30:12","name":"x86: generalize gas documentation for disabling of ISA extensions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/85dd526c-d3a7-72dc-5444-ed5573eebec1@suse.com/mbox/"},{"id":3759,"url":"https://patchwork.plctlab.org/api/1.2/patches/3759/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-2-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-2-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:15:58","name":"[V2,01/15] sframe.h: Add SFrame format definition","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-2-indu.bhagat@oracle.com/mbox/"},{"id":3762,"url":"https://patchwork.plctlab.org/api/1.2/patches/3762/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-3-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-3-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:15:59","name":"[V2,02/15] gas: add new command line option --gsframe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-3-indu.bhagat@oracle.com/mbox/"},{"id":3761,"url":"https://patchwork.plctlab.org/api/1.2/patches/3761/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-4-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-4-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:00","name":"[V2,03/15] gas: generate .sframe from CFI directives","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-4-indu.bhagat@oracle.com/mbox/"},{"id":3760,"url":"https://patchwork.plctlab.org/api/1.2/patches/3760/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-5-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-5-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:01","name":"[V2,04/15] gas: testsuite: add new tests for SFrame unwind info","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-5-indu.bhagat@oracle.com/mbox/"},{"id":3764,"url":"https://patchwork.plctlab.org/api/1.2/patches/3764/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-6-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-6-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:02","name":"[V2,05/15] libsframe: add the SFrame library","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-6-indu.bhagat@oracle.com/mbox/"},{"id":3766,"url":"https://patchwork.plctlab.org/api/1.2/patches/3766/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-7-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-7-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:03","name":"[V2,06/15] bfd: linker: merge .sframe sections","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-7-indu.bhagat@oracle.com/mbox/"},{"id":3763,"url":"https://patchwork.plctlab.org/api/1.2/patches/3763/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-8-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-8-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:04","name":"[V2,07/15] readelf/objdump: support for SFrame section","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-8-indu.bhagat@oracle.com/mbox/"},{"id":3765,"url":"https://patchwork.plctlab.org/api/1.2/patches/3765/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-9-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-9-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:05","name":"[V2,08/15] unwinder: generate backtrace using SFrame format","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-9-indu.bhagat@oracle.com/mbox/"},{"id":3770,"url":"https://patchwork.plctlab.org/api/1.2/patches/3770/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-10-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-10-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:06","name":"[V2,09/15] unwinder: Add SFrame unwinder tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-10-indu.bhagat@oracle.com/mbox/"},{"id":3769,"url":"https://patchwork.plctlab.org/api/1.2/patches/3769/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-11-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-11-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:07","name":"[V2,10/15] gdb: sim: buildsystem changes to accommodate libsframe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-11-indu.bhagat@oracle.com/mbox/"},{"id":3771,"url":"https://patchwork.plctlab.org/api/1.2/patches/3771/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-12-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-12-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:08","name":"[V2,11/15] libctf: add libsframe to LDFLAGS and LIBS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-12-indu.bhagat@oracle.com/mbox/"},{"id":3768,"url":"https://patchwork.plctlab.org/api/1.2/patches/3768/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-13-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-13-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:09","name":"[V2,12/15] src-release.sh: Add libsframe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-13-indu.bhagat@oracle.com/mbox/"},{"id":3767,"url":"https://patchwork.plctlab.org/api/1.2/patches/3767/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-14-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-14-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:10","name":"[V2,13/15] binutils/NEWS: add text for SFrame support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-14-indu.bhagat@oracle.com/mbox/"},{"id":3772,"url":"https://patchwork.plctlab.org/api/1.2/patches/3772/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-15-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-15-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:11","name":"[V2,14/15] gas/NEWS: add text about new command line option and SFrame support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-15-indu.bhagat@oracle.com/mbox/"},{"id":3773,"url":"https://patchwork.plctlab.org/api/1.2/patches/3773/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-16-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-16-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:12","name":"[V2,15/15] doc: add SFrame spec file","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-16-indu.bhagat@oracle.com/mbox/"},{"id":3999,"url":"https://patchwork.plctlab.org/api/1.2/patches/3999/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221018081205.17880-1-krebbel@linux.ibm.com/","msgid":"<20221018081205.17880-1-krebbel@linux.ibm.com>","list_archive_url":null,"date":"2022-10-18T08:12:05","name":"[1/1] IBM zSystems: Issue error for *DBL relocs on misaligned symbols","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221018081205.17880-1-krebbel@linux.ibm.com/mbox/"},{"id":4141,"url":"https://patchwork.plctlab.org/api/1.2/patches/4141/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/baffaf673f17692b7bcbd604b31800b189988596.camel@espressif.com/","msgid":"","list_archive_url":null,"date":"2022-10-18T12:12:07","name":"xtensa: use definitions from xtensa-config.h","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/baffaf673f17692b7bcbd604b31800b189988596.camel@espressif.com/mbox/"},{"id":4272,"url":"https://patchwork.plctlab.org/api/1.2/patches/4272/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221018174914.470062-1-hjl.tools@gmail.com/","msgid":"<20221018174914.470062-1-hjl.tools@gmail.com>","list_archive_url":null,"date":"2022-10-18T17:49:14","name":"x86: Disable AVX-VNNI when disabling AVX2","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221018174914.470062-1-hjl.tools@gmail.com/mbox/"},{"id":4998,"url":"https://patchwork.plctlab.org/api/1.2/patches/4998/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c2f76e95-09f6-1d92-7ef4-38a3c2955fcd@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-19T09:52:46","name":"x86: re-work AVX-VNNI support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c2f76e95-09f6-1d92-7ef4-38a3c2955fcd@suse.com/mbox/"},{"id":5276,"url":"https://patchwork.plctlab.org/api/1.2/patches/5276/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0/lLtlKqqsmAx0s@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-19T11:53:18","name":"Fix addr2line test for ppc64 elfv1 and mingw","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0/lLtlKqqsmAx0s@squeak.grove.modra.org/mbox/"},{"id":5424,"url":"https://patchwork.plctlab.org/api/1.2/patches/5424/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/07bfebbf3843b47e13d82d4fa16eb14fec942ef7.1666184962.git.research_trasio@irq.a4lg.com/","msgid":"<07bfebbf3843b47e13d82d4fa16eb14fec942ef7.1666184962.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:09:54","name":"binutils: Remove unused substitution PROGRAM","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/07bfebbf3843b47e13d82d4fa16eb14fec942ef7.1666184962.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5433,"url":"https://patchwork.plctlab.org/api/1.2/patches/5433/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2fa7ff719223232402e82a9c91331aea22ace1bb.1666185116.git.research_trasio@irq.a4lg.com/","msgid":"<2fa7ff719223232402e82a9c91331aea22ace1bb.1666185116.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:11:55","name":"[v2,1/8] RISC-V: Add a space at the end of pinfo","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2fa7ff719223232402e82a9c91331aea22ace1bb.1666185116.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5435,"url":"https://patchwork.plctlab.org/api/1.2/patches/5435/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1b30cce5db2cce3b8edca42ab5da114d0b8c9e93.1666185116.git.research_trasio@irq.a4lg.com/","msgid":"<1b30cce5db2cce3b8edca42ab5da114d0b8c9e93.1666185116.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:11:56","name":"[v2,2/8] RISC-V: Fix obvious misalignments ('\''Zbb'\''/'\''Zba'\'')","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1b30cce5db2cce3b8edca42ab5da114d0b8c9e93.1666185116.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5437,"url":"https://patchwork.plctlab.org/api/1.2/patches/5437/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6b0857aa1a2d15ca1cf00b4dcaae0032efbb88ff.1666185116.git.research_trasio@irq.a4lg.com/","msgid":"<6b0857aa1a2d15ca1cf00b4dcaae0032efbb88ff.1666185116.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:11:57","name":"[v2,3/8] RISC-V: Remove spaces in opcode entries","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6b0857aa1a2d15ca1cf00b4dcaae0032efbb88ff.1666185116.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5436,"url":"https://patchwork.plctlab.org/api/1.2/patches/5436/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/889d956caac0f2e95543a14afaeed97188ce384c.1666185116.git.research_trasio@irq.a4lg.com/","msgid":"<889d956caac0f2e95543a14afaeed97188ce384c.1666185116.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:11:58","name":"[v2,4/8] RISC-V: Remove unused instruction macros","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/889d956caac0f2e95543a14afaeed97188ce384c.1666185116.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5440,"url":"https://patchwork.plctlab.org/api/1.2/patches/5440/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8f226ee20d8a5ef6ad7b6c4408b44794a99d542a.1666185116.git.research_trasio@irq.a4lg.com/","msgid":"<8f226ee20d8a5ef6ad7b6c4408b44794a99d542a.1666185116.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:11:59","name":"[v2,5/8] RISC-V: Complete tidying up with SCALL and SBREAK","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8f226ee20d8a5ef6ad7b6c4408b44794a99d542a.1666185116.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5442,"url":"https://patchwork.plctlab.org/api/1.2/patches/5442/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4070184c454a05a39adf0790951e5856e6b2ecb6.1666185116.git.research_trasio@irq.a4lg.com/","msgid":"<4070184c454a05a39adf0790951e5856e6b2ecb6.1666185116.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:12:00","name":"[v2,6/8] RISC-V: Tidying up with fmv.w.x and fmv.x.w","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4070184c454a05a39adf0790951e5856e6b2ecb6.1666185116.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5438,"url":"https://patchwork.plctlab.org/api/1.2/patches/5438/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c1ccda3e7c8fb297eda46dab3936d5c5977178fc.1666185116.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-19T13:12:01","name":"[v2,7/8] RISC-V: Make alias instructions aliases","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c1ccda3e7c8fb297eda46dab3936d5c5977178fc.1666185116.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5441,"url":"https://patchwork.plctlab.org/api/1.2/patches/5441/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/413cfca82c7e8d8a2e977dfda9135903c9cb7c57.1666185116.git.research_trasio@irq.a4lg.com/","msgid":"<413cfca82c7e8d8a2e977dfda9135903c9cb7c57.1666185116.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:12:02","name":"[v2,8/8] RISC-V: Use defined mask and match values","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/413cfca82c7e8d8a2e977dfda9135903c9cb7c57.1666185116.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5439,"url":"https://patchwork.plctlab.org/api/1.2/patches/5439/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/345c5c3b3a53eab04a1e6e91197de2642095c94f.1666185237.git.research_trasio@irq.a4lg.com/","msgid":"<345c5c3b3a53eab04a1e6e91197de2642095c94f.1666185237.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:14:01","name":"RISC-V: Remove RV32EF conflict","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/345c5c3b3a53eab04a1e6e91197de2642095c94f.1666185237.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5616,"url":"https://patchwork.plctlab.org/api/1.2/patches/5616/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019145608.45213-5-haochen.jiang@intel.com/","msgid":"<20221019145608.45213-5-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T14:56:02","name":"[04/10] Support Intel CMPccXADD","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019145608.45213-5-haochen.jiang@intel.com/mbox/"},{"id":5614,"url":"https://patchwork.plctlab.org/api/1.2/patches/5614/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019145608.45213-6-haochen.jiang@intel.com/","msgid":"<20221019145608.45213-6-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T14:56:03","name":"[05/10] Add handler for more i386_cpu_flags","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019145608.45213-6-haochen.jiang@intel.com/mbox/"},{"id":5672,"url":"https://patchwork.plctlab.org/api/1.2/patches/5672/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-2-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-2-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:25","name":"[01/10] Support Intel AVX-IFMA","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-2-haochen.jiang@intel.com/mbox/"},{"id":5691,"url":"https://patchwork.plctlab.org/api/1.2/patches/5691/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-3-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-3-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:26","name":"[02/10] Support Intel AVX-VNNI-INT8","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-3-haochen.jiang@intel.com/mbox/"},{"id":5690,"url":"https://patchwork.plctlab.org/api/1.2/patches/5690/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-4-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-4-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:27","name":"[03/10] Support Intel AVX-NE-CONVERT","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-4-haochen.jiang@intel.com/mbox/"},{"id":5689,"url":"https://patchwork.plctlab.org/api/1.2/patches/5689/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-5-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-5-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:28","name":"[04/10] Support Intel CMPccXADD","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-5-haochen.jiang@intel.com/mbox/"},{"id":5676,"url":"https://patchwork.plctlab.org/api/1.2/patches/5676/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-6-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-6-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:29","name":"[05/10] Add handler for more i386_cpu_flags","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-6-haochen.jiang@intel.com/mbox/"},{"id":5677,"url":"https://patchwork.plctlab.org/api/1.2/patches/5677/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-7-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-7-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:30","name":"[06/10] Support Intel RAO-INT","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-7-haochen.jiang@intel.com/mbox/"},{"id":5681,"url":"https://patchwork.plctlab.org/api/1.2/patches/5681/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-8-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-8-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:31","name":"[07/10] Support Intel WRMSRNS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-8-haochen.jiang@intel.com/mbox/"},{"id":5682,"url":"https://patchwork.plctlab.org/api/1.2/patches/5682/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-9-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-9-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:32","name":"[08/10] Support Intel MSRLIST","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-9-haochen.jiang@intel.com/mbox/"},{"id":5673,"url":"https://patchwork.plctlab.org/api/1.2/patches/5673/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-10-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-10-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:33","name":"[09/10] Support Intel AMX-FP16","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-10-haochen.jiang@intel.com/mbox/"},{"id":5686,"url":"https://patchwork.plctlab.org/api/1.2/patches/5686/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-11-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-11-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:34","name":"[10/10] Support Intel PREFETCHI","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-11-haochen.jiang@intel.com/mbox/"},{"id":5940,"url":"https://patchwork.plctlab.org/api/1.2/patches/5940/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1CMrFUC8d9lC/NL@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-19T23:47:56","name":"Obsolete beos","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1CMrFUC8d9lC/NL@squeak.grove.modra.org/mbox/"},{"id":6080,"url":"https://patchwork.plctlab.org/api/1.2/patches/6080/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8b99d666e78ba5b9d32c7889a2161c70b3da88df.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<8b99d666e78ba5b9d32c7889a2161c70b3da88df.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:25:47","name":"[01/40] gdb/unittests: PR28413, suppress warnings generated by Gnulib","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8b99d666e78ba5b9d32c7889a2161c70b3da88df.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6081,"url":"https://patchwork.plctlab.org/api/1.2/patches/6081/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b05adb17e401d621dbdad791281bc7af7806906e.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-20T09:25:48","name":"[02/40] sim: Check known getrusage declaration existence","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b05adb17e401d621dbdad791281bc7af7806906e.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6083,"url":"https://patchwork.plctlab.org/api/1.2/patches/6083/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/796962a87e569feeafb5ef636de3c79000ae152c.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<796962a87e569feeafb5ef636de3c79000ae152c.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:25:49","name":"[03/40] sim/aarch64: Remove unused functions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/796962a87e569feeafb5ef636de3c79000ae152c.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6084,"url":"https://patchwork.plctlab.org/api/1.2/patches/6084/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/65223c79fdfd7faf132275415cd9da9852c5bec3.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<65223c79fdfd7faf132275415cd9da9852c5bec3.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:25:50","name":"[04/40] cpu/cris: Initialize some variables on CRIS CPU","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/65223c79fdfd7faf132275415cd9da9852c5bec3.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6082,"url":"https://patchwork.plctlab.org/api/1.2/patches/6082/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/24baefe92148f4b7968115ba13de9b0c863a65f6.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<24baefe92148f4b7968115ba13de9b0c863a65f6.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:25:51","name":"[05/40] cpu/cris: Add u-stall virtual unit to CRIS v32","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/24baefe92148f4b7968115ba13de9b0c863a65f6.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6087,"url":"https://patchwork.plctlab.org/api/1.2/patches/6087/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3904a5c3e80f8548150d8088a92059dd728c7ff8.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<3904a5c3e80f8548150d8088a92059dd728c7ff8.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:25:52","name":"[06/40] sim/cris: Move declarations of f_specific_init","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3904a5c3e80f8548150d8088a92059dd728c7ff8.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6091,"url":"https://patchwork.plctlab.org/api/1.2/patches/6091/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/69ef2d7dd519ed572511890a215a0f6d74e53384.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<69ef2d7dd519ed572511890a215a0f6d74e53384.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:25:53","name":"[07/40] sim/cris: Regenerate with CGEN","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/69ef2d7dd519ed572511890a215a0f6d74e53384.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6085,"url":"https://patchwork.plctlab.org/api/1.2/patches/6085/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/26a3eaf4f5d2e0db6977738ddfd65d82b36e38b2.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<26a3eaf4f5d2e0db6977738ddfd65d82b36e38b2.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:25:54","name":"[08/40] sim/erc32: Insert void parameter","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/26a3eaf4f5d2e0db6977738ddfd65d82b36e38b2.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6086,"url":"https://patchwork.plctlab.org/api/1.2/patches/6086/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/057c2f8392410494c3bc5dc98052246508e6a73e.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<057c2f8392410494c3bc5dc98052246508e6a73e.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:25:55","name":"[09/40] sim/erc32: Use int32_t as event callback argument","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/057c2f8392410494c3bc5dc98052246508e6a73e.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6090,"url":"https://patchwork.plctlab.org/api/1.2/patches/6090/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8c05aec20557191434485be347d37177a2ec5ff2.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<8c05aec20557191434485be347d37177a2ec5ff2.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:25:56","name":"[10/40] sim/erc32: Use int32_t as IRQ callback argument","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8c05aec20557191434485be347d37177a2ec5ff2.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6089,"url":"https://patchwork.plctlab.org/api/1.2/patches/6089/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/afd7757aae21743c29f2aa4135a23b31d4959e9b.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-20T09:25:57","name":"[11/40] cpu/frv: Initialize some variables","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/afd7757aae21743c29f2aa4135a23b31d4959e9b.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6088,"url":"https://patchwork.plctlab.org/api/1.2/patches/6088/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/021dbd238af5dfe74523ed229d2156a155a6bb9e.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<021dbd238af5dfe74523ed229d2156a155a6bb9e.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:25:58","name":"[12/40] sim/frv: Initialize nesr variable","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/021dbd238af5dfe74523ed229d2156a155a6bb9e.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6093,"url":"https://patchwork.plctlab.org/api/1.2/patches/6093/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/51a03f7097921cc48954210cf99e370ae8982ec8.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<51a03f7097921cc48954210cf99e370ae8982ec8.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:25:59","name":"[13/40] sim/frv: Initialize some variables","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/51a03f7097921cc48954210cf99e370ae8982ec8.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6092,"url":"https://patchwork.plctlab.org/api/1.2/patches/6092/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e1baa1be3601612266dc6ae0bdde8426ff2a42c8.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-20T09:26:00","name":"[14/40] sim/frv: Add explicit casts","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e1baa1be3601612266dc6ae0bdde8426ff2a42c8.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6095,"url":"https://patchwork.plctlab.org/api/1.2/patches/6095/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5ab303a5bdfc1da7832f8fa22f57678c9ef1a5fa.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<5ab303a5bdfc1da7832f8fa22f57678c9ef1a5fa.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:26:01","name":"[15/40] sim/h8300: Add \"+ 0x0\" to avoid self-assignments","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5ab303a5bdfc1da7832f8fa22f57678c9ef1a5fa.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6101,"url":"https://patchwork.plctlab.org/api/1.2/patches/6101/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ddff80db3328a2286fe6fbc1240d2abc1e3813eb.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-20T09:26:02","name":"[16/40] sim/lm32: fix some missing function declaration warnings","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ddff80db3328a2286fe6fbc1240d2abc1e3813eb.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6094,"url":"https://patchwork.plctlab.org/api/1.2/patches/6094/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e094b1379231d9ffb59a78cfebbcc84634c779c6.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-20T09:26:03","name":"[17/40] sim/lm32: Add explicit casts","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e094b1379231d9ffb59a78cfebbcc84634c779c6.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6141,"url":"https://patchwork.plctlab.org/api/1.2/patches/6141/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/cabebead-489b-528c-580e-933832417474@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-20T10:25:51","name":"[1/3] x86: emit {evex} prefix when disassembling ambiguous AVX512VL insns","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/cabebead-489b-528c-580e-933832417474@suse.com/mbox/"},{"id":6143,"url":"https://patchwork.plctlab.org/api/1.2/patches/6143/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a032d61c-63a0-23d1-331f-619a2b8bbde3@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-20T10:26:15","name":"[2/3] x86: consolidate VAES tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a032d61c-63a0-23d1-331f-619a2b8bbde3@suse.com/mbox/"},{"id":6142,"url":"https://patchwork.plctlab.org/api/1.2/patches/6142/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7ff09c86-2de7-dc34-3183-5187de3df5ac@suse.com/","msgid":"<7ff09c86-2de7-dc34-3183-5187de3df5ac@suse.com>","list_archive_url":null,"date":"2022-10-20T10:26:40","name":"[3/3] x86: consolidate VPCLMUL tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7ff09c86-2de7-dc34-3183-5187de3df5ac@suse.com/mbox/"},{"id":6228,"url":"https://patchwork.plctlab.org/api/1.2/patches/6228/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.LSU.2.20.2210201432170.29399@wotan.suse.de/","msgid":"","list_archive_url":null,"date":"2022-10-20T14:42:25","name":"x86-64: Use only one default max-page-size","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.LSU.2.20.2210201432170.29399@wotan.suse.de/mbox/"},{"id":6229,"url":"https://patchwork.plctlab.org/api/1.2/patches/6229/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221020144351.1398099-1-chigot@adacore.com/","msgid":"<20221020144351.1398099-1-chigot@adacore.com>","list_archive_url":null,"date":"2022-10-20T14:43:50","name":"[1/2] ld/testsuite: skip ld-elf/exclude when -shared is not supported","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221020144351.1398099-1-chigot@adacore.com/mbox/"},{"id":6230,"url":"https://patchwork.plctlab.org/api/1.2/patches/6230/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221020144351.1398099-2-chigot@adacore.com/","msgid":"<20221020144351.1398099-2-chigot@adacore.com>","list_archive_url":null,"date":"2022-10-20T14:43:51","name":"[2/2] ld/testsuite: adjust ld-arm to run shared tests only when supported","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221020144351.1398099-2-chigot@adacore.com/mbox/"},{"id":6236,"url":"https://patchwork.plctlab.org/api/1.2/patches/6236/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221020151027.GA1300@delia.home/","msgid":"<20221020151027.GA1300@delia.home>","list_archive_url":null,"date":"2022-10-20T15:10:28","name":"[RFC,top-level] Add configure test-case","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221020151027.GA1300@delia.home/mbox/"},{"id":6286,"url":"https://patchwork.plctlab.org/api/1.2/patches/6286/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221020162911.1113338-1-hjl.tools@gmail.com/","msgid":"<20221020162911.1113338-1-hjl.tools@gmail.com>","list_archive_url":null,"date":"2022-10-20T16:29:11","name":"x86: Check VEX/EVEX encoding before checking vector operands","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221020162911.1113338-1-hjl.tools@gmail.com/mbox/"},{"id":7884,"url":"https://patchwork.plctlab.org/api/1.2/patches/7884/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7e53b7980f2b3b74d2250bc87f5db94b1d888a2d.camel@espressif.com/","msgid":"<7e53b7980f2b3b74d2250bc87f5db94b1d888a2d.camel@espressif.com>","list_archive_url":null,"date":"2022-10-22T12:53:54","name":"[1/5] bfd: xtensa: move common code from ld and gas","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7e53b7980f2b3b74d2250bc87f5db94b1d888a2d.camel@espressif.com/mbox/"},{"id":7885,"url":"https://patchwork.plctlab.org/api/1.2/patches/7885/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/63f2699e6ef3e6d1ca415a6ed1187d4f64297521.camel@espressif.com/","msgid":"<63f2699e6ef3e6d1ca415a6ed1187d4f64297521.camel@espressif.com>","list_archive_url":null,"date":"2022-10-22T12:55:16","name":"[2/5] gas: xtensa: add endianness, loops, booleans options","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/63f2699e6ef3e6d1ca415a6ed1187d4f64297521.camel@espressif.com/mbox/"},{"id":7886,"url":"https://patchwork.plctlab.org/api/1.2/patches/7886/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/34d2f747237aeeda595560cfded8096d9bd1c28c.camel@espressif.com/","msgid":"<34d2f747237aeeda595560cfded8096d9bd1c28c.camel@espressif.com>","list_archive_url":null,"date":"2022-10-22T12:56:02","name":"[3/5] ld: xtensa: use default LD command line options for endianness","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/34d2f747237aeeda595560cfded8096d9bd1c28c.camel@espressif.com/mbox/"},{"id":7891,"url":"https://patchwork.plctlab.org/api/1.2/patches/7891/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/535b6208c1718b9acf3258575e1ebc0a65af9f07.camel@espressif.com/","msgid":"<535b6208c1718b9acf3258575e1ebc0a65af9f07.camel@espressif.com>","list_archive_url":null,"date":"2022-10-22T13:56:44","name":"[5/5] gdb: xtensa: add support for esp32, esp32s2, esp32s3 isa-modules","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/535b6208c1718b9acf3258575e1ebc0a65af9f07.camel@espressif.com/mbox/"},{"id":10456,"url":"https://patchwork.plctlab.org/api/1.2/patches/10456/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221025013347.68282-1-nelson@rivosinc.com/","msgid":"<20221025013347.68282-1-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-10-25T01:33:46","name":"[committed,1/2] RISC-V: Improve link time complexity.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221025013347.68282-1-nelson@rivosinc.com/mbox/"},{"id":10454,"url":"https://patchwork.plctlab.org/api/1.2/patches/10454/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221025013347.68282-2-nelson@rivosinc.com/","msgid":"<20221025013347.68282-2-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-10-25T01:33:47","name":"[committed,2/2] RISC-V: Should reset `again'\'' flag for _bfd_riscv_relax_pc.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221025013347.68282-2-nelson@rivosinc.com/mbox/"},{"id":10536,"url":"https://patchwork.plctlab.org/api/1.2/patches/10536/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/bb7b87e4-1893-5c86-4a14-92bafc818b03@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-25T07:24:56","name":"[v5,1/8] x86: constify parse_insn()'\''s input","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/bb7b87e4-1893-5c86-4a14-92bafc818b03@suse.com/mbox/"},{"id":10537,"url":"https://patchwork.plctlab.org/api/1.2/patches/10537/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b9273ae6-0218-54f8-5374-b265ed13b71a@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-25T07:25:26","name":"[v5,1/8] x86: introduce Pass2 insn attribute","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b9273ae6-0218-54f8-5374-b265ed13b71a@suse.com/mbox/"},{"id":10541,"url":"https://patchwork.plctlab.org/api/1.2/patches/10541/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7250dab9-e218-e6dd-4c74-23da9f611ab4@suse.com/","msgid":"<7250dab9-e218-e6dd-4c74-23da9f611ab4@suse.com>","list_archive_url":null,"date":"2022-10-25T07:26:11","name":"[v5,3/8] x86: re-work insn/suffix recognition","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7250dab9-e218-e6dd-4c74-23da9f611ab4@suse.com/mbox/"},{"id":10540,"url":"https://patchwork.plctlab.org/api/1.2/patches/10540/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/13fc630f-e116-0099-5c9e-2697df6519d7@suse.com/","msgid":"<13fc630f-e116-0099-5c9e-2697df6519d7@suse.com>","list_archive_url":null,"date":"2022-10-25T07:26:40","name":"[v5,4/8] ix86: don'\''t recognize/derive Q suffix in the common case","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/13fc630f-e116-0099-5c9e-2697df6519d7@suse.com/mbox/"},{"id":10543,"url":"https://patchwork.plctlab.org/api/1.2/patches/10543/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/74db429d-d203-eab8-4ae1-18b9ad416b02@suse.com/","msgid":"<74db429d-d203-eab8-4ae1-18b9ad416b02@suse.com>","list_archive_url":null,"date":"2022-10-25T07:27:11","name":"[v5,5/8] x86-64: allow HLE store of accumulator to absolute 32-bit address","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/74db429d-d203-eab8-4ae1-18b9ad416b02@suse.com/mbox/"},{"id":10542,"url":"https://patchwork.plctlab.org/api/1.2/patches/10542/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2e2f7841-de4e-b5de-e8d9-a47a6a4113c8@suse.com/","msgid":"<2e2f7841-de4e-b5de-e8d9-a47a6a4113c8@suse.com>","list_archive_url":null,"date":"2022-10-25T07:27:35","name":"[v5,6/8] x86: move bad-use-of-TLS-reloc check","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2e2f7841-de4e-b5de-e8d9-a47a6a4113c8@suse.com/mbox/"},{"id":10545,"url":"https://patchwork.plctlab.org/api/1.2/patches/10545/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/421bc96e-7591-6980-48e9-5af8c8b0775a@suse.com/","msgid":"<421bc96e-7591-6980-48e9-5af8c8b0775a@suse.com>","list_archive_url":null,"date":"2022-10-25T07:28:27","name":"[v5,7/8] x86: drop (now) stray IsString","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/421bc96e-7591-6980-48e9-5af8c8b0775a@suse.com/mbox/"},{"id":10546,"url":"https://patchwork.plctlab.org/api/1.2/patches/10546/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/06ff83d4-4633-a07b-70e5-a8e049981dd4@suse.com/","msgid":"<06ff83d4-4633-a07b-70e5-a8e049981dd4@suse.com>","list_archive_url":null,"date":"2022-10-25T07:29:18","name":"[v5,8/8] x86: further re-work insn/suffix recognition to also cover MOVSX","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/06ff83d4-4633-a07b-70e5-a8e049981dd4@suse.com/mbox/"},{"id":10777,"url":"https://patchwork.plctlab.org/api/1.2/patches/10777/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6a8e7a71acccd0efb9789dfb3edfa307e83bdaa1.1666702934.git.research_trasio@irq.a4lg.com/","msgid":"<6a8e7a71acccd0efb9789dfb3edfa307e83bdaa1.1666702934.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-25T13:04:02","name":"[RFC] RISC-V: Allocate \"various\" operand type","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6a8e7a71acccd0efb9789dfb3edfa307e83bdaa1.1666702934.git.research_trasio@irq.a4lg.com/mbox/"},{"id":11062,"url":"https://patchwork.plctlab.org/api/1.2/patches/11062/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jAhwbXhxJHL66v@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-26T05:07:19","name":"PR29720, objdump -S crashes if build-id is missing","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jAhwbXhxJHL66v@squeak.grove.modra.org/mbox/"},{"id":11063,"url":"https://patchwork.plctlab.org/api/1.2/patches/11063/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jAxD+NxpMIah6s@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-26T05:08:20","name":"som.c buffer overflow","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jAxD+NxpMIah6s@squeak.grove.modra.org/mbox/"},{"id":11064,"url":"https://patchwork.plctlab.org/api/1.2/patches/11064/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jBYw4lfRQfOZhi@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-26T05:10:59","name":"som.c reloc sanity checking","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jBYw4lfRQfOZhi@squeak.grove.modra.org/mbox/"},{"id":11080,"url":"https://patchwork.plctlab.org/api/1.2/patches/11080/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jY7hygm01PelCY@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-26T06:51:26","name":"segfault in objdump.c reloc_at","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jY7hygm01PelCY@squeak.grove.modra.org/mbox/"},{"id":11081,"url":"https://patchwork.plctlab.org/api/1.2/patches/11081/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jZWIeIvCCYm9/g@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-26T06:53:12","name":"Correct ELF reloc size sanity check","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jZWIeIvCCYm9/g@squeak.grove.modra.org/mbox/"},{"id":11082,"url":"https://patchwork.plctlab.org/api/1.2/patches/11082/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221026070009.3663574-1-ysato@users.sourceforge.jp/","msgid":"<20221026070009.3663574-1-ysato@users.sourceforge.jp>","list_archive_url":null,"date":"2022-10-26T07:00:09","name":"opcodes: RX fix invalid output.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221026070009.3663574-1-ysato@users.sourceforge.jp/mbox/"},{"id":11089,"url":"https://patchwork.plctlab.org/api/1.2/patches/11089/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jhW48kuVC8Ig2d@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-26T07:27:23","name":"buffer overflow in _bfd_XX_print_ce_compressed_pdata","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jhW48kuVC8Ig2d@squeak.grove.modra.org/mbox/"},{"id":11157,"url":"https://patchwork.plctlab.org/api/1.2/patches/11157/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c52dbd16-7e1b-c356-7a92-1ff089564ef7@suse.cz/","msgid":"","list_archive_url":null,"date":"2022-10-26T08:47:09","name":"tests: use canonical option name","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c52dbd16-7e1b-c356-7a92-1ff089564ef7@suse.cz/mbox/"},{"id":11526,"url":"https://patchwork.plctlab.org/api/1.2/patches/11526/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027031915.4013-1-lifang_xia@linux.alibaba.com/","msgid":"<20221027031915.4013-1-lifang_xia@linux.alibaba.com>","list_archive_url":null,"date":"2022-10-27T03:19:15","name":"[v2] RISC-V: Optimize relax of GP/call with max_alignment.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027031915.4013-1-lifang_xia@linux.alibaba.com/mbox/"},{"id":11619,"url":"https://patchwork.plctlab.org/api/1.2/patches/11619/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9df9d9e5bb4c7594b76c40613a349b4d2364e9c5.1666854355.git.research_trasio@irq.a4lg.com/","msgid":"<9df9d9e5bb4c7594b76c40613a349b4d2364e9c5.1666854355.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-27T07:06:01","name":"include: Define macro to ignore -Wdeprecated-declarations on GCC","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9df9d9e5bb4c7594b76c40613a349b4d2364e9c5.1666854355.git.research_trasio@irq.a4lg.com/mbox/"},{"id":11627,"url":"https://patchwork.plctlab.org/api/1.2/patches/11627/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1o06O9Pp8ncCsOw@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-27T07:36:08","name":"Fuzzed files in archives","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1o06O9Pp8ncCsOw@squeak.grove.modra.org/mbox/"},{"id":11658,"url":"https://patchwork.plctlab.org/api/1.2/patches/11658/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027084808.37252-1-nelson@rivosinc.com/","msgid":"<20221027084808.37252-1-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-10-27T08:48:08","name":"[committed] RISC-V: Fix build failures for -Werror=sign-compare.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027084808.37252-1-nelson@rivosinc.com/mbox/"},{"id":11921,"url":"https://patchwork.plctlab.org/api/1.2/patches/11921/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027190052.10536-1-mark@harmstone.com/","msgid":"<20221027190052.10536-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-27T19:00:51","name":"[1/2] ld: Add section header stream to PDB files","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027190052.10536-1-mark@harmstone.com/mbox/"},{"id":11922,"url":"https://patchwork.plctlab.org/api/1.2/patches/11922/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027190052.10536-2-mark@harmstone.com/","msgid":"<20221027190052.10536-2-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-27T19:00:52","name":"[2/2] ld: Add publics stream to PDB files","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027190052.10536-2-mark@harmstone.com/mbox/"},{"id":11965,"url":"https://patchwork.plctlab.org/api/1.2/patches/11965/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027202719.32497-1-palmer@rivosinc.com/","msgid":"<20221027202719.32497-1-palmer@rivosinc.com>","list_archive_url":null,"date":"2022-10-27T20:27:18","name":"[1/2] gas: NEWS: Add a missing newline","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027202719.32497-1-palmer@rivosinc.com/mbox/"},{"id":11966,"url":"https://patchwork.plctlab.org/api/1.2/patches/11966/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027202719.32497-2-palmer@rivosinc.com/","msgid":"<20221027202719.32497-2-palmer@rivosinc.com>","list_archive_url":null,"date":"2022-10-27T20:27:19","name":"[2/2] gas: NEWS: Note support for RISC-V Zawrs","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027202719.32497-2-palmer@rivosinc.com/mbox/"},{"id":12016,"url":"https://patchwork.plctlab.org/api/1.2/patches/12016/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/21ec9a18-fa89-0828-f625-499680022ec7@linux.ibm.com/","msgid":"<21ec9a18-fa89-0828-f625-499680022ec7@linux.ibm.com>","list_archive_url":null,"date":"2022-10-28T00:35:19","name":"[COMMITTED] PowerPC: Add support for RFC02653 - Dense Math Facility","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/21ec9a18-fa89-0828-f625-499680022ec7@linux.ibm.com/mbox/"},{"id":12017,"url":"https://patchwork.plctlab.org/api/1.2/patches/12017/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fd94047d-a070-45a6-3840-c105391718e0@linux.ibm.com/","msgid":"","list_archive_url":null,"date":"2022-10-28T00:37:18","name":"[COMMITTED] PowerPC: Add support for RFC02658 - MMA+ Outer-Product, Instructions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fd94047d-a070-45a6-3840-c105391718e0@linux.ibm.com/mbox/"},{"id":12122,"url":"https://patchwork.plctlab.org/api/1.2/patches/12122/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ac4f3f3c7115a824f73aca6935789b14d33c9a58.1666939920.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-28T06:53:02","name":"RISC-V: Fix build failure for -Werror=maybe-uninitialized","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ac4f3f3c7115a824f73aca6935789b14d33c9a58.1666939920.git.research_trasio@irq.a4lg.com/mbox/"},{"id":12181,"url":"https://patchwork.plctlab.org/api/1.2/patches/12181/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221028093840.19164-1-nelson@rivosinc.com/","msgid":"<20221028093840.19164-1-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-10-28T09:38:40","name":"RISC-V: Added SiFive custom cache control extensions.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221028093840.19164-1-nelson@rivosinc.com/mbox/"},{"id":12211,"url":"https://patchwork.plctlab.org/api/1.2/patches/12211/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4a280588-a85b-6ed3-634b-2b9cbc128f86@suse.com/","msgid":"<4a280588-a85b-6ed3-634b-2b9cbc128f86@suse.com>","list_archive_url":null,"date":"2022-10-28T10:06:35","name":"RISC-V/gas: fix build with certain gcc versions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4a280588-a85b-6ed3-634b-2b9cbc128f86@suse.com/mbox/"},{"id":12249,"url":"https://patchwork.plctlab.org/api/1.2/patches/12249/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/eb0e1bff-675e-72db-b8b1-b0f0e50b7121@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-28T12:35:35","name":"x86: minor improvements to optimize_imm() (part III)","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/eb0e1bff-675e-72db-b8b1-b0f0e50b7121@suse.com/mbox/"},{"id":12382,"url":"https://patchwork.plctlab.org/api/1.2/patches/12382/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/17f57574936af82be381a1451eac56b3709b60bb.1666968673.git.research_trasio@irq.a4lg.com/","msgid":"<17f57574936af82be381a1451eac56b3709b60bb.1666968673.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-28T14:52:12","name":"RISC-V: Emit mapping symbol with ISA string if non-default arch is used","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/17f57574936af82be381a1451eac56b3709b60bb.1666968673.git.research_trasio@irq.a4lg.com/mbox/"},{"id":12627,"url":"https://patchwork.plctlab.org/api/1.2/patches/12627/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221029034432.49859-1-nelson@rivosinc.com/","msgid":"<20221029034432.49859-1-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-10-29T03:44:32","name":"[committed] RISC-V: Always generate mapping symbols at the start of the sections.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221029034432.49859-1-nelson@rivosinc.com/mbox/"},{"id":12629,"url":"https://patchwork.plctlab.org/api/1.2/patches/12629/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1yxgzNJg5M48uPI@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-29T04:52:19","name":"NULL dereference read in som_write_object_contents","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1yxgzNJg5M48uPI@squeak.grove.modra.org/mbox/"},{"id":12630,"url":"https://patchwork.plctlab.org/api/1.2/patches/12630/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1yxnSHLY+FeB5DQ@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-29T04:52:45","name":"Fix small objcopy memory leak","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1yxnSHLY+FeB5DQ@squeak.grove.modra.org/mbox/"},{"id":12631,"url":"https://patchwork.plctlab.org/api/1.2/patches/12631/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1yxxfpJz+Jx4KTh@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-29T04:53:25","name":"pef: sanity check before malloc","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1yxxfpJz+Jx4KTh@squeak.grove.modra.org/mbox/"},{"id":12950,"url":"https://patchwork.plctlab.org/api/1.2/patches/12950/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-2-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-2-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:36","name":"[V3,01/15] sframe.h: Add SFrame format definition","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-2-indu.bhagat@oracle.com/mbox/"},{"id":12952,"url":"https://patchwork.plctlab.org/api/1.2/patches/12952/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-3-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-3-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:37","name":"[V3,02/15] gas: add new command line option --gsframe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-3-indu.bhagat@oracle.com/mbox/"},{"id":12951,"url":"https://patchwork.plctlab.org/api/1.2/patches/12951/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-4-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-4-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:38","name":"[V3,03/15] gas: generate .sframe from CFI directives","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-4-indu.bhagat@oracle.com/mbox/"},{"id":12956,"url":"https://patchwork.plctlab.org/api/1.2/patches/12956/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-5-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-5-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:39","name":"[V3,04/15] gas: testsuite: add new tests for SFrame unwind info","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-5-indu.bhagat@oracle.com/mbox/"},{"id":12955,"url":"https://patchwork.plctlab.org/api/1.2/patches/12955/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-6-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-6-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:40","name":"[V3,05/15] libsframe: add the SFrame library","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-6-indu.bhagat@oracle.com/mbox/"},{"id":12959,"url":"https://patchwork.plctlab.org/api/1.2/patches/12959/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-7-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-7-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:41","name":"[V3,06/15] bfd: linker: merge .sframe sections","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-7-indu.bhagat@oracle.com/mbox/"},{"id":12961,"url":"https://patchwork.plctlab.org/api/1.2/patches/12961/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-8-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-8-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:42","name":"[V3,07/15] readelf/objdump: support for SFrame section","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-8-indu.bhagat@oracle.com/mbox/"},{"id":12962,"url":"https://patchwork.plctlab.org/api/1.2/patches/12962/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-9-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-9-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:43","name":"[V3,08/15] unwinder: generate backtrace using SFrame format","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-9-indu.bhagat@oracle.com/mbox/"},{"id":12963,"url":"https://patchwork.plctlab.org/api/1.2/patches/12963/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-10-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-10-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:44","name":"[V3,09/15] unwinder: Add SFrame unwinder tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-10-indu.bhagat@oracle.com/mbox/"},{"id":12964,"url":"https://patchwork.plctlab.org/api/1.2/patches/12964/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-11-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-11-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:45","name":"[V3,10/15] gdb: sim: buildsystem changes to accommodate libsframe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-11-indu.bhagat@oracle.com/mbox/"},{"id":12957,"url":"https://patchwork.plctlab.org/api/1.2/patches/12957/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-12-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-12-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:46","name":"[V3,11/15] libctf: add libsframe to LDFLAGS and LIBS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-12-indu.bhagat@oracle.com/mbox/"},{"id":12960,"url":"https://patchwork.plctlab.org/api/1.2/patches/12960/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-13-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-13-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:47","name":"[V3,12/15] src-release.sh: Add libsframe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-13-indu.bhagat@oracle.com/mbox/"},{"id":12953,"url":"https://patchwork.plctlab.org/api/1.2/patches/12953/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-14-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-14-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:48","name":"[V3,13/15] binutils/NEWS: add text for SFrame support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-14-indu.bhagat@oracle.com/mbox/"},{"id":12954,"url":"https://patchwork.plctlab.org/api/1.2/patches/12954/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-15-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-15-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:49","name":"[V3,14/15] gas/NEWS: add text about new command line option and SFrame support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-15-indu.bhagat@oracle.com/mbox/"},{"id":12958,"url":"https://patchwork.plctlab.org/api/1.2/patches/12958/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-16-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-16-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:50","name":"[V3,15/15] doc: add SFrame spec file","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-16-indu.bhagat@oracle.com/mbox/"},{"id":12988,"url":"https://patchwork.plctlab.org/api/1.2/patches/12988/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y15KFY32CyFhh/+u@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-30T09:55:33","name":"Pool section entries for DWP version 1","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y15KFY32CyFhh/+u@squeak.grove.modra.org/mbox/"},{"id":13076,"url":"https://patchwork.plctlab.org/api/1.2/patches/13076/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031001554.14615-1-mark@harmstone.com/","msgid":"<20221031001554.14615-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-31T00:15:52","name":"[v2,1/3] ld: Use %E in einfo in pdb.c","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031001554.14615-1-mark@harmstone.com/mbox/"},{"id":13078,"url":"https://patchwork.plctlab.org/api/1.2/patches/13078/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031001554.14615-2-mark@harmstone.com/","msgid":"<20221031001554.14615-2-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-31T00:15:53","name":"[v2,2/3] ld: Add section header stream to PDB files","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031001554.14615-2-mark@harmstone.com/mbox/"},{"id":13077,"url":"https://patchwork.plctlab.org/api/1.2/patches/13077/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031001554.14615-3-mark@harmstone.com/","msgid":"<20221031001554.14615-3-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-31T00:15:54","name":"[v2,3/3] ld: Add publics stream to PDB files","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031001554.14615-3-mark@harmstone.com/mbox/"},{"id":13106,"url":"https://patchwork.plctlab.org/api/1.2/patches/13106/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031030507.35588-2-haochen.jiang@intel.com/","msgid":"<20221031030507.35588-2-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-31T03:05:02","name":"[1/6] Support Intel AVX-IFMA","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031030507.35588-2-haochen.jiang@intel.com/mbox/"},{"id":13105,"url":"https://patchwork.plctlab.org/api/1.2/patches/13105/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031030507.35588-3-haochen.jiang@intel.com/","msgid":"<20221031030507.35588-3-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-31T03:05:03","name":"[2/6] Support Intel AVX-VNNI-INT8","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031030507.35588-3-haochen.jiang@intel.com/mbox/"},{"id":13103,"url":"https://patchwork.plctlab.org/api/1.2/patches/13103/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031030507.35588-4-haochen.jiang@intel.com/","msgid":"<20221031030507.35588-4-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-31T03:05:04","name":"[3/6] Support Intel CMPccXADD","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031030507.35588-4-haochen.jiang@intel.com/mbox/"},{"id":13101,"url":"https://patchwork.plctlab.org/api/1.2/patches/13101/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031030507.35588-5-haochen.jiang@intel.com/","msgid":"<20221031030507.35588-5-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-31T03:05:05","name":"[4/6] Add handler for more i386_cpu_flags","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031030507.35588-5-haochen.jiang@intel.com/mbox/"},{"id":13104,"url":"https://patchwork.plctlab.org/api/1.2/patches/13104/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031030507.35588-6-haochen.jiang@intel.com/","msgid":"<20221031030507.35588-6-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-31T03:05:06","name":"[5/6] Support Intel WRMSRNS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031030507.35588-6-haochen.jiang@intel.com/mbox/"},{"id":13102,"url":"https://patchwork.plctlab.org/api/1.2/patches/13102/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031030507.35588-7-haochen.jiang@intel.com/","msgid":"<20221031030507.35588-7-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-31T03:05:07","name":"[6/6] Support Intel MSRLIST","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031030507.35588-7-haochen.jiang@intel.com/mbox/"},{"id":13120,"url":"https://patchwork.plctlab.org/api/1.2/patches/13120/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031060601.38460-2-haochen.jiang@intel.com/","msgid":"<20221031060601.38460-2-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-31T06:06:00","name":"[1/2] i386: Add and ","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031060601.38460-2-haochen.jiang@intel.com/mbox/"},{"id":13121,"url":"https://patchwork.plctlab.org/api/1.2/patches/13121/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031060601.38460-3-haochen.jiang@intel.com/","msgid":"<20221031060601.38460-3-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-31T06:06:01","name":"[2/2] Support Intel AVX-NE-CONVERT","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031060601.38460-3-haochen.jiang@intel.com/mbox/"},{"id":13188,"url":"https://patchwork.plctlab.org/api/1.2/patches/13188/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9f6f8888-4dc1-a6b0-0590-35fc8a276369@suse.com/","msgid":"<9f6f8888-4dc1-a6b0-0590-35fc8a276369@suse.com>","list_archive_url":null,"date":"2022-10-31T10:18:20","name":"x86: drop bogus Tbyte","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9f6f8888-4dc1-a6b0-0590-35fc8a276369@suse.com/mbox/"},{"id":13213,"url":"https://patchwork.plctlab.org/api/1.2/patches/13213/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4f1aac95-fea5-2279-cb18-dfcdb51a2589@arm.com/","msgid":"<4f1aac95-fea5-2279-cb18-dfcdb51a2589@arm.com>","list_archive_url":null,"date":"2022-10-31T11:14:44","name":"aarch64: Add support for Common Short Sequence Compression extension","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4f1aac95-fea5-2279-cb18-dfcdb51a2589@arm.com/mbox/"}],"public":true,"mbox":"https://patchwork.plctlab.org/bundle/patchwork-bot/binutils-gdb_2022-10/mbox/"},{"id":7,"url":"https://patchwork.plctlab.org/api/1.2/bundles/7/","web_url":"https://patchwork.plctlab.org/bundle/patchwork-bot/binutils-gdb_2022-09/","project":{"id":2,"url":"https://patchwork.plctlab.org/api/1.2/projects/2/","name":"binutils-gdb","link_name":"binutils-gdb","list_id":"binutils.sourceware.org","list_email":"binutils@sourceware.org","web_url":"https://github.com/wangliu-iscas/Patchwork-Bundles/blob/main/binutils-gdb.md","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"name":"binutils-gdb_2022-09","owner":{"id":3,"url":"https://patchwork.plctlab.org/api/1.2/users/3/","username":"patchwork-bot","first_name":"","last_name":"","email":"ouuuleilei@gmail.com"},"patches":[{"id":1573,"url":"https://patchwork.plctlab.org/api/1.2/patches/1573/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930073211.2634-1-jiawei@iscas.ac.cn/","msgid":"<20220930073211.2634-1-jiawei@iscas.ac.cn>","list_archive_url":null,"date":"2022-09-30T07:32:11","name":"[V2] RISC-V: Add Smepmp CSR '\''mseccfg'\'' define and testcases.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930073211.2634-1-jiawei@iscas.ac.cn/mbox/"},{"id":1577,"url":"https://patchwork.plctlab.org/api/1.2/patches/1577/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/76fa0c3c-2303-ebdf-a765-ac4731581517@suse.com/","msgid":"<76fa0c3c-2303-ebdf-a765-ac4731581517@suse.com>","list_archive_url":null,"date":"2022-09-30T08:54:18","name":"objcopy: avoid \"shadowing\" of remove() function name","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/76fa0c3c-2303-ebdf-a765-ac4731581517@suse.com/mbox/"},{"id":1579,"url":"https://patchwork.plctlab.org/api/1.2/patches/1579/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930085852.71213-1-nelson@rivosinc.com/","msgid":"<20220930085852.71213-1-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-09-30T08:58:51","name":"[1/2] RISC-V: Output mapping symbols with ISA string.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930085852.71213-1-nelson@rivosinc.com/mbox/"},{"id":1578,"url":"https://patchwork.plctlab.org/api/1.2/patches/1578/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930085852.71213-2-nelson@rivosinc.com/","msgid":"<20220930085852.71213-2-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-09-30T08:58:52","name":"[2/2] RISC-V: Refer mapping symbol to R_RISCV_RELAX for rvc relaxations.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930085852.71213-2-nelson@rivosinc.com/mbox/"},{"id":1581,"url":"https://patchwork.plctlab.org/api/1.2/patches/1581/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930092058.71286-1-nelson@rivosinc.com/","msgid":"<20220930092058.71286-1-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-09-30T09:20:57","name":"[1/2] RISC-V: Output mapping symbols with ISA string.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930092058.71286-1-nelson@rivosinc.com/mbox/"},{"id":1580,"url":"https://patchwork.plctlab.org/api/1.2/patches/1580/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930092058.71286-2-nelson@rivosinc.com/","msgid":"<20220930092058.71286-2-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-09-30T09:20:58","name":"[2/2] RISC-V: Refer mapping symbol to R_RISCV_RELAX for rvc relaxations.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930092058.71286-2-nelson@rivosinc.com/mbox/"},{"id":1582,"url":"https://patchwork.plctlab.org/api/1.2/patches/1582/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5874dd79-0cf5-d65c-7ea2-13adfc799c0f@suse.com/","msgid":"<5874dd79-0cf5-d65c-7ea2-13adfc799c0f@suse.com>","list_archive_url":null,"date":"2022-09-30T09:41:29","name":"RISC-V: fix build after \"Add support for arbitrary immediate encoding formats\"","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5874dd79-0cf5-d65c-7ea2-13adfc799c0f@suse.com/mbox/"},{"id":1583,"url":"https://patchwork.plctlab.org/api/1.2/patches/1583/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/57d8ac2a-5757-3776-9924-99c17ca69938@suse.com/","msgid":"<57d8ac2a-5757-3776-9924-99c17ca69938@suse.com>","list_archive_url":null,"date":"2022-09-30T09:42:08","name":"RISC-V: fallout from \"re-arrange opcode table for consistent alias handling\"","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/57d8ac2a-5757-3776-9924-99c17ca69938@suse.com/mbox/"},{"id":1584,"url":"https://patchwork.plctlab.org/api/1.2/patches/1584/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e76ef8f7-72b9-5103-cb43-9608af01d017@suse.com/","msgid":"","list_archive_url":null,"date":"2022-09-30T09:42:50","name":"RISC-V: don'\''t cast expressions'\'' X_add_number to long in diagnostics","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e76ef8f7-72b9-5103-cb43-9608af01d017@suse.com/mbox/"},{"id":1585,"url":"https://patchwork.plctlab.org/api/1.2/patches/1585/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/61355429-24b3-17d0-ab03-6fa57ee861d5@suse.cz/","msgid":"<61355429-24b3-17d0-ab03-6fa57ee861d5@suse.cz>","list_archive_url":null,"date":"2022-09-30T09:48:52","name":"[RFC] add --enable-zstd-compressed-debug-sections configure option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/61355429-24b3-17d0-ab03-6fa57ee861d5@suse.cz/mbox/"},{"id":1586,"url":"https://patchwork.plctlab.org/api/1.2/patches/1586/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930103919.323690-1-christoph.muellner@vrull.eu/","msgid":"<20220930103919.323690-1-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2022-09-30T10:39:19","name":"RISC-V: Eliminate long-casts of X_add_number in diagnostics","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930103919.323690-1-christoph.muellner@vrull.eu/mbox/"},{"id":1590,"url":"https://patchwork.plctlab.org/api/1.2/patches/1590/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/DM6PR12MB4219C943049C6D883DEA3E55E7569@DM6PR12MB4219.namprd12.prod.outlook.com/","msgid":"","list_archive_url":null,"date":"2022-09-30T11:41:37","name":"[V2] Ignore DWARF debug information for -gsplit-dwarf with dwarf-5.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/DM6PR12MB4219C943049C6D883DEA3E55E7569@DM6PR12MB4219.namprd12.prod.outlook.com/mbox/"},{"id":1591,"url":"https://patchwork.plctlab.org/api/1.2/patches/1591/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c10321f9-d289-ef84-d263-bc278fb3d31b@suse.com/","msgid":"","list_archive_url":null,"date":"2022-09-30T11:59:04","name":"[1/4] RISC-V/gas: drop riscv_subsets static variable","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c10321f9-d289-ef84-d263-bc278fb3d31b@suse.com/mbox/"},{"id":1593,"url":"https://patchwork.plctlab.org/api/1.2/patches/1593/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3244eea0-c18c-e49a-4588-d69423130226@suse.com/","msgid":"<3244eea0-c18c-e49a-4588-d69423130226@suse.com>","list_archive_url":null,"date":"2022-09-30T11:59:23","name":"[2/4] RISC-V/gas: drop stray call to install_insn()","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3244eea0-c18c-e49a-4588-d69423130226@suse.com/mbox/"},{"id":1592,"url":"https://patchwork.plctlab.org/api/1.2/patches/1592/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/385d01fd-7e57-1f3f-1bae-30aa0c313d63@suse.com/","msgid":"<385d01fd-7e57-1f3f-1bae-30aa0c313d63@suse.com>","list_archive_url":null,"date":"2022-09-30T11:59:45","name":"[3/4] RISC-V/gas: don'\''t open-code insn_length()","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/385d01fd-7e57-1f3f-1bae-30aa0c313d63@suse.com/mbox/"},{"id":1594,"url":"https://patchwork.plctlab.org/api/1.2/patches/1594/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f5757acf-7b90-a0e3-5eea-3b97cc226930@suse.com/","msgid":"","list_archive_url":null,"date":"2022-09-30T12:00:12","name":"[4/4] RISC-V/gas: allow generating up to 176-bit instructions with .insn","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f5757acf-7b90-a0e3-5eea-3b97cc226930@suse.com/mbox/"},{"id":1596,"url":"https://patchwork.plctlab.org/api/1.2/patches/1596/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930140503.38233-1-chigot@adacore.com/","msgid":"<20220930140503.38233-1-chigot@adacore.com>","list_archive_url":null,"date":"2022-09-30T14:05:03","name":"ld/testsuite: consistently add board_ldflags when linking with GCC","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930140503.38233-1-chigot@adacore.com/mbox/"}],"public":true,"mbox":"https://patchwork.plctlab.org/bundle/patchwork-bot/binutils-gdb_2022-09/mbox/"},{"id":9,"url":"https://patchwork.plctlab.org/api/1.2/bundles/9/","web_url":"https://patchwork.plctlab.org/bundle/patchwork-bot/binutils-gdb_2022-11/","project":{"id":2,"url":"https://patchwork.plctlab.org/api/1.2/projects/2/","name":"binutils-gdb","link_name":"binutils-gdb","list_id":"binutils.sourceware.org","list_email":"binutils@sourceware.org","web_url":"https://github.com/wangliu-iscas/Patchwork-Bundles/blob/main/binutils-gdb.md","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"name":"binutils-gdb_2022-11","owner":{"id":3,"url":"https://patchwork.plctlab.org/api/1.2/users/3/","username":"patchwork-bot","first_name":"","last_name":"","email":"ouuuleilei@gmail.com"},"patches":[{"id":13337,"url":"https://patchwork.plctlab.org/api/1.2/patches/13337/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031160625.684434-1-hjl.tools@gmail.com/","msgid":"<20221031160625.684434-1-hjl.tools@gmail.com>","list_archive_url":null,"date":"2022-10-31T16:06:25","name":"x86: Silence GCC 12 warning on tc-i386.c","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031160625.684434-1-hjl.tools@gmail.com/mbox/"},{"id":13350,"url":"https://patchwork.plctlab.org/api/1.2/patches/13350/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c8d25b29-37fe-9623-a799-e67e1f991743@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-31T17:00:56","name":"x86: simplify expressions in update_imm()","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c8d25b29-37fe-9623-a799-e67e1f991743@suse.com/mbox/"},{"id":13487,"url":"https://patchwork.plctlab.org/api/1.2/patches/13487/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/CAMe9rOohVjin92PTeeiu_dvAtzYJn4dGtu5E=OxYfbyteraZWw@mail.gmail.com/","msgid":"","list_archive_url":null,"date":"2022-11-01T00:08:04","name":"binutils: Run PR binutils/26160 test","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/CAMe9rOohVjin92PTeeiu_dvAtzYJn4dGtu5E=OxYfbyteraZWw@mail.gmail.com/mbox/"},{"id":13621,"url":"https://patchwork.plctlab.org/api/1.2/patches/13621/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221101105724.1527333-1-aburgess@redhat.com/","msgid":"<20221101105724.1527333-1-aburgess@redhat.com>","list_archive_url":null,"date":"2022-11-01T10:57:24","name":"[PUSHED] opcodes/arm: silence compiler warning about uninitialized variable use","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221101105724.1527333-1-aburgess@redhat.com/mbox/"},{"id":13628,"url":"https://patchwork.plctlab.org/api/1.2/patches/13628/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221101111802.1532080-1-aburgess@redhat.com/","msgid":"<20221101111802.1532080-1-aburgess@redhat.com>","list_archive_url":null,"date":"2022-11-01T11:18:02","name":"[PUSHED] opcodes/arm: don'\''t pass non-string literal to printf like function","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221101111802.1532080-1-aburgess@redhat.com/mbox/"},{"id":13747,"url":"https://patchwork.plctlab.org/api/1.2/patches/13747/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/yw8jbkpqk6vw.fsf@arm.com/","msgid":"","list_archive_url":null,"date":"2022-11-01T15:54:11","name":"[Binutils-2.39,backport,GAS] arm: Use DWARF numbering convention for pseudo-register representation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/yw8jbkpqk6vw.fsf@arm.com/mbox/"},{"id":13993,"url":"https://patchwork.plctlab.org/api/1.2/patches/13993/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221102020752.24441-1-mark@harmstone.com/","msgid":"<20221102020752.24441-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-11-02T02:07:52","name":"ld: Add module information substream to PDB files","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221102020752.24441-1-mark@harmstone.com/mbox/"},{"id":14028,"url":"https://patchwork.plctlab.org/api/1.2/patches/14028/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221102050430.1053-1-nelson@rivosinc.com/","msgid":"<20221102050430.1053-1-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-11-02T05:04:30","name":"[committed] RISC-V: Fixed the missing $x+arch when adding odd paddings for alignment.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221102050430.1053-1-nelson@rivosinc.com/mbox/"},{"id":14043,"url":"https://patchwork.plctlab.org/api/1.2/patches/14043/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221102063046.31551-1-rjiejie@linux.alibaba.com/","msgid":"<20221102063046.31551-1-rjiejie@linux.alibaba.com>","list_archive_url":null,"date":"2022-11-02T06:30:46","name":"gas/doc/internals.texi: fix typo","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221102063046.31551-1-rjiejie@linux.alibaba.com/mbox/"},{"id":14069,"url":"https://patchwork.plctlab.org/api/1.2/patches/14069/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221102080112.33378-1-rjiejie@linux.alibaba.com/","msgid":"<20221102080112.33378-1-rjiejie@linux.alibaba.com>","list_archive_url":null,"date":"2022-11-02T08:01:12","name":"[v2] Support multiple .eh_frame sections","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221102080112.33378-1-rjiejie@linux.alibaba.com/mbox/"},{"id":14409,"url":"https://patchwork.plctlab.org/api/1.2/patches/14409/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221102172923.4009281-1-christophe.lyon@arm.com/","msgid":"<20221102172923.4009281-1-christophe.lyon@arm.com>","list_archive_url":null,"date":"2022-11-02T17:29:23","name":"arm: PR 29739 Fix typo where '\''; '\'' should not have been replaced with '\''@'\''","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221102172923.4009281-1-christophe.lyon@arm.com/mbox/"},{"id":14588,"url":"https://patchwork.plctlab.org/api/1.2/patches/14588/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221103020409.37322-1-rjiejie@linux.alibaba.com/","msgid":"<20221103020409.37322-1-rjiejie@linux.alibaba.com>","list_archive_url":null,"date":"2022-11-03T02:04:09","name":"[v3] Support multiple .eh_frame sections","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221103020409.37322-1-rjiejie@linux.alibaba.com/mbox/"},{"id":14602,"url":"https://patchwork.plctlab.org/api/1.2/patches/14602/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221103024604.614-1-mark@harmstone.com/","msgid":"<20221103024604.614-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-11-03T02:46:04","name":"[v2] ld: Add module information substream to PDB files","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221103024604.614-1-mark@harmstone.com/mbox/"},{"id":14706,"url":"https://patchwork.plctlab.org/api/1.2/patches/14706/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221103071519.3510462-1-luis.machado@arm.com/","msgid":"<20221103071519.3510462-1-luis.machado@arm.com>","list_archive_url":null,"date":"2022-11-03T07:15:19","name":"[opcodes/arm] Fix potential null pointer dereferences","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221103071519.3510462-1-luis.machado@arm.com/mbox/"},{"id":14840,"url":"https://patchwork.plctlab.org/api/1.2/patches/14840/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/283a86ebf0941f0f63dc1a590ec3d547bd5d69e8.1667478033.git.research_trasio@irq.a4lg.com/","msgid":"<283a86ebf0941f0f63dc1a590ec3d547bd5d69e8.1667478033.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-03T12:26:28","name":"[REVIEW,ONLY,1/2] NEAR-RATIFICATION RISC-V: Add '\''Ssstateen'\'' extension and its CSRs","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/283a86ebf0941f0f63dc1a590ec3d547bd5d69e8.1667478033.git.research_trasio@irq.a4lg.com/mbox/"},{"id":14841,"url":"https://patchwork.plctlab.org/api/1.2/patches/14841/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8083ad9d5339afdeb7f1ba88ee6af0665dcc76d5.1667478033.git.research_trasio@irq.a4lg.com/","msgid":"<8083ad9d5339afdeb7f1ba88ee6af0665dcc76d5.1667478033.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-03T12:26:29","name":"[REVIEW,ONLY,2/2] NEAR-RATIFICATION RISC-V: Add platform property/capability extensions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8083ad9d5339afdeb7f1ba88ee6af0665dcc76d5.1667478033.git.research_trasio@irq.a4lg.com/mbox/"},{"id":14894,"url":"https://patchwork.plctlab.org/api/1.2/patches/14894/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e53fbf5025e59fe6a3481b9c1fe37e4f6cf6e03d.1667483581.git.aburgess@redhat.com/","msgid":"","list_archive_url":null,"date":"2022-11-03T13:58:12","name":"[1/2] opcodes/mips: use .word/.short for undefined instructions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e53fbf5025e59fe6a3481b9c1fe37e4f6cf6e03d.1667483581.git.aburgess@redhat.com/mbox/"},{"id":14893,"url":"https://patchwork.plctlab.org/api/1.2/patches/14893/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ca81edb86580566b1641ad140eb2bed385160ab7.1667483581.git.aburgess@redhat.com/","msgid":"","list_archive_url":null,"date":"2022-11-03T13:58:13","name":"[2/2] libopcodes/mips: add support for disassembler styling","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ca81edb86580566b1641ad140eb2bed385160ab7.1667483581.git.aburgess@redhat.com/mbox/"},{"id":15465,"url":"https://patchwork.plctlab.org/api/1.2/patches/15465/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/926e5154-b40b-9df8-d770-a8bf7d40e40e@suse.com/","msgid":"<926e5154-b40b-9df8-d770-a8bf7d40e40e@suse.com>","list_archive_url":null,"date":"2022-11-04T10:50:38","name":"[v6,1/7] x86: constify parse_insn()'\''s input","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/926e5154-b40b-9df8-d770-a8bf7d40e40e@suse.com/mbox/"},{"id":15466,"url":"https://patchwork.plctlab.org/api/1.2/patches/15466/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/07ef67fd-752c-ad1f-b8cb-4eaec1f420fc@suse.com/","msgid":"<07ef67fd-752c-ad1f-b8cb-4eaec1f420fc@suse.com>","list_archive_url":null,"date":"2022-11-04T10:51:34","name":"[v6,2/7] x86: re-work insn/suffix recognition","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/07ef67fd-752c-ad1f-b8cb-4eaec1f420fc@suse.com/mbox/"},{"id":15467,"url":"https://patchwork.plctlab.org/api/1.2/patches/15467/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ee8fd655-19a5-d944-0f5e-4351b88a59f9@suse.com/","msgid":"","list_archive_url":null,"date":"2022-11-04T10:52:02","name":"[v6,3/7] ix86: don'\''t recognize/derive Q suffix in the common case","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ee8fd655-19a5-d944-0f5e-4351b88a59f9@suse.com/mbox/"},{"id":15468,"url":"https://patchwork.plctlab.org/api/1.2/patches/15468/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/15ab2cf5-f1ac-e882-c415-6318f1bcc7f0@suse.com/","msgid":"<15ab2cf5-f1ac-e882-c415-6318f1bcc7f0@suse.com>","list_archive_url":null,"date":"2022-11-04T10:52:31","name":"[v6,4/7] x86-64: allow HLE store of accumulator to absolute 32-bit address","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/15ab2cf5-f1ac-e882-c415-6318f1bcc7f0@suse.com/mbox/"},{"id":15470,"url":"https://patchwork.plctlab.org/api/1.2/patches/15470/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/352d1e49-ac9f-ee86-7e9d-74f79744268b@suse.com/","msgid":"<352d1e49-ac9f-ee86-7e9d-74f79744268b@suse.com>","list_archive_url":null,"date":"2022-11-04T10:53:14","name":"[v6,5/7] x86: move bad-use-of-TLS-reloc check","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/352d1e49-ac9f-ee86-7e9d-74f79744268b@suse.com/mbox/"},{"id":15469,"url":"https://patchwork.plctlab.org/api/1.2/patches/15469/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c1913bf6-7328-e45f-69f1-20da1954af43@suse.com/","msgid":"","list_archive_url":null,"date":"2022-11-04T10:53:52","name":"[v6,6/7] x86: drop (now) stray IsString","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c1913bf6-7328-e45f-69f1-20da1954af43@suse.com/mbox/"},{"id":15471,"url":"https://patchwork.plctlab.org/api/1.2/patches/15471/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2baf6a9d-c1bf-660d-bbca-99b1604f5478@suse.com/","msgid":"<2baf6a9d-c1bf-660d-bbca-99b1604f5478@suse.com>","list_archive_url":null,"date":"2022-11-04T10:54:30","name":"[v6,7/7] x86: further re-work insn/suffix recognition to also cover MOVSX","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2baf6a9d-c1bf-660d-bbca-99b1604f5478@suse.com/mbox/"},{"id":15472,"url":"https://patchwork.plctlab.org/api/1.2/patches/15472/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104110132.694984-1-aburgess@redhat.com/","msgid":"<20221104110132.694984-1-aburgess@redhat.com>","list_archive_url":null,"date":"2022-11-04T11:01:32","name":"[PUSHED] opcodes/arm: silence compiler warning about uninitialized variable use","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104110132.694984-1-aburgess@redhat.com/mbox/"},{"id":15473,"url":"https://patchwork.plctlab.org/api/1.2/patches/15473/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104110214.129095-1-christophe.lyon@arm.com/","msgid":"<20221104110214.129095-1-christophe.lyon@arm.com>","list_archive_url":null,"date":"2022-11-04T11:02:14","name":"configure: require libzstd >= 1.4.0","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104110214.129095-1-christophe.lyon@arm.com/mbox/"},{"id":15485,"url":"https://patchwork.plctlab.org/api/1.2/patches/15485/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104115038.8957-1-nelson@rivosinc.com/","msgid":"<20221104115038.8957-1-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-11-04T11:50:37","name":"[1/2] RISC-V: File-level architecture shouldn'\''t be affected by section-level ones.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104115038.8957-1-nelson@rivosinc.com/mbox/"},{"id":15486,"url":"https://patchwork.plctlab.org/api/1.2/patches/15486/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104115038.8957-2-nelson@rivosinc.com/","msgid":"<20221104115038.8957-2-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-11-04T11:50:38","name":"[2/2] RISC-V: Clarify the suppress rule of mapping symbol with architecture string.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104115038.8957-2-nelson@rivosinc.com/mbox/"},{"id":15509,"url":"https://patchwork.plctlab.org/api/1.2/patches/15509/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/cc133c88-9ce9-5e3a-a8f7-ad72766862b9@suse.com/","msgid":"","list_archive_url":null,"date":"2022-11-04T13:12:07","name":"x86: adjust recently introduced testcases","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/cc133c88-9ce9-5e3a-a8f7-ad72766862b9@suse.com/mbox/"},{"id":15679,"url":"https://patchwork.plctlab.org/api/1.2/patches/15679/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104163328.2274371-1-chigot@adacore.com/","msgid":"<20221104163328.2274371-1-chigot@adacore.com>","list_archive_url":null,"date":"2022-11-04T16:33:28","name":"ld/testsuite: skip tests related to -shared when disabled","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104163328.2274371-1-chigot@adacore.com/mbox/"},{"id":15751,"url":"https://patchwork.plctlab.org/api/1.2/patches/15751/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104190216.1352855-1-indu.bhagat@oracle.com/","msgid":"<20221104190216.1352855-1-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-04T19:02:16","name":"[V3.1,11/15] libctf: add libsframe to LDFLAGS and LIBS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104190216.1352855-1-indu.bhagat@oracle.com/mbox/"},{"id":15792,"url":"https://patchwork.plctlab.org/api/1.2/patches/15792/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104205547.3728827-1-hjl.tools@gmail.com/","msgid":"<20221104205547.3728827-1-hjl.tools@gmail.com>","list_archive_url":null,"date":"2022-11-04T20:55:47","name":"i386: Check invalid (%dx) usage","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104205547.3728827-1-hjl.tools@gmail.com/mbox/"},{"id":15794,"url":"https://patchwork.plctlab.org/api/1.2/patches/15794/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104210134.1721620-1-indu.bhagat@oracle.com/","msgid":"<20221104210134.1721620-1-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-04T21:01:34","name":"[V3.2,11/15] libctf: add libsframe to LDFLAGS and LIBS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104210134.1721620-1-indu.bhagat@oracle.com/mbox/"},{"id":15959,"url":"https://patchwork.plctlab.org/api/1.2/patches/15959/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c620070e3e335df2b487d3836e20d251dac37525.1667651354.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-11-05T12:29:07","name":"[01/12] RISC-V: Remove unnecessary empty matching file","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c620070e3e335df2b487d3836e20d251dac37525.1667651354.git.research_trasio@irq.a4lg.com/mbox/"},{"id":15961,"url":"https://patchwork.plctlab.org/api/1.2/patches/15961/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4496235002a396043598ab9755bd8eda5c077b1f.1667651354.git.research_trasio@irq.a4lg.com/","msgid":"<4496235002a396043598ab9755bd8eda5c077b1f.1667651354.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-05T12:29:08","name":"[02/12] RISC-V: Tidy disassembler corner case tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4496235002a396043598ab9755bd8eda5c077b1f.1667651354.git.research_trasio@irq.a4lg.com/mbox/"},{"id":15960,"url":"https://patchwork.plctlab.org/api/1.2/patches/15960/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a9229a2798480f00bf12ac3c435b3ef57f867022.1667651354.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-11-05T12:29:09","name":"[03/12] RISC-V: Tidying related to '\''Zfinx'\'' disassembler test","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a9229a2798480f00bf12ac3c435b3ef57f867022.1667651354.git.research_trasio@irq.a4lg.com/mbox/"},{"id":15962,"url":"https://patchwork.plctlab.org/api/1.2/patches/15962/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6a020edd0e114a003edbaafe1088a040e9fa07e7.1667651354.git.research_trasio@irq.a4lg.com/","msgid":"<6a020edd0e114a003edbaafe1088a040e9fa07e7.1667651354.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-05T12:29:10","name":"[04/12] RISC-V: GAS: Add basic shared test utilities","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6a020edd0e114a003edbaafe1088a040e9fa07e7.1667651354.git.research_trasio@irq.a4lg.com/mbox/"},{"id":15966,"url":"https://patchwork.plctlab.org/api/1.2/patches/15966/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6fc2851a4161edc429089bd2bbd9c2bb4c0c118f.1667651354.git.research_trasio@irq.a4lg.com/","msgid":"<6fc2851a4161edc429089bd2bbd9c2bb4c0c118f.1667651354.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-05T12:29:11","name":"[05/12] RISC-V: Redefine \"nop\" test","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6fc2851a4161edc429089bd2bbd9c2bb4c0c118f.1667651354.git.research_trasio@irq.a4lg.com/mbox/"},{"id":15963,"url":"https://patchwork.plctlab.org/api/1.2/patches/15963/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7311ed3d2429000e18877d7af594890da170a7a3.1667651354.git.research_trasio@irq.a4lg.com/","msgid":"<7311ed3d2429000e18877d7af594890da170a7a3.1667651354.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-05T12:29:12","name":"[06/12] RISC-V: Reorganize/enhance {sign, zero}-extension instructions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7311ed3d2429000e18877d7af594890da170a7a3.1667651354.git.research_trasio@irq.a4lg.com/mbox/"},{"id":15968,"url":"https://patchwork.plctlab.org/api/1.2/patches/15968/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ac99c9696c156207f06c18f2d6bf423c96c5876b.1667651354.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-11-05T12:29:13","name":"[07/12] RISC-V: Combine complex extension error handling tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ac99c9696c156207f06c18f2d6bf423c96c5876b.1667651354.git.research_trasio@irq.a4lg.com/mbox/"},{"id":15970,"url":"https://patchwork.plctlab.org/api/1.2/patches/15970/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9378b9505e3e230e0a690c56e67d253e2a0f5864.1667651354.git.research_trasio@irq.a4lg.com/","msgid":"<9378b9505e3e230e0a690c56e67d253e2a0f5864.1667651354.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-05T12:29:14","name":"[08/12] RISC-V: Refine/enhance '\''M'\''/'\''Zmmul'\'' extension tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9378b9505e3e230e0a690c56e67d253e2a0f5864.1667651354.git.research_trasio@irq.a4lg.com/mbox/"},{"id":15964,"url":"https://patchwork.plctlab.org/api/1.2/patches/15964/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/82832a67f240d5857fd502d4b74fd7d841ee2d6e.1667651354.git.research_trasio@irq.a4lg.com/","msgid":"<82832a67f240d5857fd502d4b74fd7d841ee2d6e.1667651354.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-05T12:29:15","name":"[09/12] RISC-V: Combine/enhance '\''Zicbo[mz]'\'' extension tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/82832a67f240d5857fd502d4b74fd7d841ee2d6e.1667651354.git.research_trasio@irq.a4lg.com/mbox/"},{"id":15965,"url":"https://patchwork.plctlab.org/api/1.2/patches/15965/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9c47e59868a64b13e5a7bb487e3619d4f1497d78.1667651354.git.research_trasio@irq.a4lg.com/","msgid":"<9c47e59868a64b13e5a7bb487e3619d4f1497d78.1667651354.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-05T12:29:16","name":"[10/12] RISC-V: Enhance '\''Zicbop'\'' testcases","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9c47e59868a64b13e5a7bb487e3619d4f1497d78.1667651354.git.research_trasio@irq.a4lg.com/mbox/"},{"id":15967,"url":"https://patchwork.plctlab.org/api/1.2/patches/15967/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2d9befc5bc5eed80b6bd7da6d092a61b1162ecac.1667651354.git.research_trasio@irq.a4lg.com/","msgid":"<2d9befc5bc5eed80b6bd7da6d092a61b1162ecac.1667651354.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-05T12:29:17","name":"[11/12] RISC-V: Reorganize/enhance '\''Zb*'\'' extension tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2d9befc5bc5eed80b6bd7da6d092a61b1162ecac.1667651354.git.research_trasio@irq.a4lg.com/mbox/"},{"id":15969,"url":"https://patchwork.plctlab.org/api/1.2/patches/15969/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f1c5589ab606b74eeac98e3dafd4a7903450d3b2.1667651354.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-11-05T12:29:18","name":"[12/12] RISC-V: Combine/enhance '\''Zk*'\''/'\''Zbk*'\'' extension tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f1c5589ab606b74eeac98e3dafd4a7903450d3b2.1667651354.git.research_trasio@irq.a4lg.com/mbox/"},{"id":16066,"url":"https://patchwork.plctlab.org/api/1.2/patches/16066/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221106053640.1649752-1-indu.bhagat@oracle.com/","msgid":"<20221106053640.1649752-1-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-06T05:36:40","name":"[V3.1,03/15] gas: generate .sframe from CFI directives","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221106053640.1649752-1-indu.bhagat@oracle.com/mbox/"},{"id":16379,"url":"https://patchwork.plctlab.org/api/1.2/patches/16379/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221107112805.3332619-1-och95@yandex.ru/","msgid":"<20221107112805.3332619-1-och95@yandex.ru>","list_archive_url":null,"date":"2022-11-07T11:28:05","name":"gold/aarch64: Fix adrp distance check","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221107112805.3332619-1-och95@yandex.ru/mbox/"},{"id":16400,"url":"https://patchwork.plctlab.org/api/1.2/patches/16400/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221107124620.1271470-1-christoph.muellner@vrull.eu/","msgid":"<20221107124620.1271470-1-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2022-11-07T12:46:20","name":"RISC-V: xtheadfmemidx: Use fp register in mnemonics","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221107124620.1271470-1-christoph.muellner@vrull.eu/mbox/"},{"id":16594,"url":"https://patchwork.plctlab.org/api/1.2/patches/16594/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/CACVBkZ+kM2xcpwk5zHQ4bqDV7dbPjZ6cMU9tR-h62+tDTgi3Tw@mail.gmail.com/","msgid":"","list_archive_url":null,"date":"2022-11-07T17:53:35","name":"GAS fix section alignment for aarch64-pe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/CACVBkZ+kM2xcpwk5zHQ4bqDV7dbPjZ6cMU9tR-h62+tDTgi3Tw@mail.gmail.com/mbox/"},{"id":16744,"url":"https://patchwork.plctlab.org/api/1.2/patches/16744/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221107222809.924195-1-indu.bhagat@oracle.com/","msgid":"<20221107222809.924195-1-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-07T22:28:09","name":"[V3.3,11/15] libctf: add libsframe to LDFLAGS and LIBS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221107222809.924195-1-indu.bhagat@oracle.com/mbox/"},{"id":16797,"url":"https://patchwork.plctlab.org/api/1.2/patches/16797/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221108012556.66467-1-haochen.jiang@intel.com/","msgid":"<20221108012556.66467-1-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-11-08T01:25:56","name":"x86: Correct wrong comments in vex_w_table","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221108012556.66467-1-haochen.jiang@intel.com/mbox/"},{"id":16884,"url":"https://patchwork.plctlab.org/api/1.2/patches/16884/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221108054530.796968-1-markus.t.metzger@intel.com/","msgid":"<20221108054530.796968-1-markus.t.metzger@intel.com>","list_archive_url":null,"date":"2022-11-08T05:45:29","name":"[1/2] gprofng: make cpu identification available to others","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221108054530.796968-1-markus.t.metzger@intel.com/mbox/"},{"id":16885,"url":"https://patchwork.plctlab.org/api/1.2/patches/16885/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221108054530.796968-2-markus.t.metzger@intel.com/","msgid":"<20221108054530.796968-2-markus.t.metzger@intel.com>","list_archive_url":null,"date":"2022-11-08T05:45:30","name":"[2/2] gdb, btrace: use cpuident.h to implement btrace_this_cpu","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221108054530.796968-2-markus.t.metzger@intel.com/mbox/"},{"id":16995,"url":"https://patchwork.plctlab.org/api/1.2/patches/16995/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ea0daf08-4923-ebfa-dcfe-699c43d63822@suse.com/","msgid":"","list_archive_url":null,"date":"2022-11-08T11:29:40","name":"x86/Intel: don'\''t accept malformed EXTRQ / INSERTQ","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ea0daf08-4923-ebfa-dcfe-699c43d63822@suse.com/mbox/"},{"id":17057,"url":"https://patchwork.plctlab.org/api/1.2/patches/17057/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221108141352.6613-1-jwilk@jwilk.net/","msgid":"<20221108141352.6613-1-jwilk@jwilk.net>","list_archive_url":null,"date":"2022-11-08T14:13:52","name":"Fix typos in the list of objdump options","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221108141352.6613-1-jwilk@jwilk.net/mbox/"},{"id":17117,"url":"https://patchwork.plctlab.org/api/1.2/patches/17117/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1667924955-9218-1-git-send-email-apinski@marvell.com/","msgid":"<1667924955-9218-1-git-send-email-apinski@marvell.com>","list_archive_url":null,"date":"2022-11-08T16:29:15","name":"Use toplevel configure for GMP and MPFR for gdb","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1667924955-9218-1-git-send-email-apinski@marvell.com/mbox/"},{"id":17160,"url":"https://patchwork.plctlab.org/api/1.2/patches/17160/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/27382086-397f-060f-6cf6-c1d36ff6b812@linux.ibm.com/","msgid":"<27382086-397f-060f-6cf6-c1d36ff6b812@linux.ibm.com>","list_archive_url":null,"date":"2022-11-08T18:23:32","name":"[COMMITTED] PowerPC: Add XSP operand define","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/27382086-397f-060f-6cf6-c1d36ff6b812@linux.ibm.com/mbox/"},{"id":17202,"url":"https://patchwork.plctlab.org/api/1.2/patches/17202/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221108192248.1622627-1-indu.bhagat@oracle.com/","msgid":"<20221108192248.1622627-1-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-08T19:22:48","name":"libctf: use libtool for link test in configure","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221108192248.1622627-1-indu.bhagat@oracle.com/mbox/"},{"id":17262,"url":"https://patchwork.plctlab.org/api/1.2/patches/17262/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221108225030.371817-1-hjl.tools@gmail.com/","msgid":"<20221108225030.371817-1-hjl.tools@gmail.com>","list_archive_url":null,"date":"2022-11-08T22:50:30","name":"ld: Always output local symbol for relocatable link","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221108225030.371817-1-hjl.tools@gmail.com/mbox/"},{"id":17399,"url":"https://patchwork.plctlab.org/api/1.2/patches/17399/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-2-indu.bhagat@oracle.com/","msgid":"<20221109084244.261296-2-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-09T08:42:34","name":"[V4,01/11] sframe.h: Add SFrame format definition","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-2-indu.bhagat@oracle.com/mbox/"},{"id":17398,"url":"https://patchwork.plctlab.org/api/1.2/patches/17398/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-3-indu.bhagat@oracle.com/","msgid":"<20221109084244.261296-3-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-09T08:42:35","name":"[V4,02/11] gas: add new command line option --gsframe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-3-indu.bhagat@oracle.com/mbox/"},{"id":17400,"url":"https://patchwork.plctlab.org/api/1.2/patches/17400/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-4-indu.bhagat@oracle.com/","msgid":"<20221109084244.261296-4-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-09T08:42:36","name":"[V4,03/11] gas: generate .sframe from CFI directives","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-4-indu.bhagat@oracle.com/mbox/"},{"id":17403,"url":"https://patchwork.plctlab.org/api/1.2/patches/17403/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-5-indu.bhagat@oracle.com/","msgid":"<20221109084244.261296-5-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-09T08:42:37","name":"[V4,04/11] gas: testsuite: add new tests for SFrame unwind info","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-5-indu.bhagat@oracle.com/mbox/"},{"id":17407,"url":"https://patchwork.plctlab.org/api/1.2/patches/17407/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-6-indu.bhagat@oracle.com/","msgid":"<20221109084244.261296-6-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-09T08:42:38","name":"[V4,05/11] libsframe: add the SFrame library","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-6-indu.bhagat@oracle.com/mbox/"},{"id":17406,"url":"https://patchwork.plctlab.org/api/1.2/patches/17406/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-7-indu.bhagat@oracle.com/","msgid":"<20221109084244.261296-7-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-09T08:42:39","name":"[V4,06/11] bfd: linker: merge .sframe sections","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-7-indu.bhagat@oracle.com/mbox/"},{"id":17402,"url":"https://patchwork.plctlab.org/api/1.2/patches/17402/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-8-indu.bhagat@oracle.com/","msgid":"<20221109084244.261296-8-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-09T08:42:40","name":"[V4,07/11] readelf/objdump: support for SFrame section","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-8-indu.bhagat@oracle.com/mbox/"},{"id":17401,"url":"https://patchwork.plctlab.org/api/1.2/patches/17401/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-9-indu.bhagat@oracle.com/","msgid":"<20221109084244.261296-9-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-09T08:42:41","name":"[V4,08/11] src-release.sh: Add libsframe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-9-indu.bhagat@oracle.com/mbox/"},{"id":17404,"url":"https://patchwork.plctlab.org/api/1.2/patches/17404/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-10-indu.bhagat@oracle.com/","msgid":"<20221109084244.261296-10-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-09T08:42:42","name":"[V4,09/11] binutils/NEWS: add text for SFrame support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-10-indu.bhagat@oracle.com/mbox/"},{"id":17405,"url":"https://patchwork.plctlab.org/api/1.2/patches/17405/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-11-indu.bhagat@oracle.com/","msgid":"<20221109084244.261296-11-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-09T08:42:43","name":"[V4,10/11] gas/NEWS: add text about new command line option and SFrame support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-11-indu.bhagat@oracle.com/mbox/"}],"public":true,"mbox":"https://patchwork.plctlab.org/bundle/patchwork-bot/binutils-gdb_2022-11/mbox/"}]' + bundle_name_list='binutils-gdb_2022-10 binutils-gdb_2022-09 binutils-gdb_2022-11' + [[ binutils-gdb_2022-10 binutils-gdb_2022-09 binutils-gdb_2022-11 =~ 2022-11 ]] ++ jq -rc --arg bundle_name binutils-gdb_2022-11 '.[] | select(.name==$bundle_name) | (.id|tostring)' ++ echo '[{"id":6,"url":"https://patchwork.plctlab.org/api/1.2/bundles/6/","web_url":"https://patchwork.plctlab.org/bundle/patchwork-bot/binutils-gdb_2022-10/","project":{"id":2,"url":"https://patchwork.plctlab.org/api/1.2/projects/2/","name":"binutils-gdb","link_name":"binutils-gdb","list_id":"binutils.sourceware.org","list_email":"binutils@sourceware.org","web_url":"https://github.com/wangliu-iscas/Patchwork-Bundles/blob/main/binutils-gdb.md","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"name":"binutils-gdb_2022-10","owner":{"id":3,"url":"https://patchwork.plctlab.org/api/1.2/users/3/","username":"patchwork-bot","first_name":"","last_name":"","email":"ouuuleilei@gmail.com"},"patches":[{"id":1592,"url":"https://patchwork.plctlab.org/api/1.2/patches/1592/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/385d01fd-7e57-1f3f-1bae-30aa0c313d63@suse.com/","msgid":"<385d01fd-7e57-1f3f-1bae-30aa0c313d63@suse.com>","list_archive_url":null,"date":"2022-09-30T11:59:45","name":"[3/4] RISC-V/gas: don'\''t open-code insn_length()","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/385d01fd-7e57-1f3f-1bae-30aa0c313d63@suse.com/mbox/"},{"id":1594,"url":"https://patchwork.plctlab.org/api/1.2/patches/1594/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f5757acf-7b90-a0e3-5eea-3b97cc226930@suse.com/","msgid":"","list_archive_url":null,"date":"2022-09-30T12:00:12","name":"[4/4] RISC-V/gas: allow generating up to 176-bit instructions with .insn","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f5757acf-7b90-a0e3-5eea-3b97cc226930@suse.com/mbox/"},{"id":1596,"url":"https://patchwork.plctlab.org/api/1.2/patches/1596/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930140503.38233-1-chigot@adacore.com/","msgid":"<20220930140503.38233-1-chigot@adacore.com>","list_archive_url":null,"date":"2022-09-30T14:05:03","name":"ld/testsuite: consistently add board_ldflags when linking with GCC","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930140503.38233-1-chigot@adacore.com/mbox/"},{"id":1619,"url":"https://patchwork.plctlab.org/api/1.2/patches/1619/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221001014451.532772-1-maskray@google.com/","msgid":"<20221001014451.532772-1-maskray@google.com>","list_archive_url":null,"date":"2022-10-01T01:44:51","name":"gold, dwp: support zstd compressed input debug sections [PR 29641]","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221001014451.532772-1-maskray@google.com/mbox/"},{"id":1620,"url":"https://patchwork.plctlab.org/api/1.2/patches/1620/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221001023846.590825-1-maskray@google.com/","msgid":"<20221001023846.590825-1-maskray@google.com>","list_archive_url":null,"date":"2022-10-01T02:38:46","name":"gold: add --compress-debug-sections=zstd [PR 29641]","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221001023846.590825-1-maskray@google.com/mbox/"},{"id":1623,"url":"https://patchwork.plctlab.org/api/1.2/patches/1623/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b4477c7f666bdeb7f8e998633c7b0cb62310b9ef.1664599545.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-01T04:45:52","name":"[RFC,1/1] RISC-V: Implement common register pair framework","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b4477c7f666bdeb7f8e998633c7b0cb62310b9ef.1664599545.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1625,"url":"https://patchwork.plctlab.org/api/1.2/patches/1625/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/53a265a1f14d17a6f7b106082f610994c5d546e0.1664602025.git.research_trasio@irq.a4lg.com/","msgid":"<53a265a1f14d17a6f7b106082f610994c5d546e0.1664602025.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-01T05:27:31","name":"[RFC,1/1] RISC-V: Implement extension variants","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/53a265a1f14d17a6f7b106082f610994c5d546e0.1664602025.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1626,"url":"https://patchwork.plctlab.org/api/1.2/patches/1626/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8db04962aba9c780f133840a8934353a58f223fe.1664602716.git.research_trasio@irq.a4lg.com/","msgid":"<8db04962aba9c780f133840a8934353a58f223fe.1664602716.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-01T05:39:26","name":"[1/1] RISC-V: Move supervisor instructions after all unprivileged ones","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8db04962aba9c780f133840a8934353a58f223fe.1664602716.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1627,"url":"https://patchwork.plctlab.org/api/1.2/patches/1627/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221001062057.681440-1-maskray@google.com/","msgid":"<20221001062057.681440-1-maskray@google.com>","list_archive_url":null,"date":"2022-10-01T06:20:57","name":"readelf: support zstd compressed debug sections [PR 29640]","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221001062057.681440-1-maskray@google.com/mbox/"},{"id":1631,"url":"https://patchwork.plctlab.org/api/1.2/patches/1631/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/619f112539c0bdecd58e25664f1250a3479a37f5.1664707612.git.aburgess@redhat.com/","msgid":"<619f112539c0bdecd58e25664f1250a3479a37f5.1664707612.git.aburgess@redhat.com>","list_archive_url":null,"date":"2022-10-02T10:47:52","name":"[PATCHv2,2/2] opcodes/arm: add disassembler styling for arm","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/619f112539c0bdecd58e25664f1250a3479a37f5.1664707612.git.aburgess@redhat.com/mbox/"},{"id":1635,"url":"https://patchwork.plctlab.org/api/1.2/patches/1635/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221002185433.gl7dvytfh5wthifx@lug-owl.de/","msgid":"<20221002185433.gl7dvytfh5wthifx@lug-owl.de>","list_archive_url":null,"date":"2022-10-02T18:54:33","name":"diagnostics.h: GCC 13 got -Wself-move, breaks GDB build","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221002185433.gl7dvytfh5wthifx@lug-owl.de/mbox/"},{"id":1637,"url":"https://patchwork.plctlab.org/api/1.2/patches/1637/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003014313.28766-1-mark@harmstone.com/","msgid":"<20221003014313.28766-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-03T01:43:12","name":"[1/2] ld: Add --pdb option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003014313.28766-1-mark@harmstone.com/mbox/"},{"id":1638,"url":"https://patchwork.plctlab.org/api/1.2/patches/1638/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003014313.28766-2-mark@harmstone.com/","msgid":"<20221003014313.28766-2-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-03T01:43:13","name":"[2/2] ld: Add minimal pdb generation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003014313.28766-2-mark@harmstone.com/mbox/"},{"id":1640,"url":"https://patchwork.plctlab.org/api/1.2/patches/1640/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/597ed978-d121-220c-b56b-2ffb94bd091c@suse.cz/","msgid":"<597ed978-d121-220c-b56b-2ffb94bd091c@suse.cz>","list_archive_url":null,"date":"2022-10-03T07:50:38","name":"[1/2] refactor usage of compressed_debug_section_type","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/597ed978-d121-220c-b56b-2ffb94bd091c@suse.cz/mbox/"},{"id":1641,"url":"https://patchwork.plctlab.org/api/1.2/patches/1641/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b8acdd83-f33a-74b8-e21a-23719a0b1a60@suse.cz/","msgid":"","list_archive_url":null,"date":"2022-10-03T07:50:44","name":"[2/2] add --enable-default-compressed-debug-sections-algorithm configure option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b8acdd83-f33a-74b8-e21a-23719a0b1a60@suse.cz/mbox/"},{"id":1642,"url":"https://patchwork.plctlab.org/api/1.2/patches/1642/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003101328.1790113-1-aburgess@redhat.com/","msgid":"<20221003101328.1790113-1-aburgess@redhat.com>","list_archive_url":null,"date":"2022-10-03T10:13:28","name":"opcodes/riscv: style csr names as registers","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003101328.1790113-1-aburgess@redhat.com/mbox/"},{"id":1643,"url":"https://patchwork.plctlab.org/api/1.2/patches/1643/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7ba14fc4472ce97d4f7a4433cad8a571e89f82f4.1664793840.git.research_trasio@irq.a4lg.com/","msgid":"<7ba14fc4472ce97d4f7a4433cad8a571e89f82f4.1664793840.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-03T10:43:59","name":"[v3,1/6] RISC-V: Fix immediates to have \"immediate\" style","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7ba14fc4472ce97d4f7a4433cad8a571e89f82f4.1664793840.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1644,"url":"https://patchwork.plctlab.org/api/1.2/patches/1644/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a498bec37c1fd1dcda57cbf95e5f8cfba09b31d3.1664793840.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-03T10:44:00","name":"[v3,2/6] RISC-V: Fix printf argument types corresponding %x","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a498bec37c1fd1dcda57cbf95e5f8cfba09b31d3.1664793840.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1647,"url":"https://patchwork.plctlab.org/api/1.2/patches/1647/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0002ea716713ace4998a33dde0b81f4f890d10bf.1664793840.git.research_trasio@irq.a4lg.com/","msgid":"<0002ea716713ace4998a33dde0b81f4f890d10bf.1664793840.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-03T10:44:01","name":"[v3,3/6] RISC-V: Optimize riscv_disassemble_data printf","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0002ea716713ace4998a33dde0b81f4f890d10bf.1664793840.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1646,"url":"https://patchwork.plctlab.org/api/1.2/patches/1646/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c65fc3e9aa58965d6768a28c9fd7467fea9897a5.1664793840.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-03T10:44:02","name":"[v3,4/6] RISC-V: Print comma and tabs as the \"text\" style","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c65fc3e9aa58965d6768a28c9fd7467fea9897a5.1664793840.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1648,"url":"https://patchwork.plctlab.org/api/1.2/patches/1648/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5abe1d8a7694417b990e11d8f6cd6789573872e5.1664793840.git.research_trasio@irq.a4lg.com/","msgid":"<5abe1d8a7694417b990e11d8f6cd6789573872e5.1664793840.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-03T10:44:03","name":"[v3,5/6] RISC-V: Fix T-Head immediate types on printing","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5abe1d8a7694417b990e11d8f6cd6789573872e5.1664793840.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1649,"url":"https://patchwork.plctlab.org/api/1.2/patches/1649/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0b68af932117258c908db62cf87c3a15d3cdec41.1664793840.git.research_trasio@irq.a4lg.com/","msgid":"<0b68af932117258c908db62cf87c3a15d3cdec41.1664793840.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-03T10:44:04","name":"[v3,6/6] RISC-V: Print XTheadMemPair literal as \"immediate\"","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0b68af932117258c908db62cf87c3a15d3cdec41.1664793840.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1656,"url":"https://patchwork.plctlab.org/api/1.2/patches/1656/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/87lepxcd6x.fsf@redhat.com/","msgid":"<87lepxcd6x.fsf@redhat.com>","list_archive_url":null,"date":"2022-10-03T12:19:02","name":"Commit: readelf: Do not load section data from offset 0","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/87lepxcd6x.fsf@redhat.com/mbox/"},{"id":1659,"url":"https://patchwork.plctlab.org/api/1.2/patches/1659/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e0d369d419da9c0441f415da7f54352aead8f655.1664707612.git.aburgess@redhat.com/","msgid":"","list_archive_url":null,"date":"2022-10-03T16:37:36","name":"[PATCHv2,1/2] opcodes/arm: use '\''@'\'' consistently for the comment character","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e0d369d419da9c0441f415da7f54352aead8f655.1664707612.git.aburgess@redhat.com/mbox/"},{"id":1660,"url":"https://patchwork.plctlab.org/api/1.2/patches/1660/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003165848.11142-1-palmer@rivosinc.com/","msgid":"<20221003165848.11142-1-palmer@rivosinc.com>","list_archive_url":null,"date":"2022-10-03T16:58:48","name":"gas: NEWS: Mention the T-Head extensions that were recently added","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003165848.11142-1-palmer@rivosinc.com/mbox/"},{"id":1671,"url":"https://patchwork.plctlab.org/api/1.2/patches/1671/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/YzvrMEdkXjIn5Lfz@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-04T08:13:36","name":"Support objcopy changing compression to or from zstd","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/YzvrMEdkXjIn5Lfz@squeak.grove.modra.org/mbox/"},{"id":1673,"url":"https://patchwork.plctlab.org/api/1.2/patches/1673/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0bc857d306bb7c8130e5328dbe6b9ed2fed3ef87.1664873933.git.research_trasio@irq.a4lg.com/","msgid":"<0bc857d306bb7c8130e5328dbe6b9ed2fed3ef87.1664873933.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-04T08:59:07","name":"[1/2] RISC-V: Fix buffer overflow on print_insn_riscv","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0bc857d306bb7c8130e5328dbe6b9ed2fed3ef87.1664873933.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1672,"url":"https://patchwork.plctlab.org/api/1.2/patches/1672/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/89612fe01d902007bf84a7dfb0df5f85d5c166e4.1664873933.git.research_trasio@irq.a4lg.com/","msgid":"<89612fe01d902007bf84a7dfb0df5f85d5c166e4.1664873933.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-04T08:59:08","name":"[2/2] gdb/riscv: Fix buffer overflow on riscv_insn::fetch_instruction","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/89612fe01d902007bf84a7dfb0df5f85d5c166e4.1664873933.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1676,"url":"https://patchwork.plctlab.org/api/1.2/patches/1676/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fc849c94f4adcac1c4ccc5508c7a145a2f13b2a9.1664876744.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-04T09:45:49","name":"[v2,1/2] RISC-V: Fix buffer overflow on print_insn_riscv","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fc849c94f4adcac1c4ccc5508c7a145a2f13b2a9.1664876744.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1677,"url":"https://patchwork.plctlab.org/api/1.2/patches/1677/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4eb6e59ae2e790dbbf2bc92477edd281648d8814.1664876744.git.research_trasio@irq.a4lg.com/","msgid":"<4eb6e59ae2e790dbbf2bc92477edd281648d8814.1664876744.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-04T09:45:50","name":"[v2,2/2] gdb/riscv: Partial support for instructions up to 176-bits","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4eb6e59ae2e790dbbf2bc92477edd281648d8814.1664876744.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1678,"url":"https://patchwork.plctlab.org/api/1.2/patches/1678/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ebf16f9e1f45115d0793952ccb4a94d4233303f9.1664882725.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-04T11:25:56","name":"[v3,1/2] RISC-V: Fix buffer overflow on print_insn_riscv","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ebf16f9e1f45115d0793952ccb4a94d4233303f9.1664882725.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1679,"url":"https://patchwork.plctlab.org/api/1.2/patches/1679/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/83464b09b8649525259c69c853dfa2c9575a204b.1664882725.git.research_trasio@irq.a4lg.com/","msgid":"<83464b09b8649525259c69c853dfa2c9575a204b.1664882725.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-04T11:25:57","name":"[v3,2/2] gdb/riscv: Partial support for instructions up to 176-bit","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/83464b09b8649525259c69c853dfa2c9575a204b.1664882725.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1681,"url":"https://patchwork.plctlab.org/api/1.2/patches/1681/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ffa9c1d7-e8c2-a62b-ef3e-b565c0ffbe5b@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-04T13:56:27","name":"RISC-V: Zicbo{m,p,z} adjustments to riscv_multi_subset_supports_ext()","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ffa9c1d7-e8c2-a62b-ef3e-b565c0ffbe5b@suse.com/mbox/"},{"id":1690,"url":"https://patchwork.plctlab.org/api/1.2/patches/1690/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221004161720.1963953-1-vladimir.mezentsev@oracle.com/","msgid":"<20221004161720.1963953-1-vladimir.mezentsev@oracle.com>","list_archive_url":null,"date":"2022-10-04T16:17:20","name":"gprofng: fix build with --enable-pgo-build=lto","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221004161720.1963953-1-vladimir.mezentsev@oracle.com/mbox/"},{"id":1691,"url":"https://patchwork.plctlab.org/api/1.2/patches/1691/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c0211bc9c57be6c79c6d878ce147f63b657f461d.camel@espressif.com/","msgid":"","list_archive_url":null,"date":"2022-10-04T16:22:05","name":"bfd: xtensa: fix __stop_SECTION literal drop,","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c0211bc9c57be6c79c6d878ce147f63b657f461d.camel@espressif.com/mbox/"},{"id":1702,"url":"https://patchwork.plctlab.org/api/1.2/patches/1702/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5f482299-6c60-b2b3-9abe-f4a55a5a26c5@univ-grenoble-alpes.fr/","msgid":"<5f482299-6c60-b2b3-9abe-f4a55a5a26c5@univ-grenoble-alpes.fr>","list_archive_url":null,"date":"2022-10-04T20:03:20","name":"[RFC] bfd: use bfd_vma for the 64-bit version of put[lb] and get[lb]","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5f482299-6c60-b2b3-9abe-f4a55a5a26c5@univ-grenoble-alpes.fr/mbox/"},{"id":1711,"url":"https://patchwork.plctlab.org/api/1.2/patches/1711/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Yz0Gsxdxe0TePbJT@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-05T04:23:15","name":"PR29647, objdump -S looping","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Yz0Gsxdxe0TePbJT@squeak.grove.modra.org/mbox/"},{"id":1712,"url":"https://patchwork.plctlab.org/api/1.2/patches/1712/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/02d747d2-f57b-0fb5-b893-842b6cc41f2f@suse.com/","msgid":"<02d747d2-f57b-0fb5-b893-842b6cc41f2f@suse.com>","list_archive_url":null,"date":"2022-10-05T07:20:47","name":"[v3,1/7] x86: constify parse_insn()'\''s input","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/02d747d2-f57b-0fb5-b893-842b6cc41f2f@suse.com/mbox/"},{"id":1713,"url":"https://patchwork.plctlab.org/api/1.2/patches/1713/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/925cb740-4e1b-abc4-8526-aaab6faae5e1@suse.com/","msgid":"<925cb740-4e1b-abc4-8526-aaab6faae5e1@suse.com>","list_archive_url":null,"date":"2022-10-05T07:22:19","name":"[v3,2/7] x86: introduce Pass2 insn attribute","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/925cb740-4e1b-abc4-8526-aaab6faae5e1@suse.com/mbox/"},{"id":1714,"url":"https://patchwork.plctlab.org/api/1.2/patches/1714/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e16d3e78-39ca-f715-508f-a4104b8ab9a9@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-05T07:23:51","name":"[v3,3/7] x86: re-work insn/suffix recognition","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e16d3e78-39ca-f715-508f-a4104b8ab9a9@suse.com/mbox/"},{"id":1715,"url":"https://patchwork.plctlab.org/api/1.2/patches/1715/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e4e4b80b-794c-7485-1997-685adab8fb27@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-05T07:24:20","name":"[v3,4/7] x86-64: further re-work insn/suffix recognition to also cover MOVSL","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e4e4b80b-794c-7485-1997-685adab8fb27@suse.com/mbox/"},{"id":1716,"url":"https://patchwork.plctlab.org/api/1.2/patches/1716/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/540678fc-8bff-ec68-c97c-478d2631998c@suse.com/","msgid":"<540678fc-8bff-ec68-c97c-478d2631998c@suse.com>","list_archive_url":null,"date":"2022-10-05T07:24:55","name":"[v3,5/7] ix86: don'\''t recognize/derive Q suffix in the common case","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/540678fc-8bff-ec68-c97c-478d2631998c@suse.com/mbox/"},{"id":1718,"url":"https://patchwork.plctlab.org/api/1.2/patches/1718/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e4692495-7d3d-074d-14f9-364d4a9a998c@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-05T07:25:25","name":"[v3,6/7] x86-64: allow HLE store of accumulator to absolute 32-bit address","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e4692495-7d3d-074d-14f9-364d4a9a998c@suse.com/mbox/"},{"id":1717,"url":"https://patchwork.plctlab.org/api/1.2/patches/1717/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e8014ebd-d16b-17a7-9f34-3700fc164136@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-05T07:25:57","name":"[v3,7/7] x86: move bad-use-of-TLS-reloc check","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e8014ebd-d16b-17a7-9f34-3700fc164136@suse.com/mbox/"},{"id":1719,"url":"https://patchwork.plctlab.org/api/1.2/patches/1719/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1266f001-4511-2662-dba9-14b4d0317c57@suse.com/","msgid":"<1266f001-4511-2662-dba9-14b4d0317c57@suse.com>","list_archive_url":null,"date":"2022-10-05T07:40:50","name":"x86: drop \"regmask\" static variable","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1266f001-4511-2662-dba9-14b4d0317c57@suse.com/mbox/"},{"id":1751,"url":"https://patchwork.plctlab.org/api/1.2/patches/1751/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/af45c5d57c221e43101c2aa38b14f4b4ac12d011.1665031170.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-06T04:40:15","name":"[v2,1/2] RISC-V: Fallback for instructions longer than 64b","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/af45c5d57c221e43101c2aa38b14f4b4ac12d011.1665031170.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1752,"url":"https://patchwork.plctlab.org/api/1.2/patches/1752/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c6e55781245dd3e8e9b8debd6130fc5449dfbd55.1665031170.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-06T04:40:16","name":"[v2,2/2] RISC-V: Improve \"bits undefined\" diagnostics","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c6e55781245dd3e8e9b8debd6130fc5449dfbd55.1665031170.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1776,"url":"https://patchwork.plctlab.org/api/1.2/patches/1776/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d52952119e15357c0e823f8a2398999359588b4d.1665050099.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-06T09:56:30","name":"[v3,1/2] RISC-V: Fallback for instructions longer than 64b","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d52952119e15357c0e823f8a2398999359588b4d.1665050099.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1777,"url":"https://patchwork.plctlab.org/api/1.2/patches/1777/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d907b1997f60ff7823c4a23e281ec9d8ddcbf3f1.1665050099.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-06T09:56:31","name":"[v3,2/2] RISC-V: Improve \"bits undefined\" diagnostics","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d907b1997f60ff7823c4a23e281ec9d8ddcbf3f1.1665050099.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1781,"url":"https://patchwork.plctlab.org/api/1.2/patches/1781/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221006114628.304185-1-chigot@adacore.com/","msgid":"<20221006114628.304185-1-chigot@adacore.com>","list_archive_url":null,"date":"2022-10-06T11:46:28","name":"RISC-V: fix linker message when relaxation deletes bytes","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221006114628.304185-1-chigot@adacore.com/mbox/"},{"id":1801,"url":"https://patchwork.plctlab.org/api/1.2/patches/1801/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Yz+Yhyg7UewC9/kp@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-07T03:09:59","name":"PR29653, objcopy/strip: fuzzed small input file induces large output file","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Yz+Yhyg7UewC9/kp@squeak.grove.modra.org/mbox/"},{"id":1803,"url":"https://patchwork.plctlab.org/api/1.2/patches/1803/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/PH1P110MB16505D9D39EC5B1DE22FE3D5EC5F9@PH1P110MB1650.NAMP110.PROD.OUTLOOK.COM/","msgid":"","list_archive_url":null,"date":"2022-10-07T04:10:07","name":"@CPP_FOR_BUILD@ problem since binutils-2.38","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/PH1P110MB16505D9D39EC5B1DE22FE3D5EC5F9@PH1P110MB1650.NAMP110.PROD.OUTLOOK.COM/mbox/"},{"id":1827,"url":"https://patchwork.plctlab.org/api/1.2/patches/1827/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8e13bce108ac10a0c1dd911e23ec572926f7ae44.1665203374.git.research_trasio@irq.a4lg.com/","msgid":"<8e13bce108ac10a0c1dd911e23ec572926f7ae44.1665203374.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-08T04:29:53","name":"[v2,1/1] RISC-V: Test DWARF register numbers for \"fp\"","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8e13bce108ac10a0c1dd911e23ec572926f7ae44.1665203374.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1828,"url":"https://patchwork.plctlab.org/api/1.2/patches/1828/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0883001b3572e54d3fba264429c7ade2adb66610.1665203441.git.research_trasio@irq.a4lg.com/","msgid":"<0883001b3572e54d3fba264429c7ade2adb66610.1665203441.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-08T04:31:15","name":"[1/1] RISC-V: Move standard hints before all instructions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0883001b3572e54d3fba264429c7ade2adb66610.1665203441.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1829,"url":"https://patchwork.plctlab.org/api/1.2/patches/1829/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/58e16a241d7376fcae2515c6bd5a2b41d275eeba.1665203531.git.research_trasio@irq.a4lg.com/","msgid":"<58e16a241d7376fcae2515c6bd5a2b41d275eeba.1665203531.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-08T04:32:18","name":"[RFC,1/1] RISC-V: Imply '\''Zicsr'\'' from privileged extensions with CSRs","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/58e16a241d7376fcae2515c6bd5a2b41d275eeba.1665203531.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1830,"url":"https://patchwork.plctlab.org/api/1.2/patches/1830/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/cb5076fc96e8f2097779a3abcde843dcdd660031.1665203660.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-08T04:34:23","name":"[1/5] opcodes/riscv-dis.c: Tidying with comments/clarity","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/cb5076fc96e8f2097779a3abcde843dcdd660031.1665203660.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1832,"url":"https://patchwork.plctlab.org/api/1.2/patches/1832/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1f1aa0838bf9c4f10a45fcfe3c682f7efc79d9ae.1665203660.git.research_trasio@irq.a4lg.com/","msgid":"<1f1aa0838bf9c4f10a45fcfe3c682f7efc79d9ae.1665203660.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-08T04:34:24","name":"[2/5] opcodes/riscv-dis.c: Tidying with spacing","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1f1aa0838bf9c4f10a45fcfe3c682f7efc79d9ae.1665203660.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1831,"url":"https://patchwork.plctlab.org/api/1.2/patches/1831/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/740bc5e2d2618d236519b39fedd1a1d7ae4e05da.1665203660.git.research_trasio@irq.a4lg.com/","msgid":"<740bc5e2d2618d236519b39fedd1a1d7ae4e05da.1665203660.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-08T04:34:25","name":"[3/5] opcodes/riscv-dis.c: Use bool type whenever possible","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/740bc5e2d2618d236519b39fedd1a1d7ae4e05da.1665203660.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1833,"url":"https://patchwork.plctlab.org/api/1.2/patches/1833/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6e3a9c235e317f441b4383b3daa68f2051bdc149.1665203660.git.research_trasio@irq.a4lg.com/","msgid":"<6e3a9c235e317f441b4383b3daa68f2051bdc149.1665203660.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-08T04:34:26","name":"[4/5] opcodes/riscv-dis.c: Make XLEN variable static","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6e3a9c235e317f441b4383b3daa68f2051bdc149.1665203660.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1834,"url":"https://patchwork.plctlab.org/api/1.2/patches/1834/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ad929233a62d887495122721340b2f9c80392963.1665203660.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-08T04:34:27","name":"[5/5] opcodes/riscv-dis.c: Remove last_map_state","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ad929233a62d887495122721340b2f9c80392963.1665203660.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1836,"url":"https://patchwork.plctlab.org/api/1.2/patches/1836/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d07e2b6f36ea2fd5830924a9bfeda941b774b687.1665290422.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-09T05:09:22","name":"RISC-V: Move certain arrays to riscv-opc.c","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d07e2b6f36ea2fd5830924a9bfeda941b774b687.1665290422.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1844,"url":"https://patchwork.plctlab.org/api/1.2/patches/1844/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010004623.16582-1-mark@harmstone.com/","msgid":"<20221010004623.16582-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-10T00:46:22","name":"[v2,1/2] ld: Add --pdb option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010004623.16582-1-mark@harmstone.com/mbox/"},{"id":1845,"url":"https://patchwork.plctlab.org/api/1.2/patches/1845/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010004623.16582-2-mark@harmstone.com/","msgid":"<20221010004623.16582-2-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-10T00:46:23","name":"[v2,2/2] ld: Add minimal pdb generation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010004623.16582-2-mark@harmstone.com/mbox/"},{"id":1890,"url":"https://patchwork.plctlab.org/api/1.2/patches/1890/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010200433.414320-1-vladimir.mezentsev@oracle.com/","msgid":"<20221010200433.414320-1-vladimir.mezentsev@oracle.com>","list_archive_url":null,"date":"2022-10-10T20:04:33","name":"gprofng: run tests without installation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010200433.414320-1-vladimir.mezentsev@oracle.com/mbox/"},{"id":1893,"url":"https://patchwork.plctlab.org/api/1.2/patches/1893/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010230426.719238-1-vladimir.mezentsev@oracle.com/","msgid":"<20221010230426.719238-1-vladimir.mezentsev@oracle.com>","list_archive_url":null,"date":"2022-10-10T23:04:26","name":"[2/2] gprofng: use the --libdir path to find libraries","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010230426.719238-1-vladimir.mezentsev@oracle.com/mbox/"},{"id":1894,"url":"https://patchwork.plctlab.org/api/1.2/patches/1894/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010235155.842469-1-vladimir.mezentsev@oracle.com/","msgid":"<20221010235155.842469-1-vladimir.mezentsev@oracle.com>","list_archive_url":null,"date":"2022-10-10T23:51:55","name":"[3/3] gprofng: no need to build version.texi","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010235155.842469-1-vladimir.mezentsev@oracle.com/mbox/"},{"id":1895,"url":"https://patchwork.plctlab.org/api/1.2/patches/1895/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011003702.4287-1-mark@harmstone.com/","msgid":"<20221011003702.4287-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-11T00:37:01","name":"[v3,1/2] ld: Add --pdb option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011003702.4287-1-mark@harmstone.com/mbox/"},{"id":1897,"url":"https://patchwork.plctlab.org/api/1.2/patches/1897/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011003702.4287-2-mark@harmstone.com/","msgid":"<20221011003702.4287-2-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-11T00:37:02","name":"[v3,2/2] ld: Add minimal pdb generation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011003702.4287-2-mark@harmstone.com/mbox/"},{"id":1928,"url":"https://patchwork.plctlab.org/api/1.2/patches/1928/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011175332.17156-1-mark@harmstone.com/","msgid":"<20221011175332.17156-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-11T17:53:31","name":"[v4,1/2] ld: Add --pdb option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011175332.17156-1-mark@harmstone.com/mbox/"},{"id":1929,"url":"https://patchwork.plctlab.org/api/1.2/patches/1929/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011175332.17156-2-mark@harmstone.com/","msgid":"<20221011175332.17156-2-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-11T17:53:32","name":"[v4,2/2] ld: Add minimal pdb generation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011175332.17156-2-mark@harmstone.com/mbox/"},{"id":1941,"url":"https://patchwork.plctlab.org/api/1.2/patches/1941/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221012031005.237446-1-simon.marchi@polymtl.ca/","msgid":"<20221012031005.237446-1-simon.marchi@polymtl.ca>","list_archive_url":null,"date":"2022-10-12T03:10:05","name":"[pushed] Re-apply \"Pass PKG_CONFIG_PATH down from top-level Makefile\"","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221012031005.237446-1-simon.marchi@polymtl.ca/mbox/"},{"id":1976,"url":"https://patchwork.plctlab.org/api/1.2/patches/1976/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1216a3f8-2273-8681-f528-9493a66891f0@suse.com/","msgid":"<1216a3f8-2273-8681-f528-9493a66891f0@suse.com>","list_archive_url":null,"date":"2022-10-13T08:16:49","name":"[v4,1/8] x86: constify parse_insn()'\''s input","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1216a3f8-2273-8681-f528-9493a66891f0@suse.com/mbox/"},{"id":1977,"url":"https://patchwork.plctlab.org/api/1.2/patches/1977/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/11599bbe-c779-aa9f-4d5d-c2243f0e69dc@suse.com/","msgid":"<11599bbe-c779-aa9f-4d5d-c2243f0e69dc@suse.com>","list_archive_url":null,"date":"2022-10-13T08:17:17","name":"[v4,2/8] x86: introduce Pass2 insn attribute","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/11599bbe-c779-aa9f-4d5d-c2243f0e69dc@suse.com/mbox/"},{"id":1978,"url":"https://patchwork.plctlab.org/api/1.2/patches/1978/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/357273a3-060c-23db-72da-3fc9d1be3d2a@suse.com/","msgid":"<357273a3-060c-23db-72da-3fc9d1be3d2a@suse.com>","list_archive_url":null,"date":"2022-10-13T08:18:09","name":"[v4,3/8] x86: re-work insn/suffix recognition","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/357273a3-060c-23db-72da-3fc9d1be3d2a@suse.com/mbox/"},{"id":1979,"url":"https://patchwork.plctlab.org/api/1.2/patches/1979/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0ec0587f-6a7b-45b6-8346-e5d774e73636@suse.com/","msgid":"<0ec0587f-6a7b-45b6-8346-e5d774e73636@suse.com>","list_archive_url":null,"date":"2022-10-13T08:18:39","name":"[v4,4/8] x86-64: further re-work insn/suffix recognition to also cover MOVSL","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0ec0587f-6a7b-45b6-8346-e5d774e73636@suse.com/mbox/"},{"id":1980,"url":"https://patchwork.plctlab.org/api/1.2/patches/1980/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fb617d0b-8759-3169-5a65-1178b7fef3d7@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-13T08:19:34","name":"[v4,5/8] ix86: don'\''t recognize/derive Q suffix in the common case","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fb617d0b-8759-3169-5a65-1178b7fef3d7@suse.com/mbox/"},{"id":1981,"url":"https://patchwork.plctlab.org/api/1.2/patches/1981/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1df3bd01-99c5-f56c-d937-970edd42b2b8@suse.com/","msgid":"<1df3bd01-99c5-f56c-d937-970edd42b2b8@suse.com>","list_archive_url":null,"date":"2022-10-13T08:20:14","name":"[v4,6/8] x86-64: allow HLE store of accumulator to absolute 32-bit address","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1df3bd01-99c5-f56c-d937-970edd42b2b8@suse.com/mbox/"},{"id":1982,"url":"https://patchwork.plctlab.org/api/1.2/patches/1982/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8486a218-39ec-16b2-5c6c-5037196b93cf@suse.com/","msgid":"<8486a218-39ec-16b2-5c6c-5037196b93cf@suse.com>","list_archive_url":null,"date":"2022-10-13T08:21:00","name":"[v4,7/8] x86: move bad-use-of-TLS-reloc check","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8486a218-39ec-16b2-5c6c-5037196b93cf@suse.com/mbox/"},{"id":1983,"url":"https://patchwork.plctlab.org/api/1.2/patches/1983/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7d82692d-93df-fbee-9efb-2f44e8a91df3@suse.com/","msgid":"<7d82692d-93df-fbee-9efb-2f44e8a91df3@suse.com>","list_archive_url":null,"date":"2022-10-13T08:22:00","name":"[v4,8/8] x86: drop (now) stray IsString","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7d82692d-93df-fbee-9efb-2f44e8a91df3@suse.com/mbox/"},{"id":2013,"url":"https://patchwork.plctlab.org/api/1.2/patches/2013/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8ab93d7a617ad480dd786210f46db0e5aa07d1ac.1665655719.git.research_trasio@irq.a4lg.com/","msgid":"<8ab93d7a617ad480dd786210f46db0e5aa07d1ac.1665655719.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-13T10:11:41","name":"include: Declare getopt function on old GNU libc","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8ab93d7a617ad480dd786210f46db0e5aa07d1ac.1665655719.git.research_trasio@irq.a4lg.com/mbox/"},{"id":2352,"url":"https://patchwork.plctlab.org/api/1.2/patches/2352/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221013201332.2747246-1-maskray@google.com/","msgid":"<20221013201332.2747246-1-maskray@google.com>","list_archive_url":null,"date":"2022-10-13T20:13:32","name":"ld: Add --undefined-version","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221013201332.2747246-1-maskray@google.com/mbox/"},{"id":2532,"url":"https://patchwork.plctlab.org/api/1.2/patches/2532/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014063520.1428330-2-zengxiao@eswincomputing.com/","msgid":"<20221014063520.1428330-2-zengxiao@eswincomputing.com>","list_archive_url":null,"date":"2022-10-14T06:35:20","name":"[1/1] RISC-V: Make R_RISCV_SUB6 conforms to riscv abi standard","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014063520.1428330-2-zengxiao@eswincomputing.com/mbox/"},{"id":2560,"url":"https://patchwork.plctlab.org/api/1.2/patches/2560/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/027ae69a-636b-6757-297a-eec42936401e@linaro.org/","msgid":"<027ae69a-636b-6757-297a-eec42936401e@linaro.org>","list_archive_url":null,"date":"2022-10-14T07:58:22","name":"[v3] aarch64-pe support for LD, GAS and BFD","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/027ae69a-636b-6757-297a-eec42936401e@linaro.org/mbox/"},{"id":2602,"url":"https://patchwork.plctlab.org/api/1.2/patches/2602/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-2-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-2-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:39","name":"[01/10] Support Intel AVX-IFMA","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-2-haochen.jiang@intel.com/mbox/"},{"id":2608,"url":"https://patchwork.plctlab.org/api/1.2/patches/2608/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-3-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-3-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:40","name":"[02/10] Support Intel AVX-VNNI-INT8","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-3-haochen.jiang@intel.com/mbox/"},{"id":2611,"url":"https://patchwork.plctlab.org/api/1.2/patches/2611/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-4-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-4-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:41","name":"[03/10] Support Intel AVX-NE-CONVERT","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-4-haochen.jiang@intel.com/mbox/"},{"id":2610,"url":"https://patchwork.plctlab.org/api/1.2/patches/2610/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-5-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-5-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:42","name":"[04/10] Support Intel CMPccXADD","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-5-haochen.jiang@intel.com/mbox/"},{"id":2601,"url":"https://patchwork.plctlab.org/api/1.2/patches/2601/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-6-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-6-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:43","name":"[05/10] Add handler for more i386_cpu_flags","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-6-haochen.jiang@intel.com/mbox/"},{"id":2606,"url":"https://patchwork.plctlab.org/api/1.2/patches/2606/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-7-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-7-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:44","name":"[06/10] Support Intel RAO-INT","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-7-haochen.jiang@intel.com/mbox/"},{"id":2609,"url":"https://patchwork.plctlab.org/api/1.2/patches/2609/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-8-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-8-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:45","name":"[07/10] Support Intel WRMSRNS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-8-haochen.jiang@intel.com/mbox/"},{"id":2605,"url":"https://patchwork.plctlab.org/api/1.2/patches/2605/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-9-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-9-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:46","name":"[08/10] Support Intel MSRLIST","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-9-haochen.jiang@intel.com/mbox/"},{"id":2607,"url":"https://patchwork.plctlab.org/api/1.2/patches/2607/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-10-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-10-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:47","name":"[09/10] Support Intel AMX-FP16","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-10-haochen.jiang@intel.com/mbox/"},{"id":2604,"url":"https://patchwork.plctlab.org/api/1.2/patches/2604/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-11-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-11-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:48","name":"[10/10] Support Intel PREFETCHI","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-11-haochen.jiang@intel.com/mbox/"},{"id":2643,"url":"https://patchwork.plctlab.org/api/1.2/patches/2643/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7bac66be-535e-9051-d674-f2f5ba180e17@suse.com/","msgid":"<7bac66be-535e-9051-d674-f2f5ba180e17@suse.com>","list_archive_url":null,"date":"2022-10-14T10:22:34","name":"x86: fold AVX512-VNNI disassembler entries with AVX-VNNI ones","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7bac66be-535e-9051-d674-f2f5ba180e17@suse.com/mbox/"},{"id":2654,"url":"https://patchwork.plctlab.org/api/1.2/patches/2654/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0lIo5+ncY/MqBEq@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-14T11:31:47","name":"PR29677, Field `the_bfd` of `asymbol` is uninitialised","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0lIo5+ncY/MqBEq@squeak.grove.modra.org/mbox/"},{"id":2656,"url":"https://patchwork.plctlab.org/api/1.2/patches/2656/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0lJksn49ZpABY89@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-14T11:35:46","name":"e200 LSP support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0lJksn49ZpABY89@squeak.grove.modra.org/mbox/"},{"id":2657,"url":"https://patchwork.plctlab.org/api/1.2/patches/2657/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0lJxxYoeD5iDYAD@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-14T11:36:39","name":"PowerPC SPE disassembly and tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0lJxxYoeD5iDYAD@squeak.grove.modra.org/mbox/"},{"id":2695,"url":"https://patchwork.plctlab.org/api/1.2/patches/2695/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/DM6PR12MB4219611F6CC2A0702884A602E7249@DM6PR12MB4219.namprd12.prod.outlook.com/","msgid":"","list_archive_url":null,"date":"2022-10-14T13:29:40","name":"Binutils: Adding new testcase for addr2line.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/DM6PR12MB4219611F6CC2A0702884A602E7249@DM6PR12MB4219.namprd12.prod.outlook.com/mbox/"},{"id":2700,"url":"https://patchwork.plctlab.org/api/1.2/patches/2700/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9fd2c88d-98b2-99a4-419f-c7235b2cf960@suse.com/","msgid":"<9fd2c88d-98b2-99a4-419f-c7235b2cf960@suse.com>","list_archive_url":null,"date":"2022-10-14T14:11:35","name":"x86: properly decode EVEX.W for AVX512_4{FMAPS,VNNIW} insns","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9fd2c88d-98b2-99a4-419f-c7235b2cf960@suse.com/mbox/"},{"id":2981,"url":"https://patchwork.plctlab.org/api/1.2/patches/2981/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0uLzalqjm4C87GN@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-16T04:42:53","name":"PowerPC se_rfmci and VLE, SPE2 and LSP insns with -many","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0uLzalqjm4C87GN@squeak.grove.modra.org/mbox/"},{"id":3152,"url":"https://patchwork.plctlab.org/api/1.2/patches/3152/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221016232419.1135-1-mark@harmstone.com/","msgid":"<20221016232419.1135-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-16T23:24:18","name":"[v5,1/2] ld: Add --pdb option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221016232419.1135-1-mark@harmstone.com/mbox/"},{"id":3151,"url":"https://patchwork.plctlab.org/api/1.2/patches/3151/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221016232419.1135-2-mark@harmstone.com/","msgid":"<20221016232419.1135-2-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-16T23:24:19","name":"[v5,2/2] ld: Add minimal pdb generation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221016232419.1135-2-mark@harmstone.com/mbox/"},{"id":3258,"url":"https://patchwork.plctlab.org/api/1.2/patches/3258/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/19c08747-fa5b-1e67-3dd2-c891a2c0c1fa@suse.com/","msgid":"<19c08747-fa5b-1e67-3dd2-c891a2c0c1fa@suse.com>","list_archive_url":null,"date":"2022-10-17T07:44:51","name":"x86: correct CPU_AMX_{BF16,INT8}_FLAGS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/19c08747-fa5b-1e67-3dd2-c891a2c0c1fa@suse.com/mbox/"},{"id":3272,"url":"https://patchwork.plctlab.org/api/1.2/patches/3272/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/85dd526c-d3a7-72dc-5444-ed5573eebec1@suse.com/","msgid":"<85dd526c-d3a7-72dc-5444-ed5573eebec1@suse.com>","list_archive_url":null,"date":"2022-10-17T08:30:12","name":"x86: generalize gas documentation for disabling of ISA extensions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/85dd526c-d3a7-72dc-5444-ed5573eebec1@suse.com/mbox/"},{"id":3759,"url":"https://patchwork.plctlab.org/api/1.2/patches/3759/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-2-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-2-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:15:58","name":"[V2,01/15] sframe.h: Add SFrame format definition","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-2-indu.bhagat@oracle.com/mbox/"},{"id":3762,"url":"https://patchwork.plctlab.org/api/1.2/patches/3762/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-3-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-3-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:15:59","name":"[V2,02/15] gas: add new command line option --gsframe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-3-indu.bhagat@oracle.com/mbox/"},{"id":3761,"url":"https://patchwork.plctlab.org/api/1.2/patches/3761/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-4-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-4-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:00","name":"[V2,03/15] gas: generate .sframe from CFI directives","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-4-indu.bhagat@oracle.com/mbox/"},{"id":3760,"url":"https://patchwork.plctlab.org/api/1.2/patches/3760/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-5-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-5-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:01","name":"[V2,04/15] gas: testsuite: add new tests for SFrame unwind info","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-5-indu.bhagat@oracle.com/mbox/"},{"id":3764,"url":"https://patchwork.plctlab.org/api/1.2/patches/3764/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-6-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-6-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:02","name":"[V2,05/15] libsframe: add the SFrame library","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-6-indu.bhagat@oracle.com/mbox/"},{"id":3766,"url":"https://patchwork.plctlab.org/api/1.2/patches/3766/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-7-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-7-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:03","name":"[V2,06/15] bfd: linker: merge .sframe sections","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-7-indu.bhagat@oracle.com/mbox/"},{"id":3763,"url":"https://patchwork.plctlab.org/api/1.2/patches/3763/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-8-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-8-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:04","name":"[V2,07/15] readelf/objdump: support for SFrame section","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-8-indu.bhagat@oracle.com/mbox/"},{"id":3765,"url":"https://patchwork.plctlab.org/api/1.2/patches/3765/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-9-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-9-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:05","name":"[V2,08/15] unwinder: generate backtrace using SFrame format","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-9-indu.bhagat@oracle.com/mbox/"},{"id":3770,"url":"https://patchwork.plctlab.org/api/1.2/patches/3770/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-10-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-10-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:06","name":"[V2,09/15] unwinder: Add SFrame unwinder tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-10-indu.bhagat@oracle.com/mbox/"},{"id":3769,"url":"https://patchwork.plctlab.org/api/1.2/patches/3769/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-11-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-11-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:07","name":"[V2,10/15] gdb: sim: buildsystem changes to accommodate libsframe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-11-indu.bhagat@oracle.com/mbox/"},{"id":3771,"url":"https://patchwork.plctlab.org/api/1.2/patches/3771/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-12-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-12-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:08","name":"[V2,11/15] libctf: add libsframe to LDFLAGS and LIBS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-12-indu.bhagat@oracle.com/mbox/"},{"id":3768,"url":"https://patchwork.plctlab.org/api/1.2/patches/3768/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-13-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-13-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:09","name":"[V2,12/15] src-release.sh: Add libsframe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-13-indu.bhagat@oracle.com/mbox/"},{"id":3767,"url":"https://patchwork.plctlab.org/api/1.2/patches/3767/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-14-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-14-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:10","name":"[V2,13/15] binutils/NEWS: add text for SFrame support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-14-indu.bhagat@oracle.com/mbox/"},{"id":3772,"url":"https://patchwork.plctlab.org/api/1.2/patches/3772/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-15-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-15-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:11","name":"[V2,14/15] gas/NEWS: add text about new command line option and SFrame support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-15-indu.bhagat@oracle.com/mbox/"},{"id":3773,"url":"https://patchwork.plctlab.org/api/1.2/patches/3773/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-16-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-16-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:12","name":"[V2,15/15] doc: add SFrame spec file","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-16-indu.bhagat@oracle.com/mbox/"},{"id":3999,"url":"https://patchwork.plctlab.org/api/1.2/patches/3999/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221018081205.17880-1-krebbel@linux.ibm.com/","msgid":"<20221018081205.17880-1-krebbel@linux.ibm.com>","list_archive_url":null,"date":"2022-10-18T08:12:05","name":"[1/1] IBM zSystems: Issue error for *DBL relocs on misaligned symbols","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221018081205.17880-1-krebbel@linux.ibm.com/mbox/"},{"id":4141,"url":"https://patchwork.plctlab.org/api/1.2/patches/4141/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/baffaf673f17692b7bcbd604b31800b189988596.camel@espressif.com/","msgid":"","list_archive_url":null,"date":"2022-10-18T12:12:07","name":"xtensa: use definitions from xtensa-config.h","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/baffaf673f17692b7bcbd604b31800b189988596.camel@espressif.com/mbox/"},{"id":4272,"url":"https://patchwork.plctlab.org/api/1.2/patches/4272/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221018174914.470062-1-hjl.tools@gmail.com/","msgid":"<20221018174914.470062-1-hjl.tools@gmail.com>","list_archive_url":null,"date":"2022-10-18T17:49:14","name":"x86: Disable AVX-VNNI when disabling AVX2","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221018174914.470062-1-hjl.tools@gmail.com/mbox/"},{"id":4998,"url":"https://patchwork.plctlab.org/api/1.2/patches/4998/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c2f76e95-09f6-1d92-7ef4-38a3c2955fcd@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-19T09:52:46","name":"x86: re-work AVX-VNNI support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c2f76e95-09f6-1d92-7ef4-38a3c2955fcd@suse.com/mbox/"},{"id":5276,"url":"https://patchwork.plctlab.org/api/1.2/patches/5276/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0/lLtlKqqsmAx0s@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-19T11:53:18","name":"Fix addr2line test for ppc64 elfv1 and mingw","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0/lLtlKqqsmAx0s@squeak.grove.modra.org/mbox/"},{"id":5424,"url":"https://patchwork.plctlab.org/api/1.2/patches/5424/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/07bfebbf3843b47e13d82d4fa16eb14fec942ef7.1666184962.git.research_trasio@irq.a4lg.com/","msgid":"<07bfebbf3843b47e13d82d4fa16eb14fec942ef7.1666184962.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:09:54","name":"binutils: Remove unused substitution PROGRAM","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/07bfebbf3843b47e13d82d4fa16eb14fec942ef7.1666184962.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5433,"url":"https://patchwork.plctlab.org/api/1.2/patches/5433/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2fa7ff719223232402e82a9c91331aea22ace1bb.1666185116.git.research_trasio@irq.a4lg.com/","msgid":"<2fa7ff719223232402e82a9c91331aea22ace1bb.1666185116.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:11:55","name":"[v2,1/8] RISC-V: Add a space at the end of pinfo","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2fa7ff719223232402e82a9c91331aea22ace1bb.1666185116.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5435,"url":"https://patchwork.plctlab.org/api/1.2/patches/5435/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1b30cce5db2cce3b8edca42ab5da114d0b8c9e93.1666185116.git.research_trasio@irq.a4lg.com/","msgid":"<1b30cce5db2cce3b8edca42ab5da114d0b8c9e93.1666185116.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:11:56","name":"[v2,2/8] RISC-V: Fix obvious misalignments ('\''Zbb'\''/'\''Zba'\'')","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1b30cce5db2cce3b8edca42ab5da114d0b8c9e93.1666185116.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5437,"url":"https://patchwork.plctlab.org/api/1.2/patches/5437/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6b0857aa1a2d15ca1cf00b4dcaae0032efbb88ff.1666185116.git.research_trasio@irq.a4lg.com/","msgid":"<6b0857aa1a2d15ca1cf00b4dcaae0032efbb88ff.1666185116.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:11:57","name":"[v2,3/8] RISC-V: Remove spaces in opcode entries","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6b0857aa1a2d15ca1cf00b4dcaae0032efbb88ff.1666185116.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5436,"url":"https://patchwork.plctlab.org/api/1.2/patches/5436/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/889d956caac0f2e95543a14afaeed97188ce384c.1666185116.git.research_trasio@irq.a4lg.com/","msgid":"<889d956caac0f2e95543a14afaeed97188ce384c.1666185116.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:11:58","name":"[v2,4/8] RISC-V: Remove unused instruction macros","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/889d956caac0f2e95543a14afaeed97188ce384c.1666185116.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5440,"url":"https://patchwork.plctlab.org/api/1.2/patches/5440/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8f226ee20d8a5ef6ad7b6c4408b44794a99d542a.1666185116.git.research_trasio@irq.a4lg.com/","msgid":"<8f226ee20d8a5ef6ad7b6c4408b44794a99d542a.1666185116.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:11:59","name":"[v2,5/8] RISC-V: Complete tidying up with SCALL and SBREAK","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8f226ee20d8a5ef6ad7b6c4408b44794a99d542a.1666185116.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5442,"url":"https://patchwork.plctlab.org/api/1.2/patches/5442/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4070184c454a05a39adf0790951e5856e6b2ecb6.1666185116.git.research_trasio@irq.a4lg.com/","msgid":"<4070184c454a05a39adf0790951e5856e6b2ecb6.1666185116.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:12:00","name":"[v2,6/8] RISC-V: Tidying up with fmv.w.x and fmv.x.w","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4070184c454a05a39adf0790951e5856e6b2ecb6.1666185116.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5438,"url":"https://patchwork.plctlab.org/api/1.2/patches/5438/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c1ccda3e7c8fb297eda46dab3936d5c5977178fc.1666185116.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-19T13:12:01","name":"[v2,7/8] RISC-V: Make alias instructions aliases","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c1ccda3e7c8fb297eda46dab3936d5c5977178fc.1666185116.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5441,"url":"https://patchwork.plctlab.org/api/1.2/patches/5441/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/413cfca82c7e8d8a2e977dfda9135903c9cb7c57.1666185116.git.research_trasio@irq.a4lg.com/","msgid":"<413cfca82c7e8d8a2e977dfda9135903c9cb7c57.1666185116.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:12:02","name":"[v2,8/8] RISC-V: Use defined mask and match values","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/413cfca82c7e8d8a2e977dfda9135903c9cb7c57.1666185116.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5439,"url":"https://patchwork.plctlab.org/api/1.2/patches/5439/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/345c5c3b3a53eab04a1e6e91197de2642095c94f.1666185237.git.research_trasio@irq.a4lg.com/","msgid":"<345c5c3b3a53eab04a1e6e91197de2642095c94f.1666185237.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:14:01","name":"RISC-V: Remove RV32EF conflict","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/345c5c3b3a53eab04a1e6e91197de2642095c94f.1666185237.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5616,"url":"https://patchwork.plctlab.org/api/1.2/patches/5616/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019145608.45213-5-haochen.jiang@intel.com/","msgid":"<20221019145608.45213-5-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T14:56:02","name":"[04/10] Support Intel CMPccXADD","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019145608.45213-5-haochen.jiang@intel.com/mbox/"},{"id":5614,"url":"https://patchwork.plctlab.org/api/1.2/patches/5614/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019145608.45213-6-haochen.jiang@intel.com/","msgid":"<20221019145608.45213-6-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T14:56:03","name":"[05/10] Add handler for more i386_cpu_flags","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019145608.45213-6-haochen.jiang@intel.com/mbox/"},{"id":5672,"url":"https://patchwork.plctlab.org/api/1.2/patches/5672/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-2-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-2-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:25","name":"[01/10] Support Intel AVX-IFMA","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-2-haochen.jiang@intel.com/mbox/"},{"id":5691,"url":"https://patchwork.plctlab.org/api/1.2/patches/5691/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-3-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-3-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:26","name":"[02/10] Support Intel AVX-VNNI-INT8","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-3-haochen.jiang@intel.com/mbox/"},{"id":5690,"url":"https://patchwork.plctlab.org/api/1.2/patches/5690/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-4-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-4-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:27","name":"[03/10] Support Intel AVX-NE-CONVERT","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-4-haochen.jiang@intel.com/mbox/"},{"id":5689,"url":"https://patchwork.plctlab.org/api/1.2/patches/5689/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-5-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-5-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:28","name":"[04/10] Support Intel CMPccXADD","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-5-haochen.jiang@intel.com/mbox/"},{"id":5676,"url":"https://patchwork.plctlab.org/api/1.2/patches/5676/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-6-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-6-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:29","name":"[05/10] Add handler for more i386_cpu_flags","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-6-haochen.jiang@intel.com/mbox/"},{"id":5677,"url":"https://patchwork.plctlab.org/api/1.2/patches/5677/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-7-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-7-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:30","name":"[06/10] Support Intel RAO-INT","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-7-haochen.jiang@intel.com/mbox/"},{"id":5681,"url":"https://patchwork.plctlab.org/api/1.2/patches/5681/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-8-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-8-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:31","name":"[07/10] Support Intel WRMSRNS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-8-haochen.jiang@intel.com/mbox/"},{"id":5682,"url":"https://patchwork.plctlab.org/api/1.2/patches/5682/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-9-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-9-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:32","name":"[08/10] Support Intel MSRLIST","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-9-haochen.jiang@intel.com/mbox/"},{"id":5673,"url":"https://patchwork.plctlab.org/api/1.2/patches/5673/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-10-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-10-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:33","name":"[09/10] Support Intel AMX-FP16","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-10-haochen.jiang@intel.com/mbox/"},{"id":5686,"url":"https://patchwork.plctlab.org/api/1.2/patches/5686/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-11-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-11-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:34","name":"[10/10] Support Intel PREFETCHI","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-11-haochen.jiang@intel.com/mbox/"},{"id":5940,"url":"https://patchwork.plctlab.org/api/1.2/patches/5940/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1CMrFUC8d9lC/NL@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-19T23:47:56","name":"Obsolete beos","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1CMrFUC8d9lC/NL@squeak.grove.modra.org/mbox/"},{"id":6080,"url":"https://patchwork.plctlab.org/api/1.2/patches/6080/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8b99d666e78ba5b9d32c7889a2161c70b3da88df.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<8b99d666e78ba5b9d32c7889a2161c70b3da88df.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:25:47","name":"[01/40] gdb/unittests: PR28413, suppress warnings generated by Gnulib","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8b99d666e78ba5b9d32c7889a2161c70b3da88df.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6081,"url":"https://patchwork.plctlab.org/api/1.2/patches/6081/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b05adb17e401d621dbdad791281bc7af7806906e.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-20T09:25:48","name":"[02/40] sim: Check known getrusage declaration existence","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b05adb17e401d621dbdad791281bc7af7806906e.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6083,"url":"https://patchwork.plctlab.org/api/1.2/patches/6083/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/796962a87e569feeafb5ef636de3c79000ae152c.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<796962a87e569feeafb5ef636de3c79000ae152c.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:25:49","name":"[03/40] sim/aarch64: Remove unused functions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/796962a87e569feeafb5ef636de3c79000ae152c.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6084,"url":"https://patchwork.plctlab.org/api/1.2/patches/6084/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/65223c79fdfd7faf132275415cd9da9852c5bec3.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<65223c79fdfd7faf132275415cd9da9852c5bec3.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:25:50","name":"[04/40] cpu/cris: Initialize some variables on CRIS CPU","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/65223c79fdfd7faf132275415cd9da9852c5bec3.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6082,"url":"https://patchwork.plctlab.org/api/1.2/patches/6082/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/24baefe92148f4b7968115ba13de9b0c863a65f6.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<24baefe92148f4b7968115ba13de9b0c863a65f6.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:25:51","name":"[05/40] cpu/cris: Add u-stall virtual unit to CRIS v32","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/24baefe92148f4b7968115ba13de9b0c863a65f6.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6087,"url":"https://patchwork.plctlab.org/api/1.2/patches/6087/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3904a5c3e80f8548150d8088a92059dd728c7ff8.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<3904a5c3e80f8548150d8088a92059dd728c7ff8.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:25:52","name":"[06/40] sim/cris: Move declarations of f_specific_init","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3904a5c3e80f8548150d8088a92059dd728c7ff8.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6091,"url":"https://patchwork.plctlab.org/api/1.2/patches/6091/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/69ef2d7dd519ed572511890a215a0f6d74e53384.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<69ef2d7dd519ed572511890a215a0f6d74e53384.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:25:53","name":"[07/40] sim/cris: Regenerate with CGEN","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/69ef2d7dd519ed572511890a215a0f6d74e53384.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6085,"url":"https://patchwork.plctlab.org/api/1.2/patches/6085/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/26a3eaf4f5d2e0db6977738ddfd65d82b36e38b2.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<26a3eaf4f5d2e0db6977738ddfd65d82b36e38b2.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:25:54","name":"[08/40] sim/erc32: Insert void parameter","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/26a3eaf4f5d2e0db6977738ddfd65d82b36e38b2.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6086,"url":"https://patchwork.plctlab.org/api/1.2/patches/6086/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/057c2f8392410494c3bc5dc98052246508e6a73e.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<057c2f8392410494c3bc5dc98052246508e6a73e.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:25:55","name":"[09/40] sim/erc32: Use int32_t as event callback argument","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/057c2f8392410494c3bc5dc98052246508e6a73e.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6090,"url":"https://patchwork.plctlab.org/api/1.2/patches/6090/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8c05aec20557191434485be347d37177a2ec5ff2.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<8c05aec20557191434485be347d37177a2ec5ff2.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:25:56","name":"[10/40] sim/erc32: Use int32_t as IRQ callback argument","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8c05aec20557191434485be347d37177a2ec5ff2.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6089,"url":"https://patchwork.plctlab.org/api/1.2/patches/6089/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/afd7757aae21743c29f2aa4135a23b31d4959e9b.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-20T09:25:57","name":"[11/40] cpu/frv: Initialize some variables","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/afd7757aae21743c29f2aa4135a23b31d4959e9b.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6088,"url":"https://patchwork.plctlab.org/api/1.2/patches/6088/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/021dbd238af5dfe74523ed229d2156a155a6bb9e.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<021dbd238af5dfe74523ed229d2156a155a6bb9e.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:25:58","name":"[12/40] sim/frv: Initialize nesr variable","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/021dbd238af5dfe74523ed229d2156a155a6bb9e.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6093,"url":"https://patchwork.plctlab.org/api/1.2/patches/6093/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/51a03f7097921cc48954210cf99e370ae8982ec8.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<51a03f7097921cc48954210cf99e370ae8982ec8.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:25:59","name":"[13/40] sim/frv: Initialize some variables","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/51a03f7097921cc48954210cf99e370ae8982ec8.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6092,"url":"https://patchwork.plctlab.org/api/1.2/patches/6092/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e1baa1be3601612266dc6ae0bdde8426ff2a42c8.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-20T09:26:00","name":"[14/40] sim/frv: Add explicit casts","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e1baa1be3601612266dc6ae0bdde8426ff2a42c8.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6095,"url":"https://patchwork.plctlab.org/api/1.2/patches/6095/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5ab303a5bdfc1da7832f8fa22f57678c9ef1a5fa.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<5ab303a5bdfc1da7832f8fa22f57678c9ef1a5fa.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:26:01","name":"[15/40] sim/h8300: Add \"+ 0x0\" to avoid self-assignments","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5ab303a5bdfc1da7832f8fa22f57678c9ef1a5fa.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6101,"url":"https://patchwork.plctlab.org/api/1.2/patches/6101/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ddff80db3328a2286fe6fbc1240d2abc1e3813eb.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-20T09:26:02","name":"[16/40] sim/lm32: fix some missing function declaration warnings","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ddff80db3328a2286fe6fbc1240d2abc1e3813eb.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6094,"url":"https://patchwork.plctlab.org/api/1.2/patches/6094/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e094b1379231d9ffb59a78cfebbcc84634c779c6.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-20T09:26:03","name":"[17/40] sim/lm32: Add explicit casts","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e094b1379231d9ffb59a78cfebbcc84634c779c6.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6141,"url":"https://patchwork.plctlab.org/api/1.2/patches/6141/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/cabebead-489b-528c-580e-933832417474@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-20T10:25:51","name":"[1/3] x86: emit {evex} prefix when disassembling ambiguous AVX512VL insns","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/cabebead-489b-528c-580e-933832417474@suse.com/mbox/"},{"id":6143,"url":"https://patchwork.plctlab.org/api/1.2/patches/6143/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a032d61c-63a0-23d1-331f-619a2b8bbde3@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-20T10:26:15","name":"[2/3] x86: consolidate VAES tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a032d61c-63a0-23d1-331f-619a2b8bbde3@suse.com/mbox/"},{"id":6142,"url":"https://patchwork.plctlab.org/api/1.2/patches/6142/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7ff09c86-2de7-dc34-3183-5187de3df5ac@suse.com/","msgid":"<7ff09c86-2de7-dc34-3183-5187de3df5ac@suse.com>","list_archive_url":null,"date":"2022-10-20T10:26:40","name":"[3/3] x86: consolidate VPCLMUL tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7ff09c86-2de7-dc34-3183-5187de3df5ac@suse.com/mbox/"},{"id":6228,"url":"https://patchwork.plctlab.org/api/1.2/patches/6228/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.LSU.2.20.2210201432170.29399@wotan.suse.de/","msgid":"","list_archive_url":null,"date":"2022-10-20T14:42:25","name":"x86-64: Use only one default max-page-size","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.LSU.2.20.2210201432170.29399@wotan.suse.de/mbox/"},{"id":6229,"url":"https://patchwork.plctlab.org/api/1.2/patches/6229/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221020144351.1398099-1-chigot@adacore.com/","msgid":"<20221020144351.1398099-1-chigot@adacore.com>","list_archive_url":null,"date":"2022-10-20T14:43:50","name":"[1/2] ld/testsuite: skip ld-elf/exclude when -shared is not supported","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221020144351.1398099-1-chigot@adacore.com/mbox/"},{"id":6230,"url":"https://patchwork.plctlab.org/api/1.2/patches/6230/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221020144351.1398099-2-chigot@adacore.com/","msgid":"<20221020144351.1398099-2-chigot@adacore.com>","list_archive_url":null,"date":"2022-10-20T14:43:51","name":"[2/2] ld/testsuite: adjust ld-arm to run shared tests only when supported","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221020144351.1398099-2-chigot@adacore.com/mbox/"},{"id":6236,"url":"https://patchwork.plctlab.org/api/1.2/patches/6236/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221020151027.GA1300@delia.home/","msgid":"<20221020151027.GA1300@delia.home>","list_archive_url":null,"date":"2022-10-20T15:10:28","name":"[RFC,top-level] Add configure test-case","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221020151027.GA1300@delia.home/mbox/"},{"id":6286,"url":"https://patchwork.plctlab.org/api/1.2/patches/6286/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221020162911.1113338-1-hjl.tools@gmail.com/","msgid":"<20221020162911.1113338-1-hjl.tools@gmail.com>","list_archive_url":null,"date":"2022-10-20T16:29:11","name":"x86: Check VEX/EVEX encoding before checking vector operands","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221020162911.1113338-1-hjl.tools@gmail.com/mbox/"},{"id":7884,"url":"https://patchwork.plctlab.org/api/1.2/patches/7884/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7e53b7980f2b3b74d2250bc87f5db94b1d888a2d.camel@espressif.com/","msgid":"<7e53b7980f2b3b74d2250bc87f5db94b1d888a2d.camel@espressif.com>","list_archive_url":null,"date":"2022-10-22T12:53:54","name":"[1/5] bfd: xtensa: move common code from ld and gas","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7e53b7980f2b3b74d2250bc87f5db94b1d888a2d.camel@espressif.com/mbox/"},{"id":7885,"url":"https://patchwork.plctlab.org/api/1.2/patches/7885/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/63f2699e6ef3e6d1ca415a6ed1187d4f64297521.camel@espressif.com/","msgid":"<63f2699e6ef3e6d1ca415a6ed1187d4f64297521.camel@espressif.com>","list_archive_url":null,"date":"2022-10-22T12:55:16","name":"[2/5] gas: xtensa: add endianness, loops, booleans options","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/63f2699e6ef3e6d1ca415a6ed1187d4f64297521.camel@espressif.com/mbox/"},{"id":7886,"url":"https://patchwork.plctlab.org/api/1.2/patches/7886/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/34d2f747237aeeda595560cfded8096d9bd1c28c.camel@espressif.com/","msgid":"<34d2f747237aeeda595560cfded8096d9bd1c28c.camel@espressif.com>","list_archive_url":null,"date":"2022-10-22T12:56:02","name":"[3/5] ld: xtensa: use default LD command line options for endianness","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/34d2f747237aeeda595560cfded8096d9bd1c28c.camel@espressif.com/mbox/"},{"id":7891,"url":"https://patchwork.plctlab.org/api/1.2/patches/7891/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/535b6208c1718b9acf3258575e1ebc0a65af9f07.camel@espressif.com/","msgid":"<535b6208c1718b9acf3258575e1ebc0a65af9f07.camel@espressif.com>","list_archive_url":null,"date":"2022-10-22T13:56:44","name":"[5/5] gdb: xtensa: add support for esp32, esp32s2, esp32s3 isa-modules","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/535b6208c1718b9acf3258575e1ebc0a65af9f07.camel@espressif.com/mbox/"},{"id":10456,"url":"https://patchwork.plctlab.org/api/1.2/patches/10456/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221025013347.68282-1-nelson@rivosinc.com/","msgid":"<20221025013347.68282-1-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-10-25T01:33:46","name":"[committed,1/2] RISC-V: Improve link time complexity.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221025013347.68282-1-nelson@rivosinc.com/mbox/"},{"id":10454,"url":"https://patchwork.plctlab.org/api/1.2/patches/10454/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221025013347.68282-2-nelson@rivosinc.com/","msgid":"<20221025013347.68282-2-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-10-25T01:33:47","name":"[committed,2/2] RISC-V: Should reset `again'\'' flag for _bfd_riscv_relax_pc.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221025013347.68282-2-nelson@rivosinc.com/mbox/"},{"id":10536,"url":"https://patchwork.plctlab.org/api/1.2/patches/10536/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/bb7b87e4-1893-5c86-4a14-92bafc818b03@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-25T07:24:56","name":"[v5,1/8] x86: constify parse_insn()'\''s input","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/bb7b87e4-1893-5c86-4a14-92bafc818b03@suse.com/mbox/"},{"id":10537,"url":"https://patchwork.plctlab.org/api/1.2/patches/10537/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b9273ae6-0218-54f8-5374-b265ed13b71a@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-25T07:25:26","name":"[v5,1/8] x86: introduce Pass2 insn attribute","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b9273ae6-0218-54f8-5374-b265ed13b71a@suse.com/mbox/"},{"id":10541,"url":"https://patchwork.plctlab.org/api/1.2/patches/10541/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7250dab9-e218-e6dd-4c74-23da9f611ab4@suse.com/","msgid":"<7250dab9-e218-e6dd-4c74-23da9f611ab4@suse.com>","list_archive_url":null,"date":"2022-10-25T07:26:11","name":"[v5,3/8] x86: re-work insn/suffix recognition","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7250dab9-e218-e6dd-4c74-23da9f611ab4@suse.com/mbox/"},{"id":10540,"url":"https://patchwork.plctlab.org/api/1.2/patches/10540/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/13fc630f-e116-0099-5c9e-2697df6519d7@suse.com/","msgid":"<13fc630f-e116-0099-5c9e-2697df6519d7@suse.com>","list_archive_url":null,"date":"2022-10-25T07:26:40","name":"[v5,4/8] ix86: don'\''t recognize/derive Q suffix in the common case","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/13fc630f-e116-0099-5c9e-2697df6519d7@suse.com/mbox/"},{"id":10543,"url":"https://patchwork.plctlab.org/api/1.2/patches/10543/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/74db429d-d203-eab8-4ae1-18b9ad416b02@suse.com/","msgid":"<74db429d-d203-eab8-4ae1-18b9ad416b02@suse.com>","list_archive_url":null,"date":"2022-10-25T07:27:11","name":"[v5,5/8] x86-64: allow HLE store of accumulator to absolute 32-bit address","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/74db429d-d203-eab8-4ae1-18b9ad416b02@suse.com/mbox/"},{"id":10542,"url":"https://patchwork.plctlab.org/api/1.2/patches/10542/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2e2f7841-de4e-b5de-e8d9-a47a6a4113c8@suse.com/","msgid":"<2e2f7841-de4e-b5de-e8d9-a47a6a4113c8@suse.com>","list_archive_url":null,"date":"2022-10-25T07:27:35","name":"[v5,6/8] x86: move bad-use-of-TLS-reloc check","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2e2f7841-de4e-b5de-e8d9-a47a6a4113c8@suse.com/mbox/"},{"id":10545,"url":"https://patchwork.plctlab.org/api/1.2/patches/10545/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/421bc96e-7591-6980-48e9-5af8c8b0775a@suse.com/","msgid":"<421bc96e-7591-6980-48e9-5af8c8b0775a@suse.com>","list_archive_url":null,"date":"2022-10-25T07:28:27","name":"[v5,7/8] x86: drop (now) stray IsString","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/421bc96e-7591-6980-48e9-5af8c8b0775a@suse.com/mbox/"},{"id":10546,"url":"https://patchwork.plctlab.org/api/1.2/patches/10546/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/06ff83d4-4633-a07b-70e5-a8e049981dd4@suse.com/","msgid":"<06ff83d4-4633-a07b-70e5-a8e049981dd4@suse.com>","list_archive_url":null,"date":"2022-10-25T07:29:18","name":"[v5,8/8] x86: further re-work insn/suffix recognition to also cover MOVSX","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/06ff83d4-4633-a07b-70e5-a8e049981dd4@suse.com/mbox/"},{"id":10777,"url":"https://patchwork.plctlab.org/api/1.2/patches/10777/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6a8e7a71acccd0efb9789dfb3edfa307e83bdaa1.1666702934.git.research_trasio@irq.a4lg.com/","msgid":"<6a8e7a71acccd0efb9789dfb3edfa307e83bdaa1.1666702934.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-25T13:04:02","name":"[RFC] RISC-V: Allocate \"various\" operand type","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6a8e7a71acccd0efb9789dfb3edfa307e83bdaa1.1666702934.git.research_trasio@irq.a4lg.com/mbox/"},{"id":11062,"url":"https://patchwork.plctlab.org/api/1.2/patches/11062/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jAhwbXhxJHL66v@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-26T05:07:19","name":"PR29720, objdump -S crashes if build-id is missing","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jAhwbXhxJHL66v@squeak.grove.modra.org/mbox/"},{"id":11063,"url":"https://patchwork.plctlab.org/api/1.2/patches/11063/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jAxD+NxpMIah6s@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-26T05:08:20","name":"som.c buffer overflow","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jAxD+NxpMIah6s@squeak.grove.modra.org/mbox/"},{"id":11064,"url":"https://patchwork.plctlab.org/api/1.2/patches/11064/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jBYw4lfRQfOZhi@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-26T05:10:59","name":"som.c reloc sanity checking","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jBYw4lfRQfOZhi@squeak.grove.modra.org/mbox/"},{"id":11080,"url":"https://patchwork.plctlab.org/api/1.2/patches/11080/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jY7hygm01PelCY@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-26T06:51:26","name":"segfault in objdump.c reloc_at","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jY7hygm01PelCY@squeak.grove.modra.org/mbox/"},{"id":11081,"url":"https://patchwork.plctlab.org/api/1.2/patches/11081/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jZWIeIvCCYm9/g@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-26T06:53:12","name":"Correct ELF reloc size sanity check","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jZWIeIvCCYm9/g@squeak.grove.modra.org/mbox/"},{"id":11082,"url":"https://patchwork.plctlab.org/api/1.2/patches/11082/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221026070009.3663574-1-ysato@users.sourceforge.jp/","msgid":"<20221026070009.3663574-1-ysato@users.sourceforge.jp>","list_archive_url":null,"date":"2022-10-26T07:00:09","name":"opcodes: RX fix invalid output.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221026070009.3663574-1-ysato@users.sourceforge.jp/mbox/"},{"id":11089,"url":"https://patchwork.plctlab.org/api/1.2/patches/11089/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jhW48kuVC8Ig2d@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-26T07:27:23","name":"buffer overflow in _bfd_XX_print_ce_compressed_pdata","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jhW48kuVC8Ig2d@squeak.grove.modra.org/mbox/"},{"id":11157,"url":"https://patchwork.plctlab.org/api/1.2/patches/11157/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c52dbd16-7e1b-c356-7a92-1ff089564ef7@suse.cz/","msgid":"","list_archive_url":null,"date":"2022-10-26T08:47:09","name":"tests: use canonical option name","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c52dbd16-7e1b-c356-7a92-1ff089564ef7@suse.cz/mbox/"},{"id":11526,"url":"https://patchwork.plctlab.org/api/1.2/patches/11526/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027031915.4013-1-lifang_xia@linux.alibaba.com/","msgid":"<20221027031915.4013-1-lifang_xia@linux.alibaba.com>","list_archive_url":null,"date":"2022-10-27T03:19:15","name":"[v2] RISC-V: Optimize relax of GP/call with max_alignment.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027031915.4013-1-lifang_xia@linux.alibaba.com/mbox/"},{"id":11619,"url":"https://patchwork.plctlab.org/api/1.2/patches/11619/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9df9d9e5bb4c7594b76c40613a349b4d2364e9c5.1666854355.git.research_trasio@irq.a4lg.com/","msgid":"<9df9d9e5bb4c7594b76c40613a349b4d2364e9c5.1666854355.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-27T07:06:01","name":"include: Define macro to ignore -Wdeprecated-declarations on GCC","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9df9d9e5bb4c7594b76c40613a349b4d2364e9c5.1666854355.git.research_trasio@irq.a4lg.com/mbox/"},{"id":11627,"url":"https://patchwork.plctlab.org/api/1.2/patches/11627/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1o06O9Pp8ncCsOw@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-27T07:36:08","name":"Fuzzed files in archives","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1o06O9Pp8ncCsOw@squeak.grove.modra.org/mbox/"},{"id":11658,"url":"https://patchwork.plctlab.org/api/1.2/patches/11658/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027084808.37252-1-nelson@rivosinc.com/","msgid":"<20221027084808.37252-1-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-10-27T08:48:08","name":"[committed] RISC-V: Fix build failures for -Werror=sign-compare.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027084808.37252-1-nelson@rivosinc.com/mbox/"},{"id":11921,"url":"https://patchwork.plctlab.org/api/1.2/patches/11921/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027190052.10536-1-mark@harmstone.com/","msgid":"<20221027190052.10536-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-27T19:00:51","name":"[1/2] ld: Add section header stream to PDB files","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027190052.10536-1-mark@harmstone.com/mbox/"},{"id":11922,"url":"https://patchwork.plctlab.org/api/1.2/patches/11922/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027190052.10536-2-mark@harmstone.com/","msgid":"<20221027190052.10536-2-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-27T19:00:52","name":"[2/2] ld: Add publics stream to PDB files","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027190052.10536-2-mark@harmstone.com/mbox/"},{"id":11965,"url":"https://patchwork.plctlab.org/api/1.2/patches/11965/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027202719.32497-1-palmer@rivosinc.com/","msgid":"<20221027202719.32497-1-palmer@rivosinc.com>","list_archive_url":null,"date":"2022-10-27T20:27:18","name":"[1/2] gas: NEWS: Add a missing newline","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027202719.32497-1-palmer@rivosinc.com/mbox/"},{"id":11966,"url":"https://patchwork.plctlab.org/api/1.2/patches/11966/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027202719.32497-2-palmer@rivosinc.com/","msgid":"<20221027202719.32497-2-palmer@rivosinc.com>","list_archive_url":null,"date":"2022-10-27T20:27:19","name":"[2/2] gas: NEWS: Note support for RISC-V Zawrs","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027202719.32497-2-palmer@rivosinc.com/mbox/"},{"id":12016,"url":"https://patchwork.plctlab.org/api/1.2/patches/12016/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/21ec9a18-fa89-0828-f625-499680022ec7@linux.ibm.com/","msgid":"<21ec9a18-fa89-0828-f625-499680022ec7@linux.ibm.com>","list_archive_url":null,"date":"2022-10-28T00:35:19","name":"[COMMITTED] PowerPC: Add support for RFC02653 - Dense Math Facility","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/21ec9a18-fa89-0828-f625-499680022ec7@linux.ibm.com/mbox/"},{"id":12017,"url":"https://patchwork.plctlab.org/api/1.2/patches/12017/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fd94047d-a070-45a6-3840-c105391718e0@linux.ibm.com/","msgid":"","list_archive_url":null,"date":"2022-10-28T00:37:18","name":"[COMMITTED] PowerPC: Add support for RFC02658 - MMA+ Outer-Product, Instructions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fd94047d-a070-45a6-3840-c105391718e0@linux.ibm.com/mbox/"},{"id":12122,"url":"https://patchwork.plctlab.org/api/1.2/patches/12122/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ac4f3f3c7115a824f73aca6935789b14d33c9a58.1666939920.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-28T06:53:02","name":"RISC-V: Fix build failure for -Werror=maybe-uninitialized","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ac4f3f3c7115a824f73aca6935789b14d33c9a58.1666939920.git.research_trasio@irq.a4lg.com/mbox/"},{"id":12181,"url":"https://patchwork.plctlab.org/api/1.2/patches/12181/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221028093840.19164-1-nelson@rivosinc.com/","msgid":"<20221028093840.19164-1-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-10-28T09:38:40","name":"RISC-V: Added SiFive custom cache control extensions.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221028093840.19164-1-nelson@rivosinc.com/mbox/"},{"id":12211,"url":"https://patchwork.plctlab.org/api/1.2/patches/12211/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4a280588-a85b-6ed3-634b-2b9cbc128f86@suse.com/","msgid":"<4a280588-a85b-6ed3-634b-2b9cbc128f86@suse.com>","list_archive_url":null,"date":"2022-10-28T10:06:35","name":"RISC-V/gas: fix build with certain gcc versions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4a280588-a85b-6ed3-634b-2b9cbc128f86@suse.com/mbox/"},{"id":12249,"url":"https://patchwork.plctlab.org/api/1.2/patches/12249/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/eb0e1bff-675e-72db-b8b1-b0f0e50b7121@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-28T12:35:35","name":"x86: minor improvements to optimize_imm() (part III)","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/eb0e1bff-675e-72db-b8b1-b0f0e50b7121@suse.com/mbox/"},{"id":12382,"url":"https://patchwork.plctlab.org/api/1.2/patches/12382/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/17f57574936af82be381a1451eac56b3709b60bb.1666968673.git.research_trasio@irq.a4lg.com/","msgid":"<17f57574936af82be381a1451eac56b3709b60bb.1666968673.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-28T14:52:12","name":"RISC-V: Emit mapping symbol with ISA string if non-default arch is used","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/17f57574936af82be381a1451eac56b3709b60bb.1666968673.git.research_trasio@irq.a4lg.com/mbox/"},{"id":12627,"url":"https://patchwork.plctlab.org/api/1.2/patches/12627/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221029034432.49859-1-nelson@rivosinc.com/","msgid":"<20221029034432.49859-1-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-10-29T03:44:32","name":"[committed] RISC-V: Always generate mapping symbols at the start of the sections.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221029034432.49859-1-nelson@rivosinc.com/mbox/"},{"id":12629,"url":"https://patchwork.plctlab.org/api/1.2/patches/12629/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1yxgzNJg5M48uPI@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-29T04:52:19","name":"NULL dereference read in som_write_object_contents","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1yxgzNJg5M48uPI@squeak.grove.modra.org/mbox/"},{"id":12630,"url":"https://patchwork.plctlab.org/api/1.2/patches/12630/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1yxnSHLY+FeB5DQ@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-29T04:52:45","name":"Fix small objcopy memory leak","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1yxnSHLY+FeB5DQ@squeak.grove.modra.org/mbox/"},{"id":12631,"url":"https://patchwork.plctlab.org/api/1.2/patches/12631/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1yxxfpJz+Jx4KTh@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-29T04:53:25","name":"pef: sanity check before malloc","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1yxxfpJz+Jx4KTh@squeak.grove.modra.org/mbox/"},{"id":12950,"url":"https://patchwork.plctlab.org/api/1.2/patches/12950/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-2-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-2-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:36","name":"[V3,01/15] sframe.h: Add SFrame format definition","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-2-indu.bhagat@oracle.com/mbox/"},{"id":12952,"url":"https://patchwork.plctlab.org/api/1.2/patches/12952/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-3-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-3-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:37","name":"[V3,02/15] gas: add new command line option --gsframe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-3-indu.bhagat@oracle.com/mbox/"},{"id":12951,"url":"https://patchwork.plctlab.org/api/1.2/patches/12951/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-4-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-4-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:38","name":"[V3,03/15] gas: generate .sframe from CFI directives","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-4-indu.bhagat@oracle.com/mbox/"},{"id":12956,"url":"https://patchwork.plctlab.org/api/1.2/patches/12956/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-5-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-5-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:39","name":"[V3,04/15] gas: testsuite: add new tests for SFrame unwind info","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-5-indu.bhagat@oracle.com/mbox/"},{"id":12955,"url":"https://patchwork.plctlab.org/api/1.2/patches/12955/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-6-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-6-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:40","name":"[V3,05/15] libsframe: add the SFrame library","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-6-indu.bhagat@oracle.com/mbox/"},{"id":12959,"url":"https://patchwork.plctlab.org/api/1.2/patches/12959/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-7-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-7-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:41","name":"[V3,06/15] bfd: linker: merge .sframe sections","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-7-indu.bhagat@oracle.com/mbox/"},{"id":12961,"url":"https://patchwork.plctlab.org/api/1.2/patches/12961/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-8-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-8-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:42","name":"[V3,07/15] readelf/objdump: support for SFrame section","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-8-indu.bhagat@oracle.com/mbox/"},{"id":12962,"url":"https://patchwork.plctlab.org/api/1.2/patches/12962/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-9-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-9-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:43","name":"[V3,08/15] unwinder: generate backtrace using SFrame format","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-9-indu.bhagat@oracle.com/mbox/"},{"id":12963,"url":"https://patchwork.plctlab.org/api/1.2/patches/12963/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-10-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-10-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:44","name":"[V3,09/15] unwinder: Add SFrame unwinder tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-10-indu.bhagat@oracle.com/mbox/"},{"id":12964,"url":"https://patchwork.plctlab.org/api/1.2/patches/12964/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-11-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-11-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:45","name":"[V3,10/15] gdb: sim: buildsystem changes to accommodate libsframe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-11-indu.bhagat@oracle.com/mbox/"},{"id":12957,"url":"https://patchwork.plctlab.org/api/1.2/patches/12957/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-12-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-12-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:46","name":"[V3,11/15] libctf: add libsframe to LDFLAGS and LIBS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-12-indu.bhagat@oracle.com/mbox/"},{"id":12960,"url":"https://patchwork.plctlab.org/api/1.2/patches/12960/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-13-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-13-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:47","name":"[V3,12/15] src-release.sh: Add libsframe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-13-indu.bhagat@oracle.com/mbox/"},{"id":12953,"url":"https://patchwork.plctlab.org/api/1.2/patches/12953/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-14-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-14-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:48","name":"[V3,13/15] binutils/NEWS: add text for SFrame support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-14-indu.bhagat@oracle.com/mbox/"},{"id":12954,"url":"https://patchwork.plctlab.org/api/1.2/patches/12954/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-15-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-15-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:49","name":"[V3,14/15] gas/NEWS: add text about new command line option and SFrame support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-15-indu.bhagat@oracle.com/mbox/"},{"id":12958,"url":"https://patchwork.plctlab.org/api/1.2/patches/12958/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-16-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-16-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:50","name":"[V3,15/15] doc: add SFrame spec file","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-16-indu.bhagat@oracle.com/mbox/"},{"id":12988,"url":"https://patchwork.plctlab.org/api/1.2/patches/12988/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y15KFY32CyFhh/+u@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-30T09:55:33","name":"Pool section entries for DWP version 1","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y15KFY32CyFhh/+u@squeak.grove.modra.org/mbox/"},{"id":13076,"url":"https://patchwork.plctlab.org/api/1.2/patches/13076/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031001554.14615-1-mark@harmstone.com/","msgid":"<20221031001554.14615-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-31T00:15:52","name":"[v2,1/3] ld: Use %E in einfo in pdb.c","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031001554.14615-1-mark@harmstone.com/mbox/"},{"id":13078,"url":"https://patchwork.plctlab.org/api/1.2/patches/13078/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031001554.14615-2-mark@harmstone.com/","msgid":"<20221031001554.14615-2-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-31T00:15:53","name":"[v2,2/3] ld: Add section header stream to PDB files","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031001554.14615-2-mark@harmstone.com/mbox/"},{"id":13077,"url":"https://patchwork.plctlab.org/api/1.2/patches/13077/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031001554.14615-3-mark@harmstone.com/","msgid":"<20221031001554.14615-3-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-31T00:15:54","name":"[v2,3/3] ld: Add publics stream to PDB files","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031001554.14615-3-mark@harmstone.com/mbox/"},{"id":13106,"url":"https://patchwork.plctlab.org/api/1.2/patches/13106/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031030507.35588-2-haochen.jiang@intel.com/","msgid":"<20221031030507.35588-2-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-31T03:05:02","name":"[1/6] Support Intel AVX-IFMA","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031030507.35588-2-haochen.jiang@intel.com/mbox/"},{"id":13105,"url":"https://patchwork.plctlab.org/api/1.2/patches/13105/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031030507.35588-3-haochen.jiang@intel.com/","msgid":"<20221031030507.35588-3-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-31T03:05:03","name":"[2/6] Support Intel AVX-VNNI-INT8","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031030507.35588-3-haochen.jiang@intel.com/mbox/"},{"id":13103,"url":"https://patchwork.plctlab.org/api/1.2/patches/13103/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031030507.35588-4-haochen.jiang@intel.com/","msgid":"<20221031030507.35588-4-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-31T03:05:04","name":"[3/6] Support Intel CMPccXADD","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031030507.35588-4-haochen.jiang@intel.com/mbox/"},{"id":13101,"url":"https://patchwork.plctlab.org/api/1.2/patches/13101/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031030507.35588-5-haochen.jiang@intel.com/","msgid":"<20221031030507.35588-5-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-31T03:05:05","name":"[4/6] Add handler for more i386_cpu_flags","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031030507.35588-5-haochen.jiang@intel.com/mbox/"},{"id":13104,"url":"https://patchwork.plctlab.org/api/1.2/patches/13104/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031030507.35588-6-haochen.jiang@intel.com/","msgid":"<20221031030507.35588-6-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-31T03:05:06","name":"[5/6] Support Intel WRMSRNS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031030507.35588-6-haochen.jiang@intel.com/mbox/"},{"id":13102,"url":"https://patchwork.plctlab.org/api/1.2/patches/13102/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031030507.35588-7-haochen.jiang@intel.com/","msgid":"<20221031030507.35588-7-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-31T03:05:07","name":"[6/6] Support Intel MSRLIST","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031030507.35588-7-haochen.jiang@intel.com/mbox/"},{"id":13120,"url":"https://patchwork.plctlab.org/api/1.2/patches/13120/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031060601.38460-2-haochen.jiang@intel.com/","msgid":"<20221031060601.38460-2-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-31T06:06:00","name":"[1/2] i386: Add and ","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031060601.38460-2-haochen.jiang@intel.com/mbox/"},{"id":13121,"url":"https://patchwork.plctlab.org/api/1.2/patches/13121/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031060601.38460-3-haochen.jiang@intel.com/","msgid":"<20221031060601.38460-3-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-31T06:06:01","name":"[2/2] Support Intel AVX-NE-CONVERT","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031060601.38460-3-haochen.jiang@intel.com/mbox/"},{"id":13188,"url":"https://patchwork.plctlab.org/api/1.2/patches/13188/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9f6f8888-4dc1-a6b0-0590-35fc8a276369@suse.com/","msgid":"<9f6f8888-4dc1-a6b0-0590-35fc8a276369@suse.com>","list_archive_url":null,"date":"2022-10-31T10:18:20","name":"x86: drop bogus Tbyte","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9f6f8888-4dc1-a6b0-0590-35fc8a276369@suse.com/mbox/"},{"id":13213,"url":"https://patchwork.plctlab.org/api/1.2/patches/13213/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4f1aac95-fea5-2279-cb18-dfcdb51a2589@arm.com/","msgid":"<4f1aac95-fea5-2279-cb18-dfcdb51a2589@arm.com>","list_archive_url":null,"date":"2022-10-31T11:14:44","name":"aarch64: Add support for Common Short Sequence Compression extension","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4f1aac95-fea5-2279-cb18-dfcdb51a2589@arm.com/mbox/"}],"public":true,"mbox":"https://patchwork.plctlab.org/bundle/patchwork-bot/binutils-gdb_2022-10/mbox/"},{"id":7,"url":"https://patchwork.plctlab.org/api/1.2/bundles/7/","web_url":"https://patchwork.plctlab.org/bundle/patchwork-bot/binutils-gdb_2022-09/","project":{"id":2,"url":"https://patchwork.plctlab.org/api/1.2/projects/2/","name":"binutils-gdb","link_name":"binutils-gdb","list_id":"binutils.sourceware.org","list_email":"binutils@sourceware.org","web_url":"https://github.com/wangliu-iscas/Patchwork-Bundles/blob/main/binutils-gdb.md","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"name":"binutils-gdb_2022-09","owner":{"id":3,"url":"https://patchwork.plctlab.org/api/1.2/users/3/","username":"patchwork-bot","first_name":"","last_name":"","email":"ouuuleilei@gmail.com"},"patches":[{"id":1573,"url":"https://patchwork.plctlab.org/api/1.2/patches/1573/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930073211.2634-1-jiawei@iscas.ac.cn/","msgid":"<20220930073211.2634-1-jiawei@iscas.ac.cn>","list_archive_url":null,"date":"2022-09-30T07:32:11","name":"[V2] RISC-V: Add Smepmp CSR '\''mseccfg'\'' define and testcases.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930073211.2634-1-jiawei@iscas.ac.cn/mbox/"},{"id":1577,"url":"https://patchwork.plctlab.org/api/1.2/patches/1577/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/76fa0c3c-2303-ebdf-a765-ac4731581517@suse.com/","msgid":"<76fa0c3c-2303-ebdf-a765-ac4731581517@suse.com>","list_archive_url":null,"date":"2022-09-30T08:54:18","name":"objcopy: avoid \"shadowing\" of remove() function name","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/76fa0c3c-2303-ebdf-a765-ac4731581517@suse.com/mbox/"},{"id":1579,"url":"https://patchwork.plctlab.org/api/1.2/patches/1579/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930085852.71213-1-nelson@rivosinc.com/","msgid":"<20220930085852.71213-1-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-09-30T08:58:51","name":"[1/2] RISC-V: Output mapping symbols with ISA string.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930085852.71213-1-nelson@rivosinc.com/mbox/"},{"id":1578,"url":"https://patchwork.plctlab.org/api/1.2/patches/1578/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930085852.71213-2-nelson@rivosinc.com/","msgid":"<20220930085852.71213-2-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-09-30T08:58:52","name":"[2/2] RISC-V: Refer mapping symbol to R_RISCV_RELAX for rvc relaxations.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930085852.71213-2-nelson@rivosinc.com/mbox/"},{"id":1581,"url":"https://patchwork.plctlab.org/api/1.2/patches/1581/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930092058.71286-1-nelson@rivosinc.com/","msgid":"<20220930092058.71286-1-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-09-30T09:20:57","name":"[1/2] RISC-V: Output mapping symbols with ISA string.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930092058.71286-1-nelson@rivosinc.com/mbox/"},{"id":1580,"url":"https://patchwork.plctlab.org/api/1.2/patches/1580/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930092058.71286-2-nelson@rivosinc.com/","msgid":"<20220930092058.71286-2-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-09-30T09:20:58","name":"[2/2] RISC-V: Refer mapping symbol to R_RISCV_RELAX for rvc relaxations.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930092058.71286-2-nelson@rivosinc.com/mbox/"},{"id":1582,"url":"https://patchwork.plctlab.org/api/1.2/patches/1582/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5874dd79-0cf5-d65c-7ea2-13adfc799c0f@suse.com/","msgid":"<5874dd79-0cf5-d65c-7ea2-13adfc799c0f@suse.com>","list_archive_url":null,"date":"2022-09-30T09:41:29","name":"RISC-V: fix build after \"Add support for arbitrary immediate encoding formats\"","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5874dd79-0cf5-d65c-7ea2-13adfc799c0f@suse.com/mbox/"},{"id":1583,"url":"https://patchwork.plctlab.org/api/1.2/patches/1583/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/57d8ac2a-5757-3776-9924-99c17ca69938@suse.com/","msgid":"<57d8ac2a-5757-3776-9924-99c17ca69938@suse.com>","list_archive_url":null,"date":"2022-09-30T09:42:08","name":"RISC-V: fallout from \"re-arrange opcode table for consistent alias handling\"","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/57d8ac2a-5757-3776-9924-99c17ca69938@suse.com/mbox/"},{"id":1584,"url":"https://patchwork.plctlab.org/api/1.2/patches/1584/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e76ef8f7-72b9-5103-cb43-9608af01d017@suse.com/","msgid":"","list_archive_url":null,"date":"2022-09-30T09:42:50","name":"RISC-V: don'\''t cast expressions'\'' X_add_number to long in diagnostics","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e76ef8f7-72b9-5103-cb43-9608af01d017@suse.com/mbox/"},{"id":1585,"url":"https://patchwork.plctlab.org/api/1.2/patches/1585/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/61355429-24b3-17d0-ab03-6fa57ee861d5@suse.cz/","msgid":"<61355429-24b3-17d0-ab03-6fa57ee861d5@suse.cz>","list_archive_url":null,"date":"2022-09-30T09:48:52","name":"[RFC] add --enable-zstd-compressed-debug-sections configure option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/61355429-24b3-17d0-ab03-6fa57ee861d5@suse.cz/mbox/"},{"id":1586,"url":"https://patchwork.plctlab.org/api/1.2/patches/1586/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930103919.323690-1-christoph.muellner@vrull.eu/","msgid":"<20220930103919.323690-1-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2022-09-30T10:39:19","name":"RISC-V: Eliminate long-casts of X_add_number in diagnostics","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930103919.323690-1-christoph.muellner@vrull.eu/mbox/"},{"id":1590,"url":"https://patchwork.plctlab.org/api/1.2/patches/1590/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/DM6PR12MB4219C943049C6D883DEA3E55E7569@DM6PR12MB4219.namprd12.prod.outlook.com/","msgid":"","list_archive_url":null,"date":"2022-09-30T11:41:37","name":"[V2] Ignore DWARF debug information for -gsplit-dwarf with dwarf-5.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/DM6PR12MB4219C943049C6D883DEA3E55E7569@DM6PR12MB4219.namprd12.prod.outlook.com/mbox/"},{"id":1591,"url":"https://patchwork.plctlab.org/api/1.2/patches/1591/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c10321f9-d289-ef84-d263-bc278fb3d31b@suse.com/","msgid":"","list_archive_url":null,"date":"2022-09-30T11:59:04","name":"[1/4] RISC-V/gas: drop riscv_subsets static variable","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c10321f9-d289-ef84-d263-bc278fb3d31b@suse.com/mbox/"},{"id":1593,"url":"https://patchwork.plctlab.org/api/1.2/patches/1593/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3244eea0-c18c-e49a-4588-d69423130226@suse.com/","msgid":"<3244eea0-c18c-e49a-4588-d69423130226@suse.com>","list_archive_url":null,"date":"2022-09-30T11:59:23","name":"[2/4] RISC-V/gas: drop stray call to install_insn()","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3244eea0-c18c-e49a-4588-d69423130226@suse.com/mbox/"},{"id":1592,"url":"https://patchwork.plctlab.org/api/1.2/patches/1592/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/385d01fd-7e57-1f3f-1bae-30aa0c313d63@suse.com/","msgid":"<385d01fd-7e57-1f3f-1bae-30aa0c313d63@suse.com>","list_archive_url":null,"date":"2022-09-30T11:59:45","name":"[3/4] RISC-V/gas: don'\''t open-code insn_length()","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/385d01fd-7e57-1f3f-1bae-30aa0c313d63@suse.com/mbox/"},{"id":1594,"url":"https://patchwork.plctlab.org/api/1.2/patches/1594/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f5757acf-7b90-a0e3-5eea-3b97cc226930@suse.com/","msgid":"","list_archive_url":null,"date":"2022-09-30T12:00:12","name":"[4/4] RISC-V/gas: allow generating up to 176-bit instructions with .insn","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f5757acf-7b90-a0e3-5eea-3b97cc226930@suse.com/mbox/"},{"id":1596,"url":"https://patchwork.plctlab.org/api/1.2/patches/1596/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930140503.38233-1-chigot@adacore.com/","msgid":"<20220930140503.38233-1-chigot@adacore.com>","list_archive_url":null,"date":"2022-09-30T14:05:03","name":"ld/testsuite: consistently add board_ldflags when linking with GCC","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930140503.38233-1-chigot@adacore.com/mbox/"}],"public":true,"mbox":"https://patchwork.plctlab.org/bundle/patchwork-bot/binutils-gdb_2022-09/mbox/"},{"id":9,"url":"https://patchwork.plctlab.org/api/1.2/bundles/9/","web_url":"https://patchwork.plctlab.org/bundle/patchwork-bot/binutils-gdb_2022-11/","project":{"id":2,"url":"https://patchwork.plctlab.org/api/1.2/projects/2/","name":"binutils-gdb","link_name":"binutils-gdb","list_id":"binutils.sourceware.org","list_email":"binutils@sourceware.org","web_url":"https://github.com/wangliu-iscas/Patchwork-Bundles/blob/main/binutils-gdb.md","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"name":"binutils-gdb_2022-11","owner":{"id":3,"url":"https://patchwork.plctlab.org/api/1.2/users/3/","username":"patchwork-bot","first_name":"","last_name":"","email":"ouuuleilei@gmail.com"},"patches":[{"id":13337,"url":"https://patchwork.plctlab.org/api/1.2/patches/13337/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031160625.684434-1-hjl.tools@gmail.com/","msgid":"<20221031160625.684434-1-hjl.tools@gmail.com>","list_archive_url":null,"date":"2022-10-31T16:06:25","name":"x86: Silence GCC 12 warning on tc-i386.c","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031160625.684434-1-hjl.tools@gmail.com/mbox/"},{"id":13350,"url":"https://patchwork.plctlab.org/api/1.2/patches/13350/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c8d25b29-37fe-9623-a799-e67e1f991743@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-31T17:00:56","name":"x86: simplify expressions in update_imm()","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c8d25b29-37fe-9623-a799-e67e1f991743@suse.com/mbox/"},{"id":13487,"url":"https://patchwork.plctlab.org/api/1.2/patches/13487/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/CAMe9rOohVjin92PTeeiu_dvAtzYJn4dGtu5E=OxYfbyteraZWw@mail.gmail.com/","msgid":"","list_archive_url":null,"date":"2022-11-01T00:08:04","name":"binutils: Run PR binutils/26160 test","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/CAMe9rOohVjin92PTeeiu_dvAtzYJn4dGtu5E=OxYfbyteraZWw@mail.gmail.com/mbox/"},{"id":13621,"url":"https://patchwork.plctlab.org/api/1.2/patches/13621/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221101105724.1527333-1-aburgess@redhat.com/","msgid":"<20221101105724.1527333-1-aburgess@redhat.com>","list_archive_url":null,"date":"2022-11-01T10:57:24","name":"[PUSHED] opcodes/arm: silence compiler warning about uninitialized variable use","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221101105724.1527333-1-aburgess@redhat.com/mbox/"},{"id":13628,"url":"https://patchwork.plctlab.org/api/1.2/patches/13628/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221101111802.1532080-1-aburgess@redhat.com/","msgid":"<20221101111802.1532080-1-aburgess@redhat.com>","list_archive_url":null,"date":"2022-11-01T11:18:02","name":"[PUSHED] opcodes/arm: don'\''t pass non-string literal to printf like function","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221101111802.1532080-1-aburgess@redhat.com/mbox/"},{"id":13747,"url":"https://patchwork.plctlab.org/api/1.2/patches/13747/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/yw8jbkpqk6vw.fsf@arm.com/","msgid":"","list_archive_url":null,"date":"2022-11-01T15:54:11","name":"[Binutils-2.39,backport,GAS] arm: Use DWARF numbering convention for pseudo-register representation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/yw8jbkpqk6vw.fsf@arm.com/mbox/"},{"id":13993,"url":"https://patchwork.plctlab.org/api/1.2/patches/13993/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221102020752.24441-1-mark@harmstone.com/","msgid":"<20221102020752.24441-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-11-02T02:07:52","name":"ld: Add module information substream to PDB files","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221102020752.24441-1-mark@harmstone.com/mbox/"},{"id":14028,"url":"https://patchwork.plctlab.org/api/1.2/patches/14028/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221102050430.1053-1-nelson@rivosinc.com/","msgid":"<20221102050430.1053-1-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-11-02T05:04:30","name":"[committed] RISC-V: Fixed the missing $x+arch when adding odd paddings for alignment.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221102050430.1053-1-nelson@rivosinc.com/mbox/"},{"id":14043,"url":"https://patchwork.plctlab.org/api/1.2/patches/14043/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221102063046.31551-1-rjiejie@linux.alibaba.com/","msgid":"<20221102063046.31551-1-rjiejie@linux.alibaba.com>","list_archive_url":null,"date":"2022-11-02T06:30:46","name":"gas/doc/internals.texi: fix typo","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221102063046.31551-1-rjiejie@linux.alibaba.com/mbox/"},{"id":14069,"url":"https://patchwork.plctlab.org/api/1.2/patches/14069/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221102080112.33378-1-rjiejie@linux.alibaba.com/","msgid":"<20221102080112.33378-1-rjiejie@linux.alibaba.com>","list_archive_url":null,"date":"2022-11-02T08:01:12","name":"[v2] Support multiple .eh_frame sections","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221102080112.33378-1-rjiejie@linux.alibaba.com/mbox/"},{"id":14409,"url":"https://patchwork.plctlab.org/api/1.2/patches/14409/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221102172923.4009281-1-christophe.lyon@arm.com/","msgid":"<20221102172923.4009281-1-christophe.lyon@arm.com>","list_archive_url":null,"date":"2022-11-02T17:29:23","name":"arm: PR 29739 Fix typo where '\''; '\'' should not have been replaced with '\''@'\''","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221102172923.4009281-1-christophe.lyon@arm.com/mbox/"},{"id":14588,"url":"https://patchwork.plctlab.org/api/1.2/patches/14588/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221103020409.37322-1-rjiejie@linux.alibaba.com/","msgid":"<20221103020409.37322-1-rjiejie@linux.alibaba.com>","list_archive_url":null,"date":"2022-11-03T02:04:09","name":"[v3] Support multiple .eh_frame sections","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221103020409.37322-1-rjiejie@linux.alibaba.com/mbox/"},{"id":14602,"url":"https://patchwork.plctlab.org/api/1.2/patches/14602/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221103024604.614-1-mark@harmstone.com/","msgid":"<20221103024604.614-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-11-03T02:46:04","name":"[v2] ld: Add module information substream to PDB files","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221103024604.614-1-mark@harmstone.com/mbox/"},{"id":14706,"url":"https://patchwork.plctlab.org/api/1.2/patches/14706/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221103071519.3510462-1-luis.machado@arm.com/","msgid":"<20221103071519.3510462-1-luis.machado@arm.com>","list_archive_url":null,"date":"2022-11-03T07:15:19","name":"[opcodes/arm] Fix potential null pointer dereferences","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221103071519.3510462-1-luis.machado@arm.com/mbox/"},{"id":14840,"url":"https://patchwork.plctlab.org/api/1.2/patches/14840/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/283a86ebf0941f0f63dc1a590ec3d547bd5d69e8.1667478033.git.research_trasio@irq.a4lg.com/","msgid":"<283a86ebf0941f0f63dc1a590ec3d547bd5d69e8.1667478033.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-03T12:26:28","name":"[REVIEW,ONLY,1/2] NEAR-RATIFICATION RISC-V: Add '\''Ssstateen'\'' extension and its CSRs","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/283a86ebf0941f0f63dc1a590ec3d547bd5d69e8.1667478033.git.research_trasio@irq.a4lg.com/mbox/"},{"id":14841,"url":"https://patchwork.plctlab.org/api/1.2/patches/14841/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8083ad9d5339afdeb7f1ba88ee6af0665dcc76d5.1667478033.git.research_trasio@irq.a4lg.com/","msgid":"<8083ad9d5339afdeb7f1ba88ee6af0665dcc76d5.1667478033.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-03T12:26:29","name":"[REVIEW,ONLY,2/2] NEAR-RATIFICATION RISC-V: Add platform property/capability extensions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8083ad9d5339afdeb7f1ba88ee6af0665dcc76d5.1667478033.git.research_trasio@irq.a4lg.com/mbox/"},{"id":14894,"url":"https://patchwork.plctlab.org/api/1.2/patches/14894/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e53fbf5025e59fe6a3481b9c1fe37e4f6cf6e03d.1667483581.git.aburgess@redhat.com/","msgid":"","list_archive_url":null,"date":"2022-11-03T13:58:12","name":"[1/2] opcodes/mips: use .word/.short for undefined instructions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e53fbf5025e59fe6a3481b9c1fe37e4f6cf6e03d.1667483581.git.aburgess@redhat.com/mbox/"},{"id":14893,"url":"https://patchwork.plctlab.org/api/1.2/patches/14893/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ca81edb86580566b1641ad140eb2bed385160ab7.1667483581.git.aburgess@redhat.com/","msgid":"","list_archive_url":null,"date":"2022-11-03T13:58:13","name":"[2/2] libopcodes/mips: add support for disassembler styling","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ca81edb86580566b1641ad140eb2bed385160ab7.1667483581.git.aburgess@redhat.com/mbox/"},{"id":15465,"url":"https://patchwork.plctlab.org/api/1.2/patches/15465/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/926e5154-b40b-9df8-d770-a8bf7d40e40e@suse.com/","msgid":"<926e5154-b40b-9df8-d770-a8bf7d40e40e@suse.com>","list_archive_url":null,"date":"2022-11-04T10:50:38","name":"[v6,1/7] x86: constify parse_insn()'\''s input","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/926e5154-b40b-9df8-d770-a8bf7d40e40e@suse.com/mbox/"},{"id":15466,"url":"https://patchwork.plctlab.org/api/1.2/patches/15466/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/07ef67fd-752c-ad1f-b8cb-4eaec1f420fc@suse.com/","msgid":"<07ef67fd-752c-ad1f-b8cb-4eaec1f420fc@suse.com>","list_archive_url":null,"date":"2022-11-04T10:51:34","name":"[v6,2/7] x86: re-work insn/suffix recognition","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/07ef67fd-752c-ad1f-b8cb-4eaec1f420fc@suse.com/mbox/"},{"id":15467,"url":"https://patchwork.plctlab.org/api/1.2/patches/15467/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ee8fd655-19a5-d944-0f5e-4351b88a59f9@suse.com/","msgid":"","list_archive_url":null,"date":"2022-11-04T10:52:02","name":"[v6,3/7] ix86: don'\''t recognize/derive Q suffix in the common case","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ee8fd655-19a5-d944-0f5e-4351b88a59f9@suse.com/mbox/"},{"id":15468,"url":"https://patchwork.plctlab.org/api/1.2/patches/15468/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/15ab2cf5-f1ac-e882-c415-6318f1bcc7f0@suse.com/","msgid":"<15ab2cf5-f1ac-e882-c415-6318f1bcc7f0@suse.com>","list_archive_url":null,"date":"2022-11-04T10:52:31","name":"[v6,4/7] x86-64: allow HLE store of accumulator to absolute 32-bit address","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/15ab2cf5-f1ac-e882-c415-6318f1bcc7f0@suse.com/mbox/"},{"id":15470,"url":"https://patchwork.plctlab.org/api/1.2/patches/15470/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/352d1e49-ac9f-ee86-7e9d-74f79744268b@suse.com/","msgid":"<352d1e49-ac9f-ee86-7e9d-74f79744268b@suse.com>","list_archive_url":null,"date":"2022-11-04T10:53:14","name":"[v6,5/7] x86: move bad-use-of-TLS-reloc check","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/352d1e49-ac9f-ee86-7e9d-74f79744268b@suse.com/mbox/"},{"id":15469,"url":"https://patchwork.plctlab.org/api/1.2/patches/15469/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c1913bf6-7328-e45f-69f1-20da1954af43@suse.com/","msgid":"","list_archive_url":null,"date":"2022-11-04T10:53:52","name":"[v6,6/7] x86: drop (now) stray IsString","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c1913bf6-7328-e45f-69f1-20da1954af43@suse.com/mbox/"},{"id":15471,"url":"https://patchwork.plctlab.org/api/1.2/patches/15471/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2baf6a9d-c1bf-660d-bbca-99b1604f5478@suse.com/","msgid":"<2baf6a9d-c1bf-660d-bbca-99b1604f5478@suse.com>","list_archive_url":null,"date":"2022-11-04T10:54:30","name":"[v6,7/7] x86: further re-work insn/suffix recognition to also cover MOVSX","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2baf6a9d-c1bf-660d-bbca-99b1604f5478@suse.com/mbox/"},{"id":15472,"url":"https://patchwork.plctlab.org/api/1.2/patches/15472/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104110132.694984-1-aburgess@redhat.com/","msgid":"<20221104110132.694984-1-aburgess@redhat.com>","list_archive_url":null,"date":"2022-11-04T11:01:32","name":"[PUSHED] opcodes/arm: silence compiler warning about uninitialized variable use","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104110132.694984-1-aburgess@redhat.com/mbox/"},{"id":15473,"url":"https://patchwork.plctlab.org/api/1.2/patches/15473/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104110214.129095-1-christophe.lyon@arm.com/","msgid":"<20221104110214.129095-1-christophe.lyon@arm.com>","list_archive_url":null,"date":"2022-11-04T11:02:14","name":"configure: require libzstd >= 1.4.0","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104110214.129095-1-christophe.lyon@arm.com/mbox/"},{"id":15485,"url":"https://patchwork.plctlab.org/api/1.2/patches/15485/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104115038.8957-1-nelson@rivosinc.com/","msgid":"<20221104115038.8957-1-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-11-04T11:50:37","name":"[1/2] RISC-V: File-level architecture shouldn'\''t be affected by section-level ones.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104115038.8957-1-nelson@rivosinc.com/mbox/"},{"id":15486,"url":"https://patchwork.plctlab.org/api/1.2/patches/15486/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104115038.8957-2-nelson@rivosinc.com/","msgid":"<20221104115038.8957-2-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-11-04T11:50:38","name":"[2/2] RISC-V: Clarify the suppress rule of mapping symbol with architecture string.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104115038.8957-2-nelson@rivosinc.com/mbox/"},{"id":15509,"url":"https://patchwork.plctlab.org/api/1.2/patches/15509/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/cc133c88-9ce9-5e3a-a8f7-ad72766862b9@suse.com/","msgid":"","list_archive_url":null,"date":"2022-11-04T13:12:07","name":"x86: adjust recently introduced testcases","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/cc133c88-9ce9-5e3a-a8f7-ad72766862b9@suse.com/mbox/"},{"id":15679,"url":"https://patchwork.plctlab.org/api/1.2/patches/15679/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104163328.2274371-1-chigot@adacore.com/","msgid":"<20221104163328.2274371-1-chigot@adacore.com>","list_archive_url":null,"date":"2022-11-04T16:33:28","name":"ld/testsuite: skip tests related to -shared when disabled","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104163328.2274371-1-chigot@adacore.com/mbox/"},{"id":15751,"url":"https://patchwork.plctlab.org/api/1.2/patches/15751/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104190216.1352855-1-indu.bhagat@oracle.com/","msgid":"<20221104190216.1352855-1-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-04T19:02:16","name":"[V3.1,11/15] libctf: add libsframe to LDFLAGS and LIBS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104190216.1352855-1-indu.bhagat@oracle.com/mbox/"},{"id":15792,"url":"https://patchwork.plctlab.org/api/1.2/patches/15792/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104205547.3728827-1-hjl.tools@gmail.com/","msgid":"<20221104205547.3728827-1-hjl.tools@gmail.com>","list_archive_url":null,"date":"2022-11-04T20:55:47","name":"i386: Check invalid (%dx) usage","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104205547.3728827-1-hjl.tools@gmail.com/mbox/"},{"id":15794,"url":"https://patchwork.plctlab.org/api/1.2/patches/15794/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104210134.1721620-1-indu.bhagat@oracle.com/","msgid":"<20221104210134.1721620-1-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-04T21:01:34","name":"[V3.2,11/15] libctf: add libsframe to LDFLAGS and LIBS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104210134.1721620-1-indu.bhagat@oracle.com/mbox/"},{"id":15959,"url":"https://patchwork.plctlab.org/api/1.2/patches/15959/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c620070e3e335df2b487d3836e20d251dac37525.1667651354.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-11-05T12:29:07","name":"[01/12] RISC-V: Remove unnecessary empty matching file","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c620070e3e335df2b487d3836e20d251dac37525.1667651354.git.research_trasio@irq.a4lg.com/mbox/"},{"id":15961,"url":"https://patchwork.plctlab.org/api/1.2/patches/15961/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4496235002a396043598ab9755bd8eda5c077b1f.1667651354.git.research_trasio@irq.a4lg.com/","msgid":"<4496235002a396043598ab9755bd8eda5c077b1f.1667651354.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-05T12:29:08","name":"[02/12] RISC-V: Tidy disassembler corner case tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4496235002a396043598ab9755bd8eda5c077b1f.1667651354.git.research_trasio@irq.a4lg.com/mbox/"},{"id":15960,"url":"https://patchwork.plctlab.org/api/1.2/patches/15960/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a9229a2798480f00bf12ac3c435b3ef57f867022.1667651354.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-11-05T12:29:09","name":"[03/12] RISC-V: Tidying related to '\''Zfinx'\'' disassembler test","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a9229a2798480f00bf12ac3c435b3ef57f867022.1667651354.git.research_trasio@irq.a4lg.com/mbox/"},{"id":15962,"url":"https://patchwork.plctlab.org/api/1.2/patches/15962/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6a020edd0e114a003edbaafe1088a040e9fa07e7.1667651354.git.research_trasio@irq.a4lg.com/","msgid":"<6a020edd0e114a003edbaafe1088a040e9fa07e7.1667651354.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-05T12:29:10","name":"[04/12] RISC-V: GAS: Add basic shared test utilities","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6a020edd0e114a003edbaafe1088a040e9fa07e7.1667651354.git.research_trasio@irq.a4lg.com/mbox/"},{"id":15966,"url":"https://patchwork.plctlab.org/api/1.2/patches/15966/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6fc2851a4161edc429089bd2bbd9c2bb4c0c118f.1667651354.git.research_trasio@irq.a4lg.com/","msgid":"<6fc2851a4161edc429089bd2bbd9c2bb4c0c118f.1667651354.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-05T12:29:11","name":"[05/12] RISC-V: Redefine \"nop\" test","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6fc2851a4161edc429089bd2bbd9c2bb4c0c118f.1667651354.git.research_trasio@irq.a4lg.com/mbox/"},{"id":15963,"url":"https://patchwork.plctlab.org/api/1.2/patches/15963/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7311ed3d2429000e18877d7af594890da170a7a3.1667651354.git.research_trasio@irq.a4lg.com/","msgid":"<7311ed3d2429000e18877d7af594890da170a7a3.1667651354.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-05T12:29:12","name":"[06/12] RISC-V: Reorganize/enhance {sign, zero}-extension instructions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7311ed3d2429000e18877d7af594890da170a7a3.1667651354.git.research_trasio@irq.a4lg.com/mbox/"},{"id":15968,"url":"https://patchwork.plctlab.org/api/1.2/patches/15968/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ac99c9696c156207f06c18f2d6bf423c96c5876b.1667651354.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-11-05T12:29:13","name":"[07/12] RISC-V: Combine complex extension error handling tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ac99c9696c156207f06c18f2d6bf423c96c5876b.1667651354.git.research_trasio@irq.a4lg.com/mbox/"},{"id":15970,"url":"https://patchwork.plctlab.org/api/1.2/patches/15970/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9378b9505e3e230e0a690c56e67d253e2a0f5864.1667651354.git.research_trasio@irq.a4lg.com/","msgid":"<9378b9505e3e230e0a690c56e67d253e2a0f5864.1667651354.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-05T12:29:14","name":"[08/12] RISC-V: Refine/enhance '\''M'\''/'\''Zmmul'\'' extension tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9378b9505e3e230e0a690c56e67d253e2a0f5864.1667651354.git.research_trasio@irq.a4lg.com/mbox/"},{"id":15964,"url":"https://patchwork.plctlab.org/api/1.2/patches/15964/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/82832a67f240d5857fd502d4b74fd7d841ee2d6e.1667651354.git.research_trasio@irq.a4lg.com/","msgid":"<82832a67f240d5857fd502d4b74fd7d841ee2d6e.1667651354.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-05T12:29:15","name":"[09/12] RISC-V: Combine/enhance '\''Zicbo[mz]'\'' extension tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/82832a67f240d5857fd502d4b74fd7d841ee2d6e.1667651354.git.research_trasio@irq.a4lg.com/mbox/"},{"id":15965,"url":"https://patchwork.plctlab.org/api/1.2/patches/15965/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9c47e59868a64b13e5a7bb487e3619d4f1497d78.1667651354.git.research_trasio@irq.a4lg.com/","msgid":"<9c47e59868a64b13e5a7bb487e3619d4f1497d78.1667651354.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-05T12:29:16","name":"[10/12] RISC-V: Enhance '\''Zicbop'\'' testcases","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9c47e59868a64b13e5a7bb487e3619d4f1497d78.1667651354.git.research_trasio@irq.a4lg.com/mbox/"},{"id":15967,"url":"https://patchwork.plctlab.org/api/1.2/patches/15967/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2d9befc5bc5eed80b6bd7da6d092a61b1162ecac.1667651354.git.research_trasio@irq.a4lg.com/","msgid":"<2d9befc5bc5eed80b6bd7da6d092a61b1162ecac.1667651354.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-05T12:29:17","name":"[11/12] RISC-V: Reorganize/enhance '\''Zb*'\'' extension tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2d9befc5bc5eed80b6bd7da6d092a61b1162ecac.1667651354.git.research_trasio@irq.a4lg.com/mbox/"},{"id":15969,"url":"https://patchwork.plctlab.org/api/1.2/patches/15969/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f1c5589ab606b74eeac98e3dafd4a7903450d3b2.1667651354.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-11-05T12:29:18","name":"[12/12] RISC-V: Combine/enhance '\''Zk*'\''/'\''Zbk*'\'' extension tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f1c5589ab606b74eeac98e3dafd4a7903450d3b2.1667651354.git.research_trasio@irq.a4lg.com/mbox/"},{"id":16066,"url":"https://patchwork.plctlab.org/api/1.2/patches/16066/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221106053640.1649752-1-indu.bhagat@oracle.com/","msgid":"<20221106053640.1649752-1-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-06T05:36:40","name":"[V3.1,03/15] gas: generate .sframe from CFI directives","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221106053640.1649752-1-indu.bhagat@oracle.com/mbox/"},{"id":16379,"url":"https://patchwork.plctlab.org/api/1.2/patches/16379/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221107112805.3332619-1-och95@yandex.ru/","msgid":"<20221107112805.3332619-1-och95@yandex.ru>","list_archive_url":null,"date":"2022-11-07T11:28:05","name":"gold/aarch64: Fix adrp distance check","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221107112805.3332619-1-och95@yandex.ru/mbox/"},{"id":16400,"url":"https://patchwork.plctlab.org/api/1.2/patches/16400/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221107124620.1271470-1-christoph.muellner@vrull.eu/","msgid":"<20221107124620.1271470-1-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2022-11-07T12:46:20","name":"RISC-V: xtheadfmemidx: Use fp register in mnemonics","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221107124620.1271470-1-christoph.muellner@vrull.eu/mbox/"},{"id":16594,"url":"https://patchwork.plctlab.org/api/1.2/patches/16594/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/CACVBkZ+kM2xcpwk5zHQ4bqDV7dbPjZ6cMU9tR-h62+tDTgi3Tw@mail.gmail.com/","msgid":"","list_archive_url":null,"date":"2022-11-07T17:53:35","name":"GAS fix section alignment for aarch64-pe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/CACVBkZ+kM2xcpwk5zHQ4bqDV7dbPjZ6cMU9tR-h62+tDTgi3Tw@mail.gmail.com/mbox/"},{"id":16744,"url":"https://patchwork.plctlab.org/api/1.2/patches/16744/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221107222809.924195-1-indu.bhagat@oracle.com/","msgid":"<20221107222809.924195-1-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-07T22:28:09","name":"[V3.3,11/15] libctf: add libsframe to LDFLAGS and LIBS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221107222809.924195-1-indu.bhagat@oracle.com/mbox/"},{"id":16797,"url":"https://patchwork.plctlab.org/api/1.2/patches/16797/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221108012556.66467-1-haochen.jiang@intel.com/","msgid":"<20221108012556.66467-1-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-11-08T01:25:56","name":"x86: Correct wrong comments in vex_w_table","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221108012556.66467-1-haochen.jiang@intel.com/mbox/"},{"id":16884,"url":"https://patchwork.plctlab.org/api/1.2/patches/16884/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221108054530.796968-1-markus.t.metzger@intel.com/","msgid":"<20221108054530.796968-1-markus.t.metzger@intel.com>","list_archive_url":null,"date":"2022-11-08T05:45:29","name":"[1/2] gprofng: make cpu identification available to others","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221108054530.796968-1-markus.t.metzger@intel.com/mbox/"},{"id":16885,"url":"https://patchwork.plctlab.org/api/1.2/patches/16885/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221108054530.796968-2-markus.t.metzger@intel.com/","msgid":"<20221108054530.796968-2-markus.t.metzger@intel.com>","list_archive_url":null,"date":"2022-11-08T05:45:30","name":"[2/2] gdb, btrace: use cpuident.h to implement btrace_this_cpu","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221108054530.796968-2-markus.t.metzger@intel.com/mbox/"},{"id":16995,"url":"https://patchwork.plctlab.org/api/1.2/patches/16995/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ea0daf08-4923-ebfa-dcfe-699c43d63822@suse.com/","msgid":"","list_archive_url":null,"date":"2022-11-08T11:29:40","name":"x86/Intel: don'\''t accept malformed EXTRQ / INSERTQ","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ea0daf08-4923-ebfa-dcfe-699c43d63822@suse.com/mbox/"},{"id":17057,"url":"https://patchwork.plctlab.org/api/1.2/patches/17057/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221108141352.6613-1-jwilk@jwilk.net/","msgid":"<20221108141352.6613-1-jwilk@jwilk.net>","list_archive_url":null,"date":"2022-11-08T14:13:52","name":"Fix typos in the list of objdump options","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221108141352.6613-1-jwilk@jwilk.net/mbox/"},{"id":17117,"url":"https://patchwork.plctlab.org/api/1.2/patches/17117/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1667924955-9218-1-git-send-email-apinski@marvell.com/","msgid":"<1667924955-9218-1-git-send-email-apinski@marvell.com>","list_archive_url":null,"date":"2022-11-08T16:29:15","name":"Use toplevel configure for GMP and MPFR for gdb","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1667924955-9218-1-git-send-email-apinski@marvell.com/mbox/"},{"id":17160,"url":"https://patchwork.plctlab.org/api/1.2/patches/17160/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/27382086-397f-060f-6cf6-c1d36ff6b812@linux.ibm.com/","msgid":"<27382086-397f-060f-6cf6-c1d36ff6b812@linux.ibm.com>","list_archive_url":null,"date":"2022-11-08T18:23:32","name":"[COMMITTED] PowerPC: Add XSP operand define","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/27382086-397f-060f-6cf6-c1d36ff6b812@linux.ibm.com/mbox/"},{"id":17202,"url":"https://patchwork.plctlab.org/api/1.2/patches/17202/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221108192248.1622627-1-indu.bhagat@oracle.com/","msgid":"<20221108192248.1622627-1-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-08T19:22:48","name":"libctf: use libtool for link test in configure","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221108192248.1622627-1-indu.bhagat@oracle.com/mbox/"},{"id":17262,"url":"https://patchwork.plctlab.org/api/1.2/patches/17262/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221108225030.371817-1-hjl.tools@gmail.com/","msgid":"<20221108225030.371817-1-hjl.tools@gmail.com>","list_archive_url":null,"date":"2022-11-08T22:50:30","name":"ld: Always output local symbol for relocatable link","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221108225030.371817-1-hjl.tools@gmail.com/mbox/"},{"id":17399,"url":"https://patchwork.plctlab.org/api/1.2/patches/17399/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-2-indu.bhagat@oracle.com/","msgid":"<20221109084244.261296-2-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-09T08:42:34","name":"[V4,01/11] sframe.h: Add SFrame format definition","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-2-indu.bhagat@oracle.com/mbox/"},{"id":17398,"url":"https://patchwork.plctlab.org/api/1.2/patches/17398/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-3-indu.bhagat@oracle.com/","msgid":"<20221109084244.261296-3-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-09T08:42:35","name":"[V4,02/11] gas: add new command line option --gsframe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-3-indu.bhagat@oracle.com/mbox/"},{"id":17400,"url":"https://patchwork.plctlab.org/api/1.2/patches/17400/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-4-indu.bhagat@oracle.com/","msgid":"<20221109084244.261296-4-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-09T08:42:36","name":"[V4,03/11] gas: generate .sframe from CFI directives","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-4-indu.bhagat@oracle.com/mbox/"},{"id":17403,"url":"https://patchwork.plctlab.org/api/1.2/patches/17403/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-5-indu.bhagat@oracle.com/","msgid":"<20221109084244.261296-5-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-09T08:42:37","name":"[V4,04/11] gas: testsuite: add new tests for SFrame unwind info","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-5-indu.bhagat@oracle.com/mbox/"},{"id":17407,"url":"https://patchwork.plctlab.org/api/1.2/patches/17407/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-6-indu.bhagat@oracle.com/","msgid":"<20221109084244.261296-6-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-09T08:42:38","name":"[V4,05/11] libsframe: add the SFrame library","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-6-indu.bhagat@oracle.com/mbox/"},{"id":17406,"url":"https://patchwork.plctlab.org/api/1.2/patches/17406/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-7-indu.bhagat@oracle.com/","msgid":"<20221109084244.261296-7-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-09T08:42:39","name":"[V4,06/11] bfd: linker: merge .sframe sections","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-7-indu.bhagat@oracle.com/mbox/"},{"id":17402,"url":"https://patchwork.plctlab.org/api/1.2/patches/17402/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-8-indu.bhagat@oracle.com/","msgid":"<20221109084244.261296-8-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-09T08:42:40","name":"[V4,07/11] readelf/objdump: support for SFrame section","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-8-indu.bhagat@oracle.com/mbox/"},{"id":17401,"url":"https://patchwork.plctlab.org/api/1.2/patches/17401/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-9-indu.bhagat@oracle.com/","msgid":"<20221109084244.261296-9-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-09T08:42:41","name":"[V4,08/11] src-release.sh: Add libsframe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-9-indu.bhagat@oracle.com/mbox/"},{"id":17404,"url":"https://patchwork.plctlab.org/api/1.2/patches/17404/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-10-indu.bhagat@oracle.com/","msgid":"<20221109084244.261296-10-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-09T08:42:42","name":"[V4,09/11] binutils/NEWS: add text for SFrame support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-10-indu.bhagat@oracle.com/mbox/"},{"id":17405,"url":"https://patchwork.plctlab.org/api/1.2/patches/17405/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-11-indu.bhagat@oracle.com/","msgid":"<20221109084244.261296-11-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-09T08:42:43","name":"[V4,10/11] gas/NEWS: add text about new command line option and SFrame support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-11-indu.bhagat@oracle.com/mbox/"}],"public":true,"mbox":"https://patchwork.plctlab.org/bundle/patchwork-bot/binutils-gdb_2022-11/mbox/"}]' + bundle_id=9 + git-pw bundle add 9 17418 +------------+-----------------------------------------------------------------------------------------------------------+ | Property | Value | |------------+-----------------------------------------------------------------------------------------------------------| | ID | 9 | | Name | binutils-gdb_2022-11 | | URL | https://patchwork.plctlab.org/bundle/patchwork-bot/binutils-gdb_2022-11/ | | Owner | patchwork-bot | | Project | binutils-gdb | | Public | True | | Patches | 13337 x86: Silence GCC 12 warning on tc-i386.c | | | 13350 x86: simplify expressions in update_imm() | | | 13487 binutils: Run PR binutils/26160 test | | | 13621 [PUSHED] opcodes/arm: silence compiler warning about uninitialized variable use | | | 13628 [PUSHED] opcodes/arm: don't pass non-string literal to printf like function | | | 13747 [Binutils-2.39,backport,GAS] arm: Use DWARF numbering convention for pseudo-register representation | | | 13993 ld: Add module information substream to PDB files | | | 14028 [committed] RISC-V: Fixed the missing $x+arch when adding odd paddings for alignment. | | | 14043 gas/doc/internals.texi: fix typo | | | 14069 [v2] Support multiple .eh_frame sections | | | 14409 arm: PR 29739 Fix typo where '; ' should not have been replaced with '@' | | | 14588 [v3] Support multiple .eh_frame sections | | | 14602 [v2] ld: Add module information substream to PDB files | | | 14706 [opcodes/arm] Fix potential null pointer dereferences | | | 14840 [REVIEW,ONLY,1/2] NEAR-RATIFICATION RISC-V: Add 'Ssstateen' extension and its CSRs | | | 14841 [REVIEW,ONLY,2/2] NEAR-RATIFICATION RISC-V: Add platform property/capability extensions | | | 14894 [1/2] opcodes/mips: use .word/.short for undefined instructions | | | 14893 [2/2] libopcodes/mips: add support for disassembler styling | | | 15465 [v6,1/7] x86: constify parse_insn()'s input | | | 15466 [v6,2/7] x86: re-work insn/suffix recognition | | | 15467 [v6,3/7] ix86: don't recognize/derive Q suffix in the common case | | | 15468 [v6,4/7] x86-64: allow HLE store of accumulator to absolute 32-bit address | | | 15470 [v6,5/7] x86: move bad-use-of-TLS-reloc check | | | 15469 [v6,6/7] x86: drop (now) stray IsString | | | 15471 [v6,7/7] x86: further re-work insn/suffix recognition to also cover MOVSX | | | 15472 [PUSHED] opcodes/arm: silence compiler warning about uninitialized variable use | | | 15473 configure: require libzstd >= 1.4.0 | | | 15485 [1/2] RISC-V: File-level architecture shouldn't be affected by section-level ones. | | | 15486 [2/2] RISC-V: Clarify the suppress rule of mapping symbol with architecture string. | | | 15509 x86: adjust recently introduced testcases | | | 15679 ld/testsuite: skip tests related to -shared when disabled | | | 15751 [V3.1,11/15] libctf: add libsframe to LDFLAGS and LIBS | | | 15792 i386: Check invalid (%dx) usage | | | 15794 [V3.2,11/15] libctf: add libsframe to LDFLAGS and LIBS | | | 15959 [01/12] RISC-V: Remove unnecessary empty matching file | | | 15961 [02/12] RISC-V: Tidy disassembler corner case tests | | | 15960 [03/12] RISC-V: Tidying related to 'Zfinx' disassembler test | | | 15962 [04/12] RISC-V: GAS: Add basic shared test utilities | | | 15966 [05/12] RISC-V: Redefine "nop" test | | | 15963 [06/12] RISC-V: Reorganize/enhance {sign, zero}-extension instructions | | | 15968 [07/12] RISC-V: Combine complex extension error handling tests | | | 15970 [08/12] RISC-V: Refine/enhance 'M'/'Zmmul' extension tests | | | 15964 [09/12] RISC-V: Combine/enhance 'Zicbo[mz]' extension tests | | | 15965 [10/12] RISC-V: Enhance 'Zicbop' testcases | | | 15967 [11/12] RISC-V: Reorganize/enhance 'Zb*' extension tests | | | 15969 [12/12] RISC-V: Combine/enhance 'Zk*'/'Zbk*' extension tests | | | 16066 [V3.1,03/15] gas: generate .sframe from CFI directives | | | 16379 gold/aarch64: Fix adrp distance check | | | 16400 RISC-V: xtheadfmemidx: Use fp register in mnemonics | | | 16594 GAS fix section alignment for aarch64-pe | | | 16744 [V3.3,11/15] libctf: add libsframe to LDFLAGS and LIBS | | | 16797 x86: Correct wrong comments in vex_w_table | | | 16884 [1/2] gprofng: make cpu identification available to others | | | 16885 [2/2] gdb, btrace: use cpuident.h to implement btrace_this_cpu | | | 16995 x86/Intel: don't accept malformed EXTRQ / INSERTQ | | | 17057 Fix typos in the list of objdump options | | | 17117 Use toplevel configure for GMP and MPFR for gdb | | | 17160 [COMMITTED] PowerPC: Add XSP operand define | | | 17202 libctf: use libtool for link test in configure | | | 17262 ld: Always output local symbol for relocatable link | | | 17399 [V4,01/11] sframe.h: Add SFrame format definition | | | 17398 [V4,02/11] gas: add new command line option --gsframe | | | 17400 [V4,03/11] gas: generate .sframe from CFI directives | | | 17403 [V4,04/11] gas: testsuite: add new tests for SFrame unwind info | | | 17407 [V4,05/11] libsframe: add the SFrame library | | | 17406 [V4,06/11] bfd: linker: merge .sframe sections | | | 17402 [V4,07/11] readelf/objdump: support for SFrame section | | | 17401 [V4,08/11] src-release.sh: Add libsframe | | | 17404 [V4,09/11] binutils/NEWS: add text for SFrame support | | | 17405 [V4,10/11] gas/NEWS: add text about new command line option and SFrame support | | | 17418 [V4,11/11] doc: add SFrame spec file | +------------+-----------------------------------------------------------------------------------------------------------+ + git config pull.rebase false + git fetch origin master From github.com:plctlab/patchwork-binutils-gdb * branch master -> FETCH_HEAD + git checkout master Switched to a new branch 'master' branch 'master' set up to track 'origin/master'. + git pull origin master From github.com:plctlab/patchwork-binutils-gdb * branch master -> FETCH_HEAD Already up to date. + git fetch origin upstream-master From github.com:plctlab/patchwork-binutils-gdb * branch upstream-master -> FETCH_HEAD + git checkout upstream-master Switched to a new branch 'upstream-master' branch 'upstream-master' set up to track 'origin/upstream-master'. + git remote add upstream https://sourceware.org/git/binutils-gdb.git + git pull upstream master From https://sourceware.org/git/binutils-gdb * branch master -> FETCH_HEAD * [new branch] master -> upstream/master Already up to date. + git push -u origin upstream-master Everything up-to-date branch 'upstream-master' set up to track 'origin/upstream-master'. + git checkout master Switched to branch 'master' Your branch is up to date with 'origin/master'. + git merge upstream-master Already up to date. + git push -u origin master Everything up-to-date branch 'master' set up to track 'origin/master'. + branchname=series6804-patch17418 ++ git branch -a ++ grep 'series6804-patch17418$' + checkbranch= + checkbranchresult=null + '[' null = series6804-patch17418 ']' + git checkout -b series6804-patch17418 Switched to a new branch 'series6804-patch17418' ++ curl https://patchwork.plctlab.org/api/1.2/series/6804/ % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 6726 100 6726 0 0 218k 0 --:--:-- --:--:-- --:--:-- 218k + series_response='{"id":6804,"url":"https://patchwork.plctlab.org/api/1.2/series/6804/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/list/?series=6804","project":{"id":2,"url":"https://patchwork.plctlab.org/api/1.2/projects/2/","name":"binutils-gdb","link_name":"binutils-gdb","list_id":"binutils.sourceware.org","list_email":"binutils@sourceware.org","web_url":"https://github.com/wangliu-iscas/Patchwork-Bundles/blob/main/binutils-gdb.md","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"name":"Definition and support for SFrame unwind format","date":"2022-11-09T08:42:33","submitter":{"id":35,"url":"https://patchwork.plctlab.org/api/1.2/people/35/","name":"Indu Bhagat","email":"indu.bhagat@oracle.com"},"version":4,"total":11,"received_total":11,"received_all":true,"mbox":"https://patchwork.plctlab.org/series/6804/mbox/","cover_letter":{"id":1374,"url":"https://patchwork.plctlab.org/api/1.2/covers/1374/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/cover/20221109084244.261296-1-indu.bhagat@oracle.com/","msgid":"<20221109084244.261296-1-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-09T08:42:33","name":"[V4,00/11] Definition and support for SFrame unwind format","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/cover/20221109084244.261296-1-indu.bhagat@oracle.com/mbox/"},"patches":[{"id":17399,"url":"https://patchwork.plctlab.org/api/1.2/patches/17399/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-2-indu.bhagat@oracle.com/","msgid":"<20221109084244.261296-2-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-09T08:42:34","name":"[V4,01/11] sframe.h: Add SFrame format definition","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-2-indu.bhagat@oracle.com/mbox/"},{"id":17398,"url":"https://patchwork.plctlab.org/api/1.2/patches/17398/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-3-indu.bhagat@oracle.com/","msgid":"<20221109084244.261296-3-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-09T08:42:35","name":"[V4,02/11] gas: add new command line option --gsframe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-3-indu.bhagat@oracle.com/mbox/"},{"id":17400,"url":"https://patchwork.plctlab.org/api/1.2/patches/17400/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-4-indu.bhagat@oracle.com/","msgid":"<20221109084244.261296-4-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-09T08:42:36","name":"[V4,03/11] gas: generate .sframe from CFI directives","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-4-indu.bhagat@oracle.com/mbox/"},{"id":17403,"url":"https://patchwork.plctlab.org/api/1.2/patches/17403/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-5-indu.bhagat@oracle.com/","msgid":"<20221109084244.261296-5-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-09T08:42:37","name":"[V4,04/11] gas: testsuite: add new tests for SFrame unwind info","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-5-indu.bhagat@oracle.com/mbox/"},{"id":17407,"url":"https://patchwork.plctlab.org/api/1.2/patches/17407/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-6-indu.bhagat@oracle.com/","msgid":"<20221109084244.261296-6-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-09T08:42:38","name":"[V4,05/11] libsframe: add the SFrame library","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-6-indu.bhagat@oracle.com/mbox/"},{"id":17406,"url":"https://patchwork.plctlab.org/api/1.2/patches/17406/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-7-indu.bhagat@oracle.com/","msgid":"<20221109084244.261296-7-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-09T08:42:39","name":"[V4,06/11] bfd: linker: merge .sframe sections","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-7-indu.bhagat@oracle.com/mbox/"},{"id":17402,"url":"https://patchwork.plctlab.org/api/1.2/patches/17402/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-8-indu.bhagat@oracle.com/","msgid":"<20221109084244.261296-8-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-09T08:42:40","name":"[V4,07/11] readelf/objdump: support for SFrame section","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-8-indu.bhagat@oracle.com/mbox/"},{"id":17401,"url":"https://patchwork.plctlab.org/api/1.2/patches/17401/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-9-indu.bhagat@oracle.com/","msgid":"<20221109084244.261296-9-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-09T08:42:41","name":"[V4,08/11] src-release.sh: Add libsframe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-9-indu.bhagat@oracle.com/mbox/"},{"id":17404,"url":"https://patchwork.plctlab.org/api/1.2/patches/17404/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-10-indu.bhagat@oracle.com/","msgid":"<20221109084244.261296-10-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-09T08:42:42","name":"[V4,09/11] binutils/NEWS: add text for SFrame support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-10-indu.bhagat@oracle.com/mbox/"},{"id":17405,"url":"https://patchwork.plctlab.org/api/1.2/patches/17405/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-11-indu.bhagat@oracle.com/","msgid":"<20221109084244.261296-11-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-09T08:42:43","name":"[V4,10/11] gas/NEWS: add text about new command line option and SFrame support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-11-indu.bhagat@oracle.com/mbox/"},{"id":17418,"url":"https://patchwork.plctlab.org/api/1.2/patches/17418/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-12-indu.bhagat@oracle.com/","msgid":"<20221109084244.261296-12-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-09T08:42:44","name":"[V4,11/11] doc: add SFrame spec file","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-12-indu.bhagat@oracle.com/mbox/"}]}' ++ echo '{"id":6804,"url":"https://patchwork.plctlab.org/api/1.2/series/6804/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/list/?series=6804","project":{"id":2,"url":"https://patchwork.plctlab.org/api/1.2/projects/2/","name":"binutils-gdb","link_name":"binutils-gdb","list_id":"binutils.sourceware.org","list_email":"binutils@sourceware.org","web_url":"https://github.com/wangliu-iscas/Patchwork-Bundles/blob/main/binutils-gdb.md","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"name":"Definition and support for SFrame unwind format","date":"2022-11-09T08:42:33","submitter":{"id":35,"url":"https://patchwork.plctlab.org/api/1.2/people/35/","name":"Indu Bhagat","email":"indu.bhagat@oracle.com"},"version":4,"total":11,"received_total":11,"received_all":true,"mbox":"https://patchwork.plctlab.org/series/6804/mbox/","cover_letter":{"id":1374,"url":"https://patchwork.plctlab.org/api/1.2/covers/1374/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/cover/20221109084244.261296-1-indu.bhagat@oracle.com/","msgid":"<20221109084244.261296-1-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-09T08:42:33","name":"[V4,00/11] Definition and support for SFrame unwind format","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/cover/20221109084244.261296-1-indu.bhagat@oracle.com/mbox/"},"patches":[{"id":17399,"url":"https://patchwork.plctlab.org/api/1.2/patches/17399/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-2-indu.bhagat@oracle.com/","msgid":"<20221109084244.261296-2-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-09T08:42:34","name":"[V4,01/11] sframe.h: Add SFrame format definition","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-2-indu.bhagat@oracle.com/mbox/"},{"id":17398,"url":"https://patchwork.plctlab.org/api/1.2/patches/17398/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-3-indu.bhagat@oracle.com/","msgid":"<20221109084244.261296-3-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-09T08:42:35","name":"[V4,02/11] gas: add new command line option --gsframe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-3-indu.bhagat@oracle.com/mbox/"},{"id":17400,"url":"https://patchwork.plctlab.org/api/1.2/patches/17400/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-4-indu.bhagat@oracle.com/","msgid":"<20221109084244.261296-4-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-09T08:42:36","name":"[V4,03/11] gas: generate .sframe from CFI directives","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-4-indu.bhagat@oracle.com/mbox/"},{"id":17403,"url":"https://patchwork.plctlab.org/api/1.2/patches/17403/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-5-indu.bhagat@oracle.com/","msgid":"<20221109084244.261296-5-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-09T08:42:37","name":"[V4,04/11] gas: testsuite: add new tests for SFrame unwind info","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-5-indu.bhagat@oracle.com/mbox/"},{"id":17407,"url":"https://patchwork.plctlab.org/api/1.2/patches/17407/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-6-indu.bhagat@oracle.com/","msgid":"<20221109084244.261296-6-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-09T08:42:38","name":"[V4,05/11] libsframe: add the SFrame library","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-6-indu.bhagat@oracle.com/mbox/"},{"id":17406,"url":"https://patchwork.plctlab.org/api/1.2/patches/17406/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-7-indu.bhagat@oracle.com/","msgid":"<20221109084244.261296-7-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-09T08:42:39","name":"[V4,06/11] bfd: linker: merge .sframe sections","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-7-indu.bhagat@oracle.com/mbox/"},{"id":17402,"url":"https://patchwork.plctlab.org/api/1.2/patches/17402/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-8-indu.bhagat@oracle.com/","msgid":"<20221109084244.261296-8-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-09T08:42:40","name":"[V4,07/11] readelf/objdump: support for SFrame section","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-8-indu.bhagat@oracle.com/mbox/"},{"id":17401,"url":"https://patchwork.plctlab.org/api/1.2/patches/17401/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-9-indu.bhagat@oracle.com/","msgid":"<20221109084244.261296-9-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-09T08:42:41","name":"[V4,08/11] src-release.sh: Add libsframe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-9-indu.bhagat@oracle.com/mbox/"},{"id":17404,"url":"https://patchwork.plctlab.org/api/1.2/patches/17404/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-10-indu.bhagat@oracle.com/","msgid":"<20221109084244.261296-10-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-09T08:42:42","name":"[V4,09/11] binutils/NEWS: add text for SFrame support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-10-indu.bhagat@oracle.com/mbox/"},{"id":17405,"url":"https://patchwork.plctlab.org/api/1.2/patches/17405/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-11-indu.bhagat@oracle.com/","msgid":"<20221109084244.261296-11-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-09T08:42:43","name":"[V4,10/11] gas/NEWS: add text about new command line option and SFrame support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-11-indu.bhagat@oracle.com/mbox/"},{"id":17418,"url":"https://patchwork.plctlab.org/api/1.2/patches/17418/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-12-indu.bhagat@oracle.com/","msgid":"<20221109084244.261296-12-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-09T08:42:44","name":"[V4,11/11] doc: add SFrame spec file","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-12-indu.bhagat@oracle.com/mbox/"}]}' ++ jq '.patches[] | (.id|tostring) + "," + .mbox' + patchid_patchurl='"17399,https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-2-indu.bhagat@oracle.com/mbox/" "17398,https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-3-indu.bhagat@oracle.com/mbox/" "17400,https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-4-indu.bhagat@oracle.com/mbox/" "17403,https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-5-indu.bhagat@oracle.com/mbox/" "17407,https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-6-indu.bhagat@oracle.com/mbox/" "17406,https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-7-indu.bhagat@oracle.com/mbox/" "17402,https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-8-indu.bhagat@oracle.com/mbox/" "17401,https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-9-indu.bhagat@oracle.com/mbox/" "17404,https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-10-indu.bhagat@oracle.com/mbox/" "17405,https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-11-indu.bhagat@oracle.com/mbox/" "17418,https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-12-indu.bhagat@oracle.com/mbox/"' + IFS=, + read -r series_patch_id series_patch_url + echo '"17399,https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-2-indu.bhagat@oracle.com/mbox/" "17398,https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-3-indu.bhagat@oracle.com/mbox/" "17400,https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-4-indu.bhagat@oracle.com/mbox/" "17403,https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-5-indu.bhagat@oracle.com/mbox/" "17407,https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-6-indu.bhagat@oracle.com/mbox/" "17406,https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-7-indu.bhagat@oracle.com/mbox/" "17402,https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-8-indu.bhagat@oracle.com/mbox/" "17401,https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-9-indu.bhagat@oracle.com/mbox/" "17404,https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-10-indu.bhagat@oracle.com/mbox/" "17405,https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-11-indu.bhagat@oracle.com/mbox/" "17418,https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-12-indu.bhagat@oracle.com/mbox/"' ++ echo '"17399' ++ sed 's/"//g' + series_patch_id=17399 ++ echo 'https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-2-indu.bhagat@oracle.com/mbox/"' ++ sed 's/"//g' + series_patch_url=https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-2-indu.bhagat@oracle.com/mbox/ ++ git rev-parse HEAD + commitid_before=2d4989e98ee5e63b76ce3e35b0e02baaee2f50cb + eval '+++ declare -p bout bret declare -- bout="Applying: sframe.h: Add SFrame format definition" declare -- bret="0" ++ berr='\''++++ git_am https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-2-indu.bhagat@oracle.com/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-2-indu.bhagat@oracle.com/mbox/ ++++ curl https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-2-indu.bhagat@oracle.com/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 25341 100 25341 0 0 353k 0 --:--:-- --:--:-- --:--:-- 353k +++ bout='\''\'\'''\''Applying: sframe.h: Add SFrame format definition'\''\'\'''\'' +++ bret=0'\'' ++ declare -p berr declare -- berr="++++ git_am https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-2-indu.bhagat@oracle.com/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-2-indu.bhagat@oracle.com/mbox/ ++++ curl https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-2-indu.bhagat@oracle.com/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 25341 100 25341 0 0 353k 0 --:--:-- --:--:-- --:--:-- 353k +++ bout='\''Applying: sframe.h: Add SFrame format definition'\'' +++ bret=0"' ++ +++ declare -p bout bret /tmp/jenkins9340818698266593740.sh: line 124: +++: command not found ++ declare -- 'bout=Applying: sframe.h: Add SFrame format definition' ++ declare -- bret=0 ++ ++ 'berr=++++ git_am https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-2-indu.bhagat@oracle.com/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-2-indu.bhagat@oracle.com/mbox/ ++++ curl https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-2-indu.bhagat@oracle.com/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 25341 100 25341 0 0 353k 0 --:--:-- --:--:-- --:--:-- 353k +++ bout='\''Applying: sframe.h: Add SFrame format definition'\'' +++ bret=0' /tmp/jenkins9340818698266593740.sh: line 135: ++: command not found ++ ++ declare -p berr /tmp/jenkins9340818698266593740.sh: line 136: ++: command not found ++ declare -- 'berr=++++ git_am https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-2-indu.bhagat@oracle.com/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-2-indu.bhagat@oracle.com/mbox/ ++++ curl https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-2-indu.bhagat@oracle.com/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 25341 100 25341 0 0 353k 0 --:--:-- --:--:-- --:--:-- 353k +++ bout='\''Applying: sframe.h: Add SFrame format definition'\'' +++ bret=0' ++ git rev-parse HEAD + commitid_after=b09404faf097405bbb36dede820b77b97e8cb717 + '[' 0 = 0 ']' + '[' b09404faf097405bbb36dede820b77b97e8cb717 = 2d4989e98ee5e63b76ce3e35b0e02baaee2f50cb ']' + '[' 17399 = 17418 ']' + IFS=, + read -r series_patch_id series_patch_url ++ sed 's/"//g' ++ echo '"17398' + series_patch_id=17398 ++ echo 'https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-3-indu.bhagat@oracle.com/mbox/"' ++ sed 's/"//g' + series_patch_url=https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-3-indu.bhagat@oracle.com/mbox/ ++ git rev-parse HEAD + commitid_before=b09404faf097405bbb36dede820b77b97e8cb717 + eval '+++ declare -p bout bret declare -- bout="Applying: gas: add new command line option --gsframe" declare -- bret="0" ++ berr='\''++++ git_am https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-3-indu.bhagat@oracle.com/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-3-indu.bhagat@oracle.com/mbox/ ++++ curl https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-3-indu.bhagat@oracle.com/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 15144 100 15144 0 0 208k 0 --:--:-- --:--:-- --:--:-- 208k +++ bout='\''\'\'''\''Applying: gas: add new command line option --gsframe'\''\'\'''\'' +++ bret=0'\'' ++ declare -p berr declare -- berr="++++ git_am https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-3-indu.bhagat@oracle.com/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-3-indu.bhagat@oracle.com/mbox/ ++++ curl https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-3-indu.bhagat@oracle.com/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 15144 100 15144 0 0 208k 0 --:--:-- --:--:-- --:--:-- 208k +++ bout='\''Applying: gas: add new command line option --gsframe'\'' +++ bret=0"' ++ +++ declare -p bout bret /tmp/jenkins9340818698266593740.sh: line 124: +++: command not found ++ declare -- 'bout=Applying: gas: add new command line option --gsframe' ++ declare -- bret=0 ++ ++ 'berr=++++ git_am https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-3-indu.bhagat@oracle.com/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-3-indu.bhagat@oracle.com/mbox/ ++++ curl https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-3-indu.bhagat@oracle.com/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 15144 100 15144 0 0 208k 0 --:--:-- --:--:-- --:--:-- 208k +++ bout='\''Applying: gas: add new command line option --gsframe'\'' +++ bret=0' /tmp/jenkins9340818698266593740.sh: line 135: ++: command not found ++ ++ declare -p berr /tmp/jenkins9340818698266593740.sh: line 136: ++: command not found ++ declare -- 'berr=++++ git_am https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-3-indu.bhagat@oracle.com/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-3-indu.bhagat@oracle.com/mbox/ ++++ curl https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-3-indu.bhagat@oracle.com/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 15144 100 15144 0 0 208k 0 --:--:-- --:--:-- --:--:-- 208k +++ bout='\''Applying: gas: add new command line option --gsframe'\'' +++ bret=0' ++ git rev-parse HEAD + commitid_after=1329d3b95b60a3db7cd27334d096fd3b2e61c24c + '[' 0 = 0 ']' + '[' 1329d3b95b60a3db7cd27334d096fd3b2e61c24c = b09404faf097405bbb36dede820b77b97e8cb717 ']' + '[' 17398 = 17418 ']' + IFS=, + read -r series_patch_id series_patch_url ++ sed 's/"//g' ++ echo '"17400' + series_patch_id=17400 ++ echo 'https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-4-indu.bhagat@oracle.com/mbox/"' ++ sed 's/"//g' + series_patch_url=https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-4-indu.bhagat@oracle.com/mbox/ ++ git rev-parse HEAD + commitid_before=1329d3b95b60a3db7cd27334d096fd3b2e61c24c + eval '+++ declare -p bout bret declare -- bout="Applying: gas: generate .sframe from CFI directives" declare -- bret="0" ++ berr='\''++++ git_am https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-4-indu.bhagat@oracle.com/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-4-indu.bhagat@oracle.com/mbox/ ++++ curl https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-4-indu.bhagat@oracle.com/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 84225 100 84225 0 0 2006k 0 --:--:-- --:--:-- --:--:-- 1958k +++ bout='\''\'\'''\''Applying: gas: generate .sframe from CFI directives'\''\'\'''\'' +++ bret=0'\'' ++ declare -p berr declare -- berr="++++ git_am https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-4-indu.bhagat@oracle.com/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-4-indu.bhagat@oracle.com/mbox/ ++++ curl https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-4-indu.bhagat@oracle.com/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 84225 100 84225 0 0 2006k 0 --:--:-- --:--:-- --:--:-- 1958k +++ bout='\''Applying: gas: generate .sframe from CFI directives'\'' +++ bret=0"' ++ +++ declare -p bout bret /tmp/jenkins9340818698266593740.sh: line 124: +++: command not found ++ declare -- 'bout=Applying: gas: generate .sframe from CFI directives' ++ declare -- bret=0 ++ ++ 'berr=++++ git_am https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-4-indu.bhagat@oracle.com/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-4-indu.bhagat@oracle.com/mbox/ ++++ curl https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-4-indu.bhagat@oracle.com/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 84225 100 84225 0 0 2006k 0 --:--:-- --:--:-- --:--:-- 1958k +++ bout='\''Applying: gas: generate .sframe from CFI directives'\'' +++ bret=0' /tmp/jenkins9340818698266593740.sh: line 135: ++: command not found ++ ++ declare -p berr /tmp/jenkins9340818698266593740.sh: line 136: ++: command not found ++ declare -- 'berr=++++ git_am https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-4-indu.bhagat@oracle.com/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-4-indu.bhagat@oracle.com/mbox/ ++++ curl https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-4-indu.bhagat@oracle.com/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 84225 100 84225 0 0 2006k 0 --:--:-- --:--:-- --:--:-- 1958k +++ bout='\''Applying: gas: generate .sframe from CFI directives'\'' +++ bret=0' ++ git rev-parse HEAD + commitid_after=718250a1e323121193b389ec12b9786878811b3e + '[' 0 = 0 ']' + '[' 718250a1e323121193b389ec12b9786878811b3e = 1329d3b95b60a3db7cd27334d096fd3b2e61c24c ']' + '[' 17400 = 17418 ']' + IFS=, + read -r series_patch_id series_patch_url ++ echo '"17403' ++ sed 's/"//g' + series_patch_id=17403 ++ echo 'https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-5-indu.bhagat@oracle.com/mbox/"' ++ sed 's/"//g' + series_patch_url=https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-5-indu.bhagat@oracle.com/mbox/ ++ git rev-parse HEAD + commitid_before=718250a1e323121193b389ec12b9786878811b3e + eval '+++ declare -p bout bret declare -- bout="Applying: gas: testsuite: add new tests for SFrame unwind info" declare -- bret="0" ++ berr='\''++++ git_am https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-5-indu.bhagat@oracle.com/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-5-indu.bhagat@oracle.com/mbox/ ++++ curl https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-5-indu.bhagat@oracle.com/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 38027 100 38027 0 0 523k 0 --:--:-- --:--:-- --:--:-- 530k +++ bout='\''\'\'''\''Applying: gas: testsuite: add new tests for SFrame unwind info'\''\'\'''\'' +++ bret=0'\'' ++ declare -p berr declare -- berr="++++ git_am https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-5-indu.bhagat@oracle.com/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-5-indu.bhagat@oracle.com/mbox/ ++++ curl https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-5-indu.bhagat@oracle.com/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 38027 100 38027 0 0 523k 0 --:--:-- --:--:-- --:--:-- 530k +++ bout='\''Applying: gas: testsuite: add new tests for SFrame unwind info'\'' +++ bret=0"' ++ +++ declare -p bout bret /tmp/jenkins9340818698266593740.sh: line 124: +++: command not found ++ declare -- 'bout=Applying: gas: testsuite: add new tests for SFrame unwind info' ++ declare -- bret=0 ++ ++ 'berr=++++ git_am https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-5-indu.bhagat@oracle.com/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-5-indu.bhagat@oracle.com/mbox/ ++++ curl https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-5-indu.bhagat@oracle.com/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 38027 100 38027 0 0 523k 0 --:--:-- --:--:-- --:--:-- 530k +++ bout='\''Applying: gas: testsuite: add new tests for SFrame unwind info'\'' +++ bret=0' /tmp/jenkins9340818698266593740.sh: line 135: ++: command not found ++ ++ declare -p berr /tmp/jenkins9340818698266593740.sh: line 136: ++: command not found ++ declare -- 'berr=++++ git_am https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-5-indu.bhagat@oracle.com/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-5-indu.bhagat@oracle.com/mbox/ ++++ curl https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-5-indu.bhagat@oracle.com/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 38027 100 38027 0 0 523k 0 --:--:-- --:--:-- --:--:-- 530k +++ bout='\''Applying: gas: testsuite: add new tests for SFrame unwind info'\'' +++ bret=0' ++ git rev-parse HEAD + commitid_after=c57beb8a81262e837ecace544ee553f95f7e62d7 + '[' 0 = 0 ']' + '[' c57beb8a81262e837ecace544ee553f95f7e62d7 = 718250a1e323121193b389ec12b9786878811b3e ']' + '[' 17403 = 17418 ']' + IFS=, + read -r series_patch_id series_patch_url ++ echo '"17407' ++ sed 's/"//g' + series_patch_id=17407 ++ echo 'https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-6-indu.bhagat@oracle.com/mbox/"' ++ sed 's/"//g' + series_patch_url=https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-6-indu.bhagat@oracle.com/mbox/ ++ git rev-parse HEAD + commitid_before=c57beb8a81262e837ecace544ee553f95f7e62d7 + eval '+++ declare -p bout bret declare -- bout="git: apply.c:3717: check_preimage: Assertion \`patch->is_new <= 0'\'' failed." declare -- bret="134" ++ berr='\''++++ git_am https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-6-indu.bhagat@oracle.com/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-6-indu.bhagat@oracle.com/mbox/ ++++ curl https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-6-indu.bhagat@oracle.com/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 270k 100 270k 0 0 3079k 0 --:--:-- --:--:-- --:--:-- 3079k +++ bout='\''\'\'''\''git: apply.c:3717: check_preimage: Assertion `patch->is_new <= 0'\''\'\'''\''\'\''\'\'''\'''\''\'\'''\'' failed.'\''\'\'''\'' +++ bret=134'\'' ++ declare -p berr declare -- berr="++++ git_am https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-6-indu.bhagat@oracle.com/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-6-indu.bhagat@oracle.com/mbox/ ++++ curl https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-6-indu.bhagat@oracle.com/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 270k 100 270k 0 0 3079k 0 --:--:-- --:--:-- --:--:-- 3079k +++ bout='\''git: apply.c:3717: check_preimage: Assertion \`patch->is_new <= 0'\''\\'\'''\'' failed.'\'' +++ bret=134"' ++ +++ declare -p bout bret /tmp/jenkins9340818698266593740.sh: line 124: +++: command not found ++ declare -- 'bout=git: apply.c:3717: check_preimage: Assertion `patch->is_new <= 0'\'' failed.' ++ declare -- bret=134 ++ ++ 'berr=++++ git_am https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-6-indu.bhagat@oracle.com/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-6-indu.bhagat@oracle.com/mbox/ ++++ curl https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-6-indu.bhagat@oracle.com/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 270k 100 270k 0 0 3079k 0 --:--:-- --:--:-- --:--:-- 3079k +++ bout='\''git: apply.c:3717: check_preimage: Assertion `patch->is_new <= 0'\''\'\'''\'' failed.'\'' +++ bret=134' /tmp/jenkins9340818698266593740.sh: line 135: ++: command not found ++ ++ declare -p berr /tmp/jenkins9340818698266593740.sh: line 136: ++: command not found ++ declare -- 'berr=++++ git_am https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-6-indu.bhagat@oracle.com/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-6-indu.bhagat@oracle.com/mbox/ ++++ curl https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-6-indu.bhagat@oracle.com/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 270k 100 270k 0 0 3079k 0 --:--:-- --:--:-- --:--:-- 3079k +++ bout='\''git: apply.c:3717: check_preimage: Assertion `patch->is_new <= 0'\''\'\'''\'' failed.'\'' +++ bret=134' ++ git rev-parse HEAD + commitid_after=c57beb8a81262e837ecace544ee553f95f7e62d7 + '[' 134 = 0 ']' + [[ ++++ git_am https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-6-indu.bhagat@oracle.com/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-6-indu.bhagat@oracle.com/mbox/ ++++ curl https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-6-indu.bhagat@oracle.com/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 270k 100 270k 0 0 3079k 0 --:--:-- --:--:-- --:--:-- 3079k +++ bout='git: apply.c:3717: check_preimage: Assertion `patch->is_new <= 0'\'' failed.' +++ bret=134 =~ sha1 information is lacking or useless ]] + [[ ++++ git_am https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-6-indu.bhagat@oracle.com/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-6-indu.bhagat@oracle.com/mbox/ ++++ curl https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-6-indu.bhagat@oracle.com/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 270k 100 270k 0 0 3079k 0 --:--:-- --:--:-- --:--:-- 3079k +++ bout='git: apply.c:3717: check_preimage: Assertion `patch->is_new <= 0'\'' failed.' +++ bret=134 =~ Failed to merge in the changes ]] + [[ ++++ git_am https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-6-indu.bhagat@oracle.com/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-6-indu.bhagat@oracle.com/mbox/ ++++ curl https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-6-indu.bhagat@oracle.com/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 270k 100 270k 0 0 3079k 0 --:--:-- --:--:-- --:--:-- 3079k +++ bout='git: apply.c:3717: check_preimage: Assertion `patch->is_new <= 0'\'' failed.' +++ bret=134 =~ corrupt patch at ]] + [[ ++++ git_am https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-6-indu.bhagat@oracle.com/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-6-indu.bhagat@oracle.com/mbox/ ++++ curl https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-6-indu.bhagat@oracle.com/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 270k 100 270k 0 0 3079k 0 --:--:-- --:--:-- --:--:-- 3079k +++ bout='git: apply.c:3717: check_preimage: Assertion `patch->is_new <= 0'\'' failed.' +++ bret=134 =~ patch fragment without header at ]] + [[ ++++ git_am https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-6-indu.bhagat@oracle.com/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-6-indu.bhagat@oracle.com/mbox/ ++++ curl https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-6-indu.bhagat@oracle.com/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 270k 100 270k 0 0 3079k 0 --:--:-- --:--:-- --:--:-- 3079k +++ bout='git: apply.c:3717: check_preimage: Assertion `patch->is_new <= 0'\'' failed.' +++ bret=134 =~ No valid patches in input ]] + submit_check fail 'Not Applicable' https://patchwork.plctlab.org/jenkins/job/binutils-gdb/340/consoleText 'Git am fail log' + check_state=fail + patch_state='Not Applicable' + repo_url=https://patchwork.plctlab.org/jenkins/job/binutils-gdb/340/consoleText + DESCRIPTION='Git am fail log' + curl -X POST -H 'Authorization: Token [*******]' -F state=fail -F target_url=https://patchwork.plctlab.org/jenkins/job/binutils-gdb/340/consoleText -F context=binutils-gdb-check -F 'description=Git am fail log' https://patchwork.plctlab.org/api/patches/17418/checks/ % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 969 100 427 100 542 6188 7855 --:--:-- --:--:-- --:--:-- 14043 {"id":1961,"url":"https://patchwork.plctlab.org/api/patches/17418/checks/1961/","user":{"id":1,"url":"https://patchwork.plctlab.org/api/users/1/","username":"snail","first_name":"","last_name":"","email":"wangliu@iscas.ac.cn"},"date":"2022-11-09T09:23:02.771862","state":"fail","target_url":"https://patchwork.plctlab.org/jenkins/job/binutils-gdb/340/consoleText","context":"binutils-gdb-check","description":"Git am fail log"}+ curl -X PATCH -H 'Authorization: Token [*******]' -F 'state=Not Applicable' https://patchwork.plctlab.org/api/1.2/patches/17418/ % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0{"id":17418,"url":"https://patchwork.plctlab.org/api/1.2/patches/17418/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-12-indu.bhagat@oracle.com/","project":{"id":2,"url":"https://patchwork.plctlab.org/api/1.2/projects/2/","name":"binutils-gdb","link_name":"binutils-gdb","list_id":"binutils.sourceware.org","list_email":"binutils@sourceware.org","web_url":"https://github.com/wangliu-iscas/Patchwork-Bundles/blob/main/binutils-gdb.md","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20221109084244.261296-12-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-09T08:42:44","name":"[V4,11/11] doc: add SFrame spec file","commit_ref":null,"pull_url":null,"state":"not-applicable","archived":false,"hash":"a70a34c98cabf9e01877cfb1fae462042f8acd97","submitter":{"id":35,"url":"https://patchwork.plctlab.org/api/1.2/people/35/","name":"Indu Bhagat","email":"indu.bhagat@oracle.com"},"delegate":null,"mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-12-indu.bhagat@oracle.com/mbox/","series":[{"id":6804,"url":"https://patchwork.plctlab.org/api/1.2/series/6804/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/list/?series=6804","date":"2022-11-09T08:42:33","name":"Definition and support for SFrame unwind format","version":4,"mbox":"https://patchwork.plctlab.org/series/6804/mbox/"}],"comments":"https://patchwork.plctlab.org/api/patches/17418/comments/","check":"fail","checks":"https://patchwork.plctlab.org/api/patches/17418/checks/","tags":{},"headers":{"Return-Path":"","Delivered-To":["ouuuleilei@gmail.com","binutils@sourceware.org"],"Received":["by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp229474wru;\n Wed, 9 Nov 2022 01:08:35 -0800 (PST)","from sourceware.org (server2.sourceware.org. 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Please\nregenerate.\n\nChangeLog:\n\n\t* libsframe/Makefile.am: Add info-in-builddir to\n\t AUTOMAKE_OPTIONS. Include doc/local.mk.\n\t* libsframe/Makefile.in: Regenerated.\n\t* libsframe/configure: Likewise. <-- [REMOVED FROM THE PATCH.\n\t PLEASE REGENRATE.]\n\t* libsframe/configure.ac: Check for makeinfo and set BUILD_INFO.\n\t* libsframe/doc/local.mk: New file.\n\t* libsframe/doc/sframe-spec.texi: Likewise.\n---\n libsframe/Makefile.am | 9 +-\n libsframe/Makefile.in | 418 +++++++++++++++++++---\n libsframe/configure.ac | 21 ++\n libsframe/doc/local.mk | 40 +++\n libsframe/doc/sframe-spec.texi | 619 +++++++++++++++++++++++++++++++++\n 5 files changed, 1058 insertions(+), 49 deletions(-)\n create mode 100644 libsframe/doc/local.mk\n create mode 100644 libsframe/doc/sframe-spec.texi","diff":"diff --git a/libsframe/Makefile.am b/libsframe/Makefile.am\nindex d8198a166c5..a976a7e6090 100644\n--- a/libsframe/Makefile.am\n+++ b/libsframe/Makefile.am\n@@ -18,7 +18,12 @@\n #\n ACLOCAL_AMFLAGS = -I .. -I ../config -I ../bfd\n \n-AUTOMAKE_OPTIONS = dejagnu foreign no-texinfo.tex subdir-objects\n+AUTOMAKE_OPTIONS = dejagnu foreign no-texinfo.tex info-in-builddir subdir-objects\n+\n+# Variables that we might accumulate conditionally or in subdirs.\n+info_TEXINFOS =\n+DISTCLEANFILES =\n+MAINTAINERCLEANFILES =\n \n INCDIR = $(srcdir)/../include\n # include libctf for swap.h\n@@ -36,4 +41,6 @@ endif\n libsframe_la_SOURCES = sframe.c sframe-dump.c sframe-error.c\n libsframe_la_CPPFLAGS = $(AM_CPPFLAGS)\n \n+include doc/local.mk\n+\n include testsuite/local.mk\ndiff --git a/libsframe/Makefile.in b/libsframe/Makefile.in\nindex 340bfe88060..8622d8bb688 100644\n--- a/libsframe/Makefile.in\n+++ b/libsframe/Makefile.in\n@@ -14,6 +14,24 @@\n \n @SET_MAKE@\n \n+#\n+# Copyright (C) 2019-2022 Free Software Foundation, Inc.\n+#\n+# This file is free software; you can redistribute it and/or modify\n+# it under the terms of the GNU General Public License as published by\n+# the Free Software Foundation; either version 2 of the License, or\n+# (at your option) any later version.\n+#\n+# This program is distributed in the hope that it will be useful,\n+# but WITHOUT ANY WARRANTY; without even the implied warranty of\n+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n+# GNU General Public License for more details.\n+#\n+# You should have received a copy of the GNU General Public License\n+# along with this program; see the file COPYING. If not see\n+# .\n+#\n+\n \n VPATH = @srcdir@\n am__is_gnu_make = { \\\n@@ -89,8 +107,11 @@ PRE_UNINSTALL = :\n POST_UNINSTALL = :\n build_triplet = @build@\n host_triplet = @host@\n+@BUILD_INFO_TRUE@am__append_1 = doc/sframe-spec.texi\n+@BUILD_INFO_TRUE@am__append_2 = texput.log\n+@BUILD_INFO_TRUE@am__append_3 = doc/sframe-spec.info\n check_PROGRAMS = $(am__EXEEXT_1)\n-@HAVE_COMPAT_DEJAGNU_TRUE@am__append_1 = testsuite/libsframe.decode/be-flipping \\\n+@HAVE_COMPAT_DEJAGNU_TRUE@am__append_4 = testsuite/libsframe.decode/be-flipping \\\n @HAVE_COMPAT_DEJAGNU_TRUE@\ttestsuite/libsframe.decode/frecnt-1 \\\n @HAVE_COMPAT_DEJAGNU_TRUE@\ttestsuite/libsframe.decode/frecnt-2 \\\n @HAVE_COMPAT_DEJAGNU_TRUE@\ttestsuite/libsframe.encode/encode-1\n@@ -145,7 +166,8 @@ am__uninstall_files_from_dir = { \\\n || { echo \" ( cd '$$dir' && rm -f\" $$files \")\"; \\\n $(am__cd) \"$$dir\" && rm -f $$files; }; \\\n }\n-am__installdirs = \"$(DESTDIR)$(libdir)\" \"$(DESTDIR)$(includedir)\"\n+am__installdirs = \"$(DESTDIR)$(libdir)\" \"$(DESTDIR)$(infodir)\" \\\n+\t\"$(DESTDIR)$(includedir)\"\n LTLIBRARIES = $(lib_LTLIBRARIES) $(noinst_LTLIBRARIES)\n libsframe_la_LIBADD =\n am_libsframe_la_OBJECTS = libsframe_la-sframe.lo \\\n@@ -226,6 +248,46 @@ DIST_SOURCES = $(libsframe_la_SOURCES) \\\n \t$(testsuite_libsframe_decode_frecnt_1_SOURCES) \\\n \t$(testsuite_libsframe_decode_frecnt_2_SOURCES) \\\n \t$(testsuite_libsframe_encode_encode_1_SOURCES)\n+AM_V_DVIPS = $(am__v_DVIPS_@AM_V@)\n+am__v_DVIPS_ = $(am__v_DVIPS_@AM_DEFAULT_V@)\n+am__v_DVIPS_0 = @echo \" DVIPS \" $@;\n+am__v_DVIPS_1 = \n+AM_V_MAKEINFO = $(am__v_MAKEINFO_@AM_V@)\n+am__v_MAKEINFO_ = $(am__v_MAKEINFO_@AM_DEFAULT_V@)\n+am__v_MAKEINFO_0 = @echo \" MAKEINFO\" $@;\n+am__v_MAKEINFO_1 = \n+AM_V_INFOHTML = $(am__v_INFOHTML_@AM_V@)\n+am__v_INFOHTML_ = $(am__v_INFOHTML_@AM_DEFAULT_V@)\n+am__v_INFOHTML_0 = @echo \" INFOHTML\" $@;\n+am__v_INFOHTML_1 = \n+AM_V_TEXI2DVI = $(am__v_TEXI2DVI_@AM_V@)\n+am__v_TEXI2DVI_ = $(am__v_TEXI2DVI_@AM_DEFAULT_V@)\n+am__v_TEXI2DVI_0 = @echo \" TEXI2DVI\" $@;\n+am__v_TEXI2DVI_1 = \n+AM_V_TEXI2PDF = $(am__v_TEXI2PDF_@AM_V@)\n+am__v_TEXI2PDF_ = $(am__v_TEXI2PDF_@AM_DEFAULT_V@)\n+am__v_TEXI2PDF_0 = @echo \" TEXI2PDF\" $@;\n+am__v_TEXI2PDF_1 = \n+AM_V_texinfo = $(am__v_texinfo_@AM_V@)\n+am__v_texinfo_ = $(am__v_texinfo_@AM_DEFAULT_V@)\n+am__v_texinfo_0 = -q\n+am__v_texinfo_1 = \n+AM_V_texidevnull = $(am__v_texidevnull_@AM_V@)\n+am__v_texidevnull_ = $(am__v_texidevnull_@AM_DEFAULT_V@)\n+am__v_texidevnull_0 = > /dev/null\n+am__v_texidevnull_1 = \n+INFO_DEPS = doc/sframe-spec.info\n+am__TEXINFO_TEX_DIR = $(srcdir)\n+DVIS = doc/sframe-spec.dvi\n+PDFS = doc/sframe-spec.pdf\n+PSS = doc/sframe-spec.ps\n+HTMLS = doc/sframe-spec.html\n+TEXINFOS = $(am__append_1)\n+TEXI2DVI = texi2dvi\n+TEXI2PDF = $(TEXI2DVI) --pdf --batch\n+MAKEINFOHTML = $(MAKEINFO) --html\n+AM_MAKEINFOHTMLFLAGS = $(AM_MAKEINFOFLAGS)\n+DVIPS = dvips\n am__can_run_installinfo = \\\n case $$AM_UPDATE_INFO_DIR in \\\n n|no|NO) false;; \\\n@@ -258,6 +320,7 @@ AM_RECURSIVE_TARGETS = cscope\n DEJATOOL = $(PACKAGE)\n RUNTESTDEFAULTFLAGS = --tool $$tool --srcdir $$srcdir\n am__DIST_COMMON = $(srcdir)/Makefile.in $(srcdir)/config.h.in \\\n+\t$(srcdir)/doc/local.mk \\\n \t$(srcdir)/testsuite/libsframe.decode/local.mk \\\n \t$(srcdir)/testsuite/libsframe.encode/local.mk \\\n \t$(srcdir)/testsuite/local.mk $(top_srcdir)/../ar-lib \\\n@@ -418,7 +481,12 @@ top_srcdir = @top_srcdir@\n # .\n #\n ACLOCAL_AMFLAGS = -I .. -I ../config -I ../bfd\n-AUTOMAKE_OPTIONS = dejagnu foreign no-texinfo.tex subdir-objects\n+AUTOMAKE_OPTIONS = dejagnu foreign no-texinfo.tex info-in-builddir subdir-objects\n+\n+# Variables that we might accumulate conditionally or in subdirs.\n+info_TEXINFOS = $(am__append_1)\n+DISTCLEANFILES = $(am__append_2)\n+MAINTAINERCLEANFILES = $(am__append_3)\n INCDIR = $(srcdir)/../include\n # include libctf for swap.h\n AM_CPPFLAGS = -I$(srcdir) -I$(srcdir)/../include -I$(srcdir)/../libctf\n@@ -429,6 +497,7 @@ AM_CFLAGS = @ac_libsframe_warn_cflags@\n @INSTALL_LIBBFD_FALSE@noinst_LTLIBRARIES = libsframe.la\n libsframe_la_SOURCES = sframe.c sframe-dump.c sframe-error.c\n libsframe_la_CPPFLAGS = $(AM_CPPFLAGS)\n+@BUILD_INFO_TRUE@AM_MAKEINFOFLAGS = --no-split\n \n # Setup the testing framework\n EXPECT = expect\n@@ -450,10 +519,10 @@ all: config.h\n \t$(MAKE) $(AM_MAKEFLAGS) all-am\n \n .SUFFIXES:\n-.SUFFIXES: .c .lo .o .obj\n+.SUFFIXES: .c .dvi .lo .o .obj .ps\n am--refresh: Makefile\n \t@:\n-$(srcdir)/Makefile.in: @MAINTAINER_MODE_TRUE@ $(srcdir)/Makefile.am $(srcdir)/testsuite/local.mk $(srcdir)/testsuite/libsframe.decode/local.mk $(srcdir)/testsuite/libsframe.encode/local.mk $(am__configure_deps)\n+$(srcdir)/Makefile.in: @MAINTAINER_MODE_TRUE@ $(srcdir)/Makefile.am $(srcdir)/doc/local.mk $(srcdir)/testsuite/local.mk $(srcdir)/testsuite/libsframe.decode/local.mk $(srcdir)/testsuite/libsframe.encode/local.mk $(am__configure_deps)\n \t@for dep in $?; do \\\n \t case '$(am__configure_deps)' in \\\n \t *$$dep*) \\\n@@ -475,7 +544,7 @@ Makefile: $(srcdir)/Makefile.in $(top_builddir)/config.status\n \t echo ' cd $(top_builddir) && $(SHELL) ./config.status $@ $(am__depfiles_maybe)'; \\\n \t cd $(top_builddir) && $(SHELL) ./config.status $@ $(am__depfiles_maybe);; \\\n \tesac;\n-$(srcdir)/testsuite/local.mk $(srcdir)/testsuite/libsframe.decode/local.mk $(srcdir)/testsuite/libsframe.encode/local.mk $(am__empty):\n+$(srcdir)/doc/local.mk $(srcdir)/testsuite/local.mk $(srcdir)/testsuite/libsframe.decode/local.mk $(srcdir)/testsuite/libsframe.encode/local.mk $(am__empty):\n \n $(top_builddir)/config.status: $(top_srcdir)/configure $(CONFIG_STATUS_DEPENDENCIES)\n \t$(SHELL) ./config.status --recheck\n@@ -726,6 +795,145 @@ clean-libtool:\n \n distclean-libtool:\n \t-rm -f libtool config.lt\n+doc/$(am__dirstamp):\n+\t@$(MKDIR_P) doc\n+\t@: > doc/$(am__dirstamp)\n+\n+@BUILD_INFO_TRUE@doc/sframe-spec.info: doc/sframe-spec.texi \n+@BUILD_INFO_TRUE@\t@test -f doc/$(am__dirstamp) || $(MAKE) $(AM_MAKEFLAGS) doc/$(am__dirstamp)\n+@BUILD_INFO_TRUE@\t$(AM_V_MAKEINFO)restore=: && backupdir=\"$(am__leading_dot)am$$$$\" && \\\n+@BUILD_INFO_TRUE@\trm -rf $$backupdir && mkdir $$backupdir && \\\n+@BUILD_INFO_TRUE@\tif ($(MAKEINFO) --version) >/dev/null 2>&1; then \\\n+@BUILD_INFO_TRUE@\t for f in $@ $@-[0-9] $@-[0-9][0-9] $(@:.info=).i[0-9] $(@:.info=).i[0-9][0-9]; do \\\n+@BUILD_INFO_TRUE@\t if test -f $$f; then mv $$f $$backupdir; restore=mv; else :; fi; \\\n+@BUILD_INFO_TRUE@\t done; \\\n+@BUILD_INFO_TRUE@\telse :; fi && \\\n+@BUILD_INFO_TRUE@\tif $(MAKEINFO) $(AM_MAKEINFOFLAGS) $(MAKEINFOFLAGS) -I doc -I $(srcdir)/doc \\\n+@BUILD_INFO_TRUE@\t -o $@ `test -f 'doc/sframe-spec.texi' || echo '$(srcdir)/'`doc/sframe-spec.texi; \\\n+@BUILD_INFO_TRUE@\tthen \\\n+@BUILD_INFO_TRUE@\t rc=0; \\\n+@BUILD_INFO_TRUE@\telse \\\n+@BUILD_INFO_TRUE@\t rc=$$?; \\\n+@BUILD_INFO_TRUE@\t $$restore $$backupdir/* `echo \"./$@\" | sed 's|[^/]*$$||'`; \\\n+@BUILD_INFO_TRUE@\tfi; \\\n+@BUILD_INFO_TRUE@\trm -rf $$backupdir; exit $$rc\n+\n+doc/sframe-spec.dvi: doc/sframe-spec.texi doc/$(am__dirstamp)\n+\t$(AM_V_TEXI2DVI)TEXINPUTS=\"$(am__TEXINFO_TEX_DIR)$(PATH_SEPARATOR)$$TEXINPUTS\" \\\n+\tMAKEINFO='$(MAKEINFO) $(AM_MAKEINFOFLAGS) $(MAKEINFOFLAGS) -I doc -I $(srcdir)/doc' \\\n+\t$(TEXI2DVI) $(AM_V_texinfo) --build-dir=$(@:.dvi=.t2d) -o $@ $(AM_V_texidevnull) \\\n+\t`test -f 'doc/sframe-spec.texi' || echo '$(srcdir)/'`doc/sframe-spec.texi\n+\n+doc/sframe-spec.pdf: doc/sframe-spec.texi doc/$(am__dirstamp)\n+\t$(AM_V_TEXI2PDF)TEXINPUTS=\"$(am__TEXINFO_TEX_DIR)$(PATH_SEPARATOR)$$TEXINPUTS\" \\\n+\tMAKEINFO='$(MAKEINFO) $(AM_MAKEINFOFLAGS) $(MAKEINFOFLAGS) -I doc -I $(srcdir)/doc' \\\n+\t$(TEXI2PDF) $(AM_V_texinfo) --build-dir=$(@:.pdf=.t2p) -o $@ $(AM_V_texidevnull) \\\n+\t`test -f 'doc/sframe-spec.texi' || echo '$(srcdir)/'`doc/sframe-spec.texi\n+\n+doc/sframe-spec.html: doc/sframe-spec.texi doc/$(am__dirstamp)\n+\t$(AM_V_MAKEINFO)rm -rf $(@:.html=.htp)\n+\t$(AM_V_at)if $(MAKEINFOHTML) $(AM_MAKEINFOHTMLFLAGS) $(MAKEINFOFLAGS) -I doc -I $(srcdir)/doc \\\n+\t -o $(@:.html=.htp) `test -f 'doc/sframe-spec.texi' || echo '$(srcdir)/'`doc/sframe-spec.texi; \\\n+\tthen \\\n+\t rm -rf $@ && mv $(@:.html=.htp) $@; \\\n+\telse \\\n+\t rm -rf $(@:.html=.htp); exit 1; \\\n+\tfi\n+.dvi.ps:\n+\t$(AM_V_DVIPS)TEXINPUTS=\"$(am__TEXINFO_TEX_DIR)$(PATH_SEPARATOR)$$TEXINPUTS\" \\\n+\t$(DVIPS) $(AM_V_texinfo) -o $@ $<\n+\n+uninstall-dvi-am:\n+\t@$(NORMAL_UNINSTALL)\n+\t@list='$(DVIS)'; test -n \"$(dvidir)\" || list=; \\\n+\tfor p in $$list; do \\\n+\t $(am__strip_dir) \\\n+\t echo \" rm -f '$(DESTDIR)$(dvidir)/$$f'\"; \\\n+\t rm -f \"$(DESTDIR)$(dvidir)/$$f\"; \\\n+\tdone\n+\n+uninstall-html-am:\n+\t@$(NORMAL_UNINSTALL)\n+\t@list='$(HTMLS)'; test -n \"$(htmldir)\" || list=; \\\n+\tfor p in $$list; do \\\n+\t $(am__strip_dir) \\\n+\t echo \" rm -rf '$(DESTDIR)$(htmldir)/$$f'\"; \\\n+\t rm -rf \"$(DESTDIR)$(htmldir)/$$f\"; \\\n+\tdone\n+\n+uninstall-info-am:\n+\t@$(PRE_UNINSTALL)\n+\t@if test -d '$(DESTDIR)$(infodir)' && $(am__can_run_installinfo); then \\\n+\t list='$(INFO_DEPS)'; \\\n+\t for file in $$list; do \\\n+\t relfile=`echo \"$$file\" | sed 's|^.*/||'`; \\\n+\t echo \" install-info --info-dir='$(DESTDIR)$(infodir)' --remove '$(DESTDIR)$(infodir)/$$relfile'\"; \\\n+\t if install-info --info-dir=\"$(DESTDIR)$(infodir)\" --remove \"$(DESTDIR)$(infodir)/$$relfile\"; \\\n+\t then :; else test ! -f \"$(DESTDIR)$(infodir)/$$relfile\" || exit 1; fi; \\\n+\t done; \\\n+\telse :; fi\n+\t@$(NORMAL_UNINSTALL)\n+\t@list='$(INFO_DEPS)'; \\\n+\tfor file in $$list; do \\\n+\t relfile=`echo \"$$file\" | sed 's|^.*/||'`; \\\n+\t relfile_i=`echo \"$$relfile\" | sed 's|\\.info$$||;s|$$|.i|'`; \\\n+\t (if test -d \"$(DESTDIR)$(infodir)\" && cd \"$(DESTDIR)$(infodir)\"; then \\\n+\t echo \" cd '$(DESTDIR)$(infodir)' && rm -f $$relfile $$relfile-[0-9] $$relfile-[0-9][0-9] $$relfile_i[0-9] $$relfile_i[0-9][0-9]\"; \\\n+\t rm -f $$relfile $$relfile-[0-9] $$relfile-[0-9][0-9] $$relfile_i[0-9] $$relfile_i[0-9][0-9]; \\\n+\t else :; fi); \\\n+\tdone\n+\n+uninstall-pdf-am:\n+\t@$(NORMAL_UNINSTALL)\n+\t@list='$(PDFS)'; test -n \"$(pdfdir)\" || list=; \\\n+\tfor p in $$list; do \\\n+\t $(am__strip_dir) \\\n+\t echo \" rm -f '$(DESTDIR)$(pdfdir)/$$f'\"; \\\n+\t rm -f \"$(DESTDIR)$(pdfdir)/$$f\"; \\\n+\tdone\n+\n+uninstall-ps-am:\n+\t@$(NORMAL_UNINSTALL)\n+\t@list='$(PSS)'; test -n \"$(psdir)\" || list=; \\\n+\tfor p in $$list; do \\\n+\t $(am__strip_dir) \\\n+\t echo \" rm -f '$(DESTDIR)$(psdir)/$$f'\"; \\\n+\t rm -f \"$(DESTDIR)$(psdir)/$$f\"; \\\n+\tdone\n+\n+dist-info: $(INFO_DEPS)\n+\t@srcdirstrip=`echo \"$(srcdir)\" | sed 's|.|.|g'`; \\\n+\tlist='$(INFO_DEPS)'; \\\n+\tfor base in $$list; do \\\n+\t case $$base in \\\n+\t $(srcdir)/*) base=`echo \"$$base\" | sed \"s|^$$srcdirstrip/||\"`;; \\\n+\t esac; \\\n+\t if test -f $$base; then d=.; else d=$(srcdir); fi; \\\n+\t base_i=`echo \"$$base\" | sed 's|\\.info$$||;s|$$|.i|'`; \\\n+\t for file in $$d/$$base $$d/$$base-[0-9] $$d/$$base-[0-9][0-9] $$d/$$base_i[0-9] $$d/$$base_i[0-9][0-9]; do \\\n+\t if test -f $$file; then \\\n+\t relfile=`expr \"$$file\" : \"$$d/\\(.*\\)\"`; \\\n+\t test -f \"$(distdir)/$$relfile\" || \\\n+\t\tcp -p $$file \"$(distdir)/$$relfile\"; \\\n+\t else :; fi; \\\n+\t done; \\\n+\tdone\n+\n+mostlyclean-aminfo:\n+\t-rm -rf doc/sframe-spec.t2d doc/sframe-spec.t2p\n+\n+clean-aminfo:\n+\t-test -z \"doc/sframe-spec.dvi doc/sframe-spec.pdf doc/sframe-spec.ps \\\n+\t doc/sframe-spec.html\" \\\n+\t|| rm -rf doc/sframe-spec.dvi doc/sframe-spec.pdf doc/sframe-spec.ps \\\n+\t doc/sframe-spec.html\n+\n+maintainer-clean-aminfo:\n+\t@list='$(INFO_DEPS)'; for i in $$list; do \\\n+\t i_i=`echo \"$$i\" | sed 's|\\.info$$||;s|$$|.i|'`; \\\n+\t echo \" rm -f $$i $$i-[0-9] $$i-[0-9][0-9] $$i_i[0-9] $$i_i[0-9][0-9]\"; \\\n+\t rm -f $$i $$i-[0-9] $$i-[0-9][0-9] $$i_i[0-9] $$i_i[0-9][0-9]; \\\n+\tdone\n install-includeHEADERS: $(include_HEADERS)\n \t@$(NORMAL_INSTALL)\n \t@list='$(include_HEADERS)'; test -n \"$(includedir)\" || list=; \\\n@@ -869,6 +1077,9 @@ distdir: $(DISTFILES)\n \t || exit 1; \\\n \t fi; \\\n \tdone\n+\t$(MAKE) $(AM_MAKEFLAGS) \\\n+\t top_distdir=\"$(top_distdir)\" distdir=\"$(distdir)\" \\\n+\t dist-info\n \t-test -n \"$(am__skip_mode_fix)\" \\\n \t|| find \"$(distdir)\" -type d ! -perm -755 \\\n \t\t-exec chmod u+rwx,go+rx {} \\; -o \\\n@@ -1004,9 +1215,9 @@ check-am: all-am\n \t$(MAKE) $(AM_MAKEFLAGS) $(check_PROGRAMS)\n \t$(MAKE) $(AM_MAKEFLAGS) check-DEJAGNU\n check: check-am\n-all-am: Makefile $(LTLIBRARIES) $(HEADERS) config.h\n+all-am: Makefile $(INFO_DEPS) $(LTLIBRARIES) $(HEADERS) config.h\n installdirs:\n-\tfor dir in \"$(DESTDIR)$(libdir)\" \"$(DESTDIR)$(includedir)\"; do \\\n+\tfor dir in \"$(DESTDIR)$(libdir)\" \"$(DESTDIR)$(infodir)\" \"$(DESTDIR)$(includedir)\"; do \\\n \t test -z \"$$dir\" || $(MKDIR_P) \"$$dir\"; \\\n \tdone\n install: install-am\n@@ -1035,18 +1246,23 @@ clean-generic:\n distclean-generic:\n \t-test -z \"$(CONFIG_CLEAN_FILES)\" || rm -f $(CONFIG_CLEAN_FILES)\n \t-test . = \"$(srcdir)\" || test -z \"$(CONFIG_CLEAN_VPATH_FILES)\" || rm -f $(CONFIG_CLEAN_VPATH_FILES)\n+\t-rm -f doc/$(am__dirstamp)\n \t-rm -f testsuite/libsframe.decode/$(DEPDIR)/$(am__dirstamp)\n \t-rm -f testsuite/libsframe.decode/$(am__dirstamp)\n \t-rm -f testsuite/libsframe.encode/$(DEPDIR)/$(am__dirstamp)\n \t-rm -f testsuite/libsframe.encode/$(am__dirstamp)\n+\t-test -z \"$(DISTCLEANFILES)\" || rm -f $(DISTCLEANFILES)\n \n maintainer-clean-generic:\n \t@echo \"This command is intended for maintainers to use\"\n \t@echo \"it deletes files that may require special tools to rebuild.\"\n+\t-test -z \"$(MAINTAINERCLEANFILES)\" || rm -f $(MAINTAINERCLEANFILES)\n+@BUILD_INFO_FALSE@html-local:\n clean: clean-am\n \n-clean-am: clean-checkPROGRAMS clean-generic clean-libLTLIBRARIES \\\n-\tclean-libtool clean-noinstLTLIBRARIES mostlyclean-am\n+clean-am: clean-aminfo clean-checkPROGRAMS clean-generic \\\n+\tclean-libLTLIBRARIES clean-libtool clean-noinstLTLIBRARIES \\\n+\tmostlyclean-am\n \n distclean: distclean-am\n \t-rm -f $(am__CONFIG_DISTCLEAN_FILES)\n@@ -1058,42 +1274,133 @@ distclean-am: clean-am distclean-DEJAGNU distclean-compile \\\n \n dvi: dvi-am\n \n-dvi-am:\n+dvi-am: $(DVIS)\n \n html: html-am\n \n-html-am:\n+html-am: $(HTMLS) html-local\n \n info: info-am\n \n-info-am:\n+info-am: $(INFO_DEPS)\n \n-install-data-am: install-includeHEADERS\n+install-data-am: install-includeHEADERS install-info-am\n \n install-dvi: install-dvi-am\n \n-install-dvi-am:\n-\n+install-dvi-am: $(DVIS)\n+\t@$(NORMAL_INSTALL)\n+\t@list='$(DVIS)'; test -n \"$(dvidir)\" || list=; \\\n+\tif test -n \"$$list\"; then \\\n+\t echo \" $(MKDIR_P) '$(DESTDIR)$(dvidir)'\"; \\\n+\t $(MKDIR_P) \"$(DESTDIR)$(dvidir)\" || exit 1; \\\n+\tfi; \\\n+\tfor p in $$list; do \\\n+\t if test -f \"$$p\"; then d=; else d=\"$(srcdir)/\"; fi; \\\n+\t echo \"$$d$$p\"; \\\n+\tdone | $(am__base_list) | \\\n+\twhile read files; do \\\n+\t echo \" $(INSTALL_DATA) $$files '$(DESTDIR)$(dvidir)'\"; \\\n+\t $(INSTALL_DATA) $$files \"$(DESTDIR)$(dvidir)\" || exit $$?; \\\n+\tdone\n install-exec-am: install-libLTLIBRARIES\n \n install-html: install-html-am\n \n-install-html-am:\n-\n+install-html-am: $(HTMLS)\n+\t@$(NORMAL_INSTALL)\n+\t@list='$(HTMLS)'; list2=; test -n \"$(htmldir)\" || list=; \\\n+\tif test -n \"$$list\"; then \\\n+\t echo \" $(MKDIR_P) '$(DESTDIR)$(htmldir)'\"; \\\n+\t $(MKDIR_P) \"$(DESTDIR)$(htmldir)\" || exit 1; \\\n+\tfi; \\\n+\tfor p in $$list; do \\\n+\t if test -f \"$$p\" || test -d \"$$p\"; then d=; else d=\"$(srcdir)/\"; fi; \\\n+\t $(am__strip_dir) \\\n+\t d2=$$d$$p; \\\n+\t if test -d \"$$d2\"; then \\\n+\t echo \" $(MKDIR_P) '$(DESTDIR)$(htmldir)/$$f'\"; \\\n+\t $(MKDIR_P) \"$(DESTDIR)$(htmldir)/$$f\" || exit 1; \\\n+\t echo \" $(INSTALL_DATA) '$$d2'/* '$(DESTDIR)$(htmldir)/$$f'\"; \\\n+\t $(INSTALL_DATA) \"$$d2\"/* \"$(DESTDIR)$(htmldir)/$$f\" || exit $$?; \\\n+\t else \\\n+\t list2=\"$$list2 $$d2\"; \\\n+\t fi; \\\n+\tdone; \\\n+\ttest -z \"$$list2\" || { echo \"$$list2\" | $(am__base_list) | \\\n+\twhile read files; do \\\n+\t echo \" $(INSTALL_DATA) $$files '$(DESTDIR)$(htmldir)'\"; \\\n+\t $(INSTALL_DATA) $$files \"$(DESTDIR)$(htmldir)\" || exit $$?; \\\n+\tdone; }\n install-info: install-info-am\n \n-install-info-am:\n-\n+install-info-am: $(INFO_DEPS)\n+\t@$(NORMAL_INSTALL)\n+\t@srcdirstrip=`echo \"$(srcdir)\" | sed 's|.|.|g'`; \\\n+\tlist='$(INFO_DEPS)'; test -n \"$(infodir)\" || list=; \\\n+\tif test -n \"$$list\"; then \\\n+\t echo \" $(MKDIR_P) '$(DESTDIR)$(infodir)'\"; \\\n+\t $(MKDIR_P) \"$(DESTDIR)$(infodir)\" || exit 1; \\\n+\tfi; \\\n+\tfor file in $$list; do \\\n+\t case $$file in \\\n+\t $(srcdir)/*) file=`echo \"$$file\" | sed \"s|^$$srcdirstrip/||\"`;; \\\n+\t esac; \\\n+\t if test -f $$file; then d=.; else d=$(srcdir); fi; \\\n+\t file_i=`echo \"$$file\" | sed 's|\\.info$$||;s|$$|.i|'`; \\\n+\t for ifile in $$d/$$file $$d/$$file-[0-9] $$d/$$file-[0-9][0-9] \\\n+\t $$d/$$file_i[0-9] $$d/$$file_i[0-9][0-9] ; do \\\n+\t if test -f $$ifile; then \\\n+\t echo \"$$ifile\"; \\\n+\t else : ; fi; \\\n+\t done; \\\n+\tdone | $(am__base_list) | \\\n+\twhile read files; do \\\n+\t echo \" $(INSTALL_DATA) $$files '$(DESTDIR)$(infodir)'\"; \\\n+\t $(INSTALL_DATA) $$files \"$(DESTDIR)$(infodir)\" || exit $$?; done\n+\t@$(POST_INSTALL)\n+\t@if $(am__can_run_installinfo); then \\\n+\t list='$(INFO_DEPS)'; test -n \"$(infodir)\" || list=; \\\n+\t for file in $$list; do \\\n+\t relfile=`echo \"$$file\" | sed 's|^.*/||'`; \\\n+\t echo \" install-info --info-dir='$(DESTDIR)$(infodir)' '$(DESTDIR)$(infodir)/$$relfile'\";\\\n+\t install-info --info-dir=\"$(DESTDIR)$(infodir)\" \"$(DESTDIR)$(infodir)/$$relfile\" || :;\\\n+\t done; \\\n+\telse : ; fi\n install-man:\n \n install-pdf: install-pdf-am\n \n-install-pdf-am:\n-\n+install-pdf-am: $(PDFS)\n+\t@$(NORMAL_INSTALL)\n+\t@list='$(PDFS)'; test -n \"$(pdfdir)\" || list=; \\\n+\tif test -n \"$$list\"; then \\\n+\t echo \" $(MKDIR_P) '$(DESTDIR)$(pdfdir)'\"; \\\n+\t $(MKDIR_P) \"$(DESTDIR)$(pdfdir)\" || exit 1; \\\n+\tfi; \\\n+\tfor p in $$list; do \\\n+\t if test -f \"$$p\"; then d=; else d=\"$(srcdir)/\"; fi; \\\n+\t echo \"$$d$$p\"; \\\n+\tdone | $(am__base_list) | \\\n+\twhile read files; do \\\n+\t echo \" $(INSTALL_DATA) $$files '$(DESTDIR)$(pdfdir)'\"; \\\n+\t $(INSTALL_DATA) $$files \"$(DESTDIR)$(pdfdir)\" || exit $$?; done\n install-ps: install-ps-am\n \n-install-ps-am:\n-\n+install-ps-am: $(PSS)\n+\t@$(NORMAL_INSTALL)\n+\t@list='$(PSS)'; test -n \"$(psdir)\" || list=; \\\n+\tif test -n \"$$list\"; then \\\n+\t echo \" $(MKDIR_P) '$(DESTDIR)$(psdir)'\"; \\\n+\t $(MKDIR_P) \"$(DESTDIR)$(psdir)\" || exit 1; \\\n+\tfi; \\\n+\tfor p in $$list; do \\\n+\t if test -f \"$$p\"; then d=; else d=\"$(srcdir)/\"; fi; \\\n+\t echo \"$$d$$p\"; \\\n+\tdone | $(am__base_list) | \\\n+\twhile read files; do \\\n+\t echo \" $(INSTALL_DATA) $$files '$(DESTDIR)$(psdir)'\"; \\\n+\t $(INSTALL_DATA) $$files \"$(DESTDIR)$(psdir)\" || exit $$?; done\n installcheck-am:\n \n maintainer-clean: maintainer-clean-am\n@@ -1101,48 +1408,63 @@ maintainer-clean: maintainer-clean-am\n \t-rm -rf $(top_srcdir)/autom4te.cache\n \t-rm -rf ./$(DEPDIR) testsuite/libsframe.decode/$(DEPDIR) testsuite/libsframe.encode/$(DEPDIR)\n \t-rm -f Makefile\n-maintainer-clean-am: distclean-am maintainer-clean-generic\n+maintainer-clean-am: distclean-am maintainer-clean-aminfo \\\n+\tmaintainer-clean-generic\n \n mostlyclean: mostlyclean-am\n \n-mostlyclean-am: mostlyclean-compile mostlyclean-generic \\\n-\tmostlyclean-libtool\n+mostlyclean-am: mostlyclean-aminfo mostlyclean-compile \\\n+\tmostlyclean-generic mostlyclean-libtool\n \n pdf: pdf-am\n \n-pdf-am:\n+pdf-am: $(PDFS)\n \n ps: ps-am\n \n-ps-am:\n+ps-am: $(PSS)\n \n-uninstall-am: uninstall-includeHEADERS uninstall-libLTLIBRARIES\n+uninstall-am: uninstall-dvi-am uninstall-html-am \\\n+\tuninstall-includeHEADERS uninstall-info-am \\\n+\tuninstall-libLTLIBRARIES uninstall-pdf-am uninstall-ps-am\n \n .MAKE: all check-am install-am install-strip\n \n .PHONY: CTAGS GTAGS TAGS all all-am am--refresh check check-DEJAGNU \\\n-\tcheck-am clean clean-checkPROGRAMS clean-cscope clean-generic \\\n-\tclean-libLTLIBRARIES clean-libtool clean-noinstLTLIBRARIES \\\n-\tcscope cscopelist-am ctags ctags-am dist dist-all dist-bzip2 \\\n-\tdist-gzip dist-lzip dist-shar dist-tarZ dist-xz dist-zip \\\n-\tdistcheck distclean distclean-DEJAGNU distclean-compile \\\n-\tdistclean-generic distclean-hdr distclean-libtool \\\n-\tdistclean-tags distcleancheck distdir distuninstallcheck dvi \\\n-\tdvi-am html html-am info info-am install install-am \\\n-\tinstall-data install-data-am install-dvi install-dvi-am \\\n-\tinstall-exec install-exec-am install-html install-html-am \\\n-\tinstall-includeHEADERS install-info install-info-am \\\n-\tinstall-libLTLIBRARIES install-man install-pdf install-pdf-am \\\n-\tinstall-ps install-ps-am install-strip installcheck \\\n-\tinstallcheck-am installdirs maintainer-clean \\\n-\tmaintainer-clean-generic mostlyclean mostlyclean-compile \\\n-\tmostlyclean-generic mostlyclean-libtool pdf pdf-am ps ps-am \\\n-\ttags tags-am uninstall uninstall-am uninstall-includeHEADERS \\\n-\tuninstall-libLTLIBRARIES\n+\tcheck-am clean clean-aminfo clean-checkPROGRAMS clean-cscope \\\n+\tclean-generic clean-libLTLIBRARIES clean-libtool \\\n+\tclean-noinstLTLIBRARIES cscope cscopelist-am ctags ctags-am \\\n+\tdist dist-all dist-bzip2 dist-gzip dist-info dist-lzip \\\n+\tdist-shar dist-tarZ dist-xz dist-zip distcheck distclean \\\n+\tdistclean-DEJAGNU distclean-compile distclean-generic \\\n+\tdistclean-hdr distclean-libtool distclean-tags distcleancheck \\\n+\tdistdir distuninstallcheck dvi dvi-am html html-am html-local \\\n+\tinfo info-am install install-am install-data install-data-am \\\n+\tinstall-dvi install-dvi-am install-exec install-exec-am \\\n+\tinstall-html install-html-am install-includeHEADERS \\\n+\tinstall-info install-info-am install-libLTLIBRARIES \\\n+\tinstall-man install-pdf install-pdf-am install-ps \\\n+\tinstall-ps-am install-strip installcheck installcheck-am \\\n+\tinstalldirs maintainer-clean maintainer-clean-aminfo \\\n+\tmaintainer-clean-generic mostlyclean mostlyclean-aminfo \\\n+\tmostlyclean-compile mostlyclean-generic mostlyclean-libtool \\\n+\tpdf pdf-am ps ps-am tags tags-am uninstall uninstall-am \\\n+\tuninstall-dvi-am uninstall-html-am uninstall-includeHEADERS \\\n+\tuninstall-info-am uninstall-libLTLIBRARIES uninstall-pdf-am \\\n+\tuninstall-ps-am\n \n .PRECIOUS: Makefile\n \n \n+@BUILD_INFO_TRUE@html-local: doc/sframe-spec/index.html\n+@BUILD_INFO_TRUE@doc/sframe-spec/index.html: doc/sframe-spec.texi doc/$(am__dirstamp)\n+@BUILD_INFO_TRUE@\t$(AM_V_GEN)$(MAKEINFOHTML) $(AM_MAKEINFOHTMLFLAGS) $(MAKEINFOFLAGS) \\\n+@BUILD_INFO_TRUE@\t --split=node -I$(srcdir) --output doc/sframe-spec $(srcdir)/doc/sframe-spec.texi\n+\n+# Workaround bug in automake: it can't handle conditionally building info pages\n+# since GNU projects normally include info pages in the source distributions.\n+@BUILD_INFO_FALSE@doc/sframe-spec.info:\n+\n check-DEJAGNU: site.exp\n \tsrcroot=`cd $(srcdir) && pwd`; export srcroot; \\\n \tr=`pwd`; export r; \\\ndiff --git a/libsframe/configure.ac b/libsframe/configure.ac\nindex a6c1d26bbbb..4182a0dc0ab 100644\n--- a/libsframe/configure.ac\n+++ b/libsframe/configure.ac\n@@ -59,6 +59,27 @@ AM_CONDITIONAL([HAVE_COMPAT_DEJAGNU], [test \"x$ac_cv_dejagnu_compat\" = \"xyes\"])\n COMPAT_DEJAGNU=$ac_cv_dejagnu_compat\n AC_SUBST(COMPAT_DEJAGNU)\n \n+dnl Check for makeinfo for building documentation\n+build_info=\n+AC_CHECK_PROGS([MAKEINFO], makeinfo, makeinfo, )\n+if test \"x$MAKEINFO\" = \"x\"; then\n+ MAKEINFO=\"@echo makeinfo missing; true\"\n+ build_info=\n+else\n+ BUILD_INFO=info\n+ case \"$MAKEINFO\" in\n+ */missing\\ makeinfo*)\n+\tbuild_info=\n+\tAC_MSG_WARN([\n+*** Makeinfo is missing. Info documentation will not be built.])\n+ ;;\n+ *)\n+\tbuild_info=yes\n+\t;;\n+ esac\n+fi\n+AM_CONDITIONAL(BUILD_INFO, test \"${build_info}\" = yes)\n+\n AM_MAINTAINER_MODE\n AM_INSTALL_LIBBFD\n \ndiff --git a/libsframe/doc/local.mk b/libsframe/doc/local.mk\nnew file mode 100644\nindex 00000000000..bdd1312e040\n--- /dev/null\n+++ b/libsframe/doc/local.mk\n@@ -0,0 +1,40 @@\n+## Process this file with automake to produce Makefile.in.\n+#\n+# Copyright (C) 2019-2022 Free Software Foundation, Inc.\n+#\n+# This file is free software; you can redistribute it and/or modify\n+# it under the terms of the GNU General Public License as published by\n+# the Free Software Foundation; either version 2 of the License, or\n+# (at your option) any later version.\n+#\n+# This program is distributed in the hope that it will be useful,\n+# but WITHOUT ANY WARRANTY; without even the implied warranty of\n+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n+# GNU General Public License for more details.\n+#\n+# You should have received a copy of the GNU General Public License\n+# along with this program; see the file COPYING. If not see\n+# .\n+#\n+\n+if BUILD_INFO\n+\n+info_TEXINFOS += %D%/sframe-spec.texi\n+\n+AM_MAKEINFOFLAGS = --no-split\n+\n+DISTCLEANFILES += texput.log\n+MAINTAINERCLEANFILES += %D%/sframe-spec.info\n+\n+html-local: %D%/sframe-spec/index.html\n+%D%/sframe-spec/index.html: %D%/sframe-spec.texi %D%/$(am__dirstamp)\n+\t$(AM_V_GEN)$(MAKEINFOHTML) $(AM_MAKEINFOHTMLFLAGS) $(MAKEINFOFLAGS) \\\n+\t --split=node -I$(srcdir) --output %D%/sframe-spec $(srcdir)/%D%/sframe-spec.texi\n+\n+else\n+\n+# Workaround bug in automake: it can't handle conditionally building info pages\n+# since GNU projects normally include info pages in the source distributions.\n+%D%/sframe-spec.info:\n+\n+endif\ndiff --git a/libsframe/doc/sframe-spec.texi b/libsframe/doc/sframe-spec.texi\nnew file mode 100644\nindex 00000000000..41f4ba17d83\n--- /dev/null\n+++ b/libsframe/doc/sframe-spec.texi\n@@ -0,0 +1,619 @@\n+\\input texinfo @c -*- Texinfo -*-\n+@setfilename sframe-spec.info\n+@settitle The SFrame Format\n+@ifnottex\n+@xrefautomaticsectiontitle on\n+@end ifnottex\n+\n+@copying\n+Copyright @copyright{} 2021-2022 Free Software Foundation, Inc.\n+\n+Permission is granted to copy, distribute and/or modify this document\n+under the terms of the GNU General Public License, Version 3 or any\n+later version published by the Free Software Foundation. A copy of the\n+license is included in the section entitled ``GNU General Public\n+License''.\n+\n+@end copying\n+\n+@dircategory Software development\n+@direntry\n+* SFrame: (sframe-spec). The Simple Frame format.\n+@end direntry\n+\n+@titlepage\n+@title The SFrame Format\n+@subtitle Version 1\n+@author Indu Bhagat\n+\n+@page\n+@vskip 0pt plus 1filll\n+@insertcopying\n+@end titlepage\n+@contents\n+\n+@ifnottex\n+@node Top\n+@top The SFrame format\n+\n+This manual describes version 1 of the SFrame file format. SFrame stands for\n+Simple Frame format. SFrame format keeps track of the minimal necessary\n+information needed for stack unwinding:\n+\n+@itemize @minus\n+@item\n+Canonical Frame Address (CFA).\n+@item\n+Frame Pointer (FP).\n+@item\n+Return Address (RA).\n+@end itemize\n+\n+The reason for existence of the SFrame format is to support fast, online\n+backtracing using a simple unwinder.\n+\n+@menu\n+* Overview::\n+* SFrame section::\n+* Index::\n+@end menu\n+\n+@end ifnottex\n+\n+@node Overview\n+@unnumbered Overview\n+@cindex Overview\n+@tindex PT_GNU_SFRAME\n+\n+The SFrame unwind information is provided in a loaded section, known as the\n+@code{.sframe} section. When available, the @code{.sframe} section appears in\n+a new segment of its own, PT_GNU_SFRAME.\n+\n+The SFrame format is currently supported only for select ABIs, namely, AMD64\n+and AAPCS64.\n+\n+The contents of the SFrame section are stored in the target endianness, i.e.,\n+in the endianness of the system on which the section is targetted to be used.\n+An SFrame section reader may use the magic number in the SFrame header to\n+identify the endianness of the SFrame section.\n+\n+Addresses in this specification are expressed in bytes.\n+\n+The associated API to decode, probe and encode the SFrame section, provided via\n+@code{libsframe}, is not accompanied here at this time. This will be added\n+later.\n+\n+This document is intended to be in sync with the C code in @file{sframe.h}.\n+Please report descrepancies between the two, if any.\n+\n+@node SFrame section\n+@chapter SFrame section\n+@cindex SFrame section\n+\n+The SFrame section consists of an SFrame header, starting with a preamble, and\n+two other sub-sections, namely the SFrame Function Descriptor Entry (SFrame\n+FDE) sub-section, and the SFrame Frame Row Entry (SFrame FRE) sub-section.\n+\n+@menu\n+* SFrame Preamble::\n+* SFrame Header::\n+* SFrame Function Descriptor Entries::\n+* SFrame Frame Row Entries::\n+@end menu\n+\n+@node SFrame Preamble\n+@section SFrame Preamble\n+@cindex SFrame preamble\n+\n+The preamble is a 32-bit packed structure; the only part of the SFrame whose\n+format cannot vary between versions.\n+\n+@example\n+typedef struct sframe_preamble\n+@{\n+ uint16_t sfp_magic;\n+ uint8_t sfp_version;\n+ uint8_t sfp_flags;\n+@} ATTRIBUTE_PACKED sframe_preamble;\n+@end example\n+\n+All values are stored in the endianness of the target system for which the\n+SFrame section is intended. Further details:\n+\n+@multitable {Offset} {@code{uint8_t sfp_version}} {The magic number for SFrame section: 0xdee2. Defined}\n+@headitem Offset @tab Name @tab Description\n+@item 0x00\n+@tab @code{uint16_t sfp_magic}\n+@tab The magic number for SFrame section: 0xdee2. Defined as a macro @code{SFRAME_MAGIC}.\n+@tindex SFRAME_MAGIC\n+\n+@item 0x02\n+@tab @code{uint8_t sfp_version}\n+@tab The version number of this SFrame section. @xref{SFrame version}, for the\n+set of valid values. Current version is\n+@code{SFRAME_VERSION_1}.\n+\n+@item 0x03\n+@tab @code{uint8_t sfp_flags}\n+@tab Flags (section-wide) for this SFrame section. @xref{SFrame flags}, for the\n+set of valid values.\n+@end multitable\n+\n+@menu\n+* SFrame endianness::\n+* SFrame version::\n+* SFrame flags::\n+@end menu\n+\n+@node SFrame endianness\n+@subsection SFrame endianness\n+\n+@cindex endianness\n+SFrame sections are stored in the target endianness of the system that consumes\n+them. The SFrame library (@code{libsframe}) can, however, detect whether to\n+endian-flip an SFrame section at decode time, by inspecting the\n+@code{sfp_magic} field in the SFrame header (If it appears as 0xe2de,\n+endian-flipping is needed).\n+\n+@node SFrame version\n+@subsection SFrame version\n+\n+The version of the SFrame format can be determined by inspecting\n+@code{sfp_version}. The following versions are currently valid:\n+\n+@tindex SFRAME_VERSION_1\n+@cindex SFrame versions\n+@multitable {SFRAME_VERSION_1} {Number} {First version, under development.}\n+@headitem Version @tab Number @tab Description\n+@item @code{SFRAME_VERSION_1}\n+@tab 1 @tab First version, under development.\n+@end multitable\n+\n+This section documents @code{SFRAME_VERSION_1}.\n+\n+@node SFrame flags\n+@subsection SFrame flags\n+@cindex SFrame flags\n+@comment @vindex sfp_flags\n+@comment @vindex SFrame section-wide flags\n+@comment @subsection SFrame section-wide flags\n+\n+The preamble contains bitflags in its @code{sfp_flags} field that\n+describe various section-wide properties.\n+\n+The following flags are currently defined.\n+\n+@multitable {@code{SFRAME_F_FRAME_POINTER}} {Versions} {Value} {Function Descriptor Entries}\n+@headitem Flag @tab Versions @tab Value @tab Meaning\n+@tindex SFRAME_F_FDE_SORTED\n+@item @code{SFRAME_F_FDE_SORTED} @tab All @tab 0x1 @tab Function Descriptor\n+Entries are sorted on PC.\n+@tindex SFRAME_F_FRAME_POINTER\n+@item @code{SFRAME_F_FRAME_POINTER} @tab All @tab 0x2\n+@tab Functions preserve frame-pointer.\n+@end multitable\n+\n+Further flags may be added in future.\n+\n+@node SFrame Header\n+@section SFrame Header\n+@cindex SFrame header\n+\n+The SFrame header is the first part of an SFrame section. It begins with the\n+SFrame preamble. All parts of it other than the preamble\n+(@pxref{SFrame Preamble}) can vary between SFrame file versions. It contains\n+things that apply to the section as a whole, and offsets to the various other\n+sub-sections defined in the format. As with the rest of the SFrame section,\n+all values are stored in the endianness of the target system.\n+\n+The two sub-sections tile the SFrame section: each section runs from the offset\n+given until the start of the next section. An explicit length is given for the\n+last sub-section, the SFrame Frame Row Entry (SFrame FRE) sub-section.\n+\n+@example\n+typedef struct sframe_header\n+@{\n+ sframe_preamble sfh_preamble;\n+ uint8_t sfh_abi_arch;\n+ int8_t sfh_cfa_fixed_fp_offset;\n+ int8_t sfh_cfa_fixed_ra_offset;\n+ uint8_t sfh_auxhdr_len;\n+ uint32_t sfh_num_fdes;\n+ uint32_t sfh_num_fres;\n+ uint32_t sfh_fre_len;\n+ uint32_t sfh_fdeoff;\n+ uint32_t sfh_freoff;\n+@} ATTRIBUTE_PACKED sframe_header;\n+@end example\n+\n+The sub-section offsets, namely @code{sfh_fdeoff} and @code{sfh_freoff}, in the\n+SFrame header are relative to the @emph{end} of the SFrame header; they are\n+each an offset in bytes into the SFrame section where the SFrame FDE\n+sub-section and the SFrame FRE sub-section respectively start.\n+\n+SFrame header allows specifying explicitly the fixed offsets from CFA, if any,\n+from which FP or RA may be recovered. For example, in AMD64, the stack offset\n+of the return address is @code{CFA - 8}. Since this offset is in close\n+vicinity with the CFA in most ABIs, @code{sfh_cfa_fixed_fp_offset} and\n+@code{sfh_cfa_fixed_ra_offset} are limited to signed 8-bit integers.\n+\n+SFrame format has provisioned for future ABIs/architectures that it may\n+support. The @code{sframe_header} structure provides an unsigned 8-bit\n+integral field to denote the size of an auxilliary SFrame header. The\n+auxilliary SFrame header follows right after the @code{sframe_header}\n+structure. As for the offset calculations, the @emph{end} of SFrame header\n+must be the end of the auxilliary SFrame header, if the latter is present.\n+\n+Tieing it all together:\n+\n+@multitable {Offset} {@code{int8_t sfh_cfa_fixed_fp_offset}} {The ABI/arch identifier. See above}\n+@headitem Offset @tab Name @tab Description\n+@item 0x00\n+@tab @code{sframe_preamble sfh_preamble}\n+@tab The SFrame preamble. @xref{SFrame Preamble}.\n+\n+@item 0x04\n+@tab @code{uint8_t sfh_abi_arch}\n+@tab The ABI/arch identifier. @xref{SFrame ABI/arch identifier}.\n+\n+@item 0x05\n+@tab @code{int8_t sfh_cfa_fixed_fp_offset}\n+@tab The CFA fixed FP offset, if any.\n+\n+@item 0x06\n+@tab @code{int8_t sfh_cfa_fixed_ra_offset}\n+@tab The CFA fixed RA offset, if any.\n+\n+@item 0x07\n+@tab @code{uint8_t sfh_auxhdr_len}\n+@tab Size in bytes of the auxilliary header that follows the\n+@code{sframe_header} structure.\n+\n+@item 0x08\n+@tab @code{uint32_t sfh_num_fdes}\n+@tab The number of SFrame FDEs in the section.\n+\n+@item 0xc\n+@tab @code{uint32_t sfh_num_fres}\n+@tab The number of SFrame FREs in the section.\n+\n+@item 0x10\n+@tab @code{uint32_t sfh_fre_len}\n+@tab The length in bytes of the SFrame FRE sub-section.\n+\n+@item 0x14\n+@tab @code{uint32_t sfh_fdeoff}\n+@tab The offset in bytes of the SFrame FDE sub-section. This sub-section\n+contains @code{sfh_num_fdes} number of fixed-length array elements. The array\n+element is of type SFrame function desciptor entry, each providing a\n+high-level function description for backtracing.\n+@xref{SFrame Function Descriptor Entries}.\n+\n+@item 0x18\n+@tab @code{uint32_t sfh_freoff}\n+@tab The offset in bytes of the SFrame FRE sub-section, the core of the SFrame\n+section, which describes the unwind information using variable-length array\n+elements. @xref{SFrame Frame Row Entries}.\n+\n+@end multitable\n+\n+@menu\n+* SFrame ABI/arch identifier::\n+@end menu\n+\n+@node SFrame ABI/arch identifier\n+@subsection SFrame ABI/arch identifier\n+@cindex SFrame ABI/arch identifier\n+\n+SFrame header identifies the ABI/arch of the target system for which the\n+executable and it's unwind information is intended. There are currently three\n+identifiable ABI/arch values in the format.\n+\n+@multitable {SFRAME_ABI_AARCH64_ENDIAN_LITTLE} {Value} {@code{AARCH64 little-endian}}\n+@headitem ABI/arch Identifier @tab Value @tab Description\n+\n+@tindex SFRAME_ABI_AARCH64_ENDIAN_BIG\n+@item @code{SFRAME_ABI_AARCH64_ENDIAN_BIG}\n+@tab 1 @tab AARCH64 big-endian\n+\n+@tindex SFRAME_ABI_AARCH64_ENDIAN_LITTLE\n+@item @code{SFRAME_ABI_AARCH64_ENDIAN_LITTLE}\n+@tab 2 @tab AARCH64 little-endian\n+\n+@tindex SFRAME_ABI_AMD64_ENDIAN_LITTLE\n+@item @code{SFRAME_ABI_AMD64_ENDIAN_LITTLE}\n+@tab 3 @tab AMD64 little-endian\n+\n+@end multitable\n+\n+The presence of an explicit identification of ABI/arch in SFrame may allow\n+unwinders to make certain ABI-specific decisions.\n+\n+@node SFrame Function Descriptor Entries\n+@section SFrame FDE\n+@cindex SFrame FDE\n+\n+The SFrame Function Descriptor Entry sub-section is a sorted array of\n+fixed-length SFrame function descriptor entries (SFrame FDEs). Each SFrame FDE\n+is a packed structure which contains information to describe a function's unwind\n+information at a high-level.\n+\n+@example\n+typedef struct sframe_func_desc_entry\n+@{\n+ int32_t sfde_func_start_address;\n+ uint32_t sfde_func_size;\n+ uint32_t sfde_func_start_fre_off;\n+ uint32_t sfde_func_num_fres;\n+ uint8_t sfde_func_info;\n+@} ATTRIBUTE_PACKED sframe_func_desc_entry;\n+@end example\n+\n+@code{sfde_func_start_fre_off} is the offset to the first SFrame FRE for the\n+function. This offset is relative to the @emph{end of the SFrame FDE}\n+sub-section (unlike the offsets in the SFrame header, which are relative to the\n+@emph{end} of the SFrame header).\n+\n+@code{sfde_func_info} is the \"info word\", containing information on the FRE\n+type and the FDE type for the function @xref{The SFrame FDE info word}.\n+\n+Following table describes each component of the SFrame FDE structure:\n+\n+@multitable {Offset} {@code{uint32_t sfde_func_start_fre_off}} {The ABI/arch identifier. See above}\n+@headitem Offset @tab Name @tab Description\n+@item 0x00\n+@tab @code{int32_t sfde_func_start_address}\n+@tab Signed 32-bit integral field denoting the virtual memory address of the\n+described function.\n+\n+@item 0x04\n+@tab @code{uint32_t sfde_func_size}\n+@tab Unsigned 32-bit integral field specifying the size of the function in\n+bytes.\n+\n+@item 0x08\n+@tab @code{uint32_t sfde_func_start_fre_off}\n+@tab Unsigned 32-bit integral field specifying the offset in bytes of the\n+function's first SFrame FRE in the SFrame section.\n+\n+@item 0x0c\n+@tab @code{uint32_t sfde_func_num_fres}\n+@tab Unsigned 32-bit integral field specifying the total number of SFrame FREs\n+used for the function.\n+\n+@item 0x10\n+@tab @code{uint8_t sfde_func_info}\n+@tab The SFrame FDE info word. @xref{The SFrame FDE info word}.\n+\n+@end multitable\n+\n+@menu\n+* The SFrame FDE info word::\n+* The SFrame FDE types::\n+* The SFrame FRE types::\n+@end menu\n+\n+@cindex The SFrame FDE info word\n+@node The SFrame FDE info word\n+@subsection The SFrame FDE info word, sfde_func_info\n+\n+The info word is a bitfield split into three parts. From MSB to LSB:\n+\n+@multitable {Bit offset} {@code{isroot}} {Length of variable-length data for this type (some kinds only).}\n+@headitem Bit offset @tab Name @tab Description\n+@item 7--5\n+@tab @code{unused}\n+@tab Unused bits.\n+\n+@item 4\n+@tab @code{fdetype}\n+@tab SFRAME_FDE_TYPE_PCMASK (1) or SFRAME_FDE_TYPE_PCINC (0). @xref{The SFrame FDE types}.\n+\n+@item 0--3\n+@tab @code{fretype}\n+@tab Choice of three SFrame FRE types. @xref{The SFrame FRE types}.\n+@end multitable\n+\n+@node The SFrame FDE types\n+@subsection The SFrame FDE types\n+@tindex SFRAME_FDE_TYPE_PCMASK\n+@tindex SFRAME_FDE_TYPE_PCINC\n+\n+SFrame format defines two types of FDE entries. The choice of which SFrame FDE\n+type to use is made based on the instruction patterns in the relevant program\n+stub.\n+\n+An SFrame FDE of type @code{SFRAME_FDE_TYPE_PCINC} is an indication that the PCs in the\n+FREs should be treated as increments in bytes. This is used fo the the bulk of\n+the executable code of a program, which contains instructions with no specific\n+pattern.\n+\n+In contrast, an SFrame FDE of type @code{SFRAME_FDE_TYPE_PCMASK} is an\n+indication that the PCs in the FREs should be treated as masks. This type is\n+useful for the cases where a small pattern of instructions in a program stub is\n+used repeatedly for a specific functionality. Typical usecases are pltN\n+entries and trampolines.\n+\n+@multitable {Name of SFrame FDE type} {Value} {Unwinders perform a (PC >= FRE_START_ADDR)}\n+@headitem Name of SFrame FDE type @tab Value @tab Description\n+\n+@item SFRAME_FDE_TYPE_PCINC\n+@tab 0 @tab Unwinders perform a (PC >= FRE_START_ADDR) to look up a matching FRE.\n+\n+@item SFRAME_FDE_TYPE_PCMASK\n+@tab 1 @tab Unwinders perform a (PC & FRE_START_ADDR_AS_MASK >= FRE_START_ADDR_AS_MASK)\n+to look up a matching FRE.\n+\n+@end multitable\n+\n+@node The SFrame FRE types\n+@subsection The SFrame FRE types\n+\n+A real world application can have functions of size big and small. SFrame\n+format defines three types of SFrame FRE entries to represent the unwind\n+information for such a variety of function sizes. These representations vary\n+in the number of bits needed to encode the start address offset in the SFrame\n+FRE.\n+\n+The following constants are defined and used to identify the SFrame FRE types:\n+\n+@multitable {SFRAME_FRE_TYPE_ADDR1} {@code{Value}} {The start address offset of FRE is an}\n+@headitem Name @tab Value @tab Description\n+\n+@tindex SFRAME_FRE_TYPE_ADDR1\n+@item @code{SFRAME_FRE_TYPE_ADDR1}\n+@tab 0\n+@tab The start address offset (in bytes) of the SFrame FRE is an unsigned\n+8-bit value.\n+\n+@tindex SFRAME_FRE_TYPE_ADDR2\n+@item @code{SFRAME_FRE_TYPE_ADDR2}\n+@tab 1\n+@tab The start address offset (in bytes) of the SFrame FRE is an unsigned\n+16-bit value.\n+\n+@tindex SFRAME_FRE_TYPE_ADDR4\n+@item @code{SFRAME_FRE_TYPE_ADDR4}\n+@tab 2\n+@tab The start address offset (in bytes) of the SFrame FRE is an unsigned\n+32-bit value.\n+@end multitable\n+\n+A single function must use the same type of FRE throughout. The choice of\n+which SFrame FRE is used to encode the unwind information of a function, is\n+stored in the @xref{The SFrame FDE info word}.\n+\n+@node SFrame Frame Row Entries\n+@section SFrame FRE\n+@cindex SFrame FRE\n+\n+The SFrame Frame Row Entry sub-section contains the core of the unwind\n+information.\n+\n+An SFrame Frame Row Entry is a self-sufficient record containing SFrame unwind\n+info for a range of contiguous addresses, starting at the specified offset from\n+the start of the function. Each SFrame Frame Row Entry is followed by S*N\n+bytes, where:\n+\n+@itemize @minus\n+@item\n+@code{S} is the size of the stack frame offset for the FRE, and\n+@item\n+@code{N} is the number of stack frame offsets in the FRE\n+@end itemize\n+\n+The stack offsets, following the FRE, are interpreted in order as follows:\n+\n+@itemize @minus\n+@item\n+The first offset is always used to locate the CFA, by interpreting it as:\n+CFA = @code{BASE_REG} + offset1.\n+@item\n+If RA is being tracked, the second offset is always used to locate the RA, by\n+interpreting it as: RA = CFA + offset2. If RA is @emph{not} being tracked\n+@emph{and} FP is being tracked, the second offset will be used to locate the\n+FP, by interpreting it as: FP = CFA + offset2.\n+@item\n+If both RA and FP are being tracked, the third offset will be used to locate\n+the FP, by interpreting it as FP = CFA + offset3.\n+@end itemize\n+\n+The entities @code{S}, @code{N} and @code{BASE_REG} are identified using the\n+SFrame FRE info word, a.k.a. the @code{sframe_fre_info}\n+@xref{The SFrame FRE info word}.\n+\n+Following are the definitions of the allowed SFrame FRE:\n+\n+@example\n+typedef struct sframe_frame_row_entry_addr1\n+@{\n+ uint8_t sfre_start_address;\n+ sframe_fre_info sfre_info;\n+@} ATTRIBUTE_PACKED sframe_frame_row_entry_addr1;\n+@end example\n+\n+@example\n+typedef struct sframe_frame_row_entry_addr2\n+@{\n+ uint16_t sfre_start_address;\n+ sframe_fre_info sfre_info;\n+@} ATTRIBUTE_PACKED sframe_frame_row_entry_addr2;\n+@end example\n+\n+@example\n+typedef struct sframe_frame_row_entry_addr4\n+@{\n+ uint32_t sfre_start_address;\n+ sframe_fre_info sfre_info;\n+@} A 100 63714 100 63560 100 154 775k 1925 --:--:-- --:--:-- --:--:-- 777k TTRIBUTE_PACKED sframe_frame_row_entry_addr4;\n+@end example\n+\n+@code{sfre_start_address} is an unsigned 8-bit/16-bit/32-bit integral field\n+identifies the start address of the range of program counters, for which the\n+SFrame FRE applies. The value encoded in the @code{sfre_start_address} field\n+is the offset in bytes of the start address of the SFrame FRE, from the start\n+address of the function.\n+\n+Further FRE types may be added in future.\n+\n+@menu\n+* The SFrame FRE info word::\n+@end menu\n+\n+@cindex The SFrame FRE info word\n+@node The SFrame FRE info word\n+@subsection The SFrame FRE info word, sfre_info\n+\n+The SFrame FRE info word is a bitfield split into four parts. From MSB to LSB:\n+\n+@multitable {Bit offset} {@code{fre_cfa_base_reg_id}} {Size of stack offsets in bytes. Valid values}\n+@headitem Bit offset @tab Name @tab Description\n+@item 7\n+@tab @code{unused}\n+@tab Unused bit.\n+\n+@item 5-6\n+@tab @code{fre_offset_size}\n+@tab Size of stack offsets in bytes. Valid values are SFRAME_FRE_OFFSET_1B,\n+SFRAME_FRE_OFFSET_2B, and SFRAME_FRE_OFFSET_4B.\n+\n+@item 1-4\n+@tab @code{fre_offset_count}\n+@tab A value of upto 3 is allowed to track all three of CFA, FP and RA.\n+\n+@item 0\n+@tab @code{fre_cfa_base_reg_id}\n+@tab Distinguish between SP or FP based CFA recovery.\n+\n+@end multitable\n+\n+@multitable {SFRAME_FRE_OFFSET_4B} {@code{Value}} {All stack offsets following the fixed-length}\n+@headitem Name @tab Value @tab Description\n+\n+@tindex SFRAME_FRE_OFFSET_1B\n+@item @code{SFRAME_FRE_OFFSET_1B}\n+@tab 0\n+@tab All stack offsets following the fixed-length FRE structure are 1 byte\n+long.\n+\n+@tindex SFRAME_FRE_OFFSET_2B\n+@item @code{SFRAME_FRE_OFFSET_2B}\n+@tab 1\n+@tab All stack offsets following the fixed-length FRE structure are 2 bytes\n+long.\n+\n+@tindex SFRAME_FRE_OFFSET_4B\n+@item @code{SFRAME_FRE_OFFSET_4B}\n+@tab 2\n+@tab All stack offsets following the fixed-length FRE structure are 4 bytes\n+long.\n+\n+@end multitable\n+\n+@node Index\n+@unnumbered Index\n+\n+@syncodeindex tp cp\n+@printindex cp\n+\n+@bye\n","prefixes":["V4","11/11"]}+ exit 1 Build step 'Execute shell' marked build as failure Finished: FAILURE