Started by user snail Running as SYSTEM [EnvInject] - Loading node environment variables. Building remotely on docker-jenkins-agent in workspace /home/jenkins/agent/workspace/binutils-gdb [WS-CLEANUP] Deleting project workspace... [WS-CLEANUP] Deferred wipeout is used... [WS-CLEANUP] Done The recommended git tool is: NONE using credential 0adb5fc7-caa2-429d-97d2-c7fa2fa1d884 Cloning the remote Git repository Using shallow clone with depth 1 Avoid fetching tags Cloning repository git@github.com:plctlab/patchwork-binutils-gdb.git > git init /home/jenkins/agent/workspace/binutils-gdb # timeout=10 Fetching upstream changes from git@github.com:plctlab/patchwork-binutils-gdb.git > git --version # timeout=10 > git --version # 'git version 2.37.2' using GIT_SSH to set credentials patchwork github wangliu-iscas git ssh key Verifying host key using known hosts file, will automatically accept unseen keys > git fetch --no-tags --force --progress --depth=1 -- git@github.com:plctlab/patchwork-binutils-gdb.git +refs/heads/*:refs/remotes/origin/* # timeout=10 > git config remote.origin.url git@github.com:plctlab/patchwork-binutils-gdb.git # timeout=10 > git config --add remote.origin.fetch +refs/heads/*:refs/remotes/origin/* # timeout=10 Avoid second fetch > git rev-parse refs/remotes/origin/master^{commit} # timeout=10 Checking out Revision 2d4989e98ee5e63b76ce3e35b0e02baaee2f50cb (refs/remotes/origin/master) > git config core.sparsecheckout # timeout=10 > git checkout -f 2d4989e98ee5e63b76ce3e35b0e02baaee2f50cb # timeout=10 Commit message: "Re: Fuzzed files in archives" > git rev-list --no-walk 2d4989e98ee5e63b76ce3e35b0e02baaee2f50cb # timeout=10 [EnvInject] - Mask passwords that will be passed as build parameters. [EnvInject] - Executing scripts and injecting environment variables after the SCM step. [EnvInject] - Injecting as environment variables the properties content GITHUB_REPO=https://github.com/plctlab/patchwork-binutils-gdb PATCHWORK_URL=https://patchwork.plctlab.org [EnvInject] - Variables injected successfully. [binutils-gdb] $ /usr/bin/env bash /tmp/jenkins8128469799047977168.sh + git config pw.server https://patchwork.plctlab.org/api/1.2/ + git config pw.project binutils-gdb + git config pw.token [*******] ++ date +%Y-%m + now_date=2022-11 ++ date +%Y + now_date_year=2022 + bundle_name=binutils-gdb_2022-11 ++ curl -s -H 'Authorization: Token [*******]' 'https://patchwork.plctlab.org/api/1.2/bundles/?project=binutils-gdb&per_page=999' + bundle_response='[{"id":6,"url":"https://patchwork.plctlab.org/api/1.2/bundles/6/","web_url":"https://patchwork.plctlab.org/bundle/patchwork-bot/binutils-gdb_2022-10/","project":{"id":2,"url":"https://patchwork.plctlab.org/api/1.2/projects/2/","name":"binutils-gdb","link_name":"binutils-gdb","list_id":"binutils.sourceware.org","list_email":"binutils@sourceware.org","web_url":"https://github.com/wangliu-iscas/Patchwork-Bundles/blob/main/binutils-gdb.md","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"name":"binutils-gdb_2022-10","owner":{"id":3,"url":"https://patchwork.plctlab.org/api/1.2/users/3/","username":"patchwork-bot","first_name":"","last_name":"","email":"ouuuleilei@gmail.com"},"patches":[{"id":1592,"url":"https://patchwork.plctlab.org/api/1.2/patches/1592/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/385d01fd-7e57-1f3f-1bae-30aa0c313d63@suse.com/","msgid":"<385d01fd-7e57-1f3f-1bae-30aa0c313d63@suse.com>","list_archive_url":null,"date":"2022-09-30T11:59:45","name":"[3/4] RISC-V/gas: don'\''t open-code insn_length()","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/385d01fd-7e57-1f3f-1bae-30aa0c313d63@suse.com/mbox/"},{"id":1594,"url":"https://patchwork.plctlab.org/api/1.2/patches/1594/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f5757acf-7b90-a0e3-5eea-3b97cc226930@suse.com/","msgid":"","list_archive_url":null,"date":"2022-09-30T12:00:12","name":"[4/4] RISC-V/gas: allow generating up to 176-bit instructions with .insn","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f5757acf-7b90-a0e3-5eea-3b97cc226930@suse.com/mbox/"},{"id":1596,"url":"https://patchwork.plctlab.org/api/1.2/patches/1596/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930140503.38233-1-chigot@adacore.com/","msgid":"<20220930140503.38233-1-chigot@adacore.com>","list_archive_url":null,"date":"2022-09-30T14:05:03","name":"ld/testsuite: consistently add board_ldflags when linking with GCC","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930140503.38233-1-chigot@adacore.com/mbox/"},{"id":1619,"url":"https://patchwork.plctlab.org/api/1.2/patches/1619/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221001014451.532772-1-maskray@google.com/","msgid":"<20221001014451.532772-1-maskray@google.com>","list_archive_url":null,"date":"2022-10-01T01:44:51","name":"gold, dwp: support zstd compressed input debug sections [PR 29641]","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221001014451.532772-1-maskray@google.com/mbox/"},{"id":1620,"url":"https://patchwork.plctlab.org/api/1.2/patches/1620/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221001023846.590825-1-maskray@google.com/","msgid":"<20221001023846.590825-1-maskray@google.com>","list_archive_url":null,"date":"2022-10-01T02:38:46","name":"gold: add --compress-debug-sections=zstd [PR 29641]","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221001023846.590825-1-maskray@google.com/mbox/"},{"id":1623,"url":"https://patchwork.plctlab.org/api/1.2/patches/1623/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b4477c7f666bdeb7f8e998633c7b0cb62310b9ef.1664599545.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-01T04:45:52","name":"[RFC,1/1] RISC-V: Implement common register pair framework","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b4477c7f666bdeb7f8e998633c7b0cb62310b9ef.1664599545.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1625,"url":"https://patchwork.plctlab.org/api/1.2/patches/1625/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/53a265a1f14d17a6f7b106082f610994c5d546e0.1664602025.git.research_trasio@irq.a4lg.com/","msgid":"<53a265a1f14d17a6f7b106082f610994c5d546e0.1664602025.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-01T05:27:31","name":"[RFC,1/1] RISC-V: Implement extension variants","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/53a265a1f14d17a6f7b106082f610994c5d546e0.1664602025.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1626,"url":"https://patchwork.plctlab.org/api/1.2/patches/1626/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8db04962aba9c780f133840a8934353a58f223fe.1664602716.git.research_trasio@irq.a4lg.com/","msgid":"<8db04962aba9c780f133840a8934353a58f223fe.1664602716.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-01T05:39:26","name":"[1/1] RISC-V: Move supervisor instructions after all unprivileged ones","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8db04962aba9c780f133840a8934353a58f223fe.1664602716.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1627,"url":"https://patchwork.plctlab.org/api/1.2/patches/1627/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221001062057.681440-1-maskray@google.com/","msgid":"<20221001062057.681440-1-maskray@google.com>","list_archive_url":null,"date":"2022-10-01T06:20:57","name":"readelf: support zstd compressed debug sections [PR 29640]","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221001062057.681440-1-maskray@google.com/mbox/"},{"id":1631,"url":"https://patchwork.plctlab.org/api/1.2/patches/1631/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/619f112539c0bdecd58e25664f1250a3479a37f5.1664707612.git.aburgess@redhat.com/","msgid":"<619f112539c0bdecd58e25664f1250a3479a37f5.1664707612.git.aburgess@redhat.com>","list_archive_url":null,"date":"2022-10-02T10:47:52","name":"[PATCHv2,2/2] opcodes/arm: add disassembler styling for arm","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/619f112539c0bdecd58e25664f1250a3479a37f5.1664707612.git.aburgess@redhat.com/mbox/"},{"id":1635,"url":"https://patchwork.plctlab.org/api/1.2/patches/1635/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221002185433.gl7dvytfh5wthifx@lug-owl.de/","msgid":"<20221002185433.gl7dvytfh5wthifx@lug-owl.de>","list_archive_url":null,"date":"2022-10-02T18:54:33","name":"diagnostics.h: GCC 13 got -Wself-move, breaks GDB build","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221002185433.gl7dvytfh5wthifx@lug-owl.de/mbox/"},{"id":1637,"url":"https://patchwork.plctlab.org/api/1.2/patches/1637/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003014313.28766-1-mark@harmstone.com/","msgid":"<20221003014313.28766-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-03T01:43:12","name":"[1/2] ld: Add --pdb option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003014313.28766-1-mark@harmstone.com/mbox/"},{"id":1638,"url":"https://patchwork.plctlab.org/api/1.2/patches/1638/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003014313.28766-2-mark@harmstone.com/","msgid":"<20221003014313.28766-2-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-03T01:43:13","name":"[2/2] ld: Add minimal pdb generation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003014313.28766-2-mark@harmstone.com/mbox/"},{"id":1640,"url":"https://patchwork.plctlab.org/api/1.2/patches/1640/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/597ed978-d121-220c-b56b-2ffb94bd091c@suse.cz/","msgid":"<597ed978-d121-220c-b56b-2ffb94bd091c@suse.cz>","list_archive_url":null,"date":"2022-10-03T07:50:38","name":"[1/2] refactor usage of compressed_debug_section_type","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/597ed978-d121-220c-b56b-2ffb94bd091c@suse.cz/mbox/"},{"id":1641,"url":"https://patchwork.plctlab.org/api/1.2/patches/1641/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b8acdd83-f33a-74b8-e21a-23719a0b1a60@suse.cz/","msgid":"","list_archive_url":null,"date":"2022-10-03T07:50:44","name":"[2/2] add --enable-default-compressed-debug-sections-algorithm configure option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b8acdd83-f33a-74b8-e21a-23719a0b1a60@suse.cz/mbox/"},{"id":1642,"url":"https://patchwork.plctlab.org/api/1.2/patches/1642/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003101328.1790113-1-aburgess@redhat.com/","msgid":"<20221003101328.1790113-1-aburgess@redhat.com>","list_archive_url":null,"date":"2022-10-03T10:13:28","name":"opcodes/riscv: style csr names as registers","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003101328.1790113-1-aburgess@redhat.com/mbox/"},{"id":1643,"url":"https://patchwork.plctlab.org/api/1.2/patches/1643/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7ba14fc4472ce97d4f7a4433cad8a571e89f82f4.1664793840.git.research_trasio@irq.a4lg.com/","msgid":"<7ba14fc4472ce97d4f7a4433cad8a571e89f82f4.1664793840.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-03T10:43:59","name":"[v3,1/6] RISC-V: Fix immediates to have \"immediate\" style","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7ba14fc4472ce97d4f7a4433cad8a571e89f82f4.1664793840.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1644,"url":"https://patchwork.plctlab.org/api/1.2/patches/1644/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a498bec37c1fd1dcda57cbf95e5f8cfba09b31d3.1664793840.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-03T10:44:00","name":"[v3,2/6] RISC-V: Fix printf argument types corresponding %x","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a498bec37c1fd1dcda57cbf95e5f8cfba09b31d3.1664793840.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1647,"url":"https://patchwork.plctlab.org/api/1.2/patches/1647/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0002ea716713ace4998a33dde0b81f4f890d10bf.1664793840.git.research_trasio@irq.a4lg.com/","msgid":"<0002ea716713ace4998a33dde0b81f4f890d10bf.1664793840.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-03T10:44:01","name":"[v3,3/6] RISC-V: Optimize riscv_disassemble_data printf","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0002ea716713ace4998a33dde0b81f4f890d10bf.1664793840.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1646,"url":"https://patchwork.plctlab.org/api/1.2/patches/1646/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c65fc3e9aa58965d6768a28c9fd7467fea9897a5.1664793840.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-03T10:44:02","name":"[v3,4/6] RISC-V: Print comma and tabs as the \"text\" style","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c65fc3e9aa58965d6768a28c9fd7467fea9897a5.1664793840.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1648,"url":"https://patchwork.plctlab.org/api/1.2/patches/1648/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5abe1d8a7694417b990e11d8f6cd6789573872e5.1664793840.git.research_trasio@irq.a4lg.com/","msgid":"<5abe1d8a7694417b990e11d8f6cd6789573872e5.1664793840.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-03T10:44:03","name":"[v3,5/6] RISC-V: Fix T-Head immediate types on printing","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5abe1d8a7694417b990e11d8f6cd6789573872e5.1664793840.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1649,"url":"https://patchwork.plctlab.org/api/1.2/patches/1649/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0b68af932117258c908db62cf87c3a15d3cdec41.1664793840.git.research_trasio@irq.a4lg.com/","msgid":"<0b68af932117258c908db62cf87c3a15d3cdec41.1664793840.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-03T10:44:04","name":"[v3,6/6] RISC-V: Print XTheadMemPair literal as \"immediate\"","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0b68af932117258c908db62cf87c3a15d3cdec41.1664793840.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1656,"url":"https://patchwork.plctlab.org/api/1.2/patches/1656/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/87lepxcd6x.fsf@redhat.com/","msgid":"<87lepxcd6x.fsf@redhat.com>","list_archive_url":null,"date":"2022-10-03T12:19:02","name":"Commit: readelf: Do not load section data from offset 0","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/87lepxcd6x.fsf@redhat.com/mbox/"},{"id":1659,"url":"https://patchwork.plctlab.org/api/1.2/patches/1659/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e0d369d419da9c0441f415da7f54352aead8f655.1664707612.git.aburgess@redhat.com/","msgid":"","list_archive_url":null,"date":"2022-10-03T16:37:36","name":"[PATCHv2,1/2] opcodes/arm: use '\''@'\'' consistently for the comment character","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e0d369d419da9c0441f415da7f54352aead8f655.1664707612.git.aburgess@redhat.com/mbox/"},{"id":1660,"url":"https://patchwork.plctlab.org/api/1.2/patches/1660/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003165848.11142-1-palmer@rivosinc.com/","msgid":"<20221003165848.11142-1-palmer@rivosinc.com>","list_archive_url":null,"date":"2022-10-03T16:58:48","name":"gas: NEWS: Mention the T-Head extensions that were recently added","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003165848.11142-1-palmer@rivosinc.com/mbox/"},{"id":1671,"url":"https://patchwork.plctlab.org/api/1.2/patches/1671/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/YzvrMEdkXjIn5Lfz@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-04T08:13:36","name":"Support objcopy changing compression to or from zstd","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/YzvrMEdkXjIn5Lfz@squeak.grove.modra.org/mbox/"},{"id":1673,"url":"https://patchwork.plctlab.org/api/1.2/patches/1673/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0bc857d306bb7c8130e5328dbe6b9ed2fed3ef87.1664873933.git.research_trasio@irq.a4lg.com/","msgid":"<0bc857d306bb7c8130e5328dbe6b9ed2fed3ef87.1664873933.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-04T08:59:07","name":"[1/2] RISC-V: Fix buffer overflow on print_insn_riscv","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0bc857d306bb7c8130e5328dbe6b9ed2fed3ef87.1664873933.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1672,"url":"https://patchwork.plctlab.org/api/1.2/patches/1672/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/89612fe01d902007bf84a7dfb0df5f85d5c166e4.1664873933.git.research_trasio@irq.a4lg.com/","msgid":"<89612fe01d902007bf84a7dfb0df5f85d5c166e4.1664873933.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-04T08:59:08","name":"[2/2] gdb/riscv: Fix buffer overflow on riscv_insn::fetch_instruction","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/89612fe01d902007bf84a7dfb0df5f85d5c166e4.1664873933.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1676,"url":"https://patchwork.plctlab.org/api/1.2/patches/1676/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fc849c94f4adcac1c4ccc5508c7a145a2f13b2a9.1664876744.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-04T09:45:49","name":"[v2,1/2] RISC-V: Fix buffer overflow on print_insn_riscv","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fc849c94f4adcac1c4ccc5508c7a145a2f13b2a9.1664876744.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1677,"url":"https://patchwork.plctlab.org/api/1.2/patches/1677/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4eb6e59ae2e790dbbf2bc92477edd281648d8814.1664876744.git.research_trasio@irq.a4lg.com/","msgid":"<4eb6e59ae2e790dbbf2bc92477edd281648d8814.1664876744.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-04T09:45:50","name":"[v2,2/2] gdb/riscv: Partial support for instructions up to 176-bits","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4eb6e59ae2e790dbbf2bc92477edd281648d8814.1664876744.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1678,"url":"https://patchwork.plctlab.org/api/1.2/patches/1678/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ebf16f9e1f45115d0793952ccb4a94d4233303f9.1664882725.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-04T11:25:56","name":"[v3,1/2] RISC-V: Fix buffer overflow on print_insn_riscv","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ebf16f9e1f45115d0793952ccb4a94d4233303f9.1664882725.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1679,"url":"https://patchwork.plctlab.org/api/1.2/patches/1679/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/83464b09b8649525259c69c853dfa2c9575a204b.1664882725.git.research_trasio@irq.a4lg.com/","msgid":"<83464b09b8649525259c69c853dfa2c9575a204b.1664882725.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-04T11:25:57","name":"[v3,2/2] gdb/riscv: Partial support for instructions up to 176-bit","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/83464b09b8649525259c69c853dfa2c9575a204b.1664882725.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1681,"url":"https://patchwork.plctlab.org/api/1.2/patches/1681/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ffa9c1d7-e8c2-a62b-ef3e-b565c0ffbe5b@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-04T13:56:27","name":"RISC-V: Zicbo{m,p,z} adjustments to riscv_multi_subset_supports_ext()","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ffa9c1d7-e8c2-a62b-ef3e-b565c0ffbe5b@suse.com/mbox/"},{"id":1690,"url":"https://patchwork.plctlab.org/api/1.2/patches/1690/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221004161720.1963953-1-vladimir.mezentsev@oracle.com/","msgid":"<20221004161720.1963953-1-vladimir.mezentsev@oracle.com>","list_archive_url":null,"date":"2022-10-04T16:17:20","name":"gprofng: fix build with --enable-pgo-build=lto","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221004161720.1963953-1-vladimir.mezentsev@oracle.com/mbox/"},{"id":1691,"url":"https://patchwork.plctlab.org/api/1.2/patches/1691/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c0211bc9c57be6c79c6d878ce147f63b657f461d.camel@espressif.com/","msgid":"","list_archive_url":null,"date":"2022-10-04T16:22:05","name":"bfd: xtensa: fix __stop_SECTION literal drop,","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c0211bc9c57be6c79c6d878ce147f63b657f461d.camel@espressif.com/mbox/"},{"id":1702,"url":"https://patchwork.plctlab.org/api/1.2/patches/1702/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5f482299-6c60-b2b3-9abe-f4a55a5a26c5@univ-grenoble-alpes.fr/","msgid":"<5f482299-6c60-b2b3-9abe-f4a55a5a26c5@univ-grenoble-alpes.fr>","list_archive_url":null,"date":"2022-10-04T20:03:20","name":"[RFC] bfd: use bfd_vma for the 64-bit version of put[lb] and get[lb]","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5f482299-6c60-b2b3-9abe-f4a55a5a26c5@univ-grenoble-alpes.fr/mbox/"},{"id":1711,"url":"https://patchwork.plctlab.org/api/1.2/patches/1711/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Yz0Gsxdxe0TePbJT@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-05T04:23:15","name":"PR29647, objdump -S looping","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Yz0Gsxdxe0TePbJT@squeak.grove.modra.org/mbox/"},{"id":1712,"url":"https://patchwork.plctlab.org/api/1.2/patches/1712/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/02d747d2-f57b-0fb5-b893-842b6cc41f2f@suse.com/","msgid":"<02d747d2-f57b-0fb5-b893-842b6cc41f2f@suse.com>","list_archive_url":null,"date":"2022-10-05T07:20:47","name":"[v3,1/7] x86: constify parse_insn()'\''s input","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/02d747d2-f57b-0fb5-b893-842b6cc41f2f@suse.com/mbox/"},{"id":1713,"url":"https://patchwork.plctlab.org/api/1.2/patches/1713/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/925cb740-4e1b-abc4-8526-aaab6faae5e1@suse.com/","msgid":"<925cb740-4e1b-abc4-8526-aaab6faae5e1@suse.com>","list_archive_url":null,"date":"2022-10-05T07:22:19","name":"[v3,2/7] x86: introduce Pass2 insn attribute","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/925cb740-4e1b-abc4-8526-aaab6faae5e1@suse.com/mbox/"},{"id":1714,"url":"https://patchwork.plctlab.org/api/1.2/patches/1714/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e16d3e78-39ca-f715-508f-a4104b8ab9a9@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-05T07:23:51","name":"[v3,3/7] x86: re-work insn/suffix recognition","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e16d3e78-39ca-f715-508f-a4104b8ab9a9@suse.com/mbox/"},{"id":1715,"url":"https://patchwork.plctlab.org/api/1.2/patches/1715/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e4e4b80b-794c-7485-1997-685adab8fb27@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-05T07:24:20","name":"[v3,4/7] x86-64: further re-work insn/suffix recognition to also cover MOVSL","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e4e4b80b-794c-7485-1997-685adab8fb27@suse.com/mbox/"},{"id":1716,"url":"https://patchwork.plctlab.org/api/1.2/patches/1716/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/540678fc-8bff-ec68-c97c-478d2631998c@suse.com/","msgid":"<540678fc-8bff-ec68-c97c-478d2631998c@suse.com>","list_archive_url":null,"date":"2022-10-05T07:24:55","name":"[v3,5/7] ix86: don'\''t recognize/derive Q suffix in the common case","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/540678fc-8bff-ec68-c97c-478d2631998c@suse.com/mbox/"},{"id":1718,"url":"https://patchwork.plctlab.org/api/1.2/patches/1718/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e4692495-7d3d-074d-14f9-364d4a9a998c@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-05T07:25:25","name":"[v3,6/7] x86-64: allow HLE store of accumulator to absolute 32-bit address","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e4692495-7d3d-074d-14f9-364d4a9a998c@suse.com/mbox/"},{"id":1717,"url":"https://patchwork.plctlab.org/api/1.2/patches/1717/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e8014ebd-d16b-17a7-9f34-3700fc164136@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-05T07:25:57","name":"[v3,7/7] x86: move bad-use-of-TLS-reloc check","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e8014ebd-d16b-17a7-9f34-3700fc164136@suse.com/mbox/"},{"id":1719,"url":"https://patchwork.plctlab.org/api/1.2/patches/1719/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1266f001-4511-2662-dba9-14b4d0317c57@suse.com/","msgid":"<1266f001-4511-2662-dba9-14b4d0317c57@suse.com>","list_archive_url":null,"date":"2022-10-05T07:40:50","name":"x86: drop \"regmask\" static variable","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1266f001-4511-2662-dba9-14b4d0317c57@suse.com/mbox/"},{"id":1751,"url":"https://patchwork.plctlab.org/api/1.2/patches/1751/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/af45c5d57c221e43101c2aa38b14f4b4ac12d011.1665031170.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-06T04:40:15","name":"[v2,1/2] RISC-V: Fallback for instructions longer than 64b","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/af45c5d57c221e43101c2aa38b14f4b4ac12d011.1665031170.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1752,"url":"https://patchwork.plctlab.org/api/1.2/patches/1752/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c6e55781245dd3e8e9b8debd6130fc5449dfbd55.1665031170.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-06T04:40:16","name":"[v2,2/2] RISC-V: Improve \"bits undefined\" diagnostics","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c6e55781245dd3e8e9b8debd6130fc5449dfbd55.1665031170.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1776,"url":"https://patchwork.plctlab.org/api/1.2/patches/1776/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d52952119e15357c0e823f8a2398999359588b4d.1665050099.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-06T09:56:30","name":"[v3,1/2] RISC-V: Fallback for instructions longer than 64b","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d52952119e15357c0e823f8a2398999359588b4d.1665050099.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1777,"url":"https://patchwork.plctlab.org/api/1.2/patches/1777/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d907b1997f60ff7823c4a23e281ec9d8ddcbf3f1.1665050099.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-06T09:56:31","name":"[v3,2/2] RISC-V: Improve \"bits undefined\" diagnostics","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d907b1997f60ff7823c4a23e281ec9d8ddcbf3f1.1665050099.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1781,"url":"https://patchwork.plctlab.org/api/1.2/patches/1781/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221006114628.304185-1-chigot@adacore.com/","msgid":"<20221006114628.304185-1-chigot@adacore.com>","list_archive_url":null,"date":"2022-10-06T11:46:28","name":"RISC-V: fix linker message when relaxation deletes bytes","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221006114628.304185-1-chigot@adacore.com/mbox/"},{"id":1801,"url":"https://patchwork.plctlab.org/api/1.2/patches/1801/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Yz+Yhyg7UewC9/kp@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-07T03:09:59","name":"PR29653, objcopy/strip: fuzzed small input file induces large output file","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Yz+Yhyg7UewC9/kp@squeak.grove.modra.org/mbox/"},{"id":1803,"url":"https://patchwork.plctlab.org/api/1.2/patches/1803/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/PH1P110MB16505D9D39EC5B1DE22FE3D5EC5F9@PH1P110MB1650.NAMP110.PROD.OUTLOOK.COM/","msgid":"","list_archive_url":null,"date":"2022-10-07T04:10:07","name":"@CPP_FOR_BUILD@ problem since binutils-2.38","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/PH1P110MB16505D9D39EC5B1DE22FE3D5EC5F9@PH1P110MB1650.NAMP110.PROD.OUTLOOK.COM/mbox/"},{"id":1827,"url":"https://patchwork.plctlab.org/api/1.2/patches/1827/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8e13bce108ac10a0c1dd911e23ec572926f7ae44.1665203374.git.research_trasio@irq.a4lg.com/","msgid":"<8e13bce108ac10a0c1dd911e23ec572926f7ae44.1665203374.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-08T04:29:53","name":"[v2,1/1] RISC-V: Test DWARF register numbers for \"fp\"","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8e13bce108ac10a0c1dd911e23ec572926f7ae44.1665203374.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1828,"url":"https://patchwork.plctlab.org/api/1.2/patches/1828/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0883001b3572e54d3fba264429c7ade2adb66610.1665203441.git.research_trasio@irq.a4lg.com/","msgid":"<0883001b3572e54d3fba264429c7ade2adb66610.1665203441.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-08T04:31:15","name":"[1/1] RISC-V: Move standard hints before all instructions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0883001b3572e54d3fba264429c7ade2adb66610.1665203441.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1829,"url":"https://patchwork.plctlab.org/api/1.2/patches/1829/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/58e16a241d7376fcae2515c6bd5a2b41d275eeba.1665203531.git.research_trasio@irq.a4lg.com/","msgid":"<58e16a241d7376fcae2515c6bd5a2b41d275eeba.1665203531.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-08T04:32:18","name":"[RFC,1/1] RISC-V: Imply '\''Zicsr'\'' from privileged extensions with CSRs","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/58e16a241d7376fcae2515c6bd5a2b41d275eeba.1665203531.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1830,"url":"https://patchwork.plctlab.org/api/1.2/patches/1830/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/cb5076fc96e8f2097779a3abcde843dcdd660031.1665203660.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-08T04:34:23","name":"[1/5] opcodes/riscv-dis.c: Tidying with comments/clarity","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/cb5076fc96e8f2097779a3abcde843dcdd660031.1665203660.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1832,"url":"https://patchwork.plctlab.org/api/1.2/patches/1832/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1f1aa0838bf9c4f10a45fcfe3c682f7efc79d9ae.1665203660.git.research_trasio@irq.a4lg.com/","msgid":"<1f1aa0838bf9c4f10a45fcfe3c682f7efc79d9ae.1665203660.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-08T04:34:24","name":"[2/5] opcodes/riscv-dis.c: Tidying with spacing","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1f1aa0838bf9c4f10a45fcfe3c682f7efc79d9ae.1665203660.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1831,"url":"https://patchwork.plctlab.org/api/1.2/patches/1831/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/740bc5e2d2618d236519b39fedd1a1d7ae4e05da.1665203660.git.research_trasio@irq.a4lg.com/","msgid":"<740bc5e2d2618d236519b39fedd1a1d7ae4e05da.1665203660.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-08T04:34:25","name":"[3/5] opcodes/riscv-dis.c: Use bool type whenever possible","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/740bc5e2d2618d236519b39fedd1a1d7ae4e05da.1665203660.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1833,"url":"https://patchwork.plctlab.org/api/1.2/patches/1833/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6e3a9c235e317f441b4383b3daa68f2051bdc149.1665203660.git.research_trasio@irq.a4lg.com/","msgid":"<6e3a9c235e317f441b4383b3daa68f2051bdc149.1665203660.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-08T04:34:26","name":"[4/5] opcodes/riscv-dis.c: Make XLEN variable static","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6e3a9c235e317f441b4383b3daa68f2051bdc149.1665203660.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1834,"url":"https://patchwork.plctlab.org/api/1.2/patches/1834/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ad929233a62d887495122721340b2f9c80392963.1665203660.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-08T04:34:27","name":"[5/5] opcodes/riscv-dis.c: Remove last_map_state","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ad929233a62d887495122721340b2f9c80392963.1665203660.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1836,"url":"https://patchwork.plctlab.org/api/1.2/patches/1836/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d07e2b6f36ea2fd5830924a9bfeda941b774b687.1665290422.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-09T05:09:22","name":"RISC-V: Move certain arrays to riscv-opc.c","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d07e2b6f36ea2fd5830924a9bfeda941b774b687.1665290422.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1844,"url":"https://patchwork.plctlab.org/api/1.2/patches/1844/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010004623.16582-1-mark@harmstone.com/","msgid":"<20221010004623.16582-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-10T00:46:22","name":"[v2,1/2] ld: Add --pdb option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010004623.16582-1-mark@harmstone.com/mbox/"},{"id":1845,"url":"https://patchwork.plctlab.org/api/1.2/patches/1845/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010004623.16582-2-mark@harmstone.com/","msgid":"<20221010004623.16582-2-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-10T00:46:23","name":"[v2,2/2] ld: Add minimal pdb generation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010004623.16582-2-mark@harmstone.com/mbox/"},{"id":1890,"url":"https://patchwork.plctlab.org/api/1.2/patches/1890/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010200433.414320-1-vladimir.mezentsev@oracle.com/","msgid":"<20221010200433.414320-1-vladimir.mezentsev@oracle.com>","list_archive_url":null,"date":"2022-10-10T20:04:33","name":"gprofng: run tests without installation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010200433.414320-1-vladimir.mezentsev@oracle.com/mbox/"},{"id":1893,"url":"https://patchwork.plctlab.org/api/1.2/patches/1893/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010230426.719238-1-vladimir.mezentsev@oracle.com/","msgid":"<20221010230426.719238-1-vladimir.mezentsev@oracle.com>","list_archive_url":null,"date":"2022-10-10T23:04:26","name":"[2/2] gprofng: use the --libdir path to find libraries","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010230426.719238-1-vladimir.mezentsev@oracle.com/mbox/"},{"id":1894,"url":"https://patchwork.plctlab.org/api/1.2/patches/1894/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010235155.842469-1-vladimir.mezentsev@oracle.com/","msgid":"<20221010235155.842469-1-vladimir.mezentsev@oracle.com>","list_archive_url":null,"date":"2022-10-10T23:51:55","name":"[3/3] gprofng: no need to build version.texi","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010235155.842469-1-vladimir.mezentsev@oracle.com/mbox/"},{"id":1895,"url":"https://patchwork.plctlab.org/api/1.2/patches/1895/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011003702.4287-1-mark@harmstone.com/","msgid":"<20221011003702.4287-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-11T00:37:01","name":"[v3,1/2] ld: Add --pdb option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011003702.4287-1-mark@harmstone.com/mbox/"},{"id":1897,"url":"https://patchwork.plctlab.org/api/1.2/patches/1897/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011003702.4287-2-mark@harmstone.com/","msgid":"<20221011003702.4287-2-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-11T00:37:02","name":"[v3,2/2] ld: Add minimal pdb generation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011003702.4287-2-mark@harmstone.com/mbox/"},{"id":1928,"url":"https://patchwork.plctlab.org/api/1.2/patches/1928/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011175332.17156-1-mark@harmstone.com/","msgid":"<20221011175332.17156-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-11T17:53:31","name":"[v4,1/2] ld: Add --pdb option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011175332.17156-1-mark@harmstone.com/mbox/"},{"id":1929,"url":"https://patchwork.plctlab.org/api/1.2/patches/1929/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011175332.17156-2-mark@harmstone.com/","msgid":"<20221011175332.17156-2-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-11T17:53:32","name":"[v4,2/2] ld: Add minimal pdb generation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011175332.17156-2-mark@harmstone.com/mbox/"},{"id":1941,"url":"https://patchwork.plctlab.org/api/1.2/patches/1941/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221012031005.237446-1-simon.marchi@polymtl.ca/","msgid":"<20221012031005.237446-1-simon.marchi@polymtl.ca>","list_archive_url":null,"date":"2022-10-12T03:10:05","name":"[pushed] Re-apply \"Pass PKG_CONFIG_PATH down from top-level Makefile\"","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221012031005.237446-1-simon.marchi@polymtl.ca/mbox/"},{"id":1976,"url":"https://patchwork.plctlab.org/api/1.2/patches/1976/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1216a3f8-2273-8681-f528-9493a66891f0@suse.com/","msgid":"<1216a3f8-2273-8681-f528-9493a66891f0@suse.com>","list_archive_url":null,"date":"2022-10-13T08:16:49","name":"[v4,1/8] x86: constify parse_insn()'\''s input","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1216a3f8-2273-8681-f528-9493a66891f0@suse.com/mbox/"},{"id":1977,"url":"https://patchwork.plctlab.org/api/1.2/patches/1977/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/11599bbe-c779-aa9f-4d5d-c2243f0e69dc@suse.com/","msgid":"<11599bbe-c779-aa9f-4d5d-c2243f0e69dc@suse.com>","list_archive_url":null,"date":"2022-10-13T08:17:17","name":"[v4,2/8] x86: introduce Pass2 insn attribute","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/11599bbe-c779-aa9f-4d5d-c2243f0e69dc@suse.com/mbox/"},{"id":1978,"url":"https://patchwork.plctlab.org/api/1.2/patches/1978/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/357273a3-060c-23db-72da-3fc9d1be3d2a@suse.com/","msgid":"<357273a3-060c-23db-72da-3fc9d1be3d2a@suse.com>","list_archive_url":null,"date":"2022-10-13T08:18:09","name":"[v4,3/8] x86: re-work insn/suffix recognition","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/357273a3-060c-23db-72da-3fc9d1be3d2a@suse.com/mbox/"},{"id":1979,"url":"https://patchwork.plctlab.org/api/1.2/patches/1979/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0ec0587f-6a7b-45b6-8346-e5d774e73636@suse.com/","msgid":"<0ec0587f-6a7b-45b6-8346-e5d774e73636@suse.com>","list_archive_url":null,"date":"2022-10-13T08:18:39","name":"[v4,4/8] x86-64: further re-work insn/suffix recognition to also cover MOVSL","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0ec0587f-6a7b-45b6-8346-e5d774e73636@suse.com/mbox/"},{"id":1980,"url":"https://patchwork.plctlab.org/api/1.2/patches/1980/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fb617d0b-8759-3169-5a65-1178b7fef3d7@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-13T08:19:34","name":"[v4,5/8] ix86: don'\''t recognize/derive Q suffix in the common case","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fb617d0b-8759-3169-5a65-1178b7fef3d7@suse.com/mbox/"},{"id":1981,"url":"https://patchwork.plctlab.org/api/1.2/patches/1981/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1df3bd01-99c5-f56c-d937-970edd42b2b8@suse.com/","msgid":"<1df3bd01-99c5-f56c-d937-970edd42b2b8@suse.com>","list_archive_url":null,"date":"2022-10-13T08:20:14","name":"[v4,6/8] x86-64: allow HLE store of accumulator to absolute 32-bit address","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1df3bd01-99c5-f56c-d937-970edd42b2b8@suse.com/mbox/"},{"id":1982,"url":"https://patchwork.plctlab.org/api/1.2/patches/1982/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8486a218-39ec-16b2-5c6c-5037196b93cf@suse.com/","msgid":"<8486a218-39ec-16b2-5c6c-5037196b93cf@suse.com>","list_archive_url":null,"date":"2022-10-13T08:21:00","name":"[v4,7/8] x86: move bad-use-of-TLS-reloc check","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8486a218-39ec-16b2-5c6c-5037196b93cf@suse.com/mbox/"},{"id":1983,"url":"https://patchwork.plctlab.org/api/1.2/patches/1983/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7d82692d-93df-fbee-9efb-2f44e8a91df3@suse.com/","msgid":"<7d82692d-93df-fbee-9efb-2f44e8a91df3@suse.com>","list_archive_url":null,"date":"2022-10-13T08:22:00","name":"[v4,8/8] x86: drop (now) stray IsString","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7d82692d-93df-fbee-9efb-2f44e8a91df3@suse.com/mbox/"},{"id":2013,"url":"https://patchwork.plctlab.org/api/1.2/patches/2013/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8ab93d7a617ad480dd786210f46db0e5aa07d1ac.1665655719.git.research_trasio@irq.a4lg.com/","msgid":"<8ab93d7a617ad480dd786210f46db0e5aa07d1ac.1665655719.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-13T10:11:41","name":"include: Declare getopt function on old GNU libc","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8ab93d7a617ad480dd786210f46db0e5aa07d1ac.1665655719.git.research_trasio@irq.a4lg.com/mbox/"},{"id":2352,"url":"https://patchwork.plctlab.org/api/1.2/patches/2352/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221013201332.2747246-1-maskray@google.com/","msgid":"<20221013201332.2747246-1-maskray@google.com>","list_archive_url":null,"date":"2022-10-13T20:13:32","name":"ld: Add --undefined-version","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221013201332.2747246-1-maskray@google.com/mbox/"},{"id":2532,"url":"https://patchwork.plctlab.org/api/1.2/patches/2532/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014063520.1428330-2-zengxiao@eswincomputing.com/","msgid":"<20221014063520.1428330-2-zengxiao@eswincomputing.com>","list_archive_url":null,"date":"2022-10-14T06:35:20","name":"[1/1] RISC-V: Make R_RISCV_SUB6 conforms to riscv abi standard","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014063520.1428330-2-zengxiao@eswincomputing.com/mbox/"},{"id":2560,"url":"https://patchwork.plctlab.org/api/1.2/patches/2560/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/027ae69a-636b-6757-297a-eec42936401e@linaro.org/","msgid":"<027ae69a-636b-6757-297a-eec42936401e@linaro.org>","list_archive_url":null,"date":"2022-10-14T07:58:22","name":"[v3] aarch64-pe support for LD, GAS and BFD","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/027ae69a-636b-6757-297a-eec42936401e@linaro.org/mbox/"},{"id":2602,"url":"https://patchwork.plctlab.org/api/1.2/patches/2602/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-2-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-2-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:39","name":"[01/10] Support Intel AVX-IFMA","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-2-haochen.jiang@intel.com/mbox/"},{"id":2608,"url":"https://patchwork.plctlab.org/api/1.2/patches/2608/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-3-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-3-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:40","name":"[02/10] Support Intel AVX-VNNI-INT8","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-3-haochen.jiang@intel.com/mbox/"},{"id":2611,"url":"https://patchwork.plctlab.org/api/1.2/patches/2611/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-4-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-4-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:41","name":"[03/10] Support Intel AVX-NE-CONVERT","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-4-haochen.jiang@intel.com/mbox/"},{"id":2610,"url":"https://patchwork.plctlab.org/api/1.2/patches/2610/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-5-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-5-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:42","name":"[04/10] Support Intel CMPccXADD","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-5-haochen.jiang@intel.com/mbox/"},{"id":2601,"url":"https://patchwork.plctlab.org/api/1.2/patches/2601/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-6-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-6-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:43","name":"[05/10] Add handler for more i386_cpu_flags","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-6-haochen.jiang@intel.com/mbox/"},{"id":2606,"url":"https://patchwork.plctlab.org/api/1.2/patches/2606/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-7-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-7-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:44","name":"[06/10] Support Intel RAO-INT","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-7-haochen.jiang@intel.com/mbox/"},{"id":2609,"url":"https://patchwork.plctlab.org/api/1.2/patches/2609/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-8-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-8-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:45","name":"[07/10] Support Intel WRMSRNS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-8-haochen.jiang@intel.com/mbox/"},{"id":2605,"url":"https://patchwork.plctlab.org/api/1.2/patches/2605/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-9-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-9-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:46","name":"[08/10] Support Intel MSRLIST","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-9-haochen.jiang@intel.com/mbox/"},{"id":2607,"url":"https://patchwork.plctlab.org/api/1.2/patches/2607/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-10-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-10-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:47","name":"[09/10] Support Intel AMX-FP16","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-10-haochen.jiang@intel.com/mbox/"},{"id":2604,"url":"https://patchwork.plctlab.org/api/1.2/patches/2604/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-11-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-11-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:48","name":"[10/10] Support Intel PREFETCHI","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-11-haochen.jiang@intel.com/mbox/"},{"id":2643,"url":"https://patchwork.plctlab.org/api/1.2/patches/2643/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7bac66be-535e-9051-d674-f2f5ba180e17@suse.com/","msgid":"<7bac66be-535e-9051-d674-f2f5ba180e17@suse.com>","list_archive_url":null,"date":"2022-10-14T10:22:34","name":"x86: fold AVX512-VNNI disassembler entries with AVX-VNNI ones","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7bac66be-535e-9051-d674-f2f5ba180e17@suse.com/mbox/"},{"id":2654,"url":"https://patchwork.plctlab.org/api/1.2/patches/2654/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0lIo5+ncY/MqBEq@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-14T11:31:47","name":"PR29677, Field `the_bfd` of `asymbol` is uninitialised","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0lIo5+ncY/MqBEq@squeak.grove.modra.org/mbox/"},{"id":2656,"url":"https://patchwork.plctlab.org/api/1.2/patches/2656/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0lJksn49ZpABY89@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-14T11:35:46","name":"e200 LSP support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0lJksn49ZpABY89@squeak.grove.modra.org/mbox/"},{"id":2657,"url":"https://patchwork.plctlab.org/api/1.2/patches/2657/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0lJxxYoeD5iDYAD@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-14T11:36:39","name":"PowerPC SPE disassembly and tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0lJxxYoeD5iDYAD@squeak.grove.modra.org/mbox/"},{"id":2695,"url":"https://patchwork.plctlab.org/api/1.2/patches/2695/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/DM6PR12MB4219611F6CC2A0702884A602E7249@DM6PR12MB4219.namprd12.prod.outlook.com/","msgid":"","list_archive_url":null,"date":"2022-10-14T13:29:40","name":"Binutils: Adding new testcase for addr2line.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/DM6PR12MB4219611F6CC2A0702884A602E7249@DM6PR12MB4219.namprd12.prod.outlook.com/mbox/"},{"id":2700,"url":"https://patchwork.plctlab.org/api/1.2/patches/2700/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9fd2c88d-98b2-99a4-419f-c7235b2cf960@suse.com/","msgid":"<9fd2c88d-98b2-99a4-419f-c7235b2cf960@suse.com>","list_archive_url":null,"date":"2022-10-14T14:11:35","name":"x86: properly decode EVEX.W for AVX512_4{FMAPS,VNNIW} insns","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9fd2c88d-98b2-99a4-419f-c7235b2cf960@suse.com/mbox/"},{"id":2981,"url":"https://patchwork.plctlab.org/api/1.2/patches/2981/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0uLzalqjm4C87GN@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-16T04:42:53","name":"PowerPC se_rfmci and VLE, SPE2 and LSP insns with -many","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0uLzalqjm4C87GN@squeak.grove.modra.org/mbox/"},{"id":3152,"url":"https://patchwork.plctlab.org/api/1.2/patches/3152/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221016232419.1135-1-mark@harmstone.com/","msgid":"<20221016232419.1135-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-16T23:24:18","name":"[v5,1/2] ld: Add --pdb option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221016232419.1135-1-mark@harmstone.com/mbox/"},{"id":3151,"url":"https://patchwork.plctlab.org/api/1.2/patches/3151/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221016232419.1135-2-mark@harmstone.com/","msgid":"<20221016232419.1135-2-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-16T23:24:19","name":"[v5,2/2] ld: Add minimal pdb generation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221016232419.1135-2-mark@harmstone.com/mbox/"},{"id":3258,"url":"https://patchwork.plctlab.org/api/1.2/patches/3258/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/19c08747-fa5b-1e67-3dd2-c891a2c0c1fa@suse.com/","msgid":"<19c08747-fa5b-1e67-3dd2-c891a2c0c1fa@suse.com>","list_archive_url":null,"date":"2022-10-17T07:44:51","name":"x86: correct CPU_AMX_{BF16,INT8}_FLAGS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/19c08747-fa5b-1e67-3dd2-c891a2c0c1fa@suse.com/mbox/"},{"id":3272,"url":"https://patchwork.plctlab.org/api/1.2/patches/3272/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/85dd526c-d3a7-72dc-5444-ed5573eebec1@suse.com/","msgid":"<85dd526c-d3a7-72dc-5444-ed5573eebec1@suse.com>","list_archive_url":null,"date":"2022-10-17T08:30:12","name":"x86: generalize gas documentation for disabling of ISA extensions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/85dd526c-d3a7-72dc-5444-ed5573eebec1@suse.com/mbox/"},{"id":3759,"url":"https://patchwork.plctlab.org/api/1.2/patches/3759/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-2-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-2-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:15:58","name":"[V2,01/15] sframe.h: Add SFrame format definition","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-2-indu.bhagat@oracle.com/mbox/"},{"id":3762,"url":"https://patchwork.plctlab.org/api/1.2/patches/3762/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-3-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-3-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:15:59","name":"[V2,02/15] gas: add new command line option --gsframe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-3-indu.bhagat@oracle.com/mbox/"},{"id":3761,"url":"https://patchwork.plctlab.org/api/1.2/patches/3761/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-4-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-4-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:00","name":"[V2,03/15] gas: generate .sframe from CFI directives","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-4-indu.bhagat@oracle.com/mbox/"},{"id":3760,"url":"https://patchwork.plctlab.org/api/1.2/patches/3760/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-5-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-5-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:01","name":"[V2,04/15] gas: testsuite: add new tests for SFrame unwind info","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-5-indu.bhagat@oracle.com/mbox/"},{"id":3764,"url":"https://patchwork.plctlab.org/api/1.2/patches/3764/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-6-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-6-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:02","name":"[V2,05/15] libsframe: add the SFrame library","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-6-indu.bhagat@oracle.com/mbox/"},{"id":3766,"url":"https://patchwork.plctlab.org/api/1.2/patches/3766/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-7-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-7-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:03","name":"[V2,06/15] bfd: linker: merge .sframe sections","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-7-indu.bhagat@oracle.com/mbox/"},{"id":3763,"url":"https://patchwork.plctlab.org/api/1.2/patches/3763/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-8-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-8-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:04","name":"[V2,07/15] readelf/objdump: support for SFrame section","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-8-indu.bhagat@oracle.com/mbox/"},{"id":3765,"url":"https://patchwork.plctlab.org/api/1.2/patches/3765/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-9-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-9-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:05","name":"[V2,08/15] unwinder: generate backtrace using SFrame format","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-9-indu.bhagat@oracle.com/mbox/"},{"id":3770,"url":"https://patchwork.plctlab.org/api/1.2/patches/3770/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-10-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-10-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:06","name":"[V2,09/15] unwinder: Add SFrame unwinder tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-10-indu.bhagat@oracle.com/mbox/"},{"id":3769,"url":"https://patchwork.plctlab.org/api/1.2/patches/3769/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-11-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-11-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:07","name":"[V2,10/15] gdb: sim: buildsystem changes to accommodate libsframe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-11-indu.bhagat@oracle.com/mbox/"},{"id":3771,"url":"https://patchwork.plctlab.org/api/1.2/patches/3771/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-12-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-12-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:08","name":"[V2,11/15] libctf: add libsframe to LDFLAGS and LIBS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-12-indu.bhagat@oracle.com/mbox/"},{"id":3768,"url":"https://patchwork.plctlab.org/api/1.2/patches/3768/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-13-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-13-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:09","name":"[V2,12/15] src-release.sh: Add libsframe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-13-indu.bhagat@oracle.com/mbox/"},{"id":3767,"url":"https://patchwork.plctlab.org/api/1.2/patches/3767/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-14-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-14-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:10","name":"[V2,13/15] binutils/NEWS: add text for SFrame support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-14-indu.bhagat@oracle.com/mbox/"},{"id":3772,"url":"https://patchwork.plctlab.org/api/1.2/patches/3772/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-15-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-15-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:11","name":"[V2,14/15] gas/NEWS: add text about new command line option and SFrame support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-15-indu.bhagat@oracle.com/mbox/"},{"id":3773,"url":"https://patchwork.plctlab.org/api/1.2/patches/3773/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-16-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-16-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:12","name":"[V2,15/15] doc: add SFrame spec file","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-16-indu.bhagat@oracle.com/mbox/"},{"id":3999,"url":"https://patchwork.plctlab.org/api/1.2/patches/3999/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221018081205.17880-1-krebbel@linux.ibm.com/","msgid":"<20221018081205.17880-1-krebbel@linux.ibm.com>","list_archive_url":null,"date":"2022-10-18T08:12:05","name":"[1/1] IBM zSystems: Issue error for *DBL relocs on misaligned symbols","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221018081205.17880-1-krebbel@linux.ibm.com/mbox/"},{"id":4141,"url":"https://patchwork.plctlab.org/api/1.2/patches/4141/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/baffaf673f17692b7bcbd604b31800b189988596.camel@espressif.com/","msgid":"","list_archive_url":null,"date":"2022-10-18T12:12:07","name":"xtensa: use definitions from xtensa-config.h","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/baffaf673f17692b7bcbd604b31800b189988596.camel@espressif.com/mbox/"},{"id":4272,"url":"https://patchwork.plctlab.org/api/1.2/patches/4272/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221018174914.470062-1-hjl.tools@gmail.com/","msgid":"<20221018174914.470062-1-hjl.tools@gmail.com>","list_archive_url":null,"date":"2022-10-18T17:49:14","name":"x86: Disable AVX-VNNI when disabling AVX2","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221018174914.470062-1-hjl.tools@gmail.com/mbox/"},{"id":4998,"url":"https://patchwork.plctlab.org/api/1.2/patches/4998/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c2f76e95-09f6-1d92-7ef4-38a3c2955fcd@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-19T09:52:46","name":"x86: re-work AVX-VNNI support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c2f76e95-09f6-1d92-7ef4-38a3c2955fcd@suse.com/mbox/"},{"id":5276,"url":"https://patchwork.plctlab.org/api/1.2/patches/5276/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0/lLtlKqqsmAx0s@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-19T11:53:18","name":"Fix addr2line test for ppc64 elfv1 and mingw","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0/lLtlKqqsmAx0s@squeak.grove.modra.org/mbox/"},{"id":5424,"url":"https://patchwork.plctlab.org/api/1.2/patches/5424/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/07bfebbf3843b47e13d82d4fa16eb14fec942ef7.1666184962.git.research_trasio@irq.a4lg.com/","msgid":"<07bfebbf3843b47e13d82d4fa16eb14fec942ef7.1666184962.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:09:54","name":"binutils: Remove unused substitution PROGRAM","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/07bfebbf3843b47e13d82d4fa16eb14fec942ef7.1666184962.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5433,"url":"https://patchwork.plctlab.org/api/1.2/patches/5433/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2fa7ff719223232402e82a9c91331aea22ace1bb.1666185116.git.research_trasio@irq.a4lg.com/","msgid":"<2fa7ff719223232402e82a9c91331aea22ace1bb.1666185116.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:11:55","name":"[v2,1/8] RISC-V: Add a space at the end of pinfo","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2fa7ff719223232402e82a9c91331aea22ace1bb.1666185116.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5435,"url":"https://patchwork.plctlab.org/api/1.2/patches/5435/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1b30cce5db2cce3b8edca42ab5da114d0b8c9e93.1666185116.git.research_trasio@irq.a4lg.com/","msgid":"<1b30cce5db2cce3b8edca42ab5da114d0b8c9e93.1666185116.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:11:56","name":"[v2,2/8] RISC-V: Fix obvious misalignments ('\''Zbb'\''/'\''Zba'\'')","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1b30cce5db2cce3b8edca42ab5da114d0b8c9e93.1666185116.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5437,"url":"https://patchwork.plctlab.org/api/1.2/patches/5437/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6b0857aa1a2d15ca1cf00b4dcaae0032efbb88ff.1666185116.git.research_trasio@irq.a4lg.com/","msgid":"<6b0857aa1a2d15ca1cf00b4dcaae0032efbb88ff.1666185116.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:11:57","name":"[v2,3/8] RISC-V: Remove spaces in opcode entries","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6b0857aa1a2d15ca1cf00b4dcaae0032efbb88ff.1666185116.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5436,"url":"https://patchwork.plctlab.org/api/1.2/patches/5436/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/889d956caac0f2e95543a14afaeed97188ce384c.1666185116.git.research_trasio@irq.a4lg.com/","msgid":"<889d956caac0f2e95543a14afaeed97188ce384c.1666185116.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:11:58","name":"[v2,4/8] RISC-V: Remove unused instruction macros","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/889d956caac0f2e95543a14afaeed97188ce384c.1666185116.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5440,"url":"https://patchwork.plctlab.org/api/1.2/patches/5440/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8f226ee20d8a5ef6ad7b6c4408b44794a99d542a.1666185116.git.research_trasio@irq.a4lg.com/","msgid":"<8f226ee20d8a5ef6ad7b6c4408b44794a99d542a.1666185116.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:11:59","name":"[v2,5/8] RISC-V: Complete tidying up with SCALL and SBREAK","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8f226ee20d8a5ef6ad7b6c4408b44794a99d542a.1666185116.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5442,"url":"https://patchwork.plctlab.org/api/1.2/patches/5442/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4070184c454a05a39adf0790951e5856e6b2ecb6.1666185116.git.research_trasio@irq.a4lg.com/","msgid":"<4070184c454a05a39adf0790951e5856e6b2ecb6.1666185116.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:12:00","name":"[v2,6/8] RISC-V: Tidying up with fmv.w.x and fmv.x.w","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4070184c454a05a39adf0790951e5856e6b2ecb6.1666185116.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5438,"url":"https://patchwork.plctlab.org/api/1.2/patches/5438/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c1ccda3e7c8fb297eda46dab3936d5c5977178fc.1666185116.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-19T13:12:01","name":"[v2,7/8] RISC-V: Make alias instructions aliases","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c1ccda3e7c8fb297eda46dab3936d5c5977178fc.1666185116.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5441,"url":"https://patchwork.plctlab.org/api/1.2/patches/5441/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/413cfca82c7e8d8a2e977dfda9135903c9cb7c57.1666185116.git.research_trasio@irq.a4lg.com/","msgid":"<413cfca82c7e8d8a2e977dfda9135903c9cb7c57.1666185116.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:12:02","name":"[v2,8/8] RISC-V: Use defined mask and match values","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/413cfca82c7e8d8a2e977dfda9135903c9cb7c57.1666185116.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5439,"url":"https://patchwork.plctlab.org/api/1.2/patches/5439/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/345c5c3b3a53eab04a1e6e91197de2642095c94f.1666185237.git.research_trasio@irq.a4lg.com/","msgid":"<345c5c3b3a53eab04a1e6e91197de2642095c94f.1666185237.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:14:01","name":"RISC-V: Remove RV32EF conflict","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/345c5c3b3a53eab04a1e6e91197de2642095c94f.1666185237.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5616,"url":"https://patchwork.plctlab.org/api/1.2/patches/5616/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019145608.45213-5-haochen.jiang@intel.com/","msgid":"<20221019145608.45213-5-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T14:56:02","name":"[04/10] Support Intel CMPccXADD","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019145608.45213-5-haochen.jiang@intel.com/mbox/"},{"id":5614,"url":"https://patchwork.plctlab.org/api/1.2/patches/5614/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019145608.45213-6-haochen.jiang@intel.com/","msgid":"<20221019145608.45213-6-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T14:56:03","name":"[05/10] Add handler for more i386_cpu_flags","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019145608.45213-6-haochen.jiang@intel.com/mbox/"},{"id":5672,"url":"https://patchwork.plctlab.org/api/1.2/patches/5672/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-2-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-2-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:25","name":"[01/10] Support Intel AVX-IFMA","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-2-haochen.jiang@intel.com/mbox/"},{"id":5691,"url":"https://patchwork.plctlab.org/api/1.2/patches/5691/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-3-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-3-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:26","name":"[02/10] Support Intel AVX-VNNI-INT8","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-3-haochen.jiang@intel.com/mbox/"},{"id":5690,"url":"https://patchwork.plctlab.org/api/1.2/patches/5690/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-4-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-4-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:27","name":"[03/10] Support Intel AVX-NE-CONVERT","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-4-haochen.jiang@intel.com/mbox/"},{"id":5689,"url":"https://patchwork.plctlab.org/api/1.2/patches/5689/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-5-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-5-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:28","name":"[04/10] Support Intel CMPccXADD","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-5-haochen.jiang@intel.com/mbox/"},{"id":5676,"url":"https://patchwork.plctlab.org/api/1.2/patches/5676/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-6-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-6-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:29","name":"[05/10] Add handler for more i386_cpu_flags","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-6-haochen.jiang@intel.com/mbox/"},{"id":5677,"url":"https://patchwork.plctlab.org/api/1.2/patches/5677/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-7-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-7-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:30","name":"[06/10] Support Intel RAO-INT","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-7-haochen.jiang@intel.com/mbox/"},{"id":5681,"url":"https://patchwork.plctlab.org/api/1.2/patches/5681/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-8-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-8-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:31","name":"[07/10] Support Intel WRMSRNS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-8-haochen.jiang@intel.com/mbox/"},{"id":5682,"url":"https://patchwork.plctlab.org/api/1.2/patches/5682/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-9-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-9-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:32","name":"[08/10] Support Intel MSRLIST","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-9-haochen.jiang@intel.com/mbox/"},{"id":5673,"url":"https://patchwork.plctlab.org/api/1.2/patches/5673/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-10-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-10-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:33","name":"[09/10] Support Intel AMX-FP16","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-10-haochen.jiang@intel.com/mbox/"},{"id":5686,"url":"https://patchwork.plctlab.org/api/1.2/patches/5686/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-11-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-11-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:34","name":"[10/10] Support Intel PREFETCHI","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-11-haochen.jiang@intel.com/mbox/"},{"id":5940,"url":"https://patchwork.plctlab.org/api/1.2/patches/5940/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1CMrFUC8d9lC/NL@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-19T23:47:56","name":"Obsolete beos","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1CMrFUC8d9lC/NL@squeak.grove.modra.org/mbox/"},{"id":6080,"url":"https://patchwork.plctlab.org/api/1.2/patches/6080/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8b99d666e78ba5b9d32c7889a2161c70b3da88df.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<8b99d666e78ba5b9d32c7889a2161c70b3da88df.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:25:47","name":"[01/40] gdb/unittests: PR28413, suppress warnings generated by Gnulib","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8b99d666e78ba5b9d32c7889a2161c70b3da88df.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6081,"url":"https://patchwork.plctlab.org/api/1.2/patches/6081/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b05adb17e401d621dbdad791281bc7af7806906e.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-20T09:25:48","name":"[02/40] sim: Check known getrusage declaration existence","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b05adb17e401d621dbdad791281bc7af7806906e.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6083,"url":"https://patchwork.plctlab.org/api/1.2/patches/6083/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/796962a87e569feeafb5ef636de3c79000ae152c.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<796962a87e569feeafb5ef636de3c79000ae152c.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:25:49","name":"[03/40] sim/aarch64: Remove unused functions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/796962a87e569feeafb5ef636de3c79000ae152c.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6084,"url":"https://patchwork.plctlab.org/api/1.2/patches/6084/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/65223c79fdfd7faf132275415cd9da9852c5bec3.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<65223c79fdfd7faf132275415cd9da9852c5bec3.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:25:50","name":"[04/40] cpu/cris: Initialize some variables on CRIS CPU","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/65223c79fdfd7faf132275415cd9da9852c5bec3.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6082,"url":"https://patchwork.plctlab.org/api/1.2/patches/6082/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/24baefe92148f4b7968115ba13de9b0c863a65f6.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<24baefe92148f4b7968115ba13de9b0c863a65f6.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:25:51","name":"[05/40] cpu/cris: Add u-stall virtual unit to CRIS v32","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/24baefe92148f4b7968115ba13de9b0c863a65f6.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6087,"url":"https://patchwork.plctlab.org/api/1.2/patches/6087/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3904a5c3e80f8548150d8088a92059dd728c7ff8.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<3904a5c3e80f8548150d8088a92059dd728c7ff8.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:25:52","name":"[06/40] sim/cris: Move declarations of f_specific_init","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3904a5c3e80f8548150d8088a92059dd728c7ff8.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6091,"url":"https://patchwork.plctlab.org/api/1.2/patches/6091/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/69ef2d7dd519ed572511890a215a0f6d74e53384.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<69ef2d7dd519ed572511890a215a0f6d74e53384.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:25:53","name":"[07/40] sim/cris: Regenerate with CGEN","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/69ef2d7dd519ed572511890a215a0f6d74e53384.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6085,"url":"https://patchwork.plctlab.org/api/1.2/patches/6085/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/26a3eaf4f5d2e0db6977738ddfd65d82b36e38b2.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<26a3eaf4f5d2e0db6977738ddfd65d82b36e38b2.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:25:54","name":"[08/40] sim/erc32: Insert void parameter","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/26a3eaf4f5d2e0db6977738ddfd65d82b36e38b2.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6086,"url":"https://patchwork.plctlab.org/api/1.2/patches/6086/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/057c2f8392410494c3bc5dc98052246508e6a73e.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<057c2f8392410494c3bc5dc98052246508e6a73e.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:25:55","name":"[09/40] sim/erc32: Use int32_t as event callback argument","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/057c2f8392410494c3bc5dc98052246508e6a73e.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6090,"url":"https://patchwork.plctlab.org/api/1.2/patches/6090/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8c05aec20557191434485be347d37177a2ec5ff2.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<8c05aec20557191434485be347d37177a2ec5ff2.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:25:56","name":"[10/40] sim/erc32: Use int32_t as IRQ callback argument","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8c05aec20557191434485be347d37177a2ec5ff2.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6089,"url":"https://patchwork.plctlab.org/api/1.2/patches/6089/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/afd7757aae21743c29f2aa4135a23b31d4959e9b.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-20T09:25:57","name":"[11/40] cpu/frv: Initialize some variables","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/afd7757aae21743c29f2aa4135a23b31d4959e9b.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6088,"url":"https://patchwork.plctlab.org/api/1.2/patches/6088/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/021dbd238af5dfe74523ed229d2156a155a6bb9e.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<021dbd238af5dfe74523ed229d2156a155a6bb9e.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:25:58","name":"[12/40] sim/frv: Initialize nesr variable","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/021dbd238af5dfe74523ed229d2156a155a6bb9e.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6093,"url":"https://patchwork.plctlab.org/api/1.2/patches/6093/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/51a03f7097921cc48954210cf99e370ae8982ec8.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<51a03f7097921cc48954210cf99e370ae8982ec8.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:25:59","name":"[13/40] sim/frv: Initialize some variables","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/51a03f7097921cc48954210cf99e370ae8982ec8.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6092,"url":"https://patchwork.plctlab.org/api/1.2/patches/6092/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e1baa1be3601612266dc6ae0bdde8426ff2a42c8.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-20T09:26:00","name":"[14/40] sim/frv: Add explicit casts","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e1baa1be3601612266dc6ae0bdde8426ff2a42c8.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6095,"url":"https://patchwork.plctlab.org/api/1.2/patches/6095/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5ab303a5bdfc1da7832f8fa22f57678c9ef1a5fa.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<5ab303a5bdfc1da7832f8fa22f57678c9ef1a5fa.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:26:01","name":"[15/40] sim/h8300: Add \"+ 0x0\" to avoid self-assignments","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5ab303a5bdfc1da7832f8fa22f57678c9ef1a5fa.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6101,"url":"https://patchwork.plctlab.org/api/1.2/patches/6101/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ddff80db3328a2286fe6fbc1240d2abc1e3813eb.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-20T09:26:02","name":"[16/40] sim/lm32: fix some missing function declaration warnings","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ddff80db3328a2286fe6fbc1240d2abc1e3813eb.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6094,"url":"https://patchwork.plctlab.org/api/1.2/patches/6094/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e094b1379231d9ffb59a78cfebbcc84634c779c6.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-20T09:26:03","name":"[17/40] sim/lm32: Add explicit casts","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e094b1379231d9ffb59a78cfebbcc84634c779c6.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6141,"url":"https://patchwork.plctlab.org/api/1.2/patches/6141/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/cabebead-489b-528c-580e-933832417474@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-20T10:25:51","name":"[1/3] x86: emit {evex} prefix when disassembling ambiguous AVX512VL insns","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/cabebead-489b-528c-580e-933832417474@suse.com/mbox/"},{"id":6143,"url":"https://patchwork.plctlab.org/api/1.2/patches/6143/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a032d61c-63a0-23d1-331f-619a2b8bbde3@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-20T10:26:15","name":"[2/3] x86: consolidate VAES tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a032d61c-63a0-23d1-331f-619a2b8bbde3@suse.com/mbox/"},{"id":6142,"url":"https://patchwork.plctlab.org/api/1.2/patches/6142/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7ff09c86-2de7-dc34-3183-5187de3df5ac@suse.com/","msgid":"<7ff09c86-2de7-dc34-3183-5187de3df5ac@suse.com>","list_archive_url":null,"date":"2022-10-20T10:26:40","name":"[3/3] x86: consolidate VPCLMUL tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7ff09c86-2de7-dc34-3183-5187de3df5ac@suse.com/mbox/"},{"id":6228,"url":"https://patchwork.plctlab.org/api/1.2/patches/6228/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.LSU.2.20.2210201432170.29399@wotan.suse.de/","msgid":"","list_archive_url":null,"date":"2022-10-20T14:42:25","name":"x86-64: Use only one default max-page-size","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.LSU.2.20.2210201432170.29399@wotan.suse.de/mbox/"},{"id":6229,"url":"https://patchwork.plctlab.org/api/1.2/patches/6229/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221020144351.1398099-1-chigot@adacore.com/","msgid":"<20221020144351.1398099-1-chigot@adacore.com>","list_archive_url":null,"date":"2022-10-20T14:43:50","name":"[1/2] ld/testsuite: skip ld-elf/exclude when -shared is not supported","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221020144351.1398099-1-chigot@adacore.com/mbox/"},{"id":6230,"url":"https://patchwork.plctlab.org/api/1.2/patches/6230/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221020144351.1398099-2-chigot@adacore.com/","msgid":"<20221020144351.1398099-2-chigot@adacore.com>","list_archive_url":null,"date":"2022-10-20T14:43:51","name":"[2/2] ld/testsuite: adjust ld-arm to run shared tests only when supported","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221020144351.1398099-2-chigot@adacore.com/mbox/"},{"id":6236,"url":"https://patchwork.plctlab.org/api/1.2/patches/6236/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221020151027.GA1300@delia.home/","msgid":"<20221020151027.GA1300@delia.home>","list_archive_url":null,"date":"2022-10-20T15:10:28","name":"[RFC,top-level] Add configure test-case","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221020151027.GA1300@delia.home/mbox/"},{"id":6286,"url":"https://patchwork.plctlab.org/api/1.2/patches/6286/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221020162911.1113338-1-hjl.tools@gmail.com/","msgid":"<20221020162911.1113338-1-hjl.tools@gmail.com>","list_archive_url":null,"date":"2022-10-20T16:29:11","name":"x86: Check VEX/EVEX encoding before checking vector operands","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221020162911.1113338-1-hjl.tools@gmail.com/mbox/"},{"id":7884,"url":"https://patchwork.plctlab.org/api/1.2/patches/7884/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7e53b7980f2b3b74d2250bc87f5db94b1d888a2d.camel@espressif.com/","msgid":"<7e53b7980f2b3b74d2250bc87f5db94b1d888a2d.camel@espressif.com>","list_archive_url":null,"date":"2022-10-22T12:53:54","name":"[1/5] bfd: xtensa: move common code from ld and gas","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7e53b7980f2b3b74d2250bc87f5db94b1d888a2d.camel@espressif.com/mbox/"},{"id":7885,"url":"https://patchwork.plctlab.org/api/1.2/patches/7885/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/63f2699e6ef3e6d1ca415a6ed1187d4f64297521.camel@espressif.com/","msgid":"<63f2699e6ef3e6d1ca415a6ed1187d4f64297521.camel@espressif.com>","list_archive_url":null,"date":"2022-10-22T12:55:16","name":"[2/5] gas: xtensa: add endianness, loops, booleans options","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/63f2699e6ef3e6d1ca415a6ed1187d4f64297521.camel@espressif.com/mbox/"},{"id":7886,"url":"https://patchwork.plctlab.org/api/1.2/patches/7886/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/34d2f747237aeeda595560cfded8096d9bd1c28c.camel@espressif.com/","msgid":"<34d2f747237aeeda595560cfded8096d9bd1c28c.camel@espressif.com>","list_archive_url":null,"date":"2022-10-22T12:56:02","name":"[3/5] ld: xtensa: use default LD command line options for endianness","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/34d2f747237aeeda595560cfded8096d9bd1c28c.camel@espressif.com/mbox/"},{"id":7891,"url":"https://patchwork.plctlab.org/api/1.2/patches/7891/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/535b6208c1718b9acf3258575e1ebc0a65af9f07.camel@espressif.com/","msgid":"<535b6208c1718b9acf3258575e1ebc0a65af9f07.camel@espressif.com>","list_archive_url":null,"date":"2022-10-22T13:56:44","name":"[5/5] gdb: xtensa: add support for esp32, esp32s2, esp32s3 isa-modules","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/535b6208c1718b9acf3258575e1ebc0a65af9f07.camel@espressif.com/mbox/"},{"id":10456,"url":"https://patchwork.plctlab.org/api/1.2/patches/10456/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221025013347.68282-1-nelson@rivosinc.com/","msgid":"<20221025013347.68282-1-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-10-25T01:33:46","name":"[committed,1/2] RISC-V: Improve link time complexity.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221025013347.68282-1-nelson@rivosinc.com/mbox/"},{"id":10454,"url":"https://patchwork.plctlab.org/api/1.2/patches/10454/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221025013347.68282-2-nelson@rivosinc.com/","msgid":"<20221025013347.68282-2-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-10-25T01:33:47","name":"[committed,2/2] RISC-V: Should reset `again'\'' flag for _bfd_riscv_relax_pc.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221025013347.68282-2-nelson@rivosinc.com/mbox/"},{"id":10536,"url":"https://patchwork.plctlab.org/api/1.2/patches/10536/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/bb7b87e4-1893-5c86-4a14-92bafc818b03@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-25T07:24:56","name":"[v5,1/8] x86: constify parse_insn()'\''s input","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/bb7b87e4-1893-5c86-4a14-92bafc818b03@suse.com/mbox/"},{"id":10537,"url":"https://patchwork.plctlab.org/api/1.2/patches/10537/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b9273ae6-0218-54f8-5374-b265ed13b71a@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-25T07:25:26","name":"[v5,1/8] x86: introduce Pass2 insn attribute","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b9273ae6-0218-54f8-5374-b265ed13b71a@suse.com/mbox/"},{"id":10541,"url":"https://patchwork.plctlab.org/api/1.2/patches/10541/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7250dab9-e218-e6dd-4c74-23da9f611ab4@suse.com/","msgid":"<7250dab9-e218-e6dd-4c74-23da9f611ab4@suse.com>","list_archive_url":null,"date":"2022-10-25T07:26:11","name":"[v5,3/8] x86: re-work insn/suffix recognition","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7250dab9-e218-e6dd-4c74-23da9f611ab4@suse.com/mbox/"},{"id":10540,"url":"https://patchwork.plctlab.org/api/1.2/patches/10540/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/13fc630f-e116-0099-5c9e-2697df6519d7@suse.com/","msgid":"<13fc630f-e116-0099-5c9e-2697df6519d7@suse.com>","list_archive_url":null,"date":"2022-10-25T07:26:40","name":"[v5,4/8] ix86: don'\''t recognize/derive Q suffix in the common case","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/13fc630f-e116-0099-5c9e-2697df6519d7@suse.com/mbox/"},{"id":10543,"url":"https://patchwork.plctlab.org/api/1.2/patches/10543/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/74db429d-d203-eab8-4ae1-18b9ad416b02@suse.com/","msgid":"<74db429d-d203-eab8-4ae1-18b9ad416b02@suse.com>","list_archive_url":null,"date":"2022-10-25T07:27:11","name":"[v5,5/8] x86-64: allow HLE store of accumulator to absolute 32-bit address","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/74db429d-d203-eab8-4ae1-18b9ad416b02@suse.com/mbox/"},{"id":10542,"url":"https://patchwork.plctlab.org/api/1.2/patches/10542/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2e2f7841-de4e-b5de-e8d9-a47a6a4113c8@suse.com/","msgid":"<2e2f7841-de4e-b5de-e8d9-a47a6a4113c8@suse.com>","list_archive_url":null,"date":"2022-10-25T07:27:35","name":"[v5,6/8] x86: move bad-use-of-TLS-reloc check","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2e2f7841-de4e-b5de-e8d9-a47a6a4113c8@suse.com/mbox/"},{"id":10545,"url":"https://patchwork.plctlab.org/api/1.2/patches/10545/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/421bc96e-7591-6980-48e9-5af8c8b0775a@suse.com/","msgid":"<421bc96e-7591-6980-48e9-5af8c8b0775a@suse.com>","list_archive_url":null,"date":"2022-10-25T07:28:27","name":"[v5,7/8] x86: drop (now) stray IsString","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/421bc96e-7591-6980-48e9-5af8c8b0775a@suse.com/mbox/"},{"id":10546,"url":"https://patchwork.plctlab.org/api/1.2/patches/10546/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/06ff83d4-4633-a07b-70e5-a8e049981dd4@suse.com/","msgid":"<06ff83d4-4633-a07b-70e5-a8e049981dd4@suse.com>","list_archive_url":null,"date":"2022-10-25T07:29:18","name":"[v5,8/8] x86: further re-work insn/suffix recognition to also cover MOVSX","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/06ff83d4-4633-a07b-70e5-a8e049981dd4@suse.com/mbox/"},{"id":10777,"url":"https://patchwork.plctlab.org/api/1.2/patches/10777/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6a8e7a71acccd0efb9789dfb3edfa307e83bdaa1.1666702934.git.research_trasio@irq.a4lg.com/","msgid":"<6a8e7a71acccd0efb9789dfb3edfa307e83bdaa1.1666702934.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-25T13:04:02","name":"[RFC] RISC-V: Allocate \"various\" operand type","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6a8e7a71acccd0efb9789dfb3edfa307e83bdaa1.1666702934.git.research_trasio@irq.a4lg.com/mbox/"},{"id":11062,"url":"https://patchwork.plctlab.org/api/1.2/patches/11062/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jAhwbXhxJHL66v@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-26T05:07:19","name":"PR29720, objdump -S crashes if build-id is missing","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jAhwbXhxJHL66v@squeak.grove.modra.org/mbox/"},{"id":11063,"url":"https://patchwork.plctlab.org/api/1.2/patches/11063/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jAxD+NxpMIah6s@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-26T05:08:20","name":"som.c buffer overflow","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jAxD+NxpMIah6s@squeak.grove.modra.org/mbox/"},{"id":11064,"url":"https://patchwork.plctlab.org/api/1.2/patches/11064/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jBYw4lfRQfOZhi@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-26T05:10:59","name":"som.c reloc sanity checking","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jBYw4lfRQfOZhi@squeak.grove.modra.org/mbox/"},{"id":11080,"url":"https://patchwork.plctlab.org/api/1.2/patches/11080/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jY7hygm01PelCY@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-26T06:51:26","name":"segfault in objdump.c reloc_at","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jY7hygm01PelCY@squeak.grove.modra.org/mbox/"},{"id":11081,"url":"https://patchwork.plctlab.org/api/1.2/patches/11081/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jZWIeIvCCYm9/g@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-26T06:53:12","name":"Correct ELF reloc size sanity check","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jZWIeIvCCYm9/g@squeak.grove.modra.org/mbox/"},{"id":11082,"url":"https://patchwork.plctlab.org/api/1.2/patches/11082/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221026070009.3663574-1-ysato@users.sourceforge.jp/","msgid":"<20221026070009.3663574-1-ysato@users.sourceforge.jp>","list_archive_url":null,"date":"2022-10-26T07:00:09","name":"opcodes: RX fix invalid output.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221026070009.3663574-1-ysato@users.sourceforge.jp/mbox/"},{"id":11089,"url":"https://patchwork.plctlab.org/api/1.2/patches/11089/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jhW48kuVC8Ig2d@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-26T07:27:23","name":"buffer overflow in _bfd_XX_print_ce_compressed_pdata","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jhW48kuVC8Ig2d@squeak.grove.modra.org/mbox/"},{"id":11157,"url":"https://patchwork.plctlab.org/api/1.2/patches/11157/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c52dbd16-7e1b-c356-7a92-1ff089564ef7@suse.cz/","msgid":"","list_archive_url":null,"date":"2022-10-26T08:47:09","name":"tests: use canonical option name","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c52dbd16-7e1b-c356-7a92-1ff089564ef7@suse.cz/mbox/"},{"id":11526,"url":"https://patchwork.plctlab.org/api/1.2/patches/11526/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027031915.4013-1-lifang_xia@linux.alibaba.com/","msgid":"<20221027031915.4013-1-lifang_xia@linux.alibaba.com>","list_archive_url":null,"date":"2022-10-27T03:19:15","name":"[v2] RISC-V: Optimize relax of GP/call with max_alignment.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027031915.4013-1-lifang_xia@linux.alibaba.com/mbox/"},{"id":11619,"url":"https://patchwork.plctlab.org/api/1.2/patches/11619/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9df9d9e5bb4c7594b76c40613a349b4d2364e9c5.1666854355.git.research_trasio@irq.a4lg.com/","msgid":"<9df9d9e5bb4c7594b76c40613a349b4d2364e9c5.1666854355.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-27T07:06:01","name":"include: Define macro to ignore -Wdeprecated-declarations on GCC","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9df9d9e5bb4c7594b76c40613a349b4d2364e9c5.1666854355.git.research_trasio@irq.a4lg.com/mbox/"},{"id":11627,"url":"https://patchwork.plctlab.org/api/1.2/patches/11627/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1o06O9Pp8ncCsOw@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-27T07:36:08","name":"Fuzzed files in archives","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1o06O9Pp8ncCsOw@squeak.grove.modra.org/mbox/"},{"id":11658,"url":"https://patchwork.plctlab.org/api/1.2/patches/11658/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027084808.37252-1-nelson@rivosinc.com/","msgid":"<20221027084808.37252-1-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-10-27T08:48:08","name":"[committed] RISC-V: Fix build failures for -Werror=sign-compare.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027084808.37252-1-nelson@rivosinc.com/mbox/"},{"id":11921,"url":"https://patchwork.plctlab.org/api/1.2/patches/11921/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027190052.10536-1-mark@harmstone.com/","msgid":"<20221027190052.10536-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-27T19:00:51","name":"[1/2] ld: Add section header stream to PDB files","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027190052.10536-1-mark@harmstone.com/mbox/"},{"id":11922,"url":"https://patchwork.plctlab.org/api/1.2/patches/11922/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027190052.10536-2-mark@harmstone.com/","msgid":"<20221027190052.10536-2-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-27T19:00:52","name":"[2/2] ld: Add publics stream to PDB files","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027190052.10536-2-mark@harmstone.com/mbox/"},{"id":11965,"url":"https://patchwork.plctlab.org/api/1.2/patches/11965/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027202719.32497-1-palmer@rivosinc.com/","msgid":"<20221027202719.32497-1-palmer@rivosinc.com>","list_archive_url":null,"date":"2022-10-27T20:27:18","name":"[1/2] gas: NEWS: Add a missing newline","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027202719.32497-1-palmer@rivosinc.com/mbox/"},{"id":11966,"url":"https://patchwork.plctlab.org/api/1.2/patches/11966/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027202719.32497-2-palmer@rivosinc.com/","msgid":"<20221027202719.32497-2-palmer@rivosinc.com>","list_archive_url":null,"date":"2022-10-27T20:27:19","name":"[2/2] gas: NEWS: Note support for RISC-V Zawrs","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027202719.32497-2-palmer@rivosinc.com/mbox/"},{"id":12016,"url":"https://patchwork.plctlab.org/api/1.2/patches/12016/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/21ec9a18-fa89-0828-f625-499680022ec7@linux.ibm.com/","msgid":"<21ec9a18-fa89-0828-f625-499680022ec7@linux.ibm.com>","list_archive_url":null,"date":"2022-10-28T00:35:19","name":"[COMMITTED] PowerPC: Add support for RFC02653 - Dense Math Facility","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/21ec9a18-fa89-0828-f625-499680022ec7@linux.ibm.com/mbox/"},{"id":12017,"url":"https://patchwork.plctlab.org/api/1.2/patches/12017/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fd94047d-a070-45a6-3840-c105391718e0@linux.ibm.com/","msgid":"","list_archive_url":null,"date":"2022-10-28T00:37:18","name":"[COMMITTED] PowerPC: Add support for RFC02658 - MMA+ Outer-Product, Instructions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fd94047d-a070-45a6-3840-c105391718e0@linux.ibm.com/mbox/"},{"id":12122,"url":"https://patchwork.plctlab.org/api/1.2/patches/12122/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ac4f3f3c7115a824f73aca6935789b14d33c9a58.1666939920.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-28T06:53:02","name":"RISC-V: Fix build failure for -Werror=maybe-uninitialized","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ac4f3f3c7115a824f73aca6935789b14d33c9a58.1666939920.git.research_trasio@irq.a4lg.com/mbox/"},{"id":12181,"url":"https://patchwork.plctlab.org/api/1.2/patches/12181/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221028093840.19164-1-nelson@rivosinc.com/","msgid":"<20221028093840.19164-1-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-10-28T09:38:40","name":"RISC-V: Added SiFive custom cache control extensions.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221028093840.19164-1-nelson@rivosinc.com/mbox/"},{"id":12211,"url":"https://patchwork.plctlab.org/api/1.2/patches/12211/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4a280588-a85b-6ed3-634b-2b9cbc128f86@suse.com/","msgid":"<4a280588-a85b-6ed3-634b-2b9cbc128f86@suse.com>","list_archive_url":null,"date":"2022-10-28T10:06:35","name":"RISC-V/gas: fix build with certain gcc versions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4a280588-a85b-6ed3-634b-2b9cbc128f86@suse.com/mbox/"},{"id":12249,"url":"https://patchwork.plctlab.org/api/1.2/patches/12249/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/eb0e1bff-675e-72db-b8b1-b0f0e50b7121@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-28T12:35:35","name":"x86: minor improvements to optimize_imm() (part III)","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/eb0e1bff-675e-72db-b8b1-b0f0e50b7121@suse.com/mbox/"},{"id":12382,"url":"https://patchwork.plctlab.org/api/1.2/patches/12382/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/17f57574936af82be381a1451eac56b3709b60bb.1666968673.git.research_trasio@irq.a4lg.com/","msgid":"<17f57574936af82be381a1451eac56b3709b60bb.1666968673.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-28T14:52:12","name":"RISC-V: Emit mapping symbol with ISA string if non-default arch is used","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/17f57574936af82be381a1451eac56b3709b60bb.1666968673.git.research_trasio@irq.a4lg.com/mbox/"},{"id":12627,"url":"https://patchwork.plctlab.org/api/1.2/patches/12627/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221029034432.49859-1-nelson@rivosinc.com/","msgid":"<20221029034432.49859-1-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-10-29T03:44:32","name":"[committed] RISC-V: Always generate mapping symbols at the start of the sections.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221029034432.49859-1-nelson@rivosinc.com/mbox/"},{"id":12629,"url":"https://patchwork.plctlab.org/api/1.2/patches/12629/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1yxgzNJg5M48uPI@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-29T04:52:19","name":"NULL dereference read in som_write_object_contents","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1yxgzNJg5M48uPI@squeak.grove.modra.org/mbox/"},{"id":12630,"url":"https://patchwork.plctlab.org/api/1.2/patches/12630/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1yxnSHLY+FeB5DQ@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-29T04:52:45","name":"Fix small objcopy memory leak","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1yxnSHLY+FeB5DQ@squeak.grove.modra.org/mbox/"},{"id":12631,"url":"https://patchwork.plctlab.org/api/1.2/patches/12631/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1yxxfpJz+Jx4KTh@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-29T04:53:25","name":"pef: sanity check before malloc","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1yxxfpJz+Jx4KTh@squeak.grove.modra.org/mbox/"},{"id":12950,"url":"https://patchwork.plctlab.org/api/1.2/patches/12950/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-2-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-2-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:36","name":"[V3,01/15] sframe.h: Add SFrame format definition","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-2-indu.bhagat@oracle.com/mbox/"},{"id":12952,"url":"https://patchwork.plctlab.org/api/1.2/patches/12952/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-3-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-3-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:37","name":"[V3,02/15] gas: add new command line option --gsframe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-3-indu.bhagat@oracle.com/mbox/"},{"id":12951,"url":"https://patchwork.plctlab.org/api/1.2/patches/12951/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-4-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-4-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:38","name":"[V3,03/15] gas: generate .sframe from CFI directives","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-4-indu.bhagat@oracle.com/mbox/"},{"id":12956,"url":"https://patchwork.plctlab.org/api/1.2/patches/12956/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-5-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-5-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:39","name":"[V3,04/15] gas: testsuite: add new tests for SFrame unwind info","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-5-indu.bhagat@oracle.com/mbox/"},{"id":12955,"url":"https://patchwork.plctlab.org/api/1.2/patches/12955/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-6-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-6-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:40","name":"[V3,05/15] libsframe: add the SFrame library","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-6-indu.bhagat@oracle.com/mbox/"},{"id":12959,"url":"https://patchwork.plctlab.org/api/1.2/patches/12959/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-7-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-7-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:41","name":"[V3,06/15] bfd: linker: merge .sframe sections","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-7-indu.bhagat@oracle.com/mbox/"},{"id":12961,"url":"https://patchwork.plctlab.org/api/1.2/patches/12961/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-8-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-8-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:42","name":"[V3,07/15] readelf/objdump: support for SFrame section","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-8-indu.bhagat@oracle.com/mbox/"},{"id":12962,"url":"https://patchwork.plctlab.org/api/1.2/patches/12962/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-9-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-9-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:43","name":"[V3,08/15] unwinder: generate backtrace using SFrame format","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-9-indu.bhagat@oracle.com/mbox/"},{"id":12963,"url":"https://patchwork.plctlab.org/api/1.2/patches/12963/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-10-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-10-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:44","name":"[V3,09/15] unwinder: Add SFrame unwinder tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-10-indu.bhagat@oracle.com/mbox/"},{"id":12964,"url":"https://patchwork.plctlab.org/api/1.2/patches/12964/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-11-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-11-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:45","name":"[V3,10/15] gdb: sim: buildsystem changes to accommodate libsframe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-11-indu.bhagat@oracle.com/mbox/"},{"id":12957,"url":"https://patchwork.plctlab.org/api/1.2/patches/12957/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-12-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-12-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:46","name":"[V3,11/15] libctf: add libsframe to LDFLAGS and LIBS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-12-indu.bhagat@oracle.com/mbox/"},{"id":12960,"url":"https://patchwork.plctlab.org/api/1.2/patches/12960/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-13-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-13-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:47","name":"[V3,12/15] src-release.sh: Add libsframe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-13-indu.bhagat@oracle.com/mbox/"},{"id":12953,"url":"https://patchwork.plctlab.org/api/1.2/patches/12953/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-14-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-14-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:48","name":"[V3,13/15] binutils/NEWS: add text for SFrame support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-14-indu.bhagat@oracle.com/mbox/"},{"id":12954,"url":"https://patchwork.plctlab.org/api/1.2/patches/12954/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-15-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-15-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:49","name":"[V3,14/15] gas/NEWS: add text about new command line option and SFrame support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-15-indu.bhagat@oracle.com/mbox/"},{"id":12958,"url":"https://patchwork.plctlab.org/api/1.2/patches/12958/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-16-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-16-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:50","name":"[V3,15/15] doc: add SFrame spec file","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-16-indu.bhagat@oracle.com/mbox/"},{"id":12988,"url":"https://patchwork.plctlab.org/api/1.2/patches/12988/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y15KFY32CyFhh/+u@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-30T09:55:33","name":"Pool section entries for DWP version 1","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y15KFY32CyFhh/+u@squeak.grove.modra.org/mbox/"},{"id":13076,"url":"https://patchwork.plctlab.org/api/1.2/patches/13076/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031001554.14615-1-mark@harmstone.com/","msgid":"<20221031001554.14615-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-31T00:15:52","name":"[v2,1/3] ld: Use %E in einfo in pdb.c","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031001554.14615-1-mark@harmstone.com/mbox/"},{"id":13078,"url":"https://patchwork.plctlab.org/api/1.2/patches/13078/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031001554.14615-2-mark@harmstone.com/","msgid":"<20221031001554.14615-2-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-31T00:15:53","name":"[v2,2/3] ld: Add section header stream to PDB files","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031001554.14615-2-mark@harmstone.com/mbox/"},{"id":13077,"url":"https://patchwork.plctlab.org/api/1.2/patches/13077/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031001554.14615-3-mark@harmstone.com/","msgid":"<20221031001554.14615-3-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-31T00:15:54","name":"[v2,3/3] ld: Add publics stream to PDB files","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031001554.14615-3-mark@harmstone.com/mbox/"},{"id":13106,"url":"https://patchwork.plctlab.org/api/1.2/patches/13106/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031030507.35588-2-haochen.jiang@intel.com/","msgid":"<20221031030507.35588-2-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-31T03:05:02","name":"[1/6] Support Intel AVX-IFMA","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031030507.35588-2-haochen.jiang@intel.com/mbox/"},{"id":13105,"url":"https://patchwork.plctlab.org/api/1.2/patches/13105/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031030507.35588-3-haochen.jiang@intel.com/","msgid":"<20221031030507.35588-3-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-31T03:05:03","name":"[2/6] Support Intel AVX-VNNI-INT8","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031030507.35588-3-haochen.jiang@intel.com/mbox/"},{"id":13103,"url":"https://patchwork.plctlab.org/api/1.2/patches/13103/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031030507.35588-4-haochen.jiang@intel.com/","msgid":"<20221031030507.35588-4-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-31T03:05:04","name":"[3/6] Support Intel CMPccXADD","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031030507.35588-4-haochen.jiang@intel.com/mbox/"},{"id":13101,"url":"https://patchwork.plctlab.org/api/1.2/patches/13101/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031030507.35588-5-haochen.jiang@intel.com/","msgid":"<20221031030507.35588-5-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-31T03:05:05","name":"[4/6] Add handler for more i386_cpu_flags","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031030507.35588-5-haochen.jiang@intel.com/mbox/"},{"id":13104,"url":"https://patchwork.plctlab.org/api/1.2/patches/13104/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031030507.35588-6-haochen.jiang@intel.com/","msgid":"<20221031030507.35588-6-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-31T03:05:06","name":"[5/6] Support Intel WRMSRNS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031030507.35588-6-haochen.jiang@intel.com/mbox/"},{"id":13102,"url":"https://patchwork.plctlab.org/api/1.2/patches/13102/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031030507.35588-7-haochen.jiang@intel.com/","msgid":"<20221031030507.35588-7-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-31T03:05:07","name":"[6/6] Support Intel MSRLIST","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031030507.35588-7-haochen.jiang@intel.com/mbox/"},{"id":13120,"url":"https://patchwork.plctlab.org/api/1.2/patches/13120/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031060601.38460-2-haochen.jiang@intel.com/","msgid":"<20221031060601.38460-2-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-31T06:06:00","name":"[1/2] i386: Add and ","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031060601.38460-2-haochen.jiang@intel.com/mbox/"},{"id":13121,"url":"https://patchwork.plctlab.org/api/1.2/patches/13121/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031060601.38460-3-haochen.jiang@intel.com/","msgid":"<20221031060601.38460-3-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-31T06:06:01","name":"[2/2] Support Intel AVX-NE-CONVERT","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031060601.38460-3-haochen.jiang@intel.com/mbox/"},{"id":13188,"url":"https://patchwork.plctlab.org/api/1.2/patches/13188/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9f6f8888-4dc1-a6b0-0590-35fc8a276369@suse.com/","msgid":"<9f6f8888-4dc1-a6b0-0590-35fc8a276369@suse.com>","list_archive_url":null,"date":"2022-10-31T10:18:20","name":"x86: drop bogus Tbyte","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9f6f8888-4dc1-a6b0-0590-35fc8a276369@suse.com/mbox/"},{"id":13213,"url":"https://patchwork.plctlab.org/api/1.2/patches/13213/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4f1aac95-fea5-2279-cb18-dfcdb51a2589@arm.com/","msgid":"<4f1aac95-fea5-2279-cb18-dfcdb51a2589@arm.com>","list_archive_url":null,"date":"2022-10-31T11:14:44","name":"aarch64: Add support for Common Short Sequence Compression extension","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4f1aac95-fea5-2279-cb18-dfcdb51a2589@arm.com/mbox/"}],"public":true,"mbox":"https://patchwork.plctlab.org/bundle/patchwork-bot/binutils-gdb_2022-10/mbox/"},{"id":7,"url":"https://patchwork.plctlab.org/api/1.2/bundles/7/","web_url":"https://patchwork.plctlab.org/bundle/patchwork-bot/binutils-gdb_2022-09/","project":{"id":2,"url":"https://patchwork.plctlab.org/api/1.2/projects/2/","name":"binutils-gdb","link_name":"binutils-gdb","list_id":"binutils.sourceware.org","list_email":"binutils@sourceware.org","web_url":"https://github.com/wangliu-iscas/Patchwork-Bundles/blob/main/binutils-gdb.md","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"name":"binutils-gdb_2022-09","owner":{"id":3,"url":"https://patchwork.plctlab.org/api/1.2/users/3/","username":"patchwork-bot","first_name":"","last_name":"","email":"ouuuleilei@gmail.com"},"patches":[{"id":1573,"url":"https://patchwork.plctlab.org/api/1.2/patches/1573/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930073211.2634-1-jiawei@iscas.ac.cn/","msgid":"<20220930073211.2634-1-jiawei@iscas.ac.cn>","list_archive_url":null,"date":"2022-09-30T07:32:11","name":"[V2] RISC-V: Add Smepmp CSR '\''mseccfg'\'' define and testcases.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930073211.2634-1-jiawei@iscas.ac.cn/mbox/"},{"id":1577,"url":"https://patchwork.plctlab.org/api/1.2/patches/1577/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/76fa0c3c-2303-ebdf-a765-ac4731581517@suse.com/","msgid":"<76fa0c3c-2303-ebdf-a765-ac4731581517@suse.com>","list_archive_url":null,"date":"2022-09-30T08:54:18","name":"objcopy: avoid \"shadowing\" of remove() function name","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/76fa0c3c-2303-ebdf-a765-ac4731581517@suse.com/mbox/"},{"id":1579,"url":"https://patchwork.plctlab.org/api/1.2/patches/1579/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930085852.71213-1-nelson@rivosinc.com/","msgid":"<20220930085852.71213-1-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-09-30T08:58:51","name":"[1/2] RISC-V: Output mapping symbols with ISA string.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930085852.71213-1-nelson@rivosinc.com/mbox/"},{"id":1578,"url":"https://patchwork.plctlab.org/api/1.2/patches/1578/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930085852.71213-2-nelson@rivosinc.com/","msgid":"<20220930085852.71213-2-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-09-30T08:58:52","name":"[2/2] RISC-V: Refer mapping symbol to R_RISCV_RELAX for rvc relaxations.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930085852.71213-2-nelson@rivosinc.com/mbox/"},{"id":1581,"url":"https://patchwork.plctlab.org/api/1.2/patches/1581/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930092058.71286-1-nelson@rivosinc.com/","msgid":"<20220930092058.71286-1-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-09-30T09:20:57","name":"[1/2] RISC-V: Output mapping symbols with ISA string.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930092058.71286-1-nelson@rivosinc.com/mbox/"},{"id":1580,"url":"https://patchwork.plctlab.org/api/1.2/patches/1580/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930092058.71286-2-nelson@rivosinc.com/","msgid":"<20220930092058.71286-2-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-09-30T09:20:58","name":"[2/2] RISC-V: Refer mapping symbol to R_RISCV_RELAX for rvc relaxations.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930092058.71286-2-nelson@rivosinc.com/mbox/"},{"id":1582,"url":"https://patchwork.plctlab.org/api/1.2/patches/1582/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5874dd79-0cf5-d65c-7ea2-13adfc799c0f@suse.com/","msgid":"<5874dd79-0cf5-d65c-7ea2-13adfc799c0f@suse.com>","list_archive_url":null,"date":"2022-09-30T09:41:29","name":"RISC-V: fix build after \"Add support for arbitrary immediate encoding formats\"","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5874dd79-0cf5-d65c-7ea2-13adfc799c0f@suse.com/mbox/"},{"id":1583,"url":"https://patchwork.plctlab.org/api/1.2/patches/1583/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/57d8ac2a-5757-3776-9924-99c17ca69938@suse.com/","msgid":"<57d8ac2a-5757-3776-9924-99c17ca69938@suse.com>","list_archive_url":null,"date":"2022-09-30T09:42:08","name":"RISC-V: fallout from \"re-arrange opcode table for consistent alias handling\"","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/57d8ac2a-5757-3776-9924-99c17ca69938@suse.com/mbox/"},{"id":1584,"url":"https://patchwork.plctlab.org/api/1.2/patches/1584/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e76ef8f7-72b9-5103-cb43-9608af01d017@suse.com/","msgid":"","list_archive_url":null,"date":"2022-09-30T09:42:50","name":"RISC-V: don'\''t cast expressions'\'' X_add_number to long in diagnostics","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e76ef8f7-72b9-5103-cb43-9608af01d017@suse.com/mbox/"},{"id":1585,"url":"https://patchwork.plctlab.org/api/1.2/patches/1585/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/61355429-24b3-17d0-ab03-6fa57ee861d5@suse.cz/","msgid":"<61355429-24b3-17d0-ab03-6fa57ee861d5@suse.cz>","list_archive_url":null,"date":"2022-09-30T09:48:52","name":"[RFC] add --enable-zstd-compressed-debug-sections configure option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/61355429-24b3-17d0-ab03-6fa57ee861d5@suse.cz/mbox/"},{"id":1586,"url":"https://patchwork.plctlab.org/api/1.2/patches/1586/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930103919.323690-1-christoph.muellner@vrull.eu/","msgid":"<20220930103919.323690-1-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2022-09-30T10:39:19","name":"RISC-V: Eliminate long-casts of X_add_number in diagnostics","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930103919.323690-1-christoph.muellner@vrull.eu/mbox/"},{"id":1590,"url":"https://patchwork.plctlab.org/api/1.2/patches/1590/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/DM6PR12MB4219C943049C6D883DEA3E55E7569@DM6PR12MB4219.namprd12.prod.outlook.com/","msgid":"","list_archive_url":null,"date":"2022-09-30T11:41:37","name":"[V2] Ignore DWARF debug information for -gsplit-dwarf with dwarf-5.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/DM6PR12MB4219C943049C6D883DEA3E55E7569@DM6PR12MB4219.namprd12.prod.outlook.com/mbox/"},{"id":1591,"url":"https://patchwork.plctlab.org/api/1.2/patches/1591/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c10321f9-d289-ef84-d263-bc278fb3d31b@suse.com/","msgid":"","list_archive_url":null,"date":"2022-09-30T11:59:04","name":"[1/4] RISC-V/gas: drop riscv_subsets static variable","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c10321f9-d289-ef84-d263-bc278fb3d31b@suse.com/mbox/"},{"id":1593,"url":"https://patchwork.plctlab.org/api/1.2/patches/1593/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3244eea0-c18c-e49a-4588-d69423130226@suse.com/","msgid":"<3244eea0-c18c-e49a-4588-d69423130226@suse.com>","list_archive_url":null,"date":"2022-09-30T11:59:23","name":"[2/4] RISC-V/gas: drop stray call to install_insn()","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3244eea0-c18c-e49a-4588-d69423130226@suse.com/mbox/"},{"id":1592,"url":"https://patchwork.plctlab.org/api/1.2/patches/1592/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/385d01fd-7e57-1f3f-1bae-30aa0c313d63@suse.com/","msgid":"<385d01fd-7e57-1f3f-1bae-30aa0c313d63@suse.com>","list_archive_url":null,"date":"2022-09-30T11:59:45","name":"[3/4] RISC-V/gas: don'\''t open-code insn_length()","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/385d01fd-7e57-1f3f-1bae-30aa0c313d63@suse.com/mbox/"},{"id":1594,"url":"https://patchwork.plctlab.org/api/1.2/patches/1594/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f5757acf-7b90-a0e3-5eea-3b97cc226930@suse.com/","msgid":"","list_archive_url":null,"date":"2022-09-30T12:00:12","name":"[4/4] RISC-V/gas: allow generating up to 176-bit instructions with .insn","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f5757acf-7b90-a0e3-5eea-3b97cc226930@suse.com/mbox/"},{"id":1596,"url":"https://patchwork.plctlab.org/api/1.2/patches/1596/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930140503.38233-1-chigot@adacore.com/","msgid":"<20220930140503.38233-1-chigot@adacore.com>","list_archive_url":null,"date":"2022-09-30T14:05:03","name":"ld/testsuite: consistently add board_ldflags when linking with GCC","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930140503.38233-1-chigot@adacore.com/mbox/"}],"public":true,"mbox":"https://patchwork.plctlab.org/bundle/patchwork-bot/binutils-gdb_2022-09/mbox/"},{"id":9,"url":"https://patchwork.plctlab.org/api/1.2/bundles/9/","web_url":"https://patchwork.plctlab.org/bundle/patchwork-bot/binutils-gdb_2022-11/","project":{"id":2,"url":"https://patchwork.plctlab.org/api/1.2/projects/2/","name":"binutils-gdb","link_name":"binutils-gdb","list_id":"binutils.sourceware.org","list_email":"binutils@sourceware.org","web_url":"https://github.com/wangliu-iscas/Patchwork-Bundles/blob/main/binutils-gdb.md","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"name":"binutils-gdb_2022-11","owner":{"id":3,"url":"https://patchwork.plctlab.org/api/1.2/users/3/","username":"patchwork-bot","first_name":"","last_name":"","email":"ouuuleilei@gmail.com"},"patches":[{"id":13337,"url":"https://patchwork.plctlab.org/api/1.2/patches/13337/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031160625.684434-1-hjl.tools@gmail.com/","msgid":"<20221031160625.684434-1-hjl.tools@gmail.com>","list_archive_url":null,"date":"2022-10-31T16:06:25","name":"x86: Silence GCC 12 warning on tc-i386.c","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031160625.684434-1-hjl.tools@gmail.com/mbox/"},{"id":13350,"url":"https://patchwork.plctlab.org/api/1.2/patches/13350/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c8d25b29-37fe-9623-a799-e67e1f991743@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-31T17:00:56","name":"x86: simplify expressions in update_imm()","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c8d25b29-37fe-9623-a799-e67e1f991743@suse.com/mbox/"},{"id":13487,"url":"https://patchwork.plctlab.org/api/1.2/patches/13487/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/CAMe9rOohVjin92PTeeiu_dvAtzYJn4dGtu5E=OxYfbyteraZWw@mail.gmail.com/","msgid":"","list_archive_url":null,"date":"2022-11-01T00:08:04","name":"binutils: Run PR binutils/26160 test","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/CAMe9rOohVjin92PTeeiu_dvAtzYJn4dGtu5E=OxYfbyteraZWw@mail.gmail.com/mbox/"},{"id":13621,"url":"https://patchwork.plctlab.org/api/1.2/patches/13621/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221101105724.1527333-1-aburgess@redhat.com/","msgid":"<20221101105724.1527333-1-aburgess@redhat.com>","list_archive_url":null,"date":"2022-11-01T10:57:24","name":"[PUSHED] opcodes/arm: silence compiler warning about uninitialized variable use","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221101105724.1527333-1-aburgess@redhat.com/mbox/"},{"id":13628,"url":"https://patchwork.plctlab.org/api/1.2/patches/13628/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221101111802.1532080-1-aburgess@redhat.com/","msgid":"<20221101111802.1532080-1-aburgess@redhat.com>","list_archive_url":null,"date":"2022-11-01T11:18:02","name":"[PUSHED] opcodes/arm: don'\''t pass non-string literal to printf like function","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221101111802.1532080-1-aburgess@redhat.com/mbox/"},{"id":13747,"url":"https://patchwork.plctlab.org/api/1.2/patches/13747/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/yw8jbkpqk6vw.fsf@arm.com/","msgid":"","list_archive_url":null,"date":"2022-11-01T15:54:11","name":"[Binutils-2.39,backport,GAS] arm: Use DWARF numbering convention for pseudo-register representation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/yw8jbkpqk6vw.fsf@arm.com/mbox/"},{"id":13993,"url":"https://patchwork.plctlab.org/api/1.2/patches/13993/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221102020752.24441-1-mark@harmstone.com/","msgid":"<20221102020752.24441-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-11-02T02:07:52","name":"ld: Add module information substream to PDB files","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221102020752.24441-1-mark@harmstone.com/mbox/"},{"id":14028,"url":"https://patchwork.plctlab.org/api/1.2/patches/14028/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221102050430.1053-1-nelson@rivosinc.com/","msgid":"<20221102050430.1053-1-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-11-02T05:04:30","name":"[committed] RISC-V: Fixed the missing $x+arch when adding odd paddings for alignment.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221102050430.1053-1-nelson@rivosinc.com/mbox/"},{"id":14043,"url":"https://patchwork.plctlab.org/api/1.2/patches/14043/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221102063046.31551-1-rjiejie@linux.alibaba.com/","msgid":"<20221102063046.31551-1-rjiejie@linux.alibaba.com>","list_archive_url":null,"date":"2022-11-02T06:30:46","name":"gas/doc/internals.texi: fix typo","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221102063046.31551-1-rjiejie@linux.alibaba.com/mbox/"},{"id":14069,"url":"https://patchwork.plctlab.org/api/1.2/patches/14069/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221102080112.33378-1-rjiejie@linux.alibaba.com/","msgid":"<20221102080112.33378-1-rjiejie@linux.alibaba.com>","list_archive_url":null,"date":"2022-11-02T08:01:12","name":"[v2] Support multiple .eh_frame sections","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221102080112.33378-1-rjiejie@linux.alibaba.com/mbox/"},{"id":14409,"url":"https://patchwork.plctlab.org/api/1.2/patches/14409/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221102172923.4009281-1-christophe.lyon@arm.com/","msgid":"<20221102172923.4009281-1-christophe.lyon@arm.com>","list_archive_url":null,"date":"2022-11-02T17:29:23","name":"arm: PR 29739 Fix typo where '\''; '\'' should not have been replaced with '\''@'\''","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221102172923.4009281-1-christophe.lyon@arm.com/mbox/"},{"id":14588,"url":"https://patchwork.plctlab.org/api/1.2/patches/14588/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221103020409.37322-1-rjiejie@linux.alibaba.com/","msgid":"<20221103020409.37322-1-rjiejie@linux.alibaba.com>","list_archive_url":null,"date":"2022-11-03T02:04:09","name":"[v3] Support multiple .eh_frame sections","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221103020409.37322-1-rjiejie@linux.alibaba.com/mbox/"},{"id":14602,"url":"https://patchwork.plctlab.org/api/1.2/patches/14602/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221103024604.614-1-mark@harmstone.com/","msgid":"<20221103024604.614-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-11-03T02:46:04","name":"[v2] ld: Add module information substream to PDB files","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221103024604.614-1-mark@harmstone.com/mbox/"},{"id":14706,"url":"https://patchwork.plctlab.org/api/1.2/patches/14706/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221103071519.3510462-1-luis.machado@arm.com/","msgid":"<20221103071519.3510462-1-luis.machado@arm.com>","list_archive_url":null,"date":"2022-11-03T07:15:19","name":"[opcodes/arm] Fix potential null pointer dereferences","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221103071519.3510462-1-luis.machado@arm.com/mbox/"},{"id":14840,"url":"https://patchwork.plctlab.org/api/1.2/patches/14840/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/283a86ebf0941f0f63dc1a590ec3d547bd5d69e8.1667478033.git.research_trasio@irq.a4lg.com/","msgid":"<283a86ebf0941f0f63dc1a590ec3d547bd5d69e8.1667478033.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-03T12:26:28","name":"[REVIEW,ONLY,1/2] NEAR-RATIFICATION RISC-V: Add '\''Ssstateen'\'' extension and its CSRs","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/283a86ebf0941f0f63dc1a590ec3d547bd5d69e8.1667478033.git.research_trasio@irq.a4lg.com/mbox/"},{"id":14841,"url":"https://patchwork.plctlab.org/api/1.2/patches/14841/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8083ad9d5339afdeb7f1ba88ee6af0665dcc76d5.1667478033.git.research_trasio@irq.a4lg.com/","msgid":"<8083ad9d5339afdeb7f1ba88ee6af0665dcc76d5.1667478033.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-03T12:26:29","name":"[REVIEW,ONLY,2/2] NEAR-RATIFICATION RISC-V: Add platform property/capability extensions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8083ad9d5339afdeb7f1ba88ee6af0665dcc76d5.1667478033.git.research_trasio@irq.a4lg.com/mbox/"},{"id":14894,"url":"https://patchwork.plctlab.org/api/1.2/patches/14894/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e53fbf5025e59fe6a3481b9c1fe37e4f6cf6e03d.1667483581.git.aburgess@redhat.com/","msgid":"","list_archive_url":null,"date":"2022-11-03T13:58:12","name":"[1/2] opcodes/mips: use .word/.short for undefined instructions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e53fbf5025e59fe6a3481b9c1fe37e4f6cf6e03d.1667483581.git.aburgess@redhat.com/mbox/"},{"id":14893,"url":"https://patchwork.plctlab.org/api/1.2/patches/14893/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ca81edb86580566b1641ad140eb2bed385160ab7.1667483581.git.aburgess@redhat.com/","msgid":"","list_archive_url":null,"date":"2022-11-03T13:58:13","name":"[2/2] libopcodes/mips: add support for disassembler styling","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ca81edb86580566b1641ad140eb2bed385160ab7.1667483581.git.aburgess@redhat.com/mbox/"},{"id":15465,"url":"https://patchwork.plctlab.org/api/1.2/patches/15465/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/926e5154-b40b-9df8-d770-a8bf7d40e40e@suse.com/","msgid":"<926e5154-b40b-9df8-d770-a8bf7d40e40e@suse.com>","list_archive_url":null,"date":"2022-11-04T10:50:38","name":"[v6,1/7] x86: constify parse_insn()'\''s input","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/926e5154-b40b-9df8-d770-a8bf7d40e40e@suse.com/mbox/"},{"id":15466,"url":"https://patchwork.plctlab.org/api/1.2/patches/15466/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/07ef67fd-752c-ad1f-b8cb-4eaec1f420fc@suse.com/","msgid":"<07ef67fd-752c-ad1f-b8cb-4eaec1f420fc@suse.com>","list_archive_url":null,"date":"2022-11-04T10:51:34","name":"[v6,2/7] x86: re-work insn/suffix recognition","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/07ef67fd-752c-ad1f-b8cb-4eaec1f420fc@suse.com/mbox/"},{"id":15467,"url":"https://patchwork.plctlab.org/api/1.2/patches/15467/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ee8fd655-19a5-d944-0f5e-4351b88a59f9@suse.com/","msgid":"","list_archive_url":null,"date":"2022-11-04T10:52:02","name":"[v6,3/7] ix86: don'\''t recognize/derive Q suffix in the common case","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ee8fd655-19a5-d944-0f5e-4351b88a59f9@suse.com/mbox/"},{"id":15468,"url":"https://patchwork.plctlab.org/api/1.2/patches/15468/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/15ab2cf5-f1ac-e882-c415-6318f1bcc7f0@suse.com/","msgid":"<15ab2cf5-f1ac-e882-c415-6318f1bcc7f0@suse.com>","list_archive_url":null,"date":"2022-11-04T10:52:31","name":"[v6,4/7] x86-64: allow HLE store of accumulator to absolute 32-bit address","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/15ab2cf5-f1ac-e882-c415-6318f1bcc7f0@suse.com/mbox/"},{"id":15470,"url":"https://patchwork.plctlab.org/api/1.2/patches/15470/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/352d1e49-ac9f-ee86-7e9d-74f79744268b@suse.com/","msgid":"<352d1e49-ac9f-ee86-7e9d-74f79744268b@suse.com>","list_archive_url":null,"date":"2022-11-04T10:53:14","name":"[v6,5/7] x86: move bad-use-of-TLS-reloc check","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/352d1e49-ac9f-ee86-7e9d-74f79744268b@suse.com/mbox/"},{"id":15469,"url":"https://patchwork.plctlab.org/api/1.2/patches/15469/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c1913bf6-7328-e45f-69f1-20da1954af43@suse.com/","msgid":"","list_archive_url":null,"date":"2022-11-04T10:53:52","name":"[v6,6/7] x86: drop (now) stray IsString","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c1913bf6-7328-e45f-69f1-20da1954af43@suse.com/mbox/"},{"id":15471,"url":"https://patchwork.plctlab.org/api/1.2/patches/15471/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2baf6a9d-c1bf-660d-bbca-99b1604f5478@suse.com/","msgid":"<2baf6a9d-c1bf-660d-bbca-99b1604f5478@suse.com>","list_archive_url":null,"date":"2022-11-04T10:54:30","name":"[v6,7/7] x86: further re-work insn/suffix recognition to also cover MOVSX","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2baf6a9d-c1bf-660d-bbca-99b1604f5478@suse.com/mbox/"},{"id":15472,"url":"https://patchwork.plctlab.org/api/1.2/patches/15472/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104110132.694984-1-aburgess@redhat.com/","msgid":"<20221104110132.694984-1-aburgess@redhat.com>","list_archive_url":null,"date":"2022-11-04T11:01:32","name":"[PUSHED] opcodes/arm: silence compiler warning about uninitialized variable use","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104110132.694984-1-aburgess@redhat.com/mbox/"},{"id":15473,"url":"https://patchwork.plctlab.org/api/1.2/patches/15473/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104110214.129095-1-christophe.lyon@arm.com/","msgid":"<20221104110214.129095-1-christophe.lyon@arm.com>","list_archive_url":null,"date":"2022-11-04T11:02:14","name":"configure: require libzstd >= 1.4.0","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104110214.129095-1-christophe.lyon@arm.com/mbox/"},{"id":15485,"url":"https://patchwork.plctlab.org/api/1.2/patches/15485/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104115038.8957-1-nelson@rivosinc.com/","msgid":"<20221104115038.8957-1-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-11-04T11:50:37","name":"[1/2] RISC-V: File-level architecture shouldn'\''t be affected by section-level ones.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104115038.8957-1-nelson@rivosinc.com/mbox/"},{"id":15486,"url":"https://patchwork.plctlab.org/api/1.2/patches/15486/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104115038.8957-2-nelson@rivosinc.com/","msgid":"<20221104115038.8957-2-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-11-04T11:50:38","name":"[2/2] RISC-V: Clarify the suppress rule of mapping symbol with architecture string.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104115038.8957-2-nelson@rivosinc.com/mbox/"},{"id":15509,"url":"https://patchwork.plctlab.org/api/1.2/patches/15509/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/cc133c88-9ce9-5e3a-a8f7-ad72766862b9@suse.com/","msgid":"","list_archive_url":null,"date":"2022-11-04T13:12:07","name":"x86: adjust recently introduced testcases","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/cc133c88-9ce9-5e3a-a8f7-ad72766862b9@suse.com/mbox/"},{"id":15679,"url":"https://patchwork.plctlab.org/api/1.2/patches/15679/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104163328.2274371-1-chigot@adacore.com/","msgid":"<20221104163328.2274371-1-chigot@adacore.com>","list_archive_url":null,"date":"2022-11-04T16:33:28","name":"ld/testsuite: skip tests related to -shared when disabled","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104163328.2274371-1-chigot@adacore.com/mbox/"},{"id":15751,"url":"https://patchwork.plctlab.org/api/1.2/patches/15751/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104190216.1352855-1-indu.bhagat@oracle.com/","msgid":"<20221104190216.1352855-1-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-04T19:02:16","name":"[V3.1,11/15] libctf: add libsframe to LDFLAGS and LIBS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104190216.1352855-1-indu.bhagat@oracle.com/mbox/"},{"id":15792,"url":"https://patchwork.plctlab.org/api/1.2/patches/15792/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104205547.3728827-1-hjl.tools@gmail.com/","msgid":"<20221104205547.3728827-1-hjl.tools@gmail.com>","list_archive_url":null,"date":"2022-11-04T20:55:47","name":"i386: Check invalid (%dx) usage","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104205547.3728827-1-hjl.tools@gmail.com/mbox/"},{"id":15794,"url":"https://patchwork.plctlab.org/api/1.2/patches/15794/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104210134.1721620-1-indu.bhagat@oracle.com/","msgid":"<20221104210134.1721620-1-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-04T21:01:34","name":"[V3.2,11/15] libctf: add libsframe to LDFLAGS and LIBS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104210134.1721620-1-indu.bhagat@oracle.com/mbox/"},{"id":15959,"url":"https://patchwork.plctlab.org/api/1.2/patches/15959/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c620070e3e335df2b487d3836e20d251dac37525.1667651354.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-11-05T12:29:07","name":"[01/12] RISC-V: Remove unnecessary empty matching file","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c620070e3e335df2b487d3836e20d251dac37525.1667651354.git.research_trasio@irq.a4lg.com/mbox/"},{"id":15961,"url":"https://patchwork.plctlab.org/api/1.2/patches/15961/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4496235002a396043598ab9755bd8eda5c077b1f.1667651354.git.research_trasio@irq.a4lg.com/","msgid":"<4496235002a396043598ab9755bd8eda5c077b1f.1667651354.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-05T12:29:08","name":"[02/12] RISC-V: Tidy disassembler corner case tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4496235002a396043598ab9755bd8eda5c077b1f.1667651354.git.research_trasio@irq.a4lg.com/mbox/"},{"id":15960,"url":"https://patchwork.plctlab.org/api/1.2/patches/15960/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a9229a2798480f00bf12ac3c435b3ef57f867022.1667651354.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-11-05T12:29:09","name":"[03/12] RISC-V: Tidying related to '\''Zfinx'\'' disassembler test","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a9229a2798480f00bf12ac3c435b3ef57f867022.1667651354.git.research_trasio@irq.a4lg.com/mbox/"},{"id":15962,"url":"https://patchwork.plctlab.org/api/1.2/patches/15962/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6a020edd0e114a003edbaafe1088a040e9fa07e7.1667651354.git.research_trasio@irq.a4lg.com/","msgid":"<6a020edd0e114a003edbaafe1088a040e9fa07e7.1667651354.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-05T12:29:10","name":"[04/12] RISC-V: GAS: Add basic shared test utilities","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6a020edd0e114a003edbaafe1088a040e9fa07e7.1667651354.git.research_trasio@irq.a4lg.com/mbox/"},{"id":15966,"url":"https://patchwork.plctlab.org/api/1.2/patches/15966/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6fc2851a4161edc429089bd2bbd9c2bb4c0c118f.1667651354.git.research_trasio@irq.a4lg.com/","msgid":"<6fc2851a4161edc429089bd2bbd9c2bb4c0c118f.1667651354.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-05T12:29:11","name":"[05/12] RISC-V: Redefine \"nop\" test","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6fc2851a4161edc429089bd2bbd9c2bb4c0c118f.1667651354.git.research_trasio@irq.a4lg.com/mbox/"},{"id":15963,"url":"https://patchwork.plctlab.org/api/1.2/patches/15963/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7311ed3d2429000e18877d7af594890da170a7a3.1667651354.git.research_trasio@irq.a4lg.com/","msgid":"<7311ed3d2429000e18877d7af594890da170a7a3.1667651354.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-05T12:29:12","name":"[06/12] RISC-V: Reorganize/enhance {sign, zero}-extension instructions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7311ed3d2429000e18877d7af594890da170a7a3.1667651354.git.research_trasio@irq.a4lg.com/mbox/"},{"id":15968,"url":"https://patchwork.plctlab.org/api/1.2/patches/15968/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ac99c9696c156207f06c18f2d6bf423c96c5876b.1667651354.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-11-05T12:29:13","name":"[07/12] RISC-V: Combine complex extension error handling tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ac99c9696c156207f06c18f2d6bf423c96c5876b.1667651354.git.research_trasio@irq.a4lg.com/mbox/"},{"id":15970,"url":"https://patchwork.plctlab.org/api/1.2/patches/15970/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9378b9505e3e230e0a690c56e67d253e2a0f5864.1667651354.git.research_trasio@irq.a4lg.com/","msgid":"<9378b9505e3e230e0a690c56e67d253e2a0f5864.1667651354.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-05T12:29:14","name":"[08/12] RISC-V: Refine/enhance '\''M'\''/'\''Zmmul'\'' extension tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9378b9505e3e230e0a690c56e67d253e2a0f5864.1667651354.git.research_trasio@irq.a4lg.com/mbox/"},{"id":15964,"url":"https://patchwork.plctlab.org/api/1.2/patches/15964/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/82832a67f240d5857fd502d4b74fd7d841ee2d6e.1667651354.git.research_trasio@irq.a4lg.com/","msgid":"<82832a67f240d5857fd502d4b74fd7d841ee2d6e.1667651354.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-05T12:29:15","name":"[09/12] RISC-V: Combine/enhance '\''Zicbo[mz]'\'' extension tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/82832a67f240d5857fd502d4b74fd7d841ee2d6e.1667651354.git.research_trasio@irq.a4lg.com/mbox/"},{"id":15965,"url":"https://patchwork.plctlab.org/api/1.2/patches/15965/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9c47e59868a64b13e5a7bb487e3619d4f1497d78.1667651354.git.research_trasio@irq.a4lg.com/","msgid":"<9c47e59868a64b13e5a7bb487e3619d4f1497d78.1667651354.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-05T12:29:16","name":"[10/12] RISC-V: Enhance '\''Zicbop'\'' testcases","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9c47e59868a64b13e5a7bb487e3619d4f1497d78.1667651354.git.research_trasio@irq.a4lg.com/mbox/"},{"id":15967,"url":"https://patchwork.plctlab.org/api/1.2/patches/15967/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2d9befc5bc5eed80b6bd7da6d092a61b1162ecac.1667651354.git.research_trasio@irq.a4lg.com/","msgid":"<2d9befc5bc5eed80b6bd7da6d092a61b1162ecac.1667651354.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-05T12:29:17","name":"[11/12] RISC-V: Reorganize/enhance '\''Zb*'\'' extension tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2d9befc5bc5eed80b6bd7da6d092a61b1162ecac.1667651354.git.research_trasio@irq.a4lg.com/mbox/"},{"id":15969,"url":"https://patchwork.plctlab.org/api/1.2/patches/15969/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f1c5589ab606b74eeac98e3dafd4a7903450d3b2.1667651354.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-11-05T12:29:18","name":"[12/12] RISC-V: Combine/enhance '\''Zk*'\''/'\''Zbk*'\'' extension tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f1c5589ab606b74eeac98e3dafd4a7903450d3b2.1667651354.git.research_trasio@irq.a4lg.com/mbox/"},{"id":16066,"url":"https://patchwork.plctlab.org/api/1.2/patches/16066/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221106053640.1649752-1-indu.bhagat@oracle.com/","msgid":"<20221106053640.1649752-1-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-06T05:36:40","name":"[V3.1,03/15] gas: generate .sframe from CFI directives","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221106053640.1649752-1-indu.bhagat@oracle.com/mbox/"},{"id":16379,"url":"https://patchwork.plctlab.org/api/1.2/patches/16379/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221107112805.3332619-1-och95@yandex.ru/","msgid":"<20221107112805.3332619-1-och95@yandex.ru>","list_archive_url":null,"date":"2022-11-07T11:28:05","name":"gold/aarch64: Fix adrp distance check","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221107112805.3332619-1-och95@yandex.ru/mbox/"},{"id":16400,"url":"https://patchwork.plctlab.org/api/1.2/patches/16400/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221107124620.1271470-1-christoph.muellner@vrull.eu/","msgid":"<20221107124620.1271470-1-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2022-11-07T12:46:20","name":"RISC-V: xtheadfmemidx: Use fp register in mnemonics","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221107124620.1271470-1-christoph.muellner@vrull.eu/mbox/"},{"id":16594,"url":"https://patchwork.plctlab.org/api/1.2/patches/16594/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/CACVBkZ+kM2xcpwk5zHQ4bqDV7dbPjZ6cMU9tR-h62+tDTgi3Tw@mail.gmail.com/","msgid":"","list_archive_url":null,"date":"2022-11-07T17:53:35","name":"GAS fix section alignment for aarch64-pe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/CACVBkZ+kM2xcpwk5zHQ4bqDV7dbPjZ6cMU9tR-h62+tDTgi3Tw@mail.gmail.com/mbox/"},{"id":16744,"url":"https://patchwork.plctlab.org/api/1.2/patches/16744/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221107222809.924195-1-indu.bhagat@oracle.com/","msgid":"<20221107222809.924195-1-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-07T22:28:09","name":"[V3.3,11/15] libctf: add libsframe to LDFLAGS and LIBS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221107222809.924195-1-indu.bhagat@oracle.com/mbox/"},{"id":16797,"url":"https://patchwork.plctlab.org/api/1.2/patches/16797/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221108012556.66467-1-haochen.jiang@intel.com/","msgid":"<20221108012556.66467-1-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-11-08T01:25:56","name":"x86: Correct wrong comments in vex_w_table","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221108012556.66467-1-haochen.jiang@intel.com/mbox/"},{"id":16884,"url":"https://patchwork.plctlab.org/api/1.2/patches/16884/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221108054530.796968-1-markus.t.metzger@intel.com/","msgid":"<20221108054530.796968-1-markus.t.metzger@intel.com>","list_archive_url":null,"date":"2022-11-08T05:45:29","name":"[1/2] gprofng: make cpu identification available to others","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221108054530.796968-1-markus.t.metzger@intel.com/mbox/"},{"id":16885,"url":"https://patchwork.plctlab.org/api/1.2/patches/16885/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221108054530.796968-2-markus.t.metzger@intel.com/","msgid":"<20221108054530.796968-2-markus.t.metzger@intel.com>","list_archive_url":null,"date":"2022-11-08T05:45:30","name":"[2/2] gdb, btrace: use cpuident.h to implement btrace_this_cpu","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221108054530.796968-2-markus.t.metzger@intel.com/mbox/"},{"id":16995,"url":"https://patchwork.plctlab.org/api/1.2/patches/16995/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ea0daf08-4923-ebfa-dcfe-699c43d63822@suse.com/","msgid":"","list_archive_url":null,"date":"2022-11-08T11:29:40","name":"x86/Intel: don'\''t accept malformed EXTRQ / INSERTQ","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ea0daf08-4923-ebfa-dcfe-699c43d63822@suse.com/mbox/"},{"id":17057,"url":"https://patchwork.plctlab.org/api/1.2/patches/17057/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221108141352.6613-1-jwilk@jwilk.net/","msgid":"<20221108141352.6613-1-jwilk@jwilk.net>","list_archive_url":null,"date":"2022-11-08T14:13:52","name":"Fix typos in the list of objdump options","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221108141352.6613-1-jwilk@jwilk.net/mbox/"},{"id":17117,"url":"https://patchwork.plctlab.org/api/1.2/patches/17117/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1667924955-9218-1-git-send-email-apinski@marvell.com/","msgid":"<1667924955-9218-1-git-send-email-apinski@marvell.com>","list_archive_url":null,"date":"2022-11-08T16:29:15","name":"Use toplevel configure for GMP and MPFR for gdb","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1667924955-9218-1-git-send-email-apinski@marvell.com/mbox/"},{"id":17160,"url":"https://patchwork.plctlab.org/api/1.2/patches/17160/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/27382086-397f-060f-6cf6-c1d36ff6b812@linux.ibm.com/","msgid":"<27382086-397f-060f-6cf6-c1d36ff6b812@linux.ibm.com>","list_archive_url":null,"date":"2022-11-08T18:23:32","name":"[COMMITTED] PowerPC: Add XSP operand define","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/27382086-397f-060f-6cf6-c1d36ff6b812@linux.ibm.com/mbox/"},{"id":17202,"url":"https://patchwork.plctlab.org/api/1.2/patches/17202/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221108192248.1622627-1-indu.bhagat@oracle.com/","msgid":"<20221108192248.1622627-1-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-08T19:22:48","name":"libctf: use libtool for link test in configure","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221108192248.1622627-1-indu.bhagat@oracle.com/mbox/"},{"id":17262,"url":"https://patchwork.plctlab.org/api/1.2/patches/17262/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221108225030.371817-1-hjl.tools@gmail.com/","msgid":"<20221108225030.371817-1-hjl.tools@gmail.com>","list_archive_url":null,"date":"2022-11-08T22:50:30","name":"ld: Always output local symbol for relocatable link","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221108225030.371817-1-hjl.tools@gmail.com/mbox/"},{"id":17399,"url":"https://patchwork.plctlab.org/api/1.2/patches/17399/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-2-indu.bhagat@oracle.com/","msgid":"<20221109084244.261296-2-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-09T08:42:34","name":"[V4,01/11] sframe.h: Add SFrame format definition","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-2-indu.bhagat@oracle.com/mbox/"},{"id":17398,"url":"https://patchwork.plctlab.org/api/1.2/patches/17398/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-3-indu.bhagat@oracle.com/","msgid":"<20221109084244.261296-3-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-09T08:42:35","name":"[V4,02/11] gas: add new command line option --gsframe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-3-indu.bhagat@oracle.com/mbox/"},{"id":17400,"url":"https://patchwork.plctlab.org/api/1.2/patches/17400/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-4-indu.bhagat@oracle.com/","msgid":"<20221109084244.261296-4-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-09T08:42:36","name":"[V4,03/11] gas: generate .sframe from CFI directives","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-4-indu.bhagat@oracle.com/mbox/"},{"id":17403,"url":"https://patchwork.plctlab.org/api/1.2/patches/17403/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-5-indu.bhagat@oracle.com/","msgid":"<20221109084244.261296-5-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-09T08:42:37","name":"[V4,04/11] gas: testsuite: add new tests for SFrame unwind info","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-5-indu.bhagat@oracle.com/mbox/"},{"id":17402,"url":"https://patchwork.plctlab.org/api/1.2/patches/17402/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-8-indu.bhagat@oracle.com/","msgid":"<20221109084244.261296-8-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-09T08:42:40","name":"[V4,07/11] readelf/objdump: support for SFrame section","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-8-indu.bhagat@oracle.com/mbox/"},{"id":17401,"url":"https://patchwork.plctlab.org/api/1.2/patches/17401/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-9-indu.bhagat@oracle.com/","msgid":"<20221109084244.261296-9-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-09T08:42:41","name":"[V4,08/11] src-release.sh: Add libsframe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-9-indu.bhagat@oracle.com/mbox/"},{"id":17404,"url":"https://patchwork.plctlab.org/api/1.2/patches/17404/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-10-indu.bhagat@oracle.com/","msgid":"<20221109084244.261296-10-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-09T08:42:42","name":"[V4,09/11] binutils/NEWS: add text for SFrame support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-10-indu.bhagat@oracle.com/mbox/"},{"id":17405,"url":"https://patchwork.plctlab.org/api/1.2/patches/17405/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-11-indu.bhagat@oracle.com/","msgid":"<20221109084244.261296-11-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-09T08:42:43","name":"[V4,10/11] gas/NEWS: add text about new command line option and SFrame support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-11-indu.bhagat@oracle.com/mbox/"}],"public":true,"mbox":"https://patchwork.plctlab.org/bundle/patchwork-bot/binutils-gdb_2022-11/mbox/"}]' ++ echo '[{"id":6,"url":"https://patchwork.plctlab.org/api/1.2/bundles/6/","web_url":"https://patchwork.plctlab.org/bundle/patchwork-bot/binutils-gdb_2022-10/","project":{"id":2,"url":"https://patchwork.plctlab.org/api/1.2/projects/2/","name":"binutils-gdb","link_name":"binutils-gdb","list_id":"binutils.sourceware.org","list_email":"binutils@sourceware.org","web_url":"https://github.com/wangliu-iscas/Patchwork-Bundles/blob/main/binutils-gdb.md","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"name":"binutils-gdb_2022-10","owner":{"id":3,"url":"https://patchwork.plctlab.org/api/1.2/users/3/","username":"patchwork-bot","first_name":"","last_name":"","email":"ouuuleilei@gmail.com"},"patches":[{"id":1592,"url":"https://patchwork.plctlab.org/api/1.2/patches/1592/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/385d01fd-7e57-1f3f-1bae-30aa0c313d63@suse.com/","msgid":"<385d01fd-7e57-1f3f-1bae-30aa0c313d63@suse.com>","list_archive_url":null,"date":"2022-09-30T11:59:45","name":"[3/4] RISC-V/gas: don'\''t open-code insn_length()","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/385d01fd-7e57-1f3f-1bae-30aa0c313d63@suse.com/mbox/"},{"id":1594,"url":"https://patchwork.plctlab.org/api/1.2/patches/1594/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f5757acf-7b90-a0e3-5eea-3b97cc226930@suse.com/","msgid":"","list_archive_url":null,"date":"2022-09-30T12:00:12","name":"[4/4] RISC-V/gas: allow generating up to 176-bit instructions with .insn","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f5757acf-7b90-a0e3-5eea-3b97cc226930@suse.com/mbox/"},{"id":1596,"url":"https://patchwork.plctlab.org/api/1.2/patches/1596/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930140503.38233-1-chigot@adacore.com/","msgid":"<20220930140503.38233-1-chigot@adacore.com>","list_archive_url":null,"date":"2022-09-30T14:05:03","name":"ld/testsuite: consistently add board_ldflags when linking with GCC","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930140503.38233-1-chigot@adacore.com/mbox/"},{"id":1619,"url":"https://patchwork.plctlab.org/api/1.2/patches/1619/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221001014451.532772-1-maskray@google.com/","msgid":"<20221001014451.532772-1-maskray@google.com>","list_archive_url":null,"date":"2022-10-01T01:44:51","name":"gold, dwp: support zstd compressed input debug sections [PR 29641]","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221001014451.532772-1-maskray@google.com/mbox/"},{"id":1620,"url":"https://patchwork.plctlab.org/api/1.2/patches/1620/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221001023846.590825-1-maskray@google.com/","msgid":"<20221001023846.590825-1-maskray@google.com>","list_archive_url":null,"date":"2022-10-01T02:38:46","name":"gold: add --compress-debug-sections=zstd [PR 29641]","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221001023846.590825-1-maskray@google.com/mbox/"},{"id":1623,"url":"https://patchwork.plctlab.org/api/1.2/patches/1623/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b4477c7f666bdeb7f8e998633c7b0cb62310b9ef.1664599545.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-01T04:45:52","name":"[RFC,1/1] RISC-V: Implement common register pair framework","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b4477c7f666bdeb7f8e998633c7b0cb62310b9ef.1664599545.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1625,"url":"https://patchwork.plctlab.org/api/1.2/patches/1625/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/53a265a1f14d17a6f7b106082f610994c5d546e0.1664602025.git.research_trasio@irq.a4lg.com/","msgid":"<53a265a1f14d17a6f7b106082f610994c5d546e0.1664602025.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-01T05:27:31","name":"[RFC,1/1] RISC-V: Implement extension variants","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/53a265a1f14d17a6f7b106082f610994c5d546e0.1664602025.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1626,"url":"https://patchwork.plctlab.org/api/1.2/patches/1626/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8db04962aba9c780f133840a8934353a58f223fe.1664602716.git.research_trasio@irq.a4lg.com/","msgid":"<8db04962aba9c780f133840a8934353a58f223fe.1664602716.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-01T05:39:26","name":"[1/1] RISC-V: Move supervisor instructions after all unprivileged ones","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8db04962aba9c780f133840a8934353a58f223fe.1664602716.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1627,"url":"https://patchwork.plctlab.org/api/1.2/patches/1627/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221001062057.681440-1-maskray@google.com/","msgid":"<20221001062057.681440-1-maskray@google.com>","list_archive_url":null,"date":"2022-10-01T06:20:57","name":"readelf: support zstd compressed debug sections [PR 29640]","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221001062057.681440-1-maskray@google.com/mbox/"},{"id":1631,"url":"https://patchwork.plctlab.org/api/1.2/patches/1631/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/619f112539c0bdecd58e25664f1250a3479a37f5.1664707612.git.aburgess@redhat.com/","msgid":"<619f112539c0bdecd58e25664f1250a3479a37f5.1664707612.git.aburgess@redhat.com>","list_archive_url":null,"date":"2022-10-02T10:47:52","name":"[PATCHv2,2/2] opcodes/arm: add disassembler styling for arm","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/619f112539c0bdecd58e25664f1250a3479a37f5.1664707612.git.aburgess@redhat.com/mbox/"},{"id":1635,"url":"https://patchwork.plctlab.org/api/1.2/patches/1635/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221002185433.gl7dvytfh5wthifx@lug-owl.de/","msgid":"<20221002185433.gl7dvytfh5wthifx@lug-owl.de>","list_archive_url":null,"date":"2022-10-02T18:54:33","name":"diagnostics.h: GCC 13 got -Wself-move, breaks GDB build","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221002185433.gl7dvytfh5wthifx@lug-owl.de/mbox/"},{"id":1637,"url":"https://patchwork.plctlab.org/api/1.2/patches/1637/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003014313.28766-1-mark@harmstone.com/","msgid":"<20221003014313.28766-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-03T01:43:12","name":"[1/2] ld: Add --pdb option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003014313.28766-1-mark@harmstone.com/mbox/"},{"id":1638,"url":"https://patchwork.plctlab.org/api/1.2/patches/1638/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003014313.28766-2-mark@harmstone.com/","msgid":"<20221003014313.28766-2-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-03T01:43:13","name":"[2/2] ld: Add minimal pdb generation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003014313.28766-2-mark@harmstone.com/mbox/"},{"id":1640,"url":"https://patchwork.plctlab.org/api/1.2/patches/1640/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/597ed978-d121-220c-b56b-2ffb94bd091c@suse.cz/","msgid":"<597ed978-d121-220c-b56b-2ffb94bd091c@suse.cz>","list_archive_url":null,"date":"2022-10-03T07:50:38","name":"[1/2] refactor usage of compressed_debug_section_type","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/597ed978-d121-220c-b56b-2ffb94bd091c@suse.cz/mbox/"},{"id":1641,"url":"https://patchwork.plctlab.org/api/1.2/patches/1641/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b8acdd83-f33a-74b8-e21a-23719a0b1a60@suse.cz/","msgid":"","list_archive_url":null,"date":"2022-10-03T07:50:44","name":"[2/2] add --enable-default-compressed-debug-sections-algorithm configure option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b8acdd83-f33a-74b8-e21a-23719a0b1a60@suse.cz/mbox/"},{"id":1642,"url":"https://patchwork.plctlab.org/api/1.2/patches/1642/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003101328.1790113-1-aburgess@redhat.com/","msgid":"<20221003101328.1790113-1-aburgess@redhat.com>","list_archive_url":null,"date":"2022-10-03T10:13:28","name":"opcodes/riscv: style csr names as registers","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003101328.1790113-1-aburgess@redhat.com/mbox/"},{"id":1643,"url":"https://patchwork.plctlab.org/api/1.2/patches/1643/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7ba14fc4472ce97d4f7a4433cad8a571e89f82f4.1664793840.git.research_trasio@irq.a4lg.com/","msgid":"<7ba14fc4472ce97d4f7a4433cad8a571e89f82f4.1664793840.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-03T10:43:59","name":"[v3,1/6] RISC-V: Fix immediates to have \"immediate\" style","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7ba14fc4472ce97d4f7a4433cad8a571e89f82f4.1664793840.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1644,"url":"https://patchwork.plctlab.org/api/1.2/patches/1644/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a498bec37c1fd1dcda57cbf95e5f8cfba09b31d3.1664793840.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-03T10:44:00","name":"[v3,2/6] RISC-V: Fix printf argument types corresponding %x","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a498bec37c1fd1dcda57cbf95e5f8cfba09b31d3.1664793840.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1647,"url":"https://patchwork.plctlab.org/api/1.2/patches/1647/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0002ea716713ace4998a33dde0b81f4f890d10bf.1664793840.git.research_trasio@irq.a4lg.com/","msgid":"<0002ea716713ace4998a33dde0b81f4f890d10bf.1664793840.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-03T10:44:01","name":"[v3,3/6] RISC-V: Optimize riscv_disassemble_data printf","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0002ea716713ace4998a33dde0b81f4f890d10bf.1664793840.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1646,"url":"https://patchwork.plctlab.org/api/1.2/patches/1646/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c65fc3e9aa58965d6768a28c9fd7467fea9897a5.1664793840.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-03T10:44:02","name":"[v3,4/6] RISC-V: Print comma and tabs as the \"text\" style","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c65fc3e9aa58965d6768a28c9fd7467fea9897a5.1664793840.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1648,"url":"https://patchwork.plctlab.org/api/1.2/patches/1648/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5abe1d8a7694417b990e11d8f6cd6789573872e5.1664793840.git.research_trasio@irq.a4lg.com/","msgid":"<5abe1d8a7694417b990e11d8f6cd6789573872e5.1664793840.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-03T10:44:03","name":"[v3,5/6] RISC-V: Fix T-Head immediate types on printing","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5abe1d8a7694417b990e11d8f6cd6789573872e5.1664793840.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1649,"url":"https://patchwork.plctlab.org/api/1.2/patches/1649/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0b68af932117258c908db62cf87c3a15d3cdec41.1664793840.git.research_trasio@irq.a4lg.com/","msgid":"<0b68af932117258c908db62cf87c3a15d3cdec41.1664793840.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-03T10:44:04","name":"[v3,6/6] RISC-V: Print XTheadMemPair literal as \"immediate\"","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0b68af932117258c908db62cf87c3a15d3cdec41.1664793840.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1656,"url":"https://patchwork.plctlab.org/api/1.2/patches/1656/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/87lepxcd6x.fsf@redhat.com/","msgid":"<87lepxcd6x.fsf@redhat.com>","list_archive_url":null,"date":"2022-10-03T12:19:02","name":"Commit: readelf: Do not load section data from offset 0","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/87lepxcd6x.fsf@redhat.com/mbox/"},{"id":1659,"url":"https://patchwork.plctlab.org/api/1.2/patches/1659/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e0d369d419da9c0441f415da7f54352aead8f655.1664707612.git.aburgess@redhat.com/","msgid":"","list_archive_url":null,"date":"2022-10-03T16:37:36","name":"[PATCHv2,1/2] opcodes/arm: use '\''@'\'' consistently for the comment character","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e0d369d419da9c0441f415da7f54352aead8f655.1664707612.git.aburgess@redhat.com/mbox/"},{"id":1660,"url":"https://patchwork.plctlab.org/api/1.2/patches/1660/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003165848.11142-1-palmer@rivosinc.com/","msgid":"<20221003165848.11142-1-palmer@rivosinc.com>","list_archive_url":null,"date":"2022-10-03T16:58:48","name":"gas: NEWS: Mention the T-Head extensions that were recently added","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003165848.11142-1-palmer@rivosinc.com/mbox/"},{"id":1671,"url":"https://patchwork.plctlab.org/api/1.2/patches/1671/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/YzvrMEdkXjIn5Lfz@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-04T08:13:36","name":"Support objcopy changing compression to or from zstd","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/YzvrMEdkXjIn5Lfz@squeak.grove.modra.org/mbox/"},{"id":1673,"url":"https://patchwork.plctlab.org/api/1.2/patches/1673/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0bc857d306bb7c8130e5328dbe6b9ed2fed3ef87.1664873933.git.research_trasio@irq.a4lg.com/","msgid":"<0bc857d306bb7c8130e5328dbe6b9ed2fed3ef87.1664873933.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-04T08:59:07","name":"[1/2] RISC-V: Fix buffer overflow on print_insn_riscv","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0bc857d306bb7c8130e5328dbe6b9ed2fed3ef87.1664873933.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1672,"url":"https://patchwork.plctlab.org/api/1.2/patches/1672/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/89612fe01d902007bf84a7dfb0df5f85d5c166e4.1664873933.git.research_trasio@irq.a4lg.com/","msgid":"<89612fe01d902007bf84a7dfb0df5f85d5c166e4.1664873933.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-04T08:59:08","name":"[2/2] gdb/riscv: Fix buffer overflow on riscv_insn::fetch_instruction","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/89612fe01d902007bf84a7dfb0df5f85d5c166e4.1664873933.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1676,"url":"https://patchwork.plctlab.org/api/1.2/patches/1676/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fc849c94f4adcac1c4ccc5508c7a145a2f13b2a9.1664876744.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-04T09:45:49","name":"[v2,1/2] RISC-V: Fix buffer overflow on print_insn_riscv","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fc849c94f4adcac1c4ccc5508c7a145a2f13b2a9.1664876744.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1677,"url":"https://patchwork.plctlab.org/api/1.2/patches/1677/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4eb6e59ae2e790dbbf2bc92477edd281648d8814.1664876744.git.research_trasio@irq.a4lg.com/","msgid":"<4eb6e59ae2e790dbbf2bc92477edd281648d8814.1664876744.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-04T09:45:50","name":"[v2,2/2] gdb/riscv: Partial support for instructions up to 176-bits","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4eb6e59ae2e790dbbf2bc92477edd281648d8814.1664876744.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1678,"url":"https://patchwork.plctlab.org/api/1.2/patches/1678/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ebf16f9e1f45115d0793952ccb4a94d4233303f9.1664882725.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-04T11:25:56","name":"[v3,1/2] RISC-V: Fix buffer overflow on print_insn_riscv","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ebf16f9e1f45115d0793952ccb4a94d4233303f9.1664882725.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1679,"url":"https://patchwork.plctlab.org/api/1.2/patches/1679/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/83464b09b8649525259c69c853dfa2c9575a204b.1664882725.git.research_trasio@irq.a4lg.com/","msgid":"<83464b09b8649525259c69c853dfa2c9575a204b.1664882725.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-04T11:25:57","name":"[v3,2/2] gdb/riscv: Partial support for instructions up to 176-bit","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/83464b09b8649525259c69c853dfa2c9575a204b.1664882725.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1681,"url":"https://patchwork.plctlab.org/api/1.2/patches/1681/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ffa9c1d7-e8c2-a62b-ef3e-b565c0ffbe5b@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-04T13:56:27","name":"RISC-V: Zicbo{m,p,z} adjustments to riscv_multi_subset_supports_ext()","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ffa9c1d7-e8c2-a62b-ef3e-b565c0ffbe5b@suse.com/mbox/"},{"id":1690,"url":"https://patchwork.plctlab.org/api/1.2/patches/1690/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221004161720.1963953-1-vladimir.mezentsev@oracle.com/","msgid":"<20221004161720.1963953-1-vladimir.mezentsev@oracle.com>","list_archive_url":null,"date":"2022-10-04T16:17:20","name":"gprofng: fix build with --enable-pgo-build=lto","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221004161720.1963953-1-vladimir.mezentsev@oracle.com/mbox/"},{"id":1691,"url":"https://patchwork.plctlab.org/api/1.2/patches/1691/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c0211bc9c57be6c79c6d878ce147f63b657f461d.camel@espressif.com/","msgid":"","list_archive_url":null,"date":"2022-10-04T16:22:05","name":"bfd: xtensa: fix __stop_SECTION literal drop,","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c0211bc9c57be6c79c6d878ce147f63b657f461d.camel@espressif.com/mbox/"},{"id":1702,"url":"https://patchwork.plctlab.org/api/1.2/patches/1702/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5f482299-6c60-b2b3-9abe-f4a55a5a26c5@univ-grenoble-alpes.fr/","msgid":"<5f482299-6c60-b2b3-9abe-f4a55a5a26c5@univ-grenoble-alpes.fr>","list_archive_url":null,"date":"2022-10-04T20:03:20","name":"[RFC] bfd: use bfd_vma for the 64-bit version of put[lb] and get[lb]","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5f482299-6c60-b2b3-9abe-f4a55a5a26c5@univ-grenoble-alpes.fr/mbox/"},{"id":1711,"url":"https://patchwork.plctlab.org/api/1.2/patches/1711/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Yz0Gsxdxe0TePbJT@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-05T04:23:15","name":"PR29647, objdump -S looping","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Yz0Gsxdxe0TePbJT@squeak.grove.modra.org/mbox/"},{"id":1712,"url":"https://patchwork.plctlab.org/api/1.2/patches/1712/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/02d747d2-f57b-0fb5-b893-842b6cc41f2f@suse.com/","msgid":"<02d747d2-f57b-0fb5-b893-842b6cc41f2f@suse.com>","list_archive_url":null,"date":"2022-10-05T07:20:47","name":"[v3,1/7] x86: constify parse_insn()'\''s input","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/02d747d2-f57b-0fb5-b893-842b6cc41f2f@suse.com/mbox/"},{"id":1713,"url":"https://patchwork.plctlab.org/api/1.2/patches/1713/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/925cb740-4e1b-abc4-8526-aaab6faae5e1@suse.com/","msgid":"<925cb740-4e1b-abc4-8526-aaab6faae5e1@suse.com>","list_archive_url":null,"date":"2022-10-05T07:22:19","name":"[v3,2/7] x86: introduce Pass2 insn attribute","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/925cb740-4e1b-abc4-8526-aaab6faae5e1@suse.com/mbox/"},{"id":1714,"url":"https://patchwork.plctlab.org/api/1.2/patches/1714/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e16d3e78-39ca-f715-508f-a4104b8ab9a9@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-05T07:23:51","name":"[v3,3/7] x86: re-work insn/suffix recognition","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e16d3e78-39ca-f715-508f-a4104b8ab9a9@suse.com/mbox/"},{"id":1715,"url":"https://patchwork.plctlab.org/api/1.2/patches/1715/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e4e4b80b-794c-7485-1997-685adab8fb27@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-05T07:24:20","name":"[v3,4/7] x86-64: further re-work insn/suffix recognition to also cover MOVSL","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e4e4b80b-794c-7485-1997-685adab8fb27@suse.com/mbox/"},{"id":1716,"url":"https://patchwork.plctlab.org/api/1.2/patches/1716/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/540678fc-8bff-ec68-c97c-478d2631998c@suse.com/","msgid":"<540678fc-8bff-ec68-c97c-478d2631998c@suse.com>","list_archive_url":null,"date":"2022-10-05T07:24:55","name":"[v3,5/7] ix86: don'\''t recognize/derive Q suffix in the common case","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/540678fc-8bff-ec68-c97c-478d2631998c@suse.com/mbox/"},{"id":1718,"url":"https://patchwork.plctlab.org/api/1.2/patches/1718/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e4692495-7d3d-074d-14f9-364d4a9a998c@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-05T07:25:25","name":"[v3,6/7] x86-64: allow HLE store of accumulator to absolute 32-bit address","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e4692495-7d3d-074d-14f9-364d4a9a998c@suse.com/mbox/"},{"id":1717,"url":"https://patchwork.plctlab.org/api/1.2/patches/1717/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e8014ebd-d16b-17a7-9f34-3700fc164136@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-05T07:25:57","name":"[v3,7/7] x86: move bad-use-of-TLS-reloc check","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e8014ebd-d16b-17a7-9f34-3700fc164136@suse.com/mbox/"},{"id":1719,"url":"https://patchwork.plctlab.org/api/1.2/patches/1719/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1266f001-4511-2662-dba9-14b4d0317c57@suse.com/","msgid":"<1266f001-4511-2662-dba9-14b4d0317c57@suse.com>","list_archive_url":null,"date":"2022-10-05T07:40:50","name":"x86: drop \"regmask\" static variable","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1266f001-4511-2662-dba9-14b4d0317c57@suse.com/mbox/"},{"id":1751,"url":"https://patchwork.plctlab.org/api/1.2/patches/1751/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/af45c5d57c221e43101c2aa38b14f4b4ac12d011.1665031170.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-06T04:40:15","name":"[v2,1/2] RISC-V: Fallback for instructions longer than 64b","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/af45c5d57c221e43101c2aa38b14f4b4ac12d011.1665031170.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1752,"url":"https://patchwork.plctlab.org/api/1.2/patches/1752/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c6e55781245dd3e8e9b8debd6130fc5449dfbd55.1665031170.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-06T04:40:16","name":"[v2,2/2] RISC-V: Improve \"bits undefined\" diagnostics","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c6e55781245dd3e8e9b8debd6130fc5449dfbd55.1665031170.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1776,"url":"https://patchwork.plctlab.org/api/1.2/patches/1776/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d52952119e15357c0e823f8a2398999359588b4d.1665050099.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-06T09:56:30","name":"[v3,1/2] RISC-V: Fallback for instructions longer than 64b","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d52952119e15357c0e823f8a2398999359588b4d.1665050099.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1777,"url":"https://patchwork.plctlab.org/api/1.2/patches/1777/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d907b1997f60ff7823c4a23e281ec9d8ddcbf3f1.1665050099.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-06T09:56:31","name":"[v3,2/2] RISC-V: Improve \"bits undefined\" diagnostics","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d907b1997f60ff7823c4a23e281ec9d8ddcbf3f1.1665050099.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1781,"url":"https://patchwork.plctlab.org/api/1.2/patches/1781/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221006114628.304185-1-chigot@adacore.com/","msgid":"<20221006114628.304185-1-chigot@adacore.com>","list_archive_url":null,"date":"2022-10-06T11:46:28","name":"RISC-V: fix linker message when relaxation deletes bytes","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221006114628.304185-1-chigot@adacore.com/mbox/"},{"id":1801,"url":"https://patchwork.plctlab.org/api/1.2/patches/1801/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Yz+Yhyg7UewC9/kp@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-07T03:09:59","name":"PR29653, objcopy/strip: fuzzed small input file induces large output file","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Yz+Yhyg7UewC9/kp@squeak.grove.modra.org/mbox/"},{"id":1803,"url":"https://patchwork.plctlab.org/api/1.2/patches/1803/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/PH1P110MB16505D9D39EC5B1DE22FE3D5EC5F9@PH1P110MB1650.NAMP110.PROD.OUTLOOK.COM/","msgid":"","list_archive_url":null,"date":"2022-10-07T04:10:07","name":"@CPP_FOR_BUILD@ problem since binutils-2.38","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/PH1P110MB16505D9D39EC5B1DE22FE3D5EC5F9@PH1P110MB1650.NAMP110.PROD.OUTLOOK.COM/mbox/"},{"id":1827,"url":"https://patchwork.plctlab.org/api/1.2/patches/1827/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8e13bce108ac10a0c1dd911e23ec572926f7ae44.1665203374.git.research_trasio@irq.a4lg.com/","msgid":"<8e13bce108ac10a0c1dd911e23ec572926f7ae44.1665203374.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-08T04:29:53","name":"[v2,1/1] RISC-V: Test DWARF register numbers for \"fp\"","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8e13bce108ac10a0c1dd911e23ec572926f7ae44.1665203374.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1828,"url":"https://patchwork.plctlab.org/api/1.2/patches/1828/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0883001b3572e54d3fba264429c7ade2adb66610.1665203441.git.research_trasio@irq.a4lg.com/","msgid":"<0883001b3572e54d3fba264429c7ade2adb66610.1665203441.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-08T04:31:15","name":"[1/1] RISC-V: Move standard hints before all instructions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0883001b3572e54d3fba264429c7ade2adb66610.1665203441.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1829,"url":"https://patchwork.plctlab.org/api/1.2/patches/1829/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/58e16a241d7376fcae2515c6bd5a2b41d275eeba.1665203531.git.research_trasio@irq.a4lg.com/","msgid":"<58e16a241d7376fcae2515c6bd5a2b41d275eeba.1665203531.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-08T04:32:18","name":"[RFC,1/1] RISC-V: Imply '\''Zicsr'\'' from privileged extensions with CSRs","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/58e16a241d7376fcae2515c6bd5a2b41d275eeba.1665203531.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1830,"url":"https://patchwork.plctlab.org/api/1.2/patches/1830/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/cb5076fc96e8f2097779a3abcde843dcdd660031.1665203660.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-08T04:34:23","name":"[1/5] opcodes/riscv-dis.c: Tidying with comments/clarity","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/cb5076fc96e8f2097779a3abcde843dcdd660031.1665203660.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1832,"url":"https://patchwork.plctlab.org/api/1.2/patches/1832/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1f1aa0838bf9c4f10a45fcfe3c682f7efc79d9ae.1665203660.git.research_trasio@irq.a4lg.com/","msgid":"<1f1aa0838bf9c4f10a45fcfe3c682f7efc79d9ae.1665203660.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-08T04:34:24","name":"[2/5] opcodes/riscv-dis.c: Tidying with spacing","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1f1aa0838bf9c4f10a45fcfe3c682f7efc79d9ae.1665203660.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1831,"url":"https://patchwork.plctlab.org/api/1.2/patches/1831/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/740bc5e2d2618d236519b39fedd1a1d7ae4e05da.1665203660.git.research_trasio@irq.a4lg.com/","msgid":"<740bc5e2d2618d236519b39fedd1a1d7ae4e05da.1665203660.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-08T04:34:25","name":"[3/5] opcodes/riscv-dis.c: Use bool type whenever possible","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/740bc5e2d2618d236519b39fedd1a1d7ae4e05da.1665203660.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1833,"url":"https://patchwork.plctlab.org/api/1.2/patches/1833/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6e3a9c235e317f441b4383b3daa68f2051bdc149.1665203660.git.research_trasio@irq.a4lg.com/","msgid":"<6e3a9c235e317f441b4383b3daa68f2051bdc149.1665203660.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-08T04:34:26","name":"[4/5] opcodes/riscv-dis.c: Make XLEN variable static","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6e3a9c235e317f441b4383b3daa68f2051bdc149.1665203660.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1834,"url":"https://patchwork.plctlab.org/api/1.2/patches/1834/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ad929233a62d887495122721340b2f9c80392963.1665203660.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-08T04:34:27","name":"[5/5] opcodes/riscv-dis.c: Remove last_map_state","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ad929233a62d887495122721340b2f9c80392963.1665203660.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1836,"url":"https://patchwork.plctlab.org/api/1.2/patches/1836/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d07e2b6f36ea2fd5830924a9bfeda941b774b687.1665290422.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-09T05:09:22","name":"RISC-V: Move certain arrays to riscv-opc.c","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d07e2b6f36ea2fd5830924a9bfeda941b774b687.1665290422.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1844,"url":"https://patchwork.plctlab.org/api/1.2/patches/1844/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010004623.16582-1-mark@harmstone.com/","msgid":"<20221010004623.16582-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-10T00:46:22","name":"[v2,1/2] ld: Add --pdb option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010004623.16582-1-mark@harmstone.com/mbox/"},{"id":1845,"url":"https://patchwork.plctlab.org/api/1.2/patches/1845/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010004623.16582-2-mark@harmstone.com/","msgid":"<20221010004623.16582-2-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-10T00:46:23","name":"[v2,2/2] ld: Add minimal pdb generation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010004623.16582-2-mark@harmstone.com/mbox/"},{"id":1890,"url":"https://patchwork.plctlab.org/api/1.2/patches/1890/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010200433.414320-1-vladimir.mezentsev@oracle.com/","msgid":"<20221010200433.414320-1-vladimir.mezentsev@oracle.com>","list_archive_url":null,"date":"2022-10-10T20:04:33","name":"gprofng: run tests without installation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010200433.414320-1-vladimir.mezentsev@oracle.com/mbox/"},{"id":1893,"url":"https://patchwork.plctlab.org/api/1.2/patches/1893/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010230426.719238-1-vladimir.mezentsev@oracle.com/","msgid":"<20221010230426.719238-1-vladimir.mezentsev@oracle.com>","list_archive_url":null,"date":"2022-10-10T23:04:26","name":"[2/2] gprofng: use the --libdir path to find libraries","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010230426.719238-1-vladimir.mezentsev@oracle.com/mbox/"},{"id":1894,"url":"https://patchwork.plctlab.org/api/1.2/patches/1894/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010235155.842469-1-vladimir.mezentsev@oracle.com/","msgid":"<20221010235155.842469-1-vladimir.mezentsev@oracle.com>","list_archive_url":null,"date":"2022-10-10T23:51:55","name":"[3/3] gprofng: no need to build version.texi","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010235155.842469-1-vladimir.mezentsev@oracle.com/mbox/"},{"id":1895,"url":"https://patchwork.plctlab.org/api/1.2/patches/1895/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011003702.4287-1-mark@harmstone.com/","msgid":"<20221011003702.4287-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-11T00:37:01","name":"[v3,1/2] ld: Add --pdb option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011003702.4287-1-mark@harmstone.com/mbox/"},{"id":1897,"url":"https://patchwork.plctlab.org/api/1.2/patches/1897/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011003702.4287-2-mark@harmstone.com/","msgid":"<20221011003702.4287-2-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-11T00:37:02","name":"[v3,2/2] ld: Add minimal pdb generation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011003702.4287-2-mark@harmstone.com/mbox/"},{"id":1928,"url":"https://patchwork.plctlab.org/api/1.2/patches/1928/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011175332.17156-1-mark@harmstone.com/","msgid":"<20221011175332.17156-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-11T17:53:31","name":"[v4,1/2] ld: Add --pdb option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011175332.17156-1-mark@harmstone.com/mbox/"},{"id":1929,"url":"https://patchwork.plctlab.org/api/1.2/patches/1929/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011175332.17156-2-mark@harmstone.com/","msgid":"<20221011175332.17156-2-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-11T17:53:32","name":"[v4,2/2] ld: Add minimal pdb generation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011175332.17156-2-mark@harmstone.com/mbox/"},{"id":1941,"url":"https://patchwork.plctlab.org/api/1.2/patches/1941/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221012031005.237446-1-simon.marchi@polymtl.ca/","msgid":"<20221012031005.237446-1-simon.marchi@polymtl.ca>","list_archive_url":null,"date":"2022-10-12T03:10:05","name":"[pushed] Re-apply \"Pass PKG_CONFIG_PATH down from top-level Makefile\"","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221012031005.237446-1-simon.marchi@polymtl.ca/mbox/"},{"id":1976,"url":"https://patchwork.plctlab.org/api/1.2/patches/1976/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1216a3f8-2273-8681-f528-9493a66891f0@suse.com/","msgid":"<1216a3f8-2273-8681-f528-9493a66891f0@suse.com>","list_archive_url":null,"date":"2022-10-13T08:16:49","name":"[v4,1/8] x86: constify parse_insn()'\''s input","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1216a3f8-2273-8681-f528-9493a66891f0@suse.com/mbox/"},{"id":1977,"url":"https://patchwork.plctlab.org/api/1.2/patches/1977/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/11599bbe-c779-aa9f-4d5d-c2243f0e69dc@suse.com/","msgid":"<11599bbe-c779-aa9f-4d5d-c2243f0e69dc@suse.com>","list_archive_url":null,"date":"2022-10-13T08:17:17","name":"[v4,2/8] x86: introduce Pass2 insn attribute","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/11599bbe-c779-aa9f-4d5d-c2243f0e69dc@suse.com/mbox/"},{"id":1978,"url":"https://patchwork.plctlab.org/api/1.2/patches/1978/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/357273a3-060c-23db-72da-3fc9d1be3d2a@suse.com/","msgid":"<357273a3-060c-23db-72da-3fc9d1be3d2a@suse.com>","list_archive_url":null,"date":"2022-10-13T08:18:09","name":"[v4,3/8] x86: re-work insn/suffix recognition","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/357273a3-060c-23db-72da-3fc9d1be3d2a@suse.com/mbox/"},{"id":1979,"url":"https://patchwork.plctlab.org/api/1.2/patches/1979/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0ec0587f-6a7b-45b6-8346-e5d774e73636@suse.com/","msgid":"<0ec0587f-6a7b-45b6-8346-e5d774e73636@suse.com>","list_archive_url":null,"date":"2022-10-13T08:18:39","name":"[v4,4/8] x86-64: further re-work insn/suffix recognition to also cover MOVSL","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0ec0587f-6a7b-45b6-8346-e5d774e73636@suse.com/mbox/"},{"id":1980,"url":"https://patchwork.plctlab.org/api/1.2/patches/1980/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fb617d0b-8759-3169-5a65-1178b7fef3d7@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-13T08:19:34","name":"[v4,5/8] ix86: don'\''t recognize/derive Q suffix in the common case","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fb617d0b-8759-3169-5a65-1178b7fef3d7@suse.com/mbox/"},{"id":1981,"url":"https://patchwork.plctlab.org/api/1.2/patches/1981/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1df3bd01-99c5-f56c-d937-970edd42b2b8@suse.com/","msgid":"<1df3bd01-99c5-f56c-d937-970edd42b2b8@suse.com>","list_archive_url":null,"date":"2022-10-13T08:20:14","name":"[v4,6/8] x86-64: allow HLE store of accumulator to absolute 32-bit address","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1df3bd01-99c5-f56c-d937-970edd42b2b8@suse.com/mbox/"},{"id":1982,"url":"https://patchwork.plctlab.org/api/1.2/patches/1982/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8486a218-39ec-16b2-5c6c-5037196b93cf@suse.com/","msgid":"<8486a218-39ec-16b2-5c6c-5037196b93cf@suse.com>","list_archive_url":null,"date":"2022-10-13T08:21:00","name":"[v4,7/8] x86: move bad-use-of-TLS-reloc check","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8486a218-39ec-16b2-5c6c-5037196b93cf@suse.com/mbox/"},{"id":1983,"url":"https://patchwork.plctlab.org/api/1.2/patches/1983/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7d82692d-93df-fbee-9efb-2f44e8a91df3@suse.com/","msgid":"<7d82692d-93df-fbee-9efb-2f44e8a91df3@suse.com>","list_archive_url":null,"date":"2022-10-13T08:22:00","name":"[v4,8/8] x86: drop (now) stray IsString","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7d82692d-93df-fbee-9efb-2f44e8a91df3@suse.com/mbox/"},{"id":2013,"url":"https://patchwork.plctlab.org/api/1.2/patches/2013/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8ab93d7a617ad480dd786210f46db0e5aa07d1ac.1665655719.git.research_trasio@irq.a4lg.com/","msgid":"<8ab93d7a617ad480dd786210f46db0e5aa07d1ac.1665655719.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-13T10:11:41","name":"include: Declare getopt function on old GNU libc","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8ab93d7a617ad480dd786210f46db0e5aa07d1ac.1665655719.git.research_trasio@irq.a4lg.com/mbox/"},{"id":2352,"url":"https://patchwork.plctlab.org/api/1.2/patches/2352/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221013201332.2747246-1-maskray@google.com/","msgid":"<20221013201332.2747246-1-maskray@google.com>","list_archive_url":null,"date":"2022-10-13T20:13:32","name":"ld: Add --undefined-version","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221013201332.2747246-1-maskray@google.com/mbox/"},{"id":2532,"url":"https://patchwork.plctlab.org/api/1.2/patches/2532/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014063520.1428330-2-zengxiao@eswincomputing.com/","msgid":"<20221014063520.1428330-2-zengxiao@eswincomputing.com>","list_archive_url":null,"date":"2022-10-14T06:35:20","name":"[1/1] RISC-V: Make R_RISCV_SUB6 conforms to riscv abi standard","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014063520.1428330-2-zengxiao@eswincomputing.com/mbox/"},{"id":2560,"url":"https://patchwork.plctlab.org/api/1.2/patches/2560/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/027ae69a-636b-6757-297a-eec42936401e@linaro.org/","msgid":"<027ae69a-636b-6757-297a-eec42936401e@linaro.org>","list_archive_url":null,"date":"2022-10-14T07:58:22","name":"[v3] aarch64-pe support for LD, GAS and BFD","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/027ae69a-636b-6757-297a-eec42936401e@linaro.org/mbox/"},{"id":2602,"url":"https://patchwork.plctlab.org/api/1.2/patches/2602/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-2-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-2-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:39","name":"[01/10] Support Intel AVX-IFMA","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-2-haochen.jiang@intel.com/mbox/"},{"id":2608,"url":"https://patchwork.plctlab.org/api/1.2/patches/2608/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-3-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-3-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:40","name":"[02/10] Support Intel AVX-VNNI-INT8","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-3-haochen.jiang@intel.com/mbox/"},{"id":2611,"url":"https://patchwork.plctlab.org/api/1.2/patches/2611/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-4-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-4-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:41","name":"[03/10] Support Intel AVX-NE-CONVERT","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-4-haochen.jiang@intel.com/mbox/"},{"id":2610,"url":"https://patchwork.plctlab.org/api/1.2/patches/2610/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-5-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-5-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:42","name":"[04/10] Support Intel CMPccXADD","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-5-haochen.jiang@intel.com/mbox/"},{"id":2601,"url":"https://patchwork.plctlab.org/api/1.2/patches/2601/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-6-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-6-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:43","name":"[05/10] Add handler for more i386_cpu_flags","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-6-haochen.jiang@intel.com/mbox/"},{"id":2606,"url":"https://patchwork.plctlab.org/api/1.2/patches/2606/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-7-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-7-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:44","name":"[06/10] Support Intel RAO-INT","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-7-haochen.jiang@intel.com/mbox/"},{"id":2609,"url":"https://patchwork.plctlab.org/api/1.2/patches/2609/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-8-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-8-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:45","name":"[07/10] Support Intel WRMSRNS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-8-haochen.jiang@intel.com/mbox/"},{"id":2605,"url":"https://patchwork.plctlab.org/api/1.2/patches/2605/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-9-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-9-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:46","name":"[08/10] Support Intel MSRLIST","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-9-haochen.jiang@intel.com/mbox/"},{"id":2607,"url":"https://patchwork.plctlab.org/api/1.2/patches/2607/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-10-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-10-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:47","name":"[09/10] Support Intel AMX-FP16","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-10-haochen.jiang@intel.com/mbox/"},{"id":2604,"url":"https://patchwork.plctlab.org/api/1.2/patches/2604/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-11-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-11-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:48","name":"[10/10] Support Intel PREFETCHI","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-11-haochen.jiang@intel.com/mbox/"},{"id":2643,"url":"https://patchwork.plctlab.org/api/1.2/patches/2643/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7bac66be-535e-9051-d674-f2f5ba180e17@suse.com/","msgid":"<7bac66be-535e-9051-d674-f2f5ba180e17@suse.com>","list_archive_url":null,"date":"2022-10-14T10:22:34","name":"x86: fold AVX512-VNNI disassembler entries with AVX-VNNI ones","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7bac66be-535e-9051-d674-f2f5ba180e17@suse.com/mbox/"},{"id":2654,"url":"https://patchwork.plctlab.org/api/1.2/patches/2654/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0lIo5+ncY/MqBEq@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-14T11:31:47","name":"PR29677, Field `the_bfd` of `asymbol` is uninitialised","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0lIo5+ncY/MqBEq@squeak.grove.modra.org/mbox/"},{"id":2656,"url":"https://patchwork.plctlab.org/api/1.2/patches/2656/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0lJksn49ZpABY89@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-14T11:35:46","name":"e200 LSP support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0lJksn49ZpABY89@squeak.grove.modra.org/mbox/"},{"id":2657,"url":"https://patchwork.plctlab.org/api/1.2/patches/2657/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0lJxxYoeD5iDYAD@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-14T11:36:39","name":"PowerPC SPE disassembly and tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0lJxxYoeD5iDYAD@squeak.grove.modra.org/mbox/"},{"id":2695,"url":"https://patchwork.plctlab.org/api/1.2/patches/2695/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/DM6PR12MB4219611F6CC2A0702884A602E7249@DM6PR12MB4219.namprd12.prod.outlook.com/","msgid":"","list_archive_url":null,"date":"2022-10-14T13:29:40","name":"Binutils: Adding new testcase for addr2line.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/DM6PR12MB4219611F6CC2A0702884A602E7249@DM6PR12MB4219.namprd12.prod.outlook.com/mbox/"},{"id":2700,"url":"https://patchwork.plctlab.org/api/1.2/patches/2700/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9fd2c88d-98b2-99a4-419f-c7235b2cf960@suse.com/","msgid":"<9fd2c88d-98b2-99a4-419f-c7235b2cf960@suse.com>","list_archive_url":null,"date":"2022-10-14T14:11:35","name":"x86: properly decode EVEX.W for AVX512_4{FMAPS,VNNIW} insns","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9fd2c88d-98b2-99a4-419f-c7235b2cf960@suse.com/mbox/"},{"id":2981,"url":"https://patchwork.plctlab.org/api/1.2/patches/2981/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0uLzalqjm4C87GN@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-16T04:42:53","name":"PowerPC se_rfmci and VLE, SPE2 and LSP insns with -many","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0uLzalqjm4C87GN@squeak.grove.modra.org/mbox/"},{"id":3152,"url":"https://patchwork.plctlab.org/api/1.2/patches/3152/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221016232419.1135-1-mark@harmstone.com/","msgid":"<20221016232419.1135-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-16T23:24:18","name":"[v5,1/2] ld: Add --pdb option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221016232419.1135-1-mark@harmstone.com/mbox/"},{"id":3151,"url":"https://patchwork.plctlab.org/api/1.2/patches/3151/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221016232419.1135-2-mark@harmstone.com/","msgid":"<20221016232419.1135-2-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-16T23:24:19","name":"[v5,2/2] ld: Add minimal pdb generation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221016232419.1135-2-mark@harmstone.com/mbox/"},{"id":3258,"url":"https://patchwork.plctlab.org/api/1.2/patches/3258/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/19c08747-fa5b-1e67-3dd2-c891a2c0c1fa@suse.com/","msgid":"<19c08747-fa5b-1e67-3dd2-c891a2c0c1fa@suse.com>","list_archive_url":null,"date":"2022-10-17T07:44:51","name":"x86: correct CPU_AMX_{BF16,INT8}_FLAGS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/19c08747-fa5b-1e67-3dd2-c891a2c0c1fa@suse.com/mbox/"},{"id":3272,"url":"https://patchwork.plctlab.org/api/1.2/patches/3272/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/85dd526c-d3a7-72dc-5444-ed5573eebec1@suse.com/","msgid":"<85dd526c-d3a7-72dc-5444-ed5573eebec1@suse.com>","list_archive_url":null,"date":"2022-10-17T08:30:12","name":"x86: generalize gas documentation for disabling of ISA extensions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/85dd526c-d3a7-72dc-5444-ed5573eebec1@suse.com/mbox/"},{"id":3759,"url":"https://patchwork.plctlab.org/api/1.2/patches/3759/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-2-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-2-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:15:58","name":"[V2,01/15] sframe.h: Add SFrame format definition","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-2-indu.bhagat@oracle.com/mbox/"},{"id":3762,"url":"https://patchwork.plctlab.org/api/1.2/patches/3762/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-3-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-3-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:15:59","name":"[V2,02/15] gas: add new command line option --gsframe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-3-indu.bhagat@oracle.com/mbox/"},{"id":3761,"url":"https://patchwork.plctlab.org/api/1.2/patches/3761/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-4-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-4-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:00","name":"[V2,03/15] gas: generate .sframe from CFI directives","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-4-indu.bhagat@oracle.com/mbox/"},{"id":3760,"url":"https://patchwork.plctlab.org/api/1.2/patches/3760/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-5-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-5-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:01","name":"[V2,04/15] gas: testsuite: add new tests for SFrame unwind info","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-5-indu.bhagat@oracle.com/mbox/"},{"id":3764,"url":"https://patchwork.plctlab.org/api/1.2/patches/3764/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-6-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-6-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:02","name":"[V2,05/15] libsframe: add the SFrame library","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-6-indu.bhagat@oracle.com/mbox/"},{"id":3766,"url":"https://patchwork.plctlab.org/api/1.2/patches/3766/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-7-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-7-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:03","name":"[V2,06/15] bfd: linker: merge .sframe sections","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-7-indu.bhagat@oracle.com/mbox/"},{"id":3763,"url":"https://patchwork.plctlab.org/api/1.2/patches/3763/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-8-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-8-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:04","name":"[V2,07/15] readelf/objdump: support for SFrame section","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-8-indu.bhagat@oracle.com/mbox/"},{"id":3765,"url":"https://patchwork.plctlab.org/api/1.2/patches/3765/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-9-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-9-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:05","name":"[V2,08/15] unwinder: generate backtrace using SFrame format","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-9-indu.bhagat@oracle.com/mbox/"},{"id":3770,"url":"https://patchwork.plctlab.org/api/1.2/patches/3770/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-10-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-10-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:06","name":"[V2,09/15] unwinder: Add SFrame unwinder tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-10-indu.bhagat@oracle.com/mbox/"},{"id":3769,"url":"https://patchwork.plctlab.org/api/1.2/patches/3769/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-11-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-11-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:07","name":"[V2,10/15] gdb: sim: buildsystem changes to accommodate libsframe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-11-indu.bhagat@oracle.com/mbox/"},{"id":3771,"url":"https://patchwork.plctlab.org/api/1.2/patches/3771/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-12-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-12-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:08","name":"[V2,11/15] libctf: add libsframe to LDFLAGS and LIBS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-12-indu.bhagat@oracle.com/mbox/"},{"id":3768,"url":"https://patchwork.plctlab.org/api/1.2/patches/3768/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-13-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-13-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:09","name":"[V2,12/15] src-release.sh: Add libsframe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-13-indu.bhagat@oracle.com/mbox/"},{"id":3767,"url":"https://patchwork.plctlab.org/api/1.2/patches/3767/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-14-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-14-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:10","name":"[V2,13/15] binutils/NEWS: add text for SFrame support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-14-indu.bhagat@oracle.com/mbox/"},{"id":3772,"url":"https://patchwork.plctlab.org/api/1.2/patches/3772/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-15-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-15-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:11","name":"[V2,14/15] gas/NEWS: add text about new command line option and SFrame support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-15-indu.bhagat@oracle.com/mbox/"},{"id":3773,"url":"https://patchwork.plctlab.org/api/1.2/patches/3773/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-16-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-16-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:12","name":"[V2,15/15] doc: add SFrame spec file","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-16-indu.bhagat@oracle.com/mbox/"},{"id":3999,"url":"https://patchwork.plctlab.org/api/1.2/patches/3999/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221018081205.17880-1-krebbel@linux.ibm.com/","msgid":"<20221018081205.17880-1-krebbel@linux.ibm.com>","list_archive_url":null,"date":"2022-10-18T08:12:05","name":"[1/1] IBM zSystems: Issue error for *DBL relocs on misaligned symbols","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221018081205.17880-1-krebbel@linux.ibm.com/mbox/"},{"id":4141,"url":"https://patchwork.plctlab.org/api/1.2/patches/4141/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/baffaf673f17692b7bcbd604b31800b189988596.camel@espressif.com/","msgid":"","list_archive_url":null,"date":"2022-10-18T12:12:07","name":"xtensa: use definitions from xtensa-config.h","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/baffaf673f17692b7bcbd604b31800b189988596.camel@espressif.com/mbox/"},{"id":4272,"url":"https://patchwork.plctlab.org/api/1.2/patches/4272/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221018174914.470062-1-hjl.tools@gmail.com/","msgid":"<20221018174914.470062-1-hjl.tools@gmail.com>","list_archive_url":null,"date":"2022-10-18T17:49:14","name":"x86: Disable AVX-VNNI when disabling AVX2","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221018174914.470062-1-hjl.tools@gmail.com/mbox/"},{"id":4998,"url":"https://patchwork.plctlab.org/api/1.2/patches/4998/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c2f76e95-09f6-1d92-7ef4-38a3c2955fcd@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-19T09:52:46","name":"x86: re-work AVX-VNNI support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c2f76e95-09f6-1d92-7ef4-38a3c2955fcd@suse.com/mbox/"},{"id":5276,"url":"https://patchwork.plctlab.org/api/1.2/patches/5276/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0/lLtlKqqsmAx0s@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-19T11:53:18","name":"Fix addr2line test for ppc64 elfv1 and mingw","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0/lLtlKqqsmAx0s@squeak.grove.modra.org/mbox/"},{"id":5424,"url":"https://patchwork.plctlab.org/api/1.2/patches/5424/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/07bfebbf3843b47e13d82d4fa16eb14fec942ef7.1666184962.git.research_trasio@irq.a4lg.com/","msgid":"<07bfebbf3843b47e13d82d4fa16eb14fec942ef7.1666184962.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:09:54","name":"binutils: Remove unused substitution PROGRAM","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/07bfebbf3843b47e13d82d4fa16eb14fec942ef7.1666184962.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5433,"url":"https://patchwork.plctlab.org/api/1.2/patches/5433/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2fa7ff719223232402e82a9c91331aea22ace1bb.1666185116.git.research_trasio@irq.a4lg.com/","msgid":"<2fa7ff719223232402e82a9c91331aea22ace1bb.1666185116.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:11:55","name":"[v2,1/8] RISC-V: Add a space at the end of pinfo","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2fa7ff719223232402e82a9c91331aea22ace1bb.1666185116.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5435,"url":"https://patchwork.plctlab.org/api/1.2/patches/5435/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1b30cce5db2cce3b8edca42ab5da114d0b8c9e93.1666185116.git.research_trasio@irq.a4lg.com/","msgid":"<1b30cce5db2cce3b8edca42ab5da114d0b8c9e93.1666185116.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:11:56","name":"[v2,2/8] RISC-V: Fix obvious misalignments ('\''Zbb'\''/'\''Zba'\'')","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1b30cce5db2cce3b8edca42ab5da114d0b8c9e93.1666185116.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5437,"url":"https://patchwork.plctlab.org/api/1.2/patches/5437/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6b0857aa1a2d15ca1cf00b4dcaae0032efbb88ff.1666185116.git.research_trasio@irq.a4lg.com/","msgid":"<6b0857aa1a2d15ca1cf00b4dcaae0032efbb88ff.1666185116.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:11:57","name":"[v2,3/8] RISC-V: Remove spaces in opcode entries","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6b0857aa1a2d15ca1cf00b4dcaae0032efbb88ff.1666185116.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5436,"url":"https://patchwork.plctlab.org/api/1.2/patches/5436/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/889d956caac0f2e95543a14afaeed97188ce384c.1666185116.git.research_trasio@irq.a4lg.com/","msgid":"<889d956caac0f2e95543a14afaeed97188ce384c.1666185116.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:11:58","name":"[v2,4/8] RISC-V: Remove unused instruction macros","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/889d956caac0f2e95543a14afaeed97188ce384c.1666185116.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5440,"url":"https://patchwork.plctlab.org/api/1.2/patches/5440/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8f226ee20d8a5ef6ad7b6c4408b44794a99d542a.1666185116.git.research_trasio@irq.a4lg.com/","msgid":"<8f226ee20d8a5ef6ad7b6c4408b44794a99d542a.1666185116.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:11:59","name":"[v2,5/8] RISC-V: Complete tidying up with SCALL and SBREAK","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8f226ee20d8a5ef6ad7b6c4408b44794a99d542a.1666185116.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5442,"url":"https://patchwork.plctlab.org/api/1.2/patches/5442/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4070184c454a05a39adf0790951e5856e6b2ecb6.1666185116.git.research_trasio@irq.a4lg.com/","msgid":"<4070184c454a05a39adf0790951e5856e6b2ecb6.1666185116.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:12:00","name":"[v2,6/8] RISC-V: Tidying up with fmv.w.x and fmv.x.w","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4070184c454a05a39adf0790951e5856e6b2ecb6.1666185116.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5438,"url":"https://patchwork.plctlab.org/api/1.2/patches/5438/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c1ccda3e7c8fb297eda46dab3936d5c5977178fc.1666185116.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-19T13:12:01","name":"[v2,7/8] RISC-V: Make alias instructions aliases","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c1ccda3e7c8fb297eda46dab3936d5c5977178fc.1666185116.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5441,"url":"https://patchwork.plctlab.org/api/1.2/patches/5441/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/413cfca82c7e8d8a2e977dfda9135903c9cb7c57.1666185116.git.research_trasio@irq.a4lg.com/","msgid":"<413cfca82c7e8d8a2e977dfda9135903c9cb7c57.1666185116.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:12:02","name":"[v2,8/8] RISC-V: Use defined mask and match values","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/413cfca82c7e8d8a2e977dfda9135903c9cb7c57.1666185116.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5439,"url":"https://patchwork.plctlab.org/api/1.2/patches/5439/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/345c5c3b3a53eab04a1e6e91197de2642095c94f.1666185237.git.research_trasio@irq.a4lg.com/","msgid":"<345c5c3b3a53eab04a1e6e91197de2642095c94f.1666185237.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:14:01","name":"RISC-V: Remove RV32EF conflict","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/345c5c3b3a53eab04a1e6e91197de2642095c94f.1666185237.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5616,"url":"https://patchwork.plctlab.org/api/1.2/patches/5616/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019145608.45213-5-haochen.jiang@intel.com/","msgid":"<20221019145608.45213-5-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T14:56:02","name":"[04/10] Support Intel CMPccXADD","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019145608.45213-5-haochen.jiang@intel.com/mbox/"},{"id":5614,"url":"https://patchwork.plctlab.org/api/1.2/patches/5614/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019145608.45213-6-haochen.jiang@intel.com/","msgid":"<20221019145608.45213-6-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T14:56:03","name":"[05/10] Add handler for more i386_cpu_flags","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019145608.45213-6-haochen.jiang@intel.com/mbox/"},{"id":5672,"url":"https://patchwork.plctlab.org/api/1.2/patches/5672/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-2-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-2-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:25","name":"[01/10] Support Intel AVX-IFMA","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-2-haochen.jiang@intel.com/mbox/"},{"id":5691,"url":"https://patchwork.plctlab.org/api/1.2/patches/5691/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-3-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-3-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:26","name":"[02/10] Support Intel AVX-VNNI-INT8","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-3-haochen.jiang@intel.com/mbox/"},{"id":5690,"url":"https://patchwork.plctlab.org/api/1.2/patches/5690/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-4-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-4-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:27","name":"[03/10] Support Intel AVX-NE-CONVERT","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-4-haochen.jiang@intel.com/mbox/"},{"id":5689,"url":"https://patchwork.plctlab.org/api/1.2/patches/5689/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-5-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-5-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:28","name":"[04/10] Support Intel CMPccXADD","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-5-haochen.jiang@intel.com/mbox/"},{"id":5676,"url":"https://patchwork.plctlab.org/api/1.2/patches/5676/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-6-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-6-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:29","name":"[05/10] Add handler for more i386_cpu_flags","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-6-haochen.jiang@intel.com/mbox/"},{"id":5677,"url":"https://patchwork.plctlab.org/api/1.2/patches/5677/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-7-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-7-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:30","name":"[06/10] Support Intel RAO-INT","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-7-haochen.jiang@intel.com/mbox/"},{"id":5681,"url":"https://patchwork.plctlab.org/api/1.2/patches/5681/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-8-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-8-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:31","name":"[07/10] Support Intel WRMSRNS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-8-haochen.jiang@intel.com/mbox/"},{"id":5682,"url":"https://patchwork.plctlab.org/api/1.2/patches/5682/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-9-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-9-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:32","name":"[08/10] Support Intel MSRLIST","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-9-haochen.jiang@intel.com/mbox/"},{"id":5673,"url":"https://patchwork.plctlab.org/api/1.2/patches/5673/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-10-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-10-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:33","name":"[09/10] Support Intel AMX-FP16","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-10-haochen.jiang@intel.com/mbox/"},{"id":5686,"url":"https://patchwork.plctlab.org/api/1.2/patches/5686/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-11-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-11-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:34","name":"[10/10] Support Intel PREFETCHI","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-11-haochen.jiang@intel.com/mbox/"},{"id":5940,"url":"https://patchwork.plctlab.org/api/1.2/patches/5940/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1CMrFUC8d9lC/NL@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-19T23:47:56","name":"Obsolete beos","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1CMrFUC8d9lC/NL@squeak.grove.modra.org/mbox/"},{"id":6080,"url":"https://patchwork.plctlab.org/api/1.2/patches/6080/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8b99d666e78ba5b9d32c7889a2161c70b3da88df.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<8b99d666e78ba5b9d32c7889a2161c70b3da88df.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:25:47","name":"[01/40] gdb/unittests: PR28413, suppress warnings generated by Gnulib","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8b99d666e78ba5b9d32c7889a2161c70b3da88df.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6081,"url":"https://patchwork.plctlab.org/api/1.2/patches/6081/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b05adb17e401d621dbdad791281bc7af7806906e.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-20T09:25:48","name":"[02/40] sim: Check known getrusage declaration existence","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b05adb17e401d621dbdad791281bc7af7806906e.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6083,"url":"https://patchwork.plctlab.org/api/1.2/patches/6083/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/796962a87e569feeafb5ef636de3c79000ae152c.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<796962a87e569feeafb5ef636de3c79000ae152c.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:25:49","name":"[03/40] sim/aarch64: Remove unused functions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/796962a87e569feeafb5ef636de3c79000ae152c.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6084,"url":"https://patchwork.plctlab.org/api/1.2/patches/6084/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/65223c79fdfd7faf132275415cd9da9852c5bec3.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<65223c79fdfd7faf132275415cd9da9852c5bec3.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:25:50","name":"[04/40] cpu/cris: Initialize some variables on CRIS CPU","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/65223c79fdfd7faf132275415cd9da9852c5bec3.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6082,"url":"https://patchwork.plctlab.org/api/1.2/patches/6082/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/24baefe92148f4b7968115ba13de9b0c863a65f6.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<24baefe92148f4b7968115ba13de9b0c863a65f6.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:25:51","name":"[05/40] cpu/cris: Add u-stall virtual unit to CRIS v32","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/24baefe92148f4b7968115ba13de9b0c863a65f6.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6087,"url":"https://patchwork.plctlab.org/api/1.2/patches/6087/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3904a5c3e80f8548150d8088a92059dd728c7ff8.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<3904a5c3e80f8548150d8088a92059dd728c7ff8.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:25:52","name":"[06/40] sim/cris: Move declarations of f_specific_init","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3904a5c3e80f8548150d8088a92059dd728c7ff8.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6091,"url":"https://patchwork.plctlab.org/api/1.2/patches/6091/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/69ef2d7dd519ed572511890a215a0f6d74e53384.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<69ef2d7dd519ed572511890a215a0f6d74e53384.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:25:53","name":"[07/40] sim/cris: Regenerate with CGEN","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/69ef2d7dd519ed572511890a215a0f6d74e53384.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6085,"url":"https://patchwork.plctlab.org/api/1.2/patches/6085/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/26a3eaf4f5d2e0db6977738ddfd65d82b36e38b2.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<26a3eaf4f5d2e0db6977738ddfd65d82b36e38b2.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:25:54","name":"[08/40] sim/erc32: Insert void parameter","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/26a3eaf4f5d2e0db6977738ddfd65d82b36e38b2.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6086,"url":"https://patchwork.plctlab.org/api/1.2/patches/6086/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/057c2f8392410494c3bc5dc98052246508e6a73e.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<057c2f8392410494c3bc5dc98052246508e6a73e.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:25:55","name":"[09/40] sim/erc32: Use int32_t as event callback argument","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/057c2f8392410494c3bc5dc98052246508e6a73e.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6090,"url":"https://patchwork.plctlab.org/api/1.2/patches/6090/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8c05aec20557191434485be347d37177a2ec5ff2.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<8c05aec20557191434485be347d37177a2ec5ff2.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:25:56","name":"[10/40] sim/erc32: Use int32_t as IRQ callback argument","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8c05aec20557191434485be347d37177a2ec5ff2.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6089,"url":"https://patchwork.plctlab.org/api/1.2/patches/6089/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/afd7757aae21743c29f2aa4135a23b31d4959e9b.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-20T09:25:57","name":"[11/40] cpu/frv: Initialize some variables","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/afd7757aae21743c29f2aa4135a23b31d4959e9b.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6088,"url":"https://patchwork.plctlab.org/api/1.2/patches/6088/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/021dbd238af5dfe74523ed229d2156a155a6bb9e.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<021dbd238af5dfe74523ed229d2156a155a6bb9e.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:25:58","name":"[12/40] sim/frv: Initialize nesr variable","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/021dbd238af5dfe74523ed229d2156a155a6bb9e.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6093,"url":"https://patchwork.plctlab.org/api/1.2/patches/6093/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/51a03f7097921cc48954210cf99e370ae8982ec8.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<51a03f7097921cc48954210cf99e370ae8982ec8.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:25:59","name":"[13/40] sim/frv: Initialize some variables","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/51a03f7097921cc48954210cf99e370ae8982ec8.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6092,"url":"https://patchwork.plctlab.org/api/1.2/patches/6092/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e1baa1be3601612266dc6ae0bdde8426ff2a42c8.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-20T09:26:00","name":"[14/40] sim/frv: Add explicit casts","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e1baa1be3601612266dc6ae0bdde8426ff2a42c8.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6095,"url":"https://patchwork.plctlab.org/api/1.2/patches/6095/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5ab303a5bdfc1da7832f8fa22f57678c9ef1a5fa.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<5ab303a5bdfc1da7832f8fa22f57678c9ef1a5fa.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:26:01","name":"[15/40] sim/h8300: Add \"+ 0x0\" to avoid self-assignments","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5ab303a5bdfc1da7832f8fa22f57678c9ef1a5fa.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6101,"url":"https://patchwork.plctlab.org/api/1.2/patches/6101/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ddff80db3328a2286fe6fbc1240d2abc1e3813eb.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-20T09:26:02","name":"[16/40] sim/lm32: fix some missing function declaration warnings","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ddff80db3328a2286fe6fbc1240d2abc1e3813eb.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6094,"url":"https://patchwork.plctlab.org/api/1.2/patches/6094/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e094b1379231d9ffb59a78cfebbcc84634c779c6.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-20T09:26:03","name":"[17/40] sim/lm32: Add explicit casts","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e094b1379231d9ffb59a78cfebbcc84634c779c6.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6141,"url":"https://patchwork.plctlab.org/api/1.2/patches/6141/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/cabebead-489b-528c-580e-933832417474@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-20T10:25:51","name":"[1/3] x86: emit {evex} prefix when disassembling ambiguous AVX512VL insns","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/cabebead-489b-528c-580e-933832417474@suse.com/mbox/"},{"id":6143,"url":"https://patchwork.plctlab.org/api/1.2/patches/6143/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a032d61c-63a0-23d1-331f-619a2b8bbde3@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-20T10:26:15","name":"[2/3] x86: consolidate VAES tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a032d61c-63a0-23d1-331f-619a2b8bbde3@suse.com/mbox/"},{"id":6142,"url":"https://patchwork.plctlab.org/api/1.2/patches/6142/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7ff09c86-2de7-dc34-3183-5187de3df5ac@suse.com/","msgid":"<7ff09c86-2de7-dc34-3183-5187de3df5ac@suse.com>","list_archive_url":null,"date":"2022-10-20T10:26:40","name":"[3/3] x86: consolidate VPCLMUL tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7ff09c86-2de7-dc34-3183-5187de3df5ac@suse.com/mbox/"},{"id":6228,"url":"https://patchwork.plctlab.org/api/1.2/patches/6228/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.LSU.2.20.2210201432170.29399@wotan.suse.de/","msgid":"","list_archive_url":null,"date":"2022-10-20T14:42:25","name":"x86-64: Use only one default max-page-size","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.LSU.2.20.2210201432170.29399@wotan.suse.de/mbox/"},{"id":6229,"url":"https://patchwork.plctlab.org/api/1.2/patches/6229/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221020144351.1398099-1-chigot@adacore.com/","msgid":"<20221020144351.1398099-1-chigot@adacore.com>","list_archive_url":null,"date":"2022-10-20T14:43:50","name":"[1/2] ld/testsuite: skip ld-elf/exclude when -shared is not supported","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221020144351.1398099-1-chigot@adacore.com/mbox/"},{"id":6230,"url":"https://patchwork.plctlab.org/api/1.2/patches/6230/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221020144351.1398099-2-chigot@adacore.com/","msgid":"<20221020144351.1398099-2-chigot@adacore.com>","list_archive_url":null,"date":"2022-10-20T14:43:51","name":"[2/2] ld/testsuite: adjust ld-arm to run shared tests only when supported","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221020144351.1398099-2-chigot@adacore.com/mbox/"},{"id":6236,"url":"https://patchwork.plctlab.org/api/1.2/patches/6236/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221020151027.GA1300@delia.home/","msgid":"<20221020151027.GA1300@delia.home>","list_archive_url":null,"date":"2022-10-20T15:10:28","name":"[RFC,top-level] Add configure test-case","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221020151027.GA1300@delia.home/mbox/"},{"id":6286,"url":"https://patchwork.plctlab.org/api/1.2/patches/6286/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221020162911.1113338-1-hjl.tools@gmail.com/","msgid":"<20221020162911.1113338-1-hjl.tools@gmail.com>","list_archive_url":null,"date":"2022-10-20T16:29:11","name":"x86: Check VEX/EVEX encoding before checking vector operands","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221020162911.1113338-1-hjl.tools@gmail.com/mbox/"},{"id":7884,"url":"https://patchwork.plctlab.org/api/1.2/patches/7884/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7e53b7980f2b3b74d2250bc87f5db94b1d888a2d.camel@espressif.com/","msgid":"<7e53b7980f2b3b74d2250bc87f5db94b1d888a2d.camel@espressif.com>","list_archive_url":null,"date":"2022-10-22T12:53:54","name":"[1/5] bfd: xtensa: move common code from ld and gas","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7e53b7980f2b3b74d2250bc87f5db94b1d888a2d.camel@espressif.com/mbox/"},{"id":7885,"url":"https://patchwork.plctlab.org/api/1.2/patches/7885/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/63f2699e6ef3e6d1ca415a6ed1187d4f64297521.camel@espressif.com/","msgid":"<63f2699e6ef3e6d1ca415a6ed1187d4f64297521.camel@espressif.com>","list_archive_url":null,"date":"2022-10-22T12:55:16","name":"[2/5] gas: xtensa: add endianness, loops, booleans options","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/63f2699e6ef3e6d1ca415a6ed1187d4f64297521.camel@espressif.com/mbox/"},{"id":7886,"url":"https://patchwork.plctlab.org/api/1.2/patches/7886/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/34d2f747237aeeda595560cfded8096d9bd1c28c.camel@espressif.com/","msgid":"<34d2f747237aeeda595560cfded8096d9bd1c28c.camel@espressif.com>","list_archive_url":null,"date":"2022-10-22T12:56:02","name":"[3/5] ld: xtensa: use default LD command line options for endianness","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/34d2f747237aeeda595560cfded8096d9bd1c28c.camel@espressif.com/mbox/"},{"id":7891,"url":"https://patchwork.plctlab.org/api/1.2/patches/7891/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/535b6208c1718b9acf3258575e1ebc0a65af9f07.camel@espressif.com/","msgid":"<535b6208c1718b9acf3258575e1ebc0a65af9f07.camel@espressif.com>","list_archive_url":null,"date":"2022-10-22T13:56:44","name":"[5/5] gdb: xtensa: add support for esp32, esp32s2, esp32s3 isa-modules","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/535b6208c1718b9acf3258575e1ebc0a65af9f07.camel@espressif.com/mbox/"},{"id":10456,"url":"https://patchwork.plctlab.org/api/1.2/patches/10456/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221025013347.68282-1-nelson@rivosinc.com/","msgid":"<20221025013347.68282-1-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-10-25T01:33:46","name":"[committed,1/2] RISC-V: Improve link time complexity.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221025013347.68282-1-nelson@rivosinc.com/mbox/"},{"id":10454,"url":"https://patchwork.plctlab.org/api/1.2/patches/10454/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221025013347.68282-2-nelson@rivosinc.com/","msgid":"<20221025013347.68282-2-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-10-25T01:33:47","name":"[committed,2/2] RISC-V: Should reset `again'\'' flag for _bfd_riscv_relax_pc.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221025013347.68282-2-nelson@rivosinc.com/mbox/"},{"id":10536,"url":"https://patchwork.plctlab.org/api/1.2/patches/10536/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/bb7b87e4-1893-5c86-4a14-92bafc818b03@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-25T07:24:56","name":"[v5,1/8] x86: constify parse_insn()'\''s input","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/bb7b87e4-1893-5c86-4a14-92bafc818b03@suse.com/mbox/"},{"id":10537,"url":"https://patchwork.plctlab.org/api/1.2/patches/10537/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b9273ae6-0218-54f8-5374-b265ed13b71a@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-25T07:25:26","name":"[v5,1/8] x86: introduce Pass2 insn attribute","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b9273ae6-0218-54f8-5374-b265ed13b71a@suse.com/mbox/"},{"id":10541,"url":"https://patchwork.plctlab.org/api/1.2/patches/10541/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7250dab9-e218-e6dd-4c74-23da9f611ab4@suse.com/","msgid":"<7250dab9-e218-e6dd-4c74-23da9f611ab4@suse.com>","list_archive_url":null,"date":"2022-10-25T07:26:11","name":"[v5,3/8] x86: re-work insn/suffix recognition","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7250dab9-e218-e6dd-4c74-23da9f611ab4@suse.com/mbox/"},{"id":10540,"url":"https://patchwork.plctlab.org/api/1.2/patches/10540/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/13fc630f-e116-0099-5c9e-2697df6519d7@suse.com/","msgid":"<13fc630f-e116-0099-5c9e-2697df6519d7@suse.com>","list_archive_url":null,"date":"2022-10-25T07:26:40","name":"[v5,4/8] ix86: don'\''t recognize/derive Q suffix in the common case","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/13fc630f-e116-0099-5c9e-2697df6519d7@suse.com/mbox/"},{"id":10543,"url":"https://patchwork.plctlab.org/api/1.2/patches/10543/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/74db429d-d203-eab8-4ae1-18b9ad416b02@suse.com/","msgid":"<74db429d-d203-eab8-4ae1-18b9ad416b02@suse.com>","list_archive_url":null,"date":"2022-10-25T07:27:11","name":"[v5,5/8] x86-64: allow HLE store of accumulator to absolute 32-bit address","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/74db429d-d203-eab8-4ae1-18b9ad416b02@suse.com/mbox/"},{"id":10542,"url":"https://patchwork.plctlab.org/api/1.2/patches/10542/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2e2f7841-de4e-b5de-e8d9-a47a6a4113c8@suse.com/","msgid":"<2e2f7841-de4e-b5de-e8d9-a47a6a4113c8@suse.com>","list_archive_url":null,"date":"2022-10-25T07:27:35","name":"[v5,6/8] x86: move bad-use-of-TLS-reloc check","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2e2f7841-de4e-b5de-e8d9-a47a6a4113c8@suse.com/mbox/"},{"id":10545,"url":"https://patchwork.plctlab.org/api/1.2/patches/10545/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/421bc96e-7591-6980-48e9-5af8c8b0775a@suse.com/","msgid":"<421bc96e-7591-6980-48e9-5af8c8b0775a@suse.com>","list_archive_url":null,"date":"2022-10-25T07:28:27","name":"[v5,7/8] x86: drop (now) stray IsString","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/421bc96e-7591-6980-48e9-5af8c8b0775a@suse.com/mbox/"},{"id":10546,"url":"https://patchwork.plctlab.org/api/1.2/patches/10546/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/06ff83d4-4633-a07b-70e5-a8e049981dd4@suse.com/","msgid":"<06ff83d4-4633-a07b-70e5-a8e049981dd4@suse.com>","list_archive_url":null,"date":"2022-10-25T07:29:18","name":"[v5,8/8] x86: further re-work insn/suffix recognition to also cover MOVSX","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/06ff83d4-4633-a07b-70e5-a8e049981dd4@suse.com/mbox/"},{"id":10777,"url":"https://patchwork.plctlab.org/api/1.2/patches/10777/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6a8e7a71acccd0efb9789dfb3edfa307e83bdaa1.1666702934.git.research_trasio@irq.a4lg.com/","msgid":"<6a8e7a71acccd0efb9789dfb3edfa307e83bdaa1.1666702934.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-25T13:04:02","name":"[RFC] RISC-V: Allocate \"various\" operand type","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6a8e7a71acccd0efb9789dfb3edfa307e83bdaa1.1666702934.git.research_trasio@irq.a4lg.com/mbox/"},{"id":11062,"url":"https://patchwork.plctlab.org/api/1.2/patches/11062/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jAhwbXhxJHL66v@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-26T05:07:19","name":"PR29720, objdump -S crashes if build-id is missing","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jAhwbXhxJHL66v@squeak.grove.modra.org/mbox/"},{"id":11063,"url":"https://patchwork.plctlab.org/api/1.2/patches/11063/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jAxD+NxpMIah6s@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-26T05:08:20","name":"som.c buffer overflow","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jAxD+NxpMIah6s@squeak.grove.modra.org/mbox/"},{"id":11064,"url":"https://patchwork.plctlab.org/api/1.2/patches/11064/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jBYw4lfRQfOZhi@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-26T05:10:59","name":"som.c reloc sanity checking","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jBYw4lfRQfOZhi@squeak.grove.modra.org/mbox/"},{"id":11080,"url":"https://patchwork.plctlab.org/api/1.2/patches/11080/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jY7hygm01PelCY@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-26T06:51:26","name":"segfault in objdump.c reloc_at","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jY7hygm01PelCY@squeak.grove.modra.org/mbox/"},{"id":11081,"url":"https://patchwork.plctlab.org/api/1.2/patches/11081/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jZWIeIvCCYm9/g@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-26T06:53:12","name":"Correct ELF reloc size sanity check","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jZWIeIvCCYm9/g@squeak.grove.modra.org/mbox/"},{"id":11082,"url":"https://patchwork.plctlab.org/api/1.2/patches/11082/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221026070009.3663574-1-ysato@users.sourceforge.jp/","msgid":"<20221026070009.3663574-1-ysato@users.sourceforge.jp>","list_archive_url":null,"date":"2022-10-26T07:00:09","name":"opcodes: RX fix invalid output.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221026070009.3663574-1-ysato@users.sourceforge.jp/mbox/"},{"id":11089,"url":"https://patchwork.plctlab.org/api/1.2/patches/11089/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jhW48kuVC8Ig2d@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-26T07:27:23","name":"buffer overflow in _bfd_XX_print_ce_compressed_pdata","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jhW48kuVC8Ig2d@squeak.grove.modra.org/mbox/"},{"id":11157,"url":"https://patchwork.plctlab.org/api/1.2/patches/11157/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c52dbd16-7e1b-c356-7a92-1ff089564ef7@suse.cz/","msgid":"","list_archive_url":null,"date":"2022-10-26T08:47:09","name":"tests: use canonical option name","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c52dbd16-7e1b-c356-7a92-1ff089564ef7@suse.cz/mbox/"},{"id":11526,"url":"https://patchwork.plctlab.org/api/1.2/patches/11526/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027031915.4013-1-lifang_xia@linux.alibaba.com/","msgid":"<20221027031915.4013-1-lifang_xia@linux.alibaba.com>","list_archive_url":null,"date":"2022-10-27T03:19:15","name":"[v2] RISC-V: Optimize relax of GP/call with max_alignment.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027031915.4013-1-lifang_xia@linux.alibaba.com/mbox/"},{"id":11619,"url":"https://patchwork.plctlab.org/api/1.2/patches/11619/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9df9d9e5bb4c7594b76c40613a349b4d2364e9c5.1666854355.git.research_trasio@irq.a4lg.com/","msgid":"<9df9d9e5bb4c7594b76c40613a349b4d2364e9c5.1666854355.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-27T07:06:01","name":"include: Define macro to ignore -Wdeprecated-declarations on GCC","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9df9d9e5bb4c7594b76c40613a349b4d2364e9c5.1666854355.git.research_trasio@irq.a4lg.com/mbox/"},{"id":11627,"url":"https://patchwork.plctlab.org/api/1.2/patches/11627/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1o06O9Pp8ncCsOw@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-27T07:36:08","name":"Fuzzed files in archives","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1o06O9Pp8ncCsOw@squeak.grove.modra.org/mbox/"},{"id":11658,"url":"https://patchwork.plctlab.org/api/1.2/patches/11658/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027084808.37252-1-nelson@rivosinc.com/","msgid":"<20221027084808.37252-1-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-10-27T08:48:08","name":"[committed] RISC-V: Fix build failures for -Werror=sign-compare.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027084808.37252-1-nelson@rivosinc.com/mbox/"},{"id":11921,"url":"https://patchwork.plctlab.org/api/1.2/patches/11921/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027190052.10536-1-mark@harmstone.com/","msgid":"<20221027190052.10536-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-27T19:00:51","name":"[1/2] ld: Add section header stream to PDB files","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027190052.10536-1-mark@harmstone.com/mbox/"},{"id":11922,"url":"https://patchwork.plctlab.org/api/1.2/patches/11922/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027190052.10536-2-mark@harmstone.com/","msgid":"<20221027190052.10536-2-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-27T19:00:52","name":"[2/2] ld: Add publics stream to PDB files","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027190052.10536-2-mark@harmstone.com/mbox/"},{"id":11965,"url":"https://patchwork.plctlab.org/api/1.2/patches/11965/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027202719.32497-1-palmer@rivosinc.com/","msgid":"<20221027202719.32497-1-palmer@rivosinc.com>","list_archive_url":null,"date":"2022-10-27T20:27:18","name":"[1/2] gas: NEWS: Add a missing newline","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027202719.32497-1-palmer@rivosinc.com/mbox/"},{"id":11966,"url":"https://patchwork.plctlab.org/api/1.2/patches/11966/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027202719.32497-2-palmer@rivosinc.com/","msgid":"<20221027202719.32497-2-palmer@rivosinc.com>","list_archive_url":null,"date":"2022-10-27T20:27:19","name":"[2/2] gas: NEWS: Note support for RISC-V Zawrs","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027202719.32497-2-palmer@rivosinc.com/mbox/"},{"id":12016,"url":"https://patchwork.plctlab.org/api/1.2/patches/12016/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/21ec9a18-fa89-0828-f625-499680022ec7@linux.ibm.com/","msgid":"<21ec9a18-fa89-0828-f625-499680022ec7@linux.ibm.com>","list_archive_url":null,"date":"2022-10-28T00:35:19","name":"[COMMITTED] PowerPC: Add support for RFC02653 - Dense Math Facility","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/21ec9a18-fa89-0828-f625-499680022ec7@linux.ibm.com/mbox/"},{"id":12017,"url":"https://patchwork.plctlab.org/api/1.2/patches/12017/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fd94047d-a070-45a6-3840-c105391718e0@linux.ibm.com/","msgid":"","list_archive_url":null,"date":"2022-10-28T00:37:18","name":"[COMMITTED] PowerPC: Add support for RFC02658 - MMA+ Outer-Product, Instructions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fd94047d-a070-45a6-3840-c105391718e0@linux.ibm.com/mbox/"},{"id":12122,"url":"https://patchwork.plctlab.org/api/1.2/patches/12122/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ac4f3f3c7115a824f73aca6935789b14d33c9a58.1666939920.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-28T06:53:02","name":"RISC-V: Fix build failure for -Werror=maybe-uninitialized","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ac4f3f3c7115a824f73aca6935789b14d33c9a58.1666939920.git.research_trasio@irq.a4lg.com/mbox/"},{"id":12181,"url":"https://patchwork.plctlab.org/api/1.2/patches/12181/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221028093840.19164-1-nelson@rivosinc.com/","msgid":"<20221028093840.19164-1-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-10-28T09:38:40","name":"RISC-V: Added SiFive custom cache control extensions.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221028093840.19164-1-nelson@rivosinc.com/mbox/"},{"id":12211,"url":"https://patchwork.plctlab.org/api/1.2/patches/12211/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4a280588-a85b-6ed3-634b-2b9cbc128f86@suse.com/","msgid":"<4a280588-a85b-6ed3-634b-2b9cbc128f86@suse.com>","list_archive_url":null,"date":"2022-10-28T10:06:35","name":"RISC-V/gas: fix build with certain gcc versions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4a280588-a85b-6ed3-634b-2b9cbc128f86@suse.com/mbox/"},{"id":12249,"url":"https://patchwork.plctlab.org/api/1.2/patches/12249/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/eb0e1bff-675e-72db-b8b1-b0f0e50b7121@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-28T12:35:35","name":"x86: minor improvements to optimize_imm() (part III)","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/eb0e1bff-675e-72db-b8b1-b0f0e50b7121@suse.com/mbox/"},{"id":12382,"url":"https://patchwork.plctlab.org/api/1.2/patches/12382/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/17f57574936af82be381a1451eac56b3709b60bb.1666968673.git.research_trasio@irq.a4lg.com/","msgid":"<17f57574936af82be381a1451eac56b3709b60bb.1666968673.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-28T14:52:12","name":"RISC-V: Emit mapping symbol with ISA string if non-default arch is used","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/17f57574936af82be381a1451eac56b3709b60bb.1666968673.git.research_trasio@irq.a4lg.com/mbox/"},{"id":12627,"url":"https://patchwork.plctlab.org/api/1.2/patches/12627/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221029034432.49859-1-nelson@rivosinc.com/","msgid":"<20221029034432.49859-1-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-10-29T03:44:32","name":"[committed] RISC-V: Always generate mapping symbols at the start of the sections.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221029034432.49859-1-nelson@rivosinc.com/mbox/"},{"id":12629,"url":"https://patchwork.plctlab.org/api/1.2/patches/12629/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1yxgzNJg5M48uPI@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-29T04:52:19","name":"NULL dereference read in som_write_object_contents","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1yxgzNJg5M48uPI@squeak.grove.modra.org/mbox/"},{"id":12630,"url":"https://patchwork.plctlab.org/api/1.2/patches/12630/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1yxnSHLY+FeB5DQ@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-29T04:52:45","name":"Fix small objcopy memory leak","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1yxnSHLY+FeB5DQ@squeak.grove.modra.org/mbox/"},{"id":12631,"url":"https://patchwork.plctlab.org/api/1.2/patches/12631/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1yxxfpJz+Jx4KTh@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-29T04:53:25","name":"pef: sanity check before malloc","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1yxxfpJz+Jx4KTh@squeak.grove.modra.org/mbox/"},{"id":12950,"url":"https://patchwork.plctlab.org/api/1.2/patches/12950/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-2-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-2-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:36","name":"[V3,01/15] sframe.h: Add SFrame format definition","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-2-indu.bhagat@oracle.com/mbox/"},{"id":12952,"url":"https://patchwork.plctlab.org/api/1.2/patches/12952/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-3-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-3-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:37","name":"[V3,02/15] gas: add new command line option --gsframe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-3-indu.bhagat@oracle.com/mbox/"},{"id":12951,"url":"https://patchwork.plctlab.org/api/1.2/patches/12951/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-4-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-4-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:38","name":"[V3,03/15] gas: generate .sframe from CFI directives","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-4-indu.bhagat@oracle.com/mbox/"},{"id":12956,"url":"https://patchwork.plctlab.org/api/1.2/patches/12956/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-5-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-5-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:39","name":"[V3,04/15] gas: testsuite: add new tests for SFrame unwind info","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-5-indu.bhagat@oracle.com/mbox/"},{"id":12955,"url":"https://patchwork.plctlab.org/api/1.2/patches/12955/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-6-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-6-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:40","name":"[V3,05/15] libsframe: add the SFrame library","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-6-indu.bhagat@oracle.com/mbox/"},{"id":12959,"url":"https://patchwork.plctlab.org/api/1.2/patches/12959/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-7-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-7-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:41","name":"[V3,06/15] bfd: linker: merge .sframe sections","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-7-indu.bhagat@oracle.com/mbox/"},{"id":12961,"url":"https://patchwork.plctlab.org/api/1.2/patches/12961/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-8-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-8-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:42","name":"[V3,07/15] readelf/objdump: support for SFrame section","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-8-indu.bhagat@oracle.com/mbox/"},{"id":12962,"url":"https://patchwork.plctlab.org/api/1.2/patches/12962/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-9-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-9-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:43","name":"[V3,08/15] unwinder: generate backtrace using SFrame format","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-9-indu.bhagat@oracle.com/mbox/"},{"id":12963,"url":"https://patchwork.plctlab.org/api/1.2/patches/12963/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-10-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-10-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:44","name":"[V3,09/15] unwinder: Add SFrame unwinder tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-10-indu.bhagat@oracle.com/mbox/"},{"id":12964,"url":"https://patchwork.plctlab.org/api/1.2/patches/12964/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-11-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-11-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:45","name":"[V3,10/15] gdb: sim: buildsystem changes to accommodate libsframe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-11-indu.bhagat@oracle.com/mbox/"},{"id":12957,"url":"https://patchwork.plctlab.org/api/1.2/patches/12957/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-12-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-12-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:46","name":"[V3,11/15] libctf: add libsframe to LDFLAGS and LIBS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-12-indu.bhagat@oracle.com/mbox/"},{"id":12960,"url":"https://patchwork.plctlab.org/api/1.2/patches/12960/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-13-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-13-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:47","name":"[V3,12/15] src-release.sh: Add libsframe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-13-indu.bhagat@oracle.com/mbox/"},{"id":12953,"url":"https://patchwork.plctlab.org/api/1.2/patches/12953/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-14-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-14-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:48","name":"[V3,13/15] binutils/NEWS: add text for SFrame support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-14-indu.bhagat@oracle.com/mbox/"},{"id":12954,"url":"https://patchwork.plctlab.org/api/1.2/patches/12954/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-15-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-15-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:49","name":"[V3,14/15] gas/NEWS: add text about new command line option and SFrame support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-15-indu.bhagat@oracle.com/mbox/"},{"id":12958,"url":"https://patchwork.plctlab.org/api/1.2/patches/12958/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-16-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-16-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:50","name":"[V3,15/15] doc: add SFrame spec file","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-16-indu.bhagat@oracle.com/mbox/"},{"id":12988,"url":"https://patchwork.plctlab.org/api/1.2/patches/12988/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y15KFY32CyFhh/+u@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-30T09:55:33","name":"Pool section entries for DWP version 1","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y15KFY32CyFhh/+u@squeak.grove.modra.org/mbox/"},{"id":13076,"url":"https://patchwork.plctlab.org/api/1.2/patches/13076/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031001554.14615-1-mark@harmstone.com/","msgid":"<20221031001554.14615-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-31T00:15:52","name":"[v2,1/3] ld: Use %E in einfo in pdb.c","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031001554.14615-1-mark@harmstone.com/mbox/"},{"id":13078,"url":"https://patchwork.plctlab.org/api/1.2/patches/13078/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031001554.14615-2-mark@harmstone.com/","msgid":"<20221031001554.14615-2-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-31T00:15:53","name":"[v2,2/3] ld: Add section header stream to PDB files","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031001554.14615-2-mark@harmstone.com/mbox/"},{"id":13077,"url":"https://patchwork.plctlab.org/api/1.2/patches/13077/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031001554.14615-3-mark@harmstone.com/","msgid":"<20221031001554.14615-3-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-31T00:15:54","name":"[v2,3/3] ld: Add publics stream to PDB files","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031001554.14615-3-mark@harmstone.com/mbox/"},{"id":13106,"url":"https://patchwork.plctlab.org/api/1.2/patches/13106/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031030507.35588-2-haochen.jiang@intel.com/","msgid":"<20221031030507.35588-2-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-31T03:05:02","name":"[1/6] Support Intel AVX-IFMA","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031030507.35588-2-haochen.jiang@intel.com/mbox/"},{"id":13105,"url":"https://patchwork.plctlab.org/api/1.2/patches/13105/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031030507.35588-3-haochen.jiang@intel.com/","msgid":"<20221031030507.35588-3-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-31T03:05:03","name":"[2/6] Support Intel AVX-VNNI-INT8","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031030507.35588-3-haochen.jiang@intel.com/mbox/"},{"id":13103,"url":"https://patchwork.plctlab.org/api/1.2/patches/13103/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031030507.35588-4-haochen.jiang@intel.com/","msgid":"<20221031030507.35588-4-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-31T03:05:04","name":"[3/6] Support Intel CMPccXADD","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031030507.35588-4-haochen.jiang@intel.com/mbox/"},{"id":13101,"url":"https://patchwork.plctlab.org/api/1.2/patches/13101/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031030507.35588-5-haochen.jiang@intel.com/","msgid":"<20221031030507.35588-5-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-31T03:05:05","name":"[4/6] Add handler for more i386_cpu_flags","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031030507.35588-5-haochen.jiang@intel.com/mbox/"},{"id":13104,"url":"https://patchwork.plctlab.org/api/1.2/patches/13104/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031030507.35588-6-haochen.jiang@intel.com/","msgid":"<20221031030507.35588-6-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-31T03:05:06","name":"[5/6] Support Intel WRMSRNS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031030507.35588-6-haochen.jiang@intel.com/mbox/"},{"id":13102,"url":"https://patchwork.plctlab.org/api/1.2/patches/13102/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031030507.35588-7-haochen.jiang@intel.com/","msgid":"<20221031030507.35588-7-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-31T03:05:07","name":"[6/6] Support Intel MSRLIST","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031030507.35588-7-haochen.jiang@intel.com/mbox/"},{"id":13120,"url":"https://patchwork.plctlab.org/api/1.2/patches/13120/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031060601.38460-2-haochen.jiang@intel.com/","msgid":"<20221031060601.38460-2-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-31T06:06:00","name":"[1/2] i386: Add and ","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031060601.38460-2-haochen.jiang@intel.com/mbox/"},{"id":13121,"url":"https://patchwork.plctlab.org/api/1.2/patches/13121/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031060601.38460-3-haochen.jiang@intel.com/","msgid":"<20221031060601.38460-3-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-31T06:06:01","name":"[2/2] Support Intel AVX-NE-CONVERT","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031060601.38460-3-haochen.jiang@intel.com/mbox/"},{"id":13188,"url":"https://patchwork.plctlab.org/api/1.2/patches/13188/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9f6f8888-4dc1-a6b0-0590-35fc8a276369@suse.com/","msgid":"<9f6f8888-4dc1-a6b0-0590-35fc8a276369@suse.com>","list_archive_url":null,"date":"2022-10-31T10:18:20","name":"x86: drop bogus Tbyte","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9f6f8888-4dc1-a6b0-0590-35fc8a276369@suse.com/mbox/"},{"id":13213,"url":"https://patchwork.plctlab.org/api/1.2/patches/13213/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4f1aac95-fea5-2279-cb18-dfcdb51a2589@arm.com/","msgid":"<4f1aac95-fea5-2279-cb18-dfcdb51a2589@arm.com>","list_archive_url":null,"date":"2022-10-31T11:14:44","name":"aarch64: Add support for Common Short Sequence Compression extension","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4f1aac95-fea5-2279-cb18-dfcdb51a2589@arm.com/mbox/"}],"public":true,"mbox":"https://patchwork.plctlab.org/bundle/patchwork-bot/binutils-gdb_2022-10/mbox/"},{"id":7,"url":"https://patchwork.plctlab.org/api/1.2/bundles/7/","web_url":"https://patchwork.plctlab.org/bundle/patchwork-bot/binutils-gdb_2022-09/","project":{"id":2,"url":"https://patchwork.plctlab.org/api/1.2/projects/2/","name":"binutils-gdb","link_name":"binutils-gdb","list_id":"binutils.sourceware.org","list_email":"binutils@sourceware.org","web_url":"https://github.com/wangliu-iscas/Patchwork-Bundles/blob/main/binutils-gdb.md","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"name":"binutils-gdb_2022-09","owner":{"id":3,"url":"https://patchwork.plctlab.org/api/1.2/users/3/","username":"patchwork-bot","first_name":"","last_name":"","email":"ouuuleilei@gmail.com"},"patches":[{"id":1573,"url":"https://patchwork.plctlab.org/api/1.2/patches/1573/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930073211.2634-1-jiawei@iscas.ac.cn/","msgid":"<20220930073211.2634-1-jiawei@iscas.ac.cn>","list_archive_url":null,"date":"2022-09-30T07:32:11","name":"[V2] RISC-V: Add Smepmp CSR '\''mseccfg'\'' define and testcases.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930073211.2634-1-jiawei@iscas.ac.cn/mbox/"},{"id":1577,"url":"https://patchwork.plctlab.org/api/1.2/patches/1577/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/76fa0c3c-2303-ebdf-a765-ac4731581517@suse.com/","msgid":"<76fa0c3c-2303-ebdf-a765-ac4731581517@suse.com>","list_archive_url":null,"date":"2022-09-30T08:54:18","name":"objcopy: avoid \"shadowing\" of remove() function name","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/76fa0c3c-2303-ebdf-a765-ac4731581517@suse.com/mbox/"},{"id":1579,"url":"https://patchwork.plctlab.org/api/1.2/patches/1579/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930085852.71213-1-nelson@rivosinc.com/","msgid":"<20220930085852.71213-1-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-09-30T08:58:51","name":"[1/2] RISC-V: Output mapping symbols with ISA string.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930085852.71213-1-nelson@rivosinc.com/mbox/"},{"id":1578,"url":"https://patchwork.plctlab.org/api/1.2/patches/1578/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930085852.71213-2-nelson@rivosinc.com/","msgid":"<20220930085852.71213-2-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-09-30T08:58:52","name":"[2/2] RISC-V: Refer mapping symbol to R_RISCV_RELAX for rvc relaxations.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930085852.71213-2-nelson@rivosinc.com/mbox/"},{"id":1581,"url":"https://patchwork.plctlab.org/api/1.2/patches/1581/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930092058.71286-1-nelson@rivosinc.com/","msgid":"<20220930092058.71286-1-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-09-30T09:20:57","name":"[1/2] RISC-V: Output mapping symbols with ISA string.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930092058.71286-1-nelson@rivosinc.com/mbox/"},{"id":1580,"url":"https://patchwork.plctlab.org/api/1.2/patches/1580/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930092058.71286-2-nelson@rivosinc.com/","msgid":"<20220930092058.71286-2-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-09-30T09:20:58","name":"[2/2] RISC-V: Refer mapping symbol to R_RISCV_RELAX for rvc relaxations.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930092058.71286-2-nelson@rivosinc.com/mbox/"},{"id":1582,"url":"https://patchwork.plctlab.org/api/1.2/patches/1582/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5874dd79-0cf5-d65c-7ea2-13adfc799c0f@suse.com/","msgid":"<5874dd79-0cf5-d65c-7ea2-13adfc799c0f@suse.com>","list_archive_url":null,"date":"2022-09-30T09:41:29","name":"RISC-V: fix build after \"Add support for arbitrary immediate encoding formats\"","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5874dd79-0cf5-d65c-7ea2-13adfc799c0f@suse.com/mbox/"},{"id":1583,"url":"https://patchwork.plctlab.org/api/1.2/patches/1583/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/57d8ac2a-5757-3776-9924-99c17ca69938@suse.com/","msgid":"<57d8ac2a-5757-3776-9924-99c17ca69938@suse.com>","list_archive_url":null,"date":"2022-09-30T09:42:08","name":"RISC-V: fallout from \"re-arrange opcode table for consistent alias handling\"","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/57d8ac2a-5757-3776-9924-99c17ca69938@suse.com/mbox/"},{"id":1584,"url":"https://patchwork.plctlab.org/api/1.2/patches/1584/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e76ef8f7-72b9-5103-cb43-9608af01d017@suse.com/","msgid":"","list_archive_url":null,"date":"2022-09-30T09:42:50","name":"RISC-V: don'\''t cast expressions'\'' X_add_number to long in diagnostics","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e76ef8f7-72b9-5103-cb43-9608af01d017@suse.com/mbox/"},{"id":1585,"url":"https://patchwork.plctlab.org/api/1.2/patches/1585/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/61355429-24b3-17d0-ab03-6fa57ee861d5@suse.cz/","msgid":"<61355429-24b3-17d0-ab03-6fa57ee861d5@suse.cz>","list_archive_url":null,"date":"2022-09-30T09:48:52","name":"[RFC] add --enable-zstd-compressed-debug-sections configure option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/61355429-24b3-17d0-ab03-6fa57ee861d5@suse.cz/mbox/"},{"id":1586,"url":"https://patchwork.plctlab.org/api/1.2/patches/1586/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930103919.323690-1-christoph.muellner@vrull.eu/","msgid":"<20220930103919.323690-1-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2022-09-30T10:39:19","name":"RISC-V: Eliminate long-casts of X_add_number in diagnostics","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930103919.323690-1-christoph.muellner@vrull.eu/mbox/"},{"id":1590,"url":"https://patchwork.plctlab.org/api/1.2/patches/1590/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/DM6PR12MB4219C943049C6D883DEA3E55E7569@DM6PR12MB4219.namprd12.prod.outlook.com/","msgid":"","list_archive_url":null,"date":"2022-09-30T11:41:37","name":"[V2] Ignore DWARF debug information for -gsplit-dwarf with dwarf-5.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/DM6PR12MB4219C943049C6D883DEA3E55E7569@DM6PR12MB4219.namprd12.prod.outlook.com/mbox/"},{"id":1591,"url":"https://patchwork.plctlab.org/api/1.2/patches/1591/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c10321f9-d289-ef84-d263-bc278fb3d31b@suse.com/","msgid":"","list_archive_url":null,"date":"2022-09-30T11:59:04","name":"[1/4] RISC-V/gas: drop riscv_subsets static variable","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c10321f9-d289-ef84-d263-bc278fb3d31b@suse.com/mbox/"},{"id":1593,"url":"https://patchwork.plctlab.org/api/1.2/patches/1593/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3244eea0-c18c-e49a-4588-d69423130226@suse.com/","msgid":"<3244eea0-c18c-e49a-4588-d69423130226@suse.com>","list_archive_url":null,"date":"2022-09-30T11:59:23","name":"[2/4] RISC-V/gas: drop stray call to install_insn()","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3244eea0-c18c-e49a-4588-d69423130226@suse.com/mbox/"},{"id":1592,"url":"https://patchwork.plctlab.org/api/1.2/patches/1592/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/385d01fd-7e57-1f3f-1bae-30aa0c313d63@suse.com/","msgid":"<385d01fd-7e57-1f3f-1bae-30aa0c313d63@suse.com>","list_archive_url":null,"date":"2022-09-30T11:59:45","name":"[3/4] RISC-V/gas: don'\''t open-code insn_length()","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/385d01fd-7e57-1f3f-1bae-30aa0c313d63@suse.com/mbox/"},{"id":1594,"url":"https://patchwork.plctlab.org/api/1.2/patches/1594/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f5757acf-7b90-a0e3-5eea-3b97cc226930@suse.com/","msgid":"","list_archive_url":null,"date":"2022-09-30T12:00:12","name":"[4/4] RISC-V/gas: allow generating up to 176-bit instructions with .insn","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f5757acf-7b90-a0e3-5eea-3b97cc226930@suse.com/mbox/"},{"id":1596,"url":"https://patchwork.plctlab.org/api/1.2/patches/1596/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930140503.38233-1-chigot@adacore.com/","msgid":"<20220930140503.38233-1-chigot@adacore.com>","list_archive_url":null,"date":"2022-09-30T14:05:03","name":"ld/testsuite: consistently add board_ldflags when linking with GCC","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930140503.38233-1-chigot@adacore.com/mbox/"}],"public":true,"mbox":"https://patchwork.plctlab.org/bundle/patchwork-bot/binutils-gdb_2022-09/mbox/"},{"id":9,"url":"https://patchwork.plctlab.org/api/1.2/bundles/9/","web_url":"https://patchwork.plctlab.org/bundle/patchwork-bot/binutils-gdb_2022-11/","project":{"id":2,"url":"https://patchwork.plctlab.org/api/1.2/projects/2/","name":"binutils-gdb","link_name":"binutils-gdb","list_id":"binutils.sourceware.org","list_email":"binutils@sourceware.org","web_url":"https://github.com/wangliu-iscas/Patchwork-Bundles/blob/main/binutils-gdb.md","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"name":"binutils-gdb_2022-11","owner":{"id":3,"url":"https://patchwork.plctlab.org/api/1.2/users/3/","username":"patchwork-bot","first_name":"","last_name":"","email":"ouuuleilei@gmail.com"},"patches":[{"id":13337,"url":"https://patchwork.plctlab.org/api/1.2/patches/13337/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031160625.684434-1-hjl.tools@gmail.com/","msgid":"<20221031160625.684434-1-hjl.tools@gmail.com>","list_archive_url":null,"date":"2022-10-31T16:06:25","name":"x86: Silence GCC 12 warning on tc-i386.c","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031160625.684434-1-hjl.tools@gmail.com/mbox/"},{"id":13350,"url":"https://patchwork.plctlab.org/api/1.2/patches/13350/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c8d25b29-37fe-9623-a799-e67e1f991743@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-31T17:00:56","name":"x86: simplify expressions in update_imm()","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c8d25b29-37fe-9623-a799-e67e1f991743@suse.com/mbox/"},{"id":13487,"url":"https://patchwork.plctlab.org/api/1.2/patches/13487/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/CAMe9rOohVjin92PTeeiu_dvAtzYJn4dGtu5E=OxYfbyteraZWw@mail.gmail.com/","msgid":"","list_archive_url":null,"date":"2022-11-01T00:08:04","name":"binutils: Run PR binutils/26160 test","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/CAMe9rOohVjin92PTeeiu_dvAtzYJn4dGtu5E=OxYfbyteraZWw@mail.gmail.com/mbox/"},{"id":13621,"url":"https://patchwork.plctlab.org/api/1.2/patches/13621/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221101105724.1527333-1-aburgess@redhat.com/","msgid":"<20221101105724.1527333-1-aburgess@redhat.com>","list_archive_url":null,"date":"2022-11-01T10:57:24","name":"[PUSHED] opcodes/arm: silence compiler warning about uninitialized variable use","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221101105724.1527333-1-aburgess@redhat.com/mbox/"},{"id":13628,"url":"https://patchwork.plctlab.org/api/1.2/patches/13628/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221101111802.1532080-1-aburgess@redhat.com/","msgid":"<20221101111802.1532080-1-aburgess@redhat.com>","list_archive_url":null,"date":"2022-11-01T11:18:02","name":"[PUSHED] opcodes/arm: don'\''t pass non-string literal to printf like function","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221101111802.1532080-1-aburgess@redhat.com/mbox/"},{"id":13747,"url":"https://patchwork.plctlab.org/api/1.2/patches/13747/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/yw8jbkpqk6vw.fsf@arm.com/","msgid":"","list_archive_url":null,"date":"2022-11-01T15:54:11","name":"[Binutils-2.39,backport,GAS] arm: Use DWARF numbering convention for pseudo-register representation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/yw8jbkpqk6vw.fsf@arm.com/mbox/"},{"id":13993,"url":"https://patchwork.plctlab.org/api/1.2/patches/13993/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221102020752.24441-1-mark@harmstone.com/","msgid":"<20221102020752.24441-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-11-02T02:07:52","name":"ld: Add module information substream to PDB files","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221102020752.24441-1-mark@harmstone.com/mbox/"},{"id":14028,"url":"https://patchwork.plctlab.org/api/1.2/patches/14028/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221102050430.1053-1-nelson@rivosinc.com/","msgid":"<20221102050430.1053-1-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-11-02T05:04:30","name":"[committed] RISC-V: Fixed the missing $x+arch when adding odd paddings for alignment.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221102050430.1053-1-nelson@rivosinc.com/mbox/"},{"id":14043,"url":"https://patchwork.plctlab.org/api/1.2/patches/14043/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221102063046.31551-1-rjiejie@linux.alibaba.com/","msgid":"<20221102063046.31551-1-rjiejie@linux.alibaba.com>","list_archive_url":null,"date":"2022-11-02T06:30:46","name":"gas/doc/internals.texi: fix typo","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221102063046.31551-1-rjiejie@linux.alibaba.com/mbox/"},{"id":14069,"url":"https://patchwork.plctlab.org/api/1.2/patches/14069/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221102080112.33378-1-rjiejie@linux.alibaba.com/","msgid":"<20221102080112.33378-1-rjiejie@linux.alibaba.com>","list_archive_url":null,"date":"2022-11-02T08:01:12","name":"[v2] Support multiple .eh_frame sections","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221102080112.33378-1-rjiejie@linux.alibaba.com/mbox/"},{"id":14409,"url":"https://patchwork.plctlab.org/api/1.2/patches/14409/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221102172923.4009281-1-christophe.lyon@arm.com/","msgid":"<20221102172923.4009281-1-christophe.lyon@arm.com>","list_archive_url":null,"date":"2022-11-02T17:29:23","name":"arm: PR 29739 Fix typo where '\''; '\'' should not have been replaced with '\''@'\''","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221102172923.4009281-1-christophe.lyon@arm.com/mbox/"},{"id":14588,"url":"https://patchwork.plctlab.org/api/1.2/patches/14588/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221103020409.37322-1-rjiejie@linux.alibaba.com/","msgid":"<20221103020409.37322-1-rjiejie@linux.alibaba.com>","list_archive_url":null,"date":"2022-11-03T02:04:09","name":"[v3] Support multiple .eh_frame sections","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221103020409.37322-1-rjiejie@linux.alibaba.com/mbox/"},{"id":14602,"url":"https://patchwork.plctlab.org/api/1.2/patches/14602/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221103024604.614-1-mark@harmstone.com/","msgid":"<20221103024604.614-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-11-03T02:46:04","name":"[v2] ld: Add module information substream to PDB files","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221103024604.614-1-mark@harmstone.com/mbox/"},{"id":14706,"url":"https://patchwork.plctlab.org/api/1.2/patches/14706/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221103071519.3510462-1-luis.machado@arm.com/","msgid":"<20221103071519.3510462-1-luis.machado@arm.com>","list_archive_url":null,"date":"2022-11-03T07:15:19","name":"[opcodes/arm] Fix potential null pointer dereferences","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221103071519.3510462-1-luis.machado@arm.com/mbox/"},{"id":14840,"url":"https://patchwork.plctlab.org/api/1.2/patches/14840/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/283a86ebf0941f0f63dc1a590ec3d547bd5d69e8.1667478033.git.research_trasio@irq.a4lg.com/","msgid":"<283a86ebf0941f0f63dc1a590ec3d547bd5d69e8.1667478033.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-03T12:26:28","name":"[REVIEW,ONLY,1/2] NEAR-RATIFICATION RISC-V: Add '\''Ssstateen'\'' extension and its CSRs","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/283a86ebf0941f0f63dc1a590ec3d547bd5d69e8.1667478033.git.research_trasio@irq.a4lg.com/mbox/"},{"id":14841,"url":"https://patchwork.plctlab.org/api/1.2/patches/14841/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8083ad9d5339afdeb7f1ba88ee6af0665dcc76d5.1667478033.git.research_trasio@irq.a4lg.com/","msgid":"<8083ad9d5339afdeb7f1ba88ee6af0665dcc76d5.1667478033.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-03T12:26:29","name":"[REVIEW,ONLY,2/2] NEAR-RATIFICATION RISC-V: Add platform property/capability extensions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8083ad9d5339afdeb7f1ba88ee6af0665dcc76d5.1667478033.git.research_trasio@irq.a4lg.com/mbox/"},{"id":14894,"url":"https://patchwork.plctlab.org/api/1.2/patches/14894/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e53fbf5025e59fe6a3481b9c1fe37e4f6cf6e03d.1667483581.git.aburgess@redhat.com/","msgid":"","list_archive_url":null,"date":"2022-11-03T13:58:12","name":"[1/2] opcodes/mips: use .word/.short for undefined instructions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e53fbf5025e59fe6a3481b9c1fe37e4f6cf6e03d.1667483581.git.aburgess@redhat.com/mbox/"},{"id":14893,"url":"https://patchwork.plctlab.org/api/1.2/patches/14893/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ca81edb86580566b1641ad140eb2bed385160ab7.1667483581.git.aburgess@redhat.com/","msgid":"","list_archive_url":null,"date":"2022-11-03T13:58:13","name":"[2/2] libopcodes/mips: add support for disassembler styling","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ca81edb86580566b1641ad140eb2bed385160ab7.1667483581.git.aburgess@redhat.com/mbox/"},{"id":15465,"url":"https://patchwork.plctlab.org/api/1.2/patches/15465/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/926e5154-b40b-9df8-d770-a8bf7d40e40e@suse.com/","msgid":"<926e5154-b40b-9df8-d770-a8bf7d40e40e@suse.com>","list_archive_url":null,"date":"2022-11-04T10:50:38","name":"[v6,1/7] x86: constify parse_insn()'\''s input","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/926e5154-b40b-9df8-d770-a8bf7d40e40e@suse.com/mbox/"},{"id":15466,"url":"https://patchwork.plctlab.org/api/1.2/patches/15466/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/07ef67fd-752c-ad1f-b8cb-4eaec1f420fc@suse.com/","msgid":"<07ef67fd-752c-ad1f-b8cb-4eaec1f420fc@suse.com>","list_archive_url":null,"date":"2022-11-04T10:51:34","name":"[v6,2/7] x86: re-work insn/suffix recognition","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/07ef67fd-752c-ad1f-b8cb-4eaec1f420fc@suse.com/mbox/"},{"id":15467,"url":"https://patchwork.plctlab.org/api/1.2/patches/15467/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ee8fd655-19a5-d944-0f5e-4351b88a59f9@suse.com/","msgid":"","list_archive_url":null,"date":"2022-11-04T10:52:02","name":"[v6,3/7] ix86: don'\''t recognize/derive Q suffix in the common case","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ee8fd655-19a5-d944-0f5e-4351b88a59f9@suse.com/mbox/"},{"id":15468,"url":"https://patchwork.plctlab.org/api/1.2/patches/15468/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/15ab2cf5-f1ac-e882-c415-6318f1bcc7f0@suse.com/","msgid":"<15ab2cf5-f1ac-e882-c415-6318f1bcc7f0@suse.com>","list_archive_url":null,"date":"2022-11-04T10:52:31","name":"[v6,4/7] x86-64: allow HLE store of accumulator to absolute 32-bit address","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/15ab2cf5-f1ac-e882-c415-6318f1bcc7f0@suse.com/mbox/"},{"id":15470,"url":"https://patchwork.plctlab.org/api/1.2/patches/15470/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/352d1e49-ac9f-ee86-7e9d-74f79744268b@suse.com/","msgid":"<352d1e49-ac9f-ee86-7e9d-74f79744268b@suse.com>","list_archive_url":null,"date":"2022-11-04T10:53:14","name":"[v6,5/7] x86: move bad-use-of-TLS-reloc check","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/352d1e49-ac9f-ee86-7e9d-74f79744268b@suse.com/mbox/"},{"id":15469,"url":"https://patchwork.plctlab.org/api/1.2/patches/15469/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c1913bf6-7328-e45f-69f1-20da1954af43@suse.com/","msgid":"","list_archive_url":null,"date":"2022-11-04T10:53:52","name":"[v6,6/7] x86: drop (now) stray IsString","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c1913bf6-7328-e45f-69f1-20da1954af43@suse.com/mbox/"},{"id":15471,"url":"https://patchwork.plctlab.org/api/1.2/patches/15471/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2baf6a9d-c1bf-660d-bbca-99b1604f5478@suse.com/","msgid":"<2baf6a9d-c1bf-660d-bbca-99b1604f5478@suse.com>","list_archive_url":null,"date":"2022-11-04T10:54:30","name":"[v6,7/7] x86: further re-work insn/suffix recognition to also cover MOVSX","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2baf6a9d-c1bf-660d-bbca-99b1604f5478@suse.com/mbox/"},{"id":15472,"url":"https://patchwork.plctlab.org/api/1.2/patches/15472/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104110132.694984-1-aburgess@redhat.com/","msgid":"<20221104110132.694984-1-aburgess@redhat.com>","list_archive_url":null,"date":"2022-11-04T11:01:32","name":"[PUSHED] opcodes/arm: silence compiler warning about uninitialized variable use","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104110132.694984-1-aburgess@redhat.com/mbox/"},{"id":15473,"url":"https://patchwork.plctlab.org/api/1.2/patches/15473/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104110214.129095-1-christophe.lyon@arm.com/","msgid":"<20221104110214.129095-1-christophe.lyon@arm.com>","list_archive_url":null,"date":"2022-11-04T11:02:14","name":"configure: require libzstd >= 1.4.0","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104110214.129095-1-christophe.lyon@arm.com/mbox/"},{"id":15485,"url":"https://patchwork.plctlab.org/api/1.2/patches/15485/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104115038.8957-1-nelson@rivosinc.com/","msgid":"<20221104115038.8957-1-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-11-04T11:50:37","name":"[1/2] RISC-V: File-level architecture shouldn'\''t be affected by section-level ones.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104115038.8957-1-nelson@rivosinc.com/mbox/"},{"id":15486,"url":"https://patchwork.plctlab.org/api/1.2/patches/15486/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104115038.8957-2-nelson@rivosinc.com/","msgid":"<20221104115038.8957-2-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-11-04T11:50:38","name":"[2/2] RISC-V: Clarify the suppress rule of mapping symbol with architecture string.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104115038.8957-2-nelson@rivosinc.com/mbox/"},{"id":15509,"url":"https://patchwork.plctlab.org/api/1.2/patches/15509/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/cc133c88-9ce9-5e3a-a8f7-ad72766862b9@suse.com/","msgid":"","list_archive_url":null,"date":"2022-11-04T13:12:07","name":"x86: adjust recently introduced testcases","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/cc133c88-9ce9-5e3a-a8f7-ad72766862b9@suse.com/mbox/"},{"id":15679,"url":"https://patchwork.plctlab.org/api/1.2/patches/15679/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104163328.2274371-1-chigot@adacore.com/","msgid":"<20221104163328.2274371-1-chigot@adacore.com>","list_archive_url":null,"date":"2022-11-04T16:33:28","name":"ld/testsuite: skip tests related to -shared when disabled","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104163328.2274371-1-chigot@adacore.com/mbox/"},{"id":15751,"url":"https://patchwork.plctlab.org/api/1.2/patches/15751/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104190216.1352855-1-indu.bhagat@oracle.com/","msgid":"<20221104190216.1352855-1-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-04T19:02:16","name":"[V3.1,11/15] libctf: add libsframe to LDFLAGS and LIBS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104190216.1352855-1-indu.bhagat@oracle.com/mbox/"},{"id":15792,"url":"https://patchwork.plctlab.org/api/1.2/patches/15792/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104205547.3728827-1-hjl.tools@gmail.com/","msgid":"<20221104205547.3728827-1-hjl.tools@gmail.com>","list_archive_url":null,"date":"2022-11-04T20:55:47","name":"i386: Check invalid (%dx) usage","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104205547.3728827-1-hjl.tools@gmail.com/mbox/"},{"id":15794,"url":"https://patchwork.plctlab.org/api/1.2/patches/15794/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104210134.1721620-1-indu.bhagat@oracle.com/","msgid":"<20221104210134.1721620-1-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-04T21:01:34","name":"[V3.2,11/15] libctf: add libsframe to LDFLAGS and LIBS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104210134.1721620-1-indu.bhagat@oracle.com/mbox/"},{"id":15959,"url":"https://patchwork.plctlab.org/api/1.2/patches/15959/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c620070e3e335df2b487d3836e20d251dac37525.1667651354.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-11-05T12:29:07","name":"[01/12] RISC-V: Remove unnecessary empty matching file","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c620070e3e335df2b487d3836e20d251dac37525.1667651354.git.research_trasio@irq.a4lg.com/mbox/"},{"id":15961,"url":"https://patchwork.plctlab.org/api/1.2/patches/15961/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4496235002a396043598ab9755bd8eda5c077b1f.1667651354.git.research_trasio@irq.a4lg.com/","msgid":"<4496235002a396043598ab9755bd8eda5c077b1f.1667651354.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-05T12:29:08","name":"[02/12] RISC-V: Tidy disassembler corner case tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4496235002a396043598ab9755bd8eda5c077b1f.1667651354.git.research_trasio@irq.a4lg.com/mbox/"},{"id":15960,"url":"https://patchwork.plctlab.org/api/1.2/patches/15960/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a9229a2798480f00bf12ac3c435b3ef57f867022.1667651354.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-11-05T12:29:09","name":"[03/12] RISC-V: Tidying related to '\''Zfinx'\'' disassembler test","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a9229a2798480f00bf12ac3c435b3ef57f867022.1667651354.git.research_trasio@irq.a4lg.com/mbox/"},{"id":15962,"url":"https://patchwork.plctlab.org/api/1.2/patches/15962/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6a020edd0e114a003edbaafe1088a040e9fa07e7.1667651354.git.research_trasio@irq.a4lg.com/","msgid":"<6a020edd0e114a003edbaafe1088a040e9fa07e7.1667651354.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-05T12:29:10","name":"[04/12] RISC-V: GAS: Add basic shared test utilities","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6a020edd0e114a003edbaafe1088a040e9fa07e7.1667651354.git.research_trasio@irq.a4lg.com/mbox/"},{"id":15966,"url":"https://patchwork.plctlab.org/api/1.2/patches/15966/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6fc2851a4161edc429089bd2bbd9c2bb4c0c118f.1667651354.git.research_trasio@irq.a4lg.com/","msgid":"<6fc2851a4161edc429089bd2bbd9c2bb4c0c118f.1667651354.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-05T12:29:11","name":"[05/12] RISC-V: Redefine \"nop\" test","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6fc2851a4161edc429089bd2bbd9c2bb4c0c118f.1667651354.git.research_trasio@irq.a4lg.com/mbox/"},{"id":15963,"url":"https://patchwork.plctlab.org/api/1.2/patches/15963/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7311ed3d2429000e18877d7af594890da170a7a3.1667651354.git.research_trasio@irq.a4lg.com/","msgid":"<7311ed3d2429000e18877d7af594890da170a7a3.1667651354.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-05T12:29:12","name":"[06/12] RISC-V: Reorganize/enhance {sign, zero}-extension instructions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7311ed3d2429000e18877d7af594890da170a7a3.1667651354.git.research_trasio@irq.a4lg.com/mbox/"},{"id":15968,"url":"https://patchwork.plctlab.org/api/1.2/patches/15968/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ac99c9696c156207f06c18f2d6bf423c96c5876b.1667651354.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-11-05T12:29:13","name":"[07/12] RISC-V: Combine complex extension error handling tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ac99c9696c156207f06c18f2d6bf423c96c5876b.1667651354.git.research_trasio@irq.a4lg.com/mbox/"},{"id":15970,"url":"https://patchwork.plctlab.org/api/1.2/patches/15970/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9378b9505e3e230e0a690c56e67d253e2a0f5864.1667651354.git.research_trasio@irq.a4lg.com/","msgid":"<9378b9505e3e230e0a690c56e67d253e2a0f5864.1667651354.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-05T12:29:14","name":"[08/12] RISC-V: Refine/enhance '\''M'\''/'\''Zmmul'\'' extension tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9378b9505e3e230e0a690c56e67d253e2a0f5864.1667651354.git.research_trasio@irq.a4lg.com/mbox/"},{"id":15964,"url":"https://patchwork.plctlab.org/api/1.2/patches/15964/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/82832a67f240d5857fd502d4b74fd7d841ee2d6e.1667651354.git.research_trasio@irq.a4lg.com/","msgid":"<82832a67f240d5857fd502d4b74fd7d841ee2d6e.1667651354.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-05T12:29:15","name":"[09/12] RISC-V: Combine/enhance '\''Zicbo[mz]'\'' extension tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/82832a67f240d5857fd502d4b74fd7d841ee2d6e.1667651354.git.research_trasio@irq.a4lg.com/mbox/"},{"id":15965,"url":"https://patchwork.plctlab.org/api/1.2/patches/15965/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9c47e59868a64b13e5a7bb487e3619d4f1497d78.1667651354.git.research_trasio@irq.a4lg.com/","msgid":"<9c47e59868a64b13e5a7bb487e3619d4f1497d78.1667651354.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-05T12:29:16","name":"[10/12] RISC-V: Enhance '\''Zicbop'\'' testcases","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9c47e59868a64b13e5a7bb487e3619d4f1497d78.1667651354.git.research_trasio@irq.a4lg.com/mbox/"},{"id":15967,"url":"https://patchwork.plctlab.org/api/1.2/patches/15967/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2d9befc5bc5eed80b6bd7da6d092a61b1162ecac.1667651354.git.research_trasio@irq.a4lg.com/","msgid":"<2d9befc5bc5eed80b6bd7da6d092a61b1162ecac.1667651354.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-05T12:29:17","name":"[11/12] RISC-V: Reorganize/enhance '\''Zb*'\'' extension tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2d9befc5bc5eed80b6bd7da6d092a61b1162ecac.1667651354.git.research_trasio@irq.a4lg.com/mbox/"},{"id":15969,"url":"https://patchwork.plctlab.org/api/1.2/patches/15969/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f1c5589ab606b74eeac98e3dafd4a7903450d3b2.1667651354.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-11-05T12:29:18","name":"[12/12] RISC-V: Combine/enhance '\''Zk*'\''/'\''Zbk*'\'' extension tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f1c5589ab606b74eeac98e3dafd4a7903450d3b2.1667651354.git.research_trasio@irq.a4lg.com/mbox/"},{"id":16066,"url":"https://patchwork.plctlab.org/api/1.2/patches/16066/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221106053640.1649752-1-indu.bhagat@oracle.com/","msgid":"<20221106053640.1649752-1-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-06T05:36:40","name":"[V3.1,03/15] gas: generate .sframe from CFI directives","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221106053640.1649752-1-indu.bhagat@oracle.com/mbox/"},{"id":16379,"url":"https://patchwork.plctlab.org/api/1.2/patches/16379/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221107112805.3332619-1-och95@yandex.ru/","msgid":"<20221107112805.3332619-1-och95@yandex.ru>","list_archive_url":null,"date":"2022-11-07T11:28:05","name":"gold/aarch64: Fix adrp distance check","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221107112805.3332619-1-och95@yandex.ru/mbox/"},{"id":16400,"url":"https://patchwork.plctlab.org/api/1.2/patches/16400/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221107124620.1271470-1-christoph.muellner@vrull.eu/","msgid":"<20221107124620.1271470-1-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2022-11-07T12:46:20","name":"RISC-V: xtheadfmemidx: Use fp register in mnemonics","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221107124620.1271470-1-christoph.muellner@vrull.eu/mbox/"},{"id":16594,"url":"https://patchwork.plctlab.org/api/1.2/patches/16594/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/CACVBkZ+kM2xcpwk5zHQ4bqDV7dbPjZ6cMU9tR-h62+tDTgi3Tw@mail.gmail.com/","msgid":"","list_archive_url":null,"date":"2022-11-07T17:53:35","name":"GAS fix section alignment for aarch64-pe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/CACVBkZ+kM2xcpwk5zHQ4bqDV7dbPjZ6cMU9tR-h62+tDTgi3Tw@mail.gmail.com/mbox/"},{"id":16744,"url":"https://patchwork.plctlab.org/api/1.2/patches/16744/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221107222809.924195-1-indu.bhagat@oracle.com/","msgid":"<20221107222809.924195-1-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-07T22:28:09","name":"[V3.3,11/15] libctf: add libsframe to LDFLAGS and LIBS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221107222809.924195-1-indu.bhagat@oracle.com/mbox/"},{"id":16797,"url":"https://patchwork.plctlab.org/api/1.2/patches/16797/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221108012556.66467-1-haochen.jiang@intel.com/","msgid":"<20221108012556.66467-1-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-11-08T01:25:56","name":"x86: Correct wrong comments in vex_w_table","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221108012556.66467-1-haochen.jiang@intel.com/mbox/"},{"id":16884,"url":"https://patchwork.plctlab.org/api/1.2/patches/16884/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221108054530.796968-1-markus.t.metzger@intel.com/","msgid":"<20221108054530.796968-1-markus.t.metzger@intel.com>","list_archive_url":null,"date":"2022-11-08T05:45:29","name":"[1/2] gprofng: make cpu identification available to others","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221108054530.796968-1-markus.t.metzger@intel.com/mbox/"},{"id":16885,"url":"https://patchwork.plctlab.org/api/1.2/patches/16885/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221108054530.796968-2-markus.t.metzger@intel.com/","msgid":"<20221108054530.796968-2-markus.t.metzger@intel.com>","list_archive_url":null,"date":"2022-11-08T05:45:30","name":"[2/2] gdb, btrace: use cpuident.h to implement btrace_this_cpu","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221108054530.796968-2-markus.t.metzger@intel.com/mbox/"},{"id":16995,"url":"https://patchwork.plctlab.org/api/1.2/patches/16995/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ea0daf08-4923-ebfa-dcfe-699c43d63822@suse.com/","msgid":"","list_archive_url":null,"date":"2022-11-08T11:29:40","name":"x86/Intel: don'\''t accept malformed EXTRQ / INSERTQ","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ea0daf08-4923-ebfa-dcfe-699c43d63822@suse.com/mbox/"},{"id":17057,"url":"https://patchwork.plctlab.org/api/1.2/patches/17057/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221108141352.6613-1-jwilk@jwilk.net/","msgid":"<20221108141352.6613-1-jwilk@jwilk.net>","list_archive_url":null,"date":"2022-11-08T14:13:52","name":"Fix typos in the list of objdump options","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221108141352.6613-1-jwilk@jwilk.net/mbox/"},{"id":17117,"url":"https://patchwork.plctlab.org/api/1.2/patches/17117/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1667924955-9218-1-git-send-email-apinski@marvell.com/","msgid":"<1667924955-9218-1-git-send-email-apinski@marvell.com>","list_archive_url":null,"date":"2022-11-08T16:29:15","name":"Use toplevel configure for GMP and MPFR for gdb","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1667924955-9218-1-git-send-email-apinski@marvell.com/mbox/"},{"id":17160,"url":"https://patchwork.plctlab.org/api/1.2/patches/17160/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/27382086-397f-060f-6cf6-c1d36ff6b812@linux.ibm.com/","msgid":"<27382086-397f-060f-6cf6-c1d36ff6b812@linux.ibm.com>","list_archive_url":null,"date":"2022-11-08T18:23:32","name":"[COMMITTED] PowerPC: Add XSP operand define","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/27382086-397f-060f-6cf6-c1d36ff6b812@linux.ibm.com/mbox/"},{"id":17202,"url":"https://patchwork.plctlab.org/api/1.2/patches/17202/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221108192248.1622627-1-indu.bhagat@oracle.com/","msgid":"<20221108192248.1622627-1-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-08T19:22:48","name":"libctf: use libtool for link test in configure","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221108192248.1622627-1-indu.bhagat@oracle.com/mbox/"},{"id":17262,"url":"https://patchwork.plctlab.org/api/1.2/patches/17262/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221108225030.371817-1-hjl.tools@gmail.com/","msgid":"<20221108225030.371817-1-hjl.tools@gmail.com>","list_archive_url":null,"date":"2022-11-08T22:50:30","name":"ld: Always output local symbol for relocatable link","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221108225030.371817-1-hjl.tools@gmail.com/mbox/"},{"id":17399,"url":"https://patchwork.plctlab.org/api/1.2/patches/17399/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-2-indu.bhagat@oracle.com/","msgid":"<20221109084244.261296-2-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-09T08:42:34","name":"[V4,01/11] sframe.h: Add SFrame format definition","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-2-indu.bhagat@oracle.com/mbox/"},{"id":17398,"url":"https://patchwork.plctlab.org/api/1.2/patches/17398/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-3-indu.bhagat@oracle.com/","msgid":"<20221109084244.261296-3-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-09T08:42:35","name":"[V4,02/11] gas: add new command line option --gsframe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-3-indu.bhagat@oracle.com/mbox/"},{"id":17400,"url":"https://patchwork.plctlab.org/api/1.2/patches/17400/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-4-indu.bhagat@oracle.com/","msgid":"<20221109084244.261296-4-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-09T08:42:36","name":"[V4,03/11] gas: generate .sframe from CFI directives","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-4-indu.bhagat@oracle.com/mbox/"},{"id":17403,"url":"https://patchwork.plctlab.org/api/1.2/patches/17403/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-5-indu.bhagat@oracle.com/","msgid":"<20221109084244.261296-5-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-09T08:42:37","name":"[V4,04/11] gas: testsuite: add new tests for SFrame unwind info","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-5-indu.bhagat@oracle.com/mbox/"},{"id":17402,"url":"https://patchwork.plctlab.org/api/1.2/patches/17402/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-8-indu.bhagat@oracle.com/","msgid":"<20221109084244.261296-8-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-09T08:42:40","name":"[V4,07/11] readelf/objdump: support for SFrame section","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-8-indu.bhagat@oracle.com/mbox/"},{"id":17401,"url":"https://patchwork.plctlab.org/api/1.2/patches/17401/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-9-indu.bhagat@oracle.com/","msgid":"<20221109084244.261296-9-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-09T08:42:41","name":"[V4,08/11] src-release.sh: Add libsframe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-9-indu.bhagat@oracle.com/mbox/"},{"id":17404,"url":"https://patchwork.plctlab.org/api/1.2/patches/17404/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-10-indu.bhagat@oracle.com/","msgid":"<20221109084244.261296-10-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-09T08:42:42","name":"[V4,09/11] binutils/NEWS: add text for SFrame support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-10-indu.bhagat@oracle.com/mbox/"},{"id":17405,"url":"https://patchwork.plctlab.org/api/1.2/patches/17405/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-11-indu.bhagat@oracle.com/","msgid":"<20221109084244.261296-11-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-09T08:42:43","name":"[V4,10/11] gas/NEWS: add text about new command line option and SFrame support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-11-indu.bhagat@oracle.com/mbox/"}],"public":true,"mbox":"https://patchwork.plctlab.org/bundle/patchwork-bot/binutils-gdb_2022-11/mbox/"}]' ++ jq -rc '.[].name' + bundle_name_list='binutils-gdb_2022-10 binutils-gdb_2022-09 binutils-gdb_2022-11' + [[ binutils-gdb_2022-10 binutils-gdb_2022-09 binutils-gdb_2022-11 =~ 2022-11 ]] ++ jq -rc --arg bundle_name binutils-gdb_2022-11 '.[] | select(.name==$bundle_name) | (.id|tostring)' ++ echo '[{"id":6,"url":"https://patchwork.plctlab.org/api/1.2/bundles/6/","web_url":"https://patchwork.plctlab.org/bundle/patchwork-bot/binutils-gdb_2022-10/","project":{"id":2,"url":"https://patchwork.plctlab.org/api/1.2/projects/2/","name":"binutils-gdb","link_name":"binutils-gdb","list_id":"binutils.sourceware.org","list_email":"binutils@sourceware.org","web_url":"https://github.com/wangliu-iscas/Patchwork-Bundles/blob/main/binutils-gdb.md","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"name":"binutils-gdb_2022-10","owner":{"id":3,"url":"https://patchwork.plctlab.org/api/1.2/users/3/","username":"patchwork-bot","first_name":"","last_name":"","email":"ouuuleilei@gmail.com"},"patches":[{"id":1592,"url":"https://patchwork.plctlab.org/api/1.2/patches/1592/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/385d01fd-7e57-1f3f-1bae-30aa0c313d63@suse.com/","msgid":"<385d01fd-7e57-1f3f-1bae-30aa0c313d63@suse.com>","list_archive_url":null,"date":"2022-09-30T11:59:45","name":"[3/4] RISC-V/gas: don'\''t open-code insn_length()","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/385d01fd-7e57-1f3f-1bae-30aa0c313d63@suse.com/mbox/"},{"id":1594,"url":"https://patchwork.plctlab.org/api/1.2/patches/1594/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f5757acf-7b90-a0e3-5eea-3b97cc226930@suse.com/","msgid":"","list_archive_url":null,"date":"2022-09-30T12:00:12","name":"[4/4] RISC-V/gas: allow generating up to 176-bit instructions with .insn","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f5757acf-7b90-a0e3-5eea-3b97cc226930@suse.com/mbox/"},{"id":1596,"url":"https://patchwork.plctlab.org/api/1.2/patches/1596/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930140503.38233-1-chigot@adacore.com/","msgid":"<20220930140503.38233-1-chigot@adacore.com>","list_archive_url":null,"date":"2022-09-30T14:05:03","name":"ld/testsuite: consistently add board_ldflags when linking with GCC","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930140503.38233-1-chigot@adacore.com/mbox/"},{"id":1619,"url":"https://patchwork.plctlab.org/api/1.2/patches/1619/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221001014451.532772-1-maskray@google.com/","msgid":"<20221001014451.532772-1-maskray@google.com>","list_archive_url":null,"date":"2022-10-01T01:44:51","name":"gold, dwp: support zstd compressed input debug sections [PR 29641]","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221001014451.532772-1-maskray@google.com/mbox/"},{"id":1620,"url":"https://patchwork.plctlab.org/api/1.2/patches/1620/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221001023846.590825-1-maskray@google.com/","msgid":"<20221001023846.590825-1-maskray@google.com>","list_archive_url":null,"date":"2022-10-01T02:38:46","name":"gold: add --compress-debug-sections=zstd [PR 29641]","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221001023846.590825-1-maskray@google.com/mbox/"},{"id":1623,"url":"https://patchwork.plctlab.org/api/1.2/patches/1623/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b4477c7f666bdeb7f8e998633c7b0cb62310b9ef.1664599545.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-01T04:45:52","name":"[RFC,1/1] RISC-V: Implement common register pair framework","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b4477c7f666bdeb7f8e998633c7b0cb62310b9ef.1664599545.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1625,"url":"https://patchwork.plctlab.org/api/1.2/patches/1625/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/53a265a1f14d17a6f7b106082f610994c5d546e0.1664602025.git.research_trasio@irq.a4lg.com/","msgid":"<53a265a1f14d17a6f7b106082f610994c5d546e0.1664602025.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-01T05:27:31","name":"[RFC,1/1] RISC-V: Implement extension variants","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/53a265a1f14d17a6f7b106082f610994c5d546e0.1664602025.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1626,"url":"https://patchwork.plctlab.org/api/1.2/patches/1626/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8db04962aba9c780f133840a8934353a58f223fe.1664602716.git.research_trasio@irq.a4lg.com/","msgid":"<8db04962aba9c780f133840a8934353a58f223fe.1664602716.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-01T05:39:26","name":"[1/1] RISC-V: Move supervisor instructions after all unprivileged ones","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8db04962aba9c780f133840a8934353a58f223fe.1664602716.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1627,"url":"https://patchwork.plctlab.org/api/1.2/patches/1627/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221001062057.681440-1-maskray@google.com/","msgid":"<20221001062057.681440-1-maskray@google.com>","list_archive_url":null,"date":"2022-10-01T06:20:57","name":"readelf: support zstd compressed debug sections [PR 29640]","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221001062057.681440-1-maskray@google.com/mbox/"},{"id":1631,"url":"https://patchwork.plctlab.org/api/1.2/patches/1631/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/619f112539c0bdecd58e25664f1250a3479a37f5.1664707612.git.aburgess@redhat.com/","msgid":"<619f112539c0bdecd58e25664f1250a3479a37f5.1664707612.git.aburgess@redhat.com>","list_archive_url":null,"date":"2022-10-02T10:47:52","name":"[PATCHv2,2/2] opcodes/arm: add disassembler styling for arm","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/619f112539c0bdecd58e25664f1250a3479a37f5.1664707612.git.aburgess@redhat.com/mbox/"},{"id":1635,"url":"https://patchwork.plctlab.org/api/1.2/patches/1635/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221002185433.gl7dvytfh5wthifx@lug-owl.de/","msgid":"<20221002185433.gl7dvytfh5wthifx@lug-owl.de>","list_archive_url":null,"date":"2022-10-02T18:54:33","name":"diagnostics.h: GCC 13 got -Wself-move, breaks GDB build","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221002185433.gl7dvytfh5wthifx@lug-owl.de/mbox/"},{"id":1637,"url":"https://patchwork.plctlab.org/api/1.2/patches/1637/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003014313.28766-1-mark@harmstone.com/","msgid":"<20221003014313.28766-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-03T01:43:12","name":"[1/2] ld: Add --pdb option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003014313.28766-1-mark@harmstone.com/mbox/"},{"id":1638,"url":"https://patchwork.plctlab.org/api/1.2/patches/1638/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003014313.28766-2-mark@harmstone.com/","msgid":"<20221003014313.28766-2-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-03T01:43:13","name":"[2/2] ld: Add minimal pdb generation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003014313.28766-2-mark@harmstone.com/mbox/"},{"id":1640,"url":"https://patchwork.plctlab.org/api/1.2/patches/1640/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/597ed978-d121-220c-b56b-2ffb94bd091c@suse.cz/","msgid":"<597ed978-d121-220c-b56b-2ffb94bd091c@suse.cz>","list_archive_url":null,"date":"2022-10-03T07:50:38","name":"[1/2] refactor usage of compressed_debug_section_type","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/597ed978-d121-220c-b56b-2ffb94bd091c@suse.cz/mbox/"},{"id":1641,"url":"https://patchwork.plctlab.org/api/1.2/patches/1641/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b8acdd83-f33a-74b8-e21a-23719a0b1a60@suse.cz/","msgid":"","list_archive_url":null,"date":"2022-10-03T07:50:44","name":"[2/2] add --enable-default-compressed-debug-sections-algorithm configure option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b8acdd83-f33a-74b8-e21a-23719a0b1a60@suse.cz/mbox/"},{"id":1642,"url":"https://patchwork.plctlab.org/api/1.2/patches/1642/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003101328.1790113-1-aburgess@redhat.com/","msgid":"<20221003101328.1790113-1-aburgess@redhat.com>","list_archive_url":null,"date":"2022-10-03T10:13:28","name":"opcodes/riscv: style csr names as registers","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003101328.1790113-1-aburgess@redhat.com/mbox/"},{"id":1643,"url":"https://patchwork.plctlab.org/api/1.2/patches/1643/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7ba14fc4472ce97d4f7a4433cad8a571e89f82f4.1664793840.git.research_trasio@irq.a4lg.com/","msgid":"<7ba14fc4472ce97d4f7a4433cad8a571e89f82f4.1664793840.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-03T10:43:59","name":"[v3,1/6] RISC-V: Fix immediates to have \"immediate\" style","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7ba14fc4472ce97d4f7a4433cad8a571e89f82f4.1664793840.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1644,"url":"https://patchwork.plctlab.org/api/1.2/patches/1644/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a498bec37c1fd1dcda57cbf95e5f8cfba09b31d3.1664793840.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-03T10:44:00","name":"[v3,2/6] RISC-V: Fix printf argument types corresponding %x","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a498bec37c1fd1dcda57cbf95e5f8cfba09b31d3.1664793840.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1647,"url":"https://patchwork.plctlab.org/api/1.2/patches/1647/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0002ea716713ace4998a33dde0b81f4f890d10bf.1664793840.git.research_trasio@irq.a4lg.com/","msgid":"<0002ea716713ace4998a33dde0b81f4f890d10bf.1664793840.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-03T10:44:01","name":"[v3,3/6] RISC-V: Optimize riscv_disassemble_data printf","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0002ea716713ace4998a33dde0b81f4f890d10bf.1664793840.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1646,"url":"https://patchwork.plctlab.org/api/1.2/patches/1646/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c65fc3e9aa58965d6768a28c9fd7467fea9897a5.1664793840.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-03T10:44:02","name":"[v3,4/6] RISC-V: Print comma and tabs as the \"text\" style","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c65fc3e9aa58965d6768a28c9fd7467fea9897a5.1664793840.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1648,"url":"https://patchwork.plctlab.org/api/1.2/patches/1648/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5abe1d8a7694417b990e11d8f6cd6789573872e5.1664793840.git.research_trasio@irq.a4lg.com/","msgid":"<5abe1d8a7694417b990e11d8f6cd6789573872e5.1664793840.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-03T10:44:03","name":"[v3,5/6] RISC-V: Fix T-Head immediate types on printing","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5abe1d8a7694417b990e11d8f6cd6789573872e5.1664793840.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1649,"url":"https://patchwork.plctlab.org/api/1.2/patches/1649/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0b68af932117258c908db62cf87c3a15d3cdec41.1664793840.git.research_trasio@irq.a4lg.com/","msgid":"<0b68af932117258c908db62cf87c3a15d3cdec41.1664793840.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-03T10:44:04","name":"[v3,6/6] RISC-V: Print XTheadMemPair literal as \"immediate\"","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0b68af932117258c908db62cf87c3a15d3cdec41.1664793840.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1656,"url":"https://patchwork.plctlab.org/api/1.2/patches/1656/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/87lepxcd6x.fsf@redhat.com/","msgid":"<87lepxcd6x.fsf@redhat.com>","list_archive_url":null,"date":"2022-10-03T12:19:02","name":"Commit: readelf: Do not load section data from offset 0","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/87lepxcd6x.fsf@redhat.com/mbox/"},{"id":1659,"url":"https://patchwork.plctlab.org/api/1.2/patches/1659/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e0d369d419da9c0441f415da7f54352aead8f655.1664707612.git.aburgess@redhat.com/","msgid":"","list_archive_url":null,"date":"2022-10-03T16:37:36","name":"[PATCHv2,1/2] opcodes/arm: use '\''@'\'' consistently for the comment character","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e0d369d419da9c0441f415da7f54352aead8f655.1664707612.git.aburgess@redhat.com/mbox/"},{"id":1660,"url":"https://patchwork.plctlab.org/api/1.2/patches/1660/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003165848.11142-1-palmer@rivosinc.com/","msgid":"<20221003165848.11142-1-palmer@rivosinc.com>","list_archive_url":null,"date":"2022-10-03T16:58:48","name":"gas: NEWS: Mention the T-Head extensions that were recently added","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003165848.11142-1-palmer@rivosinc.com/mbox/"},{"id":1671,"url":"https://patchwork.plctlab.org/api/1.2/patches/1671/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/YzvrMEdkXjIn5Lfz@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-04T08:13:36","name":"Support objcopy changing compression to or from zstd","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/YzvrMEdkXjIn5Lfz@squeak.grove.modra.org/mbox/"},{"id":1673,"url":"https://patchwork.plctlab.org/api/1.2/patches/1673/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0bc857d306bb7c8130e5328dbe6b9ed2fed3ef87.1664873933.git.research_trasio@irq.a4lg.com/","msgid":"<0bc857d306bb7c8130e5328dbe6b9ed2fed3ef87.1664873933.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-04T08:59:07","name":"[1/2] RISC-V: Fix buffer overflow on print_insn_riscv","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0bc857d306bb7c8130e5328dbe6b9ed2fed3ef87.1664873933.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1672,"url":"https://patchwork.plctlab.org/api/1.2/patches/1672/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/89612fe01d902007bf84a7dfb0df5f85d5c166e4.1664873933.git.research_trasio@irq.a4lg.com/","msgid":"<89612fe01d902007bf84a7dfb0df5f85d5c166e4.1664873933.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-04T08:59:08","name":"[2/2] gdb/riscv: Fix buffer overflow on riscv_insn::fetch_instruction","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/89612fe01d902007bf84a7dfb0df5f85d5c166e4.1664873933.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1676,"url":"https://patchwork.plctlab.org/api/1.2/patches/1676/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fc849c94f4adcac1c4ccc5508c7a145a2f13b2a9.1664876744.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-04T09:45:49","name":"[v2,1/2] RISC-V: Fix buffer overflow on print_insn_riscv","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fc849c94f4adcac1c4ccc5508c7a145a2f13b2a9.1664876744.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1677,"url":"https://patchwork.plctlab.org/api/1.2/patches/1677/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4eb6e59ae2e790dbbf2bc92477edd281648d8814.1664876744.git.research_trasio@irq.a4lg.com/","msgid":"<4eb6e59ae2e790dbbf2bc92477edd281648d8814.1664876744.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-04T09:45:50","name":"[v2,2/2] gdb/riscv: Partial support for instructions up to 176-bits","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4eb6e59ae2e790dbbf2bc92477edd281648d8814.1664876744.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1678,"url":"https://patchwork.plctlab.org/api/1.2/patches/1678/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ebf16f9e1f45115d0793952ccb4a94d4233303f9.1664882725.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-04T11:25:56","name":"[v3,1/2] RISC-V: Fix buffer overflow on print_insn_riscv","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ebf16f9e1f45115d0793952ccb4a94d4233303f9.1664882725.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1679,"url":"https://patchwork.plctlab.org/api/1.2/patches/1679/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/83464b09b8649525259c69c853dfa2c9575a204b.1664882725.git.research_trasio@irq.a4lg.com/","msgid":"<83464b09b8649525259c69c853dfa2c9575a204b.1664882725.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-04T11:25:57","name":"[v3,2/2] gdb/riscv: Partial support for instructions up to 176-bit","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/83464b09b8649525259c69c853dfa2c9575a204b.1664882725.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1681,"url":"https://patchwork.plctlab.org/api/1.2/patches/1681/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ffa9c1d7-e8c2-a62b-ef3e-b565c0ffbe5b@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-04T13:56:27","name":"RISC-V: Zicbo{m,p,z} adjustments to riscv_multi_subset_supports_ext()","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ffa9c1d7-e8c2-a62b-ef3e-b565c0ffbe5b@suse.com/mbox/"},{"id":1690,"url":"https://patchwork.plctlab.org/api/1.2/patches/1690/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221004161720.1963953-1-vladimir.mezentsev@oracle.com/","msgid":"<20221004161720.1963953-1-vladimir.mezentsev@oracle.com>","list_archive_url":null,"date":"2022-10-04T16:17:20","name":"gprofng: fix build with --enable-pgo-build=lto","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221004161720.1963953-1-vladimir.mezentsev@oracle.com/mbox/"},{"id":1691,"url":"https://patchwork.plctlab.org/api/1.2/patches/1691/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c0211bc9c57be6c79c6d878ce147f63b657f461d.camel@espressif.com/","msgid":"","list_archive_url":null,"date":"2022-10-04T16:22:05","name":"bfd: xtensa: fix __stop_SECTION literal drop,","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c0211bc9c57be6c79c6d878ce147f63b657f461d.camel@espressif.com/mbox/"},{"id":1702,"url":"https://patchwork.plctlab.org/api/1.2/patches/1702/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5f482299-6c60-b2b3-9abe-f4a55a5a26c5@univ-grenoble-alpes.fr/","msgid":"<5f482299-6c60-b2b3-9abe-f4a55a5a26c5@univ-grenoble-alpes.fr>","list_archive_url":null,"date":"2022-10-04T20:03:20","name":"[RFC] bfd: use bfd_vma for the 64-bit version of put[lb] and get[lb]","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5f482299-6c60-b2b3-9abe-f4a55a5a26c5@univ-grenoble-alpes.fr/mbox/"},{"id":1711,"url":"https://patchwork.plctlab.org/api/1.2/patches/1711/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Yz0Gsxdxe0TePbJT@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-05T04:23:15","name":"PR29647, objdump -S looping","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Yz0Gsxdxe0TePbJT@squeak.grove.modra.org/mbox/"},{"id":1712,"url":"https://patchwork.plctlab.org/api/1.2/patches/1712/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/02d747d2-f57b-0fb5-b893-842b6cc41f2f@suse.com/","msgid":"<02d747d2-f57b-0fb5-b893-842b6cc41f2f@suse.com>","list_archive_url":null,"date":"2022-10-05T07:20:47","name":"[v3,1/7] x86: constify parse_insn()'\''s input","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/02d747d2-f57b-0fb5-b893-842b6cc41f2f@suse.com/mbox/"},{"id":1713,"url":"https://patchwork.plctlab.org/api/1.2/patches/1713/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/925cb740-4e1b-abc4-8526-aaab6faae5e1@suse.com/","msgid":"<925cb740-4e1b-abc4-8526-aaab6faae5e1@suse.com>","list_archive_url":null,"date":"2022-10-05T07:22:19","name":"[v3,2/7] x86: introduce Pass2 insn attribute","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/925cb740-4e1b-abc4-8526-aaab6faae5e1@suse.com/mbox/"},{"id":1714,"url":"https://patchwork.plctlab.org/api/1.2/patches/1714/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e16d3e78-39ca-f715-508f-a4104b8ab9a9@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-05T07:23:51","name":"[v3,3/7] x86: re-work insn/suffix recognition","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e16d3e78-39ca-f715-508f-a4104b8ab9a9@suse.com/mbox/"},{"id":1715,"url":"https://patchwork.plctlab.org/api/1.2/patches/1715/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e4e4b80b-794c-7485-1997-685adab8fb27@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-05T07:24:20","name":"[v3,4/7] x86-64: further re-work insn/suffix recognition to also cover MOVSL","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e4e4b80b-794c-7485-1997-685adab8fb27@suse.com/mbox/"},{"id":1716,"url":"https://patchwork.plctlab.org/api/1.2/patches/1716/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/540678fc-8bff-ec68-c97c-478d2631998c@suse.com/","msgid":"<540678fc-8bff-ec68-c97c-478d2631998c@suse.com>","list_archive_url":null,"date":"2022-10-05T07:24:55","name":"[v3,5/7] ix86: don'\''t recognize/derive Q suffix in the common case","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/540678fc-8bff-ec68-c97c-478d2631998c@suse.com/mbox/"},{"id":1718,"url":"https://patchwork.plctlab.org/api/1.2/patches/1718/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e4692495-7d3d-074d-14f9-364d4a9a998c@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-05T07:25:25","name":"[v3,6/7] x86-64: allow HLE store of accumulator to absolute 32-bit address","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e4692495-7d3d-074d-14f9-364d4a9a998c@suse.com/mbox/"},{"id":1717,"url":"https://patchwork.plctlab.org/api/1.2/patches/1717/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e8014ebd-d16b-17a7-9f34-3700fc164136@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-05T07:25:57","name":"[v3,7/7] x86: move bad-use-of-TLS-reloc check","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e8014ebd-d16b-17a7-9f34-3700fc164136@suse.com/mbox/"},{"id":1719,"url":"https://patchwork.plctlab.org/api/1.2/patches/1719/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1266f001-4511-2662-dba9-14b4d0317c57@suse.com/","msgid":"<1266f001-4511-2662-dba9-14b4d0317c57@suse.com>","list_archive_url":null,"date":"2022-10-05T07:40:50","name":"x86: drop \"regmask\" static variable","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1266f001-4511-2662-dba9-14b4d0317c57@suse.com/mbox/"},{"id":1751,"url":"https://patchwork.plctlab.org/api/1.2/patches/1751/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/af45c5d57c221e43101c2aa38b14f4b4ac12d011.1665031170.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-06T04:40:15","name":"[v2,1/2] RISC-V: Fallback for instructions longer than 64b","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/af45c5d57c221e43101c2aa38b14f4b4ac12d011.1665031170.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1752,"url":"https://patchwork.plctlab.org/api/1.2/patches/1752/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c6e55781245dd3e8e9b8debd6130fc5449dfbd55.1665031170.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-06T04:40:16","name":"[v2,2/2] RISC-V: Improve \"bits undefined\" diagnostics","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c6e55781245dd3e8e9b8debd6130fc5449dfbd55.1665031170.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1776,"url":"https://patchwork.plctlab.org/api/1.2/patches/1776/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d52952119e15357c0e823f8a2398999359588b4d.1665050099.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-06T09:56:30","name":"[v3,1/2] RISC-V: Fallback for instructions longer than 64b","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d52952119e15357c0e823f8a2398999359588b4d.1665050099.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1777,"url":"https://patchwork.plctlab.org/api/1.2/patches/1777/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d907b1997f60ff7823c4a23e281ec9d8ddcbf3f1.1665050099.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-06T09:56:31","name":"[v3,2/2] RISC-V: Improve \"bits undefined\" diagnostics","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d907b1997f60ff7823c4a23e281ec9d8ddcbf3f1.1665050099.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1781,"url":"https://patchwork.plctlab.org/api/1.2/patches/1781/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221006114628.304185-1-chigot@adacore.com/","msgid":"<20221006114628.304185-1-chigot@adacore.com>","list_archive_url":null,"date":"2022-10-06T11:46:28","name":"RISC-V: fix linker message when relaxation deletes bytes","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221006114628.304185-1-chigot@adacore.com/mbox/"},{"id":1801,"url":"https://patchwork.plctlab.org/api/1.2/patches/1801/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Yz+Yhyg7UewC9/kp@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-07T03:09:59","name":"PR29653, objcopy/strip: fuzzed small input file induces large output file","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Yz+Yhyg7UewC9/kp@squeak.grove.modra.org/mbox/"},{"id":1803,"url":"https://patchwork.plctlab.org/api/1.2/patches/1803/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/PH1P110MB16505D9D39EC5B1DE22FE3D5EC5F9@PH1P110MB1650.NAMP110.PROD.OUTLOOK.COM/","msgid":"","list_archive_url":null,"date":"2022-10-07T04:10:07","name":"@CPP_FOR_BUILD@ problem since binutils-2.38","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/PH1P110MB16505D9D39EC5B1DE22FE3D5EC5F9@PH1P110MB1650.NAMP110.PROD.OUTLOOK.COM/mbox/"},{"id":1827,"url":"https://patchwork.plctlab.org/api/1.2/patches/1827/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8e13bce108ac10a0c1dd911e23ec572926f7ae44.1665203374.git.research_trasio@irq.a4lg.com/","msgid":"<8e13bce108ac10a0c1dd911e23ec572926f7ae44.1665203374.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-08T04:29:53","name":"[v2,1/1] RISC-V: Test DWARF register numbers for \"fp\"","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8e13bce108ac10a0c1dd911e23ec572926f7ae44.1665203374.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1828,"url":"https://patchwork.plctlab.org/api/1.2/patches/1828/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0883001b3572e54d3fba264429c7ade2adb66610.1665203441.git.research_trasio@irq.a4lg.com/","msgid":"<0883001b3572e54d3fba264429c7ade2adb66610.1665203441.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-08T04:31:15","name":"[1/1] RISC-V: Move standard hints before all instructions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0883001b3572e54d3fba264429c7ade2adb66610.1665203441.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1829,"url":"https://patchwork.plctlab.org/api/1.2/patches/1829/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/58e16a241d7376fcae2515c6bd5a2b41d275eeba.1665203531.git.research_trasio@irq.a4lg.com/","msgid":"<58e16a241d7376fcae2515c6bd5a2b41d275eeba.1665203531.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-08T04:32:18","name":"[RFC,1/1] RISC-V: Imply '\''Zicsr'\'' from privileged extensions with CSRs","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/58e16a241d7376fcae2515c6bd5a2b41d275eeba.1665203531.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1830,"url":"https://patchwork.plctlab.org/api/1.2/patches/1830/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/cb5076fc96e8f2097779a3abcde843dcdd660031.1665203660.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-08T04:34:23","name":"[1/5] opcodes/riscv-dis.c: Tidying with comments/clarity","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/cb5076fc96e8f2097779a3abcde843dcdd660031.1665203660.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1832,"url":"https://patchwork.plctlab.org/api/1.2/patches/1832/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1f1aa0838bf9c4f10a45fcfe3c682f7efc79d9ae.1665203660.git.research_trasio@irq.a4lg.com/","msgid":"<1f1aa0838bf9c4f10a45fcfe3c682f7efc79d9ae.1665203660.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-08T04:34:24","name":"[2/5] opcodes/riscv-dis.c: Tidying with spacing","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1f1aa0838bf9c4f10a45fcfe3c682f7efc79d9ae.1665203660.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1831,"url":"https://patchwork.plctlab.org/api/1.2/patches/1831/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/740bc5e2d2618d236519b39fedd1a1d7ae4e05da.1665203660.git.research_trasio@irq.a4lg.com/","msgid":"<740bc5e2d2618d236519b39fedd1a1d7ae4e05da.1665203660.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-08T04:34:25","name":"[3/5] opcodes/riscv-dis.c: Use bool type whenever possible","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/740bc5e2d2618d236519b39fedd1a1d7ae4e05da.1665203660.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1833,"url":"https://patchwork.plctlab.org/api/1.2/patches/1833/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6e3a9c235e317f441b4383b3daa68f2051bdc149.1665203660.git.research_trasio@irq.a4lg.com/","msgid":"<6e3a9c235e317f441b4383b3daa68f2051bdc149.1665203660.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-08T04:34:26","name":"[4/5] opcodes/riscv-dis.c: Make XLEN variable static","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6e3a9c235e317f441b4383b3daa68f2051bdc149.1665203660.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1834,"url":"https://patchwork.plctlab.org/api/1.2/patches/1834/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ad929233a62d887495122721340b2f9c80392963.1665203660.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-08T04:34:27","name":"[5/5] opcodes/riscv-dis.c: Remove last_map_state","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ad929233a62d887495122721340b2f9c80392963.1665203660.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1836,"url":"https://patchwork.plctlab.org/api/1.2/patches/1836/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d07e2b6f36ea2fd5830924a9bfeda941b774b687.1665290422.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-09T05:09:22","name":"RISC-V: Move certain arrays to riscv-opc.c","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d07e2b6f36ea2fd5830924a9bfeda941b774b687.1665290422.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1844,"url":"https://patchwork.plctlab.org/api/1.2/patches/1844/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010004623.16582-1-mark@harmstone.com/","msgid":"<20221010004623.16582-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-10T00:46:22","name":"[v2,1/2] ld: Add --pdb option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010004623.16582-1-mark@harmstone.com/mbox/"},{"id":1845,"url":"https://patchwork.plctlab.org/api/1.2/patches/1845/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010004623.16582-2-mark@harmstone.com/","msgid":"<20221010004623.16582-2-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-10T00:46:23","name":"[v2,2/2] ld: Add minimal pdb generation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010004623.16582-2-mark@harmstone.com/mbox/"},{"id":1890,"url":"https://patchwork.plctlab.org/api/1.2/patches/1890/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010200433.414320-1-vladimir.mezentsev@oracle.com/","msgid":"<20221010200433.414320-1-vladimir.mezentsev@oracle.com>","list_archive_url":null,"date":"2022-10-10T20:04:33","name":"gprofng: run tests without installation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010200433.414320-1-vladimir.mezentsev@oracle.com/mbox/"},{"id":1893,"url":"https://patchwork.plctlab.org/api/1.2/patches/1893/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010230426.719238-1-vladimir.mezentsev@oracle.com/","msgid":"<20221010230426.719238-1-vladimir.mezentsev@oracle.com>","list_archive_url":null,"date":"2022-10-10T23:04:26","name":"[2/2] gprofng: use the --libdir path to find libraries","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010230426.719238-1-vladimir.mezentsev@oracle.com/mbox/"},{"id":1894,"url":"https://patchwork.plctlab.org/api/1.2/patches/1894/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010235155.842469-1-vladimir.mezentsev@oracle.com/","msgid":"<20221010235155.842469-1-vladimir.mezentsev@oracle.com>","list_archive_url":null,"date":"2022-10-10T23:51:55","name":"[3/3] gprofng: no need to build version.texi","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010235155.842469-1-vladimir.mezentsev@oracle.com/mbox/"},{"id":1895,"url":"https://patchwork.plctlab.org/api/1.2/patches/1895/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011003702.4287-1-mark@harmstone.com/","msgid":"<20221011003702.4287-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-11T00:37:01","name":"[v3,1/2] ld: Add --pdb option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011003702.4287-1-mark@harmstone.com/mbox/"},{"id":1897,"url":"https://patchwork.plctlab.org/api/1.2/patches/1897/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011003702.4287-2-mark@harmstone.com/","msgid":"<20221011003702.4287-2-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-11T00:37:02","name":"[v3,2/2] ld: Add minimal pdb generation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011003702.4287-2-mark@harmstone.com/mbox/"},{"id":1928,"url":"https://patchwork.plctlab.org/api/1.2/patches/1928/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011175332.17156-1-mark@harmstone.com/","msgid":"<20221011175332.17156-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-11T17:53:31","name":"[v4,1/2] ld: Add --pdb option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011175332.17156-1-mark@harmstone.com/mbox/"},{"id":1929,"url":"https://patchwork.plctlab.org/api/1.2/patches/1929/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011175332.17156-2-mark@harmstone.com/","msgid":"<20221011175332.17156-2-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-11T17:53:32","name":"[v4,2/2] ld: Add minimal pdb generation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011175332.17156-2-mark@harmstone.com/mbox/"},{"id":1941,"url":"https://patchwork.plctlab.org/api/1.2/patches/1941/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221012031005.237446-1-simon.marchi@polymtl.ca/","msgid":"<20221012031005.237446-1-simon.marchi@polymtl.ca>","list_archive_url":null,"date":"2022-10-12T03:10:05","name":"[pushed] Re-apply \"Pass PKG_CONFIG_PATH down from top-level Makefile\"","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221012031005.237446-1-simon.marchi@polymtl.ca/mbox/"},{"id":1976,"url":"https://patchwork.plctlab.org/api/1.2/patches/1976/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1216a3f8-2273-8681-f528-9493a66891f0@suse.com/","msgid":"<1216a3f8-2273-8681-f528-9493a66891f0@suse.com>","list_archive_url":null,"date":"2022-10-13T08:16:49","name":"[v4,1/8] x86: constify parse_insn()'\''s input","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1216a3f8-2273-8681-f528-9493a66891f0@suse.com/mbox/"},{"id":1977,"url":"https://patchwork.plctlab.org/api/1.2/patches/1977/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/11599bbe-c779-aa9f-4d5d-c2243f0e69dc@suse.com/","msgid":"<11599bbe-c779-aa9f-4d5d-c2243f0e69dc@suse.com>","list_archive_url":null,"date":"2022-10-13T08:17:17","name":"[v4,2/8] x86: introduce Pass2 insn attribute","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/11599bbe-c779-aa9f-4d5d-c2243f0e69dc@suse.com/mbox/"},{"id":1978,"url":"https://patchwork.plctlab.org/api/1.2/patches/1978/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/357273a3-060c-23db-72da-3fc9d1be3d2a@suse.com/","msgid":"<357273a3-060c-23db-72da-3fc9d1be3d2a@suse.com>","list_archive_url":null,"date":"2022-10-13T08:18:09","name":"[v4,3/8] x86: re-work insn/suffix recognition","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/357273a3-060c-23db-72da-3fc9d1be3d2a@suse.com/mbox/"},{"id":1979,"url":"https://patchwork.plctlab.org/api/1.2/patches/1979/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0ec0587f-6a7b-45b6-8346-e5d774e73636@suse.com/","msgid":"<0ec0587f-6a7b-45b6-8346-e5d774e73636@suse.com>","list_archive_url":null,"date":"2022-10-13T08:18:39","name":"[v4,4/8] x86-64: further re-work insn/suffix recognition to also cover MOVSL","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0ec0587f-6a7b-45b6-8346-e5d774e73636@suse.com/mbox/"},{"id":1980,"url":"https://patchwork.plctlab.org/api/1.2/patches/1980/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fb617d0b-8759-3169-5a65-1178b7fef3d7@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-13T08:19:34","name":"[v4,5/8] ix86: don'\''t recognize/derive Q suffix in the common case","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fb617d0b-8759-3169-5a65-1178b7fef3d7@suse.com/mbox/"},{"id":1981,"url":"https://patchwork.plctlab.org/api/1.2/patches/1981/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1df3bd01-99c5-f56c-d937-970edd42b2b8@suse.com/","msgid":"<1df3bd01-99c5-f56c-d937-970edd42b2b8@suse.com>","list_archive_url":null,"date":"2022-10-13T08:20:14","name":"[v4,6/8] x86-64: allow HLE store of accumulator to absolute 32-bit address","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1df3bd01-99c5-f56c-d937-970edd42b2b8@suse.com/mbox/"},{"id":1982,"url":"https://patchwork.plctlab.org/api/1.2/patches/1982/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8486a218-39ec-16b2-5c6c-5037196b93cf@suse.com/","msgid":"<8486a218-39ec-16b2-5c6c-5037196b93cf@suse.com>","list_archive_url":null,"date":"2022-10-13T08:21:00","name":"[v4,7/8] x86: move bad-use-of-TLS-reloc check","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8486a218-39ec-16b2-5c6c-5037196b93cf@suse.com/mbox/"},{"id":1983,"url":"https://patchwork.plctlab.org/api/1.2/patches/1983/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7d82692d-93df-fbee-9efb-2f44e8a91df3@suse.com/","msgid":"<7d82692d-93df-fbee-9efb-2f44e8a91df3@suse.com>","list_archive_url":null,"date":"2022-10-13T08:22:00","name":"[v4,8/8] x86: drop (now) stray IsString","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7d82692d-93df-fbee-9efb-2f44e8a91df3@suse.com/mbox/"},{"id":2013,"url":"https://patchwork.plctlab.org/api/1.2/patches/2013/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8ab93d7a617ad480dd786210f46db0e5aa07d1ac.1665655719.git.research_trasio@irq.a4lg.com/","msgid":"<8ab93d7a617ad480dd786210f46db0e5aa07d1ac.1665655719.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-13T10:11:41","name":"include: Declare getopt function on old GNU libc","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8ab93d7a617ad480dd786210f46db0e5aa07d1ac.1665655719.git.research_trasio@irq.a4lg.com/mbox/"},{"id":2352,"url":"https://patchwork.plctlab.org/api/1.2/patches/2352/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221013201332.2747246-1-maskray@google.com/","msgid":"<20221013201332.2747246-1-maskray@google.com>","list_archive_url":null,"date":"2022-10-13T20:13:32","name":"ld: Add --undefined-version","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221013201332.2747246-1-maskray@google.com/mbox/"},{"id":2532,"url":"https://patchwork.plctlab.org/api/1.2/patches/2532/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014063520.1428330-2-zengxiao@eswincomputing.com/","msgid":"<20221014063520.1428330-2-zengxiao@eswincomputing.com>","list_archive_url":null,"date":"2022-10-14T06:35:20","name":"[1/1] RISC-V: Make R_RISCV_SUB6 conforms to riscv abi standard","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014063520.1428330-2-zengxiao@eswincomputing.com/mbox/"},{"id":2560,"url":"https://patchwork.plctlab.org/api/1.2/patches/2560/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/027ae69a-636b-6757-297a-eec42936401e@linaro.org/","msgid":"<027ae69a-636b-6757-297a-eec42936401e@linaro.org>","list_archive_url":null,"date":"2022-10-14T07:58:22","name":"[v3] aarch64-pe support for LD, GAS and BFD","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/027ae69a-636b-6757-297a-eec42936401e@linaro.org/mbox/"},{"id":2602,"url":"https://patchwork.plctlab.org/api/1.2/patches/2602/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-2-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-2-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:39","name":"[01/10] Support Intel AVX-IFMA","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-2-haochen.jiang@intel.com/mbox/"},{"id":2608,"url":"https://patchwork.plctlab.org/api/1.2/patches/2608/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-3-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-3-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:40","name":"[02/10] Support Intel AVX-VNNI-INT8","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-3-haochen.jiang@intel.com/mbox/"},{"id":2611,"url":"https://patchwork.plctlab.org/api/1.2/patches/2611/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-4-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-4-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:41","name":"[03/10] Support Intel AVX-NE-CONVERT","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-4-haochen.jiang@intel.com/mbox/"},{"id":2610,"url":"https://patchwork.plctlab.org/api/1.2/patches/2610/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-5-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-5-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:42","name":"[04/10] Support Intel CMPccXADD","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-5-haochen.jiang@intel.com/mbox/"},{"id":2601,"url":"https://patchwork.plctlab.org/api/1.2/patches/2601/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-6-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-6-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:43","name":"[05/10] Add handler for more i386_cpu_flags","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-6-haochen.jiang@intel.com/mbox/"},{"id":2606,"url":"https://patchwork.plctlab.org/api/1.2/patches/2606/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-7-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-7-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:44","name":"[06/10] Support Intel RAO-INT","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-7-haochen.jiang@intel.com/mbox/"},{"id":2609,"url":"https://patchwork.plctlab.org/api/1.2/patches/2609/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-8-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-8-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:45","name":"[07/10] Support Intel WRMSRNS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-8-haochen.jiang@intel.com/mbox/"},{"id":2605,"url":"https://patchwork.plctlab.org/api/1.2/patches/2605/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-9-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-9-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:46","name":"[08/10] Support Intel MSRLIST","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-9-haochen.jiang@intel.com/mbox/"},{"id":2607,"url":"https://patchwork.plctlab.org/api/1.2/patches/2607/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-10-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-10-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:47","name":"[09/10] Support Intel AMX-FP16","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-10-haochen.jiang@intel.com/mbox/"},{"id":2604,"url":"https://patchwork.plctlab.org/api/1.2/patches/2604/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-11-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-11-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:48","name":"[10/10] Support Intel PREFETCHI","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-11-haochen.jiang@intel.com/mbox/"},{"id":2643,"url":"https://patchwork.plctlab.org/api/1.2/patches/2643/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7bac66be-535e-9051-d674-f2f5ba180e17@suse.com/","msgid":"<7bac66be-535e-9051-d674-f2f5ba180e17@suse.com>","list_archive_url":null,"date":"2022-10-14T10:22:34","name":"x86: fold AVX512-VNNI disassembler entries with AVX-VNNI ones","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7bac66be-535e-9051-d674-f2f5ba180e17@suse.com/mbox/"},{"id":2654,"url":"https://patchwork.plctlab.org/api/1.2/patches/2654/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0lIo5+ncY/MqBEq@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-14T11:31:47","name":"PR29677, Field `the_bfd` of `asymbol` is uninitialised","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0lIo5+ncY/MqBEq@squeak.grove.modra.org/mbox/"},{"id":2656,"url":"https://patchwork.plctlab.org/api/1.2/patches/2656/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0lJksn49ZpABY89@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-14T11:35:46","name":"e200 LSP support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0lJksn49ZpABY89@squeak.grove.modra.org/mbox/"},{"id":2657,"url":"https://patchwork.plctlab.org/api/1.2/patches/2657/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0lJxxYoeD5iDYAD@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-14T11:36:39","name":"PowerPC SPE disassembly and tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0lJxxYoeD5iDYAD@squeak.grove.modra.org/mbox/"},{"id":2695,"url":"https://patchwork.plctlab.org/api/1.2/patches/2695/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/DM6PR12MB4219611F6CC2A0702884A602E7249@DM6PR12MB4219.namprd12.prod.outlook.com/","msgid":"","list_archive_url":null,"date":"2022-10-14T13:29:40","name":"Binutils: Adding new testcase for addr2line.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/DM6PR12MB4219611F6CC2A0702884A602E7249@DM6PR12MB4219.namprd12.prod.outlook.com/mbox/"},{"id":2700,"url":"https://patchwork.plctlab.org/api/1.2/patches/2700/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9fd2c88d-98b2-99a4-419f-c7235b2cf960@suse.com/","msgid":"<9fd2c88d-98b2-99a4-419f-c7235b2cf960@suse.com>","list_archive_url":null,"date":"2022-10-14T14:11:35","name":"x86: properly decode EVEX.W for AVX512_4{FMAPS,VNNIW} insns","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9fd2c88d-98b2-99a4-419f-c7235b2cf960@suse.com/mbox/"},{"id":2981,"url":"https://patchwork.plctlab.org/api/1.2/patches/2981/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0uLzalqjm4C87GN@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-16T04:42:53","name":"PowerPC se_rfmci and VLE, SPE2 and LSP insns with -many","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0uLzalqjm4C87GN@squeak.grove.modra.org/mbox/"},{"id":3152,"url":"https://patchwork.plctlab.org/api/1.2/patches/3152/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221016232419.1135-1-mark@harmstone.com/","msgid":"<20221016232419.1135-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-16T23:24:18","name":"[v5,1/2] ld: Add --pdb option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221016232419.1135-1-mark@harmstone.com/mbox/"},{"id":3151,"url":"https://patchwork.plctlab.org/api/1.2/patches/3151/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221016232419.1135-2-mark@harmstone.com/","msgid":"<20221016232419.1135-2-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-16T23:24:19","name":"[v5,2/2] ld: Add minimal pdb generation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221016232419.1135-2-mark@harmstone.com/mbox/"},{"id":3258,"url":"https://patchwork.plctlab.org/api/1.2/patches/3258/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/19c08747-fa5b-1e67-3dd2-c891a2c0c1fa@suse.com/","msgid":"<19c08747-fa5b-1e67-3dd2-c891a2c0c1fa@suse.com>","list_archive_url":null,"date":"2022-10-17T07:44:51","name":"x86: correct CPU_AMX_{BF16,INT8}_FLAGS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/19c08747-fa5b-1e67-3dd2-c891a2c0c1fa@suse.com/mbox/"},{"id":3272,"url":"https://patchwork.plctlab.org/api/1.2/patches/3272/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/85dd526c-d3a7-72dc-5444-ed5573eebec1@suse.com/","msgid":"<85dd526c-d3a7-72dc-5444-ed5573eebec1@suse.com>","list_archive_url":null,"date":"2022-10-17T08:30:12","name":"x86: generalize gas documentation for disabling of ISA extensions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/85dd526c-d3a7-72dc-5444-ed5573eebec1@suse.com/mbox/"},{"id":3759,"url":"https://patchwork.plctlab.org/api/1.2/patches/3759/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-2-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-2-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:15:58","name":"[V2,01/15] sframe.h: Add SFrame format definition","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-2-indu.bhagat@oracle.com/mbox/"},{"id":3762,"url":"https://patchwork.plctlab.org/api/1.2/patches/3762/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-3-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-3-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:15:59","name":"[V2,02/15] gas: add new command line option --gsframe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-3-indu.bhagat@oracle.com/mbox/"},{"id":3761,"url":"https://patchwork.plctlab.org/api/1.2/patches/3761/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-4-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-4-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:00","name":"[V2,03/15] gas: generate .sframe from CFI directives","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-4-indu.bhagat@oracle.com/mbox/"},{"id":3760,"url":"https://patchwork.plctlab.org/api/1.2/patches/3760/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-5-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-5-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:01","name":"[V2,04/15] gas: testsuite: add new tests for SFrame unwind info","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-5-indu.bhagat@oracle.com/mbox/"},{"id":3764,"url":"https://patchwork.plctlab.org/api/1.2/patches/3764/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-6-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-6-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:02","name":"[V2,05/15] libsframe: add the SFrame library","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-6-indu.bhagat@oracle.com/mbox/"},{"id":3766,"url":"https://patchwork.plctlab.org/api/1.2/patches/3766/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-7-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-7-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:03","name":"[V2,06/15] bfd: linker: merge .sframe sections","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-7-indu.bhagat@oracle.com/mbox/"},{"id":3763,"url":"https://patchwork.plctlab.org/api/1.2/patches/3763/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-8-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-8-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:04","name":"[V2,07/15] readelf/objdump: support for SFrame section","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-8-indu.bhagat@oracle.com/mbox/"},{"id":3765,"url":"https://patchwork.plctlab.org/api/1.2/patches/3765/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-9-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-9-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:05","name":"[V2,08/15] unwinder: generate backtrace using SFrame format","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-9-indu.bhagat@oracle.com/mbox/"},{"id":3770,"url":"https://patchwork.plctlab.org/api/1.2/patches/3770/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-10-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-10-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:06","name":"[V2,09/15] unwinder: Add SFrame unwinder tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-10-indu.bhagat@oracle.com/mbox/"},{"id":3769,"url":"https://patchwork.plctlab.org/api/1.2/patches/3769/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-11-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-11-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:07","name":"[V2,10/15] gdb: sim: buildsystem changes to accommodate libsframe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-11-indu.bhagat@oracle.com/mbox/"},{"id":3771,"url":"https://patchwork.plctlab.org/api/1.2/patches/3771/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-12-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-12-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:08","name":"[V2,11/15] libctf: add libsframe to LDFLAGS and LIBS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-12-indu.bhagat@oracle.com/mbox/"},{"id":3768,"url":"https://patchwork.plctlab.org/api/1.2/patches/3768/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-13-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-13-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:09","name":"[V2,12/15] src-release.sh: Add libsframe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-13-indu.bhagat@oracle.com/mbox/"},{"id":3767,"url":"https://patchwork.plctlab.org/api/1.2/patches/3767/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-14-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-14-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:10","name":"[V2,13/15] binutils/NEWS: add text for SFrame support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-14-indu.bhagat@oracle.com/mbox/"},{"id":3772,"url":"https://patchwork.plctlab.org/api/1.2/patches/3772/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-15-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-15-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:11","name":"[V2,14/15] gas/NEWS: add text about new command line option and SFrame support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-15-indu.bhagat@oracle.com/mbox/"},{"id":3773,"url":"https://patchwork.plctlab.org/api/1.2/patches/3773/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-16-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-16-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:12","name":"[V2,15/15] doc: add SFrame spec file","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-16-indu.bhagat@oracle.com/mbox/"},{"id":3999,"url":"https://patchwork.plctlab.org/api/1.2/patches/3999/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221018081205.17880-1-krebbel@linux.ibm.com/","msgid":"<20221018081205.17880-1-krebbel@linux.ibm.com>","list_archive_url":null,"date":"2022-10-18T08:12:05","name":"[1/1] IBM zSystems: Issue error for *DBL relocs on misaligned symbols","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221018081205.17880-1-krebbel@linux.ibm.com/mbox/"},{"id":4141,"url":"https://patchwork.plctlab.org/api/1.2/patches/4141/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/baffaf673f17692b7bcbd604b31800b189988596.camel@espressif.com/","msgid":"","list_archive_url":null,"date":"2022-10-18T12:12:07","name":"xtensa: use definitions from xtensa-config.h","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/baffaf673f17692b7bcbd604b31800b189988596.camel@espressif.com/mbox/"},{"id":4272,"url":"https://patchwork.plctlab.org/api/1.2/patches/4272/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221018174914.470062-1-hjl.tools@gmail.com/","msgid":"<20221018174914.470062-1-hjl.tools@gmail.com>","list_archive_url":null,"date":"2022-10-18T17:49:14","name":"x86: Disable AVX-VNNI when disabling AVX2","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221018174914.470062-1-hjl.tools@gmail.com/mbox/"},{"id":4998,"url":"https://patchwork.plctlab.org/api/1.2/patches/4998/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c2f76e95-09f6-1d92-7ef4-38a3c2955fcd@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-19T09:52:46","name":"x86: re-work AVX-VNNI support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c2f76e95-09f6-1d92-7ef4-38a3c2955fcd@suse.com/mbox/"},{"id":5276,"url":"https://patchwork.plctlab.org/api/1.2/patches/5276/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0/lLtlKqqsmAx0s@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-19T11:53:18","name":"Fix addr2line test for ppc64 elfv1 and mingw","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0/lLtlKqqsmAx0s@squeak.grove.modra.org/mbox/"},{"id":5424,"url":"https://patchwork.plctlab.org/api/1.2/patches/5424/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/07bfebbf3843b47e13d82d4fa16eb14fec942ef7.1666184962.git.research_trasio@irq.a4lg.com/","msgid":"<07bfebbf3843b47e13d82d4fa16eb14fec942ef7.1666184962.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:09:54","name":"binutils: Remove unused substitution PROGRAM","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/07bfebbf3843b47e13d82d4fa16eb14fec942ef7.1666184962.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5433,"url":"https://patchwork.plctlab.org/api/1.2/patches/5433/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2fa7ff719223232402e82a9c91331aea22ace1bb.1666185116.git.research_trasio@irq.a4lg.com/","msgid":"<2fa7ff719223232402e82a9c91331aea22ace1bb.1666185116.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:11:55","name":"[v2,1/8] RISC-V: Add a space at the end of pinfo","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2fa7ff719223232402e82a9c91331aea22ace1bb.1666185116.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5435,"url":"https://patchwork.plctlab.org/api/1.2/patches/5435/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1b30cce5db2cce3b8edca42ab5da114d0b8c9e93.1666185116.git.research_trasio@irq.a4lg.com/","msgid":"<1b30cce5db2cce3b8edca42ab5da114d0b8c9e93.1666185116.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:11:56","name":"[v2,2/8] RISC-V: Fix obvious misalignments ('\''Zbb'\''/'\''Zba'\'')","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1b30cce5db2cce3b8edca42ab5da114d0b8c9e93.1666185116.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5437,"url":"https://patchwork.plctlab.org/api/1.2/patches/5437/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6b0857aa1a2d15ca1cf00b4dcaae0032efbb88ff.1666185116.git.research_trasio@irq.a4lg.com/","msgid":"<6b0857aa1a2d15ca1cf00b4dcaae0032efbb88ff.1666185116.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:11:57","name":"[v2,3/8] RISC-V: Remove spaces in opcode entries","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6b0857aa1a2d15ca1cf00b4dcaae0032efbb88ff.1666185116.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5436,"url":"https://patchwork.plctlab.org/api/1.2/patches/5436/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/889d956caac0f2e95543a14afaeed97188ce384c.1666185116.git.research_trasio@irq.a4lg.com/","msgid":"<889d956caac0f2e95543a14afaeed97188ce384c.1666185116.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:11:58","name":"[v2,4/8] RISC-V: Remove unused instruction macros","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/889d956caac0f2e95543a14afaeed97188ce384c.1666185116.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5440,"url":"https://patchwork.plctlab.org/api/1.2/patches/5440/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8f226ee20d8a5ef6ad7b6c4408b44794a99d542a.1666185116.git.research_trasio@irq.a4lg.com/","msgid":"<8f226ee20d8a5ef6ad7b6c4408b44794a99d542a.1666185116.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:11:59","name":"[v2,5/8] RISC-V: Complete tidying up with SCALL and SBREAK","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8f226ee20d8a5ef6ad7b6c4408b44794a99d542a.1666185116.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5442,"url":"https://patchwork.plctlab.org/api/1.2/patches/5442/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4070184c454a05a39adf0790951e5856e6b2ecb6.1666185116.git.research_trasio@irq.a4lg.com/","msgid":"<4070184c454a05a39adf0790951e5856e6b2ecb6.1666185116.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:12:00","name":"[v2,6/8] RISC-V: Tidying up with fmv.w.x and fmv.x.w","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4070184c454a05a39adf0790951e5856e6b2ecb6.1666185116.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5438,"url":"https://patchwork.plctlab.org/api/1.2/patches/5438/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c1ccda3e7c8fb297eda46dab3936d5c5977178fc.1666185116.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-19T13:12:01","name":"[v2,7/8] RISC-V: Make alias instructions aliases","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c1ccda3e7c8fb297eda46dab3936d5c5977178fc.1666185116.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5441,"url":"https://patchwork.plctlab.org/api/1.2/patches/5441/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/413cfca82c7e8d8a2e977dfda9135903c9cb7c57.1666185116.git.research_trasio@irq.a4lg.com/","msgid":"<413cfca82c7e8d8a2e977dfda9135903c9cb7c57.1666185116.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:12:02","name":"[v2,8/8] RISC-V: Use defined mask and match values","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/413cfca82c7e8d8a2e977dfda9135903c9cb7c57.1666185116.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5439,"url":"https://patchwork.plctlab.org/api/1.2/patches/5439/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/345c5c3b3a53eab04a1e6e91197de2642095c94f.1666185237.git.research_trasio@irq.a4lg.com/","msgid":"<345c5c3b3a53eab04a1e6e91197de2642095c94f.1666185237.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:14:01","name":"RISC-V: Remove RV32EF conflict","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/345c5c3b3a53eab04a1e6e91197de2642095c94f.1666185237.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5616,"url":"https://patchwork.plctlab.org/api/1.2/patches/5616/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019145608.45213-5-haochen.jiang@intel.com/","msgid":"<20221019145608.45213-5-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T14:56:02","name":"[04/10] Support Intel CMPccXADD","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019145608.45213-5-haochen.jiang@intel.com/mbox/"},{"id":5614,"url":"https://patchwork.plctlab.org/api/1.2/patches/5614/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019145608.45213-6-haochen.jiang@intel.com/","msgid":"<20221019145608.45213-6-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T14:56:03","name":"[05/10] Add handler for more i386_cpu_flags","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019145608.45213-6-haochen.jiang@intel.com/mbox/"},{"id":5672,"url":"https://patchwork.plctlab.org/api/1.2/patches/5672/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-2-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-2-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:25","name":"[01/10] Support Intel AVX-IFMA","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-2-haochen.jiang@intel.com/mbox/"},{"id":5691,"url":"https://patchwork.plctlab.org/api/1.2/patches/5691/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-3-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-3-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:26","name":"[02/10] Support Intel AVX-VNNI-INT8","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-3-haochen.jiang@intel.com/mbox/"},{"id":5690,"url":"https://patchwork.plctlab.org/api/1.2/patches/5690/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-4-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-4-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:27","name":"[03/10] Support Intel AVX-NE-CONVERT","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-4-haochen.jiang@intel.com/mbox/"},{"id":5689,"url":"https://patchwork.plctlab.org/api/1.2/patches/5689/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-5-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-5-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:28","name":"[04/10] Support Intel CMPccXADD","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-5-haochen.jiang@intel.com/mbox/"},{"id":5676,"url":"https://patchwork.plctlab.org/api/1.2/patches/5676/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-6-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-6-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:29","name":"[05/10] Add handler for more i386_cpu_flags","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-6-haochen.jiang@intel.com/mbox/"},{"id":5677,"url":"https://patchwork.plctlab.org/api/1.2/patches/5677/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-7-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-7-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:30","name":"[06/10] Support Intel RAO-INT","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-7-haochen.jiang@intel.com/mbox/"},{"id":5681,"url":"https://patchwork.plctlab.org/api/1.2/patches/5681/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-8-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-8-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:31","name":"[07/10] Support Intel WRMSRNS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-8-haochen.jiang@intel.com/mbox/"},{"id":5682,"url":"https://patchwork.plctlab.org/api/1.2/patches/5682/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-9-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-9-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:32","name":"[08/10] Support Intel MSRLIST","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-9-haochen.jiang@intel.com/mbox/"},{"id":5673,"url":"https://patchwork.plctlab.org/api/1.2/patches/5673/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-10-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-10-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:33","name":"[09/10] Support Intel AMX-FP16","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-10-haochen.jiang@intel.com/mbox/"},{"id":5686,"url":"https://patchwork.plctlab.org/api/1.2/patches/5686/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-11-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-11-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:34","name":"[10/10] Support Intel PREFETCHI","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-11-haochen.jiang@intel.com/mbox/"},{"id":5940,"url":"https://patchwork.plctlab.org/api/1.2/patches/5940/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1CMrFUC8d9lC/NL@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-19T23:47:56","name":"Obsolete beos","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1CMrFUC8d9lC/NL@squeak.grove.modra.org/mbox/"},{"id":6080,"url":"https://patchwork.plctlab.org/api/1.2/patches/6080/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8b99d666e78ba5b9d32c7889a2161c70b3da88df.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<8b99d666e78ba5b9d32c7889a2161c70b3da88df.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:25:47","name":"[01/40] gdb/unittests: PR28413, suppress warnings generated by Gnulib","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8b99d666e78ba5b9d32c7889a2161c70b3da88df.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6081,"url":"https://patchwork.plctlab.org/api/1.2/patches/6081/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b05adb17e401d621dbdad791281bc7af7806906e.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-20T09:25:48","name":"[02/40] sim: Check known getrusage declaration existence","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b05adb17e401d621dbdad791281bc7af7806906e.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6083,"url":"https://patchwork.plctlab.org/api/1.2/patches/6083/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/796962a87e569feeafb5ef636de3c79000ae152c.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<796962a87e569feeafb5ef636de3c79000ae152c.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:25:49","name":"[03/40] sim/aarch64: Remove unused functions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/796962a87e569feeafb5ef636de3c79000ae152c.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6084,"url":"https://patchwork.plctlab.org/api/1.2/patches/6084/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/65223c79fdfd7faf132275415cd9da9852c5bec3.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<65223c79fdfd7faf132275415cd9da9852c5bec3.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:25:50","name":"[04/40] cpu/cris: Initialize some variables on CRIS CPU","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/65223c79fdfd7faf132275415cd9da9852c5bec3.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6082,"url":"https://patchwork.plctlab.org/api/1.2/patches/6082/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/24baefe92148f4b7968115ba13de9b0c863a65f6.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<24baefe92148f4b7968115ba13de9b0c863a65f6.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:25:51","name":"[05/40] cpu/cris: Add u-stall virtual unit to CRIS v32","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/24baefe92148f4b7968115ba13de9b0c863a65f6.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6087,"url":"https://patchwork.plctlab.org/api/1.2/patches/6087/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3904a5c3e80f8548150d8088a92059dd728c7ff8.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<3904a5c3e80f8548150d8088a92059dd728c7ff8.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:25:52","name":"[06/40] sim/cris: Move declarations of f_specific_init","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3904a5c3e80f8548150d8088a92059dd728c7ff8.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6091,"url":"https://patchwork.plctlab.org/api/1.2/patches/6091/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/69ef2d7dd519ed572511890a215a0f6d74e53384.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<69ef2d7dd519ed572511890a215a0f6d74e53384.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:25:53","name":"[07/40] sim/cris: Regenerate with CGEN","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/69ef2d7dd519ed572511890a215a0f6d74e53384.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6085,"url":"https://patchwork.plctlab.org/api/1.2/patches/6085/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/26a3eaf4f5d2e0db6977738ddfd65d82b36e38b2.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<26a3eaf4f5d2e0db6977738ddfd65d82b36e38b2.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:25:54","name":"[08/40] sim/erc32: Insert void parameter","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/26a3eaf4f5d2e0db6977738ddfd65d82b36e38b2.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6086,"url":"https://patchwork.plctlab.org/api/1.2/patches/6086/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/057c2f8392410494c3bc5dc98052246508e6a73e.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<057c2f8392410494c3bc5dc98052246508e6a73e.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:25:55","name":"[09/40] sim/erc32: Use int32_t as event callback argument","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/057c2f8392410494c3bc5dc98052246508e6a73e.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6090,"url":"https://patchwork.plctlab.org/api/1.2/patches/6090/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8c05aec20557191434485be347d37177a2ec5ff2.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<8c05aec20557191434485be347d37177a2ec5ff2.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:25:56","name":"[10/40] sim/erc32: Use int32_t as IRQ callback argument","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8c05aec20557191434485be347d37177a2ec5ff2.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6089,"url":"https://patchwork.plctlab.org/api/1.2/patches/6089/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/afd7757aae21743c29f2aa4135a23b31d4959e9b.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-20T09:25:57","name":"[11/40] cpu/frv: Initialize some variables","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/afd7757aae21743c29f2aa4135a23b31d4959e9b.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6088,"url":"https://patchwork.plctlab.org/api/1.2/patches/6088/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/021dbd238af5dfe74523ed229d2156a155a6bb9e.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<021dbd238af5dfe74523ed229d2156a155a6bb9e.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:25:58","name":"[12/40] sim/frv: Initialize nesr variable","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/021dbd238af5dfe74523ed229d2156a155a6bb9e.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6093,"url":"https://patchwork.plctlab.org/api/1.2/patches/6093/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/51a03f7097921cc48954210cf99e370ae8982ec8.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<51a03f7097921cc48954210cf99e370ae8982ec8.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:25:59","name":"[13/40] sim/frv: Initialize some variables","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/51a03f7097921cc48954210cf99e370ae8982ec8.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6092,"url":"https://patchwork.plctlab.org/api/1.2/patches/6092/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e1baa1be3601612266dc6ae0bdde8426ff2a42c8.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-20T09:26:00","name":"[14/40] sim/frv: Add explicit casts","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e1baa1be3601612266dc6ae0bdde8426ff2a42c8.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6095,"url":"https://patchwork.plctlab.org/api/1.2/patches/6095/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5ab303a5bdfc1da7832f8fa22f57678c9ef1a5fa.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<5ab303a5bdfc1da7832f8fa22f57678c9ef1a5fa.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:26:01","name":"[15/40] sim/h8300: Add \"+ 0x0\" to avoid self-assignments","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5ab303a5bdfc1da7832f8fa22f57678c9ef1a5fa.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6101,"url":"https://patchwork.plctlab.org/api/1.2/patches/6101/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ddff80db3328a2286fe6fbc1240d2abc1e3813eb.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-20T09:26:02","name":"[16/40] sim/lm32: fix some missing function declaration warnings","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ddff80db3328a2286fe6fbc1240d2abc1e3813eb.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6094,"url":"https://patchwork.plctlab.org/api/1.2/patches/6094/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e094b1379231d9ffb59a78cfebbcc84634c779c6.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-20T09:26:03","name":"[17/40] sim/lm32: Add explicit casts","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e094b1379231d9ffb59a78cfebbcc84634c779c6.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6141,"url":"https://patchwork.plctlab.org/api/1.2/patches/6141/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/cabebead-489b-528c-580e-933832417474@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-20T10:25:51","name":"[1/3] x86: emit {evex} prefix when disassembling ambiguous AVX512VL insns","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/cabebead-489b-528c-580e-933832417474@suse.com/mbox/"},{"id":6143,"url":"https://patchwork.plctlab.org/api/1.2/patches/6143/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a032d61c-63a0-23d1-331f-619a2b8bbde3@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-20T10:26:15","name":"[2/3] x86: consolidate VAES tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a032d61c-63a0-23d1-331f-619a2b8bbde3@suse.com/mbox/"},{"id":6142,"url":"https://patchwork.plctlab.org/api/1.2/patches/6142/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7ff09c86-2de7-dc34-3183-5187de3df5ac@suse.com/","msgid":"<7ff09c86-2de7-dc34-3183-5187de3df5ac@suse.com>","list_archive_url":null,"date":"2022-10-20T10:26:40","name":"[3/3] x86: consolidate VPCLMUL tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7ff09c86-2de7-dc34-3183-5187de3df5ac@suse.com/mbox/"},{"id":6228,"url":"https://patchwork.plctlab.org/api/1.2/patches/6228/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.LSU.2.20.2210201432170.29399@wotan.suse.de/","msgid":"","list_archive_url":null,"date":"2022-10-20T14:42:25","name":"x86-64: Use only one default max-page-size","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.LSU.2.20.2210201432170.29399@wotan.suse.de/mbox/"},{"id":6229,"url":"https://patchwork.plctlab.org/api/1.2/patches/6229/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221020144351.1398099-1-chigot@adacore.com/","msgid":"<20221020144351.1398099-1-chigot@adacore.com>","list_archive_url":null,"date":"2022-10-20T14:43:50","name":"[1/2] ld/testsuite: skip ld-elf/exclude when -shared is not supported","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221020144351.1398099-1-chigot@adacore.com/mbox/"},{"id":6230,"url":"https://patchwork.plctlab.org/api/1.2/patches/6230/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221020144351.1398099-2-chigot@adacore.com/","msgid":"<20221020144351.1398099-2-chigot@adacore.com>","list_archive_url":null,"date":"2022-10-20T14:43:51","name":"[2/2] ld/testsuite: adjust ld-arm to run shared tests only when supported","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221020144351.1398099-2-chigot@adacore.com/mbox/"},{"id":6236,"url":"https://patchwork.plctlab.org/api/1.2/patches/6236/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221020151027.GA1300@delia.home/","msgid":"<20221020151027.GA1300@delia.home>","list_archive_url":null,"date":"2022-10-20T15:10:28","name":"[RFC,top-level] Add configure test-case","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221020151027.GA1300@delia.home/mbox/"},{"id":6286,"url":"https://patchwork.plctlab.org/api/1.2/patches/6286/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221020162911.1113338-1-hjl.tools@gmail.com/","msgid":"<20221020162911.1113338-1-hjl.tools@gmail.com>","list_archive_url":null,"date":"2022-10-20T16:29:11","name":"x86: Check VEX/EVEX encoding before checking vector operands","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221020162911.1113338-1-hjl.tools@gmail.com/mbox/"},{"id":7884,"url":"https://patchwork.plctlab.org/api/1.2/patches/7884/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7e53b7980f2b3b74d2250bc87f5db94b1d888a2d.camel@espressif.com/","msgid":"<7e53b7980f2b3b74d2250bc87f5db94b1d888a2d.camel@espressif.com>","list_archive_url":null,"date":"2022-10-22T12:53:54","name":"[1/5] bfd: xtensa: move common code from ld and gas","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7e53b7980f2b3b74d2250bc87f5db94b1d888a2d.camel@espressif.com/mbox/"},{"id":7885,"url":"https://patchwork.plctlab.org/api/1.2/patches/7885/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/63f2699e6ef3e6d1ca415a6ed1187d4f64297521.camel@espressif.com/","msgid":"<63f2699e6ef3e6d1ca415a6ed1187d4f64297521.camel@espressif.com>","list_archive_url":null,"date":"2022-10-22T12:55:16","name":"[2/5] gas: xtensa: add endianness, loops, booleans options","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/63f2699e6ef3e6d1ca415a6ed1187d4f64297521.camel@espressif.com/mbox/"},{"id":7886,"url":"https://patchwork.plctlab.org/api/1.2/patches/7886/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/34d2f747237aeeda595560cfded8096d9bd1c28c.camel@espressif.com/","msgid":"<34d2f747237aeeda595560cfded8096d9bd1c28c.camel@espressif.com>","list_archive_url":null,"date":"2022-10-22T12:56:02","name":"[3/5] ld: xtensa: use default LD command line options for endianness","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/34d2f747237aeeda595560cfded8096d9bd1c28c.camel@espressif.com/mbox/"},{"id":7891,"url":"https://patchwork.plctlab.org/api/1.2/patches/7891/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/535b6208c1718b9acf3258575e1ebc0a65af9f07.camel@espressif.com/","msgid":"<535b6208c1718b9acf3258575e1ebc0a65af9f07.camel@espressif.com>","list_archive_url":null,"date":"2022-10-22T13:56:44","name":"[5/5] gdb: xtensa: add support for esp32, esp32s2, esp32s3 isa-modules","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/535b6208c1718b9acf3258575e1ebc0a65af9f07.camel@espressif.com/mbox/"},{"id":10456,"url":"https://patchwork.plctlab.org/api/1.2/patches/10456/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221025013347.68282-1-nelson@rivosinc.com/","msgid":"<20221025013347.68282-1-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-10-25T01:33:46","name":"[committed,1/2] RISC-V: Improve link time complexity.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221025013347.68282-1-nelson@rivosinc.com/mbox/"},{"id":10454,"url":"https://patchwork.plctlab.org/api/1.2/patches/10454/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221025013347.68282-2-nelson@rivosinc.com/","msgid":"<20221025013347.68282-2-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-10-25T01:33:47","name":"[committed,2/2] RISC-V: Should reset `again'\'' flag for _bfd_riscv_relax_pc.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221025013347.68282-2-nelson@rivosinc.com/mbox/"},{"id":10536,"url":"https://patchwork.plctlab.org/api/1.2/patches/10536/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/bb7b87e4-1893-5c86-4a14-92bafc818b03@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-25T07:24:56","name":"[v5,1/8] x86: constify parse_insn()'\''s input","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/bb7b87e4-1893-5c86-4a14-92bafc818b03@suse.com/mbox/"},{"id":10537,"url":"https://patchwork.plctlab.org/api/1.2/patches/10537/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b9273ae6-0218-54f8-5374-b265ed13b71a@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-25T07:25:26","name":"[v5,1/8] x86: introduce Pass2 insn attribute","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b9273ae6-0218-54f8-5374-b265ed13b71a@suse.com/mbox/"},{"id":10541,"url":"https://patchwork.plctlab.org/api/1.2/patches/10541/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7250dab9-e218-e6dd-4c74-23da9f611ab4@suse.com/","msgid":"<7250dab9-e218-e6dd-4c74-23da9f611ab4@suse.com>","list_archive_url":null,"date":"2022-10-25T07:26:11","name":"[v5,3/8] x86: re-work insn/suffix recognition","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7250dab9-e218-e6dd-4c74-23da9f611ab4@suse.com/mbox/"},{"id":10540,"url":"https://patchwork.plctlab.org/api/1.2/patches/10540/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/13fc630f-e116-0099-5c9e-2697df6519d7@suse.com/","msgid":"<13fc630f-e116-0099-5c9e-2697df6519d7@suse.com>","list_archive_url":null,"date":"2022-10-25T07:26:40","name":"[v5,4/8] ix86: don'\''t recognize/derive Q suffix in the common case","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/13fc630f-e116-0099-5c9e-2697df6519d7@suse.com/mbox/"},{"id":10543,"url":"https://patchwork.plctlab.org/api/1.2/patches/10543/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/74db429d-d203-eab8-4ae1-18b9ad416b02@suse.com/","msgid":"<74db429d-d203-eab8-4ae1-18b9ad416b02@suse.com>","list_archive_url":null,"date":"2022-10-25T07:27:11","name":"[v5,5/8] x86-64: allow HLE store of accumulator to absolute 32-bit address","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/74db429d-d203-eab8-4ae1-18b9ad416b02@suse.com/mbox/"},{"id":10542,"url":"https://patchwork.plctlab.org/api/1.2/patches/10542/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2e2f7841-de4e-b5de-e8d9-a47a6a4113c8@suse.com/","msgid":"<2e2f7841-de4e-b5de-e8d9-a47a6a4113c8@suse.com>","list_archive_url":null,"date":"2022-10-25T07:27:35","name":"[v5,6/8] x86: move bad-use-of-TLS-reloc check","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2e2f7841-de4e-b5de-e8d9-a47a6a4113c8@suse.com/mbox/"},{"id":10545,"url":"https://patchwork.plctlab.org/api/1.2/patches/10545/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/421bc96e-7591-6980-48e9-5af8c8b0775a@suse.com/","msgid":"<421bc96e-7591-6980-48e9-5af8c8b0775a@suse.com>","list_archive_url":null,"date":"2022-10-25T07:28:27","name":"[v5,7/8] x86: drop (now) stray IsString","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/421bc96e-7591-6980-48e9-5af8c8b0775a@suse.com/mbox/"},{"id":10546,"url":"https://patchwork.plctlab.org/api/1.2/patches/10546/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/06ff83d4-4633-a07b-70e5-a8e049981dd4@suse.com/","msgid":"<06ff83d4-4633-a07b-70e5-a8e049981dd4@suse.com>","list_archive_url":null,"date":"2022-10-25T07:29:18","name":"[v5,8/8] x86: further re-work insn/suffix recognition to also cover MOVSX","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/06ff83d4-4633-a07b-70e5-a8e049981dd4@suse.com/mbox/"},{"id":10777,"url":"https://patchwork.plctlab.org/api/1.2/patches/10777/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6a8e7a71acccd0efb9789dfb3edfa307e83bdaa1.1666702934.git.research_trasio@irq.a4lg.com/","msgid":"<6a8e7a71acccd0efb9789dfb3edfa307e83bdaa1.1666702934.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-25T13:04:02","name":"[RFC] RISC-V: Allocate \"various\" operand type","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6a8e7a71acccd0efb9789dfb3edfa307e83bdaa1.1666702934.git.research_trasio@irq.a4lg.com/mbox/"},{"id":11062,"url":"https://patchwork.plctlab.org/api/1.2/patches/11062/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jAhwbXhxJHL66v@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-26T05:07:19","name":"PR29720, objdump -S crashes if build-id is missing","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jAhwbXhxJHL66v@squeak.grove.modra.org/mbox/"},{"id":11063,"url":"https://patchwork.plctlab.org/api/1.2/patches/11063/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jAxD+NxpMIah6s@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-26T05:08:20","name":"som.c buffer overflow","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jAxD+NxpMIah6s@squeak.grove.modra.org/mbox/"},{"id":11064,"url":"https://patchwork.plctlab.org/api/1.2/patches/11064/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jBYw4lfRQfOZhi@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-26T05:10:59","name":"som.c reloc sanity checking","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jBYw4lfRQfOZhi@squeak.grove.modra.org/mbox/"},{"id":11080,"url":"https://patchwork.plctlab.org/api/1.2/patches/11080/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jY7hygm01PelCY@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-26T06:51:26","name":"segfault in objdump.c reloc_at","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jY7hygm01PelCY@squeak.grove.modra.org/mbox/"},{"id":11081,"url":"https://patchwork.plctlab.org/api/1.2/patches/11081/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jZWIeIvCCYm9/g@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-26T06:53:12","name":"Correct ELF reloc size sanity check","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jZWIeIvCCYm9/g@squeak.grove.modra.org/mbox/"},{"id":11082,"url":"https://patchwork.plctlab.org/api/1.2/patches/11082/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221026070009.3663574-1-ysato@users.sourceforge.jp/","msgid":"<20221026070009.3663574-1-ysato@users.sourceforge.jp>","list_archive_url":null,"date":"2022-10-26T07:00:09","name":"opcodes: RX fix invalid output.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221026070009.3663574-1-ysato@users.sourceforge.jp/mbox/"},{"id":11089,"url":"https://patchwork.plctlab.org/api/1.2/patches/11089/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jhW48kuVC8Ig2d@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-26T07:27:23","name":"buffer overflow in _bfd_XX_print_ce_compressed_pdata","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jhW48kuVC8Ig2d@squeak.grove.modra.org/mbox/"},{"id":11157,"url":"https://patchwork.plctlab.org/api/1.2/patches/11157/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c52dbd16-7e1b-c356-7a92-1ff089564ef7@suse.cz/","msgid":"","list_archive_url":null,"date":"2022-10-26T08:47:09","name":"tests: use canonical option name","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c52dbd16-7e1b-c356-7a92-1ff089564ef7@suse.cz/mbox/"},{"id":11526,"url":"https://patchwork.plctlab.org/api/1.2/patches/11526/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027031915.4013-1-lifang_xia@linux.alibaba.com/","msgid":"<20221027031915.4013-1-lifang_xia@linux.alibaba.com>","list_archive_url":null,"date":"2022-10-27T03:19:15","name":"[v2] RISC-V: Optimize relax of GP/call with max_alignment.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027031915.4013-1-lifang_xia@linux.alibaba.com/mbox/"},{"id":11619,"url":"https://patchwork.plctlab.org/api/1.2/patches/11619/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9df9d9e5bb4c7594b76c40613a349b4d2364e9c5.1666854355.git.research_trasio@irq.a4lg.com/","msgid":"<9df9d9e5bb4c7594b76c40613a349b4d2364e9c5.1666854355.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-27T07:06:01","name":"include: Define macro to ignore -Wdeprecated-declarations on GCC","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9df9d9e5bb4c7594b76c40613a349b4d2364e9c5.1666854355.git.research_trasio@irq.a4lg.com/mbox/"},{"id":11627,"url":"https://patchwork.plctlab.org/api/1.2/patches/11627/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1o06O9Pp8ncCsOw@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-27T07:36:08","name":"Fuzzed files in archives","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1o06O9Pp8ncCsOw@squeak.grove.modra.org/mbox/"},{"id":11658,"url":"https://patchwork.plctlab.org/api/1.2/patches/11658/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027084808.37252-1-nelson@rivosinc.com/","msgid":"<20221027084808.37252-1-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-10-27T08:48:08","name":"[committed] RISC-V: Fix build failures for -Werror=sign-compare.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027084808.37252-1-nelson@rivosinc.com/mbox/"},{"id":11921,"url":"https://patchwork.plctlab.org/api/1.2/patches/11921/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027190052.10536-1-mark@harmstone.com/","msgid":"<20221027190052.10536-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-27T19:00:51","name":"[1/2] ld: Add section header stream to PDB files","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027190052.10536-1-mark@harmstone.com/mbox/"},{"id":11922,"url":"https://patchwork.plctlab.org/api/1.2/patches/11922/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027190052.10536-2-mark@harmstone.com/","msgid":"<20221027190052.10536-2-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-27T19:00:52","name":"[2/2] ld: Add publics stream to PDB files","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027190052.10536-2-mark@harmstone.com/mbox/"},{"id":11965,"url":"https://patchwork.plctlab.org/api/1.2/patches/11965/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027202719.32497-1-palmer@rivosinc.com/","msgid":"<20221027202719.32497-1-palmer@rivosinc.com>","list_archive_url":null,"date":"2022-10-27T20:27:18","name":"[1/2] gas: NEWS: Add a missing newline","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027202719.32497-1-palmer@rivosinc.com/mbox/"},{"id":11966,"url":"https://patchwork.plctlab.org/api/1.2/patches/11966/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027202719.32497-2-palmer@rivosinc.com/","msgid":"<20221027202719.32497-2-palmer@rivosinc.com>","list_archive_url":null,"date":"2022-10-27T20:27:19","name":"[2/2] gas: NEWS: Note support for RISC-V Zawrs","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027202719.32497-2-palmer@rivosinc.com/mbox/"},{"id":12016,"url":"https://patchwork.plctlab.org/api/1.2/patches/12016/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/21ec9a18-fa89-0828-f625-499680022ec7@linux.ibm.com/","msgid":"<21ec9a18-fa89-0828-f625-499680022ec7@linux.ibm.com>","list_archive_url":null,"date":"2022-10-28T00:35:19","name":"[COMMITTED] PowerPC: Add support for RFC02653 - Dense Math Facility","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/21ec9a18-fa89-0828-f625-499680022ec7@linux.ibm.com/mbox/"},{"id":12017,"url":"https://patchwork.plctlab.org/api/1.2/patches/12017/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fd94047d-a070-45a6-3840-c105391718e0@linux.ibm.com/","msgid":"","list_archive_url":null,"date":"2022-10-28T00:37:18","name":"[COMMITTED] PowerPC: Add support for RFC02658 - MMA+ Outer-Product, Instructions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fd94047d-a070-45a6-3840-c105391718e0@linux.ibm.com/mbox/"},{"id":12122,"url":"https://patchwork.plctlab.org/api/1.2/patches/12122/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ac4f3f3c7115a824f73aca6935789b14d33c9a58.1666939920.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-28T06:53:02","name":"RISC-V: Fix build failure for -Werror=maybe-uninitialized","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ac4f3f3c7115a824f73aca6935789b14d33c9a58.1666939920.git.research_trasio@irq.a4lg.com/mbox/"},{"id":12181,"url":"https://patchwork.plctlab.org/api/1.2/patches/12181/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221028093840.19164-1-nelson@rivosinc.com/","msgid":"<20221028093840.19164-1-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-10-28T09:38:40","name":"RISC-V: Added SiFive custom cache control extensions.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221028093840.19164-1-nelson@rivosinc.com/mbox/"},{"id":12211,"url":"https://patchwork.plctlab.org/api/1.2/patches/12211/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4a280588-a85b-6ed3-634b-2b9cbc128f86@suse.com/","msgid":"<4a280588-a85b-6ed3-634b-2b9cbc128f86@suse.com>","list_archive_url":null,"date":"2022-10-28T10:06:35","name":"RISC-V/gas: fix build with certain gcc versions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4a280588-a85b-6ed3-634b-2b9cbc128f86@suse.com/mbox/"},{"id":12249,"url":"https://patchwork.plctlab.org/api/1.2/patches/12249/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/eb0e1bff-675e-72db-b8b1-b0f0e50b7121@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-28T12:35:35","name":"x86: minor improvements to optimize_imm() (part III)","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/eb0e1bff-675e-72db-b8b1-b0f0e50b7121@suse.com/mbox/"},{"id":12382,"url":"https://patchwork.plctlab.org/api/1.2/patches/12382/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/17f57574936af82be381a1451eac56b3709b60bb.1666968673.git.research_trasio@irq.a4lg.com/","msgid":"<17f57574936af82be381a1451eac56b3709b60bb.1666968673.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-28T14:52:12","name":"RISC-V: Emit mapping symbol with ISA string if non-default arch is used","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/17f57574936af82be381a1451eac56b3709b60bb.1666968673.git.research_trasio@irq.a4lg.com/mbox/"},{"id":12627,"url":"https://patchwork.plctlab.org/api/1.2/patches/12627/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221029034432.49859-1-nelson@rivosinc.com/","msgid":"<20221029034432.49859-1-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-10-29T03:44:32","name":"[committed] RISC-V: Always generate mapping symbols at the start of the sections.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221029034432.49859-1-nelson@rivosinc.com/mbox/"},{"id":12629,"url":"https://patchwork.plctlab.org/api/1.2/patches/12629/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1yxgzNJg5M48uPI@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-29T04:52:19","name":"NULL dereference read in som_write_object_contents","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1yxgzNJg5M48uPI@squeak.grove.modra.org/mbox/"},{"id":12630,"url":"https://patchwork.plctlab.org/api/1.2/patches/12630/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1yxnSHLY+FeB5DQ@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-29T04:52:45","name":"Fix small objcopy memory leak","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1yxnSHLY+FeB5DQ@squeak.grove.modra.org/mbox/"},{"id":12631,"url":"https://patchwork.plctlab.org/api/1.2/patches/12631/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1yxxfpJz+Jx4KTh@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-29T04:53:25","name":"pef: sanity check before malloc","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1yxxfpJz+Jx4KTh@squeak.grove.modra.org/mbox/"},{"id":12950,"url":"https://patchwork.plctlab.org/api/1.2/patches/12950/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-2-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-2-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:36","name":"[V3,01/15] sframe.h: Add SFrame format definition","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-2-indu.bhagat@oracle.com/mbox/"},{"id":12952,"url":"https://patchwork.plctlab.org/api/1.2/patches/12952/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-3-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-3-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:37","name":"[V3,02/15] gas: add new command line option --gsframe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-3-indu.bhagat@oracle.com/mbox/"},{"id":12951,"url":"https://patchwork.plctlab.org/api/1.2/patches/12951/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-4-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-4-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:38","name":"[V3,03/15] gas: generate .sframe from CFI directives","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-4-indu.bhagat@oracle.com/mbox/"},{"id":12956,"url":"https://patchwork.plctlab.org/api/1.2/patches/12956/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-5-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-5-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:39","name":"[V3,04/15] gas: testsuite: add new tests for SFrame unwind info","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-5-indu.bhagat@oracle.com/mbox/"},{"id":12955,"url":"https://patchwork.plctlab.org/api/1.2/patches/12955/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-6-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-6-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:40","name":"[V3,05/15] libsframe: add the SFrame library","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-6-indu.bhagat@oracle.com/mbox/"},{"id":12959,"url":"https://patchwork.plctlab.org/api/1.2/patches/12959/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-7-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-7-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:41","name":"[V3,06/15] bfd: linker: merge .sframe sections","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-7-indu.bhagat@oracle.com/mbox/"},{"id":12961,"url":"https://patchwork.plctlab.org/api/1.2/patches/12961/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-8-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-8-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:42","name":"[V3,07/15] readelf/objdump: support for SFrame section","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-8-indu.bhagat@oracle.com/mbox/"},{"id":12962,"url":"https://patchwork.plctlab.org/api/1.2/patches/12962/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-9-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-9-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:43","name":"[V3,08/15] unwinder: generate backtrace using SFrame format","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-9-indu.bhagat@oracle.com/mbox/"},{"id":12963,"url":"https://patchwork.plctlab.org/api/1.2/patches/12963/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-10-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-10-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:44","name":"[V3,09/15] unwinder: Add SFrame unwinder tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-10-indu.bhagat@oracle.com/mbox/"},{"id":12964,"url":"https://patchwork.plctlab.org/api/1.2/patches/12964/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-11-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-11-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:45","name":"[V3,10/15] gdb: sim: buildsystem changes to accommodate libsframe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-11-indu.bhagat@oracle.com/mbox/"},{"id":12957,"url":"https://patchwork.plctlab.org/api/1.2/patches/12957/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-12-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-12-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:46","name":"[V3,11/15] libctf: add libsframe to LDFLAGS and LIBS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-12-indu.bhagat@oracle.com/mbox/"},{"id":12960,"url":"https://patchwork.plctlab.org/api/1.2/patches/12960/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-13-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-13-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:47","name":"[V3,12/15] src-release.sh: Add libsframe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-13-indu.bhagat@oracle.com/mbox/"},{"id":12953,"url":"https://patchwork.plctlab.org/api/1.2/patches/12953/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-14-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-14-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:48","name":"[V3,13/15] binutils/NEWS: add text for SFrame support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-14-indu.bhagat@oracle.com/mbox/"},{"id":12954,"url":"https://patchwork.plctlab.org/api/1.2/patches/12954/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-15-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-15-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:49","name":"[V3,14/15] gas/NEWS: add text about new command line option and SFrame support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-15-indu.bhagat@oracle.com/mbox/"},{"id":12958,"url":"https://patchwork.plctlab.org/api/1.2/patches/12958/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-16-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-16-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:50","name":"[V3,15/15] doc: add SFrame spec file","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-16-indu.bhagat@oracle.com/mbox/"},{"id":12988,"url":"https://patchwork.plctlab.org/api/1.2/patches/12988/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y15KFY32CyFhh/+u@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-30T09:55:33","name":"Pool section entries for DWP version 1","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y15KFY32CyFhh/+u@squeak.grove.modra.org/mbox/"},{"id":13076,"url":"https://patchwork.plctlab.org/api/1.2/patches/13076/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031001554.14615-1-mark@harmstone.com/","msgid":"<20221031001554.14615-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-31T00:15:52","name":"[v2,1/3] ld: Use %E in einfo in pdb.c","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031001554.14615-1-mark@harmstone.com/mbox/"},{"id":13078,"url":"https://patchwork.plctlab.org/api/1.2/patches/13078/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031001554.14615-2-mark@harmstone.com/","msgid":"<20221031001554.14615-2-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-31T00:15:53","name":"[v2,2/3] ld: Add section header stream to PDB files","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031001554.14615-2-mark@harmstone.com/mbox/"},{"id":13077,"url":"https://patchwork.plctlab.org/api/1.2/patches/13077/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031001554.14615-3-mark@harmstone.com/","msgid":"<20221031001554.14615-3-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-31T00:15:54","name":"[v2,3/3] ld: Add publics stream to PDB files","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031001554.14615-3-mark@harmstone.com/mbox/"},{"id":13106,"url":"https://patchwork.plctlab.org/api/1.2/patches/13106/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031030507.35588-2-haochen.jiang@intel.com/","msgid":"<20221031030507.35588-2-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-31T03:05:02","name":"[1/6] Support Intel AVX-IFMA","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031030507.35588-2-haochen.jiang@intel.com/mbox/"},{"id":13105,"url":"https://patchwork.plctlab.org/api/1.2/patches/13105/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031030507.35588-3-haochen.jiang@intel.com/","msgid":"<20221031030507.35588-3-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-31T03:05:03","name":"[2/6] Support Intel AVX-VNNI-INT8","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031030507.35588-3-haochen.jiang@intel.com/mbox/"},{"id":13103,"url":"https://patchwork.plctlab.org/api/1.2/patches/13103/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031030507.35588-4-haochen.jiang@intel.com/","msgid":"<20221031030507.35588-4-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-31T03:05:04","name":"[3/6] Support Intel CMPccXADD","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031030507.35588-4-haochen.jiang@intel.com/mbox/"},{"id":13101,"url":"https://patchwork.plctlab.org/api/1.2/patches/13101/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031030507.35588-5-haochen.jiang@intel.com/","msgid":"<20221031030507.35588-5-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-31T03:05:05","name":"[4/6] Add handler for more i386_cpu_flags","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031030507.35588-5-haochen.jiang@intel.com/mbox/"},{"id":13104,"url":"https://patchwork.plctlab.org/api/1.2/patches/13104/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031030507.35588-6-haochen.jiang@intel.com/","msgid":"<20221031030507.35588-6-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-31T03:05:06","name":"[5/6] Support Intel WRMSRNS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031030507.35588-6-haochen.jiang@intel.com/mbox/"},{"id":13102,"url":"https://patchwork.plctlab.org/api/1.2/patches/13102/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031030507.35588-7-haochen.jiang@intel.com/","msgid":"<20221031030507.35588-7-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-31T03:05:07","name":"[6/6] Support Intel MSRLIST","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031030507.35588-7-haochen.jiang@intel.com/mbox/"},{"id":13120,"url":"https://patchwork.plctlab.org/api/1.2/patches/13120/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031060601.38460-2-haochen.jiang@intel.com/","msgid":"<20221031060601.38460-2-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-31T06:06:00","name":"[1/2] i386: Add and ","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031060601.38460-2-haochen.jiang@intel.com/mbox/"},{"id":13121,"url":"https://patchwork.plctlab.org/api/1.2/patches/13121/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031060601.38460-3-haochen.jiang@intel.com/","msgid":"<20221031060601.38460-3-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-31T06:06:01","name":"[2/2] Support Intel AVX-NE-CONVERT","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031060601.38460-3-haochen.jiang@intel.com/mbox/"},{"id":13188,"url":"https://patchwork.plctlab.org/api/1.2/patches/13188/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9f6f8888-4dc1-a6b0-0590-35fc8a276369@suse.com/","msgid":"<9f6f8888-4dc1-a6b0-0590-35fc8a276369@suse.com>","list_archive_url":null,"date":"2022-10-31T10:18:20","name":"x86: drop bogus Tbyte","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9f6f8888-4dc1-a6b0-0590-35fc8a276369@suse.com/mbox/"},{"id":13213,"url":"https://patchwork.plctlab.org/api/1.2/patches/13213/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4f1aac95-fea5-2279-cb18-dfcdb51a2589@arm.com/","msgid":"<4f1aac95-fea5-2279-cb18-dfcdb51a2589@arm.com>","list_archive_url":null,"date":"2022-10-31T11:14:44","name":"aarch64: Add support for Common Short Sequence Compression extension","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4f1aac95-fea5-2279-cb18-dfcdb51a2589@arm.com/mbox/"}],"public":true,"mbox":"https://patchwork.plctlab.org/bundle/patchwork-bot/binutils-gdb_2022-10/mbox/"},{"id":7,"url":"https://patchwork.plctlab.org/api/1.2/bundles/7/","web_url":"https://patchwork.plctlab.org/bundle/patchwork-bot/binutils-gdb_2022-09/","project":{"id":2,"url":"https://patchwork.plctlab.org/api/1.2/projects/2/","name":"binutils-gdb","link_name":"binutils-gdb","list_id":"binutils.sourceware.org","list_email":"binutils@sourceware.org","web_url":"https://github.com/wangliu-iscas/Patchwork-Bundles/blob/main/binutils-gdb.md","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"name":"binutils-gdb_2022-09","owner":{"id":3,"url":"https://patchwork.plctlab.org/api/1.2/users/3/","username":"patchwork-bot","first_name":"","last_name":"","email":"ouuuleilei@gmail.com"},"patches":[{"id":1573,"url":"https://patchwork.plctlab.org/api/1.2/patches/1573/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930073211.2634-1-jiawei@iscas.ac.cn/","msgid":"<20220930073211.2634-1-jiawei@iscas.ac.cn>","list_archive_url":null,"date":"2022-09-30T07:32:11","name":"[V2] RISC-V: Add Smepmp CSR '\''mseccfg'\'' define and testcases.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930073211.2634-1-jiawei@iscas.ac.cn/mbox/"},{"id":1577,"url":"https://patchwork.plctlab.org/api/1.2/patches/1577/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/76fa0c3c-2303-ebdf-a765-ac4731581517@suse.com/","msgid":"<76fa0c3c-2303-ebdf-a765-ac4731581517@suse.com>","list_archive_url":null,"date":"2022-09-30T08:54:18","name":"objcopy: avoid \"shadowing\" of remove() function name","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/76fa0c3c-2303-ebdf-a765-ac4731581517@suse.com/mbox/"},{"id":1579,"url":"https://patchwork.plctlab.org/api/1.2/patches/1579/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930085852.71213-1-nelson@rivosinc.com/","msgid":"<20220930085852.71213-1-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-09-30T08:58:51","name":"[1/2] RISC-V: Output mapping symbols with ISA string.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930085852.71213-1-nelson@rivosinc.com/mbox/"},{"id":1578,"url":"https://patchwork.plctlab.org/api/1.2/patches/1578/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930085852.71213-2-nelson@rivosinc.com/","msgid":"<20220930085852.71213-2-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-09-30T08:58:52","name":"[2/2] RISC-V: Refer mapping symbol to R_RISCV_RELAX for rvc relaxations.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930085852.71213-2-nelson@rivosinc.com/mbox/"},{"id":1581,"url":"https://patchwork.plctlab.org/api/1.2/patches/1581/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930092058.71286-1-nelson@rivosinc.com/","msgid":"<20220930092058.71286-1-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-09-30T09:20:57","name":"[1/2] RISC-V: Output mapping symbols with ISA string.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930092058.71286-1-nelson@rivosinc.com/mbox/"},{"id":1580,"url":"https://patchwork.plctlab.org/api/1.2/patches/1580/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930092058.71286-2-nelson@rivosinc.com/","msgid":"<20220930092058.71286-2-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-09-30T09:20:58","name":"[2/2] RISC-V: Refer mapping symbol to R_RISCV_RELAX for rvc relaxations.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930092058.71286-2-nelson@rivosinc.com/mbox/"},{"id":1582,"url":"https://patchwork.plctlab.org/api/1.2/patches/1582/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5874dd79-0cf5-d65c-7ea2-13adfc799c0f@suse.com/","msgid":"<5874dd79-0cf5-d65c-7ea2-13adfc799c0f@suse.com>","list_archive_url":null,"date":"2022-09-30T09:41:29","name":"RISC-V: fix build after \"Add support for arbitrary immediate encoding formats\"","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5874dd79-0cf5-d65c-7ea2-13adfc799c0f@suse.com/mbox/"},{"id":1583,"url":"https://patchwork.plctlab.org/api/1.2/patches/1583/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/57d8ac2a-5757-3776-9924-99c17ca69938@suse.com/","msgid":"<57d8ac2a-5757-3776-9924-99c17ca69938@suse.com>","list_archive_url":null,"date":"2022-09-30T09:42:08","name":"RISC-V: fallout from \"re-arrange opcode table for consistent alias handling\"","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/57d8ac2a-5757-3776-9924-99c17ca69938@suse.com/mbox/"},{"id":1584,"url":"https://patchwork.plctlab.org/api/1.2/patches/1584/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e76ef8f7-72b9-5103-cb43-9608af01d017@suse.com/","msgid":"","list_archive_url":null,"date":"2022-09-30T09:42:50","name":"RISC-V: don'\''t cast expressions'\'' X_add_number to long in diagnostics","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e76ef8f7-72b9-5103-cb43-9608af01d017@suse.com/mbox/"},{"id":1585,"url":"https://patchwork.plctlab.org/api/1.2/patches/1585/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/61355429-24b3-17d0-ab03-6fa57ee861d5@suse.cz/","msgid":"<61355429-24b3-17d0-ab03-6fa57ee861d5@suse.cz>","list_archive_url":null,"date":"2022-09-30T09:48:52","name":"[RFC] add --enable-zstd-compressed-debug-sections configure option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/61355429-24b3-17d0-ab03-6fa57ee861d5@suse.cz/mbox/"},{"id":1586,"url":"https://patchwork.plctlab.org/api/1.2/patches/1586/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930103919.323690-1-christoph.muellner@vrull.eu/","msgid":"<20220930103919.323690-1-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2022-09-30T10:39:19","name":"RISC-V: Eliminate long-casts of X_add_number in diagnostics","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930103919.323690-1-christoph.muellner@vrull.eu/mbox/"},{"id":1590,"url":"https://patchwork.plctlab.org/api/1.2/patches/1590/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/DM6PR12MB4219C943049C6D883DEA3E55E7569@DM6PR12MB4219.namprd12.prod.outlook.com/","msgid":"","list_archive_url":null,"date":"2022-09-30T11:41:37","name":"[V2] Ignore DWARF debug information for -gsplit-dwarf with dwarf-5.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/DM6PR12MB4219C943049C6D883DEA3E55E7569@DM6PR12MB4219.namprd12.prod.outlook.com/mbox/"},{"id":1591,"url":"https://patchwork.plctlab.org/api/1.2/patches/1591/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c10321f9-d289-ef84-d263-bc278fb3d31b@suse.com/","msgid":"","list_archive_url":null,"date":"2022-09-30T11:59:04","name":"[1/4] RISC-V/gas: drop riscv_subsets static variable","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c10321f9-d289-ef84-d263-bc278fb3d31b@suse.com/mbox/"},{"id":1593,"url":"https://patchwork.plctlab.org/api/1.2/patches/1593/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3244eea0-c18c-e49a-4588-d69423130226@suse.com/","msgid":"<3244eea0-c18c-e49a-4588-d69423130226@suse.com>","list_archive_url":null,"date":"2022-09-30T11:59:23","name":"[2/4] RISC-V/gas: drop stray call to install_insn()","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3244eea0-c18c-e49a-4588-d69423130226@suse.com/mbox/"},{"id":1592,"url":"https://patchwork.plctlab.org/api/1.2/patches/1592/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/385d01fd-7e57-1f3f-1bae-30aa0c313d63@suse.com/","msgid":"<385d01fd-7e57-1f3f-1bae-30aa0c313d63@suse.com>","list_archive_url":null,"date":"2022-09-30T11:59:45","name":"[3/4] RISC-V/gas: don'\''t open-code insn_length()","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/385d01fd-7e57-1f3f-1bae-30aa0c313d63@suse.com/mbox/"},{"id":1594,"url":"https://patchwork.plctlab.org/api/1.2/patches/1594/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f5757acf-7b90-a0e3-5eea-3b97cc226930@suse.com/","msgid":"","list_archive_url":null,"date":"2022-09-30T12:00:12","name":"[4/4] RISC-V/gas: allow generating up to 176-bit instructions with .insn","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f5757acf-7b90-a0e3-5eea-3b97cc226930@suse.com/mbox/"},{"id":1596,"url":"https://patchwork.plctlab.org/api/1.2/patches/1596/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930140503.38233-1-chigot@adacore.com/","msgid":"<20220930140503.38233-1-chigot@adacore.com>","list_archive_url":null,"date":"2022-09-30T14:05:03","name":"ld/testsuite: consistently add board_ldflags when linking with GCC","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930140503.38233-1-chigot@adacore.com/mbox/"}],"public":true,"mbox":"https://patchwork.plctlab.org/bundle/patchwork-bot/binutils-gdb_2022-09/mbox/"},{"id":9,"url":"https://patchwork.plctlab.org/api/1.2/bundles/9/","web_url":"https://patchwork.plctlab.org/bundle/patchwork-bot/binutils-gdb_2022-11/","project":{"id":2,"url":"https://patchwork.plctlab.org/api/1.2/projects/2/","name":"binutils-gdb","link_name":"binutils-gdb","list_id":"binutils.sourceware.org","list_email":"binutils@sourceware.org","web_url":"https://github.com/wangliu-iscas/Patchwork-Bundles/blob/main/binutils-gdb.md","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"name":"binutils-gdb_2022-11","owner":{"id":3,"url":"https://patchwork.plctlab.org/api/1.2/users/3/","username":"patchwork-bot","first_name":"","last_name":"","email":"ouuuleilei@gmail.com"},"patches":[{"id":13337,"url":"https://patchwork.plctlab.org/api/1.2/patches/13337/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031160625.684434-1-hjl.tools@gmail.com/","msgid":"<20221031160625.684434-1-hjl.tools@gmail.com>","list_archive_url":null,"date":"2022-10-31T16:06:25","name":"x86: Silence GCC 12 warning on tc-i386.c","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031160625.684434-1-hjl.tools@gmail.com/mbox/"},{"id":13350,"url":"https://patchwork.plctlab.org/api/1.2/patches/13350/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c8d25b29-37fe-9623-a799-e67e1f991743@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-31T17:00:56","name":"x86: simplify expressions in update_imm()","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c8d25b29-37fe-9623-a799-e67e1f991743@suse.com/mbox/"},{"id":13487,"url":"https://patchwork.plctlab.org/api/1.2/patches/13487/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/CAMe9rOohVjin92PTeeiu_dvAtzYJn4dGtu5E=OxYfbyteraZWw@mail.gmail.com/","msgid":"","list_archive_url":null,"date":"2022-11-01T00:08:04","name":"binutils: Run PR binutils/26160 test","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/CAMe9rOohVjin92PTeeiu_dvAtzYJn4dGtu5E=OxYfbyteraZWw@mail.gmail.com/mbox/"},{"id":13621,"url":"https://patchwork.plctlab.org/api/1.2/patches/13621/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221101105724.1527333-1-aburgess@redhat.com/","msgid":"<20221101105724.1527333-1-aburgess@redhat.com>","list_archive_url":null,"date":"2022-11-01T10:57:24","name":"[PUSHED] opcodes/arm: silence compiler warning about uninitialized variable use","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221101105724.1527333-1-aburgess@redhat.com/mbox/"},{"id":13628,"url":"https://patchwork.plctlab.org/api/1.2/patches/13628/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221101111802.1532080-1-aburgess@redhat.com/","msgid":"<20221101111802.1532080-1-aburgess@redhat.com>","list_archive_url":null,"date":"2022-11-01T11:18:02","name":"[PUSHED] opcodes/arm: don'\''t pass non-string literal to printf like function","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221101111802.1532080-1-aburgess@redhat.com/mbox/"},{"id":13747,"url":"https://patchwork.plctlab.org/api/1.2/patches/13747/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/yw8jbkpqk6vw.fsf@arm.com/","msgid":"","list_archive_url":null,"date":"2022-11-01T15:54:11","name":"[Binutils-2.39,backport,GAS] arm: Use DWARF numbering convention for pseudo-register representation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/yw8jbkpqk6vw.fsf@arm.com/mbox/"},{"id":13993,"url":"https://patchwork.plctlab.org/api/1.2/patches/13993/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221102020752.24441-1-mark@harmstone.com/","msgid":"<20221102020752.24441-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-11-02T02:07:52","name":"ld: Add module information substream to PDB files","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221102020752.24441-1-mark@harmstone.com/mbox/"},{"id":14028,"url":"https://patchwork.plctlab.org/api/1.2/patches/14028/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221102050430.1053-1-nelson@rivosinc.com/","msgid":"<20221102050430.1053-1-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-11-02T05:04:30","name":"[committed] RISC-V: Fixed the missing $x+arch when adding odd paddings for alignment.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221102050430.1053-1-nelson@rivosinc.com/mbox/"},{"id":14043,"url":"https://patchwork.plctlab.org/api/1.2/patches/14043/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221102063046.31551-1-rjiejie@linux.alibaba.com/","msgid":"<20221102063046.31551-1-rjiejie@linux.alibaba.com>","list_archive_url":null,"date":"2022-11-02T06:30:46","name":"gas/doc/internals.texi: fix typo","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221102063046.31551-1-rjiejie@linux.alibaba.com/mbox/"},{"id":14069,"url":"https://patchwork.plctlab.org/api/1.2/patches/14069/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221102080112.33378-1-rjiejie@linux.alibaba.com/","msgid":"<20221102080112.33378-1-rjiejie@linux.alibaba.com>","list_archive_url":null,"date":"2022-11-02T08:01:12","name":"[v2] Support multiple .eh_frame sections","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221102080112.33378-1-rjiejie@linux.alibaba.com/mbox/"},{"id":14409,"url":"https://patchwork.plctlab.org/api/1.2/patches/14409/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221102172923.4009281-1-christophe.lyon@arm.com/","msgid":"<20221102172923.4009281-1-christophe.lyon@arm.com>","list_archive_url":null,"date":"2022-11-02T17:29:23","name":"arm: PR 29739 Fix typo where '\''; '\'' should not have been replaced with '\''@'\''","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221102172923.4009281-1-christophe.lyon@arm.com/mbox/"},{"id":14588,"url":"https://patchwork.plctlab.org/api/1.2/patches/14588/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221103020409.37322-1-rjiejie@linux.alibaba.com/","msgid":"<20221103020409.37322-1-rjiejie@linux.alibaba.com>","list_archive_url":null,"date":"2022-11-03T02:04:09","name":"[v3] Support multiple .eh_frame sections","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221103020409.37322-1-rjiejie@linux.alibaba.com/mbox/"},{"id":14602,"url":"https://patchwork.plctlab.org/api/1.2/patches/14602/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221103024604.614-1-mark@harmstone.com/","msgid":"<20221103024604.614-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-11-03T02:46:04","name":"[v2] ld: Add module information substream to PDB files","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221103024604.614-1-mark@harmstone.com/mbox/"},{"id":14706,"url":"https://patchwork.plctlab.org/api/1.2/patches/14706/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221103071519.3510462-1-luis.machado@arm.com/","msgid":"<20221103071519.3510462-1-luis.machado@arm.com>","list_archive_url":null,"date":"2022-11-03T07:15:19","name":"[opcodes/arm] Fix potential null pointer dereferences","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221103071519.3510462-1-luis.machado@arm.com/mbox/"},{"id":14840,"url":"https://patchwork.plctlab.org/api/1.2/patches/14840/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/283a86ebf0941f0f63dc1a590ec3d547bd5d69e8.1667478033.git.research_trasio@irq.a4lg.com/","msgid":"<283a86ebf0941f0f63dc1a590ec3d547bd5d69e8.1667478033.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-03T12:26:28","name":"[REVIEW,ONLY,1/2] NEAR-RATIFICATION RISC-V: Add '\''Ssstateen'\'' extension and its CSRs","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/283a86ebf0941f0f63dc1a590ec3d547bd5d69e8.1667478033.git.research_trasio@irq.a4lg.com/mbox/"},{"id":14841,"url":"https://patchwork.plctlab.org/api/1.2/patches/14841/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8083ad9d5339afdeb7f1ba88ee6af0665dcc76d5.1667478033.git.research_trasio@irq.a4lg.com/","msgid":"<8083ad9d5339afdeb7f1ba88ee6af0665dcc76d5.1667478033.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-03T12:26:29","name":"[REVIEW,ONLY,2/2] NEAR-RATIFICATION RISC-V: Add platform property/capability extensions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8083ad9d5339afdeb7f1ba88ee6af0665dcc76d5.1667478033.git.research_trasio@irq.a4lg.com/mbox/"},{"id":14894,"url":"https://patchwork.plctlab.org/api/1.2/patches/14894/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e53fbf5025e59fe6a3481b9c1fe37e4f6cf6e03d.1667483581.git.aburgess@redhat.com/","msgid":"","list_archive_url":null,"date":"2022-11-03T13:58:12","name":"[1/2] opcodes/mips: use .word/.short for undefined instructions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e53fbf5025e59fe6a3481b9c1fe37e4f6cf6e03d.1667483581.git.aburgess@redhat.com/mbox/"},{"id":14893,"url":"https://patchwork.plctlab.org/api/1.2/patches/14893/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ca81edb86580566b1641ad140eb2bed385160ab7.1667483581.git.aburgess@redhat.com/","msgid":"","list_archive_url":null,"date":"2022-11-03T13:58:13","name":"[2/2] libopcodes/mips: add support for disassembler styling","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ca81edb86580566b1641ad140eb2bed385160ab7.1667483581.git.aburgess@redhat.com/mbox/"},{"id":15465,"url":"https://patchwork.plctlab.org/api/1.2/patches/15465/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/926e5154-b40b-9df8-d770-a8bf7d40e40e@suse.com/","msgid":"<926e5154-b40b-9df8-d770-a8bf7d40e40e@suse.com>","list_archive_url":null,"date":"2022-11-04T10:50:38","name":"[v6,1/7] x86: constify parse_insn()'\''s input","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/926e5154-b40b-9df8-d770-a8bf7d40e40e@suse.com/mbox/"},{"id":15466,"url":"https://patchwork.plctlab.org/api/1.2/patches/15466/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/07ef67fd-752c-ad1f-b8cb-4eaec1f420fc@suse.com/","msgid":"<07ef67fd-752c-ad1f-b8cb-4eaec1f420fc@suse.com>","list_archive_url":null,"date":"2022-11-04T10:51:34","name":"[v6,2/7] x86: re-work insn/suffix recognition","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/07ef67fd-752c-ad1f-b8cb-4eaec1f420fc@suse.com/mbox/"},{"id":15467,"url":"https://patchwork.plctlab.org/api/1.2/patches/15467/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ee8fd655-19a5-d944-0f5e-4351b88a59f9@suse.com/","msgid":"","list_archive_url":null,"date":"2022-11-04T10:52:02","name":"[v6,3/7] ix86: don'\''t recognize/derive Q suffix in the common case","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ee8fd655-19a5-d944-0f5e-4351b88a59f9@suse.com/mbox/"},{"id":15468,"url":"https://patchwork.plctlab.org/api/1.2/patches/15468/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/15ab2cf5-f1ac-e882-c415-6318f1bcc7f0@suse.com/","msgid":"<15ab2cf5-f1ac-e882-c415-6318f1bcc7f0@suse.com>","list_archive_url":null,"date":"2022-11-04T10:52:31","name":"[v6,4/7] x86-64: allow HLE store of accumulator to absolute 32-bit address","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/15ab2cf5-f1ac-e882-c415-6318f1bcc7f0@suse.com/mbox/"},{"id":15470,"url":"https://patchwork.plctlab.org/api/1.2/patches/15470/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/352d1e49-ac9f-ee86-7e9d-74f79744268b@suse.com/","msgid":"<352d1e49-ac9f-ee86-7e9d-74f79744268b@suse.com>","list_archive_url":null,"date":"2022-11-04T10:53:14","name":"[v6,5/7] x86: move bad-use-of-TLS-reloc check","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/352d1e49-ac9f-ee86-7e9d-74f79744268b@suse.com/mbox/"},{"id":15469,"url":"https://patchwork.plctlab.org/api/1.2/patches/15469/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c1913bf6-7328-e45f-69f1-20da1954af43@suse.com/","msgid":"","list_archive_url":null,"date":"2022-11-04T10:53:52","name":"[v6,6/7] x86: drop (now) stray IsString","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c1913bf6-7328-e45f-69f1-20da1954af43@suse.com/mbox/"},{"id":15471,"url":"https://patchwork.plctlab.org/api/1.2/patches/15471/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2baf6a9d-c1bf-660d-bbca-99b1604f5478@suse.com/","msgid":"<2baf6a9d-c1bf-660d-bbca-99b1604f5478@suse.com>","list_archive_url":null,"date":"2022-11-04T10:54:30","name":"[v6,7/7] x86: further re-work insn/suffix recognition to also cover MOVSX","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2baf6a9d-c1bf-660d-bbca-99b1604f5478@suse.com/mbox/"},{"id":15472,"url":"https://patchwork.plctlab.org/api/1.2/patches/15472/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104110132.694984-1-aburgess@redhat.com/","msgid":"<20221104110132.694984-1-aburgess@redhat.com>","list_archive_url":null,"date":"2022-11-04T11:01:32","name":"[PUSHED] opcodes/arm: silence compiler warning about uninitialized variable use","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104110132.694984-1-aburgess@redhat.com/mbox/"},{"id":15473,"url":"https://patchwork.plctlab.org/api/1.2/patches/15473/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104110214.129095-1-christophe.lyon@arm.com/","msgid":"<20221104110214.129095-1-christophe.lyon@arm.com>","list_archive_url":null,"date":"2022-11-04T11:02:14","name":"configure: require libzstd >= 1.4.0","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104110214.129095-1-christophe.lyon@arm.com/mbox/"},{"id":15485,"url":"https://patchwork.plctlab.org/api/1.2/patches/15485/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104115038.8957-1-nelson@rivosinc.com/","msgid":"<20221104115038.8957-1-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-11-04T11:50:37","name":"[1/2] RISC-V: File-level architecture shouldn'\''t be affected by section-level ones.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104115038.8957-1-nelson@rivosinc.com/mbox/"},{"id":15486,"url":"https://patchwork.plctlab.org/api/1.2/patches/15486/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104115038.8957-2-nelson@rivosinc.com/","msgid":"<20221104115038.8957-2-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-11-04T11:50:38","name":"[2/2] RISC-V: Clarify the suppress rule of mapping symbol with architecture string.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104115038.8957-2-nelson@rivosinc.com/mbox/"},{"id":15509,"url":"https://patchwork.plctlab.org/api/1.2/patches/15509/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/cc133c88-9ce9-5e3a-a8f7-ad72766862b9@suse.com/","msgid":"","list_archive_url":null,"date":"2022-11-04T13:12:07","name":"x86: adjust recently introduced testcases","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/cc133c88-9ce9-5e3a-a8f7-ad72766862b9@suse.com/mbox/"},{"id":15679,"url":"https://patchwork.plctlab.org/api/1.2/patches/15679/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104163328.2274371-1-chigot@adacore.com/","msgid":"<20221104163328.2274371-1-chigot@adacore.com>","list_archive_url":null,"date":"2022-11-04T16:33:28","name":"ld/testsuite: skip tests related to -shared when disabled","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104163328.2274371-1-chigot@adacore.com/mbox/"},{"id":15751,"url":"https://patchwork.plctlab.org/api/1.2/patches/15751/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104190216.1352855-1-indu.bhagat@oracle.com/","msgid":"<20221104190216.1352855-1-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-04T19:02:16","name":"[V3.1,11/15] libctf: add libsframe to LDFLAGS and LIBS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104190216.1352855-1-indu.bhagat@oracle.com/mbox/"},{"id":15792,"url":"https://patchwork.plctlab.org/api/1.2/patches/15792/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104205547.3728827-1-hjl.tools@gmail.com/","msgid":"<20221104205547.3728827-1-hjl.tools@gmail.com>","list_archive_url":null,"date":"2022-11-04T20:55:47","name":"i386: Check invalid (%dx) usage","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104205547.3728827-1-hjl.tools@gmail.com/mbox/"},{"id":15794,"url":"https://patchwork.plctlab.org/api/1.2/patches/15794/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104210134.1721620-1-indu.bhagat@oracle.com/","msgid":"<20221104210134.1721620-1-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-04T21:01:34","name":"[V3.2,11/15] libctf: add libsframe to LDFLAGS and LIBS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104210134.1721620-1-indu.bhagat@oracle.com/mbox/"},{"id":15959,"url":"https://patchwork.plctlab.org/api/1.2/patches/15959/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c620070e3e335df2b487d3836e20d251dac37525.1667651354.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-11-05T12:29:07","name":"[01/12] RISC-V: Remove unnecessary empty matching file","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c620070e3e335df2b487d3836e20d251dac37525.1667651354.git.research_trasio@irq.a4lg.com/mbox/"},{"id":15961,"url":"https://patchwork.plctlab.org/api/1.2/patches/15961/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4496235002a396043598ab9755bd8eda5c077b1f.1667651354.git.research_trasio@irq.a4lg.com/","msgid":"<4496235002a396043598ab9755bd8eda5c077b1f.1667651354.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-05T12:29:08","name":"[02/12] RISC-V: Tidy disassembler corner case tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4496235002a396043598ab9755bd8eda5c077b1f.1667651354.git.research_trasio@irq.a4lg.com/mbox/"},{"id":15960,"url":"https://patchwork.plctlab.org/api/1.2/patches/15960/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a9229a2798480f00bf12ac3c435b3ef57f867022.1667651354.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-11-05T12:29:09","name":"[03/12] RISC-V: Tidying related to '\''Zfinx'\'' disassembler test","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a9229a2798480f00bf12ac3c435b3ef57f867022.1667651354.git.research_trasio@irq.a4lg.com/mbox/"},{"id":15962,"url":"https://patchwork.plctlab.org/api/1.2/patches/15962/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6a020edd0e114a003edbaafe1088a040e9fa07e7.1667651354.git.research_trasio@irq.a4lg.com/","msgid":"<6a020edd0e114a003edbaafe1088a040e9fa07e7.1667651354.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-05T12:29:10","name":"[04/12] RISC-V: GAS: Add basic shared test utilities","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6a020edd0e114a003edbaafe1088a040e9fa07e7.1667651354.git.research_trasio@irq.a4lg.com/mbox/"},{"id":15966,"url":"https://patchwork.plctlab.org/api/1.2/patches/15966/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6fc2851a4161edc429089bd2bbd9c2bb4c0c118f.1667651354.git.research_trasio@irq.a4lg.com/","msgid":"<6fc2851a4161edc429089bd2bbd9c2bb4c0c118f.1667651354.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-05T12:29:11","name":"[05/12] RISC-V: Redefine \"nop\" test","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6fc2851a4161edc429089bd2bbd9c2bb4c0c118f.1667651354.git.research_trasio@irq.a4lg.com/mbox/"},{"id":15963,"url":"https://patchwork.plctlab.org/api/1.2/patches/15963/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7311ed3d2429000e18877d7af594890da170a7a3.1667651354.git.research_trasio@irq.a4lg.com/","msgid":"<7311ed3d2429000e18877d7af594890da170a7a3.1667651354.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-05T12:29:12","name":"[06/12] RISC-V: Reorganize/enhance {sign, zero}-extension instructions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7311ed3d2429000e18877d7af594890da170a7a3.1667651354.git.research_trasio@irq.a4lg.com/mbox/"},{"id":15968,"url":"https://patchwork.plctlab.org/api/1.2/patches/15968/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ac99c9696c156207f06c18f2d6bf423c96c5876b.1667651354.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-11-05T12:29:13","name":"[07/12] RISC-V: Combine complex extension error handling tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ac99c9696c156207f06c18f2d6bf423c96c5876b.1667651354.git.research_trasio@irq.a4lg.com/mbox/"},{"id":15970,"url":"https://patchwork.plctlab.org/api/1.2/patches/15970/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9378b9505e3e230e0a690c56e67d253e2a0f5864.1667651354.git.research_trasio@irq.a4lg.com/","msgid":"<9378b9505e3e230e0a690c56e67d253e2a0f5864.1667651354.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-05T12:29:14","name":"[08/12] RISC-V: Refine/enhance '\''M'\''/'\''Zmmul'\'' extension tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9378b9505e3e230e0a690c56e67d253e2a0f5864.1667651354.git.research_trasio@irq.a4lg.com/mbox/"},{"id":15964,"url":"https://patchwork.plctlab.org/api/1.2/patches/15964/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/82832a67f240d5857fd502d4b74fd7d841ee2d6e.1667651354.git.research_trasio@irq.a4lg.com/","msgid":"<82832a67f240d5857fd502d4b74fd7d841ee2d6e.1667651354.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-05T12:29:15","name":"[09/12] RISC-V: Combine/enhance '\''Zicbo[mz]'\'' extension tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/82832a67f240d5857fd502d4b74fd7d841ee2d6e.1667651354.git.research_trasio@irq.a4lg.com/mbox/"},{"id":15965,"url":"https://patchwork.plctlab.org/api/1.2/patches/15965/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9c47e59868a64b13e5a7bb487e3619d4f1497d78.1667651354.git.research_trasio@irq.a4lg.com/","msgid":"<9c47e59868a64b13e5a7bb487e3619d4f1497d78.1667651354.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-05T12:29:16","name":"[10/12] RISC-V: Enhance '\''Zicbop'\'' testcases","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9c47e59868a64b13e5a7bb487e3619d4f1497d78.1667651354.git.research_trasio@irq.a4lg.com/mbox/"},{"id":15967,"url":"https://patchwork.plctlab.org/api/1.2/patches/15967/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2d9befc5bc5eed80b6bd7da6d092a61b1162ecac.1667651354.git.research_trasio@irq.a4lg.com/","msgid":"<2d9befc5bc5eed80b6bd7da6d092a61b1162ecac.1667651354.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-05T12:29:17","name":"[11/12] RISC-V: Reorganize/enhance '\''Zb*'\'' extension tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2d9befc5bc5eed80b6bd7da6d092a61b1162ecac.1667651354.git.research_trasio@irq.a4lg.com/mbox/"},{"id":15969,"url":"https://patchwork.plctlab.org/api/1.2/patches/15969/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f1c5589ab606b74eeac98e3dafd4a7903450d3b2.1667651354.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-11-05T12:29:18","name":"[12/12] RISC-V: Combine/enhance '\''Zk*'\''/'\''Zbk*'\'' extension tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f1c5589ab606b74eeac98e3dafd4a7903450d3b2.1667651354.git.research_trasio@irq.a4lg.com/mbox/"},{"id":16066,"url":"https://patchwork.plctlab.org/api/1.2/patches/16066/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221106053640.1649752-1-indu.bhagat@oracle.com/","msgid":"<20221106053640.1649752-1-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-06T05:36:40","name":"[V3.1,03/15] gas: generate .sframe from CFI directives","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221106053640.1649752-1-indu.bhagat@oracle.com/mbox/"},{"id":16379,"url":"https://patchwork.plctlab.org/api/1.2/patches/16379/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221107112805.3332619-1-och95@yandex.ru/","msgid":"<20221107112805.3332619-1-och95@yandex.ru>","list_archive_url":null,"date":"2022-11-07T11:28:05","name":"gold/aarch64: Fix adrp distance check","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221107112805.3332619-1-och95@yandex.ru/mbox/"},{"id":16400,"url":"https://patchwork.plctlab.org/api/1.2/patches/16400/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221107124620.1271470-1-christoph.muellner@vrull.eu/","msgid":"<20221107124620.1271470-1-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2022-11-07T12:46:20","name":"RISC-V: xtheadfmemidx: Use fp register in mnemonics","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221107124620.1271470-1-christoph.muellner@vrull.eu/mbox/"},{"id":16594,"url":"https://patchwork.plctlab.org/api/1.2/patches/16594/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/CACVBkZ+kM2xcpwk5zHQ4bqDV7dbPjZ6cMU9tR-h62+tDTgi3Tw@mail.gmail.com/","msgid":"","list_archive_url":null,"date":"2022-11-07T17:53:35","name":"GAS fix section alignment for aarch64-pe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/CACVBkZ+kM2xcpwk5zHQ4bqDV7dbPjZ6cMU9tR-h62+tDTgi3Tw@mail.gmail.com/mbox/"},{"id":16744,"url":"https://patchwork.plctlab.org/api/1.2/patches/16744/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221107222809.924195-1-indu.bhagat@oracle.com/","msgid":"<20221107222809.924195-1-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-07T22:28:09","name":"[V3.3,11/15] libctf: add libsframe to LDFLAGS and LIBS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221107222809.924195-1-indu.bhagat@oracle.com/mbox/"},{"id":16797,"url":"https://patchwork.plctlab.org/api/1.2/patches/16797/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221108012556.66467-1-haochen.jiang@intel.com/","msgid":"<20221108012556.66467-1-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-11-08T01:25:56","name":"x86: Correct wrong comments in vex_w_table","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221108012556.66467-1-haochen.jiang@intel.com/mbox/"},{"id":16884,"url":"https://patchwork.plctlab.org/api/1.2/patches/16884/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221108054530.796968-1-markus.t.metzger@intel.com/","msgid":"<20221108054530.796968-1-markus.t.metzger@intel.com>","list_archive_url":null,"date":"2022-11-08T05:45:29","name":"[1/2] gprofng: make cpu identification available to others","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221108054530.796968-1-markus.t.metzger@intel.com/mbox/"},{"id":16885,"url":"https://patchwork.plctlab.org/api/1.2/patches/16885/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221108054530.796968-2-markus.t.metzger@intel.com/","msgid":"<20221108054530.796968-2-markus.t.metzger@intel.com>","list_archive_url":null,"date":"2022-11-08T05:45:30","name":"[2/2] gdb, btrace: use cpuident.h to implement btrace_this_cpu","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221108054530.796968-2-markus.t.metzger@intel.com/mbox/"},{"id":16995,"url":"https://patchwork.plctlab.org/api/1.2/patches/16995/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ea0daf08-4923-ebfa-dcfe-699c43d63822@suse.com/","msgid":"","list_archive_url":null,"date":"2022-11-08T11:29:40","name":"x86/Intel: don'\''t accept malformed EXTRQ / INSERTQ","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ea0daf08-4923-ebfa-dcfe-699c43d63822@suse.com/mbox/"},{"id":17057,"url":"https://patchwork.plctlab.org/api/1.2/patches/17057/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221108141352.6613-1-jwilk@jwilk.net/","msgid":"<20221108141352.6613-1-jwilk@jwilk.net>","list_archive_url":null,"date":"2022-11-08T14:13:52","name":"Fix typos in the list of objdump options","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221108141352.6613-1-jwilk@jwilk.net/mbox/"},{"id":17117,"url":"https://patchwork.plctlab.org/api/1.2/patches/17117/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1667924955-9218-1-git-send-email-apinski@marvell.com/","msgid":"<1667924955-9218-1-git-send-email-apinski@marvell.com>","list_archive_url":null,"date":"2022-11-08T16:29:15","name":"Use toplevel configure for GMP and MPFR for gdb","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1667924955-9218-1-git-send-email-apinski@marvell.com/mbox/"},{"id":17160,"url":"https://patchwork.plctlab.org/api/1.2/patches/17160/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/27382086-397f-060f-6cf6-c1d36ff6b812@linux.ibm.com/","msgid":"<27382086-397f-060f-6cf6-c1d36ff6b812@linux.ibm.com>","list_archive_url":null,"date":"2022-11-08T18:23:32","name":"[COMMITTED] PowerPC: Add XSP operand define","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/27382086-397f-060f-6cf6-c1d36ff6b812@linux.ibm.com/mbox/"},{"id":17202,"url":"https://patchwork.plctlab.org/api/1.2/patches/17202/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221108192248.1622627-1-indu.bhagat@oracle.com/","msgid":"<20221108192248.1622627-1-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-08T19:22:48","name":"libctf: use libtool for link test in configure","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221108192248.1622627-1-indu.bhagat@oracle.com/mbox/"},{"id":17262,"url":"https://patchwork.plctlab.org/api/1.2/patches/17262/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221108225030.371817-1-hjl.tools@gmail.com/","msgid":"<20221108225030.371817-1-hjl.tools@gmail.com>","list_archive_url":null,"date":"2022-11-08T22:50:30","name":"ld: Always output local symbol for relocatable link","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221108225030.371817-1-hjl.tools@gmail.com/mbox/"},{"id":17399,"url":"https://patchwork.plctlab.org/api/1.2/patches/17399/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-2-indu.bhagat@oracle.com/","msgid":"<20221109084244.261296-2-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-09T08:42:34","name":"[V4,01/11] sframe.h: Add SFrame format definition","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-2-indu.bhagat@oracle.com/mbox/"},{"id":17398,"url":"https://patchwork.plctlab.org/api/1.2/patches/17398/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-3-indu.bhagat@oracle.com/","msgid":"<20221109084244.261296-3-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-09T08:42:35","name":"[V4,02/11] gas: add new command line option --gsframe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-3-indu.bhagat@oracle.com/mbox/"},{"id":17400,"url":"https://patchwork.plctlab.org/api/1.2/patches/17400/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-4-indu.bhagat@oracle.com/","msgid":"<20221109084244.261296-4-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-09T08:42:36","name":"[V4,03/11] gas: generate .sframe from CFI directives","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-4-indu.bhagat@oracle.com/mbox/"},{"id":17403,"url":"https://patchwork.plctlab.org/api/1.2/patches/17403/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-5-indu.bhagat@oracle.com/","msgid":"<20221109084244.261296-5-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-09T08:42:37","name":"[V4,04/11] gas: testsuite: add new tests for SFrame unwind info","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-5-indu.bhagat@oracle.com/mbox/"},{"id":17402,"url":"https://patchwork.plctlab.org/api/1.2/patches/17402/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-8-indu.bhagat@oracle.com/","msgid":"<20221109084244.261296-8-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-09T08:42:40","name":"[V4,07/11] readelf/objdump: support for SFrame section","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-8-indu.bhagat@oracle.com/mbox/"},{"id":17401,"url":"https://patchwork.plctlab.org/api/1.2/patches/17401/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-9-indu.bhagat@oracle.com/","msgid":"<20221109084244.261296-9-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-09T08:42:41","name":"[V4,08/11] src-release.sh: Add libsframe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-9-indu.bhagat@oracle.com/mbox/"},{"id":17404,"url":"https://patchwork.plctlab.org/api/1.2/patches/17404/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-10-indu.bhagat@oracle.com/","msgid":"<20221109084244.261296-10-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-09T08:42:42","name":"[V4,09/11] binutils/NEWS: add text for SFrame support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-10-indu.bhagat@oracle.com/mbox/"},{"id":17405,"url":"https://patchwork.plctlab.org/api/1.2/patches/17405/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-11-indu.bhagat@oracle.com/","msgid":"<20221109084244.261296-11-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-09T08:42:43","name":"[V4,10/11] gas/NEWS: add text about new command line option and SFrame support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-11-indu.bhagat@oracle.com/mbox/"}],"public":true,"mbox":"https://patchwork.plctlab.org/bundle/patchwork-bot/binutils-gdb_2022-11/mbox/"}]' + bundle_id=9 + git-pw bundle add 9 17406 +------------+-----------------------------------------------------------------------------------------------------------+ | Property | Value | |------------+-----------------------------------------------------------------------------------------------------------| | ID | 9 | | Name | binutils-gdb_2022-11 | | URL | https://patchwork.plctlab.org/bundle/patchwork-bot/binutils-gdb_2022-11/ | | Owner | patchwork-bot | | Project | binutils-gdb | | Public | True | | Patches | 13337 x86: Silence GCC 12 warning on tc-i386.c | | | 13350 x86: simplify expressions in update_imm() | | | 13487 binutils: Run PR binutils/26160 test | | | 13621 [PUSHED] opcodes/arm: silence compiler warning about uninitialized variable use | | | 13628 [PUSHED] opcodes/arm: don't pass non-string literal to printf like function | | | 13747 [Binutils-2.39,backport,GAS] arm: Use DWARF numbering convention for pseudo-register representation | | | 13993 ld: Add module information substream to PDB files | | | 14028 [committed] RISC-V: Fixed the missing $x+arch when adding odd paddings for alignment. | | | 14043 gas/doc/internals.texi: fix typo | | | 14069 [v2] Support multiple .eh_frame sections | | | 14409 arm: PR 29739 Fix typo where '; ' should not have been replaced with '@' | | | 14588 [v3] Support multiple .eh_frame sections | | | 14602 [v2] ld: Add module information substream to PDB files | | | 14706 [opcodes/arm] Fix potential null pointer dereferences | | | 14840 [REVIEW,ONLY,1/2] NEAR-RATIFICATION RISC-V: Add 'Ssstateen' extension and its CSRs | | | 14841 [REVIEW,ONLY,2/2] NEAR-RATIFICATION RISC-V: Add platform property/capability extensions | | | 14894 [1/2] opcodes/mips: use .word/.short for undefined instructions | | | 14893 [2/2] libopcodes/mips: add support for disassembler styling | | | 15465 [v6,1/7] x86: constify parse_insn()'s input | | | 15466 [v6,2/7] x86: re-work insn/suffix recognition | | | 15467 [v6,3/7] ix86: don't recognize/derive Q suffix in the common case | | | 15468 [v6,4/7] x86-64: allow HLE store of accumulator to absolute 32-bit address | | | 15470 [v6,5/7] x86: move bad-use-of-TLS-reloc check | | | 15469 [v6,6/7] x86: drop (now) stray IsString | | | 15471 [v6,7/7] x86: further re-work insn/suffix recognition to also cover MOVSX | | | 15472 [PUSHED] opcodes/arm: silence compiler warning about uninitialized variable use | | | 15473 configure: require libzstd >= 1.4.0 | | | 15485 [1/2] RISC-V: File-level architecture shouldn't be affected by section-level ones. | | | 15486 [2/2] RISC-V: Clarify the suppress rule of mapping symbol with architecture string. | | | 15509 x86: adjust recently introduced testcases | | | 15679 ld/testsuite: skip tests related to -shared when disabled | | | 15751 [V3.1,11/15] libctf: add libsframe to LDFLAGS and LIBS | | | 15792 i386: Check invalid (%dx) usage | | | 15794 [V3.2,11/15] libctf: add libsframe to LDFLAGS and LIBS | | | 15959 [01/12] RISC-V: Remove unnecessary empty matching file | | | 15961 [02/12] RISC-V: Tidy disassembler corner case tests | | | 15960 [03/12] RISC-V: Tidying related to 'Zfinx' disassembler test | | | 15962 [04/12] RISC-V: GAS: Add basic shared test utilities | | | 15966 [05/12] RISC-V: Redefine "nop" test | | | 15963 [06/12] RISC-V: Reorganize/enhance {sign, zero}-extension instructions | | | 15968 [07/12] RISC-V: Combine complex extension error handling tests | | | 15970 [08/12] RISC-V: Refine/enhance 'M'/'Zmmul' extension tests | | | 15964 [09/12] RISC-V: Combine/enhance 'Zicbo[mz]' extension tests | | | 15965 [10/12] RISC-V: Enhance 'Zicbop' testcases | | | 15967 [11/12] RISC-V: Reorganize/enhance 'Zb*' extension tests | | | 15969 [12/12] RISC-V: Combine/enhance 'Zk*'/'Zbk*' extension tests | | | 16066 [V3.1,03/15] gas: generate .sframe from CFI directives | | | 16379 gold/aarch64: Fix adrp distance check | | | 16400 RISC-V: xtheadfmemidx: Use fp register in mnemonics | | | 16594 GAS fix section alignment for aarch64-pe | | | 16744 [V3.3,11/15] libctf: add libsframe to LDFLAGS and LIBS | | | 16797 x86: Correct wrong comments in vex_w_table | | | 16884 [1/2] gprofng: make cpu identification available to others | | | 16885 [2/2] gdb, btrace: use cpuident.h to implement btrace_this_cpu | | | 16995 x86/Intel: don't accept malformed EXTRQ / INSERTQ | | | 17057 Fix typos in the list of objdump options | | | 17117 Use toplevel configure for GMP and MPFR for gdb | | | 17160 [COMMITTED] PowerPC: Add XSP operand define | | | 17202 libctf: use libtool for link test in configure | | | 17262 ld: Always output local symbol for relocatable link | | | 17399 [V4,01/11] sframe.h: Add SFrame format definition | | | 17398 [V4,02/11] gas: add new command line option --gsframe | | | 17400 [V4,03/11] gas: generate .sframe from CFI directives | | | 17403 [V4,04/11] gas: testsuite: add new tests for SFrame unwind info | | | 17406 [V4,06/11] bfd: linker: merge .sframe sections | | | 17402 [V4,07/11] readelf/objdump: support for SFrame section | | | 17401 [V4,08/11] src-release.sh: Add libsframe | | | 17404 [V4,09/11] binutils/NEWS: add text for SFrame support | | | 17405 [V4,10/11] gas/NEWS: add text about new command line option and SFrame support | +------------+-----------------------------------------------------------------------------------------------------------+ + git config pull.rebase false + git fetch origin master From github.com:plctlab/patchwork-binutils-gdb * branch master -> FETCH_HEAD + git checkout master Switched to a new branch 'master' branch 'master' set up to track 'origin/master'. + git pull origin master From github.com:plctlab/patchwork-binutils-gdb * branch master -> FETCH_HEAD Already up to date. + git fetch origin upstream-master From github.com:plctlab/patchwork-binutils-gdb * branch upstream-master -> FETCH_HEAD + git checkout upstream-master Switched to a new branch 'upstream-master' branch 'upstream-master' set up to track 'origin/upstream-master'. + git remote add upstream https://sourceware.org/git/binutils-gdb.git + git pull upstream master From https://sourceware.org/git/binutils-gdb * branch master -> FETCH_HEAD * [new branch] master -> upstream/master Already up to date. + git push -u origin upstream-master Everything up-to-date branch 'upstream-master' set up to track 'origin/upstream-master'. + git checkout master Switched to branch 'master' Your branch is up to date with 'origin/master'. + git merge upstream-master Already up to date. + git push -u origin master Everything up-to-date branch 'master' set up to track 'origin/master'. + branchname=series6804-patch17406 ++ git branch -a ++ grep 'series6804-patch17406$' + checkbranch= + checkbranchresult=null + '[' null = series6804-patch17406 ']' + git checkout -b series6804-patch17406 Switched to a new branch 'series6804-patch17406' ++ curl https://patchwork.plctlab.org/api/1.2/series/6804/ % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 6726 100 6726 0 0 145k 0 --:--:-- --:--:-- --:--:-- 149k + series_response='{"id":6804,"url":"https://patchwork.plctlab.org/api/1.2/series/6804/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/list/?series=6804","project":{"id":2,"url":"https://patchwork.plctlab.org/api/1.2/projects/2/","name":"binutils-gdb","link_name":"binutils-gdb","list_id":"binutils.sourceware.org","list_email":"binutils@sourceware.org","web_url":"https://github.com/wangliu-iscas/Patchwork-Bundles/blob/main/binutils-gdb.md","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"name":"Definition and support for SFrame unwind format","date":"2022-11-09T08:42:33","submitter":{"id":35,"url":"https://patchwork.plctlab.org/api/1.2/people/35/","name":"Indu Bhagat","email":"indu.bhagat@oracle.com"},"version":4,"total":11,"received_total":11,"received_all":true,"mbox":"https://patchwork.plctlab.org/series/6804/mbox/","cover_letter":{"id":1374,"url":"https://patchwork.plctlab.org/api/1.2/covers/1374/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/cover/20221109084244.261296-1-indu.bhagat@oracle.com/","msgid":"<20221109084244.261296-1-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-09T08:42:33","name":"[V4,00/11] Definition and support for SFrame unwind format","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/cover/20221109084244.261296-1-indu.bhagat@oracle.com/mbox/"},"patches":[{"id":17399,"url":"https://patchwork.plctlab.org/api/1.2/patches/17399/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-2-indu.bhagat@oracle.com/","msgid":"<20221109084244.261296-2-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-09T08:42:34","name":"[V4,01/11] sframe.h: Add SFrame format definition","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-2-indu.bhagat@oracle.com/mbox/"},{"id":17398,"url":"https://patchwork.plctlab.org/api/1.2/patches/17398/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-3-indu.bhagat@oracle.com/","msgid":"<20221109084244.261296-3-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-09T08:42:35","name":"[V4,02/11] gas: add new command line option --gsframe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-3-indu.bhagat@oracle.com/mbox/"},{"id":17400,"url":"https://patchwork.plctlab.org/api/1.2/patches/17400/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-4-indu.bhagat@oracle.com/","msgid":"<20221109084244.261296-4-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-09T08:42:36","name":"[V4,03/11] gas: generate .sframe from CFI directives","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-4-indu.bhagat@oracle.com/mbox/"},{"id":17403,"url":"https://patchwork.plctlab.org/api/1.2/patches/17403/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-5-indu.bhagat@oracle.com/","msgid":"<20221109084244.261296-5-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-09T08:42:37","name":"[V4,04/11] gas: testsuite: add new tests for SFrame unwind info","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-5-indu.bhagat@oracle.com/mbox/"},{"id":17407,"url":"https://patchwork.plctlab.org/api/1.2/patches/17407/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-6-indu.bhagat@oracle.com/","msgid":"<20221109084244.261296-6-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-09T08:42:38","name":"[V4,05/11] libsframe: add the SFrame library","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-6-indu.bhagat@oracle.com/mbox/"},{"id":17406,"url":"https://patchwork.plctlab.org/api/1.2/patches/17406/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-7-indu.bhagat@oracle.com/","msgid":"<20221109084244.261296-7-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-09T08:42:39","name":"[V4,06/11] bfd: linker: merge .sframe sections","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-7-indu.bhagat@oracle.com/mbox/"},{"id":17402,"url":"https://patchwork.plctlab.org/api/1.2/patches/17402/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-8-indu.bhagat@oracle.com/","msgid":"<20221109084244.261296-8-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-09T08:42:40","name":"[V4,07/11] readelf/objdump: support for SFrame section","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-8-indu.bhagat@oracle.com/mbox/"},{"id":17401,"url":"https://patchwork.plctlab.org/api/1.2/patches/17401/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-9-indu.bhagat@oracle.com/","msgid":"<20221109084244.261296-9-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-09T08:42:41","name":"[V4,08/11] src-release.sh: Add libsframe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-9-indu.bhagat@oracle.com/mbox/"},{"id":17404,"url":"https://patchwork.plctlab.org/api/1.2/patches/17404/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-10-indu.bhagat@oracle.com/","msgid":"<20221109084244.261296-10-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-09T08:42:42","name":"[V4,09/11] binutils/NEWS: add text for SFrame support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-10-indu.bhagat@oracle.com/mbox/"},{"id":17405,"url":"https://patchwork.plctlab.org/api/1.2/patches/17405/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-11-indu.bhagat@oracle.com/","msgid":"<20221109084244.261296-11-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-09T08:42:43","name":"[V4,10/11] gas/NEWS: add text about new command line option and SFrame support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-11-indu.bhagat@oracle.com/mbox/"},{"id":17418,"url":"https://patchwork.plctlab.org/api/1.2/patches/17418/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-12-indu.bhagat@oracle.com/","msgid":"<20221109084244.261296-12-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-09T08:42:44","name":"[V4,11/11] doc: add SFrame spec file","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-12-indu.bhagat@oracle.com/mbox/"}]}' ++ echo '{"id":6804,"url":"https://patchwork.plctlab.org/api/1.2/series/6804/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/list/?series=6804","project":{"id":2,"url":"https://patchwork.plctlab.org/api/1.2/projects/2/","name":"binutils-gdb","link_name":"binutils-gdb","list_id":"binutils.sourceware.org","list_email":"binutils@sourceware.org","web_url":"https://github.com/wangliu-iscas/Patchwork-Bundles/blob/main/binutils-gdb.md","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"name":"Definition and support for SFrame unwind format","date":"2022-11-09T08:42:33","submitter":{"id":35,"url":"https://patchwork.plctlab.org/api/1.2/people/35/","name":"Indu Bhagat","email":"indu.bhagat@oracle.com"},"version":4,"total":11,"received_total":11,"received_all":true,"mbox":"https://patchwork.plctlab.org/series/6804/mbox/","cover_letter":{"id":1374,"url":"https://patchwork.plctlab.org/api/1.2/covers/1374/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/cover/20221109084244.261296-1-indu.bhagat@oracle.com/","msgid":"<20221109084244.261296-1-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-09T08:42:33","name":"[V4,00/11] Definition and support for SFrame unwind format","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/cover/20221109084244.261296-1-indu.bhagat@oracle.com/mbox/"},"patches":[{"id":17399,"url":"https://patchwork.plctlab.org/api/1.2/patches/17399/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-2-indu.bhagat@oracle.com/","msgid":"<20221109084244.261296-2-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-09T08:42:34","name":"[V4,01/11] sframe.h: Add SFrame format definition","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-2-indu.bhagat@oracle.com/mbox/"},{"id":17398,"url":"https://patchwork.plctlab.org/api/1.2/patches/17398/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-3-indu.bhagat@oracle.com/","msgid":"<20221109084244.261296-3-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-09T08:42:35","name":"[V4,02/11] gas: add new command line option --gsframe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-3-indu.bhagat@oracle.com/mbox/"},{"id":17400,"url":"https://patchwork.plctlab.org/api/1.2/patches/17400/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-4-indu.bhagat@oracle.com/","msgid":"<20221109084244.261296-4-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-09T08:42:36","name":"[V4,03/11] gas: generate .sframe from CFI directives","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-4-indu.bhagat@oracle.com/mbox/"},{"id":17403,"url":"https://patchwork.plctlab.org/api/1.2/patches/17403/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-5-indu.bhagat@oracle.com/","msgid":"<20221109084244.261296-5-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-09T08:42:37","name":"[V4,04/11] gas: testsuite: add new tests for SFrame unwind info","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-5-indu.bhagat@oracle.com/mbox/"},{"id":17407,"url":"https://patchwork.plctlab.org/api/1.2/patches/17407/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-6-indu.bhagat@oracle.com/","msgid":"<20221109084244.261296-6-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-09T08:42:38","name":"[V4,05/11] libsframe: add the SFrame library","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-6-indu.bhagat@oracle.com/mbox/"},{"id":17406,"url":"https://patchwork.plctlab.org/api/1.2/patches/17406/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-7-indu.bhagat@oracle.com/","msgid":"<20221109084244.261296-7-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-09T08:42:39","name":"[V4,06/11] bfd: linker: merge .sframe sections","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-7-indu.bhagat@oracle.com/mbox/"},{"id":17402,"url":"https://patchwork.plctlab.org/api/1.2/patches/17402/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-8-indu.bhagat@oracle.com/","msgid":"<20221109084244.261296-8-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-09T08:42:40","name":"[V4,07/11] readelf/objdump: support for SFrame section","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-8-indu.bhagat@oracle.com/mbox/"},{"id":17401,"url":"https://patchwork.plctlab.org/api/1.2/patches/17401/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-9-indu.bhagat@oracle.com/","msgid":"<20221109084244.261296-9-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-09T08:42:41","name":"[V4,08/11] src-release.sh: Add libsframe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-9-indu.bhagat@oracle.com/mbox/"},{"id":17404,"url":"https://patchwork.plctlab.org/api/1.2/patches/17404/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-10-indu.bhagat@oracle.com/","msgid":"<20221109084244.261296-10-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-09T08:42:42","name":"[V4,09/11] binutils/NEWS: add text for SFrame support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-10-indu.bhagat@oracle.com/mbox/"},{"id":17405,"url":"https://patchwork.plctlab.org/api/1.2/patches/17405/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-11-indu.bhagat@oracle.com/","msgid":"<20221109084244.261296-11-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-09T08:42:43","name":"[V4,10/11] gas/NEWS: add text about new command line option and SFrame support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-11-indu.bhagat@oracle.com/mbox/"},{"id":17418,"url":"https://patchwork.plctlab.org/api/1.2/patches/17418/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-12-indu.bhagat@oracle.com/","msgid":"<20221109084244.261296-12-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-09T08:42:44","name":"[V4,11/11] doc: add SFrame spec file","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-12-indu.bhagat@oracle.com/mbox/"}]}' ++ jq '.patches[] | (.id|tostring) + "," + .mbox' + patchid_patchurl='"17399,https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-2-indu.bhagat@oracle.com/mbox/" "17398,https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-3-indu.bhagat@oracle.com/mbox/" "17400,https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-4-indu.bhagat@oracle.com/mbox/" "17403,https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-5-indu.bhagat@oracle.com/mbox/" "17407,https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-6-indu.bhagat@oracle.com/mbox/" "17406,https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-7-indu.bhagat@oracle.com/mbox/" "17402,https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-8-indu.bhagat@oracle.com/mbox/" "17401,https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-9-indu.bhagat@oracle.com/mbox/" "17404,https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-10-indu.bhagat@oracle.com/mbox/" "17405,https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-11-indu.bhagat@oracle.com/mbox/" "17418,https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-12-indu.bhagat@oracle.com/mbox/"' + echo '"17399,https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-2-indu.bhagat@oracle.com/mbox/" "17398,https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-3-indu.bhagat@oracle.com/mbox/" "17400,https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-4-indu.bhagat@oracle.com/mbox/" "17403,https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-5-indu.bhagat@oracle.com/mbox/" "17407,https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-6-indu.bhagat@oracle.com/mbox/" "17406,https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-7-indu.bhagat@oracle.com/mbox/" "17402,https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-8-indu.bhagat@oracle.com/mbox/" "17401,https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-9-indu.bhagat@oracle.com/mbox/" "17404,https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-10-indu.bhagat@oracle.com/mbox/" "17405,https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-11-indu.bhagat@oracle.com/mbox/" "17418,https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-12-indu.bhagat@oracle.com/mbox/"' + IFS=, + read -r series_patch_id series_patch_url ++ echo '"17399' ++ sed 's/"//g' + series_patch_id=17399 ++ echo 'https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-2-indu.bhagat@oracle.com/mbox/"' ++ sed 's/"//g' + series_patch_url=https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-2-indu.bhagat@oracle.com/mbox/ ++ git rev-parse HEAD + commitid_before=2d4989e98ee5e63b76ce3e35b0e02baaee2f50cb + eval '+++ declare -p bout bret declare -- bout="Applying: sframe.h: Add SFrame format definition" declare -- bret="0" ++ berr='\''++++ git_am https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-2-indu.bhagat@oracle.com/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-2-indu.bhagat@oracle.com/mbox/ ++++ curl https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-2-indu.bhagat@oracle.com/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 25341 100 25341 0 0 494k 0 --:--:-- --:--:-- --:--:-- 494k +++ bout='\''\'\'''\''Applying: sframe.h: Add SFrame format definition'\''\'\'''\'' +++ bret=0'\'' ++ declare -p berr declare -- berr="++++ git_am https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-2-indu.bhagat@oracle.com/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-2-indu.bhagat@oracle.com/mbox/ ++++ curl https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-2-indu.bhagat@oracle.com/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 25341 100 25341 0 0 494k 0 --:--:-- --:--:-- --:--:-- 494k +++ bout='\''Applying: sframe.h: Add SFrame format definition'\'' +++ bret=0"' ++ +++ declare -p bout bret /tmp/jenkins8128469799047977168.sh: line 124: +++: command not found ++ declare -- 'bout=Applying: sframe.h: Add SFrame format definition' ++ declare -- bret=0 ++ ++ 'berr=++++ git_am https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-2-indu.bhagat@oracle.com/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-2-indu.bhagat@oracle.com/mbox/ ++++ curl https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-2-indu.bhagat@oracle.com/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 25341 100 25341 0 0 494k 0 --:--:-- --:--:-- --:--:-- 494k +++ bout='\''Applying: sframe.h: Add SFrame format definition'\'' +++ bret=0' /tmp/jenkins8128469799047977168.sh: line 135: ++: command not found ++ ++ declare -p berr /tmp/jenkins8128469799047977168.sh: line 136: ++: command not found ++ declare -- 'berr=++++ git_am https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-2-indu.bhagat@oracle.com/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-2-indu.bhagat@oracle.com/mbox/ ++++ curl https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-2-indu.bhagat@oracle.com/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 25341 100 25341 0 0 494k 0 --:--:-- --:--:-- --:--:-- 494k +++ bout='\''Applying: sframe.h: Add SFrame format definition'\'' +++ bret=0' ++ git rev-parse HEAD + commitid_after=5efd2cfe311fce627663b0c1e91c8bef6b70e3b5 + '[' 0 = 0 ']' + '[' 5efd2cfe311fce627663b0c1e91c8bef6b70e3b5 = 2d4989e98ee5e63b76ce3e35b0e02baaee2f50cb ']' + '[' 17399 = 17406 ']' + IFS=, + read -r series_patch_id series_patch_url ++ sed 's/"//g' ++ echo '"17398' + series_patch_id=17398 ++ echo 'https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-3-indu.bhagat@oracle.com/mbox/"' ++ sed 's/"//g' + series_patch_url=https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-3-indu.bhagat@oracle.com/mbox/ ++ git rev-parse HEAD + commitid_before=5efd2cfe311fce627663b0c1e91c8bef6b70e3b5 + eval '+++ declare -p bout bret declare -- bout="Applying: gas: add new command line option --gsframe" declare -- bret="0" ++ berr='\''++++ git_am https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-3-indu.bhagat@oracle.com/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-3-indu.bhagat@oracle.com/mbox/ ++++ curl https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-3-indu.bhagat@oracle.com/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 15144 100 15144 0 0 336k 0 --:--:-- --:--:-- --:--:-- 336k +++ bout='\''\'\'''\''Applying: gas: add new command line option --gsframe'\''\'\'''\'' +++ bret=0'\'' ++ declare -p berr declare -- berr="++++ git_am https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-3-indu.bhagat@oracle.com/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-3-indu.bhagat@oracle.com/mbox/ ++++ curl https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-3-indu.bhagat@oracle.com/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 15144 100 15144 0 0 336k 0 --:--:-- --:--:-- --:--:-- 336k +++ bout='\''Applying: gas: add new command line option --gsframe'\'' +++ bret=0"' ++ +++ declare -p bout bret /tmp/jenkins8128469799047977168.sh: line 124: +++: command not found ++ declare -- 'bout=Applying: gas: add new command line option --gsframe' ++ declare -- bret=0 ++ ++ 'berr=++++ git_am https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-3-indu.bhagat@oracle.com/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-3-indu.bhagat@oracle.com/mbox/ ++++ curl https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-3-indu.bhagat@oracle.com/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 15144 100 15144 0 0 336k 0 --:--:-- --:--:-- --:--:-- 336k +++ bout='\''Applying: gas: add new command line option --gsframe'\'' +++ bret=0' /tmp/jenkins8128469799047977168.sh: line 135: ++: command not found ++ ++ declare -p berr /tmp/jenkins8128469799047977168.sh: line 136: ++: command not found ++ declare -- 'berr=++++ git_am https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-3-indu.bhagat@oracle.com/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-3-indu.bhagat@oracle.com/mbox/ ++++ curl https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-3-indu.bhagat@oracle.com/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 15144 100 15144 0 0 336k 0 --:--:-- --:--:-- --:--:-- 336k +++ bout='\''Applying: gas: add new command line option --gsframe'\'' +++ bret=0' ++ git rev-parse HEAD + commitid_after=aab455c7f91f859e3f76f52ca0d2a2d5f620f528 + '[' 0 = 0 ']' + '[' aab455c7f91f859e3f76f52ca0d2a2d5f620f528 = 5efd2cfe311fce627663b0c1e91c8bef6b70e3b5 ']' + '[' 17398 = 17406 ']' + IFS=, + read -r series_patch_id series_patch_url ++ sed 's/"//g' ++ echo '"17400' + series_patch_id=17400 ++ echo 'https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-4-indu.bhagat@oracle.com/mbox/"' ++ sed 's/"//g' + series_patch_url=https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-4-indu.bhagat@oracle.com/mbox/ ++ git rev-parse HEAD + commitid_before=aab455c7f91f859e3f76f52ca0d2a2d5f620f528 + eval '+++ declare -p bout bret declare -- bout="Applying: gas: generate .sframe from CFI directives" declare -- bret="0" ++ berr='\''++++ git_am https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-4-indu.bhagat@oracle.com/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-4-indu.bhagat@oracle.com/mbox/ ++++ curl https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-4-indu.bhagat@oracle.com/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 84225 100 84225 0 0 1096k 0 --:--:-- --:--:-- --:--:-- 1096k +++ bout='\''\'\'''\''Applying: gas: generate .sframe from CFI directives'\''\'\'''\'' +++ bret=0'\'' ++ declare -p berr declare -- berr="++++ git_am https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-4-indu.bhagat@oracle.com/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-4-indu.bhagat@oracle.com/mbox/ ++++ curl https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-4-indu.bhagat@oracle.com/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 84225 100 84225 0 0 1096k 0 --:--:-- --:--:-- --:--:-- 1096k +++ bout='\''Applying: gas: generate .sframe from CFI directives'\'' +++ bret=0"' ++ +++ declare -p bout bret /tmp/jenkins8128469799047977168.sh: line 124: +++: command not found ++ declare -- 'bout=Applying: gas: generate .sframe from CFI directives' ++ declare -- bret=0 ++ ++ 'berr=++++ git_am https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-4-indu.bhagat@oracle.com/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-4-indu.bhagat@oracle.com/mbox/ ++++ curl https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-4-indu.bhagat@oracle.com/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 84225 100 84225 0 0 1096k 0 --:--:-- --:--:-- --:--:-- 1096k +++ bout='\''Applying: gas: generate .sframe from CFI directives'\'' +++ bret=0' /tmp/jenkins8128469799047977168.sh: line 135: ++: command not found ++ ++ declare -p berr /tmp/jenkins8128469799047977168.sh: line 136: ++: command not found ++ declare -- 'berr=++++ git_am https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-4-indu.bhagat@oracle.com/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-4-indu.bhagat@oracle.com/mbox/ ++++ curl https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-4-indu.bhagat@oracle.com/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 84225 100 84225 0 0 1096k 0 --:--:-- --:--:-- --:--:-- 1096k +++ bout='\''Applying: gas: generate .sframe from CFI directives'\'' +++ bret=0' ++ git rev-parse HEAD + commitid_after=639309d363f878a0f466b3f23c6cd161b8b7b7e2 + '[' 0 = 0 ']' + '[' 639309d363f878a0f466b3f23c6cd161b8b7b7e2 = aab455c7f91f859e3f76f52ca0d2a2d5f620f528 ']' + '[' 17400 = 17406 ']' + IFS=, + read -r series_patch_id series_patch_url ++ echo '"17403' ++ sed 's/"//g' + series_patch_id=17403 ++ echo 'https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-5-indu.bhagat@oracle.com/mbox/"' ++ sed 's/"//g' + series_patch_url=https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-5-indu.bhagat@oracle.com/mbox/ ++ git rev-parse HEAD + commitid_before=639309d363f878a0f466b3f23c6cd161b8b7b7e2 + eval '+++ declare -p bout bret declare -- bout="Applying: gas: testsuite: add new tests for SFrame unwind info" declare -- bret="0" ++ berr='\''++++ git_am https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-5-indu.bhagat@oracle.com/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-5-indu.bhagat@oracle.com/mbox/ ++++ curl https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-5-indu.bhagat@oracle.com/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 38027 100 38027 0 0 530k 0 --:--:-- --:--:-- --:--:-- 530k +++ bout='\''\'\'''\''Applying: gas: testsuite: add new tests for SFrame unwind info'\''\'\'''\'' +++ bret=0'\'' ++ declare -p berr declare -- berr="++++ git_am https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-5-indu.bhagat@oracle.com/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-5-indu.bhagat@oracle.com/mbox/ ++++ curl https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-5-indu.bhagat@oracle.com/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 38027 100 38027 0 0 530k 0 --:--:-- --:--:-- --:--:-- 530k +++ bout='\''Applying: gas: testsuite: add new tests for SFrame unwind info'\'' +++ bret=0"' ++ +++ declare -p bout bret /tmp/jenkins8128469799047977168.sh: line 124: +++: command not found ++ declare -- 'bout=Applying: gas: testsuite: add new tests for SFrame unwind info' ++ declare -- bret=0 ++ ++ 'berr=++++ git_am https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-5-indu.bhagat@oracle.com/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-5-indu.bhagat@oracle.com/mbox/ ++++ curl https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-5-indu.bhagat@oracle.com/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 38027 100 38027 0 0 530k 0 --:--:-- --:--:-- --:--:-- 530k +++ bout='\''Applying: gas: testsuite: add new tests for SFrame unwind info'\'' +++ bret=0' /tmp/jenkins8128469799047977168.sh: line 135: ++: command not found ++ ++ declare -p berr /tmp/jenkins8128469799047977168.sh: line 136: ++: command not found ++ declare -- 'berr=++++ git_am https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-5-indu.bhagat@oracle.com/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-5-indu.bhagat@oracle.com/mbox/ ++++ curl https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-5-indu.bhagat@oracle.com/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 38027 100 38027 0 0 530k 0 --:--:-- --:--:-- --:--:-- 530k +++ bout='\''Applying: gas: testsuite: add new tests for SFrame unwind info'\'' +++ bret=0' ++ git rev-parse HEAD + commitid_after=6675f325721056d5548b6dff5cd0cebe13c111a5 + '[' 0 = 0 ']' + '[' 6675f325721056d5548b6dff5cd0cebe13c111a5 = 639309d363f878a0f466b3f23c6cd161b8b7b7e2 ']' + '[' 17403 = 17406 ']' + IFS=, + read -r series_patch_id series_patch_url ++ sed 's/"//g' ++ echo '"17407' + series_patch_id=17407 ++ echo 'https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-6-indu.bhagat@oracle.com/mbox/"' ++ sed 's/"//g' + series_patch_url=https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-6-indu.bhagat@oracle.com/mbox/ ++ git rev-parse HEAD + commitid_before=6675f325721056d5548b6dff5cd0cebe13c111a5 + eval '+++ declare -p bout bret declare -- bout="git: apply.c:3717: check_preimage: Assertion \`patch->is_new <= 0'\'' failed." declare -- bret="134" ++ berr='\''++++ git_am https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-6-indu.bhagat@oracle.com/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-6-indu.bhagat@oracle.com/mbox/ ++++ curl https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-6-indu.bhagat@oracle.com/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 270k 100 270k 0 0 4753k 0 --:--:-- --:--:-- --:--:-- 4753k +++ bout='\''\'\'''\''git: apply.c:3717: check_preimage: Assertion `patch->is_new <= 0'\''\'\'''\''\'\''\'\'''\'''\''\'\'''\'' failed.'\''\'\'''\'' +++ bret=134'\'' ++ declare -p berr declare -- berr="++++ git_am https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-6-indu.bhagat@oracle.com/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-6-indu.bhagat@oracle.com/mbox/ ++++ curl https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-6-indu.bhagat@oracle.com/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 270k 100 270k 0 0 4753k 0 --:--:-- --:--:-- --:--:-- 4753k +++ bout='\''git: apply.c:3717: check_preimage: Assertion \`patch->is_new <= 0'\''\\'\'''\'' failed.'\'' +++ bret=134"' ++ +++ declare -p bout bret /tmp/jenkins8128469799047977168.sh: line 124: +++: command not found ++ declare -- 'bout=git: apply.c:3717: check_preimage: Assertion `patch->is_new <= 0'\'' failed.' ++ declare -- bret=134 ++ ++ 'berr=++++ git_am https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-6-indu.bhagat@oracle.com/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-6-indu.bhagat@oracle.com/mbox/ ++++ curl https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-6-indu.bhagat@oracle.com/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 270k 100 270k 0 0 4753k 0 --:--:-- --:--:-- --:--:-- 4753k +++ bout='\''git: apply.c:3717: check_preimage: Assertion `patch->is_new <= 0'\''\'\'''\'' failed.'\'' +++ bret=134' /tmp/jenkins8128469799047977168.sh: line 135: ++: command not found ++ ++ declare -p berr /tmp/jenkins8128469799047977168.sh: line 136: ++: command not found ++ declare -- 'berr=++++ git_am https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-6-indu.bhagat@oracle.com/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-6-indu.bhagat@oracle.com/mbox/ ++++ curl https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-6-indu.bhagat@oracle.com/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 270k 100 270k 0 0 4753k 0 --:--:-- --:--:-- --:--:-- 4753k +++ bout='\''git: apply.c:3717: check_preimage: Assertion `patch->is_new <= 0'\''\'\'''\'' failed.'\'' +++ bret=134' ++ git rev-parse HEAD + commitid_after=6675f325721056d5548b6dff5cd0cebe13c111a5 + '[' 134 = 0 ']' + [[ ++++ git_am https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-6-indu.bhagat@oracle.com/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-6-indu.bhagat@oracle.com/mbox/ ++++ curl https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-6-indu.bhagat@oracle.com/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 270k 100 270k 0 0 4753k 0 --:--:-- --:--:-- --:--:-- 4753k +++ bout='git: apply.c:3717: check_preimage: Assertion `patch->is_new <= 0'\'' failed.' +++ bret=134 =~ sha1 information is lacking or useless ]] + [[ ++++ git_am https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-6-indu.bhagat@oracle.com/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-6-indu.bhagat@oracle.com/mbox/ ++++ curl https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-6-indu.bhagat@oracle.com/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 270k 100 270k 0 0 4753k 0 --:--:-- --:--:-- --:--:-- 4753k +++ bout='git: apply.c:3717: check_preimage: Assertion `patch->is_new <= 0'\'' failed.' +++ bret=134 =~ Failed to merge in the changes ]] + [[ ++++ git_am https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-6-indu.bhagat@oracle.com/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-6-indu.bhagat@oracle.com/mbox/ ++++ curl https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-6-indu.bhagat@oracle.com/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 270k 100 270k 0 0 4753k 0 --:--:-- --:--:-- --:--:-- 4753k +++ bout='git: apply.c:3717: check_preimage: Assertion `patch->is_new <= 0'\'' failed.' +++ bret=134 =~ corrupt patch at ]] + [[ ++++ git_am https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-6-indu.bhagat@oracle.com/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-6-indu.bhagat@oracle.com/mbox/ ++++ curl https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-6-indu.bhagat@oracle.com/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 270k 100 270k 0 0 4753k 0 --:--:-- --:--:-- --:--:-- 4753k +++ bout='git: apply.c:3717: check_preimage: Assertion `patch->is_new <= 0'\'' failed.' +++ bret=134 =~ patch fragment without header at ]] + [[ ++++ git_am https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-6-indu.bhagat@oracle.com/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-6-indu.bhagat@oracle.com/mbox/ ++++ curl https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-6-indu.bhagat@oracle.com/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 270k 100 270k 0 0 4753k 0 --:--:-- --:--:-- --:--:-- 4753k +++ bout='git: apply.c:3717: check_preimage: Assertion `patch->is_new <= 0'\'' failed.' +++ bret=134 =~ No valid patches in input ]] + submit_check fail 'Not Applicable' https://patchwork.plctlab.org/jenkins/job/binutils-gdb/338/consoleText 'Git am fail log' + check_state=fail + patch_state='Not Applicable' + repo_url=https://patchwork.plctlab.org/jenkins/job/binutils-gdb/338/consoleText + DESCRIPTION='Git am fail log' + curl -X POST -H 'Authorization: Token [*******]' -F state=fail -F target_url=https://patchwork.plctlab.org/jenkins/job/binutils-gdb/338/consoleText -F context=binutils-gdb-check -F 'description=Git am fail log' https://patchwork.plctlab.org/api/patches/17406/checks/ % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 969 100 427 100 542 12558 15941 --:--:-- --:--:-- --:--:-- 28500 {"id":1959,"url":"https://patchwork.plctlab.org/api/patches/17406/checks/1959/","user":{"id":1,"url":"https://patchwork.plctlab.org/api/users/1/","username":"snail","first_name":"","last_name":"","email":"wangliu@iscas.ac.cn"},"date":"2022-11-09T09:21:56.933380","state":"fail","target_url":"https://patchwork.plctlab.org/jenkins/job/binutils-gdb/338/consoleText","context":"binutils-gdb-check","description":"Git am fail log"}+ curl -X PATCH -H 'Authorization: Token [*******]' -F 'state=Not Applicable' https://patchwork.plctlab.org/api/1.2/patches/17406/ % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0{"id":17406,"url":"https://patchwork.plctlab.org/api/1.2/patches/17406/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-7-indu.bhagat@oracle.com/","project":{"id":2,"url":"https://patchwork.plctlab.org/api/1.2/projects/2/","name":"binutils-gdb","link_name":"binutils-gdb","list_id":"binutils.sourceware.org","list_email":"binutils@sourceware.org","web_url":"https://github.com/wangliu-iscas/Patchwork-Bundles/blob/main/binutils-gdb.md","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20221109084244.261296-7-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-09T08:42:39","name":"[V4,06/11] bfd: linker: merge .sframe sections","commit_ref":null,"pull_url":null,"state":"not-applicable","archived":false,"hash":"badf47ca3b4334b12ea31be38263a1613a165871","submitter":{"id":35,"url":"https://patchwork.plctlab.org/api/1.2/people/35/","name":"Indu Bhagat","email":"indu.bhagat@oracle.com"},"delegate":null,"mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-7-indu.bhagat@oracle.com/mbox/","series":[{"id":6804,"url":"https://patchwork.plctlab.org/api/1.2/series/6804/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/list/?series=6804","date":"2022-11-09T08:42:33","name":"Definition and support for SFrame unwind format","version":4,"mbox":"https://patchwork.plctlab.org/series/6804/mbox/"}],"comments":"https://patchwork.plctlab.org/api/patches/17406/comments/","check":"fail","checks":"https://patchwork.plctlab.org/api/patches/17406/checks/","tags":{},"headers":{"Return-Path":"","Delivered-To":["ouuuleilei@gmail.com","binutils@sourceware.org"],"Received":["by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp222627wru;\n Wed, 9 Nov 2022 00:50:43 -0800 (PST)","from sourceware.org (server2.sourceware.org.\n [2620:52:3:1:0:246e:9693:128c])\n by mx.google.com with ESMTPS id\n c16-20020a05640227d000b00461dc830100si14567196ede.452.2022.11.09.00.50.42\n for \n (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256);\n Wed, 09 Nov 2022 00:50:42 -0800 (PST)","from server2.sourceware.org (localhost [IPv6:::1])\n\tby sourceware.org (Postfix) with ESMTP id 2777038A814D\n\tfor ; Wed, 9 Nov 2022 08:47:46 +0000 (GMT)","from mx0a-00069f02.pphosted.com (mx0a-00069f02.pphosted.com\n [205.220.165.32])\n by sourceware.org (Postfix) with ESMTPS id 88A74385840A\n for ; Wed, 9 Nov 2022 08:43:46 +0000 (GMT)","from pps.filterd (m0246629.ppops.net [127.0.0.1])\n by mx0b-00069f02.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id\n 2A98arlW028817;\n Wed, 9 Nov 2022 08:43:43 GMT","from phxpaimrmta01.imrmtpd1.prodappphxaev1.oraclevcn.com\n (phxpaimrmta01.appoci.oracle.com [138.1.114.2])\n by mx0b-00069f02.pphosted.com (PPS) with ESMTPS id 3kr8urr1jq-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK);\n Wed, 09 Nov 2022 08:43:35 +0000","from pps.filterd\n (phxpaimrmta01.imrmtpd1.prodappphxaev1.oraclevcn.com [127.0.0.1])\n by phxpaimrmta01.imrmtpd1.prodappphxaev1.oraclevcn.com (8.17.1.5/8.17.1.5)\n with ESMTP id 2A97xGQj004265; Wed, 9 Nov 2022 08:43:21 GMT","from nam12-mw2-obe.outbound.protection.outlook.com\n (mail-mw2nam12lp2041.outbound.protection.outlook.com [104.47.66.41])\n by phxpaimrmta01.imrmtpd1.prodappphxaev1.oraclevcn.com (PPS) with ESMTPS id\n 3kpcq33jkd-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK);\n Wed, 09 Nov 2022 08:43:21 +0000","from MWHPR1001MB2158.namprd10.prod.outlook.com\n (2603:10b6:301:2d::17) by CO1PR10MB4772.namprd10.prod.outlook.com\n (2603:10b6:303:94::11) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5769.19; Wed, 9 Nov\n 2022 08:43:17 +0000","from MWHPR1001MB2158.namprd10.prod.outlook.com\n ([fe80::a505:15c2:a248:efa2]) by MWHPR1001MB2158.namprd10.prod.outlook.com\n ([fe80::a505:15c2:a248:efa2%7]) with mapi id 15.20.5723.033; Wed, 9 Nov 2022\n 08:43:17 +0000"],"X-Google-Smtp-Source":"\n AMsMyM6AQ+2F1z8XtZauAdirJWHgwy99zVmk3ARJQFAammUn0nCrwEqmiTogDJX6xohENQSAVwkg","X-Received":"by 2002:a17:906:8a48:b0:7ab:afd4:d7ed with SMTP id\n gx8-20020a1709068a4800b007abafd4d7edmr1095681ejc.228.1667983842855;\n Wed, 09 Nov 2022 00:50:42 -0800 (PST)","Received-SPF":"pass (google.com: domain of\n binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates\n 2620:52:3:1:0:246e:9693:128c as permitted sender)\n client-ip=2620:52:3:1:0:246e:9693:128c;","Authentication-Results":"mx.google.com;\n dkim=pass header.i=@sourceware.org header.s=default header.b=SZC00EGe;\n arc=fail (signature failed);\n spf=pass (google.com: domain of\n binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates\n 2620:52:3:1:0:246e:9693:128c as permitted sender)\n smtp.mailfrom=\"binutils-bounces+ouuuleilei=gmail.com@sourceware.org\";\n dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=sourceware.org","DKIM-Filter":"OpenDKIM Filter v2.11.0 sourceware.org 2777038A814D","DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org;\n\ts=default; t=1667983666;\n\tbh=9ojEWhXCgvNLfG3cNmyu7Fi2kOS6uNXCjeZakUtFMJo=;\n\th=To:Cc:Subject:Date:In-Reply-To:References:List-Id:\n\t List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe:\n\t From:Reply-To:From;\n\tb=SZC00EGeppW3JpYsxn6KthpTS9QkuWh/IfU00mp8TD82icMZrdbBGiThZcfLd9ThR\n\t k+zl9V9imFmH3jVTMi13Sa60vJ5gO91FIpcplaibqs545K8eXCtJe+E85LcRzZs/to\n\t f6r1gqZhKVNzunzbIuoT3aYI6uGr+lonb2NnOZ20=","X-Original-To":"binutils@sourceware.org","DMARC-Filter":"OpenDMARC Filter v1.4.1 sourceware.org 88A74385840A","ARC-Seal":"i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none;\n b=aHGTCbMFFNu4ZvGoY2c6+n/1EfcxPLjmiEdPHX1kVB6xNsQNNT1H4WWSh+Zv49Rcix0W1btfNkX1KZZ/ikwpZcfmbOMacGWcHYoI6gR+rG7BfFiZ2g+MhVnb77UEfWN5paEfAnbBWgYXt9vAzEfFZiWLlQQaW91jorN2kcWJllNcKIHQt8g9WcSzYCBz68LZpXaOcU8daeWm/YgZ0+fiST4tWL/3ObUoJYIBP/xYxH71bAotxx5HrCbnUyvmeKCKJjEdhgTXIpKIIeyyl4MArSE5paWXl5J9oND6chrOJJbvCYKIpvsLZPqzbp21XqtUQtgfPvSUW2Hf42B7L/673Q==","ARC-Message-Signature":"i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com;\n s=arcselector9901;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1;\n bh=9ojEWhXCgvNLfG3cNmyu7Fi2kOS6uNXCjeZakUtFMJo=;\n b=ASUK5WRSqW3Dt9waPCbvtVySy0tyBVyavKNHLoZfilhTwbsDaEufO/AkFh1lIGNYxWuDIDZS80zOkAcG/yhYhkxRVEJzW8vpWlh4zNKwdOQRBIOdl+jDzVRsiO7E3c0mF6mSm13XtA+DFW9mMleEPHMIIolZatEuK+eq5r/F52Li9IVhsZTq2ViM8hJU52MnzpNE4d7glFeqACGNM6ncEJQPjDTzDJVsr7yGQR9gEaiUrcHEqCNaHOfxwfyHAv03f+g6+gaZFMQ3PQZ6xu4G/gAqwrMZ3XDcveH0cRK51n6KmuQ10qX3YGN84Sd/rIs2h170hLayH9oCatW62QedRQ==","ARC-Authentication-Results":"i=1; mx.microsoft.com 1; spf=pass\n smtp.mailfrom=oracle.com; dmarc=pass action=none header.from=oracle.com;\n dkim=pass header.d=oracle.com; arc=none","To":"binutils@sourceware.org","Cc":"weimin.pan@oracle.com, nickc@redhat.com,\n Indu Bhagat ","Subject":"[PATCH,V4 06/11] bfd: linker: merge .sframe sections","Date":"Wed, 9 Nov 2022 00:42:39 -0800","Message-Id":"<20221109084244.261296-7-indu.bhagat@oracle.com>","X-Mailer":"git-send-email 2.37.2","In-Reply-To":"<20221109084244.261296-1-indu.bhagat@oracle.com>","References":"<20221109084244.261296-1-indu.bhagat@oracle.com>","Content-Transfer-Encoding":"8bit","Content-Type":"text/plain","X-ClientProxiedBy":"MW4PR03CA0025.namprd03.prod.outlook.com\n (2603:10b6:303:8f::30) To MWHPR1001MB2158.namprd10.prod.outlook.com\n (2603:10b6:301:2d::17)","MIME-Version":"1.0","X-MS-PublicTrafficType":"Email","X-MS-TrafficTypeDiagnostic":"MWHPR1001MB2158:EE_|CO1PR10MB4772:EE_","X-MS-Office365-Filtering-Correlation-Id":"51074fcb-d705-4ea1-de65-08dac22e7255","X-MS-Exchange-SenderADCheck":"1","X-MS-Exchange-AntiSpam-Relay":"0","X-Microsoft-Antispam":"BCL:0;","X-Microsoft-Antispam-Message-Info":"\n 6/SHa1V5rHmW8Zk6bcT3FPXpWCc+OhCG4SyKUeual09+cWqRYW29eUOaVTopJEH8LGm0guDax4zPcofJTeanMW7JMsbg/m04XiirBrKgRmhy5uN17MmEUuJvwmp7eUN0ljsUjF57r1qBRBVomyoMnN9K20arbiwkJeWzlNkonljbXF8Bwddk4JI8cPz7E52dJ6t6shmAGairfty85jZQdujiwTojaJVMKi7Hylfc1mfMXpK5kvekUa/87r+WopVkw1naCw2+3F3LRzIpft2tNybBFtFJAPhXUF7zfcbx37GbCKz+p+luB3hBnDOMaBNVgeCkOuk8TG0ahggmrJ0MfI23E3ZzdCv0hDQIxv9UuPDJgYjqzjXHX1Wk4rSphuu2+IGO91N4LJGArqjj4bPO9K0gyoi+HfWyLcoFI16F6FkXrHmYX/9vuDdon29hlnPbHGeWPXx2JI9imf3HntJEwjpgqw2e7m6iKNqOt9PFbDNswodPULHYmwAzjM9QC7fyCnuphUGnoXgJUQQuDnSdQV8wiL7058VPFb90/6+gZKH6UPo3LGJUIySUFb2T1cmhdXFJo0G546nF+gy82XXbN2tu5xQmqdC+jZKrOyAn8X0QXQ3yZXFPbdfeQhj0kEN68KW64GY4YRw+cmcZAi4zjX0qtNMthY1+RhYYauRTcStBB5EAcOlSF4qIIbEEFHSZJncuS2R6BvP6Ua2wkt9iCbNca3W2lNOhzkKcBZAD/VG/7l9SvOvjcmeml9e/r5F9tAUz/exkTeQS7nDh+2F3bA==","X-Forefront-Antispam-Report":"CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:;\n IPV:NLI; SFV:NSPM; H:MWHPR1001MB2158.namprd10.prod.outlook.com; PTR:;\n CAT:NONE;\n SFS:(13230022)(346002)(136003)(39860400002)(366004)(396003)(376002)(451199015)(66476007)(66556008)(6512007)(8676002)(86362001)(6506007)(44832011)(4326008)(66946007)(5660300002)(30864003)(83380400001)(8936002)(38100700002)(2906002)(36756003)(41300700001)(6916009)(186003)(2616005)(6486002)(107886003)(316002)(6666004)(478600001)(1076003)(142923001)(2004002)(559001)(579004);\n DIR:OUT; SFP:1101;","X-MS-Exchange-AntiSpam-MessageData-ChunkCount":"1","X-MS-Exchange-AntiSpam-MessageData-0":"\n SaN4ycJ0zfjqVcjIRItntMRK5EfovlQlwnYFkC6OIWFdM4BKCVw/GeAm0XXkkECMbiySSerkGAB5ADbAEVFg/RIK9HOl/QRO1Dxv9HoWBO+mdJX7gIyA5Z/Q+n6k1JDYfDy14bVI4d9YPd4Uu58eZmUPwsnlPiZ7lqOH2SXpycRz1WmNXanDv1OupdffKLt51XxZd5ndfLHZkU4HjvGLemy0Xv3BxnUHy9MzsuWAVzA5HnXv3knzBo8TXSBtC/bjhhBzCAzjrTq9aMxPY75oysFXKVIrOaVI7zoxnFFnTnfxrKqdxT+AdWlUscfVFrCsC1aheaf26Dg5/Jzqv7QGz4Bg55MDfcw9iMg1SuQBEHB4LIYh4Gwb+RxWBes4q+LwKiJfYp0dgwNR1IUBI3/dRG9ikNjSqYlzz4Jfjj5+VhbXE2zazec4cYll4dVkCPXyBW/uJPKU7gXwjHxtZniggSVfThUHR7EdYEsCELf72HtN04COaIXDQADnSieZCs2s5GBBQKGz/XCqSZnd5ErjxcJoD/2x88oe/pOViJ5jEnpKLgWeYsEeLYquL/oGLah6JXT2uCywDWhWmUHvI4SYVMcn9ncDIiSbJu+95khIAKeLb5p5FBXmGUD9QFlUIMp7pxg+LwRMlCULBvJlHcPl9lPmEmpsgbIwLvBoles7WAfgI3QRiaVDwdDAnKJIbPXqWRnwrp5xcoUrvaEIPEUVybbQiqTj0wNHovdtWL6cLz51KrKNZw4aDse91825bdmf8822glZMsyXWnXve9HvYkaqS5xUFaybB2jjdWjAjPYWVXUvae6eW3aeVm8lij7xnI+0z7sVbusizaYqMrM6+Auuo/afJN5oiyPOF3k08sJ0fsWE/sQNfqAeJvb5JNyMrz208ykRR2s8x1zwif0stpsrT+uGZsaIPfNsgNfYSwtZAiD92rXRxyTISx28IbS4R46hUefuuyM/oVXP/uSJcU3XchYmBRyWLAXaQUX9qFLFTBeayW7egdUTpGJnYV371dnfKNgQWVUUu+Uty/pXNYZJ+BY+KlL5Xya3lXT0HeUgZkKdge91NTh8g30wzzTxnlObCdBtRvvw88rYYRs1ck4QDWcLpz0cRJjcqbN87BujX7AfTA2jg22SPc8xlk1PYaRPJvXbhEbgEBaSfevIv2NSN+q803xJuqNLWqQCZIXXvP1FqoZgGvio5aKkanFZ48LjEr9yaWDmFvn3L//AIUoqlxZ7X0SqkmVVAauX17Yw8NRJsnkzculbBm7Sx8VehZK4bhs/IY3m9USR5/Dk4C0x6DV9IMY+1hndmhmfJptyVNDy0G844vUhFxGa1V3X6duYsPgOcGuBibH/dRMQBvJoywpLDk7qhmcc9aieItHQRWlDOq3YpbnoClVYtbJvcKCdTm1zYAiitCnT+yFE+qCmv9GdDVGXVal7dmMmRJvI+onHtyA4JvThfqt6K7zkuGde9xymcp8r2/PHbbOOjc/s2IKCUdR14LbdsAqk8bcd/l7UOEXQ6jfd2X5XuKyN92AcfqRokXYlOXJSz0hHoQf4B/pySQeyE6wuPfCtVqCdCSDAMKkrH/DgbU7+m40jmsy1sHrml84HF4AVocjDhoB6UQonLiuzE+1JRgyyXPzo=","X-OriginatorOrg":"oracle.com","X-MS-Exchange-CrossTenant-Network-Message-Id":"\n 51074fcb-d705-4ea1-de65-08dac22e7255","X-MS-Exchange-CrossTenant-AuthSource":"\n MWHPR1001MB2158.namprd10.prod.outlook.com","X-MS-Exchange-CrossTenant-AuthAs":"Internal","X-MS-Exchange-CrossTenant-OriginalArrivalTime":"09 Nov 2022 08:43:17.1829 (UTC)","X-MS-Exchange-CrossTenant-FromEntityHeader":"Hosted","X-MS-Exchange-CrossTenant-Id":"4e2c6054-71cb-48f1-bd6c-3a9705aca71b","X-MS-Exchange-CrossTenant-MailboxType":"HOSTED","X-MS-Exchange-CrossTenant-UserPrincipalName":"\n V20vVO9UvNVVJjOGbxCfI5f4gdd9w/uZ2KidcQEcI6lEDRwGVPuOLk4AqJSCAihKAE1GVKwfNjPtmHsoliCXRA==","X-MS-Exchange-Transport-CrossTenantHeadersStamped":"CO1PR10MB4772","X-Proofpoint-Virus-Version":"vendor=baseguard\n engine=ICAP:2.0.219,Aquarius:18.0.895,Hydra:6.0.545,FMLib:17.11.122.1\n definitions=2022-11-09_03,2022-11-08_01,2022-06-22_01","X-Proofpoint-Spam-Details":"rule=notspam policy=default score=0 bulkscore=0\n spamscore=0 adultscore=0\n malwarescore=0 mlxlogscore=999 mlxscore=0 phishscore=0 suspectscore=0\n classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2210170000\n definitions=main-2211090066","X-Proofpoint-GUID":"uTuNzGHdX0zbTcx9tG2jmDiEuEmIfv2Q","X-Proofpoint-ORIG-GUID":"uTuNzGHdX0zbTcx9tG2jmDiEuEmIfv2Q","X-Spam-Status":"No, score=-12.7 required=5.0 tests=BAYES_00, DKIM_SIGNED,\n DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_DNSWL_LOW,\n RCVD_IN_MSPIKE_H2, SCC_5_SHORT_WORD_LINES, SPF_HELO_NONE, SPF_NONE,\n TXREP autolearn=ham autolearn_force=no version=3.4.6","X-Spam-Checker-Version":"SpamAssassin 3.4.6 (2021-04-09) on\n server2.sourceware.org","X-BeenThere":"binutils@sourceware.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"Binutils mailing list ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","From":"Indu Bhagat via Binutils ","Reply-To":"Indu Bhagat ","Errors-To":"binutils-bounces+ouuuleilei=gmail.com@sourceware.org","Sender":"\"Binutils\" ","X-getmail-retrieved-from-mailbox":"=?utf-8?q?INBOX?=","X-GMAIL-THRID":"=?utf-8?q?1749007826235988229?=","X-GMAIL-MSGID":"=?utf-8?q?1749007826235988229?="},"content":"[No Changes in V4]\n\n[Changes in V3]\n - sframe_encode () now has explicit arguments for passing fixed RA and\n fixed FP offsets.\n[End of changes in V3]\n\n[Changes in V2]\n - Minor code improvements, formatting touch-ups\n - ld testsuite: check if as supports SFrame before running sframe\n tests.\n - Changes to support auxilliary SFrame header.\n[End of changes in V2]\n\nThe linker merges all the input .sframe sections. When merging, the\nlinker verifies that all the input .sframe sections have the same\nabi/arch.\n\nThe linker uses libsframe library to perform key actions on the\n.sframe sections - decode, read, and create output data. This\nimplies buildsystem changes to make and install libsframe before\nlibbfd.\n\nThe linker places the output .sframe section in a new segment of its\nown: PT_GNU_SFRAME. A new segment is not added, however, if the\ngenerated .sframe section is empty.\n\nWhen a section is discarded from the final link, the corresponding\nentries in the .sframe section for those functions are also deleted.\n\nThe linker sorts the SFrame FDEs on start address by default and sets\nthe SFRAME_F_FDE_SORTED flag in the .sframe section.\n\nThis patch also adds support for generation of SFrame unwind\ninformation for the .plt* sections on x86_64. SFrame unwind info is\ngenerated for IBT enabled PLT, lazy/non-lazy PLT.\n\nThe existing linker option --no-ld-generated-unwind-info has been\nadapted to include the control of whether .sframe unwind information\nwill be generated for the linker generated sections like PLT.\n\nChanges to the linker script have been made as necessary.\n\nChangeLog:\n\n\t* Makefile.def: Add install dependency on libsframe for libbfd.\n\t* Makefile.in: Regenerated.\n\t* bfd/Makefile.am: Add elf-sframe.c\n\t* bfd/Makefile.in: Regenerated.\n\t* bfd/bfd-in2.h (SEC_INFO_TYPE_SFRAME): Regenerated.\n\t* bfd/configure: Regenerate.\n\t* bfd/configure.ac: Add elf-sframe.lo.\n\t* bfd/elf-bfd.h (struct sframe_func_bfdinfo): New struct.\n\t(struct sframe_dec_info): Likewise.\n\t(struct sframe_enc_info): Likewise.\n\t(struct elf_link_hash_table): New member for encoded .sframe\n\tobject.\n\t(struct output_elf_obj_tdata): New member.\n\t(elf_sframe): New access macro.\n\t(_bfd_elf_set_section_sframe): New declaration.\n\t* bfd/elf.c (get_segment_type): Handle new segment\n\tPT_GNU_SFRAME.\n\t(bfd_section_from_phdr): Likewise.\n\t(get_program_header_size): Likewise.\n\t(_bfd_elf_map_sections_to_segments): Likewise.\n\t* bfd/elf64-x86-64.c (elf_x86_64_link_setup_gnu_properties): Add\n\tcontents to the .sframe sections or .plt* entries.\n\t* bfd/elflink.c (elf_section_ignore_discarded_relocs): Handle\n\tSEC_INFO_TYPE_SFRAME.\n\t(_bfd_elf_default_action_discarded): Handle .sframe section.\n\t(elf_link_input_bfd): Merge .sframe section.\n\t(bfd_elf_final_link): Write the output .sframe section.\n\t(bfd_elf_discard_info): Handle discarding .sframe section.\n\t* bfd/elfxx-x86.c (_bfd_x86_elf_size_dynamic_sections): Create\n\t.sframe section for .plt and .plt.sec.\n\t(_bfd_x86_elf_finish_dynamic_sections): Handle .sframe from\n\t.plt* sections.\n\t* bfd/elfxx-x86.h (PLT_SFRAME_FDE_START_OFFSET): New\n\tdefinition.\n\t(SFRAME_PLT0_MAX_NUM_FRES): Likewise.\n\t(SFRAME_PLTN_MAX_NUM_FRES): Likewise.\n\t(struct elf_x86_sframe_plt): New structure.\n\t(struct elf_x86_link_hash_table): New member.\n\t(struct elf_x86_init_table): New members for .sframe\n\tcreation.\n\t* bfd/section.c: Add new definition SEC_INFO_TYPE_SFRAME.\n\t* binutils/readelf.c (get_segment_type): Handle new segment\n\tPT_GNU_SFRAME.\n\t* ld/ld.texi: Update documentation for\n\t--no-ld-generated-unwind-info.\n\t* ld/scripttempl/elf.sc: Support .sframe sections.\n\t* Makefile.am (TESTSFRAMELIB): Use it.\n\t(check-DEJAGNU): Likewise.\n\t* configure.ac (TESTSFRAMELIB): Set to the .so or .a like TESTBFDLIB.\n\t* testsuite/ld-bootstrap/bootstrap.exp: Add SFRAMELIB.\n\t* bfd/elf-sframe.c: New file.\n\ninclude/ChangeLog:\n\n\t* elf/common.h (PT_GNU_SFRAME): New definition.\n\t* elf/internal.h (struct elf_segment_map): Handle new segment\n\ttype PT_GNU_SFRAME.\n\nld/testsuite/ChangeLog:\n\n\t* ld/testsuite/ld-aarch64/aarch64-elf.exp: Add new test\n\t sframe-simple-1.\n\t* ld/testsuite/ld-aarch64/sframe-bar.s: New file.\n\t* ld/testsuite/ld-aarch64/sframe-foo.s: Likewise.\n\t* ld/testsuite/ld-aarch64/sframe-simple-1.d: Likewise.\n\t* ld/testsuite/ld-sframe/sframe-empty.d: New test.\n\t* ld/testsuite/ld-sframe/sframe-empty.s: New file.\n\t* ld/testsuite/ld-sframe/sframe.exp: New testsuite.\n\t* ld/testsuite/ld-x86-64/sframe-bar.s: New file.\n\t* ld/testsuite/ld-x86-64/sframe-foo.s: Likewise.\n\t* ld/testsuite/ld-x86-64/sframe-simple-1.d: Likewise.\n\t* ld/testsuite/ld-x86-64/sframe-plt-1.d: Likewise.\n\t* ld/testsuite/ld-x86-64/sframe-simple-1.d: Likewise.\n\t* ld/testsuite/ld-x86-64/x86-64.exp: Add new tests -\n\t sframe-simple-1, sframe-plt-1.\n\t* ld/testsuite/lib/ld-lib.exp: Add new proc to check if\n\t assembler supports SFrame section.\n\t* ld/testsuite/ld-sframe/discard.d: New file.\n\t* ld/testsuite/ld-sframe/discard.ld: Likewise.\n\t* ld/testsuite/ld-sframe/discard.s: Likewise.\n---\n Makefile.def | 4 +\n Makefile.in | 11 +\n bfd/Makefile.am | 6 +-\n bfd/Makefile.in | 7 +-\n bfd/bfd-in2.h | 1 +\n bfd/configure | 2 +-\n bfd/configure.ac | 2 +-\n bfd/elf-bfd.h | 54 +++\n bfd/elf-sframe.c | 544 ++++++++++++++++++++++\n bfd/elf.c | 32 ++\n bfd/elf64-x86-64.c | 97 +++-\n bfd/elflink.c | 52 +++\n bfd/elfxx-x86.c | 375 ++++++++++++++-\n bfd/elfxx-x86.h | 49 ++\n bfd/section.c | 1 +\n binutils/readelf.c | 1 +\n include/elf/common.h | 1 +\n include/elf/internal.h | 1 +\n include/sframe-api.h | 2 +-\n ld/Makefile.am | 2 +\n ld/Makefile.in | 2 +\n ld/configure | 8 +-\n ld/configure.ac | 3 +\n ld/ld.texi | 4 +-\n ld/scripttempl/elf.sc | 2 +\n ld/testsuite/ld-aarch64/aarch64-elf.exp | 4 +\n ld/testsuite/ld-aarch64/sframe-bar.s | 7 +\n ld/testsuite/ld-aarch64/sframe-foo.s | 10 +\n ld/testsuite/ld-aarch64/sframe-simple-1.d | 26 ++\n ld/testsuite/ld-bootstrap/bootstrap.exp | 8 +-\n ld/testsuite/ld-sframe/discard.d | 10 +\n ld/testsuite/ld-sframe/discard.ld | 9 +\n ld/testsuite/ld-sframe/discard.s | 13 +\n ld/testsuite/ld-sframe/sframe-empty.d | 10 +\n ld/testsuite/ld-sframe/sframe-empty.s | 2 +\n ld/testsuite/ld-sframe/sframe.exp | 47 ++\n ld/testsuite/ld-x86-64/sframe-bar.s | 31 ++\n ld/testsuite/ld-x86-64/sframe-foo.s | 37 ++\n ld/testsuite/ld-x86-64/sframe-plt-1.d | 29 ++\n ld/testsuite/ld-x86-64/sframe-simple-1.d | 35 ++\n ld/testsuite/ld-x86-64/x86-64.exp | 5 +\n ld/testsuite/lib/ld-lib.exp | 45 ++\n libsframe/sframe.c | 28 +-\n 43 files changed, 1595 insertions(+), 24 deletions(-)\n create mode 100644 bfd/elf-sframe.c\n create mode 100644 ld/testsuite/ld-aarch64/sframe-bar.s\n create mode 100644 ld/testsuite/ld-aarch64/sframe-foo.s\n create mode 100644 ld/testsuite/ld-aarch64/sframe-simple-1.d\n create mode 100644 ld/testsuite/ld-sframe/discard.d\n create mode 100644 ld/testsuite/ld-sframe/discard.ld\n create mode 100644 ld/testsuite/ld-sframe/discard.s\n create mode 100644 ld/testsuite/ld-sframe/sframe-empty.d\n create mode 100644 ld/testsuite/ld-sframe/sframe-empty.s\n create mode 100644 ld/testsuite/ld-sframe/sframe.exp\n create mode 100644 ld/testsuite/ld-x86-64/sframe-bar.s\n create mode 100644 ld/testsuite/ld-x86-64/sframe-foo.s\n create mode 100644 ld/testsuite/ld-x86-64/sframe-plt-1.d\n create mode 100644 ld/testsuite/ld-x86-64/sframe-simple-1.d","diff":"diff --git a/Makefile.def b/Makefile.def\nindex 1b39c910447..f974565d8ca 100644\n--- a/Makefile.def\n+++ b/Makefile.def\n@@ -458,11 +458,14 @@ dependencies = { module=all-gdbsupport; on=all-gnulib; };\n dependencies = { module=all-gdbsupport; on=all-intl; };\n \n // Host modules specific to binutils.\n+// build libsframe before bfd for encoder/decoder support for linking\n+// SFrame sections\n dependencies = { module=configure-bfd; on=configure-libiberty; hard=true; };\n dependencies = { module=configure-bfd; on=configure-intl; };\n dependencies = { module=all-bfd; on=all-libiberty; };\n dependencies = { module=all-bfd; on=all-intl; };\n dependencies = { module=all-bfd; on=all-zlib; };\n+dependencies = { module=all-bfd; on=all-libsframe; };\n dependencies = { module=configure-opcodes; on=configure-libiberty; hard=true; };\n dependencies = { module=all-opcodes; on=all-libiberty; };\n \n@@ -488,6 +491,7 @@ dependencies = { module=install-binutils; on=install-opcodes; };\n dependencies = { module=install-strip-binutils; on=install-strip-opcodes; };\n \n // Likewise for ld, libctf, and bfd.\n+dependencies = { module=install-bfd; on=install-libsframe; };\n dependencies = { module=install-libctf; on=install-bfd; };\n dependencies = { module=install-ld; on=install-bfd; };\n dependencies = { module=install-ld; on=install-libctf; };\ndiff --git a/Makefile.in b/Makefile.in\nindex b26f778a94a..a425b54e094 100644\n--- a/Makefile.in\n+++ b/Makefile.in\n@@ -64407,6 +64407,16 @@ all-stagetrain-bfd: maybe-all-stagetrain-zlib\n all-stagefeedback-bfd: maybe-all-stagefeedback-zlib\n all-stageautoprofile-bfd: maybe-all-stageautoprofile-zlib\n all-stageautofeedback-bfd: maybe-all-stageautofeedback-zlib\n+all-bfd: maybe-all-libsframe\n+all-stage1-bfd: maybe-all-stage1-libsframe\n+all-stage2-bfd: maybe-all-stage2-libsframe\n+all-stage3-bfd: maybe-all-stage3-libsframe\n+all-stage4-bfd: maybe-all-stage4-libsframe\n+all-stageprofile-bfd: maybe-all-stageprofile-libsframe\n+all-stagetrain-bfd: maybe-all-stagetrain-libsframe\n+all-stagefeedback-bfd: maybe-all-stagefeedback-libsframe\n+all-stageautoprofile-bfd: maybe-all-stageautoprofile-libsframe\n+all-stageautofeedback-bfd: maybe-all-stageautofeedback-libsframe\n configure-opcodes: configure-libiberty\n configure-stage1-opcodes: configure-stage1-libiberty\n configure-stage2-opcodes: configure-stage2-libiberty\n@@ -64539,6 +64549,7 @@ all-stageautoprofile-binutils: maybe-all-stageautoprofile-libsframe\n all-stageautofeedback-binutils: maybe-all-stageautofeedback-libsframe\n install-binutils: maybe-install-opcodes\n install-strip-binutils: maybe-install-strip-opcodes\n+install-bfd: maybe-install-libsframe\n install-libctf: maybe-install-bfd\n install-ld: maybe-install-bfd\n install-ld: maybe-install-libctf\ndiff --git a/bfd/Makefile.am b/bfd/Makefile.am\nindex b70d8f3ccea..85b6e71140f 100644\n--- a/bfd/Makefile.am\n+++ b/bfd/Makefile.am\n@@ -286,6 +286,7 @@ BFD32_BACKENDS = \\\n \tecofflink.lo \\\n \telf-attrs.lo \\\n \telf-eh-frame.lo \\\n+\telf-sframe.lo \\\n \telf-ifunc.lo \\\n \telf-m10200.lo \\\n \telf-m10300.lo \\\n@@ -419,6 +420,7 @@ BFD32_BACKENDS_CFILES = \\\n \tecofflink.c \\\n \telf-attrs.c \\\n \telf-eh-frame.c \\\n+\telf-sframe.c \\\n \telf-ifunc.c \\\n \telf-m10200.c \\\n \telf-m10300.c \\\n@@ -777,8 +779,8 @@ ofiles: stamp-ofiles ; @true\n # dependency tracking fragments are picked up in the Makefile.\n libbfd_la_SOURCES = $(BFD32_LIBS_CFILES)\n EXTRA_libbfd_la_SOURCES = $(CFILES)\n-libbfd_la_DEPENDENCIES = $(OFILES) ofiles\n-libbfd_la_LIBADD = `cat ofiles` @SHARED_LIBADD@ $(LIBDL) $(ZLIB) $(ZSTD_LIBS)\n+libbfd_la_DEPENDENCIES = $(OFILES) ofiles ../libsframe/libsframe.la\n+libbfd_la_LIBADD = `cat ofiles` @SHARED_LIBADD@ $(LIBDL) $(ZLIB) $(ZSTD_LIBS) ../libsframe/libsframe.la\n libbfd_la_LDFLAGS += -release `cat libtool-soversion` @SHARED_LDFLAGS@\n \n # libtool will build .libs/libbfd.a. We create libbfd.a in the build\ndiff --git a/bfd/Makefile.in b/bfd/Makefile.in\nindex b906976a1c0..ba1fd1bcc5e 100644\n--- a/bfd/Makefile.in\n+++ b/bfd/Makefile.in\n@@ -755,6 +755,7 @@ BFD32_BACKENDS = \\\n \tecofflink.lo \\\n \telf-attrs.lo \\\n \telf-eh-frame.lo \\\n+\telf-sframe.lo \\\n \telf-ifunc.lo \\\n \telf-m10200.lo \\\n \telf-m10300.lo \\\n@@ -888,6 +889,7 @@ BFD32_BACKENDS_CFILES = \\\n \tecofflink.c \\\n \telf-attrs.c \\\n \telf-eh-frame.c \\\n+\telf-sframe.c \\\n \telf-ifunc.c \\\n \telf-m10200.c \\\n \telf-m10300.c \\\n@@ -1207,8 +1209,8 @@ OFILES = $(BFD_BACKENDS) $(BFD_MACHINES) @COREFILE@ @bfd64_libs@\n # dependency tracking fragments are picked up in the Makefile.\n libbfd_la_SOURCES = $(BFD32_LIBS_CFILES)\n EXTRA_libbfd_la_SOURCES = $(CFILES)\n-libbfd_la_DEPENDENCIES = $(OFILES) ofiles\n-libbfd_la_LIBADD = `cat ofiles` @SHARED_LIBADD@ $(LIBDL) $(ZLIB) $(ZSTD_LIBS)\n+libbfd_la_DEPENDENCIES = $(OFILES) ofiles ../libsframe/libsframe.la\n+libbfd_la_LIBADD = `cat ofiles` @SHARED_LIBADD@ $(LIBDL) $(ZLIB) $(ZSTD_LIBS) ../libsframe/libsframe.la\n \n # libtool will build .libs/libbfd.a. We create libbfd.a in the build\n # directory so that we don't have to convert all the programs that use\n@@ -1574,6 +1576,7 @@ distclean-compile:\n @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf-m10300.Plo@am__quote@\n @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf-nacl.Plo@am__quote@\n @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf-properties.Plo@am__quote@\n+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf-sframe.Plo@am__quote@\n @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf-strtab.Plo@am__quote@\n @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf-vxworks.Plo@am__quote@\n @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf.Plo@am__quote@\ndiff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h\nindex e09259b7eae..0b071dda1e5 100644\n--- a/bfd/bfd-in2.h\n+++ b/bfd/bfd-in2.h\n@@ -994,6 +994,7 @@ typedef struct bfd_section\n #define SEC_INFO_TYPE_JUST_SYMS 4\n #define SEC_INFO_TYPE_TARGET 5\n #define SEC_INFO_TYPE_EH_FRAME_ENTRY 6\n+#define SEC_INFO_TYPE_SFRAME 7\n \n /* Nonzero if this section uses RELA relocations, rather than REL. */\n unsigned int use_rela_p:1;\ndiff --git a/bfd/configure b/bfd/configure\nindex 5c6e3821a13..74bc5a18471 100755\n--- a/bfd/configure\n+++ b/bfd/configure\n@@ -13582,7 +13582,7 @@ selarchs=\"$f\"\n tb=\n \n elf=\"elf.lo elflink.lo elf-attrs.lo elf-strtab.lo elf-eh-frame.lo\n- dwarf1.lo dwarf2.lo\"\n+ elf-sframe.lo dwarf1.lo dwarf2.lo\"\n coffgen=\"coffgen.lo dwarf2.lo\"\n coff=\"cofflink.lo $coffgen\"\n ecoff=\"ecofflink.lo $coffgen\"\ndiff --git a/bfd/configure.ac b/bfd/configure.ac\nindex 74c0f072225..5d450a4ad25 100644\n--- a/bfd/configure.ac\n+++ b/bfd/configure.ac\n@@ -383,7 +383,7 @@ selarchs=\"$f\"\n tb=\n \n elf=\"elf.lo elflink.lo elf-attrs.lo elf-strtab.lo elf-eh-frame.lo\n- dwarf1.lo dwarf2.lo\"\n+ elf-sframe.lo dwarf1.lo dwarf2.lo\"\n coffgen=\"coffgen.lo dwarf2.lo\"\n coff=\"cofflink.lo $coffgen\"\n ecoff=\"ecofflink.lo $coffgen\"\ndiff --git a/bfd/elf-bfd.h b/bfd/elf-bfd.h\nindex fa4b9bcf193..fc32fbe51e9 100644\n--- a/bfd/elf-bfd.h\n+++ b/bfd/elf-bfd.h\n@@ -490,6 +490,40 @@ struct eh_frame_hdr_info\n u;\n };\n \n+/* Additional information for each function (used at link time). */\n+struct sframe_func_bfdinfo\n+{\n+ /* Whether the function has been discarded from the final output. */\n+ bool func_deleted_p;\n+ /* Relocation offset. */\n+ unsigned int func_r_offset;\n+ /* Relocation index. */\n+ unsigned int func_reloc_index;\n+};\n+\n+/* SFrame decoder info.\n+ Contains all information for a decoded .sframe section. */\n+struct sframe_dec_info\n+{\n+ /* Decoder context. */\n+ struct sframe_decoder_ctx *sfd_ctx;\n+ /* Number of function descriptor entries in this .sframe. */\n+ unsigned int sfd_fde_count;\n+ /* Additional information for linking. */\n+ struct sframe_func_bfdinfo *sfd_func_bfdinfo;\n+};\n+\n+/* SFrame encoder info.\n+ Contains all information for an encoded .sframe section to be\n+ written out. */\n+struct sframe_enc_info\n+{\n+ /* Encoder context. */\n+ struct sframe_encoder_ctx *sfe_ctx;\n+ /* Output section. */\n+ asection *sframe_section;\n+};\n+\n /* Enum used to identify target specific extensions to the elf_obj_tdata\n and elf_link_hash_table structures. Note the enums deliberately start\n from 1 so that we can detect an uninitialized field. The generic value\n@@ -668,6 +702,9 @@ struct elf_link_hash_table\n /* Used by eh_frame code when editing .eh_frame. */\n struct eh_frame_hdr_info eh_info;\n \n+ /* Used to link unwind data in .sframe sections. */\n+ struct sframe_enc_info sfe_info;\n+\n /* A linked list of local symbols to be added to .dynsym. */\n struct elf_link_local_dynamic_entry *dynlocal;\n \n@@ -1944,6 +1981,10 @@ struct output_elf_obj_tdata\n /* Segment flags for the PT_GNU_STACK segment. */\n unsigned int stack_flags;\n \n+ /* Used to determine if PT_GNU_SFRAME segment header should be\n+ created. */\n+ asection *sframe;\n+\n /* Used to determine if the e_flags field has been initialized */\n bool flags_init;\n };\n@@ -2125,6 +2166,7 @@ struct elf_obj_tdata\n #define elf_link_info(bfd)\t(elf_tdata(bfd) -> o->link_info)\n #define elf_next_file_pos(bfd)\t(elf_tdata(bfd) -> o->next_file_pos)\n #define elf_stack_flags(bfd)\t(elf_tdata(bfd) -> o->stack_flags)\n+#define elf_sframe(bfd)\t\t(elf_tdata(bfd) -> o->sframe)\n #define elf_shstrtab(bfd)\t(elf_tdata(bfd) -> o->strtab_ptr)\n #define elf_onesymtab(bfd)\t(elf_tdata(bfd) -> symtab_section)\n #define elf_symtab_shndx_list(bfd)\t(elf_tdata(bfd) -> symtab_shndx_list)\n@@ -2439,6 +2481,18 @@ extern bool _bfd_elf_eh_frame_entry_present\n extern bool _bfd_elf_maybe_strip_eh_frame_hdr\n (struct bfd_link_info *);\n \n+extern bool _bfd_elf_sframe_present\n+ (struct bfd_link_info *);\n+extern bool _bfd_elf_parse_sframe\n+ (bfd *, struct bfd_link_info *, asection *, struct elf_reloc_cookie *);\n+extern bool _bfd_elf_discard_section_sframe\n+ (asection *, bool (*) (bfd_vma, void *), struct elf_reloc_cookie *);\n+extern bool _bfd_elf_merge_section_sframe\n+ (bfd *, struct bfd_link_info *, asection *, bfd_byte *);\n+extern bool _bfd_elf_write_section_sframe\n+ (bfd *, struct bfd_link_info *);\n+extern bool _bfd_elf_set_section_sframe (bfd *, struct bfd_link_info *);\n+\n extern bool _bfd_elf_hash_symbol (struct elf_link_hash_entry *);\n \n extern long _bfd_elf_link_lookup_local_dynindx\ndiff --git a/bfd/elf-sframe.c b/bfd/elf-sframe.c\nnew file mode 100644\nindex 00000000000..8055aa3ea3b\n--- /dev/null\n+++ b/bfd/elf-sframe.c\n@@ -0,0 +1,544 @@\n+/* .sframe section processing.\n+ Copyright (C) 2022 Free Software Foundation, Inc.\n+\n+ This file is part of BFD, the Binary File Descriptor library.\n+\n+ This program is free software; you can redistribute it and/or modify\n+ it under the terms of the GNU General Public License as published by\n+ the Free Software Foundation; either version 3 of the License, or\n+ (at your option) any later version.\n+\n+ This program is distributed in the hope that it will be useful,\n+ but WITHOUT ANY WARRANTY; without even the implied warranty of\n+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n+ GNU General Public License for more details.\n+\n+ You should have received a copy of the GNU General Public License\n+ along with this program; if not, write to the Free Software\n+ Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,\n+ MA 02110-1301, USA. */\n+\n+#include \"sysdep.h\"\n+#include \"bfd.h\"\n+#include \"libbfd.h\"\n+#include \"elf-bfd.h\"\n+#include \"sframe-api.h\"\n+\n+/* Return TRUE if the function has been marked for deletion during the linking\n+ process. */\n+\n+static bool\n+sframe_decoder_func_deleted_p (struct sframe_dec_info *sfd_info,\n+\t\t\t unsigned int func_idx)\n+{\n+ if (func_idx < sfd_info->sfd_fde_count)\n+ return sfd_info->sfd_func_bfdinfo[func_idx].func_deleted_p;\n+\n+ return false;\n+}\n+\n+/* Mark the function in the decoder info for deletion. */\n+\n+static void\n+sframe_decoder_mark_func_deleted (struct sframe_dec_info *sfd_info,\n+\t\t\t\t unsigned int func_idx)\n+{\n+ if (func_idx < sfd_info->sfd_fde_count)\n+ sfd_info->sfd_func_bfdinfo[func_idx].func_deleted_p = true;\n+}\n+\n+/* Get the relocation offset from the decoder info for the given function. */\n+\n+static unsigned int\n+sframe_decoder_get_func_r_offset (struct sframe_dec_info *sfd_info,\n+\t\t\t\t unsigned int func_idx)\n+{\n+ BFD_ASSERT (func_idx < sfd_info->sfd_fde_count);\n+ unsigned int func_r_offset\n+ = sfd_info->sfd_func_bfdinfo[func_idx].func_r_offset;\n+ /* There must have been a reloc. */\n+ BFD_ASSERT (func_r_offset);\n+ return func_r_offset;\n+}\n+\n+/* Bookkeep the function relocation offset in the decoder info. */\n+\n+static void\n+sframe_decoder_set_func_r_offset (struct sframe_dec_info *sfd_info,\n+\t\t\t\t unsigned int func_idx,\n+\t\t\t\t unsigned int r_offset)\n+{\n+ if (func_idx < sfd_info->sfd_fde_count)\n+ sfd_info->sfd_func_bfdinfo[func_idx].func_r_offset = r_offset;\n+}\n+\n+/* Get the relocation index in the elf_reloc_cookie for the function. */\n+\n+static unsigned int\n+sframe_decoder_get_func_reloc_index (struct sframe_dec_info *sfd_info,\n+\t\t\t\t unsigned int func_idx)\n+{\n+ BFD_ASSERT (func_idx < sfd_info->sfd_fde_count);\n+ return sfd_info->sfd_func_bfdinfo[func_idx].func_reloc_index;\n+}\n+\n+/* Bookkeep the relocation index in the elf_reloc_cookie for the function. */\n+\n+static void\n+sframe_decoder_set_func_reloc_index (struct sframe_dec_info *sfd_info,\n+\t\t\t\t unsigned int func_idx,\n+\t\t\t\t unsigned int reloc_index)\n+{\n+ if (func_idx < sfd_info->sfd_fde_count)\n+ sfd_info->sfd_func_bfdinfo[func_idx].func_reloc_index = reloc_index;\n+}\n+\n+/* Initialize the set of additional information in CFD_INFO,\n+ needed for linking SEC. Returns TRUE if setup is done successfully. */\n+\n+static bool\n+sframe_decoder_init_func_bfdinfo (asection *sec,\n+\t\t\t\t struct sframe_dec_info *sfd_info,\n+\t\t\t\t struct elf_reloc_cookie *cookie)\n+{\n+ unsigned int fde_count;\n+ unsigned int func_bfdinfo_size, i;\n+\n+ fde_count = sframe_decoder_get_num_fidx (sfd_info->sfd_ctx);\n+ sfd_info->sfd_fde_count = fde_count;\n+\n+ /* Allocate and clear the memory. */\n+ func_bfdinfo_size = (sizeof (struct sframe_func_bfdinfo)) * fde_count;\n+ sfd_info->sfd_func_bfdinfo\n+ = (struct sframe_func_bfdinfo*) bfd_malloc (func_bfdinfo_size);\n+ if (sfd_info->sfd_func_bfdinfo == NULL)\n+ return false;\n+ memset (sfd_info->sfd_func_bfdinfo, 0, func_bfdinfo_size);\n+\n+ /* For linker generated .sframe sections, we have no relocs. Skip. */\n+ if ((sec->flags & SEC_LINKER_CREATED) && cookie->rels == NULL)\n+ return true;\n+\n+ for (i = 0; i < fde_count; i++)\n+ {\n+ cookie->rel = cookie->rels + i;\n+ BFD_ASSERT (cookie->rel < cookie->relend);\n+ /* Bookkeep the relocation offset and relocation index of each function\n+\t for later use. */\n+ sframe_decoder_set_func_r_offset (sfd_info, i, cookie->rel->r_offset);\n+ sframe_decoder_set_func_reloc_index (sfd_info, i,\n+\t\t\t\t\t (cookie->rel - cookie->rels));\n+\n+ cookie->rel++;\n+ }\n+ BFD_ASSERT (cookie->rel == cookie->relend);\n+\n+ return true;\n+}\n+\n+/* Read the value from CONTENTS at the specified OFFSET for the given ABFD. */\n+\n+static bfd_vma\n+sframe_read_value (bfd *abfd, bfd_byte *contents, unsigned int offset,\n+\t\t unsigned int width)\n+{\n+ BFD_ASSERT (contents && offset);\n+ /* Supporting the usecase of reading only the 4-byte relocated\n+ value (signed offset for func start addr) for now. */\n+ BFD_ASSERT (width == 4);\n+ /* FIXME endianness ?? */\n+ unsigned char *buf = contents + offset;\n+ bfd_vma value = bfd_get_signed_32 (abfd, buf);\n+ return value;\n+}\n+\n+/* Return true if there is at least one non-empty .sframe section in\n+ input files. Can only be called after ld has mapped input to\n+ output sections, and before sections are stripped. */\n+\n+bool\n+_bfd_elf_sframe_present (struct bfd_link_info *info)\n+{\n+ asection *sframe = bfd_get_section_by_name (info->output_bfd, \".sframe\");\n+\n+ if (sframe == NULL)\n+ return false;\n+\n+ /* Count only sections which have at least a single FDE. */\n+ for (sframe = sframe->map_head.s; sframe != NULL; sframe = sframe->map_head.s)\n+ /* Note that this may become an approximate check in the future when\n+ some ABI/arch begin to use the sfh_auxhdr_len. When sfh_auxhdr_len has\n+ non-zero value, it will need to be accounted for in the calculation of\n+ the SFrame header size. */\n+ if (sframe->size > sizeof (sframe_header))\n+ return true;\n+ return false;\n+}\n+\n+/* Try to parse .sframe section SEC, which belongs to ABFD. Store the\n+ information in the section's sec_info field on success. COOKIE\n+ describes the relocations in SEC.\n+\n+ Returns TRUE if success, FALSE if any error or failure. */\n+\n+bool\n+_bfd_elf_parse_sframe (bfd *abfd,\n+\t\t struct bfd_link_info *info ATTRIBUTE_UNUSED,\n+\t\t asection *sec, struct elf_reloc_cookie *cookie)\n+{\n+ bfd_byte *sfbuf = NULL;\n+ struct sframe_dec_info *sfd_info;\n+ sframe_decoder_ctx *sfd_ctx;\n+ bfd_size_type sf_size;\n+ int decerr = 0;\n+\n+ if (sec->size == 0\n+ || sec->sec_info_type != SEC_INFO_TYPE_NONE)\n+ {\n+ /* This file does not contain .sframe information. */\n+ return false;\n+ }\n+\n+ if (bfd_is_abs_section (sec->output_section))\n+ {\n+ /* At least one of the sections is being discarded from the\n+\t link, so we should just ignore them. */\n+ return false;\n+ }\n+\n+ /* Read the SFrame unwind information from abfd. */\n+ if (!bfd_malloc_and_get_section (abfd, sec, &sfbuf))\n+ goto fail_no_free;\n+\n+ /* Decode the buffer and keep decoded contents for later use.\n+ Relocations are performed later, but are such that the section's\n+ size is unaffected. */\n+ sfd_info = bfd_malloc (sizeof (struct sframe_dec_info));\n+ sf_size = sec->size;\n+\n+ sfd_info->sfd_ctx = sframe_decode ((const char*)sfbuf, sf_size, &decerr);\n+ sfd_ctx = sfd_info->sfd_ctx;\n+ if (!sfd_ctx)\n+ /* Free'ing up any memory held by decoder context is done by\n+ sframe_decode in case of error. */\n+ goto fail_no_free;\n+\n+ if (!sframe_decoder_init_func_bfdinfo (sec, sfd_info, cookie))\n+ {\n+ sframe_decoder_free (&sfd_ctx);\n+ goto fail_no_free;\n+ }\n+\n+ elf_section_data (sec)->sec_info = sfd_info;\n+ sec->sec_info_type = SEC_INFO_TYPE_SFRAME;\n+\n+ goto success;\n+\n+fail_no_free:\n+ _bfd_error_handler\n+ (_(\"error in %pB(%pA); no .sframe will be created\"),\n+ abfd, sec);\n+ return false;\n+success:\n+ free (sfbuf);\n+ return true;\n+}\n+\n+/* This function is called for each input file before the .sframe section\n+ is relocated. It marks the SFrame FDE for the discarded functions for\n+ deletion.\n+\n+ The function returns TRUE iff any entries have been deleted. */\n+\n+bool\n+_bfd_elf_discard_section_sframe\n+ (asection *sec,\n+ bool (*reloc_symbol_deleted_p) (bfd_vma, void *),\n+ struct elf_reloc_cookie *cookie)\n+{\n+ bool changed;\n+ bool keep;\n+ unsigned int i;\n+ unsigned int func_desc_offset;\n+ unsigned int num_fidx;\n+ struct sframe_dec_info *sfd_info;\n+\n+ changed = false;\n+ /* FIXME - if relocatable link and changed = true, how does the final\n+ .rela.sframe get updated ?. */\n+ keep = false;\n+\n+ sfd_info = (struct sframe_dec_info *) elf_section_data (sec)->sec_info;\n+\n+ /* Skip checking for the linker created .sframe sections\n+ (for PLT sections). */\n+ if ((sec->flags & SEC_LINKER_CREATED) == 0 || cookie->rels != NULL)\n+ {\n+ num_fidx = sframe_decoder_get_num_fidx (sfd_info->sfd_ctx);\n+ for (i = 0; i < num_fidx; i++)\n+\t{\n+\t func_desc_offset = sframe_decoder_get_func_r_offset (sfd_info, i);\n+\n+\t cookie->rel = cookie->rels\n+\t + sframe_decoder_get_func_reloc_index (sfd_info, i);\n+\t keep = !(*reloc_symbol_deleted_p) (func_desc_offset, cookie);\n+\n+\t if (!keep)\n+\t {\n+\t sframe_decoder_mark_func_deleted (sfd_info, i);\n+\t changed = true;\n+\t }\n+\t}\n+ }\n+ return changed;\n+}\n+\n+/* Update the reference to the output .sframe section in the output ELF\n+ BFD ABFD. Returns true if no error. */\n+\n+bool\n+_bfd_elf_set_section_sframe (bfd *abfd,\n+\t\t\t\tstruct bfd_link_info *info)\n+{\n+ asection *cfsec;\n+\n+ cfsec = bfd_get_section_by_name (info->output_bfd, \".sframe\");\n+ if (!cfsec)\n+ return false;\n+\n+ elf_sframe (abfd) = cfsec;\n+\n+ return true;\n+}\n+\n+/* Merge .sframe section SEC. This is called with the relocated\n+ CONTENTS. */\n+\n+bool\n+_bfd_elf_merge_section_sframe (bfd *abfd,\n+\t\t\t struct bfd_link_info *info,\n+\t\t\t asection *sec,\n+\t\t\t bfd_byte *contents)\n+{\n+ struct sframe_dec_info *sfd_info;\n+ struct sframe_enc_info *sfe_info;\n+ sframe_decoder_ctx *sfd_ctx;\n+ sframe_encoder_ctx *sfe_ctx;\n+ unsigned char sfd_ctx_abi_arch;\n+ int8_t sfd_ctx_fixed_fp_offset;\n+ int8_t sfd_ctx_fixed_ra_offset;\n+ int encerr = 0;\n+\n+ struct elf_link_hash_table *htab;\n+ asection *cfsec;\n+\n+ /* Sanity check - handle SFrame sections only. */\n+ if (sec->sec_info_type != SEC_INFO_TYPE_SFRAME)\n+ return false;\n+\n+ sfd_info = (struct sframe_dec_info *) elf_section_data (sec)->sec_info;\n+ sfd_ctx = sfd_info->sfd_ctx;\n+\n+ htab = elf_hash_table (info);\n+ sfe_info = &(htab->sfe_info);\n+ sfe_ctx = sfe_info->sfe_ctx;\n+\n+ /* All input bfds are expected to have a valid SFrame section. Even if\n+ the SFrame section is empty with only a header, there must be a valid\n+ SFrame decoder context by now. The SFrame encoder context, however,\n+ will get set later here, if this is the first call to the function. */\n+ if (sfd_ctx == NULL || sfe_info == NULL)\n+ return false;\n+\n+ if (htab->sfe_info.sfe_ctx == NULL)\n+ {\n+ sfd_ctx_abi_arch = sframe_decoder_get_abi_arch (sfd_ctx);\n+ sfd_ctx_fixed_fp_offset = sframe_decoder_get_fixed_fp_offset (sfd_ctx);\n+ sfd_ctx_fixed_ra_offset = sframe_decoder_get_fixed_ra_offset (sfd_ctx);\n+\n+ /* Valid values are non-zero. */\n+ if (!sfd_ctx_abi_arch)\n+\treturn false;\n+\n+ htab->sfe_info.sfe_ctx = sframe_encode (SFRAME_VERSION_1,\n+\t\t\t\t\t 0, /* SFrame flags. */\n+\t\t\t\t\t sfd_ctx_abi_arch,\n+\t\t\t\t\t sfd_ctx_fixed_fp_offset,\n+\t\t\t\t\t sfd_ctx_fixed_ra_offset,\n+\t\t\t\t\t &encerr);\n+ /* Handle errors from sframe_encode. */\n+ if (htab->sfe_info.sfe_ctx == NULL)\n+\treturn false;\n+ }\n+ sfe_ctx = sfe_info->sfe_ctx;\n+\n+ if (sfe_info->sframe_section == NULL)\n+ {\n+ /* Make sure things are set for an eventual write.\n+\t Size of the output section is not known until\n+\t _bfd_elf_write_section_sframe is ready with the buffer\n+\t to write out. */\n+ cfsec = bfd_get_section_by_name (info->output_bfd, \".sframe\");\n+ if (cfsec)\n+\t{\n+\t sfe_info->sframe_section = cfsec;\n+\t // elf_sframe (abfd) = cfsec;\n+\t}\n+ else\n+\treturn false;\n+ }\n+\n+ /* Check that all .sframe sections being linked have the same\n+ ABI/arch. */\n+ if (sframe_decoder_get_abi_arch (sfd_ctx)\n+ != sframe_encoder_get_abi_arch (sfe_ctx))\n+ {\n+ _bfd_error_handler\n+\t(_(\"input SFrame sections with different abi prevent .sframe\"\n+\t \" generation\"));\n+ return false;\n+ }\n+\n+ /* Iterate over the function descriptor entries and the FREs of the\n+ function from the decoder context. Add each of them to the encoder\n+ context, if suitable. */\n+ unsigned int i = 0, j = 0, cur_fidx = 0;\n+\n+ unsigned int num_fidx = sframe_decoder_get_num_fidx (sfd_ctx);\n+ unsigned int num_enc_fidx = sframe_encoder_get_num_fidx (sfe_ctx);\n+\n+ for (i = 0; i < num_fidx; i++)\n+ {\n+ unsigned int num_fres = 0;\n+ int32_t func_start_address;\n+ bfd_vma address;\n+ uint32_t func_size = 0;\n+ unsigned char func_info = 0;\n+ unsigned int r_offset = 0;\n+ bool pltn_reloc_by_hand = false;\n+ unsigned int pltn_r_offset = 0;\n+\n+ if (!sframe_decoder_get_funcdesc (sfd_ctx, i, &num_fres, &func_size,\n+\t\t\t\t\t&func_start_address, &func_info))\n+\t{\n+\t /* If function belongs to a deleted section, skip editing the\n+\t function descriptor entry. */\n+\t if (sframe_decoder_func_deleted_p(sfd_info, i))\n+\t continue;\n+\n+\t /* Don't edit function descriptor entries for relocatable link. */\n+\t if (!bfd_link_relocatable (info))\n+\t {\n+\t if (!(sec->flags & SEC_LINKER_CREATED))\n+\t\t{\n+\t\t /* Get relocated contents by reading the value of the\n+\t\t relocated function start address at the beginning of the\n+\t\t function descriptor entry. */\n+\t\t r_offset = sframe_decoder_get_func_r_offset (sfd_info, i);\n+\t\t}\n+\t else\n+\t\t{\n+\t\t /* Expected to land here for SFrame unwind info as created\n+\t\t for the .plt* sections. These sections can have upto two\n+\t\t FDE entries. Although the code should work for > 2,\n+\t\t leaving this assert here for safety. */\n+\t\t BFD_ASSERT (num_fidx <= 2);\n+\t\t /* For the first entry, we know the offset of the SFrame FDE's\n+\t\t sfde_func_start_address. Side note: see how the value\n+\t\t of PLT_SFRAME_FDE_START_OFFSET is also set to the\n+\t\t same. */\n+\t\t r_offset = sframe_decoder_get_hdr_size (sfd_ctx);\n+\t\t /* For any further SFrame FDEs, the generator has already put\n+\t\t in an offset in place of sfde_func_start_address of the\n+\t\t corresponding FDE. We will use it by hand to relocate. */\n+\t\t if (i > 0)\n+\t\t {\n+\t\t pltn_r_offset\n+\t\t\t= r_offset + (i * sizeof (sframe_func_desc_entry));\n+\t\t pltn_reloc_by_hand = true;\n+\t\t }\n+\t\t}\n+\n+\t /* Get the SFrame FDE function start address after relocation. */\n+\t address = sframe_read_value (abfd, contents, r_offset, 4);\n+\t if (pltn_reloc_by_hand)\n+\t\taddress += sframe_read_value (abfd, contents,\n+\t\t\t\t\t pltn_r_offset, 4);\n+\t address += (sec->output_offset + r_offset);\n+\n+\t /* FIXME For testing only. Cleanup later. */\n+\t // address += (sec->output_section->vma);\n+\n+\t func_start_address = address;\n+\t }\n+\n+\t /* Update the encoder context with updated content. */\n+\t int err = sframe_encoder_add_funcdesc (sfe_ctx, func_start_address,\n+\t\t\t\t\t\t func_size, func_info,\n+\t\t\t\t\t\t num_fres);\n+\t cur_fidx++;\n+\t BFD_ASSERT (!err);\n+\t}\n+\n+ for (j = 0; j < num_fres; j++)\n+\t{\n+\t sframe_frame_row_entry fre;\n+\t if (!sframe_decoder_get_fre (sfd_ctx, i, j, &fre))\n+\t {\n+\t int err = sframe_encoder_add_fre (sfe_ctx,\n+\t\t\t\t\t\tcur_fidx-1+num_enc_fidx,\n+\t\t\t\t\t\t&fre);\n+\t BFD_ASSERT (!err);\n+\t }\n+\t}\n+ }\n+ /* Free the SFrame decoder context. */\n+ sframe_decoder_free (&sfd_ctx);\n+\n+ return true;\n+}\n+\n+/* Write out the .sframe section. This must be called after\n+ _bfd_elf_merge_section_sframe has been called on all input\n+ .sframe sections. */\n+\n+bool\n+_bfd_elf_write_section_sframe (bfd *abfd, struct bfd_link_info *info)\n+{\n+ bool retval = true;\n+\n+ struct elf_link_hash_table *htab;\n+ struct sframe_enc_info *sfe_info;\n+ sframe_encoder_ctx *sfe_ctx;\n+ asection *sec;\n+ void *contents;\n+ size_t sec_size;\n+ int err = 0;\n+\n+ htab = elf_hash_table (info);\n+ sfe_info = &htab->sfe_info;\n+ sec = sfe_info->sframe_section;\n+ sfe_ctx = sfe_info->sfe_ctx;\n+\n+ if (sec == NULL)\n+ return true;\n+\n+ contents = sframe_encoder_write (sfe_ctx, &sec_size, &err);\n+ sec->size = (bfd_size_type) sec_size;\n+\n+ if (!bfd_set_section_contents (abfd, sec->output_section, contents,\n+\t\t\t\t (file_ptr) sec->output_offset,\n+\t\t\t\t sec->size))\n+ retval = false;\n+ else if (!bfd_link_relocatable (info))\n+ {\n+ Elf_Internal_Shdr *hdr = &elf_section_data (sec)->this_hdr;\n+ hdr->sh_size = sec->size;\n+ }\n+ /* For relocatable links, do not update the section size as the section\n+ contents have not been relocated. */\n+\n+ sframe_encoder_free (&sfe_ctx);\n+\n+ return retval;\n+}\ndiff --git a/bfd/elf.c b/bfd/elf.c\nindex 81825b748d7..87ec1623313 100644\n--- a/bfd/elf.c\n+++ b/bfd/elf.c\n@@ -1673,6 +1673,7 @@ get_segment_type (unsigned int p_type)\n case PT_GNU_EH_FRAME: pt = \"EH_FRAME\"; break;\n case PT_GNU_STACK: pt = \"STACK\"; break;\n case PT_GNU_RELRO: pt = \"RELRO\"; break;\n+ case PT_GNU_SFRAME: pt = \"SFRAME\"; break;\n default: pt = NULL; break;\n }\n return pt;\n@@ -3081,6 +3082,10 @@ bfd_section_from_phdr (bfd *abfd, Elf_Internal_Phdr *hdr, int hdr_index)\n case PT_GNU_RELRO:\n return _bfd_elf_make_section_from_phdr (abfd, hdr, hdr_index, \"relro\");\n \n+ case PT_GNU_SFRAME:\n+ return _bfd_elf_make_section_from_phdr (abfd, hdr, hdr_index,\n+\t\t\t\t\t \"sframe\");\n+\n default:\n /* Check for any processor-specific program segment types. */\n bed = get_elf_backend_data (abfd);\n@@ -4450,6 +4455,12 @@ get_program_header_size (bfd *abfd, struct bfd_link_info *info)\n ++segs;\n }\n \n+ if (elf_sframe (abfd))\n+ {\n+ /* We need a PT_GNU_SFRAME segment. */\n+ ++segs;\n+ }\n+\n s = bfd_get_section_by_name (abfd,\n \t\t\t NOTE_GNU_PROPERTY_SECTION_NAME);\n if (s != NULL && s->size != 0)\n@@ -4715,6 +4726,7 @@ _bfd_elf_map_sections_to_segments (bfd *abfd,\n asection *first_tls = NULL;\n asection *first_mbind = NULL;\n asection *dynsec, *eh_frame_hdr;\n+ asection *sframe;\n size_t amt;\n bfd_vma addr_mask, wrap_to = 0; /* Bytes. */\n bfd_size_type phdr_size; /* Octets/bytes. */\n@@ -5210,6 +5222,26 @@ _bfd_elf_map_sections_to_segments (bfd *abfd,\n \t pm = &m->next;\n \t}\n \n+ /* If there is a .sframe section, throw in a PT_GNU_SFRAME\n+\t segment. */\n+ sframe = elf_sframe (abfd);\n+ if (sframe != NULL\n+\t && (sframe->output_section->flags & SEC_LOAD) != 0\n+\t && sframe->size != 0)\n+\t{\n+\t amt = sizeof (struct elf_segment_map);\n+\t m = (struct elf_segment_map *) bfd_zalloc (abfd, amt);\n+\t if (m == NULL)\n+\t goto error_return;\n+\t m->next = NULL;\n+\t m->p_type = PT_GNU_SFRAME;\n+\t m->count = 1;\n+\t m->sections[0] = sframe->output_section;\n+\n+\t *pm = m;\n+\t pm = &m->next;\n+\t}\n+\n if (elf_stack_flags (abfd))\n \t{\n \t amt = sizeof (struct elf_segment_map);\ndiff --git a/bfd/elf64-x86-64.c b/bfd/elf64-x86-64.c\nindex 2ae8dffba0f..fb872793d5f 100644\n--- a/bfd/elf64-x86-64.c\n+++ b/bfd/elf64-x86-64.c\n@@ -22,6 +22,7 @@\n #include \"elfxx-x86.h\"\n #include \"dwarf2.h\"\n #include \"libiberty.h\"\n+#include \"sframe.h\"\n \n #include \"opcode/i386.h\"\n \n@@ -818,6 +819,87 @@ static const bfd_byte elf_x86_64_eh_frame_non_lazy_plt[] =\n DW_CFA_nop, DW_CFA_nop, DW_CFA_nop\n };\n \n+static const sframe_frame_row_entry elf_x86_64_sframe_null_fre =\n+{\n+ 0,\n+ SFRAME_V1_FRE_INFO (SFRAME_BASE_REG_SP, 1, SFRAME_FRE_OFFSET_1B), /* FRE info. */\n+ {16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} /* 12 bytes. */\n+};\n+\n+/* .sframe FRE covering the .plt section entry. */\n+static const sframe_frame_row_entry elf_x86_64_sframe_plt0_fre1 =\n+{\n+ 0, /* SFrame FRE start address. */\n+ SFRAME_V1_FRE_INFO (SFRAME_BASE_REG_SP, 1, SFRAME_FRE_OFFSET_1B), /* FRE info. */\n+ {16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} /* 12 bytes. */\n+};\n+\n+/* .sframe FRE covering the .plt section entry. */\n+static const sframe_frame_row_entry elf_x86_64_sframe_plt0_fre2 =\n+{\n+ 6, /* SFrame FRE start address. */\n+ SFRAME_V1_FRE_INFO (SFRAME_BASE_REG_SP, 1, SFRAME_FRE_OFFSET_1B), /* FRE info. */\n+ {24, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} /* 12 bytes. */\n+};\n+\n+/* .sframe FRE covering the .plt section entry. */\n+static const sframe_frame_row_entry elf_x86_64_sframe_pltn_fre1 =\n+{\n+ 0, /* SFrame FRE start address. */\n+ SFRAME_V1_FRE_INFO (SFRAME_BASE_REG_SP, 1, SFRAME_FRE_OFFSET_1B), /* FRE info. */\n+ {8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} /* 12 bytes. */\n+};\n+\n+/* .sframe FRE covering the .plt section entry. */\n+static const sframe_frame_row_entry elf_x86_64_sframe_pltn_fre2 =\n+{\n+ 11, /* SFrame FRE start address. */\n+ SFRAME_V1_FRE_INFO (SFRAME_BASE_REG_SP, 1, SFRAME_FRE_OFFSET_1B), /* FRE info. */\n+ {16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} /* 12 bytes. */\n+};\n+\n+/* .sframe FRE covering the second .plt section entry. */\n+static const sframe_frame_row_entry elf_x86_64_sframe_sec_pltn_fre1 =\n+{\n+ 0, /* SFrame FRE start address. */\n+ SFRAME_V1_FRE_INFO (SFRAME_BASE_REG_SP, 1, SFRAME_FRE_OFFSET_1B), /* FRE info. */\n+ {8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} /* 12 bytes. */\n+};\n+\n+/* SFrame helper object for non-lazy PLT. Also used for IBT enabled PLT. */\n+static const struct elf_x86_sframe_plt elf_x86_64_sframe_non_lazy_plt =\n+{\n+ LAZY_PLT_ENTRY_SIZE,\n+ 2, /* Number of FREs for PLT0. */\n+ /* Array of SFrame FREs for plt0. */\n+ { &elf_x86_64_sframe_plt0_fre1, &elf_x86_64_sframe_plt0_fre2 },\n+ LAZY_PLT_ENTRY_SIZE,\n+ 1, /* Number of FREs for PLTn. */\n+ /* Array of SFrame FREs for plt. */\n+ { &elf_x86_64_sframe_sec_pltn_fre1, &elf_x86_64_sframe_null_fre },\n+ 0,\n+ 0, /* There is no second PLT necessary. */\n+ { &elf_x86_64_sframe_null_fre }\n+};\n+\n+/* SFrame helper object for lazy PLT. Also used for IBT enabled PLT. */\n+static const struct elf_x86_sframe_plt elf_x86_64_sframe_plt =\n+{\n+ LAZY_PLT_ENTRY_SIZE,\n+ 2, /* Number of FREs for PLT0. */\n+ /* Array of SFrame FREs for plt0. */\n+ { &elf_x86_64_sframe_plt0_fre1, &elf_x86_64_sframe_plt0_fre2 },\n+ LAZY_PLT_ENTRY_SIZE,\n+ 2, /* Number of FREs for PLTn. */\n+ /* Array of SFrame FREs for plt. */\n+ { &elf_x86_64_sframe_pltn_fre1, &elf_x86_64_sframe_pltn_fre2 },\n+ NON_LAZY_PLT_ENTRY_SIZE,\n+ 1, /* Number of FREs for PLTn for second PLT. */\n+ /* FREs for second plt ( unwind info for .plt.got is\n+ identical). Used when IBT or non-lazy PLT is in effect. */\n+ { &elf_x86_64_sframe_sec_pltn_fre1 }\n+};\n+\n /* These are the standard parameters. */\n static const struct elf_x86_lazy_plt_layout elf_x86_64_lazy_plt =\n {\n@@ -971,7 +1053,6 @@ static const struct elf_x86_non_lazy_plt_layout elf_x32_non_lazy_ibt_plt =\n sizeof (elf_x86_64_eh_frame_non_lazy_plt) /* eh_frame_plt_size */\n };\n \n-\n static bool\n elf64_x86_64_elf_object_p (bfd *abfd)\n {\n@@ -5228,6 +5309,20 @@ elf_x86_64_link_setup_gnu_properties (struct bfd_link_info *info)\n init_table.non_lazy_ibt_plt = &elf_x32_non_lazy_ibt_plt;\n }\n \n+ if (ABI_64_P (info->output_bfd))\n+ {\n+ init_table.sframe_lazy_plt = &elf_x86_64_sframe_plt;\n+ init_table.sframe_non_lazy_plt = &elf_x86_64_sframe_non_lazy_plt;\n+ init_table.sframe_lazy_ibt_plt = &elf_x86_64_sframe_plt;\n+ init_table.sframe_non_lazy_ibt_plt = &elf_x86_64_sframe_non_lazy_plt;\n+ }\n+ else\n+ {\n+ /* SFrame is not supported for non AMD64. */\n+ init_table.sframe_lazy_plt = NULL;\n+ init_table.sframe_non_lazy_plt = NULL;\n+ }\n+\n if (ABI_64_P (info->output_bfd))\n {\n init_table.r_info = elf64_r_info;\ndiff --git a/bfd/elflink.c b/bfd/elflink.c\nindex 019ac302905..dcbcc2f03b6 100644\n--- a/bfd/elflink.c\n+++ b/bfd/elflink.c\n@@ -10899,6 +10899,7 @@ elf_section_ignore_discarded_relocs (asection *sec)\n case SEC_INFO_TYPE_STABS:\n case SEC_INFO_TYPE_EH_FRAME:\n case SEC_INFO_TYPE_EH_FRAME_ENTRY:\n+ case SEC_INFO_TYPE_SFRAME:\n return true;\n default:\n break;\n@@ -10937,6 +10938,9 @@ _bfd_elf_default_action_discarded (asection *sec)\n && strncmp (sec->name, \".eh_frame.\", 10) == 0)\n return 0;\n \n+ if (strcmp (\".sframe\", sec->name) == 0)\n+ return 0;\n+\n if (strcmp (\".gcc_except_table\", sec->name) == 0)\n return 0;\n \n@@ -11870,6 +11874,16 @@ elf_link_input_bfd (struct elf_final_link_info *flinfo, bfd *input_bfd)\n \t return false;\n \t }\n \t break;\n+\tcase SEC_INFO_TYPE_SFRAME:\n+\t {\n+\t /* Merge .sframe sections into the ctf frame encoder\n+\t\t context of the output_bfd's section. The final .sframe\n+\t\t output section will be written out later. */\n+\t if (!_bfd_elf_merge_section_sframe (output_bfd, flinfo->info,\n+\t\t\t\t\t\t o, contents))\n+\t\treturn false;\n+\t }\n+\t break;\n \tdefault:\n \t {\n \t if (! (o->flags & SEC_EXCLUDE))\n@@ -13453,6 +13467,9 @@ bfd_elf_final_link (bfd *abfd, struct bfd_link_info *info)\n if (! _bfd_elf_write_section_eh_frame_hdr (abfd, info))\n goto error_return;\n \n+ if (! _bfd_elf_write_section_sframe (abfd, info))\n+ goto error_return;\n+\n if (info->callbacks->emit_ctf)\n info->callbacks->emit_ctf ();\n \n@@ -14908,6 +14925,41 @@ bfd_elf_discard_info (bfd *output_bfd, struct bfd_link_info *info)\n \t\t\t\t_bfd_elf_adjust_eh_frame_global_symbol, NULL);\n }\n \n+ o = bfd_get_section_by_name (output_bfd, \".sframe\");\n+ if (o != NULL)\n+ {\n+ asection *i;\n+\n+ for (i = o->map_head.s; i != NULL; i = i->map_head.s)\n+\t{\n+\t if (i->size == 0)\n+\t continue;\n+\n+\t abfd = i->owner;\n+\t if (bfd_get_flavour (abfd) != bfd_target_elf_flavour)\n+\t continue;\n+\n+\t if (!init_reloc_cookie_for_section (&cookie, info, i))\n+\t return -1;\n+\n+\t if (_bfd_elf_parse_sframe (abfd, info, i, &cookie))\n+\t {\n+\t if (_bfd_elf_discard_section_sframe (i,\n+\t\t\t\t\t\t bfd_elf_reloc_symbol_deleted_p,\n+\t\t\t\t\t\t &cookie))\n+\t\t{\n+\t\t if (i->size != i->rawsize)\n+\t\t changed = 1;\n+\t\t}\n+\t }\n+\t fini_reloc_cookie_for_section (&cookie, i);\n+\t}\n+ /* Update the reference to the output .sframe section. Used to\n+\t determine later if PT_GNU_SFRAME segment is to be generated. */\n+ if (!_bfd_elf_set_section_sframe (output_bfd, info))\n+\treturn -1;\n+ }\n+\n for (abfd = info->input_bfds; abfd != NULL; abfd = abfd->link.next)\n {\n const struct elf_backend_data *bed;\ndiff --git a/bfd/elfxx-x86.c b/bfd/elfxx-x86.c\nindex 7fb972752b3..c48d0385485 100644\n--- a/bfd/elfxx-x86.c\n+++ b/bfd/elfxx-x86.c\n@@ -1777,6 +1777,191 @@ elf_x86_relative_reloc_compare (const void *pa, const void *pb)\n return 0;\n }\n \n+enum dynobj_sframe_plt_type\n+{\n+ SFRAME_PLT = 1,\n+ SFRAME_PLT_SEC = 2\n+};\n+\n+/* Create SFrame unwind info for the plt entries in the .plt section\n+ of type PLT_SEC_TYPE. */\n+\n+static bool\n+_bfd_x86_elf_create_sframe_plt (bfd *output_bfd,\n+\t\t\t\tstruct bfd_link_info *info,\n+\t\t\t\tunsigned int plt_sec_type)\n+{\n+ struct elf_x86_link_hash_table *htab;\n+ const struct elf_backend_data *bed;\n+\n+ bool plt0_generated_p;\n+ unsigned int plt0_entry_size;\n+ unsigned char func_info;\n+ unsigned int fre_type;\n+ /* The dynamic plt section for which .sframe unwind information is being\n+ created. */\n+ asection *dpltsec;\n+\n+ int err = 0;\n+\n+ sframe_encoder_ctx **ectx = NULL;\n+ unsigned plt_entry_size = 0;\n+ unsigned int num_pltn_fres = 0;\n+ unsigned int num_pltn_entries = 0;\n+\n+ bed = get_elf_backend_data (output_bfd);\n+ htab = elf_x86_hash_table (info, bed->target_id);\n+ /* Whether SFrame unwind info for plt0 is to be generated. */\n+ plt0_generated_p = htab->plt.has_plt0;\n+ plt0_entry_size\n+ = (plt0_generated_p) ? htab->sframe_plt->plt0_entry_size : 0;\n+\n+ switch (plt_sec_type)\n+ {\n+ case SFRAME_PLT:\n+\t{\n+\t ectx = &htab->plt_cfe_ctx;\n+\t dpltsec = htab->elf.splt;\n+\n+\t plt_entry_size = htab->plt.plt_entry_size;\n+\t num_pltn_fres = htab->sframe_plt->pltn_num_fres;\n+\t num_pltn_entries\n+\t = (htab->elf.splt->size - plt0_entry_size) / plt_entry_size;\n+\n+\t break;\n+\t}\n+ case SFRAME_PLT_SEC:\n+\t{\n+\t ectx = &htab->plt_second_cfe_ctx;\n+\t /* FIXME - this or htab->plt_second_sframe ? */\n+\t dpltsec = htab->plt_second_eh_frame;\n+\n+\t plt_entry_size = htab->sframe_plt->sec_pltn_entry_size;\n+\t num_pltn_fres = htab->sframe_plt->sec_pltn_num_fres;\n+\t num_pltn_entries\n+\t\t= htab->plt_second_eh_frame->size / plt_entry_size;\n+\t break;\n+\t}\n+ default:\n+ /* No other value is possible. */\n+ return false;\n+ break;\n+ }\n+\n+ *ectx = sframe_encode (SFRAME_VERSION_1,\n+\t\t\t 0,\n+\t\t\t SFRAME_ABI_AMD64_ENDIAN_LITTLE,\n+\t\t\t SFRAME_CFA_FIXED_FP_INVALID,\n+\t\t\t -8, /* Fixed RA offset. */\n+\t\t\t &err);\n+\n+ /* FRE type is dependent on the size of the function. */\n+ fre_type = sframe_calc_fre_type (dpltsec->size);\n+ func_info = sframe_fde_func_info (fre_type,\n+\t\t\t\t SFRAME_FDE_TYPE_PCINC);\n+\n+ /* Add SFrame FDE and the associated FREs for plt0 if plt0 has been\n+ generated. */\n+ if (plt0_generated_p)\n+ {\n+ /* Add SFrame FDE for plt0, the function start address is updated later\n+\t at _bfd_elf_merge_section_sframe time. */\n+ sframe_encoder_add_funcdesc (*ectx,\n+\t\t\t\t 0, /* func start addr. */\n+\t\t\t\t plt0_entry_size,\n+\t\t\t\t func_info,\n+\t\t\t\t 0 /* Num FREs. */);\n+ sframe_frame_row_entry plt0_fre;\n+ unsigned int num_plt0_fres = htab->sframe_plt->plt0_num_fres;\n+ for (unsigned int j = 0; j < num_plt0_fres; j++)\n+\t{\n+\t plt0_fre = *(htab->sframe_plt->plt0_fres[j]);\n+\t sframe_encoder_add_fre (*ectx, 0, &plt0_fre);\n+\t}\n+ }\n+\n+\n+ if (num_pltn_entries)\n+ {\n+ /* pltn entries use an SFrame FDE of type\n+\t SFRAME_FDE_TYPE_PCMASK to exploit the repetitive\n+\t pattern of the instructions in these entries. Using this SFrame FDE\n+\t type helps in keeping the unwind information for pltn entries\n+\t compact. */\n+ func_info\t= sframe_fde_func_info (fre_type, SFRAME_FDE_TYPE_PCMASK);\n+ /* Add the SFrame FDE for all PCs starting at the first pltn entry (hence,\n+\t function start address = plt0_entry_size. As usual, this will be\n+\t updated later at _bfd_elf_merge_section_sframe, by when the\n+\t sections are relocated. */\n+ sframe_encoder_add_funcdesc (*ectx,\n+\t\t\t\t plt0_entry_size, /* func start addr. */\n+\t\t\t\t dpltsec->size - plt0_entry_size,\n+\t\t\t\t func_info,\n+\t\t\t\t 0 /* Num FREs. */);\n+\n+ sframe_frame_row_entry pltn_fre;\n+ /* Now add the FREs for pltn. Simply adding the two FREs suffices due\n+\t to the usage of SFRAME_FDE_TYPE_PCMASK above. */\n+ for (unsigned int j = 0; j < num_pltn_fres; j++)\n+\t{\n+\t pltn_fre = *(htab->sframe_plt->pltn_fres[j]);\n+\t sframe_encoder_add_fre (*ectx, 1, &pltn_fre);\n+\t}\n+ }\n+\n+ return true;\n+}\n+\n+/* Put contents of the .sframe section corresponding to the specified\n+ PLT_SEC_TYPE. */\n+\n+static bool\n+_bfd_x86_elf_write_sframe_plt (bfd *output_bfd,\n+\t\t\t struct bfd_link_info *info,\n+\t\t\t unsigned int plt_sec_type)\n+{\n+ struct elf_x86_link_hash_table *htab;\n+ const struct elf_backend_data *bed;\n+ sframe_encoder_ctx *ectx;\n+ size_t sec_size;\n+ asection *sec;\n+ bfd *dynobj;\n+\n+ int err = 0;\n+\n+ bed = get_elf_backend_data (output_bfd);\n+ htab = elf_x86_hash_table (info, bed->target_id);\n+ dynobj = htab->elf.dynobj;\n+\n+ switch (plt_sec_type)\n+ {\n+ case SFRAME_PLT:\n+ ectx = htab->plt_cfe_ctx;\n+ sec = htab->plt_sframe;\n+ break;\n+ case SFRAME_PLT_SEC:\n+ ectx = htab->plt_second_cfe_ctx;\n+ sec = htab->plt_second_sframe;\n+ break;\n+ default:\n+ /* No other value is possible. */\n+ return false;\n+ break;\n+ }\n+\n+ BFD_ASSERT (ectx);\n+\n+ void *contents = sframe_encoder_write (ectx, &sec_size, &err);\n+\n+ sec->size = (bfd_size_type) sec_size;\n+ sec->contents = (unsigned char *) bfd_zalloc (dynobj, sec->size);\n+ memcpy (sec->contents, contents, sec_size);\n+\n+ sframe_encoder_free (&ectx);\n+\n+ return true;\n+}\n+\n bool\n _bfd_elf_x86_size_relative_relocs (struct bfd_link_info *info,\n \t\t\t\t bool *need_layout)\n@@ -2267,6 +2452,42 @@ _bfd_x86_elf_size_dynamic_sections (bfd *output_bfd,\n \t = htab->non_lazy_plt->eh_frame_plt_size;\n }\n \n+ /* No need to size the .sframe section explicitly because the write-out\n+ mechanism is different. Simply prep up the FDE/FRE for the\n+ .plt section. */\n+ if (_bfd_elf_sframe_present (info))\n+ {\n+ if (htab->plt_sframe != NULL\n+\t && htab->elf.splt != NULL\n+\t && htab->elf.splt->size != 0\n+\t && !bfd_is_abs_section (htab->elf.splt->output_section))\n+\t{\n+\t _bfd_x86_elf_create_sframe_plt (output_bfd, info, SFRAME_PLT);\n+\t /* FIXME - Dirty Hack. Set the size to something non-zero for now,\n+\t so that the section does not get stripped out below. The precise\n+\t size of this section is known only when the contents are\n+\t serialized in _bfd_x86_elf_write_sframe_plt. */\n+\t htab->plt_sframe->size = sizeof (sframe_header) + 1;\n+\t}\n+\n+ /* FIXME - generate for .got.plt ? */\n+\n+ /* Unwind info for the second PLT. */\n+ if (htab->plt_second_sframe != NULL\n+\t && htab->plt_second != NULL\n+\t && htab->plt_second->size != 0\n+\t && !bfd_is_abs_section (htab->plt_second->output_section))\n+\t{\n+\t _bfd_x86_elf_create_sframe_plt (output_bfd, info,\n+\t\t\t\t\t SFRAME_PLT_SEC);\n+\t /* FIXME - Dirty Hack. Set the size to something non-zero for now,\n+\t so that the section does not get stripped out below. The precise\n+\t size of this section is known only when the contents are\n+\t serialized in _bfd_x86_elf_write_sframe_plt. */\n+\t htab->plt_second_sframe->size = sizeof (sframe_header) + 1;\n+\t}\n+ }\n+\n /* We now have determined the sizes of the various dynamic sections.\n Allocate memory for them. */\n relocs = false;\n@@ -2302,6 +2523,8 @@ _bfd_x86_elf_size_dynamic_sections (bfd *output_bfd,\n \t || s == htab->plt_eh_frame\n \t || s == htab->plt_got_eh_frame\n \t || s == htab->plt_second_eh_frame\n+\t || s == htab->plt_sframe\n+\t || s == htab->plt_second_sframe\n \t || s == htab->elf.sdynbss\n \t || s == htab->elf.sdynrelro)\n \t{\n@@ -2344,6 +2567,11 @@ _bfd_x86_elf_size_dynamic_sections (bfd *output_bfd,\n if ((s->flags & SEC_HAS_CONTENTS) == 0)\n \tcontinue;\n \n+ /* Skip allocating contents for .sframe section as it is written\n+\t out differently. See below. */\n+ if ((s == htab->plt_sframe) || (s == htab->plt_second_sframe))\n+\tcontinue;\n+\n /* NB: Initially, the iplt section has minimal alignment to\n \t avoid moving dot of the following section backwards when\n \t it is empty. Update its section alignment now since it\n@@ -2393,6 +2621,21 @@ _bfd_x86_elf_size_dynamic_sections (bfd *output_bfd,\n \t\t + PLT_FDE_LEN_OFFSET));\n }\n \n+ if (_bfd_elf_sframe_present (info))\n+ {\n+ if (htab->plt_sframe != NULL\n+\t && htab->elf.splt != NULL\n+\t && htab->elf.splt->size != 0\n+\t && htab->plt_sframe->contents == NULL)\n+\t_bfd_x86_elf_write_sframe_plt (output_bfd, info, SFRAME_PLT);\n+\n+ if (htab->plt_second_sframe != NULL\n+\t && htab->elf.splt != NULL\n+\t && htab->elf.splt->size != 0\n+\t && htab->plt_second_sframe->contents == NULL)\n+\t_bfd_x86_elf_write_sframe_plt (output_bfd, info, SFRAME_PLT_SEC);\n+ }\n+\n return _bfd_elf_maybe_vxworks_add_dynamic_tags (output_bfd, info,\n \t\t\t\t\t\t relocs);\n }\n@@ -2607,6 +2850,74 @@ _bfd_x86_elf_finish_dynamic_sections (bfd *output_bfd,\n \t}\n }\n \n+ /* Make any adjustment if necessary and merge .sframe section to\n+ create the final .sframe section for output_bfd. */\n+ if (htab->plt_sframe != NULL\n+ && htab->plt_sframe->contents != NULL)\n+ {\n+ if (htab->elf.splt != NULL\n+\t && htab->elf.splt->size != 0\n+\t && (htab->elf.splt->flags & SEC_EXCLUDE) == 0\n+\t && htab->elf.splt->output_section != NULL\n+\t && htab->plt_sframe->output_section != NULL)\n+\t{\n+\t bfd_vma plt_start = htab->elf.splt->output_section->vma;\n+\t bfd_vma sframe_start = htab->plt_sframe->output_section->vma\n+\t\t\t\t + htab->plt_sframe->output_offset\n+\t\t\t\t + PLT_SFRAME_FDE_START_OFFSET;\n+#if 0 /* FIXME Testing only. Remove before review. */\n+\t bfd_vma test_value = (plt_start - sframe_start)\n+\t + htab->plt_sframe->output_section->vma\n+\t + htab->plt_sframe->output_offset\n+\t + PLT_SFRAME_FDE_START_OFFSET;\n+\t bfd_put_signed_32 (dynobj, test_value,\n+#endif\n+\t bfd_put_signed_32 (dynobj, plt_start - sframe_start,\n+\t\t\t htab->plt_sframe->contents\n+\t\t\t + PLT_SFRAME_FDE_START_OFFSET);\n+\t}\n+ if (htab->plt_sframe->sec_info_type == SEC_INFO_TYPE_SFRAME)\n+\t{\n+\t if (! _bfd_elf_merge_section_sframe (output_bfd, info,\n+\t\t\t\t\t htab->plt_sframe,\n+\t\t\t\t\t htab->plt_sframe->contents))\n+\t return NULL;\n+\t}\n+ }\n+\n+ if (htab->plt_second_sframe != NULL\n+ && htab->plt_second_sframe->contents != NULL)\n+ {\n+ if (htab->plt_second != NULL\n+\t && htab->plt_second->size != 0\n+\t && (htab->plt_second->flags & SEC_EXCLUDE) == 0\n+\t && htab->plt_second->output_section != NULL\n+\t && htab->plt_second_sframe->output_section != NULL)\n+\t{\n+\t bfd_vma plt_start = htab->plt_second->output_section->vma;\n+\t bfd_vma sframe_start\n+\t = (htab->plt_second_sframe->output_section->vma\n+\t + htab->plt_second_sframe->output_offset\n+\t + PLT_SFRAME_FDE_START_OFFSET);\n+#if 0 /* FIXME Testing only. Remove before review. */\n+\t bfd_vma test_value = (plt_start - sframe_start)\n+\t + htab->plt_second_sframe->output_section->vma\n+\t + htab->plt_second_sframe->output_offset\n+\t + PLT_SFRAME_FDE_START_OFFSET;\n+\t bfd_put_signed_32 (dynobj, test_value,\n+#endif\n+\t bfd_put_signed_32 (dynobj, plt_start - sframe_start,\n+\t\t\t htab->plt_second_sframe->contents\n+\t\t\t + PLT_SFRAME_FDE_START_OFFSET);\n+\t}\n+ if (htab->plt_second_sframe->sec_info_type == SEC_INFO_TYPE_SFRAME)\n+\t{\n+\t if (! _bfd_elf_merge_section_sframe (output_bfd, info,\n+\t\t\t\t\t htab->plt_second_sframe,\n+\t\t\t\t\t htab->plt_second_sframe->contents))\n+\t return NULL;\n+\t}\n+ }\n if (htab->elf.sgot && htab->elf.sgot->size > 0)\n elf_section_data (htab->elf.sgot->output_section)->this_hdr.sh_entsize\n = htab->got_entry_size;\n@@ -3949,12 +4260,36 @@ _bfd_x86_elf_link_setup_gnu_properties\n \n pltsec = htab->elf.splt;\n \n- /* If the non-lazy PLT is available, use it for all PLT entries if\n- there are no PLT0 or no .plt section. */\n if (htab->non_lazy_plt != NULL\n && (!htab->plt.has_plt0 || pltsec == NULL))\n+ lazy_plt = false;\n+ else\n+ lazy_plt = true;\n+\n+ if (normal_target)\n+ {\n+ if (use_ibt_plt)\n+\t{\n+\t if (lazy_plt)\n+\t htab->sframe_plt = init_table->sframe_lazy_ibt_plt;\n+\t else\n+\t htab->sframe_plt = init_table->sframe_non_lazy_ibt_plt;\n+\t}\n+ else\n+\t{\n+\t if (lazy_plt)\n+\t htab->sframe_plt = init_table->sframe_lazy_plt;\n+\t else\n+\t htab->sframe_plt = init_table->sframe_non_lazy_plt;\n+\t}\n+ }\n+ else\n+ htab->sframe_plt = NULL;\n+\n+ /* If the non-lazy PLT is available, use it for all PLT entries if\n+ there are no PLT0 or no .plt section. */\n+ if (!lazy_plt)\n {\n- lazy_plt = false;\n if (bfd_link_pic (info))\n \thtab->plt.plt_entry = htab->non_lazy_plt->pic_plt_entry;\n else\n@@ -3969,7 +4304,6 @@ _bfd_x86_elf_link_setup_gnu_properties\n }\n else\n {\n- lazy_plt = true;\n if (bfd_link_pic (info))\n \t{\n \t htab->plt.plt0_entry = htab->lazy_plt->pic_plt0_entry;\n@@ -4145,6 +4479,39 @@ _bfd_x86_elf_link_setup_gnu_properties\n \t htab->plt_second_eh_frame = sec;\n \t }\n \t}\n+\n+ /* .sframe sections are emitted for AMD64 ABI only. */\n+ if (ABI_64_P (info->output_bfd) && !info->no_ld_generated_unwind_info)\n+\t{\n+\t flagword flags = (SEC_ALLOC | SEC_LOAD | SEC_READONLY\n+\t\t\t | SEC_HAS_CONTENTS | SEC_IN_MEMORY\n+\t\t\t | SEC_LINKER_CREATED);\n+\n+\t sec = bfd_make_section_anyway_with_flags (dynobj,\n+\t\t\t\t\t\t \".sframe\",\n+\t\t\t\t\t\t flags);\n+\t if (sec == NULL)\n+\t info->callbacks->einfo (_(\"%F%P: failed to create PLT .sframe section\\n\"));\n+\n+\t // FIXME check this\n+\t // if (!bfd_set_section_alignment (sec, class_align))\n+\t // goto error_alignment;\n+\n+\t htab->plt_sframe = sec;\n+\n+\t /* Second PLT is generated for Intel IBT / MPX Support + lazy plt. */\n+\t if (htab->plt_second != NULL)\n+\t {\n+\t sec = bfd_make_section_anyway_with_flags (dynobj,\n+\t\t\t\t\t\t\t\".sframe\",\n+\t\t\t\t\t\t\tflags);\n+\t if (sec == NULL)\n+\t\tinfo->callbacks->einfo (_(\"%F%P: failed to create second PLT .sframe section\\n\"));\n+\n+\t htab->plt_second_sframe = sec;\n+\t }\n+\t /* FIXME - add later for plt_got. */\n+\t}\n }\n \n /* The .iplt section is used for IFUNC symbols in static\ndiff --git a/bfd/elfxx-x86.h b/bfd/elfxx-x86.h\nindex 7d23893938c..83f417acb0c 100644\n--- a/bfd/elfxx-x86.h\n+++ b/bfd/elfxx-x86.h\n@@ -30,6 +30,7 @@\n #include \"elf-linker-x86.h\"\n #include \"elf/i386.h\"\n #include \"elf/x86-64.h\"\n+#include \"sframe-api.h\"\n \n #define X86_64_PCREL_TYPE_P(TYPE) \\\n ((TYPE) == R_X86_64_PC8 \\\n@@ -105,6 +106,11 @@\n || (TYPE) == R_X86_64_PC32_BND \\\n || (TYPE) == R_X86_64_PC64)\n \n+/* This must be the same as sframe_get_hdr_size (sfh). For x86-64, this value\n+ is the same as sizeof (sframe_header) because there is no SFrame auxilliary\n+ header. */\n+#define PLT_SFRAME_FDE_START_OFFSET\tsizeof (sframe_header)\n+\n #define ABI_64_P(abfd) \\\n (get_elf_backend_data (abfd)->s->elfclass == ELFCLASS64)\n \n@@ -388,6 +394,24 @@ struct elf_x86_link_hash_entry\n bfd_vma tlsdesc_got;\n };\n \n+#define SFRAME_PLT0_MAX_NUM_FRES 2\n+#define SFRAME_PLTN_MAX_NUM_FRES 2\n+\n+struct elf_x86_sframe_plt\n+{\n+ unsigned int plt0_entry_size;\n+ unsigned int plt0_num_fres;\n+ const sframe_frame_row_entry *plt0_fres[SFRAME_PLT0_MAX_NUM_FRES];\n+\n+ unsigned int pltn_entry_size;\n+ unsigned int pltn_num_fres;\n+ const sframe_frame_row_entry *pltn_fres[SFRAME_PLTN_MAX_NUM_FRES];\n+\n+ unsigned int sec_pltn_entry_size;\n+ unsigned int sec_pltn_num_fres;\n+ const sframe_frame_row_entry *sec_pltn_fres[SFRAME_PLTN_MAX_NUM_FRES];\n+};\n+\n struct elf_x86_lazy_plt_layout\n {\n /* The first entry in a lazy procedure linkage table looks like this. */\n@@ -584,6 +608,11 @@ struct elf_x86_link_hash_table\n asection *plt_got;\n asection *plt_got_eh_frame;\n \n+ sframe_encoder_ctx *plt_cfe_ctx;\n+ asection *plt_sframe;\n+ sframe_encoder_ctx *plt_second_cfe_ctx;\n+ asection *plt_second_sframe;\n+\n /* Parameters describing PLT generation, lazy or non-lazy. */\n struct elf_x86_plt_layout plt;\n \n@@ -593,6 +622,10 @@ struct elf_x86_link_hash_table\n /* Parameters describing non-lazy PLT generation. */\n const struct elf_x86_non_lazy_plt_layout *non_lazy_plt;\n \n+ /* The .sframe helper object for .plt section.\n+ This is used for x86-64 only. */\n+ const struct elf_x86_sframe_plt *sframe_plt;\n+\n union\n {\n bfd_signed_vma refcount;\n@@ -682,6 +715,22 @@ struct elf_x86_init_table\n /* The non-lazy PLT layout for IBT. */\n const struct elf_x86_non_lazy_plt_layout *non_lazy_ibt_plt;\n \n+ /* The .sframe helper object for lazy .plt section.\n+ This is used for x86-64 only. */\n+ const struct elf_x86_sframe_plt *sframe_lazy_plt;\n+\n+ /* The .sframe helper object for non-lazy .plt section.\n+ This is used for x86-64 only. */\n+ const struct elf_x86_sframe_plt *sframe_non_lazy_plt;\n+\n+ /* The .sframe helper object for lazy IBT .plt section.\n+ This is used for x86-64 only. */\n+ const struct elf_x86_sframe_plt *sframe_lazy_ibt_plt;\n+\n+ /* The .sframe helper object for non-lazy IBT .plt section.\n+ This is used for x86-64 only. */\n+ const struct elf_x86_sframe_plt *sframe_non_lazy_ibt_plt;\n+\n bfd_byte plt0_pad_byte;\n \n bfd_vma (*r_info) (bfd_vma, bfd_vma);\ndiff --git a/bfd/section.c b/bfd/section.c\nindex 614570e976e..ba8904d228e 100644\n--- a/bfd/section.c\n+++ b/bfd/section.c\n@@ -409,6 +409,7 @@ CODE_FRAGMENT\n .#define SEC_INFO_TYPE_JUST_SYMS 4\n .#define SEC_INFO_TYPE_TARGET 5\n .#define SEC_INFO_TYPE_EH_FRAME_ENTRY 6\n+.#define SEC_INFO_TYPE_SFRAME 7\n .\n . {* Nonzero if this section uses RELA relocations, rather than REL. *}\n . unsigned int use_rela_p:1;\ndiff --git a/binutils/readelf.c b/binutils/readelf.c\nindex 4d8e540b39b..e52060dbf91 100644\n--- a/binutils/readelf.c\n+++ b/binutils/readelf.c\n@@ -4604,6 +4604,7 @@ get_segment_type (Filedata * filedata, unsigned long p_type)\n case PT_GNU_STACK:\treturn \"GNU_STACK\";\n case PT_GNU_RELRO: return \"GNU_RELRO\";\n case PT_GNU_PROPERTY: return \"GNU_PROPERTY\";\n+ case PT_GNU_SFRAME: return \"GNU_SFRAME\";\n \n case PT_OPENBSD_RANDOMIZE: return \"OPENBSD_RANDOMIZE\";\n case PT_OPENBSD_WXNEEDED: return \"OPENBSD_WXNEEDED\";\ndiff --git a/include/elf/common.h b/include/elf/common.h\nindex 287526d74ed..16587f6fb06 100644\n--- a/include/elf/common.h\n+++ b/include/elf/common.h\n@@ -489,6 +489,7 @@\n #define PT_GNU_STACK\t(PT_LOOS + 0x474e551) /* Stack flags */\n #define PT_GNU_RELRO\t(PT_LOOS + 0x474e552) /* Read-only after relocation */\n #define PT_GNU_PROPERTY\t(PT_LOOS + 0x474e553) /* GNU property */\n+#define PT_GNU_SFRAME\t(PT_LOOS + 0x474e554) /* SFrame unwind information */\n \n /* OpenBSD segment types. */\n #define PT_OPENBSD_RANDOMIZE (PT_LOOS + 0x5a3dbe6) /* Fill with random data. */\ndiff --git a/include/elf/internal.h b/include/elf/internal.h\nindex 8affb3d9b2e..de9f67809b3 100644\n--- a/include/elf/internal.h\n+++ b/include/elf/internal.h\n@@ -339,6 +339,7 @@ struct elf_segment_map\n \t || (segment)->p_type == PT_GNU_EH_FRAME\t\t\t\\\n \t || (segment)->p_type == PT_GNU_STACK\t\t\t\\\n \t || (segment)->p_type == PT_GNU_RELRO\t\t\t\\\n+\t || (segment)->p_type == PT_GNU_SFRAME\t\t\t\\\n \t || ((segment)->p_type >= PT_GNU_MBIND_LO\t\t\t\\\n \t\t&& (segment)->p_type <= PT_GNU_MBIND_HI)))\t\t\\\n /* Any section besides one of type SHT_NOBITS must have file\t\t\\\ndiff --git a/include/sframe-api.h b/include/sframe-api.h\nindex f0924dc91e3..010a35a1674 100644\n--- a/include/sframe-api.h\n+++ b/include/sframe-api.h\n@@ -187,7 +187,7 @@ sframe_encode (unsigned char ver, unsigned char flags, int abi,\n \n /* Free the encoder context. */\n extern void\n-sframe_free_encoder (sframe_encoder_ctx *encoder);\n+sframe_encoder_free (sframe_encoder_ctx **encoder);\n \n /* Get the size of the SFrame header from the encoder ctx ENCODER. */\n extern unsigned int\ndiff --git a/ld/Makefile.am b/ld/Makefile.am\nindex 66e9094e86a..65fef4e1690 100644\n--- a/ld/Makefile.am\n+++ b/ld/Makefile.am\n@@ -972,6 +972,7 @@ EXTRA_ld_new_SOURCES += $(ALL_EMULATION_SOURCES) $(ALL_64_EMULATION_SOURCES)\n # This is the real libbfd.a and libctf.a created by libtool.\n TESTBFDLIB = @TESTBFDLIB@\n TESTCTFLIB = @TESTCTFLIB@\n+TESTSFRAMELIB = @TESTSFRAMELIB@\n \n check-DEJAGNU: site.exp\n \t(cd .libs; test -e ldscripts || test ! -e ld-new || $(LN_S) ../ldscripts .)\n@@ -989,6 +990,7 @@ check-DEJAGNU: site.exp\n \t\tCXX_FOR_TARGET=\"$(CXX_FOR_TARGET)\" \\\n \t\tCXXFLAGS_FOR_TARGET=\"$(CXXFLAGS_FOR_TARGET)\" \\\n \t\tOFILES=\"$(OFILES)\" BFDLIB=\"$(TESTBFDLIB)\" CTFLIB=\"$(TESTCTFLIB) $(ZLIB)\" \\\n+\t\tSFRAMELIB=\"$(TESTSFRAMELIB)\" \\\n \t\tLIBIBERTY=\"$(LIBIBERTY) $(LIBINTL)\" LIBS=\"$(LIBS)\" \\\n \t\tDO_COMPARE=\"`echo '$(do_compare)' | sed -e 's,\\\\$$,,g'`\" \\\n \t\t$(RUNTESTFLAGS); \\\ndiff --git a/ld/Makefile.in b/ld/Makefile.in\nindex 5e4787f89b4..ff4c916c27b 100644\n--- a/ld/Makefile.in\n+++ b/ld/Makefile.in\n@@ -470,6 +470,7 @@ TARGET_SYSTEM_ROOT_DEFINE = @TARGET_SYSTEM_ROOT_DEFINE@\n # This is the real libbfd.a and libctf.a created by libtool.\n TESTBFDLIB = @TESTBFDLIB@\n TESTCTFLIB = @TESTCTFLIB@\n+TESTSFRAMELIB = @TESTSFRAMELIB@\n USE_NLS = @USE_NLS@\n VERSION = @VERSION@\n WARN_CFLAGS = @WARN_CFLAGS@\n@@ -2642,6 +2643,7 @@ check-DEJAGNU: site.exp\n \t\tCXX_FOR_TARGET=\"$(CXX_FOR_TARGET)\" \\\n \t\tCXXFLAGS_FOR_TARGET=\"$(CXXFLAGS_FOR_TARGET)\" \\\n \t\tOFILES=\"$(OFILES)\" BFDLIB=\"$(TESTBFDLIB)\" CTFLIB=\"$(TESTCTFLIB) $(ZLIB)\" \\\n+\t\tSFRAMELIB=\"$(TESTSFRAMELIB)\" \\\n \t\tLIBIBERTY=\"$(LIBIBERTY) $(LIBINTL)\" LIBS=\"$(LIBS)\" \\\n \t\tDO_COMPARE=\"`echo '$(do_compare)' | sed -e 's,\\\\$$,,g'`\" \\\n \t\t$(RUNTESTFLAGS); \\\ndiff --git a/ld/configure b/ld/configure\nindex 79000452c95..a4d30abfb1c 100755\n--- a/ld/configure\n+++ b/ld/configure\n@@ -634,6 +634,7 @@ ac_subst_vars='am__EXEEXT_FALSE\n am__EXEEXT_TRUE\n LTLIBOBJS\n LIBOBJS\n+TESTSFRAMELIB\n TESTCTFLIB\n TESTBFDLIB\n EMULATION_LIBPATH\n@@ -11624,7 +11625,7 @@ else\n lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2\n lt_status=$lt_dlunknown\n cat > conftest.$ac_ext <<_LT_EOF\n-#line 11627 \"configure\"\n+#line 11628 \"configure\"\n #include \"confdefs.h\"\n \n #if HAVE_DLFCN_H\n@@ -11730,7 +11731,7 @@ else\n lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2\n lt_status=$lt_dlunknown\n cat > conftest.$ac_ext <<_LT_EOF\n-#line 11733 \"configure\"\n+#line 11734 \"configure\"\n #include \"confdefs.h\"\n \n #if HAVE_DLFCN_H\n@@ -17487,9 +17488,11 @@ EMULATION_LIBPATH=$all_libpath\n if test x${enable_static} = xno; then\n TESTBFDLIB=\"-Wl,--rpath,../bfd/.libs ../bfd/.libs/libbfd.so\"\n TESTCTFLIB=\"-Wl,--rpath,../libctf/.libs ../libctf/.libs/libctf.so\"\n+ TESTSFRAMELIB=\"-Wl,--rpath,../libsframe/.libs ../libsframe/.libs/libsframe.so\"\n else\n TESTBFDLIB=\"../bfd/.libs/libbfd.a\"\n TESTCTFLIB=\"../libctf/.libs/libctf.a\"\n+ TESTSFRAMELIB=\"../libsframe/.libs/libsframe.a\"\n fi\n if test \"${enable_libctf}\" = no; then\n TESTCTFLIB=\n@@ -17497,6 +17500,7 @@ fi\n \n \n \n+\n target_vendor=${target_vendor=$host_vendor}\n case \"$target_vendor\" in\n hp) EXTRA_SHLIB_EXTENSION=\".sl\" ;;\ndiff --git a/ld/configure.ac b/ld/configure.ac\nindex 6123ea78611..1ee40a51b08 100644\n--- a/ld/configure.ac\n+++ b/ld/configure.ac\n@@ -628,15 +628,18 @@ AC_SUBST(EMULATION_LIBPATH)\n if test x${enable_static} = xno; then\n TESTBFDLIB=\"-Wl,--rpath,../bfd/.libs ../bfd/.libs/libbfd.so\"\n TESTCTFLIB=\"-Wl,--rpath,../libctf/.libs ../libctf/.libs/libctf.so\"\n+ TESTSFRAMELIB=\"-Wl,--rpath,../libsframe/.libs ../libsframe/.libs/libsframe.so\"\n else\n TESTBFDLIB=\"../bfd/.libs/libbfd.a\"\n TESTCTFLIB=\"../libctf/.libs/libctf.a\"\n+ TESTSFRAMELIB=\"../libsframe/.libs/libsframe.a\"\n fi\n if test \"${enable_libctf}\" = no; then\n TESTCTFLIB=\n fi\n AC_SUBST(TESTBFDLIB)\n AC_SUBST(TESTCTFLIB)\n+AC_SUBST(TESTSFRAMELIB)\n \n target_vendor=${target_vendor=$host_vendor}\n case \"$target_vendor\" in\ndiff --git a/ld/ld.texi b/ld/ld.texi\nindex 82527e3652c..3836465730c 100644\n--- a/ld/ld.texi\n+++ b/ld/ld.texi\n@@ -2837,7 +2837,9 @@ section and ELF @code{PT_GNU_EH_FRAME} segment header.\n @item --no-ld-generated-unwind-info\n Request creation of @code{.eh_frame} unwind info for linker\n generated code sections like PLT. This option is on by default\n-if linker generated unwind info is supported.\n+if linker generated unwind info is supported. This option also\n+controls the generation of @code{.sframe} unwind info for linker\n+generated code sections like PLT.\n \n @kindex --enable-new-dtags\n @kindex --disable-new-dtags\ndiff --git a/ld/scripttempl/elf.sc b/ld/scripttempl/elf.sc\nindex bf2268bb0ad..5cc364b0c2a 100644\n--- a/ld/scripttempl/elf.sc\n+++ b/ld/scripttempl/elf.sc\n@@ -601,6 +601,7 @@ cat <sfe_funcdesc);\n- free (encoder->sfe_fres);\n- free (encoder->sfe_data);\n- free (encoder);\n+ sframe_encoder_ctx *ectx = *encoder;\n+ if (ectx == NULL)\n+\treturn;\n+\n+ if (ectx->sfe_funcdesc != NULL)\n+\t{\n+\t free (ectx->sfe_funcdesc);\n+\t ectx->sfe_funcdesc = NULL;\n+\t}\n+ if (ectx->sfe_fres != NULL)\n+\t{\n+\t free (ectx->sfe_fres);\n+\t ectx->sfe_fres = NULL;\n+\t}\n+ if (ectx->sfe_data != NULL)\n+\t{\n+\t free (ectx->sfe_data);\n+\t ectx->sfe_data = NULL;\n+\t}\n+\n+ free (*encoder);\n+ *encoder = NULL;\n }\n }\n \n","prefixes":["V4","06/11"]}+ exit 1 Build step 'Execute shell' marked build as failure Finished: FAILURE