Started by user snail Running as SYSTEM [EnvInject] - Loading node environment variables. Building remotely on docker-jenkins-agent in workspace /home/jenkins/agent/workspace/binutils-gdb [WS-CLEANUP] Deleting project workspace... [WS-CLEANUP] Deferred wipeout is used... [WS-CLEANUP] Done The recommended git tool is: NONE using credential 0adb5fc7-caa2-429d-97d2-c7fa2fa1d884 Cloning the remote Git repository Using shallow clone with depth 1 Avoid fetching tags Cloning repository git@github.com:wangliu-iscas/binutils-gdb.git/ > git init /home/jenkins/agent/workspace/binutils-gdb # timeout=10 Fetching upstream changes from git@github.com:wangliu-iscas/binutils-gdb.git/ > git --version # timeout=10 > git --version # 'git version 2.37.2' using GIT_SSH to set credentials patchwork github wangliu-iscas git ssh key Verifying host key using known hosts file, will automatically accept unseen keys > git fetch --no-tags --force --progress --depth=1 -- git@github.com:wangliu-iscas/binutils-gdb.git/ +refs/heads/*:refs/remotes/origin/* # timeout=10 > git config remote.origin.url git@github.com:wangliu-iscas/binutils-gdb.git/ # timeout=10 > git config --add remote.origin.fetch +refs/heads/*:refs/remotes/origin/* # timeout=10 Avoid second fetch > git rev-parse refs/remotes/origin/master^{commit} # timeout=10 Checking out Revision 0882710510059d9bf10d3e2324e0441029b50ce9 (refs/remotes/origin/master) > git config core.sparsecheckout # timeout=10 > git checkout -f 0882710510059d9bf10d3e2324e0441029b50ce9 # timeout=10 Commit message: "ld: Add publics stream to PDB files" > git rev-list --no-walk beaad4923538f17bb3d915245115e5e6b9830d74 # timeout=10 First time build. Skipping changelog. [EnvInject] - Mask passwords that will be passed as build parameters. [EnvInject] - Executing scripts and injecting environment variables after the SCM step. [EnvInject] - Injecting as environment variables the properties content GITHUB_REPO=https://github.com/wangliu-iscas/ PATCHWORK_URL=https://patchwork.plctlab.org [EnvInject] - Variables injected successfully. [binutils-gdb] $ /usr/bin/env bash /tmp/jenkins5884167289722083710.sh + git config pw.server https://patchwork.plctlab.org/api/1.2/ + git config pw.project binutils-gdb + git config pw.token [*******] ++ date +%Y-%m + now_date=2022-10 ++ date +%Y + now_date_year=2022 + bundle_name=binutils-gdb_2022-10 ++ curl -s -H 'Authorization: Token [*******]' 'https://patchwork.plctlab.org/api/1.2/bundles/?project=binutils-gdb&per_page=999' + bundle_response='[{"id":6,"url":"https://patchwork.plctlab.org/api/1.2/bundles/6/","web_url":"https://patchwork.plctlab.org/bundle/patchwork-bot/binutils-gdb_2022-10/","project":{"id":2,"url":"https://patchwork.plctlab.org/api/1.2/projects/2/","name":"binutils-gdb","link_name":"binutils-gdb","list_id":"binutils.sourceware.org","list_email":"binutils@sourceware.org","web_url":"https://github.com/wangliu-iscas/Patchwork-Bundles/blob/main/binutils-gdb.md","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"name":"binutils-gdb_2022-10","owner":{"id":3,"url":"https://patchwork.plctlab.org/api/1.2/users/3/","username":"patchwork-bot","first_name":"","last_name":"","email":"ouuuleilei@gmail.com"},"patches":[{"id":1592,"url":"https://patchwork.plctlab.org/api/1.2/patches/1592/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/385d01fd-7e57-1f3f-1bae-30aa0c313d63@suse.com/","msgid":"<385d01fd-7e57-1f3f-1bae-30aa0c313d63@suse.com>","list_archive_url":null,"date":"2022-09-30T11:59:45","name":"[3/4] RISC-V/gas: don'\''t open-code insn_length()","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/385d01fd-7e57-1f3f-1bae-30aa0c313d63@suse.com/mbox/"},{"id":1594,"url":"https://patchwork.plctlab.org/api/1.2/patches/1594/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f5757acf-7b90-a0e3-5eea-3b97cc226930@suse.com/","msgid":"","list_archive_url":null,"date":"2022-09-30T12:00:12","name":"[4/4] RISC-V/gas: allow generating up to 176-bit instructions with .insn","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f5757acf-7b90-a0e3-5eea-3b97cc226930@suse.com/mbox/"},{"id":1596,"url":"https://patchwork.plctlab.org/api/1.2/patches/1596/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930140503.38233-1-chigot@adacore.com/","msgid":"<20220930140503.38233-1-chigot@adacore.com>","list_archive_url":null,"date":"2022-09-30T14:05:03","name":"ld/testsuite: consistently add board_ldflags when linking with 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ones","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8db04962aba9c780f133840a8934353a58f223fe.1664602716.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1627,"url":"https://patchwork.plctlab.org/api/1.2/patches/1627/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221001062057.681440-1-maskray@google.com/","msgid":"<20221001062057.681440-1-maskray@google.com>","list_archive_url":null,"date":"2022-10-01T06:20:57","name":"readelf: support zstd compressed debug sections [PR 29640]","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221001062057.681440-1-maskray@google.com/mbox/"},{"id":1631,"url":"https://patchwork.plctlab.org/api/1.2/patches/1631/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/619f112539c0bdecd58e25664f1250a3479a37f5.1664707612.git.aburgess@redhat.com/","msgid":"<619f112539c0bdecd58e25664f1250a3479a37f5.1664707612.git.aburgess@redhat.com>","list_archive_url":null,"date":"2022-10-02T10:47:52","name":"[PATCHv2,2/2] opcodes/arm: add disassembler styling for arm","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/619f112539c0bdecd58e25664f1250a3479a37f5.1664707612.git.aburgess@redhat.com/mbox/"},{"id":1635,"url":"https://patchwork.plctlab.org/api/1.2/patches/1635/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221002185433.gl7dvytfh5wthifx@lug-owl.de/","msgid":"<20221002185433.gl7dvytfh5wthifx@lug-owl.de>","list_archive_url":null,"date":"2022-10-02T18:54:33","name":"diagnostics.h: GCC 13 got -Wself-move, breaks GDB build","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221002185433.gl7dvytfh5wthifx@lug-owl.de/mbox/"},{"id":1637,"url":"https://patchwork.plctlab.org/api/1.2/patches/1637/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003014313.28766-1-mark@harmstone.com/","msgid":"<20221003014313.28766-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-03T01:43:12","name":"[1/2] ld: Add --pdb option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003014313.28766-1-mark@harmstone.com/mbox/"},{"id":1638,"url":"https://patchwork.plctlab.org/api/1.2/patches/1638/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003014313.28766-2-mark@harmstone.com/","msgid":"<20221003014313.28766-2-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-03T01:43:13","name":"[2/2] ld: Add minimal pdb generation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003014313.28766-2-mark@harmstone.com/mbox/"},{"id":1640,"url":"https://patchwork.plctlab.org/api/1.2/patches/1640/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/597ed978-d121-220c-b56b-2ffb94bd091c@suse.cz/","msgid":"<597ed978-d121-220c-b56b-2ffb94bd091c@suse.cz>","list_archive_url":null,"date":"2022-10-03T07:50:38","name":"[1/2] refactor usage of compressed_debug_section_type","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/597ed978-d121-220c-b56b-2ffb94bd091c@suse.cz/mbox/"},{"id":1641,"url":"https://patchwork.plctlab.org/api/1.2/patches/1641/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b8acdd83-f33a-74b8-e21a-23719a0b1a60@suse.cz/","msgid":"","list_archive_url":null,"date":"2022-10-03T07:50:44","name":"[2/2] add --enable-default-compressed-debug-sections-algorithm configure option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b8acdd83-f33a-74b8-e21a-23719a0b1a60@suse.cz/mbox/"},{"id":1642,"url":"https://patchwork.plctlab.org/api/1.2/patches/1642/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003101328.1790113-1-aburgess@redhat.com/","msgid":"<20221003101328.1790113-1-aburgess@redhat.com>","list_archive_url":null,"date":"2022-10-03T10:13:28","name":"opcodes/riscv: style csr names as registers","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003101328.1790113-1-aburgess@redhat.com/mbox/"},{"id":1643,"url":"https://patchwork.plctlab.org/api/1.2/patches/1643/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7ba14fc4472ce97d4f7a4433cad8a571e89f82f4.1664793840.git.research_trasio@irq.a4lg.com/","msgid":"<7ba14fc4472ce97d4f7a4433cad8a571e89f82f4.1664793840.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-03T10:43:59","name":"[v3,1/6] RISC-V: Fix immediates to have \"immediate\" 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\"immediate\"","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0b68af932117258c908db62cf87c3a15d3cdec41.1664793840.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1656,"url":"https://patchwork.plctlab.org/api/1.2/patches/1656/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/87lepxcd6x.fsf@redhat.com/","msgid":"<87lepxcd6x.fsf@redhat.com>","list_archive_url":null,"date":"2022-10-03T12:19:02","name":"Commit: readelf: Do not load section data from offset 0","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/87lepxcd6x.fsf@redhat.com/mbox/"},{"id":1659,"url":"https://patchwork.plctlab.org/api/1.2/patches/1659/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e0d369d419da9c0441f415da7f54352aead8f655.1664707612.git.aburgess@redhat.com/","msgid":"","list_archive_url":null,"date":"2022-10-03T16:37:36","name":"[PATCHv2,1/2] opcodes/arm: use '\''@'\'' consistently for the comment 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| | | 1620 gold: add --compress-debug-sections=zstd [PR 29641] | | | 1623 [RFC,1/1] RISC-V: Implement common register pair framework | | | 1625 [RFC,1/1] RISC-V: Implement extension variants | | | 1626 [1/1] RISC-V: Move supervisor instructions after all unprivileged ones | | | 1627 readelf: support zstd compressed debug sections [PR 29640] | | | 1631 [PATCHv2,2/2] opcodes/arm: add disassembler styling for arm | | | 1635 diagnostics.h: GCC 13 got -Wself-move, breaks GDB build | | | 1637 [1/2] ld: Add --pdb option | | | 1638 [2/2] ld: Add minimal pdb generation | | | 1640 [1/2] refactor usage of compressed_debug_section_type | | | 1641 [2/2] add --enable-default-compressed-debug-sections-algorithm configure option | | | 1642 opcodes/riscv: style csr names as registers | | | 1643 [v3,1/6] RISC-V: Fix immediates to have "immediate" style | | | 1644 [v3,2/6] RISC-V: Fix printf argument types corresponding %x | | | 1647 [v3,3/6] RISC-V: Optimize riscv_disassemble_data printf | | | 1646 [v3,4/6] RISC-V: Print comma and tabs as the "text" style | | | 1648 [v3,5/6] RISC-V: Fix T-Head immediate types on printing | | | 1649 [v3,6/6] RISC-V: Print XTheadMemPair literal as "immediate" | | | 1656 Commit: readelf: Do not load section data from offset 0 | | | 1659 [PATCHv2,1/2] opcodes/arm: use '@' consistently for the comment character | | | 1660 gas: NEWS: Mention the T-Head extensions that were recently added | | | 1671 Support objcopy changing compression to or from zstd | | | 1673 [1/2] RISC-V: Fix buffer overflow on print_insn_riscv | | | 1672 [2/2] gdb/riscv: Fix buffer overflow on riscv_insn::fetch_instruction | | | 1676 [v2,1/2] RISC-V: Fix buffer overflow on print_insn_riscv | | | 1677 [v2,2/2] gdb/riscv: Partial support for instructions up to 176-bits | | | 1678 [v3,1/2] RISC-V: Fix buffer overflow on print_insn_riscv | | | 1679 [v3,2/2] gdb/riscv: Partial support for instructions up to 176-bit | | | 1681 RISC-V: Zicbo{m,p,z} adjustments to riscv_multi_subset_supports_ext() | | | 1690 gprofng: fix build with --enable-pgo-build=lto | | | 1691 bfd: xtensa: fix __stop_SECTION literal drop, | | | 1702 [RFC] bfd: use bfd_vma for the 64-bit version of put[lb] and get[lb] | | | 1711 PR29647, objdump -S looping | | | 1712 [v3,1/7] x86: constify parse_insn()'s input | | | 1713 [v3,2/7] x86: introduce Pass2 insn attribute | | | 1714 [v3,3/7] x86: re-work insn/suffix recognition | | | 1715 [v3,4/7] x86-64: further re-work insn/suffix recognition to also cover MOVSL | | | 1716 [v3,5/7] ix86: don't recognize/derive Q suffix in the common case | | | 1718 [v3,6/7] x86-64: allow HLE store of accumulator to absolute 32-bit address | | | 1717 [v3,7/7] x86: move bad-use-of-TLS-reloc check | | | 1719 x86: drop "regmask" static variable | | | 1751 [v2,1/2] RISC-V: Fallback for instructions longer than 64b | | | 1752 [v2,2/2] RISC-V: Improve "bits undefined" diagnostics | | | 1776 [v3,1/2] RISC-V: Fallback for instructions longer than 64b | | | 1777 [v3,2/2] RISC-V: Improve "bits undefined" diagnostics | | | 1781 RISC-V: fix linker message when relaxation deletes bytes | | | 1801 PR29653, objcopy/strip: fuzzed small input file induces large output file | | | 1803 @CPP_FOR_BUILD@ problem since binutils-2.38 | | | 1827 [v2,1/1] RISC-V: Test DWARF register numbers for "fp" | | | 1828 [1/1] RISC-V: Move standard hints before all instructions | | | 1829 [RFC,1/1] RISC-V: Imply 'Zicsr' from privileged extensions with CSRs | | | 1830 [1/5] opcodes/riscv-dis.c: Tidying with comments/clarity | | | 1832 [2/5] opcodes/riscv-dis.c: Tidying with spacing | | | 1831 [3/5] opcodes/riscv-dis.c: Use bool type whenever possible | | | 1833 [4/5] opcodes/riscv-dis.c: Make XLEN variable static | | | 1834 [5/5] opcodes/riscv-dis.c: Remove last_map_state | | | 1836 RISC-V: Move certain arrays to riscv-opc.c | | | 1844 [v2,1/2] ld: Add --pdb option | | | 1845 [v2,2/2] ld: Add minimal pdb generation | | | 1890 gprofng: run tests without installation | | | 1893 [2/2] gprofng: use the --libdir path to find libraries | | | 1894 [3/3] gprofng: no need to build version.texi | | | 1895 [v3,1/2] ld: Add --pdb option | | | 1897 [v3,2/2] ld: Add minimal pdb generation | | | 1928 [v4,1/2] ld: Add --pdb option | | | 1929 [v4,2/2] ld: Add minimal pdb generation | | | 1941 [pushed] Re-apply "Pass PKG_CONFIG_PATH down from top-level Makefile" | | | 1976 [v4,1/8] x86: constify parse_insn()'s input | | | 1977 [v4,2/8] x86: introduce Pass2 insn attribute | | | 1978 [v4,3/8] x86: re-work insn/suffix recognition | | | 1979 [v4,4/8] x86-64: further re-work insn/suffix recognition to also cover MOVSL | | | 1980 [v4,5/8] ix86: don't recognize/derive Q suffix in the common case | | | 1981 [v4,6/8] x86-64: allow HLE store of accumulator to absolute 32-bit address | | | 1982 [v4,7/8] x86: move bad-use-of-TLS-reloc check | | | 1983 [v4,8/8] x86: drop (now) stray IsString | | | 2013 include: Declare getopt function on old GNU libc | | | 2352 ld: Add --undefined-version | | | 2532 [1/1] RISC-V: Make R_RISCV_SUB6 conforms to riscv abi standard | | | 2560 [v3] aarch64-pe support for LD, GAS and BFD | | | 2602 [01/10] Support Intel AVX-IFMA | | | 2608 [02/10] Support Intel AVX-VNNI-INT8 | | | 2611 [03/10] Support Intel AVX-NE-CONVERT | | | 2610 [04/10] Support Intel CMPccXADD | | | 2601 [05/10] Add handler for more i386_cpu_flags | | | 2606 [06/10] Support Intel RAO-INT | | | 2609 [07/10] Support Intel WRMSRNS | | | 2605 [08/10] Support Intel MSRLIST | | | 2607 [09/10] Support Intel AMX-FP16 | | | 2604 [10/10] Support Intel PREFETCHI | | | 2643 x86: fold AVX512-VNNI disassembler entries with AVX-VNNI ones | | | 2654 PR29677, Field `the_bfd` of `asymbol` is uninitialised | | | 2656 e200 LSP support | | | 2657 PowerPC SPE disassembly and tests | | | 2695 Binutils: Adding new testcase for addr2line. | | | 2700 x86: properly decode EVEX.W for AVX512_4{FMAPS,VNNIW} insns | | | 2981 PowerPC se_rfmci and VLE, SPE2 and LSP insns with -many | | | 3152 [v5,1/2] ld: Add --pdb option | | | 3151 [v5,2/2] ld: Add minimal pdb generation | | | 3258 x86: correct CPU_AMX_{BF16,INT8}_FLAGS | | | 3272 x86: generalize gas documentation for disabling of ISA extensions | | | 3759 [V2,01/15] sframe.h: Add SFrame format definition | | | 3762 [V2,02/15] gas: add new command line option --gsframe | | | 3761 [V2,03/15] gas: generate .sframe from CFI directives | | | 3760 [V2,04/15] gas: testsuite: add new tests for SFrame unwind info | | | 3764 [V2,05/15] libsframe: add the SFrame library | | | 3766 [V2,06/15] bfd: linker: merge .sframe sections | | | 3763 [V2,07/15] readelf/objdump: support for SFrame section | | | 3765 [V2,08/15] unwinder: generate backtrace using SFrame format | | | 3770 [V2,09/15] unwinder: Add SFrame unwinder tests | | | 3769 [V2,10/15] gdb: sim: buildsystem changes to accommodate libsframe | | | 3771 [V2,11/15] libctf: add libsframe to LDFLAGS and LIBS | | | 3768 [V2,12/15] src-release.sh: Add libsframe | | | 3767 [V2,13/15] binutils/NEWS: add text for SFrame support | | | 3772 [V2,14/15] gas/NEWS: add text about new command line option and SFrame support | | | 3773 [V2,15/15] doc: add SFrame spec file | | | 3999 [1/1] IBM zSystems: Issue error for *DBL relocs on misaligned symbols | | | 4141 xtensa: use definitions from xtensa-config.h | | | 4272 x86: Disable AVX-VNNI when disabling AVX2 | | | 4998 x86: re-work AVX-VNNI support | | | 5276 Fix addr2line test for ppc64 elfv1 and mingw | | | 5424 binutils: Remove unused substitution PROGRAM | | | 5433 [v2,1/8] RISC-V: Add a space at the end of pinfo | | | 5435 [v2,2/8] RISC-V: Fix obvious misalignments ('Zbb'/'Zba') | | | 5437 [v2,3/8] RISC-V: Remove spaces in opcode entries | | | 5436 [v2,4/8] RISC-V: Remove unused instruction macros | | | 5440 [v2,5/8] RISC-V: Complete tidying up with SCALL and SBREAK | | | 5442 [v2,6/8] RISC-V: Tidying up with fmv.w.x and fmv.x.w | | | 5438 [v2,7/8] RISC-V: Make alias instructions aliases | | | 5441 [v2,8/8] RISC-V: Use defined mask and match values | | | 5439 RISC-V: Remove RV32EF conflict | | | 5616 [04/10] Support Intel CMPccXADD | | | 5614 [05/10] Add handler for more i386_cpu_flags | | | 5672 [01/10] Support Intel AVX-IFMA | | | 5691 [02/10] Support Intel AVX-VNNI-INT8 | | | 5690 [03/10] Support Intel AVX-NE-CONVERT | | | 5689 [04/10] Support Intel CMPccXADD | | | 5676 [05/10] Add handler for more i386_cpu_flags | | | 5677 [06/10] Support Intel RAO-INT | | | 5681 [07/10] Support Intel WRMSRNS | | | 5682 [08/10] Support Intel MSRLIST | | | 5673 [09/10] Support Intel AMX-FP16 | | | 5686 [10/10] Support Intel PREFETCHI | | | 5940 Obsolete beos | | | 6080 [01/40] gdb/unittests: PR28413, suppress warnings generated by Gnulib | | | 6081 [02/40] sim: Check known getrusage declaration existence | | | 6083 [03/40] sim/aarch64: Remove unused functions | | | 6084 [04/40] cpu/cris: Initialize some variables on CRIS CPU | | | 6082 [05/40] cpu/cris: Add u-stall virtual unit to CRIS v32 | | | 6087 [06/40] sim/cris: Move declarations of f_specific_init | | | 6091 [07/40] sim/cris: Regenerate with CGEN | | | 6085 [08/40] sim/erc32: Insert void parameter | | | 6086 [09/40] sim/erc32: Use int32_t as event callback argument | | | 6090 [10/40] sim/erc32: Use int32_t as IRQ callback argument | | | 6089 [11/40] cpu/frv: Initialize some variables | | | 6088 [12/40] sim/frv: Initialize nesr variable | | | 6093 [13/40] sim/frv: Initialize some variables | | | 6092 [14/40] sim/frv: Add explicit casts | | | 6095 [15/40] sim/h8300: Add "+ 0x0" to avoid self-assignments | | | 6101 [16/40] sim/lm32: fix some missing function declaration warnings | | | 6094 [17/40] sim/lm32: Add explicit casts | | | 6141 [1/3] x86: emit {evex} prefix when disassembling ambiguous AVX512VL insns | | | 6143 [2/3] x86: consolidate VAES tests | | | 6142 [3/3] x86: consolidate VPCLMUL tests | | | 6228 x86-64: Use only one default max-page-size | | | 6229 [1/2] ld/testsuite: skip ld-elf/exclude when -shared is not supported | | | 6230 [2/2] ld/testsuite: adjust ld-arm to run shared tests only when supported | | | 6236 [RFC,top-level] Add configure test-case | | | 6286 x86: Check VEX/EVEX encoding before checking vector operands | | | 7884 [1/5] bfd: xtensa: move common code from ld and gas | | | 7885 [2/5] gas: xtensa: add endianness, loops, booleans options | | | 7886 [3/5] ld: xtensa: use default LD command line options for endianness | | | 7891 [5/5] gdb: xtensa: add support for esp32, esp32s2, esp32s3 isa-modules | | | 10456 [committed,1/2] RISC-V: Improve link time complexity. | | | 10454 [committed,2/2] RISC-V: Should reset `again' flag for _bfd_riscv_relax_pc. | | | 10536 [v5,1/8] x86: constify parse_insn()'s input | | | 10537 [v5,1/8] x86: introduce Pass2 insn attribute | | | 10541 [v5,3/8] x86: re-work insn/suffix recognition | | | 10540 [v5,4/8] ix86: don't recognize/derive Q suffix in the common case | | | 10543 [v5,5/8] x86-64: allow HLE store of accumulator to absolute 32-bit address | | | 10542 [v5,6/8] x86: move bad-use-of-TLS-reloc check | | | 10545 [v5,7/8] x86: drop (now) stray IsString | | | 10546 [v5,8/8] x86: further re-work insn/suffix recognition to also cover MOVSX | | | 10777 [RFC] RISC-V: Allocate "various" operand type | | | 11062 PR29720, objdump -S crashes if build-id is missing | | | 11063 som.c buffer overflow | | | 11064 som.c reloc sanity checking | | | 11080 segfault in objdump.c reloc_at | | | 11081 Correct ELF reloc size sanity check | | | 11082 opcodes: RX fix invalid output. | | | 11089 buffer overflow in _bfd_XX_print_ce_compressed_pdata | | | 11157 tests: use canonical option name | | | 11526 [v2] RISC-V: Optimize relax of GP/call with max_alignment. | | | 11619 include: Define macro to ignore -Wdeprecated-declarations on GCC | | | 11627 Fuzzed files in archives | | | 11658 [committed] RISC-V: Fix build failures for -Werror=sign-compare. | | | 11921 [1/2] ld: Add section header stream to PDB files | | | 11922 [2/2] ld: Add publics stream to PDB files | | | 11965 [1/2] gas: NEWS: Add a missing newline | | | 11966 [2/2] gas: NEWS: Note support for RISC-V Zawrs | | | 12016 [COMMITTED] PowerPC: Add support for RFC02653 - Dense Math Facility | | | 12017 [COMMITTED] PowerPC: Add support for RFC02658 - MMA+ Outer-Product, Instructions | | | 12122 RISC-V: Fix build failure for -Werror=maybe-uninitialized | | | 12181 RISC-V: Added SiFive custom cache control extensions. | | | 12211 RISC-V/gas: fix build with certain gcc versions | | | 12249 x86: minor improvements to optimize_imm() (part III) | | | 12382 RISC-V: Emit mapping symbol with ISA string if non-default arch is used | | | 12627 [committed] RISC-V: Always generate mapping symbols at the start of the sections. | | | 12629 NULL dereference read in som_write_object_contents | | | 12630 Fix small objcopy memory leak | | | 12631 pef: sanity check before malloc | | | 12950 [V3,01/15] sframe.h: Add SFrame format definition | | | 12952 [V3,02/15] gas: add new command line option --gsframe | | | 12951 [V3,03/15] gas: generate .sframe from CFI directives | | | 12956 [V3,04/15] gas: testsuite: add new tests for SFrame unwind info | | | 12955 [V3,05/15] libsframe: add the SFrame library | | | 12959 [V3,06/15] bfd: linker: merge .sframe sections | | | 12961 [V3,07/15] readelf/objdump: support for SFrame section | | | 12962 [V3,08/15] unwinder: generate backtrace using SFrame format | | | 12963 [V3,09/15] unwinder: Add SFrame unwinder tests | | | 12964 [V3,10/15] gdb: sim: buildsystem changes to accommodate libsframe | | | 12957 [V3,11/15] libctf: add libsframe to LDFLAGS and LIBS | | | 12960 [V3,12/15] src-release.sh: Add libsframe | | | 12953 [V3,13/15] binutils/NEWS: add text for SFrame support | | | 12954 [V3,14/15] gas/NEWS: add text about new command line option and SFrame support | | | 12958 [V3,15/15] doc: add SFrame spec file | | | 12988 Pool section entries for DWP version 1 | | | 13076 [v2,1/3] ld: Use %E in einfo in pdb.c | | | 13078 [v2,2/3] ld: Add section header stream to PDB files | | | 13077 [v2,3/3] ld: Add publics stream to PDB files | | | 13106 [1/6] Support Intel AVX-IFMA | | | 13105 [2/6] Support Intel AVX-VNNI-INT8 | | | 13103 [3/6] Support Intel CMPccXADD | | | 13101 [4/6] Add handler for more i386_cpu_flags | | | 13104 [5/6] Support Intel WRMSRNS | | | 13102 [6/6] Support Intel MSRLIST | | | 13120 [1/2] i386: Add and | | | 13121 [2/2] Support Intel AVX-NE-CONVERT | +------------+-----------------------------------------------------------------------------------------+ + git config pull.rebase false + git fetch origin master From github.com:wangliu-iscas/binutils-gdb * branch master -> FETCH_HEAD + git checkout master Switched to a new branch 'master' branch 'master' set up to track 'origin/master'. + git pull origin master From github.com:wangliu-iscas/binutils-gdb * branch master -> FETCH_HEAD Already up to date. + git fetch origin upstream-master From github.com:wangliu-iscas/binutils-gdb * branch upstream-master -> FETCH_HEAD + git checkout upstream-master Switched to a new branch 'upstream-master' branch 'upstream-master' set up to track 'origin/upstream-master'. + git remote add upstream https://sourceware.org/git/binutils-gdb.git + git pull upstream master From https://sourceware.org/git/binutils-gdb * branch master -> FETCH_HEAD * [new branch] master -> upstream/master Already up to date. + git push -u origin upstream-master Everything up-to-date branch 'upstream-master' set up to track 'origin/upstream-master'. + git checkout master Switched to branch 'master' Your branch is up to date with 'origin/master'. + git merge upstream-master Already up to date. + git push -u origin master Everything up-to-date branch 'master' set up to track 'origin/master'. + branchname=series4929-patch13121 ++ git branch -a ++ grep 'series4929-patch13121$' + checkbranch= + checkbranchresult=null + '[' null = series4929-patch13121 ']' + git checkout -b series4929-patch13121 Switched to a new branch 'series4929-patch13121' ++ curl https://patchwork.plctlab.org/api/1.2/series/4929/ % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 2287 100 2287 0 0 60184 0 --:--:-- --:--:-- --:--:-- 60184 + series_response='{"id":4929,"url":"https://patchwork.plctlab.org/api/1.2/series/4929/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/list/?series=4929","project":{"id":2,"url":"https://patchwork.plctlab.org/api/1.2/projects/2/","name":"binutils-gdb","link_name":"binutils-gdb","list_id":"binutils.sourceware.org","list_email":"binutils@sourceware.org","web_url":"https://github.com/wangliu-iscas/Patchwork-Bundles/blob/main/binutils-gdb.md","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"name":"Support Intel AVX-NE-CONVERT","date":"2022-10-31T06:05:59","submitter":{"id":113,"url":"https://patchwork.plctlab.org/api/1.2/people/113/","name":"Haochen Jiang","email":"haochen.jiang@intel.com"},"version":4,"total":2,"received_total":2,"received_all":true,"mbox":"https://patchwork.plctlab.org/series/4929/mbox/","cover_letter":{"id":901,"url":"https://patchwork.plctlab.org/api/1.2/covers/901/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/cover/20221031060601.38460-1-haochen.jiang@intel.com/","msgid":"<20221031060601.38460-1-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-31T06:05:59","name":"[v4,0/2] Support Intel AVX-NE-CONVERT","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/cover/20221031060601.38460-1-haochen.jiang@intel.com/mbox/"},"patches":[{"id":13120,"url":"https://patchwork.plctlab.org/api/1.2/patches/13120/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031060601.38460-2-haochen.jiang@intel.com/","msgid":"<20221031060601.38460-2-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-31T06:06:00","name":"[1/2] i386: Add and ","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031060601.38460-2-haochen.jiang@intel.com/mbox/"},{"id":13121,"url":"https://patchwork.plctlab.org/api/1.2/patches/13121/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031060601.38460-3-haochen.jiang@intel.com/","msgid":"<20221031060601.38460-3-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-31T06:06:01","name":"[2/2] Support Intel AVX-NE-CONVERT","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031060601.38460-3-haochen.jiang@intel.com/mbox/"}]}' ++ echo '{"id":4929,"url":"https://patchwork.plctlab.org/api/1.2/series/4929/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/list/?series=4929","project":{"id":2,"url":"https://patchwork.plctlab.org/api/1.2/projects/2/","name":"binutils-gdb","link_name":"binutils-gdb","list_id":"binutils.sourceware.org","list_email":"binutils@sourceware.org","web_url":"https://github.com/wangliu-iscas/Patchwork-Bundles/blob/main/binutils-gdb.md","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"name":"Support Intel AVX-NE-CONVERT","date":"2022-10-31T06:05:59","submitter":{"id":113,"url":"https://patchwork.plctlab.org/api/1.2/people/113/","name":"Haochen Jiang","email":"haochen.jiang@intel.com"},"version":4,"total":2,"received_total":2,"received_all":true,"mbox":"https://patchwork.plctlab.org/series/4929/mbox/","cover_letter":{"id":901,"url":"https://patchwork.plctlab.org/api/1.2/covers/901/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/cover/20221031060601.38460-1-haochen.jiang@intel.com/","msgid":"<20221031060601.38460-1-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-31T06:05:59","name":"[v4,0/2] Support Intel AVX-NE-CONVERT","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/cover/20221031060601.38460-1-haochen.jiang@intel.com/mbox/"},"patches":[{"id":13120,"url":"https://patchwork.plctlab.org/api/1.2/patches/13120/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031060601.38460-2-haochen.jiang@intel.com/","msgid":"<20221031060601.38460-2-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-31T06:06:00","name":"[1/2] i386: Add and ","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031060601.38460-2-haochen.jiang@intel.com/mbox/"},{"id":13121,"url":"https://patchwork.plctlab.org/api/1.2/patches/13121/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031060601.38460-3-haochen.jiang@intel.com/","msgid":"<20221031060601.38460-3-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-31T06:06:01","name":"[2/2] Support Intel AVX-NE-CONVERT","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031060601.38460-3-haochen.jiang@intel.com/mbox/"}]}' ++ jq '.patches[] | (.id|tostring) + "," + .mbox' + patchid_patchurl='"13120,https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031060601.38460-2-haochen.jiang@intel.com/mbox/" "13121,https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031060601.38460-3-haochen.jiang@intel.com/mbox/"' + echo '"13120,https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031060601.38460-2-haochen.jiang@intel.com/mbox/" + IFS=, + read -r series_patch_id series_patch_url "13121,https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031060601.38460-3-haochen.jiang@intel.com/mbox/"' ++ echo '"13120' ++ sed 's/"//g' + series_patch_id=13120 ++ echo 'https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031060601.38460-2-haochen.jiang@intel.com/mbox/"' ++ sed 's/"//g' + series_patch_url=https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031060601.38460-2-haochen.jiang@intel.com/mbox/ ++ git rev-parse HEAD + commitid_before=0882710510059d9bf10d3e2324e0441029b50ce9 + eval '+++ declare -p bout bret declare -- bout="Applying: i386: Add and " declare -- bret="0" ++ berr='\''++++ git_am https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031060601.38460-2-haochen.jiang@intel.com/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031060601.38460-2-haochen.jiang@intel.com/mbox/ ++++ curl https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031060601.38460-2-haochen.jiang@intel.com/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 22159 100 22159 0 0 309k 0 --:--:-- --:--:-- --:--:-- 309k +++ bout='\''\'\'''\''Applying: i386: Add and '\''\'\'''\'' +++ bret=0'\'' ++ declare -p berr declare -- berr="++++ git_am https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031060601.38460-2-haochen.jiang@intel.com/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031060601.38460-2-haochen.jiang@intel.com/mbox/ ++++ curl https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031060601.38460-2-haochen.jiang@intel.com/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 22159 100 22159 0 0 309k 0 --:--:-- --:--:-- --:--:-- 309k +++ bout='\''Applying: i386: Add and '\'' +++ bret=0"' ++ +++ declare -p bout bret /tmp/jenkins5884167289722083710.sh: line 124: +++: command not found ++ declare -- 'bout=Applying: i386: Add and ' ++ declare -- bret=0 ++ ++ 'berr=++++ git_am https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031060601.38460-2-haochen.jiang@intel.com/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031060601.38460-2-haochen.jiang@intel.com/mbox/ ++++ curl https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031060601.38460-2-haochen.jiang@intel.com/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 22159 100 22159 0 0 309k 0 --:--:-- --:--:-- --:--:-- 309k +++ bout='\''Applying: i386: Add and '\'' +++ bret=0' /tmp/jenkins5884167289722083710.sh: line 135: ++: command not found ++ ++ declare -p berr /tmp/jenkins5884167289722083710.sh: line 136: ++: command not found ++ declare -- 'berr=++++ git_am https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031060601.38460-2-haochen.jiang@intel.com/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031060601.38460-2-haochen.jiang@intel.com/mbox/ ++++ curl https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031060601.38460-2-haochen.jiang@intel.com/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 22159 100 22159 0 0 309k 0 --:--:-- --:--:-- --:--:-- 309k +++ bout='\''Applying: i386: Add and '\'' +++ bret=0' ++ git rev-parse HEAD + commitid_after=c3611e63f8f67ddbdc0df15ceef64ded9401d4d1 + '[' 0 = 0 ']' + '[' c3611e63f8f67ddbdc0df15ceef64ded9401d4d1 = 0882710510059d9bf10d3e2324e0441029b50ce9 ']' + '[' 13120 = 13121 ']' + IFS=, + read -r series_patch_id series_patch_url ++ sed 's/"//g' ++ echo '"13121' + series_patch_id=13121 ++ echo 'https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031060601.38460-3-haochen.jiang@intel.com/mbox/"' ++ sed 's/"//g' + series_patch_url=https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031060601.38460-3-haochen.jiang@intel.com/mbox/ ++ git rev-parse HEAD + commitid_before=c3611e63f8f67ddbdc0df15ceef64ded9401d4d1 + eval '+++ declare -p bout bret declare -- bout="Applying: Support Intel AVX-NE-CONVERT error: sha1 information is lacking or useless (gas/NEWS). error: could not build fake ancestor hint: Use '\''git am --show-current-patch=diff'\'' to see the failed patch Patch failed at 0001 Support Intel AVX-NE-CONVERT When you have resolved this problem, run \"git am --continue\". If you prefer to skip this patch, run \"git am --skip\" instead. To restore the original branch and stop patching, run \"git am --abort\"." declare -- bret="128" ++ berr='\''++++ git_am https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031060601.38460-3-haochen.jiang@intel.com/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031060601.38460-3-haochen.jiang@intel.com/mbox/ ++++ curl https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031060601.38460-3-haochen.jiang@intel.com/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 97207 100 97207 0 0 1300k 0 --:--:-- --:--:-- --:--:-- 1300k +++ bout='\''\'\'''\''Applying: Support Intel AVX-NE-CONVERT error: sha1 information is lacking or useless (gas/NEWS). error: could not build fake ancestor hint: Use '\''\'\'''\''\'\''\'\'''\'''\''\'\'''\''git am --show-current-patch=diff'\''\'\'''\''\'\''\'\'''\'''\''\'\'''\'' to see the failed patch Patch failed at 0001 Support Intel AVX-NE-CONVERT When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort".'\''\'\'''\'' +++ bret=128'\'' ++ declare -p berr declare -- berr="++++ git_am https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031060601.38460-3-haochen.jiang@intel.com/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031060601.38460-3-haochen.jiang@intel.com/mbox/ ++++ curl https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031060601.38460-3-haochen.jiang@intel.com/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 97207 100 97207 0 0 1300k 0 --:--:-- --:--:-- --:--:-- 1300k +++ bout='\''Applying: Support Intel AVX-NE-CONVERT error: sha1 information is lacking or useless (gas/NEWS). error: could not build fake ancestor hint: Use '\''\\'\'''\''git am --show-current-patch=diff'\''\\'\'''\'' to see the failed patch Patch failed at 0001 Support Intel AVX-NE-CONVERT When you have resolved this problem, run \"git am --continue\". If you prefer to skip this patch, run \"git am --skip\" instead. To restore the original branch and stop patching, run \"git am --abort\".'\'' +++ bret=128"' ++ +++ declare -p bout bret /tmp/jenkins5884167289722083710.sh: line 124: +++: command not found ++ declare -- 'bout=Applying: Support Intel AVX-NE-CONVERT error: sha1 information is lacking or useless (gas/NEWS). error: could not build fake ancestor hint: Use '\''git am --show-current-patch=diff'\'' to see the failed patch Patch failed at 0001 Support Intel AVX-NE-CONVERT When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort".' ++ declare -- bret=128 ++ ++ 'berr=++++ git_am https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031060601.38460-3-haochen.jiang@intel.com/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031060601.38460-3-haochen.jiang@intel.com/mbox/ ++++ curl https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031060601.38460-3-haochen.jiang@intel.com/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 97207 100 97207 0 0 1300k 0 --:--:-- --:--:-- --:--:-- 1300k +++ bout='\''Applying: Support Intel AVX-NE-CONVERT error: sha1 information is lacking or useless (gas/NEWS). error: could not build fake ancestor hint: Use '\''\'\'''\''git am --show-current-patch=diff'\''\'\'''\'' to see the failed patch Patch failed at 0001 Support Intel AVX-NE-CONVERT When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort".'\'' +++ bret=128' /tmp/jenkins5884167289722083710.sh: line 149: ++: command not found ++ ++ declare -p berr /tmp/jenkins5884167289722083710.sh: line 150: ++: command not found ++ declare -- 'berr=++++ git_am https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031060601.38460-3-haochen.jiang@intel.com/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031060601.38460-3-haochen.jiang@intel.com/mbox/ ++++ curl https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031060601.38460-3-haochen.jiang@intel.com/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 97207 100 97207 0 0 1300k 0 --:--:-- --:--:-- --:--:-- 1300k +++ bout='\''Applying: Support Intel AVX-NE-CONVERT error: sha1 information is lacking or useless (gas/NEWS). error: could not build fake ancestor hint: Use '\''\'\'''\''git am --show-current-patch=diff'\''\'\'''\'' to see the failed patch Patch failed at 0001 Support Intel AVX-NE-CONVERT When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort".'\'' +++ bret=128' ++ git rev-parse HEAD + commitid_after=c3611e63f8f67ddbdc0df15ceef64ded9401d4d1 + '[' 128 = 0 ']' + [[ ++++ git_am https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031060601.38460-3-haochen.jiang@intel.com/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031060601.38460-3-haochen.jiang@intel.com/mbox/ ++++ curl https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031060601.38460-3-haochen.jiang@intel.com/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 97207 100 97207 0 0 1300k 0 --:--:-- --:--:-- --:--:-- 1300k +++ bout='Applying: Support Intel AVX-NE-CONVERT error: sha1 information is lacking or useless (gas/NEWS). error: could not build fake ancestor hint: Use '\''git am --show-current-patch=diff'\'' to see the failed patch Patch failed at 0001 Support Intel AVX-NE-CONVERT When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort".' +++ bret=128 =~ sha1 information is lacking or useless ]] + submit_check warning Unresolved https://patchwork.plctlab.org/jenkins/job/binutils-gdb/265/consoleText 'Git am fail log' + check_state=warning + patch_state=Unresolved + repo_url=https://patchwork.plctlab.org/jenkins/job/binutils-gdb/265/consoleText + DESCRIPTION='Git am fail log' + curl -X POST -H 'Authorization: Token [*******]' -F state=warning -F target_url=https://patchwork.plctlab.org/jenkins/job/binutils-gdb/265/consoleText -F context=binutils-gdb-check -F 'description=Git am fail log' https://patchwork.plctlab.org/api/patches/13121/checks/ % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 975 100 430 100 545 11025 13974 --:--:-- --:--:-- --:--:-- 25000 {"id":1536,"url":"https://patchwork.plctlab.org/api/patches/13121/checks/1536/","user":{"id":1,"url":"https://patchwork.plctlab.org/api/users/1/","username":"snail","first_name":"","last_name":"","email":"wangliu@iscas.ac.cn"},"date":"2022-10-31T06:16:13.137956","state":"warning","target_url":"https://patchwork.plctlab.org/jenkins/job/binutils-gdb/265/consoleText","context":"binutils-gdb-check","description":"Git am fail log"}+ curl -X PATCH -H 'Authorization: Token [*******]' -F state=Unresolved https://patchwork.plctlab.org/api/1.2/patches/13121/ % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0{"id":13121,"url":"https://patchwork.plctlab.org/api/1.2/patches/13121/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031060601.38460-3-haochen.jiang@intel.com/","project":{"id":2,"url":"https://patchwork.plctlab.org/api/1.2/projects/2/","name":"binutils-gdb","link_name":"binutils-gdb","list_id":"binutils.sourceware.org","list_email":"binutils@sourceware.org","web_url":"https://github.com/wangliu-iscas/Patchwork-Bundles/blob/main/binutils-gdb.md","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20221031060601.38460-3-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-31T06:06:01","name":"[2/2] Support Intel AVX-NE-CONVERT","commit_ref":null,"pull_url":null,"state":"unresolved","archived":false,"hash":"a642207007bfb7660abe590ee3e0ab2533e7c54d","submitter":{"id":113,"url":"https://patchwork.plctlab.org/api/1.2/people/113/","name":"Haochen Jiang","email":"haochen.jiang@intel.com"},"delegate":null,"mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031060601.38460-3-haochen.jiang@intel.com/mbox/","series":[{"id":4929,"url":"https://patchwork.plctlab.org/api/1.2/series/4929/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/list/?series=4929","date":"2022-10-31T06:05:59","name":"Support Intel AVX-NE-CONVERT","version":4,"mbox":"https://patchwork.plctlab.org/series/4929/mbox/"}],"comments":"https://patchwork.plctlab.org/api/patches/13121/comments/","check":"warning","checks":"https://patchwork.plctlab.org/api/patches/13121/checks/","tags":{},"headers":{"Return-Path":"","Delivered-To":["ouuuleilei@gmail.com","binutils@sourceware.org"],"Received":["by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp2137171wru;\n Sun, 30 Oct 2022 23:10:02 -0700 (PDT)","from sourceware.org (server2.sourceware.org.\n [2620:52:3:1:0:246e:9693:128c])\n by mx.google.com with ESMTPS id\n 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KxV9C0mZhjYuMLuyUmlRXujVrddIjYbgG4/uku4I8cY7vYkwhfR+6EoyOI1nc0Y1pJ\n\t aefOvhd0Y9dHieeA02NQNhFSh3vKamMDi9qe68hk=","X-Original-To":"binutils@sourceware.org","DMARC-Filter":"OpenDMARC Filter v1.4.1 sourceware.org 401D1385701D","X-IronPort-AV":["E=McAfee;i=\"6500,9779,10516\"; a=\"307550079\"","E=Sophos;i=\"5.95,227,1661842800\"; d=\"scan'208\";a=\"307550079\"","E=McAfee;i=\"6500,9779,10516\"; a=\"633416090\"","E=Sophos;i=\"5.95,227,1661842800\"; d=\"scan'208\";a=\"633416090\""],"X-ExtLoop1":"1","To":"binutils@sourceware.org","Subject":"[PATCH 2/2] Support Intel AVX-NE-CONVERT","Date":"Mon, 31 Oct 2022 14:06:01 +0800","Message-Id":"<20221031060601.38460-3-haochen.jiang@intel.com>","X-Mailer":"git-send-email 2.18.1","In-Reply-To":"<20221031060601.38460-1-haochen.jiang@intel.com>","References":"<20221031060601.38460-1-haochen.jiang@intel.com>","X-Spam-Status":"No, score=-11.6 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH,\n DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0,\n SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6","X-Spam-Checker-Version":"SpamAssassin 3.4.6 (2021-04-09) on\n server2.sourceware.org","X-BeenThere":"binutils@sourceware.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"Binutils mailing list ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","From":"Haochen Jiang via Binutils ","Reply-To":"Haochen Jiang ","Cc":"konglin1 ","Errors-To":"binutils-bounces+ouuuleilei=gmail.com@sourceware.org","Sender":"\"Binutils\" ","X-getmail-retrieved-from-mailbox":"=?utf-8?q?INBOX?=","X-GMAIL-THRID":"=?utf-8?q?1748182254947007122?=","X-GMAIL-MSGID":"=?utf-8?q?1748182344879260307?="},"content":"From: konglin1 \n\ngas/ChangeLog:\n\n\t* NEWS: Support Intel AVX-NE-CONVERT.\n\t* config/tc-i386.c: Add avx_ne_convert.\n\t* doc/c-i386.texi: Document .avx_ne_convert.\n\t* testsuite/gas/i386/i386.exp: Run AVX NE CONVERT tests.\n\t* testsuite/gas/i386/avx-ne-convert-intel.d: New test.\n\t* testsuite/gas/i386/avx-ne-convert.d: Ditto.\n\t* testsuite/gas/i386/avx-ne-convert.s: Ditto.\n\t* testsuite/gas/i386/x86-64-avx-ne-convert-intel.d: Ditto.\n\t* testsuite/gas/i386/x86-64-avx-ne-convert.d: Ditto.\n\t* testsuite/gas/i386/x86-64-avx-ne-convert.s: Ditto.\n\nopcodes/ChangeLog:\n\n\t* i386-dis.c (PREFIX_VEX_0F3872): New.\n\t(PREFIX_VEX_0F38B0_M_1_W_0): Ditto.\n\t(PREFIX_VEX_0F38B1_M_1_W_0): Ditto.\n\t(VEX_W_0F3872_P_1): Ditto.\n\t(VEX_W_0F38B0_M_1): Ditto.\n\t(VEX_W_0F38B1_M_1): Ditto.\n\t(MOD_VEX_0F38B0): Ditto.\n\t(MOD_VEX_0F38B1): Ditto.\n\t(prefix_table): Add PREFIX_VEX_0F3872, PREFIX_VEX_0F38B0_M_1_W_0,\n\tPREFIX_VEX_0F38B1_M_1_W_0.\n\t(vex_table): Add MOD_VEX_0F38B0, MOD_VEX_0F38B1.\n\t(vex_w_table): Add VEX_W_0F3872_P_1, VEX_W_0F38B0_M_1,\n\tVEX_W_0F38B1_M_1.\n\t* i386-gen.c (cpu_flag_init): Add CPU_AVX_NE_CONVERT_FLGAS and\n\tCPU_ANY_AVX_NE_CONVERT_FLAGS.\n\t(cpu_flags): Add CpuAVX_NE_CONVERT.\n\t* i386-init.h: Regenerated.\n\t* i386-opc.h (CpuAVX_NE CONVERT): New.\n\t(i386_cpu_flags): Add cpuavx_ne_convert.\n\t* i386-opc.tbl: Add Intel AVX-NE-CONVERT instructions.\n\t* i386-tbl.h: Regenerated.\n---\n gas/NEWS | 2 +\n gas/config/tc-i386.c | 1 +\n gas/doc/c-i386.texi | 2 +\n gas/testsuite/gas/i386/avx-ne-convert-intel.d | 170 +\n gas/testsuite/gas/i386/avx-ne-convert.d | 170 +\n gas/testsuite/gas/i386/avx-ne-convert.s | 167 +\n gas/testsuite/gas/i386/i386.exp | 4 +\n .../gas/i386/x86-64-avx-ne-convert-intel.d | 170 +\n .../gas/i386/x86-64-avx-ne-convert.d | 170 +\n .../gas/i386/x86-64-avx-ne-convert.s | 167 +\n opcodes/i386-dis.c | 55 +-\n opcodes/i386-gen.c | 7 +-\n opcodes/i386-init.h | 522 +-\n opcodes/i386-opc.h | 3 +\n opcodes/i386-opc.tbl | 12 +\n opcodes/i386-tbl.h | 7978 +++++++++--------\n 16 files changed, 5430 insertions(+), 4170 deletions(-)\n create mode 100644 gas/testsuite/gas/i386/avx-ne-convert-intel.d\n create mode 100644 gas/testsuite/gas/i386/avx-ne-convert.d\n create mode 100644 gas/testsuite/gas/i386/avx-ne-convert.s\n create mode 100644 gas/testsuite/gas/i386/x86-64-avx-ne-convert-intel.d\n create mode 100644 gas/testsuite/gas/i386/x86-64-avx-ne-convert.d\n create mode 100644 gas/testsuite/gas/i386/x86-64-avx-ne-convert.s","diff":"diff --git a/gas/NEWS b/gas/NEWS\nindex c9df5608ec..61e85a8bff 100644\n--- a/gas/NEWS\n+++ b/gas/NEWS\n@@ -1,5 +1,7 @@\n -*- text -*-\n \n+* Add support for Intel AVX-NE-CONVERT instructions.\n+\n * Add support for Intel MSRLIST instructions.\n \n * Add support for Intel WRMSRNS instructions.\ndiff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c\nindex e1de7d9c76..997a87c7c6 100644\n--- a/gas/config/tc-i386.c\n+++ b/gas/config/tc-i386.c\n@@ -1101,6 +1101,7 @@ static const arch_entry cpu_arch[] =\n SUBARCH (cmpccxadd, CMPCCXADD, ANY_CMPCCXADD, false),\n SUBARCH (wrmsrns, WRMSRNS, ANY_WRMSRNS, false),\n SUBARCH (msrlist, MSRLIST, ANY_MSRLIST, false),\n+ SUBARCH (avx_ne_convert, AVX_NE_CONVERT, ANY_AVX_NE_CONVERT, false),\n };\n \n #undef SUBARCH\ndiff --git a/gas/doc/c-i386.texi b/gas/doc/c-i386.texi\nindex 1774979a83..0ef1cece48 100644\n--- a/gas/doc/c-i386.texi\n+++ b/gas/doc/c-i386.texi\n@@ -200,6 +200,7 @@ accept various extension mnemonics. For example,\n @code{cmpccxadd},\n @code{wrmsrns},\n @code{msrlist},\n+@code{avx_ne_convert},\n @code{amx_int8},\n @code{amx_bf16},\n @code{amx_fp16},\n@@ -1495,6 +1496,7 @@ supported on the CPU specified. The choices for @var{cpu_type} are:\n @item @samp{.clwb} @tab @samp{.rdpid} @tab @samp{.ptwrite} @tab @samp{.ibt}\n @item @samp{.prefetchi} @tab @samp{.avx_ifma} @tab @samp{.avx_vnni_int8}\n @item @samp{.cmpccxadd} @tab @samp{.wrmsrns} @tab @samp{.msrlist}\n+@item @samp{.avx_ne_convert}\n @item @samp{.wbnoinvd} @tab @samp{.pconfig} @tab @samp{.waitpkg} @tab @samp{.cldemote}\n @item @samp{.shstk} @tab @samp{.gfni} @tab @samp{.vaes} @tab @samp{.vpclmulqdq}\n @item @samp{.movdiri} @tab @samp{.movdir64b} @tab @samp{.enqcmd} @tab @samp{.tsxldtrk}\ndiff --git a/gas/testsuite/gas/i386/avx-ne-convert-intel.d b/gas/testsuite/gas/i386/avx-ne-convert-intel.d\nnew file mode 100644\nindex 0000000000..490fd9516f\n--- /dev/null\n+++ b/gas/testsuite/gas/i386/avx-ne-convert-intel.d\n@@ -0,0 +1,170 @@\n+#as:\n+#objdump: -dw -Mintel\n+#name: i386 AVX-NE-CONVERT insns (Intel disassembly)\n+#source: avx-ne-convert.s\n+\n+.*: +file format .*\n+\n+Disassembly of section \\.text:\n+\n+0+ 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ymm6,YMMWORD PTR \\[esp\\+esi\\*8\\+0x10000000\\]\n+\\s*[a-f0-9]+:\\s*c4 e2 7e b0 31\\s+vcvtneebf162ps ymm6,YMMWORD PTR \\[ecx\\]\n+\\s*[a-f0-9]+:\\s*c4 e2 7e b0 b1 e0 0f 00 00\\s+vcvtneebf162ps ymm6,YMMWORD PTR \\[ecx\\+0xfe0\\]\n+\\s*[a-f0-9]+:\\s*c4 e2 7e b0 b2 00 f0 ff ff\\s+vcvtneebf162ps ymm6,YMMWORD PTR \\[edx-0x1000\\]\n+\\s*[a-f0-9]+:\\s*c4 e2 79 b0 b4 f4 00 00 00 10\\s+vcvtneeph2ps xmm6,XMMWORD PTR \\[esp\\+esi\\*8\\+0x10000000\\]\n+\\s*[a-f0-9]+:\\s*c4 e2 79 b0 31\\s+vcvtneeph2ps xmm6,XMMWORD PTR \\[ecx\\]\n+\\s*[a-f0-9]+:\\s*c4 e2 79 b0 b1 f0 07 00 00\\s+vcvtneeph2ps xmm6,XMMWORD PTR \\[ecx\\+0x7f0\\]\n+\\s*[a-f0-9]+:\\s*c4 e2 79 b0 b2 00 f8 ff ff\\s+vcvtneeph2ps xmm6,XMMWORD PTR \\[edx-0x800\\]\n+\\s*[a-f0-9]+:\\s*c4 e2 7d b0 b4 f4 00 00 00 10\\s+vcvtneeph2ps ymm6,YMMWORD PTR \\[esp\\+esi\\*8\\+0x10000000\\]\n+\\s*[a-f0-9]+:\\s*c4 e2 7d b0 31\\s+vcvtneeph2ps ymm6,YMMWORD PTR \\[ecx\\]\n+\\s*[a-f0-9]+:\\s*c4 e2 7d b0 b1 e0 0f 00 00\\s+vcvtneeph2ps ymm6,YMMWORD PTR \\[ecx\\+0xfe0\\]\n+\\s*[a-f0-9]+:\\s*c4 e2 7d b0 b2 00 f0 ff ff\\s+vcvtneeph2ps ymm6,YMMWORD PTR \\[edx-0x1000\\]\n+\\s*[a-f0-9]+:\\s*c4 e2 7b b0 b4 f4 00 00 00 10\\s+vcvtneobf162ps xmm6,XMMWORD PTR \\[esp\\+esi\\*8\\+0x10000000\\]\n+\\s*[a-f0-9]+:\\s*c4 e2 7b b0 31\\s+vcvtneobf162ps xmm6,XMMWORD PTR \\[ecx\\]\n+\\s*[a-f0-9]+:\\s*c4 e2 7b b0 b1 f0 07 00 00\\s+vcvtneobf162ps xmm6,XMMWORD PTR \\[ecx\\+0x7f0\\]\n+\\s*[a-f0-9]+:\\s*c4 e2 7b b0 b2 00 f8 ff ff\\s+vcvtneobf162ps xmm6,XMMWORD PTR \\[edx-0x800\\]\n+\\s*[a-f0-9]+:\\s*c4 e2 7f b0 b4 f4 00 00 00 10\\s+vcvtneobf162ps ymm6,YMMWORD PTR \\[esp\\+esi\\*8\\+0x10000000\\]\n+\\s*[a-f0-9]+:\\s*c4 e2 7f b0 31\\s+vcvtneobf162ps ymm6,YMMWORD PTR \\[ecx\\]\n+\\s*[a-f0-9]+:\\s*c4 e2 7f b0 b1 e0 0f 00 00\\s+vcvtneobf162ps ymm6,YMMWORD PTR \\[ecx\\+0xfe0\\]\n+\\s*[a-f0-9]+:\\s*c4 e2 7f b0 b2 00 f0 ff ff\\s+vcvtneobf162ps ymm6,YMMWORD PTR \\[edx-0x1000\\]\n+\\s*[a-f0-9]+:\\s*c4 e2 78 b0 b4 f4 00 00 00 10\\s+vcvtneoph2ps xmm6,XMMWORD PTR \\[esp\\+esi\\*8\\+0x10000000\\]\n+\\s*[a-f0-9]+:\\s*c4 e2 78 b0 31\\s+vcvtneoph2ps xmm6,XMMWORD PTR \\[ecx\\]\n+\\s*[a-f0-9]+:\\s*c4 e2 78 b0 b1 f0 07 00 00\\s+vcvtneoph2ps xmm6,XMMWORD PTR \\[ecx\\+0x7f0\\]\n+\\s*[a-f0-9]+:\\s*c4 e2 78 b0 b2 00 f8 ff ff\\s+vcvtneoph2ps xmm6,XMMWORD PTR \\[edx-0x800\\]\n+\\s*[a-f0-9]+:\\s*c4 e2 7c b0 b4 f4 00 00 00 10\\s+vcvtneoph2ps ymm6,YMMWORD PTR \\[esp\\+esi\\*8\\+0x10000000\\]\n+\\s*[a-f0-9]+:\\s*c4 e2 7c b0 31\\s+vcvtneoph2ps ymm6,YMMWORD PTR \\[ecx\\]\n+\\s*[a-f0-9]+:\\s*c4 e2 7c b0 b1 e0 0f 00 00\\s+vcvtneoph2ps ymm6,YMMWORD PTR \\[ecx\\+0xfe0\\]\n+\\s*[a-f0-9]+:\\s*c4 e2 7c b0 b2 00 f0 ff ff\\s+vcvtneoph2ps ymm6,YMMWORD PTR \\[edx-0x1000\\]\n+\\s*[a-f0-9]+:\\s*62 f2 7e 08 72 f5\\s+vcvtneps2bf16 xmm6,xmm5\n+\\s*[a-f0-9]+:\\s*62 f2 7e 08 72 f5\\s+vcvtneps2bf16 xmm6,xmm5\n+\\s*[a-f0-9]+:\\s*c4 e2 7a 72 f5\\s+\\{vex\\} vcvtneps2bf16 xmm6,xmm5\n+\\s*[a-f0-9]+:\\s*c4 e2 7a 72 f5\\s+\\{vex\\} vcvtneps2bf16 xmm6,xmm5\n+\\s*[a-f0-9]+:\\s*62 f2 7e 28 72 f5\\s+vcvtneps2bf16 xmm6,ymm5\n+\\s*[a-f0-9]+:\\s*62 f2 7e 28 72 f5\\s+vcvtneps2bf16 xmm6,ymm5\n+\\s*[a-f0-9]+:\\s*c4 e2 7e 72 f5\\s+\\{vex\\} vcvtneps2bf16 xmm6,ymm5\n+\\s*[a-f0-9]+:\\s*c4 e2 7e 72 f5\\s+\\{vex\\} vcvtneps2bf16 xmm6,ymm5\n+\\s*[a-f0-9]+:\\s*62 f2 7e 08 72 b4 f4 00 00 00 10\\s+vcvtneps2bf16 xmm6,XMMWORD PTR \\[esp\\+esi\\*8\\+0x10000000\\]\n+\\s*[a-f0-9]+:\\s*62 f2 7e 08 72 b4 f4 00 00 00 10\\s+vcvtneps2bf16 xmm6,XMMWORD PTR \\[esp\\+esi\\*8\\+0x10000000\\]\n+\\s*[a-f0-9]+:\\s*c4 e2 7a 72 b4 f4 00 00 00 10\\s+\\{vex\\} vcvtneps2bf16 xmm6,XMMWORD PTR \\[esp\\+esi\\*8\\+0x10000000\\]\n+\\s*[a-f0-9]+:\\s*c4 e2 7a 72 b4 f4 00 00 00 10\\s+\\{vex\\} vcvtneps2bf16 xmm6,XMMWORD PTR \\[esp\\+esi\\*8\\+0x10000000\\]\n+\\s*[a-f0-9]+:\\s*62 f2 7e 08 72 31\\s+vcvtneps2bf16 xmm6,XMMWORD PTR \\[ecx\\]\n+\\s*[a-f0-9]+:\\s*62 f2 7e 08 72 31\\s+vcvtneps2bf16 xmm6,XMMWORD PTR \\[ecx\\]\n+\\s*[a-f0-9]+:\\s*c4 e2 7a 72 31\\s+\\{vex\\} vcvtneps2bf16 xmm6,XMMWORD PTR \\[ecx\\]\n+\\s*[a-f0-9]+:\\s*c4 e2 7a 72 31\\s+\\{vex\\} vcvtneps2bf16 xmm6,XMMWORD PTR \\[ecx\\]\n+\\s*[a-f0-9]+:\\s*62 f2 7e 08 72 71 7f\\s+vcvtneps2bf16 xmm6,XMMWORD PTR \\[ecx\\+0x7f0\\]\n+\\s*[a-f0-9]+:\\s*62 f2 7e 08 72 71 7f\\s+vcvtneps2bf16 xmm6,XMMWORD PTR \\[ecx\\+0x7f0\\]\n+\\s*[a-f0-9]+:\\s*c4 e2 7a 72 b1 f0 07 00 00\\s+\\{vex\\} vcvtneps2bf16 xmm6,XMMWORD PTR \\[ecx\\+0x7f0\\]\n+\\s*[a-f0-9]+:\\s*c4 e2 7a 72 b1 f0 07 00 00\\s+\\{vex\\} vcvtneps2bf16 xmm6,XMMWORD PTR \\[ecx\\+0x7f0\\]\n+\\s*[a-f0-9]+:\\s*62 f2 7e 08 72 72 80\\s+vcvtneps2bf16 xmm6,XMMWORD PTR \\[edx-0x800\\]\n+\\s*[a-f0-9]+:\\s*62 f2 7e 08 72 72 80\\s+vcvtneps2bf16 xmm6,XMMWORD PTR \\[edx-0x800\\]\n+\\s*[a-f0-9]+:\\s*c4 e2 7a 72 b2 00 f8 ff ff\\s+\\{vex\\} vcvtneps2bf16 xmm6,XMMWORD PTR \\[edx-0x800\\]\n+\\s*[a-f0-9]+:\\s*c4 e2 7a 72 b2 00 f8 ff ff\\s+\\{vex\\} vcvtneps2bf16 xmm6,XMMWORD PTR \\[edx-0x800\\]\n+\\s*[a-f0-9]+:\\s*62 f2 7e 28 72 71 7f\\s+vcvtneps2bf16 xmm6,YMMWORD PTR \\[ecx\\+0xfe0\\]\n+\\s*[a-f0-9]+:\\s*62 f2 7e 28 72 71 7f\\s+vcvtneps2bf16 xmm6,YMMWORD PTR \\[ecx\\+0xfe0\\]\n+\\s*[a-f0-9]+:\\s*c4 e2 7e 72 b1 e0 0f 00 00\\s+\\{vex\\} vcvtneps2bf16 xmm6,YMMWORD PTR \\[ecx\\+0xfe0\\]\n+\\s*[a-f0-9]+:\\s*c4 e2 7e 72 b1 e0 0f 00 00\\s+\\{vex\\} vcvtneps2bf16 xmm6,YMMWORD PTR \\[ecx\\+0xfe0\\]\n+\\s*[a-f0-9]+:\\s*62 f2 7e 28 72 72 80\\s+vcvtneps2bf16 xmm6,YMMWORD PTR \\[edx-0x1000\\]\n+\\s*[a-f0-9]+:\\s*62 f2 7e 28 72 72 80\\s+vcvtneps2bf16 xmm6,YMMWORD PTR \\[edx-0x1000\\]\n+\\s*[a-f0-9]+:\\s*c4 e2 7e 72 b2 00 f0 ff ff\\s+\\{vex\\} vcvtneps2bf16 xmm6,YMMWORD PTR \\[edx-0x1000\\]\n+\\s*[a-f0-9]+:\\s*c4 e2 7e 72 b2 00 f0 ff ff\\s+\\{vex\\} vcvtneps2bf16 xmm6,YMMWORD PTR \\[edx-0x1000\\]\n+\\s*[a-f0-9]+:\\s*c4 e2 7a b1 b4 f4 00 00 00 10\\s+vbcstnebf162ps xmm6,WORD PTR \\[esp\\+esi\\*8\\+0x10000000\\]\n+\\s*[a-f0-9]+:\\s*c4 e2 7a b1 31\\s+vbcstnebf162ps xmm6,WORD PTR \\[ecx\\]\n+\\s*[a-f0-9]+:\\s*c4 e2 7a b1 b1 fe 00 00 00\\s+vbcstnebf162ps xmm6,WORD PTR \\[ecx\\+0xfe\\]\n+\\s*[a-f0-9]+:\\s*c4 e2 7a b1 b2 00 ff ff ff\\s+vbcstnebf162ps xmm6,WORD PTR \\[edx-0x100\\]\n+\\s*[a-f0-9]+:\\s*c4 e2 7e b1 b4 f4 00 00 00 10\\s+vbcstnebf162ps ymm6,WORD PTR \\[esp\\+esi\\*8\\+0x10000000\\]\n+\\s*[a-f0-9]+:\\s*c4 e2 7e b1 31\\s+vbcstnebf162ps ymm6,WORD PTR \\[ecx\\]\n+\\s*[a-f0-9]+:\\s*c4 e2 7e b1 b1 fe 00 00 00\\s+vbcstnebf162ps ymm6,WORD PTR \\[ecx\\+0xfe\\]\n+\\s*[a-f0-9]+:\\s*c4 e2 7e b1 b2 00 ff ff ff\\s+vbcstnebf162ps ymm6,WORD PTR \\[edx-0x100\\]\n+\\s*[a-f0-9]+:\\s*c4 e2 79 b1 b4 f4 00 00 00 10\\s+vbcstnesh2ps xmm6,WORD PTR \\[esp\\+esi\\*8\\+0x10000000\\]\n+\\s*[a-f0-9]+:\\s*c4 e2 79 b1 31\\s+vbcstnesh2ps xmm6,WORD PTR \\[ecx\\]\n+\\s*[a-f0-9]+:\\s*c4 e2 79 b1 b1 fe 00 00 00\\s+vbcstnesh2ps xmm6,WORD PTR \\[ecx\\+0xfe\\]\n+\\s*[a-f0-9]+:\\s*c4 e2 79 b1 b2 00 ff ff ff\\s+vbcstnesh2ps xmm6,WORD PTR \\[edx-0x100\\]\n+\\s*[a-f0-9]+:\\s*c4 e2 7d b1 b4 f4 00 00 00 10\\s+vbcstnesh2ps ymm6,WORD PTR \\[esp\\+esi\\*8\\+0x10000000\\]\n+\\s*[a-f0-9]+:\\s*c4 e2 7d b1 31\\s+vbcstnesh2ps ymm6,WORD PTR \\[ecx\\]\n+\\s*[a-f0-9]+:\\s*c4 e2 7d b1 b1 fe 00 00 00\\s+vbcstnesh2ps ymm6,WORD PTR \\[ecx\\+0xfe\\]\n+\\s*[a-f0-9]+:\\s*c4 e2 7d b1 b2 00 ff ff ff\\s+vbcstnesh2ps ymm6,WORD PTR \\[edx-0x100\\]\n+\\s*[a-f0-9]+:\\s*c4 e2 7a b0 b4 f4 00 00 00 10\\s+vcvtneebf162ps xmm6,XMMWORD PTR \\[esp\\+esi\\*8\\+0x10000000\\]\n+\\s*[a-f0-9]+:\\s*c4 e2 7a b0 31\\s+vcvtneebf162ps xmm6,XMMWORD PTR \\[ecx\\]\n+\\s*[a-f0-9]+:\\s*c4 e2 7a b0 b1 f0 07 00 00\\s+vcvtneebf162ps xmm6,XMMWORD PTR \\[ecx\\+0x7f0\\]\n+\\s*[a-f0-9]+:\\s*c4 e2 7a b0 b2 00 f8 ff ff\\s+vcvtneebf162ps xmm6,XMMWORD PTR \\[edx-0x800\\]\n+\\s*[a-f0-9]+:\\s*c4 e2 7e b0 b4 f4 00 00 00 10\\s+vcvtneebf162ps ymm6,YMMWORD PTR \\[esp\\+esi\\*8\\+0x10000000\\]\n+\\s*[a-f0-9]+:\\s*c4 e2 7e b0 31\\s+vcvtneebf162ps ymm6,YMMWORD PTR \\[ecx\\]\n+\\s*[a-f0-9]+:\\s*c4 e2 7e b0 b1 e0 0f 00 00\\s+vcvtneebf162ps ymm6,YMMWORD PTR \\[ecx\\+0xfe0\\]\n+\\s*[a-f0-9]+:\\s*c4 e2 7e b0 b2 00 f0 ff ff\\s+vcvtneebf162ps ymm6,YMMWORD PTR \\[edx-0x1000\\]\n+\\s*[a-f0-9]+:\\s*c4 e2 79 b0 b4 f4 00 00 00 10\\s+vcvtneeph2ps xmm6,XMMWORD PTR \\[esp\\+esi\\*8\\+0x10000000\\]\n+\\s*[a-f0-9]+:\\s*c4 e2 79 b0 31\\s+vcvtneeph2ps xmm6,XMMWORD PTR \\[ecx\\]\n+\\s*[a-f0-9]+:\\s*c4 e2 79 b0 b1 f0 07 00 00\\s+vcvtneeph2ps xmm6,XMMWORD PTR \\[ecx\\+0x7f0\\]\n+\\s*[a-f0-9]+:\\s*c4 e2 79 b0 b2 00 f8 ff ff\\s+vcvtneeph2ps xmm6,XMMWORD PTR \\[edx-0x800\\]\n+\\s*[a-f0-9]+:\\s*c4 e2 7d b0 b4 f4 00 00 00 10\\s+vcvtneeph2ps ymm6,YMMWORD PTR \\[esp\\+esi\\*8\\+0x10000000\\]\n+\\s*[a-f0-9]+:\\s*c4 e2 7d b0 31\\s+vcvtneeph2ps ymm6,YMMWORD PTR \\[ecx\\]\n+\\s*[a-f0-9]+:\\s*c4 e2 7d b0 b1 e0 0f 00 00\\s+vcvtneeph2ps ymm6,YMMWORD PTR \\[ecx\\+0xfe0\\]\n+\\s*[a-f0-9]+:\\s*c4 e2 7d b0 b2 00 f0 ff ff\\s+vcvtneeph2ps ymm6,YMMWORD PTR \\[edx-0x1000\\]\n+\\s*[a-f0-9]+:\\s*c4 e2 7b b0 b4 f4 00 00 00 10\\s+vcvtneobf162ps xmm6,XMMWORD PTR \\[esp\\+esi\\*8\\+0x10000000\\]\n+\\s*[a-f0-9]+:\\s*c4 e2 7b b0 31\\s+vcvtneobf162ps xmm6,XMMWORD PTR \\[ecx\\]\n+\\s*[a-f0-9]+:\\s*c4 e2 7b b0 b1 f0 07 00 00\\s+vcvtneobf162ps xmm6,XMMWORD PTR \\[ecx\\+0x7f0\\]\n+\\s*[a-f0-9]+:\\s*c4 e2 7b b0 b2 00 f8 ff ff\\s+vcvtneobf162ps xmm6,XMMWORD PTR \\[edx-0x800\\]\n+\\s*[a-f0-9]+:\\s*c4 e2 7f b0 b4 f4 00 00 00 10\\s+vcvtneobf162ps ymm6,YMMWORD PTR \\[esp\\+esi\\*8\\+0x10000000\\]\n+\\s*[a-f0-9]+:\\s*c4 e2 7f b0 31\\s+vcvtneobf162ps ymm6,YMMWORD PTR \\[ecx\\]\n+\\s*[a-f0-9]+:\\s*c4 e2 7f b0 b1 e0 0f 00 00\\s+vcvtneobf162ps ymm6,YMMWORD PTR \\[ecx\\+0xfe0\\]\n+\\s*[a-f0-9]+:\\s*c4 e2 7f b0 b2 00 f0 ff ff\\s+vcvtneobf162ps ymm6,YMMWORD PTR \\[edx-0x1000\\]\n+\\s*[a-f0-9]+:\\s*c4 e2 78 b0 b4 f4 00 00 00 10\\s+vcvtneoph2ps xmm6,XMMWORD PTR \\[esp\\+esi\\*8\\+0x10000000\\]\n+\\s*[a-f0-9]+:\\s*c4 e2 78 b0 31\\s+vcvtneoph2ps xmm6,XMMWORD PTR \\[ecx\\]\n+\\s*[a-f0-9]+:\\s*c4 e2 78 b0 b1 f0 07 00 00\\s+vcvtneoph2ps xmm6,XMMWORD PTR \\[ecx\\+0x7f0\\]\n+\\s*[a-f0-9]+:\\s*c4 e2 78 b0 b2 00 f8 ff ff\\s+vcvtneoph2ps xmm6,XMMWORD PTR \\[edx-0x800\\]\n+\\s*[a-f0-9]+:\\s*c4 e2 7c b0 b4 f4 00 00 00 10\\s+vcvtneoph2ps ymm6,YMMWORD PTR \\[esp\\+esi\\*8\\+0x10000000\\]\n+\\s*[a-f0-9]+:\\s*c4 e2 7c b0 31\\s+vcvtneoph2ps ymm6,YMMWORD PTR \\[ecx\\]\n+\\s*[a-f0-9]+:\\s*c4 e2 7c b0 b1 e0 0f 00 00\\s+vcvtneoph2ps ymm6,YMMWORD PTR \\[ecx\\+0xfe0\\]\n+\\s*[a-f0-9]+:\\s*c4 e2 7c b0 b2 00 f0 ff ff\\s+vcvtneoph2ps ymm6,YMMWORD PTR \\[edx-0x1000\\]\n+\\s*[a-f0-9]+:\\s*62 f2 7e 08 72 f5\\s+vcvtneps2bf16 xmm6,xmm5\n+\\s*[a-f0-9]+:\\s*62 f2 7e 08 72 f5\\s+vcvtneps2bf16 xmm6,xmm5\n+\\s*[a-f0-9]+:\\s*c4 e2 7a 72 f5\\s+\\{vex\\} vcvtneps2bf16 xmm6,xmm5\n+\\s*[a-f0-9]+:\\s*c4 e2 7a 72 f5\\s+\\{vex\\} vcvtneps2bf16 xmm6,xmm5\n+\\s*[a-f0-9]+:\\s*62 f2 7e 28 72 f5\\s+vcvtneps2bf16 xmm6,ymm5\n+\\s*[a-f0-9]+:\\s*62 f2 7e 28 72 f5\\s+vcvtneps2bf16 xmm6,ymm5\n+\\s*[a-f0-9]+:\\s*c4 e2 7e 72 f5\\s+\\{vex\\} vcvtneps2bf16 xmm6,ymm5\n+\\s*[a-f0-9]+:\\s*c4 e2 7e 72 f5\\s+\\{vex\\} vcvtneps2bf16 xmm6,ymm5\n+\\s*[a-f0-9]+:\\s*62 f2 7e 08 72 b4 f4 00 00 00 10\\s+vcvtneps2bf16 xmm6,XMMWORD PTR \\[esp\\+esi\\*8\\+0x10000000\\]\n+\\s*[a-f0-9]+:\\s*62 f2 7e 08 72 b4 f4 00 00 00 10\\s+vcvtneps2bf16 xmm6,XMMWORD PTR \\[esp\\+esi\\*8\\+0x10000000\\]\n+\\s*[a-f0-9]+:\\s*c4 e2 7a 72 b4 f4 00 00 00 10\\s+\\{vex\\} vcvtneps2bf16 xmm6,XMMWORD PTR \\[esp\\+esi\\*8\\+0x10000000\\]\n+\\s*[a-f0-9]+:\\s*c4 e2 7a 72 b4 f4 00 00 00 10\\s+\\{vex\\} vcvtneps2bf16 xmm6,XMMWORD PTR \\[esp\\+esi\\*8\\+0x10000000\\]\n+\\s*[a-f0-9]+:\\s*62 f2 7e 08 72 31\\s+vcvtneps2bf16 xmm6,XMMWORD PTR \\[ecx\\]\n+\\s*[a-f0-9]+:\\s*62 f2 7e 08 72 31\\s+vcvtneps2bf16 xmm6,XMMWORD PTR \\[ecx\\]\n+\\s*[a-f0-9]+:\\s*c4 e2 7a 72 31\\s+\\{vex\\} vcvtneps2bf16 xmm6,XMMWORD PTR \\[ecx\\]\n+\\s*[a-f0-9]+:\\s*c4 e2 7a 72 31\\s+\\{vex\\} vcvtneps2bf16 xmm6,XMMWORD PTR \\[ecx\\]\n+\\s*[a-f0-9]+:\\s*62 f2 7e 08 72 71 7f\\s+vcvtneps2bf16 xmm6,XMMWORD PTR \\[ecx\\+0x7f0\\]\n+\\s*[a-f0-9]+:\\s*62 f2 7e 08 72 71 7f\\s+vcvtneps2bf16 xmm6,XMMWORD PTR \\[ecx\\+0x7f0\\]\n+\\s*[a-f0-9]+:\\s*c4 e2 7a 72 b1 f0 07 00 00\\s+\\{vex\\} vcvtneps2bf16 xmm6,XMMWORD PTR \\[ecx\\+0x7f0\\]\n+\\s*[a-f0-9]+:\\s*c4 e2 7a 72 b1 f0 07 00 00\\s+\\{vex\\} vcvtneps2bf16 xmm6,XMMWORD PTR \\[ecx\\+0x7f0\\]\n+\\s*[a-f0-9]+:\\s*62 f2 7e 08 72 72 80\\s+vcvtneps2bf16 xmm6,XMMWORD PTR \\[edx-0x800\\]\n+\\s*[a-f0-9]+:\\s*62 f2 7e 08 72 72 80\\s+vcvtneps2bf16 xmm6,XMMWORD PTR \\[edx-0x800\\]\n+\\s*[a-f0-9]+:\\s*c4 e2 7a 72 b2 00 f8 ff ff\\s+\\{vex\\} vcvtneps2bf16 xmm6,XMMWORD PTR \\[edx-0x800\\]\n+\\s*[a-f0-9]+:\\s*c4 e2 7a 72 b2 00 f8 ff ff\\s+\\{vex\\} vcvtneps2bf16 xmm6,XMMWORD PTR \\[edx-0x800\\]\n+\\s*[a-f0-9]+:\\s*62 f2 7e 28 72 71 7f\\s+vcvtneps2bf16 xmm6,YMMWORD PTR \\[ecx\\+0xfe0\\]\n+\\s*[a-f0-9]+:\\s*62 f2 7e 28 72 71 7f\\s+vcvtneps2bf16 xmm6,YMMWORD PTR \\[ecx\\+0xfe0\\]\n+\\s*[a-f0-9]+:\\s*c4 e2 7e 72 b1 e0 0f 00 00\\s+\\{vex\\} vcvtneps2bf16 xmm6,YMMWORD PTR \\[ecx\\+0xfe0\\]\n+\\s*[a-f0-9]+:\\s*c4 e2 7e 72 b1 e0 0f 00 00\\s+\\{vex\\} vcvtneps2bf16 xmm6,YMMWORD PTR \\[ecx\\+0xfe0\\]\n+\\s*[a-f0-9]+:\\s*62 f2 7e 28 72 72 80\\s+vcvtneps2bf16 xmm6,YMMWORD PTR \\[edx-0x1000\\]\n+\\s*[a-f0-9]+:\\s*62 f2 7e 28 72 72 80\\s+vcvtneps2bf16 xmm6,YMMWORD PTR \\[edx-0x1000\\]\n+\\s*[a-f0-9]+:\\s*c4 e2 7e 72 b2 00 f0 ff ff\\s+\\{vex\\} vcvtneps2bf16 xmm6,YMMWORD PTR \\[edx-0x1000\\]\n+\\s*[a-f0-9]+:\\s*c4 e2 7e 72 b2 00 f0 ff ff\\s+\\{vex\\} vcvtneps2bf16 xmm6,YMMWORD PTR \\[edx-0x1000\\]\ndiff --git a/gas/testsuite/gas/i386/avx-ne-convert.d b/gas/testsuite/gas/i386/avx-ne-convert.d\nnew file mode 100644\nindex 0000000000..24f6ae09fe\n--- /dev/null\n+++ b/gas/testsuite/gas/i386/avx-ne-convert.d\n@@ -0,0 +1,170 @@\n+#as:\n+#objdump: -dw\n+#name: i386 AVX-NE-CONVERT insns\n+#source: avx-ne-convert.s\n+\n+.*: +file format .*\n+\n+Disassembly of section \\.text:\n+\n+0+ <_start>:\n+\\s*[a-f0-9]+:\\s*c4 e2 7a b1 b4 f4 00 00 00 10\\s+vbcstnebf162ps 0x10000000\\(%esp,%esi,8\\),%xmm6\n+\\s*[a-f0-9]+:\\s*c4 e2 7a b1 31\\s+vbcstnebf162ps \\(%ecx\\),%xmm6\n+\\s*[a-f0-9]+:\\s*c4 e2 7a b1 b1 fe 00 00 00\\s+vbcstnebf162ps 0xfe\\(%ecx\\),%xmm6\n+\\s*[a-f0-9]+:\\s*c4 e2 7a b1 b2 00 ff ff ff\\s+vbcstnebf162ps -0x100\\(%edx\\),%xmm6\n+\\s*[a-f0-9]+:\\s*c4 e2 7e b1 b4 f4 00 00 00 10\\s+vbcstnebf162ps 0x10000000\\(%esp,%esi,8\\),%ymm6\n+\\s*[a-f0-9]+:\\s*c4 e2 7e b1 31\\s+vbcstnebf162ps \\(%ecx\\),%ymm6\n+\\s*[a-f0-9]+:\\s*c4 e2 7e b1 b1 fe 00 00 00\\s+vbcstnebf162ps 0xfe\\(%ecx\\),%ymm6\n+\\s*[a-f0-9]+:\\s*c4 e2 7e b1 b2 00 ff ff ff\\s+vbcstnebf162ps -0x100\\(%edx\\),%ymm6\n+\\s*[a-f0-9]+:\\s*c4 e2 79 b1 b4 f4 00 00 00 10\\s+vbcstnesh2ps 0x10000000\\(%esp,%esi,8\\),%xmm6\n+\\s*[a-f0-9]+:\\s*c4 e2 79 b1 31\\s+vbcstnesh2ps \\(%ecx\\),%xmm6\n+\\s*[a-f0-9]+:\\s*c4 e2 79 b1 b1 fe 00 00 00\\s+vbcstnesh2ps 0xfe\\(%ecx\\),%xmm6\n+\\s*[a-f0-9]+:\\s*c4 e2 79 b1 b2 00 ff ff ff\\s+vbcstnesh2ps -0x100\\(%edx\\),%xmm6\n+\\s*[a-f0-9]+:\\s*c4 e2 7d b1 b4 f4 00 00 00 10\\s+vbcstnesh2ps 0x10000000\\(%esp,%esi,8\\),%ymm6\n+\\s*[a-f0-9]+:\\s*c4 e2 7d b1 31\\s+vbcstnesh2ps \\(%ecx\\),%ymm6\n+\\s*[a-f0-9]+:\\s*c4 e2 7d b1 b1 fe 00 00 00\\s+vbcstnesh2ps 0xfe\\(%ecx\\),%ymm6\n+\\s*[a-f0-9]+:\\s*c4 e2 7d b1 b2 00 ff ff ff\\s+vbcstnesh2ps -0x100\\(%edx\\),%ymm6\n+\\s*[a-f0-9]+:\\s*c4 e2 7a b0 b4 f4 00 00 00 10\\s+vcvtneebf162ps 0x10000000\\(%esp,%esi,8\\),%xmm6\n+\\s*[a-f0-9]+:\\s*c4 e2 7a b0 31\\s+vcvtneebf162ps \\(%ecx\\),%xmm6\n+\\s*[a-f0-9]+:\\s*c4 e2 7a b0 b1 f0 07 00 00\\s+vcvtneebf162ps 0x7f0\\(%ecx\\),%xmm6\n+\\s*[a-f0-9]+:\\s*c4 e2 7a b0 b2 00 f8 ff ff\\s+vcvtneebf162ps -0x800\\(%edx\\),%xmm6\n+\\s*[a-f0-9]+:\\s*c4 e2 7e b0 b4 f4 00 00 00 10\\s+vcvtneebf162ps 0x10000000\\(%esp,%esi,8\\),%ymm6\n+\\s*[a-f0-9]+:\\s*c4 e2 7e b0 31\\s+vcvtneebf162ps \\(%ecx\\),%ymm6\n+\\s*[a-f0-9]+:\\s*c4 e2 7e b0 b1 e0 0f 00 00\\s+vcvtneebf162ps 0xfe0\\(%ecx\\),%ymm6\n+\\s*[a-f0-9]+:\\s*c4 e2 7e b0 b2 00 f0 ff ff\\s+vcvtneebf162ps -0x1000\\(%edx\\),%ymm6\n+\\s*[a-f0-9]+:\\s*c4 e2 79 b0 b4 f4 00 00 00 10\\s+vcvtneeph2ps 0x10000000\\(%esp,%esi,8\\),%xmm6\n+\\s*[a-f0-9]+:\\s*c4 e2 79 b0 31\\s+vcvtneeph2ps \\(%ecx\\),%xmm6\n+\\s*[a-f0-9]+:\\s*c4 e2 79 b0 b1 f0 07 00 00\\s+vcvtneeph2ps 0x7f0\\(%ecx\\),%xmm6\n+\\s*[a-f0-9]+:\\s*c4 e2 79 b0 b2 00 f8 ff ff\\s+vcvtneeph2ps -0x800\\(%edx\\),%xmm6\n+\\s*[a-f0-9]+:\\s*c4 e2 7d b0 b4 f4 00 00 00 10\\s+vcvtneeph2ps 0x10000000\\(%esp,%esi,8\\),%ymm6\n+\\s*[a-f0-9]+:\\s*c4 e2 7d b0 31\\s+vcvtneeph2ps \\(%ecx\\),%ymm6\n+\\s*[a-f0-9]+:\\s*c4 e2 7d b0 b1 e0 0f 00 00\\s+vcvtneeph2ps 0xfe0\\(%ecx\\),%ymm6\n+\\s*[a-f0-9]+:\\s*c4 e2 7d b0 b2 00 f0 ff ff\\s+vcvtneeph2ps -0x1000\\(%edx\\),%ymm6\n+\\s*[a-f0-9]+:\\s*c4 e2 7b b0 b4 f4 00 00 00 10\\s+vcvtneobf162ps 0x10000000\\(%esp,%esi,8\\),%xmm6\n+\\s*[a-f0-9]+:\\s*c4 e2 7b b0 31\\s+vcvtneobf162ps \\(%ecx\\),%xmm6\n+\\s*[a-f0-9]+:\\s*c4 e2 7b b0 b1 f0 07 00 00\\s+vcvtneobf162ps 0x7f0\\(%ecx\\),%xmm6\n+\\s*[a-f0-9]+:\\s*c4 e2 7b b0 b2 00 f8 ff ff\\s+vcvtneobf162ps -0x800\\(%edx\\),%xmm6\n+\\s*[a-f0-9]+:\\s*c4 e2 7f b0 b4 f4 00 00 00 10\\s+vcvtneobf162ps 0x10000000\\(%esp,%esi,8\\),%ymm6\n+\\s*[a-f0-9]+:\\s*c4 e2 7f b0 31\\s+vcvtneobf162ps \\(%ecx\\),%ymm6\n+\\s*[a-f0-9]+:\\s*c4 e2 7f b0 b1 e0 0f 00 00\\s+vcvtneobf162ps 0xfe0\\(%ecx\\),%ymm6\n+\\s*[a-f0-9]+:\\s*c4 e2 7f b0 b2 00 f0 ff ff\\s+vcvtneobf162ps -0x1000\\(%edx\\),%ymm6\n+\\s*[a-f0-9]+:\\s*c4 e2 78 b0 b4 f4 00 00 00 10\\s+vcvtneoph2ps 0x10000000\\(%esp,%esi,8\\),%xmm6\n+\\s*[a-f0-9]+:\\s*c4 e2 78 b0 31\\s+vcvtneoph2ps \\(%ecx\\),%xmm6\n+\\s*[a-f0-9]+:\\s*c4 e2 78 b0 b1 f0 07 00 00\\s+vcvtneoph2ps 0x7f0\\(%ecx\\),%xmm6\n+\\s*[a-f0-9]+:\\s*c4 e2 78 b0 b2 00 f8 ff ff\\s+vcvtneoph2ps -0x800\\(%edx\\),%xmm6\n+\\s*[a-f0-9]+:\\s*c4 e2 7c b0 b4 f4 00 00 00 10\\s+vcvtneoph2ps 0x10000000\\(%esp,%esi,8\\),%ymm6\n+\\s*[a-f0-9]+:\\s*c4 e2 7c b0 31\\s+vcvtneoph2ps \\(%ecx\\),%ymm6\n+\\s*[a-f0-9]+:\\s*c4 e2 7c b0 b1 e0 0f 00 00\\s+vcvtneoph2ps 0xfe0\\(%ecx\\),%ymm6\n+\\s*[a-f0-9]+:\\s*c4 e2 7c b0 b2 00 f0 ff ff\\s+vcvtneoph2ps -0x1000\\(%edx\\),%ymm6\n+\\s*[a-f0-9]+:\\s*62 f2 7e 08 72 f5\\s+vcvtneps2bf16 %xmm5,%xmm6\n+\\s*[a-f0-9]+:\\s*62 f2 7e 08 72 f5\\s+vcvtneps2bf16 %xmm5,%xmm6\n+\\s*[a-f0-9]+:\\s*c4 e2 7a 72 f5\\s+\\{vex\\} vcvtneps2bf16 %xmm5,%xmm6\n+\\s*[a-f0-9]+:\\s*c4 e2 7a 72 f5\\s+\\{vex\\} vcvtneps2bf16 %xmm5,%xmm6\n+\\s*[a-f0-9]+:\\s*62 f2 7e 28 72 f5\\s+vcvtneps2bf16 %ymm5,%xmm6\n+\\s*[a-f0-9]+:\\s*62 f2 7e 28 72 f5\\s+vcvtneps2bf16 %ymm5,%xmm6\n+\\s*[a-f0-9]+:\\s*c4 e2 7e 72 f5\\s+\\{vex\\} vcvtneps2bf16 %ymm5,%xmm6\n+\\s*[a-f0-9]+:\\s*c4 e2 7e 72 f5\\s+\\{vex\\} vcvtneps2bf16 %ymm5,%xmm6\n+\\s*[a-f0-9]+:\\s*62 f2 7e 08 72 b4 f4 00 00 00 10\\s+vcvtneps2bf16x 0x10000000\\(%esp,%esi,8\\),%xmm6\n+\\s*[a-f0-9]+:\\s*62 f2 7e 08 72 b4 f4 00 00 00 10\\s+vcvtneps2bf16x 0x10000000\\(%esp,%esi,8\\),%xmm6\n+\\s*[a-f0-9]+:\\s*c4 e2 7a 72 b4 f4 00 00 00 10\\s+\\{vex\\} vcvtneps2bf16x 0x10000000\\(%esp,%esi,8\\),%xmm6\n+\\s*[a-f0-9]+:\\s*c4 e2 7a 72 b4 f4 00 00 00 10\\s+\\{vex\\} vcvtneps2bf16x 0x10000000\\(%esp,%esi,8\\),%xmm6\n+\\s*[a-f0-9]+:\\s*62 f2 7e 08 72 31\\s+vcvtneps2bf16x \\(%ecx\\),%xmm6\n+\\s*[a-f0-9]+:\\s*62 f2 7e 08 72 31\\s+vcvtneps2bf16x \\(%ecx\\),%xmm6\n+\\s*[a-f0-9]+:\\s*c4 e2 7a 72 31\\s+\\{vex\\} vcvtneps2bf16x \\(%ecx\\),%xmm6\n+\\s*[a-f0-9]+:\\s*c4 e2 7a 72 31\\s+\\{vex\\} vcvtneps2bf16x \\(%ecx\\),%xmm6\n+\\s*[a-f0-9]+:\\s*62 f2 7e 08 72 71 7f\\s+vcvtneps2bf16x 0x7f0\\(%ecx\\),%xmm6\n+\\s*[a-f0-9]+:\\s*62 f2 7e 08 72 71 7f\\s+vcvtneps2bf16x 0x7f0\\(%ecx\\),%xmm6\n+\\s*[a-f0-9]+:\\s*c4 e2 7a 72 b1 f0 07 00 00\\s+\\{vex\\} vcvtneps2bf16x 0x7f0\\(%ecx\\),%xmm6\n+\\s*[a-f0-9]+:\\s*c4 e2 7a 72 b1 f0 07 00 00\\s+\\{vex\\} vcvtneps2bf16x 0x7f0\\(%ecx\\),%xmm6\n+\\s*[a-f0-9]+:\\s*62 f2 7e 08 72 72 80\\s+vcvtneps2bf16x -0x800\\(%edx\\),%xmm6\n+\\s*[a-f0-9]+:\\s*62 f2 7e 08 72 72 80\\s+vcvtneps2bf16x -0x800\\(%edx\\),%xmm6\n+\\s*[a-f0-9]+:\\s*c4 e2 7a 72 b2 00 f8 ff ff\\s+\\{vex\\} vcvtneps2bf16x -0x800\\(%edx\\),%xmm6\n+\\s*[a-f0-9]+:\\s*c4 e2 7a 72 b2 00 f8 ff ff\\s+\\{vex\\} vcvtneps2bf16x -0x800\\(%edx\\),%xmm6\n+\\s*[a-f0-9]+:\\s*62 f2 7e 28 72 71 7f\\s+vcvtneps2bf16y 0xfe0\\(%ecx\\),%xmm6\n+\\s*[a-f0-9]+:\\s*62 f2 7e 28 72 71 7f\\s+vcvtneps2bf16y 0xfe0\\(%ecx\\),%xmm6\n+\\s*[a-f0-9]+:\\s*c4 e2 7e 72 b1 e0 0f 00 00\\s+\\{vex\\} vcvtneps2bf16y 0xfe0\\(%ecx\\),%xmm6\n+\\s*[a-f0-9]+:\\s*c4 e2 7e 72 b1 e0 0f 00 00\\s+\\{vex\\} vcvtneps2bf16y 0xfe0\\(%ecx\\),%xmm6\n+\\s*[a-f0-9]+:\\s*62 f2 7e 28 72 72 80\\s+vcvtneps2bf16y -0x1000\\(%edx\\),%xmm6\n+\\s*[a-f0-9]+:\\s*62 f2 7e 28 72 72 80\\s+vcvtneps2bf16y -0x1000\\(%edx\\),%xmm6\n+\\s*[a-f0-9]+:\\s*c4 e2 7e 72 b2 00 f0 ff ff\\s+\\{vex\\} vcvtneps2bf16y -0x1000\\(%edx\\),%xmm6\n+\\s*[a-f0-9]+:\\s*c4 e2 7e 72 b2 00 f0 ff ff\\s+\\{vex\\} vcvtneps2bf16y -0x1000\\(%edx\\),%xmm6\n+\\s*[a-f0-9]+:\\s*c4 e2 7a b1 b4 f4 00 00 00 10\\s+vbcstnebf162ps 0x10000000\\(%esp,%esi,8\\),%xmm6\n+\\s*[a-f0-9]+:\\s*c4 e2 7a b1 31\\s+vbcstnebf162ps \\(%ecx\\),%xmm6\n+\\s*[a-f0-9]+:\\s*c4 e2 7a b1 b1 fe 00 00 00\\s+vbcstnebf162ps 0xfe\\(%ecx\\),%xmm6\n+\\s*[a-f0-9]+:\\s*c4 e2 7a b1 b2 00 ff ff ff\\s+vbcstnebf162ps -0x100\\(%edx\\),%xmm6\n+\\s*[a-f0-9]+:\\s*c4 e2 7e b1 b4 f4 00 00 00 10\\s+vbcstnebf162ps 0x10000000\\(%esp,%esi,8\\),%ymm6\n+\\s*[a-f0-9]+:\\s*c4 e2 7e b1 31\\s+vbcstnebf162ps \\(%ecx\\),%ymm6\n+\\s*[a-f0-9]+:\\s*c4 e2 7e b1 b1 fe 00 00 00\\s+vbcstnebf162ps 0xfe\\(%ecx\\),%ymm6\n+\\s*[a-f0-9]+:\\s*c4 e2 7e b1 b2 00 ff ff ff\\s+vbcstnebf162ps -0x100\\(%edx\\),%ymm6\n+\\s*[a-f0-9]+:\\s*c4 e2 79 b1 b4 f4 00 00 00 10\\s+vbcstnesh2ps 0x10000000\\(%esp,%esi,8\\),%xmm6\n+\\s*[a-f0-9]+:\\s*c4 e2 79 b1 31\\s+vbcstnesh2ps \\(%ecx\\),%xmm6\n+\\s*[a-f0-9]+:\\s*c4 e2 79 b1 b1 fe 00 00 00\\s+vbcstnesh2ps 0xfe\\(%ecx\\),%xmm6\n+\\s*[a-f0-9]+:\\s*c4 e2 79 b1 b2 00 ff ff ff\\s+vbcstnesh2ps -0x100\\(%edx\\),%xmm6\n+\\s*[a-f0-9]+:\\s*c4 e2 7d b1 b4 f4 00 00 00 10\\s+vbcstnesh2ps 0x10000000\\(%esp,%esi,8\\),%ymm6\n+\\s*[a-f0-9]+:\\s*c4 e2 7d b1 31\\s+vbcstnesh2ps \\(%ecx\\),%ymm6\n+\\s*[a-f0-9]+:\\s*c4 e2 7d b1 b1 fe 00 00 00\\s+vbcstnesh2ps 0xfe\\(%ecx\\),%ymm6\n+\\s*[a-f0-9]+:\\s*c4 e2 7d b1 b2 00 ff ff ff\\s+vbcstnesh2ps -0x100\\(%edx\\),%ymm6\n+\\s*[a-f0-9]+:\\s*c4 e2 7a b0 b4 f4 00 00 00 10\\s+vcvtneebf162ps 0x10000000\\(%esp,%esi,8\\),%xmm6\n+\\s*[a-f0-9]+:\\s*c4 e2 7a b0 31\\s+vcvtneebf162ps \\(%ecx\\),%xmm6\n+\\s*[a-f0-9]+:\\s*c4 e2 7a b0 b1 f0 07 00 00\\s+vcvtneebf162ps 0x7f0\\(%ecx\\),%xmm6\n+\\s*[a-f0-9]+:\\s*c4 e2 7a b0 b2 00 f8 ff ff\\s+vcvtneebf162ps -0x800\\(%edx\\),%xmm6\n+\\s*[a-f0-9]+:\\s*c4 e2 7e b0 b4 f4 00 00 00 10\\s+vcvtneebf162ps 0x10000000\\(%esp,%esi,8\\),%ymm6\n+\\s*[a-f0-9]+:\\s*c4 e2 7e b0 31\\s+vcvtneebf162ps \\(%ecx\\),%ymm6\n+\\s*[a-f0-9]+:\\s*c4 e2 7e b0 b1 e0 0f 00 00\\s+vcvtneebf162ps 0xfe0\\(%ecx\\),%ymm6\n+\\s*[a-f0-9]+:\\s*c4 e2 7e b0 b2 00 f0 ff ff\\s+vcvtneebf162ps -0x1000\\(%edx\\),%ymm6\n+\\s*[a-f0-9]+:\\s*c4 e2 79 b0 b4 f4 00 00 00 10\\s+vcvtneeph2ps 0x10000000\\(%esp,%esi,8\\),%xmm6\n+\\s*[a-f0-9]+:\\s*c4 e2 79 b0 31\\s+vcvtneeph2ps \\(%ecx\\),%xmm6\n+\\s*[a-f0-9]+:\\s*c4 e2 79 b0 b1 f0 07 00 00\\s+vcvtneeph2ps 0x7f0\\(%ecx\\),%xmm6\n+\\s*[a-f0-9]+:\\s*c4 e2 79 b0 b2 00 f8 ff ff\\s+vcvtneeph2ps -0x800\\(%edx\\),%xmm6\n+\\s*[a-f0-9]+:\\s*c4 e2 7d b0 b4 f4 00 00 00 10\\s+vcvtneeph2ps 0x10000000\\(%esp,%esi,8\\),%ymm6\n+\\s*[a-f0-9]+:\\s*c4 e2 7d b0 31\\s+vcvtneeph2ps \\(%ecx\\),%ymm6\n+\\s*[a-f0-9]+:\\s*c4 e2 7d b0 b1 e0 0f 00 00\\s+vcvtneeph2ps 0xfe0\\(%ecx\\),%ymm6\n+\\s*[a-f0-9]+:\\s*c4 e2 7d b0 b2 00 f0 ff ff\\s+vcvtneeph2ps -0x1000\\(%edx\\),%ymm6\n+\\s*[a-f0-9]+:\\s*c4 e2 7b b0 b4 f4 00 00 00 10\\s+vcvtneobf162ps 0x10000000\\(%esp,%esi,8\\),%xmm6\n+\\s*[a-f0-9]+:\\s*c4 e2 7b b0 31\\s+vcvtneobf162ps \\(%ecx\\),%xmm6\n+\\s*[a-f0-9]+:\\s*c4 e2 7b b0 b1 f0 07 00 00\\s+vcvtneobf162ps 0x7f0\\(%ecx\\),%xmm6\n+\\s*[a-f0-9]+:\\s*c4 e2 7b b0 b2 00 f8 ff ff\\s+vcvtneobf162ps -0x800\\(%edx\\),%xmm6\n+\\s*[a-f0-9]+:\\s*c4 e2 7f b0 b4 f4 00 00 00 10\\s+vcvtneobf162ps 0x10000000\\(%esp,%esi,8\\),%ymm6\n+\\s*[a-f0-9]+:\\s*c4 e2 7f b0 31\\s+vcvtneobf162ps \\(%ecx\\),%ymm6\n+\\s*[a-f0-9]+:\\s*c4 e2 7f b0 b1 e0 0f 00 00\\s+vcvtneobf162ps 0xfe0\\(%ecx\\),%ymm6\n+\\s*[a-f0-9]+:\\s*c4 e2 7f b0 b2 00 f0 ff ff\\s+vcvtneobf162ps -0x1000\\(%edx\\),%ymm6\n+\\s*[a-f0-9]+:\\s*c4 e2 78 b0 b4 f4 00 00 00 10\\s+vcvtneoph2ps 0x10000000\\(%esp,%esi,8\\),%xmm6\n+\\s*[a-f0-9]+:\\s*c4 e2 78 b0 31\\s+vcvtneoph2ps \\(%ecx\\),%xmm6\n+\\s*[a-f0-9]+:\\s*c4 e2 78 b0 b1 f0 07 00 00\\s+vcvtneoph2ps 0x7f0\\(%ecx\\),%xmm6\n+\\s*[a-f0-9]+:\\s*c4 e2 78 b0 b2 00 f8 ff ff\\s+vcvtneoph2ps -0x800\\(%edx\\),%xmm6\n+\\s*[a-f0-9]+:\\s*c4 e2 7c b0 b4 f4 00 00 00 10\\s+vcvtneoph2ps 0x10000000\\(%esp,%esi,8\\),%ymm6\n+\\s*[a-f0-9]+:\\s*c4 e2 7c b0 31\\s+vcvtneoph2ps \\(%ecx\\),%ymm6\n+\\s*[a-f0-9]+:\\s*c4 e2 7c b0 b1 e0 0f 00 00\\s+vcvtneoph2ps 0xfe0\\(%ecx\\),%ymm6\n+\\s*[a-f0-9]+:\\s*c4 e2 7c b0 b2 00 f0 ff ff\\s+vcvtneoph2ps -0x1000\\(%edx\\),%ymm6\n+\\s*[a-f0-9]+:\\s*62 f2 7e 08 72 f5\\s+vcvtneps2bf16 %xmm5,%xmm6\n+\\s*[a-f0-9]+:\\s*62 f2 7e 08 72 f5\\s+vcvtneps2bf16 %xmm5,%xmm6\n+\\s*[a-f0-9]+:\\s*c4 e2 7a 72 f5\\s+\\{vex\\} vcvtneps2bf16 %xmm5,%xmm6\n+\\s*[a-f0-9]+:\\s*c4 e2 7a 72 f5\\s+\\{vex\\} vcvtneps2bf16 %xmm5,%xmm6\n+\\s*[a-f0-9]+:\\s*62 f2 7e 28 72 f5\\s+vcvtneps2bf16 %ymm5,%xmm6\n+\\s*[a-f0-9]+:\\s*62 f2 7e 28 72 f5\\s+vcvtneps2bf16 %ymm5,%xmm6\n+\\s*[a-f0-9]+:\\s*c4 e2 7e 72 f5\\s+\\{vex\\} vcvtneps2bf16 %ymm5,%xmm6\n+\\s*[a-f0-9]+:\\s*c4 e2 7e 72 f5\\s+\\{vex\\} vcvtneps2bf16 %ymm5,%xmm6\n+\\s*[a-f0-9]+:\\s*62 f2 7e 08 72 b4 f4 00 00 00 10\\s+vcvtneps2bf16x 0x10000000\\(%esp,%esi,8\\),%xmm6\n+\\s*[a-f0-9]+:\\s*62 f2 7e 08 72 b4 f4 00 00 00 10\\s+vcvtneps2bf16x 0x10000000\\(%esp,%esi,8\\),%xmm6\n+\\s*[a-f0-9]+:\\s*c4 e2 7a 72 b4 f4 00 00 00 10\\s+\\{vex\\} vcvtneps2bf16x 0x10000000\\(%esp,%esi,8\\),%xmm6\n+\\s*[a-f0-9]+:\\s*c4 e2 7a 72 b4 f4 00 00 00 10\\s+\\{vex\\} vcvtneps2bf16x 0x10000000\\(%esp,%esi,8\\),%xmm6\n+\\s*[a-f0-9]+:\\s*62 f2 7e 08 72 31\\s+vcvtneps2bf16x \\(%ecx\\),%xmm6\n+\\s*[a-f0-9]+:\\s*62 f2 7e 08 72 31\\s+vcvtneps2bf16x \\(%ecx\\),%xmm6\n+\\s*[a-f0-9]+:\\s*c4 e2 7a 72 31\\s+\\{vex\\} vcvtneps2bf16x \\(%ecx\\),%xmm6\n+\\s*[a-f0-9]+:\\s*c4 e2 7a 72 31\\s+\\{vex\\} vcvtneps2bf16x \\(%ecx\\),%xmm6\n+\\s*[a-f0-9]+:\\s*62 f2 7e 08 72 71 7f\\s+vcvtneps2bf16x 0x7f0\\(%ecx\\),%xmm6\n+\\s*[a-f0-9]+:\\s*62 f2 7e 08 72 71 7f\\s+vcvtneps2bf16x 0x7f0\\(%ecx\\),%xmm6\n+\\s*[a-f0-9]+:\\s*c4 e2 7a 72 b1 f0 07 00 00\\s+\\{vex\\} vcvtneps2bf16x 0x7f0\\(%ecx\\),%xmm6\n+\\s*[a-f0-9]+:\\s*c4 e2 7a 72 b1 f0 07 00 00\\s+\\{vex\\} vcvtneps2bf16x 0x7f0\\(%ecx\\),%xmm6\n+\\s*[a-f0-9]+:\\s*62 f2 7e 08 72 72 80\\s+vcvtneps2bf16x -0x800\\(%edx\\),%xmm6\n+\\s*[a-f0-9]+:\\s*62 f2 7e 08 72 72 80\\s+vcvtneps2bf16x -0x800\\(%edx\\),%xmm6\n+\\s*[a-f0-9]+:\\s*c4 e2 7a 72 b2 00 f8 ff ff\\s+\\{vex\\} vcvtneps2bf16x -0x800\\(%edx\\),%xmm6\n+\\s*[a-f0-9]+:\\s*c4 e2 7a 72 b2 00 f8 ff ff\\s+\\{vex\\} vcvtneps2bf16x -0x800\\(%edx\\),%xmm6\n+\\s*[a-f0-9]+:\\s*62 f2 7e 28 72 71 7f\\s+vcvtneps2bf16y 0xfe0\\(%ecx\\),%xmm6\n+\\s*[a-f0-9]+:\\s*62 f2 7e 28 72 71 7f\\s+vcvtneps2bf16y 0xfe0\\(%ecx\\),%xmm6\n+\\s*[a-f0-9]+:\\s*c4 e2 7e 72 b1 e0 0f 00 00\\s+\\{vex\\} vcvtneps2bf16y 0xfe0\\(%ecx\\),%xmm6\n+\\s*[a-f0-9]+:\\s*c4 e2 7e 72 b1 e0 0f 00 00\\s+\\{vex\\} vcvtneps2bf16y 0xfe0\\(%ecx\\),%xmm6\n+\\s*[a-f0-9]+:\\s*62 f2 7e 28 72 72 80\\s+vcvtneps2bf16y -0x1000\\(%edx\\),%xmm6\n+\\s*[a-f0-9]+:\\s*62 f2 7e 28 72 72 80\\s+vcvtneps2bf16y -0x1000\\(%edx\\),%xmm6\n+\\s*[a-f0-9]+:\\s*c4 e2 7e 72 b2 00 f0 ff ff\\s+\\{vex\\} vcvtneps2bf16y -0x1000\\(%edx\\),%xmm6\n+\\s*[a-f0-9]+:\\s*c4 e2 7e 72 b2 00 f0 ff ff\\s+\\{vex\\} vcvtneps2bf16y -0x1000\\(%edx\\),%xmm6\ndiff --git a/gas/testsuite/gas/i386/avx-ne-convert.s b/gas/testsuite/gas/i386/avx-ne-convert.s\nnew file mode 100644\nindex 0000000000..7fb866630d\n--- /dev/null\n+++ b/gas/testsuite/gas/i386/avx-ne-convert.s\n@@ -0,0 +1,167 @@\n+# Check 32bit AVX-NE-CONVERT instructions\n+\n+\t.allow_index_reg\n+\t.text\n+_start:\n+\tvbcstnebf162ps\t0x10000000(%esp, %esi, 8), %xmm6\t #AVX-NE-CONVERT\n+\tvbcstnebf162ps\t(%ecx), %xmm6\t #AVX-NE-CONVERT\n+\tvbcstnebf162ps\t254(%ecx), %xmm6\t #AVX-NE-CONVERT Disp32(fe000000)\n+\tvbcstnebf162ps\t-256(%edx), %xmm6\t #AVX-NE-CONVERT Disp32(00ffffff)\n+\tvbcstnebf162ps\t0x10000000(%esp, %esi, 8), %ymm6\t #AVX-NE-CONVERT\n+\tvbcstnebf162ps\t(%ecx), %ymm6\t #AVX-NE-CONVERT\n+\tvbcstnebf162ps\t254(%ecx), %ymm6\t #AVX-NE-CONVERT Disp32(fe000000)\n+\tvbcstnebf162ps\t-256(%edx), %ymm6\t #AVX-NE-CONVERT Disp32(00ffffff)\n+\tvbcstnesh2ps\t0x10000000(%esp, %esi, 8), %xmm6\t #AVX-NE-CONVERT\n+\tvbcstnesh2ps\t(%ecx), %xmm6\t #AVX-NE-CONVERT\n+\tvbcstnesh2ps\t254(%ecx), %xmm6\t #AVX-NE-CONVERT Disp32(fe000000)\n+\tvbcstnesh2ps\t-256(%edx), %xmm6\t #AVX-NE-CONVERT Disp32(00ffffff)\n+\tvbcstnesh2ps\t0x10000000(%esp, %esi, 8), %ymm6\t #AVX-NE-CONVERT\n+\tvbcstnesh2ps\t(%ecx), %ymm6\t #AVX-NE-CONVERT\n+\tvbcstnesh2ps\t254(%ecx), %ymm6\t #AVX-NE-CONVERT Disp32(fe000000)\n+\tvbcstnesh2ps\t-256(%edx), %ymm6\t #AVX-NE-CONVERT Disp32(00ffffff)\n+\tvcvtneebf162ps\t0x10000000(%esp, %esi, 8), %xmm6\t #AVX-NE-CONVERT\n+\tvcvtneebf162ps\t(%ecx), %xmm6\t #AVX-NE-CONVERT\n+\tvcvtneebf162ps\t2032(%ecx), %xmm6\t #AVX-NE-CONVERT Disp32(f0070000)\n+\tvcvtneebf162ps\t-2048(%edx), %xmm6\t #AVX-NE-CONVERT Disp32(00f8ffff)\n+\tvcvtneebf162ps\t0x10000000(%esp, %esi, 8), %ymm6\t #AVX-NE-CONVERT\n+\tvcvtneebf162ps\t(%ecx), %ymm6\t #AVX-NE-CONVERT\n+\tvcvtneebf162ps\t4064(%ecx), %ymm6\t #AVX-NE-CONVERT Disp32(e00f0000)\n+\tvcvtneebf162ps\t-4096(%edx), %ymm6\t #AVX-NE-CONVERT Disp32(00f0ffff)\n+\tvcvtneeph2ps\t0x10000000(%esp, %esi, 8), %xmm6\t #AVX-NE-CONVERT\n+\tvcvtneeph2ps\t(%ecx), %xmm6\t #AVX-NE-CONVERT\n+\tvcvtneeph2ps\t2032(%ecx), %xmm6\t #AVX-NE-CONVERT Disp32(f0070000)\n+\tvcvtneeph2ps\t-2048(%edx), %xmm6\t #AVX-NE-CONVERT Disp32(00f8ffff)\n+\tvcvtneeph2ps\t0x10000000(%esp, %esi, 8), %ymm6\t #AVX-NE-CONVERT\n+\tvcvtneeph2ps\t(%ecx), %ymm6\t #AVX-NE-CONVERT\n+\tvcvtneeph2ps\t4064(%ecx), %ymm6\t #AVX-NE-CONVERT Disp32(e00f0000)\n+\tvcvtneeph2ps\t-4096(%edx), %ymm6\t #AVX-NE-CONVERT Disp32(00f0ffff)\n+\tvcvtneobf162ps\t0x10000000(%esp, %esi, 8), %xmm6\t #AVX-NE-CONVERT\n+\tvcvtneobf162ps\t(%ecx), %xmm6\t #AVX-NE-CONVERT\n+\tvcvtneobf162ps\t2032(%ecx), %xmm6\t #AVX-NE-CONVERT Disp32(f0070000)\n+\tvcvtneobf162ps\t-2048(%edx), %xmm6\t #AVX-NE-CONVERT Disp32(00f8ffff)\n+\tvcvtneobf162ps\t0x10000000(%esp, %esi, 8), %ymm6\t #AVX-NE-CONVERT\n+\tvcvtneobf162ps\t(%ecx), %ymm6\t #AVX-NE-CONVERT\n+\tvcvtneobf162ps\t4064(%ecx), %ymm6\t #AVX-NE-CONVERT Disp32(e00f0000)\n+\tvcvtneobf162ps\t-4096(%edx), %ymm6\t #AVX-NE-CONVERT Disp32(00f0ffff)\n+\tvcvtneoph2ps\t0x10000000(%esp, %esi, 8), %xmm6\t #AVX-NE-CONVERT\n+\tvcvtneoph2ps\t(%ecx), %xmm6\t #AVX-NE-CONVERT\n+\tvcvtneoph2ps\t2032(%ecx), %xmm6\t #AVX-NE-CONVERT Disp32(f0070000)\n+\tvcvtneoph2ps\t-2048(%edx), %xmm6\t #AVX-NE-CONVERT Disp32(00f8ffff)\n+\tvcvtneoph2ps\t0x10000000(%esp, %esi, 8), %ymm6\t #AVX-NE-CONVERT\n+\tvcvtneoph2ps\t(%ecx), %ymm6\t #AVX-NE-CONVERT\n+\tvcvtneoph2ps\t4064(%ecx), %ymm6\t #AVX-NE-CONVERT Disp32(e00f0000)\n+\tvcvtneoph2ps\t-4096(%edx), %ymm6\t #AVX-NE-CONVERT Disp32(00f0ffff)\n+\tvcvtneps2bf16\t%xmm5, %xmm6\t #AVX-NE-CONVERT\n+\t{evex} vcvtneps2bf16\t%xmm5, %xmm6\t #AVX-NE-CONVERT\n+\t{vex} vcvtneps2bf16\t%xmm5, %xmm6\t #AVX-NE-CONVERT\n+\t{vex3} vcvtneps2bf16\t%xmm5, %xmm6\t #AVX-NE-CONVERT\n+\tvcvtneps2bf16\t%ymm5, %xmm6\t #AVX-NE-CONVERT\n+\t{evex} vcvtneps2bf16\t%ymm5, %xmm6\t #AVX-NE-CONVERT\n+\t{vex} vcvtneps2bf16\t%ymm5, %xmm6\t #AVX-NE-CONVERT\n+\t{vex3} vcvtneps2bf16\t%ymm5, %xmm6\t #AVX-NE-CONVERT\n+\tvcvtneps2bf16x\t0x10000000(%esp, %esi, 8), %xmm6\t #AVX-NE-CONVERT\n+\t{evex} vcvtneps2bf16x\t0x10000000(%esp, %esi, 8), %xmm6\t #AVX-NE-CONVERT\n+\t{vex} vcvtneps2bf16x\t0x10000000(%esp, %esi, 8), %xmm6\t #AVX-NE-CONVERT\n+\t{vex3} vcvtneps2bf16x\t0x10000000(%esp, %esi, 8), %xmm6\t #AVX-NE-CONVERT\n+\tvcvtneps2bf16x\t(%ecx), %xmm6\t #AVX-NE-CONVERT\n+\t{evex} vcvtneps2bf16x\t(%ecx), %xmm6\t #AVX-NE-CONVERT\n+\t{vex} vcvtneps2bf16x\t(%ecx), %xmm6\t #AVX-NE-CONVERT\n+\t{vex3} vcvtneps2bf16x\t(%ecx), %xmm6\t #AVX-NE-CONVERT\n+\tvcvtneps2bf16x\t2032(%ecx), %xmm6\t #AVX-NE-CONVERT Disp32(f0070000)\n+\t{evex} vcvtneps2bf16x\t2032(%ecx), %xmm6\t #AVX-NE-CONVERT Disp32(f0070000)\n+\t{vex} vcvtneps2bf16x\t2032(%ecx), %xmm6\t #AVX-NE-CONVERT Disp32(f0070000)\n+\t{vex3} vcvtneps2bf16x\t2032(%ecx), %xmm6\t #AVX-NE-CONVERT Disp32(f0070000)\n+\tvcvtneps2bf16x\t-2048(%edx), %xmm6\t #AVX-NE-CONVERT Disp32(00f8ffff)\n+\t{evex} vcvtneps2bf16x\t-2048(%edx), %xmm6\t #AVX-NE-CONVERT Disp32(00f8ffff)\n+\t{vex} vcvtneps2bf16x\t-2048(%edx), %xmm6\t #AVX-NE-CONVERT Disp32(00f8ffff)\n+\t{vex3} vcvtneps2bf16x\t-2048(%edx), %xmm6\t #AVX-NE-CONVERT Disp32(00f8ffff)\n+\tvcvtneps2bf16y\t4064(%ecx), %xmm6\t #AVX-NE-CONVERT Disp32(e00f0000)\n+\t{evex} vcvtneps2bf16y\t4064(%ecx), %xmm6\t #AVX-NE-CONVERT Disp32(e00f0000)\n+\t{vex} vcvtneps2bf16y\t4064(%ecx), %xmm6\t #AVX-NE-CONVERT Disp32(e00f0000)\n+\t{vex3} vcvtneps2bf16y\t4064(%ecx), %xmm6\t #AVX-NE-CONVERT Disp32(e00f0000)\n+\tvcvtneps2bf16y\t-4096(%edx), %xmm6\t #AVX-NE-CONVERT Disp32(00f0ffff)\n+\t{evex} vcvtneps2bf16y\t-4096(%edx), %xmm6\t #AVX-NE-CONVERT Disp32(00f0ffff)\n+\t{vex} vcvtneps2bf16y\t-4096(%edx), %xmm6\t #AVX-NE-CONVERT Disp32(00f0ffff)\n+\t{vex3} vcvtneps2bf16y\t-4096(%edx), %xmm6\t #AVX-NE-CONVERT Disp32(00f0ffff)\n+\n+.intel_syntax noprefix\n+\tvbcstnebf162ps\txmm6, WORD PTR [esp+esi*8+0x10000000]\t #AVX-NE-CONVERT\n+\tvbcstnebf162ps\txmm6, WORD PTR [ecx]\t #AVX-NE-CONVERT\n+\tvbcstnebf162ps\txmm6, WORD PTR [ecx+254]\t #AVX-NE-CONVERT Disp32(fe000000)\n+\tvbcstnebf162ps\txmm6, WORD PTR [edx-256]\t #AVX-NE-CONVERT Disp32(00ffffff)\n+\tvbcstnebf162ps\tymm6, WORD PTR [esp+esi*8+0x10000000]\t #AVX-NE-CONVERT\n+\tvbcstnebf162ps\tymm6, WORD PTR [ecx]\t #AVX-NE-CONVERT\n+\tvbcstnebf162ps\tymm6, WORD PTR [ecx+254]\t #AVX-NE-CONVERT Disp32(fe000000)\n+\tvbcstnebf162ps\tymm6, WORD PTR [edx-256]\t #AVX-NE-CONVERT Disp32(00ffffff)\n+\tvbcstnesh2ps\txmm6, WORD PTR [esp+esi*8+0x10000000]\t #AVX-NE-CONVERT\n+\tvbcstnesh2ps\txmm6, WORD PTR [ecx]\t #AVX-NE-CONVERT\n+\tvbcstnesh2ps\txmm6, WORD PTR [ecx+254]\t #AVX-NE-CONVERT Disp32(fe000000)\n+\tvbcstnesh2ps\txmm6, WORD PTR [edx-256]\t #AVX-NE-CONVERT Disp32(00ffffff)\n+\tvbcstnesh2ps\tymm6, WORD PTR [esp+esi*8+0x10000000]\t #AVX-NE-CONVERT\n+\tvbcstnesh2ps\tymm6, WORD PTR [ecx]\t #AVX-NE-CONVERT\n+\tvbcstnesh2ps\tymm6, WORD PTR [ecx+254]\t #AVX-NE-CONVERT Disp32(fe000000)\n+\tvbcstnesh2ps\tymm6, WORD PTR [edx-256]\t #AVX-NE-CONVERT Disp32(00ffffff)\n+\tvcvtneebf162ps\txmm6, XMMWORD PTR [esp+esi*8+0x10000000]\t #AVX-NE-CONVERT\n+\tvcvtneebf162ps\txmm6, XMMWORD PTR [ecx]\t #AVX-NE-CONVERT\n+\tvcvtneebf162ps\txmm6, XMMWORD PTR [ecx+2032]\t #AVX-NE-CONVERT Disp32(f0070000)\n+\tvcvtneebf162ps\txmm6, XMMWORD PTR [edx-2048]\t #AVX-NE-CONVERT Disp32(00f8ffff)\n+\tvcvtneebf162ps\tymm6, YMMWORD PTR [esp+esi*8+0x10000000]\t #AVX-NE-CONVERT\n+\tvcvtneebf162ps\tymm6, YMMWORD PTR [ecx]\t #AVX-NE-CONVERT\n+\tvcvtneebf162ps\tymm6, YMMWORD PTR [ecx+4064]\t #AVX-NE-CONVERT Disp32(e00f0000)\n+\tvcvtneebf162ps\tymm6, YMMWORD PTR [edx-4096]\t #AVX-NE-CONVERT Disp32(00f0ffff)\n+\tvcvtneeph2ps\txmm6, XMMWORD PTR [esp+esi*8+0x10000000]\t #AVX-NE-CONVERT\n+\tvcvtneeph2ps\txmm6, XMMWORD PTR [ecx]\t #AVX-NE-CONVERT\n+\tvcvtneeph2ps\txmm6, XMMWORD PTR [ecx+2032]\t #AVX-NE-CONVERT Disp32(f0070000)\n+\tvcvtneeph2ps\txmm6, XMMWORD PTR [edx-2048]\t #AVX-NE-CONVERT Disp32(00f8ffff)\n+\tvcvtneeph2ps\tymm6, YMMWORD PTR [esp+esi*8+0x10000000]\t #AVX-NE-CONVERT\n+\tvcvtneeph2ps\tymm6, YMMWORD PTR [ecx]\t #AVX-NE-CONVERT\n+\tvcvtneeph2ps\tymm6, YMMWORD PTR [ecx+4064]\t #AVX-NE-CONVERT Disp32(e00f0000)\n+\tvcvtneeph2ps\tymm6, YMMWORD PTR [edx-4096]\t #AVX-NE-CONVERT Disp32(00f0ffff)\n+\tvcvtneobf162ps\txmm6, XMMWORD PTR [esp+esi*8+0x10000000]\t #AVX-NE-CONVERT\n+\tvcvtneobf162ps\txmm6, XMMWORD PTR [ecx]\t #AVX-NE-CONVERT\n+\tvcvtneobf162ps\txmm6, XMMWORD PTR [ecx+2032]\t #AVX-NE-CONVERT Disp32(f0070000)\n+\tvcvtneobf162ps\txmm6, XMMWORD PTR [edx-2048]\t #AVX-NE-CONVERT Disp32(00f8ffff)\n+\tvcvtneobf162ps\tymm6, YMMWORD PTR [esp+esi*8+0x10000000]\t #AVX-NE-CONVERT\n+\tvcvtneobf162ps\tymm6, YMMWORD PTR [ecx]\t #AVX-NE-CONVERT\n+\tvcvtneobf162ps\tymm6, YMMWORD PTR [ecx+4064]\t #AVX-NE-CONVERT Disp32(e00f0000)\n+\tvcvtneobf162ps\tymm6, YMMWORD PTR [edx-4096]\t #AVX-NE-CONVERT Disp32(00f0ffff)\n+\tvcvtneoph2ps\txmm6, XMMWORD PTR [esp+esi*8+0x10000000]\t #AVX-NE-CONVERT\n+\tvcvtneoph2ps\txmm6, XMMWORD PTR [ecx]\t #AVX-NE-CONVERT\n+\tvcvtneoph2ps\txmm6, XMMWORD PTR [ecx+2032]\t #AVX-NE-CONVERT Disp32(f0070000)\n+\tvcvtneoph2ps\txmm6, XMMWORD PTR [edx-2048]\t #AVX-NE-CONVERT Disp32(00f8ffff)\n+\tvcvtneoph2ps\tymm6, YMMWORD PTR [esp+esi*8+0x10000000]\t #AVX-NE-CONVERT\n+\tvcvtneoph2ps\tymm6, YMMWORD PTR [ecx]\t #AVX-NE-CONVERT\n+\tvcvtneoph2ps\tymm6, YMMWORD PTR [ecx+4064]\t #AVX-NE-CONVERT Disp32(e00f0000)\n+\tvcvtneoph2ps\tymm6, YMMWORD PTR [edx-4096]\t #AVX-NE-CONVERT Disp32(00f0ffff)\n+\tvcvtneps2bf16\txmm6, xmm5\t #AVX-NE-CONVERT\n+\t{evex} vcvtneps2bf16\txmm6, xmm5\t #AVX-NE-CONVERT\n+\t{vex} vcvtneps2bf16\txmm6, xmm5\t #AVX-NE-CONVERT\n+\t{vex3} vcvtneps2bf16\txmm6, xmm5\t #AVX-NE-CONVERT\n+\tvcvtneps2bf16\txmm6, ymm5\t #AVX-NE-CONVERT\n+\t{evex} vcvtneps2bf16\txmm6, ymm5\t #AVX-NE-CONVERT\n+\t{vex} vcvtneps2bf16\txmm6, ymm5\t #AVX-NE-CONVERT\n+\t{vex3} vcvtneps2bf16\txmm6, ymm5\t #AVX-NE-CONVERT\n+\tvcvtneps2bf16\txmm6, XMMWORD PTR [esp+esi*8+0x10000000]\t #AVX-NE-CONVERT\n+\t{evex} vcvtneps2bf16\txmm6, XMMWORD PTR [esp+esi*8+0x10000000]\t #AVX-NE-CONVERT\n+\t{vex} vcvtneps2bf16\txmm6, XMMWORD PTR [esp+esi*8+0x10000000]\t #AVX-NE-CONVERT\n+\t{vex3} vcvtneps2bf16\txmm6, XMMWORD PTR [esp+esi*8+0x10000000]\t #AVX-NE-CONVERT\n+\tvcvtneps2bf16\txmm6, XMMWORD PTR [ecx]\t #AVX-NE-CONVERT\n+\t{evex} vcvtneps2bf16\txmm6, XMMWORD PTR [ecx]\t #AVX-NE-CONVERT\n+\t{vex} vcvtneps2bf16\txmm6, XMMWORD PTR [ecx]\t #AVX-NE-CONVERT\n+\t{vex3} vcvtneps2bf16\txmm6, XMMWORD PTR [ecx]\t #AVX-NE-CONVERT\n+\tvcvtneps2bf16\txmm6, XMMWORD PTR [ecx+2032]\t #AVX-NE-CONVERT Disp32(f0070000)\n+\t{evex} vcvtneps2bf16\txmm6, XMMWORD PTR [ecx+2032]\t #AVX-NE-CONVERT Disp32(f0070000)\n+\t{vex} vcvtneps2bf16\txmm6, XMMWORD PTR [ecx+2032]\t #AVX-NE-CONVERT Disp32(f0070000)\n+\t{vex3} vcvtneps2bf16\txmm6, XMMWORD PTR [ecx+2032]\t #AVX-NE-CONVERT Disp32(f0070000)\n+\tvcvtneps2bf16\txmm6, XMMWORD PTR [edx-2048]\t #AVX-NE-CONVERT Disp32(00f8ffff)\n+\t{evex} vcvtneps2bf16\txmm6, XMMWORD PTR [edx-2048]\t #AVX-NE-CONVERT Disp32(00f8ffff)\n+\t{vex} vcvtneps2bf16\txmm6, XMMWORD PTR [edx-2048]\t #AVX-NE-CONVERT Disp32(00f8ffff)\n+\t{vex3} vcvtneps2bf16\txmm6, XMMWORD PTR [edx-2048]\t #AVX-NE-CONVERT Disp32(00f8ffff)\n+\tvcvtneps2bf16\txmm6, YMMWORD PTR [ecx+4064]\t #AVX-NE-CONVERT Disp32(e00f0000)\n+\t{evex} vcvtneps2bf16\txmm6, YMMWORD PTR [ecx+4064]\t #AVX-NE-CONVERT Disp32(e00f0000)\n+\t{vex} vcvtneps2bf16\txmm6, YMMWORD PTR [ecx+4064]\t #AVX-NE-CONVERT Disp32(e00f0000)\n+\t{vex3} vcvtneps2bf16\txmm6, YMMWORD PTR [ecx+4064]\t #AVX-NE-CONVERT Disp32(e00f0000)\n+\tvcvtneps2bf16\txmm6, YMMWORD PTR [edx-4096]\t #AVX-NE-CONVERT Disp32(00f0ffff)\n+\t{evex} vcvtneps2bf16\txmm6, YMMWORD PTR [edx-4096]\t #AVX-NE-CONVERT Disp32(00f0ffff)\n+\t{vex} vcvtneps2bf16\txmm6, YMMWORD PTR [edx-4096]\t #AVX-NE-CONVERT Disp32(00f0ffff)\n+\t{vex3} vcvtneps2bf16\txmm6, YMMWORD PTR [edx-4096]\t #AVX-NE-CONVERT Disp32(00f0ffff)\ndiff --git a/gas/testsuite/gas/i386/i386.exp b/gas/testsuite/gas/i386/i386.exp\nindex 9eaadd131d..cbaec1ad14 100644\n--- a/gas/testsuite/gas/i386/i386.exp\n+++ b/gas/testsuite/gas/i386/i386.exp\n@@ -483,6 +483,8 @@ if [gas_32_check] then {\n run_dump_test \"wrmsrns\"\n run_dump_test \"wrmsrns-intel\"\n run_list_test \"msrlist-inval\"\n+ run_dump_test \"avx-ne-convert\"\n+ run_dump_test \"avx-ne-convert-intel\"\n run_list_test \"sg\"\n run_dump_test \"clzero\"\n run_dump_test \"invlpgb\"\n@@ -1162,6 +1164,8 @@ if [gas_64_check] then {\n run_dump_test \"x86-64-wrmsrns-intel\"\n run_dump_test \"x86-64-msrlist\"\n run_dump_test \"x86-64-msrlist-intel\"\n+ run_dump_test \"x86-64-avx-ne-convert\"\n+ run_dump_test \"x86-64-avx-ne-convert-intel\"\n run_dump_test \"x86-64-clzero\"\n run_dump_test \"x86-64-mwaitx-bdver4\"\n run_list_test \"x86-64-mwaitx-reg\"\ndiff --git a/gas/testsuite/gas/i386/x86-64-avx-ne-convert-intel.d b/gas/testsuite/gas/i386/x86-64-avx-ne-convert-intel.d\nnew file mode 100644\nindex 0000000000..96ec69a12c\n--- /dev/null\n+++ b/gas/testsuite/gas/i386/x86-64-avx-ne-convert-intel.d\n@@ -0,0 +1,170 @@\n+#as:\n+#objdump: -dw -Mintel\n+#name: x86_64 AVX-NE-CONVERT insns (Intel disassembly)\n+#source: x86-64-avx-ne-convert.s\n+\n+.*: +file format .*\n+\n+Disassembly of section \\.text:\n+\n+0+ <_start>:\n+\\s*[a-f0-9]+:\\s*c4 a2 7a b1 b4 f5 00 00 00 10\\s+vbcstnebf162ps xmm6,WORD PTR \\[rbp\\+r14\\*8\\+0x10000000\\]\n+\\s*[a-f0-9]+:\\s*c4 c2 7a b1 31\\s+vbcstnebf162ps xmm6,WORD PTR \\[r9\\]\n+\\s*[a-f0-9]+:\\s*c4 e2 7a b1 b1 fe 00 00 00\\s+vbcstnebf162ps xmm6,WORD PTR \\[rcx\\+0xfe\\]\n+\\s*[a-f0-9]+:\\s*c4 e2 7a b1 b2 00 ff ff ff\\s+vbcstnebf162ps xmm6,WORD PTR \\[rdx-0x100\\]\n+\\s*[a-f0-9]+:\\s*c4 a2 7e b1 b4 f5 00 00 00 10\\s+vbcstnebf162ps ymm6,WORD PTR \\[rbp\\+r14\\*8\\+0x10000000\\]\n+\\s*[a-f0-9]+:\\s*c4 c2 7e b1 31\\s+vbcstnebf162ps ymm6,WORD PTR \\[r9\\]\n+\\s*[a-f0-9]+:\\s*c4 e2 7e b1 b1 fe 00 00 00\\s+vbcstnebf162ps ymm6,WORD PTR \\[rcx\\+0xfe\\]\n+\\s*[a-f0-9]+:\\s*c4 e2 7e b1 b2 00 ff ff ff\\s+vbcstnebf162ps ymm6,WORD PTR \\[rdx-0x100\\]\n+\\s*[a-f0-9]+:\\s*c4 a2 79 b1 b4 f5 00 00 00 10\\s+vbcstnesh2ps xmm6,WORD PTR \\[rbp\\+r14\\*8\\+0x10000000\\]\n+\\s*[a-f0-9]+:\\s*c4 c2 79 b1 31\\s+vbcstnesh2ps xmm6,WORD PTR \\[r9\\]\n+\\s*[a-f0-9]+:\\s*c4 e2 79 b1 b1 fe 00 00 00\\s+vbcstnesh2ps xmm6,WORD PTR \\[rcx\\+0xfe\\]\n+\\s*[a-f0-9]+:\\s*c4 e2 79 b1 b2 00 ff ff ff\\s+vbcstnesh2ps xmm6,WORD PTR \\[rdx-0x100\\]\n+\\s*[a-f0-9]+:\\s*c4 a2 7d b1 b4 f5 00 00 00 10\\s+vbcstnesh2ps ymm6,WORD PTR \\[rbp\\+r14\\*8\\+0x10000000\\]\n+\\s*[a-f0-9]+:\\s*c4 c2 7d b1 31\\s+vbcstnesh2ps ymm6,WORD PTR \\[r9\\]\n+\\s*[a-f0-9]+:\\s*c4 e2 7d b1 b1 fe 00 00 00\\s+vbcstnesh2ps ymm6,WORD PTR \\[rcx\\+0xfe\\]\n+\\s*[a-f0-9]+:\\s*c4 e2 7d b1 b2 00 ff ff ff\\s+vbcstnesh2ps ymm6,WORD PTR \\[rdx-0x100\\]\n+\\s*[a-f0-9]+:\\s*c4 a2 7a b0 b4 f5 00 00 00 10\\s+vcvtneebf162ps xmm6,XMMWORD PTR \\[rbp\\+r14\\*8\\+0x10000000\\]\n+\\s*[a-f0-9]+:\\s*c4 c2 7a b0 31\\s+vcvtneebf162ps xmm6,XMMWORD PTR \\[r9\\]\n+\\s*[a-f0-9]+:\\s*c4 e2 7a b0 b1 f0 07 00 00\\s+vcvtneebf162ps xmm6,XMMWORD PTR \\[rcx\\+0x7f0\\]\n+\\s*[a-f0-9]+:\\s*c4 e2 7a b0 b2 00 f8 ff ff\\s+vcvtneebf162ps xmm6,XMMWORD PTR \\[rdx-0x800\\]\n+\\s*[a-f0-9]+:\\s*c4 a2 7e b0 b4 f5 00 00 00 10\\s+vcvtneebf162ps ymm6,YMMWORD PTR \\[rbp\\+r14\\*8\\+0x10000000\\]\n+\\s*[a-f0-9]+:\\s*c4 c2 7e b0 31\\s+vcvtneebf162ps ymm6,YMMWORD PTR \\[r9\\]\n+\\s*[a-f0-9]+:\\s*c4 e2 7e b0 b1 e0 0f 00 00\\s+vcvtneebf162ps ymm6,YMMWORD PTR \\[rcx\\+0xfe0\\]\n+\\s*[a-f0-9]+:\\s*c4 e2 7e b0 b2 00 f0 ff ff\\s+vcvtneebf162ps ymm6,YMMWORD PTR \\[rdx-0x1000\\]\n+\\s*[a-f0-9]+:\\s*c4 a2 79 b0 b4 f5 00 00 00 10\\s+vcvtneeph2ps xmm6,XMMWORD PTR \\[rbp\\+r14\\*8\\+0x10000000\\]\n+\\s*[a-f0-9]+:\\s*c4 c2 79 b0 31\\s+vcvtneeph2ps xmm6,XMMWORD PTR \\[r9\\]\n+\\s*[a-f0-9]+:\\s*c4 e2 79 b0 b1 f0 07 00 00\\s+vcvtneeph2ps xmm6,XMMWORD PTR \\[rcx\\+0x7f0\\]\n+\\s*[a-f0-9]+:\\s*c4 e2 79 b0 b2 00 f8 ff ff\\s+vcvtneeph2ps xmm6,XMMWORD PTR \\[rdx-0x800\\]\n+\\s*[a-f0-9]+:\\s*c4 a2 7d b0 b4 f5 00 00 00 10\\s+vcvtneeph2ps ymm6,YMMWORD PTR \\[rbp\\+r14\\*8\\+0x10000000\\]\n+\\s*[a-f0-9]+:\\s*c4 c2 7d b0 31\\s+vcvtneeph2ps ymm6,YMMWORD PTR \\[r9\\]\n+\\s*[a-f0-9]+:\\s*c4 e2 7d b0 b1 e0 0f 00 00\\s+vcvtneeph2ps ymm6,YMMWORD PTR \\[rcx\\+0xfe0\\]\n+\\s*[a-f0-9]+:\\s*c4 e2 7d b0 b2 00 f0 ff ff\\s+vcvtneeph2ps ymm6,YMMWORD PTR \\[rdx-0x1000\\]\n+\\s*[a-f0-9]+:\\s*c4 a2 7b b0 b4 f5 00 00 00 10\\s+vcvtneobf162ps xmm6,XMMWORD PTR \\[rbp\\+r14\\*8\\+0x10000000\\]\n+\\s*[a-f0-9]+:\\s*c4 c2 7b b0 31\\s+vcvtneobf162ps xmm6,XMMWORD PTR \\[r9\\]\n+\\s*[a-f0-9]+:\\s*c4 e2 7b b0 b1 f0 07 00 00\\s+vcvtneobf162ps xmm6,XMMWORD PTR \\[rcx\\+0x7f0\\]\n+\\s*[a-f0-9]+:\\s*c4 e2 7b b0 b2 00 f8 ff ff\\s+vcvtneobf162ps xmm6,XMMWORD PTR \\[rdx-0x800\\]\n+\\s*[a-f0-9]+:\\s*c4 a2 7f b0 b4 f5 00 00 00 10\\s+vcvtneobf162ps ymm6,YMMWORD PTR \\[rbp\\+r14\\*8\\+0x10000000\\]\n+\\s*[a-f0-9]+:\\s*c4 c2 7f b0 31\\s+vcvtneobf162ps ymm6,YMMWORD PTR \\[r9\\]\n+\\s*[a-f0-9]+:\\s*c4 e2 7f b0 b1 e0 0f 00 00\\s+vcvtneobf162ps ymm6,YMMWORD PTR \\[rcx\\+0xfe0\\]\n+\\s*[a-f0-9]+:\\s*c4 e2 7f b0 b2 00 f0 ff ff\\s+vcvtneobf162ps ymm6,YMMWORD PTR \\[rdx-0x1000\\]\n+\\s*[a-f0-9]+:\\s*c4 a2 78 b0 b4 f5 00 00 00 10\\s+vcvtneoph2ps xmm6,XMMWORD PTR \\[rbp\\+r14\\*8\\+0x10000000\\]\n+\\s*[a-f0-9]+:\\s*c4 c2 78 b0 31\\s+vcvtneoph2ps xmm6,XMMWORD PTR \\[r9\\]\n+\\s*[a-f0-9]+:\\s*c4 e2 78 b0 b1 f0 07 00 00\\s+vcvtneoph2ps xmm6,XMMWORD PTR \\[rcx\\+0x7f0\\]\n+\\s*[a-f0-9]+:\\s*c4 e2 78 b0 b2 00 f8 ff ff\\s+vcvtneoph2ps xmm6,XMMWORD PTR \\[rdx-0x800\\]\n+\\s*[a-f0-9]+:\\s*c4 a2 7c b0 b4 f5 00 00 00 10\\s+vcvtneoph2ps ymm6,YMMWORD PTR \\[rbp\\+r14\\*8\\+0x10000000\\]\n+\\s*[a-f0-9]+:\\s*c4 c2 7c b0 31\\s+vcvtneoph2ps ymm6,YMMWORD PTR \\[r9\\]\n+\\s*[a-f0-9]+:\\s*c4 e2 7c b0 b1 e0 0f 00 00\\s+vcvtneoph2ps ymm6,YMMWORD PTR \\[rcx\\+0xfe0\\]\n+\\s*[a-f0-9]+:\\s*c4 e2 7c b0 b2 00 f0 ff ff\\s+vcvtneoph2ps ymm6,YMMWORD PTR \\[rdx-0x1000\\]\n+\\s*[a-f0-9]+:\\s*62 f2 7e 08 72 f5\\s+vcvtneps2bf16 xmm6,xmm5\n+\\s*[a-f0-9]+:\\s*62 f2 7e 08 72 f5\\s+vcvtneps2bf16 xmm6,xmm5\n+\\s*[a-f0-9]+:\\s*c4 e2 7a 72 f5\\s+\\{vex\\} vcvtneps2bf16 xmm6,xmm5\n+\\s*[a-f0-9]+:\\s*c4 e2 7a 72 f5\\s+\\{vex\\} vcvtneps2bf16 xmm6,xmm5\n+\\s*[a-f0-9]+:\\s*62 f2 7e 28 72 f5\\s+vcvtneps2bf16 xmm6,ymm5\n+\\s*[a-f0-9]+:\\s*62 f2 7e 28 72 f5\\s+vcvtneps2bf16 xmm6,ymm5\n+\\s*[a-f0-9]+:\\s*c4 e2 7e 72 f5\\s+\\{vex\\} vcvtneps2bf16 xmm6,ymm5\n+\\s*[a-f0-9]+:\\s*c4 e2 7e 72 f5\\s+\\{vex\\} vcvtneps2bf16 xmm6,ymm5\n+\\s*[a-f0-9]+:\\s*62 b2 7e 08 72 b4 f5 00 00 00 10\\s+vcvtneps2bf16 xmm6,XMMWORD PTR \\[rbp\\+r14\\*8\\+0x10000000\\]\n+\\s*[a-f0-9]+:\\s*62 b2 7e 08 72 b4 f5 00 00 00 10\\s+vcvtneps2bf16 xmm6,XMMWORD PTR \\[rbp\\+r14\\*8\\+0x10000000\\]\n+\\s*[a-f0-9]+:\\s*c4 a2 7a 72 b4 f5 00 00 00 10\\s+\\{vex\\} vcvtneps2bf16 xmm6,XMMWORD PTR \\[rbp\\+r14\\*8\\+0x10000000\\]\n+\\s*[a-f0-9]+:\\s*c4 a2 7a 72 b4 f5 00 00 00 10\\s+\\{vex\\} vcvtneps2bf16 xmm6,XMMWORD PTR \\[rbp\\+r14\\*8\\+0x10000000\\]\n+\\s*[a-f0-9]+:\\s*62 d2 7e 08 72 31\\s+vcvtneps2bf16 xmm6,XMMWORD PTR \\[r9\\]\n+\\s*[a-f0-9]+:\\s*62 d2 7e 08 72 31\\s+vcvtneps2bf16 xmm6,XMMWORD PTR \\[r9\\]\n+\\s*[a-f0-9]+:\\s*c4 c2 7a 72 31\\s+\\{vex\\} vcvtneps2bf16 xmm6,XMMWORD PTR \\[r9\\]\n+\\s*[a-f0-9]+:\\s*c4 c2 7a 72 31\\s+\\{vex\\} vcvtneps2bf16 xmm6,XMMWORD PTR \\[r9\\]\n+\\s*[a-f0-9]+:\\s*62 f2 7e 08 72 71 7f\\s+vcvtneps2bf16 xmm6,XMMWORD PTR \\[rcx\\+0x7f0\\]\n+\\s*[a-f0-9]+:\\s*62 f2 7e 08 72 71 7f\\s+vcvtneps2bf16 xmm6,XMMWORD PTR \\[rcx\\+0x7f0\\]\n+\\s*[a-f0-9]+:\\s*c4 e2 7a 72 b1 f0 07 00 00\\s+\\{vex\\} vcvtneps2bf16 xmm6,XMMWORD PTR \\[rcx\\+0x7f0\\]\n+\\s*[a-f0-9]+:\\s*c4 e2 7a 72 b1 f0 07 00 00\\s+\\{vex\\} vcvtneps2bf16 xmm6,XMMWORD PTR \\[rcx\\+0x7f0\\]\n+\\s*[a-f0-9]+:\\s*62 f2 7e 08 72 72 80\\s+vcvtneps2bf16 xmm6,XMMWORD PTR \\[rdx-0x800\\]\n+\\s*[a-f0-9]+:\\s*62 f2 7e 08 72 72 80\\s+vcvtneps2bf16 xmm6,XMMWORD PTR \\[rdx-0x800\\]\n+\\s*[a-f0-9]+:\\s*c4 e2 7a 72 b2 00 f8 ff ff\\s+\\{vex\\} vcvtneps2bf16 xmm6,XMMWORD PTR \\[rdx-0x800\\]\n+\\s*[a-f0-9]+:\\s*c4 e2 7a 72 b2 00 f8 ff ff\\s+\\{vex\\} vcvtneps2bf16 xmm6,XMMWORD PTR \\[rdx-0x800\\]\n+\\s*[a-f0-9]+:\\s*62 f2 7e 28 72 71 7f\\s+vcvtneps2bf16 xmm6,YMMWORD PTR \\[rcx\\+0xfe0\\]\n+\\s*[a-f0-9]+:\\s*62 f2 7e 28 72 71 7f\\s+vcvtneps2bf16 xmm6,YMMWORD PTR \\[rcx\\+0xfe0\\]\n+\\s*[a-f0-9]+:\\s*c4 e2 7e 72 b1 e0 0f 00 00\\s+\\{vex\\} vcvtneps2bf16 xmm6,YMMWORD PTR \\[rcx\\+0xfe0\\]\n+\\s*[a-f0-9]+:\\s*c4 e2 7e 72 b1 e0 0f 00 00\\s+\\{vex\\} vcvtneps2bf16 xmm6,YMMWORD PTR \\[rcx\\+0xfe0\\]\n+\\s*[a-f0-9]+:\\s*62 f2 7e 28 72 72 80\\s+vcvtneps2bf16 xmm6,YMMWORD PTR \\[rdx-0x1000\\]\n+\\s*[a-f0-9]+:\\s*62 f2 7e 28 72 72 80\\s+vcvtneps2bf16 xmm6,YMMWORD PTR \\[rdx-0x1000\\]\n+\\s*[a-f0-9]+:\\s*c4 e2 7e 72 b2 00 f0 ff ff\\s+\\{vex\\} vcvtneps2bf16 xmm6,YMMWORD PTR \\[rdx-0x1000\\]\n+\\s*[a-f0-9]+:\\s*c4 e2 7e 72 b2 00 f0 ff ff\\s+\\{vex\\} vcvtneps2bf16 xmm6,YMMWORD PTR \\[rdx-0x1000\\]\n+\\s*[a-f0-9]+:\\s*c4 a2 7a b1 b4 f5 00 00 00 10\\s+vbcstnebf162ps xmm6,WORD PTR \\[rbp\\+r14\\*8\\+0x10000000\\]\n+\\s*[a-f0-9]+:\\s*c4 c2 7a b1 31\\s+vbcstnebf162ps xmm6,WORD PTR \\[r9\\]\n+\\s*[a-f0-9]+:\\s*c4 e2 7a b1 b1 fe 00 00 00\\s+vbcstnebf162ps xmm6,WORD PTR \\[rcx\\+0xfe\\]\n+\\s*[a-f0-9]+:\\s*c4 e2 7a b1 b2 00 ff ff ff\\s+vbcstnebf162ps xmm6,WORD PTR \\[rdx-0x100\\]\n+\\s*[a-f0-9]+:\\s*c4 a2 7e b1 b4 f5 00 00 00 10\\s+vbcstnebf162ps ymm6,WORD PTR \\[rbp\\+r14\\*8\\+0x10000000\\]\n+\\s*[a-f0-9]+:\\s*c4 c2 7e b1 31\\s+vbcstnebf162ps ymm6,WORD PTR \\[r9\\]\n+\\s*[a-f0-9]+:\\s*c4 e2 7e b1 b1 fe 00 00 00\\s+vbcstnebf162ps ymm6,WORD PTR \\[rcx\\+0xfe\\]\n+\\s*[a-f0-9]+:\\s*c4 e2 7e b1 b2 00 ff ff ff\\s+vbcstnebf162ps ymm6,WORD PTR \\[rdx-0x100\\]\n+\\s*[a-f0-9]+:\\s*c4 a2 79 b1 b4 f5 00 00 00 10\\s+vbcstnesh2ps xmm6,WORD PTR \\[rbp\\+r14\\*8\\+0x10000000\\]\n+\\s*[a-f0-9]+:\\s*c4 c2 79 b1 31\\s+vbcstnesh2ps xmm6,WORD PTR \\[r9\\]\n+\\s*[a-f0-9]+:\\s*c4 e2 79 b1 b1 fe 00 00 00\\s+vbcstnesh2ps xmm6,WORD PTR \\[rcx\\+0xfe\\]\n+\\s*[a-f0-9]+:\\s*c4 e2 79 b1 b2 00 ff ff ff\\s+vbcstnesh2ps xmm6,WORD PTR \\[rdx-0x100\\]\n+\\s*[a-f0-9]+:\\s*c4 a2 7d b1 b4 f5 00 00 00 10\\s+vbcstnesh2ps ymm6,WORD PTR \\[rbp\\+r14\\*8\\+0x10000000\\]\n+\\s*[a-f0-9]+:\\s*c4 c2 7d b1 31\\s+vbcstnesh2ps ymm6,WORD PTR \\[r9\\]\n+\\s*[a-f0-9]+:\\s*c4 e2 7d b1 b1 fe 00 00 00\\s+vbcstnesh2ps ymm6,WORD PTR \\[rcx\\+0xfe\\]\n+\\s*[a-f0-9]+:\\s*c4 e2 7d b1 b2 00 ff ff ff\\s+vbcstnesh2ps ymm6,WORD PTR \\[rdx-0x100\\]\n+\\s*[a-f0-9]+:\\s*c4 a2 7a b0 b4 f5 00 00 00 10\\s+vcvtneebf162ps xmm6,XMMWORD PTR \\[rbp\\+r14\\*8\\+0x10000000\\]\n+\\s*[a-f0-9]+:\\s*c4 c2 7a b0 31\\s+vcvtneebf162ps xmm6,XMMWORD PTR \\[r9\\]\n+\\s*[a-f0-9]+:\\s*c4 e2 7a b0 b1 f0 07 00 00\\s+vcvtneebf162ps xmm6,XMMWORD PTR \\[rcx\\+0x7f0\\]\n+\\s*[a-f0-9]+:\\s*c4 e2 7a b0 b2 00 f8 ff ff\\s+vcvtneebf162ps xmm6,XMMWORD PTR \\[rdx-0x800\\]\n+\\s*[a-f0-9]+:\\s*c4 a2 7e b0 b4 f5 00 00 00 10\\s+vcvtneebf162ps ymm6,YMMWORD PTR \\[rbp\\+r14\\*8\\+0x10000000\\]\n+\\s*[a-f0-9]+:\\s*c4 c2 7e b0 31\\s+vcvtneebf162ps ymm6,YMMWORD PTR \\[r9\\]\n+\\s*[a-f0-9]+:\\s*c4 e2 7e b0 b1 e0 0f 00 00\\s+vcvtneebf162ps ymm6,YMMWORD PTR \\[rcx\\+0xfe0\\]\n+\\s*[a-f0-9]+:\\s*c4 e2 7e b0 b2 00 f0 ff ff\\s+vcvtneebf162ps ymm6,YMMWORD PTR \\[rdx-0x1000\\]\n+\\s*[a-f0-9]+:\\s*c4 a2 79 b0 b4 f5 00 00 00 10\\s+vcvtneeph2ps xmm6,XMMWORD PTR \\[rbp\\+r14\\*8\\+0x10000000\\]\n+\\s*[a-f0-9]+:\\s*c4 c2 79 b0 31\\s+vcvtneeph2ps xmm6,XMMWORD PTR \\[r9\\]\n+\\s*[a-f0-9]+:\\s*c4 e2 79 b0 b1 f0 07 00 00\\s+vcvtneeph2ps xmm6,XMMWORD PTR \\[rcx\\+0x7f0\\]\n+\\s*[a-f0-9]+:\\s*c4 e2 79 b0 b2 00 f8 ff ff\\s+vcvtneeph2ps xmm6,XMMWORD PTR \\[rdx-0x800\\]\n+\\s*[a-f0-9]+:\\s*c4 a2 7d b0 b4 f5 00 00 00 10\\s+vcvtneeph2ps ymm6,YMMWORD PTR \\[rbp\\+r14\\*8\\+0x10000000\\]\n+\\s*[a-f0-9]+:\\s*c4 c2 7d b0 31\\s+vcvtneeph2ps ymm6,YMMWORD PTR \\[r9\\]\n+\\s*[a-f0-9]+:\\s*c4 e2 7d b0 b1 e0 0f 00 00\\s+vcvtneeph2ps ymm6,YMMWORD PTR \\[rcx\\+0xfe0\\]\n+\\s*[a-f0-9]+:\\s*c4 e2 7d b0 b2 00 f0 ff ff\\s+vcvtneeph2ps ymm6,YMMWORD PTR \\[rdx-0x1000\\]\n+\\s*[a-f0-9]+:\\s*c4 a2 7b b0 b4 f5 00 00 00 10\\s+vcvtneobf162ps xmm6,XMMWORD PTR \\[rbp\\+r14\\*8\\+0x10000000\\]\n+\\s*[a-f0-9]+:\\s*c4 c2 7b b0 31\\s+vcvtneobf162ps xmm6,XMMWORD PTR \\[r9\\]\n+\\s*[a-f0-9]+:\\s*c4 e2 7b b0 b1 f0 07 00 00\\s+vcvtneobf162ps xmm6,XMMWORD PTR \\[rcx\\+0x7f0\\]\n+\\s*[a-f0-9]+:\\s*c4 e2 7b b0 b2 00 f8 ff ff\\s+vcvtneobf162ps xmm6,XMMWORD PTR \\[rdx-0x800\\]\n+\\s*[a-f0-9]+:\\s*c4 a2 7f b0 b4 f5 00 00 00 10\\s+vcvtneobf162ps ymm6,YMMWORD PTR \\[rbp\\+r14\\*8\\+0x10000000\\]\n+\\s*[a-f0-9]+:\\s*c4 c2 7f b0 31\\s+vcvtneobf162ps ymm6,YMMWORD PTR \\[r9\\]\n+\\s*[a-f0-9]+:\\s*c4 e2 7f b0 b1 e0 0f 00 00\\s+vcvtneobf162ps ymm6,YMMWORD PTR \\[rcx\\+0xfe0\\]\n+\\s*[a-f0-9]+:\\s*c4 e2 7f b0 b2 00 f0 ff ff\\s+vcvtneobf162ps ymm6,YMMWORD PTR \\[rdx-0x1000\\]\n+\\s*[a-f0-9]+:\\s*c4 a2 78 b0 b4 f5 00 00 00 10\\s+vcvtneoph2ps xmm6,XMMWORD PTR \\[rbp\\+r14\\*8\\+0x10000000\\]\n+\\s*[a-f0-9]+:\\s*c4 c2 78 b0 31\\s+vcvtneoph2ps xmm6,XMMWORD PTR \\[r9\\]\n+\\s*[a-f0-9]+:\\s*c4 e2 78 b0 b1 f0 07 00 00\\s+vcvtneoph2ps xmm6,XMMWORD PTR \\[rcx\\+0x7f0\\]\n+\\s*[a-f0-9]+:\\s*c4 e2 78 b0 b2 00 f8 ff ff\\s+vcvtneoph2ps xmm6,XMMWORD PTR \\[rdx-0x800\\]\n+\\s*[a-f0-9]+:\\s*c4 a2 7c b0 b4 f5 00 00 00 10\\s+vcvtneoph2ps ymm6,YMMWORD PTR \\[rbp\\+r14\\*8\\+0x10000000\\]\n+\\s*[a-f0-9]+:\\s*c4 c2 7c b0 31\\s+vcvtneoph2ps ymm6,YMMWORD PTR \\[r9\\]\n+\\s*[a-f0-9]+:\\s*c4 e2 7c b0 b1 e0 0f 00 00\\s+vcvtneoph2ps ymm6,YMMWORD PTR \\[rcx\\+0xfe0\\]\n+\\s*[a-f0-9]+:\\s*c4 e2 7c b0 b2 00 f0 ff ff\\s+vcvtneoph2ps ymm6,YMMWORD PTR \\[rdx-0x1000\\]\n+\\s*[a-f0-9]+:\\s*62 f2 7e 08 72 f5\\s+vcvtneps2bf16 xmm6,xmm5\n+\\s*[a-f0-9]+:\\s*62 f2 7e 08 72 f5\\s+vcvtneps2bf16 xmm6,xmm5\n+\\s*[a-f0-9]+:\\s*c4 e2 7a 72 f5\\s+\\{vex\\} vcvtneps2bf16 xmm6,xmm5\n+\\s*[a-f0-9]+:\\s*c4 e2 7a 72 f5\\s+\\{vex\\} vcvtneps2bf16 xmm6,xmm5\n+\\s*[a-f0-9]+:\\s*62 f2 7e 28 72 f5\\s+vcvtneps2bf16 xmm6,ymm5\n+\\s*[a-f0-9]+:\\s*62 f2 7e 28 72 f5\\s+vcvtneps2bf16 xmm6,ymm5\n+\\s*[a-f0-9]+:\\s*c4 e2 7e 72 f5\\s+\\{vex\\} vcvtneps2bf16 xmm6,ymm5\n+\\s*[a-f0-9]+:\\s*c4 e2 7e 72 f5\\s+\\{vex\\} vcvtneps2bf16 xmm6,ymm5\n+\\s*[a-f0-9]+:\\s*62 b2 7e 08 72 b4 f5 00 00 00 10\\s+vcvtneps2bf16 xmm6,XMMWORD PTR \\[rbp\\+r14\\*8\\+0x10000000\\]\n+\\s*[a-f0-9]+:\\s*62 b2 7e 08 72 b4 f5 00 00 00 10\\s+vcvtneps2bf16 xmm6,XMMWORD PTR \\[rbp\\+r14\\*8\\+0x10000000\\]\n+\\s*[a-f0-9]+:\\s*c4 a2 7a 72 b4 f5 00 00 00 10\\s+\\{vex\\} vcvtneps2bf16 xmm6,XMMWORD PTR \\[rbp\\+r14\\*8\\+0x10000000\\]\n+\\s*[a-f0-9]+:\\s*c4 a2 7a 72 b4 f5 00 00 00 10\\s+\\{vex\\} vcvtneps2bf16 xmm6,XMMWORD PTR \\[rbp\\+r14\\*8\\+0x10000000\\]\n+\\s*[a-f0-9]+:\\s*62 d2 7e 08 72 31\\s+vcvtneps2bf16 xmm6,XMMWORD PTR \\[r9\\]\n+\\s*[a-f0-9]+:\\s*62 d2 7e 08 72 31\\s+vcvtneps2bf16 xmm6,XMMWORD PTR \\[r9\\]\n+\\s*[a-f0-9]+:\\s*c4 c2 7a 72 31\\s+\\{vex\\} vcvtneps2bf16 xmm6,XMMWORD PTR \\[r9\\]\n+\\s*[a-f0-9]+:\\s*c4 c2 7a 72 31\\s+\\{vex\\} vcvtneps2bf16 xmm6,XMMWORD PTR \\[r9\\]\n+\\s*[a-f0-9]+:\\s*62 f2 7e 08 72 71 7f\\s+vcvtneps2bf16 xmm6,XMMWORD PTR \\[rcx\\+0x7f0\\]\n+\\s*[a-f0-9]+:\\s*62 f2 7e 08 72 71 7f\\s+vcvtneps2bf16 xmm6,XMMWORD PTR \\[rcx\\+0x7f0\\]\n+\\s*[a-f0-9]+:\\s*c4 e2 7a 72 b1 f0 07 00 00\\s+\\{vex\\} vcvtneps2bf16 xmm6,XMMWORD PTR \\[rcx\\+0x7f0\\]\n+\\s*[a-f0-9]+:\\s*c4 e2 7a 72 b1 f0 07 00 00\\s+\\{vex\\} vcvtneps2bf16 xmm6,XMMWORD PTR \\[rcx\\+0x7f0\\]\n+\\s*[a-f0-9]+:\\s*62 f2 7e 08 72 72 80\\s+vcvtneps2bf16 xmm6,XMMWORD PTR \\[rdx-0x800\\]\n+\\s*[a-f0-9]+:\\s*62 f2 7e 08 72 72 80\\s+vcvtneps2bf16 xmm6,XMMWORD PTR \\[rdx-0x800\\]\n+\\s*[a-f0-9]+:\\s*c4 e2 7a 72 b2 00 f8 ff ff\\s+\\{vex\\} vcvtneps2bf16 xmm6,XMMWORD PTR \\[rdx-0x800\\]\n+\\s*[a-f0-9]+:\\s*c4 e2 7a 72 b2 00 f8 ff ff\\s+\\{vex\\} vcvtneps2bf16 xmm6,XMMWORD PTR \\[rdx-0x800\\]\n+\\s*[a-f0-9]+:\\s*62 f2 7e 28 72 71 7f\\s+vcvtneps2bf16 xmm6,YMMWORD PTR \\[rcx\\+0xfe0\\]\n+\\s*[a-f0-9]+:\\s*62 f2 7e 28 72 71 7f\\s+vcvtneps2bf16 xmm6,YMMWORD PTR \\[rcx\\+0xfe0\\]\n+\\s*[a-f0-9]+:\\s*c4 e2 7e 72 b1 e0 0f 00 00\\s+\\{vex\\} vcvtneps2bf16 xmm6,YMMWORD PTR \\[rcx\\+0xfe0\\]\n+\\s*[a-f0-9]+:\\s*c4 e2 7e 72 b1 e0 0f 00 00\\s+\\{vex\\} vcvtneps2bf16 xmm6,YMMWORD PTR \\[rcx\\+0xfe0\\]\n+\\s*[a-f0-9]+:\\s*62 f2 7e 28 72 72 80\\s+vcvtneps2bf16 xmm6,YMMWORD PTR \\[rdx-0x1000\\]\n+\\s*[a-f0-9]+:\\s*62 f2 7e 28 72 72 80\\s+vcvtneps2bf16 xmm6,YMMWORD PTR \\[rdx-0x1000\\]\n+\\s*[a-f0-9]+:\\s*c4 e2 7e 72 b2 00 f0 ff ff\\s+\\{vex\\} vcvtneps2bf16 xmm6,YMMWORD PTR \\[rdx-0x1000\\]\n+\\s*[a-f0-9]+:\\s*c4 e2 7e 72 b2 00 f0 ff ff\\s+\\{vex\\} vcvtneps2bf16 xmm6,YMMWORD PTR \\[rdx-0x1000\\]\ndiff --git a/gas/testsuite/gas/i386/x86-64-avx-ne-convert.d b/gas/testsuite/gas/i386/x86-64-avx-ne-convert.d\nnew file mode 100644\nindex 0000000000..6bd8391ed5\n--- /dev/null\n+++ b/gas/testsuite/gas/i386/x86-64-avx-ne-convert.d\n@@ -0,0 +1,170 @@\n+#as:\n+#objdump: -dw\n+#name: x86_64 AVX-NE-CONVERT insns\n+#source: x86-64-avx-ne-convert.s\n+\n+.*: +file format .*\n+\n+Disassembly of section \\.text:\n+\n+0+ <_start>:\n+\\s*[a-f0-9]+:\\s*c4 a2 7a b1 b4 f5 00 00 00 10\\s+vbcstnebf162ps 0x10000000\\(%rbp,%r14,8\\),%xmm6\n+\\s*[a-f0-9]+:\\s*c4 c2 7a b1 31\\s+vbcstnebf162ps \\(%r9\\),%xmm6\n+\\s*[a-f0-9]+:\\s*c4 e2 7a b1 b1 fe 00 00 00\\s+vbcstnebf162ps 0xfe\\(%rcx\\),%xmm6\n+\\s*[a-f0-9]+:\\s*c4 e2 7a b1 b2 00 ff ff ff\\s+vbcstnebf162ps -0x100\\(%rdx\\),%xmm6\n+\\s*[a-f0-9]+:\\s*c4 a2 7e b1 b4 f5 00 00 00 10\\s+vbcstnebf162ps 0x10000000\\(%rbp,%r14,8\\),%ymm6\n+\\s*[a-f0-9]+:\\s*c4 c2 7e b1 31\\s+vbcstnebf162ps \\(%r9\\),%ymm6\n+\\s*[a-f0-9]+:\\s*c4 e2 7e b1 b1 fe 00 00 00\\s+vbcstnebf162ps 0xfe\\(%rcx\\),%ymm6\n+\\s*[a-f0-9]+:\\s*c4 e2 7e b1 b2 00 ff ff ff\\s+vbcstnebf162ps -0x100\\(%rdx\\),%ymm6\n+\\s*[a-f0-9]+:\\s*c4 a2 79 b1 b4 f5 00 00 00 10\\s+vbcstnesh2ps 0x10000000\\(%rbp,%r14,8\\),%xmm6\n+\\s*[a-f0-9]+:\\s*c4 c2 79 b1 31\\s+vbcstnesh2ps \\(%r9\\),%xmm6\n+\\s*[a-f0-9]+:\\s*c4 e2 79 b1 b1 fe 00 00 00\\s+vbcstnesh2ps 0xfe\\(%rcx\\),%xmm6\n+\\s*[a-f0-9]+:\\s*c4 e2 79 b1 b2 00 ff ff ff\\s+vbcstnesh2ps -0x100\\(%rdx\\),%xmm6\n+\\s*[a-f0-9]+:\\s*c4 a2 7d b1 b4 f5 00 00 00 10\\s+vbcstnesh2ps 0x10000000\\(%rbp,%r14,8\\),%ymm6\n+\\s*[a-f0-9]+:\\s*c4 c2 7d b1 31\\s+vbcstnesh2ps \\(%r9\\),%ymm6\n+\\s*[a-f0-9]+:\\s*c4 e2 7d b1 b1 fe 00 00 00\\s+vbcstnesh2ps 0xfe\\(%rcx\\),%ymm6\n+\\s*[a-f0-9]+:\\s*c4 e2 7d b1 b2 00 ff ff ff\\s+vbcstnesh2ps -0x100\\(%rdx\\),%ymm6\n+\\s*[a-f0-9]+:\\s*c4 a2 7a b0 b4 f5 00 00 00 10\\s+vcvtneebf162ps 0x10000000\\(%rbp,%r14,8\\),%xmm6\n+\\s*[a-f0-9]+:\\s*c4 c2 7a b0 31\\s+vcvtneebf162ps \\(%r9\\),%xmm6\n+\\s*[a-f0-9]+:\\s*c4 e2 7a b0 b1 f0 07 00 00\\s+vcvtneebf162ps 0x7f0\\(%rcx\\),%xmm6\n+\\s*[a-f0-9]+:\\s*c4 e2 7a b0 b2 00 f8 ff ff\\s+vcvtneebf162ps -0x800\\(%rdx\\),%xmm6\n+\\s*[a-f0-9]+:\\s*c4 a2 7e b0 b4 f5 00 00 00 10\\s+vcvtneebf162ps 0x10000000\\(%rbp,%r14,8\\),%ymm6\n+\\s*[a-f0-9]+:\\s*c4 c2 7e b0 31\\s+vcvtneebf162ps \\(%r9\\),%ymm6\n+\\s*[a-f0-9]+:\\s*c4 e2 7e b0 b1 e0 0f 00 00\\s+vcvtneebf162ps 0xfe0\\(%rcx\\),%ymm6\n+\\s*[a-f0-9]+:\\s*c4 e2 7e b0 b2 00 f0 ff ff\\s+vcvtneebf162ps -0x1000\\(%rdx\\),%ymm6\n+\\s*[a-f0-9]+:\\s*c4 a2 79 b0 b4 f5 00 00 00 10\\s+vcvtneeph2ps 0x10000000\\(%rbp,%r14,8\\),%xmm6\n+\\s*[a-f0-9]+:\\s*c4 c2 79 b0 31\\s+vcvtneeph2ps \\(%r9\\),%xmm6\n+\\s*[a-f0-9]+:\\s*c4 e2 79 b0 b1 f0 07 00 00\\s+vcvtneeph2ps 0x7f0\\(%rcx\\),%xmm6\n+\\s*[a-f0-9]+:\\s*c4 e2 79 b0 b2 00 f8 ff ff\\s+vcvtneeph2ps -0x800\\(%rdx\\),%xmm6\n+\\s*[a-f0-9]+:\\s*c4 a2 7d b0 b4 f5 00 00 00 10\\s+vcvtneeph2ps 0x10000000\\(%rbp,%r14,8\\),%ymm6\n+\\s*[a-f0-9]+:\\s*c4 c2 7d b0 31\\s+vcvtneeph2ps \\(%r9\\),%ymm6\n+\\s*[a-f0-9]+:\\s*c4 e2 7d b0 b1 e0 0f 00 00\\s+vcvtneeph2ps 0xfe0\\(%rcx\\),%ymm6\n+\\s*[a-f0-9]+:\\s*c4 e2 7d b0 b2 00 f0 ff ff\\s+vcvtneeph2ps -0x1000\\(%rdx\\),%ymm6\n+\\s*[a-f0-9]+:\\s*c4 a2 7b b0 b4 f5 00 00 00 10\\s+vcvtneobf162ps 0x10000000\\(%rbp,%r14,8\\),%xmm6\n+\\s*[a-f0-9]+:\\s*c4 c2 7b b0 31\\s+vcvtneobf162ps \\(%r9\\),%xmm6\n+\\s*[a-f0-9]+:\\s*c4 e2 7b b0 b1 f0 07 00 00\\s+vcvtneobf162ps 0x7f0\\(%rcx\\),%xmm6\n+\\s*[a-f0-9]+:\\s*c4 e2 7b b0 b2 00 f8 ff ff\\s+vcvtneobf162ps -0x800\\(%rdx\\),%xmm6\n+\\s*[a-f0-9]+:\\s*c4 a2 7f b0 b4 f5 00 00 00 10\\s+vcvtneobf162ps 0x10000000\\(%rbp,%r14,8\\),%ymm6\n+\\s*[a-f0-9]+:\\s*c4 c2 7f b0 31\\s+vcvtneobf162ps \\(%r9\\),%ymm6\n+\\s*[a-f0-9]+:\\s*c4 e2 7f b0 b1 e0 0f 00 00\\s+vcvtneobf162ps 0xfe0\\(%rcx\\),%ymm6\n+\\s*[a-f0-9]+:\\s*c4 e2 7f b0 b2 00 f0 ff ff\\s+vcvtneobf162ps -0x1000\\(%rdx\\),%ymm6\n+\\s*[a-f0-9]+:\\s*c4 a2 78 b0 b4 f5 00 00 00 10\\s+vcvtneoph2ps 0x10000000\\(%rbp,%r14,8\\),%xmm6\n+\\s*[a-f0-9]+:\\s*c4 c2 78 b0 31\\s+vcvtneoph2ps \\(%r9\\),%xmm6\n+\\s*[a-f0-9]+:\\s*c4 e2 78 b0 b1 f0 07 00 00\\s+vcvtneoph2ps 0x7f0\\(%rcx\\),%xmm6\n+\\s*[a-f0-9]+:\\s*c4 e2 78 b0 b2 00 f8 ff ff\\s+vcvtneoph2ps -0x800\\(%rdx\\),%xmm6\n+\\s*[a-f0-9]+:\\s*c4 a2 7c b0 b4 f5 00 00 00 10\\s+vcvtneoph2ps 0x10000000\\(%rbp,%r14,8\\),%ymm6\n+\\s*[a-f0-9]+:\\s*c4 c2 7c b0 31\\s+vcvtneoph2ps \\(%r9\\),%ymm6\n+\\s*[a-f0-9]+:\\s*c4 e2 7c b0 b1 e0 0f 00 00\\s+vcvtneoph2ps 0xfe0\\(%rcx\\),%ymm6\n+\\s*[a-f0-9]+:\\s*c4 e2 7c b0 b2 00 f0 ff ff\\s+vcvtneoph2ps -0x1000\\(%rdx\\),%ymm6\n+\\s*[a-f0-9]+:\\s*62 f2 7e 08 72 f5\\s+vcvtneps2bf16 %xmm5,%xmm6\n+\\s*[a-f0-9]+:\\s*62 f2 7e 08 72 f5\\s+vcvtneps2bf16 %xmm5,%xmm6\n+\\s*[a-f0-9]+:\\s*c4 e2 7a 72 f5\\s+\\{vex\\} vcvtneps2bf16 %xmm5,%xmm6\n+\\s*[a-f0-9]+:\\s*c4 e2 7a 72 f5\\s+\\{vex\\} vcvtneps2bf16 %xmm5,%xmm6\n+\\s*[a-f0-9]+:\\s*62 f2 7e 28 72 f5\\s+vcvtneps2bf16 %ymm5,%xmm6\n+\\s*[a-f0-9]+:\\s*62 f2 7e 28 72 f5\\s+vcvtneps2bf16 %ymm5,%xmm6\n+\\s*[a-f0-9]+:\\s*c4 e2 7e 72 f5\\s+\\{vex\\} vcvtneps2bf16 %ymm5,%xmm6\n+\\s*[a-f0-9]+:\\s*c4 e2 7e 72 f5\\s+\\{vex\\} vcvtneps2bf16 %ymm5,%xmm6\n+\\s*[a-f0-9]+:\\s*62 b2 7e 08 72 b4 f5 00 00 00 10\\s+vcvtneps2bf16x 0x10000000\\(%rbp,%r14,8\\),%xmm6\n+\\s*[a-f0-9]+:\\s*62 b2 7e 08 72 b4 f5 00 00 00 10\\s+vcvtneps2bf16x 0x10000000\\(%rbp,%r14,8\\),%xmm6\n+\\s*[a-f0-9]+:\\s*c4 a2 7a 72 b4 f5 00 00 00 10\\s+\\{vex\\} vcvtneps2bf16x 0x10000000\\(%rbp,%r14,8\\),%xmm6\n+\\s*[a-f0-9]+:\\s*c4 a2 7a 72 b4 f5 00 00 00 10\\s+\\{vex\\} vcvtneps2bf16x 0x10000000\\(%rbp,%r14,8\\),%xmm6\n+\\s*[a-f0-9]+:\\s*62 d2 7e 08 72 31\\s+vcvtneps2bf16x \\(%r9\\),%xmm6\n+\\s*[a-f0-9]+:\\s*62 d2 7e 08 72 31\\s+vcvtneps2bf16x \\(%r9\\),%xmm6\n+\\s*[a-f0-9]+:\\s*c4 c2 7a 72 31\\s+\\{vex\\} vcvtneps2bf16x \\(%r9\\),%xmm6\n+\\s*[a-f0-9]+:\\s*c4 c2 7a 72 31\\s+\\{vex\\} vcvtneps2bf16x \\(%r9\\),%xmm6\n+\\s*[a-f0-9]+:\\s*62 f2 7e 08 72 71 7f\\s+vcvtneps2bf16x 0x7f0\\(%rcx\\),%xmm6\n+\\s*[a-f0-9]+:\\s*62 f2 7e 08 72 71 7f\\s+vcvtneps2bf16x 0x7f0\\(%rcx\\),%xmm6\n+\\s*[a-f0-9]+:\\s*c4 e2 7a 72 b1 f0 07 00 00\\s+\\{vex\\} vcvtneps2bf16x 0x7f0\\(%rcx\\),%xmm6\n+\\s*[a-f0-9]+:\\s*c4 e2 7a 72 b1 f0 07 00 00\\s+\\{vex\\} vcvtneps2bf16x 0x7f0\\(%rcx\\),%xmm6\n+\\s*[a-f0-9]+:\\s*62 f2 7e 08 72 72 80\\s+vcvtneps2bf16x -0x800\\(%rdx\\),%xmm6\n+\\s*[a-f0-9]+:\\s*62 f2 7e 08 72 72 80\\s+vcvtneps2bf16x -0x800\\(%rdx\\),%xmm6\n+\\s*[a-f0-9]+:\\s*c4 e2 7a 72 b2 00 f8 ff ff\\s+\\{vex\\} vcvtneps2bf16x -0x800\\(%rdx\\),%xmm6\n+\\s*[a-f0-9]+:\\s*c4 e2 7a 72 b2 00 f8 ff ff\\s+\\{vex\\} vcvtneps2bf16x -0x800\\(%rdx\\),%xmm6\n+\\s*[a-f0-9]+:\\s*62 f2 7e 28 72 71 7f\\s+vcvtneps2bf16y 0xfe0\\(%rcx\\),%xmm6\n+\\s*[a-f0-9]+:\\s*62 f2 7e 28 72 71 7f\\s+vcvtneps2bf16y 0xfe0\\(%rcx\\),%xmm6\n+\\s*[a-f0-9]+:\\s*c4 e2 7e 72 b1 e0 0f 00 00\\s+\\{vex\\} vcvtneps2bf16y 0xfe0\\(%rcx\\),%xmm6\n+\\s*[a-f0-9]+:\\s*c4 e2 7e 72 b1 e0 0f 00 00\\s+\\{vex\\} vcvtneps2bf16y 0xfe0\\(%rcx\\),%xmm6\n+\\s*[a-f0-9]+:\\s*62 f2 7e 28 72 72 80\\s+vcvtneps2bf16y -0x1000\\(%rdx\\),%xmm6\n+\\s*[a-f0-9]+:\\s*62 f2 7e 28 72 72 80\\s+vcvtneps2bf16y -0x1000\\(%rdx\\),%xmm6\n+\\s*[a-f0-9]+:\\s*c4 e2 7e 72 b2 00 f0 ff ff\\s+\\{vex\\} vcvtneps2bf16y -0x1000\\(%rdx\\),%xmm6\n+\\s*[a-f0-9]+:\\s*c4 e2 7e 72 b2 00 f0 ff ff\\s+\\{vex\\} vcvtneps2bf16y -0x1000\\(%rdx\\),%xmm6\n+\\s*[a-f0-9]+:\\s*c4 a2 7a b1 b4 f5 00 00 00 10\\s+vbcstnebf162ps 0x10000000\\(%rbp,%r14,8\\),%xmm6\n+\\s*[a-f0-9]+:\\s*c4 c2 7a b1 31\\s+vbcstnebf162ps \\(%r9\\),%xmm6\n+\\s*[a-f0-9]+:\\s*c4 e2 7a b1 b1 fe 00 00 00\\s+vbcstnebf162ps 0xfe\\(%rcx\\),%xmm6\n+\\s*[a-f0-9]+:\\s*c4 e2 7a b1 b2 00 ff ff ff\\s+vbcstnebf162ps -0x100\\(%rdx\\),%xmm6\n+\\s*[a-f0-9]+:\\s*c4 a2 7e b1 b4 f5 00 00 00 10\\s+vbcstnebf162ps 0x10000000\\(%rbp,%r14,8\\),%ymm6\n+\\s*[a-f0-9]+:\\s*c4 c2 7e b1 31\\s+vbcstnebf162ps \\(%r9\\),%ymm6\n+\\s*[a-f0-9]+:\\s*c4 e2 7e b1 b1 fe 00 00 00\\s+vbcstnebf162ps 0xfe\\(%rcx\\),%ymm6\n+\\s*[a-f0-9]+:\\s*c4 e2 7e b1 b2 00 ff ff ff\\s+vbcstnebf162ps -0x100\\(%rdx\\),%ymm6\n+\\s*[a-f0-9]+:\\s*c4 a2 79 b1 b4 f5 00 00 00 10\\s+vbcstnesh2ps 0x10000000\\(%rbp,%r14,8\\),%xmm6\n+\\s*[a-f0-9]+:\\s*c4 c2 79 b1 31\\s+vbcstnesh2ps \\(%r9\\),%xmm6\n+\\s*[a-f0-9]+:\\s*c4 e2 79 b1 b1 fe 00 00 00\\s+vbcstnesh2ps 0xfe\\(%rcx\\),%xmm6\n+\\s*[a-f0-9]+:\\s*c4 e2 79 b1 b2 00 ff ff ff\\s+vbcstnesh2ps -0x100\\(%rdx\\),%xmm6\n+\\s*[a-f0-9]+:\\s*c4 a2 7d b1 b4 f5 00 00 00 10\\s+vbcstnesh2ps 0x10000000\\(%rbp,%r14,8\\),%ymm6\n+\\s*[a-f0-9]+:\\s*c4 c2 7d b1 31\\s+vbcstnesh2ps \\(%r9\\),%ymm6\n+\\s*[a-f0-9]+:\\s*c4 e2 7d b1 b1 fe 00 00 00\\s+vbcstnesh2ps 0xfe\\(%rcx\\),%ymm6\n+\\s*[a-f0-9]+:\\s*c4 e2 7d b1 b2 00 ff ff ff\\s+vbcstnesh2ps -0x100\\(%rdx\\),%ymm6\n+\\s*[a-f0-9]+:\\s*c4 a2 7a b0 b4 f5 00 00 00 10\\s+vcvtneebf162ps 0x10000000\\(%rbp,%r14,8\\),%xmm6\n+\\s*[a-f0-9]+:\\s*c4 c2 7a b0 31\\s+vcvtneebf162ps \\(%r9\\),%xmm6\n+\\s*[a-f0-9]+:\\s*c4 e2 7a b0 b1 f0 07 00 00\\s+vcvtneebf162ps 0x7f0\\(%rcx\\),%xmm6\n+\\s*[a-f0-9]+:\\s*c4 e2 7a b0 b2 00 f8 ff ff\\s+vcvtneebf162ps -0x800\\(%rdx\\),%xmm6\n+\\s*[a-f0-9]+:\\s*c4 a2 7e b0 b4 f5 00 00 00 10\\s+vcvtneebf162ps 0x10000000\\(%rbp,%r14,8\\),%ymm6\n+\\s*[a-f0-9]+:\\s*c4 c2 7e b0 31\\s+vcvtneebf162ps \\(%r9\\),%ymm6\n+\\s*[a-f0-9]+:\\s*c4 e2 7e b0 b1 e0 0f 00 00\\s+vcvtneebf162ps 0xfe0\\(%rcx\\),%ymm6\n+\\s*[a-f0-9]+:\\s*c4 e2 7e b0 b2 00 f0 ff ff\\s+vcvtneebf162ps -0x1000\\(%rdx\\),%ymm6\n+\\s*[a-f0-9]+:\\s*c4 a2 79 b0 b4 f5 00 00 00 10\\s+vcvtneeph2ps 0x10000000\\(%rbp,%r14,8\\),%xmm6\n+\\s*[a-f0-9]+:\\s*c4 c2 79 b0 31\\s+vcvtneeph2ps \\(%r9\\),%xmm6\n+\\s*[a-f0-9]+:\\s*c4 e2 79 b0 b1 f0 07 00 00\\s+vcvtneeph2ps 0x7f0\\(%rcx\\),%xmm6\n+\\s*[a-f0-9]+:\\s*c4 e2 79 b0 b2 00 f8 ff ff\\s+vcvtneeph2ps -0x800\\(%rdx\\),%xmm6\n+\\s*[a-f0-9]+:\\s*c4 a2 7d b0 b4 f5 00 00 00 10\\s+vcvtneeph2ps 0x10000000\\(%rbp,%r14,8\\),%ymm6\n+\\s*[a-f0-9]+:\\s*c4 c2 7d b0 31\\s+vcvtneeph2ps \\(%r9\\),%ymm6\n+\\s*[a-f0-9]+:\\s*c4 e2 7d b0 b1 e0 0f 00 00\\s+vcvtneeph2ps 0xfe0\\(%rcx\\),%ymm6\n+\\s*[a-f0-9]+:\\s*c4 e2 7d b0 b2 00 f0 ff ff\\s+vcvtneeph2ps -0x1000\\(%rdx\\),%ymm6\n+\\s*[a-f0-9]+:\\s*c4 a2 7b b0 b4 f5 00 00 00 10\\s+vcvtneobf162ps 0x10000000\\(%rbp,%r14,8\\),%xmm6\n+\\s*[a-f0-9]+:\\s*c4 c2 7b b0 31\\s+vcvtneobf162ps \\(%r9\\),%xmm6\n+\\s*[a-f0-9]+:\\s*c4 e2 7b b0 b1 f0 07 00 00\\s+vcvtneobf162ps 0x7f0\\(%rcx\\),%xmm6\n+\\s*[a-f0-9]+:\\s*c4 e2 7b b0 b2 00 f8 ff ff\\s+vcvtneobf162ps -0x800\\(%rdx\\),%xmm6\n+\\s*[a-f0-9]+:\\s*c4 a2 7f b0 b4 f5 00 00 00 10\\s+vcvtneobf162ps 0x10000000\\(%rbp,%r14,8\\),%ymm6\n+\\s*[a-f0-9]+:\\s*c4 c2 7f b0 31\\s+vcvtneobf162ps \\(%r9\\),%ymm6\n+\\s*[a-f0-9]+:\\s*c4 e2 7f b0 b1 e0 0f 00 00\\s+vcvtneobf162ps 0xfe0\\(%rcx\\),%ymm6\n+\\s*[a-f0-9]+:\\s*c4 e2 7f b0 b2 00 f0 ff ff\\s+vcvtneobf162ps -0x1000\\(%rdx\\),%ymm6\n+\\s*[a-f0-9]+:\\s*c4 a2 78 b0 b4 f5 00 00 00 10\\s+vcvtneoph2ps 0x10000000\\(%rbp,%r14,8\\),%xmm6\n+\\s*[a-f0-9]+:\\s*c4 c2 78 b0 31\\s+vcvtneoph2ps \\(%r9\\),%xmm6\n+\\s*[a-f0-9]+:\\s*c4 e2 78 b0 b1 f0 07 00 00\\s+vcvtneoph2ps 0x7f0\\(%rcx\\),%xmm6\n+\\s*[a-f0-9]+:\\s*c4 e2 78 b0 b2 00 f8 ff ff\\s+vcvtneoph2ps -0x800\\(%rdx\\),%xmm6\n+\\s*[a-f0-9]+:\\s*c4 a2 7c b0 b4 f5 00 00 00 10\\s+vcvtneoph2ps 0x10000000\\(%rbp,%r14,8\\),%ymm6\n+\\s*[a-f0-9]+:\\s*c4 c2 7c b0 31\\s+vcvtneoph2ps \\(%r9\\),%ymm6\n+\\s*[a-f0-9]+:\\s*c4 e2 7c b0 b1 e0 0f 00 00\\s+vcvtneoph2ps 0xfe0\\(%rcx\\),%ymm6\n+\\s*[a-f0-9]+:\\s*c4 e2 7c b0 b2 00 f0 ff ff\\s+vcvtneoph2ps -0x1000\\(%rdx\\),%ymm6\n+\\s*[a-f0-9]+:\\s*62 f2 7e 08 72 f5\\s+vcvtneps2bf16 %xmm5,%xmm6\n+\\s*[a-f0-9]+:\\s*62 f2 7e 08 72 f5\\s+vcvtneps2bf16 %xmm5,%xmm6\n+\\s*[a-f0-9]+:\\s*c4 e2 7a 72 f5\\s+\\{vex\\} vcvtneps2bf16 %xmm5,%xmm6\n+\\s*[a-f0-9]+:\\s*c4 e2 7a 72 f5\\s+\\{vex\\} vcvtneps2bf16 %xmm5,%xmm6\n+\\s*[a-f0-9]+:\\s*62 f2 7e 28 72 f5\\s+vcvtneps2bf16 %ymm5,%xmm6\n+\\s*[a-f0-9]+:\\s*62 f2 7e 28 72 f5\\s+vcvtneps2bf16 %ymm5,%xmm6\n+\\s*[a-f0-9]+:\\s*c4 e2 7e 72 f5\\s+\\{vex\\} vcvtneps2bf16 %ymm5,%xmm6\n+\\s*[a-f0-9]+:\\s*c4 e2 7e 72 f5\\s+\\{vex\\} vcvtneps2bf16 %ymm5,%xmm6\n+\\s*[a-f0-9]+:\\s*62 b2 7e 08 72 b4 f5 00 00 00 10\\s+vcvtneps2bf16x 0x10000000\\(%rbp,%r14,8\\),%xmm6\n+\\s*[a-f0-9]+:\\s*62 b2 7e 08 72 b4 f5 00 00 00 10\\s+vcvtneps2bf16x 0x10000000\\(%rbp,%r14,8\\),%xmm6\n+\\s*[a-f0-9]+:\\s*c4 a2 7a 72 b4 f5 00 00 00 10\\s+\\{vex\\} vcvtneps2bf16x 0x10000000\\(%rbp,%r14,8\\),%xmm6\n+\\s*[a-f0-9]+:\\s*c4 a2 7a 72 b4 f5 00 00 00 10\\s+\\{vex\\} vcvtneps2bf16x 0x10000000\\(%rbp,%r14,8\\),%xmm6\n+\\s*[a-f0-9]+:\\s*62 d2 7e 08 72 31\\s+vcvtneps2bf16x \\(%r9\\),%xmm6\n+\\s*[a-f0-9]+:\\s*62 d2 7e 08 72 31\\s+vcvtneps2bf16x \\(%r9\\),%xmm6\n+\\s*[a-f0-9]+:\\s*c4 c2 7a 72 31\\s+\\{vex\\} vcvtneps2bf16x \\(%r9\\),%xmm6\n+\\s*[a-f0-9]+:\\s*c4 c2 7a 72 31\\s+\\{vex\\} vcvtneps2bf16x \\(%r9\\),%xmm6\n+\\s*[a-f0-9]+:\\s*62 f2 7e 08 72 71 7f\\s+vcvtneps2bf16x 0x7f0\\(%rcx\\),%xmm6\n+\\s*[a-f0-9]+:\\s*62 f2 7e 08 72 71 7f\\s+vcvtneps2bf16x 0x7f0\\(%rcx\\),%xmm6\n+\\s*[a-f0-9]+:\\s*c4 e2 7a 72 b1 f0 07 00 00\\s+\\{vex\\} vcvtneps2bf16x 0x7f0\\(%rcx\\),%xmm6\n+\\s*[a-f0-9]+:\\s*c4 e2 7a 72 b1 f0 07 00 00\\s+\\{vex\\} vcvtneps2bf16x 0x7f0\\(%rcx\\),%xmm6\n+\\s*[a-f0-9]+:\\s*62 f2 7e 08 72 72 80\\s+vcvtneps2bf16x -0x800\\(%rdx\\),%xmm6\n+\\s*[a-f0-9]+:\\s*62 f2 7e 08 72 72 80\\s+vcvtneps2bf16x -0x800\\(%rdx\\),%xmm6\n+\\s*[a-f0-9]+:\\s*c4 e2 7a 72 b2 00 f8 ff ff\\s+\\{vex\\} vcvtneps2bf16x -0x800\\(%rdx\\),%xmm6\n+\\s*[a-f0-9]+:\\s*c4 e2 7a 72 b2 00 f8 ff ff\\s+\\{vex\\} vcvtneps2bf16x -0x800\\(%rdx\\),%xmm6\n+\\s*[a-f0-9]+:\\s*62 f2 7e 28 72 71 7f\\s+vcvtneps2bf16y 0xfe0\\(%rcx\\),%xmm6\n+\\s*[a-f0-9]+:\\s*62 f2 7e 28 72 71 7f\\s+vcvtneps2bf16y 0xfe0\\(%rcx\\),%xmm6\n+\\s*[a-f0-9]+:\\s*c4 e2 7e 72 b1 e0 0f 00 00\\s+\\{vex\\} vcvtneps2bf16y 0xfe0\\(%rcx\\),%xmm6\n+\\s*[a-f0-9]+:\\s*c4 e2 7e 72 b1 e0 0f 00 00\\s+\\{vex\\} vcvtneps2bf16y 0xfe0\\(%rcx\\),%xmm6\n+\\s*[a-f0-9]+:\\s*62 f2 7e 28 72 72 80\\s+vcvtneps2bf16y -0x1000\\(%rdx\\),%xmm6\n+\\s*[a-f0-9]+:\\s*62 f2 7e 28 72 72 80\\s+vcvtneps2bf16y -0x1000\\(%rdx\\),%xmm6\n+\\s*[a-f0-9]+:\\s*c4 e2 7e 72 b2 00 f0 ff ff\\s+\\{vex\\} vcvtneps2bf16y -0x1000\\(%rdx\\),%xmm6\n+\\s*[a-f0-9]+:\\s*c4 e2 7e 72 b2 00 f0 ff ff\\s+\\{vex\\} vcvtneps2bf16y -0x1000\\(%rdx\\),%xmm6\ndiff --git a/gas/testsuite/gas/i386/x86-64-avx-ne-convert.s b/gas/testsuite/gas/i386/x86-64-avx-ne-convert.s\nnew file mode 100644\nindex 0000000000..c01a95d943\n--- /dev/null\n+++ b/gas/testsuite/gas/i386/x86-64-avx-ne-convert.s\n@@ -0,0 +1,167 @@\n+# Check 64bit AVX-NE-CONVERT instructions\n+\n+\t.allow_index_reg\n+\t.text\n+_start:\n+\tvbcstnebf162ps\t0x10000000(%rbp, %r14, 8), %xmm6\t #AVX-NE-CONVERT\n+\tvbcstnebf162ps\t(%r9), %xmm6\t #AVX-NE-CONVERT\n+\tvbcstnebf162ps\t254(%rcx), %xmm6\t #AVX-NE-CONVERT Disp32(fe000000)\n+\tvbcstnebf162ps\t-256(%rdx), %xmm6\t #AVX-NE-CONVERT Disp32(00ffffff)\n+\tvbcstnebf162ps\t0x10000000(%rbp, %r14, 8), %ymm6\t #AVX-NE-CONVERT\n+\tvbcstnebf162ps\t(%r9), %ymm6\t #AVX-NE-CONVERT\n+\tvbcstnebf162ps\t254(%rcx), %ymm6\t #AVX-NE-CONVERT Disp32(fe000000)\n+\tvbcstnebf162ps\t-256(%rdx), %ymm6\t #AVX-NE-CONVERT Disp32(00ffffff)\n+\tvbcstnesh2ps\t0x10000000(%rbp, %r14, 8), %xmm6\t #AVX-NE-CONVERT\n+\tvbcstnesh2ps\t(%r9), %xmm6\t #AVX-NE-CONVERT\n+\tvbcstnesh2ps\t254(%rcx), %xmm6\t #AVX-NE-CONVERT Disp32(fe000000)\n+\tvbcstnesh2ps\t-256(%rdx), %xmm6\t #AVX-NE-CONVERT Disp32(00ffffff)\n+\tvbcstnesh2ps\t0x10000000(%rbp, %r14, 8), %ymm6\t #AVX-NE-CONVERT\n+\tvbcstnesh2ps\t(%r9), %ymm6\t #AVX-NE-CONVERT\n+\tvbcstnesh2ps\t254(%rcx), %ymm6\t #AVX-NE-CONVERT Disp32(fe000000)\n+\tvbcstnesh2ps\t-256(%rdx), %ymm6\t #AVX-NE-CONVERT Disp32(00ffffff)\n+\tvcvtneebf162ps\t0x10000000(%rbp, %r14, 8), %xmm6\t #AVX-NE-CONVERT\n+\tvcvtneebf162ps\t(%r9), %xmm6\t #AVX-NE-CONVERT\n+\tvcvtneebf162ps\t2032(%rcx), %xmm6\t #AVX-NE-CONVERT Disp32(f0070000)\n+\tvcvtneebf162ps\t-2048(%rdx), %xmm6\t #AVX-NE-CONVERT Disp32(00f8ffff)\n+\tvcvtneebf162ps\t0x10000000(%rbp, %r14, 8), %ymm6\t #AVX-NE-CONVERT\n+\tvcvtneebf162ps\t(%r9), %ymm6\t #AVX-NE-CONVERT\n+\tvcvtneebf162ps\t4064(%rcx), %ymm6\t #AVX-NE-CONVERT Disp32(e00f0000)\n+\tvcvtneebf162ps\t-4096(%rdx), %ymm6\t #AVX-NE-CONVERT Disp32(00f0ffff)\n+\tvcvtneeph2ps\t0x10000000(%rbp, %r14, 8), %xmm6\t #AVX-NE-CONVERT\n+\tvcvtneeph2ps\t(%r9), %xmm6\t #AVX-NE-CONVERT\n+\tvcvtneeph2ps\t2032(%rcx), %xmm6\t #AVX-NE-CONVERT Disp32(f0070000)\n+\tvcvtneeph2ps\t-2048(%rdx), %xmm6\t #AVX-NE-CONVERT Disp32(00f8ffff)\n+\tvcvtneeph2ps\t0x10000000(%rbp, %r14, 8), %ymm6\t #AVX-NE-CONVERT\n+\tvcvtneeph2ps\t(%r9), %ymm6\t #AVX-NE-CONVERT\n+\tvcvtneeph2ps\t4064(%rcx), %ymm6\t #AVX-NE-CONVERT Disp32(e00f0000)\n+\tvcvtneeph2ps\t-4096(%rdx), %ymm6\t #AVX-NE-CONVERT Disp32(00f0ffff)\n+\tvcvtneobf162ps\t0x10000000(%rbp, %r14, 8), %xmm6\t #AVX-NE-CONVERT\n+\tvcvtneobf162ps\t(%r9), %xmm6\t #AVX-NE-CONVERT\n+\tvcvtneobf162ps\t2032(%rcx), %xmm6\t #AVX-NE-CONVERT Disp32(f0070000)\n+\tvcvtneobf162ps\t-2048(%rdx), %xmm6\t #AVX-NE-CONVERT Disp32(00f8ffff)\n+\tvcvtneobf162ps\t0x10000000(%rbp, %r14, 8), %ymm6\t #AVX-NE-CONVERT\n+\tvcvtneobf162ps\t(%r9), %ymm6\t #AVX-NE-CONVERT\n+\tvcvtneobf162ps\t4064(%rcx), %ymm6\t #AVX-NE-CONVERT Disp32(e00f0000)\n+\tvcvtneobf162ps\t-4096(%rdx), %ymm6\t #AVX-NE-CONVERT Disp32(00f0ffff)\n+\tvcvtneoph2ps\t0x10000000(%rbp, %r14, 8), %xmm6\t #AVX-NE-CONVERT\n+\tvcvtneoph2ps\t(%r9), %xmm6\t #AVX-NE-CONVERT\n+\tvcvtneoph2ps\t2032(%rcx), %xmm6\t #AVX-NE-CONVERT Disp32(f0070000)\n+\tvcvtneoph2ps\t-2048(%rdx), %xmm6\t #AVX-NE-CONVERT Disp32(00f8ffff)\n+\tvcvtneoph2ps\t0x10000000(%rbp, %r14, 8), %ymm6\t #AVX-NE-CONVERT\n+\tvcvtneoph2ps\t(%r9), %ymm6\t #AVX-NE-CONVERT\n+\tvcvtneoph2ps\t4064(%rcx), %ymm6\t #AVX-NE-CONVERT Disp32(e00f0000)\n+\tvcvtneoph2ps\t-4096(%rdx), %ymm6\t #AVX-NE-CONVERT Disp32(00f0ffff)\n+\tvcvtneps2bf16\t%xmm5, %xmm6\t #AVX-NE-CONVERT\n+\t{evex} vcvtneps2bf16\t%xmm5, %xmm6\t #AVX-NE-CONVERT\n+\t{vex} vcvtneps2bf16\t%xmm5, %xmm6\t #AVX-NE-CONVERT\n+\t{vex3} vcvtneps2bf16\t%xmm5, %xmm6\t #AVX-NE-CONVERT\n+\tvcvtneps2bf16\t%ymm5, %xmm6\t #AVX-NE-CONVERT\n+\t{evex} vcvtneps2bf16\t%ymm5, %xmm6\t #AVX-NE-CONVERT\n+\t{vex} vcvtneps2bf16\t%ymm5, %xmm6\t #AVX-NE-CONVERT\n+\t{vex3} vcvtneps2bf16\t%ymm5, %xmm6\t #AVX-NE-CONVERT\n+\tvcvtneps2bf16x\t0x10000000(%rbp, %r14, 8), %xmm6\t #AVX-NE-CONVERT\n+\t{evex} vcvtneps2bf16x\t0x10000000(%rbp, %r14, 8), %xmm6\t #AVX-NE-CONVERT\n+\t{vex} vcvtneps2bf16x\t0x10000000(%rbp, %r14, 8), %xmm6\t #AVX-NE-CONVERT\n+\t{vex3} vcvtneps2bf16x\t0x10000000(%rbp, %r14, 8), %xmm6\t #AVX-NE-CONVERT\n+\tvcvtneps2bf16x\t(%r9), %xmm6\t #AVX-NE-CONVERT\n+\t{evex} vcvtneps2bf16x\t(%r9), %xmm6\t #AVX-NE-CONVERT\n+\t{vex} vcvtneps2bf16x\t(%r9), %xmm6\t #AVX-NE-CONVERT\n+\t{vex3} vcvtneps2bf16x\t(%r9), %xmm6\t #AVX-NE-CONVERT\n+\tvcvtneps2bf16x\t2032(%rcx), %xmm6\t #AVX-NE-CONVERT Disp32(f0070000)\n+\t{evex} vcvtneps2bf16x\t2032(%rcx), %xmm6\t #AVX-NE-CONVERT Disp32(f0070000)\n+\t{vex} vcvtneps2bf16x\t2032(%rcx), %xmm6\t #AVX-NE-CONVERT Disp32(f0070000)\n+\t{vex3} vcvtneps2bf16x\t2032(%rcx), %xmm6\t #AVX-NE-CONVERT Disp32(f0070000)\n+\tvcvtneps2bf16x\t-2048(%rdx), %xmm6\t #AVX-NE-CONVERT Disp32(00f8ffff)\n+\t{evex} vcvtneps2bf16x\t-2048(%rdx), %xmm6\t #AVX-NE-CONVERT Disp32(00f8ffff)\n+\t{vex} vcvtneps2bf16x\t-2048(%rdx), %xmm6\t #AVX-NE-CONVERT Disp32(00f8ffff)\n+\t{vex3} vcvtneps2bf16x\t-2048(%rdx), %xmm6\t #AVX-NE-CONVERT Disp32(00f8ffff)\n+\tvcvtneps2bf16y\t4064(%rcx), %xmm6\t #AVX-NE-CONVERT Disp32(e00f0000)\n+\t{evex} vcvtneps2bf16y\t4064(%rcx), %xmm6\t #AVX-NE-CONVERT Disp32(e00f0000)\n+\t{vex} vcvtneps2bf16y\t4064(%rcx), %xmm6\t #AVX-NE-CONVERT Disp32(e00f0000)\n+\t{vex3} vcvtneps2bf16y\t4064(%rcx), %xmm6\t #AVX-NE-CONVERT Disp32(e00f0000)\n+\tvcvtneps2bf16y\t-4096(%rdx), %xmm6\t #AVX-NE-CONVERT Disp32(00f0ffff)\n+\t{evex} vcvtneps2bf16y\t-4096(%rdx), %xmm6\t #AVX-NE-CONVERT Disp32(00f0ffff)\n+\t{vex} vcvtneps2bf16y\t-4096(%rdx), %xmm6\t #AVX-NE-CONVERT Disp32(00f0ffff)\n+\t{vex3} vcvtneps2bf16y\t-4096(%rdx), %xmm6\t #AVX-NE-CONVERT Disp32(00f0ffff)\n+\n+.intel_syntax noprefix\n+\tvbcstnebf162ps\txmm6, WORD PTR [rbp+r14*8+0x10000000]\t #AVX-NE-CONVERT\n+\tvbcstnebf162ps\txmm6, WORD PTR [r9]\t #AVX-NE-CONVERT\n+\tvbcstnebf162ps\txmm6, WORD PTR [rcx+254]\t #AVX-NE-CONVERT Disp32(fe000000)\n+\tvbcstnebf162ps\txmm6, WORD PTR [rdx-256]\t #AVX-NE-CONVERT Disp32(00ffffff)\n+\tvbcstnebf162ps\tymm6, WORD PTR [rbp+r14*8+0x10000000]\t #AVX-NE-CONVERT\n+\tvbcstnebf162ps\tymm6, WORD PTR [r9]\t #AVX-NE-CONVERT\n+\tvbcstnebf162ps\tymm6, WORD PTR [rcx+254]\t #AVX-NE-CONVERT Disp32(fe000000)\n+\tvbcstnebf162ps\tymm6, WORD PTR [rdx-256]\t #AVX-NE-CONVERT Disp32(00ffffff)\n+\tvbcstnesh2ps\txmm6, WORD PTR [rbp+r14*8+0x10000000]\t #AVX-NE-CONVERT\n+\tvbcstnesh2ps\txmm6, WORD PTR [r9]\t #AVX-NE-CONVERT\n+\tvbcstnesh2ps\txmm6, WORD PTR [rcx+254]\t #AVX-NE-CONVERT Disp32(fe000000)\n+\tvbcstnesh2ps\txmm6, WORD PTR [rdx-256]\t #AVX-NE-CONVERT Disp32(00ffffff)\n+\tvbcstnesh2ps\tymm6, WORD PTR [rbp+r14*8+0x10000000]\t #AVX-NE-CONVERT\n+\tvbcstnesh2ps\tymm6, WORD PTR [r9]\t #AVX-NE-CONVERT\n+\tvbcstnesh2ps\tymm6, WORD PTR [rcx+254]\t #AVX-NE-CONVERT Disp32(fe000000)\n+\tvbcstnesh2ps\tymm6, WORD PTR [rdx-256]\t #AVX-NE-CONVERT Disp32(00ffffff)\n+\tvcvtneebf162ps\txmm6, XMMWORD PTR [rbp+r14*8+0x10000000]\t #AVX-NE-CONVERT\n+\tvcvtneebf162ps\txmm6, XMMWORD PTR [r9]\t #AVX-NE-CONVERT\n+\tvcvtneebf162ps\txmm6, XMMWORD PTR [rcx+2032]\t #AVX-NE-CONVERT Disp32(f0070000)\n+\tvcvtneebf162ps\txmm6, XMMWORD PTR [rdx-2048]\t #AVX-NE-CONVERT Disp32(00f8ffff)\n+\tvcvtneebf162ps\tymm6, YMMWORD PTR [rbp+r14*8+0x10000000]\t #AVX-NE-CONVERT\n+\tvcvtneebf162ps\tymm6, YMMWORD PTR [r9]\t #AVX-NE-CONVERT\n+\tvcvtneebf162ps\tymm6, YMMWORD PTR [rcx+4064]\t #AVX-NE-CONVERT Disp32(e00f0000)\n+\tvcvtneebf162ps\tymm6, YMMWORD PTR [rdx-4096]\t #AVX-NE-CONVERT Disp32(00f0ffff)\n+\tvcvtneeph2ps\txmm6, XMMWORD PTR [rbp+r14*8+0x10000000]\t #AVX-NE-CONVERT\n+\tvcvtneeph2ps\txmm6, XMMWORD PTR [r9]\t #AVX-NE-CONVERT\n+\tvcvtneeph2ps\txmm6, XMMWORD PTR [rcx+2032]\t #AVX-NE-CONVERT Disp32(f0070000)\n+\tvcvtneeph2ps\txmm6, XMMWORD PTR [rdx-2048]\t #AVX-NE-CONVERT Disp32(00f8ffff)\n+\tvcvtneeph2ps\tymm6, YMMWORD PTR [rbp+r14*8+0x10000000]\t #AVX-NE-CONVERT\n+\tvcvtneeph2ps\tymm6, YMMWORD PTR [r9]\t #AVX-NE-CONVERT\n+\tvcvtneeph2ps\tymm6, YMMWORD PTR [rcx+4064]\t #AVX-NE-CONVERT Disp32(e00f0000)\n+\tvcvtneeph2ps\tymm6, YMMWORD PTR [rdx-4096]\t #AVX-NE-CONVERT Disp32(00f0ffff)\n+\tvcvtneobf162ps\txmm6, XMMWORD PTR [rbp+r14*8+0x10000000]\t #AVX-NE-CONVERT\n+\tvcvtneobf162ps\txmm6, XMMWORD PTR [r9]\t #AVX-NE-CONVERT\n+\tvcvtneobf162ps\txmm6, XMMWORD PTR [rcx+2032]\t #AVX-NE-CONVERT Disp32(f0070000)\n+\tvcvtneobf162ps\txmm6, XMMWORD PTR [rdx-2048]\t #AVX-NE-CONVERT Disp32(00f8ffff)\n+\tvcvtneobf162ps\tymm6, YMMWORD PTR [rbp+r14*8+0x10000000]\t #AVX-NE-CONVERT\n+\tvcvtneobf162ps\tymm6, YMMWORD PTR [r9]\t #AVX-NE-CONVERT\n+\tvcvtneobf162ps\tymm6, YMMWORD PTR [rcx+4064]\t #AVX-NE-CONVERT Disp32(e00f0000)\n+\tvcvtneobf162ps\tymm6, YMMWORD PTR [rdx-4096]\t #AVX-NE-CONVERT Disp32(00f0ffff)\n+\tvcvtneoph2ps\txmm6, XMMWORD PTR [rbp+r14*8+0x10000000]\t #AVX-NE-CONVERT\n+\tvcvtneoph2ps\txmm6, XMMWORD PTR [r9]\t #AVX-NE-CONVERT\n+\tvcvtneoph2ps\txmm6, XMMWORD PTR [rcx+2032]\t #AVX-NE-CONVERT Disp32(f0070000)\n+\tvcvtneoph2ps\txmm6, XMMWORD PTR [rdx-2048]\t #AVX-NE-CONVERT Disp32(00f8ffff)\n+\tvcvtneoph2ps\tymm6, YMMWORD PTR [rbp+r14*8+0x10000000]\t #AVX-NE-CONVERT\n+\tvcvtneoph2ps\tymm6, YMMWORD PTR [r9]\t #AVX-NE-CONVERT\n+\tvcvtneoph2ps\tymm6, YMMWORD PTR [rcx+4064]\t #AVX-NE-CONVERT Disp32(e00f0000)\n+\tvcvtneoph2ps\tymm6, YMMWORD PTR [rdx-4096]\t #AVX-NE-CONVERT Disp32(00f0ffff)\n+\tvcvtneps2bf16\txmm6, xmm5\t #AVX-NE-CONVERT\n+\t{evex} vcvtneps2bf16\txmm6, xmm5\t #AVX-NE-CONVERT\n+\t{vex} vcvtneps2bf16\txmm6, xmm5\t #AVX-NE-CONVERT\n+\t{vex3} vcvtneps2bf16\txmm6, xmm5\t #AVX-NE-CONVERT\n+\tvcvtneps2bf16\txmm6, ymm5\t #AVX-NE-CONVERT\n+\t{evex} vcvtneps2bf16\txmm6, ymm5\t #AVX-NE-CONVERT\n+\t{vex} vcvtneps2bf16\txmm6, ymm5\t #AVX-NE-CONVERT\n+\t{vex3} vcvtneps2bf16\txmm6, ymm5\t #AVX-NE-CONVERT\n+\tvcvtneps2bf16\txmm6, XMMWORD PTR [rbp+r14*8+0x10000000]\t #AVX-NE-CONVERT\n+\t{evex} vcvtneps2bf16\txmm6, XMMWORD PTR [rbp+r14*8+0x10000000]\t #AVX-NE-CONVERT\n+\t{vex} vcvtneps2bf16\txmm6, XMMWORD PTR [rbp+r14*8+0x10000000]\t #AVX-NE-CONVERT\n+\t{vex3} vcvtneps2bf16\txmm6, XMMWORD PTR [rbp+r14*8+0x10000000]\t #AVX-NE-CONVERT\n+\tvcvtneps2bf16\txmm6, XMMWORD PTR [r9]\t #AVX-NE-CONVERT\n+\t{evex} vcvtneps2bf16\txmm6, XMMWORD PTR [r9]\t #AVX-NE-CONVERT\n+\t{vex} vcvtneps2bf16\txmm6, XMMWORD PTR [r9]\t #AVX-NE-CONVERT\n+\t{vex3} vcvtneps2bf16\txmm6, XMMWORD PTR [r9]\t #AVX-NE-CONVERT\n+\tvcvtneps2bf16\txmm6, XMMWORD PTR [rcx+2032]\t #AVX-NE-CONVERT Disp32(f0070000)\n+\t{evex} vcvtneps2bf16\txmm6, XMMWORD PTR [rcx+2032]\t #AVX-NE-CONVERT Disp32(f0070000)\n+\t{vex} vcvtneps2bf16\txmm6, XMMWORD PTR [rcx+2032]\t #AVX-NE-CONVERT Disp32(f0070000)\n+\t{vex3} vcvtneps2bf16\txmm6, XMMWORD PTR [rcx+2032]\t #AVX-NE-CONVERT Disp32(f0070000)\n+\tvcvtneps2bf16\txmm6, XMMWORD PTR [rdx-2048]\t #AVX-NE-CONVERT Disp32(00f8ffff)\n+\t{evex} vcvtneps2bf16\txmm6, XMMWORD PTR [rdx-2048]\t #AVX-NE-CONVERT Disp32(00f8ffff)\n+\t{vex} vcvtneps2bf16\txmm6, XMMWORD PTR [rdx-2048]\t #AVX-NE-CONVERT Disp32(00f8ffff)\n+\t{vex3} vcvtneps2bf16\txmm6, XMMWORD PTR [rdx-2048]\t #AVX-NE-CONVERT Disp32(00f8ffff)\n+\tvcvtneps2bf16\txmm6, YMMWORD PTR [rcx+4064]\t #AVX-NE-CONVERT Disp32(e00f0000)\n+\t{evex} vcvtneps2bf16\txmm6, YMMWORD PTR [rcx+4064]\t #AVX-NE-CONVERT Disp32(e00f0000)\n+\t{vex} vcvtneps2bf16\txmm6, YMMWORD PTR [rcx+4064]\t #AVX-NE-CONVERT Disp32(e00f0000)\n+\t{vex3} vcvtneps2bf16\txmm6, YMMWORD PTR [rcx+4064]\t #AVX-NE-CONVERT Disp32(e00f0000)\n+\tvcvtneps2bf16\txmm6, YMMWORD PTR [rdx-4096]\t #AVX-NE-CONVERT Disp32(00f0ffff)\n+\t{evex} vcvtneps2bf16\txmm6, YMMWORD PTR [rdx-4096]\t #AVX-NE-CONVERT Disp32(00f0ffff)\n+\t{vex} vcvtneps2bf16\txmm6, YMMWORD PTR [rdx-4096]\t #AVX-NE-CONVERT Disp32(00f0ffff)\n+\t{vex3} vcvtneps2bf16\txmm6, YMMWORD PTR [rdx-4096]\t #AVX-NE-CONVERT Disp32(00f0ffff)\ndiff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c\nindex ab43d0cd8e..4739685ff3 100644\n--- a/opcodes/i386-dis.c\n+++ b/opcodes/i386-dis.c\n@@ -942,6 +942,8 @@ enum\n MOD_VEX_0F385E_X86_64_P_3_W_0,\n MOD_VEX_0F388C,\n MOD_VEX_0F388E,\n+ MOD_VEX_0F38B0,\n+ MOD_VEX_0F38B1,\n MOD_VEX_0F3A30_L_0,\n MOD_VEX_0F3A31_L_0,\n MOD_VEX_0F3A32_L_0,\n@@ -1138,6 +1140,9 @@ enum\n PREFIX_VEX_0F3851_W_0,\n PREFIX_VEX_0F385C_X86_64,\n PREFIX_VEX_0F385E_X86_64,\n+ PREFIX_VEX_0F3872,\n+ PREFIX_VEX_0F38B0_M_1_W_0,\n+ PREFIX_VEX_0F38B1_M_1_W_0,\n PREFIX_VEX_0F38F5_L_0,\n PREFIX_VEX_0F38F6_L_0,\n PREFIX_VEX_0F38F7_L_0,\n@@ -1554,8 +1559,11 @@ enum\n VEX_W_0F385E_X86_64_P_1,\n VEX_W_0F385E_X86_64_P_2,\n VEX_W_0F385E_X86_64_P_3,\n+ VEX_W_0F3872_P_1,\n VEX_W_0F3878,\n VEX_W_0F3879,\n+ VEX_W_0F38B0_M_1,\n+ VEX_W_0F38B1_M_1,\n VEX_W_0F38B4,\n VEX_W_0F38B5,\n VEX_W_0F38CF,\n@@ -4075,6 +4083,27 @@ static const struct dis386 prefix_table[][4] = {\n { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_3) },\n },\n \n+ /* PREFIX_VEX_0F3872 */\n+ {\n+ { Bad_Opcode },\n+ { VEX_W_TABLE (VEX_W_0F3872_P_1) },\n+ },\n+\n+ /* PREFIX_VEX_0F38B0_M_1_W_0 */\n+ {\n+ { \"vcvtneoph2ps\", { XM, Mx }, 0 },\n+ { \"vcvtneebf162ps\", { XM, Mx }, 0 },\n+ { \"vcvtneeph2ps\", { XM, Mx }, 0 },\n+ { \"vcvtneobf162ps\", { XM, Mx }, 0 },\n+ },\n+\n+ /* PREFIX_VEX_0F38B1_M_1_W_0 */\n+ {\n+ { Bad_Opcode },\n+ { \"vbcstnebf162ps\", { XM, Ew }, 0 },\n+ { \"vbcstnesh2ps\", { XM, Ew }, 0 },\n+ },\n+ \n /* PREFIX_VEX_0F38F5_L_0 */\n {\n { \"bzhiS\",\t\t{ Gdq, Edq, VexGdq }, 0 },\n@@ -6397,7 +6426,7 @@ static const struct dis386 vex_table[][256] = {\n /* 70 */\n { Bad_Opcode },\n { Bad_Opcode },\n- { Bad_Opcode },\n+ { PREFIX_TABLE (PREFIX_VEX_0F3872) },\n { Bad_Opcode },\n { Bad_Opcode },\n { Bad_Opcode },\n@@ -6467,8 +6496,8 @@ static const struct dis386 vex_table[][256] = {\n { \"vfnmsub213p%XW\", { XM, Vex, EXx }, PREFIX_DATA },\n { \"vfnmsub213s%XW\", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },\n /* b0 */\n- { Bad_Opcode },\n- { Bad_Opcode },\n+ { MOD_TABLE (MOD_VEX_0F38B0) },\n+ { MOD_TABLE (MOD_VEX_0F38B1) },\n { Bad_Opcode },\n { Bad_Opcode },\n { VEX_W_TABLE (VEX_W_0F38B4) },\n@@ -7778,6 +7807,10 @@ static const struct dis386 vex_w_table[][2] = {\n /* VEX_W_0F385E_X86_64_P_3 */\n { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_3_W_0) },\n },\n+ {\n+ /* VEX_W_0F3872_P_1 */\n+ { \"%XVvcvtneps2bf16%XY\", { XMM, EXx }, 0 },\n+ },\n {\n /* VEX_W_0F3878 */\n { \"%XEvpbroadcastb\",\t{ XM, EXb }, PREFIX_DATA },\n@@ -7786,6 +7819,14 @@ static const struct dis386 vex_w_table[][2] = {\n /* VEX_W_0F3879 */\n { \"%XEvpbroadcastw\",\t{ XM, EXw }, PREFIX_DATA },\n },\n+ {\n+ /* VEX_W_0F38B0_M_1 */\n+ { PREFIX_TABLE (PREFIX_VEX_0F38B0_M_1_W_0) },\n+ },\n+ {\n+ /* VEX_W_0F38B1_M_1 */\n+ { PREFIX_TABLE (PREFIX_VEX_0F38B1_M_1_W_0) },\n+ },\n {\n /* VEX_W_0F38B4 */\n { Bad_Opcode },\n@@ -8611,6 +8652,14 @@ static const struct dis386 mod_table[][2] = {\n /* MOD_VEX_0F388E */\n { \"vpmaskmov%DQ\",\t{ Mx, Vex, XM }, PREFIX_DATA },\n },\n+ {\n+ /* MOD_VEX_0F38B0 */\n+ { VEX_W_TABLE (VEX_W_0F38B0_M_1) },\n+ },\n+ {\n+ /* MOD_VEX_0F38B1 */\n+ { VEX_W_TABLE (VEX_W_0F38B1_M_1) },\n+ },\n {\n /* MOD_VEX_0F3A30_L_0 */\n { Bad_Opcode },\ndiff --git a/opcodes/i386-gen.c b/opcodes/i386-gen.c\nindex b820104234..fc23332298 100644\n--- a/opcodes/i386-gen.c\n+++ b/opcodes/i386-gen.c\n@@ -257,6 +257,8 @@ static initializer cpu_flag_init[] =\n \"CpuWRMSRNS\" },\n { \"CPU_MSRLIST_FLAGS\",\n \"CpuMSRLIST\" },\n+ { \"CPU_AVX_NE_CONVERT_FLAGS\",\n+ \"CPU_AVX2_FLAGS|CpuAVX_NE_CONVERT\" },\n { \"CPU_IAMCU_FLAGS\",\n \"Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuIAMCU\" },\n { \"CPU_ADX_FLAGS\",\n@@ -384,7 +386,7 @@ static initializer cpu_flag_init[] =\n { \"CPU_ANY_AVX_FLAGS\",\n \"CPU_ANY_AVX2_FLAGS|CpuF16C|CpuFMA|CpuFMA4|CpuXOP|CpuAVX\" },\n { \"CPU_ANY_AVX2_FLAGS\",\n- \"CPU_ANY_AVX512F_FLAGS|CpuAVX2|CpuAVX_VNNI|CpuAVX_IFMA|CpuAVX_VNNI_INT8\" },\n+ \"CPU_ANY_AVX512F_FLAGS|CpuAVX2|CpuAVX_VNNI|CpuAVX_IFMA|CpuAVX_VNNI_INT8|CpuAVX_NE_CONVERT\" },\n { \"CPU_ANY_AVX512F_FLAGS\",\n \"CpuAVX512F|CpuAVX512CD|CpuAVX512ER|CpuAVX512PF|CpuAVX512DQ|CPU_ANY_AVX512BW_FLAGS|CpuAVX512VL|CpuAVX512IFMA|CpuAVX512VBMI|CpuAVX512_4FMAPS|CpuAVX512_4VNNIW|CpuAVX512_VPOPCNTDQ|CpuAVX512_VBMI2|CpuAVX512_VNNI|CpuAVX512_BITALG|CpuAVX512_BF16|CpuAVX512_VP2INTERSECT\" },\n { \"CPU_ANY_AVX512CD_FLAGS\",\n@@ -465,6 +467,8 @@ static initializer cpu_flag_init[] =\n \"CpuWRMSRNS\" },\n { \"CPU_ANY_MSRLIST_FLAGS\",\n \"CpuMSRLIST\" },\n+ { \"CPU_ANY_AVX_NE_CONVERT_FLAGS\",\n+ \"CpuAVX_NE_CONVERT\" },\n };\n \n static initializer operand_type_init[] =\n@@ -672,6 +676,7 @@ static bitfield cpu_flags[] =\n BITFIELD (CpuCMPCCXADD),\n BITFIELD (CpuWRMSRNS),\n BITFIELD (CpuMSRLIST),\n+ BITFIELD (CpuAVX_NE_CONVERT),\n BITFIELD (CpuMWAITX),\n BITFIELD (CpuCLZERO),\n BITFIELD (CpuOSPKE),\ndiff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h\nindex a409b10ca1..78fc019c3c 100644\n--- a/opcodes/i386-opc.h\n++ 100 102k 100 102k 100 150 1827k 2678 --:--:-- --:--:-- --:--:-- 1830k + b/opcodes/i386-opc.h\n@@ -221,6 +221,8 @@ enum\n CpuWRMSRNS,\n /* Intel MSRLIST Instructions support required. */\n CpuMSRLIST,\n+ /* Intel AVX NE CONVERT Instructions support required. */\n+ CpuAVX_NE_CONVERT,\n /* mwaitx instruction required */\n CpuMWAITX,\n /* Clzero instruction required */\n@@ -408,6 +410,7 @@ typedef union i386_cpu_flags\n unsigned int cpucmpccxadd:1;\n unsigned int cpuwrmsrns:1;\n unsigned int cpumsrlist:1;\n+ unsigned int cpuavx_ne_convert:1;\n unsigned int cpumwaitx:1;\n unsigned int cpuclzero:1;\n unsigned int cpuospke:1;\ndiff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl\nindex 3238c4fc2e..2fccbfcf77 100644\n--- a/opcodes/i386-opc.tbl\n+++ b/opcodes/i386-opc.tbl\n@@ -3056,6 +3056,18 @@ vdpbf16ps, 0xf352, None, CpuAVX512_BF16, Modrm|Space0F38|VexVVVV|Masking=3|VexW0\n \n // AVX512_BF16 instructions end.\n \n+// AVX-NE-CONVERT instructions.\n+\n+vbcstnebf162ps, 0xf3b1, None, CpuAVX_NE_CONVERT, Modrm|Vex|Space0F38|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Word|Unspecified|BaseIndex, RegXMM|RegYMM }\n+vbcstnesh2ps, 0x66b1, None, CpuAVX_NE_CONVERT, Modrm|Vex|Space0F38|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Word|Unspecified|BaseIndex, RegXMM|RegYMM }\n+vcvtneebf162ps, 0xf3b0, None, CpuAVX_NE_CONVERT, Modrm|Vex|Space0F38|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Ymmword|Unspecified|BaseIndex, RegXMM|RegYMM }\n+vcvtneeph2ps, 0x66b0, None, CpuAVX_NE_CONVERT, Modrm|Vex|Space0F38|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Ymmword|Unspecified|BaseIndex, RegXMM|RegYMM }\n+vcvtneobf162ps, 0xf2b0, None, CpuAVX_NE_CONVERT, Modrm|Vex|Space0F38|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Ymmword|Unspecified|BaseIndex, RegXMM|RegYMM }\n+vcvtneoph2ps, 0xb0, None, CpuAVX_NE_CONVERT, Modrm|Vex|Space0F38|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Ymmword|Unspecified|BaseIndex, RegXMM|RegYMM }\n+vcvtneps2bf16, 0xf372, None, CpuAVX_NE_CONVERT, Modrm||Space0F38|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|, { , RegXMM }\n+\n+// AVX-NE-CONVERT instructions end.\n+\n // ENQCMD instructions.\n \n enqcmd, 0xf20f38f8, None, CpuENQCMD, Modrm|AddrPrefixOpReg, { Unspecified|BaseIndex, Reg16|Reg32|Reg64 }\n","prefixes":["2/2"]}+ exit 1 Build step 'Execute shell' marked build as failure Finished: FAILURE