Started by user snail Running as SYSTEM [EnvInject] - Loading node environment variables. Building remotely on docker-jenkins-agent in workspace /home/jenkins/agent/workspace/binutils-gdb [WS-CLEANUP] Deleting project workspace... [WS-CLEANUP] Deferred wipeout is used... [WS-CLEANUP] Done The recommended git tool is: NONE using credential 0adb5fc7-caa2-429d-97d2-c7fa2fa1d884 Cloning the remote Git repository Using shallow clone with depth 1 Avoid fetching tags Cloning repository git@github.com:wangliu-iscas/binutils-gdb.git/ > git init /home/jenkins/agent/workspace/binutils-gdb # timeout=10 Fetching upstream changes from git@github.com:wangliu-iscas/binutils-gdb.git/ > git --version # timeout=10 > git --version # 'git version 2.37.2' using GIT_SSH to set credentials patchwork github wangliu-iscas git ssh key Verifying host key using known hosts file, will automatically accept unseen keys > git fetch --no-tags --force --progress --depth=1 -- git@github.com:wangliu-iscas/binutils-gdb.git/ +refs/heads/*:refs/remotes/origin/* # timeout=10 > git config remote.origin.url git@github.com:wangliu-iscas/binutils-gdb.git/ # timeout=10 > git config --add remote.origin.fetch +refs/heads/*:refs/remotes/origin/* # timeout=10 Avoid second fetch > git rev-parse refs/remotes/origin/master^{commit} # timeout=10 Checking out Revision 60095ba3b8f8ba26a6389dded732fa446422c98f (refs/remotes/origin/master) > git config core.sparsecheckout # timeout=10 > git checkout -f 60095ba3b8f8ba26a6389dded732fa446422c98f # timeout=10 Commit message: "Automatic date update in version.in" > git rev-list --no-walk 60095ba3b8f8ba26a6389dded732fa446422c98f # timeout=10 [EnvInject] - Mask passwords that will be passed as build parameters. [EnvInject] - Executing scripts and injecting environment variables after the SCM step. [EnvInject] - Injecting as environment variables the properties content GITHUB_REPO=https://github.com/wangliu-iscas/ PATCHWORK_URL=https://patchwork.plctlab.org [EnvInject] - Variables injected successfully. [binutils-gdb] $ /usr/bin/env bash /tmp/jenkins2109134673540936569.sh + git config pw.server https://patchwork.plctlab.org/api/1.2/ + git config pw.project binutils-gdb + git config pw.token [*******] ++ date +%Y-%m + now_date=2022-10 ++ date +%Y + now_date_year=2022 + bundle_name=binutils-gdb_2022-10 ++ curl -s -H 'Authorization: Token [*******]' 'https://patchwork.plctlab.org/api/1.2/bundles/?project=binutils-gdb&per_page=999' + bundle_response='[{"id":6,"url":"https://patchwork.plctlab.org/api/1.2/bundles/6/","web_url":"https://patchwork.plctlab.org/bundle/patchwork-bot/binutils-gdb_2022-10/","project":{"id":2,"url":"https://patchwork.plctlab.org/api/1.2/projects/2/","name":"binutils-gdb","link_name":"binutils-gdb","list_id":"binutils.sourceware.org","list_email":"binutils@sourceware.org","web_url":"https://github.com/wangliu-iscas/Patchwork-Bundles/blob/main/binutils-gdb.md","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"name":"binutils-gdb_2022-10","owner":{"id":3,"url":"https://patchwork.plctlab.org/api/1.2/users/3/","username":"patchwork-bot","first_name":"","last_name":"","email":"ouuuleilei@gmail.com"},"patches":[{"id":1592,"url":"https://patchwork.plctlab.org/api/1.2/patches/1592/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/385d01fd-7e57-1f3f-1bae-30aa0c313d63@suse.com/","msgid":"<385d01fd-7e57-1f3f-1bae-30aa0c313d63@suse.com>","list_archive_url":null,"date":"2022-09-30T11:59:45","name":"[3/4] RISC-V/gas: don'\''t open-code insn_length()","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/385d01fd-7e57-1f3f-1bae-30aa0c313d63@suse.com/mbox/"},{"id":1594,"url":"https://patchwork.plctlab.org/api/1.2/patches/1594/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f5757acf-7b90-a0e3-5eea-3b97cc226930@suse.com/","msgid":"","list_archive_url":null,"date":"2022-09-30T12:00:12","name":"[4/4] RISC-V/gas: allow generating up to 176-bit instructions with .insn","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f5757acf-7b90-a0e3-5eea-3b97cc226930@suse.com/mbox/"},{"id":1596,"url":"https://patchwork.plctlab.org/api/1.2/patches/1596/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930140503.38233-1-chigot@adacore.com/","msgid":"<20220930140503.38233-1-chigot@adacore.com>","list_archive_url":null,"date":"2022-09-30T14:05:03","name":"ld/testsuite: consistently add board_ldflags when linking with GCC","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930140503.38233-1-chigot@adacore.com/mbox/"},{"id":1619,"url":"https://patchwork.plctlab.org/api/1.2/patches/1619/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221001014451.532772-1-maskray@google.com/","msgid":"<20221001014451.532772-1-maskray@google.com>","list_archive_url":null,"date":"2022-10-01T01:44:51","name":"gold, dwp: support zstd compressed input debug sections [PR 29641]","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221001014451.532772-1-maskray@google.com/mbox/"},{"id":1620,"url":"https://patchwork.plctlab.org/api/1.2/patches/1620/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221001023846.590825-1-maskray@google.com/","msgid":"<20221001023846.590825-1-maskray@google.com>","list_archive_url":null,"date":"2022-10-01T02:38:46","name":"gold: add --compress-debug-sections=zstd [PR 29641]","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221001023846.590825-1-maskray@google.com/mbox/"},{"id":1623,"url":"https://patchwork.plctlab.org/api/1.2/patches/1623/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b4477c7f666bdeb7f8e998633c7b0cb62310b9ef.1664599545.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-01T04:45:52","name":"[RFC,1/1] RISC-V: Implement common register pair framework","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b4477c7f666bdeb7f8e998633c7b0cb62310b9ef.1664599545.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1625,"url":"https://patchwork.plctlab.org/api/1.2/patches/1625/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/53a265a1f14d17a6f7b106082f610994c5d546e0.1664602025.git.research_trasio@irq.a4lg.com/","msgid":"<53a265a1f14d17a6f7b106082f610994c5d546e0.1664602025.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-01T05:27:31","name":"[RFC,1/1] RISC-V: Implement extension variants","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/53a265a1f14d17a6f7b106082f610994c5d546e0.1664602025.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1626,"url":"https://patchwork.plctlab.org/api/1.2/patches/1626/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8db04962aba9c780f133840a8934353a58f223fe.1664602716.git.research_trasio@irq.a4lg.com/","msgid":"<8db04962aba9c780f133840a8934353a58f223fe.1664602716.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-01T05:39:26","name":"[1/1] RISC-V: Move supervisor instructions after all unprivileged ones","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8db04962aba9c780f133840a8934353a58f223fe.1664602716.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1627,"url":"https://patchwork.plctlab.org/api/1.2/patches/1627/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221001062057.681440-1-maskray@google.com/","msgid":"<20221001062057.681440-1-maskray@google.com>","list_archive_url":null,"date":"2022-10-01T06:20:57","name":"readelf: support zstd compressed debug sections [PR 29640]","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221001062057.681440-1-maskray@google.com/mbox/"},{"id":1631,"url":"https://patchwork.plctlab.org/api/1.2/patches/1631/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/619f112539c0bdecd58e25664f1250a3479a37f5.1664707612.git.aburgess@redhat.com/","msgid":"<619f112539c0bdecd58e25664f1250a3479a37f5.1664707612.git.aburgess@redhat.com>","list_archive_url":null,"date":"2022-10-02T10:47:52","name":"[PATCHv2,2/2] opcodes/arm: add disassembler styling for arm","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/619f112539c0bdecd58e25664f1250a3479a37f5.1664707612.git.aburgess@redhat.com/mbox/"},{"id":1635,"url":"https://patchwork.plctlab.org/api/1.2/patches/1635/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221002185433.gl7dvytfh5wthifx@lug-owl.de/","msgid":"<20221002185433.gl7dvytfh5wthifx@lug-owl.de>","list_archive_url":null,"date":"2022-10-02T18:54:33","name":"diagnostics.h: GCC 13 got -Wself-move, breaks GDB build","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221002185433.gl7dvytfh5wthifx@lug-owl.de/mbox/"},{"id":1637,"url":"https://patchwork.plctlab.org/api/1.2/patches/1637/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003014313.28766-1-mark@harmstone.com/","msgid":"<20221003014313.28766-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-03T01:43:12","name":"[1/2] ld: Add --pdb option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003014313.28766-1-mark@harmstone.com/mbox/"},{"id":1638,"url":"https://patchwork.plctlab.org/api/1.2/patches/1638/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003014313.28766-2-mark@harmstone.com/","msgid":"<20221003014313.28766-2-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-03T01:43:13","name":"[2/2] ld: Add minimal pdb generation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003014313.28766-2-mark@harmstone.com/mbox/"},{"id":1640,"url":"https://patchwork.plctlab.org/api/1.2/patches/1640/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/597ed978-d121-220c-b56b-2ffb94bd091c@suse.cz/","msgid":"<597ed978-d121-220c-b56b-2ffb94bd091c@suse.cz>","list_archive_url":null,"date":"2022-10-03T07:50:38","name":"[1/2] refactor usage of compressed_debug_section_type","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/597ed978-d121-220c-b56b-2ffb94bd091c@suse.cz/mbox/"},{"id":1641,"url":"https://patchwork.plctlab.org/api/1.2/patches/1641/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b8acdd83-f33a-74b8-e21a-23719a0b1a60@suse.cz/","msgid":"","list_archive_url":null,"date":"2022-10-03T07:50:44","name":"[2/2] add --enable-default-compressed-debug-sections-algorithm configure option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b8acdd83-f33a-74b8-e21a-23719a0b1a60@suse.cz/mbox/"},{"id":1642,"url":"https://patchwork.plctlab.org/api/1.2/patches/1642/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003101328.1790113-1-aburgess@redhat.com/","msgid":"<20221003101328.1790113-1-aburgess@redhat.com>","list_archive_url":null,"date":"2022-10-03T10:13:28","name":"opcodes/riscv: style csr names as registers","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003101328.1790113-1-aburgess@redhat.com/mbox/"},{"id":1643,"url":"https://patchwork.plctlab.org/api/1.2/patches/1643/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7ba14fc4472ce97d4f7a4433cad8a571e89f82f4.1664793840.git.research_trasio@irq.a4lg.com/","msgid":"<7ba14fc4472ce97d4f7a4433cad8a571e89f82f4.1664793840.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-03T10:43:59","name":"[v3,1/6] RISC-V: Fix immediates to have \"immediate\" style","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7ba14fc4472ce97d4f7a4433cad8a571e89f82f4.1664793840.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1644,"url":"https://patchwork.plctlab.org/api/1.2/patches/1644/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a498bec37c1fd1dcda57cbf95e5f8cfba09b31d3.1664793840.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-03T10:44:00","name":"[v3,2/6] RISC-V: Fix printf argument types corresponding %x","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a498bec37c1fd1dcda57cbf95e5f8cfba09b31d3.1664793840.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1647,"url":"https://patchwork.plctlab.org/api/1.2/patches/1647/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0002ea716713ace4998a33dde0b81f4f890d10bf.1664793840.git.research_trasio@irq.a4lg.com/","msgid":"<0002ea716713ace4998a33dde0b81f4f890d10bf.1664793840.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-03T10:44:01","name":"[v3,3/6] RISC-V: Optimize riscv_disassemble_data printf","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0002ea716713ace4998a33dde0b81f4f890d10bf.1664793840.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1646,"url":"https://patchwork.plctlab.org/api/1.2/patches/1646/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c65fc3e9aa58965d6768a28c9fd7467fea9897a5.1664793840.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-03T10:44:02","name":"[v3,4/6] RISC-V: Print comma and tabs as the \"text\" style","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c65fc3e9aa58965d6768a28c9fd7467fea9897a5.1664793840.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1648,"url":"https://patchwork.plctlab.org/api/1.2/patches/1648/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5abe1d8a7694417b990e11d8f6cd6789573872e5.1664793840.git.research_trasio@irq.a4lg.com/","msgid":"<5abe1d8a7694417b990e11d8f6cd6789573872e5.1664793840.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-03T10:44:03","name":"[v3,5/6] RISC-V: Fix T-Head immediate types on printing","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5abe1d8a7694417b990e11d8f6cd6789573872e5.1664793840.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1649,"url":"https://patchwork.plctlab.org/api/1.2/patches/1649/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0b68af932117258c908db62cf87c3a15d3cdec41.1664793840.git.research_trasio@irq.a4lg.com/","msgid":"<0b68af932117258c908db62cf87c3a15d3cdec41.1664793840.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-03T10:44:04","name":"[v3,6/6] RISC-V: Print XTheadMemPair literal as \"immediate\"","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0b68af932117258c908db62cf87c3a15d3cdec41.1664793840.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1656,"url":"https://patchwork.plctlab.org/api/1.2/patches/1656/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/87lepxcd6x.fsf@redhat.com/","msgid":"<87lepxcd6x.fsf@redhat.com>","list_archive_url":null,"date":"2022-10-03T12:19:02","name":"Commit: readelf: Do not load section data from offset 0","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/87lepxcd6x.fsf@redhat.com/mbox/"},{"id":1659,"url":"https://patchwork.plctlab.org/api/1.2/patches/1659/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e0d369d419da9c0441f415da7f54352aead8f655.1664707612.git.aburgess@redhat.com/","msgid":"","list_archive_url":null,"date":"2022-10-03T16:37:36","name":"[PATCHv2,1/2] opcodes/arm: use '\''@'\'' consistently for the comment character","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e0d369d419da9c0441f415da7f54352aead8f655.1664707612.git.aburgess@redhat.com/mbox/"},{"id":1660,"url":"https://patchwork.plctlab.org/api/1.2/patches/1660/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003165848.11142-1-palmer@rivosinc.com/","msgid":"<20221003165848.11142-1-palmer@rivosinc.com>","list_archive_url":null,"date":"2022-10-03T16:58:48","name":"gas: NEWS: Mention the T-Head extensions that were recently added","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003165848.11142-1-palmer@rivosinc.com/mbox/"},{"id":1671,"url":"https://patchwork.plctlab.org/api/1.2/patches/1671/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/YzvrMEdkXjIn5Lfz@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-04T08:13:36","name":"Support objcopy changing compression to or from zstd","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/YzvrMEdkXjIn5Lfz@squeak.grove.modra.org/mbox/"},{"id":1673,"url":"https://patchwork.plctlab.org/api/1.2/patches/1673/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0bc857d306bb7c8130e5328dbe6b9ed2fed3ef87.1664873933.git.research_trasio@irq.a4lg.com/","msgid":"<0bc857d306bb7c8130e5328dbe6b9ed2fed3ef87.1664873933.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-04T08:59:07","name":"[1/2] RISC-V: Fix buffer overflow on print_insn_riscv","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0bc857d306bb7c8130e5328dbe6b9ed2fed3ef87.1664873933.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1672,"url":"https://patchwork.plctlab.org/api/1.2/patches/1672/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/89612fe01d902007bf84a7dfb0df5f85d5c166e4.1664873933.git.research_trasio@irq.a4lg.com/","msgid":"<89612fe01d902007bf84a7dfb0df5f85d5c166e4.1664873933.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-04T08:59:08","name":"[2/2] gdb/riscv: Fix buffer overflow on riscv_insn::fetch_instruction","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/89612fe01d902007bf84a7dfb0df5f85d5c166e4.1664873933.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1676,"url":"https://patchwork.plctlab.org/api/1.2/patches/1676/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fc849c94f4adcac1c4ccc5508c7a145a2f13b2a9.1664876744.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-04T09:45:49","name":"[v2,1/2] RISC-V: Fix buffer overflow on print_insn_riscv","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fc849c94f4adcac1c4ccc5508c7a145a2f13b2a9.1664876744.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1677,"url":"https://patchwork.plctlab.org/api/1.2/patches/1677/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4eb6e59ae2e790dbbf2bc92477edd281648d8814.1664876744.git.research_trasio@irq.a4lg.com/","msgid":"<4eb6e59ae2e790dbbf2bc92477edd281648d8814.1664876744.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-04T09:45:50","name":"[v2,2/2] gdb/riscv: Partial support for instructions up to 176-bits","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4eb6e59ae2e790dbbf2bc92477edd281648d8814.1664876744.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1678,"url":"https://patchwork.plctlab.org/api/1.2/patches/1678/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ebf16f9e1f45115d0793952ccb4a94d4233303f9.1664882725.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-04T11:25:56","name":"[v3,1/2] RISC-V: Fix buffer overflow on print_insn_riscv","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ebf16f9e1f45115d0793952ccb4a94d4233303f9.1664882725.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1679,"url":"https://patchwork.plctlab.org/api/1.2/patches/1679/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/83464b09b8649525259c69c853dfa2c9575a204b.1664882725.git.research_trasio@irq.a4lg.com/","msgid":"<83464b09b8649525259c69c853dfa2c9575a204b.1664882725.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-04T11:25:57","name":"[v3,2/2] gdb/riscv: Partial support for instructions up to 176-bit","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/83464b09b8649525259c69c853dfa2c9575a204b.1664882725.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1681,"url":"https://patchwork.plctlab.org/api/1.2/patches/1681/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ffa9c1d7-e8c2-a62b-ef3e-b565c0ffbe5b@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-04T13:56:27","name":"RISC-V: Zicbo{m,p,z} adjustments to riscv_multi_subset_supports_ext()","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ffa9c1d7-e8c2-a62b-ef3e-b565c0ffbe5b@suse.com/mbox/"},{"id":1690,"url":"https://patchwork.plctlab.org/api/1.2/patches/1690/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221004161720.1963953-1-vladimir.mezentsev@oracle.com/","msgid":"<20221004161720.1963953-1-vladimir.mezentsev@oracle.com>","list_archive_url":null,"date":"2022-10-04T16:17:20","name":"gprofng: fix build with --enable-pgo-build=lto","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221004161720.1963953-1-vladimir.mezentsev@oracle.com/mbox/"},{"id":1691,"url":"https://patchwork.plctlab.org/api/1.2/patches/1691/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c0211bc9c57be6c79c6d878ce147f63b657f461d.camel@espressif.com/","msgid":"","list_archive_url":null,"date":"2022-10-04T16:22:05","name":"bfd: xtensa: fix __stop_SECTION literal drop,","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c0211bc9c57be6c79c6d878ce147f63b657f461d.camel@espressif.com/mbox/"},{"id":1702,"url":"https://patchwork.plctlab.org/api/1.2/patches/1702/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5f482299-6c60-b2b3-9abe-f4a55a5a26c5@univ-grenoble-alpes.fr/","msgid":"<5f482299-6c60-b2b3-9abe-f4a55a5a26c5@univ-grenoble-alpes.fr>","list_archive_url":null,"date":"2022-10-04T20:03:20","name":"[RFC] bfd: use bfd_vma for the 64-bit version of put[lb] and get[lb]","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5f482299-6c60-b2b3-9abe-f4a55a5a26c5@univ-grenoble-alpes.fr/mbox/"},{"id":1711,"url":"https://patchwork.plctlab.org/api/1.2/patches/1711/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Yz0Gsxdxe0TePbJT@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-05T04:23:15","name":"PR29647, objdump -S looping","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Yz0Gsxdxe0TePbJT@squeak.grove.modra.org/mbox/"},{"id":1712,"url":"https://patchwork.plctlab.org/api/1.2/patches/1712/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/02d747d2-f57b-0fb5-b893-842b6cc41f2f@suse.com/","msgid":"<02d747d2-f57b-0fb5-b893-842b6cc41f2f@suse.com>","list_archive_url":null,"date":"2022-10-05T07:20:47","name":"[v3,1/7] x86: constify parse_insn()'\''s input","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/02d747d2-f57b-0fb5-b893-842b6cc41f2f@suse.com/mbox/"},{"id":1713,"url":"https://patchwork.plctlab.org/api/1.2/patches/1713/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/925cb740-4e1b-abc4-8526-aaab6faae5e1@suse.com/","msgid":"<925cb740-4e1b-abc4-8526-aaab6faae5e1@suse.com>","list_archive_url":null,"date":"2022-10-05T07:22:19","name":"[v3,2/7] x86: introduce Pass2 insn attribute","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/925cb740-4e1b-abc4-8526-aaab6faae5e1@suse.com/mbox/"},{"id":1714,"url":"https://patchwork.plctlab.org/api/1.2/patches/1714/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e16d3e78-39ca-f715-508f-a4104b8ab9a9@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-05T07:23:51","name":"[v3,3/7] x86: re-work insn/suffix recognition","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e16d3e78-39ca-f715-508f-a4104b8ab9a9@suse.com/mbox/"},{"id":1715,"url":"https://patchwork.plctlab.org/api/1.2/patches/1715/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e4e4b80b-794c-7485-1997-685adab8fb27@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-05T07:24:20","name":"[v3,4/7] x86-64: further re-work insn/suffix recognition to also cover MOVSL","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e4e4b80b-794c-7485-1997-685adab8fb27@suse.com/mbox/"},{"id":1716,"url":"https://patchwork.plctlab.org/api/1.2/patches/1716/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/540678fc-8bff-ec68-c97c-478d2631998c@suse.com/","msgid":"<540678fc-8bff-ec68-c97c-478d2631998c@suse.com>","list_archive_url":null,"date":"2022-10-05T07:24:55","name":"[v3,5/7] ix86: don'\''t recognize/derive Q suffix in the common case","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/540678fc-8bff-ec68-c97c-478d2631998c@suse.com/mbox/"},{"id":1718,"url":"https://patchwork.plctlab.org/api/1.2/patches/1718/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e4692495-7d3d-074d-14f9-364d4a9a998c@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-05T07:25:25","name":"[v3,6/7] x86-64: allow HLE store of accumulator to absolute 32-bit address","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e4692495-7d3d-074d-14f9-364d4a9a998c@suse.com/mbox/"},{"id":1717,"url":"https://patchwork.plctlab.org/api/1.2/patches/1717/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e8014ebd-d16b-17a7-9f34-3700fc164136@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-05T07:25:57","name":"[v3,7/7] x86: move bad-use-of-TLS-reloc check","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e8014ebd-d16b-17a7-9f34-3700fc164136@suse.com/mbox/"},{"id":1719,"url":"https://patchwork.plctlab.org/api/1.2/patches/1719/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1266f001-4511-2662-dba9-14b4d0317c57@suse.com/","msgid":"<1266f001-4511-2662-dba9-14b4d0317c57@suse.com>","list_archive_url":null,"date":"2022-10-05T07:40:50","name":"x86: drop \"regmask\" static variable","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1266f001-4511-2662-dba9-14b4d0317c57@suse.com/mbox/"},{"id":1751,"url":"https://patchwork.plctlab.org/api/1.2/patches/1751/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/af45c5d57c221e43101c2aa38b14f4b4ac12d011.1665031170.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-06T04:40:15","name":"[v2,1/2] RISC-V: Fallback for instructions longer than 64b","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/af45c5d57c221e43101c2aa38b14f4b4ac12d011.1665031170.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1752,"url":"https://patchwork.plctlab.org/api/1.2/patches/1752/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c6e55781245dd3e8e9b8debd6130fc5449dfbd55.1665031170.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-06T04:40:16","name":"[v2,2/2] RISC-V: Improve \"bits undefined\" diagnostics","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c6e55781245dd3e8e9b8debd6130fc5449dfbd55.1665031170.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1776,"url":"https://patchwork.plctlab.org/api/1.2/patches/1776/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d52952119e15357c0e823f8a2398999359588b4d.1665050099.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-06T09:56:30","name":"[v3,1/2] RISC-V: Fallback for instructions longer than 64b","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d52952119e15357c0e823f8a2398999359588b4d.1665050099.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1777,"url":"https://patchwork.plctlab.org/api/1.2/patches/1777/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d907b1997f60ff7823c4a23e281ec9d8ddcbf3f1.1665050099.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-06T09:56:31","name":"[v3,2/2] RISC-V: Improve \"bits undefined\" diagnostics","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d907b1997f60ff7823c4a23e281ec9d8ddcbf3f1.1665050099.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1781,"url":"https://patchwork.plctlab.org/api/1.2/patches/1781/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221006114628.304185-1-chigot@adacore.com/","msgid":"<20221006114628.304185-1-chigot@adacore.com>","list_archive_url":null,"date":"2022-10-06T11:46:28","name":"RISC-V: fix linker message when relaxation deletes bytes","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221006114628.304185-1-chigot@adacore.com/mbox/"},{"id":1801,"url":"https://patchwork.plctlab.org/api/1.2/patches/1801/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Yz+Yhyg7UewC9/kp@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-07T03:09:59","name":"PR29653, objcopy/strip: fuzzed small input file induces large output file","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Yz+Yhyg7UewC9/kp@squeak.grove.modra.org/mbox/"},{"id":1803,"url":"https://patchwork.plctlab.org/api/1.2/patches/1803/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/PH1P110MB16505D9D39EC5B1DE22FE3D5EC5F9@PH1P110MB1650.NAMP110.PROD.OUTLOOK.COM/","msgid":"","list_archive_url":null,"date":"2022-10-07T04:10:07","name":"@CPP_FOR_BUILD@ problem since binutils-2.38","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/PH1P110MB16505D9D39EC5B1DE22FE3D5EC5F9@PH1P110MB1650.NAMP110.PROD.OUTLOOK.COM/mbox/"},{"id":1827,"url":"https://patchwork.plctlab.org/api/1.2/patches/1827/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8e13bce108ac10a0c1dd911e23ec572926f7ae44.1665203374.git.research_trasio@irq.a4lg.com/","msgid":"<8e13bce108ac10a0c1dd911e23ec572926f7ae44.1665203374.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-08T04:29:53","name":"[v2,1/1] RISC-V: Test DWARF register numbers for \"fp\"","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8e13bce108ac10a0c1dd911e23ec572926f7ae44.1665203374.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1828,"url":"https://patchwork.plctlab.org/api/1.2/patches/1828/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0883001b3572e54d3fba264429c7ade2adb66610.1665203441.git.research_trasio@irq.a4lg.com/","msgid":"<0883001b3572e54d3fba264429c7ade2adb66610.1665203441.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-08T04:31:15","name":"[1/1] RISC-V: Move standard hints before all instructions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0883001b3572e54d3fba264429c7ade2adb66610.1665203441.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1829,"url":"https://patchwork.plctlab.org/api/1.2/patches/1829/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/58e16a241d7376fcae2515c6bd5a2b41d275eeba.1665203531.git.research_trasio@irq.a4lg.com/","msgid":"<58e16a241d7376fcae2515c6bd5a2b41d275eeba.1665203531.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-08T04:32:18","name":"[RFC,1/1] RISC-V: Imply '\''Zicsr'\'' from privileged extensions with CSRs","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/58e16a241d7376fcae2515c6bd5a2b41d275eeba.1665203531.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1830,"url":"https://patchwork.plctlab.org/api/1.2/patches/1830/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/cb5076fc96e8f2097779a3abcde843dcdd660031.1665203660.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-08T04:34:23","name":"[1/5] opcodes/riscv-dis.c: Tidying with comments/clarity","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/cb5076fc96e8f2097779a3abcde843dcdd660031.1665203660.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1832,"url":"https://patchwork.plctlab.org/api/1.2/patches/1832/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1f1aa0838bf9c4f10a45fcfe3c682f7efc79d9ae.1665203660.git.research_trasio@irq.a4lg.com/","msgid":"<1f1aa0838bf9c4f10a45fcfe3c682f7efc79d9ae.1665203660.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-08T04:34:24","name":"[2/5] opcodes/riscv-dis.c: Tidying with spacing","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1f1aa0838bf9c4f10a45fcfe3c682f7efc79d9ae.1665203660.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1831,"url":"https://patchwork.plctlab.org/api/1.2/patches/1831/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/740bc5e2d2618d236519b39fedd1a1d7ae4e05da.1665203660.git.research_trasio@irq.a4lg.com/","msgid":"<740bc5e2d2618d236519b39fedd1a1d7ae4e05da.1665203660.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-08T04:34:25","name":"[3/5] opcodes/riscv-dis.c: Use bool type whenever possible","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/740bc5e2d2618d236519b39fedd1a1d7ae4e05da.1665203660.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1833,"url":"https://patchwork.plctlab.org/api/1.2/patches/1833/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6e3a9c235e317f441b4383b3daa68f2051bdc149.1665203660.git.research_trasio@irq.a4lg.com/","msgid":"<6e3a9c235e317f441b4383b3daa68f2051bdc149.1665203660.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-08T04:34:26","name":"[4/5] opcodes/riscv-dis.c: Make XLEN variable static","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6e3a9c235e317f441b4383b3daa68f2051bdc149.1665203660.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1834,"url":"https://patchwork.plctlab.org/api/1.2/patches/1834/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ad929233a62d887495122721340b2f9c80392963.1665203660.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-08T04:34:27","name":"[5/5] opcodes/riscv-dis.c: Remove last_map_state","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ad929233a62d887495122721340b2f9c80392963.1665203660.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1836,"url":"https://patchwork.plctlab.org/api/1.2/patches/1836/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d07e2b6f36ea2fd5830924a9bfeda941b774b687.1665290422.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-09T05:09:22","name":"RISC-V: Move certain arrays to riscv-opc.c","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d07e2b6f36ea2fd5830924a9bfeda941b774b687.1665290422.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1844,"url":"https://patchwork.plctlab.org/api/1.2/patches/1844/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010004623.16582-1-mark@harmstone.com/","msgid":"<20221010004623.16582-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-10T00:46:22","name":"[v2,1/2] ld: Add --pdb option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010004623.16582-1-mark@harmstone.com/mbox/"},{"id":1845,"url":"https://patchwork.plctlab.org/api/1.2/patches/1845/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010004623.16582-2-mark@harmstone.com/","msgid":"<20221010004623.16582-2-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-10T00:46:23","name":"[v2,2/2] ld: Add minimal pdb generation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010004623.16582-2-mark@harmstone.com/mbox/"},{"id":1890,"url":"https://patchwork.plctlab.org/api/1.2/patches/1890/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010200433.414320-1-vladimir.mezentsev@oracle.com/","msgid":"<20221010200433.414320-1-vladimir.mezentsev@oracle.com>","list_archive_url":null,"date":"2022-10-10T20:04:33","name":"gprofng: run tests without installation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010200433.414320-1-vladimir.mezentsev@oracle.com/mbox/"},{"id":1893,"url":"https://patchwork.plctlab.org/api/1.2/patches/1893/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010230426.719238-1-vladimir.mezentsev@oracle.com/","msgid":"<20221010230426.719238-1-vladimir.mezentsev@oracle.com>","list_archive_url":null,"date":"2022-10-10T23:04:26","name":"[2/2] gprofng: use the --libdir path to find libraries","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010230426.719238-1-vladimir.mezentsev@oracle.com/mbox/"},{"id":1894,"url":"https://patchwork.plctlab.org/api/1.2/patches/1894/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010235155.842469-1-vladimir.mezentsev@oracle.com/","msgid":"<20221010235155.842469-1-vladimir.mezentsev@oracle.com>","list_archive_url":null,"date":"2022-10-10T23:51:55","name":"[3/3] gprofng: no need to build version.texi","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010235155.842469-1-vladimir.mezentsev@oracle.com/mbox/"},{"id":1895,"url":"https://patchwork.plctlab.org/api/1.2/patches/1895/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011003702.4287-1-mark@harmstone.com/","msgid":"<20221011003702.4287-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-11T00:37:01","name":"[v3,1/2] ld: Add --pdb option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011003702.4287-1-mark@harmstone.com/mbox/"},{"id":1897,"url":"https://patchwork.plctlab.org/api/1.2/patches/1897/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011003702.4287-2-mark@harmstone.com/","msgid":"<20221011003702.4287-2-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-11T00:37:02","name":"[v3,2/2] ld: Add minimal pdb generation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011003702.4287-2-mark@harmstone.com/mbox/"},{"id":1928,"url":"https://patchwork.plctlab.org/api/1.2/patches/1928/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011175332.17156-1-mark@harmstone.com/","msgid":"<20221011175332.17156-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-11T17:53:31","name":"[v4,1/2] ld: Add --pdb option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011175332.17156-1-mark@harmstone.com/mbox/"},{"id":1929,"url":"https://patchwork.plctlab.org/api/1.2/patches/1929/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011175332.17156-2-mark@harmstone.com/","msgid":"<20221011175332.17156-2-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-11T17:53:32","name":"[v4,2/2] ld: Add minimal pdb generation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011175332.17156-2-mark@harmstone.com/mbox/"},{"id":1941,"url":"https://patchwork.plctlab.org/api/1.2/patches/1941/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221012031005.237446-1-simon.marchi@polymtl.ca/","msgid":"<20221012031005.237446-1-simon.marchi@polymtl.ca>","list_archive_url":null,"date":"2022-10-12T03:10:05","name":"[pushed] Re-apply \"Pass PKG_CONFIG_PATH down from top-level Makefile\"","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221012031005.237446-1-simon.marchi@polymtl.ca/mbox/"},{"id":1976,"url":"https://patchwork.plctlab.org/api/1.2/patches/1976/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1216a3f8-2273-8681-f528-9493a66891f0@suse.com/","msgid":"<1216a3f8-2273-8681-f528-9493a66891f0@suse.com>","list_archive_url":null,"date":"2022-10-13T08:16:49","name":"[v4,1/8] x86: constify parse_insn()'\''s input","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1216a3f8-2273-8681-f528-9493a66891f0@suse.com/mbox/"},{"id":1977,"url":"https://patchwork.plctlab.org/api/1.2/patches/1977/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/11599bbe-c779-aa9f-4d5d-c2243f0e69dc@suse.com/","msgid":"<11599bbe-c779-aa9f-4d5d-c2243f0e69dc@suse.com>","list_archive_url":null,"date":"2022-10-13T08:17:17","name":"[v4,2/8] x86: introduce Pass2 insn attribute","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/11599bbe-c779-aa9f-4d5d-c2243f0e69dc@suse.com/mbox/"},{"id":1978,"url":"https://patchwork.plctlab.org/api/1.2/patches/1978/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/357273a3-060c-23db-72da-3fc9d1be3d2a@suse.com/","msgid":"<357273a3-060c-23db-72da-3fc9d1be3d2a@suse.com>","list_archive_url":null,"date":"2022-10-13T08:18:09","name":"[v4,3/8] x86: re-work insn/suffix recognition","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/357273a3-060c-23db-72da-3fc9d1be3d2a@suse.com/mbox/"},{"id":1979,"url":"https://patchwork.plctlab.org/api/1.2/patches/1979/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0ec0587f-6a7b-45b6-8346-e5d774e73636@suse.com/","msgid":"<0ec0587f-6a7b-45b6-8346-e5d774e73636@suse.com>","list_archive_url":null,"date":"2022-10-13T08:18:39","name":"[v4,4/8] x86-64: further re-work insn/suffix recognition to also cover MOVSL","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0ec0587f-6a7b-45b6-8346-e5d774e73636@suse.com/mbox/"},{"id":1980,"url":"https://patchwork.plctlab.org/api/1.2/patches/1980/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fb617d0b-8759-3169-5a65-1178b7fef3d7@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-13T08:19:34","name":"[v4,5/8] ix86: don'\''t recognize/derive Q suffix in the common case","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fb617d0b-8759-3169-5a65-1178b7fef3d7@suse.com/mbox/"},{"id":1981,"url":"https://patchwork.plctlab.org/api/1.2/patches/1981/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1df3bd01-99c5-f56c-d937-970edd42b2b8@suse.com/","msgid":"<1df3bd01-99c5-f56c-d937-970edd42b2b8@suse.com>","list_archive_url":null,"date":"2022-10-13T08:20:14","name":"[v4,6/8] x86-64: allow HLE store of accumulator to absolute 32-bit address","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1df3bd01-99c5-f56c-d937-970edd42b2b8@suse.com/mbox/"},{"id":1982,"url":"https://patchwork.plctlab.org/api/1.2/patches/1982/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8486a218-39ec-16b2-5c6c-5037196b93cf@suse.com/","msgid":"<8486a218-39ec-16b2-5c6c-5037196b93cf@suse.com>","list_archive_url":null,"date":"2022-10-13T08:21:00","name":"[v4,7/8] x86: move bad-use-of-TLS-reloc check","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8486a218-39ec-16b2-5c6c-5037196b93cf@suse.com/mbox/"},{"id":1983,"url":"https://patchwork.plctlab.org/api/1.2/patches/1983/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7d82692d-93df-fbee-9efb-2f44e8a91df3@suse.com/","msgid":"<7d82692d-93df-fbee-9efb-2f44e8a91df3@suse.com>","list_archive_url":null,"date":"2022-10-13T08:22:00","name":"[v4,8/8] x86: drop (now) stray IsString","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7d82692d-93df-fbee-9efb-2f44e8a91df3@suse.com/mbox/"},{"id":2013,"url":"https://patchwork.plctlab.org/api/1.2/patches/2013/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8ab93d7a617ad480dd786210f46db0e5aa07d1ac.1665655719.git.research_trasio@irq.a4lg.com/","msgid":"<8ab93d7a617ad480dd786210f46db0e5aa07d1ac.1665655719.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-13T10:11:41","name":"include: Declare getopt function on old GNU libc","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8ab93d7a617ad480dd786210f46db0e5aa07d1ac.1665655719.git.research_trasio@irq.a4lg.com/mbox/"},{"id":2352,"url":"https://patchwork.plctlab.org/api/1.2/patches/2352/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221013201332.2747246-1-maskray@google.com/","msgid":"<20221013201332.2747246-1-maskray@google.com>","list_archive_url":null,"date":"2022-10-13T20:13:32","name":"ld: Add --undefined-version","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221013201332.2747246-1-maskray@google.com/mbox/"},{"id":2532,"url":"https://patchwork.plctlab.org/api/1.2/patches/2532/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014063520.1428330-2-zengxiao@eswincomputing.com/","msgid":"<20221014063520.1428330-2-zengxiao@eswincomputing.com>","list_archive_url":null,"date":"2022-10-14T06:35:20","name":"[1/1] RISC-V: Make R_RISCV_SUB6 conforms to riscv abi standard","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014063520.1428330-2-zengxiao@eswincomputing.com/mbox/"},{"id":2560,"url":"https://patchwork.plctlab.org/api/1.2/patches/2560/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/027ae69a-636b-6757-297a-eec42936401e@linaro.org/","msgid":"<027ae69a-636b-6757-297a-eec42936401e@linaro.org>","list_archive_url":null,"date":"2022-10-14T07:58:22","name":"[v3] aarch64-pe support for LD, GAS and BFD","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/027ae69a-636b-6757-297a-eec42936401e@linaro.org/mbox/"},{"id":2602,"url":"https://patchwork.plctlab.org/api/1.2/patches/2602/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-2-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-2-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:39","name":"[01/10] Support Intel AVX-IFMA","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-2-haochen.jiang@intel.com/mbox/"},{"id":2608,"url":"https://patchwork.plctlab.org/api/1.2/patches/2608/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-3-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-3-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:40","name":"[02/10] Support Intel AVX-VNNI-INT8","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-3-haochen.jiang@intel.com/mbox/"},{"id":2611,"url":"https://patchwork.plctlab.org/api/1.2/patches/2611/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-4-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-4-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:41","name":"[03/10] Support Intel AVX-NE-CONVERT","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-4-haochen.jiang@intel.com/mbox/"},{"id":2610,"url":"https://patchwork.plctlab.org/api/1.2/patches/2610/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-5-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-5-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:42","name":"[04/10] Support Intel CMPccXADD","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-5-haochen.jiang@intel.com/mbox/"},{"id":2601,"url":"https://patchwork.plctlab.org/api/1.2/patches/2601/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-6-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-6-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:43","name":"[05/10] Add handler for more i386_cpu_flags","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-6-haochen.jiang@intel.com/mbox/"},{"id":2606,"url":"https://patchwork.plctlab.org/api/1.2/patches/2606/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-7-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-7-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:44","name":"[06/10] Support Intel RAO-INT","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-7-haochen.jiang@intel.com/mbox/"},{"id":2609,"url":"https://patchwork.plctlab.org/api/1.2/patches/2609/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-8-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-8-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:45","name":"[07/10] Support Intel WRMSRNS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-8-haochen.jiang@intel.com/mbox/"},{"id":2605,"url":"https://patchwork.plctlab.org/api/1.2/patches/2605/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-9-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-9-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:46","name":"[08/10] Support Intel MSRLIST","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-9-haochen.jiang@intel.com/mbox/"},{"id":2607,"url":"https://patchwork.plctlab.org/api/1.2/patches/2607/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-10-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-10-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:47","name":"[09/10] Support Intel AMX-FP16","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-10-haochen.jiang@intel.com/mbox/"},{"id":2604,"url":"https://patchwork.plctlab.org/api/1.2/patches/2604/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-11-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-11-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:48","name":"[10/10] Support Intel PREFETCHI","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-11-haochen.jiang@intel.com/mbox/"},{"id":2643,"url":"https://patchwork.plctlab.org/api/1.2/patches/2643/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7bac66be-535e-9051-d674-f2f5ba180e17@suse.com/","msgid":"<7bac66be-535e-9051-d674-f2f5ba180e17@suse.com>","list_archive_url":null,"date":"2022-10-14T10:22:34","name":"x86: fold AVX512-VNNI disassembler entries with AVX-VNNI ones","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7bac66be-535e-9051-d674-f2f5ba180e17@suse.com/mbox/"},{"id":2654,"url":"https://patchwork.plctlab.org/api/1.2/patches/2654/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0lIo5+ncY/MqBEq@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-14T11:31:47","name":"PR29677, Field `the_bfd` of `asymbol` is uninitialised","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0lIo5+ncY/MqBEq@squeak.grove.modra.org/mbox/"},{"id":2656,"url":"https://patchwork.plctlab.org/api/1.2/patches/2656/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0lJksn49ZpABY89@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-14T11:35:46","name":"e200 LSP support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0lJksn49ZpABY89@squeak.grove.modra.org/mbox/"},{"id":2657,"url":"https://patchwork.plctlab.org/api/1.2/patches/2657/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0lJxxYoeD5iDYAD@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-14T11:36:39","name":"PowerPC SPE disassembly and tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0lJxxYoeD5iDYAD@squeak.grove.modra.org/mbox/"},{"id":2695,"url":"https://patchwork.plctlab.org/api/1.2/patches/2695/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/DM6PR12MB4219611F6CC2A0702884A602E7249@DM6PR12MB4219.namprd12.prod.outlook.com/","msgid":"","list_archive_url":null,"date":"2022-10-14T13:29:40","name":"Binutils: Adding new testcase for addr2line.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/DM6PR12MB4219611F6CC2A0702884A602E7249@DM6PR12MB4219.namprd12.prod.outlook.com/mbox/"},{"id":2700,"url":"https://patchwork.plctlab.org/api/1.2/patches/2700/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9fd2c88d-98b2-99a4-419f-c7235b2cf960@suse.com/","msgid":"<9fd2c88d-98b2-99a4-419f-c7235b2cf960@suse.com>","list_archive_url":null,"date":"2022-10-14T14:11:35","name":"x86: properly decode EVEX.W for AVX512_4{FMAPS,VNNIW} insns","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9fd2c88d-98b2-99a4-419f-c7235b2cf960@suse.com/mbox/"},{"id":2981,"url":"https://patchwork.plctlab.org/api/1.2/patches/2981/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0uLzalqjm4C87GN@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-16T04:42:53","name":"PowerPC se_rfmci and VLE, SPE2 and LSP insns with -many","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0uLzalqjm4C87GN@squeak.grove.modra.org/mbox/"},{"id":3152,"url":"https://patchwork.plctlab.org/api/1.2/patches/3152/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221016232419.1135-1-mark@harmstone.com/","msgid":"<20221016232419.1135-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-16T23:24:18","name":"[v5,1/2] ld: Add --pdb option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221016232419.1135-1-mark@harmstone.com/mbox/"},{"id":3151,"url":"https://patchwork.plctlab.org/api/1.2/patches/3151/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221016232419.1135-2-mark@harmstone.com/","msgid":"<20221016232419.1135-2-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-16T23:24:19","name":"[v5,2/2] ld: Add minimal pdb generation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221016232419.1135-2-mark@harmstone.com/mbox/"},{"id":3258,"url":"https://patchwork.plctlab.org/api/1.2/patches/3258/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/19c08747-fa5b-1e67-3dd2-c891a2c0c1fa@suse.com/","msgid":"<19c08747-fa5b-1e67-3dd2-c891a2c0c1fa@suse.com>","list_archive_url":null,"date":"2022-10-17T07:44:51","name":"x86: correct CPU_AMX_{BF16,INT8}_FLAGS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/19c08747-fa5b-1e67-3dd2-c891a2c0c1fa@suse.com/mbox/"},{"id":3272,"url":"https://patchwork.plctlab.org/api/1.2/patches/3272/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/85dd526c-d3a7-72dc-5444-ed5573eebec1@suse.com/","msgid":"<85dd526c-d3a7-72dc-5444-ed5573eebec1@suse.com>","list_archive_url":null,"date":"2022-10-17T08:30:12","name":"x86: generalize gas documentation for disabling of ISA extensions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/85dd526c-d3a7-72dc-5444-ed5573eebec1@suse.com/mbox/"},{"id":3759,"url":"https://patchwork.plctlab.org/api/1.2/patches/3759/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-2-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-2-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:15:58","name":"[V2,01/15] sframe.h: Add SFrame format definition","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-2-indu.bhagat@oracle.com/mbox/"},{"id":3762,"url":"https://patchwork.plctlab.org/api/1.2/patches/3762/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-3-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-3-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:15:59","name":"[V2,02/15] gas: add new command line option --gsframe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-3-indu.bhagat@oracle.com/mbox/"},{"id":3761,"url":"https://patchwork.plctlab.org/api/1.2/patches/3761/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-4-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-4-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:00","name":"[V2,03/15] gas: generate .sframe from CFI directives","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-4-indu.bhagat@oracle.com/mbox/"},{"id":3760,"url":"https://patchwork.plctlab.org/api/1.2/patches/3760/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-5-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-5-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:01","name":"[V2,04/15] gas: testsuite: add new tests for SFrame unwind info","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-5-indu.bhagat@oracle.com/mbox/"},{"id":3764,"url":"https://patchwork.plctlab.org/api/1.2/patches/3764/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-6-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-6-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:02","name":"[V2,05/15] libsframe: add the SFrame library","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-6-indu.bhagat@oracle.com/mbox/"},{"id":3766,"url":"https://patchwork.plctlab.org/api/1.2/patches/3766/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-7-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-7-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:03","name":"[V2,06/15] bfd: linker: merge .sframe sections","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-7-indu.bhagat@oracle.com/mbox/"},{"id":3763,"url":"https://patchwork.plctlab.org/api/1.2/patches/3763/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-8-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-8-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:04","name":"[V2,07/15] readelf/objdump: support for SFrame section","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-8-indu.bhagat@oracle.com/mbox/"},{"id":3765,"url":"https://patchwork.plctlab.org/api/1.2/patches/3765/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-9-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-9-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:05","name":"[V2,08/15] unwinder: generate backtrace using SFrame format","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-9-indu.bhagat@oracle.com/mbox/"},{"id":3770,"url":"https://patchwork.plctlab.org/api/1.2/patches/3770/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-10-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-10-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:06","name":"[V2,09/15] unwinder: Add SFrame unwinder tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-10-indu.bhagat@oracle.com/mbox/"},{"id":3769,"url":"https://patchwork.plctlab.org/api/1.2/patches/3769/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-11-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-11-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:07","name":"[V2,10/15] gdb: sim: buildsystem changes to accommodate libsframe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-11-indu.bhagat@oracle.com/mbox/"},{"id":3771,"url":"https://patchwork.plctlab.org/api/1.2/patches/3771/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-12-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-12-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:08","name":"[V2,11/15] libctf: add libsframe to LDFLAGS and LIBS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-12-indu.bhagat@oracle.com/mbox/"},{"id":3768,"url":"https://patchwork.plctlab.org/api/1.2/patches/3768/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-13-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-13-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:09","name":"[V2,12/15] src-release.sh: Add libsframe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-13-indu.bhagat@oracle.com/mbox/"},{"id":3767,"url":"https://patchwork.plctlab.org/api/1.2/patches/3767/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-14-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-14-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:10","name":"[V2,13/15] binutils/NEWS: add text for SFrame support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-14-indu.bhagat@oracle.com/mbox/"},{"id":3772,"url":"https://patchwork.plctlab.org/api/1.2/patches/3772/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-15-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-15-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:11","name":"[V2,14/15] gas/NEWS: add text about new command line option and SFrame support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-15-indu.bhagat@oracle.com/mbox/"},{"id":3773,"url":"https://patchwork.plctlab.org/api/1.2/patches/3773/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-16-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-16-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:12","name":"[V2,15/15] doc: add SFrame spec file","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-16-indu.bhagat@oracle.com/mbox/"},{"id":3999,"url":"https://patchwork.plctlab.org/api/1.2/patches/3999/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221018081205.17880-1-krebbel@linux.ibm.com/","msgid":"<20221018081205.17880-1-krebbel@linux.ibm.com>","list_archive_url":null,"date":"2022-10-18T08:12:05","name":"[1/1] IBM zSystems: Issue error for *DBL relocs on misaligned symbols","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221018081205.17880-1-krebbel@linux.ibm.com/mbox/"},{"id":4141,"url":"https://patchwork.plctlab.org/api/1.2/patches/4141/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/baffaf673f17692b7bcbd604b31800b189988596.camel@espressif.com/","msgid":"","list_archive_url":null,"date":"2022-10-18T12:12:07","name":"xtensa: use definitions from xtensa-config.h","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/baffaf673f17692b7bcbd604b31800b189988596.camel@espressif.com/mbox/"},{"id":4272,"url":"https://patchwork.plctlab.org/api/1.2/patches/4272/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221018174914.470062-1-hjl.tools@gmail.com/","msgid":"<20221018174914.470062-1-hjl.tools@gmail.com>","list_archive_url":null,"date":"2022-10-18T17:49:14","name":"x86: Disable AVX-VNNI when disabling AVX2","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221018174914.470062-1-hjl.tools@gmail.com/mbox/"},{"id":4998,"url":"https://patchwork.plctlab.org/api/1.2/patches/4998/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c2f76e95-09f6-1d92-7ef4-38a3c2955fcd@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-19T09:52:46","name":"x86: re-work AVX-VNNI support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c2f76e95-09f6-1d92-7ef4-38a3c2955fcd@suse.com/mbox/"},{"id":5276,"url":"https://patchwork.plctlab.org/api/1.2/patches/5276/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0/lLtlKqqsmAx0s@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-19T11:53:18","name":"Fix addr2line test for ppc64 elfv1 and mingw","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0/lLtlKqqsmAx0s@squeak.grove.modra.org/mbox/"},{"id":5424,"url":"https://patchwork.plctlab.org/api/1.2/patches/5424/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/07bfebbf3843b47e13d82d4fa16eb14fec942ef7.1666184962.git.research_trasio@irq.a4lg.com/","msgid":"<07bfebbf3843b47e13d82d4fa16eb14fec942ef7.1666184962.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:09:54","name":"binutils: Remove unused substitution PROGRAM","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/07bfebbf3843b47e13d82d4fa16eb14fec942ef7.1666184962.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5433,"url":"https://patchwork.plctlab.org/api/1.2/patches/5433/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2fa7ff719223232402e82a9c91331aea22ace1bb.1666185116.git.research_trasio@irq.a4lg.com/","msgid":"<2fa7ff719223232402e82a9c91331aea22ace1bb.1666185116.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:11:55","name":"[v2,1/8] RISC-V: Add a space at the end of pinfo","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2fa7ff719223232402e82a9c91331aea22ace1bb.1666185116.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5435,"url":"https://patchwork.plctlab.org/api/1.2/patches/5435/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1b30cce5db2cce3b8edca42ab5da114d0b8c9e93.1666185116.git.research_trasio@irq.a4lg.com/","msgid":"<1b30cce5db2cce3b8edca42ab5da114d0b8c9e93.1666185116.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:11:56","name":"[v2,2/8] RISC-V: Fix obvious misalignments ('\''Zbb'\''/'\''Zba'\'')","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1b30cce5db2cce3b8edca42ab5da114d0b8c9e93.1666185116.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5437,"url":"https://patchwork.plctlab.org/api/1.2/patches/5437/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6b0857aa1a2d15ca1cf00b4dcaae0032efbb88ff.1666185116.git.research_trasio@irq.a4lg.com/","msgid":"<6b0857aa1a2d15ca1cf00b4dcaae0032efbb88ff.1666185116.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:11:57","name":"[v2,3/8] RISC-V: Remove spaces in opcode entries","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6b0857aa1a2d15ca1cf00b4dcaae0032efbb88ff.1666185116.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5436,"url":"https://patchwork.plctlab.org/api/1.2/patches/5436/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/889d956caac0f2e95543a14afaeed97188ce384c.1666185116.git.research_trasio@irq.a4lg.com/","msgid":"<889d956caac0f2e95543a14afaeed97188ce384c.1666185116.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:11:58","name":"[v2,4/8] RISC-V: Remove unused instruction macros","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/889d956caac0f2e95543a14afaeed97188ce384c.1666185116.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5440,"url":"https://patchwork.plctlab.org/api/1.2/patches/5440/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8f226ee20d8a5ef6ad7b6c4408b44794a99d542a.1666185116.git.research_trasio@irq.a4lg.com/","msgid":"<8f226ee20d8a5ef6ad7b6c4408b44794a99d542a.1666185116.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:11:59","name":"[v2,5/8] RISC-V: Complete tidying up with SCALL and SBREAK","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8f226ee20d8a5ef6ad7b6c4408b44794a99d542a.1666185116.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5442,"url":"https://patchwork.plctlab.org/api/1.2/patches/5442/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4070184c454a05a39adf0790951e5856e6b2ecb6.1666185116.git.research_trasio@irq.a4lg.com/","msgid":"<4070184c454a05a39adf0790951e5856e6b2ecb6.1666185116.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:12:00","name":"[v2,6/8] RISC-V: Tidying up with fmv.w.x and fmv.x.w","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4070184c454a05a39adf0790951e5856e6b2ecb6.1666185116.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5438,"url":"https://patchwork.plctlab.org/api/1.2/patches/5438/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c1ccda3e7c8fb297eda46dab3936d5c5977178fc.1666185116.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-19T13:12:01","name":"[v2,7/8] RISC-V: Make alias instructions aliases","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c1ccda3e7c8fb297eda46dab3936d5c5977178fc.1666185116.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5441,"url":"https://patchwork.plctlab.org/api/1.2/patches/5441/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/413cfca82c7e8d8a2e977dfda9135903c9cb7c57.1666185116.git.research_trasio@irq.a4lg.com/","msgid":"<413cfca82c7e8d8a2e977dfda9135903c9cb7c57.1666185116.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:12:02","name":"[v2,8/8] RISC-V: Use defined mask and match values","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/413cfca82c7e8d8a2e977dfda9135903c9cb7c57.1666185116.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5439,"url":"https://patchwork.plctlab.org/api/1.2/patches/5439/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/345c5c3b3a53eab04a1e6e91197de2642095c94f.1666185237.git.research_trasio@irq.a4lg.com/","msgid":"<345c5c3b3a53eab04a1e6e91197de2642095c94f.1666185237.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:14:01","name":"RISC-V: Remove RV32EF conflict","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/345c5c3b3a53eab04a1e6e91197de2642095c94f.1666185237.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5616,"url":"https://patchwork.plctlab.org/api/1.2/patches/5616/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019145608.45213-5-haochen.jiang@intel.com/","msgid":"<20221019145608.45213-5-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T14:56:02","name":"[04/10] Support Intel CMPccXADD","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019145608.45213-5-haochen.jiang@intel.com/mbox/"},{"id":5614,"url":"https://patchwork.plctlab.org/api/1.2/patches/5614/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019145608.45213-6-haochen.jiang@intel.com/","msgid":"<20221019145608.45213-6-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T14:56:03","name":"[05/10] Add handler for more i386_cpu_flags","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019145608.45213-6-haochen.jiang@intel.com/mbox/"},{"id":5672,"url":"https://patchwork.plctlab.org/api/1.2/patches/5672/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-2-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-2-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:25","name":"[01/10] Support Intel AVX-IFMA","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-2-haochen.jiang@intel.com/mbox/"},{"id":5691,"url":"https://patchwork.plctlab.org/api/1.2/patches/5691/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-3-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-3-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:26","name":"[02/10] Support Intel AVX-VNNI-INT8","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-3-haochen.jiang@intel.com/mbox/"},{"id":5690,"url":"https://patchwork.plctlab.org/api/1.2/patches/5690/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-4-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-4-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:27","name":"[03/10] Support Intel AVX-NE-CONVERT","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-4-haochen.jiang@intel.com/mbox/"},{"id":5689,"url":"https://patchwork.plctlab.org/api/1.2/patches/5689/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-5-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-5-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:28","name":"[04/10] Support Intel CMPccXADD","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-5-haochen.jiang@intel.com/mbox/"},{"id":5676,"url":"https://patchwork.plctlab.org/api/1.2/patches/5676/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-6-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-6-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:29","name":"[05/10] Add handler for more i386_cpu_flags","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-6-haochen.jiang@intel.com/mbox/"},{"id":5677,"url":"https://patchwork.plctlab.org/api/1.2/patches/5677/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-7-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-7-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:30","name":"[06/10] Support Intel RAO-INT","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-7-haochen.jiang@intel.com/mbox/"},{"id":5681,"url":"https://patchwork.plctlab.org/api/1.2/patches/5681/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-8-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-8-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:31","name":"[07/10] Support Intel WRMSRNS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-8-haochen.jiang@intel.com/mbox/"},{"id":5682,"url":"https://patchwork.plctlab.org/api/1.2/patches/5682/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-9-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-9-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:32","name":"[08/10] Support Intel MSRLIST","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-9-haochen.jiang@intel.com/mbox/"},{"id":5673,"url":"https://patchwork.plctlab.org/api/1.2/patches/5673/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-10-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-10-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:33","name":"[09/10] Support Intel AMX-FP16","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-10-haochen.jiang@intel.com/mbox/"},{"id":5686,"url":"https://patchwork.plctlab.org/api/1.2/patches/5686/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-11-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-11-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:34","name":"[10/10] Support Intel PREFETCHI","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-11-haochen.jiang@intel.com/mbox/"},{"id":5940,"url":"https://patchwork.plctlab.org/api/1.2/patches/5940/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1CMrFUC8d9lC/NL@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-19T23:47:56","name":"Obsolete beos","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1CMrFUC8d9lC/NL@squeak.grove.modra.org/mbox/"},{"id":6080,"url":"https://patchwork.plctlab.org/api/1.2/patches/6080/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8b99d666e78ba5b9d32c7889a2161c70b3da88df.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<8b99d666e78ba5b9d32c7889a2161c70b3da88df.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:25:47","name":"[01/40] gdb/unittests: PR28413, suppress warnings generated by Gnulib","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8b99d666e78ba5b9d32c7889a2161c70b3da88df.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6081,"url":"https://patchwork.plctlab.org/api/1.2/patches/6081/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b05adb17e401d621dbdad791281bc7af7806906e.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-20T09:25:48","name":"[02/40] sim: Check known getrusage declaration existence","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b05adb17e401d621dbdad791281bc7af7806906e.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6083,"url":"https://patchwork.plctlab.org/api/1.2/patches/6083/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/796962a87e569feeafb5ef636de3c79000ae152c.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<796962a87e569feeafb5ef636de3c79000ae152c.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:25:49","name":"[03/40] sim/aarch64: Remove unused functions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/796962a87e569feeafb5ef636de3c79000ae152c.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6084,"url":"https://patchwork.plctlab.org/api/1.2/patches/6084/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/65223c79fdfd7faf132275415cd9da9852c5bec3.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<65223c79fdfd7faf132275415cd9da9852c5bec3.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:25:50","name":"[04/40] cpu/cris: Initialize some variables on CRIS CPU","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/65223c79fdfd7faf132275415cd9da9852c5bec3.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6082,"url":"https://patchwork.plctlab.org/api/1.2/patches/6082/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/24baefe92148f4b7968115ba13de9b0c863a65f6.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<24baefe92148f4b7968115ba13de9b0c863a65f6.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:25:51","name":"[05/40] cpu/cris: Add u-stall virtual unit to CRIS v32","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/24baefe92148f4b7968115ba13de9b0c863a65f6.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6087,"url":"https://patchwork.plctlab.org/api/1.2/patches/6087/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3904a5c3e80f8548150d8088a92059dd728c7ff8.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<3904a5c3e80f8548150d8088a92059dd728c7ff8.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:25:52","name":"[06/40] sim/cris: Move declarations of f_specific_init","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3904a5c3e80f8548150d8088a92059dd728c7ff8.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6091,"url":"https://patchwork.plctlab.org/api/1.2/patches/6091/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/69ef2d7dd519ed572511890a215a0f6d74e53384.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<69ef2d7dd519ed572511890a215a0f6d74e53384.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:25:53","name":"[07/40] sim/cris: Regenerate with CGEN","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/69ef2d7dd519ed572511890a215a0f6d74e53384.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6085,"url":"https://patchwork.plctlab.org/api/1.2/patches/6085/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/26a3eaf4f5d2e0db6977738ddfd65d82b36e38b2.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<26a3eaf4f5d2e0db6977738ddfd65d82b36e38b2.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:25:54","name":"[08/40] sim/erc32: Insert void parameter","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/26a3eaf4f5d2e0db6977738ddfd65d82b36e38b2.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6086,"url":"https://patchwork.plctlab.org/api/1.2/patches/6086/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/057c2f8392410494c3bc5dc98052246508e6a73e.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<057c2f8392410494c3bc5dc98052246508e6a73e.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:25:55","name":"[09/40] sim/erc32: Use int32_t as event callback argument","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/057c2f8392410494c3bc5dc98052246508e6a73e.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6090,"url":"https://patchwork.plctlab.org/api/1.2/patches/6090/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8c05aec20557191434485be347d37177a2ec5ff2.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<8c05aec20557191434485be347d37177a2ec5ff2.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:25:56","name":"[10/40] sim/erc32: Use int32_t as IRQ callback argument","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8c05aec20557191434485be347d37177a2ec5ff2.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6089,"url":"https://patchwork.plctlab.org/api/1.2/patches/6089/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/afd7757aae21743c29f2aa4135a23b31d4959e9b.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-20T09:25:57","name":"[11/40] cpu/frv: Initialize some variables","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/afd7757aae21743c29f2aa4135a23b31d4959e9b.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6088,"url":"https://patchwork.plctlab.org/api/1.2/patches/6088/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/021dbd238af5dfe74523ed229d2156a155a6bb9e.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<021dbd238af5dfe74523ed229d2156a155a6bb9e.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:25:58","name":"[12/40] sim/frv: Initialize nesr variable","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/021dbd238af5dfe74523ed229d2156a155a6bb9e.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6093,"url":"https://patchwork.plctlab.org/api/1.2/patches/6093/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/51a03f7097921cc48954210cf99e370ae8982ec8.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<51a03f7097921cc48954210cf99e370ae8982ec8.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:25:59","name":"[13/40] sim/frv: Initialize some variables","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/51a03f7097921cc48954210cf99e370ae8982ec8.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6092,"url":"https://patchwork.plctlab.org/api/1.2/patches/6092/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e1baa1be3601612266dc6ae0bdde8426ff2a42c8.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-20T09:26:00","name":"[14/40] sim/frv: Add explicit casts","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e1baa1be3601612266dc6ae0bdde8426ff2a42c8.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6095,"url":"https://patchwork.plctlab.org/api/1.2/patches/6095/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5ab303a5bdfc1da7832f8fa22f57678c9ef1a5fa.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<5ab303a5bdfc1da7832f8fa22f57678c9ef1a5fa.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:26:01","name":"[15/40] sim/h8300: Add \"+ 0x0\" to avoid self-assignments","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5ab303a5bdfc1da7832f8fa22f57678c9ef1a5fa.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6101,"url":"https://patchwork.plctlab.org/api/1.2/patches/6101/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ddff80db3328a2286fe6fbc1240d2abc1e3813eb.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-20T09:26:02","name":"[16/40] sim/lm32: fix some missing function declaration warnings","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ddff80db3328a2286fe6fbc1240d2abc1e3813eb.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6094,"url":"https://patchwork.plctlab.org/api/1.2/patches/6094/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e094b1379231d9ffb59a78cfebbcc84634c779c6.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-20T09:26:03","name":"[17/40] sim/lm32: Add explicit casts","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e094b1379231d9ffb59a78cfebbcc84634c779c6.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6141,"url":"https://patchwork.plctlab.org/api/1.2/patches/6141/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/cabebead-489b-528c-580e-933832417474@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-20T10:25:51","name":"[1/3] x86: emit {evex} prefix when disassembling ambiguous AVX512VL insns","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/cabebead-489b-528c-580e-933832417474@suse.com/mbox/"},{"id":6143,"url":"https://patchwork.plctlab.org/api/1.2/patches/6143/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a032d61c-63a0-23d1-331f-619a2b8bbde3@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-20T10:26:15","name":"[2/3] x86: consolidate VAES tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a032d61c-63a0-23d1-331f-619a2b8bbde3@suse.com/mbox/"},{"id":6142,"url":"https://patchwork.plctlab.org/api/1.2/patches/6142/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7ff09c86-2de7-dc34-3183-5187de3df5ac@suse.com/","msgid":"<7ff09c86-2de7-dc34-3183-5187de3df5ac@suse.com>","list_archive_url":null,"date":"2022-10-20T10:26:40","name":"[3/3] x86: consolidate VPCLMUL tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7ff09c86-2de7-dc34-3183-5187de3df5ac@suse.com/mbox/"},{"id":6228,"url":"https://patchwork.plctlab.org/api/1.2/patches/6228/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.LSU.2.20.2210201432170.29399@wotan.suse.de/","msgid":"","list_archive_url":null,"date":"2022-10-20T14:42:25","name":"x86-64: Use only one default max-page-size","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.LSU.2.20.2210201432170.29399@wotan.suse.de/mbox/"},{"id":6229,"url":"https://patchwork.plctlab.org/api/1.2/patches/6229/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221020144351.1398099-1-chigot@adacore.com/","msgid":"<20221020144351.1398099-1-chigot@adacore.com>","list_archive_url":null,"date":"2022-10-20T14:43:50","name":"[1/2] ld/testsuite: skip ld-elf/exclude when -shared is not supported","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221020144351.1398099-1-chigot@adacore.com/mbox/"},{"id":6230,"url":"https://patchwork.plctlab.org/api/1.2/patches/6230/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221020144351.1398099-2-chigot@adacore.com/","msgid":"<20221020144351.1398099-2-chigot@adacore.com>","list_archive_url":null,"date":"2022-10-20T14:43:51","name":"[2/2] ld/testsuite: adjust ld-arm to run shared tests only when supported","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221020144351.1398099-2-chigot@adacore.com/mbox/"},{"id":6236,"url":"https://patchwork.plctlab.org/api/1.2/patches/6236/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221020151027.GA1300@delia.home/","msgid":"<20221020151027.GA1300@delia.home>","list_archive_url":null,"date":"2022-10-20T15:10:28","name":"[RFC,top-level] Add configure test-case","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221020151027.GA1300@delia.home/mbox/"},{"id":6286,"url":"https://patchwork.plctlab.org/api/1.2/patches/6286/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221020162911.1113338-1-hjl.tools@gmail.com/","msgid":"<20221020162911.1113338-1-hjl.tools@gmail.com>","list_archive_url":null,"date":"2022-10-20T16:29:11","name":"x86: Check VEX/EVEX encoding before checking vector operands","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221020162911.1113338-1-hjl.tools@gmail.com/mbox/"},{"id":7884,"url":"https://patchwork.plctlab.org/api/1.2/patches/7884/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7e53b7980f2b3b74d2250bc87f5db94b1d888a2d.camel@espressif.com/","msgid":"<7e53b7980f2b3b74d2250bc87f5db94b1d888a2d.camel@espressif.com>","list_archive_url":null,"date":"2022-10-22T12:53:54","name":"[1/5] bfd: xtensa: move common code from ld and gas","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7e53b7980f2b3b74d2250bc87f5db94b1d888a2d.camel@espressif.com/mbox/"},{"id":7885,"url":"https://patchwork.plctlab.org/api/1.2/patches/7885/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/63f2699e6ef3e6d1ca415a6ed1187d4f64297521.camel@espressif.com/","msgid":"<63f2699e6ef3e6d1ca415a6ed1187d4f64297521.camel@espressif.com>","list_archive_url":null,"date":"2022-10-22T12:55:16","name":"[2/5] gas: xtensa: add endianness, loops, booleans options","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/63f2699e6ef3e6d1ca415a6ed1187d4f64297521.camel@espressif.com/mbox/"},{"id":7886,"url":"https://patchwork.plctlab.org/api/1.2/patches/7886/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/34d2f747237aeeda595560cfded8096d9bd1c28c.camel@espressif.com/","msgid":"<34d2f747237aeeda595560cfded8096d9bd1c28c.camel@espressif.com>","list_archive_url":null,"date":"2022-10-22T12:56:02","name":"[3/5] ld: xtensa: use default LD command line options for endianness","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/34d2f747237aeeda595560cfded8096d9bd1c28c.camel@espressif.com/mbox/"},{"id":7891,"url":"https://patchwork.plctlab.org/api/1.2/patches/7891/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/535b6208c1718b9acf3258575e1ebc0a65af9f07.camel@espressif.com/","msgid":"<535b6208c1718b9acf3258575e1ebc0a65af9f07.camel@espressif.com>","list_archive_url":null,"date":"2022-10-22T13:56:44","name":"[5/5] gdb: xtensa: add support for esp32, esp32s2, esp32s3 isa-modules","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/535b6208c1718b9acf3258575e1ebc0a65af9f07.camel@espressif.com/mbox/"},{"id":10456,"url":"https://patchwork.plctlab.org/api/1.2/patches/10456/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221025013347.68282-1-nelson@rivosinc.com/","msgid":"<20221025013347.68282-1-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-10-25T01:33:46","name":"[committed,1/2] RISC-V: Improve link time complexity.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221025013347.68282-1-nelson@rivosinc.com/mbox/"},{"id":10454,"url":"https://patchwork.plctlab.org/api/1.2/patches/10454/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221025013347.68282-2-nelson@rivosinc.com/","msgid":"<20221025013347.68282-2-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-10-25T01:33:47","name":"[committed,2/2] RISC-V: Should reset `again'\'' flag for _bfd_riscv_relax_pc.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221025013347.68282-2-nelson@rivosinc.com/mbox/"},{"id":10536,"url":"https://patchwork.plctlab.org/api/1.2/patches/10536/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/bb7b87e4-1893-5c86-4a14-92bafc818b03@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-25T07:24:56","name":"[v5,1/8] x86: constify parse_insn()'\''s input","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/bb7b87e4-1893-5c86-4a14-92bafc818b03@suse.com/mbox/"},{"id":10537,"url":"https://patchwork.plctlab.org/api/1.2/patches/10537/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b9273ae6-0218-54f8-5374-b265ed13b71a@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-25T07:25:26","name":"[v5,1/8] x86: introduce Pass2 insn attribute","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b9273ae6-0218-54f8-5374-b265ed13b71a@suse.com/mbox/"},{"id":10541,"url":"https://patchwork.plctlab.org/api/1.2/patches/10541/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7250dab9-e218-e6dd-4c74-23da9f611ab4@suse.com/","msgid":"<7250dab9-e218-e6dd-4c74-23da9f611ab4@suse.com>","list_archive_url":null,"date":"2022-10-25T07:26:11","name":"[v5,3/8] x86: re-work insn/suffix recognition","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7250dab9-e218-e6dd-4c74-23da9f611ab4@suse.com/mbox/"},{"id":10540,"url":"https://patchwork.plctlab.org/api/1.2/patches/10540/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/13fc630f-e116-0099-5c9e-2697df6519d7@suse.com/","msgid":"<13fc630f-e116-0099-5c9e-2697df6519d7@suse.com>","list_archive_url":null,"date":"2022-10-25T07:26:40","name":"[v5,4/8] ix86: don'\''t recognize/derive Q suffix in the common case","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/13fc630f-e116-0099-5c9e-2697df6519d7@suse.com/mbox/"},{"id":10543,"url":"https://patchwork.plctlab.org/api/1.2/patches/10543/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/74db429d-d203-eab8-4ae1-18b9ad416b02@suse.com/","msgid":"<74db429d-d203-eab8-4ae1-18b9ad416b02@suse.com>","list_archive_url":null,"date":"2022-10-25T07:27:11","name":"[v5,5/8] x86-64: allow HLE store of accumulator to absolute 32-bit address","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/74db429d-d203-eab8-4ae1-18b9ad416b02@suse.com/mbox/"},{"id":10542,"url":"https://patchwork.plctlab.org/api/1.2/patches/10542/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2e2f7841-de4e-b5de-e8d9-a47a6a4113c8@suse.com/","msgid":"<2e2f7841-de4e-b5de-e8d9-a47a6a4113c8@suse.com>","list_archive_url":null,"date":"2022-10-25T07:27:35","name":"[v5,6/8] x86: move bad-use-of-TLS-reloc check","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2e2f7841-de4e-b5de-e8d9-a47a6a4113c8@suse.com/mbox/"},{"id":10545,"url":"https://patchwork.plctlab.org/api/1.2/patches/10545/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/421bc96e-7591-6980-48e9-5af8c8b0775a@suse.com/","msgid":"<421bc96e-7591-6980-48e9-5af8c8b0775a@suse.com>","list_archive_url":null,"date":"2022-10-25T07:28:27","name":"[v5,7/8] x86: drop (now) stray IsString","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/421bc96e-7591-6980-48e9-5af8c8b0775a@suse.com/mbox/"},{"id":10546,"url":"https://patchwork.plctlab.org/api/1.2/patches/10546/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/06ff83d4-4633-a07b-70e5-a8e049981dd4@suse.com/","msgid":"<06ff83d4-4633-a07b-70e5-a8e049981dd4@suse.com>","list_archive_url":null,"date":"2022-10-25T07:29:18","name":"[v5,8/8] x86: further re-work insn/suffix recognition to also cover MOVSX","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/06ff83d4-4633-a07b-70e5-a8e049981dd4@suse.com/mbox/"},{"id":10777,"url":"https://patchwork.plctlab.org/api/1.2/patches/10777/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6a8e7a71acccd0efb9789dfb3edfa307e83bdaa1.1666702934.git.research_trasio@irq.a4lg.com/","msgid":"<6a8e7a71acccd0efb9789dfb3edfa307e83bdaa1.1666702934.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-25T13:04:02","name":"[RFC] RISC-V: Allocate \"various\" operand type","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6a8e7a71acccd0efb9789dfb3edfa307e83bdaa1.1666702934.git.research_trasio@irq.a4lg.com/mbox/"},{"id":11062,"url":"https://patchwork.plctlab.org/api/1.2/patches/11062/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jAhwbXhxJHL66v@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-26T05:07:19","name":"PR29720, objdump -S crashes if build-id is missing","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jAhwbXhxJHL66v@squeak.grove.modra.org/mbox/"},{"id":11063,"url":"https://patchwork.plctlab.org/api/1.2/patches/11063/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jAxD+NxpMIah6s@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-26T05:08:20","name":"som.c buffer overflow","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jAxD+NxpMIah6s@squeak.grove.modra.org/mbox/"},{"id":11064,"url":"https://patchwork.plctlab.org/api/1.2/patches/11064/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jBYw4lfRQfOZhi@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-26T05:10:59","name":"som.c reloc sanity checking","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jBYw4lfRQfOZhi@squeak.grove.modra.org/mbox/"},{"id":11080,"url":"https://patchwork.plctlab.org/api/1.2/patches/11080/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jY7hygm01PelCY@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-26T06:51:26","name":"segfault in objdump.c reloc_at","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jY7hygm01PelCY@squeak.grove.modra.org/mbox/"},{"id":11081,"url":"https://patchwork.plctlab.org/api/1.2/patches/11081/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jZWIeIvCCYm9/g@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-26T06:53:12","name":"Correct ELF reloc size sanity check","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jZWIeIvCCYm9/g@squeak.grove.modra.org/mbox/"},{"id":11082,"url":"https://patchwork.plctlab.org/api/1.2/patches/11082/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221026070009.3663574-1-ysato@users.sourceforge.jp/","msgid":"<20221026070009.3663574-1-ysato@users.sourceforge.jp>","list_archive_url":null,"date":"2022-10-26T07:00:09","name":"opcodes: RX fix invalid output.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221026070009.3663574-1-ysato@users.sourceforge.jp/mbox/"},{"id":11089,"url":"https://patchwork.plctlab.org/api/1.2/patches/11089/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jhW48kuVC8Ig2d@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-26T07:27:23","name":"buffer overflow in _bfd_XX_print_ce_compressed_pdata","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jhW48kuVC8Ig2d@squeak.grove.modra.org/mbox/"},{"id":11157,"url":"https://patchwork.plctlab.org/api/1.2/patches/11157/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c52dbd16-7e1b-c356-7a92-1ff089564ef7@suse.cz/","msgid":"","list_archive_url":null,"date":"2022-10-26T08:47:09","name":"tests: use canonical option name","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c52dbd16-7e1b-c356-7a92-1ff089564ef7@suse.cz/mbox/"},{"id":11526,"url":"https://patchwork.plctlab.org/api/1.2/patches/11526/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027031915.4013-1-lifang_xia@linux.alibaba.com/","msgid":"<20221027031915.4013-1-lifang_xia@linux.alibaba.com>","list_archive_url":null,"date":"2022-10-27T03:19:15","name":"[v2] RISC-V: Optimize relax of GP/call with max_alignment.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027031915.4013-1-lifang_xia@linux.alibaba.com/mbox/"},{"id":11619,"url":"https://patchwork.plctlab.org/api/1.2/patches/11619/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9df9d9e5bb4c7594b76c40613a349b4d2364e9c5.1666854355.git.research_trasio@irq.a4lg.com/","msgid":"<9df9d9e5bb4c7594b76c40613a349b4d2364e9c5.1666854355.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-27T07:06:01","name":"include: Define macro to ignore -Wdeprecated-declarations on GCC","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9df9d9e5bb4c7594b76c40613a349b4d2364e9c5.1666854355.git.research_trasio@irq.a4lg.com/mbox/"},{"id":11627,"url":"https://patchwork.plctlab.org/api/1.2/patches/11627/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1o06O9Pp8ncCsOw@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-27T07:36:08","name":"Fuzzed files in archives","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1o06O9Pp8ncCsOw@squeak.grove.modra.org/mbox/"},{"id":11658,"url":"https://patchwork.plctlab.org/api/1.2/patches/11658/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027084808.37252-1-nelson@rivosinc.com/","msgid":"<20221027084808.37252-1-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-10-27T08:48:08","name":"[committed] RISC-V: Fix build failures for -Werror=sign-compare.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027084808.37252-1-nelson@rivosinc.com/mbox/"},{"id":11921,"url":"https://patchwork.plctlab.org/api/1.2/patches/11921/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027190052.10536-1-mark@harmstone.com/","msgid":"<20221027190052.10536-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-27T19:00:51","name":"[1/2] ld: Add section header stream to PDB files","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027190052.10536-1-mark@harmstone.com/mbox/"},{"id":11922,"url":"https://patchwork.plctlab.org/api/1.2/patches/11922/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027190052.10536-2-mark@harmstone.com/","msgid":"<20221027190052.10536-2-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-27T19:00:52","name":"[2/2] ld: Add publics stream to PDB files","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027190052.10536-2-mark@harmstone.com/mbox/"},{"id":11965,"url":"https://patchwork.plctlab.org/api/1.2/patches/11965/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027202719.32497-1-palmer@rivosinc.com/","msgid":"<20221027202719.32497-1-palmer@rivosinc.com>","list_archive_url":null,"date":"2022-10-27T20:27:18","name":"[1/2] gas: NEWS: Add a missing newline","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027202719.32497-1-palmer@rivosinc.com/mbox/"},{"id":11966,"url":"https://patchwork.plctlab.org/api/1.2/patches/11966/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027202719.32497-2-palmer@rivosinc.com/","msgid":"<20221027202719.32497-2-palmer@rivosinc.com>","list_archive_url":null,"date":"2022-10-27T20:27:19","name":"[2/2] gas: NEWS: Note support for RISC-V Zawrs","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027202719.32497-2-palmer@rivosinc.com/mbox/"},{"id":12016,"url":"https://patchwork.plctlab.org/api/1.2/patches/12016/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/21ec9a18-fa89-0828-f625-499680022ec7@linux.ibm.com/","msgid":"<21ec9a18-fa89-0828-f625-499680022ec7@linux.ibm.com>","list_archive_url":null,"date":"2022-10-28T00:35:19","name":"[COMMITTED] PowerPC: Add support for RFC02653 - Dense Math Facility","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/21ec9a18-fa89-0828-f625-499680022ec7@linux.ibm.com/mbox/"},{"id":12017,"url":"https://patchwork.plctlab.org/api/1.2/patches/12017/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fd94047d-a070-45a6-3840-c105391718e0@linux.ibm.com/","msgid":"","list_archive_url":null,"date":"2022-10-28T00:37:18","name":"[COMMITTED] PowerPC: Add support for RFC02658 - MMA+ Outer-Product, Instructions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fd94047d-a070-45a6-3840-c105391718e0@linux.ibm.com/mbox/"},{"id":12122,"url":"https://patchwork.plctlab.org/api/1.2/patches/12122/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ac4f3f3c7115a824f73aca6935789b14d33c9a58.1666939920.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-28T06:53:02","name":"RISC-V: Fix build failure for -Werror=maybe-uninitialized","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ac4f3f3c7115a824f73aca6935789b14d33c9a58.1666939920.git.research_trasio@irq.a4lg.com/mbox/"},{"id":12181,"url":"https://patchwork.plctlab.org/api/1.2/patches/12181/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221028093840.19164-1-nelson@rivosinc.com/","msgid":"<20221028093840.19164-1-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-10-28T09:38:40","name":"RISC-V: Added SiFive custom cache control extensions.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221028093840.19164-1-nelson@rivosinc.com/mbox/"},{"id":12211,"url":"https://patchwork.plctlab.org/api/1.2/patches/12211/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4a280588-a85b-6ed3-634b-2b9cbc128f86@suse.com/","msgid":"<4a280588-a85b-6ed3-634b-2b9cbc128f86@suse.com>","list_archive_url":null,"date":"2022-10-28T10:06:35","name":"RISC-V/gas: fix build with certain gcc versions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4a280588-a85b-6ed3-634b-2b9cbc128f86@suse.com/mbox/"},{"id":12249,"url":"https://patchwork.plctlab.org/api/1.2/patches/12249/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/eb0e1bff-675e-72db-b8b1-b0f0e50b7121@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-28T12:35:35","name":"x86: minor improvements to optimize_imm() (part III)","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/eb0e1bff-675e-72db-b8b1-b0f0e50b7121@suse.com/mbox/"},{"id":12382,"url":"https://patchwork.plctlab.org/api/1.2/patches/12382/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/17f57574936af82be381a1451eac56b3709b60bb.1666968673.git.research_trasio@irq.a4lg.com/","msgid":"<17f57574936af82be381a1451eac56b3709b60bb.1666968673.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-28T14:52:12","name":"RISC-V: Emit mapping symbol with ISA string if non-default arch is used","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/17f57574936af82be381a1451eac56b3709b60bb.1666968673.git.research_trasio@irq.a4lg.com/mbox/"},{"id":12627,"url":"https://patchwork.plctlab.org/api/1.2/patches/12627/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221029034432.49859-1-nelson@rivosinc.com/","msgid":"<20221029034432.49859-1-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-10-29T03:44:32","name":"[committed] RISC-V: Always generate mapping symbols at the start of the sections.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221029034432.49859-1-nelson@rivosinc.com/mbox/"},{"id":12629,"url":"https://patchwork.plctlab.org/api/1.2/patches/12629/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1yxgzNJg5M48uPI@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-29T04:52:19","name":"NULL dereference read in som_write_object_contents","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1yxgzNJg5M48uPI@squeak.grove.modra.org/mbox/"},{"id":12630,"url":"https://patchwork.plctlab.org/api/1.2/patches/12630/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1yxnSHLY+FeB5DQ@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-29T04:52:45","name":"Fix small objcopy memory leak","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1yxnSHLY+FeB5DQ@squeak.grove.modra.org/mbox/"},{"id":12631,"url":"https://patchwork.plctlab.org/api/1.2/patches/12631/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1yxxfpJz+Jx4KTh@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-29T04:53:25","name":"pef: sanity check before malloc","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1yxxfpJz+Jx4KTh@squeak.grove.modra.org/mbox/"},{"id":12950,"url":"https://patchwork.plctlab.org/api/1.2/patches/12950/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-2-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-2-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:36","name":"[V3,01/15] sframe.h: Add SFrame format definition","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-2-indu.bhagat@oracle.com/mbox/"},{"id":12952,"url":"https://patchwork.plctlab.org/api/1.2/patches/12952/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-3-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-3-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:37","name":"[V3,02/15] gas: add new command line option --gsframe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-3-indu.bhagat@oracle.com/mbox/"},{"id":12951,"url":"https://patchwork.plctlab.org/api/1.2/patches/12951/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-4-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-4-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:38","name":"[V3,03/15] gas: generate .sframe from CFI directives","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-4-indu.bhagat@oracle.com/mbox/"},{"id":12956,"url":"https://patchwork.plctlab.org/api/1.2/patches/12956/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-5-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-5-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:39","name":"[V3,04/15] gas: testsuite: add new tests for SFrame unwind info","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-5-indu.bhagat@oracle.com/mbox/"},{"id":12955,"url":"https://patchwork.plctlab.org/api/1.2/patches/12955/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-6-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-6-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:40","name":"[V3,05/15] libsframe: add the SFrame library","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-6-indu.bhagat@oracle.com/mbox/"},{"id":12959,"url":"https://patchwork.plctlab.org/api/1.2/patches/12959/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-7-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-7-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:41","name":"[V3,06/15] bfd: linker: merge .sframe sections","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-7-indu.bhagat@oracle.com/mbox/"},{"id":12957,"url":"https://patchwork.plctlab.org/api/1.2/patches/12957/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-12-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-12-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:46","name":"[V3,11/15] libctf: add libsframe to LDFLAGS and LIBS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-12-indu.bhagat@oracle.com/mbox/"},{"id":12960,"url":"https://patchwork.plctlab.org/api/1.2/patches/12960/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-13-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-13-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:47","name":"[V3,12/15] src-release.sh: Add libsframe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-13-indu.bhagat@oracle.com/mbox/"},{"id":12953,"url":"https://patchwork.plctlab.org/api/1.2/patches/12953/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-14-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-14-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:48","name":"[V3,13/15] binutils/NEWS: add text for SFrame support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-14-indu.bhagat@oracle.com/mbox/"},{"id":12954,"url":"https://patchwork.plctlab.org/api/1.2/patches/12954/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-15-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-15-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:49","name":"[V3,14/15] gas/NEWS: add text about new command line option and SFrame support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-15-indu.bhagat@oracle.com/mbox/"},{"id":12958,"url":"https://patchwork.plctlab.org/api/1.2/patches/12958/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-16-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-16-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:50","name":"[V3,15/15] doc: add SFrame spec file","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-16-indu.bhagat@oracle.com/mbox/"}],"public":true,"mbox":"https://patchwork.plctlab.org/bundle/patchwork-bot/binutils-gdb_2022-10/mbox/"},{"id":7,"url":"https://patchwork.plctlab.org/api/1.2/bundles/7/","web_url":"https://patchwork.plctlab.org/bundle/patchwork-bot/binutils-gdb_2022-09/","project":{"id":2,"url":"https://patchwork.plctlab.org/api/1.2/projects/2/","name":"binutils-gdb","link_name":"binutils-gdb","list_id":"binutils.sourceware.org","list_email":"binutils@sourceware.org","web_url":"https://github.com/wangliu-iscas/Patchwork-Bundles/blob/main/binutils-gdb.md","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"name":"binutils-gdb_2022-09","owner":{"id":3,"url":"https://patchwork.plctlab.org/api/1.2/users/3/","username":"patchwork-bot","first_name":"","last_name":"","email":"ouuuleilei@gmail.com"},"patches":[{"id":1573,"url":"https://patchwork.plctlab.org/api/1.2/patches/1573/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930073211.2634-1-jiawei@iscas.ac.cn/","msgid":"<20220930073211.2634-1-jiawei@iscas.ac.cn>","list_archive_url":null,"date":"2022-09-30T07:32:11","name":"[V2] RISC-V: Add Smepmp CSR '\''mseccfg'\'' define and testcases.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930073211.2634-1-jiawei@iscas.ac.cn/mbox/"},{"id":1577,"url":"https://patchwork.plctlab.org/api/1.2/patches/1577/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/76fa0c3c-2303-ebdf-a765-ac4731581517@suse.com/","msgid":"<76fa0c3c-2303-ebdf-a765-ac4731581517@suse.com>","list_archive_url":null,"date":"2022-09-30T08:54:18","name":"objcopy: avoid \"shadowing\" of remove() function name","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/76fa0c3c-2303-ebdf-a765-ac4731581517@suse.com/mbox/"},{"id":1579,"url":"https://patchwork.plctlab.org/api/1.2/patches/1579/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930085852.71213-1-nelson@rivosinc.com/","msgid":"<20220930085852.71213-1-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-09-30T08:58:51","name":"[1/2] RISC-V: Output mapping symbols with ISA string.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930085852.71213-1-nelson@rivosinc.com/mbox/"},{"id":1578,"url":"https://patchwork.plctlab.org/api/1.2/patches/1578/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930085852.71213-2-nelson@rivosinc.com/","msgid":"<20220930085852.71213-2-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-09-30T08:58:52","name":"[2/2] RISC-V: Refer mapping symbol to R_RISCV_RELAX for rvc relaxations.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930085852.71213-2-nelson@rivosinc.com/mbox/"},{"id":1581,"url":"https://patchwork.plctlab.org/api/1.2/patches/1581/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930092058.71286-1-nelson@rivosinc.com/","msgid":"<20220930092058.71286-1-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-09-30T09:20:57","name":"[1/2] RISC-V: Output mapping symbols with ISA string.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930092058.71286-1-nelson@rivosinc.com/mbox/"},{"id":1580,"url":"https://patchwork.plctlab.org/api/1.2/patches/1580/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930092058.71286-2-nelson@rivosinc.com/","msgid":"<20220930092058.71286-2-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-09-30T09:20:58","name":"[2/2] RISC-V: Refer mapping symbol to R_RISCV_RELAX for rvc relaxations.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930092058.71286-2-nelson@rivosinc.com/mbox/"},{"id":1582,"url":"https://patchwork.plctlab.org/api/1.2/patches/1582/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5874dd79-0cf5-d65c-7ea2-13adfc799c0f@suse.com/","msgid":"<5874dd79-0cf5-d65c-7ea2-13adfc799c0f@suse.com>","list_archive_url":null,"date":"2022-09-30T09:41:29","name":"RISC-V: fix build after \"Add support for arbitrary immediate encoding formats\"","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5874dd79-0cf5-d65c-7ea2-13adfc799c0f@suse.com/mbox/"},{"id":1583,"url":"https://patchwork.plctlab.org/api/1.2/patches/1583/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/57d8ac2a-5757-3776-9924-99c17ca69938@suse.com/","msgid":"<57d8ac2a-5757-3776-9924-99c17ca69938@suse.com>","list_archive_url":null,"date":"2022-09-30T09:42:08","name":"RISC-V: fallout from \"re-arrange opcode table for consistent alias handling\"","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/57d8ac2a-5757-3776-9924-99c17ca69938@suse.com/mbox/"},{"id":1584,"url":"https://patchwork.plctlab.org/api/1.2/patches/1584/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e76ef8f7-72b9-5103-cb43-9608af01d017@suse.com/","msgid":"","list_archive_url":null,"date":"2022-09-30T09:42:50","name":"RISC-V: don'\''t cast expressions'\'' X_add_number to long in diagnostics","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e76ef8f7-72b9-5103-cb43-9608af01d017@suse.com/mbox/"},{"id":1585,"url":"https://patchwork.plctlab.org/api/1.2/patches/1585/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/61355429-24b3-17d0-ab03-6fa57ee861d5@suse.cz/","msgid":"<61355429-24b3-17d0-ab03-6fa57ee861d5@suse.cz>","list_archive_url":null,"date":"2022-09-30T09:48:52","name":"[RFC] add --enable-zstd-compressed-debug-sections configure option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/61355429-24b3-17d0-ab03-6fa57ee861d5@suse.cz/mbox/"},{"id":1586,"url":"https://patchwork.plctlab.org/api/1.2/patches/1586/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930103919.323690-1-christoph.muellner@vrull.eu/","msgid":"<20220930103919.323690-1-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2022-09-30T10:39:19","name":"RISC-V: Eliminate long-casts of X_add_number in diagnostics","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930103919.323690-1-christoph.muellner@vrull.eu/mbox/"},{"id":1590,"url":"https://patchwork.plctlab.org/api/1.2/patches/1590/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/DM6PR12MB4219C943049C6D883DEA3E55E7569@DM6PR12MB4219.namprd12.prod.outlook.com/","msgid":"","list_archive_url":null,"date":"2022-09-30T11:41:37","name":"[V2] Ignore DWARF debug information for -gsplit-dwarf with dwarf-5.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/DM6PR12MB4219C943049C6D883DEA3E55E7569@DM6PR12MB4219.namprd12.prod.outlook.com/mbox/"},{"id":1591,"url":"https://patchwork.plctlab.org/api/1.2/patches/1591/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c10321f9-d289-ef84-d263-bc278fb3d31b@suse.com/","msgid":"","list_archive_url":null,"date":"2022-09-30T11:59:04","name":"[1/4] RISC-V/gas: drop riscv_subsets static variable","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c10321f9-d289-ef84-d263-bc278fb3d31b@suse.com/mbox/"},{"id":1593,"url":"https://patchwork.plctlab.org/api/1.2/patches/1593/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3244eea0-c18c-e49a-4588-d69423130226@suse.com/","msgid":"<3244eea0-c18c-e49a-4588-d69423130226@suse.com>","list_archive_url":null,"date":"2022-09-30T11:59:23","name":"[2/4] RISC-V/gas: drop stray call to install_insn()","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3244eea0-c18c-e49a-4588-d69423130226@suse.com/mbox/"},{"id":1592,"url":"https://patchwork.plctlab.org/api/1.2/patches/1592/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/385d01fd-7e57-1f3f-1bae-30aa0c313d63@suse.com/","msgid":"<385d01fd-7e57-1f3f-1bae-30aa0c313d63@suse.com>","list_archive_url":null,"date":"2022-09-30T11:59:45","name":"[3/4] RISC-V/gas: don'\''t open-code insn_length()","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/385d01fd-7e57-1f3f-1bae-30aa0c313d63@suse.com/mbox/"},{"id":1594,"url":"https://patchwork.plctlab.org/api/1.2/patches/1594/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f5757acf-7b90-a0e3-5eea-3b97cc226930@suse.com/","msgid":"","list_archive_url":null,"date":"2022-09-30T12:00:12","name":"[4/4] RISC-V/gas: allow generating up to 176-bit instructions with .insn","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f5757acf-7b90-a0e3-5eea-3b97cc226930@suse.com/mbox/"},{"id":1596,"url":"https://patchwork.plctlab.org/api/1.2/patches/1596/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930140503.38233-1-chigot@adacore.com/","msgid":"<20220930140503.38233-1-chigot@adacore.com>","list_archive_url":null,"date":"2022-09-30T14:05:03","name":"ld/testsuite: consistently add board_ldflags when linking with GCC","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930140503.38233-1-chigot@adacore.com/mbox/"}],"public":true,"mbox":"https://patchwork.plctlab.org/bundle/patchwork-bot/binutils-gdb_2022-09/mbox/"}]' ++ jq -rc '.[].name' ++ echo '[{"id":6,"url":"https://patchwork.plctlab.org/api/1.2/bundles/6/","web_url":"https://patchwork.plctlab.org/bundle/patchwork-bot/binutils-gdb_2022-10/","project":{"id":2,"url":"https://patchwork.plctlab.org/api/1.2/projects/2/","name":"binutils-gdb","link_name":"binutils-gdb","list_id":"binutils.sourceware.org","list_email":"binutils@sourceware.org","web_url":"https://github.com/wangliu-iscas/Patchwork-Bundles/blob/main/binutils-gdb.md","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"name":"binutils-gdb_2022-10","owner":{"id":3,"url":"https://patchwork.plctlab.org/api/1.2/users/3/","username":"patchwork-bot","first_name":"","last_name":"","email":"ouuuleilei@gmail.com"},"patches":[{"id":1592,"url":"https://patchwork.plctlab.org/api/1.2/patches/1592/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/385d01fd-7e57-1f3f-1bae-30aa0c313d63@suse.com/","msgid":"<385d01fd-7e57-1f3f-1bae-30aa0c313d63@suse.com>","list_archive_url":null,"date":"2022-09-30T11:59:45","name":"[3/4] RISC-V/gas: don'\''t open-code insn_length()","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/385d01fd-7e57-1f3f-1bae-30aa0c313d63@suse.com/mbox/"},{"id":1594,"url":"https://patchwork.plctlab.org/api/1.2/patches/1594/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f5757acf-7b90-a0e3-5eea-3b97cc226930@suse.com/","msgid":"","list_archive_url":null,"date":"2022-09-30T12:00:12","name":"[4/4] RISC-V/gas: allow generating up to 176-bit instructions with .insn","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f5757acf-7b90-a0e3-5eea-3b97cc226930@suse.com/mbox/"},{"id":1596,"url":"https://patchwork.plctlab.org/api/1.2/patches/1596/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930140503.38233-1-chigot@adacore.com/","msgid":"<20220930140503.38233-1-chigot@adacore.com>","list_archive_url":null,"date":"2022-09-30T14:05:03","name":"ld/testsuite: consistently add board_ldflags when linking with GCC","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930140503.38233-1-chigot@adacore.com/mbox/"},{"id":1619,"url":"https://patchwork.plctlab.org/api/1.2/patches/1619/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221001014451.532772-1-maskray@google.com/","msgid":"<20221001014451.532772-1-maskray@google.com>","list_archive_url":null,"date":"2022-10-01T01:44:51","name":"gold, dwp: support zstd compressed input debug sections [PR 29641]","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221001014451.532772-1-maskray@google.com/mbox/"},{"id":1620,"url":"https://patchwork.plctlab.org/api/1.2/patches/1620/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221001023846.590825-1-maskray@google.com/","msgid":"<20221001023846.590825-1-maskray@google.com>","list_archive_url":null,"date":"2022-10-01T02:38:46","name":"gold: add --compress-debug-sections=zstd [PR 29641]","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221001023846.590825-1-maskray@google.com/mbox/"},{"id":1623,"url":"https://patchwork.plctlab.org/api/1.2/patches/1623/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b4477c7f666bdeb7f8e998633c7b0cb62310b9ef.1664599545.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-01T04:45:52","name":"[RFC,1/1] RISC-V: Implement common register pair framework","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b4477c7f666bdeb7f8e998633c7b0cb62310b9ef.1664599545.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1625,"url":"https://patchwork.plctlab.org/api/1.2/patches/1625/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/53a265a1f14d17a6f7b106082f610994c5d546e0.1664602025.git.research_trasio@irq.a4lg.com/","msgid":"<53a265a1f14d17a6f7b106082f610994c5d546e0.1664602025.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-01T05:27:31","name":"[RFC,1/1] RISC-V: Implement extension variants","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/53a265a1f14d17a6f7b106082f610994c5d546e0.1664602025.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1626,"url":"https://patchwork.plctlab.org/api/1.2/patches/1626/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8db04962aba9c780f133840a8934353a58f223fe.1664602716.git.research_trasio@irq.a4lg.com/","msgid":"<8db04962aba9c780f133840a8934353a58f223fe.1664602716.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-01T05:39:26","name":"[1/1] RISC-V: Move supervisor instructions after all unprivileged ones","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8db04962aba9c780f133840a8934353a58f223fe.1664602716.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1627,"url":"https://patchwork.plctlab.org/api/1.2/patches/1627/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221001062057.681440-1-maskray@google.com/","msgid":"<20221001062057.681440-1-maskray@google.com>","list_archive_url":null,"date":"2022-10-01T06:20:57","name":"readelf: support zstd compressed debug sections [PR 29640]","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221001062057.681440-1-maskray@google.com/mbox/"},{"id":1631,"url":"https://patchwork.plctlab.org/api/1.2/patches/1631/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/619f112539c0bdecd58e25664f1250a3479a37f5.1664707612.git.aburgess@redhat.com/","msgid":"<619f112539c0bdecd58e25664f1250a3479a37f5.1664707612.git.aburgess@redhat.com>","list_archive_url":null,"date":"2022-10-02T10:47:52","name":"[PATCHv2,2/2] opcodes/arm: add disassembler styling for arm","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/619f112539c0bdecd58e25664f1250a3479a37f5.1664707612.git.aburgess@redhat.com/mbox/"},{"id":1635,"url":"https://patchwork.plctlab.org/api/1.2/patches/1635/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221002185433.gl7dvytfh5wthifx@lug-owl.de/","msgid":"<20221002185433.gl7dvytfh5wthifx@lug-owl.de>","list_archive_url":null,"date":"2022-10-02T18:54:33","name":"diagnostics.h: GCC 13 got -Wself-move, breaks GDB build","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221002185433.gl7dvytfh5wthifx@lug-owl.de/mbox/"},{"id":1637,"url":"https://patchwork.plctlab.org/api/1.2/patches/1637/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003014313.28766-1-mark@harmstone.com/","msgid":"<20221003014313.28766-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-03T01:43:12","name":"[1/2] ld: Add --pdb option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003014313.28766-1-mark@harmstone.com/mbox/"},{"id":1638,"url":"https://patchwork.plctlab.org/api/1.2/patches/1638/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003014313.28766-2-mark@harmstone.com/","msgid":"<20221003014313.28766-2-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-03T01:43:13","name":"[2/2] ld: Add minimal pdb generation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003014313.28766-2-mark@harmstone.com/mbox/"},{"id":1640,"url":"https://patchwork.plctlab.org/api/1.2/patches/1640/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/597ed978-d121-220c-b56b-2ffb94bd091c@suse.cz/","msgid":"<597ed978-d121-220c-b56b-2ffb94bd091c@suse.cz>","list_archive_url":null,"date":"2022-10-03T07:50:38","name":"[1/2] refactor usage of compressed_debug_section_type","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/597ed978-d121-220c-b56b-2ffb94bd091c@suse.cz/mbox/"},{"id":1641,"url":"https://patchwork.plctlab.org/api/1.2/patches/1641/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b8acdd83-f33a-74b8-e21a-23719a0b1a60@suse.cz/","msgid":"","list_archive_url":null,"date":"2022-10-03T07:50:44","name":"[2/2] add --enable-default-compressed-debug-sections-algorithm configure option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b8acdd83-f33a-74b8-e21a-23719a0b1a60@suse.cz/mbox/"},{"id":1642,"url":"https://patchwork.plctlab.org/api/1.2/patches/1642/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003101328.1790113-1-aburgess@redhat.com/","msgid":"<20221003101328.1790113-1-aburgess@redhat.com>","list_archive_url":null,"date":"2022-10-03T10:13:28","name":"opcodes/riscv: style csr names as registers","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003101328.1790113-1-aburgess@redhat.com/mbox/"},{"id":1643,"url":"https://patchwork.plctlab.org/api/1.2/patches/1643/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7ba14fc4472ce97d4f7a4433cad8a571e89f82f4.1664793840.git.research_trasio@irq.a4lg.com/","msgid":"<7ba14fc4472ce97d4f7a4433cad8a571e89f82f4.1664793840.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-03T10:43:59","name":"[v3,1/6] RISC-V: Fix immediates to have \"immediate\" style","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7ba14fc4472ce97d4f7a4433cad8a571e89f82f4.1664793840.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1644,"url":"https://patchwork.plctlab.org/api/1.2/patches/1644/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a498bec37c1fd1dcda57cbf95e5f8cfba09b31d3.1664793840.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-03T10:44:00","name":"[v3,2/6] RISC-V: Fix printf argument types corresponding %x","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a498bec37c1fd1dcda57cbf95e5f8cfba09b31d3.1664793840.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1647,"url":"https://patchwork.plctlab.org/api/1.2/patches/1647/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0002ea716713ace4998a33dde0b81f4f890d10bf.1664793840.git.research_trasio@irq.a4lg.com/","msgid":"<0002ea716713ace4998a33dde0b81f4f890d10bf.1664793840.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-03T10:44:01","name":"[v3,3/6] RISC-V: Optimize riscv_disassemble_data printf","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0002ea716713ace4998a33dde0b81f4f890d10bf.1664793840.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1646,"url":"https://patchwork.plctlab.org/api/1.2/patches/1646/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c65fc3e9aa58965d6768a28c9fd7467fea9897a5.1664793840.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-03T10:44:02","name":"[v3,4/6] RISC-V: Print comma and tabs as the \"text\" style","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c65fc3e9aa58965d6768a28c9fd7467fea9897a5.1664793840.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1648,"url":"https://patchwork.plctlab.org/api/1.2/patches/1648/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5abe1d8a7694417b990e11d8f6cd6789573872e5.1664793840.git.research_trasio@irq.a4lg.com/","msgid":"<5abe1d8a7694417b990e11d8f6cd6789573872e5.1664793840.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-03T10:44:03","name":"[v3,5/6] RISC-V: Fix T-Head immediate types on printing","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5abe1d8a7694417b990e11d8f6cd6789573872e5.1664793840.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1649,"url":"https://patchwork.plctlab.org/api/1.2/patches/1649/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0b68af932117258c908db62cf87c3a15d3cdec41.1664793840.git.research_trasio@irq.a4lg.com/","msgid":"<0b68af932117258c908db62cf87c3a15d3cdec41.1664793840.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-03T10:44:04","name":"[v3,6/6] RISC-V: Print XTheadMemPair literal as \"immediate\"","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0b68af932117258c908db62cf87c3a15d3cdec41.1664793840.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1656,"url":"https://patchwork.plctlab.org/api/1.2/patches/1656/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/87lepxcd6x.fsf@redhat.com/","msgid":"<87lepxcd6x.fsf@redhat.com>","list_archive_url":null,"date":"2022-10-03T12:19:02","name":"Commit: readelf: Do not load section data from offset 0","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/87lepxcd6x.fsf@redhat.com/mbox/"},{"id":1659,"url":"https://patchwork.plctlab.org/api/1.2/patches/1659/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e0d369d419da9c0441f415da7f54352aead8f655.1664707612.git.aburgess@redhat.com/","msgid":"","list_archive_url":null,"date":"2022-10-03T16:37:36","name":"[PATCHv2,1/2] opcodes/arm: use '\''@'\'' consistently for the comment character","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e0d369d419da9c0441f415da7f54352aead8f655.1664707612.git.aburgess@redhat.com/mbox/"},{"id":1660,"url":"https://patchwork.plctlab.org/api/1.2/patches/1660/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003165848.11142-1-palmer@rivosinc.com/","msgid":"<20221003165848.11142-1-palmer@rivosinc.com>","list_archive_url":null,"date":"2022-10-03T16:58:48","name":"gas: NEWS: Mention the T-Head extensions that were recently added","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003165848.11142-1-palmer@rivosinc.com/mbox/"},{"id":1671,"url":"https://patchwork.plctlab.org/api/1.2/patches/1671/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/YzvrMEdkXjIn5Lfz@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-04T08:13:36","name":"Support objcopy changing compression to or from zstd","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/YzvrMEdkXjIn5Lfz@squeak.grove.modra.org/mbox/"},{"id":1673,"url":"https://patchwork.plctlab.org/api/1.2/patches/1673/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0bc857d306bb7c8130e5328dbe6b9ed2fed3ef87.1664873933.git.research_trasio@irq.a4lg.com/","msgid":"<0bc857d306bb7c8130e5328dbe6b9ed2fed3ef87.1664873933.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-04T08:59:07","name":"[1/2] RISC-V: Fix buffer overflow on print_insn_riscv","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0bc857d306bb7c8130e5328dbe6b9ed2fed3ef87.1664873933.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1672,"url":"https://patchwork.plctlab.org/api/1.2/patches/1672/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/89612fe01d902007bf84a7dfb0df5f85d5c166e4.1664873933.git.research_trasio@irq.a4lg.com/","msgid":"<89612fe01d902007bf84a7dfb0df5f85d5c166e4.1664873933.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-04T08:59:08","name":"[2/2] gdb/riscv: Fix buffer overflow on riscv_insn::fetch_instruction","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/89612fe01d902007bf84a7dfb0df5f85d5c166e4.1664873933.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1676,"url":"https://patchwork.plctlab.org/api/1.2/patches/1676/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fc849c94f4adcac1c4ccc5508c7a145a2f13b2a9.1664876744.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-04T09:45:49","name":"[v2,1/2] RISC-V: Fix buffer overflow on print_insn_riscv","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fc849c94f4adcac1c4ccc5508c7a145a2f13b2a9.1664876744.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1677,"url":"https://patchwork.plctlab.org/api/1.2/patches/1677/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4eb6e59ae2e790dbbf2bc92477edd281648d8814.1664876744.git.research_trasio@irq.a4lg.com/","msgid":"<4eb6e59ae2e790dbbf2bc92477edd281648d8814.1664876744.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-04T09:45:50","name":"[v2,2/2] gdb/riscv: Partial support for instructions up to 176-bits","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4eb6e59ae2e790dbbf2bc92477edd281648d8814.1664876744.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1678,"url":"https://patchwork.plctlab.org/api/1.2/patches/1678/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ebf16f9e1f45115d0793952ccb4a94d4233303f9.1664882725.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-04T11:25:56","name":"[v3,1/2] RISC-V: Fix buffer overflow on print_insn_riscv","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ebf16f9e1f45115d0793952ccb4a94d4233303f9.1664882725.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1679,"url":"https://patchwork.plctlab.org/api/1.2/patches/1679/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/83464b09b8649525259c69c853dfa2c9575a204b.1664882725.git.research_trasio@irq.a4lg.com/","msgid":"<83464b09b8649525259c69c853dfa2c9575a204b.1664882725.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-04T11:25:57","name":"[v3,2/2] gdb/riscv: Partial support for instructions up to 176-bit","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/83464b09b8649525259c69c853dfa2c9575a204b.1664882725.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1681,"url":"https://patchwork.plctlab.org/api/1.2/patches/1681/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ffa9c1d7-e8c2-a62b-ef3e-b565c0ffbe5b@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-04T13:56:27","name":"RISC-V: Zicbo{m,p,z} adjustments to riscv_multi_subset_supports_ext()","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ffa9c1d7-e8c2-a62b-ef3e-b565c0ffbe5b@suse.com/mbox/"},{"id":1690,"url":"https://patchwork.plctlab.org/api/1.2/patches/1690/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221004161720.1963953-1-vladimir.mezentsev@oracle.com/","msgid":"<20221004161720.1963953-1-vladimir.mezentsev@oracle.com>","list_archive_url":null,"date":"2022-10-04T16:17:20","name":"gprofng: fix build with --enable-pgo-build=lto","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221004161720.1963953-1-vladimir.mezentsev@oracle.com/mbox/"},{"id":1691,"url":"https://patchwork.plctlab.org/api/1.2/patches/1691/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c0211bc9c57be6c79c6d878ce147f63b657f461d.camel@espressif.com/","msgid":"","list_archive_url":null,"date":"2022-10-04T16:22:05","name":"bfd: xtensa: fix __stop_SECTION literal drop,","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c0211bc9c57be6c79c6d878ce147f63b657f461d.camel@espressif.com/mbox/"},{"id":1702,"url":"https://patchwork.plctlab.org/api/1.2/patches/1702/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5f482299-6c60-b2b3-9abe-f4a55a5a26c5@univ-grenoble-alpes.fr/","msgid":"<5f482299-6c60-b2b3-9abe-f4a55a5a26c5@univ-grenoble-alpes.fr>","list_archive_url":null,"date":"2022-10-04T20:03:20","name":"[RFC] bfd: use bfd_vma for the 64-bit version of put[lb] and get[lb]","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5f482299-6c60-b2b3-9abe-f4a55a5a26c5@univ-grenoble-alpes.fr/mbox/"},{"id":1711,"url":"https://patchwork.plctlab.org/api/1.2/patches/1711/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Yz0Gsxdxe0TePbJT@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-05T04:23:15","name":"PR29647, objdump -S looping","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Yz0Gsxdxe0TePbJT@squeak.grove.modra.org/mbox/"},{"id":1712,"url":"https://patchwork.plctlab.org/api/1.2/patches/1712/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/02d747d2-f57b-0fb5-b893-842b6cc41f2f@suse.com/","msgid":"<02d747d2-f57b-0fb5-b893-842b6cc41f2f@suse.com>","list_archive_url":null,"date":"2022-10-05T07:20:47","name":"[v3,1/7] x86: constify parse_insn()'\''s input","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/02d747d2-f57b-0fb5-b893-842b6cc41f2f@suse.com/mbox/"},{"id":1713,"url":"https://patchwork.plctlab.org/api/1.2/patches/1713/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/925cb740-4e1b-abc4-8526-aaab6faae5e1@suse.com/","msgid":"<925cb740-4e1b-abc4-8526-aaab6faae5e1@suse.com>","list_archive_url":null,"date":"2022-10-05T07:22:19","name":"[v3,2/7] x86: introduce Pass2 insn attribute","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/925cb740-4e1b-abc4-8526-aaab6faae5e1@suse.com/mbox/"},{"id":1714,"url":"https://patchwork.plctlab.org/api/1.2/patches/1714/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e16d3e78-39ca-f715-508f-a4104b8ab9a9@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-05T07:23:51","name":"[v3,3/7] x86: re-work insn/suffix recognition","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e16d3e78-39ca-f715-508f-a4104b8ab9a9@suse.com/mbox/"},{"id":1715,"url":"https://patchwork.plctlab.org/api/1.2/patches/1715/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e4e4b80b-794c-7485-1997-685adab8fb27@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-05T07:24:20","name":"[v3,4/7] x86-64: further re-work insn/suffix recognition to also cover MOVSL","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e4e4b80b-794c-7485-1997-685adab8fb27@suse.com/mbox/"},{"id":1716,"url":"https://patchwork.plctlab.org/api/1.2/patches/1716/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/540678fc-8bff-ec68-c97c-478d2631998c@suse.com/","msgid":"<540678fc-8bff-ec68-c97c-478d2631998c@suse.com>","list_archive_url":null,"date":"2022-10-05T07:24:55","name":"[v3,5/7] ix86: don'\''t recognize/derive Q suffix in the common case","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/540678fc-8bff-ec68-c97c-478d2631998c@suse.com/mbox/"},{"id":1718,"url":"https://patchwork.plctlab.org/api/1.2/patches/1718/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e4692495-7d3d-074d-14f9-364d4a9a998c@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-05T07:25:25","name":"[v3,6/7] x86-64: allow HLE store of accumulator to absolute 32-bit address","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e4692495-7d3d-074d-14f9-364d4a9a998c@suse.com/mbox/"},{"id":1717,"url":"https://patchwork.plctlab.org/api/1.2/patches/1717/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e8014ebd-d16b-17a7-9f34-3700fc164136@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-05T07:25:57","name":"[v3,7/7] x86: move bad-use-of-TLS-reloc check","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e8014ebd-d16b-17a7-9f34-3700fc164136@suse.com/mbox/"},{"id":1719,"url":"https://patchwork.plctlab.org/api/1.2/patches/1719/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1266f001-4511-2662-dba9-14b4d0317c57@suse.com/","msgid":"<1266f001-4511-2662-dba9-14b4d0317c57@suse.com>","list_archive_url":null,"date":"2022-10-05T07:40:50","name":"x86: drop \"regmask\" static variable","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1266f001-4511-2662-dba9-14b4d0317c57@suse.com/mbox/"},{"id":1751,"url":"https://patchwork.plctlab.org/api/1.2/patches/1751/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/af45c5d57c221e43101c2aa38b14f4b4ac12d011.1665031170.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-06T04:40:15","name":"[v2,1/2] RISC-V: Fallback for instructions longer than 64b","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/af45c5d57c221e43101c2aa38b14f4b4ac12d011.1665031170.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1752,"url":"https://patchwork.plctlab.org/api/1.2/patches/1752/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c6e55781245dd3e8e9b8debd6130fc5449dfbd55.1665031170.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-06T04:40:16","name":"[v2,2/2] RISC-V: Improve \"bits undefined\" diagnostics","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c6e55781245dd3e8e9b8debd6130fc5449dfbd55.1665031170.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1776,"url":"https://patchwork.plctlab.org/api/1.2/patches/1776/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d52952119e15357c0e823f8a2398999359588b4d.1665050099.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-06T09:56:30","name":"[v3,1/2] RISC-V: Fallback for instructions longer than 64b","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d52952119e15357c0e823f8a2398999359588b4d.1665050099.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1777,"url":"https://patchwork.plctlab.org/api/1.2/patches/1777/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d907b1997f60ff7823c4a23e281ec9d8ddcbf3f1.1665050099.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-06T09:56:31","name":"[v3,2/2] RISC-V: Improve \"bits undefined\" diagnostics","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d907b1997f60ff7823c4a23e281ec9d8ddcbf3f1.1665050099.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1781,"url":"https://patchwork.plctlab.org/api/1.2/patches/1781/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221006114628.304185-1-chigot@adacore.com/","msgid":"<20221006114628.304185-1-chigot@adacore.com>","list_archive_url":null,"date":"2022-10-06T11:46:28","name":"RISC-V: fix linker message when relaxation deletes bytes","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221006114628.304185-1-chigot@adacore.com/mbox/"},{"id":1801,"url":"https://patchwork.plctlab.org/api/1.2/patches/1801/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Yz+Yhyg7UewC9/kp@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-07T03:09:59","name":"PR29653, objcopy/strip: fuzzed small input file induces large output file","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Yz+Yhyg7UewC9/kp@squeak.grove.modra.org/mbox/"},{"id":1803,"url":"https://patchwork.plctlab.org/api/1.2/patches/1803/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/PH1P110MB16505D9D39EC5B1DE22FE3D5EC5F9@PH1P110MB1650.NAMP110.PROD.OUTLOOK.COM/","msgid":"","list_archive_url":null,"date":"2022-10-07T04:10:07","name":"@CPP_FOR_BUILD@ problem since binutils-2.38","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/PH1P110MB16505D9D39EC5B1DE22FE3D5EC5F9@PH1P110MB1650.NAMP110.PROD.OUTLOOK.COM/mbox/"},{"id":1827,"url":"https://patchwork.plctlab.org/api/1.2/patches/1827/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8e13bce108ac10a0c1dd911e23ec572926f7ae44.1665203374.git.research_trasio@irq.a4lg.com/","msgid":"<8e13bce108ac10a0c1dd911e23ec572926f7ae44.1665203374.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-08T04:29:53","name":"[v2,1/1] RISC-V: Test DWARF register numbers for \"fp\"","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8e13bce108ac10a0c1dd911e23ec572926f7ae44.1665203374.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1828,"url":"https://patchwork.plctlab.org/api/1.2/patches/1828/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0883001b3572e54d3fba264429c7ade2adb66610.1665203441.git.research_trasio@irq.a4lg.com/","msgid":"<0883001b3572e54d3fba264429c7ade2adb66610.1665203441.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-08T04:31:15","name":"[1/1] RISC-V: Move standard hints before all instructions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0883001b3572e54d3fba264429c7ade2adb66610.1665203441.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1829,"url":"https://patchwork.plctlab.org/api/1.2/patches/1829/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/58e16a241d7376fcae2515c6bd5a2b41d275eeba.1665203531.git.research_trasio@irq.a4lg.com/","msgid":"<58e16a241d7376fcae2515c6bd5a2b41d275eeba.1665203531.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-08T04:32:18","name":"[RFC,1/1] RISC-V: Imply '\''Zicsr'\'' from privileged extensions with CSRs","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/58e16a241d7376fcae2515c6bd5a2b41d275eeba.1665203531.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1830,"url":"https://patchwork.plctlab.org/api/1.2/patches/1830/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/cb5076fc96e8f2097779a3abcde843dcdd660031.1665203660.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-08T04:34:23","name":"[1/5] opcodes/riscv-dis.c: Tidying with comments/clarity","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/cb5076fc96e8f2097779a3abcde843dcdd660031.1665203660.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1832,"url":"https://patchwork.plctlab.org/api/1.2/patches/1832/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1f1aa0838bf9c4f10a45fcfe3c682f7efc79d9ae.1665203660.git.research_trasio@irq.a4lg.com/","msgid":"<1f1aa0838bf9c4f10a45fcfe3c682f7efc79d9ae.1665203660.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-08T04:34:24","name":"[2/5] opcodes/riscv-dis.c: Tidying with spacing","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1f1aa0838bf9c4f10a45fcfe3c682f7efc79d9ae.1665203660.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1831,"url":"https://patchwork.plctlab.org/api/1.2/patches/1831/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/740bc5e2d2618d236519b39fedd1a1d7ae4e05da.1665203660.git.research_trasio@irq.a4lg.com/","msgid":"<740bc5e2d2618d236519b39fedd1a1d7ae4e05da.1665203660.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-08T04:34:25","name":"[3/5] opcodes/riscv-dis.c: Use bool type whenever possible","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/740bc5e2d2618d236519b39fedd1a1d7ae4e05da.1665203660.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1833,"url":"https://patchwork.plctlab.org/api/1.2/patches/1833/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6e3a9c235e317f441b4383b3daa68f2051bdc149.1665203660.git.research_trasio@irq.a4lg.com/","msgid":"<6e3a9c235e317f441b4383b3daa68f2051bdc149.1665203660.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-08T04:34:26","name":"[4/5] opcodes/riscv-dis.c: Make XLEN variable static","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6e3a9c235e317f441b4383b3daa68f2051bdc149.1665203660.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1834,"url":"https://patchwork.plctlab.org/api/1.2/patches/1834/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ad929233a62d887495122721340b2f9c80392963.1665203660.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-08T04:34:27","name":"[5/5] opcodes/riscv-dis.c: Remove last_map_state","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ad929233a62d887495122721340b2f9c80392963.1665203660.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1836,"url":"https://patchwork.plctlab.org/api/1.2/patches/1836/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d07e2b6f36ea2fd5830924a9bfeda941b774b687.1665290422.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-09T05:09:22","name":"RISC-V: Move certain arrays to riscv-opc.c","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d07e2b6f36ea2fd5830924a9bfeda941b774b687.1665290422.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1844,"url":"https://patchwork.plctlab.org/api/1.2/patches/1844/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010004623.16582-1-mark@harmstone.com/","msgid":"<20221010004623.16582-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-10T00:46:22","name":"[v2,1/2] ld: Add --pdb option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010004623.16582-1-mark@harmstone.com/mbox/"},{"id":1845,"url":"https://patchwork.plctlab.org/api/1.2/patches/1845/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010004623.16582-2-mark@harmstone.com/","msgid":"<20221010004623.16582-2-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-10T00:46:23","name":"[v2,2/2] ld: Add minimal pdb generation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010004623.16582-2-mark@harmstone.com/mbox/"},{"id":1890,"url":"https://patchwork.plctlab.org/api/1.2/patches/1890/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010200433.414320-1-vladimir.mezentsev@oracle.com/","msgid":"<20221010200433.414320-1-vladimir.mezentsev@oracle.com>","list_archive_url":null,"date":"2022-10-10T20:04:33","name":"gprofng: run tests without installation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010200433.414320-1-vladimir.mezentsev@oracle.com/mbox/"},{"id":1893,"url":"https://patchwork.plctlab.org/api/1.2/patches/1893/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010230426.719238-1-vladimir.mezentsev@oracle.com/","msgid":"<20221010230426.719238-1-vladimir.mezentsev@oracle.com>","list_archive_url":null,"date":"2022-10-10T23:04:26","name":"[2/2] gprofng: use the --libdir path to find libraries","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010230426.719238-1-vladimir.mezentsev@oracle.com/mbox/"},{"id":1894,"url":"https://patchwork.plctlab.org/api/1.2/patches/1894/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010235155.842469-1-vladimir.mezentsev@oracle.com/","msgid":"<20221010235155.842469-1-vladimir.mezentsev@oracle.com>","list_archive_url":null,"date":"2022-10-10T23:51:55","name":"[3/3] gprofng: no need to build version.texi","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010235155.842469-1-vladimir.mezentsev@oracle.com/mbox/"},{"id":1895,"url":"https://patchwork.plctlab.org/api/1.2/patches/1895/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011003702.4287-1-mark@harmstone.com/","msgid":"<20221011003702.4287-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-11T00:37:01","name":"[v3,1/2] ld: Add --pdb option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011003702.4287-1-mark@harmstone.com/mbox/"},{"id":1897,"url":"https://patchwork.plctlab.org/api/1.2/patches/1897/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011003702.4287-2-mark@harmstone.com/","msgid":"<20221011003702.4287-2-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-11T00:37:02","name":"[v3,2/2] ld: Add minimal pdb generation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011003702.4287-2-mark@harmstone.com/mbox/"},{"id":1928,"url":"https://patchwork.plctlab.org/api/1.2/patches/1928/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011175332.17156-1-mark@harmstone.com/","msgid":"<20221011175332.17156-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-11T17:53:31","name":"[v4,1/2] ld: Add --pdb option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011175332.17156-1-mark@harmstone.com/mbox/"},{"id":1929,"url":"https://patchwork.plctlab.org/api/1.2/patches/1929/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011175332.17156-2-mark@harmstone.com/","msgid":"<20221011175332.17156-2-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-11T17:53:32","name":"[v4,2/2] ld: Add minimal pdb generation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011175332.17156-2-mark@harmstone.com/mbox/"},{"id":1941,"url":"https://patchwork.plctlab.org/api/1.2/patches/1941/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221012031005.237446-1-simon.marchi@polymtl.ca/","msgid":"<20221012031005.237446-1-simon.marchi@polymtl.ca>","list_archive_url":null,"date":"2022-10-12T03:10:05","name":"[pushed] Re-apply \"Pass PKG_CONFIG_PATH down from top-level Makefile\"","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221012031005.237446-1-simon.marchi@polymtl.ca/mbox/"},{"id":1976,"url":"https://patchwork.plctlab.org/api/1.2/patches/1976/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1216a3f8-2273-8681-f528-9493a66891f0@suse.com/","msgid":"<1216a3f8-2273-8681-f528-9493a66891f0@suse.com>","list_archive_url":null,"date":"2022-10-13T08:16:49","name":"[v4,1/8] x86: constify parse_insn()'\''s input","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1216a3f8-2273-8681-f528-9493a66891f0@suse.com/mbox/"},{"id":1977,"url":"https://patchwork.plctlab.org/api/1.2/patches/1977/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/11599bbe-c779-aa9f-4d5d-c2243f0e69dc@suse.com/","msgid":"<11599bbe-c779-aa9f-4d5d-c2243f0e69dc@suse.com>","list_archive_url":null,"date":"2022-10-13T08:17:17","name":"[v4,2/8] x86: introduce Pass2 insn attribute","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/11599bbe-c779-aa9f-4d5d-c2243f0e69dc@suse.com/mbox/"},{"id":1978,"url":"https://patchwork.plctlab.org/api/1.2/patches/1978/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/357273a3-060c-23db-72da-3fc9d1be3d2a@suse.com/","msgid":"<357273a3-060c-23db-72da-3fc9d1be3d2a@suse.com>","list_archive_url":null,"date":"2022-10-13T08:18:09","name":"[v4,3/8] x86: re-work insn/suffix recognition","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/357273a3-060c-23db-72da-3fc9d1be3d2a@suse.com/mbox/"},{"id":1979,"url":"https://patchwork.plctlab.org/api/1.2/patches/1979/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0ec0587f-6a7b-45b6-8346-e5d774e73636@suse.com/","msgid":"<0ec0587f-6a7b-45b6-8346-e5d774e73636@suse.com>","list_archive_url":null,"date":"2022-10-13T08:18:39","name":"[v4,4/8] x86-64: further re-work insn/suffix recognition to also cover MOVSL","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0ec0587f-6a7b-45b6-8346-e5d774e73636@suse.com/mbox/"},{"id":1980,"url":"https://patchwork.plctlab.org/api/1.2/patches/1980/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fb617d0b-8759-3169-5a65-1178b7fef3d7@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-13T08:19:34","name":"[v4,5/8] ix86: don'\''t recognize/derive Q suffix in the common case","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fb617d0b-8759-3169-5a65-1178b7fef3d7@suse.com/mbox/"},{"id":1981,"url":"https://patchwork.plctlab.org/api/1.2/patches/1981/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1df3bd01-99c5-f56c-d937-970edd42b2b8@suse.com/","msgid":"<1df3bd01-99c5-f56c-d937-970edd42b2b8@suse.com>","list_archive_url":null,"date":"2022-10-13T08:20:14","name":"[v4,6/8] x86-64: allow HLE store of accumulator to absolute 32-bit address","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1df3bd01-99c5-f56c-d937-970edd42b2b8@suse.com/mbox/"},{"id":1982,"url":"https://patchwork.plctlab.org/api/1.2/patches/1982/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8486a218-39ec-16b2-5c6c-5037196b93cf@suse.com/","msgid":"<8486a218-39ec-16b2-5c6c-5037196b93cf@suse.com>","list_archive_url":null,"date":"2022-10-13T08:21:00","name":"[v4,7/8] x86: move bad-use-of-TLS-reloc check","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8486a218-39ec-16b2-5c6c-5037196b93cf@suse.com/mbox/"},{"id":1983,"url":"https://patchwork.plctlab.org/api/1.2/patches/1983/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7d82692d-93df-fbee-9efb-2f44e8a91df3@suse.com/","msgid":"<7d82692d-93df-fbee-9efb-2f44e8a91df3@suse.com>","list_archive_url":null,"date":"2022-10-13T08:22:00","name":"[v4,8/8] x86: drop (now) stray IsString","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7d82692d-93df-fbee-9efb-2f44e8a91df3@suse.com/mbox/"},{"id":2013,"url":"https://patchwork.plctlab.org/api/1.2/patches/2013/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8ab93d7a617ad480dd786210f46db0e5aa07d1ac.1665655719.git.research_trasio@irq.a4lg.com/","msgid":"<8ab93d7a617ad480dd786210f46db0e5aa07d1ac.1665655719.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-13T10:11:41","name":"include: Declare getopt function on old GNU libc","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8ab93d7a617ad480dd786210f46db0e5aa07d1ac.1665655719.git.research_trasio@irq.a4lg.com/mbox/"},{"id":2352,"url":"https://patchwork.plctlab.org/api/1.2/patches/2352/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221013201332.2747246-1-maskray@google.com/","msgid":"<20221013201332.2747246-1-maskray@google.com>","list_archive_url":null,"date":"2022-10-13T20:13:32","name":"ld: Add --undefined-version","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221013201332.2747246-1-maskray@google.com/mbox/"},{"id":2532,"url":"https://patchwork.plctlab.org/api/1.2/patches/2532/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014063520.1428330-2-zengxiao@eswincomputing.com/","msgid":"<20221014063520.1428330-2-zengxiao@eswincomputing.com>","list_archive_url":null,"date":"2022-10-14T06:35:20","name":"[1/1] RISC-V: Make R_RISCV_SUB6 conforms to riscv abi standard","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014063520.1428330-2-zengxiao@eswincomputing.com/mbox/"},{"id":2560,"url":"https://patchwork.plctlab.org/api/1.2/patches/2560/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/027ae69a-636b-6757-297a-eec42936401e@linaro.org/","msgid":"<027ae69a-636b-6757-297a-eec42936401e@linaro.org>","list_archive_url":null,"date":"2022-10-14T07:58:22","name":"[v3] aarch64-pe support for LD, GAS and BFD","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/027ae69a-636b-6757-297a-eec42936401e@linaro.org/mbox/"},{"id":2602,"url":"https://patchwork.plctlab.org/api/1.2/patches/2602/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-2-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-2-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:39","name":"[01/10] Support Intel AVX-IFMA","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-2-haochen.jiang@intel.com/mbox/"},{"id":2608,"url":"https://patchwork.plctlab.org/api/1.2/patches/2608/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-3-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-3-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:40","name":"[02/10] Support Intel AVX-VNNI-INT8","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-3-haochen.jiang@intel.com/mbox/"},{"id":2611,"url":"https://patchwork.plctlab.org/api/1.2/patches/2611/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-4-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-4-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:41","name":"[03/10] Support Intel AVX-NE-CONVERT","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-4-haochen.jiang@intel.com/mbox/"},{"id":2610,"url":"https://patchwork.plctlab.org/api/1.2/patches/2610/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-5-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-5-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:42","name":"[04/10] Support Intel CMPccXADD","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-5-haochen.jiang@intel.com/mbox/"},{"id":2601,"url":"https://patchwork.plctlab.org/api/1.2/patches/2601/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-6-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-6-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:43","name":"[05/10] Add handler for more i386_cpu_flags","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-6-haochen.jiang@intel.com/mbox/"},{"id":2606,"url":"https://patchwork.plctlab.org/api/1.2/patches/2606/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-7-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-7-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:44","name":"[06/10] Support Intel RAO-INT","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-7-haochen.jiang@intel.com/mbox/"},{"id":2609,"url":"https://patchwork.plctlab.org/api/1.2/patches/2609/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-8-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-8-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:45","name":"[07/10] Support Intel WRMSRNS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-8-haochen.jiang@intel.com/mbox/"},{"id":2605,"url":"https://patchwork.plctlab.org/api/1.2/patches/2605/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-9-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-9-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:46","name":"[08/10] Support Intel MSRLIST","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-9-haochen.jiang@intel.com/mbox/"},{"id":2607,"url":"https://patchwork.plctlab.org/api/1.2/patches/2607/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-10-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-10-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:47","name":"[09/10] Support Intel AMX-FP16","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-10-haochen.jiang@intel.com/mbox/"},{"id":2604,"url":"https://patchwork.plctlab.org/api/1.2/patches/2604/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-11-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-11-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:48","name":"[10/10] Support Intel PREFETCHI","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-11-haochen.jiang@intel.com/mbox/"},{"id":2643,"url":"https://patchwork.plctlab.org/api/1.2/patches/2643/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7bac66be-535e-9051-d674-f2f5ba180e17@suse.com/","msgid":"<7bac66be-535e-9051-d674-f2f5ba180e17@suse.com>","list_archive_url":null,"date":"2022-10-14T10:22:34","name":"x86: fold AVX512-VNNI disassembler entries with AVX-VNNI ones","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7bac66be-535e-9051-d674-f2f5ba180e17@suse.com/mbox/"},{"id":2654,"url":"https://patchwork.plctlab.org/api/1.2/patches/2654/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0lIo5+ncY/MqBEq@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-14T11:31:47","name":"PR29677, Field `the_bfd` of `asymbol` is uninitialised","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0lIo5+ncY/MqBEq@squeak.grove.modra.org/mbox/"},{"id":2656,"url":"https://patchwork.plctlab.org/api/1.2/patches/2656/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0lJksn49ZpABY89@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-14T11:35:46","name":"e200 LSP support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0lJksn49ZpABY89@squeak.grove.modra.org/mbox/"},{"id":2657,"url":"https://patchwork.plctlab.org/api/1.2/patches/2657/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0lJxxYoeD5iDYAD@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-14T11:36:39","name":"PowerPC SPE disassembly and tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0lJxxYoeD5iDYAD@squeak.grove.modra.org/mbox/"},{"id":2695,"url":"https://patchwork.plctlab.org/api/1.2/patches/2695/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/DM6PR12MB4219611F6CC2A0702884A602E7249@DM6PR12MB4219.namprd12.prod.outlook.com/","msgid":"","list_archive_url":null,"date":"2022-10-14T13:29:40","name":"Binutils: Adding new testcase for addr2line.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/DM6PR12MB4219611F6CC2A0702884A602E7249@DM6PR12MB4219.namprd12.prod.outlook.com/mbox/"},{"id":2700,"url":"https://patchwork.plctlab.org/api/1.2/patches/2700/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9fd2c88d-98b2-99a4-419f-c7235b2cf960@suse.com/","msgid":"<9fd2c88d-98b2-99a4-419f-c7235b2cf960@suse.com>","list_archive_url":null,"date":"2022-10-14T14:11:35","name":"x86: properly decode EVEX.W for AVX512_4{FMAPS,VNNIW} insns","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9fd2c88d-98b2-99a4-419f-c7235b2cf960@suse.com/mbox/"},{"id":2981,"url":"https://patchwork.plctlab.org/api/1.2/patches/2981/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0uLzalqjm4C87GN@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-16T04:42:53","name":"PowerPC se_rfmci and VLE, SPE2 and LSP insns with -many","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0uLzalqjm4C87GN@squeak.grove.modra.org/mbox/"},{"id":3152,"url":"https://patchwork.plctlab.org/api/1.2/patches/3152/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221016232419.1135-1-mark@harmstone.com/","msgid":"<20221016232419.1135-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-16T23:24:18","name":"[v5,1/2] ld: Add --pdb option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221016232419.1135-1-mark@harmstone.com/mbox/"},{"id":3151,"url":"https://patchwork.plctlab.org/api/1.2/patches/3151/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221016232419.1135-2-mark@harmstone.com/","msgid":"<20221016232419.1135-2-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-16T23:24:19","name":"[v5,2/2] ld: Add minimal pdb generation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221016232419.1135-2-mark@harmstone.com/mbox/"},{"id":3258,"url":"https://patchwork.plctlab.org/api/1.2/patches/3258/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/19c08747-fa5b-1e67-3dd2-c891a2c0c1fa@suse.com/","msgid":"<19c08747-fa5b-1e67-3dd2-c891a2c0c1fa@suse.com>","list_archive_url":null,"date":"2022-10-17T07:44:51","name":"x86: correct CPU_AMX_{BF16,INT8}_FLAGS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/19c08747-fa5b-1e67-3dd2-c891a2c0c1fa@suse.com/mbox/"},{"id":3272,"url":"https://patchwork.plctlab.org/api/1.2/patches/3272/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/85dd526c-d3a7-72dc-5444-ed5573eebec1@suse.com/","msgid":"<85dd526c-d3a7-72dc-5444-ed5573eebec1@suse.com>","list_archive_url":null,"date":"2022-10-17T08:30:12","name":"x86: generalize gas documentation for disabling of ISA extensions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/85dd526c-d3a7-72dc-5444-ed5573eebec1@suse.com/mbox/"},{"id":3759,"url":"https://patchwork.plctlab.org/api/1.2/patches/3759/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-2-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-2-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:15:58","name":"[V2,01/15] sframe.h: Add SFrame format definition","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-2-indu.bhagat@oracle.com/mbox/"},{"id":3762,"url":"https://patchwork.plctlab.org/api/1.2/patches/3762/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-3-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-3-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:15:59","name":"[V2,02/15] gas: add new command line option --gsframe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-3-indu.bhagat@oracle.com/mbox/"},{"id":3761,"url":"https://patchwork.plctlab.org/api/1.2/patches/3761/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-4-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-4-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:00","name":"[V2,03/15] gas: generate .sframe from CFI directives","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-4-indu.bhagat@oracle.com/mbox/"},{"id":3760,"url":"https://patchwork.plctlab.org/api/1.2/patches/3760/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-5-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-5-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:01","name":"[V2,04/15] gas: testsuite: add new tests for SFrame unwind info","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-5-indu.bhagat@oracle.com/mbox/"},{"id":3764,"url":"https://patchwork.plctlab.org/api/1.2/patches/3764/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-6-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-6-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:02","name":"[V2,05/15] libsframe: add the SFrame library","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-6-indu.bhagat@oracle.com/mbox/"},{"id":3766,"url":"https://patchwork.plctlab.org/api/1.2/patches/3766/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-7-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-7-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:03","name":"[V2,06/15] bfd: linker: merge .sframe sections","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-7-indu.bhagat@oracle.com/mbox/"},{"id":3763,"url":"https://patchwork.plctlab.org/api/1.2/patches/3763/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-8-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-8-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:04","name":"[V2,07/15] readelf/objdump: support for SFrame section","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-8-indu.bhagat@oracle.com/mbox/"},{"id":3765,"url":"https://patchwork.plctlab.org/api/1.2/patches/3765/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-9-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-9-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:05","name":"[V2,08/15] unwinder: generate backtrace using SFrame format","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-9-indu.bhagat@oracle.com/mbox/"},{"id":3770,"url":"https://patchwork.plctlab.org/api/1.2/patches/3770/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-10-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-10-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:06","name":"[V2,09/15] unwinder: Add SFrame unwinder tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-10-indu.bhagat@oracle.com/mbox/"},{"id":3769,"url":"https://patchwork.plctlab.org/api/1.2/patches/3769/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-11-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-11-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:07","name":"[V2,10/15] gdb: sim: buildsystem changes to accommodate libsframe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-11-indu.bhagat@oracle.com/mbox/"},{"id":3771,"url":"https://patchwork.plctlab.org/api/1.2/patches/3771/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-12-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-12-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:08","name":"[V2,11/15] libctf: add libsframe to LDFLAGS and LIBS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-12-indu.bhagat@oracle.com/mbox/"},{"id":3768,"url":"https://patchwork.plctlab.org/api/1.2/patches/3768/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-13-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-13-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:09","name":"[V2,12/15] src-release.sh: Add libsframe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-13-indu.bhagat@oracle.com/mbox/"},{"id":3767,"url":"https://patchwork.plctlab.org/api/1.2/patches/3767/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-14-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-14-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:10","name":"[V2,13/15] binutils/NEWS: add text for SFrame support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-14-indu.bhagat@oracle.com/mbox/"},{"id":3772,"url":"https://patchwork.plctlab.org/api/1.2/patches/3772/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-15-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-15-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:11","name":"[V2,14/15] gas/NEWS: add text about new command line option and SFrame support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-15-indu.bhagat@oracle.com/mbox/"},{"id":3773,"url":"https://patchwork.plctlab.org/api/1.2/patches/3773/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-16-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-16-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:12","name":"[V2,15/15] doc: add SFrame spec file","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-16-indu.bhagat@oracle.com/mbox/"},{"id":3999,"url":"https://patchwork.plctlab.org/api/1.2/patches/3999/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221018081205.17880-1-krebbel@linux.ibm.com/","msgid":"<20221018081205.17880-1-krebbel@linux.ibm.com>","list_archive_url":null,"date":"2022-10-18T08:12:05","name":"[1/1] IBM zSystems: Issue error for *DBL relocs on misaligned symbols","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221018081205.17880-1-krebbel@linux.ibm.com/mbox/"},{"id":4141,"url":"https://patchwork.plctlab.org/api/1.2/patches/4141/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/baffaf673f17692b7bcbd604b31800b189988596.camel@espressif.com/","msgid":"","list_archive_url":null,"date":"2022-10-18T12:12:07","name":"xtensa: use definitions from xtensa-config.h","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/baffaf673f17692b7bcbd604b31800b189988596.camel@espressif.com/mbox/"},{"id":4272,"url":"https://patchwork.plctlab.org/api/1.2/patches/4272/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221018174914.470062-1-hjl.tools@gmail.com/","msgid":"<20221018174914.470062-1-hjl.tools@gmail.com>","list_archive_url":null,"date":"2022-10-18T17:49:14","name":"x86: Disable AVX-VNNI when disabling AVX2","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221018174914.470062-1-hjl.tools@gmail.com/mbox/"},{"id":4998,"url":"https://patchwork.plctlab.org/api/1.2/patches/4998/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c2f76e95-09f6-1d92-7ef4-38a3c2955fcd@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-19T09:52:46","name":"x86: re-work AVX-VNNI support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c2f76e95-09f6-1d92-7ef4-38a3c2955fcd@suse.com/mbox/"},{"id":5276,"url":"https://patchwork.plctlab.org/api/1.2/patches/5276/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0/lLtlKqqsmAx0s@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-19T11:53:18","name":"Fix addr2line test for ppc64 elfv1 and mingw","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0/lLtlKqqsmAx0s@squeak.grove.modra.org/mbox/"},{"id":5424,"url":"https://patchwork.plctlab.org/api/1.2/patches/5424/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/07bfebbf3843b47e13d82d4fa16eb14fec942ef7.1666184962.git.research_trasio@irq.a4lg.com/","msgid":"<07bfebbf3843b47e13d82d4fa16eb14fec942ef7.1666184962.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:09:54","name":"binutils: Remove unused substitution PROGRAM","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/07bfebbf3843b47e13d82d4fa16eb14fec942ef7.1666184962.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5433,"url":"https://patchwork.plctlab.org/api/1.2/patches/5433/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2fa7ff719223232402e82a9c91331aea22ace1bb.1666185116.git.research_trasio@irq.a4lg.com/","msgid":"<2fa7ff719223232402e82a9c91331aea22ace1bb.1666185116.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:11:55","name":"[v2,1/8] RISC-V: Add a space at the end of pinfo","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2fa7ff719223232402e82a9c91331aea22ace1bb.1666185116.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5435,"url":"https://patchwork.plctlab.org/api/1.2/patches/5435/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1b30cce5db2cce3b8edca42ab5da114d0b8c9e93.1666185116.git.research_trasio@irq.a4lg.com/","msgid":"<1b30cce5db2cce3b8edca42ab5da114d0b8c9e93.1666185116.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:11:56","name":"[v2,2/8] RISC-V: Fix obvious misalignments ('\''Zbb'\''/'\''Zba'\'')","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1b30cce5db2cce3b8edca42ab5da114d0b8c9e93.1666185116.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5437,"url":"https://patchwork.plctlab.org/api/1.2/patches/5437/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6b0857aa1a2d15ca1cf00b4dcaae0032efbb88ff.1666185116.git.research_trasio@irq.a4lg.com/","msgid":"<6b0857aa1a2d15ca1cf00b4dcaae0032efbb88ff.1666185116.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:11:57","name":"[v2,3/8] RISC-V: Remove spaces in opcode entries","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6b0857aa1a2d15ca1cf00b4dcaae0032efbb88ff.1666185116.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5436,"url":"https://patchwork.plctlab.org/api/1.2/patches/5436/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/889d956caac0f2e95543a14afaeed97188ce384c.1666185116.git.research_trasio@irq.a4lg.com/","msgid":"<889d956caac0f2e95543a14afaeed97188ce384c.1666185116.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:11:58","name":"[v2,4/8] RISC-V: Remove unused instruction macros","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/889d956caac0f2e95543a14afaeed97188ce384c.1666185116.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5440,"url":"https://patchwork.plctlab.org/api/1.2/patches/5440/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8f226ee20d8a5ef6ad7b6c4408b44794a99d542a.1666185116.git.research_trasio@irq.a4lg.com/","msgid":"<8f226ee20d8a5ef6ad7b6c4408b44794a99d542a.1666185116.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:11:59","name":"[v2,5/8] RISC-V: Complete tidying up with SCALL and SBREAK","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8f226ee20d8a5ef6ad7b6c4408b44794a99d542a.1666185116.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5442,"url":"https://patchwork.plctlab.org/api/1.2/patches/5442/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4070184c454a05a39adf0790951e5856e6b2ecb6.1666185116.git.research_trasio@irq.a4lg.com/","msgid":"<4070184c454a05a39adf0790951e5856e6b2ecb6.1666185116.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:12:00","name":"[v2,6/8] RISC-V: Tidying up with fmv.w.x and fmv.x.w","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4070184c454a05a39adf0790951e5856e6b2ecb6.1666185116.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5438,"url":"https://patchwork.plctlab.org/api/1.2/patches/5438/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c1ccda3e7c8fb297eda46dab3936d5c5977178fc.1666185116.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-19T13:12:01","name":"[v2,7/8] RISC-V: Make alias instructions aliases","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c1ccda3e7c8fb297eda46dab3936d5c5977178fc.1666185116.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5441,"url":"https://patchwork.plctlab.org/api/1.2/patches/5441/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/413cfca82c7e8d8a2e977dfda9135903c9cb7c57.1666185116.git.research_trasio@irq.a4lg.com/","msgid":"<413cfca82c7e8d8a2e977dfda9135903c9cb7c57.1666185116.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:12:02","name":"[v2,8/8] RISC-V: Use defined mask and match values","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/413cfca82c7e8d8a2e977dfda9135903c9cb7c57.1666185116.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5439,"url":"https://patchwork.plctlab.org/api/1.2/patches/5439/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/345c5c3b3a53eab04a1e6e91197de2642095c94f.1666185237.git.research_trasio@irq.a4lg.com/","msgid":"<345c5c3b3a53eab04a1e6e91197de2642095c94f.1666185237.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:14:01","name":"RISC-V: Remove RV32EF conflict","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/345c5c3b3a53eab04a1e6e91197de2642095c94f.1666185237.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5616,"url":"https://patchwork.plctlab.org/api/1.2/patches/5616/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019145608.45213-5-haochen.jiang@intel.com/","msgid":"<20221019145608.45213-5-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T14:56:02","name":"[04/10] Support Intel CMPccXADD","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019145608.45213-5-haochen.jiang@intel.com/mbox/"},{"id":5614,"url":"https://patchwork.plctlab.org/api/1.2/patches/5614/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019145608.45213-6-haochen.jiang@intel.com/","msgid":"<20221019145608.45213-6-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T14:56:03","name":"[05/10] Add handler for more i386_cpu_flags","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019145608.45213-6-haochen.jiang@intel.com/mbox/"},{"id":5672,"url":"https://patchwork.plctlab.org/api/1.2/patches/5672/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-2-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-2-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:25","name":"[01/10] Support Intel AVX-IFMA","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-2-haochen.jiang@intel.com/mbox/"},{"id":5691,"url":"https://patchwork.plctlab.org/api/1.2/patches/5691/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-3-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-3-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:26","name":"[02/10] Support Intel AVX-VNNI-INT8","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-3-haochen.jiang@intel.com/mbox/"},{"id":5690,"url":"https://patchwork.plctlab.org/api/1.2/patches/5690/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-4-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-4-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:27","name":"[03/10] Support Intel AVX-NE-CONVERT","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-4-haochen.jiang@intel.com/mbox/"},{"id":5689,"url":"https://patchwork.plctlab.org/api/1.2/patches/5689/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-5-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-5-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:28","name":"[04/10] Support Intel CMPccXADD","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-5-haochen.jiang@intel.com/mbox/"},{"id":5676,"url":"https://patchwork.plctlab.org/api/1.2/patches/5676/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-6-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-6-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:29","name":"[05/10] Add handler for more i386_cpu_flags","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-6-haochen.jiang@intel.com/mbox/"},{"id":5677,"url":"https://patchwork.plctlab.org/api/1.2/patches/5677/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-7-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-7-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:30","name":"[06/10] Support Intel RAO-INT","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-7-haochen.jiang@intel.com/mbox/"},{"id":5681,"url":"https://patchwork.plctlab.org/api/1.2/patches/5681/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-8-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-8-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:31","name":"[07/10] Support Intel WRMSRNS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-8-haochen.jiang@intel.com/mbox/"},{"id":5682,"url":"https://patchwork.plctlab.org/api/1.2/patches/5682/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-9-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-9-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:32","name":"[08/10] Support Intel MSRLIST","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-9-haochen.jiang@intel.com/mbox/"},{"id":5673,"url":"https://patchwork.plctlab.org/api/1.2/patches/5673/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-10-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-10-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:33","name":"[09/10] Support Intel AMX-FP16","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-10-haochen.jiang@intel.com/mbox/"},{"id":5686,"url":"https://patchwork.plctlab.org/api/1.2/patches/5686/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-11-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-11-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:34","name":"[10/10] Support Intel PREFETCHI","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-11-haochen.jiang@intel.com/mbox/"},{"id":5940,"url":"https://patchwork.plctlab.org/api/1.2/patches/5940/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1CMrFUC8d9lC/NL@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-19T23:47:56","name":"Obsolete beos","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1CMrFUC8d9lC/NL@squeak.grove.modra.org/mbox/"},{"id":6080,"url":"https://patchwork.plctlab.org/api/1.2/patches/6080/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8b99d666e78ba5b9d32c7889a2161c70b3da88df.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<8b99d666e78ba5b9d32c7889a2161c70b3da88df.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:25:47","name":"[01/40] gdb/unittests: PR28413, suppress warnings generated by Gnulib","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8b99d666e78ba5b9d32c7889a2161c70b3da88df.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6081,"url":"https://patchwork.plctlab.org/api/1.2/patches/6081/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b05adb17e401d621dbdad791281bc7af7806906e.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-20T09:25:48","name":"[02/40] sim: Check known getrusage declaration existence","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b05adb17e401d621dbdad791281bc7af7806906e.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6083,"url":"https://patchwork.plctlab.org/api/1.2/patches/6083/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/796962a87e569feeafb5ef636de3c79000ae152c.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<796962a87e569feeafb5ef636de3c79000ae152c.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:25:49","name":"[03/40] sim/aarch64: Remove unused functions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/796962a87e569feeafb5ef636de3c79000ae152c.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6084,"url":"https://patchwork.plctlab.org/api/1.2/patches/6084/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/65223c79fdfd7faf132275415cd9da9852c5bec3.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<65223c79fdfd7faf132275415cd9da9852c5bec3.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:25:50","name":"[04/40] cpu/cris: Initialize some variables on CRIS CPU","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/65223c79fdfd7faf132275415cd9da9852c5bec3.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6082,"url":"https://patchwork.plctlab.org/api/1.2/patches/6082/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/24baefe92148f4b7968115ba13de9b0c863a65f6.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<24baefe92148f4b7968115ba13de9b0c863a65f6.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:25:51","name":"[05/40] cpu/cris: Add u-stall virtual unit to CRIS v32","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/24baefe92148f4b7968115ba13de9b0c863a65f6.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6087,"url":"https://patchwork.plctlab.org/api/1.2/patches/6087/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3904a5c3e80f8548150d8088a92059dd728c7ff8.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<3904a5c3e80f8548150d8088a92059dd728c7ff8.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:25:52","name":"[06/40] sim/cris: Move declarations of f_specific_init","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3904a5c3e80f8548150d8088a92059dd728c7ff8.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6091,"url":"https://patchwork.plctlab.org/api/1.2/patches/6091/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/69ef2d7dd519ed572511890a215a0f6d74e53384.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<69ef2d7dd519ed572511890a215a0f6d74e53384.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:25:53","name":"[07/40] sim/cris: Regenerate with CGEN","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/69ef2d7dd519ed572511890a215a0f6d74e53384.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6085,"url":"https://patchwork.plctlab.org/api/1.2/patches/6085/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/26a3eaf4f5d2e0db6977738ddfd65d82b36e38b2.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<26a3eaf4f5d2e0db6977738ddfd65d82b36e38b2.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:25:54","name":"[08/40] sim/erc32: Insert void parameter","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/26a3eaf4f5d2e0db6977738ddfd65d82b36e38b2.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6086,"url":"https://patchwork.plctlab.org/api/1.2/patches/6086/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/057c2f8392410494c3bc5dc98052246508e6a73e.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<057c2f8392410494c3bc5dc98052246508e6a73e.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:25:55","name":"[09/40] sim/erc32: Use int32_t as event callback argument","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/057c2f8392410494c3bc5dc98052246508e6a73e.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6090,"url":"https://patchwork.plctlab.org/api/1.2/patches/6090/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8c05aec20557191434485be347d37177a2ec5ff2.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<8c05aec20557191434485be347d37177a2ec5ff2.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:25:56","name":"[10/40] sim/erc32: Use int32_t as IRQ callback argument","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8c05aec20557191434485be347d37177a2ec5ff2.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6089,"url":"https://patchwork.plctlab.org/api/1.2/patches/6089/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/afd7757aae21743c29f2aa4135a23b31d4959e9b.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-20T09:25:57","name":"[11/40] cpu/frv: Initialize some variables","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/afd7757aae21743c29f2aa4135a23b31d4959e9b.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6088,"url":"https://patchwork.plctlab.org/api/1.2/patches/6088/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/021dbd238af5dfe74523ed229d2156a155a6bb9e.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<021dbd238af5dfe74523ed229d2156a155a6bb9e.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:25:58","name":"[12/40] sim/frv: Initialize nesr variable","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/021dbd238af5dfe74523ed229d2156a155a6bb9e.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6093,"url":"https://patchwork.plctlab.org/api/1.2/patches/6093/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/51a03f7097921cc48954210cf99e370ae8982ec8.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<51a03f7097921cc48954210cf99e370ae8982ec8.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:25:59","name":"[13/40] sim/frv: Initialize some variables","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/51a03f7097921cc48954210cf99e370ae8982ec8.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6092,"url":"https://patchwork.plctlab.org/api/1.2/patches/6092/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e1baa1be3601612266dc6ae0bdde8426ff2a42c8.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-20T09:26:00","name":"[14/40] sim/frv: Add explicit casts","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e1baa1be3601612266dc6ae0bdde8426ff2a42c8.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6095,"url":"https://patchwork.plctlab.org/api/1.2/patches/6095/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5ab303a5bdfc1da7832f8fa22f57678c9ef1a5fa.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<5ab303a5bdfc1da7832f8fa22f57678c9ef1a5fa.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:26:01","name":"[15/40] sim/h8300: Add \"+ 0x0\" to avoid self-assignments","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5ab303a5bdfc1da7832f8fa22f57678c9ef1a5fa.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6101,"url":"https://patchwork.plctlab.org/api/1.2/patches/6101/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ddff80db3328a2286fe6fbc1240d2abc1e3813eb.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-20T09:26:02","name":"[16/40] sim/lm32: fix some missing function declaration warnings","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ddff80db3328a2286fe6fbc1240d2abc1e3813eb.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6094,"url":"https://patchwork.plctlab.org/api/1.2/patches/6094/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e094b1379231d9ffb59a78cfebbcc84634c779c6.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-20T09:26:03","name":"[17/40] sim/lm32: Add explicit casts","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e094b1379231d9ffb59a78cfebbcc84634c779c6.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6141,"url":"https://patchwork.plctlab.org/api/1.2/patches/6141/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/cabebead-489b-528c-580e-933832417474@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-20T10:25:51","name":"[1/3] x86: emit {evex} prefix when disassembling ambiguous AVX512VL insns","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/cabebead-489b-528c-580e-933832417474@suse.com/mbox/"},{"id":6143,"url":"https://patchwork.plctlab.org/api/1.2/patches/6143/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a032d61c-63a0-23d1-331f-619a2b8bbde3@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-20T10:26:15","name":"[2/3] x86: consolidate VAES tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a032d61c-63a0-23d1-331f-619a2b8bbde3@suse.com/mbox/"},{"id":6142,"url":"https://patchwork.plctlab.org/api/1.2/patches/6142/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7ff09c86-2de7-dc34-3183-5187de3df5ac@suse.com/","msgid":"<7ff09c86-2de7-dc34-3183-5187de3df5ac@suse.com>","list_archive_url":null,"date":"2022-10-20T10:26:40","name":"[3/3] x86: consolidate VPCLMUL tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7ff09c86-2de7-dc34-3183-5187de3df5ac@suse.com/mbox/"},{"id":6228,"url":"https://patchwork.plctlab.org/api/1.2/patches/6228/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.LSU.2.20.2210201432170.29399@wotan.suse.de/","msgid":"","list_archive_url":null,"date":"2022-10-20T14:42:25","name":"x86-64: Use only one default max-page-size","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.LSU.2.20.2210201432170.29399@wotan.suse.de/mbox/"},{"id":6229,"url":"https://patchwork.plctlab.org/api/1.2/patches/6229/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221020144351.1398099-1-chigot@adacore.com/","msgid":"<20221020144351.1398099-1-chigot@adacore.com>","list_archive_url":null,"date":"2022-10-20T14:43:50","name":"[1/2] ld/testsuite: skip ld-elf/exclude when -shared is not supported","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221020144351.1398099-1-chigot@adacore.com/mbox/"},{"id":6230,"url":"https://patchwork.plctlab.org/api/1.2/patches/6230/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221020144351.1398099-2-chigot@adacore.com/","msgid":"<20221020144351.1398099-2-chigot@adacore.com>","list_archive_url":null,"date":"2022-10-20T14:43:51","name":"[2/2] ld/testsuite: adjust ld-arm to run shared tests only when supported","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221020144351.1398099-2-chigot@adacore.com/mbox/"},{"id":6236,"url":"https://patchwork.plctlab.org/api/1.2/patches/6236/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221020151027.GA1300@delia.home/","msgid":"<20221020151027.GA1300@delia.home>","list_archive_url":null,"date":"2022-10-20T15:10:28","name":"[RFC,top-level] Add configure test-case","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221020151027.GA1300@delia.home/mbox/"},{"id":6286,"url":"https://patchwork.plctlab.org/api/1.2/patches/6286/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221020162911.1113338-1-hjl.tools@gmail.com/","msgid":"<20221020162911.1113338-1-hjl.tools@gmail.com>","list_archive_url":null,"date":"2022-10-20T16:29:11","name":"x86: Check VEX/EVEX encoding before checking vector operands","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221020162911.1113338-1-hjl.tools@gmail.com/mbox/"},{"id":7884,"url":"https://patchwork.plctlab.org/api/1.2/patches/7884/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7e53b7980f2b3b74d2250bc87f5db94b1d888a2d.camel@espressif.com/","msgid":"<7e53b7980f2b3b74d2250bc87f5db94b1d888a2d.camel@espressif.com>","list_archive_url":null,"date":"2022-10-22T12:53:54","name":"[1/5] bfd: xtensa: move common code from ld and gas","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7e53b7980f2b3b74d2250bc87f5db94b1d888a2d.camel@espressif.com/mbox/"},{"id":7885,"url":"https://patchwork.plctlab.org/api/1.2/patches/7885/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/63f2699e6ef3e6d1ca415a6ed1187d4f64297521.camel@espressif.com/","msgid":"<63f2699e6ef3e6d1ca415a6ed1187d4f64297521.camel@espressif.com>","list_archive_url":null,"date":"2022-10-22T12:55:16","name":"[2/5] gas: xtensa: add endianness, loops, booleans options","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/63f2699e6ef3e6d1ca415a6ed1187d4f64297521.camel@espressif.com/mbox/"},{"id":7886,"url":"https://patchwork.plctlab.org/api/1.2/patches/7886/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/34d2f747237aeeda595560cfded8096d9bd1c28c.camel@espressif.com/","msgid":"<34d2f747237aeeda595560cfded8096d9bd1c28c.camel@espressif.com>","list_archive_url":null,"date":"2022-10-22T12:56:02","name":"[3/5] ld: xtensa: use default LD command line options for endianness","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/34d2f747237aeeda595560cfded8096d9bd1c28c.camel@espressif.com/mbox/"},{"id":7891,"url":"https://patchwork.plctlab.org/api/1.2/patches/7891/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/535b6208c1718b9acf3258575e1ebc0a65af9f07.camel@espressif.com/","msgid":"<535b6208c1718b9acf3258575e1ebc0a65af9f07.camel@espressif.com>","list_archive_url":null,"date":"2022-10-22T13:56:44","name":"[5/5] gdb: xtensa: add support for esp32, esp32s2, esp32s3 isa-modules","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/535b6208c1718b9acf3258575e1ebc0a65af9f07.camel@espressif.com/mbox/"},{"id":10456,"url":"https://patchwork.plctlab.org/api/1.2/patches/10456/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221025013347.68282-1-nelson@rivosinc.com/","msgid":"<20221025013347.68282-1-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-10-25T01:33:46","name":"[committed,1/2] RISC-V: Improve link time complexity.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221025013347.68282-1-nelson@rivosinc.com/mbox/"},{"id":10454,"url":"https://patchwork.plctlab.org/api/1.2/patches/10454/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221025013347.68282-2-nelson@rivosinc.com/","msgid":"<20221025013347.68282-2-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-10-25T01:33:47","name":"[committed,2/2] RISC-V: Should reset `again'\'' flag for _bfd_riscv_relax_pc.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221025013347.68282-2-nelson@rivosinc.com/mbox/"},{"id":10536,"url":"https://patchwork.plctlab.org/api/1.2/patches/10536/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/bb7b87e4-1893-5c86-4a14-92bafc818b03@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-25T07:24:56","name":"[v5,1/8] x86: constify parse_insn()'\''s input","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/bb7b87e4-1893-5c86-4a14-92bafc818b03@suse.com/mbox/"},{"id":10537,"url":"https://patchwork.plctlab.org/api/1.2/patches/10537/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b9273ae6-0218-54f8-5374-b265ed13b71a@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-25T07:25:26","name":"[v5,1/8] x86: introduce Pass2 insn attribute","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b9273ae6-0218-54f8-5374-b265ed13b71a@suse.com/mbox/"},{"id":10541,"url":"https://patchwork.plctlab.org/api/1.2/patches/10541/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7250dab9-e218-e6dd-4c74-23da9f611ab4@suse.com/","msgid":"<7250dab9-e218-e6dd-4c74-23da9f611ab4@suse.com>","list_archive_url":null,"date":"2022-10-25T07:26:11","name":"[v5,3/8] x86: re-work insn/suffix recognition","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7250dab9-e218-e6dd-4c74-23da9f611ab4@suse.com/mbox/"},{"id":10540,"url":"https://patchwork.plctlab.org/api/1.2/patches/10540/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/13fc630f-e116-0099-5c9e-2697df6519d7@suse.com/","msgid":"<13fc630f-e116-0099-5c9e-2697df6519d7@suse.com>","list_archive_url":null,"date":"2022-10-25T07:26:40","name":"[v5,4/8] ix86: don'\''t recognize/derive Q suffix in the common case","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/13fc630f-e116-0099-5c9e-2697df6519d7@suse.com/mbox/"},{"id":10543,"url":"https://patchwork.plctlab.org/api/1.2/patches/10543/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/74db429d-d203-eab8-4ae1-18b9ad416b02@suse.com/","msgid":"<74db429d-d203-eab8-4ae1-18b9ad416b02@suse.com>","list_archive_url":null,"date":"2022-10-25T07:27:11","name":"[v5,5/8] x86-64: allow HLE store of accumulator to absolute 32-bit address","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/74db429d-d203-eab8-4ae1-18b9ad416b02@suse.com/mbox/"},{"id":10542,"url":"https://patchwork.plctlab.org/api/1.2/patches/10542/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2e2f7841-de4e-b5de-e8d9-a47a6a4113c8@suse.com/","msgid":"<2e2f7841-de4e-b5de-e8d9-a47a6a4113c8@suse.com>","list_archive_url":null,"date":"2022-10-25T07:27:35","name":"[v5,6/8] x86: move bad-use-of-TLS-reloc check","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2e2f7841-de4e-b5de-e8d9-a47a6a4113c8@suse.com/mbox/"},{"id":10545,"url":"https://patchwork.plctlab.org/api/1.2/patches/10545/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/421bc96e-7591-6980-48e9-5af8c8b0775a@suse.com/","msgid":"<421bc96e-7591-6980-48e9-5af8c8b0775a@suse.com>","list_archive_url":null,"date":"2022-10-25T07:28:27","name":"[v5,7/8] x86: drop (now) stray IsString","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/421bc96e-7591-6980-48e9-5af8c8b0775a@suse.com/mbox/"},{"id":10546,"url":"https://patchwork.plctlab.org/api/1.2/patches/10546/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/06ff83d4-4633-a07b-70e5-a8e049981dd4@suse.com/","msgid":"<06ff83d4-4633-a07b-70e5-a8e049981dd4@suse.com>","list_archive_url":null,"date":"2022-10-25T07:29:18","name":"[v5,8/8] x86: further re-work insn/suffix recognition to also cover MOVSX","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/06ff83d4-4633-a07b-70e5-a8e049981dd4@suse.com/mbox/"},{"id":10777,"url":"https://patchwork.plctlab.org/api/1.2/patches/10777/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6a8e7a71acccd0efb9789dfb3edfa307e83bdaa1.1666702934.git.research_trasio@irq.a4lg.com/","msgid":"<6a8e7a71acccd0efb9789dfb3edfa307e83bdaa1.1666702934.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-25T13:04:02","name":"[RFC] RISC-V: Allocate \"various\" operand type","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6a8e7a71acccd0efb9789dfb3edfa307e83bdaa1.1666702934.git.research_trasio@irq.a4lg.com/mbox/"},{"id":11062,"url":"https://patchwork.plctlab.org/api/1.2/patches/11062/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jAhwbXhxJHL66v@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-26T05:07:19","name":"PR29720, objdump -S crashes if build-id is missing","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jAhwbXhxJHL66v@squeak.grove.modra.org/mbox/"},{"id":11063,"url":"https://patchwork.plctlab.org/api/1.2/patches/11063/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jAxD+NxpMIah6s@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-26T05:08:20","name":"som.c buffer overflow","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jAxD+NxpMIah6s@squeak.grove.modra.org/mbox/"},{"id":11064,"url":"https://patchwork.plctlab.org/api/1.2/patches/11064/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jBYw4lfRQfOZhi@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-26T05:10:59","name":"som.c reloc sanity checking","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jBYw4lfRQfOZhi@squeak.grove.modra.org/mbox/"},{"id":11080,"url":"https://patchwork.plctlab.org/api/1.2/patches/11080/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jY7hygm01PelCY@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-26T06:51:26","name":"segfault in objdump.c reloc_at","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jY7hygm01PelCY@squeak.grove.modra.org/mbox/"},{"id":11081,"url":"https://patchwork.plctlab.org/api/1.2/patches/11081/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jZWIeIvCCYm9/g@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-26T06:53:12","name":"Correct ELF reloc size sanity check","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jZWIeIvCCYm9/g@squeak.grove.modra.org/mbox/"},{"id":11082,"url":"https://patchwork.plctlab.org/api/1.2/patches/11082/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221026070009.3663574-1-ysato@users.sourceforge.jp/","msgid":"<20221026070009.3663574-1-ysato@users.sourceforge.jp>","list_archive_url":null,"date":"2022-10-26T07:00:09","name":"opcodes: RX fix invalid output.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221026070009.3663574-1-ysato@users.sourceforge.jp/mbox/"},{"id":11089,"url":"https://patchwork.plctlab.org/api/1.2/patches/11089/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jhW48kuVC8Ig2d@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-26T07:27:23","name":"buffer overflow in _bfd_XX_print_ce_compressed_pdata","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jhW48kuVC8Ig2d@squeak.grove.modra.org/mbox/"},{"id":11157,"url":"https://patchwork.plctlab.org/api/1.2/patches/11157/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c52dbd16-7e1b-c356-7a92-1ff089564ef7@suse.cz/","msgid":"","list_archive_url":null,"date":"2022-10-26T08:47:09","name":"tests: use canonical option name","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c52dbd16-7e1b-c356-7a92-1ff089564ef7@suse.cz/mbox/"},{"id":11526,"url":"https://patchwork.plctlab.org/api/1.2/patches/11526/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027031915.4013-1-lifang_xia@linux.alibaba.com/","msgid":"<20221027031915.4013-1-lifang_xia@linux.alibaba.com>","list_archive_url":null,"date":"2022-10-27T03:19:15","name":"[v2] RISC-V: Optimize relax of GP/call with max_alignment.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027031915.4013-1-lifang_xia@linux.alibaba.com/mbox/"},{"id":11619,"url":"https://patchwork.plctlab.org/api/1.2/patches/11619/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9df9d9e5bb4c7594b76c40613a349b4d2364e9c5.1666854355.git.research_trasio@irq.a4lg.com/","msgid":"<9df9d9e5bb4c7594b76c40613a349b4d2364e9c5.1666854355.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-27T07:06:01","name":"include: Define macro to ignore -Wdeprecated-declarations on GCC","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9df9d9e5bb4c7594b76c40613a349b4d2364e9c5.1666854355.git.research_trasio@irq.a4lg.com/mbox/"},{"id":11627,"url":"https://patchwork.plctlab.org/api/1.2/patches/11627/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1o06O9Pp8ncCsOw@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-27T07:36:08","name":"Fuzzed files in archives","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1o06O9Pp8ncCsOw@squeak.grove.modra.org/mbox/"},{"id":11658,"url":"https://patchwork.plctlab.org/api/1.2/patches/11658/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027084808.37252-1-nelson@rivosinc.com/","msgid":"<20221027084808.37252-1-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-10-27T08:48:08","name":"[committed] RISC-V: Fix build failures for -Werror=sign-compare.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027084808.37252-1-nelson@rivosinc.com/mbox/"},{"id":11921,"url":"https://patchwork.plctlab.org/api/1.2/patches/11921/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027190052.10536-1-mark@harmstone.com/","msgid":"<20221027190052.10536-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-27T19:00:51","name":"[1/2] ld: Add section header stream to PDB files","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027190052.10536-1-mark@harmstone.com/mbox/"},{"id":11922,"url":"https://patchwork.plctlab.org/api/1.2/patches/11922/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027190052.10536-2-mark@harmstone.com/","msgid":"<20221027190052.10536-2-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-27T19:00:52","name":"[2/2] ld: Add publics stream to PDB files","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027190052.10536-2-mark@harmstone.com/mbox/"},{"id":11965,"url":"https://patchwork.plctlab.org/api/1.2/patches/11965/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027202719.32497-1-palmer@rivosinc.com/","msgid":"<20221027202719.32497-1-palmer@rivosinc.com>","list_archive_url":null,"date":"2022-10-27T20:27:18","name":"[1/2] gas: NEWS: Add a missing newline","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027202719.32497-1-palmer@rivosinc.com/mbox/"},{"id":11966,"url":"https://patchwork.plctlab.org/api/1.2/patches/11966/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027202719.32497-2-palmer@rivosinc.com/","msgid":"<20221027202719.32497-2-palmer@rivosinc.com>","list_archive_url":null,"date":"2022-10-27T20:27:19","name":"[2/2] gas: NEWS: Note support for RISC-V Zawrs","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027202719.32497-2-palmer@rivosinc.com/mbox/"},{"id":12016,"url":"https://patchwork.plctlab.org/api/1.2/patches/12016/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/21ec9a18-fa89-0828-f625-499680022ec7@linux.ibm.com/","msgid":"<21ec9a18-fa89-0828-f625-499680022ec7@linux.ibm.com>","list_archive_url":null,"date":"2022-10-28T00:35:19","name":"[COMMITTED] PowerPC: Add support for RFC02653 - Dense Math Facility","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/21ec9a18-fa89-0828-f625-499680022ec7@linux.ibm.com/mbox/"},{"id":12017,"url":"https://patchwork.plctlab.org/api/1.2/patches/12017/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fd94047d-a070-45a6-3840-c105391718e0@linux.ibm.com/","msgid":"","list_archive_url":null,"date":"2022-10-28T00:37:18","name":"[COMMITTED] PowerPC: Add support for RFC02658 - MMA+ Outer-Product, Instructions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fd94047d-a070-45a6-3840-c105391718e0@linux.ibm.com/mbox/"},{"id":12122,"url":"https://patchwork.plctlab.org/api/1.2/patches/12122/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ac4f3f3c7115a824f73aca6935789b14d33c9a58.1666939920.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-28T06:53:02","name":"RISC-V: Fix build failure for -Werror=maybe-uninitialized","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ac4f3f3c7115a824f73aca6935789b14d33c9a58.1666939920.git.research_trasio@irq.a4lg.com/mbox/"},{"id":12181,"url":"https://patchwork.plctlab.org/api/1.2/patches/12181/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221028093840.19164-1-nelson@rivosinc.com/","msgid":"<20221028093840.19164-1-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-10-28T09:38:40","name":"RISC-V: Added SiFive custom cache control extensions.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221028093840.19164-1-nelson@rivosinc.com/mbox/"},{"id":12211,"url":"https://patchwork.plctlab.org/api/1.2/patches/12211/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4a280588-a85b-6ed3-634b-2b9cbc128f86@suse.com/","msgid":"<4a280588-a85b-6ed3-634b-2b9cbc128f86@suse.com>","list_archive_url":null,"date":"2022-10-28T10:06:35","name":"RISC-V/gas: fix build with certain gcc versions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4a280588-a85b-6ed3-634b-2b9cbc128f86@suse.com/mbox/"},{"id":12249,"url":"https://patchwork.plctlab.org/api/1.2/patches/12249/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/eb0e1bff-675e-72db-b8b1-b0f0e50b7121@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-28T12:35:35","name":"x86: minor improvements to optimize_imm() (part III)","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/eb0e1bff-675e-72db-b8b1-b0f0e50b7121@suse.com/mbox/"},{"id":12382,"url":"https://patchwork.plctlab.org/api/1.2/patches/12382/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/17f57574936af82be381a1451eac56b3709b60bb.1666968673.git.research_trasio@irq.a4lg.com/","msgid":"<17f57574936af82be381a1451eac56b3709b60bb.1666968673.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-28T14:52:12","name":"RISC-V: Emit mapping symbol with ISA string if non-default arch is used","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/17f57574936af82be381a1451eac56b3709b60bb.1666968673.git.research_trasio@irq.a4lg.com/mbox/"},{"id":12627,"url":"https://patchwork.plctlab.org/api/1.2/patches/12627/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221029034432.49859-1-nelson@rivosinc.com/","msgid":"<20221029034432.49859-1-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-10-29T03:44:32","name":"[committed] RISC-V: Always generate mapping symbols at the start of the sections.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221029034432.49859-1-nelson@rivosinc.com/mbox/"},{"id":12629,"url":"https://patchwork.plctlab.org/api/1.2/patches/12629/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1yxgzNJg5M48uPI@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-29T04:52:19","name":"NULL dereference read in som_write_object_contents","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1yxgzNJg5M48uPI@squeak.grove.modra.org/mbox/"},{"id":12630,"url":"https://patchwork.plctlab.org/api/1.2/patches/12630/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1yxnSHLY+FeB5DQ@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-29T04:52:45","name":"Fix small objcopy memory leak","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1yxnSHLY+FeB5DQ@squeak.grove.modra.org/mbox/"},{"id":12631,"url":"https://patchwork.plctlab.org/api/1.2/patches/12631/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1yxxfpJz+Jx4KTh@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-29T04:53:25","name":"pef: sanity check before malloc","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1yxxfpJz+Jx4KTh@squeak.grove.modra.org/mbox/"},{"id":12950,"url":"https://patchwork.plctlab.org/api/1.2/patches/12950/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-2-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-2-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:36","name":"[V3,01/15] sframe.h: Add SFrame format definition","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-2-indu.bhagat@oracle.com/mbox/"},{"id":12952,"url":"https://patchwork.plctlab.org/api/1.2/patches/12952/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-3-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-3-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:37","name":"[V3,02/15] gas: add new command line option --gsframe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-3-indu.bhagat@oracle.com/mbox/"},{"id":12951,"url":"https://patchwork.plctlab.org/api/1.2/patches/12951/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-4-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-4-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:38","name":"[V3,03/15] gas: generate .sframe from CFI directives","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-4-indu.bhagat@oracle.com/mbox/"},{"id":12956,"url":"https://patchwork.plctlab.org/api/1.2/patches/12956/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-5-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-5-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:39","name":"[V3,04/15] gas: testsuite: add new tests for SFrame unwind info","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-5-indu.bhagat@oracle.com/mbox/"},{"id":12955,"url":"https://patchwork.plctlab.org/api/1.2/patches/12955/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-6-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-6-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:40","name":"[V3,05/15] libsframe: add the SFrame library","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-6-indu.bhagat@oracle.com/mbox/"},{"id":12959,"url":"https://patchwork.plctlab.org/api/1.2/patches/12959/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-7-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-7-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:41","name":"[V3,06/15] bfd: linker: merge .sframe sections","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-7-indu.bhagat@oracle.com/mbox/"},{"id":12957,"url":"https://patchwork.plctlab.org/api/1.2/patches/12957/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-12-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-12-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:46","name":"[V3,11/15] libctf: add libsframe to LDFLAGS and LIBS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-12-indu.bhagat@oracle.com/mbox/"},{"id":12960,"url":"https://patchwork.plctlab.org/api/1.2/patches/12960/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-13-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-13-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:47","name":"[V3,12/15] src-release.sh: Add libsframe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-13-indu.bhagat@oracle.com/mbox/"},{"id":12953,"url":"https://patchwork.plctlab.org/api/1.2/patches/12953/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-14-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-14-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:48","name":"[V3,13/15] binutils/NEWS: add text for SFrame support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-14-indu.bhagat@oracle.com/mbox/"},{"id":12954,"url":"https://patchwork.plctlab.org/api/1.2/patches/12954/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-15-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-15-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:49","name":"[V3,14/15] gas/NEWS: add text about new command line option and SFrame support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-15-indu.bhagat@oracle.com/mbox/"},{"id":12958,"url":"https://patchwork.plctlab.org/api/1.2/patches/12958/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-16-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-16-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:50","name":"[V3,15/15] doc: add SFrame spec file","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-16-indu.bhagat@oracle.com/mbox/"}],"public":true,"mbox":"https://patchwork.plctlab.org/bundle/patchwork-bot/binutils-gdb_2022-10/mbox/"},{"id":7,"url":"https://patchwork.plctlab.org/api/1.2/bundles/7/","web_url":"https://patchwork.plctlab.org/bundle/patchwork-bot/binutils-gdb_2022-09/","project":{"id":2,"url":"https://patchwork.plctlab.org/api/1.2/projects/2/","name":"binutils-gdb","link_name":"binutils-gdb","list_id":"binutils.sourceware.org","list_email":"binutils@sourceware.org","web_url":"https://github.com/wangliu-iscas/Patchwork-Bundles/blob/main/binutils-gdb.md","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"name":"binutils-gdb_2022-09","owner":{"id":3,"url":"https://patchwork.plctlab.org/api/1.2/users/3/","username":"patchwork-bot","first_name":"","last_name":"","email":"ouuuleilei@gmail.com"},"patches":[{"id":1573,"url":"https://patchwork.plctlab.org/api/1.2/patches/1573/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930073211.2634-1-jiawei@iscas.ac.cn/","msgid":"<20220930073211.2634-1-jiawei@iscas.ac.cn>","list_archive_url":null,"date":"2022-09-30T07:32:11","name":"[V2] RISC-V: Add Smepmp CSR '\''mseccfg'\'' define and testcases.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930073211.2634-1-jiawei@iscas.ac.cn/mbox/"},{"id":1577,"url":"https://patchwork.plctlab.org/api/1.2/patches/1577/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/76fa0c3c-2303-ebdf-a765-ac4731581517@suse.com/","msgid":"<76fa0c3c-2303-ebdf-a765-ac4731581517@suse.com>","list_archive_url":null,"date":"2022-09-30T08:54:18","name":"objcopy: avoid \"shadowing\" of remove() function name","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/76fa0c3c-2303-ebdf-a765-ac4731581517@suse.com/mbox/"},{"id":1579,"url":"https://patchwork.plctlab.org/api/1.2/patches/1579/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930085852.71213-1-nelson@rivosinc.com/","msgid":"<20220930085852.71213-1-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-09-30T08:58:51","name":"[1/2] RISC-V: Output mapping symbols with ISA string.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930085852.71213-1-nelson@rivosinc.com/mbox/"},{"id":1578,"url":"https://patchwork.plctlab.org/api/1.2/patches/1578/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930085852.71213-2-nelson@rivosinc.com/","msgid":"<20220930085852.71213-2-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-09-30T08:58:52","name":"[2/2] RISC-V: Refer mapping symbol to R_RISCV_RELAX for rvc relaxations.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930085852.71213-2-nelson@rivosinc.com/mbox/"},{"id":1581,"url":"https://patchwork.plctlab.org/api/1.2/patches/1581/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930092058.71286-1-nelson@rivosinc.com/","msgid":"<20220930092058.71286-1-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-09-30T09:20:57","name":"[1/2] RISC-V: Output mapping symbols with ISA string.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930092058.71286-1-nelson@rivosinc.com/mbox/"},{"id":1580,"url":"https://patchwork.plctlab.org/api/1.2/patches/1580/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930092058.71286-2-nelson@rivosinc.com/","msgid":"<20220930092058.71286-2-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-09-30T09:20:58","name":"[2/2] RISC-V: Refer mapping symbol to R_RISCV_RELAX for rvc relaxations.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930092058.71286-2-nelson@rivosinc.com/mbox/"},{"id":1582,"url":"https://patchwork.plctlab.org/api/1.2/patches/1582/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5874dd79-0cf5-d65c-7ea2-13adfc799c0f@suse.com/","msgid":"<5874dd79-0cf5-d65c-7ea2-13adfc799c0f@suse.com>","list_archive_url":null,"date":"2022-09-30T09:41:29","name":"RISC-V: fix build after \"Add support for arbitrary immediate encoding formats\"","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5874dd79-0cf5-d65c-7ea2-13adfc799c0f@suse.com/mbox/"},{"id":1583,"url":"https://patchwork.plctlab.org/api/1.2/patches/1583/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/57d8ac2a-5757-3776-9924-99c17ca69938@suse.com/","msgid":"<57d8ac2a-5757-3776-9924-99c17ca69938@suse.com>","list_archive_url":null,"date":"2022-09-30T09:42:08","name":"RISC-V: fallout from \"re-arrange opcode table for consistent alias handling\"","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/57d8ac2a-5757-3776-9924-99c17ca69938@suse.com/mbox/"},{"id":1584,"url":"https://patchwork.plctlab.org/api/1.2/patches/1584/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e76ef8f7-72b9-5103-cb43-9608af01d017@suse.com/","msgid":"","list_archive_url":null,"date":"2022-09-30T09:42:50","name":"RISC-V: don'\''t cast expressions'\'' X_add_number to long in diagnostics","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e76ef8f7-72b9-5103-cb43-9608af01d017@suse.com/mbox/"},{"id":1585,"url":"https://patchwork.plctlab.org/api/1.2/patches/1585/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/61355429-24b3-17d0-ab03-6fa57ee861d5@suse.cz/","msgid":"<61355429-24b3-17d0-ab03-6fa57ee861d5@suse.cz>","list_archive_url":null,"date":"2022-09-30T09:48:52","name":"[RFC] add --enable-zstd-compressed-debug-sections configure option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/61355429-24b3-17d0-ab03-6fa57ee861d5@suse.cz/mbox/"},{"id":1586,"url":"https://patchwork.plctlab.org/api/1.2/patches/1586/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930103919.323690-1-christoph.muellner@vrull.eu/","msgid":"<20220930103919.323690-1-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2022-09-30T10:39:19","name":"RISC-V: Eliminate long-casts of X_add_number in diagnostics","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930103919.323690-1-christoph.muellner@vrull.eu/mbox/"},{"id":1590,"url":"https://patchwork.plctlab.org/api/1.2/patches/1590/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/DM6PR12MB4219C943049C6D883DEA3E55E7569@DM6PR12MB4219.namprd12.prod.outlook.com/","msgid":"","list_archive_url":null,"date":"2022-09-30T11:41:37","name":"[V2] Ignore DWARF debug information for -gsplit-dwarf with dwarf-5.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/DM6PR12MB4219C943049C6D883DEA3E55E7569@DM6PR12MB4219.namprd12.prod.outlook.com/mbox/"},{"id":1591,"url":"https://patchwork.plctlab.org/api/1.2/patches/1591/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c10321f9-d289-ef84-d263-bc278fb3d31b@suse.com/","msgid":"","list_archive_url":null,"date":"2022-09-30T11:59:04","name":"[1/4] RISC-V/gas: drop riscv_subsets static variable","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c10321f9-d289-ef84-d263-bc278fb3d31b@suse.com/mbox/"},{"id":1593,"url":"https://patchwork.plctlab.org/api/1.2/patches/1593/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3244eea0-c18c-e49a-4588-d69423130226@suse.com/","msgid":"<3244eea0-c18c-e49a-4588-d69423130226@suse.com>","list_archive_url":null,"date":"2022-09-30T11:59:23","name":"[2/4] RISC-V/gas: drop stray call to install_insn()","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3244eea0-c18c-e49a-4588-d69423130226@suse.com/mbox/"},{"id":1592,"url":"https://patchwork.plctlab.org/api/1.2/patches/1592/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/385d01fd-7e57-1f3f-1bae-30aa0c313d63@suse.com/","msgid":"<385d01fd-7e57-1f3f-1bae-30aa0c313d63@suse.com>","list_archive_url":null,"date":"2022-09-30T11:59:45","name":"[3/4] RISC-V/gas: don'\''t open-code insn_length()","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/385d01fd-7e57-1f3f-1bae-30aa0c313d63@suse.com/mbox/"},{"id":1594,"url":"https://patchwork.plctlab.org/api/1.2/patches/1594/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f5757acf-7b90-a0e3-5eea-3b97cc226930@suse.com/","msgid":"","list_archive_url":null,"date":"2022-09-30T12:00:12","name":"[4/4] RISC-V/gas: allow generating up to 176-bit instructions with .insn","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f5757acf-7b90-a0e3-5eea-3b97cc226930@suse.com/mbox/"},{"id":1596,"url":"https://patchwork.plctlab.org/api/1.2/patches/1596/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930140503.38233-1-chigot@adacore.com/","msgid":"<20220930140503.38233-1-chigot@adacore.com>","list_archive_url":null,"date":"2022-09-30T14:05:03","name":"ld/testsuite: consistently add board_ldflags when linking with GCC","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930140503.38233-1-chigot@adacore.com/mbox/"}],"public":true,"mbox":"https://patchwork.plctlab.org/bundle/patchwork-bot/binutils-gdb_2022-09/mbox/"}]' + bundle_name_list='binutils-gdb_2022-10 binutils-gdb_2022-09' + [[ binutils-gdb_2022-10 binutils-gdb_2022-09 =~ 2022-10 ]] ++ jq -rc --arg bundle_name binutils-gdb_2022-10 '.[] | select(.name==$bundle_name) | (.id|tostring)' ++ echo '[{"id":6,"url":"https://patchwork.plctlab.org/api/1.2/bundles/6/","web_url":"https://patchwork.plctlab.org/bundle/patchwork-bot/binutils-gdb_2022-10/","project":{"id":2,"url":"https://patchwork.plctlab.org/api/1.2/projects/2/","name":"binutils-gdb","link_name":"binutils-gdb","list_id":"binutils.sourceware.org","list_email":"binutils@sourceware.org","web_url":"https://github.com/wangliu-iscas/Patchwork-Bundles/blob/main/binutils-gdb.md","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"name":"binutils-gdb_2022-10","owner":{"id":3,"url":"https://patchwork.plctlab.org/api/1.2/users/3/","username":"patchwork-bot","first_name":"","last_name":"","email":"ouuuleilei@gmail.com"},"patches":[{"id":1592,"url":"https://patchwork.plctlab.org/api/1.2/patches/1592/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/385d01fd-7e57-1f3f-1bae-30aa0c313d63@suse.com/","msgid":"<385d01fd-7e57-1f3f-1bae-30aa0c313d63@suse.com>","list_archive_url":null,"date":"2022-09-30T11:59:45","name":"[3/4] RISC-V/gas: don'\''t open-code insn_length()","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/385d01fd-7e57-1f3f-1bae-30aa0c313d63@suse.com/mbox/"},{"id":1594,"url":"https://patchwork.plctlab.org/api/1.2/patches/1594/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f5757acf-7b90-a0e3-5eea-3b97cc226930@suse.com/","msgid":"","list_archive_url":null,"date":"2022-09-30T12:00:12","name":"[4/4] RISC-V/gas: allow generating up to 176-bit instructions with .insn","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f5757acf-7b90-a0e3-5eea-3b97cc226930@suse.com/mbox/"},{"id":1596,"url":"https://patchwork.plctlab.org/api/1.2/patches/1596/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930140503.38233-1-chigot@adacore.com/","msgid":"<20220930140503.38233-1-chigot@adacore.com>","list_archive_url":null,"date":"2022-09-30T14:05:03","name":"ld/testsuite: consistently add board_ldflags when linking with GCC","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930140503.38233-1-chigot@adacore.com/mbox/"},{"id":1619,"url":"https://patchwork.plctlab.org/api/1.2/patches/1619/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221001014451.532772-1-maskray@google.com/","msgid":"<20221001014451.532772-1-maskray@google.com>","list_archive_url":null,"date":"2022-10-01T01:44:51","name":"gold, dwp: support zstd compressed input debug sections [PR 29641]","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221001014451.532772-1-maskray@google.com/mbox/"},{"id":1620,"url":"https://patchwork.plctlab.org/api/1.2/patches/1620/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221001023846.590825-1-maskray@google.com/","msgid":"<20221001023846.590825-1-maskray@google.com>","list_archive_url":null,"date":"2022-10-01T02:38:46","name":"gold: add --compress-debug-sections=zstd [PR 29641]","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221001023846.590825-1-maskray@google.com/mbox/"},{"id":1623,"url":"https://patchwork.plctlab.org/api/1.2/patches/1623/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b4477c7f666bdeb7f8e998633c7b0cb62310b9ef.1664599545.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-01T04:45:52","name":"[RFC,1/1] RISC-V: Implement common register pair framework","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b4477c7f666bdeb7f8e998633c7b0cb62310b9ef.1664599545.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1625,"url":"https://patchwork.plctlab.org/api/1.2/patches/1625/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/53a265a1f14d17a6f7b106082f610994c5d546e0.1664602025.git.research_trasio@irq.a4lg.com/","msgid":"<53a265a1f14d17a6f7b106082f610994c5d546e0.1664602025.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-01T05:27:31","name":"[RFC,1/1] RISC-V: Implement extension variants","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/53a265a1f14d17a6f7b106082f610994c5d546e0.1664602025.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1626,"url":"https://patchwork.plctlab.org/api/1.2/patches/1626/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8db04962aba9c780f133840a8934353a58f223fe.1664602716.git.research_trasio@irq.a4lg.com/","msgid":"<8db04962aba9c780f133840a8934353a58f223fe.1664602716.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-01T05:39:26","name":"[1/1] RISC-V: Move supervisor instructions after all unprivileged ones","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8db04962aba9c780f133840a8934353a58f223fe.1664602716.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1627,"url":"https://patchwork.plctlab.org/api/1.2/patches/1627/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221001062057.681440-1-maskray@google.com/","msgid":"<20221001062057.681440-1-maskray@google.com>","list_archive_url":null,"date":"2022-10-01T06:20:57","name":"readelf: support zstd compressed debug sections [PR 29640]","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221001062057.681440-1-maskray@google.com/mbox/"},{"id":1631,"url":"https://patchwork.plctlab.org/api/1.2/patches/1631/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/619f112539c0bdecd58e25664f1250a3479a37f5.1664707612.git.aburgess@redhat.com/","msgid":"<619f112539c0bdecd58e25664f1250a3479a37f5.1664707612.git.aburgess@redhat.com>","list_archive_url":null,"date":"2022-10-02T10:47:52","name":"[PATCHv2,2/2] opcodes/arm: add disassembler styling for arm","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/619f112539c0bdecd58e25664f1250a3479a37f5.1664707612.git.aburgess@redhat.com/mbox/"},{"id":1635,"url":"https://patchwork.plctlab.org/api/1.2/patches/1635/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221002185433.gl7dvytfh5wthifx@lug-owl.de/","msgid":"<20221002185433.gl7dvytfh5wthifx@lug-owl.de>","list_archive_url":null,"date":"2022-10-02T18:54:33","name":"diagnostics.h: GCC 13 got -Wself-move, breaks GDB build","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221002185433.gl7dvytfh5wthifx@lug-owl.de/mbox/"},{"id":1637,"url":"https://patchwork.plctlab.org/api/1.2/patches/1637/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003014313.28766-1-mark@harmstone.com/","msgid":"<20221003014313.28766-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-03T01:43:12","name":"[1/2] ld: Add --pdb option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003014313.28766-1-mark@harmstone.com/mbox/"},{"id":1638,"url":"https://patchwork.plctlab.org/api/1.2/patches/1638/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003014313.28766-2-mark@harmstone.com/","msgid":"<20221003014313.28766-2-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-03T01:43:13","name":"[2/2] ld: Add minimal pdb generation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003014313.28766-2-mark@harmstone.com/mbox/"},{"id":1640,"url":"https://patchwork.plctlab.org/api/1.2/patches/1640/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/597ed978-d121-220c-b56b-2ffb94bd091c@suse.cz/","msgid":"<597ed978-d121-220c-b56b-2ffb94bd091c@suse.cz>","list_archive_url":null,"date":"2022-10-03T07:50:38","name":"[1/2] refactor usage of compressed_debug_section_type","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/597ed978-d121-220c-b56b-2ffb94bd091c@suse.cz/mbox/"},{"id":1641,"url":"https://patchwork.plctlab.org/api/1.2/patches/1641/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b8acdd83-f33a-74b8-e21a-23719a0b1a60@suse.cz/","msgid":"","list_archive_url":null,"date":"2022-10-03T07:50:44","name":"[2/2] add --enable-default-compressed-debug-sections-algorithm configure option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b8acdd83-f33a-74b8-e21a-23719a0b1a60@suse.cz/mbox/"},{"id":1642,"url":"https://patchwork.plctlab.org/api/1.2/patches/1642/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003101328.1790113-1-aburgess@redhat.com/","msgid":"<20221003101328.1790113-1-aburgess@redhat.com>","list_archive_url":null,"date":"2022-10-03T10:13:28","name":"opcodes/riscv: style csr names as registers","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003101328.1790113-1-aburgess@redhat.com/mbox/"},{"id":1643,"url":"https://patchwork.plctlab.org/api/1.2/patches/1643/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7ba14fc4472ce97d4f7a4433cad8a571e89f82f4.1664793840.git.research_trasio@irq.a4lg.com/","msgid":"<7ba14fc4472ce97d4f7a4433cad8a571e89f82f4.1664793840.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-03T10:43:59","name":"[v3,1/6] RISC-V: Fix immediates to have \"immediate\" style","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7ba14fc4472ce97d4f7a4433cad8a571e89f82f4.1664793840.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1644,"url":"https://patchwork.plctlab.org/api/1.2/patches/1644/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a498bec37c1fd1dcda57cbf95e5f8cfba09b31d3.1664793840.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-03T10:44:00","name":"[v3,2/6] RISC-V: Fix printf argument types corresponding %x","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a498bec37c1fd1dcda57cbf95e5f8cfba09b31d3.1664793840.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1647,"url":"https://patchwork.plctlab.org/api/1.2/patches/1647/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0002ea716713ace4998a33dde0b81f4f890d10bf.1664793840.git.research_trasio@irq.a4lg.com/","msgid":"<0002ea716713ace4998a33dde0b81f4f890d10bf.1664793840.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-03T10:44:01","name":"[v3,3/6] RISC-V: Optimize riscv_disassemble_data printf","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0002ea716713ace4998a33dde0b81f4f890d10bf.1664793840.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1646,"url":"https://patchwork.plctlab.org/api/1.2/patches/1646/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c65fc3e9aa58965d6768a28c9fd7467fea9897a5.1664793840.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-03T10:44:02","name":"[v3,4/6] RISC-V: Print comma and tabs as the \"text\" style","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c65fc3e9aa58965d6768a28c9fd7467fea9897a5.1664793840.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1648,"url":"https://patchwork.plctlab.org/api/1.2/patches/1648/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5abe1d8a7694417b990e11d8f6cd6789573872e5.1664793840.git.research_trasio@irq.a4lg.com/","msgid":"<5abe1d8a7694417b990e11d8f6cd6789573872e5.1664793840.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-03T10:44:03","name":"[v3,5/6] RISC-V: Fix T-Head immediate types on printing","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5abe1d8a7694417b990e11d8f6cd6789573872e5.1664793840.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1649,"url":"https://patchwork.plctlab.org/api/1.2/patches/1649/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0b68af932117258c908db62cf87c3a15d3cdec41.1664793840.git.research_trasio@irq.a4lg.com/","msgid":"<0b68af932117258c908db62cf87c3a15d3cdec41.1664793840.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-03T10:44:04","name":"[v3,6/6] RISC-V: Print XTheadMemPair literal as \"immediate\"","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0b68af932117258c908db62cf87c3a15d3cdec41.1664793840.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1656,"url":"https://patchwork.plctlab.org/api/1.2/patches/1656/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/87lepxcd6x.fsf@redhat.com/","msgid":"<87lepxcd6x.fsf@redhat.com>","list_archive_url":null,"date":"2022-10-03T12:19:02","name":"Commit: readelf: Do not load section data from offset 0","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/87lepxcd6x.fsf@redhat.com/mbox/"},{"id":1659,"url":"https://patchwork.plctlab.org/api/1.2/patches/1659/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e0d369d419da9c0441f415da7f54352aead8f655.1664707612.git.aburgess@redhat.com/","msgid":"","list_archive_url":null,"date":"2022-10-03T16:37:36","name":"[PATCHv2,1/2] opcodes/arm: use '\''@'\'' consistently for the comment character","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e0d369d419da9c0441f415da7f54352aead8f655.1664707612.git.aburgess@redhat.com/mbox/"},{"id":1660,"url":"https://patchwork.plctlab.org/api/1.2/patches/1660/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003165848.11142-1-palmer@rivosinc.com/","msgid":"<20221003165848.11142-1-palmer@rivosinc.com>","list_archive_url":null,"date":"2022-10-03T16:58:48","name":"gas: NEWS: Mention the T-Head extensions that were recently added","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003165848.11142-1-palmer@rivosinc.com/mbox/"},{"id":1671,"url":"https://patchwork.plctlab.org/api/1.2/patches/1671/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/YzvrMEdkXjIn5Lfz@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-04T08:13:36","name":"Support objcopy changing compression to or from zstd","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/YzvrMEdkXjIn5Lfz@squeak.grove.modra.org/mbox/"},{"id":1673,"url":"https://patchwork.plctlab.org/api/1.2/patches/1673/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0bc857d306bb7c8130e5328dbe6b9ed2fed3ef87.1664873933.git.research_trasio@irq.a4lg.com/","msgid":"<0bc857d306bb7c8130e5328dbe6b9ed2fed3ef87.1664873933.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-04T08:59:07","name":"[1/2] RISC-V: Fix buffer overflow on print_insn_riscv","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0bc857d306bb7c8130e5328dbe6b9ed2fed3ef87.1664873933.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1672,"url":"https://patchwork.plctlab.org/api/1.2/patches/1672/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/89612fe01d902007bf84a7dfb0df5f85d5c166e4.1664873933.git.research_trasio@irq.a4lg.com/","msgid":"<89612fe01d902007bf84a7dfb0df5f85d5c166e4.1664873933.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-04T08:59:08","name":"[2/2] gdb/riscv: Fix buffer overflow on riscv_insn::fetch_instruction","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/89612fe01d902007bf84a7dfb0df5f85d5c166e4.1664873933.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1676,"url":"https://patchwork.plctlab.org/api/1.2/patches/1676/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fc849c94f4adcac1c4ccc5508c7a145a2f13b2a9.1664876744.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-04T09:45:49","name":"[v2,1/2] RISC-V: Fix buffer overflow on print_insn_riscv","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fc849c94f4adcac1c4ccc5508c7a145a2f13b2a9.1664876744.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1677,"url":"https://patchwork.plctlab.org/api/1.2/patches/1677/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4eb6e59ae2e790dbbf2bc92477edd281648d8814.1664876744.git.research_trasio@irq.a4lg.com/","msgid":"<4eb6e59ae2e790dbbf2bc92477edd281648d8814.1664876744.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-04T09:45:50","name":"[v2,2/2] gdb/riscv: Partial support for instructions up to 176-bits","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4eb6e59ae2e790dbbf2bc92477edd281648d8814.1664876744.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1678,"url":"https://patchwork.plctlab.org/api/1.2/patches/1678/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ebf16f9e1f45115d0793952ccb4a94d4233303f9.1664882725.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-04T11:25:56","name":"[v3,1/2] RISC-V: Fix buffer overflow on print_insn_riscv","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ebf16f9e1f45115d0793952ccb4a94d4233303f9.1664882725.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1679,"url":"https://patchwork.plctlab.org/api/1.2/patches/1679/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/83464b09b8649525259c69c853dfa2c9575a204b.1664882725.git.research_trasio@irq.a4lg.com/","msgid":"<83464b09b8649525259c69c853dfa2c9575a204b.1664882725.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-04T11:25:57","name":"[v3,2/2] gdb/riscv: Partial support for instructions up to 176-bit","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/83464b09b8649525259c69c853dfa2c9575a204b.1664882725.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1681,"url":"https://patchwork.plctlab.org/api/1.2/patches/1681/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ffa9c1d7-e8c2-a62b-ef3e-b565c0ffbe5b@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-04T13:56:27","name":"RISC-V: Zicbo{m,p,z} adjustments to riscv_multi_subset_supports_ext()","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ffa9c1d7-e8c2-a62b-ef3e-b565c0ffbe5b@suse.com/mbox/"},{"id":1690,"url":"https://patchwork.plctlab.org/api/1.2/patches/1690/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221004161720.1963953-1-vladimir.mezentsev@oracle.com/","msgid":"<20221004161720.1963953-1-vladimir.mezentsev@oracle.com>","list_archive_url":null,"date":"2022-10-04T16:17:20","name":"gprofng: fix build with --enable-pgo-build=lto","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221004161720.1963953-1-vladimir.mezentsev@oracle.com/mbox/"},{"id":1691,"url":"https://patchwork.plctlab.org/api/1.2/patches/1691/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c0211bc9c57be6c79c6d878ce147f63b657f461d.camel@espressif.com/","msgid":"","list_archive_url":null,"date":"2022-10-04T16:22:05","name":"bfd: xtensa: fix __stop_SECTION literal drop,","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c0211bc9c57be6c79c6d878ce147f63b657f461d.camel@espressif.com/mbox/"},{"id":1702,"url":"https://patchwork.plctlab.org/api/1.2/patches/1702/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5f482299-6c60-b2b3-9abe-f4a55a5a26c5@univ-grenoble-alpes.fr/","msgid":"<5f482299-6c60-b2b3-9abe-f4a55a5a26c5@univ-grenoble-alpes.fr>","list_archive_url":null,"date":"2022-10-04T20:03:20","name":"[RFC] bfd: use bfd_vma for the 64-bit version of put[lb] and get[lb]","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5f482299-6c60-b2b3-9abe-f4a55a5a26c5@univ-grenoble-alpes.fr/mbox/"},{"id":1711,"url":"https://patchwork.plctlab.org/api/1.2/patches/1711/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Yz0Gsxdxe0TePbJT@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-05T04:23:15","name":"PR29647, objdump -S looping","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Yz0Gsxdxe0TePbJT@squeak.grove.modra.org/mbox/"},{"id":1712,"url":"https://patchwork.plctlab.org/api/1.2/patches/1712/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/02d747d2-f57b-0fb5-b893-842b6cc41f2f@suse.com/","msgid":"<02d747d2-f57b-0fb5-b893-842b6cc41f2f@suse.com>","list_archive_url":null,"date":"2022-10-05T07:20:47","name":"[v3,1/7] x86: constify parse_insn()'\''s input","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/02d747d2-f57b-0fb5-b893-842b6cc41f2f@suse.com/mbox/"},{"id":1713,"url":"https://patchwork.plctlab.org/api/1.2/patches/1713/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/925cb740-4e1b-abc4-8526-aaab6faae5e1@suse.com/","msgid":"<925cb740-4e1b-abc4-8526-aaab6faae5e1@suse.com>","list_archive_url":null,"date":"2022-10-05T07:22:19","name":"[v3,2/7] x86: introduce Pass2 insn attribute","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/925cb740-4e1b-abc4-8526-aaab6faae5e1@suse.com/mbox/"},{"id":1714,"url":"https://patchwork.plctlab.org/api/1.2/patches/1714/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e16d3e78-39ca-f715-508f-a4104b8ab9a9@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-05T07:23:51","name":"[v3,3/7] x86: re-work insn/suffix recognition","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e16d3e78-39ca-f715-508f-a4104b8ab9a9@suse.com/mbox/"},{"id":1715,"url":"https://patchwork.plctlab.org/api/1.2/patches/1715/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e4e4b80b-794c-7485-1997-685adab8fb27@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-05T07:24:20","name":"[v3,4/7] x86-64: further re-work insn/suffix recognition to also cover MOVSL","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e4e4b80b-794c-7485-1997-685adab8fb27@suse.com/mbox/"},{"id":1716,"url":"https://patchwork.plctlab.org/api/1.2/patches/1716/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/540678fc-8bff-ec68-c97c-478d2631998c@suse.com/","msgid":"<540678fc-8bff-ec68-c97c-478d2631998c@suse.com>","list_archive_url":null,"date":"2022-10-05T07:24:55","name":"[v3,5/7] ix86: don'\''t recognize/derive Q suffix in the common case","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/540678fc-8bff-ec68-c97c-478d2631998c@suse.com/mbox/"},{"id":1718,"url":"https://patchwork.plctlab.org/api/1.2/patches/1718/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e4692495-7d3d-074d-14f9-364d4a9a998c@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-05T07:25:25","name":"[v3,6/7] x86-64: allow HLE store of accumulator to absolute 32-bit address","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e4692495-7d3d-074d-14f9-364d4a9a998c@suse.com/mbox/"},{"id":1717,"url":"https://patchwork.plctlab.org/api/1.2/patches/1717/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e8014ebd-d16b-17a7-9f34-3700fc164136@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-05T07:25:57","name":"[v3,7/7] x86: move bad-use-of-TLS-reloc check","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e8014ebd-d16b-17a7-9f34-3700fc164136@suse.com/mbox/"},{"id":1719,"url":"https://patchwork.plctlab.org/api/1.2/patches/1719/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1266f001-4511-2662-dba9-14b4d0317c57@suse.com/","msgid":"<1266f001-4511-2662-dba9-14b4d0317c57@suse.com>","list_archive_url":null,"date":"2022-10-05T07:40:50","name":"x86: drop \"regmask\" static variable","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1266f001-4511-2662-dba9-14b4d0317c57@suse.com/mbox/"},{"id":1751,"url":"https://patchwork.plctlab.org/api/1.2/patches/1751/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/af45c5d57c221e43101c2aa38b14f4b4ac12d011.1665031170.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-06T04:40:15","name":"[v2,1/2] RISC-V: Fallback for instructions longer than 64b","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/af45c5d57c221e43101c2aa38b14f4b4ac12d011.1665031170.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1752,"url":"https://patchwork.plctlab.org/api/1.2/patches/1752/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c6e55781245dd3e8e9b8debd6130fc5449dfbd55.1665031170.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-06T04:40:16","name":"[v2,2/2] RISC-V: Improve \"bits undefined\" diagnostics","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c6e55781245dd3e8e9b8debd6130fc5449dfbd55.1665031170.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1776,"url":"https://patchwork.plctlab.org/api/1.2/patches/1776/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d52952119e15357c0e823f8a2398999359588b4d.1665050099.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-06T09:56:30","name":"[v3,1/2] RISC-V: Fallback for instructions longer than 64b","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d52952119e15357c0e823f8a2398999359588b4d.1665050099.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1777,"url":"https://patchwork.plctlab.org/api/1.2/patches/1777/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d907b1997f60ff7823c4a23e281ec9d8ddcbf3f1.1665050099.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-06T09:56:31","name":"[v3,2/2] RISC-V: Improve \"bits undefined\" diagnostics","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d907b1997f60ff7823c4a23e281ec9d8ddcbf3f1.1665050099.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1781,"url":"https://patchwork.plctlab.org/api/1.2/patches/1781/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221006114628.304185-1-chigot@adacore.com/","msgid":"<20221006114628.304185-1-chigot@adacore.com>","list_archive_url":null,"date":"2022-10-06T11:46:28","name":"RISC-V: fix linker message when relaxation deletes bytes","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221006114628.304185-1-chigot@adacore.com/mbox/"},{"id":1801,"url":"https://patchwork.plctlab.org/api/1.2/patches/1801/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Yz+Yhyg7UewC9/kp@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-07T03:09:59","name":"PR29653, objcopy/strip: fuzzed small input file induces large output file","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Yz+Yhyg7UewC9/kp@squeak.grove.modra.org/mbox/"},{"id":1803,"url":"https://patchwork.plctlab.org/api/1.2/patches/1803/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/PH1P110MB16505D9D39EC5B1DE22FE3D5EC5F9@PH1P110MB1650.NAMP110.PROD.OUTLOOK.COM/","msgid":"","list_archive_url":null,"date":"2022-10-07T04:10:07","name":"@CPP_FOR_BUILD@ problem since binutils-2.38","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/PH1P110MB16505D9D39EC5B1DE22FE3D5EC5F9@PH1P110MB1650.NAMP110.PROD.OUTLOOK.COM/mbox/"},{"id":1827,"url":"https://patchwork.plctlab.org/api/1.2/patches/1827/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8e13bce108ac10a0c1dd911e23ec572926f7ae44.1665203374.git.research_trasio@irq.a4lg.com/","msgid":"<8e13bce108ac10a0c1dd911e23ec572926f7ae44.1665203374.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-08T04:29:53","name":"[v2,1/1] RISC-V: Test DWARF register numbers for \"fp\"","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8e13bce108ac10a0c1dd911e23ec572926f7ae44.1665203374.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1828,"url":"https://patchwork.plctlab.org/api/1.2/patches/1828/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0883001b3572e54d3fba264429c7ade2adb66610.1665203441.git.research_trasio@irq.a4lg.com/","msgid":"<0883001b3572e54d3fba264429c7ade2adb66610.1665203441.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-08T04:31:15","name":"[1/1] RISC-V: Move standard hints before all instructions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0883001b3572e54d3fba264429c7ade2adb66610.1665203441.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1829,"url":"https://patchwork.plctlab.org/api/1.2/patches/1829/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/58e16a241d7376fcae2515c6bd5a2b41d275eeba.1665203531.git.research_trasio@irq.a4lg.com/","msgid":"<58e16a241d7376fcae2515c6bd5a2b41d275eeba.1665203531.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-08T04:32:18","name":"[RFC,1/1] RISC-V: Imply '\''Zicsr'\'' from privileged extensions with CSRs","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/58e16a241d7376fcae2515c6bd5a2b41d275eeba.1665203531.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1830,"url":"https://patchwork.plctlab.org/api/1.2/patches/1830/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/cb5076fc96e8f2097779a3abcde843dcdd660031.1665203660.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-08T04:34:23","name":"[1/5] opcodes/riscv-dis.c: Tidying with comments/clarity","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/cb5076fc96e8f2097779a3abcde843dcdd660031.1665203660.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1832,"url":"https://patchwork.plctlab.org/api/1.2/patches/1832/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1f1aa0838bf9c4f10a45fcfe3c682f7efc79d9ae.1665203660.git.research_trasio@irq.a4lg.com/","msgid":"<1f1aa0838bf9c4f10a45fcfe3c682f7efc79d9ae.1665203660.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-08T04:34:24","name":"[2/5] opcodes/riscv-dis.c: Tidying with spacing","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1f1aa0838bf9c4f10a45fcfe3c682f7efc79d9ae.1665203660.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1831,"url":"https://patchwork.plctlab.org/api/1.2/patches/1831/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/740bc5e2d2618d236519b39fedd1a1d7ae4e05da.1665203660.git.research_trasio@irq.a4lg.com/","msgid":"<740bc5e2d2618d236519b39fedd1a1d7ae4e05da.1665203660.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-08T04:34:25","name":"[3/5] opcodes/riscv-dis.c: Use bool type whenever possible","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/740bc5e2d2618d236519b39fedd1a1d7ae4e05da.1665203660.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1833,"url":"https://patchwork.plctlab.org/api/1.2/patches/1833/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6e3a9c235e317f441b4383b3daa68f2051bdc149.1665203660.git.research_trasio@irq.a4lg.com/","msgid":"<6e3a9c235e317f441b4383b3daa68f2051bdc149.1665203660.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-08T04:34:26","name":"[4/5] opcodes/riscv-dis.c: Make XLEN variable static","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6e3a9c235e317f441b4383b3daa68f2051bdc149.1665203660.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1834,"url":"https://patchwork.plctlab.org/api/1.2/patches/1834/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ad929233a62d887495122721340b2f9c80392963.1665203660.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-08T04:34:27","name":"[5/5] opcodes/riscv-dis.c: Remove last_map_state","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ad929233a62d887495122721340b2f9c80392963.1665203660.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1836,"url":"https://patchwork.plctlab.org/api/1.2/patches/1836/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d07e2b6f36ea2fd5830924a9bfeda941b774b687.1665290422.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-09T05:09:22","name":"RISC-V: Move certain arrays to riscv-opc.c","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d07e2b6f36ea2fd5830924a9bfeda941b774b687.1665290422.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1844,"url":"https://patchwork.plctlab.org/api/1.2/patches/1844/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010004623.16582-1-mark@harmstone.com/","msgid":"<20221010004623.16582-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-10T00:46:22","name":"[v2,1/2] ld: Add --pdb option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010004623.16582-1-mark@harmstone.com/mbox/"},{"id":1845,"url":"https://patchwork.plctlab.org/api/1.2/patches/1845/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010004623.16582-2-mark@harmstone.com/","msgid":"<20221010004623.16582-2-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-10T00:46:23","name":"[v2,2/2] ld: Add minimal pdb generation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010004623.16582-2-mark@harmstone.com/mbox/"},{"id":1890,"url":"https://patchwork.plctlab.org/api/1.2/patches/1890/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010200433.414320-1-vladimir.mezentsev@oracle.com/","msgid":"<20221010200433.414320-1-vladimir.mezentsev@oracle.com>","list_archive_url":null,"date":"2022-10-10T20:04:33","name":"gprofng: run tests without installation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010200433.414320-1-vladimir.mezentsev@oracle.com/mbox/"},{"id":1893,"url":"https://patchwork.plctlab.org/api/1.2/patches/1893/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010230426.719238-1-vladimir.mezentsev@oracle.com/","msgid":"<20221010230426.719238-1-vladimir.mezentsev@oracle.com>","list_archive_url":null,"date":"2022-10-10T23:04:26","name":"[2/2] gprofng: use the --libdir path to find libraries","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010230426.719238-1-vladimir.mezentsev@oracle.com/mbox/"},{"id":1894,"url":"https://patchwork.plctlab.org/api/1.2/patches/1894/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010235155.842469-1-vladimir.mezentsev@oracle.com/","msgid":"<20221010235155.842469-1-vladimir.mezentsev@oracle.com>","list_archive_url":null,"date":"2022-10-10T23:51:55","name":"[3/3] gprofng: no need to build version.texi","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010235155.842469-1-vladimir.mezentsev@oracle.com/mbox/"},{"id":1895,"url":"https://patchwork.plctlab.org/api/1.2/patches/1895/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011003702.4287-1-mark@harmstone.com/","msgid":"<20221011003702.4287-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-11T00:37:01","name":"[v3,1/2] ld: Add --pdb option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011003702.4287-1-mark@harmstone.com/mbox/"},{"id":1897,"url":"https://patchwork.plctlab.org/api/1.2/patches/1897/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011003702.4287-2-mark@harmstone.com/","msgid":"<20221011003702.4287-2-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-11T00:37:02","name":"[v3,2/2] ld: Add minimal pdb generation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011003702.4287-2-mark@harmstone.com/mbox/"},{"id":1928,"url":"https://patchwork.plctlab.org/api/1.2/patches/1928/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011175332.17156-1-mark@harmstone.com/","msgid":"<20221011175332.17156-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-11T17:53:31","name":"[v4,1/2] ld: Add --pdb option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011175332.17156-1-mark@harmstone.com/mbox/"},{"id":1929,"url":"https://patchwork.plctlab.org/api/1.2/patches/1929/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011175332.17156-2-mark@harmstone.com/","msgid":"<20221011175332.17156-2-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-11T17:53:32","name":"[v4,2/2] ld: Add minimal pdb generation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011175332.17156-2-mark@harmstone.com/mbox/"},{"id":1941,"url":"https://patchwork.plctlab.org/api/1.2/patches/1941/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221012031005.237446-1-simon.marchi@polymtl.ca/","msgid":"<20221012031005.237446-1-simon.marchi@polymtl.ca>","list_archive_url":null,"date":"2022-10-12T03:10:05","name":"[pushed] Re-apply \"Pass PKG_CONFIG_PATH down from top-level Makefile\"","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221012031005.237446-1-simon.marchi@polymtl.ca/mbox/"},{"id":1976,"url":"https://patchwork.plctlab.org/api/1.2/patches/1976/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1216a3f8-2273-8681-f528-9493a66891f0@suse.com/","msgid":"<1216a3f8-2273-8681-f528-9493a66891f0@suse.com>","list_archive_url":null,"date":"2022-10-13T08:16:49","name":"[v4,1/8] x86: constify parse_insn()'\''s input","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1216a3f8-2273-8681-f528-9493a66891f0@suse.com/mbox/"},{"id":1977,"url":"https://patchwork.plctlab.org/api/1.2/patches/1977/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/11599bbe-c779-aa9f-4d5d-c2243f0e69dc@suse.com/","msgid":"<11599bbe-c779-aa9f-4d5d-c2243f0e69dc@suse.com>","list_archive_url":null,"date":"2022-10-13T08:17:17","name":"[v4,2/8] x86: introduce Pass2 insn attribute","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/11599bbe-c779-aa9f-4d5d-c2243f0e69dc@suse.com/mbox/"},{"id":1978,"url":"https://patchwork.plctlab.org/api/1.2/patches/1978/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/357273a3-060c-23db-72da-3fc9d1be3d2a@suse.com/","msgid":"<357273a3-060c-23db-72da-3fc9d1be3d2a@suse.com>","list_archive_url":null,"date":"2022-10-13T08:18:09","name":"[v4,3/8] x86: re-work insn/suffix recognition","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/357273a3-060c-23db-72da-3fc9d1be3d2a@suse.com/mbox/"},{"id":1979,"url":"https://patchwork.plctlab.org/api/1.2/patches/1979/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0ec0587f-6a7b-45b6-8346-e5d774e73636@suse.com/","msgid":"<0ec0587f-6a7b-45b6-8346-e5d774e73636@suse.com>","list_archive_url":null,"date":"2022-10-13T08:18:39","name":"[v4,4/8] x86-64: further re-work insn/suffix recognition to also cover MOVSL","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0ec0587f-6a7b-45b6-8346-e5d774e73636@suse.com/mbox/"},{"id":1980,"url":"https://patchwork.plctlab.org/api/1.2/patches/1980/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fb617d0b-8759-3169-5a65-1178b7fef3d7@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-13T08:19:34","name":"[v4,5/8] ix86: don'\''t recognize/derive Q suffix in the common case","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fb617d0b-8759-3169-5a65-1178b7fef3d7@suse.com/mbox/"},{"id":1981,"url":"https://patchwork.plctlab.org/api/1.2/patches/1981/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1df3bd01-99c5-f56c-d937-970edd42b2b8@suse.com/","msgid":"<1df3bd01-99c5-f56c-d937-970edd42b2b8@suse.com>","list_archive_url":null,"date":"2022-10-13T08:20:14","name":"[v4,6/8] x86-64: allow HLE store of accumulator to absolute 32-bit address","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1df3bd01-99c5-f56c-d937-970edd42b2b8@suse.com/mbox/"},{"id":1982,"url":"https://patchwork.plctlab.org/api/1.2/patches/1982/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8486a218-39ec-16b2-5c6c-5037196b93cf@suse.com/","msgid":"<8486a218-39ec-16b2-5c6c-5037196b93cf@suse.com>","list_archive_url":null,"date":"2022-10-13T08:21:00","name":"[v4,7/8] x86: move bad-use-of-TLS-reloc check","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8486a218-39ec-16b2-5c6c-5037196b93cf@suse.com/mbox/"},{"id":1983,"url":"https://patchwork.plctlab.org/api/1.2/patches/1983/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7d82692d-93df-fbee-9efb-2f44e8a91df3@suse.com/","msgid":"<7d82692d-93df-fbee-9efb-2f44e8a91df3@suse.com>","list_archive_url":null,"date":"2022-10-13T08:22:00","name":"[v4,8/8] x86: drop (now) stray IsString","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7d82692d-93df-fbee-9efb-2f44e8a91df3@suse.com/mbox/"},{"id":2013,"url":"https://patchwork.plctlab.org/api/1.2/patches/2013/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8ab93d7a617ad480dd786210f46db0e5aa07d1ac.1665655719.git.research_trasio@irq.a4lg.com/","msgid":"<8ab93d7a617ad480dd786210f46db0e5aa07d1ac.1665655719.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-13T10:11:41","name":"include: Declare getopt function on old GNU libc","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8ab93d7a617ad480dd786210f46db0e5aa07d1ac.1665655719.git.research_trasio@irq.a4lg.com/mbox/"},{"id":2352,"url":"https://patchwork.plctlab.org/api/1.2/patches/2352/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221013201332.2747246-1-maskray@google.com/","msgid":"<20221013201332.2747246-1-maskray@google.com>","list_archive_url":null,"date":"2022-10-13T20:13:32","name":"ld: Add --undefined-version","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221013201332.2747246-1-maskray@google.com/mbox/"},{"id":2532,"url":"https://patchwork.plctlab.org/api/1.2/patches/2532/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014063520.1428330-2-zengxiao@eswincomputing.com/","msgid":"<20221014063520.1428330-2-zengxiao@eswincomputing.com>","list_archive_url":null,"date":"2022-10-14T06:35:20","name":"[1/1] RISC-V: Make R_RISCV_SUB6 conforms to riscv abi standard","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014063520.1428330-2-zengxiao@eswincomputing.com/mbox/"},{"id":2560,"url":"https://patchwork.plctlab.org/api/1.2/patches/2560/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/027ae69a-636b-6757-297a-eec42936401e@linaro.org/","msgid":"<027ae69a-636b-6757-297a-eec42936401e@linaro.org>","list_archive_url":null,"date":"2022-10-14T07:58:22","name":"[v3] aarch64-pe support for LD, GAS and BFD","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/027ae69a-636b-6757-297a-eec42936401e@linaro.org/mbox/"},{"id":2602,"url":"https://patchwork.plctlab.org/api/1.2/patches/2602/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-2-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-2-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:39","name":"[01/10] Support Intel AVX-IFMA","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-2-haochen.jiang@intel.com/mbox/"},{"id":2608,"url":"https://patchwork.plctlab.org/api/1.2/patches/2608/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-3-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-3-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:40","name":"[02/10] Support Intel AVX-VNNI-INT8","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-3-haochen.jiang@intel.com/mbox/"},{"id":2611,"url":"https://patchwork.plctlab.org/api/1.2/patches/2611/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-4-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-4-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:41","name":"[03/10] Support Intel AVX-NE-CONVERT","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-4-haochen.jiang@intel.com/mbox/"},{"id":2610,"url":"https://patchwork.plctlab.org/api/1.2/patches/2610/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-5-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-5-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:42","name":"[04/10] Support Intel CMPccXADD","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-5-haochen.jiang@intel.com/mbox/"},{"id":2601,"url":"https://patchwork.plctlab.org/api/1.2/patches/2601/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-6-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-6-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:43","name":"[05/10] Add handler for more i386_cpu_flags","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-6-haochen.jiang@intel.com/mbox/"},{"id":2606,"url":"https://patchwork.plctlab.org/api/1.2/patches/2606/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-7-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-7-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:44","name":"[06/10] Support Intel RAO-INT","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-7-haochen.jiang@intel.com/mbox/"},{"id":2609,"url":"https://patchwork.plctlab.org/api/1.2/patches/2609/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-8-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-8-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:45","name":"[07/10] Support Intel WRMSRNS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-8-haochen.jiang@intel.com/mbox/"},{"id":2605,"url":"https://patchwork.plctlab.org/api/1.2/patches/2605/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-9-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-9-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:46","name":"[08/10] Support Intel MSRLIST","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-9-haochen.jiang@intel.com/mbox/"},{"id":2607,"url":"https://patchwork.plctlab.org/api/1.2/patches/2607/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-10-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-10-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:47","name":"[09/10] Support Intel AMX-FP16","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-10-haochen.jiang@intel.com/mbox/"},{"id":2604,"url":"https://patchwork.plctlab.org/api/1.2/patches/2604/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-11-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-11-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:48","name":"[10/10] Support Intel PREFETCHI","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-11-haochen.jiang@intel.com/mbox/"},{"id":2643,"url":"https://patchwork.plctlab.org/api/1.2/patches/2643/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7bac66be-535e-9051-d674-f2f5ba180e17@suse.com/","msgid":"<7bac66be-535e-9051-d674-f2f5ba180e17@suse.com>","list_archive_url":null,"date":"2022-10-14T10:22:34","name":"x86: fold AVX512-VNNI disassembler entries with AVX-VNNI ones","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7bac66be-535e-9051-d674-f2f5ba180e17@suse.com/mbox/"},{"id":2654,"url":"https://patchwork.plctlab.org/api/1.2/patches/2654/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0lIo5+ncY/MqBEq@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-14T11:31:47","name":"PR29677, Field `the_bfd` of `asymbol` is uninitialised","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0lIo5+ncY/MqBEq@squeak.grove.modra.org/mbox/"},{"id":2656,"url":"https://patchwork.plctlab.org/api/1.2/patches/2656/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0lJksn49ZpABY89@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-14T11:35:46","name":"e200 LSP support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0lJksn49ZpABY89@squeak.grove.modra.org/mbox/"},{"id":2657,"url":"https://patchwork.plctlab.org/api/1.2/patches/2657/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0lJxxYoeD5iDYAD@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-14T11:36:39","name":"PowerPC SPE disassembly and tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0lJxxYoeD5iDYAD@squeak.grove.modra.org/mbox/"},{"id":2695,"url":"https://patchwork.plctlab.org/api/1.2/patches/2695/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/DM6PR12MB4219611F6CC2A0702884A602E7249@DM6PR12MB4219.namprd12.prod.outlook.com/","msgid":"","list_archive_url":null,"date":"2022-10-14T13:29:40","name":"Binutils: Adding new testcase for addr2line.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/DM6PR12MB4219611F6CC2A0702884A602E7249@DM6PR12MB4219.namprd12.prod.outlook.com/mbox/"},{"id":2700,"url":"https://patchwork.plctlab.org/api/1.2/patches/2700/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9fd2c88d-98b2-99a4-419f-c7235b2cf960@suse.com/","msgid":"<9fd2c88d-98b2-99a4-419f-c7235b2cf960@suse.com>","list_archive_url":null,"date":"2022-10-14T14:11:35","name":"x86: properly decode EVEX.W for AVX512_4{FMAPS,VNNIW} insns","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9fd2c88d-98b2-99a4-419f-c7235b2cf960@suse.com/mbox/"},{"id":2981,"url":"https://patchwork.plctlab.org/api/1.2/patches/2981/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0uLzalqjm4C87GN@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-16T04:42:53","name":"PowerPC se_rfmci and VLE, SPE2 and LSP insns with -many","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0uLzalqjm4C87GN@squeak.grove.modra.org/mbox/"},{"id":3152,"url":"https://patchwork.plctlab.org/api/1.2/patches/3152/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221016232419.1135-1-mark@harmstone.com/","msgid":"<20221016232419.1135-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-16T23:24:18","name":"[v5,1/2] ld: Add --pdb option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221016232419.1135-1-mark@harmstone.com/mbox/"},{"id":3151,"url":"https://patchwork.plctlab.org/api/1.2/patches/3151/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221016232419.1135-2-mark@harmstone.com/","msgid":"<20221016232419.1135-2-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-16T23:24:19","name":"[v5,2/2] ld: Add minimal pdb generation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221016232419.1135-2-mark@harmstone.com/mbox/"},{"id":3258,"url":"https://patchwork.plctlab.org/api/1.2/patches/3258/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/19c08747-fa5b-1e67-3dd2-c891a2c0c1fa@suse.com/","msgid":"<19c08747-fa5b-1e67-3dd2-c891a2c0c1fa@suse.com>","list_archive_url":null,"date":"2022-10-17T07:44:51","name":"x86: correct CPU_AMX_{BF16,INT8}_FLAGS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/19c08747-fa5b-1e67-3dd2-c891a2c0c1fa@suse.com/mbox/"},{"id":3272,"url":"https://patchwork.plctlab.org/api/1.2/patches/3272/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/85dd526c-d3a7-72dc-5444-ed5573eebec1@suse.com/","msgid":"<85dd526c-d3a7-72dc-5444-ed5573eebec1@suse.com>","list_archive_url":null,"date":"2022-10-17T08:30:12","name":"x86: generalize gas documentation for disabling of ISA extensions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/85dd526c-d3a7-72dc-5444-ed5573eebec1@suse.com/mbox/"},{"id":3759,"url":"https://patchwork.plctlab.org/api/1.2/patches/3759/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-2-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-2-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:15:58","name":"[V2,01/15] sframe.h: Add SFrame format definition","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-2-indu.bhagat@oracle.com/mbox/"},{"id":3762,"url":"https://patchwork.plctlab.org/api/1.2/patches/3762/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-3-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-3-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:15:59","name":"[V2,02/15] gas: add new command line option --gsframe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-3-indu.bhagat@oracle.com/mbox/"},{"id":3761,"url":"https://patchwork.plctlab.org/api/1.2/patches/3761/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-4-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-4-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:00","name":"[V2,03/15] gas: generate .sframe from CFI directives","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-4-indu.bhagat@oracle.com/mbox/"},{"id":3760,"url":"https://patchwork.plctlab.org/api/1.2/patches/3760/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-5-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-5-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:01","name":"[V2,04/15] gas: testsuite: add new tests for SFrame unwind info","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-5-indu.bhagat@oracle.com/mbox/"},{"id":3764,"url":"https://patchwork.plctlab.org/api/1.2/patches/3764/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-6-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-6-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:02","name":"[V2,05/15] libsframe: add the SFrame library","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-6-indu.bhagat@oracle.com/mbox/"},{"id":3766,"url":"https://patchwork.plctlab.org/api/1.2/patches/3766/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-7-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-7-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:03","name":"[V2,06/15] bfd: linker: merge .sframe sections","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-7-indu.bhagat@oracle.com/mbox/"},{"id":3763,"url":"https://patchwork.plctlab.org/api/1.2/patches/3763/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-8-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-8-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:04","name":"[V2,07/15] readelf/objdump: support for SFrame section","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-8-indu.bhagat@oracle.com/mbox/"},{"id":3765,"url":"https://patchwork.plctlab.org/api/1.2/patches/3765/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-9-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-9-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:05","name":"[V2,08/15] unwinder: generate backtrace using SFrame format","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-9-indu.bhagat@oracle.com/mbox/"},{"id":3770,"url":"https://patchwork.plctlab.org/api/1.2/patches/3770/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-10-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-10-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:06","name":"[V2,09/15] unwinder: Add SFrame unwinder tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-10-indu.bhagat@oracle.com/mbox/"},{"id":3769,"url":"https://patchwork.plctlab.org/api/1.2/patches/3769/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-11-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-11-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:07","name":"[V2,10/15] gdb: sim: buildsystem changes to accommodate libsframe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-11-indu.bhagat@oracle.com/mbox/"},{"id":3771,"url":"https://patchwork.plctlab.org/api/1.2/patches/3771/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-12-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-12-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:08","name":"[V2,11/15] libctf: add libsframe to LDFLAGS and LIBS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-12-indu.bhagat@oracle.com/mbox/"},{"id":3768,"url":"https://patchwork.plctlab.org/api/1.2/patches/3768/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-13-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-13-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:09","name":"[V2,12/15] src-release.sh: Add libsframe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-13-indu.bhagat@oracle.com/mbox/"},{"id":3767,"url":"https://patchwork.plctlab.org/api/1.2/patches/3767/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-14-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-14-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:10","name":"[V2,13/15] binutils/NEWS: add text for SFrame support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-14-indu.bhagat@oracle.com/mbox/"},{"id":3772,"url":"https://patchwork.plctlab.org/api/1.2/patches/3772/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-15-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-15-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:11","name":"[V2,14/15] gas/NEWS: add text about new command line option and SFrame support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-15-indu.bhagat@oracle.com/mbox/"},{"id":3773,"url":"https://patchwork.plctlab.org/api/1.2/patches/3773/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-16-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-16-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:12","name":"[V2,15/15] doc: add SFrame spec file","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-16-indu.bhagat@oracle.com/mbox/"},{"id":3999,"url":"https://patchwork.plctlab.org/api/1.2/patches/3999/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221018081205.17880-1-krebbel@linux.ibm.com/","msgid":"<20221018081205.17880-1-krebbel@linux.ibm.com>","list_archive_url":null,"date":"2022-10-18T08:12:05","name":"[1/1] IBM zSystems: Issue error for *DBL relocs on misaligned symbols","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221018081205.17880-1-krebbel@linux.ibm.com/mbox/"},{"id":4141,"url":"https://patchwork.plctlab.org/api/1.2/patches/4141/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/baffaf673f17692b7bcbd604b31800b189988596.camel@espressif.com/","msgid":"","list_archive_url":null,"date":"2022-10-18T12:12:07","name":"xtensa: use definitions from xtensa-config.h","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/baffaf673f17692b7bcbd604b31800b189988596.camel@espressif.com/mbox/"},{"id":4272,"url":"https://patchwork.plctlab.org/api/1.2/patches/4272/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221018174914.470062-1-hjl.tools@gmail.com/","msgid":"<20221018174914.470062-1-hjl.tools@gmail.com>","list_archive_url":null,"date":"2022-10-18T17:49:14","name":"x86: Disable AVX-VNNI when disabling AVX2","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221018174914.470062-1-hjl.tools@gmail.com/mbox/"},{"id":4998,"url":"https://patchwork.plctlab.org/api/1.2/patches/4998/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c2f76e95-09f6-1d92-7ef4-38a3c2955fcd@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-19T09:52:46","name":"x86: re-work AVX-VNNI support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c2f76e95-09f6-1d92-7ef4-38a3c2955fcd@suse.com/mbox/"},{"id":5276,"url":"https://patchwork.plctlab.org/api/1.2/patches/5276/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0/lLtlKqqsmAx0s@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-19T11:53:18","name":"Fix addr2line test for ppc64 elfv1 and mingw","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0/lLtlKqqsmAx0s@squeak.grove.modra.org/mbox/"},{"id":5424,"url":"https://patchwork.plctlab.org/api/1.2/patches/5424/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/07bfebbf3843b47e13d82d4fa16eb14fec942ef7.1666184962.git.research_trasio@irq.a4lg.com/","msgid":"<07bfebbf3843b47e13d82d4fa16eb14fec942ef7.1666184962.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:09:54","name":"binutils: Remove unused substitution PROGRAM","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/07bfebbf3843b47e13d82d4fa16eb14fec942ef7.1666184962.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5433,"url":"https://patchwork.plctlab.org/api/1.2/patches/5433/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2fa7ff719223232402e82a9c91331aea22ace1bb.1666185116.git.research_trasio@irq.a4lg.com/","msgid":"<2fa7ff719223232402e82a9c91331aea22ace1bb.1666185116.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:11:55","name":"[v2,1/8] RISC-V: Add a space at the end of pinfo","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2fa7ff719223232402e82a9c91331aea22ace1bb.1666185116.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5435,"url":"https://patchwork.plctlab.org/api/1.2/patches/5435/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1b30cce5db2cce3b8edca42ab5da114d0b8c9e93.1666185116.git.research_trasio@irq.a4lg.com/","msgid":"<1b30cce5db2cce3b8edca42ab5da114d0b8c9e93.1666185116.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:11:56","name":"[v2,2/8] RISC-V: Fix obvious misalignments ('\''Zbb'\''/'\''Zba'\'')","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1b30cce5db2cce3b8edca42ab5da114d0b8c9e93.1666185116.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5437,"url":"https://patchwork.plctlab.org/api/1.2/patches/5437/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6b0857aa1a2d15ca1cf00b4dcaae0032efbb88ff.1666185116.git.research_trasio@irq.a4lg.com/","msgid":"<6b0857aa1a2d15ca1cf00b4dcaae0032efbb88ff.1666185116.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:11:57","name":"[v2,3/8] RISC-V: Remove spaces in opcode entries","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6b0857aa1a2d15ca1cf00b4dcaae0032efbb88ff.1666185116.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5436,"url":"https://patchwork.plctlab.org/api/1.2/patches/5436/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/889d956caac0f2e95543a14afaeed97188ce384c.1666185116.git.research_trasio@irq.a4lg.com/","msgid":"<889d956caac0f2e95543a14afaeed97188ce384c.1666185116.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:11:58","name":"[v2,4/8] RISC-V: Remove unused instruction macros","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/889d956caac0f2e95543a14afaeed97188ce384c.1666185116.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5440,"url":"https://patchwork.plctlab.org/api/1.2/patches/5440/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8f226ee20d8a5ef6ad7b6c4408b44794a99d542a.1666185116.git.research_trasio@irq.a4lg.com/","msgid":"<8f226ee20d8a5ef6ad7b6c4408b44794a99d542a.1666185116.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:11:59","name":"[v2,5/8] RISC-V: Complete tidying up with SCALL and SBREAK","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8f226ee20d8a5ef6ad7b6c4408b44794a99d542a.1666185116.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5442,"url":"https://patchwork.plctlab.org/api/1.2/patches/5442/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4070184c454a05a39adf0790951e5856e6b2ecb6.1666185116.git.research_trasio@irq.a4lg.com/","msgid":"<4070184c454a05a39adf0790951e5856e6b2ecb6.1666185116.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:12:00","name":"[v2,6/8] RISC-V: Tidying up with fmv.w.x and fmv.x.w","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4070184c454a05a39adf0790951e5856e6b2ecb6.1666185116.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5438,"url":"https://patchwork.plctlab.org/api/1.2/patches/5438/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c1ccda3e7c8fb297eda46dab3936d5c5977178fc.1666185116.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-19T13:12:01","name":"[v2,7/8] RISC-V: Make alias instructions aliases","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c1ccda3e7c8fb297eda46dab3936d5c5977178fc.1666185116.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5441,"url":"https://patchwork.plctlab.org/api/1.2/patches/5441/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/413cfca82c7e8d8a2e977dfda9135903c9cb7c57.1666185116.git.research_trasio@irq.a4lg.com/","msgid":"<413cfca82c7e8d8a2e977dfda9135903c9cb7c57.1666185116.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:12:02","name":"[v2,8/8] RISC-V: Use defined mask and match values","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/413cfca82c7e8d8a2e977dfda9135903c9cb7c57.1666185116.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5439,"url":"https://patchwork.plctlab.org/api/1.2/patches/5439/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/345c5c3b3a53eab04a1e6e91197de2642095c94f.1666185237.git.research_trasio@irq.a4lg.com/","msgid":"<345c5c3b3a53eab04a1e6e91197de2642095c94f.1666185237.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:14:01","name":"RISC-V: Remove RV32EF conflict","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/345c5c3b3a53eab04a1e6e91197de2642095c94f.1666185237.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5616,"url":"https://patchwork.plctlab.org/api/1.2/patches/5616/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019145608.45213-5-haochen.jiang@intel.com/","msgid":"<20221019145608.45213-5-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T14:56:02","name":"[04/10] Support Intel CMPccXADD","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019145608.45213-5-haochen.jiang@intel.com/mbox/"},{"id":5614,"url":"https://patchwork.plctlab.org/api/1.2/patches/5614/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019145608.45213-6-haochen.jiang@intel.com/","msgid":"<20221019145608.45213-6-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T14:56:03","name":"[05/10] Add handler for more i386_cpu_flags","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019145608.45213-6-haochen.jiang@intel.com/mbox/"},{"id":5672,"url":"https://patchwork.plctlab.org/api/1.2/patches/5672/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-2-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-2-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:25","name":"[01/10] Support Intel AVX-IFMA","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-2-haochen.jiang@intel.com/mbox/"},{"id":5691,"url":"https://patchwork.plctlab.org/api/1.2/patches/5691/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-3-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-3-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:26","name":"[02/10] Support Intel AVX-VNNI-INT8","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-3-haochen.jiang@intel.com/mbox/"},{"id":5690,"url":"https://patchwork.plctlab.org/api/1.2/patches/5690/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-4-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-4-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:27","name":"[03/10] Support Intel AVX-NE-CONVERT","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-4-haochen.jiang@intel.com/mbox/"},{"id":5689,"url":"https://patchwork.plctlab.org/api/1.2/patches/5689/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-5-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-5-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:28","name":"[04/10] Support Intel CMPccXADD","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-5-haochen.jiang@intel.com/mbox/"},{"id":5676,"url":"https://patchwork.plctlab.org/api/1.2/patches/5676/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-6-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-6-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:29","name":"[05/10] Add handler for more i386_cpu_flags","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-6-haochen.jiang@intel.com/mbox/"},{"id":5677,"url":"https://patchwork.plctlab.org/api/1.2/patches/5677/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-7-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-7-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:30","name":"[06/10] Support Intel RAO-INT","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-7-haochen.jiang@intel.com/mbox/"},{"id":5681,"url":"https://patchwork.plctlab.org/api/1.2/patches/5681/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-8-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-8-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:31","name":"[07/10] Support Intel WRMSRNS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-8-haochen.jiang@intel.com/mbox/"},{"id":5682,"url":"https://patchwork.plctlab.org/api/1.2/patches/5682/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-9-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-9-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:32","name":"[08/10] Support Intel MSRLIST","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-9-haochen.jiang@intel.com/mbox/"},{"id":5673,"url":"https://patchwork.plctlab.org/api/1.2/patches/5673/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-10-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-10-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:33","name":"[09/10] Support Intel AMX-FP16","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-10-haochen.jiang@intel.com/mbox/"},{"id":5686,"url":"https://patchwork.plctlab.org/api/1.2/patches/5686/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-11-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-11-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:34","name":"[10/10] Support Intel PREFETCHI","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-11-haochen.jiang@intel.com/mbox/"},{"id":5940,"url":"https://patchwork.plctlab.org/api/1.2/patches/5940/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1CMrFUC8d9lC/NL@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-19T23:47:56","name":"Obsolete beos","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1CMrFUC8d9lC/NL@squeak.grove.modra.org/mbox/"},{"id":6080,"url":"https://patchwork.plctlab.org/api/1.2/patches/6080/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8b99d666e78ba5b9d32c7889a2161c70b3da88df.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<8b99d666e78ba5b9d32c7889a2161c70b3da88df.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:25:47","name":"[01/40] gdb/unittests: PR28413, suppress warnings generated by Gnulib","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8b99d666e78ba5b9d32c7889a2161c70b3da88df.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6081,"url":"https://patchwork.plctlab.org/api/1.2/patches/6081/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b05adb17e401d621dbdad791281bc7af7806906e.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-20T09:25:48","name":"[02/40] sim: Check known getrusage declaration existence","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b05adb17e401d621dbdad791281bc7af7806906e.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6083,"url":"https://patchwork.plctlab.org/api/1.2/patches/6083/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/796962a87e569feeafb5ef636de3c79000ae152c.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<796962a87e569feeafb5ef636de3c79000ae152c.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:25:49","name":"[03/40] sim/aarch64: Remove unused functions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/796962a87e569feeafb5ef636de3c79000ae152c.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6084,"url":"https://patchwork.plctlab.org/api/1.2/patches/6084/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/65223c79fdfd7faf132275415cd9da9852c5bec3.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<65223c79fdfd7faf132275415cd9da9852c5bec3.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:25:50","name":"[04/40] cpu/cris: Initialize some variables on CRIS CPU","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/65223c79fdfd7faf132275415cd9da9852c5bec3.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6082,"url":"https://patchwork.plctlab.org/api/1.2/patches/6082/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/24baefe92148f4b7968115ba13de9b0c863a65f6.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<24baefe92148f4b7968115ba13de9b0c863a65f6.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:25:51","name":"[05/40] cpu/cris: Add u-stall virtual unit to CRIS v32","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/24baefe92148f4b7968115ba13de9b0c863a65f6.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6087,"url":"https://patchwork.plctlab.org/api/1.2/patches/6087/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3904a5c3e80f8548150d8088a92059dd728c7ff8.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<3904a5c3e80f8548150d8088a92059dd728c7ff8.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:25:52","name":"[06/40] sim/cris: Move declarations of f_specific_init","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3904a5c3e80f8548150d8088a92059dd728c7ff8.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6091,"url":"https://patchwork.plctlab.org/api/1.2/patches/6091/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/69ef2d7dd519ed572511890a215a0f6d74e53384.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<69ef2d7dd519ed572511890a215a0f6d74e53384.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:25:53","name":"[07/40] sim/cris: Regenerate with CGEN","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/69ef2d7dd519ed572511890a215a0f6d74e53384.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6085,"url":"https://patchwork.plctlab.org/api/1.2/patches/6085/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/26a3eaf4f5d2e0db6977738ddfd65d82b36e38b2.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<26a3eaf4f5d2e0db6977738ddfd65d82b36e38b2.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:25:54","name":"[08/40] sim/erc32: Insert void parameter","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/26a3eaf4f5d2e0db6977738ddfd65d82b36e38b2.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6086,"url":"https://patchwork.plctlab.org/api/1.2/patches/6086/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/057c2f8392410494c3bc5dc98052246508e6a73e.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<057c2f8392410494c3bc5dc98052246508e6a73e.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:25:55","name":"[09/40] sim/erc32: Use int32_t as event callback argument","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/057c2f8392410494c3bc5dc98052246508e6a73e.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6090,"url":"https://patchwork.plctlab.org/api/1.2/patches/6090/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8c05aec20557191434485be347d37177a2ec5ff2.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<8c05aec20557191434485be347d37177a2ec5ff2.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:25:56","name":"[10/40] sim/erc32: Use int32_t as IRQ callback argument","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8c05aec20557191434485be347d37177a2ec5ff2.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6089,"url":"https://patchwork.plctlab.org/api/1.2/patches/6089/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/afd7757aae21743c29f2aa4135a23b31d4959e9b.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-20T09:25:57","name":"[11/40] cpu/frv: Initialize some variables","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/afd7757aae21743c29f2aa4135a23b31d4959e9b.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6088,"url":"https://patchwork.plctlab.org/api/1.2/patches/6088/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/021dbd238af5dfe74523ed229d2156a155a6bb9e.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<021dbd238af5dfe74523ed229d2156a155a6bb9e.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:25:58","name":"[12/40] sim/frv: Initialize nesr variable","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/021dbd238af5dfe74523ed229d2156a155a6bb9e.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6093,"url":"https://patchwork.plctlab.org/api/1.2/patches/6093/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/51a03f7097921cc48954210cf99e370ae8982ec8.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<51a03f7097921cc48954210cf99e370ae8982ec8.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:25:59","name":"[13/40] sim/frv: Initialize some variables","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/51a03f7097921cc48954210cf99e370ae8982ec8.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6092,"url":"https://patchwork.plctlab.org/api/1.2/patches/6092/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e1baa1be3601612266dc6ae0bdde8426ff2a42c8.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-20T09:26:00","name":"[14/40] sim/frv: Add explicit casts","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e1baa1be3601612266dc6ae0bdde8426ff2a42c8.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6095,"url":"https://patchwork.plctlab.org/api/1.2/patches/6095/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5ab303a5bdfc1da7832f8fa22f57678c9ef1a5fa.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<5ab303a5bdfc1da7832f8fa22f57678c9ef1a5fa.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:26:01","name":"[15/40] sim/h8300: Add \"+ 0x0\" to avoid self-assignments","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5ab303a5bdfc1da7832f8fa22f57678c9ef1a5fa.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6101,"url":"https://patchwork.plctlab.org/api/1.2/patches/6101/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ddff80db3328a2286fe6fbc1240d2abc1e3813eb.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-20T09:26:02","name":"[16/40] sim/lm32: fix some missing function declaration warnings","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ddff80db3328a2286fe6fbc1240d2abc1e3813eb.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6094,"url":"https://patchwork.plctlab.org/api/1.2/patches/6094/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e094b1379231d9ffb59a78cfebbcc84634c779c6.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-20T09:26:03","name":"[17/40] sim/lm32: Add explicit casts","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e094b1379231d9ffb59a78cfebbcc84634c779c6.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6141,"url":"https://patchwork.plctlab.org/api/1.2/patches/6141/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/cabebead-489b-528c-580e-933832417474@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-20T10:25:51","name":"[1/3] x86: emit {evex} prefix when disassembling ambiguous AVX512VL insns","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/cabebead-489b-528c-580e-933832417474@suse.com/mbox/"},{"id":6143,"url":"https://patchwork.plctlab.org/api/1.2/patches/6143/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a032d61c-63a0-23d1-331f-619a2b8bbde3@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-20T10:26:15","name":"[2/3] x86: consolidate VAES tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a032d61c-63a0-23d1-331f-619a2b8bbde3@suse.com/mbox/"},{"id":6142,"url":"https://patchwork.plctlab.org/api/1.2/patches/6142/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7ff09c86-2de7-dc34-3183-5187de3df5ac@suse.com/","msgid":"<7ff09c86-2de7-dc34-3183-5187de3df5ac@suse.com>","list_archive_url":null,"date":"2022-10-20T10:26:40","name":"[3/3] x86: consolidate VPCLMUL tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7ff09c86-2de7-dc34-3183-5187de3df5ac@suse.com/mbox/"},{"id":6228,"url":"https://patchwork.plctlab.org/api/1.2/patches/6228/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.LSU.2.20.2210201432170.29399@wotan.suse.de/","msgid":"","list_archive_url":null,"date":"2022-10-20T14:42:25","name":"x86-64: Use only one default max-page-size","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.LSU.2.20.2210201432170.29399@wotan.suse.de/mbox/"},{"id":6229,"url":"https://patchwork.plctlab.org/api/1.2/patches/6229/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221020144351.1398099-1-chigot@adacore.com/","msgid":"<20221020144351.1398099-1-chigot@adacore.com>","list_archive_url":null,"date":"2022-10-20T14:43:50","name":"[1/2] ld/testsuite: skip ld-elf/exclude when -shared is not supported","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221020144351.1398099-1-chigot@adacore.com/mbox/"},{"id":6230,"url":"https://patchwork.plctlab.org/api/1.2/patches/6230/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221020144351.1398099-2-chigot@adacore.com/","msgid":"<20221020144351.1398099-2-chigot@adacore.com>","list_archive_url":null,"date":"2022-10-20T14:43:51","name":"[2/2] ld/testsuite: adjust ld-arm to run shared tests only when supported","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221020144351.1398099-2-chigot@adacore.com/mbox/"},{"id":6236,"url":"https://patchwork.plctlab.org/api/1.2/patches/6236/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221020151027.GA1300@delia.home/","msgid":"<20221020151027.GA1300@delia.home>","list_archive_url":null,"date":"2022-10-20T15:10:28","name":"[RFC,top-level] Add configure test-case","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221020151027.GA1300@delia.home/mbox/"},{"id":6286,"url":"https://patchwork.plctlab.org/api/1.2/patches/6286/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221020162911.1113338-1-hjl.tools@gmail.com/","msgid":"<20221020162911.1113338-1-hjl.tools@gmail.com>","list_archive_url":null,"date":"2022-10-20T16:29:11","name":"x86: Check VEX/EVEX encoding before checking vector operands","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221020162911.1113338-1-hjl.tools@gmail.com/mbox/"},{"id":7884,"url":"https://patchwork.plctlab.org/api/1.2/patches/7884/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7e53b7980f2b3b74d2250bc87f5db94b1d888a2d.camel@espressif.com/","msgid":"<7e53b7980f2b3b74d2250bc87f5db94b1d888a2d.camel@espressif.com>","list_archive_url":null,"date":"2022-10-22T12:53:54","name":"[1/5] bfd: xtensa: move common code from ld and gas","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7e53b7980f2b3b74d2250bc87f5db94b1d888a2d.camel@espressif.com/mbox/"},{"id":7885,"url":"https://patchwork.plctlab.org/api/1.2/patches/7885/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/63f2699e6ef3e6d1ca415a6ed1187d4f64297521.camel@espressif.com/","msgid":"<63f2699e6ef3e6d1ca415a6ed1187d4f64297521.camel@espressif.com>","list_archive_url":null,"date":"2022-10-22T12:55:16","name":"[2/5] gas: xtensa: add endianness, loops, booleans options","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/63f2699e6ef3e6d1ca415a6ed1187d4f64297521.camel@espressif.com/mbox/"},{"id":7886,"url":"https://patchwork.plctlab.org/api/1.2/patches/7886/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/34d2f747237aeeda595560cfded8096d9bd1c28c.camel@espressif.com/","msgid":"<34d2f747237aeeda595560cfded8096d9bd1c28c.camel@espressif.com>","list_archive_url":null,"date":"2022-10-22T12:56:02","name":"[3/5] ld: xtensa: use default LD command line options for endianness","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/34d2f747237aeeda595560cfded8096d9bd1c28c.camel@espressif.com/mbox/"},{"id":7891,"url":"https://patchwork.plctlab.org/api/1.2/patches/7891/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/535b6208c1718b9acf3258575e1ebc0a65af9f07.camel@espressif.com/","msgid":"<535b6208c1718b9acf3258575e1ebc0a65af9f07.camel@espressif.com>","list_archive_url":null,"date":"2022-10-22T13:56:44","name":"[5/5] gdb: xtensa: add support for esp32, esp32s2, esp32s3 isa-modules","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/535b6208c1718b9acf3258575e1ebc0a65af9f07.camel@espressif.com/mbox/"},{"id":10456,"url":"https://patchwork.plctlab.org/api/1.2/patches/10456/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221025013347.68282-1-nelson@rivosinc.com/","msgid":"<20221025013347.68282-1-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-10-25T01:33:46","name":"[committed,1/2] RISC-V: Improve link time complexity.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221025013347.68282-1-nelson@rivosinc.com/mbox/"},{"id":10454,"url":"https://patchwork.plctlab.org/api/1.2/patches/10454/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221025013347.68282-2-nelson@rivosinc.com/","msgid":"<20221025013347.68282-2-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-10-25T01:33:47","name":"[committed,2/2] RISC-V: Should reset `again'\'' flag for _bfd_riscv_relax_pc.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221025013347.68282-2-nelson@rivosinc.com/mbox/"},{"id":10536,"url":"https://patchwork.plctlab.org/api/1.2/patches/10536/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/bb7b87e4-1893-5c86-4a14-92bafc818b03@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-25T07:24:56","name":"[v5,1/8] x86: constify parse_insn()'\''s input","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/bb7b87e4-1893-5c86-4a14-92bafc818b03@suse.com/mbox/"},{"id":10537,"url":"https://patchwork.plctlab.org/api/1.2/patches/10537/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b9273ae6-0218-54f8-5374-b265ed13b71a@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-25T07:25:26","name":"[v5,1/8] x86: introduce Pass2 insn attribute","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b9273ae6-0218-54f8-5374-b265ed13b71a@suse.com/mbox/"},{"id":10541,"url":"https://patchwork.plctlab.org/api/1.2/patches/10541/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7250dab9-e218-e6dd-4c74-23da9f611ab4@suse.com/","msgid":"<7250dab9-e218-e6dd-4c74-23da9f611ab4@suse.com>","list_archive_url":null,"date":"2022-10-25T07:26:11","name":"[v5,3/8] x86: re-work insn/suffix recognition","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7250dab9-e218-e6dd-4c74-23da9f611ab4@suse.com/mbox/"},{"id":10540,"url":"https://patchwork.plctlab.org/api/1.2/patches/10540/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/13fc630f-e116-0099-5c9e-2697df6519d7@suse.com/","msgid":"<13fc630f-e116-0099-5c9e-2697df6519d7@suse.com>","list_archive_url":null,"date":"2022-10-25T07:26:40","name":"[v5,4/8] ix86: don'\''t recognize/derive Q suffix in the common case","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/13fc630f-e116-0099-5c9e-2697df6519d7@suse.com/mbox/"},{"id":10543,"url":"https://patchwork.plctlab.org/api/1.2/patches/10543/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/74db429d-d203-eab8-4ae1-18b9ad416b02@suse.com/","msgid":"<74db429d-d203-eab8-4ae1-18b9ad416b02@suse.com>","list_archive_url":null,"date":"2022-10-25T07:27:11","name":"[v5,5/8] x86-64: allow HLE store of accumulator to absolute 32-bit address","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/74db429d-d203-eab8-4ae1-18b9ad416b02@suse.com/mbox/"},{"id":10542,"url":"https://patchwork.plctlab.org/api/1.2/patches/10542/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2e2f7841-de4e-b5de-e8d9-a47a6a4113c8@suse.com/","msgid":"<2e2f7841-de4e-b5de-e8d9-a47a6a4113c8@suse.com>","list_archive_url":null,"date":"2022-10-25T07:27:35","name":"[v5,6/8] x86: move bad-use-of-TLS-reloc check","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2e2f7841-de4e-b5de-e8d9-a47a6a4113c8@suse.com/mbox/"},{"id":10545,"url":"https://patchwork.plctlab.org/api/1.2/patches/10545/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/421bc96e-7591-6980-48e9-5af8c8b0775a@suse.com/","msgid":"<421bc96e-7591-6980-48e9-5af8c8b0775a@suse.com>","list_archive_url":null,"date":"2022-10-25T07:28:27","name":"[v5,7/8] x86: drop (now) stray IsString","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/421bc96e-7591-6980-48e9-5af8c8b0775a@suse.com/mbox/"},{"id":10546,"url":"https://patchwork.plctlab.org/api/1.2/patches/10546/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/06ff83d4-4633-a07b-70e5-a8e049981dd4@suse.com/","msgid":"<06ff83d4-4633-a07b-70e5-a8e049981dd4@suse.com>","list_archive_url":null,"date":"2022-10-25T07:29:18","name":"[v5,8/8] x86: further re-work insn/suffix recognition to also cover MOVSX","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/06ff83d4-4633-a07b-70e5-a8e049981dd4@suse.com/mbox/"},{"id":10777,"url":"https://patchwork.plctlab.org/api/1.2/patches/10777/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6a8e7a71acccd0efb9789dfb3edfa307e83bdaa1.1666702934.git.research_trasio@irq.a4lg.com/","msgid":"<6a8e7a71acccd0efb9789dfb3edfa307e83bdaa1.1666702934.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-25T13:04:02","name":"[RFC] RISC-V: Allocate \"various\" operand type","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6a8e7a71acccd0efb9789dfb3edfa307e83bdaa1.1666702934.git.research_trasio@irq.a4lg.com/mbox/"},{"id":11062,"url":"https://patchwork.plctlab.org/api/1.2/patches/11062/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jAhwbXhxJHL66v@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-26T05:07:19","name":"PR29720, objdump -S crashes if build-id is missing","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jAhwbXhxJHL66v@squeak.grove.modra.org/mbox/"},{"id":11063,"url":"https://patchwork.plctlab.org/api/1.2/patches/11063/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jAxD+NxpMIah6s@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-26T05:08:20","name":"som.c buffer overflow","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jAxD+NxpMIah6s@squeak.grove.modra.org/mbox/"},{"id":11064,"url":"https://patchwork.plctlab.org/api/1.2/patches/11064/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jBYw4lfRQfOZhi@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-26T05:10:59","name":"som.c reloc sanity checking","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jBYw4lfRQfOZhi@squeak.grove.modra.org/mbox/"},{"id":11080,"url":"https://patchwork.plctlab.org/api/1.2/patches/11080/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jY7hygm01PelCY@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-26T06:51:26","name":"segfault in objdump.c reloc_at","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jY7hygm01PelCY@squeak.grove.modra.org/mbox/"},{"id":11081,"url":"https://patchwork.plctlab.org/api/1.2/patches/11081/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jZWIeIvCCYm9/g@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-26T06:53:12","name":"Correct ELF reloc size sanity check","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jZWIeIvCCYm9/g@squeak.grove.modra.org/mbox/"},{"id":11082,"url":"https://patchwork.plctlab.org/api/1.2/patches/11082/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221026070009.3663574-1-ysato@users.sourceforge.jp/","msgid":"<20221026070009.3663574-1-ysato@users.sourceforge.jp>","list_archive_url":null,"date":"2022-10-26T07:00:09","name":"opcodes: RX fix invalid output.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221026070009.3663574-1-ysato@users.sourceforge.jp/mbox/"},{"id":11089,"url":"https://patchwork.plctlab.org/api/1.2/patches/11089/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jhW48kuVC8Ig2d@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-26T07:27:23","name":"buffer overflow in _bfd_XX_print_ce_compressed_pdata","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jhW48kuVC8Ig2d@squeak.grove.modra.org/mbox/"},{"id":11157,"url":"https://patchwork.plctlab.org/api/1.2/patches/11157/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c52dbd16-7e1b-c356-7a92-1ff089564ef7@suse.cz/","msgid":"","list_archive_url":null,"date":"2022-10-26T08:47:09","name":"tests: use canonical option name","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c52dbd16-7e1b-c356-7a92-1ff089564ef7@suse.cz/mbox/"},{"id":11526,"url":"https://patchwork.plctlab.org/api/1.2/patches/11526/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027031915.4013-1-lifang_xia@linux.alibaba.com/","msgid":"<20221027031915.4013-1-lifang_xia@linux.alibaba.com>","list_archive_url":null,"date":"2022-10-27T03:19:15","name":"[v2] RISC-V: Optimize relax of GP/call with max_alignment.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027031915.4013-1-lifang_xia@linux.alibaba.com/mbox/"},{"id":11619,"url":"https://patchwork.plctlab.org/api/1.2/patches/11619/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9df9d9e5bb4c7594b76c40613a349b4d2364e9c5.1666854355.git.research_trasio@irq.a4lg.com/","msgid":"<9df9d9e5bb4c7594b76c40613a349b4d2364e9c5.1666854355.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-27T07:06:01","name":"include: Define macro to ignore -Wdeprecated-declarations on GCC","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9df9d9e5bb4c7594b76c40613a349b4d2364e9c5.1666854355.git.research_trasio@irq.a4lg.com/mbox/"},{"id":11627,"url":"https://patchwork.plctlab.org/api/1.2/patches/11627/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1o06O9Pp8ncCsOw@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-27T07:36:08","name":"Fuzzed files in archives","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1o06O9Pp8ncCsOw@squeak.grove.modra.org/mbox/"},{"id":11658,"url":"https://patchwork.plctlab.org/api/1.2/patches/11658/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027084808.37252-1-nelson@rivosinc.com/","msgid":"<20221027084808.37252-1-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-10-27T08:48:08","name":"[committed] RISC-V: Fix build failures for -Werror=sign-compare.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027084808.37252-1-nelson@rivosinc.com/mbox/"},{"id":11921,"url":"https://patchwork.plctlab.org/api/1.2/patches/11921/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027190052.10536-1-mark@harmstone.com/","msgid":"<20221027190052.10536-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-27T19:00:51","name":"[1/2] ld: Add section header stream to PDB files","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027190052.10536-1-mark@harmstone.com/mbox/"},{"id":11922,"url":"https://patchwork.plctlab.org/api/1.2/patches/11922/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027190052.10536-2-mark@harmstone.com/","msgid":"<20221027190052.10536-2-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-27T19:00:52","name":"[2/2] ld: Add publics stream to PDB files","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027190052.10536-2-mark@harmstone.com/mbox/"},{"id":11965,"url":"https://patchwork.plctlab.org/api/1.2/patches/11965/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027202719.32497-1-palmer@rivosinc.com/","msgid":"<20221027202719.32497-1-palmer@rivosinc.com>","list_archive_url":null,"date":"2022-10-27T20:27:18","name":"[1/2] gas: NEWS: Add a missing newline","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027202719.32497-1-palmer@rivosinc.com/mbox/"},{"id":11966,"url":"https://patchwork.plctlab.org/api/1.2/patches/11966/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027202719.32497-2-palmer@rivosinc.com/","msgid":"<20221027202719.32497-2-palmer@rivosinc.com>","list_archive_url":null,"date":"2022-10-27T20:27:19","name":"[2/2] gas: NEWS: Note support for RISC-V Zawrs","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027202719.32497-2-palmer@rivosinc.com/mbox/"},{"id":12016,"url":"https://patchwork.plctlab.org/api/1.2/patches/12016/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/21ec9a18-fa89-0828-f625-499680022ec7@linux.ibm.com/","msgid":"<21ec9a18-fa89-0828-f625-499680022ec7@linux.ibm.com>","list_archive_url":null,"date":"2022-10-28T00:35:19","name":"[COMMITTED] PowerPC: Add support for RFC02653 - Dense Math Facility","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/21ec9a18-fa89-0828-f625-499680022ec7@linux.ibm.com/mbox/"},{"id":12017,"url":"https://patchwork.plctlab.org/api/1.2/patches/12017/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fd94047d-a070-45a6-3840-c105391718e0@linux.ibm.com/","msgid":"","list_archive_url":null,"date":"2022-10-28T00:37:18","name":"[COMMITTED] PowerPC: Add support for RFC02658 - MMA+ Outer-Product, Instructions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fd94047d-a070-45a6-3840-c105391718e0@linux.ibm.com/mbox/"},{"id":12122,"url":"https://patchwork.plctlab.org/api/1.2/patches/12122/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ac4f3f3c7115a824f73aca6935789b14d33c9a58.1666939920.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-28T06:53:02","name":"RISC-V: Fix build failure for -Werror=maybe-uninitialized","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ac4f3f3c7115a824f73aca6935789b14d33c9a58.1666939920.git.research_trasio@irq.a4lg.com/mbox/"},{"id":12181,"url":"https://patchwork.plctlab.org/api/1.2/patches/12181/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221028093840.19164-1-nelson@rivosinc.com/","msgid":"<20221028093840.19164-1-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-10-28T09:38:40","name":"RISC-V: Added SiFive custom cache control extensions.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221028093840.19164-1-nelson@rivosinc.com/mbox/"},{"id":12211,"url":"https://patchwork.plctlab.org/api/1.2/patches/12211/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4a280588-a85b-6ed3-634b-2b9cbc128f86@suse.com/","msgid":"<4a280588-a85b-6ed3-634b-2b9cbc128f86@suse.com>","list_archive_url":null,"date":"2022-10-28T10:06:35","name":"RISC-V/gas: fix build with certain gcc versions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4a280588-a85b-6ed3-634b-2b9cbc128f86@suse.com/mbox/"},{"id":12249,"url":"https://patchwork.plctlab.org/api/1.2/patches/12249/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/eb0e1bff-675e-72db-b8b1-b0f0e50b7121@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-28T12:35:35","name":"x86: minor improvements to optimize_imm() (part III)","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/eb0e1bff-675e-72db-b8b1-b0f0e50b7121@suse.com/mbox/"},{"id":12382,"url":"https://patchwork.plctlab.org/api/1.2/patches/12382/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/17f57574936af82be381a1451eac56b3709b60bb.1666968673.git.research_trasio@irq.a4lg.com/","msgid":"<17f57574936af82be381a1451eac56b3709b60bb.1666968673.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-28T14:52:12","name":"RISC-V: Emit mapping symbol with ISA string if non-default arch is used","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/17f57574936af82be381a1451eac56b3709b60bb.1666968673.git.research_trasio@irq.a4lg.com/mbox/"},{"id":12627,"url":"https://patchwork.plctlab.org/api/1.2/patches/12627/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221029034432.49859-1-nelson@rivosinc.com/","msgid":"<20221029034432.49859-1-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-10-29T03:44:32","name":"[committed] RISC-V: Always generate mapping symbols at the start of the sections.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221029034432.49859-1-nelson@rivosinc.com/mbox/"},{"id":12629,"url":"https://patchwork.plctlab.org/api/1.2/patches/12629/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1yxgzNJg5M48uPI@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-29T04:52:19","name":"NULL dereference read in som_write_object_contents","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1yxgzNJg5M48uPI@squeak.grove.modra.org/mbox/"},{"id":12630,"url":"https://patchwork.plctlab.org/api/1.2/patches/12630/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1yxnSHLY+FeB5DQ@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-29T04:52:45","name":"Fix small objcopy memory leak","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1yxnSHLY+FeB5DQ@squeak.grove.modra.org/mbox/"},{"id":12631,"url":"https://patchwork.plctlab.org/api/1.2/patches/12631/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1yxxfpJz+Jx4KTh@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-29T04:53:25","name":"pef: sanity check before malloc","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1yxxfpJz+Jx4KTh@squeak.grove.modra.org/mbox/"},{"id":12950,"url":"https://patchwork.plctlab.org/api/1.2/patches/12950/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-2-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-2-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:36","name":"[V3,01/15] sframe.h: Add SFrame format definition","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-2-indu.bhagat@oracle.com/mbox/"},{"id":12952,"url":"https://patchwork.plctlab.org/api/1.2/patches/12952/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-3-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-3-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:37","name":"[V3,02/15] gas: add new command line option --gsframe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-3-indu.bhagat@oracle.com/mbox/"},{"id":12951,"url":"https://patchwork.plctlab.org/api/1.2/patches/12951/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-4-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-4-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:38","name":"[V3,03/15] gas: generate .sframe from CFI directives","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-4-indu.bhagat@oracle.com/mbox/"},{"id":12956,"url":"https://patchwork.plctlab.org/api/1.2/patches/12956/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-5-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-5-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:39","name":"[V3,04/15] gas: testsuite: add new tests for SFrame unwind info","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-5-indu.bhagat@oracle.com/mbox/"},{"id":12955,"url":"https://patchwork.plctlab.org/api/1.2/patches/12955/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-6-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-6-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:40","name":"[V3,05/15] libsframe: add the SFrame library","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-6-indu.bhagat@oracle.com/mbox/"},{"id":12959,"url":"https://patchwork.plctlab.org/api/1.2/patches/12959/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-7-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-7-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:41","name":"[V3,06/15] bfd: linker: merge .sframe sections","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-7-indu.bhagat@oracle.com/mbox/"},{"id":12957,"url":"https://patchwork.plctlab.org/api/1.2/patches/12957/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-12-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-12-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:46","name":"[V3,11/15] libctf: add libsframe to LDFLAGS and LIBS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-12-indu.bhagat@oracle.com/mbox/"},{"id":12960,"url":"https://patchwork.plctlab.org/api/1.2/patches/12960/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-13-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-13-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:47","name":"[V3,12/15] src-release.sh: Add libsframe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-13-indu.bhagat@oracle.com/mbox/"},{"id":12953,"url":"https://patchwork.plctlab.org/api/1.2/patches/12953/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-14-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-14-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:48","name":"[V3,13/15] binutils/NEWS: add text for SFrame support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-14-indu.bhagat@oracle.com/mbox/"},{"id":12954,"url":"https://patchwork.plctlab.org/api/1.2/patches/12954/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-15-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-15-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:49","name":"[V3,14/15] gas/NEWS: add text about new command line option and SFrame support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-15-indu.bhagat@oracle.com/mbox/"},{"id":12958,"url":"https://patchwork.plctlab.org/api/1.2/patches/12958/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-16-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-16-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:50","name":"[V3,15/15] doc: add SFrame spec file","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-16-indu.bhagat@oracle.com/mbox/"}],"public":true,"mbox":"https://patchwork.plctlab.org/bundle/patchwork-bot/binutils-gdb_2022-10/mbox/"},{"id":7,"url":"https://patchwork.plctlab.org/api/1.2/bundles/7/","web_url":"https://patchwork.plctlab.org/bundle/patchwork-bot/binutils-gdb_2022-09/","project":{"id":2,"url":"https://patchwork.plctlab.org/api/1.2/projects/2/","name":"binutils-gdb","link_name":"binutils-gdb","list_id":"binutils.sourceware.org","list_email":"binutils@sourceware.org","web_url":"https://github.com/wangliu-iscas/Patchwork-Bundles/blob/main/binutils-gdb.md","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"name":"binutils-gdb_2022-09","owner":{"id":3,"url":"https://patchwork.plctlab.org/api/1.2/users/3/","username":"patchwork-bot","first_name":"","last_name":"","email":"ouuuleilei@gmail.com"},"patches":[{"id":1573,"url":"https://patchwork.plctlab.org/api/1.2/patches/1573/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930073211.2634-1-jiawei@iscas.ac.cn/","msgid":"<20220930073211.2634-1-jiawei@iscas.ac.cn>","list_archive_url":null,"date":"2022-09-30T07:32:11","name":"[V2] RISC-V: Add Smepmp CSR '\''mseccfg'\'' define and testcases.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930073211.2634-1-jiawei@iscas.ac.cn/mbox/"},{"id":1577,"url":"https://patchwork.plctlab.org/api/1.2/patches/1577/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/76fa0c3c-2303-ebdf-a765-ac4731581517@suse.com/","msgid":"<76fa0c3c-2303-ebdf-a765-ac4731581517@suse.com>","list_archive_url":null,"date":"2022-09-30T08:54:18","name":"objcopy: avoid \"shadowing\" of remove() function name","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/76fa0c3c-2303-ebdf-a765-ac4731581517@suse.com/mbox/"},{"id":1579,"url":"https://patchwork.plctlab.org/api/1.2/patches/1579/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930085852.71213-1-nelson@rivosinc.com/","msgid":"<20220930085852.71213-1-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-09-30T08:58:51","name":"[1/2] RISC-V: Output mapping symbols with ISA string.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930085852.71213-1-nelson@rivosinc.com/mbox/"},{"id":1578,"url":"https://patchwork.plctlab.org/api/1.2/patches/1578/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930085852.71213-2-nelson@rivosinc.com/","msgid":"<20220930085852.71213-2-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-09-30T08:58:52","name":"[2/2] RISC-V: Refer mapping symbol to R_RISCV_RELAX for rvc relaxations.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930085852.71213-2-nelson@rivosinc.com/mbox/"},{"id":1581,"url":"https://patchwork.plctlab.org/api/1.2/patches/1581/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930092058.71286-1-nelson@rivosinc.com/","msgid":"<20220930092058.71286-1-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-09-30T09:20:57","name":"[1/2] RISC-V: Output mapping symbols with ISA string.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930092058.71286-1-nelson@rivosinc.com/mbox/"},{"id":1580,"url":"https://patchwork.plctlab.org/api/1.2/patches/1580/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930092058.71286-2-nelson@rivosinc.com/","msgid":"<20220930092058.71286-2-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-09-30T09:20:58","name":"[2/2] RISC-V: Refer mapping symbol to R_RISCV_RELAX for rvc relaxations.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930092058.71286-2-nelson@rivosinc.com/mbox/"},{"id":1582,"url":"https://patchwork.plctlab.org/api/1.2/patches/1582/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5874dd79-0cf5-d65c-7ea2-13adfc799c0f@suse.com/","msgid":"<5874dd79-0cf5-d65c-7ea2-13adfc799c0f@suse.com>","list_archive_url":null,"date":"2022-09-30T09:41:29","name":"RISC-V: fix build after \"Add support for arbitrary immediate encoding formats\"","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5874dd79-0cf5-d65c-7ea2-13adfc799c0f@suse.com/mbox/"},{"id":1583,"url":"https://patchwork.plctlab.org/api/1.2/patches/1583/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/57d8ac2a-5757-3776-9924-99c17ca69938@suse.com/","msgid":"<57d8ac2a-5757-3776-9924-99c17ca69938@suse.com>","list_archive_url":null,"date":"2022-09-30T09:42:08","name":"RISC-V: fallout from \"re-arrange opcode table for consistent alias handling\"","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/57d8ac2a-5757-3776-9924-99c17ca69938@suse.com/mbox/"},{"id":1584,"url":"https://patchwork.plctlab.org/api/1.2/patches/1584/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e76ef8f7-72b9-5103-cb43-9608af01d017@suse.com/","msgid":"","list_archive_url":null,"date":"2022-09-30T09:42:50","name":"RISC-V: don'\''t cast expressions'\'' X_add_number to long in diagnostics","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e76ef8f7-72b9-5103-cb43-9608af01d017@suse.com/mbox/"},{"id":1585,"url":"https://patchwork.plctlab.org/api/1.2/patches/1585/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/61355429-24b3-17d0-ab03-6fa57ee861d5@suse.cz/","msgid":"<61355429-24b3-17d0-ab03-6fa57ee861d5@suse.cz>","list_archive_url":null,"date":"2022-09-30T09:48:52","name":"[RFC] add --enable-zstd-compressed-debug-sections configure option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/61355429-24b3-17d0-ab03-6fa57ee861d5@suse.cz/mbox/"},{"id":1586,"url":"https://patchwork.plctlab.org/api/1.2/patches/1586/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930103919.323690-1-christoph.muellner@vrull.eu/","msgid":"<20220930103919.323690-1-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2022-09-30T10:39:19","name":"RISC-V: Eliminate long-casts of X_add_number in diagnostics","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930103919.323690-1-christoph.muellner@vrull.eu/mbox/"},{"id":1590,"url":"https://patchwork.plctlab.org/api/1.2/patches/1590/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/DM6PR12MB4219C943049C6D883DEA3E55E7569@DM6PR12MB4219.namprd12.prod.outlook.com/","msgid":"","list_archive_url":null,"date":"2022-09-30T11:41:37","name":"[V2] Ignore DWARF debug information for -gsplit-dwarf with dwarf-5.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/DM6PR12MB4219C943049C6D883DEA3E55E7569@DM6PR12MB4219.namprd12.prod.outlook.com/mbox/"},{"id":1591,"url":"https://patchwork.plctlab.org/api/1.2/patches/1591/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c10321f9-d289-ef84-d263-bc278fb3d31b@suse.com/","msgid":"","list_archive_url":null,"date":"2022-09-30T11:59:04","name":"[1/4] RISC-V/gas: drop riscv_subsets static variable","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c10321f9-d289-ef84-d263-bc278fb3d31b@suse.com/mbox/"},{"id":1593,"url":"https://patchwork.plctlab.org/api/1.2/patches/1593/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3244eea0-c18c-e49a-4588-d69423130226@suse.com/","msgid":"<3244eea0-c18c-e49a-4588-d69423130226@suse.com>","list_archive_url":null,"date":"2022-09-30T11:59:23","name":"[2/4] RISC-V/gas: drop stray call to install_insn()","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3244eea0-c18c-e49a-4588-d69423130226@suse.com/mbox/"},{"id":1592,"url":"https://patchwork.plctlab.org/api/1.2/patches/1592/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/385d01fd-7e57-1f3f-1bae-30aa0c313d63@suse.com/","msgid":"<385d01fd-7e57-1f3f-1bae-30aa0c313d63@suse.com>","list_archive_url":null,"date":"2022-09-30T11:59:45","name":"[3/4] RISC-V/gas: don'\''t open-code insn_length()","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/385d01fd-7e57-1f3f-1bae-30aa0c313d63@suse.com/mbox/"},{"id":1594,"url":"https://patchwork.plctlab.org/api/1.2/patches/1594/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f5757acf-7b90-a0e3-5eea-3b97cc226930@suse.com/","msgid":"","list_archive_url":null,"date":"2022-09-30T12:00:12","name":"[4/4] RISC-V/gas: allow generating up to 176-bit instructions with .insn","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f5757acf-7b90-a0e3-5eea-3b97cc226930@suse.com/mbox/"},{"id":1596,"url":"https://patchwork.plctlab.org/api/1.2/patches/1596/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930140503.38233-1-chigot@adacore.com/","msgid":"<20220930140503.38233-1-chigot@adacore.com>","list_archive_url":null,"date":"2022-09-30T14:05:03","name":"ld/testsuite: consistently add board_ldflags when linking with GCC","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930140503.38233-1-chigot@adacore.com/mbox/"}],"public":true,"mbox":"https://patchwork.plctlab.org/bundle/patchwork-bot/binutils-gdb_2022-09/mbox/"}]' + bundle_id=6 + git-pw bundle add 6 12961 +------------+-----------------------------------------------------------------------------------------+ | Property | Value | |------------+-----------------------------------------------------------------------------------------| | ID | 6 | | Name | binutils-gdb_2022-10 | | URL | https://patchwork.plctlab.org/bundle/patchwork-bot/binutils-gdb_2022-10/ | | Owner | patchwork-bot | | Project | binutils-gdb | | Public | True | | Patches | 1592 [3/4] RISC-V/gas: don't open-code insn_length() | | | 1594 [4/4] RISC-V/gas: allow generating up to 176-bit instructions with .insn | | | 1596 ld/testsuite: consistently add board_ldflags when linking with GCC | | | 1619 gold, dwp: support zstd compressed input debug sections [PR 29641] | | | 1620 gold: add --compress-debug-sections=zstd [PR 29641] | | | 1623 [RFC,1/1] RISC-V: Implement common register pair framework | | | 1625 [RFC,1/1] RISC-V: Implement extension variants | | | 1626 [1/1] RISC-V: Move supervisor instructions after all unprivileged ones | | | 1627 readelf: support zstd compressed debug sections [PR 29640] | | | 1631 [PATCHv2,2/2] opcodes/arm: add disassembler styling for arm | | | 1635 diagnostics.h: GCC 13 got -Wself-move, breaks GDB build | | | 1637 [1/2] ld: Add --pdb option | | | 1638 [2/2] ld: Add minimal pdb generation | | | 1640 [1/2] refactor usage of compressed_debug_section_type | | | 1641 [2/2] add --enable-default-compressed-debug-sections-algorithm configure option | | | 1642 opcodes/riscv: style csr names as registers | | | 1643 [v3,1/6] RISC-V: Fix immediates to have "immediate" style | | | 1644 [v3,2/6] RISC-V: Fix printf argument types corresponding %x | | | 1647 [v3,3/6] RISC-V: Optimize riscv_disassemble_data printf | | | 1646 [v3,4/6] RISC-V: Print comma and tabs as the "text" style | | | 1648 [v3,5/6] RISC-V: Fix T-Head immediate types on printing | | | 1649 [v3,6/6] RISC-V: Print XTheadMemPair literal as "immediate" | | | 1656 Commit: readelf: Do not load section data from offset 0 | | | 1659 [PATCHv2,1/2] opcodes/arm: use '@' consistently for the comment character | | | 1660 gas: NEWS: Mention the T-Head extensions that were recently added | | | 1671 Support objcopy changing compression to or from zstd | | | 1673 [1/2] RISC-V: Fix buffer overflow on print_insn_riscv | | | 1672 [2/2] gdb/riscv: Fix buffer overflow on riscv_insn::fetch_instruction | | | 1676 [v2,1/2] RISC-V: Fix buffer overflow on print_insn_riscv | | | 1677 [v2,2/2] gdb/riscv: Partial support for instructions up to 176-bits | | | 1678 [v3,1/2] RISC-V: Fix buffer overflow on print_insn_riscv | | | 1679 [v3,2/2] gdb/riscv: Partial support for instructions up to 176-bit | | | 1681 RISC-V: Zicbo{m,p,z} adjustments to riscv_multi_subset_supports_ext() | | | 1690 gprofng: fix build with --enable-pgo-build=lto | | | 1691 bfd: xtensa: fix __stop_SECTION literal drop, | | | 1702 [RFC] bfd: use bfd_vma for the 64-bit version of put[lb] and get[lb] | | | 1711 PR29647, objdump -S looping | | | 1712 [v3,1/7] x86: constify parse_insn()'s input | | | 1713 [v3,2/7] x86: introduce Pass2 insn attribute | | | 1714 [v3,3/7] x86: re-work insn/suffix recognition | | | 1715 [v3,4/7] x86-64: further re-work insn/suffix recognition to also cover MOVSL | | | 1716 [v3,5/7] ix86: don't recognize/derive Q suffix in the common case | | | 1718 [v3,6/7] x86-64: allow HLE store of accumulator to absolute 32-bit address | | | 1717 [v3,7/7] x86: move bad-use-of-TLS-reloc check | | | 1719 x86: drop "regmask" static variable | | | 1751 [v2,1/2] RISC-V: Fallback for instructions longer than 64b | | | 1752 [v2,2/2] RISC-V: Improve "bits undefined" diagnostics | | | 1776 [v3,1/2] RISC-V: Fallback for instructions longer than 64b | | | 1777 [v3,2/2] RISC-V: Improve "bits undefined" diagnostics | | | 1781 RISC-V: fix linker message when relaxation deletes bytes | | | 1801 PR29653, objcopy/strip: fuzzed small input file induces large output file | | | 1803 @CPP_FOR_BUILD@ problem since binutils-2.38 | | | 1827 [v2,1/1] RISC-V: Test DWARF register numbers for "fp" | | | 1828 [1/1] RISC-V: Move standard hints before all instructions | | | 1829 [RFC,1/1] RISC-V: Imply 'Zicsr' from privileged extensions with CSRs | | | 1830 [1/5] opcodes/riscv-dis.c: Tidying with comments/clarity | | | 1832 [2/5] opcodes/riscv-dis.c: Tidying with spacing | | | 1831 [3/5] opcodes/riscv-dis.c: Use bool type whenever possible | | | 1833 [4/5] opcodes/riscv-dis.c: Make XLEN variable static | | | 1834 [5/5] opcodes/riscv-dis.c: Remove last_map_state | | | 1836 RISC-V: Move certain arrays to riscv-opc.c | | | 1844 [v2,1/2] ld: Add --pdb option | | | 1845 [v2,2/2] ld: Add minimal pdb generation | | | 1890 gprofng: run tests without installation | | | 1893 [2/2] gprofng: use the --libdir path to find libraries | | | 1894 [3/3] gprofng: no need to build version.texi | | | 1895 [v3,1/2] ld: Add --pdb option | | | 1897 [v3,2/2] ld: Add minimal pdb generation | | | 1928 [v4,1/2] ld: Add --pdb option | | | 1929 [v4,2/2] ld: Add minimal pdb generation | | | 1941 [pushed] Re-apply "Pass PKG_CONFIG_PATH down from top-level Makefile" | | | 1976 [v4,1/8] x86: constify parse_insn()'s input | | | 1977 [v4,2/8] x86: introduce Pass2 insn attribute | | | 1978 [v4,3/8] x86: re-work insn/suffix recognition | | | 1979 [v4,4/8] x86-64: further re-work insn/suffix recognition to also cover MOVSL | | | 1980 [v4,5/8] ix86: don't recognize/derive Q suffix in the common case | | | 1981 [v4,6/8] x86-64: allow HLE store of accumulator to absolute 32-bit address | | | 1982 [v4,7/8] x86: move bad-use-of-TLS-reloc check | | | 1983 [v4,8/8] x86: drop (now) stray IsString | | | 2013 include: Declare getopt function on old GNU libc | | | 2352 ld: Add --undefined-version | | | 2532 [1/1] RISC-V: Make R_RISCV_SUB6 conforms to riscv abi standard | | | 2560 [v3] aarch64-pe support for LD, GAS and BFD | | | 2602 [01/10] Support Intel AVX-IFMA | | | 2608 [02/10] Support Intel AVX-VNNI-INT8 | | | 2611 [03/10] Support Intel AVX-NE-CONVERT | | | 2610 [04/10] Support Intel CMPccXADD | | | 2601 [05/10] Add handler for more i386_cpu_flags | | | 2606 [06/10] Support Intel RAO-INT | | | 2609 [07/10] Support Intel WRMSRNS | | | 2605 [08/10] Support Intel MSRLIST | | | 2607 [09/10] Support Intel AMX-FP16 | | | 2604 [10/10] Support Intel PREFETCHI | | | 2643 x86: fold AVX512-VNNI disassembler entries with AVX-VNNI ones | | | 2654 PR29677, Field `the_bfd` of `asymbol` is uninitialised | | | 2656 e200 LSP support | | | 2657 PowerPC SPE disassembly and tests | | | 2695 Binutils: Adding new testcase for addr2line. | | | 2700 x86: properly decode EVEX.W for AVX512_4{FMAPS,VNNIW} insns | | | 2981 PowerPC se_rfmci and VLE, SPE2 and LSP insns with -many | | | 3152 [v5,1/2] ld: Add --pdb option | | | 3151 [v5,2/2] ld: Add minimal pdb generation | | | 3258 x86: correct CPU_AMX_{BF16,INT8}_FLAGS | | | 3272 x86: generalize gas documentation for disabling of ISA extensions | | | 3759 [V2,01/15] sframe.h: Add SFrame format definition | | | 3762 [V2,02/15] gas: add new command line option --gsframe | | | 3761 [V2,03/15] gas: generate .sframe from CFI directives | | | 3760 [V2,04/15] gas: testsuite: add new tests for SFrame unwind info | | | 3764 [V2,05/15] libsframe: add the SFrame library | | | 3766 [V2,06/15] bfd: linker: merge .sframe sections | | | 3763 [V2,07/15] readelf/objdump: support for SFrame section | | | 3765 [V2,08/15] unwinder: generate backtrace using SFrame format | | | 3770 [V2,09/15] unwinder: Add SFrame unwinder tests | | | 3769 [V2,10/15] gdb: sim: buildsystem changes to accommodate libsframe | | | 3771 [V2,11/15] libctf: add libsframe to LDFLAGS and LIBS | | | 3768 [V2,12/15] src-release.sh: Add libsframe | | | 3767 [V2,13/15] binutils/NEWS: add text for SFrame support | | | 3772 [V2,14/15] gas/NEWS: add text about new command line option and SFrame support | | | 3773 [V2,15/15] doc: add SFrame spec file | | | 3999 [1/1] IBM zSystems: Issue error for *DBL relocs on misaligned symbols | | | 4141 xtensa: use definitions from xtensa-config.h | | | 4272 x86: Disable AVX-VNNI when disabling AVX2 | | | 4998 x86: re-work AVX-VNNI support | | | 5276 Fix addr2line test for ppc64 elfv1 and mingw | | | 5424 binutils: Remove unused substitution PROGRAM | | | 5433 [v2,1/8] RISC-V: Add a space at the end of pinfo | | | 5435 [v2,2/8] RISC-V: Fix obvious misalignments ('Zbb'/'Zba') | | | 5437 [v2,3/8] RISC-V: Remove spaces in opcode entries | | | 5436 [v2,4/8] RISC-V: Remove unused instruction macros | | | 5440 [v2,5/8] RISC-V: Complete tidying up with SCALL and SBREAK | | | 5442 [v2,6/8] RISC-V: Tidying up with fmv.w.x and fmv.x.w | | | 5438 [v2,7/8] RISC-V: Make alias instructions aliases | | | 5441 [v2,8/8] RISC-V: Use defined mask and match values | | | 5439 RISC-V: Remove RV32EF conflict | | | 5616 [04/10] Support Intel CMPccXADD | | | 5614 [05/10] Add handler for more i386_cpu_flags | | | 5672 [01/10] Support Intel AVX-IFMA | | | 5691 [02/10] Support Intel AVX-VNNI-INT8 | | | 5690 [03/10] Support Intel AVX-NE-CONVERT | | | 5689 [04/10] Support Intel CMPccXADD | | | 5676 [05/10] Add handler for more i386_cpu_flags | | | 5677 [06/10] Support Intel RAO-INT | | | 5681 [07/10] Support Intel WRMSRNS | | | 5682 [08/10] Support Intel MSRLIST | | | 5673 [09/10] Support Intel AMX-FP16 | | | 5686 [10/10] Support Intel PREFETCHI | | | 5940 Obsolete beos | | | 6080 [01/40] gdb/unittests: PR28413, suppress warnings generated by Gnulib | | | 6081 [02/40] sim: Check known getrusage declaration existence | | | 6083 [03/40] sim/aarch64: Remove unused functions | | | 6084 [04/40] cpu/cris: Initialize some variables on CRIS CPU | | | 6082 [05/40] cpu/cris: Add u-stall virtual unit to CRIS v32 | | | 6087 [06/40] sim/cris: Move declarations of f_specific_init | | | 6091 [07/40] sim/cris: Regenerate with CGEN | | | 6085 [08/40] sim/erc32: Insert void parameter | | | 6086 [09/40] sim/erc32: Use int32_t as event callback argument | | | 6090 [10/40] sim/erc32: Use int32_t as IRQ callback argument | | | 6089 [11/40] cpu/frv: Initialize some variables | | | 6088 [12/40] sim/frv: Initialize nesr variable | | | 6093 [13/40] sim/frv: Initialize some variables | | | 6092 [14/40] sim/frv: Add explicit casts | | | 6095 [15/40] sim/h8300: Add "+ 0x0" to avoid self-assignments | | | 6101 [16/40] sim/lm32: fix some missing function declaration warnings | | | 6094 [17/40] sim/lm32: Add explicit casts | | | 6141 [1/3] x86: emit {evex} prefix when disassembling ambiguous AVX512VL insns | | | 6143 [2/3] x86: consolidate VAES tests | | | 6142 [3/3] x86: consolidate VPCLMUL tests | | | 6228 x86-64: Use only one default max-page-size | | | 6229 [1/2] ld/testsuite: skip ld-elf/exclude when -shared is not supported | | | 6230 [2/2] ld/testsuite: adjust ld-arm to run shared tests only when supported | | | 6236 [RFC,top-level] Add configure test-case | | | 6286 x86: Check VEX/EVEX encoding before checking vector operands | | | 7884 [1/5] bfd: xtensa: move common code from ld and gas | | | 7885 [2/5] gas: xtensa: add endianness, loops, booleans options | | | 7886 [3/5] ld: xtensa: use default LD command line options for endianness | | | 7891 [5/5] gdb: xtensa: add support for esp32, esp32s2, esp32s3 isa-modules | | | 10456 [committed,1/2] RISC-V: Improve link time complexity. | | | 10454 [committed,2/2] RISC-V: Should reset `again' flag for _bfd_riscv_relax_pc. | | | 10536 [v5,1/8] x86: constify parse_insn()'s input | | | 10537 [v5,1/8] x86: introduce Pass2 insn attribute | | | 10541 [v5,3/8] x86: re-work insn/suffix recognition | | | 10540 [v5,4/8] ix86: don't recognize/derive Q suffix in the common case | | | 10543 [v5,5/8] x86-64: allow HLE store of accumulator to absolute 32-bit address | | | 10542 [v5,6/8] x86: move bad-use-of-TLS-reloc check | | | 10545 [v5,7/8] x86: drop (now) stray IsString | | | 10546 [v5,8/8] x86: further re-work insn/suffix recognition to also cover MOVSX | | | 10777 [RFC] RISC-V: Allocate "various" operand type | | | 11062 PR29720, objdump -S crashes if build-id is missing | | | 11063 som.c buffer overflow | | | 11064 som.c reloc sanity checking | | | 11080 segfault in objdump.c reloc_at | | | 11081 Correct ELF reloc size sanity check | | | 11082 opcodes: RX fix invalid output. | | | 11089 buffer overflow in _bfd_XX_print_ce_compressed_pdata | | | 11157 tests: use canonical option name | | | 11526 [v2] RISC-V: Optimize relax of GP/call with max_alignment. | | | 11619 include: Define macro to ignore -Wdeprecated-declarations on GCC | | | 11627 Fuzzed files in archives | | | 11658 [committed] RISC-V: Fix build failures for -Werror=sign-compare. | | | 11921 [1/2] ld: Add section header stream to PDB files | | | 11922 [2/2] ld: Add publics stream to PDB files | | | 11965 [1/2] gas: NEWS: Add a missing newline | | | 11966 [2/2] gas: NEWS: Note support for RISC-V Zawrs | | | 12016 [COMMITTED] PowerPC: Add support for RFC02653 - Dense Math Facility | | | 12017 [COMMITTED] PowerPC: Add support for RFC02658 - MMA+ Outer-Product, Instructions | | | 12122 RISC-V: Fix build failure for -Werror=maybe-uninitialized | | | 12181 RISC-V: Added SiFive custom cache control extensions. | | | 12211 RISC-V/gas: fix build with certain gcc versions | | | 12249 x86: minor improvements to optimize_imm() (part III) | | | 12382 RISC-V: Emit mapping symbol with ISA string if non-default arch is used | | | 12627 [committed] RISC-V: Always generate mapping symbols at the start of the sections. | | | 12629 NULL dereference read in som_write_object_contents | | | 12630 Fix small objcopy memory leak | | | 12631 pef: sanity check before malloc | | | 12950 [V3,01/15] sframe.h: Add SFrame format definition | | | 12952 [V3,02/15] gas: add new command line option --gsframe | | | 12951 [V3,03/15] gas: generate .sframe from CFI directives | | | 12956 [V3,04/15] gas: testsuite: add new tests for SFrame unwind info | | | 12955 [V3,05/15] libsframe: add the SFrame library | | | 12959 [V3,06/15] bfd: linker: merge .sframe sections | | | 12961 [V3,07/15] readelf/objdump: support for SFrame section | | | 12957 [V3,11/15] libctf: add libsframe to LDFLAGS and LIBS | | | 12960 [V3,12/15] src-release.sh: Add libsframe | | | 12953 [V3,13/15] binutils/NEWS: add text for SFrame support | | | 12954 [V3,14/15] gas/NEWS: add text about new command line option and SFrame support | | | 12958 [V3,15/15] doc: add SFrame spec file | +------------+-----------------------------------------------------------------------------------------+ + git config pull.rebase false + git fetch origin master From github.com:wangliu-iscas/binutils-gdb * branch master -> FETCH_HEAD + git checkout master Switched to a new branch 'master' branch 'master' set up to track 'origin/master'. + git pull origin master From github.com:wangliu-iscas/binutils-gdb * branch master -> FETCH_HEAD Already up to date. + git fetch origin upstream-master From github.com:wangliu-iscas/binutils-gdb * branch upstream-master -> FETCH_HEAD + git checkout upstream-master Switched to a new branch 'upstream-master' branch 'upstream-master' set up to track 'origin/upstream-master'. + git remote add upstream https://sourceware.org/git/binutils-gdb.git + git pull upstream master From https://sourceware.org/git/binutils-gdb * branch master -> FETCH_HEAD * [new branch] master -> upstream/master Already up to date. + git push -u origin upstream-master Everything up-to-date branch 'upstream-master' set up to track 'origin/upstream-master'. + git checkout master Switched to branch 'master' Your branch is up to date with 'origin/master'. + git merge upstream-master Already up to date. + git push -u origin master Everything up-to-date branch 'master' set up to track 'origin/master'. + branchname=series4870-patch12961 ++ git branch -a ++ grep 'series4870-patch12961$' + checkbranch= + checkbranchresult=null + '[' null = series4870-patch12961 ']' + git checkout -b series4870-patch12961 Switched to a new branch 'series4870-patch12961' ++ curl https://patchwork.plctlab.org/api/1.2/series/4870/ % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 8734 100 8734 0 0 189k 0 --:--:-- --:--:-- --:--:-- 189k + series_response='{"id":4870,"url":"https://patchwork.plctlab.org/api/1.2/series/4870/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/list/?series=4870","project":{"id":2,"url":"https://patchwork.plctlab.org/api/1.2/projects/2/","name":"binutils-gdb","link_name":"binutils-gdb","list_id":"binutils.sourceware.org","list_email":"binutils@sourceware.org","web_url":"https://github.com/wangliu-iscas/Patchwork-Bundles/blob/main/binutils-gdb.md","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"name":"Definition and support for SFrame unwind format","date":"2022-10-30T07:44:35","submitter":{"id":35,"url":"https://patchwork.plctlab.org/api/1.2/people/35/","name":"Indu Bhagat","email":"indu.bhagat@oracle.com"},"version":3,"total":15,"received_total":15,"received_all":true,"mbox":"https://patchwork.plctlab.org/series/4870/mbox/","cover_letter":{"id":883,"url":"https://patchwork.plctlab.org/api/1.2/covers/883/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/cover/20221030074450.1956074-1-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-1-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:35","name":"[V3,00/15] Definition and support for SFrame unwind format","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/cover/20221030074450.1956074-1-indu.bhagat@oracle.com/mbox/"},"patches":[{"id":12950,"url":"https://patchwork.plctlab.org/api/1.2/patches/12950/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-2-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-2-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:36","name":"[V3,01/15] sframe.h: Add SFrame format definition","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-2-indu.bhagat@oracle.com/mbox/"},{"id":12952,"url":"https://patchwork.plctlab.org/api/1.2/patches/12952/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-3-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-3-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:37","name":"[V3,02/15] gas: add new command line option --gsframe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-3-indu.bhagat@oracle.com/mbox/"},{"id":12951,"url":"https://patchwork.plctlab.org/api/1.2/patches/12951/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-4-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-4-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:38","name":"[V3,03/15] gas: generate .sframe from CFI directives","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-4-indu.bhagat@oracle.com/mbox/"},{"id":12956,"url":"https://patchwork.plctlab.org/api/1.2/patches/12956/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-5-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-5-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:39","name":"[V3,04/15] gas: testsuite: add new tests for SFrame unwind info","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-5-indu.bhagat@oracle.com/mbox/"},{"id":12955,"url":"https://patchwork.plctlab.org/api/1.2/patches/12955/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-6-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-6-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:40","name":"[V3,05/15] libsframe: add the SFrame library","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-6-indu.bhagat@oracle.com/mbox/"},{"id":12959,"url":"https://patchwork.plctlab.org/api/1.2/patches/12959/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-7-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-7-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:41","name":"[V3,06/15] bfd: linker: merge .sframe sections","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-7-indu.bhagat@oracle.com/mbox/"},{"id":12961,"url":"https://patchwork.plctlab.org/api/1.2/patches/12961/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-8-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-8-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:42","name":"[V3,07/15] readelf/objdump: support for SFrame section","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-8-indu.bhagat@oracle.com/mbox/"},{"id":12962,"url":"https://patchwork.plctlab.org/api/1.2/patches/12962/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-9-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-9-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:43","name":"[V3,08/15] unwinder: generate backtrace using SFrame format","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-9-indu.bhagat@oracle.com/mbox/"},{"id":12963,"url":"https://patchwork.plctlab.org/api/1.2/patches/12963/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-10-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-10-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:44","name":"[V3,09/15] unwinder: Add SFrame unwinder tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-10-indu.bhagat@oracle.com/mbox/"},{"id":12964,"url":"https://patchwork.plctlab.org/api/1.2/patches/12964/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-11-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-11-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:45","name":"[V3,10/15] gdb: sim: buildsystem changes to accommodate libsframe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-11-indu.bhagat@oracle.com/mbox/"},{"id":12957,"url":"https://patchwork.plctlab.org/api/1.2/patches/12957/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-12-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-12-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:46","name":"[V3,11/15] libctf: add libsframe to LDFLAGS and LIBS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-12-indu.bhagat@oracle.com/mbox/"},{"id":12960,"url":"https://patchwork.plctlab.org/api/1.2/patches/12960/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-13-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-13-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:47","name":"[V3,12/15] src-release.sh: Add libsframe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-13-indu.bhagat@oracle.com/mbox/"},{"id":12953,"url":"https://patchwork.plctlab.org/api/1.2/patches/12953/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-14-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-14-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:48","name":"[V3,13/15] binutils/NEWS: add text for SFrame support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-14-indu.bhagat@oracle.com/mbox/"},{"id":12954,"url":"https://patchwork.plctlab.org/api/1.2/patches/12954/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-15-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-15-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:49","name":"[V3,14/15] gas/NEWS: add text about new command line option and SFrame support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-15-indu.bhagat@oracle.com/mbox/"},{"id":12958,"url":"https://patchwork.plctlab.org/api/1.2/patches/12958/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-16-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-16-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:50","name":"[V3,15/15] doc: add SFrame spec file","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-16-indu.bhagat@oracle.com/mbox/"}]}' ++ jq '.patches[] | (.id|tostring) + "," + .mbox' ++ echo '{"id":4870,"url":"https://patchwork.plctlab.org/api/1.2/series/4870/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/list/?series=4870","project":{"id":2,"url":"https://patchwork.plctlab.org/api/1.2/projects/2/","name":"binutils-gdb","link_name":"binutils-gdb","list_id":"binutils.sourceware.org","list_email":"binutils@sourceware.org","web_url":"https://github.com/wangliu-iscas/Patchwork-Bundles/blob/main/binutils-gdb.md","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"name":"Definition and support for SFrame unwind format","date":"2022-10-30T07:44:35","submitter":{"id":35,"url":"https://patchwork.plctlab.org/api/1.2/people/35/","name":"Indu Bhagat","email":"indu.bhagat@oracle.com"},"version":3,"total":15,"received_total":15,"received_all":true,"mbox":"https://patchwork.plctlab.org/series/4870/mbox/","cover_letter":{"id":883,"url":"https://patchwork.plctlab.org/api/1.2/covers/883/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/cover/20221030074450.1956074-1-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-1-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:35","name":"[V3,00/15] Definition and support for SFrame unwind format","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/cover/20221030074450.1956074-1-indu.bhagat@oracle.com/mbox/"},"patches":[{"id":12950,"url":"https://patchwork.plctlab.org/api/1.2/patches/12950/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-2-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-2-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:36","name":"[V3,01/15] sframe.h: Add SFrame format definition","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-2-indu.bhagat@oracle.com/mbox/"},{"id":12952,"url":"https://patchwork.plctlab.org/api/1.2/patches/12952/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-3-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-3-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:37","name":"[V3,02/15] gas: add new command line option --gsframe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-3-indu.bhagat@oracle.com/mbox/"},{"id":12951,"url":"https://patchwork.plctlab.org/api/1.2/patches/12951/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-4-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-4-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:38","name":"[V3,03/15] gas: generate .sframe from CFI directives","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-4-indu.bhagat@oracle.com/mbox/"},{"id":12956,"url":"https://patchwork.plctlab.org/api/1.2/patches/12956/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-5-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-5-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:39","name":"[V3,04/15] gas: testsuite: add new tests for SFrame unwind info","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-5-indu.bhagat@oracle.com/mbox/"},{"id":12955,"url":"https://patchwork.plctlab.org/api/1.2/patches/12955/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-6-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-6-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:40","name":"[V3,05/15] libsframe: add the SFrame library","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-6-indu.bhagat@oracle.com/mbox/"},{"id":12959,"url":"https://patchwork.plctlab.org/api/1.2/patches/12959/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-7-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-7-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:41","name":"[V3,06/15] bfd: linker: merge .sframe sections","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-7-indu.bhagat@oracle.com/mbox/"},{"id":12961,"url":"https://patchwork.plctlab.org/api/1.2/patches/12961/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-8-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-8-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:42","name":"[V3,07/15] readelf/objdump: support for SFrame section","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-8-indu.bhagat@oracle.com/mbox/"},{"id":12962,"url":"https://patchwork.plctlab.org/api/1.2/patches/12962/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-9-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-9-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:43","name":"[V3,08/15] unwinder: generate backtrace using SFrame format","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-9-indu.bhagat@oracle.com/mbox/"},{"id":12963,"url":"https://patchwork.plctlab.org/api/1.2/patches/12963/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-10-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-10-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:44","name":"[V3,09/15] unwinder: Add SFrame unwinder tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-10-indu.bhagat@oracle.com/mbox/"},{"id":12964,"url":"https://patchwork.plctlab.org/api/1.2/patches/12964/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-11-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-11-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:45","name":"[V3,10/15] gdb: sim: buildsystem changes to accommodate libsframe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-11-indu.bhagat@oracle.com/mbox/"},{"id":12957,"url":"https://patchwork.plctlab.org/api/1.2/patches/12957/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-12-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-12-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:46","name":"[V3,11/15] libctf: add libsframe to LDFLAGS and LIBS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-12-indu.bhagat@oracle.com/mbox/"},{"id":12960,"url":"https://patchwork.plctlab.org/api/1.2/patches/12960/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-13-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-13-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:47","name":"[V3,12/15] src-release.sh: Add libsframe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-13-indu.bhagat@oracle.com/mbox/"},{"id":12953,"url":"https://patchwork.plctlab.org/api/1.2/patches/12953/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-14-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-14-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:48","name":"[V3,13/15] binutils/NEWS: add text for SFrame support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-14-indu.bhagat@oracle.com/mbox/"},{"id":12954,"url":"https://patchwork.plctlab.org/api/1.2/patches/12954/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-15-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-15-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:49","name":"[V3,14/15] gas/NEWS: add text about new command line option and SFrame support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-15-indu.bhagat@oracle.com/mbox/"},{"id":12958,"url":"https://patchwork.plctlab.org/api/1.2/patches/12958/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-16-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-16-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:50","name":"[V3,15/15] doc: add SFrame spec file","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-16-indu.bhagat@oracle.com/mbox/"}]}' + patchid_patchurl='"12950,https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-2-indu.bhagat@oracle.com/mbox/" "12952,https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-3-indu.bhagat@oracle.com/mbox/" "12951,https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-4-indu.bhagat@oracle.com/mbox/" "12956,https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-5-indu.bhagat@oracle.com/mbox/" "12955,https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-6-indu.bhagat@oracle.com/mbox/" "12959,https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-7-indu.bhagat@oracle.com/mbox/" "12961,https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-8-indu.bhagat@oracle.com/mbox/" "12962,https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-9-indu.bhagat@oracle.com/mbox/" "12963,https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-10-indu.bhagat@oracle.com/mbox/" "12964,https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-11-indu.bhagat@oracle.com/mbox/" "12957,https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-12-indu.bhagat@oracle.com/mbox/" "12960,https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-13-indu.bhagat@oracle.com/mbox/" "12953,https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-14-indu.bhagat@oracle.com/mbox/" "12954,https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-15-indu.bhagat@oracle.com/mbox/" "12958,https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-16-indu.bhagat@oracle.com/mbox/"' + IFS=, + echo '"12950,https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-2-indu.bhagat@oracle.com/mbox/" "12952,https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-3-indu.bhagat@oracle.com/mbox/" "12951,https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-4-indu.bhagat@oracle.com/mbox/" "12956,https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-5-indu.bhagat@oracle.com/mbox/" "12955,https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-6-indu.bhagat@oracle.com/mbox/" "12959,https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-7-indu.bhagat@oracle.com/mbox/" "12961,https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-8-indu.bhagat@oracle.com/mbox/" "12962,https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-9-indu.bhagat@oracle.com/mbox/" "12963,https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-10-indu.bhagat@oracle.com/mbox/" "12964,https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-11-indu.bhagat@oracle.com/mbox/" "12957,https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-12-indu.bhagat@oracle.com/mbox/" "12960,https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-13-indu.bhagat@oracle.com/mbox/" "12953,https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-14-indu.bhagat@oracle.com/mbox/" "12954,https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-15-indu.bhagat@oracle.com/mbox/" "12958,https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-16-indu.bhagat@oracle.com/mbox/"' + read -r series_patch_id series_patch_url ++ echo '"12950' ++ sed 's/"//g' + series_patch_id=12950 ++ echo 'https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-2-indu.bhagat@oracle.com/mbox/"' ++ sed 's/"//g' + series_patch_url=https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-2-indu.bhagat@oracle.com/mbox/ ++ git rev-parse HEAD + commitid_before=60095ba3b8f8ba26a6389dded732fa446422c98f + eval '+++ declare -p bout bret declare -- bout="Applying: sframe.h: Add SFrame format definition" declare -- bret="0" ++ berr='\''++++ git_am https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-2-indu.bhagat@oracle.com/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-2-indu.bhagat@oracle.com/mbox/ ++++ curl https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-2-indu.bhagat@oracle.com/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 25422 100 25422 0 0 349k 0 --:--:-- --:--:-- --:--:-- 349k +++ bout='\''\'\'''\''Applying: sframe.h: Add SFrame format definition'\''\'\'''\'' +++ bret=0'\'' ++ declare -p berr declare -- berr="++++ git_am https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-2-indu.bhagat@oracle.com/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-2-indu.bhagat@oracle.com/mbox/ ++++ curl https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-2-indu.bhagat@oracle.com/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 25422 100 25422 0 0 349k 0 --:--:-- --:--:-- --:--:-- 349k +++ bout='\''Applying: sframe.h: Add SFrame format definition'\'' +++ bret=0"' ++ +++ declare -p bout bret /tmp/jenkins2109134673540936569.sh: line 124: +++: command not found ++ declare -- 'bout=Applying: sframe.h: Add SFrame format definition' ++ declare -- bret=0 ++ ++ 'berr=++++ git_am https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-2-indu.bhagat@oracle.com/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-2-indu.bhagat@oracle.com/mbox/ ++++ curl https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-2-indu.bhagat@oracle.com/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 25422 100 25422 0 0 349k 0 --:--:-- --:--:-- --:--:-- 349k +++ bout='\''Applying: sframe.h: Add SFrame format definition'\'' +++ bret=0' /tmp/jenkins2109134673540936569.sh: line 135: ++: command not found ++ ++ declare -p berr /tmp/jenkins2109134673540936569.sh: line 136: ++: command not found ++ declare -- 'berr=++++ git_am https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-2-indu.bhagat@oracle.com/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-2-indu.bhagat@oracle.com/mbox/ ++++ curl https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-2-indu.bhagat@oracle.com/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 25422 100 25422 0 0 349k 0 --:--:-- --:--:-- --:--:-- 349k +++ bout='\''Applying: sframe.h: Add SFrame format definition'\'' +++ bret=0' ++ git rev-parse HEAD + commitid_after=137b07e64c1191f6775cacc5e3f5b1f6ae38b3b2 + '[' 0 = 0 ']' + '[' 137b07e64c1191f6775cacc5e3f5b1f6ae38b3b2 = 60095ba3b8f8ba26a6389dded732fa446422c98f ']' + '[' 12950 = 12961 ']' + IFS=, + read -r series_patch_id series_patch_url ++ echo '"12952' ++ sed 's/"//g' + series_patch_id=12952 ++ echo 'https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-3-indu.bhagat@oracle.com/mbox/"' ++ sed 's/"//g' + series_patch_url=https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-3-indu.bhagat@oracle.com/mbox/ ++ git rev-parse HEAD + commitid_before=137b07e64c1191f6775cacc5e3f5b1f6ae38b3b2 + eval '+++ declare -p bout bret declare -- bout="Applying: gas: add new command line option --gsframe" declare -- bret="0" ++ berr='\''++++ git_am https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-3-indu.bhagat@oracle.com/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-3-indu.bhagat@oracle.com/mbox/ ++++ curl https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-3-indu.bhagat@oracle.com/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 15231 100 15231 0 0 206k 0 --:--:-- --:--:-- --:--:-- 206k +++ bout='\''\'\'''\''Applying: gas: add new command line option --gsframe'\''\'\'''\'' +++ bret=0'\'' ++ declare -p berr declare -- berr="++++ git_am https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-3-indu.bhagat@oracle.com/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-3-indu.bhagat@oracle.com/mbox/ ++++ curl https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-3-indu.bhagat@oracle.com/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 15231 100 15231 0 0 206k 0 --:--:-- --:--:-- --:--:-- 206k +++ bout='\''Applying: gas: add new command line option --gsframe'\'' +++ bret=0"' ++ +++ declare -p bout bret /tmp/jenkins2109134673540936569.sh: line 124: +++: command not found ++ declare -- 'bout=Applying: gas: add new command line option --gsframe' ++ declare -- bret=0 ++ ++ 'berr=++++ git_am https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-3-indu.bhagat@oracle.com/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-3-indu.bhagat@oracle.com/mbox/ ++++ curl https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-3-indu.bhagat@oracle.com/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 15231 100 15231 0 0 206k 0 --:--:-- --:--:-- --:--:-- 206k +++ bout='\''Applying: gas: add new command line option --gsframe'\'' +++ bret=0' /tmp/jenkins2109134673540936569.sh: line 135: ++: command not found ++ ++ declare -p berr /tmp/jenkins2109134673540936569.sh: line 136: ++: command not found ++ declare -- 'berr=++++ git_am https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-3-indu.bhagat@oracle.com/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-3-indu.bhagat@oracle.com/mbox/ ++++ curl https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-3-indu.bhagat@oracle.com/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 15231 100 15231 0 0 206k 0 --:--:-- --:--:-- --:--:-- 206k +++ bout='\''Applying: gas: add new command line option --gsframe'\'' +++ bret=0' ++ git rev-parse HEAD + commitid_after=4f501bc6007ceacd3efe4904bf6c7d48a6f78df2 + '[' 0 = 0 ']' + '[' 4f501bc6007ceacd3efe4904bf6c7d48a6f78df2 = 137b07e64c1191f6775cacc5e3f5b1f6ae38b3b2 ']' + '[' 12952 = 12961 ']' + IFS=, + read -r series_patch_id series_patch_url ++ echo '"12951' ++ sed 's/"//g' + series_patch_id=12951 ++ echo 'https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-4-indu.bhagat@oracle.com/mbox/"' ++ sed 's/"//g' + series_patch_url=https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-4-indu.bhagat@oracle.com/mbox/ ++ git rev-parse HEAD + commitid_before=4f501bc6007ceacd3efe4904bf6c7d48a6f78df2 + eval '+++ declare -p bout bret declare -- bout="Applying: gas: generate .sframe from CFI directives" declare -- bret="0" ++ berr='\''++++ git_am https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-4-indu.bhagat@oracle.com/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-4-indu.bhagat@oracle.com/mbox/ ++++ curl https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-4-indu.bhagat@oracle.com/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 83463 100 83463 0 0 1101k 0 --:--:-- --:--:-- --:--:-- 1101k +++ bout='\''\'\'''\''Applying: gas: generate .sframe from CFI directives'\''\'\'''\'' +++ bret=0'\'' ++ declare -p berr declare -- berr="++++ git_am https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-4-indu.bhagat@oracle.com/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-4-indu.bhagat@oracle.com/mbox/ ++++ curl https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-4-indu.bhagat@oracle.com/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 83463 100 83463 0 0 1101k 0 --:--:-- --:--:-- --:--:-- 1101k +++ bout='\''Applying: gas: generate .sframe from CFI directives'\'' +++ bret=0"' ++ +++ declare -p bout bret /tmp/jenkins2109134673540936569.sh: line 124: +++: command not found ++ declare -- 'bout=Applying: gas: generate .sframe from CFI directives' ++ declare -- bret=0 ++ ++ 'berr=++++ git_am https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-4-indu.bhagat@oracle.com/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-4-indu.bhagat@oracle.com/mbox/ ++++ curl https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-4-indu.bhagat@oracle.com/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 83463 100 83463 0 0 1101k 0 --:--:-- --:--:-- --:--:-- 1101k +++ bout='\''Applying: gas: generate .sframe from CFI directives'\'' +++ bret=0' /tmp/jenkins2109134673540936569.sh: line 135: ++: command not found ++ ++ declare -p berr /tmp/jenkins2109134673540936569.sh: line 136: ++: command not found ++ declare -- 'berr=++++ git_am https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-4-indu.bhagat@oracle.com/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-4-indu.bhagat@oracle.com/mbox/ ++++ curl https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-4-indu.bhagat@oracle.com/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 83463 100 83463 0 0 1101k 0 --:--:-- --:--:-- --:--:-- 1101k +++ bout='\''Applying: gas: generate .sframe from CFI directives'\'' +++ bret=0' ++ git rev-parse HEAD + commitid_after=df6ac29fa9355d709740ea0b0f8b4b4adb0c4576 + '[' 0 = 0 ']' + '[' df6ac29fa9355d709740ea0b0f8b4b4adb0c4576 = 4f501bc6007ceacd3efe4904bf6c7d48a6f78df2 ']' + '[' 12951 = 12961 ']' + IFS=, + read -r series_patch_id series_patch_url ++ echo '"12956' ++ sed 's/"//g' + series_patch_id=12956 ++ echo 'https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-5-indu.bhagat@oracle.com/mbox/"' ++ sed 's/"//g' + series_patch_url=https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-5-indu.bhagat@oracle.com/mbox/ ++ git rev-parse HEAD + commitid_before=df6ac29fa9355d709740ea0b0f8b4b4adb0c4576 + eval '+++ declare -p bout bret declare -- bout="Applying: gas: testsuite: add new tests for SFrame unwind info" declare -- bret="0" ++ berr='\''++++ git_am https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-5-indu.bhagat@oracle.com/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-5-indu.bhagat@oracle.com/mbox/ ++++ curl https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-5-indu.bhagat@oracle.com/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 37920 100 37920 0 0 514k 0 --:--:-- --:--:-- --:--:-- 514k +++ bout='\''\'\'''\''Applying: gas: testsuite: add new tests for SFrame unwind info'\''\'\'''\'' +++ bret=0'\'' ++ declare -p berr declare -- berr="++++ git_am https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-5-indu.bhagat@oracle.com/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-5-indu.bhagat@oracle.com/mbox/ ++++ curl https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-5-indu.bhagat@oracle.com/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 37920 100 37920 0 0 514k 0 --:--:-- --:--:-- --:--:-- 514k +++ bout='\''Applying: gas: testsuite: add new tests for SFrame unwind info'\'' +++ bret=0"' ++ +++ declare -p bout bret /tmp/jenkins2109134673540936569.sh: line 124: +++: command not found ++ declare -- 'bout=Applying: gas: testsuite: add new tests for SFrame unwind info' ++ declare -- bret=0 ++ ++ 'berr=++++ git_am https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-5-indu.bhagat@oracle.com/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-5-indu.bhagat@oracle.com/mbox/ ++++ curl https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-5-indu.bhagat@oracle.com/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 37920 100 37920 0 0 514k 0 --:--:-- --:--:-- --:--:-- 514k +++ bout='\''Applying: gas: testsuite: add new tests for SFrame unwind info'\'' +++ bret=0' /tmp/jenkins2109134673540936569.sh: line 135: ++: command not found ++ ++ declare -p berr /tmp/jenkins2109134673540936569.sh: line 136: ++: command not found ++ declare -- 'berr=++++ git_am https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-5-indu.bhagat@oracle.com/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-5-indu.bhagat@oracle.com/mbox/ ++++ curl https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-5-indu.bhagat@oracle.com/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 37920 100 37920 0 0 514k 0 --:--:-- --:--:-- --:--:-- 514k +++ bout='\''Applying: gas: testsuite: add new tests for SFrame unwind info'\'' +++ bret=0' ++ git rev-parse HEAD + commitid_after=19da143b5a3e694365681c83d486abe52b78602b + '[' 0 = 0 ']' + '[' 19da143b5a3e694365681c83d486abe52b78602b = df6ac29fa9355d709740ea0b0f8b4b4adb0c4576 ']' + '[' 12956 = 12961 ']' + IFS=, + read -r series_patch_id series_patch_url ++ echo '"12955' ++ sed 's/"//g' + series_patch_id=12955 ++ echo 'https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-6-indu.bhagat@oracle.com/mbox/"' ++ sed 's/"//g' + series_patch_url=https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-6-indu.bhagat@oracle.com/mbox/ ++ git rev-parse HEAD + commitid_before=19da143b5a3e694365681c83d486abe52b78602b + eval '+++ declare -p bout bret declare -- bout="git: apply.c:3717: check_preimage: Assertion \`patch->is_new <= 0'\'' failed." declare -- bret="134" ++ berr='\''++++ git_am https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-6-indu.bhagat@oracle.com/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-6-indu.bhagat@oracle.com/mbox/ ++++ curl https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-6-indu.bhagat@oracle.com/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 270k 100 270k 0 0 3384k 0 --:--:-- --:--:-- --:--:-- 3384k +++ bout='\''\'\'''\''git: apply.c:3717: check_preimage: Assertion `patch->is_new <= 0'\''\'\'''\''\'\''\'\'''\'''\''\'\'''\'' failed.'\''\'\'''\'' +++ bret=134'\'' ++ declare -p berr declare -- berr="++++ git_am https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-6-indu.bhagat@oracle.com/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-6-indu.bhagat@oracle.com/mbox/ ++++ curl https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-6-indu.bhagat@oracle.com/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 270k 100 270k 0 0 3384k 0 --:--:-- --:--:-- --:--:-- 3384k +++ bout='\''git: apply.c:3717: check_preimage: Assertion \`patch->is_new <= 0'\''\\'\'''\'' failed.'\'' +++ bret=134"' ++ +++ declare -p bout bret /tmp/jenkins2109134673540936569.sh: line 124: +++: command not found ++ declare -- 'bout=git: apply.c:3717: check_preimage: Assertion `patch->is_new <= 0'\'' failed.' ++ declare -- bret=134 ++ ++ 'berr=++++ git_am https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-6-indu.bhagat@oracle.com/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-6-indu.bhagat@oracle.com/mbox/ ++++ curl https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-6-indu.bhagat@oracle.com/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 270k 100 270k 0 0 3384k 0 --:--:-- --:--:-- --:--:-- 3384k +++ bout='\''git: apply.c:3717: check_preimage: Assertion `patch->is_new <= 0'\''\'\'''\'' failed.'\'' +++ bret=134' /tmp/jenkins2109134673540936569.sh: line 135: ++: command not found ++ ++ declare -p berr /tmp/jenkins2109134673540936569.sh: line 136: ++: command not found ++ declare -- 'berr=++++ git_am https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-6-indu.bhagat@oracle.com/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-6-indu.bhagat@oracle.com/mbox/ ++++ curl https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-6-indu.bhagat@oracle.com/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 270k 100 270k 0 0 3384k 0 --:--:-- --:--:-- --:--:-- 3384k +++ bout='\''git: apply.c:3717: check_preimage: Assertion `patch->is_new <= 0'\''\'\'''\'' failed.'\'' +++ bret=134' ++ git rev-parse HEAD + commitid_after=19da143b5a3e694365681c83d486abe52b78602b + '[' 134 = 0 ']' + [[ ++++ git_am https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-6-indu.bhagat@oracle.com/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-6-indu.bhagat@oracle.com/mbox/ ++++ curl https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-6-indu.bhagat@oracle.com/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 270k 100 270k 0 0 3384k 0 --:--:-- --:--:-- --:--:-- 3384k +++ bout='git: apply.c:3717: check_preimage: Assertion `patch->is_new <= 0'\'' failed.' +++ bret=134 =~ sha1 information is lacking or useless ]] + [[ ++++ git_am https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-6-indu.bhagat@oracle.com/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-6-indu.bhagat@oracle.com/mbox/ ++++ curl https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-6-indu.bhagat@oracle.com/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 270k 100 270k 0 0 3384k 0 --:--:-- --:--:-- --:--:-- 3384k +++ bout='git: apply.c:3717: check_preimage: Assertion `patch->is_new <= 0'\'' failed.' +++ bret=134 =~ Failed to merge in the changes ]] + [[ ++++ git_am https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-6-indu.bhagat@oracle.com/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-6-indu.bhagat@oracle.com/mbox/ ++++ curl https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-6-indu.bhagat@oracle.com/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 270k 100 270k 0 0 3384k 0 --:--:-- --:--:-- --:--:-- 3384k +++ bout='git: apply.c:3717: check_preimage: Assertion `patch->is_new <= 0'\'' failed.' +++ bret=134 =~ corrupt patch at ]] + [[ ++++ git_am https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-6-indu.bhagat@oracle.com/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-6-indu.bhagat@oracle.com/mbox/ ++++ curl https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-6-indu.bhagat@oracle.com/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 270k 100 270k 0 0 3384k 0 --:--:-- --:--:-- --:--:-- 3384k +++ bout='git: apply.c:3717: check_preimage: Assertion `patch->is_new <= 0'\'' failed.' +++ bret=134 =~ patch fragment without header at ]] + [[ ++++ git_am https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-6-indu.bhagat@oracle.com/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-6-indu.bhagat@oracle.com/mbox/ ++++ curl https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-6-indu.bhagat@oracle.com/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 270k 100 270k 0 0 3384k 0 --:--:-- --:--:-- --:--:-- 3384k +++ bout='git: apply.c:3717: check_preimage: Assertion `patch->is_new <= 0'\'' failed.' +++ bret=134 =~ No valid patches in input ]] + submit_check fail 'Not Applicable' https://patchwork.plctlab.org/jenkins/job/binutils-gdb/250/consoleText 'Git am fail log' + check_state=fail + patch_state='Not Applicable' + repo_url=https://patchwork.plctlab.org/jenkins/job/binutils-gdb/250/consoleText + DESCRIPTION='Git am fail log' + curl -X POST -H 'Authorization: Token [*******]' -F state=fail -F target_url=https://patchwork.plctlab.org/jenkins/job/binutils-gdb/250/consoleText -F context=binutils-gdb-check -F 'description=Git am fail log' https://patchwork.plctlab.org/api/patches/12961/checks/ % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 969 100 427 100 542 14724 18689 --:--:-- --:--:-- --:--:-- 33413 {"id":1518,"url":"https://patchwork.plctlab.org/api/patches/12961/checks/1518/","user":{"id":1,"url":"https://patchwork.plctlab.org/api/users/1/","username":"snail","first_name":"","last_name":"","email":"wangliu@iscas.ac.cn"},"date":"2022-10-30T08:21:18.122764","state":"fail","target_url":"https://patchwork.plctlab.org/jenkins/job/binutils-gdb/250/consoleText","context":"binutils-gdb-check","description":"Git am fail log"}+ curl -X PATCH -H 'Authorization: Token [*******]' -F 'state=Not Applicable' https://patchwork.plctlab.org/api/1.2/patches/12961/ % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0{"id":12961,"url":"https://patchwork.plctlab.org/api/1.2/patches/12961/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-8-indu.bhagat@oracle.com/","project":{"id":2,"url":"https://patchwork.plctlab.org/api/1.2/projects/2/","name":"binutils-gdb","link_name":"binutils-gdb","list_id":"binutils.sourceware.org","list_email":"binutils@sourceware.org","web_url":"https://github.com/wangliu-iscas/Patchwork-Bundles/blob/main/binutils-gdb.md","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20221030074450.1956074-8-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:42","name":"[V3,07/15] readelf/objdump: support for SFrame section","commit_ref":null,"pull_url":null,"state":"not-applicable","archived":false,"hash":"cfd3c29fa430f9540245c9cbb118dd733c49ecfe","submitter":{"id":35,"url":"https://patchwork.plctlab.org/api/1.2/people/35/","name":"Indu Bhagat","email":"indu.bhagat@oracle.com"},"delegate":null,"mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-8-indu.bhagat@oracle.com/mbox/","series":[{"id":4870,"url":"https://patchwork.plctlab.org/api/1.2/series/4870/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/list/?series=4870","date":"2022-10-30T07:44:35","name":"Definition and support for SFrame unwind format","version":3,"mbox":"https://patchwork.plctlab.org/series/4870/mbox/"}],"comments":"https://patchwork.plctlab.org/api/patches/12961/comments/","check":"fail","checks":"https://patchwork.plctlab.org/api/patches/12961/checks/","tags":{},"headers":{"Return-Path":"","Delivered-To":["ouuuleilei@gmail.com","binutils@sourceware.org"],"Received":["by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp1687915wru;\n Sun, 30 Oct 2022 00:54:07 -0700 (PDT)","from sourceware.org (ip-8-43-85-97.sourceware.org. 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","X-getmail-retrieved-from-mailbox":"=?utf-8?q?INBOX?=","X-GMAIL-THRID":"=?utf-8?q?1748098296023131181?=","X-GMAIL-MSGID":"=?utf-8?q?1748098296023131181?="},"content":"[Changes in V3]\n - Minor changes to uptake API signature changes in libsframe.\n - Fixed -Wformat warnings in dump_sframe_func_with_fres ().\n[End of changes in V3]\n\n[Changes in V2]\n - Fixed compilation errors seen on i686.\n - readelf: bugfix: --sframe=.eh_frame gives no error\n New behaviour:\n $ readelf --sframe=.eh_frame \n readelf: Error: SFrame decode failure: Buffer does not contain SFrame data.\n $ readelf --sframe=.foo \n readelf: Warning: Section '.foo' was not dumped because it does not exist\n - readelf: make --sframe arguments optional (similar to the command\n line option for objdump)\n[End of changes in V2]\n\nThis patch adds support for SFrame in readelf and objdump.\n\ninclude/ChangeLog:\n\n\t* sframe-api.h (dump_sframe): New function declaration.\n\nChangeLog:\n\n\t* binutils/Makefile.am: Add dependency on libsframe for\n\treadelf and objdump.\n\t* binutils/Makefile.in: Regenerate.\n\t* binutils/doc/binutils.texi: Document --sframe=[section].\n\t* binutils/doc/sframe.options.texi: New file.\n\t* binutils/objdump.c: Add support for SFrame format.\n\t* binutils/readelf.c: Likewise.\n\t* include/sframe-api.h: Add new API for dumping .sframe\n\tsection.\n\t* libsframe/Makefile.am: Add sframe-dump.c.\n\t* libsframe/Makefile.in: Regenerate.\n\t* libsframe/sframe-dump.c: New file.\n---\n binutils/Makefile.am | 8 +-\n binutils/Makefile.in | 8 +-\n binutils/doc/binutils.texi | 4 +\n binutils/doc/sframe.options.texi | 10 ++\n binutils/objdump.c | 75 +++++++++++++\n binutils/readelf.c | 63 +++++++++++\n include/sframe-api.h | 3 +\n libsframe/Makefile.am | 2 +-\n libsframe/Makefile.in | 12 +-\n libsframe/sframe-dump.c | 181 +++++++++++++++++++++++++++++++\n 10 files changed, 355 insertions(+), 11 deletions(-)\n create mode 100644 binutils/doc/sframe.options.texi\n create mode 100644 libsframe/sframe-dump.c","diff":"diff --git a/binutils/Makefile.am b/binutils/Makefile.am\nindex 6d974fd3f8a..ce5fa1d39bb 100644\n--- a/binutils/Makefile.am\n+++ b/binutils/Makefile.am\n@@ -228,7 +228,7 @@ installcheck-local:\n # which depends on libintl, since we don't know whether LIBINTL_DEP will be\n # non-empty until configure time. Ugh!\n size_DEPENDENCIES = $(LIBINTL_DEP) $(LIBIBERTY) $(BFDLIB)\n-objdump_DEPENDENCIES = $(LIBINTL_DEP) $(LIBIBERTY) $(BFDLIB) $(OPCODES) $(LIBCTF) $(OBJDUMP_PRIVATE_OFILES)\n+objdump_DEPENDENCIES = $(LIBINTL_DEP) $(LIBIBERTY) $(BFDLIB) $(OPCODES) $(LIBCTF) $(OBJDUMP_PRIVATE_OFILES) $(LIBSFRAME)\n nm_new_DEPENDENCIES = $(LIBINTL_DEP) $(LIBIBERTY) $(BFDLIB)\n ar_DEPENDENCIES = $(LIBINTL_DEP) $(LIBIBERTY) $(BFDLIB)\n strings_DEPENDENCIES = $(LIBINTL_DEP) $(LIBIBERTY) $(BFDLIB)\n@@ -243,7 +243,7 @@ dlltool_DEPENDENCIES = $(LIBINTL_DEP) $(LIBIBERTY) $(BFDLIB)\n windres_DEPENDENCIES = $(LIBINTL_DEP) $(LIBIBERTY) $(BFDLIB)\n windmc_DEPENDENCIES = $(LIBINTL_DEP) $(LIBIBERTY) $(BFDLIB)\n addr2line_DEPENDENCIES = $(LIBINTL_DEP) $(LIBIBERTY) $(BFDLIB)\n-readelf_DEPENDENCIES = $(LIBINTL_DEP) $(LIBIBERTY) $(LIBCTF_NOBFD)\n+readelf_DEPENDENCIES = $(LIBINTL_DEP) $(LIBIBERTY) $(LIBCTF_NOBFD) $(LIBSFRAME)\n elfedit_DEPENDENCIES = $(LIBINTL_DEP) $(LIBIBERTY)\n dllwrap_DEPENDENCIES = $(LIBINTL_DEP) $(LIBIBERTY)\n bfdtest1_DEPENDENCIES = $(LIBINTL_DEP) $(LIBIBERTY) $(BFDLIB)\n@@ -258,7 +258,7 @@ objcopy_SOURCES = objcopy.c not-strip.c rename.c $(WRITE_DEBUG_SRCS) $(BULIBS)\n strings_SOURCES = strings.c $(BULIBS)\n \n readelf_SOURCES = readelf.c version.c unwind-ia64.c dwarf.c demanguse.c $(ELFLIBS)\n-readelf_LDADD = $(LIBCTF_NOBFD) $(LIBINTL) $(LIBIBERTY) $(ZLIB) $(ZSTD_LIBS) $(DEBUGINFOD_LIBS) $(MSGPACK_LIBS)\n+readelf_LDADD = $(LIBCTF_NOBFD) $(LIBINTL) $(LIBIBERTY) $(ZLIB) $(ZSTD_LIBS) $(DEBUGINFOD_LIBS) $(MSGPACK_LIBS) $(LIBSFRAME)\n \n elfedit_SOURCES = elfedit.c version.c $(ELFLIBS)\n elfedit_LDADD = $(LIBINTL) $(LIBIBERTY)\n@@ -269,7 +269,7 @@ nm_new_SOURCES = nm.c demanguse.c $(BULIBS)\n \n objdump_SOURCES = objdump.c dwarf.c prdbg.c demanguse.c $(DEBUG_SRCS) $(BULIBS) $(ELFLIBS)\n EXTRA_objdump_SOURCES = od-xcoff.c\n-objdump_LDADD = $(OBJDUMP_PRIVATE_OFILES) $(OPCODES) $(LIBCTF) $(BFDLIB) $(LIBIBERTY) $(LIBINTL) $(DEBUGINFOD_LIBS)\n+objdump_LDADD = $(OBJDUMP_PRIVATE_OFILES) $(OPCODES) $(LIBCTF) $(BFDLIB) $(LIBIBERTY) $(LIBINTL) $(DEBUGINFOD_LIBS) $(LIBSFRAME)\n \n objdump.@OBJEXT@:objdump.c\n if am__fastdepCC\ndiff --git a/binutils/Makefile.in b/binutils/Makefile.in\nindex 05aca3d3965..30b78a961dd 100644\n--- a/binutils/Makefile.in\n+++ b/binutils/Makefile.in\n@@ -766,7 +766,7 @@ CC_FOR_TARGET = ` \\\n # which depends on libintl, since we don't know whether LIBINTL_DEP will be\n # non-empty until configure time. Ugh!\n size_DEPENDENCIES = $(LIBINTL_DEP) $(LIBIBERTY) $(BFDLIB)\n-objdump_DEPENDENCIES = $(LIBINTL_DEP) $(LIBIBERTY) $(BFDLIB) $(OPCODES) $(LIBCTF) $(OBJDUMP_PRIVATE_OFILES)\n+objdump_DEPENDENCIES = $(LIBINTL_DEP) $(LIBIBERTY) $(BFDLIB) $(OPCODES) $(LIBCTF) $(OBJDUMP_PRIVATE_OFILES) $(LIBSFRAME)\n nm_new_DEPENDENCIES = $(LIBINTL_DEP) $(LIBIBERTY) $(BFDLIB)\n ar_DEPENDENCIES = $(LIBINTL_DEP) $(LIBIBERTY) $(BFDLIB)\n strings_DEPENDENCIES = $(LIBINTL_DEP) $(LIBIBERTY) $(BFDLIB)\n@@ -781,7 +781,7 @@ dlltool_DEPENDENCIES = $(LIBINTL_DEP) $(LIBIBERTY) $(BFDLIB)\n windres_DEPENDENCIES = $(LIBINTL_DEP) $(LIBIBERTY) $(BFDLIB)\n windmc_DEPENDENCIES = $(LIBINTL_DEP) $(LIBIBERTY) $(BFDLIB)\n addr2line_DEPENDENCIES = $(LIBINTL_DEP) $(LIBIBERTY) $(BFDLIB)\n-readelf_DEPENDENCIES = $(LIBINTL_DEP) $(LIBIBERTY) $(LIBCTF_NOBFD)\n+readelf_DEPENDENCIES = $(LIBINTL_DEP) $(LIBIBERTY) $(LIBCTF_NOBFD) $(LIBSFRAME)\n elfedit_DEPENDENCIES = $(LIBINTL_DEP) $(LIBIBERTY)\n dllwrap_DEPENDENCIES = $(LIBINTL_DEP) $(LIBIBERTY)\n bfdtest1_DEPENDENCIES = $(LIBINTL_DEP) $(LIBIBERTY) $(BFDLIB)\n@@ -791,14 +791,14 @@ size_SOURCES = size.c $(BULIBS)\n objcopy_SOURCES = objcopy.c not-strip.c rename.c $(WRITE_DEBUG_SRCS) $(BULIBS)\n strings_SOURCES = strings.c $(BULIBS)\n readelf_SOURCES = readelf.c version.c unwind-ia64.c dwarf.c demanguse.c $(ELFLIBS)\n-readelf_LDADD = $(LIBCTF_NOBFD) $(LIBINTL) $(LIBIBERTY) $(ZLIB) $(ZSTD_LIBS) $(DEBUGINFOD_LIBS) $(MSGPACK_LIBS)\n+readelf_LDADD = $(LIBCTF_NOBFD) $(LIBINTL) $(LIBIBERTY) $(ZLIB) $(ZSTD_LIBS) $(DEBUGINFOD_LIBS) $(MSGPACK_LIBS) $(LIBSFRAME)\n elfedit_SOURCES = elfedit.c version.c $(ELFLIBS)\n elfedit_LDADD = $(LIBINTL) $(LIBIBERTY)\n strip_new_SOURCES = objcopy.c is-strip.c rename.c $(WRITE_DEBUG_SRCS) $(BULIBS)\n nm_new_SOURCES = nm.c demanguse.c $(BULIBS)\n objdump_SOURCES = objdump.c dwarf.c prdbg.c demanguse.c $(DEBUG_SRCS) $(BULIBS) $(ELFLIBS)\n EXTRA_objdump_SOURCES = od-xcoff.c\n-objdump_LDADD = $(OBJDUMP_PRIVATE_OFILES) $(OPCODES) $(LIBCTF) $(BFDLIB) $(LIBIBERTY) $(LIBINTL) $(DEBUGINFOD_LIBS)\n+objdump_LDADD = $(OBJDUMP_PRIVATE_OFILES) $(OPCODES) $(LIBCTF) $(BFDLIB) $(LIBIBERTY) $(LIBINTL) $(DEBUGINFOD_LIBS) $(LIBSFRAME)\n cxxfilt_SOURCES = cxxfilt.c $(BULIBS)\n ar_SOURCES = arparse.y arlex.l ar.c not-ranlib.c arsup.c rename.c binemul.c \\\n \temul_$(EMULATION).c $(BULIBS)\ndiff --git a/binutils/doc/binutils.texi b/binutils/doc/binutils.texi\nindex 6eea08fb91b..0f3860abaaa 100644\n--- a/binutils/doc/binutils.texi\n+++ b/binutils/doc/binutils.texi\n@@ -2262,6 +2262,7 @@ objdump [@option{-a}|@option{--archive-headers}]\n [@option{-wE}|@option{--dwarf=do-not-use-debuginfod}]\n [@option{-L}|@option{--process-links}]\n [@option{--ctf=}@var{section}]\n+ [@option{--sframe=}@var{section}]\n [@option{-G}|@option{--stabs}]\n [@option{-t}|@option{--syms}]\n [@option{-T}|@option{--dynamic-syms}]\n@@ -2843,6 +2844,8 @@ Enable additional checks for consistency of Dwarf information.\n \n @include ctf.options.texi\n \n+@include sframe.options.texi\n+\n @item -G\n @itemx --stabs\n @cindex stab\n@@ -4940,6 +4943,7 @@ readelf [@option{-a}|@option{--all}]\n [@option{--ctf-parent=}@var{section}]\n [@option{--ctf-symbols=}@var{section}]\n [@option{--ctf-strings=}@var{section}]\n+ [@option{--sframe=}@var{section}]\n [@option{-I}|@option{--histogram}]\n [@option{-v}|@option{--version}]\n [@option{-W}|@option{--wide}]\ndiff --git a/binutils/doc/sframe.options.texi b/binutils/doc/sframe.options.texi\nnew file mode 100644\nindex 00000000000..9e23679a3da\n--- /dev/null\n+++ b/binutils/doc/sframe.options.texi\n@@ -0,0 +1,10 @@\n+@c This file contains the entry for the --sframe option that is\n+@c common to both readelf and objdump.\n+\n+@item --sframe[=@var{section}]\n+@cindex SFrame\n+\n+Display the contents of the specified SFrame section.\n+\n+By default, display the name of the section named @var{.sframe}, which is the\n+name emitted by @command{ld}.\ndiff --git a/binutils/objdump.c b/binutils/objdump.c\nindex 0825e051ef6..dac5d73009f 100644\n--- a/binutils/objdump.c\n+++ b/binutils/objdump.c\n@@ -58,6 +58,7 @@\n #include \"demanguse.h\"\n #include \"dwarf.h\"\n #include \"ctf-api.h\"\n+#include \"sframe-api.h\"\n #include \"getopt.h\"\n #include \"safe-ctype.h\"\n #include \"dis-asm.h\"\n@@ -108,6 +109,8 @@ static int dump_stab_section_info;\t/* --stabs */\n static int dump_ctf_section_info; /* --ctf */\n static char *dump_ctf_section_name;\n static char *dump_ctf_parent_name;\t/* --ctf-parent */\n+static int dump_sframe_section_info;\t/* --sframe */\n+static char *dump_sframe_section_name;\n static int do_demangle;\t\t\t/* -C, --demangle */\n static bool disassemble;\t\t/* -d */\n static bool disassemble_all;\t\t/* -D */\n@@ -316,6 +319,8 @@ usage (FILE *stream, int status)\n fprintf (stream, _(\"\\\n --ctf[=SECTION] Display CTF info from SECTION, (default `.ctf')\\n\"));\n #endif\n+ fprintf (stream, _(\"\\\n+ --sframe[=SECTION] Display SFrame info from SECTION, (default '.sframe')\\n\"));\n fprintf (stream, _(\"\\\n -t, --syms Display the contents of the symbol table(s)\\n\"));\n fprintf (stream, _(\"\\\n@@ -462,6 +467,7 @@ enum option_values\n OPTION_CTF,\n OPTION_CTF_PARENT,\n #endif\n+ OPTION_SFRAME,\n OPTION_VISUALIZE_JUMPS,\n OPTION_DISASSEMBLER_COLOR\n };\n@@ -516,6 +522,7 @@ static struct option long_options[]=\n {\"reloc\", no_argument, NULL, 'r'},\n {\"section\", required_argument, NULL, 'j'},\n {\"section-headers\", no_argument, NULL, 'h'},\n+ {\"sframe\", optional_argument, NULL, OPTION_SFRAME},\n {\"show-raw-insn\", no_argument, &show_raw_insn, 1},\n {\"source\", no_argument, NULL, 'S'},\n {\"source-comment\", optional_argument, NULL, OPTION_SOURCE_COMMENT},\n@@ -4801,6 +4808,66 @@ dump_ctf (bfd *abfd ATTRIBUTE_UNUSED, const char *sect_name ATTRIBUTE_UNUSED,\n \t const char *parent_name ATTRIBUTE_UNUSED) {}\n #endif\n \n+static bfd_byte*\n+read_section_sframe (bfd *abfd, const char *sect_name, bfd_size_type *size_ptr,\n+\t\t bfd_vma *sframe_vma)\n+{\n+ asection *sframe_sect;\n+ bfd_byte *contents;\n+\n+ sframe_sect = bfd_get_section_by_name (abfd, sect_name);\n+ if (sframe_sect == NULL)\n+ {\n+ printf (_(\"No %s section present\\n\\n\"),\n+\t sanitize_string (sect_name));\n+ return NULL;\n+ }\n+\n+ if (!bfd_malloc_and_get_section (abfd, sframe_sect, &contents))\n+ {\n+ non_fatal (_(\"reading %s section of %s failed: %s\"),\n+\t\t sect_name, bfd_get_filename (abfd),\n+\t\t bfd_errmsg (bfd_get_error ()));\n+ exit_status = 1;\n+ free (contents);\n+ return NULL;\n+ }\n+\n+ *size_ptr = bfd_section_size (sframe_sect);\n+ *sframe_vma = bfd_section_vma (sframe_sect);\n+\n+ return contents;\n+}\n+\n+static void\n+dump_section_sframe (bfd *abfd ATTRIBUTE_UNUSED,\n+\t\t const char * sect_name)\n+{\n+ sframe_decoder_ctx *sfd_ctx = NULL;\n+ bfd_size_type sf_size;\n+ bfd_byte *sframe_data = NULL;\n+ bfd_vma sf_vma;\n+ int err = 0;\n+\n+ if (sect_name == NULL)\n+ sect_name = \".sframe\";\n+\n+ sframe_data = read_section_sframe (abfd, sect_name, &sf_size, &sf_vma);\n+\n+ if (sframe_data == NULL)\n+ bfd_fatal (bfd_get_filename (abfd));\n+\n+ /* Decode the contents of the section. */\n+ sfd_ctx = sframe_decode ((const char*)sframe_data, sf_size, &err);\n+ if (!sfd_ctx)\n+ bfd_fatal (bfd_get_filename (abfd));\n+\n+ printf (_(\"Contents of the SFrame section %s:\"),\n+\t sanitize_string (sect_name));\n+ /* Dump the contents as text. */\n+ dump_sframe (sfd_ctx, sf_vma);\n+}\n+\n \f\n static void\n dump_bfd_private_header (bfd *abfd)\n@@ -5554,6 +5621,8 @@ dump_bfd (bfd *abfd, bool is_mainfile)\n {\n if (dump_ctf_section_info)\n \tdump_ctf (abfd, dump_ctf_section_name, dump_ctf_parent_name);\n+ if (dump_sframe_section_info)\n+\tdump_section_sframe (abfd, dump_sframe_section_name);\n if (dump_stab_section_info)\n \tdump_stabs (abfd);\n if (dump_reloc_info && ! disassemble)\n@@ -6051,6 +6120,12 @@ main (int argc, char **argv)\n \t dump_ctf_parent_name = xstrdup (optarg);\n \t break;\n #endif\n+\tcase OPTION_SFRAME:\n+\t dump_sframe_section_info = true;\n+\t if (optarg)\n+\t dump_sframe_section_name = xstrdup (optarg);\n+\t seenflag = true;\n+\t break;\n \tcase 'G':\n \t dump_stab_section_info = true;\n \t seenflag = true;\ndiff --git a/binutils/readelf.c b/binutils/readelf.c\nindex e52060dbf91..8cfa6cb0a5c 100644\n--- a/binutils/readelf.c\n+++ b/binutils/readelf.c\n@@ -63,6 +63,7 @@\n #include \"demanguse.h\"\n #include \"dwarf.h\"\n #include \"ctf-api.h\"\n+#include \"sframe-api.h\"\n #include \"demangle.h\"\n \n #include \"elf/common.h\"\n@@ -190,6 +191,7 @@ typedef struct elf_section_list\n #define STRING_DUMP (1 << 3)\t/* The -p command line switch. */\n #define RELOC_DUMP (1 << 4)\t/* The -R command line switch. */\n #define CTF_DUMP\t(1 << 5)\t/* The --ctf command line switch. */\n+#define SFRAME_DUMP\t(1 << 6)\t/* The --sframe command line switch. */\n \n typedef unsigned char dump_type;\n \n@@ -233,6 +235,7 @@ static bool do_version = false;\n static bool do_histogram = false;\n static bool do_debugging = false;\n static bool do_ctf = false;\n+static bool do_sframe = false;\n static bool do_arch = false;\n static bool do_notes = false;\n static bool do_archive_index = false;\n@@ -5071,6 +5074,7 @@ enum long_option_values\n OPTION_CTF_PARENT,\n OPTION_CTF_SYMBOLS,\n OPTION_CTF_STRINGS,\n+ OPTION_SFRAME_DUMP,\n OPTION_WITH_SYMBOL_VERSIONS,\n OPTION_RECURSE_LIMIT,\n OPTION_NO_RECURSE_LIMIT,\n@@ -5133,6 +5137,7 @@ static struct option options[] =\n {\"ctf-strings\", required_argument, 0, OPTION_CTF_STRINGS},\n {\"ctf-parent\", required_argument, 0, OPTION_CTF_PARENT},\n #endif\n+ {\"sframe\",\t optional_argument, 0, OPTION_SFRAME_DUMP},\n {\"sym-base\",\t optional_argument, 0, OPTION_SYM_BASE},\n \n {0,\t\t no_argument, 0, 0}\n@@ -5273,6 +5278,8 @@ usage (FILE * stream)\n --ctf-strings=\\n\\\n Use section as the CTF external strtab\\n\"));\n #endif\n+ fprintf (stream, _(\"\\\n+ --sframe[=NAME] Display SFrame info from section NAME, (default '.sframe')\\n\"));\n \n #ifdef SUPPORT_DISASSEMBLY\n fprintf (stream, _(\"\\\n@@ -5546,6 +5553,19 @@ parse_args (struct dump_data *dumpdata, int argc, char ** argv)\n \t free (dump_ctf_parent_name);\n \t dump_ctf_parent_name = strdup (optarg);\n \t break;\n+\tcase OPTION_SFRAME_DUMP:\n+\t do_sframe = true;\n+\t /* Providing section name is optional. request_dump (), however,\n+\t thrives on non NULL optarg. Handle it explicitly here. */\n+\t if (optarg != NULL)\n+\t request_dump (dumpdata, SFRAME_DUMP);\n+\t else\n+\t {\n+\t do_dump = true;\n+\t const char *sframe_sec_name = strdup (\".sframe\");\n+\t request_dump_byname (sframe_sec_name, SFRAME_DUMP);\n+\t }\n+\t break;\n \tcase OPTION_DYN_SYMS:\n \t do_dyn_syms = true;\n \t break;\n@@ -15857,6 +15877,44 @@ dump_section_as_ctf (Elf_Internal_Shdr * section, Filedata * filedata)\n }\n #endif\n \n+static bool\n+dump_section_as_sframe (Elf_Internal_Shdr * section, Filedata * filedata)\n+{\n+ void *\t\t data = NULL;\n+ sframe_decoder_ctx\t *sfd_ctx = NULL;\n+ const char *print_name = printable_section_name (filedata, section);\n+\n+ bool ret = true;\n+ size_t sf_size;\n+ int err = 0;\n+\n+ if (strcmp (print_name, \"\") == 0)\n+ {\n+ error (_(\"Section name must be provided \\n\"));\n+ ret = false;\n+ return ret;\n+ }\n+\n+ data = get_section_contents (section, filedata);\n+ sf_size = section->sh_size;\n+ /* Decode the contents of the section. */\n+ sfd_ctx = sframe_decode ((const char*)data, sf_size, &err);\n+ if (!sfd_ctx)\n+ {\n+ ret = false;\n+ error (_(\"SFrame decode failure: %s\\n\"), sframe_errmsg (err));\n+ goto fail;\n+ }\n+\n+ printf (_(\"Contents of the SFrame section %s:\"), print_name);\n+ /* Dump the contents as text. */\n+ dump_sframe (sfd_ctx, section->sh_addr);\n+\n+ fail:\n+ free (data);\n+ return ret;\n+}\n+\n static bool\n load_specific_debug_section (enum dwarf_section_display_enum debug,\n \t\t\t const Elf_Internal_Shdr * sec,\n@@ -16363,6 +16421,11 @@ process_section_contents (Filedata * filedata)\n \t res = false;\n \t}\n #endif\n+ if (dump & SFRAME_DUMP)\n+\t{\n+\t if (! dump_section_as_sframe (section, filedata))\n+\t res = false;\n+\t}\n }\n \n if (! filedata->is_separate)\ndiff --git a/include/sframe-api.h b/include/sframe-api.h\nindex 0fbed017ecd..077985b2017 100644\n--- a/include/sframe-api.h\n+++ b/include/sframe-api.h\n@@ -157,6 +157,9 @@ sframe_decoder_get_funcdesc (sframe_decoder_ctx *ctx,\n \t\t\t int32_t *func_start_address,\n \t\t\t unsigned char *func_info);\n \n+/* SFrame textual dump. */\n+extern void\n+dump_sframe (sframe_decoder_ctx *decoder, uint64_t addr);\n \n /* Get the base reg id from the FRE info. Sets errp if fails. */\n extern unsigned int\ndiff --git a/libsframe/Makefile.am b/libsframe/Makefile.am\nindex 940494dba1e..d8198a166c5 100644\n--- a/libsframe/Makefile.am\n+++ b/libsframe/Makefile.am\n@@ -33,7 +33,7 @@ include_HEADERS =\n noinst_LTLIBRARIES = libsframe.la\n endif\n \n-libsframe_la_SOURCES = sframe.c sframe-error.c\n+libsframe_la_SOURCES = sframe.c sframe-dump.c sframe-error.c\n libsframe_la_CPPFLAGS = $(AM_CPPFLAGS)\n \n include testsuite/local.mk\ndiff --git a/libsframe/Makefile.in b/libsframe/Makefile.in\nindex 2d1ea896471..340bfe88060 100644\n--- a/libsframe/Makefile.in\n+++ b/libsframe/Makefile.in\n@@ -149,7 +149,7 @@ am__installdirs = \"$(DESTDIR)$(libdir)\" \"$(DESTDIR)$(includedir)\"\n LTLIBRARIES = $(lib_LTLIBRARIES) $(noinst_LTLIBRARIES)\n libsframe_la_LIBADD =\n am_libsframe_la_OBJECTS = libsframe_la-sframe.lo \\\n-\tlibsframe_la-sframe-error.lo\n+\tlibsframe_la-sframe-dump.lo libsframe_la-sframe-error.lo\n libsframe_la_OBJECTS = $(am_libsframe_la_OBJECTS)\n AM_V_lt = $(am__v_lt_@AM_V@)\n am__v_lt_ = $(am__v_lt_@AM_DEFAULT_V@)\n@@ -427,7 +427,7 @@ AM_CFLAGS = @ac_libsframe_warn_cflags@\n @INSTALL_LIBBFD_FALSE@include_HEADERS = \n @INSTALL_LIBBFD_TRUE@include_HEADERS = $(INCDIR)/sframe.h $(INCDIR)/sframe-api.h\n @INSTALL_LIBBFD_FALSE@noinst_LTLIBRARIES = libsframe.la\n-libsframe_la_SOURCES = sframe.c sframe-error.c\n+libsframe_la_SOURCES = sframe.c sframe-dump.c sframe-error.c\n libsframe_la_CPPFLAGS = $(AM_CPPFLAGS)\n \n # Setup the testing framework\n@@ -607,6 +607,7 @@ mostlyclean-compile:\n distclean-compile:\n \t-rm -f *.tab.c\n \n+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libsframe_la-sframe-dump.Plo@am__quote@\n @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libsframe_la-sframe-error.Plo@am__quote@\n @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libsframe_la-sframe.Plo@am__quote@\n @AMDEP_TRUE@@am__include@ @am__quote@testsuite/libsframe.decode/$(DEPDIR)/testsuite_libsframe_decode_be_flipping-be-flipping.Po@am__quote@\n@@ -645,6 +646,13 @@ libsframe_la-sframe.lo: sframe.c\n @AMDEP_TRUE@@am__fastdepCC_FALSE@\tDEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@\n @am__fastdepCC_FALSE@\t$(AM_V_CC@am__nodep@)$(LIBTOOL) $(AM_V_lt) --tag=CC $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libsframe_la_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -c -o libsframe_la-sframe.lo `test -f 'sframe.c' || echo '$(srcdir)/'`sframe.c\n \n+libsframe_la-sframe-dump.lo: sframe-dump.c\n+@am__fastdepCC_TRUE@\t$(AM_V_CC)$(LIBTOOL) $(AM_V_lt) --tag=CC $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libsframe_la_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -MT libsframe_la-sframe-dump.lo -MD -MP -MF $(DEPDIR)/libsframe_la-sframe-dump.Tpo -c -o libsframe_la-sframe-dump.lo `test -f 'sframe-dump.c' || echo '$(srcdir)/'`sframe-dump.c\n+@am__fastdepCC_TRUE@\t$(AM_V_at)$(am__mv) $(DEPDIR)/libsframe_la-sframe-dump.Tpo $(DEPDIR)/libsframe_la-sframe-dump.Plo\n+@AMDEP_TRUE@@am__fastdepCC_FALSE@\t$(AM_V_CC)source='sframe-dump.c' object='libsframe_la-sframe-dump.lo' libtool=yes @AMDEPBACKSLASH@\n+@AMDEP_TRUE@@am__fastdepCC_FALSE@\tDEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@\n+@am__fastdepCC_FALSE@\t$(AM_V_CC@am__nodep@)$(LIBTOOL) $(AM_V_lt) --tag=CC $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libsframe_la_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -c -o libsframe_la-sframe-dump.lo `test -f 'sframe-dump.c' || echo '$(srcdir)/'`sframe-dump.c\n+\n libsframe_la-sframe-error.lo: sframe-error.c\n @am__fastdepCC_TRUE@\t$(AM_V_CC)$(LIBTOOL) $(AM_V_lt) --tag=CC $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libsframe_la_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -MT libsframe_la-sframe-error.lo -MD -MP -MF $(DEPDIR)/libsframe_la-sframe-error.Tpo -c -o libsframe_la-sframe-error.lo `test -f 'sframe-error.c' || echo '$(srcdir)/'`sframe-error.c\n @am__fastdepCC_TRUE@\t$(AM_V_at)$(am__mv) $(DEPDIR)/libsframe_la-sframe-error.Tpo $(DEPDIR)/libsframe_la-sframe-error.Plo\ndiff --git a/libsframe/sframe-dump.c b/libsframe/sframe-dump.c\nnew file mode 100644\nindex 00000000000..5b063c9962d\n--- /dev/null\n+++ b/libsframe/sframe-dump.c\n@@ -0,0 +1,181 @@\n+/* sframe-dump.c - Textual dump of .sframe.\n+\n+ Copyright (C) 2022 Free Software Foundation, Inc.\n+\n+ his file is part of libsframe.\n+\n+ This program is free software; you can redistribute it and/or modify\n+ it under the terms of the GNU General Public License as published by\n+ the Free Software Foundation; either version 3 of the License, or\n+ (at your option) any later version.\n+\n+ This program is distributed in the hope that it will be useful,\n+ but WITHOUT ANY WARRANTY; without even the implied warranty of\n+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n+ GNU General Public License for more details.\n+\n+ You should have received a copy of the GNU General Public License\n+ along with this program. If not, see . */\n+\n+#include \n+#include \n+#include \n+#include \n+#include \"sframe-impl.h\"\n+\n+#define SFRAME_HEADER_FLAGS_STR_MAX_LEN 50\n+\n+static void\n+dump_sframe_header (sframe_decoder_ctx *sfd_ctx)\n+{\n+ const char *verstr = NULL;\n+ const sframe_header *header = &(sfd_ctx->sfd_header);\n+\n+ /* Prepare SFrame section version string. */\n+ const char *version_names[]\n+ = { \"NULL\",\n+\t\"SFRAME_VERSION_1\" };\n+ unsigned char ver = header->sfh_preamble.sfp_version;\n+ if (ver <= SFRAME_VERSION)\n+ verstr = version_names[ver];\n+\n+ /* Prepare SFrame section flags string. */\n+ unsigned char flags = header->sfh_preamble.sfp_flags;\n+ char *flags_str\n+ = (char*) calloc (sizeof (char), SFRAME_HEADER_FLAGS_STR_MAX_LEN);\n+ if (flags)\n+ {\n+ const char *flag_names[]\n+\t= { \"SFRAME_F_FDE_SORTED\",\n+\t \"SFRAME_F_FRAME_POINTER\" };\n+ unsigned char flags = header->sfh_preamble.sfp_flags;\n+ if (flags & SFRAME_F_FDE_SORTED)\n+\tstrcpy (flags_str, flag_names[0]);\n+ if (flags & SFRAME_F_FRAME_POINTER)\n+\t{\n+\t if (strlen (flags_str) > 0)\n+\t strcpy (flags_str, \",\");\n+\t strcpy (flags_str, flag_names[1]);\n+\t}\n+ }\n+ else\n+ strcpy (flags_str, \"NONE\");\n+\n+ const char* subsec_name = \"Header\";\n+ printf (\"\\n\");\n+ printf (\" %s :\\n\", subsec_name);\n+ printf (\"\\n\");\n+ printf (\" Version: %s\\n\", verstr);\n+ printf (\" Flags: %s\\n\", flags_str);\n+ printf (\" Num FDEs: %d\\n\", header->sfh_num_fdes);\n+ printf (\" Num FREs: %d\\n\", header->sfh_num_fres);\n+\n+ free (flags_str);\n+}\n+\n+static void\n+dump_sframe_func_with_fres (sframe_decoder_ctx *sfd_ctx,\n+\t\t\t unsigned int funcidx,\n+\t\t\t uint64_t sec_addr)\n+{\n+ uint32_t j = 0;\n+ uint32_t num_fres = 0;\n+ uint32_t func_size = 0;\n+ int32_t func_start_address = 0;\n+ unsigned char func_info = 0;\n+\n+ uint64_t func_start_pc_vma = 0;\n+ uint64_t fre_start_pc_vma = 0;\n+ const char *base_reg_str[] = {\"fp\", \"sp\"};\n+ int32_t cfa_offset = 0;\n+ int32_t fp_offset = 0;\n+ int32_t ra_offset = 0;\n+ unsigned int base_reg_id = 0;\n+ int err[3] = {0, 0, 0};\n+\n+ sframe_frame_row_entry fre;\n+\n+ /* Get the SFrame function descriptor. */\n+ sframe_decoder_get_funcdesc (sfd_ctx, funcidx, &num_fres,\n+\t\t\t &func_size, &func_start_address, &func_info);\n+ /* Calculate the virtual memory address for function start pc. */\n+ func_start_pc_vma = func_start_address + sec_addr;\n+\n+ /* Mark FDEs with [m] where the FRE start address is interpreted as a\n+ mask. */\n+ int fde_type_addrmask_p = (SFRAME_V1_FUNC_FDE_TYPE (func_info)\n+\t\t\t == SFRAME_FDE_TYPE_PCMASK);\n+ const char *fde_type_marker\n+ = (fde_type_addrmask_p ? \"[m]\" : \" \");\n+\n+ printf (\"\\n func idx [%d]: pc = 0x%\"PRIx64 \", size = %d bytes\",\n+\t funcidx,\n+\t func_start_pc_vma,\n+\t func_size);\n+\n+ char temp[100];\n+ memset (temp, 0, 100);\n+\n+ printf (\"\\n %-7s%-8s %-10s%-10s%-10s\", \"STARTPC\", fde_type_marker, \"CFA\", \"FP\", \"RA\");\n+ for (j = 0; j < num_fres; j++)\n+ {\n+ sframe_decoder_get_fre (sfd_ctx, funcidx, j, &fre);\n+\n+ fre_start_pc_vma = (fde_type_addrmask_p\n+\t\t\t ? fre.fre_start_addr\n+\t\t\t : func_start_pc_vma + fre.fre_start_addr);\n+\n+ /* FIXME - fixup the err caching in array.\n+\t assert no error for base reg id. */\n+ base_reg_id = sframe_fre_get_base_reg_id (&fre, &err[0]);\n+ cfa_offset = sframe_fre_get_cfa_offset (sfd_ctx, &fre, &err[0]);\n+ fp_offset = sframe_fre_get_fp_offset (sfd_ctx, &fre, &err[1]);\n+ ra_offset = sframe_fre_get_ra_offset (sfd_ctx, &fre, &err[2]);\n+\n+ /* Dump CFA info. */\n+ printf (\"\\n\");\n+ printf (\" %016\"PRIx64, fre_start_pc_vma);\n+ sprintf (temp, \"%s+%d\", base_reg_str[base_reg_id], cfa_offset);\n+ printf (\" %-10s\", temp);\n+\ 100 42148 100 41994 100 154 836k 3142 --:--:-- --:--:-- --:--:-- 840k n+ /* Dump SP/FP info. */\n+ memset (temp, 0, 100);\n+ if (err[1] == 0)\n+\tsprintf (temp, \"c%+d\", fp_offset);\n+ else\n+\tstrcpy (temp, \"u\");\n+ printf (\"%-10s\", temp);\n+\n+ /* Dump RA info. */\n+ memset (temp, 0, 100);\n+ if (err[2] == 0)\n+\tsprintf (temp, \"c%+d\", ra_offset);\n+ else\n+\tstrcpy (temp, \"u\");\n+ printf (\"%-10s\", temp);\n+ }\n+}\n+\n+static void\n+dump_sframe_functions (sframe_decoder_ctx *sfd_ctx, uint64_t sec_addr)\n+{\n+ uint32_t i;\n+ uint32_t num_fdes;\n+\n+ const char* subsec_name = \"Function Index\";\n+ printf (\"\\n %s :\\n\", subsec_name);\n+\n+ num_fdes = sframe_decoder_get_num_fidx (sfd_ctx);\n+ for (i = 0; i < num_fdes; i++)\n+ {\n+ dump_sframe_func_with_fres (sfd_ctx, i, sec_addr);\n+ printf (\"\\n\");\n+ }\n+}\n+\n+void\n+dump_sframe (sframe_decoder_ctx *sfd_ctx, uint64_t sec_addr)\n+{\n+ dump_sframe_header (sfd_ctx);\n+ dump_sframe_functions (sfd_ctx, sec_addr);\n+}\n","prefixes":["V3","07/15"]}+ exit 1 Build step 'Execute shell' marked build as failure Finished: FAILURE