Started by user snail Running as SYSTEM [EnvInject] - Loading node environment variables. Building remotely on docker-jenkins-agent in workspace /home/jenkins/agent/workspace/binutils-gdb [WS-CLEANUP] Deleting project workspace... [WS-CLEANUP] Deferred wipeout is used... [WS-CLEANUP] Done The recommended git tool is: NONE using credential 0adb5fc7-caa2-429d-97d2-c7fa2fa1d884 Cloning the remote Git repository Using shallow clone with depth 1 Avoid fetching tags Cloning repository git@github.com:wangliu-iscas/binutils-gdb.git/ > git init /home/jenkins/agent/workspace/binutils-gdb # timeout=10 Fetching upstream changes from git@github.com:wangliu-iscas/binutils-gdb.git/ > git --version # timeout=10 > git --version # 'git version 2.37.2' using GIT_SSH to set credentials patchwork github wangliu-iscas git ssh key Verifying host key using known hosts file, will automatically accept unseen keys > git fetch --no-tags --force --progress --depth=1 -- git@github.com:wangliu-iscas/binutils-gdb.git/ +refs/heads/*:refs/remotes/origin/* # timeout=10 > git config remote.origin.url git@github.com:wangliu-iscas/binutils-gdb.git/ # timeout=10 > git config --add remote.origin.fetch +refs/heads/*:refs/remotes/origin/* # timeout=10 Avoid second fetch > git rev-parse refs/remotes/origin/master^{commit} # timeout=10 Checking out Revision bb98553cad4e017f1851153fa5de91f2cee98fb2 (refs/remotes/origin/master) > git config core.sparsecheckout # timeout=10 > git checkout -f bb98553cad4e017f1851153fa5de91f2cee98fb2 # timeout=10 Commit message: "PowerPC: Add support for RFC02658 - MMA+ Outer-Product Instructions" > git rev-list --no-walk a09f33be653fb112586be126f3d5ab848aaed095 # timeout=10 First time build. Skipping changelog. [EnvInject] - Mask passwords that will be passed as build parameters. [EnvInject] - Executing scripts and injecting environment variables after the SCM step. [EnvInject] - Injecting as environment variables the properties content GITHUB_REPO=https://github.com/wangliu-iscas/ PATCHWORK_URL=https://patchwork.plctlab.org [EnvInject] - Variables injected successfully. [binutils-gdb] $ /usr/bin/env bash /tmp/jenkins537921939128304312.sh + git config pw.server https://patchwork.plctlab.org/api/1.2/ + git config pw.project binutils-gdb + git config pw.token [*******] ++ date +%Y-%m + now_date=2022-10 ++ date +%Y + now_date_year=2022 + bundle_name=binutils-gdb_2022-10 ++ curl -s -H 'Authorization: Token [*******]' 'https://patchwork.plctlab.org/api/1.2/bundles/?project=binutils-gdb&per_page=999' + bundle_response='[{"id":6,"url":"https://patchwork.plctlab.org/api/1.2/bundles/6/","web_url":"https://patchwork.plctlab.org/bundle/patchwork-bot/binutils-gdb_2022-10/","project":{"id":2,"url":"https://patchwork.plctlab.org/api/1.2/projects/2/","name":"binutils-gdb","link_name":"binutils-gdb","list_id":"binutils.sourceware.org","list_email":"binutils@sourceware.org","web_url":"https://sourceware.org/mailman/listinfo/binutils","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"name":"binutils-gdb_2022-10","owner":{"id":3,"url":"https://patchwork.plctlab.org/api/1.2/users/3/","username":"patchwork-bot","first_name":"","last_name":"","email":"ouuuleilei@gmail.com"},"patches":[{"id":1592,"url":"https://patchwork.plctlab.org/api/1.2/patches/1592/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/385d01fd-7e57-1f3f-1bae-30aa0c313d63@suse.com/","msgid":"<385d01fd-7e57-1f3f-1bae-30aa0c313d63@suse.com>","list_archive_url":null,"date":"2022-09-30T11:59:45","name":"[3/4] RISC-V/gas: don'\''t open-code insn_length()","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/385d01fd-7e57-1f3f-1bae-30aa0c313d63@suse.com/mbox/"},{"id":1594,"url":"https://patchwork.plctlab.org/api/1.2/patches/1594/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f5757acf-7b90-a0e3-5eea-3b97cc226930@suse.com/","msgid":"","list_archive_url":null,"date":"2022-09-30T12:00:12","name":"[4/4] RISC-V/gas: allow generating up to 176-bit instructions with .insn","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f5757acf-7b90-a0e3-5eea-3b97cc226930@suse.com/mbox/"},{"id":1596,"url":"https://patchwork.plctlab.org/api/1.2/patches/1596/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930140503.38233-1-chigot@adacore.com/","msgid":"<20220930140503.38233-1-chigot@adacore.com>","list_archive_url":null,"date":"2022-09-30T14:05:03","name":"ld/testsuite: consistently add board_ldflags when linking with GCC","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930140503.38233-1-chigot@adacore.com/mbox/"},{"id":1619,"url":"https://patchwork.plctlab.org/api/1.2/patches/1619/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221001014451.532772-1-maskray@google.com/","msgid":"<20221001014451.532772-1-maskray@google.com>","list_archive_url":null,"date":"2022-10-01T01:44:51","name":"gold, dwp: support zstd compressed input debug sections [PR 29641]","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221001014451.532772-1-maskray@google.com/mbox/"},{"id":1620,"url":"https://patchwork.plctlab.org/api/1.2/patches/1620/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221001023846.590825-1-maskray@google.com/","msgid":"<20221001023846.590825-1-maskray@google.com>","list_archive_url":null,"date":"2022-10-01T02:38:46","name":"gold: add --compress-debug-sections=zstd [PR 29641]","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221001023846.590825-1-maskray@google.com/mbox/"},{"id":1623,"url":"https://patchwork.plctlab.org/api/1.2/patches/1623/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b4477c7f666bdeb7f8e998633c7b0cb62310b9ef.1664599545.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-01T04:45:52","name":"[RFC,1/1] RISC-V: Implement common register pair framework","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b4477c7f666bdeb7f8e998633c7b0cb62310b9ef.1664599545.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1625,"url":"https://patchwork.plctlab.org/api/1.2/patches/1625/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/53a265a1f14d17a6f7b106082f610994c5d546e0.1664602025.git.research_trasio@irq.a4lg.com/","msgid":"<53a265a1f14d17a6f7b106082f610994c5d546e0.1664602025.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-01T05:27:31","name":"[RFC,1/1] RISC-V: Implement extension variants","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/53a265a1f14d17a6f7b106082f610994c5d546e0.1664602025.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1626,"url":"https://patchwork.plctlab.org/api/1.2/patches/1626/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8db04962aba9c780f133840a8934353a58f223fe.1664602716.git.research_trasio@irq.a4lg.com/","msgid":"<8db04962aba9c780f133840a8934353a58f223fe.1664602716.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-01T05:39:26","name":"[1/1] RISC-V: Move supervisor instructions after all unprivileged ones","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8db04962aba9c780f133840a8934353a58f223fe.1664602716.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1627,"url":"https://patchwork.plctlab.org/api/1.2/patches/1627/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221001062057.681440-1-maskray@google.com/","msgid":"<20221001062057.681440-1-maskray@google.com>","list_archive_url":null,"date":"2022-10-01T06:20:57","name":"readelf: support zstd compressed debug sections [PR 29640]","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221001062057.681440-1-maskray@google.com/mbox/"},{"id":1631,"url":"https://patchwork.plctlab.org/api/1.2/patches/1631/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/619f112539c0bdecd58e25664f1250a3479a37f5.1664707612.git.aburgess@redhat.com/","msgid":"<619f112539c0bdecd58e25664f1250a3479a37f5.1664707612.git.aburgess@redhat.com>","list_archive_url":null,"date":"2022-10-02T10:47:52","name":"[PATCHv2,2/2] opcodes/arm: add disassembler styling for arm","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/619f112539c0bdecd58e25664f1250a3479a37f5.1664707612.git.aburgess@redhat.com/mbox/"},{"id":1635,"url":"https://patchwork.plctlab.org/api/1.2/patches/1635/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221002185433.gl7dvytfh5wthifx@lug-owl.de/","msgid":"<20221002185433.gl7dvytfh5wthifx@lug-owl.de>","list_archive_url":null,"date":"2022-10-02T18:54:33","name":"diagnostics.h: GCC 13 got -Wself-move, breaks GDB build","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221002185433.gl7dvytfh5wthifx@lug-owl.de/mbox/"},{"id":1637,"url":"https://patchwork.plctlab.org/api/1.2/patches/1637/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003014313.28766-1-mark@harmstone.com/","msgid":"<20221003014313.28766-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-03T01:43:12","name":"[1/2] ld: Add --pdb option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003014313.28766-1-mark@harmstone.com/mbox/"},{"id":1638,"url":"https://patchwork.plctlab.org/api/1.2/patches/1638/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003014313.28766-2-mark@harmstone.com/","msgid":"<20221003014313.28766-2-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-03T01:43:13","name":"[2/2] ld: Add minimal pdb generation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003014313.28766-2-mark@harmstone.com/mbox/"},{"id":1640,"url":"https://patchwork.plctlab.org/api/1.2/patches/1640/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/597ed978-d121-220c-b56b-2ffb94bd091c@suse.cz/","msgid":"<597ed978-d121-220c-b56b-2ffb94bd091c@suse.cz>","list_archive_url":null,"date":"2022-10-03T07:50:38","name":"[1/2] refactor usage of compressed_debug_section_type","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/597ed978-d121-220c-b56b-2ffb94bd091c@suse.cz/mbox/"},{"id":1641,"url":"https://patchwork.plctlab.org/api/1.2/patches/1641/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b8acdd83-f33a-74b8-e21a-23719a0b1a60@suse.cz/","msgid":"","list_archive_url":null,"date":"2022-10-03T07:50:44","name":"[2/2] add --enable-default-compressed-debug-sections-algorithm configure option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b8acdd83-f33a-74b8-e21a-23719a0b1a60@suse.cz/mbox/"},{"id":1642,"url":"https://patchwork.plctlab.org/api/1.2/patches/1642/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003101328.1790113-1-aburgess@redhat.com/","msgid":"<20221003101328.1790113-1-aburgess@redhat.com>","list_archive_url":null,"date":"2022-10-03T10:13:28","name":"opcodes/riscv: style csr names as registers","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003101328.1790113-1-aburgess@redhat.com/mbox/"},{"id":1643,"url":"https://patchwork.plctlab.org/api/1.2/patches/1643/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7ba14fc4472ce97d4f7a4433cad8a571e89f82f4.1664793840.git.research_trasio@irq.a4lg.com/","msgid":"<7ba14fc4472ce97d4f7a4433cad8a571e89f82f4.1664793840.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-03T10:43:59","name":"[v3,1/6] RISC-V: Fix immediates to have \"immediate\" style","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7ba14fc4472ce97d4f7a4433cad8a571e89f82f4.1664793840.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1644,"url":"https://patchwork.plctlab.org/api/1.2/patches/1644/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a498bec37c1fd1dcda57cbf95e5f8cfba09b31d3.1664793840.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-03T10:44:00","name":"[v3,2/6] RISC-V: Fix printf argument types corresponding %x","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a498bec37c1fd1dcda57cbf95e5f8cfba09b31d3.1664793840.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1647,"url":"https://patchwork.plctlab.org/api/1.2/patches/1647/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0002ea716713ace4998a33dde0b81f4f890d10bf.1664793840.git.research_trasio@irq.a4lg.com/","msgid":"<0002ea716713ace4998a33dde0b81f4f890d10bf.1664793840.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-03T10:44:01","name":"[v3,3/6] RISC-V: Optimize riscv_disassemble_data printf","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0002ea716713ace4998a33dde0b81f4f890d10bf.1664793840.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1646,"url":"https://patchwork.plctlab.org/api/1.2/patches/1646/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c65fc3e9aa58965d6768a28c9fd7467fea9897a5.1664793840.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-03T10:44:02","name":"[v3,4/6] RISC-V: Print comma and tabs as the \"text\" style","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c65fc3e9aa58965d6768a28c9fd7467fea9897a5.1664793840.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1648,"url":"https://patchwork.plctlab.org/api/1.2/patches/1648/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5abe1d8a7694417b990e11d8f6cd6789573872e5.1664793840.git.research_trasio@irq.a4lg.com/","msgid":"<5abe1d8a7694417b990e11d8f6cd6789573872e5.1664793840.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-03T10:44:03","name":"[v3,5/6] RISC-V: Fix T-Head immediate types on printing","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5abe1d8a7694417b990e11d8f6cd6789573872e5.1664793840.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1649,"url":"https://patchwork.plctlab.org/api/1.2/patches/1649/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0b68af932117258c908db62cf87c3a15d3cdec41.1664793840.git.research_trasio@irq.a4lg.com/","msgid":"<0b68af932117258c908db62cf87c3a15d3cdec41.1664793840.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-03T10:44:04","name":"[v3,6/6] RISC-V: Print XTheadMemPair literal as \"immediate\"","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0b68af932117258c908db62cf87c3a15d3cdec41.1664793840.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1656,"url":"https://patchwork.plctlab.org/api/1.2/patches/1656/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/87lepxcd6x.fsf@redhat.com/","msgid":"<87lepxcd6x.fsf@redhat.com>","list_archive_url":null,"date":"2022-10-03T12:19:02","name":"Commit: readelf: Do not load section data from offset 0","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/87lepxcd6x.fsf@redhat.com/mbox/"},{"id":1659,"url":"https://patchwork.plctlab.org/api/1.2/patches/1659/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e0d369d419da9c0441f415da7f54352aead8f655.1664707612.git.aburgess@redhat.com/","msgid":"","list_archive_url":null,"date":"2022-10-03T16:37:36","name":"[PATCHv2,1/2] opcodes/arm: use '\''@'\'' consistently for the comment character","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e0d369d419da9c0441f415da7f54352aead8f655.1664707612.git.aburgess@redhat.com/mbox/"},{"id":1660,"url":"https://patchwork.plctlab.org/api/1.2/patches/1660/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003165848.11142-1-palmer@rivosinc.com/","msgid":"<20221003165848.11142-1-palmer@rivosinc.com>","list_archive_url":null,"date":"2022-10-03T16:58:48","name":"gas: NEWS: Mention the T-Head extensions that were recently added","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003165848.11142-1-palmer@rivosinc.com/mbox/"},{"id":1671,"url":"https://patchwork.plctlab.org/api/1.2/patches/1671/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/YzvrMEdkXjIn5Lfz@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-04T08:13:36","name":"Support objcopy changing compression to or from zstd","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/YzvrMEdkXjIn5Lfz@squeak.grove.modra.org/mbox/"},{"id":1673,"url":"https://patchwork.plctlab.org/api/1.2/patches/1673/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0bc857d306bb7c8130e5328dbe6b9ed2fed3ef87.1664873933.git.research_trasio@irq.a4lg.com/","msgid":"<0bc857d306bb7c8130e5328dbe6b9ed2fed3ef87.1664873933.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-04T08:59:07","name":"[1/2] RISC-V: Fix buffer overflow on print_insn_riscv","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0bc857d306bb7c8130e5328dbe6b9ed2fed3ef87.1664873933.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1672,"url":"https://patchwork.plctlab.org/api/1.2/patches/1672/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/89612fe01d902007bf84a7dfb0df5f85d5c166e4.1664873933.git.research_trasio@irq.a4lg.com/","msgid":"<89612fe01d902007bf84a7dfb0df5f85d5c166e4.1664873933.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-04T08:59:08","name":"[2/2] gdb/riscv: Fix buffer overflow on riscv_insn::fetch_instruction","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/89612fe01d902007bf84a7dfb0df5f85d5c166e4.1664873933.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1676,"url":"https://patchwork.plctlab.org/api/1.2/patches/1676/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fc849c94f4adcac1c4ccc5508c7a145a2f13b2a9.1664876744.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-04T09:45:49","name":"[v2,1/2] RISC-V: Fix buffer overflow on print_insn_riscv","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fc849c94f4adcac1c4ccc5508c7a145a2f13b2a9.1664876744.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1677,"url":"https://patchwork.plctlab.org/api/1.2/patches/1677/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4eb6e59ae2e790dbbf2bc92477edd281648d8814.1664876744.git.research_trasio@irq.a4lg.com/","msgid":"<4eb6e59ae2e790dbbf2bc92477edd281648d8814.1664876744.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-04T09:45:50","name":"[v2,2/2] gdb/riscv: Partial support for instructions up to 176-bits","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4eb6e59ae2e790dbbf2bc92477edd281648d8814.1664876744.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1678,"url":"https://patchwork.plctlab.org/api/1.2/patches/1678/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ebf16f9e1f45115d0793952ccb4a94d4233303f9.1664882725.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-04T11:25:56","name":"[v3,1/2] RISC-V: Fix buffer overflow on print_insn_riscv","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ebf16f9e1f45115d0793952ccb4a94d4233303f9.1664882725.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1679,"url":"https://patchwork.plctlab.org/api/1.2/patches/1679/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/83464b09b8649525259c69c853dfa2c9575a204b.1664882725.git.research_trasio@irq.a4lg.com/","msgid":"<83464b09b8649525259c69c853dfa2c9575a204b.1664882725.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-04T11:25:57","name":"[v3,2/2] gdb/riscv: Partial support for instructions up to 176-bit","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/83464b09b8649525259c69c853dfa2c9575a204b.1664882725.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1681,"url":"https://patchwork.plctlab.org/api/1.2/patches/1681/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ffa9c1d7-e8c2-a62b-ef3e-b565c0ffbe5b@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-04T13:56:27","name":"RISC-V: Zicbo{m,p,z} adjustments to riscv_multi_subset_supports_ext()","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ffa9c1d7-e8c2-a62b-ef3e-b565c0ffbe5b@suse.com/mbox/"},{"id":1690,"url":"https://patchwork.plctlab.org/api/1.2/patches/1690/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221004161720.1963953-1-vladimir.mezentsev@oracle.com/","msgid":"<20221004161720.1963953-1-vladimir.mezentsev@oracle.com>","list_archive_url":null,"date":"2022-10-04T16:17:20","name":"gprofng: fix build with --enable-pgo-build=lto","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221004161720.1963953-1-vladimir.mezentsev@oracle.com/mbox/"},{"id":1691,"url":"https://patchwork.plctlab.org/api/1.2/patches/1691/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c0211bc9c57be6c79c6d878ce147f63b657f461d.camel@espressif.com/","msgid":"","list_archive_url":null,"date":"2022-10-04T16:22:05","name":"bfd: xtensa: fix __stop_SECTION literal drop,","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c0211bc9c57be6c79c6d878ce147f63b657f461d.camel@espressif.com/mbox/"},{"id":1702,"url":"https://patchwork.plctlab.org/api/1.2/patches/1702/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5f482299-6c60-b2b3-9abe-f4a55a5a26c5@univ-grenoble-alpes.fr/","msgid":"<5f482299-6c60-b2b3-9abe-f4a55a5a26c5@univ-grenoble-alpes.fr>","list_archive_url":null,"date":"2022-10-04T20:03:20","name":"[RFC] bfd: use bfd_vma for the 64-bit version of put[lb] and get[lb]","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5f482299-6c60-b2b3-9abe-f4a55a5a26c5@univ-grenoble-alpes.fr/mbox/"},{"id":1711,"url":"https://patchwork.plctlab.org/api/1.2/patches/1711/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Yz0Gsxdxe0TePbJT@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-05T04:23:15","name":"PR29647, objdump -S looping","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Yz0Gsxdxe0TePbJT@squeak.grove.modra.org/mbox/"},{"id":1712,"url":"https://patchwork.plctlab.org/api/1.2/patches/1712/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/02d747d2-f57b-0fb5-b893-842b6cc41f2f@suse.com/","msgid":"<02d747d2-f57b-0fb5-b893-842b6cc41f2f@suse.com>","list_archive_url":null,"date":"2022-10-05T07:20:47","name":"[v3,1/7] x86: constify parse_insn()'\''s input","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/02d747d2-f57b-0fb5-b893-842b6cc41f2f@suse.com/mbox/"},{"id":1713,"url":"https://patchwork.plctlab.org/api/1.2/patches/1713/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/925cb740-4e1b-abc4-8526-aaab6faae5e1@suse.com/","msgid":"<925cb740-4e1b-abc4-8526-aaab6faae5e1@suse.com>","list_archive_url":null,"date":"2022-10-05T07:22:19","name":"[v3,2/7] x86: introduce Pass2 insn attribute","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/925cb740-4e1b-abc4-8526-aaab6faae5e1@suse.com/mbox/"},{"id":1714,"url":"https://patchwork.plctlab.org/api/1.2/patches/1714/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e16d3e78-39ca-f715-508f-a4104b8ab9a9@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-05T07:23:51","name":"[v3,3/7] x86: re-work insn/suffix recognition","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e16d3e78-39ca-f715-508f-a4104b8ab9a9@suse.com/mbox/"},{"id":1715,"url":"https://patchwork.plctlab.org/api/1.2/patches/1715/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e4e4b80b-794c-7485-1997-685adab8fb27@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-05T07:24:20","name":"[v3,4/7] x86-64: further re-work insn/suffix recognition to also cover MOVSL","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e4e4b80b-794c-7485-1997-685adab8fb27@suse.com/mbox/"},{"id":1716,"url":"https://patchwork.plctlab.org/api/1.2/patches/1716/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/540678fc-8bff-ec68-c97c-478d2631998c@suse.com/","msgid":"<540678fc-8bff-ec68-c97c-478d2631998c@suse.com>","list_archive_url":null,"date":"2022-10-05T07:24:55","name":"[v3,5/7] ix86: don'\''t recognize/derive Q suffix in the common case","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/540678fc-8bff-ec68-c97c-478d2631998c@suse.com/mbox/"},{"id":1718,"url":"https://patchwork.plctlab.org/api/1.2/patches/1718/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e4692495-7d3d-074d-14f9-364d4a9a998c@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-05T07:25:25","name":"[v3,6/7] x86-64: allow HLE store of accumulator to absolute 32-bit address","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e4692495-7d3d-074d-14f9-364d4a9a998c@suse.com/mbox/"},{"id":1717,"url":"https://patchwork.plctlab.org/api/1.2/patches/1717/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e8014ebd-d16b-17a7-9f34-3700fc164136@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-05T07:25:57","name":"[v3,7/7] x86: move bad-use-of-TLS-reloc check","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e8014ebd-d16b-17a7-9f34-3700fc164136@suse.com/mbox/"},{"id":1719,"url":"https://patchwork.plctlab.org/api/1.2/patches/1719/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1266f001-4511-2662-dba9-14b4d0317c57@suse.com/","msgid":"<1266f001-4511-2662-dba9-14b4d0317c57@suse.com>","list_archive_url":null,"date":"2022-10-05T07:40:50","name":"x86: drop \"regmask\" static variable","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1266f001-4511-2662-dba9-14b4d0317c57@suse.com/mbox/"},{"id":1751,"url":"https://patchwork.plctlab.org/api/1.2/patches/1751/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/af45c5d57c221e43101c2aa38b14f4b4ac12d011.1665031170.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-06T04:40:15","name":"[v2,1/2] RISC-V: Fallback for instructions longer than 64b","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/af45c5d57c221e43101c2aa38b14f4b4ac12d011.1665031170.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1752,"url":"https://patchwork.plctlab.org/api/1.2/patches/1752/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c6e55781245dd3e8e9b8debd6130fc5449dfbd55.1665031170.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-06T04:40:16","name":"[v2,2/2] RISC-V: Improve \"bits undefined\" diagnostics","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c6e55781245dd3e8e9b8debd6130fc5449dfbd55.1665031170.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1776,"url":"https://patchwork.plctlab.org/api/1.2/patches/1776/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d52952119e15357c0e823f8a2398999359588b4d.1665050099.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-06T09:56:30","name":"[v3,1/2] RISC-V: Fallback for instructions longer than 64b","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d52952119e15357c0e823f8a2398999359588b4d.1665050099.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1777,"url":"https://patchwork.plctlab.org/api/1.2/patches/1777/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d907b1997f60ff7823c4a23e281ec9d8ddcbf3f1.1665050099.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-06T09:56:31","name":"[v3,2/2] RISC-V: Improve \"bits undefined\" diagnostics","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d907b1997f60ff7823c4a23e281ec9d8ddcbf3f1.1665050099.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1781,"url":"https://patchwork.plctlab.org/api/1.2/patches/1781/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221006114628.304185-1-chigot@adacore.com/","msgid":"<20221006114628.304185-1-chigot@adacore.com>","list_archive_url":null,"date":"2022-10-06T11:46:28","name":"RISC-V: fix linker message when relaxation deletes bytes","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221006114628.304185-1-chigot@adacore.com/mbox/"},{"id":1801,"url":"https://patchwork.plctlab.org/api/1.2/patches/1801/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Yz+Yhyg7UewC9/kp@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-07T03:09:59","name":"PR29653, objcopy/strip: fuzzed small input file induces large output file","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Yz+Yhyg7UewC9/kp@squeak.grove.modra.org/mbox/"},{"id":1803,"url":"https://patchwork.plctlab.org/api/1.2/patches/1803/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/PH1P110MB16505D9D39EC5B1DE22FE3D5EC5F9@PH1P110MB1650.NAMP110.PROD.OUTLOOK.COM/","msgid":"","list_archive_url":null,"date":"2022-10-07T04:10:07","name":"@CPP_FOR_BUILD@ problem since binutils-2.38","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/PH1P110MB16505D9D39EC5B1DE22FE3D5EC5F9@PH1P110MB1650.NAMP110.PROD.OUTLOOK.COM/mbox/"},{"id":1827,"url":"https://patchwork.plctlab.org/api/1.2/patches/1827/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8e13bce108ac10a0c1dd911e23ec572926f7ae44.1665203374.git.research_trasio@irq.a4lg.com/","msgid":"<8e13bce108ac10a0c1dd911e23ec572926f7ae44.1665203374.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-08T04:29:53","name":"[v2,1/1] RISC-V: Test DWARF register numbers for \"fp\"","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8e13bce108ac10a0c1dd911e23ec572926f7ae44.1665203374.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1828,"url":"https://patchwork.plctlab.org/api/1.2/patches/1828/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0883001b3572e54d3fba264429c7ade2adb66610.1665203441.git.research_trasio@irq.a4lg.com/","msgid":"<0883001b3572e54d3fba264429c7ade2adb66610.1665203441.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-08T04:31:15","name":"[1/1] RISC-V: Move standard hints before all instructions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0883001b3572e54d3fba264429c7ade2adb66610.1665203441.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1829,"url":"https://patchwork.plctlab.org/api/1.2/patches/1829/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/58e16a241d7376fcae2515c6bd5a2b41d275eeba.1665203531.git.research_trasio@irq.a4lg.com/","msgid":"<58e16a241d7376fcae2515c6bd5a2b41d275eeba.1665203531.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-08T04:32:18","name":"[RFC,1/1] RISC-V: Imply '\''Zicsr'\'' from privileged extensions with CSRs","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/58e16a241d7376fcae2515c6bd5a2b41d275eeba.1665203531.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1830,"url":"https://patchwork.plctlab.org/api/1.2/patches/1830/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/cb5076fc96e8f2097779a3abcde843dcdd660031.1665203660.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-08T04:34:23","name":"[1/5] opcodes/riscv-dis.c: Tidying with comments/clarity","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/cb5076fc96e8f2097779a3abcde843dcdd660031.1665203660.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1832,"url":"https://patchwork.plctlab.org/api/1.2/patches/1832/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1f1aa0838bf9c4f10a45fcfe3c682f7efc79d9ae.1665203660.git.research_trasio@irq.a4lg.com/","msgid":"<1f1aa0838bf9c4f10a45fcfe3c682f7efc79d9ae.1665203660.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-08T04:34:24","name":"[2/5] opcodes/riscv-dis.c: Tidying with spacing","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1f1aa0838bf9c4f10a45fcfe3c682f7efc79d9ae.1665203660.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1831,"url":"https://patchwork.plctlab.org/api/1.2/patches/1831/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/740bc5e2d2618d236519b39fedd1a1d7ae4e05da.1665203660.git.research_trasio@irq.a4lg.com/","msgid":"<740bc5e2d2618d236519b39fedd1a1d7ae4e05da.1665203660.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-08T04:34:25","name":"[3/5] opcodes/riscv-dis.c: Use bool type whenever possible","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/740bc5e2d2618d236519b39fedd1a1d7ae4e05da.1665203660.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1833,"url":"https://patchwork.plctlab.org/api/1.2/patches/1833/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6e3a9c235e317f441b4383b3daa68f2051bdc149.1665203660.git.research_trasio@irq.a4lg.com/","msgid":"<6e3a9c235e317f441b4383b3daa68f2051bdc149.1665203660.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-08T04:34:26","name":"[4/5] opcodes/riscv-dis.c: Make XLEN variable static","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6e3a9c235e317f441b4383b3daa68f2051bdc149.1665203660.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1834,"url":"https://patchwork.plctlab.org/api/1.2/patches/1834/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ad929233a62d887495122721340b2f9c80392963.1665203660.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-08T04:34:27","name":"[5/5] opcodes/riscv-dis.c: Remove last_map_state","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ad929233a62d887495122721340b2f9c80392963.1665203660.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1836,"url":"https://patchwork.plctlab.org/api/1.2/patches/1836/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d07e2b6f36ea2fd5830924a9bfeda941b774b687.1665290422.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-09T05:09:22","name":"RISC-V: Move certain arrays to riscv-opc.c","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d07e2b6f36ea2fd5830924a9bfeda941b774b687.1665290422.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1844,"url":"https://patchwork.plctlab.org/api/1.2/patches/1844/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010004623.16582-1-mark@harmstone.com/","msgid":"<20221010004623.16582-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-10T00:46:22","name":"[v2,1/2] ld: Add --pdb option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010004623.16582-1-mark@harmstone.com/mbox/"},{"id":1845,"url":"https://patchwork.plctlab.org/api/1.2/patches/1845/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010004623.16582-2-mark@harmstone.com/","msgid":"<20221010004623.16582-2-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-10T00:46:23","name":"[v2,2/2] ld: Add minimal pdb generation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010004623.16582-2-mark@harmstone.com/mbox/"},{"id":1890,"url":"https://patchwork.plctlab.org/api/1.2/patches/1890/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010200433.414320-1-vladimir.mezentsev@oracle.com/","msgid":"<20221010200433.414320-1-vladimir.mezentsev@oracle.com>","list_archive_url":null,"date":"2022-10-10T20:04:33","name":"gprofng: run tests without installation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010200433.414320-1-vladimir.mezentsev@oracle.com/mbox/"},{"id":1893,"url":"https://patchwork.plctlab.org/api/1.2/patches/1893/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010230426.719238-1-vladimir.mezentsev@oracle.com/","msgid":"<20221010230426.719238-1-vladimir.mezentsev@oracle.com>","list_archive_url":null,"date":"2022-10-10T23:04:26","name":"[2/2] gprofng: use the --libdir path to find libraries","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010230426.719238-1-vladimir.mezentsev@oracle.com/mbox/"},{"id":1894,"url":"https://patchwork.plctlab.org/api/1.2/patches/1894/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010235155.842469-1-vladimir.mezentsev@oracle.com/","msgid":"<20221010235155.842469-1-vladimir.mezentsev@oracle.com>","list_archive_url":null,"date":"2022-10-10T23:51:55","name":"[3/3] gprofng: no need to build version.texi","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010235155.842469-1-vladimir.mezentsev@oracle.com/mbox/"},{"id":1895,"url":"https://patchwork.plctlab.org/api/1.2/patches/1895/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011003702.4287-1-mark@harmstone.com/","msgid":"<20221011003702.4287-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-11T00:37:01","name":"[v3,1/2] ld: Add --pdb option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011003702.4287-1-mark@harmstone.com/mbox/"},{"id":1897,"url":"https://patchwork.plctlab.org/api/1.2/patches/1897/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011003702.4287-2-mark@harmstone.com/","msgid":"<20221011003702.4287-2-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-11T00:37:02","name":"[v3,2/2] ld: Add minimal pdb generation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011003702.4287-2-mark@harmstone.com/mbox/"},{"id":1928,"url":"https://patchwork.plctlab.org/api/1.2/patches/1928/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011175332.17156-1-mark@harmstone.com/","msgid":"<20221011175332.17156-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-11T17:53:31","name":"[v4,1/2] ld: Add --pdb option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011175332.17156-1-mark@harmstone.com/mbox/"},{"id":1929,"url":"https://patchwork.plctlab.org/api/1.2/patches/1929/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011175332.17156-2-mark@harmstone.com/","msgid":"<20221011175332.17156-2-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-11T17:53:32","name":"[v4,2/2] ld: Add minimal pdb generation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011175332.17156-2-mark@harmstone.com/mbox/"},{"id":1941,"url":"https://patchwork.plctlab.org/api/1.2/patches/1941/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221012031005.237446-1-simon.marchi@polymtl.ca/","msgid":"<20221012031005.237446-1-simon.marchi@polymtl.ca>","list_archive_url":null,"date":"2022-10-12T03:10:05","name":"[pushed] Re-apply \"Pass PKG_CONFIG_PATH down from top-level Makefile\"","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221012031005.237446-1-simon.marchi@polymtl.ca/mbox/"},{"id":1976,"url":"https://patchwork.plctlab.org/api/1.2/patches/1976/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1216a3f8-2273-8681-f528-9493a66891f0@suse.com/","msgid":"<1216a3f8-2273-8681-f528-9493a66891f0@suse.com>","list_archive_url":null,"date":"2022-10-13T08:16:49","name":"[v4,1/8] x86: constify parse_insn()'\''s input","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1216a3f8-2273-8681-f528-9493a66891f0@suse.com/mbox/"},{"id":1977,"url":"https://patchwork.plctlab.org/api/1.2/patches/1977/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/11599bbe-c779-aa9f-4d5d-c2243f0e69dc@suse.com/","msgid":"<11599bbe-c779-aa9f-4d5d-c2243f0e69dc@suse.com>","list_archive_url":null,"date":"2022-10-13T08:17:17","name":"[v4,2/8] x86: introduce Pass2 insn attribute","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/11599bbe-c779-aa9f-4d5d-c2243f0e69dc@suse.com/mbox/"},{"id":1978,"url":"https://patchwork.plctlab.org/api/1.2/patches/1978/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/357273a3-060c-23db-72da-3fc9d1be3d2a@suse.com/","msgid":"<357273a3-060c-23db-72da-3fc9d1be3d2a@suse.com>","list_archive_url":null,"date":"2022-10-13T08:18:09","name":"[v4,3/8] x86: re-work insn/suffix recognition","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/357273a3-060c-23db-72da-3fc9d1be3d2a@suse.com/mbox/"},{"id":1979,"url":"https://patchwork.plctlab.org/api/1.2/patches/1979/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0ec0587f-6a7b-45b6-8346-e5d774e73636@suse.com/","msgid":"<0ec0587f-6a7b-45b6-8346-e5d774e73636@suse.com>","list_archive_url":null,"date":"2022-10-13T08:18:39","name":"[v4,4/8] x86-64: further re-work insn/suffix recognition to also cover MOVSL","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0ec0587f-6a7b-45b6-8346-e5d774e73636@suse.com/mbox/"},{"id":1980,"url":"https://patchwork.plctlab.org/api/1.2/patches/1980/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fb617d0b-8759-3169-5a65-1178b7fef3d7@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-13T08:19:34","name":"[v4,5/8] ix86: don'\''t recognize/derive Q suffix in the common case","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fb617d0b-8759-3169-5a65-1178b7fef3d7@suse.com/mbox/"},{"id":1981,"url":"https://patchwork.plctlab.org/api/1.2/patches/1981/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1df3bd01-99c5-f56c-d937-970edd42b2b8@suse.com/","msgid":"<1df3bd01-99c5-f56c-d937-970edd42b2b8@suse.com>","list_archive_url":null,"date":"2022-10-13T08:20:14","name":"[v4,6/8] x86-64: allow HLE store of accumulator to absolute 32-bit address","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1df3bd01-99c5-f56c-d937-970edd42b2b8@suse.com/mbox/"},{"id":1982,"url":"https://patchwork.plctlab.org/api/1.2/patches/1982/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8486a218-39ec-16b2-5c6c-5037196b93cf@suse.com/","msgid":"<8486a218-39ec-16b2-5c6c-5037196b93cf@suse.com>","list_archive_url":null,"date":"2022-10-13T08:21:00","name":"[v4,7/8] x86: move bad-use-of-TLS-reloc check","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8486a218-39ec-16b2-5c6c-5037196b93cf@suse.com/mbox/"},{"id":1983,"url":"https://patchwork.plctlab.org/api/1.2/patches/1983/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7d82692d-93df-fbee-9efb-2f44e8a91df3@suse.com/","msgid":"<7d82692d-93df-fbee-9efb-2f44e8a91df3@suse.com>","list_archive_url":null,"date":"2022-10-13T08:22:00","name":"[v4,8/8] x86: drop (now) stray IsString","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7d82692d-93df-fbee-9efb-2f44e8a91df3@suse.com/mbox/"},{"id":2013,"url":"https://patchwork.plctlab.org/api/1.2/patches/2013/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8ab93d7a617ad480dd786210f46db0e5aa07d1ac.1665655719.git.research_trasio@irq.a4lg.com/","msgid":"<8ab93d7a617ad480dd786210f46db0e5aa07d1ac.1665655719.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-13T10:11:41","name":"include: Declare getopt function on old GNU libc","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8ab93d7a617ad480dd786210f46db0e5aa07d1ac.1665655719.git.research_trasio@irq.a4lg.com/mbox/"},{"id":2352,"url":"https://patchwork.plctlab.org/api/1.2/patches/2352/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221013201332.2747246-1-maskray@google.com/","msgid":"<20221013201332.2747246-1-maskray@google.com>","list_archive_url":null,"date":"2022-10-13T20:13:32","name":"ld: Add --undefined-version","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221013201332.2747246-1-maskray@google.com/mbox/"},{"id":2532,"url":"https://patchwork.plctlab.org/api/1.2/patches/2532/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014063520.1428330-2-zengxiao@eswincomputing.com/","msgid":"<20221014063520.1428330-2-zengxiao@eswincomputing.com>","list_archive_url":null,"date":"2022-10-14T06:35:20","name":"[1/1] RISC-V: Make R_RISCV_SUB6 conforms to riscv abi standard","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014063520.1428330-2-zengxiao@eswincomputing.com/mbox/"},{"id":2560,"url":"https://patchwork.plctlab.org/api/1.2/patches/2560/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/027ae69a-636b-6757-297a-eec42936401e@linaro.org/","msgid":"<027ae69a-636b-6757-297a-eec42936401e@linaro.org>","list_archive_url":null,"date":"2022-10-14T07:58:22","name":"[v3] aarch64-pe support for LD, GAS and BFD","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/027ae69a-636b-6757-297a-eec42936401e@linaro.org/mbox/"},{"id":2602,"url":"https://patchwork.plctlab.org/api/1.2/patches/2602/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-2-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-2-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:39","name":"[01/10] Support Intel AVX-IFMA","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-2-haochen.jiang@intel.com/mbox/"},{"id":2608,"url":"https://patchwork.plctlab.org/api/1.2/patches/2608/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-3-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-3-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:40","name":"[02/10] Support Intel AVX-VNNI-INT8","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-3-haochen.jiang@intel.com/mbox/"},{"id":2611,"url":"https://patchwork.plctlab.org/api/1.2/patches/2611/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-4-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-4-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:41","name":"[03/10] Support Intel AVX-NE-CONVERT","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-4-haochen.jiang@intel.com/mbox/"},{"id":2610,"url":"https://patchwork.plctlab.org/api/1.2/patches/2610/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-5-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-5-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:42","name":"[04/10] Support Intel CMPccXADD","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-5-haochen.jiang@intel.com/mbox/"},{"id":2601,"url":"https://patchwork.plctlab.org/api/1.2/patches/2601/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-6-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-6-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:43","name":"[05/10] Add handler for more i386_cpu_flags","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-6-haochen.jiang@intel.com/mbox/"},{"id":2606,"url":"https://patchwork.plctlab.org/api/1.2/patches/2606/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-7-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-7-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:44","name":"[06/10] Support Intel RAO-INT","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-7-haochen.jiang@intel.com/mbox/"},{"id":2609,"url":"https://patchwork.plctlab.org/api/1.2/patches/2609/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-8-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-8-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:45","name":"[07/10] Support Intel WRMSRNS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-8-haochen.jiang@intel.com/mbox/"},{"id":2605,"url":"https://patchwork.plctlab.org/api/1.2/patches/2605/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-9-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-9-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:46","name":"[08/10] Support Intel MSRLIST","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-9-haochen.jiang@intel.com/mbox/"},{"id":2607,"url":"https://patchwork.plctlab.org/api/1.2/patches/2607/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-10-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-10-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:47","name":"[09/10] Support Intel AMX-FP16","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-10-haochen.jiang@intel.com/mbox/"},{"id":2604,"url":"https://patchwork.plctlab.org/api/1.2/patches/2604/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-11-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-11-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:48","name":"[10/10] Support Intel PREFETCHI","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-11-haochen.jiang@intel.com/mbox/"},{"id":2643,"url":"https://patchwork.plctlab.org/api/1.2/patches/2643/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7bac66be-535e-9051-d674-f2f5ba180e17@suse.com/","msgid":"<7bac66be-535e-9051-d674-f2f5ba180e17@suse.com>","list_archive_url":null,"date":"2022-10-14T10:22:34","name":"x86: fold AVX512-VNNI disassembler entries with AVX-VNNI ones","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7bac66be-535e-9051-d674-f2f5ba180e17@suse.com/mbox/"},{"id":2654,"url":"https://patchwork.plctlab.org/api/1.2/patches/2654/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0lIo5+ncY/MqBEq@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-14T11:31:47","name":"PR29677, Field `the_bfd` of `asymbol` is uninitialised","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0lIo5+ncY/MqBEq@squeak.grove.modra.org/mbox/"},{"id":2656,"url":"https://patchwork.plctlab.org/api/1.2/patches/2656/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0lJksn49ZpABY89@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-14T11:35:46","name":"e200 LSP support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0lJksn49ZpABY89@squeak.grove.modra.org/mbox/"},{"id":2657,"url":"https://patchwork.plctlab.org/api/1.2/patches/2657/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0lJxxYoeD5iDYAD@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-14T11:36:39","name":"PowerPC SPE disassembly and tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0lJxxYoeD5iDYAD@squeak.grove.modra.org/mbox/"},{"id":2695,"url":"https://patchwork.plctlab.org/api/1.2/patches/2695/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/DM6PR12MB4219611F6CC2A0702884A602E7249@DM6PR12MB4219.namprd12.prod.outlook.com/","msgid":"","list_archive_url":null,"date":"2022-10-14T13:29:40","name":"Binutils: Adding new testcase for addr2line.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/DM6PR12MB4219611F6CC2A0702884A602E7249@DM6PR12MB4219.namprd12.prod.outlook.com/mbox/"},{"id":2700,"url":"https://patchwork.plctlab.org/api/1.2/patches/2700/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9fd2c88d-98b2-99a4-419f-c7235b2cf960@suse.com/","msgid":"<9fd2c88d-98b2-99a4-419f-c7235b2cf960@suse.com>","list_archive_url":null,"date":"2022-10-14T14:11:35","name":"x86: properly decode EVEX.W for AVX512_4{FMAPS,VNNIW} insns","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9fd2c88d-98b2-99a4-419f-c7235b2cf960@suse.com/mbox/"},{"id":2981,"url":"https://patchwork.plctlab.org/api/1.2/patches/2981/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0uLzalqjm4C87GN@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-16T04:42:53","name":"PowerPC se_rfmci and VLE, SPE2 and LSP insns with -many","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0uLzalqjm4C87GN@squeak.grove.modra.org/mbox/"},{"id":3152,"url":"https://patchwork.plctlab.org/api/1.2/patches/3152/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221016232419.1135-1-mark@harmstone.com/","msgid":"<20221016232419.1135-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-16T23:24:18","name":"[v5,1/2] ld: Add --pdb option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221016232419.1135-1-mark@harmstone.com/mbox/"},{"id":3151,"url":"https://patchwork.plctlab.org/api/1.2/patches/3151/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221016232419.1135-2-mark@harmstone.com/","msgid":"<20221016232419.1135-2-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-16T23:24:19","name":"[v5,2/2] ld: Add minimal pdb generation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221016232419.1135-2-mark@harmstone.com/mbox/"},{"id":3258,"url":"https://patchwork.plctlab.org/api/1.2/patches/3258/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/19c08747-fa5b-1e67-3dd2-c891a2c0c1fa@suse.com/","msgid":"<19c08747-fa5b-1e67-3dd2-c891a2c0c1fa@suse.com>","list_archive_url":null,"date":"2022-10-17T07:44:51","name":"x86: correct CPU_AMX_{BF16,INT8}_FLAGS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/19c08747-fa5b-1e67-3dd2-c891a2c0c1fa@suse.com/mbox/"},{"id":3272,"url":"https://patchwork.plctlab.org/api/1.2/patches/3272/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/85dd526c-d3a7-72dc-5444-ed5573eebec1@suse.com/","msgid":"<85dd526c-d3a7-72dc-5444-ed5573eebec1@suse.com>","list_archive_url":null,"date":"2022-10-17T08:30:12","name":"x86: generalize gas documentation for disabling of ISA extensions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/85dd526c-d3a7-72dc-5444-ed5573eebec1@suse.com/mbox/"},{"id":3759,"url":"https://patchwork.plctlab.org/api/1.2/patches/3759/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-2-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-2-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:15:58","name":"[V2,01/15] sframe.h: Add SFrame format definition","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-2-indu.bhagat@oracle.com/mbox/"},{"id":3762,"url":"https://patchwork.plctlab.org/api/1.2/patches/3762/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-3-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-3-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:15:59","name":"[V2,02/15] gas: add new command line option --gsframe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-3-indu.bhagat@oracle.com/mbox/"},{"id":3761,"url":"https://patchwork.plctlab.org/api/1.2/patches/3761/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-4-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-4-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:00","name":"[V2,03/15] gas: generate .sframe from CFI directives","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-4-indu.bhagat@oracle.com/mbox/"},{"id":3760,"url":"https://patchwork.plctlab.org/api/1.2/patches/3760/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-5-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-5-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:01","name":"[V2,04/15] gas: testsuite: add new tests for SFrame unwind info","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-5-indu.bhagat@oracle.com/mbox/"},{"id":3764,"url":"https://patchwork.plctlab.org/api/1.2/patches/3764/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-6-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-6-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:02","name":"[V2,05/15] libsframe: add the SFrame library","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-6-indu.bhagat@oracle.com/mbox/"},{"id":3766,"url":"https://patchwork.plctlab.org/api/1.2/patches/3766/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-7-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-7-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:03","name":"[V2,06/15] bfd: linker: merge .sframe sections","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-7-indu.bhagat@oracle.com/mbox/"},{"id":3763,"url":"https://patchwork.plctlab.org/api/1.2/patches/3763/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-8-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-8-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:04","name":"[V2,07/15] readelf/objdump: support for SFrame section","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-8-indu.bhagat@oracle.com/mbox/"},{"id":3765,"url":"https://patchwork.plctlab.org/api/1.2/patches/3765/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-9-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-9-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:05","name":"[V2,08/15] unwinder: generate backtrace using SFrame format","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-9-indu.bhagat@oracle.com/mbox/"},{"id":3770,"url":"https://patchwork.plctlab.org/api/1.2/patches/3770/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-10-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-10-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:06","name":"[V2,09/15] unwinder: Add SFrame unwinder tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-10-indu.bhagat@oracle.com/mbox/"},{"id":3769,"url":"https://patchwork.plctlab.org/api/1.2/patches/3769/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-11-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-11-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:07","name":"[V2,10/15] gdb: sim: buildsystem changes to accommodate libsframe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-11-indu.bhagat@oracle.com/mbox/"},{"id":3771,"url":"https://patchwork.plctlab.org/api/1.2/patches/3771/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-12-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-12-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:08","name":"[V2,11/15] libctf: add libsframe to LDFLAGS and LIBS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-12-indu.bhagat@oracle.com/mbox/"},{"id":3768,"url":"https://patchwork.plctlab.org/api/1.2/patches/3768/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-13-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-13-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:09","name":"[V2,12/15] src-release.sh: Add libsframe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-13-indu.bhagat@oracle.com/mbox/"},{"id":3767,"url":"https://patchwork.plctlab.org/api/1.2/patches/3767/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-14-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-14-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:10","name":"[V2,13/15] binutils/NEWS: add text for SFrame support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-14-indu.bhagat@oracle.com/mbox/"},{"id":3772,"url":"https://patchwork.plctlab.org/api/1.2/patches/3772/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-15-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-15-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:11","name":"[V2,14/15] gas/NEWS: add text about new command line option and SFrame support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-15-indu.bhagat@oracle.com/mbox/"},{"id":3773,"url":"https://patchwork.plctlab.org/api/1.2/patches/3773/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-16-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-16-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:12","name":"[V2,15/15] doc: add SFrame spec file","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-16-indu.bhagat@oracle.com/mbox/"},{"id":3999,"url":"https://patchwork.plctlab.org/api/1.2/patches/3999/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221018081205.17880-1-krebbel@linux.ibm.com/","msgid":"<20221018081205.17880-1-krebbel@linux.ibm.com>","list_archive_url":null,"date":"2022-10-18T08:12:05","name":"[1/1] IBM zSystems: Issue error for *DBL relocs on misaligned symbols","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221018081205.17880-1-krebbel@linux.ibm.com/mbox/"},{"id":4141,"url":"https://patchwork.plctlab.org/api/1.2/patches/4141/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/baffaf673f17692b7bcbd604b31800b189988596.camel@espressif.com/","msgid":"","list_archive_url":null,"date":"2022-10-18T12:12:07","name":"xtensa: use definitions from xtensa-config.h","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/baffaf673f17692b7bcbd604b31800b189988596.camel@espressif.com/mbox/"},{"id":4272,"url":"https://patchwork.plctlab.org/api/1.2/patches/4272/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221018174914.470062-1-hjl.tools@gmail.com/","msgid":"<20221018174914.470062-1-hjl.tools@gmail.com>","list_archive_url":null,"date":"2022-10-18T17:49:14","name":"x86: Disable AVX-VNNI when disabling AVX2","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221018174914.470062-1-hjl.tools@gmail.com/mbox/"},{"id":4998,"url":"https://patchwork.plctlab.org/api/1.2/patches/4998/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c2f76e95-09f6-1d92-7ef4-38a3c2955fcd@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-19T09:52:46","name":"x86: re-work AVX-VNNI support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c2f76e95-09f6-1d92-7ef4-38a3c2955fcd@suse.com/mbox/"},{"id":5276,"url":"https://patchwork.plctlab.org/api/1.2/patches/5276/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0/lLtlKqqsmAx0s@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-19T11:53:18","name":"Fix addr2line test for ppc64 elfv1 and mingw","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0/lLtlKqqsmAx0s@squeak.grove.modra.org/mbox/"},{"id":5424,"url":"https://patchwork.plctlab.org/api/1.2/patches/5424/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/07bfebbf3843b47e13d82d4fa16eb14fec942ef7.1666184962.git.research_trasio@irq.a4lg.com/","msgid":"<07bfebbf3843b47e13d82d4fa16eb14fec942ef7.1666184962.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:09:54","name":"binutils: Remove unused substitution PROGRAM","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/07bfebbf3843b47e13d82d4fa16eb14fec942ef7.1666184962.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5433,"url":"https://patchwork.plctlab.org/api/1.2/patches/5433/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2fa7ff719223232402e82a9c91331aea22ace1bb.1666185116.git.research_trasio@irq.a4lg.com/","msgid":"<2fa7ff719223232402e82a9c91331aea22ace1bb.1666185116.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:11:55","name":"[v2,1/8] RISC-V: Add a space at the end of pinfo","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2fa7ff719223232402e82a9c91331aea22ace1bb.1666185116.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5435,"url":"https://patchwork.plctlab.org/api/1.2/patches/5435/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1b30cce5db2cce3b8edca42ab5da114d0b8c9e93.1666185116.git.research_trasio@irq.a4lg.com/","msgid":"<1b30cce5db2cce3b8edca42ab5da114d0b8c9e93.1666185116.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:11:56","name":"[v2,2/8] RISC-V: Fix obvious misalignments ('\''Zbb'\''/'\''Zba'\'')","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1b30cce5db2cce3b8edca42ab5da114d0b8c9e93.1666185116.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5437,"url":"https://patchwork.plctlab.org/api/1.2/patches/5437/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6b0857aa1a2d15ca1cf00b4dcaae0032efbb88ff.1666185116.git.research_trasio@irq.a4lg.com/","msgid":"<6b0857aa1a2d15ca1cf00b4dcaae0032efbb88ff.1666185116.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:11:57","name":"[v2,3/8] RISC-V: Remove spaces in opcode entries","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6b0857aa1a2d15ca1cf00b4dcaae0032efbb88ff.1666185116.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5436,"url":"https://patchwork.plctlab.org/api/1.2/patches/5436/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/889d956caac0f2e95543a14afaeed97188ce384c.1666185116.git.research_trasio@irq.a4lg.com/","msgid":"<889d956caac0f2e95543a14afaeed97188ce384c.1666185116.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:11:58","name":"[v2,4/8] RISC-V: Remove unused instruction macros","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/889d956caac0f2e95543a14afaeed97188ce384c.1666185116.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5440,"url":"https://patchwork.plctlab.org/api/1.2/patches/5440/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8f226ee20d8a5ef6ad7b6c4408b44794a99d542a.1666185116.git.research_trasio@irq.a4lg.com/","msgid":"<8f226ee20d8a5ef6ad7b6c4408b44794a99d542a.1666185116.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:11:59","name":"[v2,5/8] RISC-V: Complete tidying up with SCALL and SBREAK","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8f226ee20d8a5ef6ad7b6c4408b44794a99d542a.1666185116.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5442,"url":"https://patchwork.plctlab.org/api/1.2/patches/5442/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4070184c454a05a39adf0790951e5856e6b2ecb6.1666185116.git.research_trasio@irq.a4lg.com/","msgid":"<4070184c454a05a39adf0790951e5856e6b2ecb6.1666185116.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:12:00","name":"[v2,6/8] RISC-V: Tidying up with fmv.w.x and fmv.x.w","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4070184c454a05a39adf0790951e5856e6b2ecb6.1666185116.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5438,"url":"https://patchwork.plctlab.org/api/1.2/patches/5438/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c1ccda3e7c8fb297eda46dab3936d5c5977178fc.1666185116.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-19T13:12:01","name":"[v2,7/8] RISC-V: Make alias instructions aliases","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c1ccda3e7c8fb297eda46dab3936d5c5977178fc.1666185116.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5441,"url":"https://patchwork.plctlab.org/api/1.2/patches/5441/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/413cfca82c7e8d8a2e977dfda9135903c9cb7c57.1666185116.git.research_trasio@irq.a4lg.com/","msgid":"<413cfca82c7e8d8a2e977dfda9135903c9cb7c57.1666185116.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:12:02","name":"[v2,8/8] RISC-V: Use defined mask and match values","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/413cfca82c7e8d8a2e977dfda9135903c9cb7c57.1666185116.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5439,"url":"https://patchwork.plctlab.org/api/1.2/patches/5439/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/345c5c3b3a53eab04a1e6e91197de2642095c94f.1666185237.git.research_trasio@irq.a4lg.com/","msgid":"<345c5c3b3a53eab04a1e6e91197de2642095c94f.1666185237.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:14:01","name":"RISC-V: Remove RV32EF conflict","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/345c5c3b3a53eab04a1e6e91197de2642095c94f.1666185237.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5616,"url":"https://patchwork.plctlab.org/api/1.2/patches/5616/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019145608.45213-5-haochen.jiang@intel.com/","msgid":"<20221019145608.45213-5-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T14:56:02","name":"[04/10] Support Intel CMPccXADD","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019145608.45213-5-haochen.jiang@intel.com/mbox/"},{"id":5614,"url":"https://patchwork.plctlab.org/api/1.2/patches/5614/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019145608.45213-6-haochen.jiang@intel.com/","msgid":"<20221019145608.45213-6-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T14:56:03","name":"[05/10] Add handler for more i386_cpu_flags","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019145608.45213-6-haochen.jiang@intel.com/mbox/"},{"id":5672,"url":"https://patchwork.plctlab.org/api/1.2/patches/5672/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-2-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-2-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:25","name":"[01/10] Support Intel AVX-IFMA","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-2-haochen.jiang@intel.com/mbox/"},{"id":5691,"url":"https://patchwork.plctlab.org/api/1.2/patches/5691/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-3-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-3-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:26","name":"[02/10] Support Intel AVX-VNNI-INT8","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-3-haochen.jiang@intel.com/mbox/"},{"id":5690,"url":"https://patchwork.plctlab.org/api/1.2/patches/5690/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-4-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-4-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:27","name":"[03/10] Support Intel AVX-NE-CONVERT","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-4-haochen.jiang@intel.com/mbox/"},{"id":5689,"url":"https://patchwork.plctlab.org/api/1.2/patches/5689/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-5-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-5-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:28","name":"[04/10] Support Intel CMPccXADD","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-5-haochen.jiang@intel.com/mbox/"},{"id":5676,"url":"https://patchwork.plctlab.org/api/1.2/patches/5676/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-6-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-6-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:29","name":"[05/10] Add handler for more i386_cpu_flags","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-6-haochen.jiang@intel.com/mbox/"},{"id":5677,"url":"https://patchwork.plctlab.org/api/1.2/patches/5677/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-7-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-7-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:30","name":"[06/10] Support Intel RAO-INT","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-7-haochen.jiang@intel.com/mbox/"},{"id":5681,"url":"https://patchwork.plctlab.org/api/1.2/patches/5681/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-8-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-8-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:31","name":"[07/10] Support Intel WRMSRNS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-8-haochen.jiang@intel.com/mbox/"},{"id":5682,"url":"https://patchwork.plctlab.org/api/1.2/patches/5682/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-9-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-9-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:32","name":"[08/10] Support Intel MSRLIST","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-9-haochen.jiang@intel.com/mbox/"},{"id":5673,"url":"https://patchwork.plctlab.org/api/1.2/patches/5673/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-10-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-10-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:33","name":"[09/10] Support Intel AMX-FP16","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-10-haochen.jiang@intel.com/mbox/"},{"id":5686,"url":"https://patchwork.plctlab.org/api/1.2/patches/5686/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-11-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-11-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:34","name":"[10/10] Support Intel PREFETCHI","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-11-haochen.jiang@intel.com/mbox/"},{"id":11921,"url":"https://patchwork.plctlab.org/api/1.2/patches/11921/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027190052.10536-1-mark@harmstone.com/","msgid":"<20221027190052.10536-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-27T19:00:51","name":"[1/2] ld: Add section header stream to PDB files","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027190052.10536-1-mark@harmstone.com/mbox/"},{"id":11922,"url":"https://patchwork.plctlab.org/api/1.2/patches/11922/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027190052.10536-2-mark@harmstone.com/","msgid":"<20221027190052.10536-2-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-27T19:00:52","name":"[2/2] ld: Add publics stream to PDB files","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027190052.10536-2-mark@harmstone.com/mbox/"},{"id":11965,"url":"https://patchwork.plctlab.org/api/1.2/patches/11965/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027202719.32497-1-palmer@rivosinc.com/","msgid":"<20221027202719.32497-1-palmer@rivosinc.com>","list_archive_url":null,"date":"2022-10-27T20:27:18","name":"[1/2] gas: NEWS: Add a missing newline","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027202719.32497-1-palmer@rivosinc.com/mbox/"},{"id":11966,"url":"https://patchwork.plctlab.org/api/1.2/patches/11966/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027202719.32497-2-palmer@rivosinc.com/","msgid":"<20221027202719.32497-2-palmer@rivosinc.com>","list_archive_url":null,"date":"2022-10-27T20:27:19","name":"[2/2] gas: NEWS: Note support for RISC-V Zawrs","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027202719.32497-2-palmer@rivosinc.com/mbox/"},{"id":12016,"url":"https://patchwork.plctlab.org/api/1.2/patches/12016/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/21ec9a18-fa89-0828-f625-499680022ec7@linux.ibm.com/","msgid":"<21ec9a18-fa89-0828-f625-499680022ec7@linux.ibm.com>","list_archive_url":null,"date":"2022-10-28T00:35:19","name":"[COMMITTED] PowerPC: Add support for RFC02653 - Dense Math Facility","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/21ec9a18-fa89-0828-f625-499680022ec7@linux.ibm.com/mbox/"}],"public":true,"mbox":"https://patchwork.plctlab.org/bundle/patchwork-bot/binutils-gdb_2022-10/mbox/"},{"id":7,"url":"https://patchwork.plctlab.org/api/1.2/bundles/7/","web_url":"https://patchwork.plctlab.org/bundle/patchwork-bot/binutils-gdb_2022-09/","project":{"id":2,"url":"https://patchwork.plctlab.org/api/1.2/projects/2/","name":"binutils-gdb","link_name":"binutils-gdb","list_id":"binutils.sourceware.org","list_email":"binutils@sourceware.org","web_url":"https://sourceware.org/mailman/listinfo/binutils","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"name":"binutils-gdb_2022-09","owner":{"id":3,"url":"https://patchwork.plctlab.org/api/1.2/users/3/","username":"patchwork-bot","first_name":"","last_name":"","email":"ouuuleilei@gmail.com"},"patches":[{"id":1573,"url":"https://patchwork.plctlab.org/api/1.2/patches/1573/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930073211.2634-1-jiawei@iscas.ac.cn/","msgid":"<20220930073211.2634-1-jiawei@iscas.ac.cn>","list_archive_url":null,"date":"2022-09-30T07:32:11","name":"[V2] RISC-V: Add Smepmp CSR '\''mseccfg'\'' define and testcases.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930073211.2634-1-jiawei@iscas.ac.cn/mbox/"},{"id":1577,"url":"https://patchwork.plctlab.org/api/1.2/patches/1577/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/76fa0c3c-2303-ebdf-a765-ac4731581517@suse.com/","msgid":"<76fa0c3c-2303-ebdf-a765-ac4731581517@suse.com>","list_archive_url":null,"date":"2022-09-30T08:54:18","name":"objcopy: avoid \"shadowing\" of remove() function name","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/76fa0c3c-2303-ebdf-a765-ac4731581517@suse.com/mbox/"},{"id":1579,"url":"https://patchwork.plctlab.org/api/1.2/patches/1579/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930085852.71213-1-nelson@rivosinc.com/","msgid":"<20220930085852.71213-1-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-09-30T08:58:51","name":"[1/2] RISC-V: Output mapping symbols with ISA string.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930085852.71213-1-nelson@rivosinc.com/mbox/"},{"id":1578,"url":"https://patchwork.plctlab.org/api/1.2/patches/1578/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930085852.71213-2-nelson@rivosinc.com/","msgid":"<20220930085852.71213-2-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-09-30T08:58:52","name":"[2/2] RISC-V: Refer mapping symbol to R_RISCV_RELAX for rvc relaxations.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930085852.71213-2-nelson@rivosinc.com/mbox/"},{"id":1581,"url":"https://patchwork.plctlab.org/api/1.2/patches/1581/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930092058.71286-1-nelson@rivosinc.com/","msgid":"<20220930092058.71286-1-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-09-30T09:20:57","name":"[1/2] RISC-V: Output mapping symbols with ISA string.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930092058.71286-1-nelson@rivosinc.com/mbox/"},{"id":1580,"url":"https://patchwork.plctlab.org/api/1.2/patches/1580/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930092058.71286-2-nelson@rivosinc.com/","msgid":"<20220930092058.71286-2-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-09-30T09:20:58","name":"[2/2] RISC-V: Refer mapping symbol to R_RISCV_RELAX for rvc relaxations.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930092058.71286-2-nelson@rivosinc.com/mbox/"},{"id":1582,"url":"https://patchwork.plctlab.org/api/1.2/patches/1582/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5874dd79-0cf5-d65c-7ea2-13adfc799c0f@suse.com/","msgid":"<5874dd79-0cf5-d65c-7ea2-13adfc799c0f@suse.com>","list_archive_url":null,"date":"2022-09-30T09:41:29","name":"RISC-V: fix build after \"Add support for arbitrary immediate encoding formats\"","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5874dd79-0cf5-d65c-7ea2-13adfc799c0f@suse.com/mbox/"},{"id":1583,"url":"https://patchwork.plctlab.org/api/1.2/patches/1583/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/57d8ac2a-5757-3776-9924-99c17ca69938@suse.com/","msgid":"<57d8ac2a-5757-3776-9924-99c17ca69938@suse.com>","list_archive_url":null,"date":"2022-09-30T09:42:08","name":"RISC-V: fallout from \"re-arrange opcode table for consistent alias handling\"","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/57d8ac2a-5757-3776-9924-99c17ca69938@suse.com/mbox/"},{"id":1584,"url":"https://patchwork.plctlab.org/api/1.2/patches/1584/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e76ef8f7-72b9-5103-cb43-9608af01d017@suse.com/","msgid":"","list_archive_url":null,"date":"2022-09-30T09:42:50","name":"RISC-V: don'\''t cast expressions'\'' X_add_number to long in diagnostics","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e76ef8f7-72b9-5103-cb43-9608af01d017@suse.com/mbox/"},{"id":1585,"url":"https://patchwork.plctlab.org/api/1.2/patches/1585/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/61355429-24b3-17d0-ab03-6fa57ee861d5@suse.cz/","msgid":"<61355429-24b3-17d0-ab03-6fa57ee861d5@suse.cz>","list_archive_url":null,"date":"2022-09-30T09:48:52","name":"[RFC] add --enable-zstd-compressed-debug-sections configure option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/61355429-24b3-17d0-ab03-6fa57ee861d5@suse.cz/mbox/"},{"id":1586,"url":"https://patchwork.plctlab.org/api/1.2/patches/1586/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930103919.323690-1-christoph.muellner@vrull.eu/","msgid":"<20220930103919.323690-1-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2022-09-30T10:39:19","name":"RISC-V: Eliminate long-casts of X_add_number in diagnostics","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930103919.323690-1-christoph.muellner@vrull.eu/mbox/"},{"id":1590,"url":"https://patchwork.plctlab.org/api/1.2/patches/1590/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/DM6PR12MB4219C943049C6D883DEA3E55E7569@DM6PR12MB4219.namprd12.prod.outlook.com/","msgid":"","list_archive_url":null,"date":"2022-09-30T11:41:37","name":"[V2] Ignore DWARF debug information for -gsplit-dwarf with dwarf-5.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/DM6PR12MB4219C943049C6D883DEA3E55E7569@DM6PR12MB4219.namprd12.prod.outlook.com/mbox/"},{"id":1591,"url":"https://patchwork.plctlab.org/api/1.2/patches/1591/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c10321f9-d289-ef84-d263-bc278fb3d31b@suse.com/","msgid":"","list_archive_url":null,"date":"2022-09-30T11:59:04","name":"[1/4] RISC-V/gas: drop riscv_subsets static variable","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c10321f9-d289-ef84-d263-bc278fb3d31b@suse.com/mbox/"},{"id":1593,"url":"https://patchwork.plctlab.org/api/1.2/patches/1593/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3244eea0-c18c-e49a-4588-d69423130226@suse.com/","msgid":"<3244eea0-c18c-e49a-4588-d69423130226@suse.com>","list_archive_url":null,"date":"2022-09-30T11:59:23","name":"[2/4] RISC-V/gas: drop stray call to install_insn()","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3244eea0-c18c-e49a-4588-d69423130226@suse.com/mbox/"},{"id":1592,"url":"https://patchwork.plctlab.org/api/1.2/patches/1592/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/385d01fd-7e57-1f3f-1bae-30aa0c313d63@suse.com/","msgid":"<385d01fd-7e57-1f3f-1bae-30aa0c313d63@suse.com>","list_archive_url":null,"date":"2022-09-30T11:59:45","name":"[3/4] RISC-V/gas: don'\''t open-code insn_length()","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/385d01fd-7e57-1f3f-1bae-30aa0c313d63@suse.com/mbox/"},{"id":1594,"url":"https://patchwork.plctlab.org/api/1.2/patches/1594/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f5757acf-7b90-a0e3-5eea-3b97cc226930@suse.com/","msgid":"","list_archive_url":null,"date":"2022-09-30T12:00:12","name":"[4/4] RISC-V/gas: allow generating up to 176-bit instructions with .insn","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f5757acf-7b90-a0e3-5eea-3b97cc226930@suse.com/mbox/"},{"id":1596,"url":"https://patchwork.plctlab.org/api/1.2/patches/1596/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930140503.38233-1-chigot@adacore.com/","msgid":"<20220930140503.38233-1-chigot@adacore.com>","list_archive_url":null,"date":"2022-09-30T14:05:03","name":"ld/testsuite: consistently add board_ldflags when linking with GCC","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930140503.38233-1-chigot@adacore.com/mbox/"}],"public":true,"mbox":"https://patchwork.plctlab.org/bundle/patchwork-bot/binutils-gdb_2022-09/mbox/"}]' ++ echo '[{"id":6,"url":"https://patchwork.plctlab.org/api/1.2/bundles/6/","web_url":"https://patchwork.plctlab.org/bundle/patchwork-bot/binutils-gdb_2022-10/","project":{"id":2,"url":"https://patchwork.plctlab.org/api/1.2/projects/2/","name":"binutils-gdb","link_name":"binutils-gdb","list_id":"binutils.sourceware.org","list_email":"binutils@sourceware.org","web_url":"https://sourceware.org/mailman/listinfo/binutils","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"name":"binutils-gdb_2022-10","owner":{"id":3,"url":"https://patchwork.plctlab.org/api/1.2/users/3/","username":"patchwork-bot","first_name":"","last_name":"","email":"ouuuleilei@gmail.com"},"patches":[{"id":1592,"url":"https://patchwork.plctlab.org/api/1.2/patches/1592/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/385d01fd-7e57-1f3f-1bae-30aa0c313d63@suse.com/","msgid":"<385d01fd-7e57-1f3f-1bae-30aa0c313d63@suse.com>","list_archive_url":null,"date":"2022-09-30T11:59:45","name":"[3/4] RISC-V/gas: don'\''t open-code insn_length()","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/385d01fd-7e57-1f3f-1bae-30aa0c313d63@suse.com/mbox/"},{"id":1594,"url":"https://patchwork.plctlab.org/api/1.2/patches/1594/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f5757acf-7b90-a0e3-5eea-3b97cc226930@suse.com/","msgid":"","list_archive_url":null,"date":"2022-09-30T12:00:12","name":"[4/4] RISC-V/gas: allow generating up to 176-bit instructions with .insn","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f5757acf-7b90-a0e3-5eea-3b97cc226930@suse.com/mbox/"},{"id":1596,"url":"https://patchwork.plctlab.org/api/1.2/patches/1596/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930140503.38233-1-chigot@adacore.com/","msgid":"<20220930140503.38233-1-chigot@adacore.com>","list_archive_url":null,"date":"2022-09-30T14:05:03","name":"ld/testsuite: consistently add board_ldflags when linking with GCC","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930140503.38233-1-chigot@adacore.com/mbox/"},{"id":1619,"url":"https://patchwork.plctlab.org/api/1.2/patches/1619/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221001014451.532772-1-maskray@google.com/","msgid":"<20221001014451.532772-1-maskray@google.com>","list_archive_url":null,"date":"2022-10-01T01:44:51","name":"gold, dwp: support zstd compressed input debug sections [PR 29641]","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221001014451.532772-1-maskray@google.com/mbox/"},{"id":1620,"url":"https://patchwork.plctlab.org/api/1.2/patches/1620/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221001023846.590825-1-maskray@google.com/","msgid":"<20221001023846.590825-1-maskray@google.com>","list_archive_url":null,"date":"2022-10-01T02:38:46","name":"gold: add --compress-debug-sections=zstd [PR 29641]","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221001023846.590825-1-maskray@google.com/mbox/"},{"id":1623,"url":"https://patchwork.plctlab.org/api/1.2/patches/1623/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b4477c7f666bdeb7f8e998633c7b0cb62310b9ef.1664599545.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-01T04:45:52","name":"[RFC,1/1] RISC-V: Implement common register pair framework","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b4477c7f666bdeb7f8e998633c7b0cb62310b9ef.1664599545.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1625,"url":"https://patchwork.plctlab.org/api/1.2/patches/1625/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/53a265a1f14d17a6f7b106082f610994c5d546e0.1664602025.git.research_trasio@irq.a4lg.com/","msgid":"<53a265a1f14d17a6f7b106082f610994c5d546e0.1664602025.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-01T05:27:31","name":"[RFC,1/1] RISC-V: Implement extension variants","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/53a265a1f14d17a6f7b106082f610994c5d546e0.1664602025.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1626,"url":"https://patchwork.plctlab.org/api/1.2/patches/1626/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8db04962aba9c780f133840a8934353a58f223fe.1664602716.git.research_trasio@irq.a4lg.com/","msgid":"<8db04962aba9c780f133840a8934353a58f223fe.1664602716.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-01T05:39:26","name":"[1/1] RISC-V: Move supervisor instructions after all unprivileged ones","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8db04962aba9c780f133840a8934353a58f223fe.1664602716.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1627,"url":"https://patchwork.plctlab.org/api/1.2/patches/1627/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221001062057.681440-1-maskray@google.com/","msgid":"<20221001062057.681440-1-maskray@google.com>","list_archive_url":null,"date":"2022-10-01T06:20:57","name":"readelf: support zstd compressed debug sections [PR 29640]","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221001062057.681440-1-maskray@google.com/mbox/"},{"id":1631,"url":"https://patchwork.plctlab.org/api/1.2/patches/1631/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/619f112539c0bdecd58e25664f1250a3479a37f5.1664707612.git.aburgess@redhat.com/","msgid":"<619f112539c0bdecd58e25664f1250a3479a37f5.1664707612.git.aburgess@redhat.com>","list_archive_url":null,"date":"2022-10-02T10:47:52","name":"[PATCHv2,2/2] opcodes/arm: add disassembler styling for arm","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/619f112539c0bdecd58e25664f1250a3479a37f5.1664707612.git.aburgess@redhat.com/mbox/"},{"id":1635,"url":"https://patchwork.plctlab.org/api/1.2/patches/1635/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221002185433.gl7dvytfh5wthifx@lug-owl.de/","msgid":"<20221002185433.gl7dvytfh5wthifx@lug-owl.de>","list_archive_url":null,"date":"2022-10-02T18:54:33","name":"diagnostics.h: GCC 13 got -Wself-move, breaks GDB build","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221002185433.gl7dvytfh5wthifx@lug-owl.de/mbox/"},{"id":1637,"url":"https://patchwork.plctlab.org/api/1.2/patches/1637/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003014313.28766-1-mark@harmstone.com/","msgid":"<20221003014313.28766-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-03T01:43:12","name":"[1/2] ld: Add --pdb option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003014313.28766-1-mark@harmstone.com/mbox/"},{"id":1638,"url":"https://patchwork.plctlab.org/api/1.2/patches/1638/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003014313.28766-2-mark@harmstone.com/","msgid":"<20221003014313.28766-2-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-03T01:43:13","name":"[2/2] ld: Add minimal pdb generation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003014313.28766-2-mark@harmstone.com/mbox/"},{"id":1640,"url":"https://patchwork.plctlab.org/api/1.2/patches/1640/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/597ed978-d121-220c-b56b-2ffb94bd091c@suse.cz/","msgid":"<597ed978-d121-220c-b56b-2ffb94bd091c@suse.cz>","list_archive_url":null,"date":"2022-10-03T07:50:38","name":"[1/2] refactor usage of compressed_debug_section_type","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/597ed978-d121-220c-b56b-2ffb94bd091c@suse.cz/mbox/"},{"id":1641,"url":"https://patchwork.plctlab.org/api/1.2/patches/1641/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b8acdd83-f33a-74b8-e21a-23719a0b1a60@suse.cz/","msgid":"","list_archive_url":null,"date":"2022-10-03T07:50:44","name":"[2/2] add --enable-default-compressed-debug-sections-algorithm configure option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b8acdd83-f33a-74b8-e21a-23719a0b1a60@suse.cz/mbox/"},{"id":1642,"url":"https://patchwork.plctlab.org/api/1.2/patches/1642/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003101328.1790113-1-aburgess@redhat.com/","msgid":"<20221003101328.1790113-1-aburgess@redhat.com>","list_archive_url":null,"date":"2022-10-03T10:13:28","name":"opcodes/riscv: style csr names as registers","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003101328.1790113-1-aburgess@redhat.com/mbox/"},{"id":1643,"url":"https://patchwork.plctlab.org/api/1.2/patches/1643/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7ba14fc4472ce97d4f7a4433cad8a571e89f82f4.1664793840.git.research_trasio@irq.a4lg.com/","msgid":"<7ba14fc4472ce97d4f7a4433cad8a571e89f82f4.1664793840.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-03T10:43:59","name":"[v3,1/6] RISC-V: Fix immediates to have \"immediate\" style","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7ba14fc4472ce97d4f7a4433cad8a571e89f82f4.1664793840.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1644,"url":"https://patchwork.plctlab.org/api/1.2/patches/1644/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a498bec37c1fd1dcda57cbf95e5f8cfba09b31d3.1664793840.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-03T10:44:00","name":"[v3,2/6] RISC-V: Fix printf argument types corresponding %x","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a498bec37c1fd1dcda57cbf95e5f8cfba09b31d3.1664793840.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1647,"url":"https://patchwork.plctlab.org/api/1.2/patches/1647/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0002ea716713ace4998a33dde0b81f4f890d10bf.1664793840.git.research_trasio@irq.a4lg.com/","msgid":"<0002ea716713ace4998a33dde0b81f4f890d10bf.1664793840.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-03T10:44:01","name":"[v3,3/6] RISC-V: Optimize riscv_disassemble_data printf","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0002ea716713ace4998a33dde0b81f4f890d10bf.1664793840.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1646,"url":"https://patchwork.plctlab.org/api/1.2/patches/1646/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c65fc3e9aa58965d6768a28c9fd7467fea9897a5.1664793840.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-03T10:44:02","name":"[v3,4/6] RISC-V: Print comma and tabs as the \"text\" style","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c65fc3e9aa58965d6768a28c9fd7467fea9897a5.1664793840.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1648,"url":"https://patchwork.plctlab.org/api/1.2/patches/1648/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5abe1d8a7694417b990e11d8f6cd6789573872e5.1664793840.git.research_trasio@irq.a4lg.com/","msgid":"<5abe1d8a7694417b990e11d8f6cd6789573872e5.1664793840.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-03T10:44:03","name":"[v3,5/6] RISC-V: Fix T-Head immediate types on printing","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5abe1d8a7694417b990e11d8f6cd6789573872e5.1664793840.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1649,"url":"https://patchwork.plctlab.org/api/1.2/patches/1649/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0b68af932117258c908db62cf87c3a15d3cdec41.1664793840.git.research_trasio@irq.a4lg.com/","msgid":"<0b68af932117258c908db62cf87c3a15d3cdec41.1664793840.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-03T10:44:04","name":"[v3,6/6] RISC-V: Print XTheadMemPair literal as \"immediate\"","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0b68af932117258c908db62cf87c3a15d3cdec41.1664793840.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1656,"url":"https://patchwork.plctlab.org/api/1.2/patches/1656/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/87lepxcd6x.fsf@redhat.com/","msgid":"<87lepxcd6x.fsf@redhat.com>","list_archive_url":null,"date":"2022-10-03T12:19:02","name":"Commit: readelf: Do not load section data from offset 0","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/87lepxcd6x.fsf@redhat.com/mbox/"},{"id":1659,"url":"https://patchwork.plctlab.org/api/1.2/patches/1659/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e0d369d419da9c0441f415da7f54352aead8f655.1664707612.git.aburgess@redhat.com/","msgid":"","list_archive_url":null,"date":"2022-10-03T16:37:36","name":"[PATCHv2,1/2] opcodes/arm: use '\''@'\'' consistently for the comment character","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e0d369d419da9c0441f415da7f54352aead8f655.1664707612.git.aburgess@redhat.com/mbox/"},{"id":1660,"url":"https://patchwork.plctlab.org/api/1.2/patches/1660/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003165848.11142-1-palmer@rivosinc.com/","msgid":"<20221003165848.11142-1-palmer@rivosinc.com>","list_archive_url":null,"date":"2022-10-03T16:58:48","name":"gas: NEWS: Mention the T-Head extensions that were recently added","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003165848.11142-1-palmer@rivosinc.com/mbox/"},{"id":1671,"url":"https://patchwork.plctlab.org/api/1.2/patches/1671/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/YzvrMEdkXjIn5Lfz@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-04T08:13:36","name":"Support objcopy changing compression to or from zstd","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/YzvrMEdkXjIn5Lfz@squeak.grove.modra.org/mbox/"},{"id":1673,"url":"https://patchwork.plctlab.org/api/1.2/patches/1673/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0bc857d306bb7c8130e5328dbe6b9ed2fed3ef87.1664873933.git.research_trasio@irq.a4lg.com/","msgid":"<0bc857d306bb7c8130e5328dbe6b9ed2fed3ef87.1664873933.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-04T08:59:07","name":"[1/2] RISC-V: Fix buffer overflow on print_insn_riscv","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0bc857d306bb7c8130e5328dbe6b9ed2fed3ef87.1664873933.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1672,"url":"https://patchwork.plctlab.org/api/1.2/patches/1672/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/89612fe01d902007bf84a7dfb0df5f85d5c166e4.1664873933.git.research_trasio@irq.a4lg.com/","msgid":"<89612fe01d902007bf84a7dfb0df5f85d5c166e4.1664873933.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-04T08:59:08","name":"[2/2] gdb/riscv: Fix buffer overflow on riscv_insn::fetch_instruction","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/89612fe01d902007bf84a7dfb0df5f85d5c166e4.1664873933.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1676,"url":"https://patchwork.plctlab.org/api/1.2/patches/1676/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fc849c94f4adcac1c4ccc5508c7a145a2f13b2a9.1664876744.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-04T09:45:49","name":"[v2,1/2] RISC-V: Fix buffer overflow on print_insn_riscv","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fc849c94f4adcac1c4ccc5508c7a145a2f13b2a9.1664876744.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1677,"url":"https://patchwork.plctlab.org/api/1.2/patches/1677/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4eb6e59ae2e790dbbf2bc92477edd281648d8814.1664876744.git.research_trasio@irq.a4lg.com/","msgid":"<4eb6e59ae2e790dbbf2bc92477edd281648d8814.1664876744.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-04T09:45:50","name":"[v2,2/2] gdb/riscv: Partial support for instructions up to 176-bits","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4eb6e59ae2e790dbbf2bc92477edd281648d8814.1664876744.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1678,"url":"https://patchwork.plctlab.org/api/1.2/patches/1678/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ebf16f9e1f45115d0793952ccb4a94d4233303f9.1664882725.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-04T11:25:56","name":"[v3,1/2] RISC-V: Fix buffer overflow on print_insn_riscv","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ebf16f9e1f45115d0793952ccb4a94d4233303f9.1664882725.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1679,"url":"https://patchwork.plctlab.org/api/1.2/patches/1679/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/83464b09b8649525259c69c853dfa2c9575a204b.1664882725.git.research_trasio@irq.a4lg.com/","msgid":"<83464b09b8649525259c69c853dfa2c9575a204b.1664882725.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-04T11:25:57","name":"[v3,2/2] gdb/riscv: Partial support for instructions up to 176-bit","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/83464b09b8649525259c69c853dfa2c9575a204b.1664882725.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1681,"url":"https://patchwork.plctlab.org/api/1.2/patches/1681/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ffa9c1d7-e8c2-a62b-ef3e-b565c0ffbe5b@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-04T13:56:27","name":"RISC-V: Zicbo{m,p,z} adjustments to riscv_multi_subset_supports_ext()","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ffa9c1d7-e8c2-a62b-ef3e-b565c0ffbe5b@suse.com/mbox/"},{"id":1690,"url":"https://patchwork.plctlab.org/api/1.2/patches/1690/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221004161720.1963953-1-vladimir.mezentsev@oracle.com/","msgid":"<20221004161720.1963953-1-vladimir.mezentsev@oracle.com>","list_archive_url":null,"date":"2022-10-04T16:17:20","name":"gprofng: fix build with --enable-pgo-build=lto","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221004161720.1963953-1-vladimir.mezentsev@oracle.com/mbox/"},{"id":1691,"url":"https://patchwork.plctlab.org/api/1.2/patches/1691/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c0211bc9c57be6c79c6d878ce147f63b657f461d.camel@espressif.com/","msgid":"","list_archive_url":null,"date":"2022-10-04T16:22:05","name":"bfd: xtensa: fix __stop_SECTION literal drop,","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c0211bc9c57be6c79c6d878ce147f63b657f461d.camel@espressif.com/mbox/"},{"id":1702,"url":"https://patchwork.plctlab.org/api/1.2/patches/1702/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5f482299-6c60-b2b3-9abe-f4a55a5a26c5@univ-grenoble-alpes.fr/","msgid":"<5f482299-6c60-b2b3-9abe-f4a55a5a26c5@univ-grenoble-alpes.fr>","list_archive_url":null,"date":"2022-10-04T20:03:20","name":"[RFC] bfd: use bfd_vma for the 64-bit version of put[lb] and get[lb]","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5f482299-6c60-b2b3-9abe-f4a55a5a26c5@univ-grenoble-alpes.fr/mbox/"},{"id":1711,"url":"https://patchwork.plctlab.org/api/1.2/patches/1711/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Yz0Gsxdxe0TePbJT@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-05T04:23:15","name":"PR29647, objdump -S looping","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Yz0Gsxdxe0TePbJT@squeak.grove.modra.org/mbox/"},{"id":1712,"url":"https://patchwork.plctlab.org/api/1.2/patches/1712/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/02d747d2-f57b-0fb5-b893-842b6cc41f2f@suse.com/","msgid":"<02d747d2-f57b-0fb5-b893-842b6cc41f2f@suse.com>","list_archive_url":null,"date":"2022-10-05T07:20:47","name":"[v3,1/7] x86: constify parse_insn()'\''s input","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/02d747d2-f57b-0fb5-b893-842b6cc41f2f@suse.com/mbox/"},{"id":1713,"url":"https://patchwork.plctlab.org/api/1.2/patches/1713/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/925cb740-4e1b-abc4-8526-aaab6faae5e1@suse.com/","msgid":"<925cb740-4e1b-abc4-8526-aaab6faae5e1@suse.com>","list_archive_url":null,"date":"2022-10-05T07:22:19","name":"[v3,2/7] x86: introduce Pass2 insn attribute","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/925cb740-4e1b-abc4-8526-aaab6faae5e1@suse.com/mbox/"},{"id":1714,"url":"https://patchwork.plctlab.org/api/1.2/patches/1714/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e16d3e78-39ca-f715-508f-a4104b8ab9a9@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-05T07:23:51","name":"[v3,3/7] x86: re-work insn/suffix recognition","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e16d3e78-39ca-f715-508f-a4104b8ab9a9@suse.com/mbox/"},{"id":1715,"url":"https://patchwork.plctlab.org/api/1.2/patches/1715/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e4e4b80b-794c-7485-1997-685adab8fb27@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-05T07:24:20","name":"[v3,4/7] x86-64: further re-work insn/suffix recognition to also cover MOVSL","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e4e4b80b-794c-7485-1997-685adab8fb27@suse.com/mbox/"},{"id":1716,"url":"https://patchwork.plctlab.org/api/1.2/patches/1716/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/540678fc-8bff-ec68-c97c-478d2631998c@suse.com/","msgid":"<540678fc-8bff-ec68-c97c-478d2631998c@suse.com>","list_archive_url":null,"date":"2022-10-05T07:24:55","name":"[v3,5/7] ix86: don'\''t recognize/derive Q suffix in the common case","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/540678fc-8bff-ec68-c97c-478d2631998c@suse.com/mbox/"},{"id":1718,"url":"https://patchwork.plctlab.org/api/1.2/patches/1718/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e4692495-7d3d-074d-14f9-364d4a9a998c@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-05T07:25:25","name":"[v3,6/7] x86-64: allow HLE store of accumulator to absolute 32-bit address","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e4692495-7d3d-074d-14f9-364d4a9a998c@suse.com/mbox/"},{"id":1717,"url":"https://patchwork.plctlab.org/api/1.2/patches/1717/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e8014ebd-d16b-17a7-9f34-3700fc164136@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-05T07:25:57","name":"[v3,7/7] x86: move bad-use-of-TLS-reloc check","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e8014ebd-d16b-17a7-9f34-3700fc164136@suse.com/mbox/"},{"id":1719,"url":"https://patchwork.plctlab.org/api/1.2/patches/1719/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1266f001-4511-2662-dba9-14b4d0317c57@suse.com/","msgid":"<1266f001-4511-2662-dba9-14b4d0317c57@suse.com>","list_archive_url":null,"date":"2022-10-05T07:40:50","name":"x86: drop \"regmask\" static variable","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1266f001-4511-2662-dba9-14b4d0317c57@suse.com/mbox/"},{"id":1751,"url":"https://patchwork.plctlab.org/api/1.2/patches/1751/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/af45c5d57c221e43101c2aa38b14f4b4ac12d011.1665031170.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-06T04:40:15","name":"[v2,1/2] RISC-V: Fallback for instructions longer than 64b","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/af45c5d57c221e43101c2aa38b14f4b4ac12d011.1665031170.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1752,"url":"https://patchwork.plctlab.org/api/1.2/patches/1752/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c6e55781245dd3e8e9b8debd6130fc5449dfbd55.1665031170.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-06T04:40:16","name":"[v2,2/2] RISC-V: Improve \"bits undefined\" diagnostics","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c6e55781245dd3e8e9b8debd6130fc5449dfbd55.1665031170.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1776,"url":"https://patchwork.plctlab.org/api/1.2/patches/1776/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d52952119e15357c0e823f8a2398999359588b4d.1665050099.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-06T09:56:30","name":"[v3,1/2] RISC-V: Fallback for instructions longer than 64b","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d52952119e15357c0e823f8a2398999359588b4d.1665050099.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1777,"url":"https://patchwork.plctlab.org/api/1.2/patches/1777/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d907b1997f60ff7823c4a23e281ec9d8ddcbf3f1.1665050099.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-06T09:56:31","name":"[v3,2/2] RISC-V: Improve \"bits undefined\" diagnostics","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d907b1997f60ff7823c4a23e281ec9d8ddcbf3f1.1665050099.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1781,"url":"https://patchwork.plctlab.org/api/1.2/patches/1781/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221006114628.304185-1-chigot@adacore.com/","msgid":"<20221006114628.304185-1-chigot@adacore.com>","list_archive_url":null,"date":"2022-10-06T11:46:28","name":"RISC-V: fix linker message when relaxation deletes bytes","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221006114628.304185-1-chigot@adacore.com/mbox/"},{"id":1801,"url":"https://patchwork.plctlab.org/api/1.2/patches/1801/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Yz+Yhyg7UewC9/kp@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-07T03:09:59","name":"PR29653, objcopy/strip: fuzzed small input file induces large output file","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Yz+Yhyg7UewC9/kp@squeak.grove.modra.org/mbox/"},{"id":1803,"url":"https://patchwork.plctlab.org/api/1.2/patches/1803/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/PH1P110MB16505D9D39EC5B1DE22FE3D5EC5F9@PH1P110MB1650.NAMP110.PROD.OUTLOOK.COM/","msgid":"","list_archive_url":null,"date":"2022-10-07T04:10:07","name":"@CPP_FOR_BUILD@ problem since binutils-2.38","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/PH1P110MB16505D9D39EC5B1DE22FE3D5EC5F9@PH1P110MB1650.NAMP110.PROD.OUTLOOK.COM/mbox/"},{"id":1827,"url":"https://patchwork.plctlab.org/api/1.2/patches/1827/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8e13bce108ac10a0c1dd911e23ec572926f7ae44.1665203374.git.research_trasio@irq.a4lg.com/","msgid":"<8e13bce108ac10a0c1dd911e23ec572926f7ae44.1665203374.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-08T04:29:53","name":"[v2,1/1] RISC-V: Test DWARF register numbers for \"fp\"","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8e13bce108ac10a0c1dd911e23ec572926f7ae44.1665203374.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1828,"url":"https://patchwork.plctlab.org/api/1.2/patches/1828/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0883001b3572e54d3fba264429c7ade2adb66610.1665203441.git.research_trasio@irq.a4lg.com/","msgid":"<0883001b3572e54d3fba264429c7ade2adb66610.1665203441.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-08T04:31:15","name":"[1/1] RISC-V: Move standard hints before all instructions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0883001b3572e54d3fba264429c7ade2adb66610.1665203441.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1829,"url":"https://patchwork.plctlab.org/api/1.2/patches/1829/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/58e16a241d7376fcae2515c6bd5a2b41d275eeba.1665203531.git.research_trasio@irq.a4lg.com/","msgid":"<58e16a241d7376fcae2515c6bd5a2b41d275eeba.1665203531.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-08T04:32:18","name":"[RFC,1/1] RISC-V: Imply '\''Zicsr'\'' from privileged extensions with CSRs","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/58e16a241d7376fcae2515c6bd5a2b41d275eeba.1665203531.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1830,"url":"https://patchwork.plctlab.org/api/1.2/patches/1830/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/cb5076fc96e8f2097779a3abcde843dcdd660031.1665203660.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-08T04:34:23","name":"[1/5] opcodes/riscv-dis.c: Tidying with comments/clarity","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/cb5076fc96e8f2097779a3abcde843dcdd660031.1665203660.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1832,"url":"https://patchwork.plctlab.org/api/1.2/patches/1832/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1f1aa0838bf9c4f10a45fcfe3c682f7efc79d9ae.1665203660.git.research_trasio@irq.a4lg.com/","msgid":"<1f1aa0838bf9c4f10a45fcfe3c682f7efc79d9ae.1665203660.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-08T04:34:24","name":"[2/5] opcodes/riscv-dis.c: Tidying with spacing","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1f1aa0838bf9c4f10a45fcfe3c682f7efc79d9ae.1665203660.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1831,"url":"https://patchwork.plctlab.org/api/1.2/patches/1831/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/740bc5e2d2618d236519b39fedd1a1d7ae4e05da.1665203660.git.research_trasio@irq.a4lg.com/","msgid":"<740bc5e2d2618d236519b39fedd1a1d7ae4e05da.1665203660.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-08T04:34:25","name":"[3/5] opcodes/riscv-dis.c: Use bool type whenever possible","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/740bc5e2d2618d236519b39fedd1a1d7ae4e05da.1665203660.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1833,"url":"https://patchwork.plctlab.org/api/1.2/patches/1833/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6e3a9c235e317f441b4383b3daa68f2051bdc149.1665203660.git.research_trasio@irq.a4lg.com/","msgid":"<6e3a9c235e317f441b4383b3daa68f2051bdc149.1665203660.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-08T04:34:26","name":"[4/5] opcodes/riscv-dis.c: Make XLEN variable static","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6e3a9c235e317f441b4383b3daa68f2051bdc149.1665203660.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1834,"url":"https://patchwork.plctlab.org/api/1.2/patches/1834/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ad929233a62d887495122721340b2f9c80392963.1665203660.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-08T04:34:27","name":"[5/5] opcodes/riscv-dis.c: Remove last_map_state","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ad929233a62d887495122721340b2f9c80392963.1665203660.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1836,"url":"https://patchwork.plctlab.org/api/1.2/patches/1836/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d07e2b6f36ea2fd5830924a9bfeda941b774b687.1665290422.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-09T05:09:22","name":"RISC-V: Move certain arrays to riscv-opc.c","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d07e2b6f36ea2fd5830924a9bfeda941b774b687.1665290422.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1844,"url":"https://patchwork.plctlab.org/api/1.2/patches/1844/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010004623.16582-1-mark@harmstone.com/","msgid":"<20221010004623.16582-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-10T00:46:22","name":"[v2,1/2] ld: Add --pdb option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010004623.16582-1-mark@harmstone.com/mbox/"},{"id":1845,"url":"https://patchwork.plctlab.org/api/1.2/patches/1845/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010004623.16582-2-mark@harmstone.com/","msgid":"<20221010004623.16582-2-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-10T00:46:23","name":"[v2,2/2] ld: Add minimal pdb generation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010004623.16582-2-mark@harmstone.com/mbox/"},{"id":1890,"url":"https://patchwork.plctlab.org/api/1.2/patches/1890/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010200433.414320-1-vladimir.mezentsev@oracle.com/","msgid":"<20221010200433.414320-1-vladimir.mezentsev@oracle.com>","list_archive_url":null,"date":"2022-10-10T20:04:33","name":"gprofng: run tests without installation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010200433.414320-1-vladimir.mezentsev@oracle.com/mbox/"},{"id":1893,"url":"https://patchwork.plctlab.org/api/1.2/patches/1893/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010230426.719238-1-vladimir.mezentsev@oracle.com/","msgid":"<20221010230426.719238-1-vladimir.mezentsev@oracle.com>","list_archive_url":null,"date":"2022-10-10T23:04:26","name":"[2/2] gprofng: use the --libdir path to find libraries","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010230426.719238-1-vladimir.mezentsev@oracle.com/mbox/"},{"id":1894,"url":"https://patchwork.plctlab.org/api/1.2/patches/1894/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010235155.842469-1-vladimir.mezentsev@oracle.com/","msgid":"<20221010235155.842469-1-vladimir.mezentsev@oracle.com>","list_archive_url":null,"date":"2022-10-10T23:51:55","name":"[3/3] gprofng: no need to build version.texi","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010235155.842469-1-vladimir.mezentsev@oracle.com/mbox/"},{"id":1895,"url":"https://patchwork.plctlab.org/api/1.2/patches/1895/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011003702.4287-1-mark@harmstone.com/","msgid":"<20221011003702.4287-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-11T00:37:01","name":"[v3,1/2] ld: Add --pdb option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011003702.4287-1-mark@harmstone.com/mbox/"},{"id":1897,"url":"https://patchwork.plctlab.org/api/1.2/patches/1897/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011003702.4287-2-mark@harmstone.com/","msgid":"<20221011003702.4287-2-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-11T00:37:02","name":"[v3,2/2] ld: Add minimal pdb generation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011003702.4287-2-mark@harmstone.com/mbox/"},{"id":1928,"url":"https://patchwork.plctlab.org/api/1.2/patches/1928/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011175332.17156-1-mark@harmstone.com/","msgid":"<20221011175332.17156-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-11T17:53:31","name":"[v4,1/2] ld: Add --pdb option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011175332.17156-1-mark@harmstone.com/mbox/"},{"id":1929,"url":"https://patchwork.plctlab.org/api/1.2/patches/1929/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011175332.17156-2-mark@harmstone.com/","msgid":"<20221011175332.17156-2-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-11T17:53:32","name":"[v4,2/2] ld: Add minimal pdb generation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011175332.17156-2-mark@harmstone.com/mbox/"},{"id":1941,"url":"https://patchwork.plctlab.org/api/1.2/patches/1941/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221012031005.237446-1-simon.marchi@polymtl.ca/","msgid":"<20221012031005.237446-1-simon.marchi@polymtl.ca>","list_archive_url":null,"date":"2022-10-12T03:10:05","name":"[pushed] Re-apply \"Pass PKG_CONFIG_PATH down from top-level Makefile\"","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221012031005.237446-1-simon.marchi@polymtl.ca/mbox/"},{"id":1976,"url":"https://patchwork.plctlab.org/api/1.2/patches/1976/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1216a3f8-2273-8681-f528-9493a66891f0@suse.com/","msgid":"<1216a3f8-2273-8681-f528-9493a66891f0@suse.com>","list_archive_url":null,"date":"2022-10-13T08:16:49","name":"[v4,1/8] x86: constify parse_insn()'\''s input","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1216a3f8-2273-8681-f528-9493a66891f0@suse.com/mbox/"},{"id":1977,"url":"https://patchwork.plctlab.org/api/1.2/patches/1977/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/11599bbe-c779-aa9f-4d5d-c2243f0e69dc@suse.com/","msgid":"<11599bbe-c779-aa9f-4d5d-c2243f0e69dc@suse.com>","list_archive_url":null,"date":"2022-10-13T08:17:17","name":"[v4,2/8] x86: introduce Pass2 insn attribute","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/11599bbe-c779-aa9f-4d5d-c2243f0e69dc@suse.com/mbox/"},{"id":1978,"url":"https://patchwork.plctlab.org/api/1.2/patches/1978/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/357273a3-060c-23db-72da-3fc9d1be3d2a@suse.com/","msgid":"<357273a3-060c-23db-72da-3fc9d1be3d2a@suse.com>","list_archive_url":null,"date":"2022-10-13T08:18:09","name":"[v4,3/8] x86: re-work insn/suffix recognition","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/357273a3-060c-23db-72da-3fc9d1be3d2a@suse.com/mbox/"},{"id":1979,"url":"https://patchwork.plctlab.org/api/1.2/patches/1979/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0ec0587f-6a7b-45b6-8346-e5d774e73636@suse.com/","msgid":"<0ec0587f-6a7b-45b6-8346-e5d774e73636@suse.com>","list_archive_url":null,"date":"2022-10-13T08:18:39","name":"[v4,4/8] x86-64: further re-work insn/suffix recognition to also cover MOVSL","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0ec0587f-6a7b-45b6-8346-e5d774e73636@suse.com/mbox/"},{"id":1980,"url":"https://patchwork.plctlab.org/api/1.2/patches/1980/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fb617d0b-8759-3169-5a65-1178b7fef3d7@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-13T08:19:34","name":"[v4,5/8] ix86: don'\''t recognize/derive Q suffix in the common case","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fb617d0b-8759-3169-5a65-1178b7fef3d7@suse.com/mbox/"},{"id":1981,"url":"https://patchwork.plctlab.org/api/1.2/patches/1981/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1df3bd01-99c5-f56c-d937-970edd42b2b8@suse.com/","msgid":"<1df3bd01-99c5-f56c-d937-970edd42b2b8@suse.com>","list_archive_url":null,"date":"2022-10-13T08:20:14","name":"[v4,6/8] x86-64: allow HLE store of accumulator to absolute 32-bit address","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1df3bd01-99c5-f56c-d937-970edd42b2b8@suse.com/mbox/"},{"id":1982,"url":"https://patchwork.plctlab.org/api/1.2/patches/1982/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8486a218-39ec-16b2-5c6c-5037196b93cf@suse.com/","msgid":"<8486a218-39ec-16b2-5c6c-5037196b93cf@suse.com>","list_archive_url":null,"date":"2022-10-13T08:21:00","name":"[v4,7/8] x86: move bad-use-of-TLS-reloc check","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8486a218-39ec-16b2-5c6c-5037196b93cf@suse.com/mbox/"},{"id":1983,"url":"https://patchwork.plctlab.org/api/1.2/patches/1983/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7d82692d-93df-fbee-9efb-2f44e8a91df3@suse.com/","msgid":"<7d82692d-93df-fbee-9efb-2f44e8a91df3@suse.com>","list_archive_url":null,"date":"2022-10-13T08:22:00","name":"[v4,8/8] x86: drop (now) stray IsString","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7d82692d-93df-fbee-9efb-2f44e8a91df3@suse.com/mbox/"},{"id":2013,"url":"https://patchwork.plctlab.org/api/1.2/patches/2013/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8ab93d7a617ad480dd786210f46db0e5aa07d1ac.1665655719.git.research_trasio@irq.a4lg.com/","msgid":"<8ab93d7a617ad480dd786210f46db0e5aa07d1ac.1665655719.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-13T10:11:41","name":"include: Declare getopt function on old GNU libc","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8ab93d7a617ad480dd786210f46db0e5aa07d1ac.1665655719.git.research_trasio@irq.a4lg.com/mbox/"},{"id":2352,"url":"https://patchwork.plctlab.org/api/1.2/patches/2352/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221013201332.2747246-1-maskray@google.com/","msgid":"<20221013201332.2747246-1-maskray@google.com>","list_archive_url":null,"date":"2022-10-13T20:13:32","name":"ld: Add --undefined-version","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221013201332.2747246-1-maskray@google.com/mbox/"},{"id":2532,"url":"https://patchwork.plctlab.org/api/1.2/patches/2532/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014063520.1428330-2-zengxiao@eswincomputing.com/","msgid":"<20221014063520.1428330-2-zengxiao@eswincomputing.com>","list_archive_url":null,"date":"2022-10-14T06:35:20","name":"[1/1] RISC-V: Make R_RISCV_SUB6 conforms to riscv abi standard","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014063520.1428330-2-zengxiao@eswincomputing.com/mbox/"},{"id":2560,"url":"https://patchwork.plctlab.org/api/1.2/patches/2560/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/027ae69a-636b-6757-297a-eec42936401e@linaro.org/","msgid":"<027ae69a-636b-6757-297a-eec42936401e@linaro.org>","list_archive_url":null,"date":"2022-10-14T07:58:22","name":"[v3] aarch64-pe support for LD, GAS and BFD","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/027ae69a-636b-6757-297a-eec42936401e@linaro.org/mbox/"},{"id":2602,"url":"https://patchwork.plctlab.org/api/1.2/patches/2602/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-2-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-2-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:39","name":"[01/10] Support Intel AVX-IFMA","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-2-haochen.jiang@intel.com/mbox/"},{"id":2608,"url":"https://patchwork.plctlab.org/api/1.2/patches/2608/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-3-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-3-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:40","name":"[02/10] Support Intel AVX-VNNI-INT8","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-3-haochen.jiang@intel.com/mbox/"},{"id":2611,"url":"https://patchwork.plctlab.org/api/1.2/patches/2611/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-4-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-4-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:41","name":"[03/10] Support Intel AVX-NE-CONVERT","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-4-haochen.jiang@intel.com/mbox/"},{"id":2610,"url":"https://patchwork.plctlab.org/api/1.2/patches/2610/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-5-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-5-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:42","name":"[04/10] Support Intel CMPccXADD","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-5-haochen.jiang@intel.com/mbox/"},{"id":2601,"url":"https://patchwork.plctlab.org/api/1.2/patches/2601/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-6-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-6-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:43","name":"[05/10] Add handler for more i386_cpu_flags","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-6-haochen.jiang@intel.com/mbox/"},{"id":2606,"url":"https://patchwork.plctlab.org/api/1.2/patches/2606/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-7-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-7-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:44","name":"[06/10] Support Intel RAO-INT","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-7-haochen.jiang@intel.com/mbox/"},{"id":2609,"url":"https://patchwork.plctlab.org/api/1.2/patches/2609/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-8-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-8-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:45","name":"[07/10] Support Intel WRMSRNS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-8-haochen.jiang@intel.com/mbox/"},{"id":2605,"url":"https://patchwork.plctlab.org/api/1.2/patches/2605/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-9-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-9-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:46","name":"[08/10] Support Intel MSRLIST","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-9-haochen.jiang@intel.com/mbox/"},{"id":2607,"url":"https://patchwork.plctlab.org/api/1.2/patches/2607/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-10-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-10-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:47","name":"[09/10] Support Intel AMX-FP16","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-10-haochen.jiang@intel.com/mbox/"},{"id":2604,"url":"https://patchwork.plctlab.org/api/1.2/patches/2604/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-11-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-11-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:48","name":"[10/10] Support Intel PREFETCHI","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-11-haochen.jiang@intel.com/mbox/"},{"id":2643,"url":"https://patchwork.plctlab.org/api/1.2/patches/2643/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7bac66be-535e-9051-d674-f2f5ba180e17@suse.com/","msgid":"<7bac66be-535e-9051-d674-f2f5ba180e17@suse.com>","list_archive_url":null,"date":"2022-10-14T10:22:34","name":"x86: fold AVX512-VNNI disassembler entries with AVX-VNNI ones","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7bac66be-535e-9051-d674-f2f5ba180e17@suse.com/mbox/"},{"id":2654,"url":"https://patchwork.plctlab.org/api/1.2/patches/2654/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0lIo5+ncY/MqBEq@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-14T11:31:47","name":"PR29677, Field `the_bfd` of `asymbol` is uninitialised","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0lIo5+ncY/MqBEq@squeak.grove.modra.org/mbox/"},{"id":2656,"url":"https://patchwork.plctlab.org/api/1.2/patches/2656/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0lJksn49ZpABY89@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-14T11:35:46","name":"e200 LSP support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0lJksn49ZpABY89@squeak.grove.modra.org/mbox/"},{"id":2657,"url":"https://patchwork.plctlab.org/api/1.2/patches/2657/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0lJxxYoeD5iDYAD@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-14T11:36:39","name":"PowerPC SPE disassembly and tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0lJxxYoeD5iDYAD@squeak.grove.modra.org/mbox/"},{"id":2695,"url":"https://patchwork.plctlab.org/api/1.2/patches/2695/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/DM6PR12MB4219611F6CC2A0702884A602E7249@DM6PR12MB4219.namprd12.prod.outlook.com/","msgid":"","list_archive_url":null,"date":"2022-10-14T13:29:40","name":"Binutils: Adding new testcase for addr2line.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/DM6PR12MB4219611F6CC2A0702884A602E7249@DM6PR12MB4219.namprd12.prod.outlook.com/mbox/"},{"id":2700,"url":"https://patchwork.plctlab.org/api/1.2/patches/2700/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9fd2c88d-98b2-99a4-419f-c7235b2cf960@suse.com/","msgid":"<9fd2c88d-98b2-99a4-419f-c7235b2cf960@suse.com>","list_archive_url":null,"date":"2022-10-14T14:11:35","name":"x86: properly decode EVEX.W for AVX512_4{FMAPS,VNNIW} insns","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9fd2c88d-98b2-99a4-419f-c7235b2cf960@suse.com/mbox/"},{"id":2981,"url":"https://patchwork.plctlab.org/api/1.2/patches/2981/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0uLzalqjm4C87GN@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-16T04:42:53","name":"PowerPC se_rfmci and VLE, SPE2 and LSP insns with -many","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0uLzalqjm4C87GN@squeak.grove.modra.org/mbox/"},{"id":3152,"url":"https://patchwork.plctlab.org/api/1.2/patches/3152/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221016232419.1135-1-mark@harmstone.com/","msgid":"<20221016232419.1135-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-16T23:24:18","name":"[v5,1/2] ld: Add --pdb option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221016232419.1135-1-mark@harmstone.com/mbox/"},{"id":3151,"url":"https://patchwork.plctlab.org/api/1.2/patches/3151/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221016232419.1135-2-mark@harmstone.com/","msgid":"<20221016232419.1135-2-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-16T23:24:19","name":"[v5,2/2] ld: Add minimal pdb generation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221016232419.1135-2-mark@harmstone.com/mbox/"},{"id":3258,"url":"https://patchwork.plctlab.org/api/1.2/patches/3258/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/19c08747-fa5b-1e67-3dd2-c891a2c0c1fa@suse.com/","msgid":"<19c08747-fa5b-1e67-3dd2-c891a2c0c1fa@suse.com>","list_archive_url":null,"date":"2022-10-17T07:44:51","name":"x86: correct CPU_AMX_{BF16,INT8}_FLAGS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/19c08747-fa5b-1e67-3dd2-c891a2c0c1fa@suse.com/mbox/"},{"id":3272,"url":"https://patchwork.plctlab.org/api/1.2/patches/3272/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/85dd526c-d3a7-72dc-5444-ed5573eebec1@suse.com/","msgid":"<85dd526c-d3a7-72dc-5444-ed5573eebec1@suse.com>","list_archive_url":null,"date":"2022-10-17T08:30:12","name":"x86: generalize gas documentation for disabling of ISA extensions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/85dd526c-d3a7-72dc-5444-ed5573eebec1@suse.com/mbox/"},{"id":3759,"url":"https://patchwork.plctlab.org/api/1.2/patches/3759/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-2-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-2-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:15:58","name":"[V2,01/15] sframe.h: Add SFrame format definition","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-2-indu.bhagat@oracle.com/mbox/"},{"id":3762,"url":"https://patchwork.plctlab.org/api/1.2/patches/3762/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-3-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-3-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:15:59","name":"[V2,02/15] gas: add new command line option --gsframe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-3-indu.bhagat@oracle.com/mbox/"},{"id":3761,"url":"https://patchwork.plctlab.org/api/1.2/patches/3761/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-4-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-4-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:00","name":"[V2,03/15] gas: generate .sframe from CFI directives","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-4-indu.bhagat@oracle.com/mbox/"},{"id":3760,"url":"https://patchwork.plctlab.org/api/1.2/patches/3760/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-5-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-5-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:01","name":"[V2,04/15] gas: testsuite: add new tests for SFrame unwind info","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-5-indu.bhagat@oracle.com/mbox/"},{"id":3764,"url":"https://patchwork.plctlab.org/api/1.2/patches/3764/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-6-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-6-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:02","name":"[V2,05/15] libsframe: add the SFrame library","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-6-indu.bhagat@oracle.com/mbox/"},{"id":3766,"url":"https://patchwork.plctlab.org/api/1.2/patches/3766/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-7-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-7-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:03","name":"[V2,06/15] bfd: linker: merge .sframe sections","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-7-indu.bhagat@oracle.com/mbox/"},{"id":3763,"url":"https://patchwork.plctlab.org/api/1.2/patches/3763/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-8-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-8-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:04","name":"[V2,07/15] readelf/objdump: support for SFrame section","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-8-indu.bhagat@oracle.com/mbox/"},{"id":3765,"url":"https://patchwork.plctlab.org/api/1.2/patches/3765/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-9-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-9-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:05","name":"[V2,08/15] unwinder: generate backtrace using SFrame format","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-9-indu.bhagat@oracle.com/mbox/"},{"id":3770,"url":"https://patchwork.plctlab.org/api/1.2/patches/3770/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-10-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-10-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:06","name":"[V2,09/15] unwinder: Add SFrame unwinder tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-10-indu.bhagat@oracle.com/mbox/"},{"id":3769,"url":"https://patchwork.plctlab.org/api/1.2/patches/3769/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-11-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-11-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:07","name":"[V2,10/15] gdb: sim: buildsystem changes to accommodate libsframe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-11-indu.bhagat@oracle.com/mbox/"},{"id":3771,"url":"https://patchwork.plctlab.org/api/1.2/patches/3771/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-12-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-12-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:08","name":"[V2,11/15] libctf: add libsframe to LDFLAGS and LIBS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-12-indu.bhagat@oracle.com/mbox/"},{"id":3768,"url":"https://patchwork.plctlab.org/api/1.2/patches/3768/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-13-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-13-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:09","name":"[V2,12/15] src-release.sh: Add libsframe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-13-indu.bhagat@oracle.com/mbox/"},{"id":3767,"url":"https://patchwork.plctlab.org/api/1.2/patches/3767/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-14-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-14-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:10","name":"[V2,13/15] binutils/NEWS: add text for SFrame support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-14-indu.bhagat@oracle.com/mbox/"},{"id":3772,"url":"https://patchwork.plctlab.org/api/1.2/patches/3772/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-15-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-15-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:11","name":"[V2,14/15] gas/NEWS: add text about new command line option and SFrame support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-15-indu.bhagat@oracle.com/mbox/"},{"id":3773,"url":"https://patchwork.plctlab.org/api/1.2/patches/3773/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-16-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-16-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:12","name":"[V2,15/15] doc: add SFrame spec file","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-16-indu.bhagat@oracle.com/mbox/"},{"id":3999,"url":"https://patchwork.plctlab.org/api/1.2/patches/3999/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221018081205.17880-1-krebbel@linux.ibm.com/","msgid":"<20221018081205.17880-1-krebbel@linux.ibm.com>","list_archive_url":null,"date":"2022-10-18T08:12:05","name":"[1/1] IBM zSystems: Issue error for *DBL relocs on misaligned symbols","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221018081205.17880-1-krebbel@linux.ibm.com/mbox/"},{"id":4141,"url":"https://patchwork.plctlab.org/api/1.2/patches/4141/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/baffaf673f17692b7bcbd604b31800b189988596.camel@espressif.com/","msgid":"","list_archive_url":null,"date":"2022-10-18T12:12:07","name":"xtensa: use definitions from xtensa-config.h","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/baffaf673f17692b7bcbd604b31800b189988596.camel@espressif.com/mbox/"},{"id":4272,"url":"https://patchwork.plctlab.org/api/1.2/patches/4272/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221018174914.470062-1-hjl.tools@gmail.com/","msgid":"<20221018174914.470062-1-hjl.tools@gmail.com>","list_archive_url":null,"date":"2022-10-18T17:49:14","name":"x86: Disable AVX-VNNI when disabling AVX2","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221018174914.470062-1-hjl.tools@gmail.com/mbox/"},{"id":4998,"url":"https://patchwork.plctlab.org/api/1.2/patches/4998/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c2f76e95-09f6-1d92-7ef4-38a3c2955fcd@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-19T09:52:46","name":"x86: re-work AVX-VNNI support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c2f76e95-09f6-1d92-7ef4-38a3c2955fcd@suse.com/mbox/"},{"id":5276,"url":"https://patchwork.plctlab.org/api/1.2/patches/5276/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0/lLtlKqqsmAx0s@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-19T11:53:18","name":"Fix addr2line test for ppc64 elfv1 and mingw","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0/lLtlKqqsmAx0s@squeak.grove.modra.org/mbox/"},{"id":5424,"url":"https://patchwork.plctlab.org/api/1.2/patches/5424/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/07bfebbf3843b47e13d82d4fa16eb14fec942ef7.1666184962.git.research_trasio@irq.a4lg.com/","msgid":"<07bfebbf3843b47e13d82d4fa16eb14fec942ef7.1666184962.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:09:54","name":"binutils: Remove unused substitution PROGRAM","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/07bfebbf3843b47e13d82d4fa16eb14fec942ef7.1666184962.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5433,"url":"https://patchwork.plctlab.org/api/1.2/patches/5433/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2fa7ff719223232402e82a9c91331aea22ace1bb.1666185116.git.research_trasio@irq.a4lg.com/","msgid":"<2fa7ff719223232402e82a9c91331aea22ace1bb.1666185116.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:11:55","name":"[v2,1/8] RISC-V: Add a space at the end of pinfo","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2fa7ff719223232402e82a9c91331aea22ace1bb.1666185116.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5435,"url":"https://patchwork.plctlab.org/api/1.2/patches/5435/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1b30cce5db2cce3b8edca42ab5da114d0b8c9e93.1666185116.git.research_trasio@irq.a4lg.com/","msgid":"<1b30cce5db2cce3b8edca42ab5da114d0b8c9e93.1666185116.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:11:56","name":"[v2,2/8] RISC-V: Fix obvious misalignments ('\''Zbb'\''/'\''Zba'\'')","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1b30cce5db2cce3b8edca42ab5da114d0b8c9e93.1666185116.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5437,"url":"https://patchwork.plctlab.org/api/1.2/patches/5437/","web_url":"https://patchwor++ jq -rc '.[].name' k.plctlab.org/project/binutils-gdb/patch/6b0857aa1a2d15ca1cf00b4dcaae0032efbb88ff.1666185116.git.research_trasio@irq.a4lg.com/","msgid":"<6b0857aa1a2d15ca1cf00b4dcaae0032efbb88ff.1666185116.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:11:57","name":"[v2,3/8] RISC-V: Remove spaces in opcode entries","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6b0857aa1a2d15ca1cf00b4dcaae0032efbb88ff.1666185116.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5436,"url":"https://patchwork.plctlab.org/api/1.2/patches/5436/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/889d956caac0f2e95543a14afaeed97188ce384c.1666185116.git.research_trasio@irq.a4lg.com/","msgid":"<889d956caac0f2e95543a14afaeed97188ce384c.1666185116.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:11:58","name":"[v2,4/8] RISC-V: Remove unused instruction macros","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/889d956caac0f2e95543a14afaeed97188ce384c.1666185116.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5440,"url":"https://patchwork.plctlab.org/api/1.2/patches/5440/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8f226ee20d8a5ef6ad7b6c4408b44794a99d542a.1666185116.git.research_trasio@irq.a4lg.com/","msgid":"<8f226ee20d8a5ef6ad7b6c4408b44794a99d542a.1666185116.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:11:59","name":"[v2,5/8] RISC-V: Complete tidying up with SCALL and SBREAK","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8f226ee20d8a5ef6ad7b6c4408b44794a99d542a.1666185116.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5442,"url":"https://patchwork.plctlab.org/api/1.2/patches/5442/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4070184c454a05a39adf0790951e5856e6b2ecb6.1666185116.git.research_trasio@irq.a4lg.com/","msgid":"<4070184c454a05a39adf0790951e5856e6b2ecb6.1666185116.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:12:00","name":"[v2,6/8] RISC-V: Tidying up with fmv.w.x and fmv.x.w","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4070184c454a05a39adf0790951e5856e6b2ecb6.1666185116.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5438,"url":"https://patchwork.plctlab.org/api/1.2/patches/5438/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c1ccda3e7c8fb297eda46dab3936d5c5977178fc.1666185116.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-19T13:12:01","name":"[v2,7/8] RISC-V: Make alias instructions aliases","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c1ccda3e7c8fb297eda46dab3936d5c5977178fc.1666185116.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5441,"url":"https://patchwork.plctlab.org/api/1.2/patches/5441/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/413cfca82c7e8d8a2e977dfda9135903c9cb7c57.1666185116.git.research_trasio@irq.a4lg.com/","msgid":"<413cfca82c7e8d8a2e977dfda9135903c9cb7c57.1666185116.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:12:02","name":"[v2,8/8] RISC-V: Use defined mask and match values","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/413cfca82c7e8d8a2e977dfda9135903c9cb7c57.1666185116.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5439,"url":"https://patchwork.plctlab.org/api/1.2/patches/5439/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/345c5c3b3a53eab04a1e6e91197de2642095c94f.1666185237.git.research_trasio@irq.a4lg.com/","msgid":"<345c5c3b3a53eab04a1e6e91197de2642095c94f.1666185237.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:14:01","name":"RISC-V: Remove RV32EF conflict","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/345c5c3b3a53eab04a1e6e91197de2642095c94f.1666185237.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5616,"url":"https://patchwork.plctlab.org/api/1.2/patches/5616/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019145608.45213-5-haochen.jiang@intel.com/","msgid":"<20221019145608.45213-5-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T14:56:02","name":"[04/10] Support Intel CMPccXADD","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019145608.45213-5-haochen.jiang@intel.com/mbox/"},{"id":5614,"url":"https://patchwork.plctlab.org/api/1.2/patches/5614/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019145608.45213-6-haochen.jiang@intel.com/","msgid":"<20221019145608.45213-6-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T14:56:03","name":"[05/10] Add handler for more i386_cpu_flags","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019145608.45213-6-haochen.jiang@intel.com/mbox/"},{"id":5672,"url":"https://patchwork.plctlab.org/api/1.2/patches/5672/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-2-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-2-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:25","name":"[01/10] Support Intel AVX-IFMA","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-2-haochen.jiang@intel.com/mbox/"},{"id":5691,"url":"https://patchwork.plctlab.org/api/1.2/patches/5691/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-3-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-3-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:26","name":"[02/10] Support Intel AVX-VNNI-INT8","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-3-haochen.jiang@intel.com/mbox/"},{"id":5690,"url":"https://patchwork.plctlab.org/api/1.2/patches/5690/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-4-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-4-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:27","name":"[03/10] Support Intel AVX-NE-CONVERT","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-4-haochen.jiang@intel.com/mbox/"},{"id":5689,"url":"https://patchwork.plctlab.org/api/1.2/patches/5689/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-5-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-5-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:28","name":"[04/10] Support Intel CMPccXADD","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-5-haochen.jiang@intel.com/mbox/"},{"id":5676,"url":"https://patchwork.plctlab.org/api/1.2/patches/5676/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-6-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-6-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:29","name":"[05/10] Add handler for more i386_cpu_flags","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-6-haochen.jiang@intel.com/mbox/"},{"id":5677,"url":"https://patchwork.plctlab.org/api/1.2/patches/5677/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-7-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-7-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:30","name":"[06/10] Support Intel RAO-INT","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-7-haochen.jiang@intel.com/mbox/"},{"id":5681,"url":"https://patchwork.plctlab.org/api/1.2/patches/5681/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-8-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-8-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:31","name":"[07/10] Support Intel WRMSRNS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-8-haochen.jiang@intel.com/mbox/"},{"id":5682,"url":"https://patchwork.plctlab.org/api/1.2/patches/5682/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-9-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-9-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:32","name":"[08/10] Support Intel MSRLIST","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-9-haochen.jiang@intel.com/mbox/"},{"id":5673,"url":"https://patchwork.plctlab.org/api/1.2/patches/5673/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-10-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-10-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:33","name":"[09/10] Support Intel AMX-FP16","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-10-haochen.jiang@intel.com/mbox/"},{"id":5686,"url":"https://patchwork.plctlab.org/api/1.2/patches/5686/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-11-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-11-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:34","name":"[10/10] Support Intel PREFETCHI","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-11-haochen.jiang@intel.com/mbox/"},{"id":11921,"url":"https://patchwork.plctlab.org/api/1.2/patches/11921/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027190052.10536-1-mark@harmstone.com/","msgid":"<20221027190052.10536-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-27T19:00:51","name":"[1/2] ld: Add section header stream to PDB files","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027190052.10536-1-mark@harmstone.com/mbox/"},{"id":11922,"url":"https://patchwork.plctlab.org/api/1.2/patches/11922/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027190052.10536-2-mark@harmstone.com/","msgid":"<20221027190052.10536-2-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-27T19:00:52","name":"[2/2] ld: Add publics stream to PDB files","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027190052.10536-2-mark@harmstone.com/mbox/"},{"id":11965,"url":"https://patchwork.plctlab.org/api/1.2/patches/11965/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027202719.32497-1-palmer@rivosinc.com/","msgid":"<20221027202719.32497-1-palmer@rivosinc.com>","list_archive_url":null,"date":"2022-10-27T20:27:18","name":"[1/2] gas: NEWS: Add a missing newline","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027202719.32497-1-palmer@rivosinc.com/mbox/"},{"id":11966,"url":"https://patchwork.plctlab.org/api/1.2/patches/11966/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027202719.32497-2-palmer@rivosinc.com/","msgid":"<20221027202719.32497-2-palmer@rivosinc.com>","list_archive_url":null,"date":"2022-10-27T20:27:19","name":"[2/2] gas: NEWS: Note support for RISC-V Zawrs","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027202719.32497-2-palmer@rivosinc.com/mbox/"},{"id":12016,"url":"https://patchwork.plctlab.org/api/1.2/patches/12016/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/21ec9a18-fa89-0828-f625-499680022ec7@linux.ibm.com/","msgid":"<21ec9a18-fa89-0828-f625-499680022ec7@linux.ibm.com>","list_archive_url":null,"date":"2022-10-28T00:35:19","name":"[COMMITTED] PowerPC: Add support for RFC02653 - Dense Math Facility","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/21ec9a18-fa89-0828-f625-499680022ec7@linux.ibm.com/mbox/"}],"public":true,"mbox":"https://patchwork.plctlab.org/bundle/patchwork-bot/binutils-gdb_2022-10/mbox/"},{"id":7,"url":"https://patchwork.plctlab.org/api/1.2/bundles/7/","web_url":"https://patchwork.plctlab.org/bundle/patchwork-bot/binutils-gdb_2022-09/","project":{"id":2,"url":"https://patchwork.plctlab.org/api/1.2/projects/2/","name":"binutils-gdb","link_name":"binutils-gdb","list_id":"binutils.sourceware.org","list_email":"binutils@sourceware.org","web_url":"https://sourceware.org/mailman/listinfo/binutils","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"name":"binutils-gdb_2022-09","owner":{"id":3,"url":"https://patchwork.plctlab.org/api/1.2/users/3/","username":"patchwork-bot","first_name":"","last_name":"","email":"ouuuleilei@gmail.com"},"patches":[{"id":1573,"url":"https://patchwork.plctlab.org/api/1.2/patches/1573/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930073211.2634-1-jiawei@iscas.ac.cn/","msgid":"<20220930073211.2634-1-jiawei@iscas.ac.cn>","list_archive_url":null,"date":"2022-09-30T07:32:11","name":"[V2] RISC-V: Add Smepmp CSR '\''mseccfg'\'' define and testcases.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930073211.2634-1-jiawei@iscas.ac.cn/mbox/"},{"id":1577,"url":"https://patchwork.plctlab.org/api/1.2/patches/1577/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/76fa0c3c-2303-ebdf-a765-ac4731581517@suse.com/","msgid":"<76fa0c3c-2303-ebdf-a765-ac4731581517@suse.com>","list_archive_url":null,"date":"2022-09-30T08:54:18","name":"objcopy: avoid \"shadowing\" of remove() function name","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/76fa0c3c-2303-ebdf-a765-ac4731581517@suse.com/mbox/"},{"id":1579,"url":"https://patchwork.plctlab.org/api/1.2/patches/1579/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930085852.71213-1-nelson@rivosinc.com/","msgid":"<20220930085852.71213-1-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-09-30T08:58:51","name":"[1/2] RISC-V: Output mapping symbols with ISA string.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930085852.71213-1-nelson@rivosinc.com/mbox/"},{"id":1578,"url":"https://patchwork.plctlab.org/api/1.2/patches/1578/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930085852.71213-2-nelson@rivosinc.com/","msgid":"<20220930085852.71213-2-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-09-30T08:58:52","name":"[2/2] RISC-V: Refer mapping symbol to R_RISCV_RELAX for rvc relaxations.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930085852.71213-2-nelson@rivosinc.com/mbox/"},{"id":1581,"url":"https://patchwork.plctlab.org/api/1.2/patches/1581/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930092058.71286-1-nelson@rivosinc.com/","msgid":"<20220930092058.71286-1-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-09-30T09:20:57","name":"[1/2] RISC-V: Output mapping symbols with ISA string.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930092058.71286-1-nelson@rivosinc.com/mbox/"},{"id":1580,"url":"https://patchwork.plctlab.org/api/1.2/patches/1580/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930092058.71286-2-nelson@rivosinc.com/","msgid":"<20220930092058.71286-2-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-09-30T09:20:58","name":"[2/2] RISC-V: Refer mapping symbol to R_RISCV_RELAX for rvc relaxations.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930092058.71286-2-nelson@rivosinc.com/mbox/"},{"id":1582,"url":"https://patchwork.plctlab.org/api/1.2/patches/1582/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5874dd79-0cf5-d65c-7ea2-13adfc799c0f@suse.com/","msgid":"<5874dd79-0cf5-d65c-7ea2-13adfc799c0f@suse.com>","list_archive_url":null,"date":"2022-09-30T09:41:29","name":"RISC-V: fix build after \"Add support for arbitrary immediate encoding formats\"","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5874dd79-0cf5-d65c-7ea2-13adfc799c0f@suse.com/mbox/"},{"id":1583,"url":"https://patchwork.plctlab.org/api/1.2/patches/1583/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/57d8ac2a-5757-3776-9924-99c17ca69938@suse.com/","msgid":"<57d8ac2a-5757-3776-9924-99c17ca69938@suse.com>","list_archive_url":null,"date":"2022-09-30T09:42:08","name":"RISC-V: fallout from \"re-arrange opcode table for consistent alias handling\"","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/57d8ac2a-5757-3776-9924-99c17ca69938@suse.com/mbox/"},{"id":1584,"url":"https://patchwork.plctlab.org/api/1.2/patches/1584/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e76ef8f7-72b9-5103-cb43-9608af01d017@suse.com/","msgid":"","list_archive_url":null,"date":"2022-09-30T09:42:50","name":"RISC-V: don'\''t cast expressions'\'' X_add_number to long in diagnostics","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e76ef8f7-72b9-5103-cb43-9608af01d017@suse.com/mbox/"},{"id":1585,"url":"https://patchwork.plctlab.org/api/1.2/patches/1585/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/61355429-24b3-17d0-ab03-6fa57ee861d5@suse.cz/","msgid":"<61355429-24b3-17d0-ab03-6fa57ee861d5@suse.cz>","list_archive_url":null,"date":"2022-09-30T09:48:52","name":"[RFC] add --enable-zstd-compressed-debug-sections configure option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/61355429-24b3-17d0-ab03-6fa57ee861d5@suse.cz/mbox/"},{"id":1586,"url":"https://patchwork.plctlab.org/api/1.2/patches/1586/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930103919.323690-1-christoph.muellner@vrull.eu/","msgid":"<20220930103919.323690-1-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2022-09-30T10:39:19","name":"RISC-V: Eliminate long-casts of X_add_number in diagnostics","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930103919.323690-1-christoph.muellner@vrull.eu/mbox/"},{"id":1590,"url":"https://patchwork.plctlab.org/api/1.2/patches/1590/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/DM6PR12MB4219C943049C6D883DEA3E55E7569@DM6PR12MB4219.namprd12.prod.outlook.com/","msgid":"","list_archive_url":null,"date":"2022-09-30T11:41:37","name":"[V2] Ignore DWARF debug information for -gsplit-dwarf with dwarf-5.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/DM6PR12MB4219C943049C6D883DEA3E55E7569@DM6PR12MB4219.namprd12.prod.outlook.com/mbox/"},{"id":1591,"url":"https://patchwork.plctlab.org/api/1.2/patches/1591/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c10321f9-d289-ef84-d263-bc278fb3d31b@suse.com/","msgid":"","list_archive_url":null,"date":"2022-09-30T11:59:04","name":"[1/4] RISC-V/gas: drop riscv_subsets static variable","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c10321f9-d289-ef84-d263-bc278fb3d31b@suse.com/mbox/"},{"id":1593,"url":"https://patchwork.plctlab.org/api/1.2/patches/1593/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3244eea0-c18c-e49a-4588-d69423130226@suse.com/","msgid":"<3244eea0-c18c-e49a-4588-d69423130226@suse.com>","list_archive_url":null,"date":"2022-09-30T11:59:23","name":"[2/4] RISC-V/gas: drop stray call to install_insn()","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3244eea0-c18c-e49a-4588-d69423130226@suse.com/mbox/"},{"id":1592,"url":"https://patchwork.plctlab.org/api/1.2/patches/1592/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/385d01fd-7e57-1f3f-1bae-30aa0c313d63@suse.com/","msgid":"<385d01fd-7e57-1f3f-1bae-30aa0c313d63@suse.com>","list_archive_url":null,"date":"2022-09-30T11:59:45","name":"[3/4] RISC-V/gas: don'\''t open-code insn_length()","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/385d01fd-7e57-1f3f-1bae-30aa0c313d63@suse.com/mbox/"},{"id":1594,"url":"https://patchwork.plctlab.org/api/1.2/patches/1594/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f5757acf-7b90-a0e3-5eea-3b97cc226930@suse.com/","msgid":"","list_archive_url":null,"date":"2022-09-30T12:00:12","name":"[4/4] RISC-V/gas: allow generating up to 176-bit instructions with .insn","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f5757acf-7b90-a0e3-5eea-3b97cc226930@suse.com/mbox/"},{"id":1596,"url":"https://patchwork.plctlab.org/api/1.2/patches/1596/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930140503.38233-1-chigot@adacore.com/","msgid":"<20220930140503.38233-1-chigot@adacore.com>","list_archive_url":null,"date":"2022-09-30T14:05:03","name":"ld/testsuite: consistently add board_ldflags when linking with GCC","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930140503.38233-1-chigot@adacore.com/mbox/"}],"public":true,"mbox":"https://patchwork.plctlab.org/bundle/patchwork-bot/binutils-gdb_2022-09/mbox/"}]' + bundle_name_list='binutils-gdb_2022-10 binutils-gdb_2022-09' + [[ binutils-gdb_2022-10 binutils-gdb_2022-09 =~ 2022-10 ]] ++ jq -rc --arg bundle_name binutils-gdb_2022-10 '.[] | select(.name==$bundle_name) | (.id|tostring)' ++ echo '[{"id":6,"url":"https://patchwork.plctlab.org/api/1.2/bundles/6/","web_url":"https://patchwork.plctlab.org/bundle/patchwork-bot/binutils-gdb_2022-10/","project":{"id":2,"url":"https://patchwork.plctlab.org/api/1.2/projects/2/","name":"binutils-gdb","link_name":"binutils-gdb","list_id":"binutils.sourceware.org","list_email":"binutils@sourceware.org","web_url":"https://sourceware.org/mailman/listinfo/binutils","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"name":"binutils-gdb_2022-10","owner":{"id":3,"url":"https://patchwork.plctlab.org/api/1.2/users/3/","username":"patchwork-bot","first_name":"","last_name":"","email":"ouuuleilei@gmail.com"},"patches":[{"id":1592,"url":"https://patchwork.plctlab.org/api/1.2/patches/1592/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/385d01fd-7e57-1f3f-1bae-30aa0c313d63@suse.com/","msgid":"<385d01fd-7e57-1f3f-1bae-30aa0c313d63@suse.com>","list_archive_url":null,"date":"2022-09-30T11:59:45","name":"[3/4] RISC-V/gas: don'\''t open-code insn_length()","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/385d01fd-7e57-1f3f-1bae-30aa0c313d63@suse.com/mbox/"},{"id":1594,"url":"https://patchwork.plctlab.org/api/1.2/patches/1594/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f5757acf-7b90-a0e3-5eea-3b97cc226930@suse.com/","msgid":"","list_archive_url":null,"date":"2022-09-30T12:00:12","name":"[4/4] RISC-V/gas: allow generating up to 176-bit instructions with .insn","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f5757acf-7b90-a0e3-5eea-3b97cc226930@suse.com/mbox/"},{"id":1596,"url":"https://patchwork.plctlab.org/api/1.2/patches/1596/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930140503.38233-1-chigot@adacore.com/","msgid":"<20220930140503.38233-1-chigot@adacore.com>","list_archive_url":null,"date":"2022-09-30T14:05:03","name":"ld/testsuite: consistently add board_ldflags when linking with GCC","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930140503.38233-1-chigot@adacore.com/mbox/"},{"id":1619,"url":"https://patchwork.plctlab.org/api/1.2/patches/1619/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221001014451.532772-1-maskray@google.com/","msgid":"<20221001014451.532772-1-maskray@google.com>","list_archive_url":null,"date":"2022-10-01T01:44:51","name":"gold, dwp: support zstd compressed input debug sections [PR 29641]","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221001014451.532772-1-maskray@google.com/mbox/"},{"id":1620,"url":"https://patchwork.plctlab.org/api/1.2/patches/1620/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221001023846.590825-1-maskray@google.com/","msgid":"<20221001023846.590825-1-maskray@google.com>","list_archive_url":null,"date":"2022-10-01T02:38:46","name":"gold: add --compress-debug-sections=zstd [PR 29641]","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221001023846.590825-1-maskray@google.com/mbox/"},{"id":1623,"url":"https://patchwork.plctlab.org/api/1.2/patches/1623/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b4477c7f666bdeb7f8e998633c7b0cb62310b9ef.1664599545.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-01T04:45:52","name":"[RFC,1/1] RISC-V: Implement common register pair framework","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b4477c7f666bdeb7f8e998633c7b0cb62310b9ef.1664599545.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1625,"url":"https://patchwork.plctlab.org/api/1.2/patches/1625/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/53a265a1f14d17a6f7b106082f610994c5d546e0.1664602025.git.research_trasio@irq.a4lg.com/","msgid":"<53a265a1f14d17a6f7b106082f610994c5d546e0.1664602025.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-01T05:27:31","name":"[RFC,1/1] RISC-V: Implement extension variants","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/53a265a1f14d17a6f7b106082f610994c5d546e0.1664602025.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1626,"url":"https://patchwork.plctlab.org/api/1.2/patches/1626/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8db04962aba9c780f133840a8934353a58f223fe.1664602716.git.research_trasio@irq.a4lg.com/","msgid":"<8db04962aba9c780f133840a8934353a58f223fe.1664602716.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-01T05:39:26","name":"[1/1] RISC-V: Move supervisor instructions after all unprivileged ones","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8db04962aba9c780f133840a8934353a58f223fe.1664602716.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1627,"url":"https://patchwork.plctlab.org/api/1.2/patches/1627/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221001062057.681440-1-maskray@google.com/","msgid":"<20221001062057.681440-1-maskray@google.com>","list_archive_url":null,"date":"2022-10-01T06:20:57","name":"readelf: support zstd compressed debug sections [PR 29640]","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221001062057.681440-1-maskray@google.com/mbox/"},{"id":1631,"url":"https://patchwork.plctlab.org/api/1.2/patches/1631/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/619f112539c0bdecd58e25664f1250a3479a37f5.1664707612.git.aburgess@redhat.com/","msgid":"<619f112539c0bdecd58e25664f1250a3479a37f5.1664707612.git.aburgess@redhat.com>","list_archive_url":null,"date":"2022-10-02T10:47:52","name":"[PATCHv2,2/2] opcodes/arm: add disassembler styling for arm","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/619f112539c0bdecd58e25664f1250a3479a37f5.1664707612.git.aburgess@redhat.com/mbox/"},{"id":1635,"url":"https://patchwork.plctlab.org/api/1.2/patches/1635/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221002185433.gl7dvytfh5wthifx@lug-owl.de/","msgid":"<20221002185433.gl7dvytfh5wthifx@lug-owl.de>","list_archive_url":null,"date":"2022-10-02T18:54:33","name":"diagnostics.h: GCC 13 got -Wself-move, breaks GDB build","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221002185433.gl7dvytfh5wthifx@lug-owl.de/mbox/"},{"id":1637,"url":"https://patchwork.plctlab.org/api/1.2/patches/1637/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003014313.28766-1-mark@harmstone.com/","msgid":"<20221003014313.28766-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-03T01:43:12","name":"[1/2] ld: Add --pdb option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003014313.28766-1-mark@harmstone.com/mbox/"},{"id":1638,"url":"https://patchwork.plctlab.org/api/1.2/patches/1638/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003014313.28766-2-mark@harmstone.com/","msgid":"<20221003014313.28766-2-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-03T01:43:13","name":"[2/2] ld: Add minimal pdb generation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003014313.28766-2-mark@harmstone.com/mbox/"},{"id":1640,"url":"https://patchwork.plctlab.org/api/1.2/patches/1640/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/597ed978-d121-220c-b56b-2ffb94bd091c@suse.cz/","msgid":"<597ed978-d121-220c-b56b-2ffb94bd091c@suse.cz>","list_archive_url":null,"date":"2022-10-03T07:50:38","name":"[1/2] refactor usage of compressed_debug_section_type","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/597ed978-d121-220c-b56b-2ffb94bd091c@suse.cz/mbox/"},{"id":1641,"url":"https://patchwork.plctlab.org/api/1.2/patches/1641/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b8acdd83-f33a-74b8-e21a-23719a0b1a60@suse.cz/","msgid":"","list_archive_url":null,"date":"2022-10-03T07:50:44","name":"[2/2] add --enable-default-compressed-debug-sections-algorithm configure option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b8acdd83-f33a-74b8-e21a-23719a0b1a60@suse.cz/mbox/"},{"id":1642,"url":"https://patchwork.plctlab.org/api/1.2/patches/1642/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003101328.1790113-1-aburgess@redhat.com/","msgid":"<20221003101328.1790113-1-aburgess@redhat.com>","list_archive_url":null,"date":"2022-10-03T10:13:28","name":"opcodes/riscv: style csr names as registers","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003101328.1790113-1-aburgess@redhat.com/mbox/"},{"id":1643,"url":"https://patchwork.plctlab.org/api/1.2/patches/1643/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7ba14fc4472ce97d4f7a4433cad8a571e89f82f4.1664793840.git.research_trasio@irq.a4lg.com/","msgid":"<7ba14fc4472ce97d4f7a4433cad8a571e89f82f4.1664793840.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-03T10:43:59","name":"[v3,1/6] RISC-V: Fix immediates to have \"immediate\" style","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7ba14fc4472ce97d4f7a4433cad8a571e89f82f4.1664793840.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1644,"url":"https://patchwork.plctlab.org/api/1.2/patches/1644/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a498bec37c1fd1dcda57cbf95e5f8cfba09b31d3.1664793840.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-03T10:44:00","name":"[v3,2/6] RISC-V: Fix printf argument types corresponding %x","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a498bec37c1fd1dcda57cbf95e5f8cfba09b31d3.1664793840.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1647,"url":"https://patchwork.plctlab.org/api/1.2/patches/1647/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0002ea716713ace4998a33dde0b81f4f890d10bf.1664793840.git.research_trasio@irq.a4lg.com/","msgid":"<0002ea716713ace4998a33dde0b81f4f890d10bf.1664793840.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-03T10:44:01","name":"[v3,3/6] RISC-V: Optimize riscv_disassemble_data printf","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0002ea716713ace4998a33dde0b81f4f890d10bf.1664793840.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1646,"url":"https://patchwork.plctlab.org/api/1.2/patches/1646/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c65fc3e9aa58965d6768a28c9fd7467fea9897a5.1664793840.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-03T10:44:02","name":"[v3,4/6] RISC-V: Print comma and tabs as the \"text\" style","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c65fc3e9aa58965d6768a28c9fd7467fea9897a5.1664793840.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1648,"url":"https://patchwork.plctlab.org/api/1.2/patches/1648/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5abe1d8a7694417b990e11d8f6cd6789573872e5.1664793840.git.research_trasio@irq.a4lg.com/","msgid":"<5abe1d8a7694417b990e11d8f6cd6789573872e5.1664793840.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-03T10:44:03","name":"[v3,5/6] RISC-V: Fix T-Head immediate types on printing","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5abe1d8a7694417b990e11d8f6cd6789573872e5.1664793840.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1649,"url":"https://patchwork.plctlab.org/api/1.2/patches/1649/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0b68af932117258c908db62cf87c3a15d3cdec41.1664793840.git.research_trasio@irq.a4lg.com/","msgid":"<0b68af932117258c908db62cf87c3a15d3cdec41.1664793840.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-03T10:44:04","name":"[v3,6/6] RISC-V: Print XTheadMemPair literal as \"immediate\"","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0b68af932117258c908db62cf87c3a15d3cdec41.1664793840.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1656,"url":"https://patchwork.plctlab.org/api/1.2/patches/1656/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/87lepxcd6x.fsf@redhat.com/","msgid":"<87lepxcd6x.fsf@redhat.com>","list_archive_url":null,"date":"2022-10-03T12:19:02","name":"Commit: readelf: Do not load section data from offset 0","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/87lepxcd6x.fsf@redhat.com/mbox/"},{"id":1659,"url":"https://patchwork.plctlab.org/api/1.2/patches/1659/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e0d369d419da9c0441f415da7f54352aead8f655.1664707612.git.aburgess@redhat.com/","msgid":"","list_archive_url":null,"date":"2022-10-03T16:37:36","name":"[PATCHv2,1/2] opcodes/arm: use '\''@'\'' consistently for the comment character","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e0d369d419da9c0441f415da7f54352aead8f655.1664707612.git.aburgess@redhat.com/mbox/"},{"id":1660,"url":"https://patchwork.plctlab.org/api/1.2/patches/1660/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003165848.11142-1-palmer@rivosinc.com/","msgid":"<20221003165848.11142-1-palmer@rivosinc.com>","list_archive_url":null,"date":"2022-10-03T16:58:48","name":"gas: NEWS: Mention the T-Head extensions that were recently added","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003165848.11142-1-palmer@rivosinc.com/mbox/"},{"id":1671,"url":"https://patchwork.plctlab.org/api/1.2/patches/1671/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/YzvrMEdkXjIn5Lfz@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-04T08:13:36","name":"Support objcopy changing compression to or from zstd","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/YzvrMEdkXjIn5Lfz@squeak.grove.modra.org/mbox/"},{"id":1673,"url":"https://patchwork.plctlab.org/api/1.2/patches/1673/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0bc857d306bb7c8130e5328dbe6b9ed2fed3ef87.1664873933.git.research_trasio@irq.a4lg.com/","msgid":"<0bc857d306bb7c8130e5328dbe6b9ed2fed3ef87.1664873933.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-04T08:59:07","name":"[1/2] RISC-V: Fix buffer overflow on print_insn_riscv","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0bc857d306bb7c8130e5328dbe6b9ed2fed3ef87.1664873933.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1672,"url":"https://patchwork.plctlab.org/api/1.2/patches/1672/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/89612fe01d902007bf84a7dfb0df5f85d5c166e4.1664873933.git.research_trasio@irq.a4lg.com/","msgid":"<89612fe01d902007bf84a7dfb0df5f85d5c166e4.1664873933.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-04T08:59:08","name":"[2/2] gdb/riscv: Fix buffer overflow on riscv_insn::fetch_instruction","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/89612fe01d902007bf84a7dfb0df5f85d5c166e4.1664873933.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1676,"url":"https://patchwork.plctlab.org/api/1.2/patches/1676/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fc849c94f4adcac1c4ccc5508c7a145a2f13b2a9.1664876744.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-04T09:45:49","name":"[v2,1/2] RISC-V: Fix buffer overflow on print_insn_riscv","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fc849c94f4adcac1c4ccc5508c7a145a2f13b2a9.1664876744.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1677,"url":"https://patchwork.plctlab.org/api/1.2/patches/1677/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4eb6e59ae2e790dbbf2bc92477edd281648d8814.1664876744.git.research_trasio@irq.a4lg.com/","msgid":"<4eb6e59ae2e790dbbf2bc92477edd281648d8814.1664876744.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-04T09:45:50","name":"[v2,2/2] gdb/riscv: Partial support for instructions up to 176-bits","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4eb6e59ae2e790dbbf2bc92477edd281648d8814.1664876744.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1678,"url":"https://patchwork.plctlab.org/api/1.2/patches/1678/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ebf16f9e1f45115d0793952ccb4a94d4233303f9.1664882725.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-04T11:25:56","name":"[v3,1/2] RISC-V: Fix buffer overflow on print_insn_riscv","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ebf16f9e1f45115d0793952ccb4a94d4233303f9.1664882725.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1679,"url":"https://patchwork.plctlab.org/api/1.2/patches/1679/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/83464b09b8649525259c69c853dfa2c9575a204b.1664882725.git.research_trasio@irq.a4lg.com/","msgid":"<83464b09b8649525259c69c853dfa2c9575a204b.1664882725.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-04T11:25:57","name":"[v3,2/2] gdb/riscv: Partial support for instructions up to 176-bit","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/83464b09b8649525259c69c853dfa2c9575a204b.1664882725.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1681,"url":"https://patchwork.plctlab.org/api/1.2/patches/1681/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ffa9c1d7-e8c2-a62b-ef3e-b565c0ffbe5b@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-04T13:56:27","name":"RISC-V: Zicbo{m,p,z} adjustments to riscv_multi_subset_supports_ext()","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ffa9c1d7-e8c2-a62b-ef3e-b565c0ffbe5b@suse.com/mbox/"},{"id":1690,"url":"https://patchwork.plctlab.org/api/1.2/patches/1690/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221004161720.1963953-1-vladimir.mezentsev@oracle.com/","msgid":"<20221004161720.1963953-1-vladimir.mezentsev@oracle.com>","list_archive_url":null,"date":"2022-10-04T16:17:20","name":"gprofng: fix build with --enable-pgo-build=lto","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221004161720.1963953-1-vladimir.mezentsev@oracle.com/mbox/"},{"id":1691,"url":"https://patchwork.plctlab.org/api/1.2/patches/1691/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c0211bc9c57be6c79c6d878ce147f63b657f461d.camel@espressif.com/","msgid":"","list_archive_url":null,"date":"2022-10-04T16:22:05","name":"bfd: xtensa: fix __stop_SECTION literal drop,","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c0211bc9c57be6c79c6d878ce147f63b657f461d.camel@espressif.com/mbox/"},{"id":1702,"url":"https://patchwork.plctlab.org/api/1.2/patches/1702/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5f482299-6c60-b2b3-9abe-f4a55a5a26c5@univ-grenoble-alpes.fr/","msgid":"<5f482299-6c60-b2b3-9abe-f4a55a5a26c5@univ-grenoble-alpes.fr>","list_archive_url":null,"date":"2022-10-04T20:03:20","name":"[RFC] bfd: use bfd_vma for the 64-bit version of put[lb] and get[lb]","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5f482299-6c60-b2b3-9abe-f4a55a5a26c5@univ-grenoble-alpes.fr/mbox/"},{"id":1711,"url":"https://patchwork.plctlab.org/api/1.2/patches/1711/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Yz0Gsxdxe0TePbJT@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-05T04:23:15","name":"PR29647, objdump -S looping","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Yz0Gsxdxe0TePbJT@squeak.grove.modra.org/mbox/"},{"id":1712,"url":"https://patchwork.plctlab.org/api/1.2/patches/1712/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/02d747d2-f57b-0fb5-b893-842b6cc41f2f@suse.com/","msgid":"<02d747d2-f57b-0fb5-b893-842b6cc41f2f@suse.com>","list_archive_url":null,"date":"2022-10-05T07:20:47","name":"[v3,1/7] x86: constify parse_insn()'\''s input","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/02d747d2-f57b-0fb5-b893-842b6cc41f2f@suse.com/mbox/"},{"id":1713,"url":"https://patchwork.plctlab.org/api/1.2/patches/1713/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/925cb740-4e1b-abc4-8526-aaab6faae5e1@suse.com/","msgid":"<925cb740-4e1b-abc4-8526-aaab6faae5e1@suse.com>","list_archive_url":null,"date":"2022-10-05T07:22:19","name":"[v3,2/7] x86: introduce Pass2 insn attribute","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/925cb740-4e1b-abc4-8526-aaab6faae5e1@suse.com/mbox/"},{"id":1714,"url":"https://patchwork.plctlab.org/api/1.2/patches/1714/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e16d3e78-39ca-f715-508f-a4104b8ab9a9@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-05T07:23:51","name":"[v3,3/7] x86: re-work insn/suffix recognition","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e16d3e78-39ca-f715-508f-a4104b8ab9a9@suse.com/mbox/"},{"id":1715,"url":"https://patchwork.plctlab.org/api/1.2/patches/1715/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e4e4b80b-794c-7485-1997-685adab8fb27@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-05T07:24:20","name":"[v3,4/7] x86-64: further re-work insn/suffix recognition to also cover MOVSL","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e4e4b80b-794c-7485-1997-685adab8fb27@suse.com/mbox/"},{"id":1716,"url":"https://patchwork.plctlab.org/api/1.2/patches/1716/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/540678fc-8bff-ec68-c97c-478d2631998c@suse.com/","msgid":"<540678fc-8bff-ec68-c97c-478d2631998c@suse.com>","list_archive_url":null,"date":"2022-10-05T07:24:55","name":"[v3,5/7] ix86: don'\''t recognize/derive Q suffix in the common case","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/540678fc-8bff-ec68-c97c-478d2631998c@suse.com/mbox/"},{"id":1718,"url":"https://patchwork.plctlab.org/api/1.2/patches/1718/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e4692495-7d3d-074d-14f9-364d4a9a998c@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-05T07:25:25","name":"[v3,6/7] x86-64: allow HLE store of accumulator to absolute 32-bit address","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e4692495-7d3d-074d-14f9-364d4a9a998c@suse.com/mbox/"},{"id":1717,"url":"https://patchwork.plctlab.org/api/1.2/patches/1717/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e8014ebd-d16b-17a7-9f34-3700fc164136@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-05T07:25:57","name":"[v3,7/7] x86: move bad-use-of-TLS-reloc check","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e8014ebd-d16b-17a7-9f34-3700fc164136@suse.com/mbox/"},{"id":1719,"url":"https://patchwork.plctlab.org/api/1.2/patches/1719/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1266f001-4511-2662-dba9-14b4d0317c57@suse.com/","msgid":"<1266f001-4511-2662-dba9-14b4d0317c57@suse.com>","list_archive_url":null,"date":"2022-10-05T07:40:50","name":"x86: drop \"regmask\" static variable","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1266f001-4511-2662-dba9-14b4d0317c57@suse.com/mbox/"},{"id":1751,"url":"https://patchwork.plctlab.org/api/1.2/patches/1751/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/af45c5d57c221e43101c2aa38b14f4b4ac12d011.1665031170.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-06T04:40:15","name":"[v2,1/2] RISC-V: Fallback for instructions longer than 64b","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/af45c5d57c221e43101c2aa38b14f4b4ac12d011.1665031170.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1752,"url":"https://patchwork.plctlab.org/api/1.2/patches/1752/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c6e55781245dd3e8e9b8debd6130fc5449dfbd55.1665031170.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-06T04:40:16","name":"[v2,2/2] RISC-V: Improve \"bits undefined\" diagnostics","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c6e55781245dd3e8e9b8debd6130fc5449dfbd55.1665031170.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1776,"url":"https://patchwork.plctlab.org/api/1.2/patches/1776/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d52952119e15357c0e823f8a2398999359588b4d.1665050099.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-06T09:56:30","name":"[v3,1/2] RISC-V: Fallback for instructions longer than 64b","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d52952119e15357c0e823f8a2398999359588b4d.1665050099.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1777,"url":"https://patchwork.plctlab.org/api/1.2/patches/1777/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d907b1997f60ff7823c4a23e281ec9d8ddcbf3f1.1665050099.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-06T09:56:31","name":"[v3,2/2] RISC-V: Improve \"bits undefined\" diagnostics","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d907b1997f60ff7823c4a23e281ec9d8ddcbf3f1.1665050099.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1781,"url":"https://patchwork.plctlab.org/api/1.2/patches/1781/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221006114628.304185-1-chigot@adacore.com/","msgid":"<20221006114628.304185-1-chigot@adacore.com>","list_archive_url":null,"date":"2022-10-06T11:46:28","name":"RISC-V: fix linker message when relaxation deletes bytes","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221006114628.304185-1-chigot@adacore.com/mbox/"},{"id":1801,"url":"https://patchwork.plctlab.org/api/1.2/patches/1801/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Yz+Yhyg7UewC9/kp@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-07T03:09:59","name":"PR29653, objcopy/strip: fuzzed small input file induces large output file","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Yz+Yhyg7UewC9/kp@squeak.grove.modra.org/mbox/"},{"id":1803,"url":"https://patchwork.plctlab.org/api/1.2/patches/1803/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/PH1P110MB16505D9D39EC5B1DE22FE3D5EC5F9@PH1P110MB1650.NAMP110.PROD.OUTLOOK.COM/","msgid":"","list_archive_url":null,"date":"2022-10-07T04:10:07","name":"@CPP_FOR_BUILD@ problem since binutils-2.38","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/PH1P110MB16505D9D39EC5B1DE22FE3D5EC5F9@PH1P110MB1650.NAMP110.PROD.OUTLOOK.COM/mbox/"},{"id":1827,"url":"https://patchwork.plctlab.org/api/1.2/patches/1827/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8e13bce108ac10a0c1dd911e23ec572926f7ae44.1665203374.git.research_trasio@irq.a4lg.com/","msgid":"<8e13bce108ac10a0c1dd911e23ec572926f7ae44.1665203374.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-08T04:29:53","name":"[v2,1/1] RISC-V: Test DWARF register numbers for \"fp\"","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8e13bce108ac10a0c1dd911e23ec572926f7ae44.1665203374.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1828,"url":"https://patchwork.plctlab.org/api/1.2/patches/1828/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0883001b3572e54d3fba264429c7ade2adb66610.1665203441.git.research_trasio@irq.a4lg.com/","msgid":"<0883001b3572e54d3fba264429c7ade2adb66610.1665203441.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-08T04:31:15","name":"[1/1] RISC-V: Move standard hints before all instructions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0883001b3572e54d3fba264429c7ade2adb66610.1665203441.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1829,"url":"https://patchwork.plctlab.org/api/1.2/patches/1829/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/58e16a241d7376fcae2515c6bd5a2b41d275eeba.1665203531.git.research_trasio@irq.a4lg.com/","msgid":"<58e16a241d7376fcae2515c6bd5a2b41d275eeba.1665203531.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-08T04:32:18","name":"[RFC,1/1] RISC-V: Imply '\''Zicsr'\'' from privileged extensions with CSRs","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/58e16a241d7376fcae2515c6bd5a2b41d275eeba.1665203531.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1830,"url":"https://patchwork.plctlab.org/api/1.2/patches/1830/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/cb5076fc96e8f2097779a3abcde843dcdd660031.1665203660.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-08T04:34:23","name":"[1/5] opcodes/riscv-dis.c: Tidying with comments/clarity","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/cb5076fc96e8f2097779a3abcde843dcdd660031.1665203660.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1832,"url":"https://patchwork.plctlab.org/api/1.2/patches/1832/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1f1aa0838bf9c4f10a45fcfe3c682f7efc79d9ae.1665203660.git.research_trasio@irq.a4lg.com/","msgid":"<1f1aa0838bf9c4f10a45fcfe3c682f7efc79d9ae.1665203660.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-08T04:34:24","name":"[2/5] opcodes/riscv-dis.c: Tidying with spacing","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1f1aa0838bf9c4f10a45fcfe3c682f7efc79d9ae.1665203660.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1831,"url":"https://patchwork.plctlab.org/api/1.2/patches/1831/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/740bc5e2d2618d236519b39fedd1a1d7ae4e05da.1665203660.git.research_trasio@irq.a4lg.com/","msgid":"<740bc5e2d2618d236519b39fedd1a1d7ae4e05da.1665203660.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-08T04:34:25","name":"[3/5] opcodes/riscv-dis.c: Use bool type whenever possible","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/740bc5e2d2618d236519b39fedd1a1d7ae4e05da.1665203660.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1833,"url":"https://patchwork.plctlab.org/api/1.2/patches/1833/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6e3a9c235e317f441b4383b3daa68f2051bdc149.1665203660.git.research_trasio@irq.a4lg.com/","msgid":"<6e3a9c235e317f441b4383b3daa68f2051bdc149.1665203660.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-08T04:34:26","name":"[4/5] opcodes/riscv-dis.c: Make XLEN variable static","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6e3a9c235e317f441b4383b3daa68f2051bdc149.1665203660.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1834,"url":"https://patchwork.plctlab.org/api/1.2/patches/1834/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ad929233a62d887495122721340b2f9c80392963.1665203660.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-08T04:34:27","name":"[5/5] opcodes/riscv-dis.c: Remove last_map_state","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ad929233a62d887495122721340b2f9c80392963.1665203660.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1836,"url":"https://patchwork.plctlab.org/api/1.2/patches/1836/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d07e2b6f36ea2fd5830924a9bfeda941b774b687.1665290422.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-09T05:09:22","name":"RISC-V: Move certain arrays to riscv-opc.c","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d07e2b6f36ea2fd5830924a9bfeda941b774b687.1665290422.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1844,"url":"https://patchwork.plctlab.org/api/1.2/patches/1844/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010004623.16582-1-mark@harmstone.com/","msgid":"<20221010004623.16582-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-10T00:46:22","name":"[v2,1/2] ld: Add --pdb option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010004623.16582-1-mark@harmstone.com/mbox/"},{"id":1845,"url":"https://patchwork.plctlab.org/api/1.2/patches/1845/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010004623.16582-2-mark@harmstone.com/","msgid":"<20221010004623.16582-2-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-10T00:46:23","name":"[v2,2/2] ld: Add minimal pdb generation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010004623.16582-2-mark@harmstone.com/mbox/"},{"id":1890,"url":"https://patchwork.plctlab.org/api/1.2/patches/1890/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010200433.414320-1-vladimir.mezentsev@oracle.com/","msgid":"<20221010200433.414320-1-vladimir.mezentsev@oracle.com>","list_archive_url":null,"date":"2022-10-10T20:04:33","name":"gprofng: run tests without installation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010200433.414320-1-vladimir.mezentsev@oracle.com/mbox/"},{"id":1893,"url":"https://patchwork.plctlab.org/api/1.2/patches/1893/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010230426.719238-1-vladimir.mezentsev@oracle.com/","msgid":"<20221010230426.719238-1-vladimir.mezentsev@oracle.com>","list_archive_url":null,"date":"2022-10-10T23:04:26","name":"[2/2] gprofng: use the --libdir path to find libraries","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010230426.719238-1-vladimir.mezentsev@oracle.com/mbox/"},{"id":1894,"url":"https://patchwork.plctlab.org/api/1.2/patches/1894/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010235155.842469-1-vladimir.mezentsev@oracle.com/","msgid":"<20221010235155.842469-1-vladimir.mezentsev@oracle.com>","list_archive_url":null,"date":"2022-10-10T23:51:55","name":"[3/3] gprofng: no need to build version.texi","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010235155.842469-1-vladimir.mezentsev@oracle.com/mbox/"},{"id":1895,"url":"https://patchwork.plctlab.org/api/1.2/patches/1895/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011003702.4287-1-mark@harmstone.com/","msgid":"<20221011003702.4287-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-11T00:37:01","name":"[v3,1/2] ld: Add --pdb option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011003702.4287-1-mark@harmstone.com/mbox/"},{"id":1897,"url":"https://patchwork.plctlab.org/api/1.2/patches/1897/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011003702.4287-2-mark@harmstone.com/","msgid":"<20221011003702.4287-2-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-11T00:37:02","name":"[v3,2/2] ld: Add minimal pdb generation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011003702.4287-2-mark@harmstone.com/mbox/"},{"id":1928,"url":"https://patchwork.plctlab.org/api/1.2/patches/1928/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011175332.17156-1-mark@harmstone.com/","msgid":"<20221011175332.17156-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-11T17:53:31","name":"[v4,1/2] ld: Add --pdb option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011175332.17156-1-mark@harmstone.com/mbox/"},{"id":1929,"url":"https://patchwork.plctlab.org/api/1.2/patches/1929/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011175332.17156-2-mark@harmstone.com/","msgid":"<20221011175332.17156-2-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-11T17:53:32","name":"[v4,2/2] ld: Add minimal pdb generation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011175332.17156-2-mark@harmstone.com/mbox/"},{"id":1941,"url":"https://patchwork.plctlab.org/api/1.2/patches/1941/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221012031005.237446-1-simon.marchi@polymtl.ca/","msgid":"<20221012031005.237446-1-simon.marchi@polymtl.ca>","list_archive_url":null,"date":"2022-10-12T03:10:05","name":"[pushed] Re-apply \"Pass PKG_CONFIG_PATH down from top-level Makefile\"","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221012031005.237446-1-simon.marchi@polymtl.ca/mbox/"},{"id":1976,"url":"https://patchwork.plctlab.org/api/1.2/patches/1976/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1216a3f8-2273-8681-f528-9493a66891f0@suse.com/","msgid":"<1216a3f8-2273-8681-f528-9493a66891f0@suse.com>","list_archive_url":null,"date":"2022-10-13T08:16:49","name":"[v4,1/8] x86: constify parse_insn()'\''s input","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1216a3f8-2273-8681-f528-9493a66891f0@suse.com/mbox/"},{"id":1977,"url":"https://patchwork.plctlab.org/api/1.2/patches/1977/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/11599bbe-c779-aa9f-4d5d-c2243f0e69dc@suse.com/","msgid":"<11599bbe-c779-aa9f-4d5d-c2243f0e69dc@suse.com>","list_archive_url":null,"date":"2022-10-13T08:17:17","name":"[v4,2/8] x86: introduce Pass2 insn attribute","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/11599bbe-c779-aa9f-4d5d-c2243f0e69dc@suse.com/mbox/"},{"id":1978,"url":"https://patchwork.plctlab.org/api/1.2/patches/1978/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/357273a3-060c-23db-72da-3fc9d1be3d2a@suse.com/","msgid":"<357273a3-060c-23db-72da-3fc9d1be3d2a@suse.com>","list_archive_url":null,"date":"2022-10-13T08:18:09","name":"[v4,3/8] x86: re-work insn/suffix recognition","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/357273a3-060c-23db-72da-3fc9d1be3d2a@suse.com/mbox/"},{"id":1979,"url":"https://patchwork.plctlab.org/api/1.2/patches/1979/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0ec0587f-6a7b-45b6-8346-e5d774e73636@suse.com/","msgid":"<0ec0587f-6a7b-45b6-8346-e5d774e73636@suse.com>","list_archive_url":null,"date":"2022-10-13T08:18:39","name":"[v4,4/8] x86-64: further re-work insn/suffix recognition to also cover MOVSL","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0ec0587f-6a7b-45b6-8346-e5d774e73636@suse.com/mbox/"},{"id":1980,"url":"https://patchwork.plctlab.org/api/1.2/patches/1980/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fb617d0b-8759-3169-5a65-1178b7fef3d7@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-13T08:19:34","name":"[v4,5/8] ix86: don'\''t recognize/derive Q suffix in the common case","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fb617d0b-8759-3169-5a65-1178b7fef3d7@suse.com/mbox/"},{"id":1981,"url":"https://patchwork.plctlab.org/api/1.2/patches/1981/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1df3bd01-99c5-f56c-d937-970edd42b2b8@suse.com/","msgid":"<1df3bd01-99c5-f56c-d937-970edd42b2b8@suse.com>","list_archive_url":null,"date":"2022-10-13T08:20:14","name":"[v4,6/8] x86-64: allow HLE store of accumulator to absolute 32-bit address","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1df3bd01-99c5-f56c-d937-970edd42b2b8@suse.com/mbox/"},{"id":1982,"url":"https://patchwork.plctlab.org/api/1.2/patches/1982/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8486a218-39ec-16b2-5c6c-5037196b93cf@suse.com/","msgid":"<8486a218-39ec-16b2-5c6c-5037196b93cf@suse.com>","list_archive_url":null,"date":"2022-10-13T08:21:00","name":"[v4,7/8] x86: move bad-use-of-TLS-reloc check","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8486a218-39ec-16b2-5c6c-5037196b93cf@suse.com/mbox/"},{"id":1983,"url":"https://patchwork.plctlab.org/api/1.2/patches/1983/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7d82692d-93df-fbee-9efb-2f44e8a91df3@suse.com/","msgid":"<7d82692d-93df-fbee-9efb-2f44e8a91df3@suse.com>","list_archive_url":null,"date":"2022-10-13T08:22:00","name":"[v4,8/8] x86: drop (now) stray IsString","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7d82692d-93df-fbee-9efb-2f44e8a91df3@suse.com/mbox/"},{"id":2013,"url":"https://patchwork.plctlab.org/api/1.2/patches/2013/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8ab93d7a617ad480dd786210f46db0e5aa07d1ac.1665655719.git.research_trasio@irq.a4lg.com/","msgid":"<8ab93d7a617ad480dd786210f46db0e5aa07d1ac.1665655719.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-13T10:11:41","name":"include: Declare getopt function on old GNU libc","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8ab93d7a617ad480dd786210f46db0e5aa07d1ac.1665655719.git.research_trasio@irq.a4lg.com/mbox/"},{"id":2352,"url":"https://patchwork.plctlab.org/api/1.2/patches/2352/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221013201332.2747246-1-maskray@google.com/","msgid":"<20221013201332.2747246-1-maskray@google.com>","list_archive_url":null,"date":"2022-10-13T20:13:32","name":"ld: Add --undefined-version","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221013201332.2747246-1-maskray@google.com/mbox/"},{"id":2532,"url":"https://patchwork.plctlab.org/api/1.2/patches/2532/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014063520.1428330-2-zengxiao@eswincomputing.com/","msgid":"<20221014063520.1428330-2-zengxiao@eswincomputing.com>","list_archive_url":null,"date":"2022-10-14T06:35:20","name":"[1/1] RISC-V: Make R_RISCV_SUB6 conforms to riscv abi standard","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014063520.1428330-2-zengxiao@eswincomputing.com/mbox/"},{"id":2560,"url":"https://patchwork.plctlab.org/api/1.2/patches/2560/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/027ae69a-636b-6757-297a-eec42936401e@linaro.org/","msgid":"<027ae69a-636b-6757-297a-eec42936401e@linaro.org>","list_archive_url":null,"date":"2022-10-14T07:58:22","name":"[v3] aarch64-pe support for LD, GAS and BFD","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/027ae69a-636b-6757-297a-eec42936401e@linaro.org/mbox/"},{"id":2602,"url":"https://patchwork.plctlab.org/api/1.2/patches/2602/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-2-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-2-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:39","name":"[01/10] Support Intel AVX-IFMA","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-2-haochen.jiang@intel.com/mbox/"},{"id":2608,"url":"https://patchwork.plctlab.org/api/1.2/patches/2608/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-3-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-3-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:40","name":"[02/10] Support Intel AVX-VNNI-INT8","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-3-haochen.jiang@intel.com/mbox/"},{"id":2611,"url":"https://patchwork.plctlab.org/api/1.2/patches/2611/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-4-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-4-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:41","name":"[03/10] Support Intel AVX-NE-CONVERT","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-4-haochen.jiang@intel.com/mbox/"},{"id":2610,"url":"https://patchwork.plctlab.org/api/1.2/patches/2610/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-5-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-5-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:42","name":"[04/10] Support Intel CMPccXADD","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-5-haochen.jiang@intel.com/mbox/"},{"id":2601,"url":"https://patchwork.plctlab.org/api/1.2/patches/2601/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-6-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-6-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:43","name":"[05/10] Add handler for more i386_cpu_flags","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-6-haochen.jiang@intel.com/mbox/"},{"id":2606,"url":"https://patchwork.plctlab.org/api/1.2/patches/2606/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-7-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-7-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:44","name":"[06/10] Support Intel RAO-INT","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-7-haochen.jiang@intel.com/mbox/"},{"id":2609,"url":"https://patchwork.plctlab.org/api/1.2/patches/2609/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-8-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-8-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:45","name":"[07/10] Support Intel WRMSRNS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-8-haochen.jiang@intel.com/mbox/"},{"id":2605,"url":"https://patchwork.plctlab.org/api/1.2/patches/2605/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-9-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-9-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:46","name":"[08/10] Support Intel MSRLIST","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-9-haochen.jiang@intel.com/mbox/"},{"id":2607,"url":"https://patchwork.plctlab.org/api/1.2/patches/2607/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-10-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-10-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:47","name":"[09/10] Support Intel AMX-FP16","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-10-haochen.jiang@intel.com/mbox/"},{"id":2604,"url":"https://patchwork.plctlab.org/api/1.2/patches/2604/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-11-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-11-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:48","name":"[10/10] Support Intel PREFETCHI","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-11-haochen.jiang@intel.com/mbox/"},{"id":2643,"url":"https://patchwork.plctlab.org/api/1.2/patches/2643/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7bac66be-535e-9051-d674-f2f5ba180e17@suse.com/","msgid":"<7bac66be-535e-9051-d674-f2f5ba180e17@suse.com>","list_archive_url":null,"date":"2022-10-14T10:22:34","name":"x86: fold AVX512-VNNI disassembler entries with AVX-VNNI ones","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7bac66be-535e-9051-d674-f2f5ba180e17@suse.com/mbox/"},{"id":2654,"url":"https://patchwork.plctlab.org/api/1.2/patches/2654/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0lIo5+ncY/MqBEq@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-14T11:31:47","name":"PR29677, Field `the_bfd` of `asymbol` is uninitialised","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0lIo5+ncY/MqBEq@squeak.grove.modra.org/mbox/"},{"id":2656,"url":"https://patchwork.plctlab.org/api/1.2/patches/2656/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0lJksn49ZpABY89@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-14T11:35:46","name":"e200 LSP support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0lJksn49ZpABY89@squeak.grove.modra.org/mbox/"},{"id":2657,"url":"https://patchwork.plctlab.org/api/1.2/patches/2657/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0lJxxYoeD5iDYAD@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-14T11:36:39","name":"PowerPC SPE disassembly and tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0lJxxYoeD5iDYAD@squeak.grove.modra.org/mbox/"},{"id":2695,"url":"https://patchwork.plctlab.org/api/1.2/patches/2695/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/DM6PR12MB4219611F6CC2A0702884A602E7249@DM6PR12MB4219.namprd12.prod.outlook.com/","msgid":"","list_archive_url":null,"date":"2022-10-14T13:29:40","name":"Binutils: Adding new testcase for addr2line.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/DM6PR12MB4219611F6CC2A0702884A602E7249@DM6PR12MB4219.namprd12.prod.outlook.com/mbox/"},{"id":2700,"url":"https://patchwork.plctlab.org/api/1.2/patches/2700/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9fd2c88d-98b2-99a4-419f-c7235b2cf960@suse.com/","msgid":"<9fd2c88d-98b2-99a4-419f-c7235b2cf960@suse.com>","list_archive_url":null,"date":"2022-10-14T14:11:35","name":"x86: properly decode EVEX.W for AVX512_4{FMAPS,VNNIW} insns","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9fd2c88d-98b2-99a4-419f-c7235b2cf960@suse.com/mbox/"},{"id":2981,"url":"https://patchwork.plctlab.org/api/1.2/patches/2981/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0uLzalqjm4C87GN@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-16T04:42:53","name":"PowerPC se_rfmci and VLE, SPE2 and LSP insns with -many","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0uLzalqjm4C87GN@squeak.grove.modra.org/mbox/"},{"id":3152,"url":"https://patchwork.plctlab.org/api/1.2/patches/3152/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221016232419.1135-1-mark@harmstone.com/","msgid":"<20221016232419.1135-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-16T23:24:18","name":"[v5,1/2] ld: Add --pdb option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221016232419.1135-1-mark@harmstone.com/mbox/"},{"id":3151,"url":"https://patchwork.plctlab.org/api/1.2/patches/3151/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221016232419.1135-2-mark@harmstone.com/","msgid":"<20221016232419.1135-2-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-16T23:24:19","name":"[v5,2/2] ld: Add minimal pdb generation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221016232419.1135-2-mark@harmstone.com/mbox/"},{"id":3258,"url":"https://patchwork.plctlab.org/api/1.2/patches/3258/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/19c08747-fa5b-1e67-3dd2-c891a2c0c1fa@suse.com/","msgid":"<19c08747-fa5b-1e67-3dd2-c891a2c0c1fa@suse.com>","list_archive_url":null,"date":"2022-10-17T07:44:51","name":"x86: correct CPU_AMX_{BF16,INT8}_FLAGS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/19c08747-fa5b-1e67-3dd2-c891a2c0c1fa@suse.com/mbox/"},{"id":3272,"url":"https://patchwork.plctlab.org/api/1.2/patches/3272/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/85dd526c-d3a7-72dc-5444-ed5573eebec1@suse.com/","msgid":"<85dd526c-d3a7-72dc-5444-ed5573eebec1@suse.com>","list_archive_url":null,"date":"2022-10-17T08:30:12","name":"x86: generalize gas documentation for disabling of ISA extensions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/85dd526c-d3a7-72dc-5444-ed5573eebec1@suse.com/mbox/"},{"id":3759,"url":"https://patchwork.plctlab.org/api/1.2/patches/3759/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-2-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-2-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:15:58","name":"[V2,01/15] sframe.h: Add SFrame format definition","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-2-indu.bhagat@oracle.com/mbox/"},{"id":3762,"url":"https://patchwork.plctlab.org/api/1.2/patches/3762/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-3-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-3-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:15:59","name":"[V2,02/15] gas: add new command line option --gsframe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-3-indu.bhagat@oracle.com/mbox/"},{"id":3761,"url":"https://patchwork.plctlab.org/api/1.2/patches/3761/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-4-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-4-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:00","name":"[V2,03/15] gas: generate .sframe from CFI directives","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-4-indu.bhagat@oracle.com/mbox/"},{"id":3760,"url":"https://patchwork.plctlab.org/api/1.2/patches/3760/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-5-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-5-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:01","name":"[V2,04/15] gas: testsuite: add new tests for SFrame unwind info","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-5-indu.bhagat@oracle.com/mbox/"},{"id":3764,"url":"https://patchwork.plctlab.org/api/1.2/patches/3764/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-6-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-6-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:02","name":"[V2,05/15] libsframe: add the SFrame library","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-6-indu.bhagat@oracle.com/mbox/"},{"id":3766,"url":"https://patchwork.plctlab.org/api/1.2/patches/3766/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-7-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-7-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:03","name":"[V2,06/15] bfd: linker: merge .sframe sections","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-7-indu.bhagat@oracle.com/mbox/"},{"id":3763,"url":"https://patchwork.plctlab.org/api/1.2/patches/3763/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-8-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-8-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:04","name":"[V2,07/15] readelf/objdump: support for SFrame section","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-8-indu.bhagat@oracle.com/mbox/"},{"id":3765,"url":"https://patchwork.plctlab.org/api/1.2/patches/3765/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-9-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-9-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:05","name":"[V2,08/15] unwinder: generate backtrace using SFrame format","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-9-indu.bhagat@oracle.com/mbox/"},{"id":3770,"url":"https://patchwork.plctlab.org/api/1.2/patches/3770/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-10-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-10-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:06","name":"[V2,09/15] unwinder: Add SFrame unwinder tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-10-indu.bhagat@oracle.com/mbox/"},{"id":3769,"url":"https://patchwork.plctlab.org/api/1.2/patches/3769/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-11-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-11-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:07","name":"[V2,10/15] gdb: sim: buildsystem changes to accommodate libsframe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-11-indu.bhagat@oracle.com/mbox/"},{"id":3771,"url":"https://patchwork.plctlab.org/api/1.2/patches/3771/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-12-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-12-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:08","name":"[V2,11/15] libctf: add libsframe to LDFLAGS and LIBS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-12-indu.bhagat@oracle.com/mbox/"},{"id":3768,"url":"https://patchwork.plctlab.org/api/1.2/patches/3768/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-13-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-13-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:09","name":"[V2,12/15] src-release.sh: Add libsframe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-13-indu.bhagat@oracle.com/mbox/"},{"id":3767,"url":"https://patchwork.plctlab.org/api/1.2/patches/3767/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-14-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-14-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:10","name":"[V2,13/15] binutils/NEWS: add text for SFrame support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-14-indu.bhagat@oracle.com/mbox/"},{"id":3772,"url":"https://patchwork.plctlab.org/api/1.2/patches/3772/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-15-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-15-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:11","name":"[V2,14/15] gas/NEWS: add text about new command line option and SFrame support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-15-indu.bhagat@oracle.com/mbox/"},{"id":3773,"url":"https://patchwork.plctlab.org/api/1.2/patches/3773/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-16-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-16-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:12","name":"[V2,15/15] doc: add SFrame spec file","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-16-indu.bhagat@oracle.com/mbox/"},{"id":3999,"url":"https://patchwork.plctlab.org/api/1.2/patches/3999/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221018081205.17880-1-krebbel@linux.ibm.com/","msgid":"<20221018081205.17880-1-krebbel@linux.ibm.com>","list_archive_url":null,"date":"2022-10-18T08:12:05","name":"[1/1] IBM zSystems: Issue error for *DBL relocs on misaligned symbols","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221018081205.17880-1-krebbel@linux.ibm.com/mbox/"},{"id":4141,"url":"https://patchwork.plctlab.org/api/1.2/patches/4141/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/baffaf673f17692b7bcbd604b31800b189988596.camel@espressif.com/","msgid":"","list_archive_url":null,"date":"2022-10-18T12:12:07","name":"xtensa: use definitions from xtensa-config.h","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/baffaf673f17692b7bcbd604b31800b189988596.camel@espressif.com/mbox/"},{"id":4272,"url":"https://patchwork.plctlab.org/api/1.2/patches/4272/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221018174914.470062-1-hjl.tools@gmail.com/","msgid":"<20221018174914.470062-1-hjl.tools@gmail.com>","list_archive_url":null,"date":"2022-10-18T17:49:14","name":"x86: Disable AVX-VNNI when disabling AVX2","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221018174914.470062-1-hjl.tools@gmail.com/mbox/"},{"id":4998,"url":"https://patchwork.plctlab.org/api/1.2/patches/4998/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c2f76e95-09f6-1d92-7ef4-38a3c2955fcd@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-19T09:52:46","name":"x86: re-work AVX-VNNI support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c2f76e95-09f6-1d92-7ef4-38a3c2955fcd@suse.com/mbox/"},{"id":5276,"url":"https://patchwork.plctlab.org/api/1.2/patches/5276/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0/lLtlKqqsmAx0s@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-19T11:53:18","name":"Fix addr2line test for ppc64 elfv1 and mingw","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0/lLtlKqqsmAx0s@squeak.grove.modra.org/mbox/"},{"id":5424,"url":"https://patchwork.plctlab.org/api/1.2/patches/5424/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/07bfebbf3843b47e13d82d4fa16eb14fec942ef7.1666184962.git.research_trasio@irq.a4lg.com/","msgid":"<07bfebbf3843b47e13d82d4fa16eb14fec942ef7.1666184962.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:09:54","name":"binutils: Remove unused substitution PROGRAM","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/07bfebbf3843b47e13d82d4fa16eb14fec942ef7.1666184962.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5433,"url":"https://patchwork.plctlab.org/api/1.2/patches/5433/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2fa7ff719223232402e82a9c91331aea22ace1bb.1666185116.git.research_trasio@irq.a4lg.com/","msgid":"<2fa7ff719223232402e82a9c91331aea22ace1bb.1666185116.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:11:55","name":"[v2,1/8] RISC-V: Add a space at the end of pinfo","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2fa7ff719223232402e82a9c91331aea22ace1bb.1666185116.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5435,"url":"https://patchwork.plctlab.org/api/1.2/patches/5435/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1b30cce5db2cce3b8edca42ab5da114d0b8c9e93.1666185116.git.research_trasio@irq.a4lg.com/","msgid":"<1b30cce5db2cce3b8edca42ab5da114d0b8c9e93.1666185116.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:11:56","name":"[v2,2/8] RISC-V: Fix obvious misalignments ('\''Zbb'\''/'\''Zba'\'')","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1b30cce5db2cce3b8edca42ab5da114d0b8c9e93.1666185116.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5437,"url":"https://patchwork.plctlab.org/api/1.2/patches/5437/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6b0857aa1a2d15ca1cf00b4dcaae0032efbb88ff.1666185116.git.research_trasio@irq.a4lg.com/","msgid":"<6b0857aa1a2d15ca1cf00b4dcaae0032efbb88ff.1666185116.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:11:57","name":"[v2,3/8] RISC-V: Remove spaces in opcode entries","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6b0857aa1a2d15ca1cf00b4dcaae0032efbb88ff.1666185116.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5436,"url":"https://patchwork.plctlab.org/api/1.2/patches/5436/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/889d956caac0f2e95543a14afaeed97188ce384c.1666185116.git.research_trasio@irq.a4lg.com/","msgid":"<889d956caac0f2e95543a14afaeed97188ce384c.1666185116.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:11:58","name":"[v2,4/8] RISC-V: Remove unused instruction macros","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/889d956caac0f2e95543a14afaeed97188ce384c.1666185116.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5440,"url":"https://patchwork.plctlab.org/api/1.2/patches/5440/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8f226ee20d8a5ef6ad7b6c4408b44794a99d542a.1666185116.git.research_trasio@irq.a4lg.com/","msgid":"<8f226ee20d8a5ef6ad7b6c4408b44794a99d542a.1666185116.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:11:59","name":"[v2,5/8] RISC-V: Complete tidying up with SCALL and SBREAK","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8f226ee20d8a5ef6ad7b6c4408b44794a99d542a.1666185116.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5442,"url":"https://patchwork.plctlab.org/api/1.2/patches/5442/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4070184c454a05a39adf0790951e5856e6b2ecb6.1666185116.git.research_trasio@irq.a4lg.com/","msgid":"<4070184c454a05a39adf0790951e5856e6b2ecb6.1666185116.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:12:00","name":"[v2,6/8] RISC-V: Tidying up with fmv.w.x and fmv.x.w","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4070184c454a05a39adf0790951e5856e6b2ecb6.1666185116.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5438,"url":"https://patchwork.plctlab.org/api/1.2/patches/5438/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c1ccda3e7c8fb297eda46dab3936d5c5977178fc.1666185116.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-19T13:12:01","name":"[v2,7/8] RISC-V: Make alias instructions aliases","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c1ccda3e7c8fb297eda46dab3936d5c5977178fc.1666185116.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5441,"url":"https://patchwork.plctlab.org/api/1.2/patches/5441/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/413cfca82c7e8d8a2e977dfda9135903c9cb7c57.1666185116.git.research_trasio@irq.a4lg.com/","msgid":"<413cfca82c7e8d8a2e977dfda9135903c9cb7c57.1666185116.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:12:02","name":"[v2,8/8] RISC-V: Use defined mask and match values","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/413cfca82c7e8d8a2e977dfda9135903c9cb7c57.1666185116.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5439,"url":"https://patchwork.plctlab.org/api/1.2/patches/5439/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/345c5c3b3a53eab04a1e6e91197de2642095c94f.1666185237.git.research_trasio@irq.a4lg.com/","msgid":"<345c5c3b3a53eab04a1e6e91197de2642095c94f.1666185237.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:14:01","name":"RISC-V: Remove RV32EF conflict","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/345c5c3b3a53eab04a1e6e91197de2642095c94f.1666185237.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5616,"url":"https://patchwork.plctlab.org/api/1.2/patches/5616/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019145608.45213-5-haochen.jiang@intel.com/","msgid":"<20221019145608.45213-5-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T14:56:02","name":"[04/10] Support Intel CMPccXADD","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019145608.45213-5-haochen.jiang@intel.com/mbox/"},{"id":5614,"url":"https://patchwork.plctlab.org/api/1.2/patches/5614/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019145608.45213-6-haochen.jiang@intel.com/","msgid":"<20221019145608.45213-6-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T14:56:03","name":"[05/10] Add handler for more i386_cpu_flags","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019145608.45213-6-haochen.jiang@intel.com/mbox/"},{"id":5672,"url":"https://patchwork.plctlab.org/api/1.2/patches/5672/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-2-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-2-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:25","name":"[01/10] Support Intel AVX-IFMA","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-2-haochen.jiang@intel.com/mbox/"},{"id":5691,"url":"https://patchwork.plctlab.org/api/1.2/patches/5691/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-3-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-3-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:26","name":"[02/10] Support Intel AVX-VNNI-INT8","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-3-haochen.jiang@intel.com/mbox/"},{"id":5690,"url":"https://patchwork.plctlab.org/api/1.2/patches/5690/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-4-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-4-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:27","name":"[03/10] Support Intel AVX-NE-CONVERT","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-4-haochen.jiang@intel.com/mbox/"},{"id":5689,"url":"https://patchwork.plctlab.org/api/1.2/patches/5689/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-5-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-5-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:28","name":"[04/10] Support Intel CMPccXADD","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-5-haochen.jiang@intel.com/mbox/"},{"id":5676,"url":"https://patchwork.plctlab.org/api/1.2/patches/5676/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-6-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-6-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:29","name":"[05/10] Add handler for more i386_cpu_flags","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-6-haochen.jiang@intel.com/mbox/"},{"id":5677,"url":"https://patchwork.plctlab.org/api/1.2/patches/5677/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-7-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-7-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:30","name":"[06/10] Support Intel RAO-INT","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-7-haochen.jiang@intel.com/mbox/"},{"id":5681,"url":"https://patchwork.plctlab.org/api/1.2/patches/5681/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-8-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-8-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:31","name":"[07/10] Support Intel WRMSRNS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-8-haochen.jiang@intel.com/mbox/"},{"id":5682,"url":"https://patchwork.plctlab.org/api/1.2/patches/5682/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-9-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-9-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:32","name":"[08/10] Support Intel MSRLIST","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-9-haochen.jiang@intel.com/mbox/"},{"id":5673,"url":"https://patchwork.plctlab.org/api/1.2/patches/5673/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-10-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-10-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:33","name":"[09/10] Support Intel AMX-FP16","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-10-haochen.jiang@intel.com/mbox/"},{"id":5686,"url":"https://patchwork.plctlab.org/api/1.2/patches/5686/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-11-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-11-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:34","name":"[10/10] Support Intel PREFETCHI","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-11-haochen.jiang@intel.com/mbox/"},{"id":11921,"url":"https://patchwork.plctlab.org/api/1.2/patches/11921/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027190052.10536-1-mark@harmstone.com/","msgid":"<20221027190052.10536-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-27T19:00:51","name":"[1/2] ld: Add section header stream to PDB files","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027190052.10536-1-mark@harmstone.com/mbox/"},{"id":11922,"url":"https://patchwork.plctlab.org/api/1.2/patches/11922/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027190052.10536-2-mark@harmstone.com/","msgid":"<20221027190052.10536-2-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-27T19:00:52","name":"[2/2] ld: Add publics stream to PDB files","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027190052.10536-2-mark@harmstone.com/mbox/"},{"id":11965,"url":"https://patchwork.plctlab.org/api/1.2/patches/11965/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027202719.32497-1-palmer@rivosinc.com/","msgid":"<20221027202719.32497-1-palmer@rivosinc.com>","list_archive_url":null,"date":"2022-10-27T20:27:18","name":"[1/2] gas: NEWS: Add a missing newline","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027202719.32497-1-palmer@rivosinc.com/mbox/"},{"id":11966,"url":"https://patchwork.plctlab.org/api/1.2/patches/11966/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027202719.32497-2-palmer@rivosinc.com/","msgid":"<20221027202719.32497-2-palmer@rivosinc.com>","list_archive_url":null,"date":"2022-10-27T20:27:19","name":"[2/2] gas: NEWS: Note support for RISC-V Zawrs","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027202719.32497-2-palmer@rivosinc.com/mbox/"},{"id":12016,"url":"https://patchwork.plctlab.org/api/1.2/patches/12016/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/21ec9a18-fa89-0828-f625-499680022ec7@linux.ibm.com/","msgid":"<21ec9a18-fa89-0828-f625-499680022ec7@linux.ibm.com>","list_archive_url":null,"date":"2022-10-28T00:35:19","name":"[COMMITTED] PowerPC: Add support for RFC02653 - Dense Math Facility","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/21ec9a18-fa89-0828-f625-499680022ec7@linux.ibm.com/mbox/"}],"public":true,"mbox":"https://patchwork.plctlab.org/bundle/patchwork-bot/binutils-gdb_2022-10/mbox/"},{"id":7,"url":"https://patchwork.plctlab.org/api/1.2/bundles/7/","web_url":"https://patchwork.plctlab.org/bundle/patchwork-bot/binutils-gdb_2022-09/","project":{"id":2,"url":"https://patchwork.plctlab.org/api/1.2/projects/2/","name":"binutils-gdb","link_name":"binutils-gdb","list_id":"binutils.sourceware.org","list_email":"binutils@sourceware.org","web_url":"https://sourceware.org/mailman/listinfo/binutils","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"name":"binutils-gdb_2022-09","owner":{"id":3,"url":"https://patchwork.plctlab.org/api/1.2/users/3/","username":"patchwork-bot","first_name":"","last_name":"","email":"ouuuleilei@gmail.com"},"patches":[{"id":1573,"url":"https://patchwork.plctlab.org/api/1.2/patches/1573/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930073211.2634-1-jiawei@iscas.ac.cn/","msgid":"<20220930073211.2634-1-jiawei@iscas.ac.cn>","list_archive_url":null,"date":"2022-09-30T07:32:11","name":"[V2] RISC-V: Add Smepmp CSR '\''mseccfg'\'' define and testcases.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930073211.2634-1-jiawei@iscas.ac.cn/mbox/"},{"id":1577,"url":"https://patchwork.plctlab.org/api/1.2/patches/1577/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/76fa0c3c-2303-ebdf-a765-ac4731581517@suse.com/","msgid":"<76fa0c3c-2303-ebdf-a765-ac4731581517@suse.com>","list_archive_url":null,"date":"2022-09-30T08:54:18","name":"objcopy: avoid \"shadowing\" of remove() function name","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/76fa0c3c-2303-ebdf-a765-ac4731581517@suse.com/mbox/"},{"id":1579,"url":"https://patchwork.plctlab.org/api/1.2/patches/1579/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930085852.71213-1-nelson@rivosinc.com/","msgid":"<20220930085852.71213-1-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-09-30T08:58:51","name":"[1/2] RISC-V: Output mapping symbols with ISA string.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930085852.71213-1-nelson@rivosinc.com/mbox/"},{"id":1578,"url":"https://patchwork.plctlab.org/api/1.2/patches/1578/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930085852.71213-2-nelson@rivosinc.com/","msgid":"<20220930085852.71213-2-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-09-30T08:58:52","name":"[2/2] RISC-V: Refer mapping symbol to R_RISCV_RELAX for rvc relaxations.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930085852.71213-2-nelson@rivosinc.com/mbox/"},{"id":1581,"url":"https://patchwork.plctlab.org/api/1.2/patches/1581/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930092058.71286-1-nelson@rivosinc.com/","msgid":"<20220930092058.71286-1-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-09-30T09:20:57","name":"[1/2] RISC-V: Output mapping symbols with ISA string.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930092058.71286-1-nelson@rivosinc.com/mbox/"},{"id":1580,"url":"https://patchwork.plctlab.org/api/1.2/patches/1580/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930092058.71286-2-nelson@rivosinc.com/","msgid":"<20220930092058.71286-2-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-09-30T09:20:58","name":"[2/2] RISC-V: Refer mapping symbol to R_RISCV_RELAX for rvc relaxations.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930092058.71286-2-nelson@rivosinc.com/mbox/"},{"id":1582,"url":"https://patchwork.plctlab.org/api/1.2/patches/1582/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5874dd79-0cf5-d65c-7ea2-13adfc799c0f@suse.com/","msgid":"<5874dd79-0cf5-d65c-7ea2-13adfc799c0f@suse.com>","list_archive_url":null,"date":"2022-09-30T09:41:29","name":"RISC-V: fix build after \"Add support for arbitrary immediate encoding formats\"","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5874dd79-0cf5-d65c-7ea2-13adfc799c0f@suse.com/mbox/"},{"id":1583,"url":"https://patchwork.plctlab.org/api/1.2/patches/1583/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/57d8ac2a-5757-3776-9924-99c17ca69938@suse.com/","msgid":"<57d8ac2a-5757-3776-9924-99c17ca69938@suse.com>","list_archive_url":null,"date":"2022-09-30T09:42:08","name":"RISC-V: fallout from \"re-arrange opcode table for consistent alias handling\"","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/57d8ac2a-5757-3776-9924-99c17ca69938@suse.com/mbox/"},{"id":1584,"url":"https://patchwork.plctlab.org/api/1.2/patches/1584/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e76ef8f7-72b9-5103-cb43-9608af01d017@suse.com/","msgid":"","list_archive_url":null,"date":"2022-09-30T09:42:50","name":"RISC-V: don'\''t cast expressions'\'' X_add_number to long in diagnostics","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e76ef8f7-72b9-5103-cb43-9608af01d017@suse.com/mbox/"},{"id":1585,"url":"https://patchwork.plctlab.org/api/1.2/patches/1585/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/61355429-24b3-17d0-ab03-6fa57ee861d5@suse.cz/","msgid":"<61355429-24b3-17d0-ab03-6fa57ee861d5@suse.cz>","list_archive_url":null,"date":"2022-09-30T09:48:52","name":"[RFC] add --enable-zstd-compressed-debug-sections configure option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/61355429-24b3-17d0-ab03-6fa57ee861d5@suse.cz/mbox/"},{"id":1586,"url":"https://patchwork.plctlab.org/api/1.2/patches/1586/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930103919.323690-1-christoph.muellner@vrull.eu/","msgid":"<20220930103919.323690-1-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2022-09-30T10:39:19","name":"RISC-V: Eliminate long-casts of X_add_number in diagnostics","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930103919.323690-1-christoph.muellner@vrull.eu/mbox/"},{"id":1590,"url":"https://patchwork.plctlab.org/api/1.2/patches/1590/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/DM6PR12MB4219C943049C6D883DEA3E55E7569@DM6PR12MB4219.namprd12.prod.outlook.com/","msgid":"","list_archive_url":null,"date":"2022-09-30T11:41:37","name":"[V2] Ignore DWARF debug information for -gsplit-dwarf with dwarf-5.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/DM6PR12MB4219C943049C6D883DEA3E55E7569@DM6PR12MB4219.namprd12.prod.outlook.com/mbox/"},{"id":1591,"url":"https://patchwork.plctlab.org/api/1.2/patches/1591/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c10321f9-d289-ef84-d263-bc278fb3d31b@suse.com/","msgid":"","list_archive_url":null,"date":"2022-09-30T11:59:04","name":"[1/4] RISC-V/gas: drop riscv_subsets static variable","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c10321f9-d289-ef84-d263-bc278fb3d31b@suse.com/mbox/"},{"id":1593,"url":"https://patchwork.plctlab.org/api/1.2/patches/1593/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3244eea0-c18c-e49a-4588-d69423130226@suse.com/","msgid":"<3244eea0-c18c-e49a-4588-d69423130226@suse.com>","list_archive_url":null,"date":"2022-09-30T11:59:23","name":"[2/4] RISC-V/gas: drop stray call to install_insn()","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3244eea0-c18c-e49a-4588-d69423130226@suse.com/mbox/"},{"id":1592,"url":"https://patchwork.plctlab.org/api/1.2/patches/1592/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/385d01fd-7e57-1f3f-1bae-30aa0c313d63@suse.com/","msgid":"<385d01fd-7e57-1f3f-1bae-30aa0c313d63@suse.com>","list_archive_url":null,"date":"2022-09-30T11:59:45","name":"[3/4] RISC-V/gas: don'\''t open-code insn_length()","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/385d01fd-7e57-1f3f-1bae-30aa0c313d63@suse.com/mbox/"},{"id":1594,"url":"https://patchwork.plctlab.org/api/1.2/patches/1594/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f5757acf-7b90-a0e3-5eea-3b97cc226930@suse.com/","msgid":"","list_archive_url":null,"date":"2022-09-30T12:00:12","name":"[4/4] RISC-V/gas: allow generating up to 176-bit instructions with .insn","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f5757acf-7b90-a0e3-5eea-3b97cc226930@suse.com/mbox/"},{"id":1596,"url":"https://patchwork.plctlab.org/api/1.2/patches/1596/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930140503.38233-1-chigot@adacore.com/","msgid":"<20220930140503.38233-1-chigot@adacore.com>","list_archive_url":null,"date":"2022-09-30T14:05:03","name":"ld/testsuite: consistently add board_ldflags when linking with GCC","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930140503.38233-1-chigot@adacore.com/mbox/"}],"public":true,"mbox":"https://patchwork.plctlab.org/bundle/patchwork-bot/binutils-gdb_2022-09/mbox/"}]' + bundle_id=6 + git-pw bundle add 6 12017 +------------+----------------------------------------------------------------------------------------+ | Property | Value | |------------+----------------------------------------------------------------------------------------| | ID | 6 | | Name | binutils-gdb_2022-10 | | URL | https://patchwork.plctlab.org/bundle/patchwork-bot/binutils-gdb_2022-10/ | | Owner | patchwork-bot | | Project | binutils-gdb | | Public | True | | Patches | 1592 [3/4] RISC-V/gas: don't open-code insn_length() | | | 1594 [4/4] RISC-V/gas: allow generating up to 176-bit instructions with .insn | | | 1596 ld/testsuite: consistently add board_ldflags when linking with GCC | | | 1619 gold, dwp: support zstd compressed input debug sections [PR 29641] | | | 1620 gold: add --compress-debug-sections=zstd [PR 29641] | | | 1623 [RFC,1/1] RISC-V: Implement common register pair framework | | | 1625 [RFC,1/1] RISC-V: Implement extension variants | | | 1626 [1/1] RISC-V: Move supervisor instructions after all unprivileged ones | | | 1627 readelf: support zstd compressed debug sections [PR 29640] | | | 1631 [PATCHv2,2/2] opcodes/arm: add disassembler styling for arm | | | 1635 diagnostics.h: GCC 13 got -Wself-move, breaks GDB build | | | 1637 [1/2] ld: Add --pdb option | | | 1638 [2/2] ld: Add minimal pdb generation | | | 1640 [1/2] refactor usage of compressed_debug_section_type | | | 1641 [2/2] add --enable-default-compressed-debug-sections-algorithm configure option | | | 1642 opcodes/riscv: style csr names as registers | | | 1643 [v3,1/6] RISC-V: Fix immediates to have "immediate" style | | | 1644 [v3,2/6] RISC-V: Fix printf argument types corresponding %x | | | 1647 [v3,3/6] RISC-V: Optimize riscv_disassemble_data printf | | | 1646 [v3,4/6] RISC-V: Print comma and tabs as the "text" style | | | 1648 [v3,5/6] RISC-V: Fix T-Head immediate types on printing | | | 1649 [v3,6/6] RISC-V: Print XTheadMemPair literal as "immediate" | | | 1656 Commit: readelf: Do not load section data from offset 0 | | | 1659 [PATCHv2,1/2] opcodes/arm: use '@' consistently for the comment character | | | 1660 gas: NEWS: Mention the T-Head extensions that were recently added | | | 1671 Support objcopy changing compression to or from zstd | | | 1673 [1/2] RISC-V: Fix buffer overflow on print_insn_riscv | | | 1672 [2/2] gdb/riscv: Fix buffer overflow on riscv_insn::fetch_instruction | | | 1676 [v2,1/2] RISC-V: Fix buffer overflow on print_insn_riscv | | | 1677 [v2,2/2] gdb/riscv: Partial support for instructions up to 176-bits | | | 1678 [v3,1/2] RISC-V: Fix buffer overflow on print_insn_riscv | | | 1679 [v3,2/2] gdb/riscv: Partial support for instructions up to 176-bit | | | 1681 RISC-V: Zicbo{m,p,z} adjustments to riscv_multi_subset_supports_ext() | | | 1690 gprofng: fix build with --enable-pgo-build=lto | | | 1691 bfd: xtensa: fix __stop_SECTION literal drop, | | | 1702 [RFC] bfd: use bfd_vma for the 64-bit version of put[lb] and get[lb] | | | 1711 PR29647, objdump -S looping | | | 1712 [v3,1/7] x86: constify parse_insn()'s input | | | 1713 [v3,2/7] x86: introduce Pass2 insn attribute | | | 1714 [v3,3/7] x86: re-work insn/suffix recognition | | | 1715 [v3,4/7] x86-64: further re-work insn/suffix recognition to also cover MOVSL | | | 1716 [v3,5/7] ix86: don't recognize/derive Q suffix in the common case | | | 1718 [v3,6/7] x86-64: allow HLE store of accumulator to absolute 32-bit address | | | 1717 [v3,7/7] x86: move bad-use-of-TLS-reloc check | | | 1719 x86: drop "regmask" static variable | | | 1751 [v2,1/2] RISC-V: Fallback for instructions longer than 64b | | | 1752 [v2,2/2] RISC-V: Improve "bits undefined" diagnostics | | | 1776 [v3,1/2] RISC-V: Fallback for instructions longer than 64b | | | 1777 [v3,2/2] RISC-V: Improve "bits undefined" diagnostics | | | 1781 RISC-V: fix linker message when relaxation deletes bytes | | | 1801 PR29653, objcopy/strip: fuzzed small input file induces large output file | | | 1803 @CPP_FOR_BUILD@ problem since binutils-2.38 | | | 1827 [v2,1/1] RISC-V: Test DWARF register numbers for "fp" | | | 1828 [1/1] RISC-V: Move standard hints before all instructions | | | 1829 [RFC,1/1] RISC-V: Imply 'Zicsr' from privileged extensions with CSRs | | | 1830 [1/5] opcodes/riscv-dis.c: Tidying with comments/clarity | | | 1832 [2/5] opcodes/riscv-dis.c: Tidying with spacing | | | 1831 [3/5] opcodes/riscv-dis.c: Use bool type whenever possible | | | 1833 [4/5] opcodes/riscv-dis.c: Make XLEN variable static | | | 1834 [5/5] opcodes/riscv-dis.c: Remove last_map_state | | | 1836 RISC-V: Move certain arrays to riscv-opc.c | | | 1844 [v2,1/2] ld: Add --pdb option | | | 1845 [v2,2/2] ld: Add minimal pdb generation | | | 1890 gprofng: run tests without installation | | | 1893 [2/2] gprofng: use the --libdir path to find libraries | | | 1894 [3/3] gprofng: no need to build version.texi | | | 1895 [v3,1/2] ld: Add --pdb option | | | 1897 [v3,2/2] ld: Add minimal pdb generation | | | 1928 [v4,1/2] ld: Add --pdb option | | | 1929 [v4,2/2] ld: Add minimal pdb generation | | | 1941 [pushed] Re-apply "Pass PKG_CONFIG_PATH down from top-level Makefile" | | | 1976 [v4,1/8] x86: constify parse_insn()'s input | | | 1977 [v4,2/8] x86: introduce Pass2 insn attribute | | | 1978 [v4,3/8] x86: re-work insn/suffix recognition | | | 1979 [v4,4/8] x86-64: further re-work insn/suffix recognition to also cover MOVSL | | | 1980 [v4,5/8] ix86: don't recognize/derive Q suffix in the common case | | | 1981 [v4,6/8] x86-64: allow HLE store of accumulator to absolute 32-bit address | | | 1982 [v4,7/8] x86: move bad-use-of-TLS-reloc check | | | 1983 [v4,8/8] x86: drop (now) stray IsString | | | 2013 include: Declare getopt function on old GNU libc | | | 2352 ld: Add --undefined-version | | | 2532 [1/1] RISC-V: Make R_RISCV_SUB6 conforms to riscv abi standard | | | 2560 [v3] aarch64-pe support for LD, GAS and BFD | | | 2602 [01/10] Support Intel AVX-IFMA | | | 2608 [02/10] Support Intel AVX-VNNI-INT8 | | | 2611 [03/10] Support Intel AVX-NE-CONVERT | | | 2610 [04/10] Support Intel CMPccXADD | | | 2601 [05/10] Add handler for more i386_cpu_flags | | | 2606 [06/10] Support Intel RAO-INT | | | 2609 [07/10] Support Intel WRMSRNS | | | 2605 [08/10] Support Intel MSRLIST | | | 2607 [09/10] Support Intel AMX-FP16 | | | 2604 [10/10] Support Intel PREFETCHI | | | 2643 x86: fold AVX512-VNNI disassembler entries with AVX-VNNI ones | | | 2654 PR29677, Field `the_bfd` of `asymbol` is uninitialised | | | 2656 e200 LSP support | | | 2657 PowerPC SPE disassembly and tests | | | 2695 Binutils: Adding new testcase for addr2line. | | | 2700 x86: properly decode EVEX.W for AVX512_4{FMAPS,VNNIW} insns | | | 2981 PowerPC se_rfmci and VLE, SPE2 and LSP insns with -many | | | 3152 [v5,1/2] ld: Add --pdb option | | | 3151 [v5,2/2] ld: Add minimal pdb generation | | | 3258 x86: correct CPU_AMX_{BF16,INT8}_FLAGS | | | 3272 x86: generalize gas documentation for disabling of ISA extensions | | | 3759 [V2,01/15] sframe.h: Add SFrame format definition | | | 3762 [V2,02/15] gas: add new command line option --gsframe | | | 3761 [V2,03/15] gas: generate .sframe from CFI directives | | | 3760 [V2,04/15] gas: testsuite: add new tests for SFrame unwind info | | | 3764 [V2,05/15] libsframe: add the SFrame library | | | 3766 [V2,06/15] bfd: linker: merge .sframe sections | | | 3763 [V2,07/15] readelf/objdump: support for SFrame section | | | 3765 [V2,08/15] unwinder: generate backtrace using SFrame format | | | 3770 [V2,09/15] unwinder: Add SFrame unwinder tests | | | 3769 [V2,10/15] gdb: sim: buildsystem changes to accommodate libsframe | | | 3771 [V2,11/15] libctf: add libsframe to LDFLAGS and LIBS | | | 3768 [V2,12/15] src-release.sh: Add libsframe | | | 3767 [V2,13/15] binutils/NEWS: add text for SFrame support | | | 3772 [V2,14/15] gas/NEWS: add text about new command line option and SFrame support | | | 3773 [V2,15/15] doc: add SFrame spec file | | | 3999 [1/1] IBM zSystems: Issue error for *DBL relocs on misaligned symbols | | | 4141 xtensa: use definitions from xtensa-config.h | | | 4272 x86: Disable AVX-VNNI when disabling AVX2 | | | 4998 x86: re-work AVX-VNNI support | | | 5276 Fix addr2line test for ppc64 elfv1 and mingw | | | 5424 binutils: Remove unused substitution PROGRAM | | | 5433 [v2,1/8] RISC-V: Add a space at the end of pinfo | | | 5435 [v2,2/8] RISC-V: Fix obvious misalignments ('Zbb'/'Zba') | | | 5437 [v2,3/8] RISC-V: Remove spaces in opcode entries | | | 5436 [v2,4/8] RISC-V: Remove unused instruction macros | | | 5440 [v2,5/8] RISC-V: Complete tidying up with SCALL and SBREAK | | | 5442 [v2,6/8] RISC-V: Tidying up with fmv.w.x and fmv.x.w | | | 5438 [v2,7/8] RISC-V: Make alias instructions aliases | | | 5441 [v2,8/8] RISC-V: Use defined mask and match values | | | 5439 RISC-V: Remove RV32EF conflict | | | 5616 [04/10] Support Intel CMPccXADD | | | 5614 [05/10] Add handler for more i386_cpu_flags | | | 5672 [01/10] Support Intel AVX-IFMA | | | 5691 [02/10] Support Intel AVX-VNNI-INT8 | | | 5690 [03/10] Support Intel AVX-NE-CONVERT | | | 5689 [04/10] Support Intel CMPccXADD | | | 5676 [05/10] Add handler for more i386_cpu_flags | | | 5677 [06/10] Support Intel RAO-INT | | | 5681 [07/10] Support Intel WRMSRNS | | | 5682 [08/10] Support Intel MSRLIST | | | 5673 [09/10] Support Intel AMX-FP16 | | | 5686 [10/10] Support Intel PREFETCHI | | | 11921 [1/2] ld: Add section header stream to PDB files | | | 11922 [2/2] ld: Add publics stream to PDB files | | | 11965 [1/2] gas: NEWS: Add a missing newline | | | 11966 [2/2] gas: NEWS: Note support for RISC-V Zawrs | | | 12016 [COMMITTED] PowerPC: Add support for RFC02653 - Dense Math Facility | | | 12017 [COMMITTED] PowerPC: Add support for RFC02658 - MMA+ Outer-Product, Instructions | +------------+----------------------------------------------------------------------------------------+ + git config pull.rebase false + git fetch origin master From github.com:wangliu-iscas/binutils-gdb * branch master -> FETCH_HEAD + git checkout master Switched to a new branch 'master' branch 'master' set up to track 'origin/master'. + git pull origin master From github.com:wangliu-iscas/binutils-gdb * branch master -> FETCH_HEAD Already up to date. + git fetch origin upstream-master From github.com:wangliu-iscas/binutils-gdb * branch upstream-master -> FETCH_HEAD + git checkout upstream-master Switched to a new branch 'upstream-master' branch 'upstream-master' set up to track 'origin/upstream-master'. + git remote add upstream https://sourceware.org/git/binutils-gdb.git + git pull upstream master From https://sourceware.org/git/binutils-gdb * branch master -> FETCH_HEAD * [new branch] master -> upstream/master Already up to date. + git push -u origin upstream-master Everything up-to-date branch 'upstream-master' set up to track 'origin/upstream-master'. + git checkout master Switched to branch 'master' Your branch is up to date with 'origin/master'. + git merge upstream-master Already up to date. + git push -u origin master Everything up-to-date branch 'master' set up to track 'origin/master'. + branchname=series4475-patch12017 ++ git branch -a ++ grep 'series4475-patch12017$' + checkbranch= + checkbranchresult=null + '[' null = series4475-patch12017 ']' + git checkout -b series4475-patch12017 Switched to a new branch 'series4475-patch12017' ++ curl https://patchwork.plctlab.org/api/1.2/series/4475/ % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 1445 100 1445 0 0 41285 0 --:--:-- --:--:-- --:--:-- 41285 + series_response='{"id":4475,"url":"https://patchwork.plctlab.org/api/1.2/series/4475/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/list/?series=4475","project":{"id":2,"url":"https://patchwork.plctlab.org/api/1.2/projects/2/","name":"binutils-gdb","link_name":"binutils-gdb","list_id":"binutils.sourceware.org","list_email":"binutils@sourceware.org","web_url":"https://sourceware.org/mailman/listinfo/binutils","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"name":"[COMMITTED] PowerPC: Add support for RFC02658 - MMA+ Outer-Product, Instructions","date":"2022-10-28T00:37:18","submitter":{"id":123,"url":"https://patchwork.plctlab.org/api/1.2/people/123/","name":"Peter Bergner","email":"bergner@linux.ibm.com"},"version":1,"total":1,"received_total":1,"received_all":true,"mbox":"https://patchwork.plctlab.org/series/4475/mbox/","cover_letter":null,"patches":[{"id":12017,"url":"https://patchwork.plctlab.org/api/1.2/patches/12017/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fd94047d-a070-45a6-3840-c105391718e0@linux.ibm.com/","msgid":"","list_archive_url":null,"date":"2022-10-28T00:37:18","name":"[COMMITTED] PowerPC: Add support for RFC02658 - MMA+ Outer-Product, Instructions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fd94047d-a070-45a6-3840-c105391718e0@linux.ibm.com/mbox/"}]}' ++ jq '.patches[] | (.id|tostring) + "," + .mbox' ++ echo '{"id":4475,"url":"https://patchwork.plctlab.org/api/1.2/series/4475/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/list/?series=4475","project":{"id":2,"url":"https://patchwork.plctlab.org/api/1.2/projects/2/","name":"binutils-gdb","link_name":"binutils-gdb","list_id":"binutils.sourceware.org","list_email":"binutils@sourceware.org","web_url":"https://sourceware.org/mailman/listinfo/binutils","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"name":"[COMMITTED] PowerPC: Add support for RFC02658 - MMA+ Outer-Product, Instructions","date":"2022-10-28T00:37:18","submitter":{"id":123,"url":"https://patchwork.plctlab.org/api/1.2/people/123/","name":"Peter Bergner","email":"bergner@linux.ibm.com"},"version":1,"total":1,"received_total":1,"received_all":true,"mbox":"https://patchwork.plctlab.org/series/4475/mbox/","cover_letter":null,"patches":[{"id":12017,"url":"https://patchwork.plctlab.org/api/1.2/patches/12017/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fd94047d-a070-45a6-3840-c105391718e0@linux.ibm.com/","msgid":"","list_archive_url":null,"date":"2022-10-28T00:37:18","name":"[COMMITTED] PowerPC: Add support for RFC02658 - MMA+ Outer-Product, Instructions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fd94047d-a070-45a6-3840-c105391718e0@linux.ibm.com/mbox/"}]}' + patchid_patchurl='"12017,https://patchwork.plctlab.org/project/binutils-gdb/patch/fd94047d-a070-45a6-3840-c105391718e0@linux.ibm.com/mbox/"' + echo '"12017,https://patchwork.plctlab.org/project/binutils-gdb/patch/fd94047d-a070-45a6-3840-c105391718e0@linux.ibm.com/mbox/"' + IFS=, + read -r series_patch_id series_patch_url ++ echo '"12017' ++ sed 's/"//g' + series_patch_id=12017 ++ echo 'https://patchwork.plctlab.org/project/binutils-gdb/patch/fd94047d-a070-45a6-3840-c105391718e0@linux.ibm.com/mbox/"' ++ sed 's/"//g' + series_patch_url=https://patchwork.plctlab.org/project/binutils-gdb/patch/fd94047d-a070-45a6-3840-c105391718e0@linux.ibm.com/mbox/ ++ git rev-parse HEAD + commitid_before=bb98553cad4e017f1851153fa5de91f2cee98fb2 + eval '+++ declare -p bout bret declare -- bout="Applying: PowerPC: Add support for RFC02658 - MMA+ Outer-Product, Instructions error: sha1 information is lacking or useless (gas/config/tc-ppc.c). error: could not build fake ancestor hint: Use '\''git am --show-current-patch=diff'\'' to see the failed patch Patch failed at 0001 PowerPC: Add support for RFC02658 - MMA+ Outer-Product, Instructions When you have resolved this problem, run \"git am --continue\". If you prefer to skip this patch, run \"git am --skip\" instead. To restore the original branch and stop patching, run \"git am --abort\"." declare -- bret="128" ++ berr='\''++++ git_am https://patchwork.plctlab.org/project/binutils-gdb/patch/fd94047d-a070-45a6-3840-c105391718e0@linux.ibm.com/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/binutils-gdb/patch/fd94047d-a070-45a6-3840-c105391718e0@linux.ibm.com/mbox/ ++++ curl https://patchwork.plctlab.org/project/binutils-gdb/patch/fd94047d-a070-45a6-3840-c105391718e0@linux.ibm.com/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 26332 100 26332 0 0 598k 0 --:--:-- --:--:-- --:--:-- 584k +++ bout='\''\'\'''\''Applying: PowerPC: Add support for RFC02658 - MMA+ Outer-Product, Instructions error: sha1 information is lacking or useless (gas/config/tc-ppc.c). error: could not build fake ancestor hint: Use '\''\'\'''\''\'\''\'\'''\'''\''\'\'''\''git am --show-current-patch=diff'\''\'\'''\''\'\''\'\'''\'''\''\'\'''\'' to see the failed patch Patch failed at 0001 PowerPC: Add support for RFC02658 - MMA+ Outer-Product, Instructions When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort".'\''\'\'''\'' +++ bret=128'\'' ++ declare -p berr declare -- berr="++++ git_am https://patchwork.plctlab.org/project/binutils-gdb/patch/fd94047d-a070-45a6-3840-c105391718e0@linux.ibm.com/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/binutils-gdb/patch/fd94047d-a070-45a6-3840-c105391718e0@linux.ibm.com/mbox/ ++++ curl https://patchwork.plctlab.org/project/binutils-gdb/patch/fd94047d-a070-45a6-3840-c105391718e0@linux.ibm.com/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 26332 100 26332 0 0 598k 0 --:--:-- --:--:-- --:--:-- 584k +++ bout='\''Applying: PowerPC: Add support for RFC02658 - MMA+ Outer-Product, Instructions error: sha1 information is lacking or useless (gas/config/tc-ppc.c). error: could not build fake ancestor hint: Use '\''\\'\'''\''git am --show-current-patch=diff'\''\\'\'''\'' to see the failed patch Patch failed at 0001 PowerPC: Add support for RFC02658 - MMA+ Outer-Product, Instructions When you have resolved this problem, run \"git am --continue\". If you prefer to skip this patch, run \"git am --skip\" instead. To restore the original branch and stop patching, run \"git am --abort\".'\'' +++ bret=128"' ++ +++ declare -p bout bret /tmp/jenkins537921939128304312.sh: line 124: +++: command not found ++ declare -- 'bout=Applying: PowerPC: Add support for RFC02658 - MMA+ Outer-Product, Instructions error: sha1 information is lacking or useless (gas/config/tc-ppc.c). error: could not build fake ancestor hint: Use '\''git am --show-current-patch=diff'\'' to see the failed patch Patch failed at 0001 PowerPC: Add support for RFC02658 - MMA+ Outer-Product, Instructions When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort".' ++ declare -- bret=128 ++ ++ 'berr=++++ git_am https://patchwork.plctlab.org/project/binutils-gdb/patch/fd94047d-a070-45a6-3840-c105391718e0@linux.ibm.com/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/binutils-gdb/patch/fd94047d-a070-45a6-3840-c105391718e0@linux.ibm.com/mbox/ ++++ curl https://patchwork.plctlab.org/project/binutils-gdb/patch/fd94047d-a070-45a6-3840-c105391718e0@linux.ibm.com/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 26332 100 26332 0 0 598k 0 --:--:-- --:--:-- --:--:-- 584k +++ bout='\''Applying: PowerPC: Add support for RFC02658 - MMA+ Outer-Product, Instructions error: sha1 information is lacking or useless (gas/config/tc-ppc.c). error: could not build fake ancestor hint: Use '\''\'\'''\''git am --show-current-patch=diff'\''\'\'''\'' to see the failed patch Patch failed at 0001 PowerPC: Add support for RFC02658 - MMA+ Outer-Product, Instructions When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort".'\'' +++ bret=128' /tmp/jenkins537921939128304312.sh: line 149: ++: command not found ++ ++ declare -p berr /tmp/jenkins537921939128304312.sh: line 150: ++: command not found ++ declare -- 'berr=++++ git_am https://patchwork.plctlab.org/project/binutils-gdb/patch/fd94047d-a070-45a6-3840-c105391718e0@linux.ibm.com/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/binutils-gdb/patch/fd94047d-a070-45a6-3840-c105391718e0@linux.ibm.com/mbox/ ++++ curl https://patchwork.plctlab.org/project/binutils-gdb/patch/fd94047d-a070-45a6-3840-c105391718e0@linux.ibm.com/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 26332 100 26332 0 0 598k 0 --:--:-- --:--:-- --:--:-- 584k +++ bout='\''Applying: PowerPC: Add support for RFC02658 - MMA+ Outer-Product, Instructions error: sha1 information is lacking or useless (gas/config/tc-ppc.c). error: could not build fake ancestor hint: Use '\''\'\'''\''git am --show-current-patch=diff'\''\'\'''\'' to see the failed patch Patch failed at 0001 PowerPC: Add support for RFC02658 - MMA+ Outer-Product, Instructions When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort".'\'' +++ bret=128' ++ git rev-parse HEAD + commitid_after=bb98553cad4e017f1851153fa5de91f2cee98fb2 + '[' 128 = 0 ']' + [[ ++++ git_am https://patchwork.plctlab.org/project/binutils-gdb/patch/fd94047d-a070-45a6-3840-c105391718e0@linux.ibm.com/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/binutils-gdb/patch/fd94047d-a070-45a6-3840-c105391718e0@linux.ibm.com/mbox/ ++++ curl https://patchwork.plctlab.org/project/binutils-gdb/patch/fd94047d-a070-45a6-3840-c105391718e0@linux.ibm.com/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 26332 100 26332 0 0 598k 0 --:--:-- --:--:-- --:--:-- 584k +++ bout='Applying: PowerPC: Add support for RFC02658 - MMA+ Outer-Product, Instructions error: sha1 information is lacking or useless (gas/config/tc-ppc.c). error: could not build fake ancestor hint: Use '\''git am --show-current-patch=diff'\'' to see the failed patch Patch failed at 0001 PowerPC: Add support for RFC02658 - MMA+ Outer-Product, Instructions When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort".' +++ bret=128 =~ sha1 information is lacking or useless ]] + submit_check warning Unresolved https://patchwork.plctlab.org/jenkins/job/binutils-gdb/229/consoleText 'Git am fail log' + check_state=warning + patch_state=Unresolved + repo_url=https://patchwork.plctlab.org/jenkins/job/binutils-gdb/229/consoleText + DESCRIPTION='Git am fail log' + curl -X POST -H 'Authorization: Token [*******]' -F state=warning -F target_url=https://patchwork.plctlab.org/jenkins/job/binutils-gdb/229/consoleText -F context=binutils-gdb-check -F 'description=Git am fail log' https://patchwork.plctlab.org/api/patches/12017/checks/ % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 975 100 430 100 545 11944 15138 --:--:-- --:--:-- --:--:-- 27083 {"id":1464,"url":"https://patchwork.plctlab.org/api/patches/12017/checks/1464/","user":{"id":1,"url":"https://patchwork.plctlab.org/api/users/1/","username":"snail","first_name":"","last_name":"","email":"wangliu@iscas.ac.cn"},"date":"2022-10-28T01:17:05.936651","state":"warning","target_url":"https://patchwork.plctlab.org/jenkins/job/binutils-gdb/229/consoleText","context":"binutils-gdb-check","description":"Git am fail log"}+ curl -X PATCH -H 'Authorization: Token [*******]' -F state=Unresolved https://patchwork.plctlab.org/api/1.2/patches/12017/ % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0{"id":12017,"url":"https://patchwork.plctlab.org/api/1.2/patches/12017/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fd94047d-a070-45a6-3840-c105391718e0@linux.ibm.com/","project":{"id":2,"url":"https://patchwork.plctlab.org/api/1.2/projects/2/","name":"binutils-gdb","link_name":"binutils-gdb","list_id":"binutils.sourceware.org","list_email":"binutils@sourceware.org","web_url":"https://sourceware.org/mailman/listinfo/binutils","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"","list_archive_url":null,"date":"2022-10-28T00:37:18","name":"[COMMITTED] PowerPC: Add support for RFC02658 - MMA+ Outer-Product, Instructions","commit_ref":null,"pull_url":null,"state":"unresolved","archived":false,"hash":"c6da927691bdc68f6c422ecdbfb9c344f0e50e95","submitter":{"id":123,"url":"https://patchwork.plctlab.org/api/1.2/people/123/","name":"Peter Bergner","email":"bergner@linux.ibm.com"},"delegate":null,"mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fd94047d-a070-45a6-3840-c105391718e0@linux.ibm.com/mbox/","series":[{"id":4475,"url":"https://patchwork.plctlab.org/api/1.2/series/4475/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/list/?series=4475","date":"2022-10-28T00:37:18","name":"[COMMITTED] PowerPC: Add support for RFC02658 - MMA+ Outer-Product, Instructions","version":1,"mbox":"https://patchwork.plctlab.org/series/4475/mbox/"}],"comments":"https://patchwork.plctlab.org/api/patches/12017/comments/","check":"warning","checks":"https://patchwork.plctlab.org/api/patches/12017/checks/","tags":{},"headers":{"Return-Path":"","Delivered-To":["ouuuleilei@gmail.com","binutils@sourceware.org"],"Received":["by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp536114wru;\n Thu, 27 Oct 2022 17:37:36 -0700 (PDT)","from sourceware.org (server2.sourceware.org.\n [2620:52:3:1:0:246e:9693:128c])\n by mx.google.com with ESMTPS id\n s20-20020a056402521400b00461e426dcb0si2868670edd.609.2022.10.27.17.37.36\n for \n (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256);\n Thu, 27 Oct 2022 17:37:36 -0700 (PDT)","from server2.sourceware.org (localhost [IPv6:::1])\n\tby sourceware.org (Postfix) with ESMTP id 019A8384A804\n\tfor ; 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a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org;\n\ts=default; t=1666917455;\n\tbh=xlEaTcf0cMcRV5IKEQWEjvvd2VLEq8lsCQaKEcx8uRM=;\n\th=Date:To:Subject:List-Id:List-Unsubscribe:List-Archive:List-Post:\n\t List-Help:List-Subscribe:From:Reply-To:From;\n\tb=aGdWGpBlmV/QIP112c0R6UinQiOwwswIysCy6/+KeeDeRbP1yYYpDhgG9OQwASC/F\n\t eNIsXwv6Jzv4QMQ7mss6bjibKvcPXFJdb/B+pdQLERF+3OaWdclG7t4+P4GIQMPMYY\n\t QBM0SiD2lpEKZtHYxlNht61JPVn/pRe7JLINX3hk=","X-Original-To":"binutils@sourceware.org","DMARC-Filter":"OpenDMARC Filter v1.4.1 sourceware.org 04EC6385D0E9","Message-ID":"","Date":"Thu, 27 Oct 2022 19:37:18 -0500","MIME-Version":"1.0","User-Agent":"Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:102.0)\n Gecko/20100101 Thunderbird/102.4.0","Content-Language":"en-US","To":"Binutils ","Subject":"[COMMITTED] PowerPC: Add support for RFC02658 - MMA+ Outer-Product,\n Instructions","Content-Type":"text/plain; charset=UTF-8","Content-Transfer-Encoding":"7bit","X-TM-AS-GCONF":"00","X-Proofpoint-ORIG-GUID":"qEdJ3Md83CU9pfmy84SbnbkldTv_N396","X-Proofpoint-GUID":"Z-eiYnfjSW7xSvPNfaRiLHgxXX0O0TTj","X-Proofpoint-Virus-Version":"vendor=baseguard\n engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.545,FMLib:17.11.122.1\n definitions=2022-10-27_07,2022-10-27_01,2022-06-22_01","X-Proofpoint-Spam-Details":"rule=outbound_notspam policy=outbound score=0\n adultscore=0\n priorityscore=1501 malwarescore=0 spamscore=0 mlxscore=0\n lowpriorityscore=0 phishscore=0 mlxlogscore=823 impostorscore=0\n clxscore=1015 bulkscore=0 suspectscore=0 classifier=spam adjust=0\n reason=mlx scancount=1 engine=8.12.0-2210170000\n definitions=main-2210280001","X-Spam-Status":"No, score=-10.9 required=5.0 tests=BAYES_00, DKIM_SIGNED,\n DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_MSPIKE_H2, SPF_HELO_NONE,\n SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6","X-Spam-Checker-Version":"SpamAssassin 3.4.6 (2021-04-09) on\n server2.sourceware.org","X-BeenThere":"binutils@sourceware.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"Binutils mailing list ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","From":"Peter Bergner via Binutils ","Reply-To":"Peter Bergner ","Errors-To":"binutils-bounces+ouuuleilei=gmail.com@sourceware.org","Sender":"\"Binutils\" ","X-getmail-retrieved-from-mailbox":"=?utf-8?q?INBOX?=","X-GMAIL-THRID":"=?utf-8?q?1747889638755073051?=","X-GMAIL-MSGID":"=?utf-8?q?1747889638755073051?="},"content":"The following patch adds support for Power RFC02658 which is an extension\nof the MMA support in power10. When or even if this will ever show up in\nhardware is not determined or guaranteed, therefore this is enabled using\nthe -mfuture gas option.\n\nPeter\n\n\nPowerPC: Add support for RFC02658 - MMA+ Outer-Product Instructions\n\ngas/\n\t* config/tc-ppc.c (md_assemble): Only check for prefix opcodes.\n\t* testsuite/gas/ppc/rfc02658.s: New test.\n\t* testsuite/gas/ppc/rfc02658.d: Likewise.\n\t* testsuite/gas/ppc/ppc.exp: Run it.\n\nopcodes/\n\t* ppc-opc.c (XMSK8, P_GERX4_MASK, P_GERX2_MASK, XX3GERX_MASK): New.\n\t(powerpc_opcodes): Add dmxvi8gerx4pp, dmxvi8gerx4, dmxvf16gerx2pp,\n\tdmxvf16gerx2, dmxvbf16gerx2pp, dmxvf16gerx2np, dmxvbf16gerx2,\n\tdmxvi8gerx4spp, dmxvbf16gerx2np, dmxvf16gerx2pn, dmxvbf16gerx2pn,\n\tdmxvf16gerx2nn, dmxvbf16gerx2nn, pmdmxvi8gerx4pp, pmdmxvi8gerx4,\n\tpmdmxvf16gerx2pp, pmdmxvf16gerx2, pmdmxvbf16gerx2pp, pmdmxvf16gerx2np,\n\tpmdmxvbf16gerx2, pmdmxvi8gerx4spp, pmdmxvbf16gerx2np, pmdmxvf16gerx2pn,\n\tpmdmxvbf16gerx2pn, pmdmxvf16gerx2nn, pmdmxvbf16gerx2nn.\n---\n gas/config/tc-ppc.c | 3 +-\n gas/testsuite/gas/ppc/ppc.exp | 1 +\n gas/testsuite/gas/ppc/rfc02658.d | 51 ++++++++++++++++++++++++++++++++\n gas/testsuite/gas/ppc/rfc02658.s | 28 ++++++++++++++++++\n opcodes/ppc-opc.c | 39 +++++++++++++++++++++++-\n 5 files changed, 119 insertions(+), 3 deletions(-)\n create mode 100644 gas/testsuite/gas/ppc/rfc02658.d\n create mode 100644 gas/testsuite/gas/ppc/rfc02658.s","diff":"diff --git a/gas/config/tc-ppc.c b/gas/config/tc-ppc.c\nindex 1acbba1791a..0868655f40d 100644\n--- a/gas/config/tc-ppc.c\n+++ b/gas/config/tc-ppc.c\n@@ -4065,8 +4065,7 @@ md_assemble (char *str)\n insn_length = 4;\n if ((ppc_cpu & PPC_OPCODE_VLE) != 0 && PPC_OP_SE_VLE (insn))\n insn_length = 2;\n- else if ((opcode->flags & PPC_OPCODE_POWER10) != 0\n-\t && PPC_PREFIX_P (insn))\n+ else if (PPC_PREFIX_P (insn))\n {\n struct insn_label_list *l;\n \ndiff --git a/gas/testsuite/gas/ppc/ppc.exp b/gas/testsuite/gas/ppc/ppc.exp\nindex f27a79cfd73..500738a06ab 100644\n--- a/gas/testsuite/gas/ppc/ppc.exp\n+++ b/gas/testsuite/gas/ppc/ppc.exp\n@@ -146,6 +146,7 @@ run_dump_test \"scalarquad\"\n run_dump_test \"rop\"\n run_dump_test \"rop-checks\"\n run_dump_test \"rfc02653\"\n+run_dump_test \"rfc02658\"\n \n run_dump_test \"dcbt\"\n run_dump_test \"pr27676\"\ndiff --git a/gas/testsuite/gas/ppc/rfc02658.d b/gas/testsuite/gas/ppc/rfc02658.d\nnew file mode 100644\nindex 00000000000..7af7b861217\n--- /dev/null\n+++ b/gas/testsuite/gas/ppc/rfc02658.d\n@@ -0,0 +1,51 @@\n+#as: -mfuture\n+#objdump: -dr -Mfuture\n+#name: RFC02658 tests\n+\n+.*\n+\n+\n+Disassembly of section \\.text:\n+\n+0+0 <_start>:\n+.*:\t(d8 12 00 ec|ec 00 12 d8) \tdmxvbf16gerx2 dm0,vs0,vs2\n+.*:\t(50 67 8a ec|ec 8a 67 50) \tdmxvbf16gerx2nn dm1,vs10,vs12\n+.*:\t(98 b3 14 ed|ed 14 b3 98) \tdmxvbf16gerx2np dm2,vs20,vs22\n+.*:\t(9a 05 9e ed|ed 9e 05 9a) \tdmxvbf16gerx2pn dm3,vs30,vs32\n+.*:\t(56 52 08 ee|ee 08 52 56) \tdmxvbf16gerx2pp dm4,vs40,vs42\n+.*:\t(1e a2 92 ee|ee 92 a2 1e) \tdmxvf16gerx2 dm5,vs50,vs52\n+.*:\t(56 f6 1c ef|ef 1c f6 56) \tdmxvf16gerx2nn dm6,vs60,vs62\n+.*:\t(98 72 8c ef|ef 8c 72 98) \tdmxvf16gerx2np dm7,vs12,vs14\n+.*:\t(98 84 0e ec|ec 0e 84 98) \tdmxvf16gerx2pn dm0,vs14,vs16\n+.*:\t(10 92 90 ec|ec 90 92 10) \tdmxvf16gerx2pp dm1,vs16,vs18\n+.*:\t(58 a0 12 ed|ed 12 a0 58) \tdmxvi8gerx4 dm2,vs18,vs20\n+.*:\t(50 c0 96 ed|ed 96 c0 50) \tdmxvi8gerx4pp dm3,vs22,vs24\n+.*:\t(10 d3 18 ee|ee 18 d3 10) \tdmxvi8gerx4spp dm4,vs24,vs26\n+.*:\t(ff cf 90 07|07 90 cf ff) \tpmdmxvbf16gerx2nn dm0,vs0,vs2,255,15,3\n+.*:\t(50 17 00 ec|ec 00 17 50) \n+.*:\t(00 00 00 60|60 00 00 00) \tnop\n+.*:\t(ff cf 90 07|07 90 cf ff) \tpmdmxvbf16gerx2np dm1,vs10,vs12,255,15,3\n+.*:\t(98 63 8a ec|ec 8a 63 98) \n+.*:\t(ff cf 90 07|07 90 cf ff) \tpmdmxvbf16gerx2 dm2,vs20,vs22,255,15,3\n+.*:\t(d8 b2 14 ed|ed 14 b2 d8) \n+.*:\t(ff cf 90 07|07 90 cf ff) \tpmdmxvbf16gerx2pn dm3,vs30,vs32,255,15,3\n+.*:\t(9a 05 9e ed|ed 9e 05 9a) \n+.*:\t(ff cf 90 07|07 90 cf ff) \tpmdmxvbf16gerx2pp dm4,vs40,vs42,255,15,3\n+.*:\t(56 52 08 ee|ee 08 52 56) \n+.*:\t(ff cf 90 07|07 90 cf ff) \tpmdmxvf16gerx2nn dm5,vs50,vs52,255,15,3\n+.*:\t(56 a6 92 ee|ee 92 a6 56) \n+.*:\t(ff cf 90 07|07 90 cf ff) \tpmdmxvf16gerx2np dm6,vs60,vs62,255,15,3\n+.*:\t(9e f2 1c ef|ef 1c f2 9e) \n+.*:\t(ff cf 90 07|07 90 cf ff) \tpmdmxvf16gerx2 dm7,vs12,vs14,255,15,3\n+.*:\t(18 72 8c ef|ef 8c 72 18) \n+.*:\t(ff cf 90 07|07 90 cf ff) \tpmdmxvf16gerx2pn dm0,vs14,vs16,255,15,3\n+.*:\t(98 84 0e ec|ec 0e 84 98) \n+.*:\t(ff cf 90 07|07 90 cf ff) \tpmdmxvf16gerx2pp dm1,vs16,vs18,255,15,3\n+.*:\t(10 92 90 ec|ec 90 92 10) \n+.*:\t(ff ff 90 07|07 90 ff ff) \tpmdmxvi8gerx4 dm2,vs18,vs20,255,15,15\n+.*:\t(58 a0 12 ed|ed 12 a0 58) \n+.*:\t(ff ff 90 07|07 90 ff ff) \tpmdmxvi8gerx4pp dm3,vs22,vs24,255,15,15\n+.*:\t(50 c0 96 ed|ed 96 c0 50) \n+.*:\t(ff ff 90 07|07 90 ff ff) \tpmdmxvi8gerx4spp dm4,vs24,vs26,255,15,15\n+.*:\t(10 d3 18 ee|ee 18 d3 10) \n+#pass\ndiff --git a/gas/testsuite/gas/ppc/rfc02658.s b/gas/testsuite/gas/ppc/rfc02658.s\nnew file mode 100644\nindex 00000000000..b15fb5fafc6\n--- /dev/null\n+++ b/gas/testsuite/gas/ppc/rfc02658.s\n@@ -0,0 +1,28 @@\n+ .text\n+_start:\n+\tdmxvbf16gerx2\t0,0,2\n+\tdmxvbf16gerx2nn\t1,10,12\n+\tdmxvbf16gerx2np\t2,20,22\n+\tdmxvbf16gerx2pn\t3,30,32\n+\tdmxvbf16gerx2pp\t4,40,42\n+\tdmxvf16gerx2\t5,50,52\n+\tdmxvf16gerx2nn\t6,60,62\n+\tdmxvf16gerx2np\t7,12,14\n+\tdmxvf16gerx2pn\t0,14,16\n+\tdmxvf16gerx2pp\t1,16,18\n+\tdmxvi8gerx4\t2,18,20\n+\tdmxvi8gerx4pp\t3,22,24\n+\tdmxvi8gerx4spp\t4,24,26\n+\tpmdmxvbf16gerx2nn\t0,0,2,0xff,0xf,0x3\n+\tpmdmxvbf16gerx2np\t1,10,12,0xff,0xf,0x3\n+\tpmdmxvbf16gerx2\t\t2,20,22,0xff,0xf,0x3\n+\tpmdmxvbf16gerx2pn\t3,30,32,0xff,0xf,0x3\n+\tpmdmxvbf16gerx2pp\t4,40,42,0xff,0xf,0x3\n+\tpmdmxvf16gerx2nn\t5,50,52,0xff,0xf,0x3\n+\tpmdmxvf16gerx2np\t6,60,62,0xff,0xf,0x3\n+\tpmdmxvf16gerx2\t\t7,12,14,0xff,0xf,0x3\n+\tpmdmxvf16gerx2pn\t0,14,16,0xff,0xf,0x3\n+\tpmdmxvf16gerx2pp\t1,16,18,0xff,0xf,0x3\n+\tpmdmxvi8gerx4\t\t2,18,20,0xff,0xf,0xf\n+\tpmdmxvi8gerx4pp\t\t3,22,24,0xff,0xf,0xf\n+\tpmdmxvi8gerx4spp\t4,24,26,0xff,0xf,0xf\ndiff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c\nindex c323a2761e3..cf729029dac 100644\n--- a/opcodes/ppc-opc.c\n+++ b/opcodes/ppc-opc.c\n@@ -3083,8 +3083,12 @@ const struct powerpc_operand powerpc_operands[] =\n #define XMSK PMSK2 + 1\n { 0xf, 36, NULL, NULL, 0 },\n \n+ /* The XMSK field in GERX prefix instructions. */\n+#define XMSK8 XMSK + 1\n+ { 0xff, 36, NULL, NULL, 0 },\n+\n /* The YMSK field in GER prefix instructions. */\n-#define YMSK XMSK + 1\n+#define YMSK XMSK8 + 1\n { 0xf, 32, NULL, NULL, 0 },\n \n /* The YMSK field in 64-bit GER prefix instructions. */\n@@ -4014,6 +4018,8 @@ const unsigned int num_powerpc_operands = ARRAY_SIZE (powerpc_operands);\n #define P_GER4_MASK (P_GER_MASK & ~(15ULL << 44))\n #define P_GER8_MASK (P_GER_MASK & ~(255ULL << 40))\n #define P_GER64_MASK (P_GER_MASK | (3ULL << 32))\n+#define P_GERX4_MASK ((-1ULL << 48) | XX3GERX_MASK)\n+#define P_GERX2_MASK (P_GERX4_MASK & ~(3ULL << 46))\n \n /* Vector splat immediate op. */\n #define VSOP(op, xop) (OP (op) | (xop << 17))\n@@ -4554,6 +4560,7 @@ const unsigned int num_powerpc_operands = ARRAY_SIZE (powerpc_operands);\n #define XX3ACC_MASK (XX3_MASK | (3 << 21) | 1)\n #define XX3DMR_MASK (XX3ACC_MASK | (1 << 11))\n #define XX2DMR_MASK (XX2ACC_MASK | (0xf << 17))\n+#define XX3GERX_MASK (XX3ACC_MASK | (1 << 16))\n \n /* The mask for an XX4 form instruction. */\n #define XX4_MASK XX4 (0x3f, 0x3)\n@@ -9036,6 +9043,9 @@ const struct powerpc_opcode powerpc_opcodes[] = {\n {\"drrnd\",\tZRC(59,35,0),\tZ2_MASK, POWER6,\tPPCVLE,\t\t{FRT, FRA, FRB, RMC}},\n {\"drrnd.\",\tZRC(59,35,1),\tZ2_MASK, POWER6,\tPPCVLE,\t\t{FRT, FRA, FRB, RMC}},\n \n+{\"dmxvi8gerx4pp\", XX3(59,10),\tXX3GERX_MASK, FUTURE,\tPPCVLE,\t\t{DMR, XA5p, XB6}},\n+{\"dmxvi8gerx4\", XX3(59,11),\tXX3GERX_MASK, FUTURE,\tPPCVLE,\t\t{DMR, XA5p, XB6}},\n+\n {\"dscli\",\tZRC(59,66,0),\tZ_MASK,\t POWER6,\tPPCVLE,\t\t{FRT, FRA, SH16}},\n {\"dscli.\",\tZRC(59,66,1),\tZ_MASK,\t POWER6,\tPPCVLE,\t\t{FRT, FRA, SH16}},\n \n@@ -9092,24 +9102,31 @@ const struct powerpc_opcode powerpc_opcodes[] = {\n {\"dctdp\",\tXRC(59,258,0),\tX_MASK,\t POWER6,\tPPCVLE,\t\t{FRT, FRB}},\n {\"dctdp.\",\tXRC(59,258,1),\tX_MASK,\t POWER6,\tPPCVLE,\t\t{FRT, FRB}},\n \n+{\"dmxvf16gerx2pp\", XX3(59,66),\tXX3GERX_MASK, FUTURE,\tPPCVLE,\t\t{DMR, XA5p, XB6}},\n+{\"dmxvf16gerx2\", XX3(59,67),\tXX3GERX_MASK, FUTURE,\tPPCVLE,\t\t{DMR, XA5p, XB6}},\n+\n {\"dctfix\",\tXRC(59,290,0),\tX_MASK,\t POWER6,\tPPCVLE,\t\t{FRT, FRB}},\n {\"dctfix.\",\tXRC(59,290,1),\tX_MASK,\t POWER6,\tPPCVLE,\t\t{FRT, FRB}},\n \n {\"ddedpd\",\tXRC(59,322,0),\tX_MASK,\t POWER6,\tPPCVLE,\t\t{SP, FRT, FRB}},\n {\"ddedpd.\",\tXRC(59,322,1),\tX_MASK,\t POWER6,\tPPCVLE,\t\t{SP, FRT, FRB}},\n \n+{\"dmxvbf16gerx2pp\", XX3(59,74),\tXX3GERX_MASK, FUTURE,\tPPCVLE,\t\t{DMR, XA5p, XB6}},\n {\"dmxvi16ger2\",\tXX3(59,75),\tXX3ACC_MASK, POWER10,\tPPCVLE,\t\t{ACC, XA6a, XB6a}},\n {\"xvi16ger2\",\tXX3(59,75),\tXX3ACC_MASK, POWER10,\tPPCVLE,\t\t{ACC, XA6a, XB6a}},\n \n {\"dmxvf16ger2np\", XX3(59,82),\tXX3ACC_MASK, POWER10,\tPPCVLE,\t\t{ACC, XA6a, XB6a}},\n {\"xvf16ger2np\",\t XX3(59,82),\tXX3ACC_MASK, POWER10,\tPPCVLE,\t\t{ACC, XA6a, XB6a}},\n+{\"dmxvf16gerx2np\",XX3(59,83),\tXX3GERX_MASK, FUTURE,\tPPCVLE,\t\t{DMR, XA5p, XB6}},\n \n {\"dxex\",\tXRC(59,354,0),\tX_MASK,\t POWER6,\tPPCVLE,\t\t{FRT, FRB}},\n {\"dxex.\",\tXRC(59,354,1),\tX_MASK,\t POWER6,\tPPCVLE,\t\t{FRT, FRB}},\n \n {\"dmxvf32gernp\", XX3(59,90),\tXX3ACC_MASK, POWER10,\tPPCVLE,\t\t{ACC, XA6a, XB6a}},\n {\"xvf32gernp\",\t XX3(59,90),\tXX3ACC_MASK, POWER10,\tPPCVLE,\t\t{ACC, XA6a, XB6a}},\n+{\"dmxvbf16gerx2\", XX3(59,91),\tXX3GERX_MASK, FUTURE,\tPPCVLE,\t\t{DMR, XA5p, XB6}},\n \n+{\"dmxvi8gerx4spp\",XX3(59,98),\tXX3GERX_MASK, FUTURE,\tPPCVLE,\t\t{DMR, XA5p, XB6}},\n {\"dmxvi8ger4spp\", XX3(59,99),\tXX3ACC_MASK, POWER10,\tPPCVLE,\t\t{ACC, XA6a, XB6a}},\n {\"xvi8ger4spp\",\t XX3(59,99),\tXX3ACC_MASK, POWER10,\tPPCVLE,\t\t{ACC, XA6a, XB6a}},\n \n@@ -9118,6 +9135,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {\n \n {\"dmxvbf16ger2np\",XX3(59,114),\tXX3ACC_MASK, POWER10,\tPPCVLE,\t\t{ACC, XA6a, XB6a}},\n {\"xvbf16ger2np\", XX3(59,114),\tXX3ACC_MASK, POWER10,\tPPCVLE,\t\t{ACC, XA6a, XB6a}},\n+{\"dmxvbf16gerx2np\",XX3(59,115),\tXX3GERX_MASK, FUTURE,\tPPCVLE,\t\t{DMR, XA5p, XB6}},\n \n {\"dmxvf64gernp\", XX3(59,122),\tXX3ACC_MASK, POWER10,\tPPCVLE,\t\t{ACC, XA6ap, XB6a}},\n {\"xvf64gernp\",\t XX3(59,122),\tXX3ACC_MASK, POWER10,\tPPCVLE,\t\t{ACC, XA6ap, XB6a}},\n@@ -9130,6 +9148,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {\n \n {\"dmxvf16ger2pn\", XX3(59,146),\tXX3ACC_MASK, POWER10,\tPPCVLE,\t\t{ACC, XA6a, XB6a}},\n {\"xvf16ger2pn\",\t XX3(59,146),\tXX3ACC_MASK, POWER10,\tPPCVLE,\t\t{ACC, XA6a, XB6a}},\n+{\"dmxvf16gerx2pn\",XX3(59,147),\tXX3GERX_MASK, FUTURE,\tPPCVLE,\t\t{DMR, XA5p, XB6}},\n \n {\"dmxvf32gerpn\",XX3(59,154),\tXX3ACC_MASK, POWER10,\tPPCVLE,\t\t{ACC, XA6a, XB6a}},\n {\"xvf32gerpn\",\tXX3(59,154),\tXX3ACC_MASK, POWER10,\tPPCVLE,\t\t{ACC, XA6a, XB6a}},\n@@ -9141,6 +9160,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {\n \n {\"dmxvbf16ger2pn\",XX3(59,178),\tXX3ACC_MASK, POWER10,\tPPCVLE,\t\t{ACC, XA6a, XB6a}},\n {\"xvbf16ger2pn\", XX3(59,178),\tXX3ACC_MASK, POWER10,\tPPCVLE,\t\t{ACC, XA6a, XB6a}},\n+{\"dmxvbf16gerx2pn\", XX3(59,179),XX3GERX_MASK, FUTURE,\tPPCVLE,\t\t{DMR, XA5p, XB6}},\n \n {\"dmxvf64gerpn\",XX3(59,186),\tXX3ACC_MASK, POWER10,\tPPCVLE,\t\t{ACC, XA6ap, XB6a}},\n {\"xvf64gerpn\",\tXX3(59,186),\tXX3ACC_MASK, POWER10,\tPPCVLE,\t\t{ACC, XA6ap, XB6a}},\n@@ -9151,6 +9171,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {\n {\"dcffix\",\tXRC(59,802,0), X_MASK|FRA_MASK, POWER7,\tPPCVLE,\t\t{FRT, FRB}},\n {\"dcffix.\",\tXRC(59,802,1), X_MASK|FRA_MASK, POWER7,\tPPCVLE,\t\t{FRT, FRB}},\n \n+{\"dmxvf16gerx2nn\", XX3(59,202),\tXX3GERX_MASK, FUTURE,\tPPCVLE,\t\t{DMR, XA5p, XB6}},\n+\n {\"denbcd\",\tXRC(59,834,0),\tX_MASK,\t POWER6,\tPPCVLE,\t\t{S, FRT, FRB}},\n {\"denbcd.\",\tXRC(59,834,1),\tX_MASK,\t POWER6,\tPPCVLE,\t\t{S, FRT, FRB}},\n \n@@ -9166,6 +9188,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {\n {\"dmxvf32gernn\",XX3(59,218),\tXX3ACC_MASK, POWER10,\tPPCVLE,\t\t{ACC, XA6a, XB6a}},\n {\"xvf32gernn\",\tXX3(59,218),\tXX3ACC_MASK, POWER10,\tPPCVLE,\t\t{ACC, XA6a, XB6a}},\n \n+{\"dmxvbf16gerx2nn\", XX3(59,234),XX3GERX_MASK, FUTURE,\tPPCVLE,\t\t{DMR, XA5p, XB6}},\n+\n {\"dmxvbf16ger2nn\",XX3(59,242),\tXX3ACC_MASK, POWER10,\tPPCVLE,\t\t{ACC, XA6a, XB6a}},\n {\"xvbf16ger2nn\", XX3(59,242),\tXX3ACC_MASK, POWER10,\tPPCVLE,\t\t{ACC, XA6a, XB6a}},\n \n@@ -9761,6 +9785,8 @@ const struct powerpc_opcode prefix_opcodes[] = {\n {\"pmxvi8ger4pp\", PMMIRR|XX3(59,2), P_GER4_MASK,\tPOWER10, 0,\t{ACC, XA6a, XB6a, XMSK, YMSK, PMSK4}},\n {\"pmdmxvi8ger4\", PMMIRR|XX3(59,3), P_GER4_MASK,\tPOWER10, 0,\t{ACC, XA6a, XB6a, XMSK, YMSK, PMSK4}},\n {\"pmxvi8ger4\",\t PMMIRR|XX3(59,3), P_GER4_MASK,\tPOWER10, 0,\t{ACC, XA6a, XB6a, XMSK, YMSK, PMSK4}},\n+{\"pmdmxvi8gerx4pp\",PMMIRR|XX3(59,10), P_GERX4_MASK,\tFUTURE, 0,\t{DMR, XA5p, XB6, XMSK8, YMSK, PMSK4}},\n+{\"pmdmxvi8gerx4\", PMMIRR|XX3(59,11), P_GERX4_MASK,\tFUTURE, 0,\t{DMR, XA5p, XB6, XMSK8, YMSK, PMSK4}},\n {\"pmdmxvf16ger2pp\",PMMIRR|XX3(59,18), P_GER2_MASK,\tPOWER10, 0,\t{ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}},\n {\"pmxvf16ger2pp\", PMMIRR|XX3(59,18), P_GER2_MASK,\tPOWER10, 0,\t{ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}},\n {\"pmdmxvf16ger2\", PMMIRR|XX3(59,19), P_GER2_MASK,\tPOWER10, 0,\t{ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}},\n@@ -9785,32 +9811,43 @@ const struct powerpc_opcode prefix_opcodes[] = {\n {\"pmxvf64gerpp\", PMMIRR|XX3(59,58), P_GER64_MASK,\tPOWER10, 0,\t{ACC, XA6ap, XB6a, XMSK, YMSK2}},\n {\"pmdmxvf64ger\", PMMIRR|XX3(59,59), P_GER64_MASK,\tPOWER10, 0,\t{ACC, XA6ap, XB6a, XMSK, YMSK2}},\n {\"pmxvf64ger\",\t PMMIRR|XX3(59,59), P_GER64_MASK,\tPOWER10, 0,\t{ACC, XA6ap, XB6a, XMSK, YMSK2}},\n+{\"pmdmxvf16gerx2pp\",PMMIRR|XX3(59,66), P_GERX2_MASK,\tFUTURE, 0,\t{DMR, XA5p, XB6, XMSK8, YMSK, PMSK2}},\n+{\"pmdmxvf16gerx2\",PMMIRR|XX3(59,67), P_GERX2_MASK,\tFUTURE, 0,\t{DMR, XA5p, XB6, XMSK8, YMSK, PMSK2}},\n+{\"pmdmxvbf16gerx2pp\",PMMIRR|XX3(59,74),P_GERX2_MASK,\tFUTURE, 0,\t{DMR, XA5p, XB6, XMSK8, YMSK, PMSK2}},\n {\"pmdmxvi16ger2\", PMMIRR|XX3(59,75), P_GER2_MASK,\tPOWER10, 0,\t{ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}},\n {\"pmxvi16ger2\", PMMIRR|XX3(59,75), P_GER2_MASK,\tPOWER10, 0,\t{ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}},\n {\"pmdmxvf16ger2np\",PMMIRR|XX3(59,82), P_GER2_MASK,\tPOWER10, 0,\t{ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}},\n {\"pmxvf16ger2np\", PMMIRR|XX3(59,82), P_GER2_MASK,\tPOWER10, 0,\t{ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}},\n+{\"pmdmxvf16gerx2np\",PMMIRR|XX3(59,83), P_GERX2_MASK,\tFUTURE, 0,\t{DMR, XA5p, XB6, XMSK8, YMSK, PMSK2}},\n {\"pmdmxvf32gernp\",PMMIRR|XX3(59,90), P_GER_MASK,\tPOWER10, 0,\t{ACC, XA6a, XB6a, XMSK, YMSK}},\n {\"pmxvf32gernp\", PMMIRR|XX3(59,90), P_GER_MASK,\tPOWER10, 0,\t{ACC, XA6a, XB6a, XMSK, YMSK}},\n+{\"pmdmxvbf16gerx2\",PMMIRR|XX3(59,91), P_GERX2_MASK,\tFUTURE, 0,\t{DMR, XA5p, XB6, XMSK8, YMSK, PMSK2}},\n+{\"pmdmxvi8gerx4spp\",PMMIRR|XX3(59,98), P_GERX4_MASK,\tFUTURE, 0,\t{DMR, XA5p, XB6, XMSK8, YMSK, PMSK4}},\n {\"pmdmxvi8ger4spp\",PMMIRR|XX3(59,99), P_GER4_MASK,\tPOWER10, 0,\t{ACC, XA6a, XB6a, XMSK, YMSK, PMSK4}},\n {\"pmxvi8ger4spp\", PMMIRR|XX3(59,99), P_GER4_MASK,\tPOWER10, 0,\t{ACC, XA6a, XB6a, XMSK, YMSK, PMSK4}},\n {\"pmdmxvi16ger2pp\",PMMIRR|XX3(59,107), P_GER2_MASK,\tPOWER10, 0,\t{ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}},\n {\"pmxvi16ger2pp\", PMMIRR|XX3(59,107), P_GER2_MASK,\tPOWER10, 0,\t{ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}},\n {\"pmdmxvbf16ger2np\",PMMIRR|XX3(59,114),P_GER2_MASK,\tPOWER10, 0,\t{ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}},\n {\"pmxvbf16ger2np\",PMMIRR|XX3(59,114), P_GER2_MASK,\tPOWER10, 0,\t{ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}},\n+{\"pmdmxvbf16gerx2np\",PMMIRR|XX3(59,115),P_GERX2_MASK,\tFUTURE, 0,\t{DMR, XA5p, XB6, XMSK8, YMSK, PMSK2}},\n {\"pmdmxvf64gernp\",PMMIRR|XX3(59,122), P_GER64_MASK,\tPOWER10, 0,\t{ACC, XA6ap, XB6a, XMSK, YMSK2}},\n {\"pmxvf64gernp\", PMMIRR|XX3(59,122), P_GER64_MASK,\tPOWER10, 0,\t{ACC, XA6ap, XB6a, XMSK, YMSK2}},\n {\"pmdmxvf16ger2pn\",PMMIRR|XX3(59,146), P_GER2_MASK,\tPOWER10, 0,\t{ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}},\n {\"pmxvf16ger2pn\", PMMIRR|XX3(59,146), P_GER2_MASK,\tPOWER10, 0,\t{ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}},\n+{\"pmdmxvf16gerx2pn\",PMMIRR|XX3(59,147),P_GERX2_MASK,\tFUTURE, 0,\t{DMR, XA5p, XB6, XMSK8, YMSK, PMSK2}},\n {\"pmdmxvf32gerpn\",PMMIRR|XX3(59,154), P_GER_MASK,\tPOWER10, 0,\t{ACC, XA6a, XB6a, XMSK, YMSK}},\n {\"pmxvf32gerpn\", PMMIRR|XX3(59,154), P_GER_MASK,\tPOWER10, 0,\t{ACC, XA6a, XB6a, XMSK, YMSK}},\n {\"pmdmxvbf16ger2pn\",PMMIRR|XX3(59,178),P_GER2_MASK,\tPOWER10, 0,\t{ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}},\n {\"pmxvbf16ger2pn\",PMMIRR|XX3(59,178), P_GER2_MASK,\tPOWER10, 0,\t{ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}},\n+{\"pmdmxvbf16gerx2pn\",PMMIRR|XX3(59,179),P_GERX2_MASK,\tFUTURE, 0,\t{DMR, XA5p, XB6, XMSK8, YMSK, PMSK2}},\n {\"pmdmxvf64gerpn\",PMMIRR|XX3(59,186), P_GER64_MASK,\tPOWER10, 0,\t{ACC, XA6ap, XB6a, XMSK, YMSK2}},\n {\"pmxvf64gerpn\", PMMIRR|XX3(59,186), P_GER64_MASK,\tPOWER10, 0,\t{ACC, XA6ap, XB6a, XMSK, YMSK2}},\n+{\"pmdmxvf16gerx2nn\",PMMIRR|XX3(59,202),P_GERX2_MASK,\tFUTURE, 0,\t{DMR, XA5p, XB6, XMSK8, YMSK, PMSK2}},\n {\"pmdmxvf16ger2nn\",PMMIRR|XX3(59,210), P_GER2_MASK,\tPOWER10, 0,\t{ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}},\n {\"pmxvf16ger2nn\", PMMIRR|XX3(59,210), P_GER2_MASK,\tPOWER10, 0,\t{ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}},\n {\"pmdmxvf32gernn\",PMMIRR|XX3(59,218), P_GER_MASK,\tPOWER10, 0,\t{ACC, XA6a, XB6a, XMSK, YMSK}},\n {\"pmxvf32gernn\", PMMIRR|XX3(59,218), P_GER_MASK,\tPOWER10, 0,\t{ACC, XA6a, XB6a, XMSK, YMSK}},\n+{\"pmdmxvbf16gerx2nn\",PMMIRR|XX3(59,234),P_GERX2_MASK,\tFUTURE, 0,\t{DMR, XA5p, XB6, XMSK8, YMSK, PM 100 29180 100 29030 100 150 515k 2727 --:--:-- --:--:-- --:--:-- 518k SK2}},\n {\"pmdmxvbf16ger2nn\",PMMIRR|XX3(59,242),P_GER2_MASK,\tPOWER10, 0,\t{ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}},\n {\"pmxvbf16ger2nn\",PMMIRR|XX3(59,242), P_GER2_MASK,\tPOWER10, 0,\t{ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}},\n {\"pmdmxvf64gernn\",PMMIRR|XX3(59,250), P_GER64_MASK,\tPOWER10, 0,\t{ACC, XA6ap, XB6a, XMSK, YMSK2}},\n","prefixes":["COMMITTED"]}+ exit 1 Build step 'Execute shell' marked build as failure Finished: FAILURE