Started by user snail Running as SYSTEM [EnvInject] - Loading node environment variables. Building remotely on docker-jenkins-agent in workspace /home/jenkins/agent/workspace/binutils-gdb [WS-CLEANUP] Deleting project workspace... [WS-CLEANUP] Deferred wipeout is used... [WS-CLEANUP] Done The recommended git tool is: NONE using credential 0adb5fc7-caa2-429d-97d2-c7fa2fa1d884 Cloning the remote Git repository Using shallow clone with depth 1 Avoid fetching tags Cloning repository git@github.com:wangliu-iscas/binutils-gdb.git/ > git init /home/jenkins/agent/workspace/binutils-gdb # timeout=10 Fetching upstream changes from git@github.com:wangliu-iscas/binutils-gdb.git/ > git --version # timeout=10 > git --version # 'git version 2.37.2' using GIT_SSH to set credentials patchwork github wangliu-iscas git ssh key Verifying host key using known hosts file, will automatically accept unseen keys > git fetch --no-tags --force --progress --depth=1 -- git@github.com:wangliu-iscas/binutils-gdb.git/ +refs/heads/*:refs/remotes/origin/* # timeout=10 > git config remote.origin.url git@github.com:wangliu-iscas/binutils-gdb.git/ # timeout=10 > git config --add remote.origin.fetch +refs/heads/*:refs/remotes/origin/* # timeout=10 Avoid second fetch > git rev-parse refs/remotes/origin/master^{commit} # timeout=10 Checking out Revision a09f33be653fb112586be126f3d5ab848aaed095 (refs/remotes/origin/master) > git config core.sparsecheckout # timeout=10 > git checkout -f a09f33be653fb112586be126f3d5ab848aaed095 # timeout=10 Commit message: "sim/cgen: initialize variable at creation in engine_run_n" > git rev-list --no-walk a09f33be653fb112586be126f3d5ab848aaed095 # timeout=10 [EnvInject] - Mask passwords that will be passed as build parameters. [EnvInject] - Executing scripts and injecting environment variables after the SCM step. [EnvInject] - Injecting as environment variables the properties content GITHUB_REPO=https://github.com/wangliu-iscas/ PATCHWORK_URL=https://patchwork.plctlab.org [EnvInject] - Variables injected successfully. [binutils-gdb] $ /usr/bin/env bash /tmp/jenkins5253060785112703983.sh + git config pw.server https://patchwork.plctlab.org/api/1.2/ + git config pw.project binutils-gdb + git config pw.token [*******] ++ date +%Y-%m + now_date=2022-10 ++ date +%Y + now_date_year=2022 + bundle_name=binutils-gdb_2022-10 ++ curl -s -H 'Authorization: Token [*******]' 'https://patchwork.plctlab.org/api/1.2/bundles/?project=binutils-gdb&per_page=999' + bundle_response='[{"id":6,"url":"https://patchwork.plctlab.org/api/1.2/bundles/6/","web_url":"https://patchwork.plctlab.org/bundle/patchwork-bot/binutils-gdb_2022-10/","project":{"id":2,"url":"https://patchwork.plctlab.org/api/1.2/projects/2/","name":"binutils-gdb","link_name":"binutils-gdb","list_id":"binutils.sourceware.org","list_email":"binutils@sourceware.org","web_url":"https://sourceware.org/mailman/listinfo/binutils","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"name":"binutils-gdb_2022-10","owner":{"id":3,"url":"https://patchwork.plctlab.org/api/1.2/users/3/","username":"patchwork-bot","first_name":"","last_name":"","email":"ouuuleilei@gmail.com"},"patches":[{"id":1592,"url":"https://patchwork.plctlab.org/api/1.2/patches/1592/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/385d01fd-7e57-1f3f-1bae-30aa0c313d63@suse.com/","msgid":"<385d01fd-7e57-1f3f-1bae-30aa0c313d63@suse.com>","list_archive_url":null,"date":"2022-09-30T11:59:45","name":"[3/4] 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arm","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/619f112539c0bdecd58e25664f1250a3479a37f5.1664707612.git.aburgess@redhat.com/mbox/"},{"id":1635,"url":"https://patchwork.plctlab.org/api/1.2/patches/1635/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221002185433.gl7dvytfh5wthifx@lug-owl.de/","msgid":"<20221002185433.gl7dvytfh5wthifx@lug-owl.de>","list_archive_url":null,"date":"2022-10-02T18:54:33","name":"diagnostics.h: GCC 13 got -Wself-move, breaks GDB build","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221002185433.gl7dvytfh5wthifx@lug-owl.de/mbox/"},{"id":1637,"url":"https://patchwork.plctlab.org/api/1.2/patches/1637/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003014313.28766-1-mark@harmstone.com/","msgid":"<20221003014313.28766-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-03T01:43:12","name":"[1/2] ld: Add --pdb option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003014313.28766-1-mark@harmstone.com/mbox/"},{"id":1638,"url":"https://patchwork.plctlab.org/api/1.2/patches/1638/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003014313.28766-2-mark@harmstone.com/","msgid":"<20221003014313.28766-2-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-03T01:43:13","name":"[2/2] ld: Add minimal pdb generation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003014313.28766-2-mark@harmstone.com/mbox/"},{"id":1640,"url":"https://patchwork.plctlab.org/api/1.2/patches/1640/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/597ed978-d121-220c-b56b-2ffb94bd091c@suse.cz/","msgid":"<597ed978-d121-220c-b56b-2ffb94bd091c@suse.cz>","list_archive_url":null,"date":"2022-10-03T07:50:38","name":"[1/2] refactor usage of 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1620 gold: add --compress-debug-sections=zstd [PR 29641] | | | 1623 [RFC,1/1] RISC-V: Implement common register pair framework | | | 1625 [RFC,1/1] RISC-V: Implement extension variants | | | 1626 [1/1] RISC-V: Move supervisor instructions after all unprivileged ones | | | 1627 readelf: support zstd compressed debug sections [PR 29640] | | | 1631 [PATCHv2,2/2] opcodes/arm: add disassembler styling for arm | | | 1635 diagnostics.h: GCC 13 got -Wself-move, breaks GDB build | | | 1637 [1/2] ld: Add --pdb option | | | 1638 [2/2] ld: Add minimal pdb generation | | | 1640 [1/2] refactor usage of compressed_debug_section_type | | | 1641 [2/2] add --enable-default-compressed-debug-sections-algorithm configure option | | | 1642 opcodes/riscv: style csr names as registers | | | 1643 [v3,1/6] RISC-V: Fix immediates to have "immediate" style | | | 1644 [v3,2/6] RISC-V: Fix printf argument types corresponding %x | | | 1647 [v3,3/6] RISC-V: Optimize riscv_disassemble_data printf | | | 1646 [v3,4/6] RISC-V: Print comma and tabs as the "text" style | | | 1648 [v3,5/6] RISC-V: Fix T-Head immediate types on printing | | | 1649 [v3,6/6] RISC-V: Print XTheadMemPair literal as "immediate" | | | 1656 Commit: readelf: Do not load section data from offset 0 | | | 1659 [PATCHv2,1/2] opcodes/arm: use '@' consistently for the comment character | | | 1660 gas: NEWS: Mention the T-Head extensions that were recently added | | | 1671 Support objcopy changing compression to or from zstd | | | 1673 [1/2] RISC-V: Fix buffer overflow on print_insn_riscv | | | 1672 [2/2] gdb/riscv: Fix buffer overflow on riscv_insn::fetch_instruction | | | 1676 [v2,1/2] RISC-V: Fix buffer overflow on print_insn_riscv | | | 1677 [v2,2/2] gdb/riscv: Partial support for instructions up to 176-bits | | | 1678 [v3,1/2] RISC-V: Fix buffer overflow on print_insn_riscv | | | 1679 [v3,2/2] gdb/riscv: Partial support for instructions up to 176-bit | | | 1681 RISC-V: Zicbo{m,p,z} adjustments to riscv_multi_subset_supports_ext() | | | 1690 gprofng: fix build with --enable-pgo-build=lto | | | 1691 bfd: xtensa: fix __stop_SECTION literal drop, | | | 1702 [RFC] bfd: use bfd_vma for the 64-bit version of put[lb] and get[lb] | | | 1711 PR29647, objdump -S looping | | | 1712 [v3,1/7] x86: constify parse_insn()'s input | | | 1713 [v3,2/7] x86: introduce Pass2 insn attribute | | | 1714 [v3,3/7] x86: re-work insn/suffix recognition | | | 1715 [v3,4/7] x86-64: further re-work insn/suffix recognition to also cover MOVSL | | | 1716 [v3,5/7] ix86: don't recognize/derive Q suffix in the common case | | | 1718 [v3,6/7] x86-64: allow HLE store of accumulator to absolute 32-bit address | | | 1717 [v3,7/7] x86: move bad-use-of-TLS-reloc check | | | 1719 x86: drop "regmask" static variable | | | 1751 [v2,1/2] RISC-V: Fallback for instructions longer than 64b | | | 1752 [v2,2/2] RISC-V: Improve "bits undefined" diagnostics | | | 1776 [v3,1/2] RISC-V: Fallback for instructions longer than 64b | | | 1777 [v3,2/2] RISC-V: Improve "bits undefined" diagnostics | | | 1781 RISC-V: fix linker message when relaxation deletes bytes | | | 1801 PR29653, objcopy/strip: fuzzed small input file induces large output file | | | 1803 @CPP_FOR_BUILD@ problem since binutils-2.38 | | | 1827 [v2,1/1] RISC-V: Test DWARF register numbers for "fp" | | | 1828 [1/1] RISC-V: Move standard hints before all instructions | | | 1829 [RFC,1/1] RISC-V: Imply 'Zicsr' from privileged extensions with CSRs | | | 1830 [1/5] opcodes/riscv-dis.c: Tidying with comments/clarity | | | 1832 [2/5] opcodes/riscv-dis.c: Tidying with spacing | | | 1831 [3/5] opcodes/riscv-dis.c: Use bool type whenever possible | | | 1833 [4/5] opcodes/riscv-dis.c: Make XLEN variable static | | | 1834 [5/5] opcodes/riscv-dis.c: Remove last_map_state | | | 1836 RISC-V: Move certain arrays to riscv-opc.c | | | 1844 [v2,1/2] ld: Add --pdb option | | | 1845 [v2,2/2] ld: Add minimal pdb generation | | | 1890 gprofng: run tests without installation | | | 1893 [2/2] gprofng: use the --libdir path to find libraries | | | 1894 [3/3] gprofng: no need to build version.texi | | | 1895 [v3,1/2] ld: Add --pdb option | | | 1897 [v3,2/2] ld: Add minimal pdb generation | | | 1928 [v4,1/2] ld: Add --pdb option | | | 1929 [v4,2/2] ld: Add minimal pdb generation | | | 1941 [pushed] Re-apply "Pass PKG_CONFIG_PATH down from top-level Makefile" | | | 1976 [v4,1/8] x86: constify parse_insn()'s input | | | 1977 [v4,2/8] x86: introduce Pass2 insn attribute | | | 1978 [v4,3/8] x86: re-work insn/suffix recognition | | | 1979 [v4,4/8] x86-64: further re-work insn/suffix recognition to also cover MOVSL | | | 1980 [v4,5/8] ix86: don't recognize/derive Q suffix in the common case | | | 1981 [v4,6/8] x86-64: allow HLE store of accumulator to absolute 32-bit address | | | 1982 [v4,7/8] x86: move bad-use-of-TLS-reloc check | | | 1983 [v4,8/8] x86: drop (now) stray IsString | | | 2013 include: Declare getopt function on old GNU libc | | | 2352 ld: Add --undefined-version | | | 2532 [1/1] RISC-V: Make R_RISCV_SUB6 conforms to riscv abi standard | | | 2560 [v3] aarch64-pe support for LD, GAS and BFD | | | 2602 [01/10] Support Intel AVX-IFMA | | | 2608 [02/10] Support Intel AVX-VNNI-INT8 | | | 2611 [03/10] Support Intel AVX-NE-CONVERT | | | 2610 [04/10] Support Intel CMPccXADD | | | 2601 [05/10] Add handler for more i386_cpu_flags | | | 2606 [06/10] Support Intel RAO-INT | | | 2609 [07/10] Support Intel WRMSRNS | | | 2605 [08/10] Support Intel MSRLIST | | | 2607 [09/10] Support Intel AMX-FP16 | | | 2604 [10/10] Support Intel PREFETCHI | | | 2643 x86: fold AVX512-VNNI disassembler entries with AVX-VNNI ones | | | 2654 PR29677, Field `the_bfd` of `asymbol` is uninitialised | | | 2656 e200 LSP support | | | 2657 PowerPC SPE disassembly and tests | | | 2695 Binutils: Adding new testcase for addr2line. | | | 2700 x86: properly decode EVEX.W for AVX512_4{FMAPS,VNNIW} insns | | | 2981 PowerPC se_rfmci and VLE, SPE2 and LSP insns with -many | | | 3152 [v5,1/2] ld: Add --pdb option | | | 3151 [v5,2/2] ld: Add minimal pdb generation | | | 3258 x86: correct CPU_AMX_{BF16,INT8}_FLAGS | | | 3272 x86: generalize gas documentation for disabling of ISA extensions | | | 3759 [V2,01/15] sframe.h: Add SFrame format definition | | | 3762 [V2,02/15] gas: add new command line option --gsframe | | | 3761 [V2,03/15] gas: generate .sframe from CFI directives | | | 3760 [V2,04/15] gas: testsuite: add new tests for SFrame unwind info | | | 3764 [V2,05/15] libsframe: add the SFrame library | | | 3766 [V2,06/15] bfd: linker: merge .sframe sections | | | 3763 [V2,07/15] readelf/objdump: support for SFrame section | | | 3765 [V2,08/15] unwinder: generate backtrace using SFrame format | | | 3770 [V2,09/15] unwinder: Add SFrame unwinder tests | | | 3769 [V2,10/15] gdb: sim: buildsystem changes to accommodate libsframe | | | 3771 [V2,11/15] libctf: add libsframe to LDFLAGS and LIBS | | | 3768 [V2,12/15] src-release.sh: Add libsframe | | | 3767 [V2,13/15] binutils/NEWS: add text for SFrame support | | | 3772 [V2,14/15] gas/NEWS: add text about new command line option and SFrame support | | | 3773 [V2,15/15] doc: add SFrame spec file | | | 3999 [1/1] IBM zSystems: Issue error for *DBL relocs on misaligned symbols | | | 4141 xtensa: use definitions from xtensa-config.h | | | 4272 x86: Disable AVX-VNNI when disabling AVX2 | | | 4998 x86: re-work AVX-VNNI support | | | 5276 Fix addr2line test for ppc64 elfv1 and mingw | | | 5424 binutils: Remove unused substitution PROGRAM | | | 5433 [v2,1/8] RISC-V: Add a space at the end of pinfo | | | 5435 [v2,2/8] RISC-V: Fix obvious misalignments ('Zbb'/'Zba') | | | 5437 [v2,3/8] RISC-V: Remove spaces in opcode entries | | | 5436 [v2,4/8] RISC-V: Remove unused instruction macros | | | 5440 [v2,5/8] RISC-V: Complete tidying up with SCALL and SBREAK | | | 5442 [v2,6/8] RISC-V: Tidying up with fmv.w.x and fmv.x.w | | | 5438 [v2,7/8] RISC-V: Make alias instructions aliases | | | 5441 [v2,8/8] RISC-V: Use defined mask and match values | | | 5439 RISC-V: Remove RV32EF conflict | | | 5616 [04/10] Support Intel CMPccXADD | | | 5614 [05/10] Add handler for more i386_cpu_flags | | | 5672 [01/10] Support Intel AVX-IFMA | | | 5691 [02/10] Support Intel AVX-VNNI-INT8 | | | 5690 [03/10] Support Intel AVX-NE-CONVERT | | | 5689 [04/10] Support Intel CMPccXADD | | | 5676 [05/10] Add handler for more i386_cpu_flags | | | 5677 [06/10] Support Intel RAO-INT | | | 5681 [07/10] Support Intel WRMSRNS | | | 5682 [08/10] Support Intel MSRLIST | | | 5673 [09/10] Support Intel AMX-FP16 | | | 5686 [10/10] Support Intel PREFETCHI | | | 11921 [1/2] ld: Add section header stream to PDB files | | | 11922 [2/2] ld: Add publics stream to PDB files | | | 11965 [1/2] gas: NEWS: Add a missing newline | | | 11966 [2/2] gas: NEWS: Note support for RISC-V Zawrs | | | 12016 [COMMITTED] PowerPC: Add support for RFC02653 - Dense Math Facility | +------------+--------------------------------------------------------------------------------------+ + git config pull.rebase false + git fetch origin master From github.com:wangliu-iscas/binutils-gdb * branch master -> FETCH_HEAD + git checkout master Switched to a new branch 'master' branch 'master' set up to track 'origin/master'. + git pull origin master From github.com:wangliu-iscas/binutils-gdb * branch master -> FETCH_HEAD Already up to date. + git fetch origin upstream-master From github.com:wangliu-iscas/binutils-gdb * branch upstream-master -> FETCH_HEAD + git checkout upstream-master Switched to a new branch 'upstream-master' branch 'upstream-master' set up to track 'origin/upstream-master'. + git remote add upstream https://sourceware.org/git/binutils-gdb.git + git pull upstream master From https://sourceware.org/git/binutils-gdb * branch master -> FETCH_HEAD * [new branch] master -> upstream/master Updating a09f33be..bb98553c Fast-forward bfd/version.h | 2 +- gas/config/tc-ppc.c | 16 ++- gas/testsuite/gas/ppc/outerprod.d | 215 ++++++++++++++++++++++---------- gas/testsuite/gas/ppc/outerprod.s | 61 +++++++++ gas/testsuite/gas/ppc/ppc.exp | 2 + gas/testsuite/gas/ppc/rfc02653.d | 27 ++++ gas/testsuite/gas/ppc/rfc02653.s | 18 +++ gas/testsuite/gas/ppc/rfc02658.d | 51 ++++++++ gas/testsuite/gas/ppc/rfc02658.s | 28 +++++ include/opcode/ppc.h | 33 ++--- opcodes/ppc-dis.c | 3 + opcodes/ppc-opc.c | 253 ++++++++++++++++++++++++++++++++++---- 12 files changed, 599 insertions(+), 110 deletions(-) create mode 100644 gas/testsuite/gas/ppc/rfc02653.d create mode 100644 gas/testsuite/gas/ppc/rfc02653.s create mode 100644 gas/testsuite/gas/ppc/rfc02658.d create mode 100644 gas/testsuite/gas/ppc/rfc02658.s + git push -u origin upstream-master To github.com:wangliu-iscas/binutils-gdb.git/ a09f33be..bb98553c upstream-master -> upstream-master branch 'upstream-master' set up to track 'origin/upstream-master'. + git checkout master Switched to branch 'master' Your branch is up to date with 'origin/master'. + git merge upstream-master Updating a09f33be..bb98553c Fast-forward bfd/version.h | 2 +- gas/config/tc-ppc.c | 16 ++- gas/testsuite/gas/ppc/outerprod.d | 215 ++++++++++++++++++++++---------- gas/testsuite/gas/ppc/outerprod.s | 61 +++++++++ gas/testsuite/gas/ppc/ppc.exp | 2 + gas/testsuite/gas/ppc/rfc02653.d | 27 ++++ gas/testsuite/gas/ppc/rfc02653.s | 18 +++ gas/testsuite/gas/ppc/rfc02658.d | 51 ++++++++ gas/testsuite/gas/ppc/rfc02658.s | 28 +++++ include/opcode/ppc.h | 33 ++--- opcodes/ppc-dis.c | 3 + opcodes/ppc-opc.c | 253 ++++++++++++++++++++++++++++++++++---- 12 files changed, 599 insertions(+), 110 deletions(-) create mode 100644 gas/testsuite/gas/ppc/rfc02653.d create mode 100644 gas/testsuite/gas/ppc/rfc02653.s create mode 100644 gas/testsuite/gas/ppc/rfc02658.d create mode 100644 gas/testsuite/gas/ppc/rfc02658.s + git push -u origin master To github.com:wangliu-iscas/binutils-gdb.git/ a09f33be..bb98553c master -> master branch 'master' set up to track 'origin/master'. + branchname=series4474-patch12016 ++ git branch -a ++ grep 'series4474-patch12016$' + checkbranch= + checkbranchresult=null + '[' null = series4474-patch12016 ']' + git checkout -b series4474-patch12016 Switched to a new branch 'series4474-patch12016' ++ curl https://patchwork.plctlab.org/api/1.2/series/4474/ % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 1419 100 1419 0 0 40542 0 --:--:-- --:--:-- --:--:-- 41735 + series_response='{"id":4474,"url":"https://patchwork.plctlab.org/api/1.2/series/4474/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/list/?series=4474","project":{"id":2,"url":"https://patchwork.plctlab.org/api/1.2/projects/2/","name":"binutils-gdb","link_name":"binutils-gdb","list_id":"binutils.sourceware.org","list_email":"binutils@sourceware.org","web_url":"https://sourceware.org/mailman/listinfo/binutils","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"name":"[COMMITTED] PowerPC: Add support for RFC02653 - Dense Math Facility","date":"2022-10-28T00:35:19","submitter":{"id":123,"url":"https://patchwork.plctlab.org/api/1.2/people/123/","name":"Peter Bergner","email":"bergner@linux.ibm.com"},"version":1,"total":1,"received_total":1,"received_all":true,"mbox":"https://patchwork.plctlab.org/series/4474/mbox/","cover_letter":null,"patches":[{"id":12016,"url":"https://patchwork.plctlab.org/api/1.2/patches/12016/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/21ec9a18-fa89-0828-f625-499680022ec7@linux.ibm.com/","msgid":"<21ec9a18-fa89-0828-f625-499680022ec7@linux.ibm.com>","list_archive_url":null,"date":"2022-10-28T00:35:19","name":"[COMMITTED] PowerPC: Add support for RFC02653 - Dense Math Facility","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/21ec9a18-fa89-0828-f625-499680022ec7@linux.ibm.com/mbox/"}]}' ++ jq '.patches[] | (.id|tostring) + "," + .mbox' ++ echo '{"id":4474,"url":"https://patchwork.plctlab.org/api/1.2/series/4474/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/list/?series=4474","project":{"id":2,"url":"https://patchwork.plctlab.org/api/1.2/projects/2/","name":"binutils-gdb","link_name":"binutils-gdb","list_id":"binutils.sourceware.org","list_email":"binutils@sourceware.org","web_url":"https://sourceware.org/mailman/listinfo/binutils","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"name":"[COMMITTED] PowerPC: Add support for RFC02653 - Dense Math Facility","date":"2022-10-28T00:35:19","submitter":{"id":123,"url":"https://patchwork.plctlab.org/api/1.2/people/123/","name":"Peter Bergner","email":"bergner@linux.ibm.com"},"version":1,"total":1,"received_total":1,"received_all":true,"mbox":"https://patchwork.plctlab.org/series/4474/mbox/","cover_letter":null,"patches":[{"id":12016,"url":"https://patchwork.plctlab.org/api/1.2/patches/12016/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/21ec9a18-fa89-0828-f625-499680022ec7@linux.ibm.com/","msgid":"<21ec9a18-fa89-0828-f625-499680022ec7@linux.ibm.com>","list_archive_url":null,"date":"2022-10-28T00:35:19","name":"[COMMITTED] PowerPC: Add support for RFC02653 - Dense Math Facility","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/21ec9a18-fa89-0828-f625-499680022ec7@linux.ibm.com/mbox/"}]}' + patchid_patchurl='"12016,https://patchwork.plctlab.org/project/binutils-gdb/patch/21ec9a18-fa89-0828-f625-499680022ec7@linux.ibm.com/mbox/"' + echo '"12016,https://patchwork.plctlab.org/project/binutils-gdb/patch/21ec9a18-fa89-0828-f625-499680022ec7@linux.ibm.com/mbox/"' + IFS=, + read -r series_patch_id series_patch_url ++ echo '"12016' ++ sed 's/"//g' + series_patch_id=12016 ++ sed 's/"//g' ++ echo 'https://patchwork.plctlab.org/project/binutils-gdb/patch/21ec9a18-fa89-0828-f625-499680022ec7@linux.ibm.com/mbox/"' + series_patch_url=https://patchwork.plctlab.org/project/binutils-gdb/patch/21ec9a18-fa89-0828-f625-499680022ec7@linux.ibm.com/mbox/ ++ git rev-parse HEAD + commitid_before=bb98553cad4e017f1851153fa5de91f2cee98fb2 + eval '+++ declare -p bout bret declare -- bout="Applying: PowerPC: Add support for RFC02653 - Dense Math Facility .git/rebase-apply/patch:74: trailing whitespace. .*: (ed 1b d1 1e|1e d1 1b ed) .git/rebase-apply/patch:76: trailing whitespace. .*: (ed 99 c1 16|16 c1 99 ed) .git/rebase-apply/patch:90: trailing whitespace. .*: (ef 13 90 1e|1e 90 13 ef) .git/rebase-apply/patch:92: trailing whitespace. .*: (ef 91 80 16|16 80 91 ef) .git/rebase-apply/patch:106: trailing whitespace. .*: (ed 0b 51 5e|5e 51 0b ed) warning: squelched 24 whitespace errors warning: 29 lines add whitespace errors. Using index info to reconstruct a base tree... M gas/config/tc-ppc.c M gas/testsuite/gas/ppc/outerprod.d M gas/testsuite/gas/ppc/outerprod.s M gas/testsuite/gas/ppc/ppc.exp M include/opcode/ppc.h M opcodes/ppc-dis.c M opcodes/ppc-opc.c Falling back to patching base and 3-way merge... Auto-merging opcodes/ppc-opc.c CONFLICT (content): Merge conflict in opcodes/ppc-opc.c Auto-merging gas/testsuite/gas/ppc/ppc.exp CONFLICT (content): Merge conflict in gas/testsuite/gas/ppc/ppc.exp Auto-merging gas/config/tc-ppc.c error: Failed to merge in the changes. hint: Use '\''git am --show-current-patch=diff'\'' to see the failed patch Patch failed at 0001 PowerPC: Add support for RFC02653 - Dense Math Facility When you have resolved this problem, run \"git am --continue\". If you prefer to skip this patch, run \"git am --skip\" instead. To restore the original branch and stop patching, run \"git am --abort\"." declare -- bret="128" ++ berr='\''++++ git_am https://patchwork.plctlab.org/project/binutils-gdb/patch/21ec9a18-fa89-0828-f625-499680022ec7@linux.ibm.com/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/binutils-gdb/patch/21ec9a18-fa89-0828-f625-499680022ec7@linux.ibm.com/mbox/ ++++ curl https://patchwork.plctlab.org/project/binutils-gdb/patch/21ec9a18-fa89-0828-f625-499680022ec7@linux.ibm.com/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 63444 100 63444 0 0 1239k 0 --:--:-- --:--:-- --:--:-- 1239k +++ bout='\''\'\'''\''Applying: PowerPC: Add support for RFC02653 - Dense Math Facility .git/rebase-apply/patch:74: trailing whitespace. .*: (ed 1b d1 1e|1e d1 1b ed) .git/rebase-apply/patch:76: trailing whitespace. .*: (ed 99 c1 16|16 c1 99 ed) .git/rebase-apply/patch:90: trailing whitespace. .*: (ef 13 90 1e|1e 90 13 ef) .git/rebase-apply/patch:92: trailing whitespace. .*: (ef 91 80 16|16 80 91 ef) .git/rebase-apply/patch:106: trailing whitespace. .*: (ed 0b 51 5e|5e 51 0b ed) warning: squelched 24 whitespace errors warning: 29 lines add whitespace errors. Using index info to reconstruct a base tree... M gas/config/tc-ppc.c M gas/testsuite/gas/ppc/outerprod.d M gas/testsuite/gas/ppc/outerprod.s M gas/testsuite/gas/ppc/ppc.exp M include/opcode/ppc.h M opcodes/ppc-dis.c M opcodes/ppc-opc.c Falling back to patching base and 3-way merge... Auto-merging opcodes/ppc-opc.c CONFLICT (content): Merge conflict in opcodes/ppc-opc.c Auto-merging gas/testsuite/gas/ppc/ppc.exp CONFLICT (content): Merge conflict in gas/testsuite/gas/ppc/ppc.exp Auto-merging gas/config/tc-ppc.c error: Failed to merge in the changes. hint: Use '\''\'\'''\''\'\''\'\'''\'''\''\'\'''\''git am --show-current-patch=diff'\''\'\'''\''\'\''\'\'''\'''\''\'\'''\'' to see the failed patch Patch failed at 0001 PowerPC: Add support for RFC02653 - Dense Math Facility When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort".'\''\'\'''\'' +++ bret=128'\'' ++ declare -p berr declare -- berr="++++ git_am https://patchwork.plctlab.org/project/binutils-gdb/patch/21ec9a18-fa89-0828-f625-499680022ec7@linux.ibm.com/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/binutils-gdb/patch/21ec9a18-fa89-0828-f625-499680022ec7@linux.ibm.com/mbox/ ++++ curl https://patchwork.plctlab.org/project/binutils-gdb/patch/21ec9a18-fa89-0828-f625-499680022ec7@linux.ibm.com/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 63444 100 63444 0 0 1239k 0 --:--:-- --:--:-- --:--:-- 1239k +++ bout='\''Applying: PowerPC: Add support for RFC02653 - Dense Math Facility .git/rebase-apply/patch:74: trailing whitespace. .*: (ed 1b d1 1e|1e d1 1b ed) .git/rebase-apply/patch:76: trailing whitespace. .*: (ed 99 c1 16|16 c1 99 ed) .git/rebase-apply/patch:90: trailing whitespace. .*: (ef 13 90 1e|1e 90 13 ef) .git/rebase-apply/patch:92: trailing whitespace. .*: (ef 91 80 16|16 80 91 ef) .git/rebase-apply/patch:106: trailing whitespace. .*: (ed 0b 51 5e|5e 51 0b ed) warning: squelched 24 whitespace errors warning: 29 lines add whitespace errors. Using index info to reconstruct a base tree... M gas/config/tc-ppc.c M gas/testsuite/gas/ppc/outerprod.d M gas/testsuite/gas/ppc/outerprod.s M gas/testsuite/gas/ppc/ppc.exp M include/opcode/ppc.h M opcodes/ppc-dis.c M opcodes/ppc-opc.c Falling back to patching base and 3-way merge... Auto-merging opcodes/ppc-opc.c CONFLICT (content): Merge conflict in opcodes/ppc-opc.c Auto-merging gas/testsuite/gas/ppc/ppc.exp CONFLICT (content): Merge conflict in gas/testsuite/gas/ppc/ppc.exp Auto-merging gas/config/tc-ppc.c error: Failed to merge in the changes. hint: Use '\''\\'\'''\''git am --show-current-patch=diff'\''\\'\'''\'' to see the failed patch Patch failed at 0001 PowerPC: Add support for RFC02653 - Dense Math Facility When you have resolved this problem, run \"git am --continue\". If you prefer to skip this patch, run \"git am --skip\" instead. To restore the original branch and stop patching, run \"git am --abort\".'\'' +++ bret=128"' ++ +++ declare -p bout bret /tmp/jenkins5253060785112703983.sh: line 124: +++: command not found ++ declare -- 'bout=Applying: PowerPC: Add support for RFC02653 - Dense Math Facility .git/rebase-apply/patch:74: trailing whitespace. .*: (ed 1b d1 1e|1e d1 1b ed) .git/rebase-apply/patch:76: trailing whitespace. .*: (ed 99 c1 16|16 c1 99 ed) .git/rebase-apply/patch:90: trailing whitespace. .*: (ef 13 90 1e|1e 90 13 ef) .git/rebase-apply/patch:92: trailing whitespace. .*: (ef 91 80 16|16 80 91 ef) .git/rebase-apply/patch:106: trailing whitespace. .*: (ed 0b 51 5e|5e 51 0b ed) warning: squelched 24 whitespace errors warning: 29 lines add whitespace errors. Using index info to reconstruct a base tree... M gas/config/tc-ppc.c M gas/testsuite/gas/ppc/outerprod.d M gas/testsuite/gas/ppc/outerprod.s M gas/testsuite/gas/ppc/ppc.exp M include/opcode/ppc.h M opcodes/ppc-dis.c M opcodes/ppc-opc.c Falling back to patching base and 3-way merge... Auto-merging opcodes/ppc-opc.c CONFLICT (content): Merge conflict in opcodes/ppc-opc.c Auto-merging gas/testsuite/gas/ppc/ppc.exp CONFLICT (content): Merge conflict in gas/testsuite/gas/ppc/ppc.exp Auto-merging gas/config/tc-ppc.c error: Failed to merge in the changes. hint: Use '\''git am --show-current-patch=diff'\'' to see the failed patch Patch failed at 0001 PowerPC: Add support for RFC02653 - Dense Math Facility When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort".' ++ declare -- bret=128 ++ ++ 'berr=++++ git_am https://patchwork.plctlab.org/project/binutils-gdb/patch/21ec9a18-fa89-0828-f625-499680022ec7@linux.ibm.com/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/binutils-gdb/patch/21ec9a18-fa89-0828-f625-499680022ec7@linux.ibm.com/mbox/ ++++ curl https://patchwork.plctlab.org/project/binutils-gdb/patch/21ec9a18-fa89-0828-f625-499680022ec7@linux.ibm.com/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 63444 100 63444 0 0 1239k 0 --:--:-- --:--:-- --:--:-- 1239k +++ bout='\''Applying: PowerPC: Add support for RFC02653 - Dense Math Facility .git/rebase-apply/patch:74: trailing whitespace. .*: (ed 1b d1 1e|1e d1 1b ed) .git/rebase-apply/patch:76: trailing whitespace. .*: (ed 99 c1 16|16 c1 99 ed) .git/rebase-apply/patch:90: trailing whitespace. .*: (ef 13 90 1e|1e 90 13 ef) .git/rebase-apply/patch:92: trailing whitespace. .*: (ef 91 80 16|16 80 91 ef) .git/rebase-apply/patch:106: trailing whitespace. .*: (ed 0b 51 5e|5e 51 0b ed) warning: squelched 24 whitespace errors warning: 29 lines add whitespace errors. Using index info to reconstruct a base tree... M gas/config/tc-ppc.c M gas/testsuite/gas/ppc/outerprod.d M gas/testsuite/gas/ppc/outerprod.s M gas/testsuite/gas/ppc/ppc.exp M include/opcode/ppc.h M opcodes/ppc-dis.c M opcodes/ppc-opc.c Falling back to patching base and 3-way merge... Auto-merging opcodes/ppc-opc.c CONFLICT (content): Merge conflict in opcodes/ppc-opc.c Auto-merging gas/testsuite/gas/ppc/ppc.exp CONFLICT (content): Merge conflict in gas/testsuite/gas/ppc/ppc.exp Auto-merging gas/config/tc-ppc.c error: Failed to merge in the changes. hint: Use '\''\'\'''\''git am --show-current-patch=diff'\''\'\'''\'' to see the failed patch Patch failed at 0001 PowerPC: Add support for RFC02653 - Dense Math Facility When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort".'\'' +++ bret=128' /tmp/jenkins5253060785112703983.sh: line 199: ++: command not found ++ ++ declare -p berr /tmp/jenkins5253060785112703983.sh: line 200: ++: command not found ++ declare -- 'berr=++++ git_am https://patchwork.plctlab.org/project/binutils-gdb/patch/21ec9a18-fa89-0828-f625-499680022ec7@linux.ibm.com/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/binutils-gdb/patch/21ec9a18-fa89-0828-f625-499680022ec7@linux.ibm.com/mbox/ ++++ curl https://patchwork.plctlab.org/project/binutils-gdb/patch/21ec9a18-fa89-0828-f625-499680022ec7@linux.ibm.com/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 63444 100 63444 0 0 1239k 0 --:--:-- --:--:-- --:--:-- 1239k +++ bout='\''Applying: PowerPC: Add support for RFC02653 - Dense Math Facility .git/rebase-apply/patch:74: trailing whitespace. .*: (ed 1b d1 1e|1e d1 1b ed) .git/rebase-apply/patch:76: trailing whitespace. .*: (ed 99 c1 16|16 c1 99 ed) .git/rebase-apply/patch:90: trailing whitespace. .*: (ef 13 90 1e|1e 90 13 ef) .git/rebase-apply/patch:92: trailing whitespace. .*: (ef 91 80 16|16 80 91 ef) .git/rebase-apply/patch:106: trailing whitespace. .*: (ed 0b 51 5e|5e 51 0b ed) warning: squelched 24 whitespace errors warning: 29 lines add whitespace errors. Using index info to reconstruct a base tree... M gas/config/tc-ppc.c M gas/testsuite/gas/ppc/outerprod.d M gas/testsuite/gas/ppc/outerprod.s M gas/testsuite/gas/ppc/ppc.exp M include/opcode/ppc.h M opcodes/ppc-dis.c M opcodes/ppc-opc.c Falling back to patching base and 3-way merge... Auto-merging opcodes/ppc-opc.c CONFLICT (content): Merge conflict in opcodes/ppc-opc.c Auto-merging gas/testsuite/gas/ppc/ppc.exp CONFLICT (content): Merge conflict in gas/testsuite/gas/ppc/ppc.exp Auto-merging gas/config/tc-ppc.c error: Failed to merge in the changes. hint: Use '\''\'\'''\''git am --show-current-patch=diff'\''\'\'''\'' to see the failed patch Patch failed at 0001 PowerPC: Add support for RFC02653 - Dense Math Facility When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort".'\'' +++ bret=128' ++ git rev-parse HEAD + commitid_after=bb98553cad4e017f1851153fa5de91f2cee98fb2 + '[' 128 = 0 ']' + [[ ++++ git_am https://patchwork.plctlab.org/project/binutils-gdb/patch/21ec9a18-fa89-0828-f625-499680022ec7@linux.ibm.com/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/binutils-gdb/patch/21ec9a18-fa89-0828-f625-499680022ec7@linux.ibm.com/mbox/ ++++ curl https://patchwork.plctlab.org/project/binutils-gdb/patch/21ec9a18-fa89-0828-f625-499680022ec7@linux.ibm.com/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 63444 100 63444 0 0 1239k 0 --:--:-- --:--:-- --:--:-- 1239k +++ bout='Applying: PowerPC: Add support for RFC02653 - Dense Math Facility .git/rebase-apply/patch:74: trailing whitespace. .*: (ed 1b d1 1e|1e d1 1b ed) .git/rebase-apply/patch:76: trailing whitespace. .*: (ed 99 c1 16|16 c1 99 ed) .git/rebase-apply/patch:90: trailing whitespace. .*: (ef 13 90 1e|1e 90 13 ef) .git/rebase-apply/patch:92: trailing whitespace. .*: (ef 91 80 16|16 80 91 ef) .git/rebase-apply/patch:106: trailing whitespace. .*: (ed 0b 51 5e|5e 51 0b ed) warning: squelched 24 whitespace errors warning: 29 lines add whitespace errors. Using index info to reconstruct a base tree... M gas/config/tc-ppc.c M gas/testsuite/gas/ppc/outerprod.d M gas/testsuite/gas/ppc/outerprod.s M gas/testsuite/gas/ppc/ppc.exp M include/opcode/ppc.h M opcodes/ppc-dis.c M opcodes/ppc-opc.c Falling back to patching base and 3-way merge... Auto-merging opcodes/ppc-opc.c CONFLICT (content): Merge conflict in opcodes/ppc-opc.c Auto-merging gas/testsuite/gas/ppc/ppc.exp CONFLICT (content): Merge conflict in gas/testsuite/gas/ppc/ppc.exp Auto-merging gas/config/tc-ppc.c error: Failed to merge in the changes. hint: Use '\''git am --show-current-patch=diff'\'' to see the failed patch Patch failed at 0001 PowerPC: Add support for RFC02653 - Dense Math Facility When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort".' +++ bret=128 =~ sha1 information is lacking or useless ]] + [[ ++++ git_am https://patchwork.plctlab.org/project/binutils-gdb/patch/21ec9a18-fa89-0828-f625-499680022ec7@linux.ibm.com/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/binutils-gdb/patch/21ec9a18-fa89-0828-f625-499680022ec7@linux.ibm.com/mbox/ ++++ curl https://patchwork.plctlab.org/project/binutils-gdb/patch/21ec9a18-fa89-0828-f625-499680022ec7@linux.ibm.com/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 63444 100 63444 0 0 1239k 0 --:--:-- --:--:-- --:--:-- 1239k +++ bout='Applying: PowerPC: Add support for RFC02653 - Dense Math Facility .git/rebase-apply/patch:74: trailing whitespace. .*: (ed 1b d1 1e|1e d1 1b ed) .git/rebase-apply/patch:76: trailing whitespace. .*: (ed 99 c1 16|16 c1 99 ed) .git/rebase-apply/patch:90: trailing whitespace. .*: (ef 13 90 1e|1e 90 13 ef) .git/rebase-apply/patch:92: trailing whitespace. .*: (ef 91 80 16|16 80 91 ef) .git/rebase-apply/patch:106: trailing whitespace. .*: (ed 0b 51 5e|5e 51 0b ed) warning: squelched 24 whitespace errors warning: 29 lines add whitespace errors. Using index info to reconstruct a base tree... M gas/config/tc-ppc.c M gas/testsuite/gas/ppc/outerprod.d M gas/testsuite/gas/ppc/outerprod.s M gas/testsuite/gas/ppc/ppc.exp M include/opcode/ppc.h M opcodes/ppc-dis.c M opcodes/ppc-opc.c Falling back to patching base and 3-way merge... Auto-merging opcodes/ppc-opc.c CONFLICT (content): Merge conflict in opcodes/ppc-opc.c Auto-merging gas/testsuite/gas/ppc/ppc.exp CONFLICT (content): Merge conflict in gas/testsuite/gas/ppc/ppc.exp Auto-merging gas/config/tc-ppc.c error: Failed to merge in the changes. hint: Use '\''git am --show-current-patch=diff'\'' to see the failed patch Patch failed at 0001 PowerPC: Add support for RFC02653 - Dense Math Facility When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort".' +++ bret=128 =~ Failed to merge in the changes ]] + submit_check warning Unresolved https://patchwork.plctlab.org/jenkins/job/binutils-gdb/228/consoleText 'Git am fail log' + check_state=warning + patch_state=Unresolved + repo_url=https://patchwork.plctlab.org/jenkins/job/binutils-gdb/228/consoleText + DESCRIPTION='Git am fail log' + curl -X POST -H 'Authorization: Token [*******]' -F state=warning -F target_url=https://patchwork.plctlab.org/jenkins/job/binutils-gdb/228/consoleText -F context=binutils-gdb-check -F 'description=Git am fail log' https://patchwork.plctlab.org/api/patches/12016/checks/ % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 975 100 430 100 545 10750 13625 --:--:-- --:--:-- --:--:-- 24375 {"id":1462,"url":"https://patchwork.plctlab.org/api/patches/12016/checks/1462/","user":{"id":1,"url":"https://patchwork.plctlab.org/api/users/1/","username":"snail","first_name":"","last_name":"","email":"wangliu@iscas.ac.cn"},"date":"2022-10-28T01:15:41.905932","state":"warning","target_url":"https://patchwork.plctlab.org/jenkins/job/binutils-gdb/228/consoleText","context":"binutils-gdb-check","description":"Git am fail log"}+ curl -X PATCH -H 'Authorization: Token [*******]' -F state=Unresolved https://patchwork.plctlab.org/api/1.2/patches/12016/ % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0{"id":12016,"url":"https://patchwork.plctlab.org/api/1.2/patches/12016/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/21ec9a18-fa89-0828-f625-499680022ec7@linux.ibm.com/","project":{"id":2,"url":"https://patchwork.plctlab.org/api/1.2/projects/2/","name":"binutils-gdb","link_name":"binutils-gdb","list_id":"binutils.sourceware.org","list_email":"binutils@sourceware.org","web_url":"https://sourceware.org/mailman/listinfo/binutils","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<21ec9a18-fa89-0828-f625-499680022ec7@linux.ibm.com>","list_archive_url":null,"date":"2022-10-28T00:35:19","name":"[COMMITTED] PowerPC: Add support for RFC02653 - Dense Math Facility","commit_ref":null,"pull_url":null,"state":"unresolved","archived":false,"hash":"62e49b666d9acd8c45f2da9468f43ec9f0fa9346","submitter":{"id":123,"url":"https://patchwork.plctlab.org/api/1.2/people/123/","name":"Peter Bergner","email":"bergner@linux.ibm.com"},"delegate":null,"mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/21ec9a18-fa89-0828-f625-499680022ec7@linux.ibm.com/mbox/","series":[{"id":4474,"url":"https://patchwork.plctlab.org/api/1.2/series/4474/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/list/?series=4474","date":"2022-10-28T00:35:19","name":"[COMMITTED] PowerPC: Add support for RFC02653 - Dense Math Facility","version":1,"mbox":"https://patchwork.plctlab.org/series/4474/mbox/"}],"comments":"https://patchwork.plctlab.org/api/patches/12016/comments/","check":"warning","checks":"https://patchwork.plctlab.org/api/patches/12016/checks/","tags":{},"headers":{"Return-Path":"","Delivered-To":["ouuuleilei@gmail.com","binutils@sourceware.org"],"Received":["by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp535802wru;\n Thu, 27 Oct 2022 17:36:40 -0700 (PDT)","from sourceware.org (server2.sourceware.org. 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a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org;\n\ts=default; t=1666917399;\n\tbh=devLV3Mu3++OCb7hFMC+rDwYjOAGFiFSkmZDvkBokHc=;\n\th=Date:To:Subject:List-Id:List-Unsubscribe:List-Archive:List-Post:\n\t List-Help:List-Subscribe:From:Reply-To:From;\n\tb=tI1FYRD/euNPaOqrUL0d6K40Uy/MLb2ULxlIDGpv146UIEmseq8EypKBNjJVCxTZh\n\t EdmyHKs2165iMTGFQnJxYR1oGOE/yO9kZs0U8Kim0kCUoNpadaVTkfpX/mpsXqvcdU\n\t 8pQUBOL2Fn4EbTqQddPEulCwvBWr6QxTnBxUiLCw=","X-Original-To":"binutils@sourceware.org","DMARC-Filter":"OpenDMARC Filter v1.4.1 sourceware.org C02C83857C5A","Message-ID":"<21ec9a18-fa89-0828-f625-499680022ec7@linux.ibm.com>","Date":"Thu, 27 Oct 2022 19:35:19 -0500","MIME-Version":"1.0","User-Agent":"Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:102.0)\n Gecko/20100101 Thunderbird/102.4.0","Content-Language":"en-US","To":"Binutils ","Subject":"[COMMITTED] PowerPC: Add support for RFC02653 - Dense Math Facility","Content-Type":"text/plain; charset=UTF-8","Content-Transfer-Encoding":"7bit","X-TM-AS-GCONF":"00","X-Proofpoint-GUID":"Y_QfumxvpkoidtWSGeaAxCIWX76Pj-9n","X-Proofpoint-ORIG-GUID":"w5yutlB0l68825lYXvrFbpcqQ5_nOSnG","X-Proofpoint-Virus-Version":"vendor=baseguard\n engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.545,FMLib:17.11.122.1\n definitions=2022-10-27_07,2022-10-27_01,2022-06-22_01","X-Proofpoint-Spam-Details":"rule=outbound_notspam policy=outbound score=0\n lowpriorityscore=0\n suspectscore=0 mlxscore=0 clxscore=1015 malwarescore=0 impostorscore=0\n bulkscore=0 mlxlogscore=999 spamscore=0 adultscore=0 phishscore=0\n priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1\n engine=8.12.0-2210170000 definitions=main-2210280001","X-Spam-Status":"No, score=-10.9 required=5.0 tests=BAYES_00, DKIM_SIGNED,\n DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_MSPIKE_H2, SPF_HELO_NONE,\n SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6","X-Spam-Checker-Version":"SpamAssassin 3.4.6 (2021-04-09) on\n server2.sourceware.org","X-BeenThere":"binutils@sourceware.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"Binutils mailing list ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","From":"Peter Bergner via Binutils ","Reply-To":"Peter Bergner ","Errors-To":"binutils-bounces+ouuuleilei=gmail.com@sourceware.org","Sender":"\"Binutils\" ","X-getmail-retrieved-from-mailbox":"=?utf-8?q?INBOX?=","X-GMAIL-THRID":"=?utf-8?q?1747889579697717279?=","X-GMAIL-MSGID":"=?utf-8?q?1747889579697717279?="},"content":"The following patch adds support for Power RFC02653 which is an extension\nof the MMA support in power10. When or even if this will ever show up in\nhardware is not determined or guaranteed, therefore this is enabled using\nthe -mfuture gas option.\n\nPeter\n\n\nPowerPC: Add support for RFC02653 - Dense Math Facility\n\ngas/\n\t* config/tc-ppc.c (pre_defined_registers): Add dense math registers.\n\t(md_assemble): Check dmr specified in correct operand.\n\t* testsuite/gas/ppc/outerprod.s : Add new tests.\n\t* testsuite/gas/ppc/outerprod.d: Likewise.\n\t* testsuite/gas/ppc/rfc02653.s: New test.\n\t* testsuite/gas/ppc/rfc02653.d: Likewise.\n\t* testsuite/gas/ppc/ppc.exp: Run it.\n\ninclude/\n\t* opcode/ppc.h (PPC_OPERAND_DMR): Define. Renumber following\n\tPPC_OPERAND defines.\n\nopcodes/\n\t* ppc-dis.c (print_insn_powerpc): Prepend 'dm' when printing DMR regs.\n\t* ppc-opc.c (insert_p2, (extract_p2, (insert_xa5, (extract_xa5,\n\tinsert_xb5, (extract_xb5): New functions.\n\t(insert_xa6a, extract_xa6a, insert_xb6a, extract_xb6a): Disallow\n\toperand overlap only on Power10.\n\t(DMR, DMRAB, P1, P2, XA5p, XB5p, XDMR_MASK, XDMRDMR_MASK, XX2ACC_MASK,\n\tXX2DMR_MASK, XX3DMR_MASK): New defines.\n\t(powerpc_opcodes): Add dmmr, dmsetaccz, dmsetdmrz, dmxor, dmxvbf16ger2,\n\tdmxvbf16ger2nn, dmxvbf16ger2np, dmxvbf16ger2pn, dmxvbf16ger2pp,\n\tdmxvf16ger2, dmxvf16ger2nn, dmxvf16ger2np, dmxvf16ger2pn, dmxvf16ger2pp,\n\tdmxvf32ger, dmxvf32gernn, dmxvf32gernp, dmxvf32gerpn, dmxvf32gerpp,\n\tdmxvf64ger, dmxvf64gernn, dmxvf64gernp, dmxvf64gerpn, dmxvf64gerpp,\n\tdmxvi16ger2, dmxvi16ger2pp, dmxvi16ger2s, dmxvi16ger2spp, dmxvi4ger8,\n\tdmxvi4ger8pp, dmxvi8ger4, dmxvi8ger4pp, dmxvi8ger4spp, dmxxextfdmr256,\n\tdmxxextfdmr512, dmxxinstdmr256, dmxxinstdmr512, dmxxmfacc, dmxxmtacc,\n\tpmdmxvbf16ger2, pmdmxvbf16ger2nn, pmdmxvbf16ger2np, pmdmxvbf16ger2pn,\n\tpmdmxvbf16ger2pp, pmdmxvf16ger2, pmdmxvf16ger2nn, pmdmxvf16ger2np,\n\tpmdmxvf16ger2pn, pmdmxvf16ger2pp, pmdmxvf32ger, pmdmxvf32gernn,\n\tpmdmxvf32gernp, pmdmxvf32gerpn, pmdmxvf32gerpp, pmdmxvf64ger,\n\tpmdmxvf64gernn, pmdmxvf64gernp, pmdmxvf64gerpn, pmdmxvf64gerpp,\n\tpmdmxvi16ger2, pmdmxvi16ger2pp, pmdmxvi16ger2s, pmdmxvi16ger2spp,\n\tpmdmxvi4ger8, pmdmxvi4ger8pp, pmdmxvi8ger4, pmdmxvi8ger4pp,\n\tpmdmxvi8ger4spp.\n---\n gas/config/tc-ppc.c | 13 +-\n gas/testsuite/gas/ppc/outerprod.d | 215 +++++++++++++++++++++---------\n gas/testsuite/gas/ppc/outerprod.s | 61 +++++++++\n gas/testsuite/gas/ppc/ppc.exp | 1 +\n gas/testsuite/gas/ppc/rfc02653.d | 27 ++++\n gas/testsuite/gas/ppc/rfc02653.s | 18 +++\n include/opcode/ppc.h | 33 ++---\n opcodes/ppc-dis.c | 3 +\n opcodes/ppc-opc.c | 214 +++++++++++++++++++++++++----\n 9 files changed, 479 insertions(+), 106 deletions(-)\n create mode 100644 gas/testsuite/gas/ppc/rfc02653.d\n create mode 100644 gas/testsuite/gas/ppc/rfc02653.s","diff":"diff --git a/gas/config/tc-ppc.c b/gas/config/tc-ppc.c\nindex 97ad782012c..1acbba1791a 100644\n--- a/gas/config/tc-ppc.c\n+++ b/gas/config/tc-ppc.c\n@@ -353,6 +353,16 @@ static const struct pd_reg pre_defined_registers[] =\n { \"dec\", 22, PPC_OPERAND_SPR },\n { \"dsisr\", 18, PPC_OPERAND_SPR },\n \n+ /* Dense Math Registers. */\n+ { \"dm0\", 0, PPC_OPERAND_DMR },\n+ { \"dm1\", 1, PPC_OPERAND_DMR },\n+ { \"dm2\", 2, PPC_OPERAND_DMR },\n+ { \"dm3\", 3, PPC_OPERAND_DMR },\n+ { \"dm4\", 4, PPC_OPERAND_DMR },\n+ { \"dm5\", 5, PPC_OPERAND_DMR },\n+ { \"dm6\", 6, PPC_OPERAND_DMR },\n+ { \"dm7\", 7, PPC_OPERAND_DMR },\n+\n /* Floating point registers */\n { \"f.0\", 0, PPC_OPERAND_FPR },\n { \"f.1\", 1, PPC_OPERAND_FPR },\n@@ -3475,7 +3485,8 @@ md_assemble (char *str)\n \t & ~operand->flags\n \t & (PPC_OPERAND_GPR | PPC_OPERAND_FPR | PPC_OPERAND_VR\n \t\t | PPC_OPERAND_VSR | PPC_OPERAND_CR_BIT | PPC_OPERAND_CR_REG\n-\t\t | PPC_OPERAND_SPR | PPC_OPERAND_GQR | PPC_OPERAND_ACC)) != 0\n+\t\t | PPC_OPERAND_SPR | PPC_OPERAND_GQR | PPC_OPERAND_ACC\n+\t\t | PPC_OPERAND_DMR)) != 0\n \t && !((ex.X_md & PPC_OPERAND_GPR) != 0\n \t\t && ex.X_add_number != 0\n \t\t && (operand->flags & PPC_OPERAND_GPR_0) != 0))\ndiff --git a/gas/testsuite/gas/ppc/outerprod.d b/gas/testsuite/gas/ppc/outerprod.d\nindex 613fb189966..332102b1318 100644\n--- a/gas/testsuite/gas/ppc/outerprod.d\n+++ b/gas/testsuite/gas/ppc/outerprod.d\n@@ -8,97 +8,184 @@\n Disassembly of section \\.text:\n \n 0+0 <_start>:\n-.*:\t(7e 80 01 62|62 01 80 7e) \txxmfacc a5\n-.*:\t(7f 01 01 62|62 01 01 7f) \txxmtacc a6\n-.*:\t(7f 83 01 62|62 01 83 7f) \txxsetaccz a7\n-.*:\t(ec 1f f1 1e|1e f1 1f ec) \txvi4ger8 a0,vs63,vs62\n-.*:\t(ec 9d e1 16|16 e1 9d ec) \txvi4ger8pp a1,vs61,vs60\n-.*:\t(07 90 ff fe|fe ff 90 07) \tpmxvi4ger8 a2,vs59,vs58,15,14,255\n+.*:\t(7e 80 01 62|62 01 80 7e) \tdmxxmfacc a5\n+.*:\t(7e 80 01 62|62 01 80 7e) \tdmxxmfacc a5\n+.*:\t(7f 01 01 62|62 01 01 7f) \tdmxxmtacc a6\n+.*:\t(7f 01 01 62|62 01 01 7f) \tdmxxmtacc a6\n+.*:\t(7f 83 01 62|62 01 83 7f) \tdmsetaccz a7\n+.*:\t(7f 83 01 62|62 01 83 7f) \tdmsetaccz a7\n+.*:\t(ec 1f f1 1e|1e f1 1f ec) \tdmxvi4ger8 a0,vs63,vs62\n+.*:\t(ec 1f f1 1e|1e f1 1f ec) \tdmxvi4ger8 a0,vs63,vs62\n+.*:\t(ec 9d e1 16|16 e1 9d ec) \tdmxvi4ger8pp a1,vs61,vs60\n+.*:\t(ec 9d e1 16|16 e1 9d ec) \tdmxvi4ger8pp a1,vs61,vs60\n+.*:\t(07 90 ff fe|fe ff 90 07) \tpmdmxvi4ger8 a2,vs59,vs58,15,14,255\n .*:\t(ed 1b d1 1e|1e d1 1b ed) \n-.*:\t(07 90 80 78|78 80 90 07) \tpmxvi4ger8pp a3,vs57,vs56,7,8,128\n+.*:\t(07 90 ff fe|fe ff 90 07) \tpmdmxvi4ger8 a2,vs59,vs58,15,14,255\n+.*:\t(ed 1b d1 1e|1e d1 1b ed) \n+.*:\t(07 90 80 78|78 80 90 07) \tpmdmxvi4ger8pp a3,vs57,vs56,7,8,128\n+.*:\t(ed 99 c1 16|16 c1 99 ed) \n+.*:\t(07 90 80 78|78 80 90 07) \tpmdmxvi4ger8pp a3,vs57,vs56,7,8,128\n .*:\t(ed 99 c1 16|16 c1 99 ed) \n-.*:\t(ee 17 b0 1e|1e b0 17 ee) \txvi8ger4 a4,vs55,vs54\n-.*:\t(ee 95 a0 16|16 a0 95 ee) \txvi8ger4pp a5,vs53,vs52\n-.*:\t(07 90 b0 dc|dc b0 90 07) \tpmxvi8ger4 a6,vs51,vs50,13,12,11\n+.*:\t(ee 17 b0 1e|1e b0 17 ee) \tdmxvi8ger4 a4,vs55,vs54\n+.*:\t(ee 17 b0 1e|1e b0 17 ee) \tdmxvi8ger4 a4,vs55,vs54\n+.*:\t(ee 95 a0 16|16 a0 95 ee) \tdmxvi8ger4pp a5,vs53,vs52\n+.*:\t(ee 95 a0 16|16 a0 95 ee) \tdmxvi8ger4pp a5,vs53,vs52\n+.*:\t(07 90 b0 dc|dc b0 90 07) \tpmdmxvi8ger4 a6,vs51,vs50,13,12,11\n .*:\t(ef 13 90 1e|1e 90 13 ef) \n-.*:\t(07 90 80 a9|a9 80 90 07) \tpmxvi8ger4pp a7,vs49,vs48,10,9,8\n+.*:\t(07 90 b0 dc|dc b0 90 07) \tpmdmxvi8ger4 a6,vs51,vs50,13,12,11\n+.*:\t(ef 13 90 1e|1e 90 13 ef) \n+.*:\t(07 90 80 a9|a9 80 90 07) \tpmdmxvi8ger4pp a7,vs49,vs48,10,9,8\n+.*:\t(ef 91 80 16|16 80 91 ef) \n+.*:\t(07 90 80 a9|a9 80 90 07) \tpmdmxvi8ger4pp a7,vs49,vs48,10,9,8\n .*:\t(ef 91 80 16|16 80 91 ef) \n-.*:\t(ec 0f 71 5e|5e 71 0f ec) \txvi16ger2s a0,vs47,vs46\n-.*:\t(ec 8d 61 56|56 61 8d ec) \txvi16ger2spp a1,vs45,vs44\n-.*:\t(07 90 c0 76|76 c0 90 07) \tpmxvi16ger2s a2,vs43,vs42,7,6,3\n+.*:\t(ec 0f 71 5e|5e 71 0f ec) \tdmxvi16ger2s a0,vs47,vs46\n+.*:\t(ec 0f 71 5e|5e 71 0f ec) \tdmxvi16ger2s a0,vs47,vs46\n+.*:\t(ec 8d 61 56|56 61 8d ec) \tdmxvi16ger2spp a1,vs45,vs44\n+.*:\t(ec 8d 61 56|56 61 8d ec) \tdmxvi16ger2spp a1,vs45,vs44\n+.*:\t(07 90 c0 76|76 c0 90 07) \tpmdmxvi16ger2s a2,vs43,vs42,7,6,3\n .*:\t(ed 0b 51 5e|5e 51 0b ed) \n-.*:\t(07 90 80 54|54 80 90 07) \tpmxvi16ger2spp a3,vs41,vs40,5,4,2\n+.*:\t(07 90 c0 76|76 c0 90 07) \tpmdmxvi16ger2s a2,vs43,vs42,7,6,3\n+.*:\t(ed 0b 51 5e|5e 51 0b ed) \n+.*:\t(07 90 80 54|54 80 90 07) \tpmdmxvi16ger2spp a3,vs41,vs40,5,4,2\n+.*:\t(ed 89 41 56|56 41 89 ed) \n+.*:\t(07 90 80 54|54 80 90 07) \tpmdmxvi16ger2spp a3,vs41,vs40,5,4,2\n .*:\t(ed 89 41 56|56 41 89 ed) \n-.*:\t(ee 07 30 9e|9e 30 07 ee) \txvf16ger2 a4,vs39,vs38\n-.*:\t(ee 85 20 96|96 20 85 ee) \txvf16ger2pp a5,vs37,vs36\n-.*:\t(ef 03 14 96|96 14 03 ef) \txvf16ger2pn a6,vs35,vs34\n-.*:\t(ef 81 02 96|96 02 81 ef) \txvf16ger2np a7,vs33,vs32\n-.*:\t(ec 04 2e 90|90 2e 04 ec) \txvf16ger2nn a0,vs4,vs5\n-.*:\t(07 90 40 32|32 40 90 07) \tpmxvf16ger2 a1,vs2,vs3,3,2,1\n+.*:\t(ee 07 30 9e|9e 30 07 ee) \tdmxvf16ger2 a4,vs39,vs38\n+.*:\t(ee 07 30 9e|9e 30 07 ee) \tdmxvf16ger2 a4,vs39,vs38\n+.*:\t(ee 85 20 96|96 20 85 ee) \tdmxvf16ger2pp a5,vs37,vs36\n+.*:\t(ee 85 20 96|96 20 85 ee) \tdmxvf16ger2pp a5,vs37,vs36\n+.*:\t(ef 03 14 96|96 14 03 ef) \tdmxvf16ger2pn a6,vs35,vs34\n+.*:\t(ef 03 14 96|96 14 03 ef) \tdmxvf16ger2pn a6,vs35,vs34\n+.*:\t(ef 81 02 96|96 02 81 ef) \tdmxvf16ger2np a7,vs33,vs32\n+.*:\t(ef 81 02 96|96 02 81 ef) \tdmxvf16ger2np a7,vs33,vs32\n+.*:\t(ec 04 2e 90|90 2e 04 ec) \tdmxvf16ger2nn a0,vs4,vs5\n+.*:\t(ec 04 2e 90|90 2e 04 ec) \tdmxvf16ger2nn a0,vs4,vs5\n+.*:\t(07 90 40 32|32 40 90 07) \tpmdmxvf16ger2 a1,vs2,vs3,3,2,1\n .*:\t(ec 82 18 98|98 18 82 ec) \n-.*:\t(07 90 00 10|10 00 90 07) \tpmxvf16ger2pp a2,vs4,vs5,1,0,0\n+.*:\t(07 90 40 32|32 40 90 07) \tpmdmxvf16ger2 a1,vs2,vs3,3,2,1\n+.*:\t(ec 82 18 98|98 18 82 ec) \n+.*:\t(07 90 00 10|10 00 90 07) \tpmdmxvf16ger2pp a2,vs4,vs5,1,0,0\n+.*:\t(ed 04 28 90|90 28 04 ed) \n+.*:\t(07 90 00 10|10 00 90 07) \tpmdmxvf16ger2pp a2,vs4,vs5,1,0,0\n .*:\t(ed 04 28 90|90 28 04 ed) \n-.*:\t(07 90 c0 fe|fe c0 90 07) \tpmxvf16ger2pn a3,vs6,vs7,15,14,3\n+.*:\t(07 90 c0 fe|fe c0 90 07) \tpmdmxvf16ger2pn a3,vs6,vs7,15,14,3\n .*:\t(ed 86 3c 90|90 3c 86 ed) \n-.*:\t(07 90 80 dc|dc 80 90 07) \tpmxvf16ger2np a4,vs8,vs9,13,12,2\n+.*:\t(07 90 c0 fe|fe c0 90 07) \tpmdmxvf16ger2pn a3,vs6,vs7,15,14,3\n+.*:\t(ed 86 3c 90|90 3c 86 ed) \n+.*:\t(07 90 80 dc|dc 80 90 07) \tpmdmxvf16ger2np a4,vs8,vs9,13,12,2\n+.*:\t(ee 08 4a 90|90 4a 08 ee) \n+.*:\t(07 90 80 dc|dc 80 90 07) \tpmdmxvf16ger2np a4,vs8,vs9,13,12,2\n .*:\t(ee 08 4a 90|90 4a 08 ee) \n-.*:\t(07 90 40 ba|ba 40 90 07) \tpmxvf16ger2nn a5,vs10,vs11,11,10,1\n+.*:\t(07 90 40 ba|ba 40 90 07) \tpmdmxvf16ger2nn a5,vs10,vs11,11,10,1\n .*:\t(ee 8a 5e 90|90 5e 8a ee) \n-.*:\t(ef 0c 68 d8|d8 68 0c ef) \txvf32ger a6,vs12,vs13\n-.*:\t(ef 8e 78 d0|d0 78 8e ef) \txvf32gerpp a7,vs14,vs15\n-.*:\t(ec 10 8c d0|d0 8c 10 ec) \txvf32gerpn a0,vs16,vs17\n-.*:\t(ec 92 9a d0|d0 9a 92 ec) \txvf32gernp a1,vs18,vs19\n-.*:\t(ed 14 ae d0|d0 ae 14 ed) \txvf32gernn a2,vs20,vs21\n-.*:\t(07 90 00 98|98 00 90 07) \tpmxvf32ger a3,vs22,vs23,9,8\n+.*:\t(07 90 40 ba|ba 40 90 07) \tpmdmxvf16ger2nn a5,vs10,vs11,11,10,1\n+.*:\t(ee 8a 5e 90|90 5e 8a ee) \n+.*:\t(ef 0c 68 d8|d8 68 0c ef) \tdmxvf32ger a6,vs12,vs13\n+.*:\t(ef 0c 68 d8|d8 68 0c ef) \tdmxvf32ger a6,vs12,vs13\n+.*:\t(ef 8e 78 d0|d0 78 8e ef) \tdmxvf32gerpp a7,vs14,vs15\n+.*:\t(ef 8e 78 d0|d0 78 8e ef) \tdmxvf32gerpp a7,vs14,vs15\n+.*:\t(ec 10 8c d0|d0 8c 10 ec) \tdmxvf32gerpn a0,vs16,vs17\n+.*:\t(ec 10 8c d0|d0 8c 10 ec) \tdmxvf32gerpn a0,vs16,vs17\n+.*:\t(ec 92 9a d0|d0 9a 92 ec) \tdmxvf32gernp a1,vs18,vs19\n+.*:\t(ec 92 9a d0|d0 9a 92 ec) \tdmxvf32gernp a1,vs18,vs19\n+.*:\t(ed 14 ae d0|d0 ae 14 ed) \tdmxvf32gernn a2,vs20,vs21\n+.*:\t(ed 14 ae d0|d0 ae 14 ed) \tdmxvf32gernn a2,vs20,vs21\n+.*:\t(07 90 00 98|98 00 90 07) \tpmdmxvf32ger a3,vs22,vs23,9,8\n+.*:\t(ed 96 b8 d8|d8 b8 96 ed) \n+.*:\t(07 90 00 98|98 00 90 07) \tpmdmxvf32ger a3,vs22,vs23,9,8\n .*:\t(ed 96 b8 d8|d8 b8 96 ed) \n-.*:\t(07 90 00 76|76 00 90 07) \tpmxvf32gerpp a4,vs24,vs25,7,6\n+.*:\t(07 90 00 76|76 00 90 07) \tpmdmxvf32gerpp a4,vs24,vs25,7,6\n .*:\t(ee 18 c8 d0|d0 c8 18 ee) \n-.*:\t(07 90 00 54|54 00 90 07) \tpmxvf32gerpn a5,vs26,vs27,5,4\n+.*:\t(07 90 00 76|76 00 90 07) \tpmdmxvf32gerpp a4,vs24,vs25,7,6\n+.*:\t(ee 18 c8 d0|d0 c8 18 ee) \n+.*:\t(07 90 00 54|54 00 90 07) \tpmdmxvf32gerpn a5,vs26,vs27,5,4\n+.*:\t(ee 9a dc d0|d0 dc 9a ee) \n+.*:\t(07 90 00 54|54 00 90 07) \tpmdmxvf32gerpn a5,vs26,vs27,5,4\n .*:\t(ee 9a dc d0|d0 dc 9a ee) \n-.*:\t(60 00 00 00|00 00 00 60) \tnop\n-.*:\t(07 90 00 32|32 00 90 07) \tpmxvf32gernp a6,vs28,vs29,3,2\n+.*:\t(07 90 00 32|32 00 90 07) \tpmdmxvf32gernp a6,vs28,vs29,3,2\n+.*:\t(ef 1c ea d0|d0 ea 1c ef) \n+.*:\t(07 90 00 32|32 00 90 07) \tpmdmxvf32gernp a6,vs28,vs29,3,2\n .*:\t(ef 1c ea d0|d0 ea 1c ef) \n-.*:\t(07 90 00 10|10 00 90 07) \tpmxvf32gernn a7,vs0,vs1,1,0\n+.*:\t(07 90 00 10|10 00 90 07) \tpmdmxvf32gernn a7,vs0,vs1,1,0\n .*:\t(ef 80 0e d0|d0 0e 80 ef) \n-.*:\t(ec 04 29 d8|d8 29 04 ec) \txvf64ger a0,vs4,vs5\n-.*:\t(ec 88 49 d0|d0 49 88 ec) \txvf64gerpp a1,vs8,vs9\n-.*:\t(ed 02 15 d0|d0 15 02 ed) \txvf64gerpn a2,vs2,vs2\n-.*:\t(ed 84 1b d0|d0 1b 84 ed) \txvf64gernp a3,vs4,vs3\n-.*:\t(ee 04 27 d0|d0 27 04 ee) \txvf64gernn a4,vs4,vs4\n-.*:\t(07 90 00 f0|f0 00 90 07) \tpmxvf64ger a5,vs6,vs5,15,0\n+.*:\t(07 90 00 10|10 00 90 07) \tpmdmxvf32gernn a7,vs0,vs1,1,0\n+.*:\t(ef 80 0e d0|d0 0e 80 ef) \n+.*:\t(ec 04 29 d8|d8 29 04 ec) \tdmxvf64ger a0,vs4,vs5\n+.*:\t(ec 04 29 d8|d8 29 04 ec) \tdmxvf64ger a0,vs4,vs5\n+.*:\t(ec 88 49 d0|d0 49 88 ec) \tdmxvf64gerpp a1,vs8,vs9\n+.*:\t(ec 88 49 d0|d0 49 88 ec) \tdmxvf64gerpp a1,vs8,vs9\n+.*:\t(ed 02 15 d0|d0 15 02 ed) \tdmxvf64gerpn a2,vs2,vs2\n+.*:\t(ed 02 15 d0|d0 15 02 ed) \tdmxvf64gerpn a2,vs2,vs2\n+.*:\t(ed 84 1b d0|d0 1b 84 ed) \tdmxvf64gernp a3,vs4,vs3\n+.*:\t(ed 84 1b d0|d0 1b 84 ed) \tdmxvf64gernp a3,vs4,vs3\n+.*:\t(ee 04 27 d0|d0 27 04 ee) \tdmxvf64gernn a4,vs4,vs4\n+.*:\t(ee 04 27 d0|d0 27 04 ee) \tdmxvf64gernn a4,vs4,vs4\n+.*:\t(07 90 00 f0|f0 00 90 07) \tpmdmxvf64ger a5,vs6,vs5,15,0\n+.*:\t(ee 86 29 d8|d8 29 86 ee) \n+.*:\t(07 90 00 f0|f0 00 90 07) \tpmdmxvf64ger a5,vs6,vs5,15,0\n .*:\t(ee 86 29 d8|d8 29 86 ee) \n-.*:\t(07 90 00 e4|e4 00 90 07) \tpmxvf64gerpp a6,vs6,vs6,14,1\n+.*:\t(07 90 00 e4|e4 00 90 07) \tpmdmxvf64gerpp a6,vs6,vs6,14,1\n .*:\t(ef 06 31 d0|d0 31 06 ef) \n-.*:\t(07 90 00 d8|d8 00 90 07) \tpmxvf64gerpn a7,vs8,vs7,13,2\n+.*:\t(07 90 00 e4|e4 00 90 07) \tpmdmxvf64gerpp a6,vs6,vs6,14,1\n+.*:\t(ef 06 31 d0|d0 31 06 ef) \n+.*:\t(07 90 00 d8|d8 00 90 07) \tpmdmxvf64gerpn a7,vs8,vs7,13,2\n+.*:\t(ef 88 3d d0|d0 3d 88 ef) \n+.*:\t(07 90 00 d8|d8 00 90 07) \tpmdmxvf64gerpn a7,vs8,vs7,13,2\n .*:\t(ef 88 3d d0|d0 3d 88 ef) \n-.*:\t(60 00 00 00|00 00 00 60) \tnop\n-.*:\t(07 90 00 cc|cc 00 90 07) \tpmxvf64gernp a0,vs4,vs5,12,3\n+.*:\t(07 90 00 cc|cc 00 90 07) \tpmdmxvf64gernp a0,vs4,vs5,12,3\n .*:\t(ec 04 2b d0|d0 2b 04 ec) \n-.*:\t(07 90 00 a0|a0 00 90 07) \tpmxvf64gernn a1,vs2,vs1,10,0\n+.*:\t(07 90 00 cc|cc 00 90 07) \tpmdmxvf64gernp a0,vs4,vs5,12,3\n+.*:\t(ec 04 2b d0|d0 2b 04 ec) \n+.*:\t(07 90 00 a0|a0 00 90 07) \tpmdmxvf64gernn a1,vs2,vs1,10,0\n+.*:\t(ec 82 0f d0|d0 0f 82 ec) \n+.*:\t(07 90 00 a0|a0 00 90 07) \tpmdmxvf64gernn a1,vs2,vs1,10,0\n .*:\t(ec 82 0f d0|d0 0f 82 ec) \n-.*:\t(ed 03 21 90|90 21 03 ed) \txvbf16ger2pp a2,vs3,vs4\n-.*:\t(ed 84 29 98|98 29 84 ed) \txvbf16ger2 a3,vs4,vs5\n-.*:\t(ee 05 33 90|90 33 05 ee) \txvbf16ger2np a4,vs5,vs6\n-.*:\t(ee 86 3d 90|90 3d 86 ee) \txvbf16ger2pn a5,vs6,vs7\n-.*:\t(ef 07 47 90|90 47 07 ef) \txvbf16ger2nn a6,vs7,vs8\n-.*:\t(07 90 c0 ff|ff c0 90 07) \tpmxvbf16ger2pp a7,vs8,vs9,15,15,3\n+.*:\t(ed 03 21 90|90 21 03 ed) \tdmxvbf16ger2pp a2,vs3,vs4\n+.*:\t(ed 03 21 90|90 21 03 ed) \tdmxvbf16ger2pp a2,vs3,vs4\n+.*:\t(ed 84 29 98|98 29 84 ed) \tdmxvbf16ger2 a3,vs4,vs5\n+.*:\t(ed 84 29 98|98 29 84 ed) \tdmxvbf16ger2 a3,vs4,vs5\n+.*:\t(ee 05 33 90|90 33 05 ee) \tdmxvbf16ger2np a4,vs5,vs6\n+.*:\t(ee 05 33 90|90 33 05 ee) \tdmxvbf16ger2np a4,vs5,vs6\n+.*:\t(ee 86 3d 90|90 3d 86 ee) \tdmxvbf16ger2pn a5,vs6,vs7\n+.*:\t(ee 86 3d 90|90 3d 86 ee) \tdmxvbf16ger2pn a5,vs6,vs7\n+.*:\t(ef 07 47 90|90 47 07 ef) \tdmxvbf16ger2nn a6,vs7,vs8\n+.*:\t(ef 07 47 90|90 47 07 ef) \tdmxvbf16ger2nn a6,vs7,vs8\n+.*:\t(07 90 c0 ff|ff c0 90 07) \tpmdmxvbf16ger2pp a7,vs8,vs9,15,15,3\n+.*:\t(ef 88 49 90|90 49 88 ef) \n+.*:\t(07 90 c0 ff|ff c0 90 07) \tpmdmxvbf16ger2pp a7,vs8,vs9,15,15,3\n .*:\t(ef 88 49 90|90 49 88 ef) \n-.*:\t(07 90 80 cc|cc 80 90 07) \tpmxvbf16ger2 a0,vs9,vs10,12,12,2\n+.*:\t(07 90 80 cc|cc 80 90 07) \tpmdmxvbf16ger2 a0,vs9,vs10,12,12,2\n .*:\t(ec 09 51 98|98 51 09 ec) \n-.*:\t(07 90 40 aa|aa 40 90 07) \tpmxvbf16ger2np a1,vs10,vs11,10,10,1\n+.*:\t(07 90 80 cc|cc 80 90 07) \tpmdmxvbf16ger2 a0,vs9,vs10,12,12,2\n+.*:\t(ec 09 51 98|98 51 09 ec) \n+.*:\t(07 90 40 aa|aa 40 90 07) \tpmdmxvbf16ger2np a1,vs10,vs11,10,10,1\n+.*:\t(ec 8a 5b 90|90 5b 8a ec) \n+.*:\t(07 90 40 aa|aa 40 90 07) \tpmdmxvbf16ger2np a1,vs10,vs11,10,10,1\n .*:\t(ec 8a 5b 90|90 5b 8a ec) \n-.*:\t(60 00 00 00|00 00 00 60) \tnop\n-.*:\t(07 90 00 dd|dd 00 90 07) \tpmxvbf16ger2pn a2,vs12,vs13,13,13,0\n+.*:\t(07 90 00 dd|dd 00 90 07) \tpmdmxvbf16ger2pn a2,vs12,vs13,13,13,0\n .*:\t(ed 0c 6d 90|90 6d 0c ed) \n-.*:\t(07 90 c0 ee|ee c0 90 07) \tpmxvbf16ger2nn a3,vs16,vs17,14,14,3\n+.*:\t(07 90 00 dd|dd 00 90 07) \tpmdmxvbf16ger2pn a2,vs12,vs13,13,13,0\n+.*:\t(ed 0c 6d 90|90 6d 0c ed) \n+.*:\t(07 90 c0 ee|ee c0 90 07) \tpmdmxvbf16ger2nn a3,vs16,vs17,14,14,3\n+.*:\t(ed 90 8f 90|90 8f 90 ed) \n+.*:\t(07 90 c0 ee|ee c0 90 07) \tpmdmxvbf16ger2nn a3,vs16,vs17,14,14,3\n .*:\t(ed 90 8f 90|90 8f 90 ed) \n-.*:\t(ee 00 0b 1e|1e 0b 00 ee) \txvi8ger4spp a4,vs32,vs33\n-.*:\t(07 90 f0 ff|ff f0 90 07) \tpmxvi8ger4spp a5,vs34,vs35,15,15,15\n+.*:\t(ee 00 0b 1e|1e 0b 00 ee) \tdmxvi8ger4spp a4,vs32,vs33\n+.*:\t(ee 00 0b 1e|1e 0b 00 ee) \tdmxvi8ger4spp a4,vs32,vs33\n+.*:\t(07 90 f0 ff|ff f0 90 07) \tpmdmxvi8ger4spp a5,vs34,vs35,15,15,15\n .*:\t(ee 82 1b 1e|1e 1b 82 ee) \n-.*:\t(ef 04 2a 5e|5e 2a 04 ef) \txvi16ger2 a6,vs36,vs37\n-.*:\t(ef 86 3b 5e|5e 3b 86 ef) \txvi16ger2pp a7,vs38,vs39\n-.*:\t(07 90 40 ff|ff 40 90 07) \tpmxvi16ger2 a0,vs38,vs39,15,15,1\n+.*:\t(07 90 f0 ff|ff f0 90 07) \tpmdmxvi8ger4spp a5,vs34,vs35,15,15,15\n+.*:\t(ee 82 1b 1e|1e 1b 82 ee) \n+.*:\t(ef 04 2a 5e|5e 2a 04 ef) \tdmxvi16ger2 a6,vs36,vs37\n+.*:\t(ef 04 2a 5e|5e 2a 04 ef) \tdmxvi16ger2 a6,vs36,vs37\n+.*:\t(ef 86 3b 5e|5e 3b 86 ef) \tdmxvi16ger2pp a7,vs38,vs39\n+.*:\t(ef 86 3b 5e|5e 3b 86 ef) \tdmxvi16ger2pp a7,vs38,vs39\n+.*:\t(07 90 40 ff|ff 40 90 07) \tpmdmxvi16ger2 a0,vs38,vs39,15,15,1\n+.*:\t(ec 06 3a 5e|5e 3a 06 ec) \n+.*:\t(07 90 40 ff|ff 40 90 07) \tpmdmxvi16ger2 a0,vs38,vs39,15,15,1\n .*:\t(ec 06 3a 5e|5e 3a 06 ec) \n-.*:\t(07 90 80 cc|cc 80 90 07) \tpmxvi16ger2pp a1,vs40,vs41,12,12,2\n+.*:\t(07 90 80 cc|cc 80 90 07) \tpmdmxvi16ger2pp a1,vs40,vs41,12,12,2\n+.*:\t(ec 88 4b 5e|5e 4b 88 ec) \n+.*:\t(07 90 80 cc|cc 80 90 07) \tpmdmxvi16ger2pp a1,vs40,vs41,12,12,2\n .*:\t(ec 88 4b 5e|5e 4b 88 ec) \n #pass\ndiff --git a/gas/testsuite/gas/ppc/outerprod.s b/gas/testsuite/gas/ppc/outerprod.s\nindex 1f02c158daa..dd947fe9720 100644\n--- a/gas/testsuite/gas/ppc/outerprod.s\n+++ b/gas/testsuite/gas/ppc/outerprod.s\n@@ -1,63 +1,124 @@\n \t.text\n _start:\n \txxmfacc\t5\n+\tdmxxmfacc 5\n \txxmtacc 6\n+\tdmxxmtacc 6\n \txxsetaccz 7\n+\tdmsetaccz 7\n \txvi4ger8 0,63,62\n+\tdmxvi4ger8 0,63,62\n \txvi4ger8pp 1,61,60\n+\tdmxvi4ger8pp 1,61,60\n \tpmxvi4ger8 2,59,58,15,14,255\n+\tpmdmxvi4ger8 2,59,58,15,14,255\n \tpmxvi4ger8pp 3,57,56,7,8,128\n+\tpmdmxvi4ger8pp 3,57,56,7,8,128\n \txvi8ger4 4,55,54\n+\tdmxvi8ger4 4,55,54\n \txvi8ger4pp 5,53,52\n+\tdmxvi8ger4pp 5,53,52\n \tpmxvi8ger4 6,51,50,13,12,11\n+\tpmdmxvi8ger4 6,51,50,13,12,11\n \tpmxvi8ger4pp 7,49,48,10,9,8\n+\tpmdmxvi8ger4pp 7,49,48,10,9,8\n \txvi16ger2s 0,47,46\n+\tdmxvi16ger2s 0,47,46\n \txvi16ger2spp 1,45,44\n+\tdmxvi16ger2spp 1,45,44\n \tpmxvi16ger2s 2,43,42,7,6,3\n+\tpmdmxvi16ger2s 2,43,42,7,6,3\n \tpmxvi16ger2spp 3,41,40,5,4,2\n+\tpmdmxvi16ger2spp 3,41,40,5,4,2\n \txvf16ger2 4,39,38\n+\tdmxvf16ger2 4,39,38\n \txvf16ger2pp 5,37,36\n+\tdmxvf16ger2pp 5,37,36\n \txvf16ger2pn 6,35,34\n+\tdmxvf16ger2pn 6,35,34\n \txvf16ger2np 7,33,32\n+\tdmxvf16ger2np 7,33,32\n \txvf16ger2nn 0,4,5\n+\tdmxvf16ger2nn 0,4,5\n \tpmxvf16ger2 1,2,3,3,2,1\n+\tpmdmxvf16ger2 1,2,3,3,2,1\n \tpmxvf16ger2pp 2,4,5,1,0,0\n+\tpmdmxvf16ger2pp 2,4,5,1,0,0\n \tpmxvf16ger2pn 3,6,7,15,14,3\n+\tpmdmxvf16ger2pn 3,6,7,15,14,3\n \tpmxvf16ger2np 4,8,9,13,12,2\n+\tpmdmxvf16ger2np 4,8,9,13,12,2\n \tpmxvf16ger2nn 5,10,11,11,10,1\n+\tpmdmxvf16ger2nn 5,10,11,11,10,1\n \txvf32ger 6,12,13\n+\tdmxvf32ger 6,12,13\n \txvf32gerpp 7,14,15\n+\tdmxvf32gerpp 7,14,15\n \txvf32gerpn 0,16,17\n+\tdmxvf32gerpn 0,16,17\n \txvf32gernp 1,18,19\n+\tdmxvf32gernp 1,18,19\n \txvf32gernn 2,20,21\n+\tdmxvf32gernn 2,20,21\n \tpmxvf32ger 3,22,23,9,8\n+\tpmdmxvf32ger 3,22,23,9,8\n \tpmxvf32gerpp 4,24,25,7,6\n+\tpmdmxvf32gerpp 4,24,25,7,6\n \tpmxvf32gerpn 5,26,27,5,4\n+\tpmdmxvf32gerpn 5,26,27,5,4\n \tpmxvf32gernp 6,28,29,3,2\n+\tpmdmxvf32gernp 6,28,29,3,2\n \tpmxvf32gernn 7,0,1,1,0\n+\tpmdmxvf32gernn 7,0,1,1,0\n \txvf64ger 0,4,5\n+\tdmxvf64ger 0,4,5\n \txvf64gerpp 1,8,9\n+\tdmxvf64gerpp 1,8,9\n \txvf64gerpn 2,2,2\n+\tdmxvf64gerpn 2,2,2\n \txvf64gernp 3,4,3\n+\tdmxvf64gernp 3,4,3\n \txvf64gernn 4,4,4\n+\tdmxvf64gernn 4,4,4\n \tpmxvf64ger 5,6,5,15,0\n+\tpmdmxvf64ger 5,6,5,15,0\n \tpmxvf64gerpp 6,6,6,14,1\n+\tpmdmxvf64gerpp 6,6,6,14,1\n \tpmxvf64gerpn 7,8,7,13,2\n+\tpmdmxvf64gerpn 7,8,7,13,2\n \tpmxvf64gernp 0,4,5,12,3\n+\tpmdmxvf64gernp 0,4,5,12,3\n \tpmxvf64gernn 1,2,1,10,0\n+\tpmdmxvf64gernn 1,2,1,10,0\n \txvbf16ger2pp 2,3,4\n+\tdmxvbf16ger2pp 2,3,4\n \txvbf16ger2 3,4,5\n+\tdmxvbf16ger2 3,4,5\n \txvbf16ger2np 4,5,6\n+\tdmxvbf16ger2np 4,5,6\n \txvbf16ger2pn 5,6,7\n+\tdmxvbf16ger2pn 5,6,7\n \txvbf16ger2nn 6,7,8\n+\tdmxvbf16ger2nn 6,7,8\n \tpmxvbf16ger2pp 7,8,9,15,15,3\n+\tpmdmxvbf16ger2pp 7,8,9,15,15,3\n \tpmxvbf16ger2 0,9,10,12,12,2\n+\tpmdmxvbf16ger2 0,9,10,12,12,2\n \tpmxvbf16ger2np 1,10,11,10,10,1\n+\tpmdmxvbf16ger2np 1,10,11,10,10,1\n \tpmxvbf16ger2pn 2,12,13,13,13,0\n+\tpmdmxvbf16ger2pn 2,12,13,13,13,0\n \tpmxvbf16ger2nn 3,16,17,14,14,3\n+\tpmdmxvbf16ger2nn 3,16,17,14,14,3\n \txvi8ger4spp 4,32,33\n+\tdmxvi8ger4spp 4,32,33\n \tpmxvi8ger4spp 5,34,35,15,15,15\n+\tpmdmxvi8ger4spp 5,34,35,15,15,15\n \txvi16ger2 6,36,37\n+\tdmxvi16ger2 6,36,37\n \txvi16ger2pp 7,38,39\n+\tdmxvi16ger2pp 7,38,39\n \tpmxvi16ger2 0,38,39,15,15,1\n+\tpmdmxvi16ger2 0,38,39,15,15,1\n \tpmxvi16ger2pp 1,40,41,12,12,2\n+\tpmdmxvi16ger2pp 1,40,41,12,12,2\ndiff --git a/gas/testsuite/gas/ppc/ppc.exp b/gas/testsuite/gas/ppc/ppc.exp\nindex ae8a7b61cde..f27a79cfd73 100644\n--- a/gas/testsuite/gas/ppc/ppc.exp\n+++ b/gas/testsuite/gas/ppc/ppc.exp\n@@ -145,6 +145,7 @@ run_dump_test \"rightmost\"\n run_dump_test \"scalarquad\"\n run_dump_test \"rop\"\n run_dump_test \"rop-checks\"\n+run_dump_test \"rfc02653\"\n \n run_dump_test \"dcbt\"\n run_dump_test \"pr27676\"\ndiff --git a/gas/testsuite/gas/ppc/rfc02653.d b/gas/testsuite/gas/ppc/rfc02653.d\nnew file mode 100644\nindex 00000000000..6ad49df9c04\n--- /dev/null\n+++ b/gas/testsuite/gas/ppc/rfc02653.d\n@@ -0,0 +1,27 @@\n+#as: -mfuture\n+#objdump: -dr -Mfuture\n+#name: RFC02653 tests\n+\n+.*\n+\n+\n+Disassembly of section \\.text:\n+\n+0+0 <_start>:\n+.*:\t(62 01 02 7c|7c 02 01 62) \tdmsetdmrz dm0\n+.*:\t(62 41 86 7c|7c 86 41 62) \tdmmr dm1,dm2\n+.*:\t(62 61 07 7d|7d 07 61 62) \tdmxor dm2,dm3\n+.*:\t(10 17 00 f2|f2 00 17 10) \tdmxxextfdmr512 vs0,vs2,dm4,0\n+.*:\t(10 37 85 f2|f2 85 37 10) \tdmxxextfdmr512 vs4,vs6,dm5,1\n+.*:\t(50 57 08 f3|f3 08 57 50) \tdmxxinstdmr512 dm6,vs8,vs10,0\n+.*:\t(50 57 89 f3|f3 89 57 50) \tdmxxinstdmr512 dm7,vs8,vs10,1\n+.*:\t(90 67 00 f0|f0 00 67 90) \tdmxxextfdmr256 vs12,dm0,0\n+.*:\t(90 7f 80 f0|f0 80 7f 90) \tdmxxextfdmr256 vs14,dm1,1\n+.*:\t(90 87 01 f1|f1 01 87 90) \tdmxxextfdmr256 vs16,dm2,2\n+.*:\t(90 9f 81 f1|f1 81 9f 90) \tdmxxextfdmr256 vs18,dm3,3\n+.*:\t(94 a7 00 f2|f2 00 a7 94) \tdmxxinstdmr256 dm4,vs20,0\n+.*:\t(94 bf 80 f2|f2 80 bf 94) \tdmxxinstdmr256 dm5,vs22,1\n+.*:\t(94 c7 01 f3|f3 01 c7 94) \tdmxxinstdmr256 dm6,vs24,2\n+.*:\t(94 df 81 f3|f3 81 df 94) \tdmxxinstdmr256 dm7,vs26,3\n+.*:\t(18 09 00 ec|ec 00 09 18) \tdmxvi4ger8 a0,vs0,vs1\n+#pass\ndiff --git a/gas/testsuite/gas/ppc/rfc02653.s b/gas/testsuite/gas/ppc/rfc02653.s\nnew file mode 100644\nindex 00000000000..8b343d6cbfc\n--- /dev/null\n+++ b/gas/testsuite/gas/ppc/rfc02653.s\n@@ -0,0 +1,18 @@\n+\t.text\n+_start:\n+\tdmsetdmrz\t0\n+\tdmmr\t\t1,2\n+\tdmxor\t\t2,3\n+\tdmxxextfdmr512\t0,2,4,0\n+\tdmxxextfdmr512\t4,6,5,1\n+\tdmxxinstdmr512\t6,8,10,0\n+\tdmxxinstdmr512\t7,8,10,1\n+\tdmxxextfdmr256\t12,0,0\n+\tdmxxextfdmr256\t14,1,1\n+\tdmxxextfdmr256\t16,2,2\n+\tdmxxextfdmr256\t18,3,3\n+\tdmxxinstdmr256\t4,20,0\n+\tdmxxinstdmr256\t5,22,1\n+\tdmxxinstdmr256\t6,24,2\n+\tdmxxinstdmr256\t7,26,3\n+\tdmxvi4ger8 0,0,1\t# VSRs can now overlap the ACCs\ndiff --git a/include/opcode/ppc.h b/include/opcode/ppc.h\nindex 930d13d3026..004b51db670 100644\n--- a/include/opcode/ppc.h\n+++ b/include/opcode/ppc.h\n@@ -384,6 +384,9 @@ extern const unsigned int num_powerpc_operands;\n /* This operand names a VSX accumulator. */\n #define PPC_OPERAND_ACC (0x20)\n \n+/* This operand names a dense math register. */\n+#define PPC_OPERAND_DMR (0x40)\n+\n /* This operand may use the symbolic names for the CR fields (even\n without -mregnames), which are\n lt 0\tgt 1\teq 2\tso 3\tun 3\n@@ -391,60 +394,60 @@ extern const unsigned int num_powerpc_operands;\n cr4 4\tcr5 5\tcr6 6\tcr7 7\n These may be combined arithmetically, as in cr2*4+gt. These are\n only supported on the PowerPC, not the POWER. */\n-#define PPC_OPERAND_CR_BIT (0x40)\n+#define PPC_OPERAND_CR_BIT (0x80)\n \n /* This is a CR FIELD that does not use symbolic names (unless\n -mregnames is in effect). If both PPC_OPERAND_CR_BIT and\n PPC_OPERAND_CR_REG are set then treat the field as per\n PPC_OPERAND_CR_BIT for assembly, but as if neither of these\n bits are set for disassembly. */\n-#define PPC_OPERAND_CR_REG (0x80)\n+#define PPC_OPERAND_CR_REG (0x100)\n \n /* This operand names a special purpose register. */\n-#define PPC_OPERAND_SPR (0x100)\n+#define PPC_OPERAND_SPR (0x200)\n \n /* This operand names a paired-single graphics quantization register. */\n-#define PPC_OPERAND_GQR (0x200)\n+#define PPC_OPERAND_GQR (0x400)\n \n /* This operand is a relative branch displacement. The disassembler\n prints these symbolically if possible. */\n-#define PPC_OPERAND_RELATIVE (0x400)\n+#define PPC_OPERAND_RELATIVE (0x800)\n \n /* This operand is an absolute branch address. The disassembler\n prints these symbolically if possible. */\n-#define PPC_OPERAND_ABSOLUTE (0x800)\n+#define PPC_OPERAND_ABSOLUTE (0x1000)\n \n /* This operand takes signed values. */\n-#define PPC_OPERAND_SIGNED (0x1000)\n+#define PPC_OPERAND_SIGNED (0x2000)\n \n /* This operand takes signed values, but also accepts a full positive\n range of values when running in 32 bit mode. That is, if bits is\n 16, it takes any value from -0x8000 to 0xffff. In 64 bit mode,\n this flag is ignored. */\n-#define PPC_OPERAND_SIGNOPT (0x2000)\n+#define PPC_OPERAND_SIGNOPT (0x4000)\n \n /* The next operand should be wrapped in parentheses rather than\n separated from this one by a comma. This is used for the load and\n store instructions which want their operands to look like\n reg,displacement(reg)\n */\n-#define PPC_OPERAND_PARENS (0x4000)\n+#define PPC_OPERAND_PARENS (0x8000)\n \n /* This operand is for the DS field in a DS form instruction. */\n-#define PPC_OPERAND_DS (0x8000)\n+#define PPC_OPERAND_DS (0x10000)\n \n /* This operand is for the DQ field in a DQ form instruction. */\n-#define PPC_OPERAND_DQ (0x10000)\n+#define PPC_OPERAND_DQ (0x20000)\n \n /* This operand should be regarded as a negative number for the\n purposes of overflow checking (i.e., the normal most negative\n number is disallowed and one more than the normal most positive\n number is allowed). This flag will only be set for a signed\n operand. */\n-#define PPC_OPERAND_NEGATIVE (0x20000)\n+#define PPC_OPERAND_NEGATIVE (0x40000)\n \n /* Valid range of operand is 0..n rather than 0..n-1. */\n-#define PPC_OPERAND_PLUS1 (0x40000)\n+#define PPC_OPERAND_PLUS1 (0x80000)\n \n /* This operand is optional, and is zero if omitted. This is used for\n example, in the optional BF field in the comparison instructions. The\n@@ -452,7 +455,7 @@ extern const unsigned int num_powerpc_operands;\n and the number of operands remaining for the opcode, and decide\n whether this operand is present or not. The disassembler should\n print this operand out only if it is not zero. */\n-#define PPC_OPERAND_OPTIONAL (0x80000)\n+#define PPC_OPERAND_OPTIONAL (0x100000)\n \n /* This flag is only used with PPC_OPERAND_OPTIONAL. If this operand\n is omitted, then for the next operand use this operand value plus\n@@ -460,7 +463,7 @@ extern const unsigned int num_powerpc_operands;\n hack is needed because the Power rotate instructions can take\n either 4 or 5 operands. The disassembler should print this operand\n out regardless of the PPC_OPERAND_OPTIONAL field. */\n-#define PPC_OPERAND_NEXT (0x100000)\n+#define PPC_OPERAND_NEXT (0x200000)\n \n /* This flag is only used with PPC_OPERAND_OPTIONAL. The operand is\n only optional when generating 32-bit code. */\ndiff --git a/opcodes/ppc-dis.c b/opcodes/ppc-dis.c\nindex 33a96701ca8..69466661800 100644\n--- a/opcodes/ppc-dis.c\n+++ b/opcodes/ppc-dis.c\n@@ -1097,6 +1097,9 @@ print_insn_powerpc (bfd_vma memaddr,\n \t else if ((operand->flags & PPC_OPERAND_VSR) != 0)\n \t (*info->fprintf_styled_func) (info->stream, dis_style_register,\n \t\t\t\t\t \"vs%\" PRId64, value);\n+\t else if ((operand->flags & PPC_OPERAND_DMR) != 0)\n+\t (*info->fprintf_styled_func) (info->stream, dis_style_register,\n+\t\t\t\t\t \"dm%\" PRId64, value);\n \t else if ((operand->flags & PPC_OPERAND_ACC) != 0)\n \t (*info->fprintf_styled_func) (info->stream, dis_style_register,\n \t\t\t\t\t \"a%\" PRId64, value);\ndiff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c\nindex b470ebd0aa9..c323a2761e3 100644\n--- a/opcodes/ppc-opc.c\n+++ b/opcodes/ppc-opc.c\n@@ -1477,6 +1477,26 @@ extract_pl (uint64_t insn,\n return value;\n }\n \n+/* The 2-bit P field in a MMA XX2-form instruction. This is split. */\n+\n+static uint64_t\n+insert_p2 (uint64_t insn,\n+\t int64_t value,\n+\t ppc_cpu_t dialect ATTRIBUTE_UNUSED,\n+\t const char **errmsg ATTRIBUTE_UNUSED)\n+{\n+ return insn | ((value & 0x2) << 15) | ((value & 0x1) << 11);\n+}\n+\n+static int64_t\n+extract_p2 (uint64_t insn,\n+\t ppc_cpu_t dialect ATTRIBUTE_UNUSED,\n+\t int *invalid ATTRIBUTE_UNUSED)\n+{\n+ uint64_t value = ((insn >> 15) & 0x2) | ((insn >> 11) & 0x1);\n+ return value;\n+}\n+\n /* The RA field in a D or X form instruction which is an updating\n load, which means that the RA field may not be zero and may not\n equal the RT field. */\n@@ -2129,6 +2149,25 @@ extract_xtq6 (uint64_t insn,\n return ((insn << 2) & 0x20) | ((insn >> 21) & 0x1f);\n }\n \n+/* The 5-bit XAp field in an XX3 form instruction. This is split. */\n+\n+static uint64_t\n+insert_xa5 (uint64_t insn,\n+\t int64_t value,\n+\t ppc_cpu_t dialect ATTRIBUTE_UNUSED,\n+\t const char **errmsg ATTRIBUTE_UNUSED)\n+{\n+ return insn | ((value & 0x1e) << 16) | ((value & 0x20) >> 3);\n+}\n+\n+static int64_t\n+extract_xa5 (uint64_t insn,\n+\t ppc_cpu_t dialect ATTRIBUTE_UNUSED,\n+\t int *invalid ATTRIBUTE_UNUSED)\n+{\n+ return ((insn << 3) & 0x20) | ((insn >> 16) & 0x1e);\n+}\n+\n /* The XA field in an XX3 form instruction. This is split. */\n \n static uint64_t\n@@ -2158,7 +2197,9 @@ insert_xa6a (uint64_t insn,\n \t const char **errmsg)\n {\n int64_t acc = (insn >> 23) & 0x7;\n- if ((value >> 2) == acc)\n+ /* Power10 doesn't allow VSRs to overlap ACCs in MMA instructions. */\n+ if ((dialect & PPC_OPCODE_FUTURE) == 0\n+ && (value >> 2) == acc)\n *errmsg = _(\"VSR overlaps ACC operand\");\n return insert_xa6 (insn, value, dialect, errmsg);\n }\n@@ -2170,11 +2211,31 @@ extract_xa6a (uint64_t insn,\n {\n int64_t acc = (insn >> 23) & 0x7;\n int64_t value = extract_xa6 (insn, dialect, invalid);\n- if ((value >> 2) == acc)\n+ /* Power10 doesn't allow VSRs to overlap ACCs in MMA instructions. */\n+ if ((dialect & PPC_OPCODE_FUTURE) == 0\n+ && (value >> 2) == acc)\n *invalid = 1;\n return value;\n }\n \n+/* The 5-bit XB field in an XX3 form instruction. This is split. */\n+\n+static uint64_t\n+insert_xb5 (uint64_t insn,\n+\t int64_t value,\n+\t ppc_cpu_t dialect ATTRIBUTE_UNUSED,\n+\t const char **errmsg ATTRIBUTE_UNUSED)\n+{\n+ return insn | ((value & 0x1e) << 11) | ((value & 0x20) >> 4);\n+}\n+\n+static int64_t\n+extract_xb5 (uint64_t insn,\n+\t ppc_cpu_t dialect ATTRIBUTE_UNUSED,\n+\t int *invalid ATTRIBUTE_UNUSED)\n+{\n+ return ((insn << 4) & 0x20) | ((insn >> 11) & 0x1e);\n+}\n /* The XB field in an XX3 form instruction. This is split. */\n \n static uint64_t\n@@ -2204,7 +2265,9 @@ insert_xb6a (uint64_t insn,\n \t const char **errmsg)\n {\n int64_t acc = (insn >> 23) & 0x7;\n- if ((value >> 2) == acc)\n+ /* Power10 doesn't allow VSRs to overlap ACCs in MMA instructions. */\n+ if ((dialect & PPC_OPCODE_FUTURE) == 0\n+ && (value >> 2) == acc)\n *errmsg = _(\"VSR overlaps ACC operand\");\n return insert_xb6 (insn, value, dialect, errmsg);\n }\n@@ -2216,7 +2279,9 @@ extract_xb6a (uint64_t insn,\n {\n int64_t acc = (insn >> 23) & 0x7;\n int64_t value = extract_xb6 (insn, dialect, invalid);\n- if ((value >> 2) == acc)\n+ /* Power10 doesn't allow VSRs to overlap ACCs in MMA instructions. */\n+ if ((dialect & PPC_OPCODE_FUTURE) == 0\n+ && (value >> 2) == acc)\n *invalid = 1;\n return value;\n }\n@@ -2824,9 +2889,17 @@ const struct powerpc_operand powerpc_operands[] =\n #define ACC BFF + 1\n { 0x7, 23, NULL, NULL, PPC_OPERAND_ACC },\n \n+ /* The DMR field in a MMA instruction. */\n+#define DMR ACC + 1\n+ { 0x7, 23, NULL, NULL, PPC_OPERAND_DMR },\n+\n+ /* The second DMR field in a two DMR operand MMA instruction. */\n+#define DMRAB DMR + 1\n+ { 0x7, 13, NULL, NULL, PPC_OPERAND_DMR },\n+\n /* An optional BF field. This is used for comparison instructions,\n in which an omitted BF field is taken as zero. */\n-#define OBF ACC + 1\n+#define OBF DMRAB + 1\n { 0x7, 23, NULL, NULL, PPC_OPERAND_CR_REG | PPC_OPERAND_OPTIONAL },\n \n /* The BFA field in an X or XL form instruction. */\n@@ -3656,6 +3729,7 @@ const struct powerpc_operand powerpc_operands[] =\n \n #define R RMC + 1\n #define MP R\n+#define P1 R\n { 0x1, 16, NULL, NULL, 0 },\n \n #define RIC R + 1\n@@ -3769,8 +3843,13 @@ const struct powerpc_operand powerpc_operands[] =\n #define XA6ap XA6a + 1\n { 0x3e, PPC_OPSHIFT_INV, insert_xa6a, extract_xa6a, PPC_OPERAND_VSR },\n \n+ /* The 5-bit XAp field in an MMA XX3 form instruction. This is split.\n+ This is like XA6, but must be even. */\n+#define XA5p XA6ap + 1\n+ { 0x3e, PPC_OPSHIFT_INV, insert_xa5, extract_xa5, PPC_OPERAND_VSR },\n+\n /* The XB field in an XX2 or XX3 form instruction. This is split. */\n-#define XB6 XA6ap + 1\n+#define XB6 XA5p + 1\n { 0x3f, PPC_OPSHIFT_INV, insert_xb6, extract_xb6, PPC_OPERAND_VSR },\n \n /* The XB field in an XX3 form instruction. This is split and\n@@ -3778,9 +3857,14 @@ const struct powerpc_operand powerpc_operands[] =\n #define XB6a XB6 + 1\n { 0x3f, PPC_OPSHIFT_INV, insert_xb6a, extract_xb6a, PPC_OPERAND_VSR },\n \n+ /* The 5-bit XBp field in an MMA XX3 form instruction. This is split.\n+ This is like XB6, but must be even. */\n+#define XB5p XB6a + 1\n+ { 0x3e, PPC_OPSHIFT_INV, insert_xb5, extract_xb5, PPC_OPERAND_VSR },\n+\n /* The XA and XB fields in an XX3 form instruction when they must be the same.\n This is used in extended mnemonics like xvmovdp. This is split. */\n-#define XAB6 XB6a + 1\n+#define XAB6 XB5p + 1\n { 0x3f, PPC_OPSHIFT_INV, insert_xab6, extract_xab6, PPC_OPERAND_VSR },\n \n /* The XC field in an XX4 form instruction. This is split. */\n@@ -3815,8 +3899,11 @@ const struct powerpc_operand powerpc_operands[] =\n #define PL SC2\n { 0x3, 16, insert_pl, extract_pl, PPC_OPERAND_OPTIONAL },\n \n+#define P2 PL + 1\n+ { 0x3, PPC_OPSHIFT_INV, insert_p2, extract_p2, 0 },\n+\n /* The 8-bit IMM8 field in a XX1 form instruction. */\n-#define IMM8 SC2 + 1\n+#define IMM8 P2 + 1\n { 0xff, 11, NULL, NULL, PPC_OPERAND_SIGNOPT },\n \n #define VX_OFF IMM8 + 1\n@@ -4452,15 +4539,22 @@ const unsigned int num_powerpc_operands = ARRAY_SIZE (powerpc_operands);\n \n /* An X_MASK with an accumulator register and the RA and RB fields fixed. */\n #define XACC_MASK (X_MASK | RA_MASK | RB_MASK | (3 << 21))\n+#define XDMR_MASK XACC_MASK\n \n-/* The mask for an XX3 form instruction with an accumulator register. */\n-#define XX3ACC_MASK (XX3 (0x3f, 0xff) | (3 << 21) | (1))\n+/* An X_MASK with two dense math register. */\n+#define XDMRDMR_MASK (X_MASK | RA_MASK | (3 << 21) | (3 << 11))\n \n /* The mask for an XX3 form instruction with the DM or SHW bits\n specified. */\n #define XX3DM_MASK (XX3 (0x3f, 0x1f) | (1 << 10))\n #define XX3SHW_MASK XX3DM_MASK\n \n+/* The masks for X* form instructions with an ACC/DMR register. */\n+#define XX2ACC_MASK (XX2 (0x3f, 0x1ff) | (3 << 21) | 1)\n+#define XX3ACC_MASK (XX3_MASK | (3 << 21) | 1)\n+#define XX3DMR_MASK (XX3ACC_MASK | (1 << 11))\n+#define XX2DMR_MASK (XX2ACC_MASK | (0xf << 17))\n+\n /* The mask for an XX4 form instruction. */\n #define XX4_MASK XX4 (0x3f, 0x3)\n \n@@ -7245,9 +7339,15 @@ const struct powerpc_opcode powerpc_opcodes[] = {\n {\"msgclrp\",\tXRTRA(31,174,0,0), XRTRA_MASK, POWER8,\t0,\t\t{RB}},\n {\"dcbtlse\",\tX(31,174),\tX_MASK,\t PPCCHLK,\tE500MC,\t\t{CT, RA0, RB}},\n \n+{\"dmxxmfacc\",\tXVA(31,177,0),\tXACC_MASK, POWER10, 0,\t\t{ACC}},\n {\"xxmfacc\",\tXVA(31,177,0),\tXACC_MASK, POWER10, 0,\t\t{ACC}},\n+{\"dmxxmtacc\",\tXVA(31,177,1),\tXACC_MASK, POWER10, 0,\t\t{ACC}},\n {\"xxmtacc\",\tXVA(31,177,1),\tXACC_MASK, POWER10, 0,\t\t{ACC}},\n+{\"dmsetdmrz\",\tXVA(31,177,2),\tXDMR_MASK, FUTURE, 0,\t\t{DMR}},\n+{\"dmsetaccz\",\tXVA(31,177,3),\tXACC_MASK, POWER10, 0,\t\t{ACC}},\n {\"xxsetaccz\",\tXVA(31,177,3),\tXACC_MASK, POWER10, 0,\t\t{ACC}},\n+{\"dmmr\",\tXVA(31,177,6),\tXDMRDMR_MASK,FUTURE, 0,\t\t{DMR, DMRAB}},\n+{\"dmxor\",\tXVA(31,177,7),\tXDMRDMR_MASK,FUTURE, 0,\t\t{DMR, DMRAB}},\n \n {\"mtmsrd\",\tX(31,178),\tXRLARB_MASK, PPC64,\t0,\t\t{RS, A_L}},\n \n@@ -8888,7 +8988,9 @@ const struct powerpc_opcode powerpc_opcodes[] = {\n {\"dqua\",\tZRC(59,3,0),\tZ2_MASK, POWER6,\tPPCVLE,\t\t{FRT,FRA,FRB,RMC}},\n {\"dqua.\",\tZRC(59,3,1),\tZ2_MASK, POWER6,\tPPCVLE,\t\t{FRT,FRA,FRB,RMC}},\n \n+{\"dmxvi8ger4pp\",XX3(59,2),\tXX3ACC_MASK, POWER10,\tPPCVLE,\t\t{ACC, XA6a, XB6a}},\n {\"xvi8ger4pp\",\tXX3(59,2),\tXX3ACC_MASK, POWER10,\tPPCVLE,\t\t{ACC, XA6a, XB6a}},\n+{\"dmxvi8ger4\",\tXX3(59,3),\tXX3ACC_MASK, POWER10,\tPPCVLE,\t\t{ACC, XA6a, XB6a}},\n {\"xvi8ger4\",\tXX3(59,3),\tXX3ACC_MASK, POWER10,\tPPCVLE,\t\t{ACC, XA6a, XB6a}},\n \n {\"fdivs\",\tA(59,18,0),\tAFRC_MASK, PPC,\tPPCEFS|PPCVLE,\t{FRT, FRA, FRB}},\n@@ -8940,8 +9042,10 @@ const struct powerpc_opcode powerpc_opcodes[] = {\n {\"dquai\",\tZRC(59,67,0),\tZ2_MASK, POWER6,\tPPCVLE,\t\t{TE, FRT,FRB,RMC}},\n {\"dquai.\",\tZRC(59,67,1),\tZ2_MASK, POWER6,\tPPCVLE,\t\t{TE, FRT,FRB,RMC}},\n \n-{\"xvf16ger2pp\",\tXX3(59,18),\tXX3ACC_MASK, POWER10,\tPPCVLE,\t\t{ACC, XA6a, XB6a}},\n-{\"xvf16ger2\",\tXX3(59,19),\tXX3ACC_MASK, POWER10,\tPPCVLE,\t\t{ACC, XA6a, XB6a}},\n+{\"dmxvf16ger2pp\",XX3(59,18),\tXX3ACC_MASK, POWER10,\tPPCVLE,\t\t{ACC, XA6a, XB6a}},\n+{\"xvf16ger2pp\",\t XX3(59,18),\tXX3ACC_MASK, POWER10,\tPPCVLE,\t\t{ACC, XA6a, XB6a}},\n+{\"dmxvf16ger2\",\t XX3(59,19),\tXX3ACC_MASK, POWER10,\tPPCVLE,\t\t{ACC, XA6a, XB6a}},\n+{\"xvf16ger2\",\t XX3(59,19),\tXX3ACC_MASK, POWER10,\tPPCVLE,\t\t{ACC, XA6a, XB6a}},\n \n {\"dscri\",\tZRC(59,98,0),\tZ_MASK,\t POWER6,\tPPCVLE,\t\t{FRT, FRA, SH16}},\n {\"dscri.\",\tZRC(59,98,1),\tZ_MASK,\t POWER6,\tPPCVLE,\t\t{FRT, FRA, SH16}},\n@@ -8949,30 +9053,40 @@ const struct powerpc_opcode powerpc_opcodes[] = {\n {\"drintx\",\tZRC(59,99,0),\tZ2_MASK, POWER6,\tPPCVLE,\t\t{R, FRT, FRB, RMC}},\n {\"drintx.\",\tZRC(59,99,1),\tZ2_MASK, POWER6,\tPPCVLE,\t\t{R, FRT, FRB, RMC}},\n \n+{\"dmxvf32gerpp\",XX3(59,26),\tXX3ACC_MASK, POWER10,\tPPCVLE,\t\t{ACC, XA6a, XB6a}},\n {\"xvf32gerpp\",\tXX3(59,26),\tXX3ACC_MASK, POWER10,\tPPCVLE,\t\t{ACC, XA6a, XB6a}},\n+{\"dmxvf32ger\",\tXX3(59,27),\tXX3ACC_MASK, POWER10,\tPPCVLE,\t\t{ACC, XA6a, XB6a}},\n {\"xvf32ger\",\tXX3(59,27),\tXX3ACC_MASK, POWER10,\tPPCVLE,\t\t{ACC, XA6a, XB6a}},\n \n {\"dcmpo\",\tX(59,130),\tX_MASK,\t POWER6,\tPPCVLE,\t\t{BF, FRA, FRB}},\n \n+{\"dmxvi4ger8pp\",XX3(59,34),\tXX3ACC_MASK, POWER10,\tPPCVLE,\t\t{ACC, XA6a, XB6a}},\n {\"xvi4ger8pp\",\tXX3(59,34),\tXX3ACC_MASK, POWER10,\tPPCVLE,\t\t{ACC, XA6a, XB6a}},\n+{\"dmxvi4ger8\",\tXX3(59,35),\tXX3ACC_MASK, POWER10,\tPPCVLE,\t\t{ACC, XA6a, XB6a}},\n {\"xvi4ger8\",\tXX3(59,35),\tXX3ACC_MASK, POWER10,\tPPCVLE,\t\t{ACC, XA6a, XB6a}},\n \n {\"dtstex\",\tX(59,162),\tX_MASK,\t POWER6,\tPPCVLE,\t\t{BF, FRA, FRB}},\n \n-{\"xvi16ger2spp\",XX3(59,42),\tXX3ACC_MASK, POWER10,\tPPCVLE,\t\t{ACC, XA6a, XB6a}},\n-{\"xvi16ger2s\",\tXX3(59,43),\tXX3ACC_MASK, POWER10,\tPPCVLE,\t\t{ACC, XA6a, XB6a}},\n+{\"dmxvi16ger2spp\",XX3(59,42),\tXX3ACC_MASK, POWER10,\tPPCVLE,\t\t{ACC, XA6a, XB6a}},\n+{\"xvi16ger2spp\", XX3(59,42),\tXX3ACC_MASK, POWER10,\tPPCVLE,\t\t{ACC, XA6a, XB6a}},\n+{\"dmxvi16ger2s\", XX3(59,43),\tXX3ACC_MASK, POWER10,\tPPCVLE,\t\t{ACC, XA6a, XB6a}},\n+{\"xvi16ger2s\",\t XX3(59,43),\tXX3ACC_MASK, POWER10,\tPPCVLE,\t\t{ACC, XA6a, XB6a}},\n \n {\"dtstdc\",\tZ(59,194),\tZ_MASK,\t POWER6,\tPPCVLE,\t\t{BF, FRA, DCM}},\n \n-{\"xvbf16ger2pp\",XX3(59,50),\tXX3ACC_MASK, POWER10,\tPPCVLE,\t\t{ACC, XA6a, XB6a}},\n-{\"xvbf16ger2\",\tXX3(59,51),\tXX3ACC_MASK, POWER10,\tPPCVLE,\t\t{ACC, XA6a, XB6a}},\n+{\"dmxvbf16ger2pp\",XX3(59,50),\tXX3ACC_MASK, POWER10,\tPPCVLE,\t\t{ACC, XA6a, XB6a}},\n+{\"xvbf16ger2pp\", XX3(59,50),\tXX3ACC_MASK, POWER10,\tPPCVLE,\t\t{ACC, XA6a, XB6a}},\n+{\"dmxvbf16ger2\", XX3(59,51),\tXX3ACC_MASK, POWER10,\tPPCVLE,\t\t{ACC, XA6a, XB6a}},\n+{\"xvbf16ger2\",\t XX3(59,51),\tXX3ACC_MASK, POWER10,\tPPCVLE,\t\t{ACC, XA6a, XB6a}},\n \n {\"dtstdg\",\tZ(59,226),\tZ_MASK,\t POWER6,\tPPCVLE,\t\t{BF, FRA, DGM}},\n \n {\"drintn\",\tZRC(59,227,0),\tZ2_MASK, POWER6,\tPPCVLE,\t\t{R, FRT, FRB, RMC}},\n {\"drintn.\",\tZRC(59,227,1),\tZ2_MASK, POWER6,\tPPCVLE,\t\t{R, FRT, FRB, RMC}},\n \n+{\"dmxvf64gerpp\",XX3(59,58),\tXX3ACC_MASK, POWER10,\tPPCVLE,\t\t{ACC, XA6ap, XB6a}},\n {\"xvf64gerpp\",\tXX3(59,58),\tXX3ACC_MASK, POWER10,\tPPCVLE,\t\t{ACC, XA6ap, XB6a}},\n+{\"dmxvf64ger\",\tXX3(59,59),\tXX3ACC_MASK, POWER10,\tPPCVLE,\t\t{ACC, XA6ap, XB6a}},\n {\"xvf64ger\",\tXX3(59,59),\tXX3ACC_MASK, POWER10,\tPPCVLE,\t\t{ACC, XA6ap, XB6a}},\n \n {\"dctdp\",\tXRC(59,258,0),\tX_MASK,\t POWER6,\tPPCVLE,\t\t{FRT, FRB}},\n@@ -8984,22 +9098,29 @@ const struct powerpc_opcode powerpc_opcodes[] = {\n {\"ddedpd\",\tXRC(59,322,0),\tX_MASK,\t POWER6,\tPPCVLE,\t\t{SP, FRT, FRB}},\n {\"ddedpd.\",\tXRC(59,322,1),\tX_MASK,\t POWER6,\tPPCVLE,\t\t{SP, FRT, FRB}},\n \n+{\"dmxvi16ger2\",\tXX3(59,75),\tXX3ACC_MASK, POWER10,\tPPCVLE,\t\t{ACC, XA6a, XB6a}},\n {\"xvi16ger2\",\tXX3(59,75),\tXX3ACC_MASK, POWER10,\tPPCVLE,\t\t{ACC, XA6a, XB6a}},\n \n-{\"xvf16ger2np\",\tXX3(59,82),\tXX3ACC_MASK, POWER10,\tPPCVLE,\t\t{ACC, XA6a, XB6a}},\n+{\"dmxvf16ger2np\", XX3(59,82),\tXX3ACC_MASK, POWER10,\tPPCVLE,\t\t{ACC, XA6a, XB6a}},\n+{\"xvf16ger2np\",\t XX3(59,82),\tXX3ACC_MASK, POWER10,\tPPCVLE,\t\t{ACC, XA6a, XB6a}},\n \n {\"dxex\",\tXRC(59,354,0),\tX_MASK,\t POWER6,\tPPCVLE,\t\t{FRT, FRB}},\n {\"dxex.\",\tXRC(59,354,1),\tX_MASK,\t POWER6,\tPPCVLE,\t\t{FRT, FRB}},\n \n-{\"xvf32gernp\",\tXX3(59,90),\tXX3ACC_MASK, POWER10,\tPPCVLE,\t\t{ACC, XA6a, XB6a}},\n+{\"dmxvf32gernp\", XX3(59,90),\tXX3ACC_MASK, POWER10,\tPPCVLE,\t\t{ACC, XA6a, XB6a}},\n+{\"xvf32gernp\",\t XX3(59,90),\tXX3ACC_MASK, POWER10,\tPPCVLE,\t\t{ACC, XA6a, XB6a}},\n \n-{\"xvi8ger4spp\",\tXX3(59,99),\tXX3ACC_MASK, POWER10,\tPPCVLE,\t\t{ACC, XA6a, XB6a}},\n+{\"dmxvi8ger4spp\", XX3(59,99),\tXX3ACC_MASK, POWER10,\tPPCVLE,\t\t{ACC, XA6a, XB6a}},\n+{\"xvi8ger4spp\",\t XX3(59,99),\tXX3ACC_MASK, POWER10,\tPPCVLE,\t\t{ACC, XA6a, XB6a}},\n \n-{\"xvi16ger2pp\",\tXX3(59,107),\tXX3ACC_MASK, POWER10,\tPPCVLE,\t\t{ACC, XA6a, XB6a}},\n+{\"dmxvi16ger2pp\", XX3(59,107),\tXX3ACC_MASK, POWER10,\tPPCVLE,\t\t{ACC, XA6a, XB6a}},\n+{\"xvi16ger2pp\",\t XX3(59,107),\tXX3ACC_MASK, POWER10,\tPPCVLE,\t\t{ACC, XA6a, XB6a}},\n \n-{\"xvbf16ger2np\",XX3(59,114),\tXX3ACC_MASK, POWER10,\tPPCVLE,\t\t{ACC, XA6a, XB6a}},\n+{\"dmxvbf16ger2np\",XX3(59,114),\tXX3ACC_MASK, POWER10,\tPPCVLE,\t\t{ACC, XA6a, XB6a}},\n+{\"xvbf16ger2np\", XX3(59,114),\tXX3ACC_MASK, POWER10,\tPPCVLE,\t\t{ACC, XA6a, XB6a}},\n \n-{\"xvf64gernp\",\tXX3(59,122),\tXX3ACC_MASK, POWER10,\tPPCVLE,\t\t{ACC, XA6ap, XB6a}},\n+{\"dmxvf64gernp\", XX3(59,122),\tXX3ACC_MASK, POWER10,\tPPCVLE,\t\t{ACC, XA6ap, XB6a}},\n+{\"xvf64gernp\",\t XX3(59,122),\tXX3ACC_MASK, POWER10,\tPPCVLE,\t\t{ACC, XA6ap, XB6a}},\n \n {\"dsub\",\tXRC(59,514,0),\tX_MASK,\t POWER6,\tPPCVLE,\t\t{FRT, FRA, FRB}},\n {\"dsub.\",\tXRC(59,514,1),\tX_MASK,\t POWER6,\tPPCVLE,\t\t{FRT, FRA, FRB}},\n@@ -9007,8 +9128,10 @@ const struct powerpc_opcode powerpc_opcodes[] = {\n {\"ddiv\",\tXRC(59,546,0),\tX_MASK,\t POWER6,\tPPCVLE,\t\t{FRT, FRA, FRB}},\n {\"ddiv.\",\tXRC(59,546,1),\tX_MASK,\t POWER6,\tPPCVLE,\t\t{FRT, FRA, FRB}},\n \n-{\"xvf16ger2pn\",\tXX3(59,146),\tXX3ACC_MASK, POWER10,\tPPCVLE,\t\t{ACC, XA6a, XB6a}},\n+{\"dmxvf16ger2pn\", XX3(59,146),\tXX3ACC_MASK, POWER10,\tPPCVLE,\t\t{ACC, XA6a, XB6a}},\n+{\"xvf16ger2pn\",\t XX3(59,146),\tXX3ACC_MASK, POWER10,\tPPCVLE,\t\t{ACC, XA6a, XB6a}},\n \n+{\"dmxvf32gerpn\",XX3(59,154),\tXX3ACC_MASK, POWER10,\tPPCVLE,\t\t{ACC, XA6a, XB6a}},\n {\"xvf32gerpn\",\tXX3(59,154),\tXX3ACC_MASK, POWER10,\tPPCVLE,\t\t{ACC, XA6a, XB6a}},\n \n {\"dcmpu\",\tX(59,642),\tX_MASK,\t POWER6,\tPPCVLE,\t\t{BF, FRA, FRB}},\n@@ -9016,8 +9139,10 @@ const struct powerpc_opcode powerpc_opcodes[] = {\n {\"dtstsf\",\tX(59,674),\tX_MASK,\t POWER6,\tPPCVLE,\t\t{BF, FRA, FRB}},\n {\"dtstsfi\",\tX(59,675),\tX_MASK|1<<22,POWER9,\tPPCVLE,\t\t{BF, UIM6, FRB}},\n \n-{\"xvbf16ger2pn\",XX3(59,178),\tXX3ACC_MASK, POWER10,\tPPCVLE,\t\t{ACC, XA6a, XB6a}},\n+{\"dmxvbf16ger2pn\",XX3(59,178),\tXX3ACC_MASK, POWER10,\tPPCVLE,\t\t{ACC, XA6a, XB6a}},\n+{\"xvbf16ger2pn\", XX3(59,178),\tXX3ACC_MASK, POWER10,\tPPCVLE,\t\t{ACC, XA6a, XB6a}},\n \n+{\"dmxvf64gerpn\",XX3(59,186),\tXX3ACC_MASK, POWER10,\tPPCVLE,\t\t{ACC, XA6ap, XB6a}},\n {\"xvf64gerpn\",\tXX3(59,186),\tXX3ACC_MASK, POWER10,\tPPCVLE,\t\t{ACC, XA6ap, XB6a}},\n \n {\"drsp\",\tXRC(59,770,0),\tX_MASK,\t POWER6,\tPPCVLE,\t\t{FRT, FRB}},\n@@ -9029,7 +9154,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {\n {\"denbcd\",\tXRC(59,834,0),\tX_MASK,\t POWER6,\tPPCVLE,\t\t{S, FRT, FRB}},\n {\"denbcd.\",\tXRC(59,834,1),\tX_MASK,\t POWER6,\tPPCVLE,\t\t{S, FRT, FRB}},\n \n-{\"xvf16ger2nn\",\tXX3(59,210),\tXX3ACC_MASK, POWER10,\tPPCVLE,\t\t{ACC, XA6a, XB6a}},\n+{\"dmxvf16ger2nn\", XX3(59,210),\tXX3ACC_MASK, POWER10,\tPPCVLE,\t\t{ACC, XA6a, XB6a}},\n+{\"xvf16ger2nn\",\t XX3(59,210),\tXX3ACC_MASK, POWER10,\tPPCVLE,\t\t{ACC, XA6a, XB6a}},\n \n {\"fcfids\",\tXRC(59,846,0),\tXRA_MASK, POWER7|PPCA2,\tPPCVLE,\t\t{FRT, FRB}},\n {\"fcfids.\",\tXRC(59,846,1),\tXRA_MASK, POWER7|PPCA2,\tPPCVLE,\t\t{FRT, FRB}},\n@@ -9037,13 +9163,16 @@ const struct powerpc_opcode powerpc_opcodes[] = {\n {\"diex\",\tXRC(59,866,0),\tX_MASK,\t POWER6,\tPPCVLE,\t\t{FRT, FRA, FRB}},\n {\"diex.\",\tXRC(59,866,1),\tX_MASK,\t POWER6,\tPPCVLE,\t\t{FRT, FRA, FRB}},\n \n+{\"dmxvf32gernn\",XX3(59,218),\tXX3ACC_MASK, POWER10,\tPPCVLE,\t\t{ACC, XA6a, XB6a}},\n {\"xvf32gernn\",\tXX3(59,218),\tXX3ACC_MASK, POWER10,\tPPCVLE,\t\t{ACC, XA6a, XB6a}},\n \n-{\"xvbf16ger2nn\",XX3(59,242),\tXX3ACC_MASK, POWER10,\tPPCVLE,\t\t{ACC, XA6a, XB6a}},\n+{\"dmxvbf16ger2nn\",XX3(59,242),\tXX3ACC_MASK, POWER10,\tPPCVLE,\t\t{ACC, XA6a, XB6a}},\n+{\"xvbf16ger2nn\", XX3(59,242),\tXX3ACC_MASK, POWER10,\tPPCVLE,\t\t{ACC, XA6a, XB6a}},\n \n {\"fcfidus\",\tXRC(59,974,0),\tXRA_MASK, POWER7|PPCA2,\tPPCVLE,\t\t{FRT, FRB}},\n {\"fcfidus.\",\tXRC(59,974,1),\tXRA_MASK, POWER7|PPCA2,\tPPCVLE,\t\t{FRT, FRB}},\n \n+{\"dmxvf64gernn\",XX3(59,250),\tXX3ACC_MASK, POWER10,\tPPCVLE,\t\t{ACC, XA6ap, XB6a}},\n {\"xvf64gernn\",\tXX3(59,250),\tXX3ACC_MASK, POWER10,\tPPCVLE,\t\t{ACC, XA6ap, XB6a}},\n \n {\"xsaddsp\",\tXX3(60,0),\tXX3_MASK, PPCVSX2,\tPPCVLE,\t\t{XT6, XA6, XB6}},\n@@ -9220,6 +9349,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {\n {\"xvnegsp\",\tXX2(60,441),\tXX2_MASK, PPCVSX,\tPPCVLE,\t\t{XT6, XB6}},\n {\"xvmaxdp\",\tXX3(60,224),\tXX3_MASK, PPCVSX,\tPPCVLE,\t\t{XT6, XA6, XB6}},\n {\"xvnmaddadp\",\tXX3(60,225),\tXX3_MASK, PPCVSX,\tPPCVLE,\t\t{XT6, XA6, XB6}},\n+{\"dmxxextfdmr512\",XX3(60,226),\tXX3DMR_MASK, FUTURE,\tPPCVLE,\t\t{XA5p, XB5p, DMR, P1}},\n {\"xvcvdpuxds\",\tXX2(60,456),\tXX2_MASK, PPCVSX,\tPPCVLE,\t\t{XT6, XB6}},\n {\"xvcvspdp\",\tXX2(60,457),\tXX2_MASK, PPCVSX,\tPPCVLE,\t\t{XT6, XB6}},\n {\"xxgenpcvbm\",\tX(60,916),\tXX1_MASK, POWER10,\tPPCVLE,\t\t{XT6, VB, UIMM}},\n@@ -9227,6 +9357,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {\n {\"xsiexpdp\",\tX(60,918),\tXX1_MASK, PPCVSX3,\tPPCVLE,\t\t{XT6, RA, RB}},\n {\"xvmindp\",\tXX3(60,232),\tXX3_MASK, PPCVSX,\tPPCVLE,\t\t{XT6, XA6, XB6}},\n {\"xvnmaddmdp\",\tXX3(60,233),\tXX3_MASK, PPCVSX,\tPPCVLE,\t\t{XT6, XA6, XB6}},\n+{\"dmxxinstdmr512\",XX3(60,234),\tXX3DMR_MASK, FUTURE,\tPPCVLE,\t\t{DMR, XA5p, XB5p,P1}},\n {\"xvcvdpsxds\",\tXX2(60,472),\tXX2_MASK, PPCVSX,\tPPCVLE,\t\t{XT6, XB6}},\n {\"xvabsdp\",\tXX2(60,473),\tXX2_MASK, PPCVSX,\tPPCVLE,\t\t{XT6, XB6}},\n {\"xxgenpcvwm\",\tX(60,948),\tXX1_MASK, POWER10,\tPPCVLE,\t\t{XT6, VB, UIMM}},\n@@ -9247,6 +9378,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {\n {\"xvmovdp\",\tXX3(60,240),\tXX3_MASK, PPCVSX,\tPPCVLE|EXT,\t{XT6, XAB6}},\n {\"xvcpsgndp\",\tXX3(60,240),\tXX3_MASK, PPCVSX,\tPPCVLE,\t\t{XT6, XA6, XB6}},\n {\"xvnmsubadp\",\tXX3(60,241),\tXX3_MASK, PPCVSX,\tPPCVLE,\t\t{XT6, XA6, XB6}},\n+{\"dmxxextfdmr256\",XX2(60,484),\tXX2DMR_MASK, FUTURE,\tPPCVLE,\t\t{XB5p, DMR, P2}},\n+{\"dmxxinstdmr256\",XX2(60,485),\tXX2DMR_MASK, FUTURE,\tPPCVLE,\t\t{DMR, XB5p, P2}},\n {\"xvcvuxddp\",\tXX2(60,488),\tXX2_MASK, PPCVSX,\tPPCVLE,\t\t{XT6, XB6}},\n {\"xvnabsdp\",\tXX2(60,489),\tXX2_MASK, PPCVSX,\tPPCVLE,\t\t{XT6, XB6}},\n {\"xvtstdcdp\",\tXX2(60,490), XX2DCMXS_MASK, PPCVSX3,\tPPCVLE,\t\t{XT6, XB6, DCMXS}},\n@@ -9624,34 +9757,63 @@ const struct powerpc_opcode prefix_opcodes[] = {\n {\"plq\",\t\t P8LS|OP(56),\t P_D_MASK,\tPOWER10, 0,\t{RTQ, D34, PRAQ, PCREL}},\n {\"pld\",\t\t P8LS|OP(57),\t P_D_MASK,\tPOWER10, 0,\t{RT, D34, PRA0, PCREL}},\n {\"plxvp\",\t P8LS|OP(58),\t P_D_MASK,\tPOWER10, 0,\t{XTP, D34, PRA0, PCREL}},\n+{\"pmdmxvi8ger4pp\",PMMIRR|XX3(59,2), P_GER4_MASK,\tPOWER10, 0,\t{ACC, XA6a, XB6a, XMSK, YMSK, PMSK4}},\n {\"pmxvi8ger4pp\", PMMIRR|XX3(59,2), P_GER4_MASK,\tPOWER10, 0,\t{ACC, XA6a, XB6a, XMSK, YMSK, PMSK4}},\n+{\"pmdmxvi8ger4\", PMMIRR|XX3(59,3), P_GER4_MASK,\tPOWER10, 0,\t{ACC, XA6a, XB6a, XMSK, YMSK, PMSK4}},\n {\"pmxvi8ger4\",\t PMMIRR|XX3(59,3), P_GER4_MASK,\tPOWER10, 0,\t{ACC, XA6a, XB6a, XMSK, YMSK, PMSK4}},\n+{\"pmdmxvf16ger2pp\",PMMIRR|XX3(59,18), P_GER2_MASK,\tPOWER10, 0,\t{ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}},\n {\"pmxvf16ger2pp\", PMMIRR|XX3(59,18), P_GER2_MASK,\tPOWER10, 0,\t{ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}},\n+{\"pmdmxvf16ger2\", PMMIRR|XX3(59,19), P_GER2_MASK,\tPOWER10, 0,\t{ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}},\n {\"pmxvf16ger2\",\t PMMIRR|XX3(59,19), P_GER2_MASK,\tPOWER10, 0,\t{ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}},\n+{\"pmdmxvf32gerpp\",PMMIRR|XX3(59,26), P_GER_MASK,\tPOWER10, 0,\t{ACC, XA6a, XB6a, XMSK, YMSK}},\n {\"pmxvf32gerpp\", PMMIRR|XX3(59,26), P_GER_MASK,\tPOWER10, 0,\t{ACC, XA6a, XB6a, XMSK, YMSK}},\n+{\"pmdmxvf32ger\", PMMIRR|XX3(59,27), P_GER_MASK,\tPOWER10, 0,\t{ACC, XA6a, XB6a, XMSK, YMSK}},\n {\"pmxvf32ger\",\t PMMIRR|XX3(59,27), P_GER_MASK,\tPOWER10, 0,\t{ACC, XA6a, XB6a, XMSK, YMSK}},\n+{\"pmdmxvi4ger8pp\",PMMIRR|XX3(59,34), P_GER8_MASK,\tPOWER10, 0,\t{ACC, XA6a, XB6a, XMSK, YMSK, PMSK8}},\n {\"pmxvi4ger8pp\", PMMIRR|XX3(59,34), P_GER8_MASK,\tPOWER10, 0,\t{ACC, XA6a, XB6a, XMSK, YMSK, PMSK8}},\n+{\"pmdmxvi4ger8\", PMMIRR|XX3(59,35), P_GER8_MASK,\tPOWER10, 0,\t{ACC, XA6a, XB6a, XMSK, YMSK, PMSK8}},\n {\"pmxvi4ger8\",\t PMMIRR|XX3(59,35), P_GER8_MASK,\tPOWER10, 0,\t{ACC, XA6a, XB6a, XMSK, YMSK, PMSK8}},\n+{\"pmdmxvi16ger2spp\",PMMIRR|XX3(59,42), P_GER2_MASK,\tPOWER10, 0,\t{ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}},\n {\"pmxvi16ger2spp\",PMMIRR|XX3(59,42), P_GER2_MASK,\tPOWER10, 0,\t{ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}},\n+{\"pmdmxvi16ger2s\",PMMIRR|XX3(59,43), P_GER2_MASK,\tPOWER10, 0,\t{ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}},\n {\"pmxvi16ger2s\", PMMIRR|XX3(59,43), P_GER2_MASK,\tPOWER10, 0,\t{ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}},\n+{\"pmdmxvbf16ger2pp\",PMMIRR|XX3(59,50), P_GER2_MASK,\tPOWER10, 0,\t{ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}},\n {\"pmxvbf16ger2pp\",PMMIRR|XX3(59,50), P_GER2_MASK,\tPOWER10, 0,\t{ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}},\n+{\"pmdmxvbf16ger2\",PMMIRR|XX3(59,51), P_GER2_MASK,\tPOWER10, 0,\t{ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}},\n {\"pmxvbf16ger2\", PMMIRR|XX3(59,51), P_GER2_MASK,\tPOWER10, 0,\t{ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}},\n+{\"pmdmxvf64gerpp\",PMMIRR|XX3(59,58), P_GER64_MASK,\tPOWER10, 0,\t{ACC, XA6ap, XB6a, XMSK, YMSK2}},\n {\"pmxvf64gerpp\", PMMIRR|XX3(59,58), P_GER64_MASK,\tPOWER10, 0,\t{ACC, XA6ap, XB6a, XMSK, YMSK2}},\n+{\"pmdmxvf64ger\", PMMIRR|XX3(59,59), P_GER64_MASK,\tPOWER10, 0,\t{ACC, XA6ap, XB6a, XMSK, YMSK2}},\n {\"pmxvf64ger\",\t PMMIRR|XX3(59,59), P_GER64_MASK,\tPOWER10, 0,\t{ACC, XA6ap, XB6a, XMSK, YMSK2}},\n+{\"pmdmxvi16ger2\", PMMIRR|XX3(59,75), P_GER2_MASK,\tPOWER10, 0,\t{ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}},\n {\"pmxvi16ger2\", PMMIRR|XX3(59,75), P_GER2_MASK,\tPOWER10, 0,\t{ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}},\n+{\"pmdmxvf16ger2np\",PMMIRR|XX3(59,82), P_GER2_MASK,\tPOWER10, 0,\t{ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}},\n {\"pmxvf16ger2np\", PMMIRR|XX3(59,82), P_GER2_MASK,\tPOWER10, 0,\t{ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}},\n+{\"pmdmxvf32gernp\",PMMIRR|XX3(59,90), P_GER_MASK,\tPOWER10, 0,\t{ACC, XA6a, XB6a, XMSK, YMSK}},\n {\"pmxvf32gernp\", PMMIRR|XX3(59,90), P_GER_MASK,\tPOWER10, 0,\t{ACC, XA6a, XB6a, XMSK, YMSK}},\n+{\"pmdmxvi8ger4spp\ 100 68426 100 68276 100 150 1258k 2830 --:--:-- --:--:-- --:--:-- 1260k ",PMMIRR|XX3(59,99), P_GER4_MASK,\tPOWER10, 0,\t{ACC, XA6a, XB6a, XMSK, YMSK, PMSK4}},\n {\"pmxvi8ger4spp\", PMMIRR|XX3(59,99), P_GER4_MASK,\tPOWER10, 0,\t{ACC, XA6a, XB6a, XMSK, YMSK, PMSK4}},\n+{\"pmdmxvi16ger2pp\",PMMIRR|XX3(59,107), P_GER2_MASK,\tPOWER10, 0,\t{ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}},\n {\"pmxvi16ger2pp\", PMMIRR|XX3(59,107), P_GER2_MASK,\tPOWER10, 0,\t{ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}},\n+{\"pmdmxvbf16ger2np\",PMMIRR|XX3(59,114),P_GER2_MASK,\tPOWER10, 0,\t{ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}},\n {\"pmxvbf16ger2np\",PMMIRR|XX3(59,114), P_GER2_MASK,\tPOWER10, 0,\t{ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}},\n+{\"pmdmxvf64gernp\",PMMIRR|XX3(59,122), P_GER64_MASK,\tPOWER10, 0,\t{ACC, XA6ap, XB6a, XMSK, YMSK2}},\n {\"pmxvf64gernp\", PMMIRR|XX3(59,122), P_GER64_MASK,\tPOWER10, 0,\t{ACC, XA6ap, XB6a, XMSK, YMSK2}},\n+{\"pmdmxvf16ger2pn\",PMMIRR|XX3(59,146), P_GER2_MASK,\tPOWER10, 0,\t{ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}},\n {\"pmxvf16ger2pn\", PMMIRR|XX3(59,146), P_GER2_MASK,\tPOWER10, 0,\t{ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}},\n+{\"pmdmxvf32gerpn\",PMMIRR|XX3(59,154), P_GER_MASK,\tPOWER10, 0,\t{ACC, XA6a, XB6a, XMSK, YMSK}},\n {\"pmxvf32gerpn\", PMMIRR|XX3(59,154), P_GER_MASK,\tPOWER10, 0,\t{ACC, XA6a, XB6a, XMSK, YMSK}},\n+{\"pmdmxvbf16ger2pn\",PMMIRR|XX3(59,178),P_GER2_MASK,\tPOWER10, 0,\t{ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}},\n {\"pmxvbf16ger2pn\",PMMIRR|XX3(59,178), P_GER2_MASK,\tPOWER10, 0,\t{ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}},\n+{\"pmdmxvf64gerpn\",PMMIRR|XX3(59,186), P_GER64_MASK,\tPOWER10, 0,\t{ACC, XA6ap, XB6a, XMSK, YMSK2}},\n {\"pmxvf64gerpn\", PMMIRR|XX3(59,186), P_GER64_MASK,\tPOWER10, 0,\t{ACC, XA6ap, XB6a, XMSK, YMSK2}},\n+{\"pmdmxvf16ger2nn\",PMMIRR|XX3(59,210), P_GER2_MASK,\tPOWER10, 0,\t{ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}},\n {\"pmxvf16ger2nn\", PMMIRR|XX3(59,210), P_GER2_MASK,\tPOWER10, 0,\t{ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}},\n+{\"pmdmxvf32gernn\",PMMIRR|XX3(59,218), P_GER_MASK,\tPOWER10, 0,\t{ACC, XA6a, XB6a, XMSK, YMSK}},\n {\"pmxvf32gernn\", PMMIRR|XX3(59,218), P_GER_MASK,\tPOWER10, 0,\t{ACC, XA6a, XB6a, XMSK, YMSK}},\n+{\"pmdmxvbf16ger2nn\",PMMIRR|XX3(59,242),P_GER2_MASK,\tPOWER10, 0,\t{ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}},\n {\"pmxvbf16ger2nn\",PMMIRR|XX3(59,242), P_GER2_MASK,\tPOWER10, 0,\t{ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}},\n+{\"pmdmxvf64gernn\",PMMIRR|XX3(59,250), P_GER64_MASK,\tPOWER10, 0,\t{ACC, XA6ap, XB6a, XMSK, YMSK2}},\n {\"pmxvf64gernn\", PMMIRR|XX3(59,250), P_GER64_MASK,\tPOWER10, 0,\t{ACC, XA6ap, XB6a, XMSK, YMSK2}},\n {\"pstq\",\t P8LS|OP(60),\t P_D_MASK,\tPOWER10, 0,\t{RSQ, D34, PRA0, PCREL}},\n {\"pstd\",\t P8LS|OP(61),\t P_D_MASK,\tPOWER10, 0,\t{RS, D34, PRA0, PCREL}},\n","prefixes":["COMMITTED"]}+ exit 1 Build step 'Execute shell' marked build as failure Finished: FAILURE