Started by user snail Running as SYSTEM [EnvInject] - Loading node environment variables. Building remotely on docker-jenkins-agent in workspace /home/jenkins/agent/workspace/binutils-gdb [WS-CLEANUP] Deleting project workspace... [WS-CLEANUP] Deferred wipeout is used... [WS-CLEANUP] Done The recommended git tool is: NONE using credential 0adb5fc7-caa2-429d-97d2-c7fa2fa1d884 Cloning the remote Git repository Using shallow clone with depth 1 Avoid fetching tags Cloning repository git@github.com:plctlab/patchwork-binutils-gdb.git > git init /home/jenkins/agent/workspace/binutils-gdb # timeout=10 Fetching upstream changes from git@github.com:plctlab/patchwork-binutils-gdb.git > git --version # timeout=10 > git --version # 'git version 2.37.2' using GIT_SSH to set credentials patchwork github wangliu-iscas git ssh key Verifying host key using known hosts file, will automatically accept unseen keys > git fetch --no-tags --force --progress --depth=1 -- git@github.com:plctlab/patchwork-binutils-gdb.git +refs/heads/*:refs/remotes/origin/* # timeout=10 > git config remote.origin.url git@github.com:plctlab/patchwork-binutils-gdb.git # timeout=10 > git config --add remote.origin.fetch +refs/heads/*:refs/remotes/origin/* # timeout=10 Avoid second fetch > git rev-parse refs/remotes/origin/master^{commit} # timeout=10 Checking out Revision 324998b47364528f407666512015370c12ab83a1 (refs/remotes/origin/master) > git config core.sparsecheckout # timeout=10 > git checkout -f 324998b47364528f407666512015370c12ab83a1 # timeout=10 Commit message: "Automatic date update in version.in" > git rev-list --no-walk 324998b47364528f407666512015370c12ab83a1 # timeout=10 [EnvInject] - Mask passwords that will be passed as build parameters. [EnvInject] - Executing scripts and injecting environment variables after the SCM step. [EnvInject] - Injecting as environment variables the properties content GITHUB_REPO=https://github.com/plctlab/patchwork-binutils-gdb PATCHWORK_URL=https://patchwork.plctlab.org [EnvInject] - Variables injected successfully. [binutils-gdb] $ /usr/bin/env bash /tmp/jenkins11257582287573373425.sh + git config pw.server https://patchwork.plctlab.org/api/1.2/ + git config pw.project binutils-gdb + git config pw.token [*******] ++ date +%Y-%m + now_date=2023-07 ++ date +%Y + now_date_year=2023 + bundle_name=binutils-gdb_2023-07 ++ curl -s -H 'Authorization: Token [*******]' 'https://patchwork.plctlab.org/api/1.2/bundles/?project=binutils-gdb&per_page=999' + bundle_response='[{"id":6,"url":"https://patchwork.plctlab.org/api/1.2/bundles/6/","web_url":"https://patchwork.plctlab.org/bundle/patchwork-bot/binutils-gdb_2022-10/","project":{"id":2,"url":"https://patchwork.plctlab.org/api/1.2/projects/2/","name":"binutils-gdb","link_name":"binutils-gdb","list_id":"binutils.sourceware.org","list_email":"binutils@sourceware.org","web_url":"https://github.com/wangliu-iscas/Patchwork-Bundles/blob/main/binutils-gdb.md","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"name":"binutils-gdb_2022-10","owner":{"id":3,"url":"https://patchwork.plctlab.org/api/1.2/users/3/","username":"patchwork-bot","first_name":"","last_name":"","email":"ouuuleilei@gmail.com"},"patches":[{"id":1592,"url":"https://patchwork.plctlab.org/api/1.2/patches/1592/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/385d01fd-7e57-1f3f-1bae-30aa0c313d63@suse.com/","msgid":"<385d01fd-7e57-1f3f-1bae-30aa0c313d63@suse.com>","list_archive_url":null,"date":"2022-09-30T11:59:45","name":"[3/4] RISC-V/gas: don'\''t open-code insn_length()","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/385d01fd-7e57-1f3f-1bae-30aa0c313d63@suse.com/mbox/"},{"id":1594,"url":"https://patchwork.plctlab.org/api/1.2/patches/1594/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f5757acf-7b90-a0e3-5eea-3b97cc226930@suse.com/","msgid":"","list_archive_url":null,"date":"2022-09-30T12:00:12","name":"[4/4] RISC-V/gas: allow generating up to 176-bit instructions with .insn","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f5757acf-7b90-a0e3-5eea-3b97cc226930@suse.com/mbox/"},{"id":1596,"url":"https://patchwork.plctlab.org/api/1.2/patches/1596/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930140503.38233-1-chigot@adacore.com/","msgid":"<20220930140503.38233-1-chigot@adacore.com>","list_archive_url":null,"date":"2022-09-30T14:05:03","name":"ld/testsuite: consistently add board_ldflags when linking with GCC","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930140503.38233-1-chigot@adacore.com/mbox/"},{"id":1619,"url":"https://patchwork.plctlab.org/api/1.2/patches/1619/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221001014451.532772-1-maskray@google.com/","msgid":"<20221001014451.532772-1-maskray@google.com>","list_archive_url":null,"date":"2022-10-01T01:44:51","name":"gold, dwp: support zstd compressed input debug sections [PR 29641]","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221001014451.532772-1-maskray@google.com/mbox/"},{"id":1620,"url":"https://patchwork.plctlab.org/api/1.2/patches/1620/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221001023846.590825-1-maskray@google.com/","msgid":"<20221001023846.590825-1-maskray@google.com>","list_archive_url":null,"date":"2022-10-01T02:38:46","name":"gold: add --compress-debug-sections=zstd [PR 29641]","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221001023846.590825-1-maskray@google.com/mbox/"},{"id":1623,"url":"https://patchwork.plctlab.org/api/1.2/patches/1623/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b4477c7f666bdeb7f8e998633c7b0cb62310b9ef.1664599545.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-01T04:45:52","name":"[RFC,1/1] RISC-V: Implement common register pair framework","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b4477c7f666bdeb7f8e998633c7b0cb62310b9ef.1664599545.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1625,"url":"https://patchwork.plctlab.org/api/1.2/patches/1625/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/53a265a1f14d17a6f7b106082f610994c5d546e0.1664602025.git.research_trasio@irq.a4lg.com/","msgid":"<53a265a1f14d17a6f7b106082f610994c5d546e0.1664602025.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-01T05:27:31","name":"[RFC,1/1] RISC-V: Implement extension variants","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/53a265a1f14d17a6f7b106082f610994c5d546e0.1664602025.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1626,"url":"https://patchwork.plctlab.org/api/1.2/patches/1626/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8db04962aba9c780f133840a8934353a58f223fe.1664602716.git.research_trasio@irq.a4lg.com/","msgid":"<8db04962aba9c780f133840a8934353a58f223fe.1664602716.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-01T05:39:26","name":"[1/1] RISC-V: Move supervisor instructions after all unprivileged ones","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8db04962aba9c780f133840a8934353a58f223fe.1664602716.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1627,"url":"https://patchwork.plctlab.org/api/1.2/patches/1627/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221001062057.681440-1-maskray@google.com/","msgid":"<20221001062057.681440-1-maskray@google.com>","list_archive_url":null,"date":"2022-10-01T06:20:57","name":"readelf: support zstd compressed debug sections [PR 29640]","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221001062057.681440-1-maskray@google.com/mbox/"},{"id":1631,"url":"https://patchwork.plctlab.org/api/1.2/patches/1631/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/619f112539c0bdecd58e25664f1250a3479a37f5.1664707612.git.aburgess@redhat.com/","msgid":"<619f112539c0bdecd58e25664f1250a3479a37f5.1664707612.git.aburgess@redhat.com>","list_archive_url":null,"date":"2022-10-02T10:47:52","name":"[PATCHv2,2/2] opcodes/arm: add disassembler styling for arm","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/619f112539c0bdecd58e25664f1250a3479a37f5.1664707612.git.aburgess@redhat.com/mbox/"},{"id":1635,"url":"https://patchwork.plctlab.org/api/1.2/patches/1635/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221002185433.gl7dvytfh5wthifx@lug-owl.de/","msgid":"<20221002185433.gl7dvytfh5wthifx@lug-owl.de>","list_archive_url":null,"date":"2022-10-02T18:54:33","name":"diagnostics.h: GCC 13 got -Wself-move, breaks GDB build","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221002185433.gl7dvytfh5wthifx@lug-owl.de/mbox/"},{"id":1637,"url":"https://patchwork.plctlab.org/api/1.2/patches/1637/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003014313.28766-1-mark@harmstone.com/","msgid":"<20221003014313.28766-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-03T01:43:12","name":"[1/2] ld: Add --pdb option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003014313.28766-1-mark@harmstone.com/mbox/"},{"id":1638,"url":"https://patchwork.plctlab.org/api/1.2/patches/1638/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003014313.28766-2-mark@harmstone.com/","msgid":"<20221003014313.28766-2-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-03T01:43:13","name":"[2/2] ld: Add minimal pdb generation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003014313.28766-2-mark@harmstone.com/mbox/"},{"id":1640,"url":"https://patchwork.plctlab.org/api/1.2/patches/1640/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/597ed978-d121-220c-b56b-2ffb94bd091c@suse.cz/","msgid":"<597ed978-d121-220c-b56b-2ffb94bd091c@suse.cz>","list_archive_url":null,"date":"2022-10-03T07:50:38","name":"[1/2] refactor usage of compressed_debug_section_type","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/597ed978-d121-220c-b56b-2ffb94bd091c@suse.cz/mbox/"},{"id":1641,"url":"https://patchwork.plctlab.org/api/1.2/patches/1641/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b8acdd83-f33a-74b8-e21a-23719a0b1a60@suse.cz/","msgid":"","list_archive_url":null,"date":"2022-10-03T07:50:44","name":"[2/2] add --enable-default-compressed-debug-sections-algorithm configure option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b8acdd83-f33a-74b8-e21a-23719a0b1a60@suse.cz/mbox/"},{"id":1642,"url":"https://patchwork.plctlab.org/api/1.2/patches/1642/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003101328.1790113-1-aburgess@redhat.com/","msgid":"<20221003101328.1790113-1-aburgess@redhat.com>","list_archive_url":null,"date":"2022-10-03T10:13:28","name":"opcodes/riscv: style csr names as registers","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003101328.1790113-1-aburgess@redhat.com/mbox/"},{"id":1643,"url":"https://patchwork.plctlab.org/api/1.2/patches/1643/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7ba14fc4472ce97d4f7a4433cad8a571e89f82f4.1664793840.git.research_trasio@irq.a4lg.com/","msgid":"<7ba14fc4472ce97d4f7a4433cad8a571e89f82f4.1664793840.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-03T10:43:59","name":"[v3,1/6] RISC-V: Fix immediates to have \"immediate\" style","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7ba14fc4472ce97d4f7a4433cad8a571e89f82f4.1664793840.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1644,"url":"https://patchwork.plctlab.org/api/1.2/patches/1644/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a498bec37c1fd1dcda57cbf95e5f8cfba09b31d3.1664793840.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-03T10:44:00","name":"[v3,2/6] RISC-V: Fix printf argument types corresponding %x","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a498bec37c1fd1dcda57cbf95e5f8cfba09b31d3.1664793840.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1647,"url":"https://patchwork.plctlab.org/api/1.2/patches/1647/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0002ea716713ace4998a33dde0b81f4f890d10bf.1664793840.git.research_trasio@irq.a4lg.com/","msgid":"<0002ea716713ace4998a33dde0b81f4f890d10bf.1664793840.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-03T10:44:01","name":"[v3,3/6] RISC-V: Optimize riscv_disassemble_data printf","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0002ea716713ace4998a33dde0b81f4f890d10bf.1664793840.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1646,"url":"https://patchwork.plctlab.org/api/1.2/patches/1646/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c65fc3e9aa58965d6768a28c9fd7467fea9897a5.1664793840.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-03T10:44:02","name":"[v3,4/6] RISC-V: Print comma and tabs as the \"text\" style","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c65fc3e9aa58965d6768a28c9fd7467fea9897a5.1664793840.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1648,"url":"https://patchwork.plctlab.org/api/1.2/patches/1648/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5abe1d8a7694417b990e11d8f6cd6789573872e5.1664793840.git.research_trasio@irq.a4lg.com/","msgid":"<5abe1d8a7694417b990e11d8f6cd6789573872e5.1664793840.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-03T10:44:03","name":"[v3,5/6] RISC-V: Fix T-Head immediate types on printing","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5abe1d8a7694417b990e11d8f6cd6789573872e5.1664793840.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1649,"url":"https://patchwork.plctlab.org/api/1.2/patches/1649/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0b68af932117258c908db62cf87c3a15d3cdec41.1664793840.git.research_trasio@irq.a4lg.com/","msgid":"<0b68af932117258c908db62cf87c3a15d3cdec41.1664793840.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-03T10:44:04","name":"[v3,6/6] RISC-V: Print XTheadMemPair literal as \"immediate\"","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0b68af932117258c908db62cf87c3a15d3cdec41.1664793840.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1656,"url":"https://patchwork.plctlab.org/api/1.2/patches/1656/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/87lepxcd6x.fsf@redhat.com/","msgid":"<87lepxcd6x.fsf@redhat.com>","list_archive_url":null,"date":"2022-10-03T12:19:02","name":"Commit: readelf: Do not load section data from offset 0","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/87lepxcd6x.fsf@redhat.com/mbox/"},{"id":1659,"url":"https://patchwork.plctlab.org/api/1.2/patches/1659/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e0d369d419da9c0441f415da7f54352aead8f655.1664707612.git.aburgess@redhat.com/","msgid":"","list_archive_url":null,"date":"2022-10-03T16:37:36","name":"[PATCHv2,1/2] opcodes/arm: use '\''@'\'' consistently for the comment character","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e0d369d419da9c0441f415da7f54352aead8f655.1664707612.git.aburgess@redhat.com/mbox/"},{"id":1660,"url":"https://patchwork.plctlab.org/api/1.2/patches/1660/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003165848.11142-1-palmer@rivosinc.com/","msgid":"<20221003165848.11142-1-palmer@rivosinc.com>","list_archive_url":null,"date":"2022-10-03T16:58:48","name":"gas: NEWS: Mention the T-Head extensions that were recently added","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003165848.11142-1-palmer@rivosinc.com/mbox/"},{"id":1671,"url":"https://patchwork.plctlab.org/api/1.2/patches/1671/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/YzvrMEdkXjIn5Lfz@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-04T08:13:36","name":"Support objcopy changing compression to or from zstd","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/YzvrMEdkXjIn5Lfz@squeak.grove.modra.org/mbox/"},{"id":1673,"url":"https://patchwork.plctlab.org/api/1.2/patches/1673/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0bc857d306bb7c8130e5328dbe6b9ed2fed3ef87.1664873933.git.research_trasio@irq.a4lg.com/","msgid":"<0bc857d306bb7c8130e5328dbe6b9ed2fed3ef87.1664873933.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-04T08:59:07","name":"[1/2] RISC-V: Fix buffer overflow on print_insn_riscv","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0bc857d306bb7c8130e5328dbe6b9ed2fed3ef87.1664873933.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1672,"url":"https://patchwork.plctlab.org/api/1.2/patches/1672/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/89612fe01d902007bf84a7dfb0df5f85d5c166e4.1664873933.git.research_trasio@irq.a4lg.com/","msgid":"<89612fe01d902007bf84a7dfb0df5f85d5c166e4.1664873933.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-04T08:59:08","name":"[2/2] gdb/riscv: Fix buffer overflow on riscv_insn::fetch_instruction","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/89612fe01d902007bf84a7dfb0df5f85d5c166e4.1664873933.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1676,"url":"https://patchwork.plctlab.org/api/1.2/patches/1676/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fc849c94f4adcac1c4ccc5508c7a145a2f13b2a9.1664876744.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-04T09:45:49","name":"[v2,1/2] RISC-V: Fix buffer overflow on print_insn_riscv","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fc849c94f4adcac1c4ccc5508c7a145a2f13b2a9.1664876744.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1677,"url":"https://patchwork.plctlab.org/api/1.2/patches/1677/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4eb6e59ae2e790dbbf2bc92477edd281648d8814.1664876744.git.research_trasio@irq.a4lg.com/","msgid":"<4eb6e59ae2e790dbbf2bc92477edd281648d8814.1664876744.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-04T09:45:50","name":"[v2,2/2] gdb/riscv: Partial support for instructions up to 176-bits","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4eb6e59ae2e790dbbf2bc92477edd281648d8814.1664876744.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1678,"url":"https://patchwork.plctlab.org/api/1.2/patches/1678/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ebf16f9e1f45115d0793952ccb4a94d4233303f9.1664882725.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-04T11:25:56","name":"[v3,1/2] RISC-V: Fix buffer overflow on print_insn_riscv","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ebf16f9e1f45115d0793952ccb4a94d4233303f9.1664882725.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1679,"url":"https://patchwork.plctlab.org/api/1.2/patches/1679/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/83464b09b8649525259c69c853dfa2c9575a204b.1664882725.git.research_trasio@irq.a4lg.com/","msgid":"<83464b09b8649525259c69c853dfa2c9575a204b.1664882725.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-04T11:25:57","name":"[v3,2/2] gdb/riscv: Partial support for instructions up to 176-bit","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/83464b09b8649525259c69c853dfa2c9575a204b.1664882725.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1681,"url":"https://patchwork.plctlab.org/api/1.2/patches/1681/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ffa9c1d7-e8c2-a62b-ef3e-b565c0ffbe5b@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-04T13:56:27","name":"RISC-V: Zicbo{m,p,z} adjustments to riscv_multi_subset_supports_ext()","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ffa9c1d7-e8c2-a62b-ef3e-b565c0ffbe5b@suse.com/mbox/"},{"id":1690,"url":"https://patchwork.plctlab.org/api/1.2/patches/1690/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221004161720.1963953-1-vladimir.mezentsev@oracle.com/","msgid":"<20221004161720.1963953-1-vladimir.mezentsev@oracle.com>","list_archive_url":null,"date":"2022-10-04T16:17:20","name":"gprofng: fix build with --enable-pgo-build=lto","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221004161720.1963953-1-vladimir.mezentsev@oracle.com/mbox/"},{"id":1691,"url":"https://patchwork.plctlab.org/api/1.2/patches/1691/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c0211bc9c57be6c79c6d878ce147f63b657f461d.camel@espressif.com/","msgid":"","list_archive_url":null,"date":"2022-10-04T16:22:05","name":"bfd: xtensa: fix __stop_SECTION literal drop,","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c0211bc9c57be6c79c6d878ce147f63b657f461d.camel@espressif.com/mbox/"},{"id":1702,"url":"https://patchwork.plctlab.org/api/1.2/patches/1702/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5f482299-6c60-b2b3-9abe-f4a55a5a26c5@univ-grenoble-alpes.fr/","msgid":"<5f482299-6c60-b2b3-9abe-f4a55a5a26c5@univ-grenoble-alpes.fr>","list_archive_url":null,"date":"2022-10-04T20:03:20","name":"[RFC] bfd: use bfd_vma for the 64-bit version of put[lb] and get[lb]","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5f482299-6c60-b2b3-9abe-f4a55a5a26c5@univ-grenoble-alpes.fr/mbox/"},{"id":1711,"url":"https://patchwork.plctlab.org/api/1.2/patches/1711/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Yz0Gsxdxe0TePbJT@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-05T04:23:15","name":"PR29647, objdump -S looping","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Yz0Gsxdxe0TePbJT@squeak.grove.modra.org/mbox/"},{"id":1712,"url":"https://patchwork.plctlab.org/api/1.2/patches/1712/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/02d747d2-f57b-0fb5-b893-842b6cc41f2f@suse.com/","msgid":"<02d747d2-f57b-0fb5-b893-842b6cc41f2f@suse.com>","list_archive_url":null,"date":"2022-10-05T07:20:47","name":"[v3,1/7] x86: constify parse_insn()'\''s input","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/02d747d2-f57b-0fb5-b893-842b6cc41f2f@suse.com/mbox/"},{"id":1713,"url":"https://patchwork.plctlab.org/api/1.2/patches/1713/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/925cb740-4e1b-abc4-8526-aaab6faae5e1@suse.com/","msgid":"<925cb740-4e1b-abc4-8526-aaab6faae5e1@suse.com>","list_archive_url":null,"date":"2022-10-05T07:22:19","name":"[v3,2/7] x86: introduce Pass2 insn attribute","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/925cb740-4e1b-abc4-8526-aaab6faae5e1@suse.com/mbox/"},{"id":1714,"url":"https://patchwork.plctlab.org/api/1.2/patches/1714/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e16d3e78-39ca-f715-508f-a4104b8ab9a9@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-05T07:23:51","name":"[v3,3/7] x86: re-work insn/suffix recognition","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e16d3e78-39ca-f715-508f-a4104b8ab9a9@suse.com/mbox/"},{"id":1715,"url":"https://patchwork.plctlab.org/api/1.2/patches/1715/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e4e4b80b-794c-7485-1997-685adab8fb27@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-05T07:24:20","name":"[v3,4/7] x86-64: further re-work insn/suffix recognition to also cover MOVSL","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e4e4b80b-794c-7485-1997-685adab8fb27@suse.com/mbox/"},{"id":1716,"url":"https://patchwork.plctlab.org/api/1.2/patches/1716/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/540678fc-8bff-ec68-c97c-478d2631998c@suse.com/","msgid":"<540678fc-8bff-ec68-c97c-478d2631998c@suse.com>","list_archive_url":null,"date":"2022-10-05T07:24:55","name":"[v3,5/7] ix86: don'\''t recognize/derive Q suffix in the common case","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/540678fc-8bff-ec68-c97c-478d2631998c@suse.com/mbox/"},{"id":1718,"url":"https://patchwork.plctlab.org/api/1.2/patches/1718/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e4692495-7d3d-074d-14f9-364d4a9a998c@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-05T07:25:25","name":"[v3,6/7] x86-64: allow HLE store of accumulator to absolute 32-bit address","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e4692495-7d3d-074d-14f9-364d4a9a998c@suse.com/mbox/"},{"id":1717,"url":"https://patchwork.plctlab.org/api/1.2/patches/1717/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e8014ebd-d16b-17a7-9f34-3700fc164136@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-05T07:25:57","name":"[v3,7/7] x86: move bad-use-of-TLS-reloc check","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e8014ebd-d16b-17a7-9f34-3700fc164136@suse.com/mbox/"},{"id":1719,"url":"https://patchwork.plctlab.org/api/1.2/patches/1719/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1266f001-4511-2662-dba9-14b4d0317c57@suse.com/","msgid":"<1266f001-4511-2662-dba9-14b4d0317c57@suse.com>","list_archive_url":null,"date":"2022-10-05T07:40:50","name":"x86: drop \"regmask\" static variable","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1266f001-4511-2662-dba9-14b4d0317c57@suse.com/mbox/"},{"id":1751,"url":"https://patchwork.plctlab.org/api/1.2/patches/1751/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/af45c5d57c221e43101c2aa38b14f4b4ac12d011.1665031170.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-06T04:40:15","name":"[v2,1/2] RISC-V: Fallback for instructions longer than 64b","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/af45c5d57c221e43101c2aa38b14f4b4ac12d011.1665031170.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1752,"url":"https://patchwork.plctlab.org/api/1.2/patches/1752/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c6e55781245dd3e8e9b8debd6130fc5449dfbd55.1665031170.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-06T04:40:16","name":"[v2,2/2] RISC-V: Improve \"bits undefined\" diagnostics","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c6e55781245dd3e8e9b8debd6130fc5449dfbd55.1665031170.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1776,"url":"https://patchwork.plctlab.org/api/1.2/patches/1776/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d52952119e15357c0e823f8a2398999359588b4d.1665050099.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-06T09:56:30","name":"[v3,1/2] RISC-V: Fallback for instructions longer than 64b","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d52952119e15357c0e823f8a2398999359588b4d.1665050099.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1777,"url":"https://patchwork.plctlab.org/api/1.2/patches/1777/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d907b1997f60ff7823c4a23e281ec9d8ddcbf3f1.1665050099.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-06T09:56:31","name":"[v3,2/2] RISC-V: Improve \"bits undefined\" diagnostics","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d907b1997f60ff7823c4a23e281ec9d8ddcbf3f1.1665050099.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1781,"url":"https://patchwork.plctlab.org/api/1.2/patches/1781/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221006114628.304185-1-chigot@adacore.com/","msgid":"<20221006114628.304185-1-chigot@adacore.com>","list_archive_url":null,"date":"2022-10-06T11:46:28","name":"RISC-V: fix linker message when relaxation deletes bytes","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221006114628.304185-1-chigot@adacore.com/mbox/"},{"id":1801,"url":"https://patchwork.plctlab.org/api/1.2/patches/1801/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Yz+Yhyg7UewC9/kp@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-07T03:09:59","name":"PR29653, objcopy/strip: fuzzed small input file induces large output file","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Yz+Yhyg7UewC9/kp@squeak.grove.modra.org/mbox/"},{"id":1803,"url":"https://patchwork.plctlab.org/api/1.2/patches/1803/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/PH1P110MB16505D9D39EC5B1DE22FE3D5EC5F9@PH1P110MB1650.NAMP110.PROD.OUTLOOK.COM/","msgid":"","list_archive_url":null,"date":"2022-10-07T04:10:07","name":"@CPP_FOR_BUILD@ problem since binutils-2.38","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/PH1P110MB16505D9D39EC5B1DE22FE3D5EC5F9@PH1P110MB1650.NAMP110.PROD.OUTLOOK.COM/mbox/"},{"id":1827,"url":"https://patchwork.plctlab.org/api/1.2/patches/1827/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8e13bce108ac10a0c1dd911e23ec572926f7ae44.1665203374.git.research_trasio@irq.a4lg.com/","msgid":"<8e13bce108ac10a0c1dd911e23ec572926f7ae44.1665203374.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-08T04:29:53","name":"[v2,1/1] RISC-V: Test DWARF register numbers for \"fp\"","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8e13bce108ac10a0c1dd911e23ec572926f7ae44.1665203374.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1828,"url":"https://patchwork.plctlab.org/api/1.2/patches/1828/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0883001b3572e54d3fba264429c7ade2adb66610.1665203441.git.research_trasio@irq.a4lg.com/","msgid":"<0883001b3572e54d3fba264429c7ade2adb66610.1665203441.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-08T04:31:15","name":"[1/1] RISC-V: Move standard hints before all instructions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0883001b3572e54d3fba264429c7ade2adb66610.1665203441.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1829,"url":"https://patchwork.plctlab.org/api/1.2/patches/1829/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/58e16a241d7376fcae2515c6bd5a2b41d275eeba.1665203531.git.research_trasio@irq.a4lg.com/","msgid":"<58e16a241d7376fcae2515c6bd5a2b41d275eeba.1665203531.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-08T04:32:18","name":"[RFC,1/1] RISC-V: Imply '\''Zicsr'\'' from privileged extensions with CSRs","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/58e16a241d7376fcae2515c6bd5a2b41d275eeba.1665203531.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1830,"url":"https://patchwork.plctlab.org/api/1.2/patches/1830/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/cb5076fc96e8f2097779a3abcde843dcdd660031.1665203660.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-08T04:34:23","name":"[1/5] opcodes/riscv-dis.c: Tidying with comments/clarity","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/cb5076fc96e8f2097779a3abcde843dcdd660031.1665203660.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1832,"url":"https://patchwork.plctlab.org/api/1.2/patches/1832/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1f1aa0838bf9c4f10a45fcfe3c682f7efc79d9ae.1665203660.git.research_trasio@irq.a4lg.com/","msgid":"<1f1aa0838bf9c4f10a45fcfe3c682f7efc79d9ae.1665203660.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-08T04:34:24","name":"[2/5] opcodes/riscv-dis.c: Tidying with spacing","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1f1aa0838bf9c4f10a45fcfe3c682f7efc79d9ae.1665203660.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1831,"url":"https://patchwork.plctlab.org/api/1.2/patches/1831/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/740bc5e2d2618d236519b39fedd1a1d7ae4e05da.1665203660.git.research_trasio@irq.a4lg.com/","msgid":"<740bc5e2d2618d236519b39fedd1a1d7ae4e05da.1665203660.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-08T04:34:25","name":"[3/5] opcodes/riscv-dis.c: Use bool type whenever possible","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/740bc5e2d2618d236519b39fedd1a1d7ae4e05da.1665203660.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1833,"url":"https://patchwork.plctlab.org/api/1.2/patches/1833/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6e3a9c235e317f441b4383b3daa68f2051bdc149.1665203660.git.research_trasio@irq.a4lg.com/","msgid":"<6e3a9c235e317f441b4383b3daa68f2051bdc149.1665203660.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-08T04:34:26","name":"[4/5] opcodes/riscv-dis.c: Make XLEN variable static","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6e3a9c235e317f441b4383b3daa68f2051bdc149.1665203660.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1834,"url":"https://patchwork.plctlab.org/api/1.2/patches/1834/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ad929233a62d887495122721340b2f9c80392963.1665203660.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-08T04:34:27","name":"[5/5] opcodes/riscv-dis.c: Remove last_map_state","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ad929233a62d887495122721340b2f9c80392963.1665203660.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1836,"url":"https://patchwork.plctlab.org/api/1.2/patches/1836/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d07e2b6f36ea2fd5830924a9bfeda941b774b687.1665290422.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-09T05:09:22","name":"RISC-V: Move certain arrays to riscv-opc.c","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d07e2b6f36ea2fd5830924a9bfeda941b774b687.1665290422.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1844,"url":"https://patchwork.plctlab.org/api/1.2/patches/1844/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010004623.16582-1-mark@harmstone.com/","msgid":"<20221010004623.16582-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-10T00:46:22","name":"[v2,1/2] ld: Add --pdb option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010004623.16582-1-mark@harmstone.com/mbox/"},{"id":1845,"url":"https://patchwork.plctlab.org/api/1.2/patches/1845/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010004623.16582-2-mark@harmstone.com/","msgid":"<20221010004623.16582-2-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-10T00:46:23","name":"[v2,2/2] ld: Add minimal pdb generation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010004623.16582-2-mark@harmstone.com/mbox/"},{"id":1890,"url":"https://patchwork.plctlab.org/api/1.2/patches/1890/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010200433.414320-1-vladimir.mezentsev@oracle.com/","msgid":"<20221010200433.414320-1-vladimir.mezentsev@oracle.com>","list_archive_url":null,"date":"2022-10-10T20:04:33","name":"gprofng: run tests without installation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010200433.414320-1-vladimir.mezentsev@oracle.com/mbox/"},{"id":1893,"url":"https://patchwork.plctlab.org/api/1.2/patches/1893/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010230426.719238-1-vladimir.mezentsev@oracle.com/","msgid":"<20221010230426.719238-1-vladimir.mezentsev@oracle.com>","list_archive_url":null,"date":"2022-10-10T23:04:26","name":"[2/2] gprofng: use the --libdir path to find libraries","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010230426.719238-1-vladimir.mezentsev@oracle.com/mbox/"},{"id":1894,"url":"https://patchwork.plctlab.org/api/1.2/patches/1894/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010235155.842469-1-vladimir.mezentsev@oracle.com/","msgid":"<20221010235155.842469-1-vladimir.mezentsev@oracle.com>","list_archive_url":null,"date":"2022-10-10T23:51:55","name":"[3/3] gprofng: no need to build version.texi","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010235155.842469-1-vladimir.mezentsev@oracle.com/mbox/"},{"id":1895,"url":"https://patchwork.plctlab.org/api/1.2/patches/1895/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011003702.4287-1-mark@harmstone.com/","msgid":"<20221011003702.4287-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-11T00:37:01","name":"[v3,1/2] ld: Add --pdb option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011003702.4287-1-mark@harmstone.com/mbox/"},{"id":1897,"url":"https://patchwork.plctlab.org/api/1.2/patches/1897/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011003702.4287-2-mark@harmstone.com/","msgid":"<20221011003702.4287-2-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-11T00:37:02","name":"[v3,2/2] ld: Add minimal pdb generation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011003702.4287-2-mark@harmstone.com/mbox/"},{"id":1928,"url":"https://patchwork.plctlab.org/api/1.2/patches/1928/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011175332.17156-1-mark@harmstone.com/","msgid":"<20221011175332.17156-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-11T17:53:31","name":"[v4,1/2] ld: Add --pdb option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011175332.17156-1-mark@harmstone.com/mbox/"},{"id":1929,"url":"https://patchwork.plctlab.org/api/1.2/patches/1929/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011175332.17156-2-mark@harmstone.com/","msgid":"<20221011175332.17156-2-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-11T17:53:32","name":"[v4,2/2] ld: Add minimal pdb generation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011175332.17156-2-mark@harmstone.com/mbox/"},{"id":1941,"url":"https://patchwork.plctlab.org/api/1.2/patches/1941/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221012031005.237446-1-simon.marchi@polymtl.ca/","msgid":"<20221012031005.237446-1-simon.marchi@polymtl.ca>","list_archive_url":null,"date":"2022-10-12T03:10:05","name":"[pushed] Re-apply \"Pass PKG_CONFIG_PATH down from top-level Makefile\"","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221012031005.237446-1-simon.marchi@polymtl.ca/mbox/"},{"id":1976,"url":"https://patchwork.plctlab.org/api/1.2/patches/1976/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1216a3f8-2273-8681-f528-9493a66891f0@suse.com/","msgid":"<1216a3f8-2273-8681-f528-9493a66891f0@suse.com>","list_archive_url":null,"date":"2022-10-13T08:16:49","name":"[v4,1/8] x86: constify parse_insn()'\''s input","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1216a3f8-2273-8681-f528-9493a66891f0@suse.com/mbox/"},{"id":1977,"url":"https://patchwork.plctlab.org/api/1.2/patches/1977/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/11599bbe-c779-aa9f-4d5d-c2243f0e69dc@suse.com/","msgid":"<11599bbe-c779-aa9f-4d5d-c2243f0e69dc@suse.com>","list_archive_url":null,"date":"2022-10-13T08:17:17","name":"[v4,2/8] x86: introduce Pass2 insn attribute","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/11599bbe-c779-aa9f-4d5d-c2243f0e69dc@suse.com/mbox/"},{"id":1978,"url":"https://patchwork.plctlab.org/api/1.2/patches/1978/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/357273a3-060c-23db-72da-3fc9d1be3d2a@suse.com/","msgid":"<357273a3-060c-23db-72da-3fc9d1be3d2a@suse.com>","list_archive_url":null,"date":"2022-10-13T08:18:09","name":"[v4,3/8] x86: re-work insn/suffix recognition","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/357273a3-060c-23db-72da-3fc9d1be3d2a@suse.com/mbox/"},{"id":1979,"url":"https://patchwork.plctlab.org/api/1.2/patches/1979/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0ec0587f-6a7b-45b6-8346-e5d774e73636@suse.com/","msgid":"<0ec0587f-6a7b-45b6-8346-e5d774e73636@suse.com>","list_archive_url":null,"date":"2022-10-13T08:18:39","name":"[v4,4/8] x86-64: further re-work insn/suffix recognition to also cover MOVSL","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0ec0587f-6a7b-45b6-8346-e5d774e73636@suse.com/mbox/"},{"id":1980,"url":"https://patchwork.plctlab.org/api/1.2/patches/1980/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fb617d0b-8759-3169-5a65-1178b7fef3d7@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-13T08:19:34","name":"[v4,5/8] ix86: don'\''t recognize/derive Q suffix in the common case","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fb617d0b-8759-3169-5a65-1178b7fef3d7@suse.com/mbox/"},{"id":1981,"url":"https://patchwork.plctlab.org/api/1.2/patches/1981/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1df3bd01-99c5-f56c-d937-970edd42b2b8@suse.com/","msgid":"<1df3bd01-99c5-f56c-d937-970edd42b2b8@suse.com>","list_archive_url":null,"date":"2022-10-13T08:20:14","name":"[v4,6/8] x86-64: allow HLE store of accumulator to absolute 32-bit address","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1df3bd01-99c5-f56c-d937-970edd42b2b8@suse.com/mbox/"},{"id":1982,"url":"https://patchwork.plctlab.org/api/1.2/patches/1982/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8486a218-39ec-16b2-5c6c-5037196b93cf@suse.com/","msgid":"<8486a218-39ec-16b2-5c6c-5037196b93cf@suse.com>","list_archive_url":null,"date":"2022-10-13T08:21:00","name":"[v4,7/8] x86: move bad-use-of-TLS-reloc check","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8486a218-39ec-16b2-5c6c-5037196b93cf@suse.com/mbox/"},{"id":1983,"url":"https://patchwork.plctlab.org/api/1.2/patches/1983/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7d82692d-93df-fbee-9efb-2f44e8a91df3@suse.com/","msgid":"<7d82692d-93df-fbee-9efb-2f44e8a91df3@suse.com>","list_archive_url":null,"date":"2022-10-13T08:22:00","name":"[v4,8/8] x86: drop (now) stray IsString","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7d82692d-93df-fbee-9efb-2f44e8a91df3@suse.com/mbox/"},{"id":2013,"url":"https://patchwork.plctlab.org/api/1.2/patches/2013/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8ab93d7a617ad480dd786210f46db0e5aa07d1ac.1665655719.git.research_trasio@irq.a4lg.com/","msgid":"<8ab93d7a617ad480dd786210f46db0e5aa07d1ac.1665655719.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-13T10:11:41","name":"include: Declare getopt function on old GNU libc","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8ab93d7a617ad480dd786210f46db0e5aa07d1ac.1665655719.git.research_trasio@irq.a4lg.com/mbox/"},{"id":2352,"url":"https://patchwork.plctlab.org/api/1.2/patches/2352/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221013201332.2747246-1-maskray@google.com/","msgid":"<20221013201332.2747246-1-maskray@google.com>","list_archive_url":null,"date":"2022-10-13T20:13:32","name":"ld: Add --undefined-version","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221013201332.2747246-1-maskray@google.com/mbox/"},{"id":2532,"url":"https://patchwork.plctlab.org/api/1.2/patches/2532/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014063520.1428330-2-zengxiao@eswincomputing.com/","msgid":"<20221014063520.1428330-2-zengxiao@eswincomputing.com>","list_archive_url":null,"date":"2022-10-14T06:35:20","name":"[1/1] RISC-V: Make R_RISCV_SUB6 conforms to riscv abi standard","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014063520.1428330-2-zengxiao@eswincomputing.com/mbox/"},{"id":2560,"url":"https://patchwork.plctlab.org/api/1.2/patches/2560/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/027ae69a-636b-6757-297a-eec42936401e@linaro.org/","msgid":"<027ae69a-636b-6757-297a-eec42936401e@linaro.org>","list_archive_url":null,"date":"2022-10-14T07:58:22","name":"[v3] aarch64-pe support for LD, GAS and BFD","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/027ae69a-636b-6757-297a-eec42936401e@linaro.org/mbox/"},{"id":2602,"url":"https://patchwork.plctlab.org/api/1.2/patches/2602/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-2-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-2-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:39","name":"[01/10] Support Intel AVX-IFMA","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-2-haochen.jiang@intel.com/mbox/"},{"id":2608,"url":"https://patchwork.plctlab.org/api/1.2/patches/2608/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-3-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-3-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:40","name":"[02/10] Support Intel AVX-VNNI-INT8","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-3-haochen.jiang@intel.com/mbox/"},{"id":2611,"url":"https://patchwork.plctlab.org/api/1.2/patches/2611/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-4-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-4-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:41","name":"[03/10] Support Intel AVX-NE-CONVERT","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-4-haochen.jiang@intel.com/mbox/"},{"id":2610,"url":"https://patchwork.plctlab.org/api/1.2/patches/2610/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-5-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-5-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:42","name":"[04/10] Support Intel CMPccXADD","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-5-haochen.jiang@intel.com/mbox/"},{"id":2601,"url":"https://patchwork.plctlab.org/api/1.2/patches/2601/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-6-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-6-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:43","name":"[05/10] Add handler for more i386_cpu_flags","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-6-haochen.jiang@intel.com/mbox/"},{"id":2606,"url":"https://patchwork.plctlab.org/api/1.2/patches/2606/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-7-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-7-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:44","name":"[06/10] Support Intel RAO-INT","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-7-haochen.jiang@intel.com/mbox/"},{"id":2609,"url":"https://patchwork.plctlab.org/api/1.2/patches/2609/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-8-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-8-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:45","name":"[07/10] Support Intel WRMSRNS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-8-haochen.jiang@intel.com/mbox/"},{"id":2605,"url":"https://patchwork.plctlab.org/api/1.2/patches/2605/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-9-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-9-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:46","name":"[08/10] Support Intel MSRLIST","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-9-haochen.jiang@intel.com/mbox/"},{"id":2607,"url":"https://patchwork.plctlab.org/api/1.2/patches/2607/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-10-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-10-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:47","name":"[09/10] Support Intel AMX-FP16","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-10-haochen.jiang@intel.com/mbox/"},{"id":2604,"url":"https://patchwork.plctlab.org/api/1.2/patches/2604/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-11-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-11-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:48","name":"[10/10] Support Intel PREFETCHI","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-11-haochen.jiang@intel.com/mbox/"},{"id":2643,"url":"https://patchwork.plctlab.org/api/1.2/patches/2643/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7bac66be-535e-9051-d674-f2f5ba180e17@suse.com/","msgid":"<7bac66be-535e-9051-d674-f2f5ba180e17@suse.com>","list_archive_url":null,"date":"2022-10-14T10:22:34","name":"x86: fold AVX512-VNNI disassembler entries with AVX-VNNI ones","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7bac66be-535e-9051-d674-f2f5ba180e17@suse.com/mbox/"},{"id":2654,"url":"https://patchwork.plctlab.org/api/1.2/patches/2654/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0lIo5+ncY/MqBEq@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-14T11:31:47","name":"PR29677, Field `the_bfd` of `asymbol` is uninitialised","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0lIo5+ncY/MqBEq@squeak.grove.modra.org/mbox/"},{"id":2656,"url":"https://patchwork.plctlab.org/api/1.2/patches/2656/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0lJksn49ZpABY89@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-14T11:35:46","name":"e200 LSP support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0lJksn49ZpABY89@squeak.grove.modra.org/mbox/"},{"id":2657,"url":"https://patchwork.plctlab.org/api/1.2/patches/2657/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0lJxxYoeD5iDYAD@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-14T11:36:39","name":"PowerPC SPE disassembly and tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0lJxxYoeD5iDYAD@squeak.grove.modra.org/mbox/"},{"id":2695,"url":"https://patchwork.plctlab.org/api/1.2/patches/2695/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/DM6PR12MB4219611F6CC2A0702884A602E7249@DM6PR12MB4219.namprd12.prod.outlook.com/","msgid":"","list_archive_url":null,"date":"2022-10-14T13:29:40","name":"Binutils: Adding new testcase for addr2line.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/DM6PR12MB4219611F6CC2A0702884A602E7249@DM6PR12MB4219.namprd12.prod.outlook.com/mbox/"},{"id":2700,"url":"https://patchwork.plctlab.org/api/1.2/patches/2700/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9fd2c88d-98b2-99a4-419f-c7235b2cf960@suse.com/","msgid":"<9fd2c88d-98b2-99a4-419f-c7235b2cf960@suse.com>","list_archive_url":null,"date":"2022-10-14T14:11:35","name":"x86: properly decode EVEX.W for AVX512_4{FMAPS,VNNIW} insns","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9fd2c88d-98b2-99a4-419f-c7235b2cf960@suse.com/mbox/"},{"id":2981,"url":"https://patchwork.plctlab.org/api/1.2/patches/2981/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0uLzalqjm4C87GN@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-16T04:42:53","name":"PowerPC se_rfmci and VLE, SPE2 and LSP insns with -many","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0uLzalqjm4C87GN@squeak.grove.modra.org/mbox/"},{"id":3152,"url":"https://patchwork.plctlab.org/api/1.2/patches/3152/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221016232419.1135-1-mark@harmstone.com/","msgid":"<20221016232419.1135-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-16T23:24:18","name":"[v5,1/2] ld: Add --pdb option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221016232419.1135-1-mark@harmstone.com/mbox/"},{"id":3151,"url":"https://patchwork.plctlab.org/api/1.2/patches/3151/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221016232419.1135-2-mark@harmstone.com/","msgid":"<20221016232419.1135-2-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-16T23:24:19","name":"[v5,2/2] ld: Add minimal pdb generation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221016232419.1135-2-mark@harmstone.com/mbox/"},{"id":3258,"url":"https://patchwork.plctlab.org/api/1.2/patches/3258/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/19c08747-fa5b-1e67-3dd2-c891a2c0c1fa@suse.com/","msgid":"<19c08747-fa5b-1e67-3dd2-c891a2c0c1fa@suse.com>","list_archive_url":null,"date":"2022-10-17T07:44:51","name":"x86: correct CPU_AMX_{BF16,INT8}_FLAGS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/19c08747-fa5b-1e67-3dd2-c891a2c0c1fa@suse.com/mbox/"},{"id":3272,"url":"https://patchwork.plctlab.org/api/1.2/patches/3272/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/85dd526c-d3a7-72dc-5444-ed5573eebec1@suse.com/","msgid":"<85dd526c-d3a7-72dc-5444-ed5573eebec1@suse.com>","list_archive_url":null,"date":"2022-10-17T08:30:12","name":"x86: generalize gas documentation for disabling of ISA extensions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/85dd526c-d3a7-72dc-5444-ed5573eebec1@suse.com/mbox/"},{"id":3759,"url":"https://patchwork.plctlab.org/api/1.2/patches/3759/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-2-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-2-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:15:58","name":"[V2,01/15] sframe.h: Add SFrame format definition","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-2-indu.bhagat@oracle.com/mbox/"},{"id":3762,"url":"https://patchwork.plctlab.org/api/1.2/patches/3762/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-3-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-3-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:15:59","name":"[V2,02/15] gas: add new command line option --gsframe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-3-indu.bhagat@oracle.com/mbox/"},{"id":3761,"url":"https://patchwork.plctlab.org/api/1.2/patches/3761/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-4-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-4-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:00","name":"[V2,03/15] gas: generate .sframe from CFI directives","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-4-indu.bhagat@oracle.com/mbox/"},{"id":3760,"url":"https://patchwork.plctlab.org/api/1.2/patches/3760/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-5-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-5-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:01","name":"[V2,04/15] gas: testsuite: add new tests for SFrame unwind info","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-5-indu.bhagat@oracle.com/mbox/"},{"id":3764,"url":"https://patchwork.plctlab.org/api/1.2/patches/3764/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-6-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-6-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:02","name":"[V2,05/15] libsframe: add the SFrame library","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-6-indu.bhagat@oracle.com/mbox/"},{"id":3766,"url":"https://patchwork.plctlab.org/api/1.2/patches/3766/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-7-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-7-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:03","name":"[V2,06/15] bfd: linker: merge .sframe sections","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-7-indu.bhagat@oracle.com/mbox/"},{"id":3763,"url":"https://patchwork.plctlab.org/api/1.2/patches/3763/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-8-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-8-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:04","name":"[V2,07/15] readelf/objdump: support for SFrame section","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-8-indu.bhagat@oracle.com/mbox/"},{"id":3765,"url":"https://patchwork.plctlab.org/api/1.2/patches/3765/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-9-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-9-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:05","name":"[V2,08/15] unwinder: generate backtrace using SFrame format","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-9-indu.bhagat@oracle.com/mbox/"},{"id":3770,"url":"https://patchwork.plctlab.org/api/1.2/patches/3770/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-10-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-10-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:06","name":"[V2,09/15] unwinder: Add SFrame unwinder tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-10-indu.bhagat@oracle.com/mbox/"},{"id":3769,"url":"https://patchwork.plctlab.org/api/1.2/patches/3769/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-11-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-11-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:07","name":"[V2,10/15] gdb: sim: buildsystem changes to accommodate libsframe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-11-indu.bhagat@oracle.com/mbox/"},{"id":3771,"url":"https://patchwork.plctlab.org/api/1.2/patches/3771/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-12-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-12-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:08","name":"[V2,11/15] libctf: add libsframe to LDFLAGS and LIBS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-12-indu.bhagat@oracle.com/mbox/"},{"id":3768,"url":"https://patchwork.plctlab.org/api/1.2/patches/3768/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-13-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-13-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:09","name":"[V2,12/15] src-release.sh: Add libsframe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-13-indu.bhagat@oracle.com/mbox/"},{"id":3767,"url":"https://patchwork.plctlab.org/api/1.2/patches/3767/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-14-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-14-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:10","name":"[V2,13/15] binutils/NEWS: add text for SFrame support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-14-indu.bhagat@oracle.com/mbox/"},{"id":3772,"url":"https://patchwork.plctlab.org/api/1.2/patches/3772/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-15-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-15-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:11","name":"[V2,14/15] gas/NEWS: add text about new command line option and SFrame support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-15-indu.bhagat@oracle.com/mbox/"},{"id":3773,"url":"https://patchwork.plctlab.org/api/1.2/patches/3773/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-16-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-16-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:12","name":"[V2,15/15] doc: add SFrame spec file","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-16-indu.bhagat@oracle.com/mbox/"},{"id":3999,"url":"https://patchwork.plctlab.org/api/1.2/patches/3999/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221018081205.17880-1-krebbel@linux.ibm.com/","msgid":"<20221018081205.17880-1-krebbel@linux.ibm.com>","list_archive_url":null,"date":"2022-10-18T08:12:05","name":"[1/1] IBM zSystems: Issue error for *DBL relocs on misaligned symbols","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221018081205.17880-1-krebbel@linux.ibm.com/mbox/"},{"id":4141,"url":"https://patchwork.plctlab.org/api/1.2/patches/4141/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/baffaf673f17692b7bcbd604b31800b189988596.camel@espressif.com/","msgid":"","list_archive_url":null,"date":"2022-10-18T12:12:07","name":"xtensa: use definitions from xtensa-config.h","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/baffaf673f17692b7bcbd604b31800b189988596.camel@espressif.com/mbox/"},{"id":4272,"url":"https://patchwork.plctlab.org/api/1.2/patches/4272/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221018174914.470062-1-hjl.tools@gmail.com/","msgid":"<20221018174914.470062-1-hjl.tools@gmail.com>","list_archive_url":null,"date":"2022-10-18T17:49:14","name":"x86: Disable AVX-VNNI when disabling AVX2","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221018174914.470062-1-hjl.tools@gmail.com/mbox/"},{"id":4998,"url":"https://patchwork.plctlab.org/api/1.2/patches/4998/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c2f76e95-09f6-1d92-7ef4-38a3c2955fcd@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-19T09:52:46","name":"x86: re-work AVX-VNNI support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c2f76e95-09f6-1d92-7ef4-38a3c2955fcd@suse.com/mbox/"},{"id":5276,"url":"https://patchwork.plctlab.org/api/1.2/patches/5276/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0/lLtlKqqsmAx0s@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-19T11:53:18","name":"Fix addr2line test for ppc64 elfv1 and mingw","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0/lLtlKqqsmAx0s@squeak.grove.modra.org/mbox/"},{"id":5424,"url":"https://patchwork.plctlab.org/api/1.2/patches/5424/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/07bfebbf3843b47e13d82d4fa16eb14fec942ef7.1666184962.git.research_trasio@irq.a4lg.com/","msgid":"<07bfebbf3843b47e13d82d4fa16eb14fec942ef7.1666184962.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:09:54","name":"binutils: Remove unused substitution PROGRAM","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/07bfebbf3843b47e13d82d4fa16eb14fec942ef7.1666184962.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5433,"url":"https://patchwork.plctlab.org/api/1.2/patches/5433/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2fa7ff719223232402e82a9c91331aea22ace1bb.1666185116.git.research_trasio@irq.a4lg.com/","msgid":"<2fa7ff719223232402e82a9c91331aea22ace1bb.1666185116.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:11:55","name":"[v2,1/8] RISC-V: Add a space at the end of pinfo","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2fa7ff719223232402e82a9c91331aea22ace1bb.1666185116.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5435,"url":"https://patchwork.plctlab.org/api/1.2/patches/5435/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1b30cce5db2cce3b8edca42ab5da114d0b8c9e93.1666185116.git.research_trasio@irq.a4lg.com/","msgid":"<1b30cce5db2cce3b8edca42ab5da114d0b8c9e93.1666185116.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:11:56","name":"[v2,2/8] RISC-V: Fix obvious misalignments ('\''Zbb'\''/'\''Zba'\'')","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1b30cce5db2cce3b8edca42ab5da114d0b8c9e93.1666185116.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5437,"url":"https://patchwork.plctlab.org/api/1.2/patches/5437/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6b0857aa1a2d15ca1cf00b4dcaae0032efbb88ff.1666185116.git.research_trasio@irq.a4lg.com/","msgid":"<6b0857aa1a2d15ca1cf00b4dcaae0032efbb88ff.1666185116.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:11:57","name":"[v2,3/8] RISC-V: Remove spaces in opcode entries","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6b0857aa1a2d15ca1cf00b4dcaae0032efbb88ff.1666185116.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5436,"url":"https://patchwork.plctlab.org/api/1.2/patches/5436/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/889d956caac0f2e95543a14afaeed97188ce384c.1666185116.git.research_trasio@irq.a4lg.com/","msgid":"<889d956caac0f2e95543a14afaeed97188ce384c.1666185116.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:11:58","name":"[v2,4/8] RISC-V: Remove unused instruction macros","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/889d956caac0f2e95543a14afaeed97188ce384c.1666185116.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5440,"url":"https://patchwork.plctlab.org/api/1.2/patches/5440/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8f226ee20d8a5ef6ad7b6c4408b44794a99d542a.1666185116.git.research_trasio@irq.a4lg.com/","msgid":"<8f226ee20d8a5ef6ad7b6c4408b44794a99d542a.1666185116.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:11:59","name":"[v2,5/8] RISC-V: Complete tidying up with SCALL and SBREAK","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8f226ee20d8a5ef6ad7b6c4408b44794a99d542a.1666185116.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5442,"url":"https://patchwork.plctlab.org/api/1.2/patches/5442/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4070184c454a05a39adf0790951e5856e6b2ecb6.1666185116.git.research_trasio@irq.a4lg.com/","msgid":"<4070184c454a05a39adf0790951e5856e6b2ecb6.1666185116.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:12:00","name":"[v2,6/8] RISC-V: Tidying up with fmv.w.x and fmv.x.w","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4070184c454a05a39adf0790951e5856e6b2ecb6.1666185116.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5438,"url":"https://patchwork.plctlab.org/api/1.2/patches/5438/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c1ccda3e7c8fb297eda46dab3936d5c5977178fc.1666185116.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-19T13:12:01","name":"[v2,7/8] RISC-V: Make alias instructions aliases","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c1ccda3e7c8fb297eda46dab3936d5c5977178fc.1666185116.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5441,"url":"https://patchwork.plctlab.org/api/1.2/patches/5441/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/413cfca82c7e8d8a2e977dfda9135903c9cb7c57.1666185116.git.research_trasio@irq.a4lg.com/","msgid":"<413cfca82c7e8d8a2e977dfda9135903c9cb7c57.1666185116.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:12:02","name":"[v2,8/8] RISC-V: Use defined mask and match values","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/413cfca82c7e8d8a2e977dfda9135903c9cb7c57.1666185116.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5439,"url":"https://patchwork.plctlab.org/api/1.2/patches/5439/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/345c5c3b3a53eab04a1e6e91197de2642095c94f.1666185237.git.research_trasio@irq.a4lg.com/","msgid":"<345c5c3b3a53eab04a1e6e91197de2642095c94f.1666185237.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:14:01","name":"RISC-V: Remove RV32EF conflict","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/345c5c3b3a53eab04a1e6e91197de2642095c94f.1666185237.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5616,"url":"https://patchwork.plctlab.org/api/1.2/patches/5616/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019145608.45213-5-haochen.jiang@intel.com/","msgid":"<20221019145608.45213-5-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T14:56:02","name":"[04/10] Support Intel CMPccXADD","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019145608.45213-5-haochen.jiang@intel.com/mbox/"},{"id":5614,"url":"https://patchwork.plctlab.org/api/1.2/patches/5614/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019145608.45213-6-haochen.jiang@intel.com/","msgid":"<20221019145608.45213-6-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T14:56:03","name":"[05/10] Add handler for more i386_cpu_flags","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019145608.45213-6-haochen.jiang@intel.com/mbox/"},{"id":5672,"url":"https://patchwork.plctlab.org/api/1.2/patches/5672/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-2-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-2-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:25","name":"[01/10] Support Intel AVX-IFMA","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-2-haochen.jiang@intel.com/mbox/"},{"id":5691,"url":"https://patchwork.plctlab.org/api/1.2/patches/5691/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-3-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-3-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:26","name":"[02/10] Support Intel AVX-VNNI-INT8","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-3-haochen.jiang@intel.com/mbox/"},{"id":5690,"url":"https://patchwork.plctlab.org/api/1.2/patches/5690/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-4-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-4-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:27","name":"[03/10] Support Intel AVX-NE-CONVERT","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-4-haochen.jiang@intel.com/mbox/"},{"id":5689,"url":"https://patchwork.plctlab.org/api/1.2/patches/5689/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-5-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-5-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:28","name":"[04/10] Support Intel CMPccXADD","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-5-haochen.jiang@intel.com/mbox/"},{"id":5676,"url":"https://patchwork.plctlab.org/api/1.2/patches/5676/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-6-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-6-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:29","name":"[05/10] Add handler for more i386_cpu_flags","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-6-haochen.jiang@intel.com/mbox/"},{"id":5677,"url":"https://patchwork.plctlab.org/api/1.2/patches/5677/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-7-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-7-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:30","name":"[06/10] Support Intel RAO-INT","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-7-haochen.jiang@intel.com/mbox/"},{"id":5681,"url":"https://patchwork.plctlab.org/api/1.2/patches/5681/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-8-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-8-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:31","name":"[07/10] Support Intel WRMSRNS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-8-haochen.jiang@intel.com/mbox/"},{"id":5682,"url":"https://patchwork.plctlab.org/api/1.2/patches/5682/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-9-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-9-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:32","name":"[08/10] Support Intel MSRLIST","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-9-haochen.jiang@intel.com/mbox/"},{"id":5673,"url":"https://patchwork.plctlab.org/api/1.2/patches/5673/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-10-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-10-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:33","name":"[09/10] Support Intel AMX-FP16","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-10-haochen.jiang@intel.com/mbox/"},{"id":5686,"url":"https://patchwork.plctlab.org/api/1.2/patches/5686/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-11-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-11-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:34","name":"[10/10] Support Intel PREFETCHI","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-11-haochen.jiang@intel.com/mbox/"},{"id":5940,"url":"https://patchwork.plctlab.org/api/1.2/patches/5940/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1CMrFUC8d9lC/NL@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-19T23:47:56","name":"Obsolete beos","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1CMrFUC8d9lC/NL@squeak.grove.modra.org/mbox/"},{"id":6080,"url":"https://patchwork.plctlab.org/api/1.2/patches/6080/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8b99d666e78ba5b9d32c7889a2161c70b3da88df.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<8b99d666e78ba5b9d32c7889a2161c70b3da88df.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:25:47","name":"[01/40] gdb/unittests: PR28413, suppress warnings generated by Gnulib","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8b99d666e78ba5b9d32c7889a2161c70b3da88df.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6081,"url":"https://patchwork.plctlab.org/api/1.2/patches/6081/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b05adb17e401d621dbdad791281bc7af7806906e.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-20T09:25:48","name":"[02/40] sim: Check known getrusage declaration existence","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b05adb17e401d621dbdad791281bc7af7806906e.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6083,"url":"https://patchwork.plctlab.org/api/1.2/patches/6083/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/796962a87e569feeafb5ef636de3c79000ae152c.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<796962a87e569feeafb5ef636de3c79000ae152c.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:25:49","name":"[03/40] sim/aarch64: Remove unused functions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/796962a87e569feeafb5ef636de3c79000ae152c.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6084,"url":"https://patchwork.plctlab.org/api/1.2/patches/6084/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/65223c79fdfd7faf132275415cd9da9852c5bec3.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<65223c79fdfd7faf132275415cd9da9852c5bec3.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:25:50","name":"[04/40] cpu/cris: Initialize some variables on CRIS CPU","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/65223c79fdfd7faf132275415cd9da9852c5bec3.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6082,"url":"https://patchwork.plctlab.org/api/1.2/patches/6082/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/24baefe92148f4b7968115ba13de9b0c863a65f6.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<24baefe92148f4b7968115ba13de9b0c863a65f6.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:25:51","name":"[05/40] cpu/cris: Add u-stall virtual unit to CRIS v32","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/24baefe92148f4b7968115ba13de9b0c863a65f6.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6087,"url":"https://patchwork.plctlab.org/api/1.2/patches/6087/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3904a5c3e80f8548150d8088a92059dd728c7ff8.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<3904a5c3e80f8548150d8088a92059dd728c7ff8.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:25:52","name":"[06/40] sim/cris: Move declarations of f_specific_init","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3904a5c3e80f8548150d8088a92059dd728c7ff8.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6091,"url":"https://patchwork.plctlab.org/api/1.2/patches/6091/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/69ef2d7dd519ed572511890a215a0f6d74e53384.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<69ef2d7dd519ed572511890a215a0f6d74e53384.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:25:53","name":"[07/40] sim/cris: Regenerate with CGEN","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/69ef2d7dd519ed572511890a215a0f6d74e53384.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6085,"url":"https://patchwork.plctlab.org/api/1.2/patches/6085/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/26a3eaf4f5d2e0db6977738ddfd65d82b36e38b2.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<26a3eaf4f5d2e0db6977738ddfd65d82b36e38b2.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:25:54","name":"[08/40] sim/erc32: Insert void parameter","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/26a3eaf4f5d2e0db6977738ddfd65d82b36e38b2.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6086,"url":"https://patchwork.plctlab.org/api/1.2/patches/6086/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/057c2f8392410494c3bc5dc98052246508e6a73e.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<057c2f8392410494c3bc5dc98052246508e6a73e.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:25:55","name":"[09/40] sim/erc32: Use int32_t as event callback argument","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/057c2f8392410494c3bc5dc98052246508e6a73e.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6090,"url":"https://patchwork.plctlab.org/api/1.2/patches/6090/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8c05aec20557191434485be347d37177a2ec5ff2.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<8c05aec20557191434485be347d37177a2ec5ff2.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:25:56","name":"[10/40] sim/erc32: Use int32_t as IRQ callback argument","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8c05aec20557191434485be347d37177a2ec5ff2.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6089,"url":"https://patchwork.plctlab.org/api/1.2/patches/6089/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/afd7757aae21743c29f2aa4135a23b31d4959e9b.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-20T09:25:57","name":"[11/40] cpu/frv: Initialize some variables","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/afd7757aae21743c29f2aa4135a23b31d4959e9b.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6088,"url":"https://patchwork.plctlab.org/api/1.2/patches/6088/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/021dbd238af5dfe74523ed229d2156a155a6bb9e.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<021dbd238af5dfe74523ed229d2156a155a6bb9e.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:25:58","name":"[12/40] sim/frv: Initialize nesr variable","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/021dbd238af5dfe74523ed229d2156a155a6bb9e.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6093,"url":"https://patchwork.plctlab.org/api/1.2/patches/6093/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/51a03f7097921cc48954210cf99e370ae8982ec8.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<51a03f7097921cc48954210cf99e370ae8982ec8.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:25:59","name":"[13/40] sim/frv: Initialize some variables","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/51a03f7097921cc48954210cf99e370ae8982ec8.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6092,"url":"https://patchwork.plctlab.org/api/1.2/patches/6092/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e1baa1be3601612266dc6ae0bdde8426ff2a42c8.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-20T09:26:00","name":"[14/40] sim/frv: Add explicit casts","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e1baa1be3601612266dc6ae0bdde8426ff2a42c8.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6095,"url":"https://patchwork.plctlab.org/api/1.2/patches/6095/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5ab303a5bdfc1da7832f8fa22f57678c9ef1a5fa.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<5ab303a5bdfc1da7832f8fa22f57678c9ef1a5fa.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:26:01","name":"[15/40] sim/h8300: Add \"+ 0x0\" to avoid self-assignments","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5ab303a5bdfc1da7832f8fa22f57678c9ef1a5fa.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6101,"url":"https://patchwork.plctlab.org/api/1.2/patches/6101/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ddff80db3328a2286fe6fbc1240d2abc1e3813eb.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-20T09:26:02","name":"[16/40] sim/lm32: fix some missing function declaration warnings","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ddff80db3328a2286fe6fbc1240d2abc1e3813eb.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6094,"url":"https://patchwork.plctlab.org/api/1.2/patches/6094/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e094b1379231d9ffb59a78cfebbcc84634c779c6.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-20T09:26:03","name":"[17/40] sim/lm32: Add explicit casts","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e094b1379231d9ffb59a78cfebbcc84634c779c6.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6141,"url":"https://patchwork.plctlab.org/api/1.2/patches/6141/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/cabebead-489b-528c-580e-933832417474@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-20T10:25:51","name":"[1/3] x86: emit {evex} prefix when disassembling ambiguous AVX512VL insns","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/cabebead-489b-528c-580e-933832417474@suse.com/mbox/"},{"id":6143,"url":"https://patchwork.plctlab.org/api/1.2/patches/6143/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a032d61c-63a0-23d1-331f-619a2b8bbde3@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-20T10:26:15","name":"[2/3] x86: consolidate VAES tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a032d61c-63a0-23d1-331f-619a2b8bbde3@suse.com/mbox/"},{"id":6142,"url":"https://patchwork.plctlab.org/api/1.2/patches/6142/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7ff09c86-2de7-dc34-3183-5187de3df5ac@suse.com/","msgid":"<7ff09c86-2de7-dc34-3183-5187de3df5ac@suse.com>","list_archive_url":null,"date":"2022-10-20T10:26:40","name":"[3/3] x86: consolidate VPCLMUL tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7ff09c86-2de7-dc34-3183-5187de3df5ac@suse.com/mbox/"},{"id":6228,"url":"https://patchwork.plctlab.org/api/1.2/patches/6228/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.LSU.2.20.2210201432170.29399@wotan.suse.de/","msgid":"","list_archive_url":null,"date":"2022-10-20T14:42:25","name":"x86-64: Use only one default max-page-size","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.LSU.2.20.2210201432170.29399@wotan.suse.de/mbox/"},{"id":6229,"url":"https://patchwork.plctlab.org/api/1.2/patches/6229/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221020144351.1398099-1-chigot@adacore.com/","msgid":"<20221020144351.1398099-1-chigot@adacore.com>","list_archive_url":null,"date":"2022-10-20T14:43:50","name":"[1/2] ld/testsuite: skip ld-elf/exclude when -shared is not supported","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221020144351.1398099-1-chigot@adacore.com/mbox/"},{"id":6230,"url":"https://patchwork.plctlab.org/api/1.2/patches/6230/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221020144351.1398099-2-chigot@adacore.com/","msgid":"<20221020144351.1398099-2-chigot@adacore.com>","list_archive_url":null,"date":"2022-10-20T14:43:51","name":"[2/2] ld/testsuite: adjust ld-arm to run shared tests only when supported","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221020144351.1398099-2-chigot@adacore.com/mbox/"},{"id":6236,"url":"https://patchwork.plctlab.org/api/1.2/patches/6236/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221020151027.GA1300@delia.home/","msgid":"<20221020151027.GA1300@delia.home>","list_archive_url":null,"date":"2022-10-20T15:10:28","name":"[RFC,top-level] Add configure test-case","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221020151027.GA1300@delia.home/mbox/"},{"id":6286,"url":"https://patchwork.plctlab.org/api/1.2/patches/6286/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221020162911.1113338-1-hjl.tools@gmail.com/","msgid":"<20221020162911.1113338-1-hjl.tools@gmail.com>","list_archive_url":null,"date":"2022-10-20T16:29:11","name":"x86: Check VEX/EVEX encoding before checking vector operands","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221020162911.1113338-1-hjl.tools@gmail.com/mbox/"},{"id":7884,"url":"https://patchwork.plctlab.org/api/1.2/patches/7884/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7e53b7980f2b3b74d2250bc87f5db94b1d888a2d.camel@espressif.com/","msgid":"<7e53b7980f2b3b74d2250bc87f5db94b1d888a2d.camel@espressif.com>","list_archive_url":null,"date":"2022-10-22T12:53:54","name":"[1/5] bfd: xtensa: move common code from ld and gas","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7e53b7980f2b3b74d2250bc87f5db94b1d888a2d.camel@espressif.com/mbox/"},{"id":7885,"url":"https://patchwork.plctlab.org/api/1.2/patches/7885/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/63f2699e6ef3e6d1ca415a6ed1187d4f64297521.camel@espressif.com/","msgid":"<63f2699e6ef3e6d1ca415a6ed1187d4f64297521.camel@espressif.com>","list_archive_url":null,"date":"2022-10-22T12:55:16","name":"[2/5] gas: xtensa: add endianness, loops, booleans options","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/63f2699e6ef3e6d1ca415a6ed1187d4f64297521.camel@espressif.com/mbox/"},{"id":7886,"url":"https://patchwork.plctlab.org/api/1.2/patches/7886/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/34d2f747237aeeda595560cfded8096d9bd1c28c.camel@espressif.com/","msgid":"<34d2f747237aeeda595560cfded8096d9bd1c28c.camel@espressif.com>","list_archive_url":null,"date":"2022-10-22T12:56:02","name":"[3/5] ld: xtensa: use default LD command line options for endianness","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/34d2f747237aeeda595560cfded8096d9bd1c28c.camel@espressif.com/mbox/"},{"id":7891,"url":"https://patchwork.plctlab.org/api/1.2/patches/7891/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/535b6208c1718b9acf3258575e1ebc0a65af9f07.camel@espressif.com/","msgid":"<535b6208c1718b9acf3258575e1ebc0a65af9f07.camel@espressif.com>","list_archive_url":null,"date":"2022-10-22T13:56:44","name":"[5/5] gdb: xtensa: add support for esp32, esp32s2, esp32s3 isa-modules","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/535b6208c1718b9acf3258575e1ebc0a65af9f07.camel@espressif.com/mbox/"},{"id":10456,"url":"https://patchwork.plctlab.org/api/1.2/patches/10456/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221025013347.68282-1-nelson@rivosinc.com/","msgid":"<20221025013347.68282-1-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-10-25T01:33:46","name":"[committed,1/2] RISC-V: Improve link time complexity.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221025013347.68282-1-nelson@rivosinc.com/mbox/"},{"id":10454,"url":"https://patchwork.plctlab.org/api/1.2/patches/10454/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221025013347.68282-2-nelson@rivosinc.com/","msgid":"<20221025013347.68282-2-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-10-25T01:33:47","name":"[committed,2/2] RISC-V: Should reset `again'\'' flag for _bfd_riscv_relax_pc.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221025013347.68282-2-nelson@rivosinc.com/mbox/"},{"id":10536,"url":"https://patchwork.plctlab.org/api/1.2/patches/10536/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/bb7b87e4-1893-5c86-4a14-92bafc818b03@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-25T07:24:56","name":"[v5,1/8] x86: constify parse_insn()'\''s input","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/bb7b87e4-1893-5c86-4a14-92bafc818b03@suse.com/mbox/"},{"id":10537,"url":"https://patchwork.plctlab.org/api/1.2/patches/10537/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b9273ae6-0218-54f8-5374-b265ed13b71a@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-25T07:25:26","name":"[v5,1/8] x86: introduce Pass2 insn attribute","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b9273ae6-0218-54f8-5374-b265ed13b71a@suse.com/mbox/"},{"id":10541,"url":"https://patchwork.plctlab.org/api/1.2/patches/10541/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7250dab9-e218-e6dd-4c74-23da9f611ab4@suse.com/","msgid":"<7250dab9-e218-e6dd-4c74-23da9f611ab4@suse.com>","list_archive_url":null,"date":"2022-10-25T07:26:11","name":"[v5,3/8] x86: re-work insn/suffix recognition","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7250dab9-e218-e6dd-4c74-23da9f611ab4@suse.com/mbox/"},{"id":10540,"url":"https://patchwork.plctlab.org/api/1.2/patches/10540/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/13fc630f-e116-0099-5c9e-2697df6519d7@suse.com/","msgid":"<13fc630f-e116-0099-5c9e-2697df6519d7@suse.com>","list_archive_url":null,"date":"2022-10-25T07:26:40","name":"[v5,4/8] ix86: don'\''t recognize/derive Q suffix in the common case","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/13fc630f-e116-0099-5c9e-2697df6519d7@suse.com/mbox/"},{"id":10543,"url":"https://patchwork.plctlab.org/api/1.2/patches/10543/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/74db429d-d203-eab8-4ae1-18b9ad416b02@suse.com/","msgid":"<74db429d-d203-eab8-4ae1-18b9ad416b02@suse.com>","list_archive_url":null,"date":"2022-10-25T07:27:11","name":"[v5,5/8] x86-64: allow HLE store of accumulator to absolute 32-bit address","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/74db429d-d203-eab8-4ae1-18b9ad416b02@suse.com/mbox/"},{"id":10542,"url":"https://patchwork.plctlab.org/api/1.2/patches/10542/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2e2f7841-de4e-b5de-e8d9-a47a6a4113c8@suse.com/","msgid":"<2e2f7841-de4e-b5de-e8d9-a47a6a4113c8@suse.com>","list_archive_url":null,"date":"2022-10-25T07:27:35","name":"[v5,6/8] x86: move bad-use-of-TLS-reloc check","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2e2f7841-de4e-b5de-e8d9-a47a6a4113c8@suse.com/mbox/"},{"id":10545,"url":"https://patchwork.plctlab.org/api/1.2/patches/10545/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/421bc96e-7591-6980-48e9-5af8c8b0775a@suse.com/","msgid":"<421bc96e-7591-6980-48e9-5af8c8b0775a@suse.com>","list_archive_url":null,"date":"2022-10-25T07:28:27","name":"[v5,7/8] x86: drop (now) stray IsString","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/421bc96e-7591-6980-48e9-5af8c8b0775a@suse.com/mbox/"},{"id":10546,"url":"https://patchwork.plctlab.org/api/1.2/patches/10546/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/06ff83d4-4633-a07b-70e5-a8e049981dd4@suse.com/","msgid":"<06ff83d4-4633-a07b-70e5-a8e049981dd4@suse.com>","list_archive_url":null,"date":"2022-10-25T07:29:18","name":"[v5,8/8] x86: further re-work insn/suffix recognition to also cover MOVSX","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/06ff83d4-4633-a07b-70e5-a8e049981dd4@suse.com/mbox/"},{"id":10777,"url":"https://patchwork.plctlab.org/api/1.2/patches/10777/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6a8e7a71acccd0efb9789dfb3edfa307e83bdaa1.1666702934.git.research_trasio@irq.a4lg.com/","msgid":"<6a8e7a71acccd0efb9789dfb3edfa307e83bdaa1.1666702934.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-25T13:04:02","name":"[RFC] RISC-V: Allocate \"various\" operand type","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6a8e7a71acccd0efb9789dfb3edfa307e83bdaa1.1666702934.git.research_trasio@irq.a4lg.com/mbox/"},{"id":11062,"url":"https://patchwork.plctlab.org/api/1.2/patches/11062/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jAhwbXhxJHL66v@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-26T05:07:19","name":"PR29720, objdump -S crashes if build-id is missing","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jAhwbXhxJHL66v@squeak.grove.modra.org/mbox/"},{"id":11063,"url":"https://patchwork.plctlab.org/api/1.2/patches/11063/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jAxD+NxpMIah6s@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-26T05:08:20","name":"som.c buffer overflow","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jAxD+NxpMIah6s@squeak.grove.modra.org/mbox/"},{"id":11064,"url":"https://patchwork.plctlab.org/api/1.2/patches/11064/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jBYw4lfRQfOZhi@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-26T05:10:59","name":"som.c reloc sanity checking","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jBYw4lfRQfOZhi@squeak.grove.modra.org/mbox/"},{"id":11080,"url":"https://patchwork.plctlab.org/api/1.2/patches/11080/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jY7hygm01PelCY@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-26T06:51:26","name":"segfault in objdump.c reloc_at","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jY7hygm01PelCY@squeak.grove.modra.org/mbox/"},{"id":11081,"url":"https://patchwork.plctlab.org/api/1.2/patches/11081/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jZWIeIvCCYm9/g@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-26T06:53:12","name":"Correct ELF reloc size sanity check","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jZWIeIvCCYm9/g@squeak.grove.modra.org/mbox/"},{"id":11082,"url":"https://patchwork.plctlab.org/api/1.2/patches/11082/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221026070009.3663574-1-ysato@users.sourceforge.jp/","msgid":"<20221026070009.3663574-1-ysato@users.sourceforge.jp>","list_archive_url":null,"date":"2022-10-26T07:00:09","name":"opcodes: RX fix invalid output.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221026070009.3663574-1-ysato@users.sourceforge.jp/mbox/"},{"id":11089,"url":"https://patchwork.plctlab.org/api/1.2/patches/11089/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jhW48kuVC8Ig2d@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-26T07:27:23","name":"buffer overflow in _bfd_XX_print_ce_compressed_pdata","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jhW48kuVC8Ig2d@squeak.grove.modra.org/mbox/"},{"id":11157,"url":"https://patchwork.plctlab.org/api/1.2/patches/11157/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c52dbd16-7e1b-c356-7a92-1ff089564ef7@suse.cz/","msgid":"","list_archive_url":null,"date":"2022-10-26T08:47:09","name":"tests: use canonical option name","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c52dbd16-7e1b-c356-7a92-1ff089564ef7@suse.cz/mbox/"},{"id":11526,"url":"https://patchwork.plctlab.org/api/1.2/patches/11526/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027031915.4013-1-lifang_xia@linux.alibaba.com/","msgid":"<20221027031915.4013-1-lifang_xia@linux.alibaba.com>","list_archive_url":null,"date":"2022-10-27T03:19:15","name":"[v2] RISC-V: Optimize relax of GP/call with max_alignment.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027031915.4013-1-lifang_xia@linux.alibaba.com/mbox/"},{"id":11619,"url":"https://patchwork.plctlab.org/api/1.2/patches/11619/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9df9d9e5bb4c7594b76c40613a349b4d2364e9c5.1666854355.git.research_trasio@irq.a4lg.com/","msgid":"<9df9d9e5bb4c7594b76c40613a349b4d2364e9c5.1666854355.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-27T07:06:01","name":"include: Define macro to ignore -Wdeprecated-declarations on GCC","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9df9d9e5bb4c7594b76c40613a349b4d2364e9c5.1666854355.git.research_trasio@irq.a4lg.com/mbox/"},{"id":11627,"url":"https://patchwork.plctlab.org/api/1.2/patches/11627/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1o06O9Pp8ncCsOw@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-27T07:36:08","name":"Fuzzed files in archives","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1o06O9Pp8ncCsOw@squeak.grove.modra.org/mbox/"},{"id":11658,"url":"https://patchwork.plctlab.org/api/1.2/patches/11658/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027084808.37252-1-nelson@rivosinc.com/","msgid":"<20221027084808.37252-1-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-10-27T08:48:08","name":"[committed] RISC-V: Fix build failures for -Werror=sign-compare.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027084808.37252-1-nelson@rivosinc.com/mbox/"},{"id":11921,"url":"https://patchwork.plctlab.org/api/1.2/patches/11921/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027190052.10536-1-mark@harmstone.com/","msgid":"<20221027190052.10536-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-27T19:00:51","name":"[1/2] ld: Add section header stream to PDB files","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027190052.10536-1-mark@harmstone.com/mbox/"},{"id":11922,"url":"https://patchwork.plctlab.org/api/1.2/patches/11922/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027190052.10536-2-mark@harmstone.com/","msgid":"<20221027190052.10536-2-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-27T19:00:52","name":"[2/2] ld: Add publics stream to PDB files","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027190052.10536-2-mark@harmstone.com/mbox/"},{"id":11965,"url":"https://patchwork.plctlab.org/api/1.2/patches/11965/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027202719.32497-1-palmer@rivosinc.com/","msgid":"<20221027202719.32497-1-palmer@rivosinc.com>","list_archive_url":null,"date":"2022-10-27T20:27:18","name":"[1/2] gas: NEWS: Add a missing newline","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027202719.32497-1-palmer@rivosinc.com/mbox/"},{"id":11966,"url":"https://patchwork.plctlab.org/api/1.2/patches/11966/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027202719.32497-2-palmer@rivosinc.com/","msgid":"<20221027202719.32497-2-palmer@rivosinc.com>","list_archive_url":null,"date":"2022-10-27T20:27:19","name":"[2/2] gas: NEWS: Note support for RISC-V Zawrs","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027202719.32497-2-palmer@rivosinc.com/mbox/"},{"id":12016,"url":"https://patchwork.plctlab.org/api/1.2/patches/12016/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/21ec9a18-fa89-0828-f625-499680022ec7@linux.ibm.com/","msgid":"<21ec9a18-fa89-0828-f625-499680022ec7@linux.ibm.com>","list_archive_url":null,"date":"2022-10-28T00:35:19","name":"[COMMITTED] PowerPC: Add support for RFC02653 - Dense Math Facility","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/21ec9a18-fa89-0828-f625-499680022ec7@linux.ibm.com/mbox/"},{"id":12017,"url":"https://patchwork.plctlab.org/api/1.2/patches/12017/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fd94047d-a070-45a6-3840-c105391718e0@linux.ibm.com/","msgid":"","list_archive_url":null,"date":"2022-10-28T00:37:18","name":"[COMMITTED] PowerPC: Add support for RFC02658 - MMA+ Outer-Product, Instructions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fd94047d-a070-45a6-3840-c105391718e0@linux.ibm.com/mbox/"},{"id":12122,"url":"https://patchwork.plctlab.org/api/1.2/patches/12122/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ac4f3f3c7115a824f73aca6935789b14d33c9a58.1666939920.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-28T06:53:02","name":"RISC-V: Fix build failure for -Werror=maybe-uninitialized","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ac4f3f3c7115a824f73aca6935789b14d33c9a58.1666939920.git.research_trasio@irq.a4lg.com/mbox/"},{"id":12181,"url":"https://patchwork.plctlab.org/api/1.2/patches/12181/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221028093840.19164-1-nelson@rivosinc.com/","msgid":"<20221028093840.19164-1-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-10-28T09:38:40","name":"RISC-V: Added SiFive custom cache control extensions.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221028093840.19164-1-nelson@rivosinc.com/mbox/"},{"id":12211,"url":"https://patchwork.plctlab.org/api/1.2/patches/12211/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4a280588-a85b-6ed3-634b-2b9cbc128f86@suse.com/","msgid":"<4a280588-a85b-6ed3-634b-2b9cbc128f86@suse.com>","list_archive_url":null,"date":"2022-10-28T10:06:35","name":"RISC-V/gas: fix build with certain gcc versions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4a280588-a85b-6ed3-634b-2b9cbc128f86@suse.com/mbox/"},{"id":12249,"url":"https://patchwork.plctlab.org/api/1.2/patches/12249/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/eb0e1bff-675e-72db-b8b1-b0f0e50b7121@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-28T12:35:35","name":"x86: minor improvements to optimize_imm() (part III)","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/eb0e1bff-675e-72db-b8b1-b0f0e50b7121@suse.com/mbox/"},{"id":12382,"url":"https://patchwork.plctlab.org/api/1.2/patches/12382/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/17f57574936af82be381a1451eac56b3709b60bb.1666968673.git.research_trasio@irq.a4lg.com/","msgid":"<17f57574936af82be381a1451eac56b3709b60bb.1666968673.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-28T14:52:12","name":"RISC-V: Emit mapping symbol with ISA string if non-default arch is used","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/17f57574936af82be381a1451eac56b3709b60bb.1666968673.git.research_trasio@irq.a4lg.com/mbox/"},{"id":12627,"url":"https://patchwork.plctlab.org/api/1.2/patches/12627/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221029034432.49859-1-nelson@rivosinc.com/","msgid":"<20221029034432.49859-1-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-10-29T03:44:32","name":"[committed] RISC-V: Always generate mapping symbols at the start of the sections.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221029034432.49859-1-nelson@rivosinc.com/mbox/"},{"id":12629,"url":"https://patchwork.plctlab.org/api/1.2/patches/12629/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1yxgzNJg5M48uPI@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-29T04:52:19","name":"NULL dereference read in som_write_object_contents","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1yxgzNJg5M48uPI@squeak.grove.modra.org/mbox/"},{"id":12630,"url":"https://patchwork.plctlab.org/api/1.2/patches/12630/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1yxnSHLY+FeB5DQ@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-29T04:52:45","name":"Fix small objcopy memory leak","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1yxnSHLY+FeB5DQ@squeak.grove.modra.org/mbox/"},{"id":12631,"url":"https://patchwork.plctlab.org/api/1.2/patches/12631/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1yxxfpJz+Jx4KTh@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-29T04:53:25","name":"pef: sanity check before malloc","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1yxxfpJz+Jx4KTh@squeak.grove.modra.org/mbox/"},{"id":12950,"url":"https://patchwork.plctlab.org/api/1.2/patches/12950/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-2-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-2-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:36","name":"[V3,01/15] sframe.h: Add SFrame format definition","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-2-indu.bhagat@oracle.com/mbox/"},{"id":12952,"url":"https://patchwork.plctlab.org/api/1.2/patches/12952/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-3-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-3-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:37","name":"[V3,02/15] gas: add new command line option --gsframe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-3-indu.bhagat@oracle.com/mbox/"},{"id":12951,"url":"https://patchwork.plctlab.org/api/1.2/patches/12951/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-4-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-4-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:38","name":"[V3,03/15] gas: generate .sframe from CFI directives","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-4-indu.bhagat@oracle.com/mbox/"},{"id":12956,"url":"https://patchwork.plctlab.org/api/1.2/patches/12956/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-5-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-5-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:39","name":"[V3,04/15] gas: testsuite: add new tests for SFrame unwind info","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-5-indu.bhagat@oracle.com/mbox/"},{"id":12955,"url":"https://patchwork.plctlab.org/api/1.2/patches/12955/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-6-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-6-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:40","name":"[V3,05/15] libsframe: add the SFrame library","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-6-indu.bhagat@oracle.com/mbox/"},{"id":12959,"url":"https://patchwork.plctlab.org/api/1.2/patches/12959/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-7-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-7-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:41","name":"[V3,06/15] bfd: linker: merge .sframe sections","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-7-indu.bhagat@oracle.com/mbox/"},{"id":12961,"url":"https://patchwork.plctlab.org/api/1.2/patches/12961/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-8-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-8-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:42","name":"[V3,07/15] readelf/objdump: support for SFrame section","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-8-indu.bhagat@oracle.com/mbox/"},{"id":12962,"url":"https://patchwork.plctlab.org/api/1.2/patches/12962/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-9-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-9-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:43","name":"[V3,08/15] unwinder: generate backtrace using SFrame format","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-9-indu.bhagat@oracle.com/mbox/"},{"id":12963,"url":"https://patchwork.plctlab.org/api/1.2/patches/12963/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-10-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-10-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:44","name":"[V3,09/15] unwinder: Add SFrame unwinder tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-10-indu.bhagat@oracle.com/mbox/"},{"id":12964,"url":"https://patchwork.plctlab.org/api/1.2/patches/12964/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-11-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-11-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:45","name":"[V3,10/15] gdb: sim: buildsystem changes to accommodate libsframe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-11-indu.bhagat@oracle.com/mbox/"},{"id":12957,"url":"https://patchwork.plctlab.org/api/1.2/patches/12957/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-12-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-12-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:46","name":"[V3,11/15] libctf: add libsframe to LDFLAGS and LIBS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-12-indu.bhagat@oracle.com/mbox/"},{"id":12960,"url":"https://patchwork.plctlab.org/api/1.2/patches/12960/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-13-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-13-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:47","name":"[V3,12/15] src-release.sh: Add libsframe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-13-indu.bhagat@oracle.com/mbox/"},{"id":12953,"url":"https://patchwork.plctlab.org/api/1.2/patches/12953/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-14-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-14-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:48","name":"[V3,13/15] binutils/NEWS: add text for SFrame support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-14-indu.bhagat@oracle.com/mbox/"},{"id":12954,"url":"https://patchwork.plctlab.org/api/1.2/patches/12954/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-15-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-15-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:49","name":"[V3,14/15] gas/NEWS: add text about new command line option and SFrame support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-15-indu.bhagat@oracle.com/mbox/"},{"id":12958,"url":"https://patchwork.plctlab.org/api/1.2/patches/12958/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-16-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-16-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:50","name":"[V3,15/15] doc: add SFrame spec file","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-16-indu.bhagat@oracle.com/mbox/"},{"id":12988,"url":"https://patchwork.plctlab.org/api/1.2/patches/12988/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y15KFY32CyFhh/+u@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-30T09:55:33","name":"Pool section entries for DWP version 1","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y15KFY32CyFhh/+u@squeak.grove.modra.org/mbox/"},{"id":13076,"url":"https://patchwork.plctlab.org/api/1.2/patches/13076/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031001554.14615-1-mark@harmstone.com/","msgid":"<20221031001554.14615-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-31T00:15:52","name":"[v2,1/3] ld: Use %E in einfo in pdb.c","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031001554.14615-1-mark@harmstone.com/mbox/"},{"id":13078,"url":"https://patchwork.plctlab.org/api/1.2/patches/13078/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031001554.14615-2-mark@harmstone.com/","msgid":"<20221031001554.14615-2-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-31T00:15:53","name":"[v2,2/3] ld: Add section header stream to PDB files","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031001554.14615-2-mark@harmstone.com/mbox/"},{"id":13077,"url":"https://patchwork.plctlab.org/api/1.2/patches/13077/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031001554.14615-3-mark@harmstone.com/","msgid":"<20221031001554.14615-3-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-31T00:15:54","name":"[v2,3/3] ld: Add publics stream to PDB files","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031001554.14615-3-mark@harmstone.com/mbox/"},{"id":13106,"url":"https://patchwork.plctlab.org/api/1.2/patches/13106/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031030507.35588-2-haochen.jiang@intel.com/","msgid":"<20221031030507.35588-2-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-31T03:05:02","name":"[1/6] Support Intel AVX-IFMA","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031030507.35588-2-haochen.jiang@intel.com/mbox/"},{"id":13105,"url":"https://patchwork.plctlab.org/api/1.2/patches/13105/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031030507.35588-3-haochen.jiang@intel.com/","msgid":"<20221031030507.35588-3-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-31T03:05:03","name":"[2/6] Support Intel AVX-VNNI-INT8","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031030507.35588-3-haochen.jiang@intel.com/mbox/"},{"id":13103,"url":"https://patchwork.plctlab.org/api/1.2/patches/13103/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031030507.35588-4-haochen.jiang@intel.com/","msgid":"<20221031030507.35588-4-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-31T03:05:04","name":"[3/6] Support Intel CMPccXADD","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031030507.35588-4-haochen.jiang@intel.com/mbox/"},{"id":13101,"url":"https://patchwork.plctlab.org/api/1.2/patches/13101/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031030507.35588-5-haochen.jiang@intel.com/","msgid":"<20221031030507.35588-5-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-31T03:05:05","name":"[4/6] Add handler for more i386_cpu_flags","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031030507.35588-5-haochen.jiang@intel.com/mbox/"},{"id":13104,"url":"https://patchwork.plctlab.org/api/1.2/patches/13104/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031030507.35588-6-haochen.jiang@intel.com/","msgid":"<20221031030507.35588-6-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-31T03:05:06","name":"[5/6] Support Intel WRMSRNS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031030507.35588-6-haochen.jiang@intel.com/mbox/"},{"id":13102,"url":"https://patchwork.plctlab.org/api/1.2/patches/13102/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031030507.35588-7-haochen.jiang@intel.com/","msgid":"<20221031030507.35588-7-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-31T03:05:07","name":"[6/6] Support Intel MSRLIST","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031030507.35588-7-haochen.jiang@intel.com/mbox/"},{"id":13120,"url":"https://patchwork.plctlab.org/api/1.2/patches/13120/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031060601.38460-2-haochen.jiang@intel.com/","msgid":"<20221031060601.38460-2-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-31T06:06:00","name":"[1/2] i386: Add and ","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031060601.38460-2-haochen.jiang@intel.com/mbox/"},{"id":13121,"url":"https://patchwork.plctlab.org/api/1.2/patches/13121/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031060601.38460-3-haochen.jiang@intel.com/","msgid":"<20221031060601.38460-3-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-31T06:06:01","name":"[2/2] Support Intel AVX-NE-CONVERT","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031060601.38460-3-haochen.jiang@intel.com/mbox/"},{"id":13188,"url":"https://patchwork.plctlab.org/api/1.2/patches/13188/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9f6f8888-4dc1-a6b0-0590-35fc8a276369@suse.com/","msgid":"<9f6f8888-4dc1-a6b0-0590-35fc8a276369@suse.com>","list_archive_url":null,"date":"2022-10-31T10:18:20","name":"x86: drop bogus Tbyte","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9f6f8888-4dc1-a6b0-0590-35fc8a276369@suse.com/mbox/"},{"id":13213,"url":"https://patchwork.plctlab.org/api/1.2/patches/13213/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4f1aac95-fea5-2279-cb18-dfcdb51a2589@arm.com/","msgid":"<4f1aac95-fea5-2279-cb18-dfcdb51a2589@arm.com>","list_archive_url":null,"date":"2022-10-31T11:14:44","name":"aarch64: Add support for Common Short Sequence Compression extension","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4f1aac95-fea5-2279-cb18-dfcdb51a2589@arm.com/mbox/"}],"public":true,"mbox":"https://patchwork.plctlab.org/bundle/patchwork-bot/binutils-gdb_2022-10/mbox/"},{"id":7,"url":"https://patchwork.plctlab.org/api/1.2/bundles/7/","web_url":"https://patchwork.plctlab.org/bundle/patchwork-bot/binutils-gdb_2022-09/","project":{"id":2,"url":"https://patchwork.plctlab.org/api/1.2/projects/2/","name":"binutils-gdb","link_name":"binutils-gdb","list_id":"binutils.sourceware.org","list_email":"binutils@sourceware.org","web_url":"https://github.com/wangliu-iscas/Patchwork-Bundles/blob/main/binutils-gdb.md","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"name":"binutils-gdb_2022-09","owner":{"id":3,"url":"https://patchwork.plctlab.org/api/1.2/users/3/","username":"patchwork-bot","first_name":"","last_name":"","email":"ouuuleilei@gmail.com"},"patches":[{"id":1573,"url":"https://patchwork.plctlab.org/api/1.2/patches/1573/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930073211.2634-1-jiawei@iscas.ac.cn/","msgid":"<20220930073211.2634-1-jiawei@iscas.ac.cn>","list_archive_url":null,"date":"2022-09-30T07:32:11","name":"[V2] RISC-V: Add Smepmp CSR '\''mseccfg'\'' define and testcases.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930073211.2634-1-jiawei@iscas.ac.cn/mbox/"},{"id":1577,"url":"https://patchwork.plctlab.org/api/1.2/patches/1577/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/76fa0c3c-2303-ebdf-a765-ac4731581517@suse.com/","msgid":"<76fa0c3c-2303-ebdf-a765-ac4731581517@suse.com>","list_archive_url":null,"date":"2022-09-30T08:54:18","name":"objcopy: avoid \"shadowing\" of remove() function name","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/76fa0c3c-2303-ebdf-a765-ac4731581517@suse.com/mbox/"},{"id":1579,"url":"https://patchwork.plctlab.org/api/1.2/patches/1579/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930085852.71213-1-nelson@rivosinc.com/","msgid":"<20220930085852.71213-1-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-09-30T08:58:51","name":"[1/2] RISC-V: Output mapping symbols with ISA string.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930085852.71213-1-nelson@rivosinc.com/mbox/"},{"id":1578,"url":"https://patchwork.plctlab.org/api/1.2/patches/1578/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930085852.71213-2-nelson@rivosinc.com/","msgid":"<20220930085852.71213-2-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-09-30T08:58:52","name":"[2/2] RISC-V: Refer mapping symbol to R_RISCV_RELAX for rvc relaxations.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930085852.71213-2-nelson@rivosinc.com/mbox/"},{"id":1581,"url":"https://patchwork.plctlab.org/api/1.2/patches/1581/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930092058.71286-1-nelson@rivosinc.com/","msgid":"<20220930092058.71286-1-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-09-30T09:20:57","name":"[1/2] RISC-V: Output mapping symbols with ISA string.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930092058.71286-1-nelson@rivosinc.com/mbox/"},{"id":1580,"url":"https://patchwork.plctlab.org/api/1.2/patches/1580/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930092058.71286-2-nelson@rivosinc.com/","msgid":"<20220930092058.71286-2-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-09-30T09:20:58","name":"[2/2] RISC-V: Refer mapping symbol to R_RISCV_RELAX for rvc relaxations.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930092058.71286-2-nelson@rivosinc.com/mbox/"},{"id":1582,"url":"https://patchwork.plctlab.org/api/1.2/patches/1582/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5874dd79-0cf5-d65c-7ea2-13adfc799c0f@suse.com/","msgid":"<5874dd79-0cf5-d65c-7ea2-13adfc799c0f@suse.com>","list_archive_url":null,"date":"2022-09-30T09:41:29","name":"RISC-V: fix build after \"Add support for arbitrary immediate encoding formats\"","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5874dd79-0cf5-d65c-7ea2-13adfc799c0f@suse.com/mbox/"},{"id":1583,"url":"https://patchwork.plctlab.org/api/1.2/patches/1583/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/57d8ac2a-5757-3776-9924-99c17ca69938@suse.com/","msgid":"<57d8ac2a-5757-3776-9924-99c17ca69938@suse.com>","list_archive_url":null,"date":"2022-09-30T09:42:08","name":"RISC-V: fallout from \"re-arrange opcode table for consistent alias handling\"","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/57d8ac2a-5757-3776-9924-99c17ca69938@suse.com/mbox/"},{"id":1584,"url":"https://patchwork.plctlab.org/api/1.2/patches/1584/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e76ef8f7-72b9-5103-cb43-9608af01d017@suse.com/","msgid":"","list_archive_url":null,"date":"2022-09-30T09:42:50","name":"RISC-V: don'\''t cast expressions'\'' X_add_number to long in diagnostics","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e76ef8f7-72b9-5103-cb43-9608af01d017@suse.com/mbox/"},{"id":1585,"url":"https://patchwork.plctlab.org/api/1.2/patches/1585/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/61355429-24b3-17d0-ab03-6fa57ee861d5@suse.cz/","msgid":"<61355429-24b3-17d0-ab03-6fa57ee861d5@suse.cz>","list_archive_url":null,"date":"2022-09-30T09:48:52","name":"[RFC] add --enable-zstd-compressed-debug-sections configure option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/61355429-24b3-17d0-ab03-6fa57ee861d5@suse.cz/mbox/"},{"id":1586,"url":"https://patchwork.plctlab.org/api/1.2/patches/1586/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930103919.323690-1-christoph.muellner@vrull.eu/","msgid":"<20220930103919.323690-1-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2022-09-30T10:39:19","name":"RISC-V: Eliminate long-casts of X_add_number in diagnostics","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930103919.323690-1-christoph.muellner@vrull.eu/mbox/"},{"id":1590,"url":"https://patchwork.plctlab.org/api/1.2/patches/1590/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/DM6PR12MB4219C943049C6D883DEA3E55E7569@DM6PR12MB4219.namprd12.prod.outlook.com/","msgid":"","list_archive_url":null,"date":"2022-09-30T11:41:37","name":"[V2] Ignore DWARF debug information for -gsplit-dwarf with dwarf-5.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/DM6PR12MB4219C943049C6D883DEA3E55E7569@DM6PR12MB4219.namprd12.prod.outlook.com/mbox/"},{"id":1591,"url":"https://patchwork.plctlab.org/api/1.2/patches/1591/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c10321f9-d289-ef84-d263-bc278fb3d31b@suse.com/","msgid":"","list_archive_url":null,"date":"2022-09-30T11:59:04","name":"[1/4] RISC-V/gas: drop riscv_subsets static variable","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c10321f9-d289-ef84-d263-bc278fb3d31b@suse.com/mbox/"},{"id":1593,"url":"https://patchwork.plctlab.org/api/1.2/patches/1593/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3244eea0-c18c-e49a-4588-d69423130226@suse.com/","msgid":"<3244eea0-c18c-e49a-4588-d69423130226@suse.com>","list_archive_url":null,"date":"2022-09-30T11:59:23","name":"[2/4] RISC-V/gas: drop stray call to install_insn()","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3244eea0-c18c-e49a-4588-d69423130226@suse.com/mbox/"},{"id":1592,"url":"https://patchwork.plctlab.org/api/1.2/patches/1592/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/385d01fd-7e57-1f3f-1bae-30aa0c313d63@suse.com/","msgid":"<385d01fd-7e57-1f3f-1bae-30aa0c313d63@suse.com>","list_archive_url":null,"date":"2022-09-30T11:59:45","name":"[3/4] RISC-V/gas: don'\''t open-code insn_length()","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/385d01fd-7e57-1f3f-1bae-30aa0c313d63@suse.com/mbox/"},{"id":1594,"url":"https://patchwork.plctlab.org/api/1.2/patches/1594/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f5757acf-7b90-a0e3-5eea-3b97cc226930@suse.com/","msgid":"","list_archive_url":null,"date":"2022-09-30T12:00:12","name":"[4/4] RISC-V/gas: allow generating up to 176-bit instructions with .insn","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f5757acf-7b90-a0e3-5eea-3b97cc226930@suse.com/mbox/"},{"id":1596,"url":"https://patchwork.plctlab.org/api/1.2/patches/1596/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930140503.38233-1-chigot@adacore.com/","msgid":"<20220930140503.38233-1-chigot@adacore.com>","list_archive_url":null,"date":"2022-09-30T14:05:03","name":"ld/testsuite: consistently add board_ldflags when linking with GCC","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930140503.38233-1-chigot@adacore.com/mbox/"}],"public":true,"mbox":"https://patchwork.plctlab.org/bundle/patchwork-bot/binutils-gdb_2022-09/mbox/"},{"id":9,"url":"https://patchwork.plctlab.org/api/1.2/bundles/9/","web_url":"https://patchwork.plctlab.org/bundle/patchwork-bot/binutils-gdb_2022-11/","project":{"id":2,"url":"https://patchwork.plctlab.org/api/1.2/projects/2/","name":"binutils-gdb","link_name":"binutils-gdb","list_id":"binutils.sourceware.org","list_email":"binutils@sourceware.org","web_url":"https://github.com/wangliu-iscas/Patchwork-Bundles/blob/main/binutils-gdb.md","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"name":"binutils-gdb_2022-11","owner":{"id":3,"url":"https://patchwork.plctlab.org/api/1.2/users/3/","username":"patchwork-bot","first_name":"","last_name":"","email":"ouuuleilei@gmail.com"},"patches":[{"id":13337,"url":"https://patchwork.plctlab.org/api/1.2/patches/13337/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031160625.684434-1-hjl.tools@gmail.com/","msgid":"<20221031160625.684434-1-hjl.tools@gmail.com>","list_archive_url":null,"date":"2022-10-31T16:06:25","name":"x86: Silence GCC 12 warning on tc-i386.c","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031160625.684434-1-hjl.tools@gmail.com/mbox/"},{"id":13350,"url":"https://patchwork.plctlab.org/api/1.2/patches/13350/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c8d25b29-37fe-9623-a799-e67e1f991743@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-31T17:00:56","name":"x86: simplify expressions in update_imm()","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c8d25b29-37fe-9623-a799-e67e1f991743@suse.com/mbox/"},{"id":13487,"url":"https://patchwork.plctlab.org/api/1.2/patches/13487/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/CAMe9rOohVjin92PTeeiu_dvAtzYJn4dGtu5E=OxYfbyteraZWw@mail.gmail.com/","msgid":"","list_archive_url":null,"date":"2022-11-01T00:08:04","name":"binutils: Run PR binutils/26160 test","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/CAMe9rOohVjin92PTeeiu_dvAtzYJn4dGtu5E=OxYfbyteraZWw@mail.gmail.com/mbox/"},{"id":13621,"url":"https://patchwork.plctlab.org/api/1.2/patches/13621/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221101105724.1527333-1-aburgess@redhat.com/","msgid":"<20221101105724.1527333-1-aburgess@redhat.com>","list_archive_url":null,"date":"2022-11-01T10:57:24","name":"[PUSHED] opcodes/arm: silence compiler warning about uninitialized variable use","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221101105724.1527333-1-aburgess@redhat.com/mbox/"},{"id":13628,"url":"https://patchwork.plctlab.org/api/1.2/patches/13628/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221101111802.1532080-1-aburgess@redhat.com/","msgid":"<20221101111802.1532080-1-aburgess@redhat.com>","list_archive_url":null,"date":"2022-11-01T11:18:02","name":"[PUSHED] opcodes/arm: don'\''t pass non-string literal to printf like function","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221101111802.1532080-1-aburgess@redhat.com/mbox/"},{"id":13747,"url":"https://patchwork.plctlab.org/api/1.2/patches/13747/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/yw8jbkpqk6vw.fsf@arm.com/","msgid":"","list_archive_url":null,"date":"2022-11-01T15:54:11","name":"[Binutils-2.39,backport,GAS] arm: Use DWARF numbering convention for pseudo-register representation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/yw8jbkpqk6vw.fsf@arm.com/mbox/"},{"id":13993,"url":"https://patchwork.plctlab.org/api/1.2/patches/13993/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221102020752.24441-1-mark@harmstone.com/","msgid":"<20221102020752.24441-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-11-02T02:07:52","name":"ld: Add module information substream to PDB files","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221102020752.24441-1-mark@harmstone.com/mbox/"},{"id":14028,"url":"https://patchwork.plctlab.org/api/1.2/patches/14028/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221102050430.1053-1-nelson@rivosinc.com/","msgid":"<20221102050430.1053-1-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-11-02T05:04:30","name":"[committed] RISC-V: Fixed the missing $x+arch when adding odd paddings for alignment.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221102050430.1053-1-nelson@rivosinc.com/mbox/"},{"id":14043,"url":"https://patchwork.plctlab.org/api/1.2/patches/14043/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221102063046.31551-1-rjiejie@linux.alibaba.com/","msgid":"<20221102063046.31551-1-rjiejie@linux.alibaba.com>","list_archive_url":null,"date":"2022-11-02T06:30:46","name":"gas/doc/internals.texi: fix typo","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221102063046.31551-1-rjiejie@linux.alibaba.com/mbox/"},{"id":14069,"url":"https://patchwork.plctlab.org/api/1.2/patches/14069/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221102080112.33378-1-rjiejie@linux.alibaba.com/","msgid":"<20221102080112.33378-1-rjiejie@linux.alibaba.com>","list_archive_url":null,"date":"2022-11-02T08:01:12","name":"[v2] Support multiple .eh_frame sections","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221102080112.33378-1-rjiejie@linux.alibaba.com/mbox/"},{"id":14409,"url":"https://patchwork.plctlab.org/api/1.2/patches/14409/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221102172923.4009281-1-christophe.lyon@arm.com/","msgid":"<20221102172923.4009281-1-christophe.lyon@arm.com>","list_archive_url":null,"date":"2022-11-02T17:29:23","name":"arm: PR 29739 Fix typo where '\''; '\'' should not have been replaced with '\''@'\''","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221102172923.4009281-1-christophe.lyon@arm.com/mbox/"},{"id":14588,"url":"https://patchwork.plctlab.org/api/1.2/patches/14588/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221103020409.37322-1-rjiejie@linux.alibaba.com/","msgid":"<20221103020409.37322-1-rjiejie@linux.alibaba.com>","list_archive_url":null,"date":"2022-11-03T02:04:09","name":"[v3] Support multiple .eh_frame sections","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221103020409.37322-1-rjiejie@linux.alibaba.com/mbox/"},{"id":14602,"url":"https://patchwork.plctlab.org/api/1.2/patches/14602/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221103024604.614-1-mark@harmstone.com/","msgid":"<20221103024604.614-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-11-03T02:46:04","name":"[v2] ld: Add module information substream to PDB files","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221103024604.614-1-mark@harmstone.com/mbox/"},{"id":14706,"url":"https://patchwork.plctlab.org/api/1.2/patches/14706/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221103071519.3510462-1-luis.machado@arm.com/","msgid":"<20221103071519.3510462-1-luis.machado@arm.com>","list_archive_url":null,"date":"2022-11-03T07:15:19","name":"[opcodes/arm] Fix potential null pointer dereferences","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221103071519.3510462-1-luis.machado@arm.com/mbox/"},{"id":14840,"url":"https://patchwork.plctlab.org/api/1.2/patches/14840/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/283a86ebf0941f0f63dc1a590ec3d547bd5d69e8.1667478033.git.research_trasio@irq.a4lg.com/","msgid":"<283a86ebf0941f0f63dc1a590ec3d547bd5d69e8.1667478033.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-03T12:26:28","name":"[REVIEW,ONLY,1/2] NEAR-RATIFICATION RISC-V: Add '\''Ssstateen'\'' extension and its CSRs","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/283a86ebf0941f0f63dc1a590ec3d547bd5d69e8.1667478033.git.research_trasio@irq.a4lg.com/mbox/"},{"id":14841,"url":"https://patchwork.plctlab.org/api/1.2/patches/14841/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8083ad9d5339afdeb7f1ba88ee6af0665dcc76d5.1667478033.git.research_trasio@irq.a4lg.com/","msgid":"<8083ad9d5339afdeb7f1ba88ee6af0665dcc76d5.1667478033.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-03T12:26:29","name":"[REVIEW,ONLY,2/2] NEAR-RATIFICATION RISC-V: Add platform property/capability extensions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8083ad9d5339afdeb7f1ba88ee6af0665dcc76d5.1667478033.git.research_trasio@irq.a4lg.com/mbox/"},{"id":14894,"url":"https://patchwork.plctlab.org/api/1.2/patches/14894/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e53fbf5025e59fe6a3481b9c1fe37e4f6cf6e03d.1667483581.git.aburgess@redhat.com/","msgid":"","list_archive_url":null,"date":"2022-11-03T13:58:12","name":"[1/2] opcodes/mips: use .word/.short for undefined instructions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e53fbf5025e59fe6a3481b9c1fe37e4f6cf6e03d.1667483581.git.aburgess@redhat.com/mbox/"},{"id":14893,"url":"https://patchwork.plctlab.org/api/1.2/patches/14893/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ca81edb86580566b1641ad140eb2bed385160ab7.1667483581.git.aburgess@redhat.com/","msgid":"","list_archive_url":null,"date":"2022-11-03T13:58:13","name":"[2/2] libopcodes/mips: add support for disassembler styling","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ca81edb86580566b1641ad140eb2bed385160ab7.1667483581.git.aburgess@redhat.com/mbox/"},{"id":15465,"url":"https://patchwork.plctlab.org/api/1.2/patches/15465/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/926e5154-b40b-9df8-d770-a8bf7d40e40e@suse.com/","msgid":"<926e5154-b40b-9df8-d770-a8bf7d40e40e@suse.com>","list_archive_url":null,"date":"2022-11-04T10:50:38","name":"[v6,1/7] x86: constify parse_insn()'\''s input","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/926e5154-b40b-9df8-d770-a8bf7d40e40e@suse.com/mbox/"},{"id":15466,"url":"https://patchwork.plctlab.org/api/1.2/patches/15466/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/07ef67fd-752c-ad1f-b8cb-4eaec1f420fc@suse.com/","msgid":"<07ef67fd-752c-ad1f-b8cb-4eaec1f420fc@suse.com>","list_archive_url":null,"date":"2022-11-04T10:51:34","name":"[v6,2/7] x86: re-work insn/suffix recognition","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/07ef67fd-752c-ad1f-b8cb-4eaec1f420fc@suse.com/mbox/"},{"id":15467,"url":"https://patchwork.plctlab.org/api/1.2/patches/15467/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ee8fd655-19a5-d944-0f5e-4351b88a59f9@suse.com/","msgid":"","list_archive_url":null,"date":"2022-11-04T10:52:02","name":"[v6,3/7] ix86: don'\''t recognize/derive Q suffix in the common case","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ee8fd655-19a5-d944-0f5e-4351b88a59f9@suse.com/mbox/"},{"id":15468,"url":"https://patchwork.plctlab.org/api/1.2/patches/15468/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/15ab2cf5-f1ac-e882-c415-6318f1bcc7f0@suse.com/","msgid":"<15ab2cf5-f1ac-e882-c415-6318f1bcc7f0@suse.com>","list_archive_url":null,"date":"2022-11-04T10:52:31","name":"[v6,4/7] x86-64: allow HLE store of accumulator to absolute 32-bit address","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/15ab2cf5-f1ac-e882-c415-6318f1bcc7f0@suse.com/mbox/"},{"id":15470,"url":"https://patchwork.plctlab.org/api/1.2/patches/15470/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/352d1e49-ac9f-ee86-7e9d-74f79744268b@suse.com/","msgid":"<352d1e49-ac9f-ee86-7e9d-74f79744268b@suse.com>","list_archive_url":null,"date":"2022-11-04T10:53:14","name":"[v6,5/7] x86: move bad-use-of-TLS-reloc check","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/352d1e49-ac9f-ee86-7e9d-74f79744268b@suse.com/mbox/"},{"id":15469,"url":"https://patchwork.plctlab.org/api/1.2/patches/15469/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c1913bf6-7328-e45f-69f1-20da1954af43@suse.com/","msgid":"","list_archive_url":null,"date":"2022-11-04T10:53:52","name":"[v6,6/7] x86: drop (now) stray IsString","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c1913bf6-7328-e45f-69f1-20da1954af43@suse.com/mbox/"},{"id":15471,"url":"https://patchwork.plctlab.org/api/1.2/patches/15471/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2baf6a9d-c1bf-660d-bbca-99b1604f5478@suse.com/","msgid":"<2baf6a9d-c1bf-660d-bbca-99b1604f5478@suse.com>","list_archive_url":null,"date":"2022-11-04T10:54:30","name":"[v6,7/7] x86: further re-work insn/suffix recognition to also cover MOVSX","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2baf6a9d-c1bf-660d-bbca-99b1604f5478@suse.com/mbox/"},{"id":15472,"url":"https://patchwork.plctlab.org/api/1.2/patches/15472/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104110132.694984-1-aburgess@redhat.com/","msgid":"<20221104110132.694984-1-aburgess@redhat.com>","list_archive_url":null,"date":"2022-11-04T11:01:32","name":"[PUSHED] opcodes/arm: silence compiler warning about uninitialized variable use","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104110132.694984-1-aburgess@redhat.com/mbox/"},{"id":15473,"url":"https://patchwork.plctlab.org/api/1.2/patches/15473/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104110214.129095-1-christophe.lyon@arm.com/","msgid":"<20221104110214.129095-1-christophe.lyon@arm.com>","list_archive_url":null,"date":"2022-11-04T11:02:14","name":"configure: require libzstd >= 1.4.0","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104110214.129095-1-christophe.lyon@arm.com/mbox/"},{"id":15485,"url":"https://patchwork.plctlab.org/api/1.2/patches/15485/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104115038.8957-1-nelson@rivosinc.com/","msgid":"<20221104115038.8957-1-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-11-04T11:50:37","name":"[1/2] RISC-V: File-level architecture shouldn'\''t be affected by section-level ones.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104115038.8957-1-nelson@rivosinc.com/mbox/"},{"id":15486,"url":"https://patchwork.plctlab.org/api/1.2/patches/15486/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104115038.8957-2-nelson@rivosinc.com/","msgid":"<20221104115038.8957-2-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-11-04T11:50:38","name":"[2/2] RISC-V: Clarify the suppress rule of mapping symbol with architecture string.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104115038.8957-2-nelson@rivosinc.com/mbox/"},{"id":15509,"url":"https://patchwork.plctlab.org/api/1.2/patches/15509/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/cc133c88-9ce9-5e3a-a8f7-ad72766862b9@suse.com/","msgid":"","list_archive_url":null,"date":"2022-11-04T13:12:07","name":"x86: adjust recently introduced testcases","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/cc133c88-9ce9-5e3a-a8f7-ad72766862b9@suse.com/mbox/"},{"id":15679,"url":"https://patchwork.plctlab.org/api/1.2/patches/15679/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104163328.2274371-1-chigot@adacore.com/","msgid":"<20221104163328.2274371-1-chigot@adacore.com>","list_archive_url":null,"date":"2022-11-04T16:33:28","name":"ld/testsuite: skip tests related to -shared when disabled","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104163328.2274371-1-chigot@adacore.com/mbox/"},{"id":15751,"url":"https://patchwork.plctlab.org/api/1.2/patches/15751/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104190216.1352855-1-indu.bhagat@oracle.com/","msgid":"<20221104190216.1352855-1-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-04T19:02:16","name":"[V3.1,11/15] libctf: add libsframe to LDFLAGS and LIBS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104190216.1352855-1-indu.bhagat@oracle.com/mbox/"},{"id":15792,"url":"https://patchwork.plctlab.org/api/1.2/patches/15792/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104205547.3728827-1-hjl.tools@gmail.com/","msgid":"<20221104205547.3728827-1-hjl.tools@gmail.com>","list_archive_url":null,"date":"2022-11-04T20:55:47","name":"i386: Check invalid (%dx) usage","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104205547.3728827-1-hjl.tools@gmail.com/mbox/"},{"id":15794,"url":"https://patchwork.plctlab.org/api/1.2/patches/15794/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104210134.1721620-1-indu.bhagat@oracle.com/","msgid":"<20221104210134.1721620-1-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-04T21:01:34","name":"[V3.2,11/15] libctf: add libsframe to LDFLAGS and LIBS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104210134.1721620-1-indu.bhagat@oracle.com/mbox/"},{"id":15959,"url":"https://patchwork.plctlab.org/api/1.2/patches/15959/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c620070e3e335df2b487d3836e20d251dac37525.1667651354.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-11-05T12:29:07","name":"[01/12] RISC-V: Remove unnecessary empty matching file","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c620070e3e335df2b487d3836e20d251dac37525.1667651354.git.research_trasio@irq.a4lg.com/mbox/"},{"id":15961,"url":"https://patchwork.plctlab.org/api/1.2/patches/15961/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4496235002a396043598ab9755bd8eda5c077b1f.1667651354.git.research_trasio@irq.a4lg.com/","msgid":"<4496235002a396043598ab9755bd8eda5c077b1f.1667651354.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-05T12:29:08","name":"[02/12] RISC-V: Tidy disassembler corner case tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4496235002a396043598ab9755bd8eda5c077b1f.1667651354.git.research_trasio@irq.a4lg.com/mbox/"},{"id":15960,"url":"https://patchwork.plctlab.org/api/1.2/patches/15960/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a9229a2798480f00bf12ac3c435b3ef57f867022.1667651354.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-11-05T12:29:09","name":"[03/12] RISC-V: Tidying related to '\''Zfinx'\'' disassembler test","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a9229a2798480f00bf12ac3c435b3ef57f867022.1667651354.git.research_trasio@irq.a4lg.com/mbox/"},{"id":15962,"url":"https://patchwork.plctlab.org/api/1.2/patches/15962/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6a020edd0e114a003edbaafe1088a040e9fa07e7.1667651354.git.research_trasio@irq.a4lg.com/","msgid":"<6a020edd0e114a003edbaafe1088a040e9fa07e7.1667651354.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-05T12:29:10","name":"[04/12] RISC-V: GAS: Add basic shared test utilities","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6a020edd0e114a003edbaafe1088a040e9fa07e7.1667651354.git.research_trasio@irq.a4lg.com/mbox/"},{"id":15966,"url":"https://patchwork.plctlab.org/api/1.2/patches/15966/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6fc2851a4161edc429089bd2bbd9c2bb4c0c118f.1667651354.git.research_trasio@irq.a4lg.com/","msgid":"<6fc2851a4161edc429089bd2bbd9c2bb4c0c118f.1667651354.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-05T12:29:11","name":"[05/12] RISC-V: Redefine \"nop\" test","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6fc2851a4161edc429089bd2bbd9c2bb4c0c118f.1667651354.git.research_trasio@irq.a4lg.com/mbox/"},{"id":15963,"url":"https://patchwork.plctlab.org/api/1.2/patches/15963/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7311ed3d2429000e18877d7af594890da170a7a3.1667651354.git.research_trasio@irq.a4lg.com/","msgid":"<7311ed3d2429000e18877d7af594890da170a7a3.1667651354.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-05T12:29:12","name":"[06/12] RISC-V: Reorganize/enhance {sign, zero}-extension instructions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7311ed3d2429000e18877d7af594890da170a7a3.1667651354.git.research_trasio@irq.a4lg.com/mbox/"},{"id":15968,"url":"https://patchwork.plctlab.org/api/1.2/patches/15968/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ac99c9696c156207f06c18f2d6bf423c96c5876b.1667651354.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-11-05T12:29:13","name":"[07/12] RISC-V: Combine complex extension error handling tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ac99c9696c156207f06c18f2d6bf423c96c5876b.1667651354.git.research_trasio@irq.a4lg.com/mbox/"},{"id":15970,"url":"https://patchwork.plctlab.org/api/1.2/patches/15970/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9378b9505e3e230e0a690c56e67d253e2a0f5864.1667651354.git.research_trasio@irq.a4lg.com/","msgid":"<9378b9505e3e230e0a690c56e67d253e2a0f5864.1667651354.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-05T12:29:14","name":"[08/12] RISC-V: Refine/enhance '\''M'\''/'\''Zmmul'\'' extension tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9378b9505e3e230e0a690c56e67d253e2a0f5864.1667651354.git.research_trasio@irq.a4lg.com/mbox/"},{"id":15964,"url":"https://patchwork.plctlab.org/api/1.2/patches/15964/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/82832a67f240d5857fd502d4b74fd7d841ee2d6e.1667651354.git.research_trasio@irq.a4lg.com/","msgid":"<82832a67f240d5857fd502d4b74fd7d841ee2d6e.1667651354.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-05T12:29:15","name":"[09/12] RISC-V: Combine/enhance '\''Zicbo[mz]'\'' extension tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/82832a67f240d5857fd502d4b74fd7d841ee2d6e.1667651354.git.research_trasio@irq.a4lg.com/mbox/"},{"id":15965,"url":"https://patchwork.plctlab.org/api/1.2/patches/15965/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9c47e59868a64b13e5a7bb487e3619d4f1497d78.1667651354.git.research_trasio@irq.a4lg.com/","msgid":"<9c47e59868a64b13e5a7bb487e3619d4f1497d78.1667651354.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-05T12:29:16","name":"[10/12] RISC-V: Enhance '\''Zicbop'\'' testcases","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9c47e59868a64b13e5a7bb487e3619d4f1497d78.1667651354.git.research_trasio@irq.a4lg.com/mbox/"},{"id":15967,"url":"https://patchwork.plctlab.org/api/1.2/patches/15967/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2d9befc5bc5eed80b6bd7da6d092a61b1162ecac.1667651354.git.research_trasio@irq.a4lg.com/","msgid":"<2d9befc5bc5eed80b6bd7da6d092a61b1162ecac.1667651354.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-05T12:29:17","name":"[11/12] RISC-V: Reorganize/enhance '\''Zb*'\'' extension tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2d9befc5bc5eed80b6bd7da6d092a61b1162ecac.1667651354.git.research_trasio@irq.a4lg.com/mbox/"},{"id":15969,"url":"https://patchwork.plctlab.org/api/1.2/patches/15969/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f1c5589ab606b74eeac98e3dafd4a7903450d3b2.1667651354.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-11-05T12:29:18","name":"[12/12] RISC-V: Combine/enhance '\''Zk*'\''/'\''Zbk*'\'' extension tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f1c5589ab606b74eeac98e3dafd4a7903450d3b2.1667651354.git.research_trasio@irq.a4lg.com/mbox/"},{"id":16066,"url":"https://patchwork.plctlab.org/api/1.2/patches/16066/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221106053640.1649752-1-indu.bhagat@oracle.com/","msgid":"<20221106053640.1649752-1-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-06T05:36:40","name":"[V3.1,03/15] gas: generate .sframe from CFI directives","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221106053640.1649752-1-indu.bhagat@oracle.com/mbox/"},{"id":16379,"url":"https://patchwork.plctlab.org/api/1.2/patches/16379/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221107112805.3332619-1-och95@yandex.ru/","msgid":"<20221107112805.3332619-1-och95@yandex.ru>","list_archive_url":null,"date":"2022-11-07T11:28:05","name":"gold/aarch64: Fix adrp distance check","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221107112805.3332619-1-och95@yandex.ru/mbox/"},{"id":16400,"url":"https://patchwork.plctlab.org/api/1.2/patches/16400/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221107124620.1271470-1-christoph.muellner@vrull.eu/","msgid":"<20221107124620.1271470-1-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2022-11-07T12:46:20","name":"RISC-V: xtheadfmemidx: Use fp register in mnemonics","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221107124620.1271470-1-christoph.muellner@vrull.eu/mbox/"},{"id":16594,"url":"https://patchwork.plctlab.org/api/1.2/patches/16594/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/CACVBkZ+kM2xcpwk5zHQ4bqDV7dbPjZ6cMU9tR-h62+tDTgi3Tw@mail.gmail.com/","msgid":"","list_archive_url":null,"date":"2022-11-07T17:53:35","name":"GAS fix section alignment for aarch64-pe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/CACVBkZ+kM2xcpwk5zHQ4bqDV7dbPjZ6cMU9tR-h62+tDTgi3Tw@mail.gmail.com/mbox/"},{"id":16744,"url":"https://patchwork.plctlab.org/api/1.2/patches/16744/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221107222809.924195-1-indu.bhagat@oracle.com/","msgid":"<20221107222809.924195-1-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-07T22:28:09","name":"[V3.3,11/15] libctf: add libsframe to LDFLAGS and LIBS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221107222809.924195-1-indu.bhagat@oracle.com/mbox/"},{"id":16797,"url":"https://patchwork.plctlab.org/api/1.2/patches/16797/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221108012556.66467-1-haochen.jiang@intel.com/","msgid":"<20221108012556.66467-1-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-11-08T01:25:56","name":"x86: Correct wrong comments in vex_w_table","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221108012556.66467-1-haochen.jiang@intel.com/mbox/"},{"id":16884,"url":"https://patchwork.plctlab.org/api/1.2/patches/16884/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221108054530.796968-1-markus.t.metzger@intel.com/","msgid":"<20221108054530.796968-1-markus.t.metzger@intel.com>","list_archive_url":null,"date":"2022-11-08T05:45:29","name":"[1/2] gprofng: make cpu identification available to others","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221108054530.796968-1-markus.t.metzger@intel.com/mbox/"},{"id":16885,"url":"https://patchwork.plctlab.org/api/1.2/patches/16885/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221108054530.796968-2-markus.t.metzger@intel.com/","msgid":"<20221108054530.796968-2-markus.t.metzger@intel.com>","list_archive_url":null,"date":"2022-11-08T05:45:30","name":"[2/2] gdb, btrace: use cpuident.h to implement btrace_this_cpu","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221108054530.796968-2-markus.t.metzger@intel.com/mbox/"},{"id":16995,"url":"https://patchwork.plctlab.org/api/1.2/patches/16995/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ea0daf08-4923-ebfa-dcfe-699c43d63822@suse.com/","msgid":"","list_archive_url":null,"date":"2022-11-08T11:29:40","name":"x86/Intel: don'\''t accept malformed EXTRQ / INSERTQ","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ea0daf08-4923-ebfa-dcfe-699c43d63822@suse.com/mbox/"},{"id":17057,"url":"https://patchwork.plctlab.org/api/1.2/patches/17057/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221108141352.6613-1-jwilk@jwilk.net/","msgid":"<20221108141352.6613-1-jwilk@jwilk.net>","list_archive_url":null,"date":"2022-11-08T14:13:52","name":"Fix typos in the list of objdump options","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221108141352.6613-1-jwilk@jwilk.net/mbox/"},{"id":17117,"url":"https://patchwork.plctlab.org/api/1.2/patches/17117/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1667924955-9218-1-git-send-email-apinski@marvell.com/","msgid":"<1667924955-9218-1-git-send-email-apinski@marvell.com>","list_archive_url":null,"date":"2022-11-08T16:29:15","name":"Use toplevel configure for GMP and MPFR for gdb","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1667924955-9218-1-git-send-email-apinski@marvell.com/mbox/"},{"id":17160,"url":"https://patchwork.plctlab.org/api/1.2/patches/17160/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/27382086-397f-060f-6cf6-c1d36ff6b812@linux.ibm.com/","msgid":"<27382086-397f-060f-6cf6-c1d36ff6b812@linux.ibm.com>","list_archive_url":null,"date":"2022-11-08T18:23:32","name":"[COMMITTED] PowerPC: Add XSP operand define","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/27382086-397f-060f-6cf6-c1d36ff6b812@linux.ibm.com/mbox/"},{"id":17202,"url":"https://patchwork.plctlab.org/api/1.2/patches/17202/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221108192248.1622627-1-indu.bhagat@oracle.com/","msgid":"<20221108192248.1622627-1-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-08T19:22:48","name":"libctf: use libtool for link test in configure","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221108192248.1622627-1-indu.bhagat@oracle.com/mbox/"},{"id":17262,"url":"https://patchwork.plctlab.org/api/1.2/patches/17262/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221108225030.371817-1-hjl.tools@gmail.com/","msgid":"<20221108225030.371817-1-hjl.tools@gmail.com>","list_archive_url":null,"date":"2022-11-08T22:50:30","name":"ld: Always output local symbol for relocatable link","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221108225030.371817-1-hjl.tools@gmail.com/mbox/"},{"id":17399,"url":"https://patchwork.plctlab.org/api/1.2/patches/17399/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-2-indu.bhagat@oracle.com/","msgid":"<20221109084244.261296-2-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-09T08:42:34","name":"[V4,01/11] sframe.h: Add SFrame format definition","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-2-indu.bhagat@oracle.com/mbox/"},{"id":17398,"url":"https://patchwork.plctlab.org/api/1.2/patches/17398/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-3-indu.bhagat@oracle.com/","msgid":"<20221109084244.261296-3-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-09T08:42:35","name":"[V4,02/11] gas: add new command line option --gsframe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-3-indu.bhagat@oracle.com/mbox/"},{"id":17400,"url":"https://patchwork.plctlab.org/api/1.2/patches/17400/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-4-indu.bhagat@oracle.com/","msgid":"<20221109084244.261296-4-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-09T08:42:36","name":"[V4,03/11] gas: generate .sframe from CFI directives","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-4-indu.bhagat@oracle.com/mbox/"},{"id":17403,"url":"https://patchwork.plctlab.org/api/1.2/patches/17403/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-5-indu.bhagat@oracle.com/","msgid":"<20221109084244.261296-5-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-09T08:42:37","name":"[V4,04/11] gas: testsuite: add new tests for SFrame unwind info","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-5-indu.bhagat@oracle.com/mbox/"},{"id":17407,"url":"https://patchwork.plctlab.org/api/1.2/patches/17407/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-6-indu.bhagat@oracle.com/","msgid":"<20221109084244.261296-6-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-09T08:42:38","name":"[V4,05/11] libsframe: add the SFrame library","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-6-indu.bhagat@oracle.com/mbox/"},{"id":17406,"url":"https://patchwork.plctlab.org/api/1.2/patches/17406/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-7-indu.bhagat@oracle.com/","msgid":"<20221109084244.261296-7-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-09T08:42:39","name":"[V4,06/11] bfd: linker: merge .sframe sections","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-7-indu.bhagat@oracle.com/mbox/"},{"id":17402,"url":"https://patchwork.plctlab.org/api/1.2/patches/17402/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-8-indu.bhagat@oracle.com/","msgid":"<20221109084244.261296-8-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-09T08:42:40","name":"[V4,07/11] readelf/objdump: support for SFrame section","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-8-indu.bhagat@oracle.com/mbox/"},{"id":17401,"url":"https://patchwork.plctlab.org/api/1.2/patches/17401/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-9-indu.bhagat@oracle.com/","msgid":"<20221109084244.261296-9-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-09T08:42:41","name":"[V4,08/11] src-release.sh: Add libsframe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-9-indu.bhagat@oracle.com/mbox/"},{"id":17404,"url":"https://patchwork.plctlab.org/api/1.2/patches/17404/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-10-indu.bhagat@oracle.com/","msgid":"<20221109084244.261296-10-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-09T08:42:42","name":"[V4,09/11] binutils/NEWS: add text for SFrame support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-10-indu.bhagat@oracle.com/mbox/"},{"id":17405,"url":"https://patchwork.plctlab.org/api/1.2/patches/17405/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-11-indu.bhagat@oracle.com/","msgid":"<20221109084244.261296-11-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-09T08:42:43","name":"[V4,10/11] gas/NEWS: add text about new command line option and SFrame support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-11-indu.bhagat@oracle.com/mbox/"},{"id":17418,"url":"https://patchwork.plctlab.org/api/1.2/patches/17418/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-12-indu.bhagat@oracle.com/","msgid":"<20221109084244.261296-12-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-09T08:42:44","name":"[V4,11/11] doc: add SFrame spec file","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-12-indu.bhagat@oracle.com/mbox/"},{"id":17662,"url":"https://patchwork.plctlab.org/api/1.2/patches/17662/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109162611.760465-1-chigot@adacore.com/","msgid":"<20221109162611.760465-1-chigot@adacore.com>","list_archive_url":null,"date":"2022-11-09T16:26:11","name":"ld/testsuite: skip ld-size when -shared is not supported","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109162611.760465-1-chigot@adacore.com/mbox/"},{"id":17804,"url":"https://patchwork.plctlab.org/api/1.2/patches/17804/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109202129.475283-1-hjl.tools@gmail.com/","msgid":"<20221109202129.475283-1-hjl.tools@gmail.com>","list_archive_url":null,"date":"2022-11-09T20:21:29","name":"[v2] i386: Check invalid (%dx) usage","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109202129.475283-1-hjl.tools@gmail.com/mbox/"},{"id":18043,"url":"https://patchwork.plctlab.org/api/1.2/patches/18043/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y2zOaxv1jkhwTIAi@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-11-10T10:11:55","name":"Sanity check reloc count in get_reloc_upper_bound","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y2zOaxv1jkhwTIAi@squeak.grove.modra.org/mbox/"},{"id":18044,"url":"https://patchwork.plctlab.org/api/1.2/patches/18044/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y2zOkpGuKAn+V2Tk@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-11-10T10:12:34","name":"mach-o reloc size overflow","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y2zOkpGuKAn+V2Tk@squeak.grove.modra.org/mbox/"},{"id":18045,"url":"https://patchwork.plctlab.org/api/1.2/patches/18045/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fddbca08-756a-4d78-b117-3e82dc40df8d@AZ-NEU-EX04.Arm.com/","msgid":"","list_archive_url":null,"date":"2022-11-10T10:17:38","name":"[BINTUILS] arm: Add support for Cortex-X1C CPU.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fddbca08-756a-4d78-b117-3e82dc40df8d@AZ-NEU-EX04.Arm.com/mbox/"},{"id":18051,"url":"https://patchwork.plctlab.org/api/1.2/patches/18051/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1518b510-2124-cbcb-9dcb-059dcfdc6cd4@suse.com/","msgid":"<1518b510-2124-cbcb-9dcb-059dcfdc6cd4@suse.com>","list_archive_url":null,"date":"2022-11-10T10:24:31","name":"x86: drop stray IsString from PadLock insns","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1518b510-2124-cbcb-9dcb-059dcfdc6cd4@suse.com/mbox/"},{"id":18088,"url":"https://patchwork.plctlab.org/api/1.2/patches/18088/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/25e8786d-289e-0521-baa2-2f2b85124dfe@suse.com/","msgid":"<25e8786d-289e-0521-baa2-2f2b85124dfe@suse.com>","list_archive_url":null,"date":"2022-11-10T12:12:46","name":"[v2] x86: drop stray IsString from PadLock insns","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/25e8786d-289e-0521-baa2-2f2b85124dfe@suse.com/mbox/"},{"id":18130,"url":"https://patchwork.plctlab.org/api/1.2/patches/18130/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9bb8ebe7-9e49-d60b-d586-e4d98242acda@suse.com/","msgid":"<9bb8ebe7-9e49-d60b-d586-e4d98242acda@suse.com>","list_archive_url":null,"date":"2022-11-10T13:36:16","name":"x86: drop duplicate sse4a entry from cpu_arch[]","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9bb8ebe7-9e49-d60b-d586-e4d98242acda@suse.com/mbox/"},{"id":18135,"url":"https://patchwork.plctlab.org/api/1.2/patches/18135/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/21665493-a9f9-3429-c9ae-ea69bc7751e2@suse.com/","msgid":"<21665493-a9f9-3429-c9ae-ea69bc7751e2@suse.com>","list_archive_url":null,"date":"2022-11-10T13:45:30","name":"x86: fold special-operand insn attributes into a single enum","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/21665493-a9f9-3429-c9ae-ea69bc7751e2@suse.com/mbox/"},{"id":18284,"url":"https://patchwork.plctlab.org/api/1.2/patches/18284/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1668107159-16961-1-git-send-email-apinski@marvell.com/","msgid":"<1668107159-16961-1-git-send-email-apinski@marvell.com>","list_archive_url":null,"date":"2022-11-10T19:05:59","name":"[PATCHv2] Use toplevel configure for GMP and MPFR for gdb","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1668107159-16961-1-git-send-email-apinski@marvell.com/mbox/"},{"id":18337,"url":"https://patchwork.plctlab.org/api/1.2/patches/18337/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221110224002.3798725-1-vladimir.mezentsev@oracle.com/","msgid":"<20221110224002.3798725-1-vladimir.mezentsev@oracle.com>","list_archive_url":null,"date":"2022-11-10T22:40:02","name":"gprofng: fix typo in configure.ac","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221110224002.3798725-1-vladimir.mezentsev@oracle.com/mbox/"},{"id":18424,"url":"https://patchwork.plctlab.org/api/1.2/patches/18424/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221111033040.23115-1-mark@harmstone.com/","msgid":"<20221111033040.23115-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-11-11T03:30:40","name":"ld: Add section contributions substream to PDB files","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221111033040.23115-1-mark@harmstone.com/mbox/"},{"id":18513,"url":"https://patchwork.plctlab.org/api/1.2/patches/18513/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/40e89395-1438-6cbe-aa37-1a04a724c8c7@suse.com/","msgid":"<40e89395-1438-6cbe-aa37-1a04a724c8c7@suse.com>","list_archive_url":null,"date":"2022-11-11T07:32:17","name":"gas: accept custom \".linefile .\"","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/40e89395-1438-6cbe-aa37-1a04a724c8c7@suse.com/mbox/"},{"id":18517,"url":"https://patchwork.plctlab.org/api/1.2/patches/18517/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y23642YK4HTWnn3X@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-11-11T07:33:55","name":"Sanity check SHT_MIPS_OPTIONS size","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y23642YK4HTWnn3X@squeak.grove.modra.org/mbox/"},{"id":18519,"url":"https://patchwork.plctlab.org/api/1.2/patches/18519/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y237HYVYLWv1R4b/@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-11-11T07:34:53","name":"PR28834, PR26946 sanity checking section size","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y237HYVYLWv1R4b/@squeak.grove.modra.org/mbox/"},{"id":18670,"url":"https://patchwork.plctlab.org/api/1.2/patches/18670/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c5ab35f0-595a-439c-b120-f93bd109ab96@AZ-NEU-EX04.Arm.com/","msgid":"","list_archive_url":null,"date":"2022-11-11T10:51:43","name":"[Binutils,gas] arm: Add support for new unwinder directive \".pacspval\".","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c5ab35f0-595a-439c-b120-f93bd109ab96@AZ-NEU-EX04.Arm.com/mbox/"},{"id":18672,"url":"https://patchwork.plctlab.org/api/1.2/patches/18672/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/33eb9aff-d813-44c5-8315-aeb3e339b3f2@AZ-NEU-EX04.Arm.com/","msgid":"<33eb9aff-d813-44c5-8315-aeb3e339b3f2@AZ-NEU-EX04.Arm.com>","list_archive_url":null,"date":"2022-11-11T10:53:55","name":"[Binutils,readelf] arm: Support for new pacbti unwind opcode 0xb5.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/33eb9aff-d813-44c5-8315-aeb3e339b3f2@AZ-NEU-EX04.Arm.com/mbox/"},{"id":19116,"url":"https://patchwork.plctlab.org/api/1.2/patches/19116/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y29EZ/ykU1Qe6AAw@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-11-12T06:59:51","name":"PowerPC64 paddi -Mraw","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y29EZ/ykU1Qe6AAw@squeak.grove.modra.org/mbox/"},{"id":19138,"url":"https://patchwork.plctlab.org/api/1.2/patches/19138/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221112091217.558020-1-dimitar@dinux.eu/","msgid":"<20221112091217.558020-1-dimitar@dinux.eu>","list_archive_url":null,"date":"2022-11-12T09:12:17","name":"pru: bfd: Correct default to no execstack","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221112091217.558020-1-dimitar@dinux.eu/mbox/"},{"id":19173,"url":"https://patchwork.plctlab.org/api/1.2/patches/19173/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221112124441.5084-1-patrick@monnerat.net/","msgid":"<20221112124441.5084-1-patrick@monnerat.net>","list_archive_url":null,"date":"2022-11-12T12:44:41","name":"binutils/objcopy: keep relocation while renaming a section with explicit flags","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221112124441.5084-1-patrick@monnerat.net/mbox/"},{"id":19377,"url":"https://patchwork.plctlab.org/api/1.2/patches/19377/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221113155921.1445808-1-christoph.muellner@vrull.eu/","msgid":"<20221113155921.1445808-1-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2022-11-13T15:59:20","name":"[1/2] RISC-V: Add T-Head Fmv vendor extension","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221113155921.1445808-1-christoph.muellner@vrull.eu/mbox/"},{"id":19378,"url":"https://patchwork.plctlab.org/api/1.2/patches/19378/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221113155921.1445808-2-christoph.muellner@vrull.eu/","msgid":"<20221113155921.1445808-2-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2022-11-13T15:59:21","name":"[2/2] RISC-V: Add T-Head Int vendor extension","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221113155921.1445808-2-christoph.muellner@vrull.eu/mbox/"},{"id":19850,"url":"https://patchwork.plctlab.org/api/1.2/patches/19850/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221114150348.112815-1-bwerl.dev@gmail.com/","msgid":"<20221114150348.112815-1-bwerl.dev@gmail.com>","list_archive_url":null,"date":"2022-11-14T15:03:48","name":"readelf: use fseeko for elf files >= 2 GiB on x86_64-mingw32","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221114150348.112815-1-bwerl.dev@gmail.com/mbox/"},{"id":19866,"url":"https://patchwork.plctlab.org/api/1.2/patches/19866/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3dd1c6f9-a773-c05f-44d7-12b7947072d2@suse.com/","msgid":"<3dd1c6f9-a773-c05f-44d7-12b7947072d2@suse.com>","list_archive_url":null,"date":"2022-11-14T16:12:26","name":"x86: infer No_*Suf from other insn attributes","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3dd1c6f9-a773-c05f-44d7-12b7947072d2@suse.com/mbox/"},{"id":19934,"url":"https://patchwork.plctlab.org/api/1.2/patches/19934/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f659dfbb-b84b-af86-bd8c-d177900af779@linaro.org/","msgid":"","list_archive_url":null,"date":"2022-11-14T17:24:23","name":"[V2] GAS fix alignment for aarch64-pe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f659dfbb-b84b-af86-bd8c-d177900af779@linaro.org/mbox/"},{"id":20111,"url":"https://patchwork.plctlab.org/api/1.2/patches/20111/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221115010409.24214-1-mark@harmstone.com/","msgid":"<20221115010409.24214-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-11-15T01:04:09","name":"gas: Add --gcodeview option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221115010409.24214-1-mark@harmstone.com/mbox/"},{"id":20174,"url":"https://patchwork.plctlab.org/api/1.2/patches/20174/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d305cd6178975195b025828561d59e505524ea45.1668486687.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-11-15T04:31:22","name":"[v3,1/8] RISC-V: Add a space at the end of pinfo","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d305cd6178975195b025828561d59e505524ea45.1668486687.git.research_trasio@irq.a4lg.com/mbox/"},{"id":20177,"url":"https://patchwork.plctlab.org/api/1.2/patches/20177/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2627dd5e18e59b6d976a8e6f1be39336e8a12cc3.1668486687.git.research_trasio@irq.a4lg.com/","msgid":"<2627dd5e18e59b6d976a8e6f1be39336e8a12cc3.1668486687.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-15T04:31:23","name":"[v3,2/8] RISC-V: Fix obvious misalignments ('\''Zbb'\''/'\''Zba'\'')","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2627dd5e18e59b6d976a8e6f1be39336e8a12cc3.1668486687.git.research_trasio@irq.a4lg.com/mbox/"},{"id":20173,"url":"https://patchwork.plctlab.org/api/1.2/patches/20173/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9d110279505cf502900a000a07e6e82b50f12adc.1668486687.git.research_trasio@irq.a4lg.com/","msgid":"<9d110279505cf502900a000a07e6e82b50f12adc.1668486687.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-15T04:31:24","name":"[v3,3/8] RISC-V: Remove spaces in opcode entries","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9d110279505cf502900a000a07e6e82b50f12adc.1668486687.git.research_trasio@irq.a4lg.com/mbox/"},{"id":20179,"url":"https://patchwork.plctlab.org/api/1.2/patches/20179/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8f77aa968ed9457ce1bce0a1f6449a287d0e6a18.1668486687.git.research_trasio@irq.a4lg.com/","msgid":"<8f77aa968ed9457ce1bce0a1f6449a287d0e6a18.1668486687.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-15T04:31:25","name":"[v3,4/8] RISC-V: Remove unused instruction macros","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8f77aa968ed9457ce1bce0a1f6449a287d0e6a18.1668486687.git.research_trasio@irq.a4lg.com/mbox/"},{"id":20176,"url":"https://patchwork.plctlab.org/api/1.2/patches/20176/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b43454773d597c1bc51741ef09aac960fecdfbd5.1668486687.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-11-15T04:31:26","name":"[v3,5/8] RISC-V: Complete tidying up with SCALL and SBREAK","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b43454773d597c1bc51741ef09aac960fecdfbd5.1668486687.git.research_trasio@irq.a4lg.com/mbox/"},{"id":20178,"url":"https://patchwork.plctlab.org/api/1.2/patches/20178/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/58cfec431ff2535aeb0c3fd9213933cf28864cb9.1668486687.git.research_trasio@irq.a4lg.com/","msgid":"<58cfec431ff2535aeb0c3fd9213933cf28864cb9.1668486687.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-15T04:31:27","name":"[v3,6/8] RISC-V: Tidying up with fmv.w.x and fmv.x.w","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/58cfec431ff2535aeb0c3fd9213933cf28864cb9.1668486687.git.research_trasio@irq.a4lg.com/mbox/"},{"id":20180,"url":"https://patchwork.plctlab.org/api/1.2/patches/20180/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/192f62be797f7c46a03acadb7d1bcdb83a7e9d6e.1668486687.git.research_trasio@irq.a4lg.com/","msgid":"<192f62be797f7c46a03acadb7d1bcdb83a7e9d6e.1668486687.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-15T04:31:28","name":"[v3,7/8] RISC-V: Make alias instructions aliases","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/192f62be797f7c46a03acadb7d1bcdb83a7e9d6e.1668486687.git.research_trasio@irq.a4lg.com/mbox/"},{"id":20175,"url":"https://patchwork.plctlab.org/api/1.2/patches/20175/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c89919c84067e1c2105b1857937df6405aec70fa.1668486687.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-11-15T04:31:29","name":"[v3,8/8] RISC-V: Use defined mask and match values","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c89919c84067e1c2105b1857937df6405aec70fa.1668486687.git.research_trasio@irq.a4lg.com/mbox/"},{"id":20185,"url":"https://patchwork.plctlab.org/api/1.2/patches/20185/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ebc1e98ae09f2c209ebaed2b81d5b418ce2c5128.1668487922.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-11-15T04:52:44","name":"[01/11] opcodes/riscv-dis.c: More tidying","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ebc1e98ae09f2c209ebaed2b81d5b418ce2c5128.1668487922.git.research_trasio@irq.a4lg.com/mbox/"},{"id":20188,"url":"https://patchwork.plctlab.org/api/1.2/patches/20188/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9795298f970f0b8a02796edc2c4249417614103b.1668487922.git.research_trasio@irq.a4lg.com/","msgid":"<9795298f970f0b8a02796edc2c4249417614103b.1668487922.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-15T04:52:45","name":"[02/11] RISC-V: Add test for '\''Zfinx'\'' register switching","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9795298f970f0b8a02796edc2c4249417614103b.1668487922.git.research_trasio@irq.a4lg.com/mbox/"},{"id":20186,"url":"https://patchwork.plctlab.org/api/1.2/patches/20186/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6c6c644515c6bc2751062543097eb14ee98e97c8.1668487922.git.research_trasio@irq.a4lg.com/","msgid":"<6c6c644515c6bc2751062543097eb14ee98e97c8.1668487922.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-15T04:52:46","name":"[03/11] RISC-V: Make mapping symbol checking consistent","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6c6c644515c6bc2751062543097eb14ee98e97c8.1668487922.git.research_trasio@irq.a4lg.com/mbox/"},{"id":20187,"url":"https://patchwork.plctlab.org/api/1.2/patches/20187/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b5b5ce7e34544c7934b775062413e0fe07dcd6e6.1668487922.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-11-15T04:52:47","name":"[04/11] RISC-V: Split riscv_get_map_state into two steps","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b5b5ce7e34544c7934b775062413e0fe07dcd6e6.1668487922.git.research_trasio@irq.a4lg.com/mbox/"},{"id":20192,"url":"https://patchwork.plctlab.org/api/1.2/patches/20192/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c143088cbaf7a19a992e008689420d95a90f3fab.1668487922.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-11-15T04:52:48","name":"[05/11] RISC-V: One time CSR hash table initialization","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c143088cbaf7a19a992e008689420d95a90f3fab.1668487922.git.research_trasio@irq.a4lg.com/mbox/"},{"id":20193,"url":"https://patchwork.plctlab.org/api/1.2/patches/20193/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9734125736efc8b63be17df87d38cf24bb14a156.1668487922.git.research_trasio@irq.a4lg.com/","msgid":"<9734125736efc8b63be17df87d38cf24bb14a156.1668487922.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-15T04:52:49","name":"[06/11] RISC-V: Use static xlen on ADDIW sequence","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9734125736efc8b63be17df87d38cf24bb14a156.1668487922.git.research_trasio@irq.a4lg.com/mbox/"},{"id":20191,"url":"https://patchwork.plctlab.org/api/1.2/patches/20191/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/34dbd0c82de0af284887a3bff649c8c53d67e752.1668487922.git.research_trasio@irq.a4lg.com/","msgid":"<34dbd0c82de0af284887a3bff649c8c53d67e752.1668487922.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-15T04:52:50","name":"[07/11] opcodes/riscv-dis.c: Add form feed for separation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/34dbd0c82de0af284887a3bff649c8c53d67e752.1668487922.git.research_trasio@irq.a4lg.com/mbox/"},{"id":20190,"url":"https://patchwork.plctlab.org/api/1.2/patches/20190/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1352fb8c63539727204df94651f371ed09bbce4c.1668487922.git.research_trasio@irq.a4lg.com/","msgid":"<1352fb8c63539727204df94651f371ed09bbce4c.1668487922.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-15T04:52:51","name":"[08/11] RISC-V: Split match/print steps on disassembler","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1352fb8c63539727204df94651f371ed09bbce4c.1668487922.git.research_trasio@irq.a4lg.com/mbox/"},{"id":20189,"url":"https://patchwork.plctlab.org/api/1.2/patches/20189/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/12cd8820841f695708875206b6461b6322c74428.1668487922.git.research_trasio@irq.a4lg.com/","msgid":"<12cd8820841f695708875206b6461b6322c74428.1668487922.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-15T04:52:52","name":"[09/11] RISC-V: Reorganize disassembler state initialization","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/12cd8820841f695708875206b6461b6322c74428.1668487922.git.research_trasio@irq.a4lg.com/mbox/"},{"id":20194,"url":"https://patchwork.plctlab.org/api/1.2/patches/20194/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6aade17e12ce2a928d044d9f148c874cf9922da8.1668487922.git.research_trasio@irq.a4lg.com/","msgid":"<6aade17e12ce2a928d044d9f148c874cf9922da8.1668487922.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-15T04:52:53","name":"[10/11] RISC-V: Reorganize arch-related initialization and management","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6aade17e12ce2a928d044d9f148c874cf9922da8.1668487922.git.research_trasio@irq.a4lg.com/mbox/"},{"id":20195,"url":"https://patchwork.plctlab.org/api/1.2/patches/20195/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a239fb0682bd24d4f1eb3014685eed78f9ea779a.1668487922.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-11-15T04:52:54","name":"[11/11] RISC-V: Move disassembler private data initialization","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a239fb0682bd24d4f1eb3014685eed78f9ea779a.1668487922.git.research_trasio@irq.a4lg.com/mbox/"},{"id":20236,"url":"https://patchwork.plctlab.org/api/1.2/patches/20236/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221115081455.2354987-2-zengxiao@eswincomputing.com/","msgid":"<20221115081455.2354987-2-zengxiao@eswincomputing.com>","list_archive_url":null,"date":"2022-11-15T08:14:55","name":"[v1,1/1] RISC-V: Make R_RISCV_SUB6 conforms to riscv abi standard","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221115081455.2354987-2-zengxiao@eswincomputing.com/mbox/"},{"id":20422,"url":"https://patchwork.plctlab.org/api/1.2/patches/20422/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221115145717.64948-1-bwerl.dev@gmail.com/","msgid":"<20221115145717.64948-1-bwerl.dev@gmail.com>","list_archive_url":null,"date":"2022-11-15T14:57:17","name":"readelf: use fseeko64 or fseeko if possible","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221115145717.64948-1-bwerl.dev@gmail.com/mbox/"},{"id":20600,"url":"https://patchwork.plctlab.org/api/1.2/patches/20600/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y3QKUwDn748CbDIs@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-11-15T21:53:23","name":"aarch64-pe can'\''t fill 16 bytes in section .text","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y3QKUwDn748CbDIs@squeak.grove.modra.org/mbox/"},{"id":20720,"url":"https://patchwork.plctlab.org/api/1.2/patches/20720/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221116053326.1337432-1-vladimir.mezentsev@oracle.com/","msgid":"<20221116053326.1337432-1-vladimir.mezentsev@oracle.com>","list_archive_url":null,"date":"2022-11-16T05:33:26","name":"PR29788, gprofng cannot display Java'\''s generated assembly code","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221116053326.1337432-1-vladimir.mezentsev@oracle.com/mbox/"},{"id":21321,"url":"https://patchwork.plctlab.org/api/1.2/patches/21321/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221116232039.1793148-1-hjl.tools@gmail.com/","msgid":"<20221116232039.1793148-1-hjl.tools@gmail.com>","list_archive_url":null,"date":"2022-11-16T23:20:39","name":"ld: Always call elf_backend_output_arch_local_syms","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221116232039.1793148-1-hjl.tools@gmail.com/mbox/"},{"id":21322,"url":"https://patchwork.plctlab.org/api/1.2/patches/21322/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221116232132.1009459-1-indu.bhagat@oracle.com/","msgid":"<20221116232132.1009459-1-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-16T23:21:32","name":"[gas,aarch64] : fix build breakage for aarch64-pe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221116232132.1009459-1-indu.bhagat@oracle.com/mbox/"},{"id":21449,"url":"https://patchwork.plctlab.org/api/1.2/patches/21449/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221117060234.1771025-1-indu.bhagat@oracle.com/","msgid":"<20221117060234.1771025-1-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-17T06:02:34","name":"[V2,gas,aarch64] : fix build breakage for aarch64-pe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221117060234.1771025-1-indu.bhagat@oracle.com/mbox/"},{"id":21662,"url":"https://patchwork.plctlab.org/api/1.2/patches/21662/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a050b8da-b978-d443-eee0-32b5a7836bb4@suse.com/","msgid":"","list_archive_url":null,"date":"2022-11-17T13:29:02","name":"[1/2] x86: instantiate i386_{op, reg}tab[] in gas instead of in libopcodes","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a050b8da-b978-d443-eee0-32b5a7836bb4@suse.com/mbox/"},{"id":21663,"url":"https://patchwork.plctlab.org/api/1.2/patches/21663/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d9b5137b-3bc0-8496-4533-03402ac00628@suse.com/","msgid":"","list_archive_url":null,"date":"2022-11-17T13:29:36","name":"[2/2] x86: break gas dependency on libopcodes","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d9b5137b-3bc0-8496-4533-03402ac00628@suse.com/mbox/"},{"id":21682,"url":"https://patchwork.plctlab.org/api/1.2/patches/21682/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221117143419.19571-1-bwerl.dev@gmail.com/","msgid":"<20221117143419.19571-1-bwerl.dev@gmail.com>","list_archive_url":null,"date":"2022-11-17T14:34:19","name":"readelf: use fseeko64 or fseeko if possible","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221117143419.19571-1-bwerl.dev@gmail.com/mbox/"},{"id":21850,"url":"https://patchwork.plctlab.org/api/1.2/patches/21850/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221117170546.1941945-1-hjl.tools@gmail.com/","msgid":"<20221117170546.1941945-1-hjl.tools@gmail.com>","list_archive_url":null,"date":"2022-11-17T17:05:46","name":"i386: Move i386_seg_prefixes to gas","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221117170546.1941945-1-hjl.tools@gmail.com/mbox/"},{"id":21858,"url":"https://patchwork.plctlab.org/api/1.2/patches/21858/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/CAPOVtOvi0D-u7MKAuO97-q241JZFojD8xppn3GdF2kH57iT+TA@mail.gmail.com/","msgid":"","list_archive_url":null,"date":"2022-11-17T17:44:00","name":"binutils: partially revert 17c6c3b99156fe82c1e637e1a5fd9f163ac788c8","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/CAPOVtOvi0D-u7MKAuO97-q241JZFojD8xppn3GdF2kH57iT+TA@mail.gmail.com/mbox/"},{"id":21992,"url":"https://patchwork.plctlab.org/api/1.2/patches/21992/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221118003212.3628771-1-christoph.muellner@vrull.eu/","msgid":"<20221118003212.3628771-1-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2022-11-18T00:32:12","name":"riscv: Add AIA extension support (Smaia, Ssaia)","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221118003212.3628771-1-christoph.muellner@vrull.eu/mbox/"},{"id":22004,"url":"https://patchwork.plctlab.org/api/1.2/patches/22004/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y3bZt50nhFXkf2WU@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-11-18T01:02:47","name":"go32 sanity check","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y3bZt50nhFXkf2WU@squeak.grove.modra.org/mbox/"},{"id":22005,"url":"https://patchwork.plctlab.org/api/1.2/patches/22005/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y3bZ0x42eeZFSqXt@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-11-18T01:03:15","name":"PR29799 heap buffer overflow in display_gdb_index dwarf.c:10548","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y3bZ0x42eeZFSqXt@squeak.grove.modra.org/mbox/"},{"id":22050,"url":"https://patchwork.plctlab.org/api/1.2/patches/22050/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4c45925619ab51261ca87d309883c9aa7cd05240.1668736896.git.research_trasio@irq.a4lg.com/","msgid":"<4c45925619ab51261ca87d309883c9aa7cd05240.1668736896.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-18T02:02:21","name":"RISC-V: Add INSN_DREF to memory read/write instructions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4c45925619ab51261ca87d309883c9aa7cd05240.1668736896.git.research_trasio@irq.a4lg.com/mbox/"},{"id":22053,"url":"https://patchwork.plctlab.org/api/1.2/patches/22053/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/13809b68ae60e912f3cb8e9bedd8eedf3899b547.1668737241.git.research_trasio@irq.a4lg.com/","msgid":"<13809b68ae60e912f3cb8e9bedd8eedf3899b547.1668737241.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-18T02:07:48","name":"[v4,1/8] RISC-V: Add a space at the end of pinfo","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/13809b68ae60e912f3cb8e9bedd8eedf3899b547.1668737241.git.research_trasio@irq.a4lg.com/mbox/"},{"id":22051,"url":"https://patchwork.plctlab.org/api/1.2/patches/22051/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9abf4696a17c5407a75d87b3c200fb9958ff227e.1668737241.git.research_trasio@irq.a4lg.com/","msgid":"<9abf4696a17c5407a75d87b3c200fb9958ff227e.1668737241.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-18T02:07:49","name":"[v4,2/8] RISC-V: Fix obvious misalignments ('\''Zbb'\''/'\''Zba'\'')","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9abf4696a17c5407a75d87b3c200fb9958ff227e.1668737241.git.research_trasio@irq.a4lg.com/mbox/"},{"id":22052,"url":"https://patchwork.plctlab.org/api/1.2/patches/22052/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/80185b54704af681ba81c6f84b6ce099cc3b5970.1668737241.git.research_trasio@irq.a4lg.com/","msgid":"<80185b54704af681ba81c6f84b6ce099cc3b5970.1668737241.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-18T02:07:50","name":"[v4,3/8] RISC-V: Remove spaces in opcode entries","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/80185b54704af681ba81c6f84b6ce099cc3b5970.1668737241.git.research_trasio@irq.a4lg.com/mbox/"},{"id":22055,"url":"https://patchwork.plctlab.org/api/1.2/patches/22055/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5d675a4132e2f6160d3294563e16f5093b5b1e20.1668737241.git.research_trasio@irq.a4lg.com/","msgid":"<5d675a4132e2f6160d3294563e16f5093b5b1e20.1668737241.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-18T02:07:51","name":"[v4,4/8] RISC-V: Remove unused instruction macros","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5d675a4132e2f6160d3294563e16f5093b5b1e20.1668737241.git.research_trasio@irq.a4lg.com/mbox/"},{"id":22056,"url":"https://patchwork.plctlab.org/api/1.2/patches/22056/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/27a4301cbae3d6788c878924f55aa9a6ae910669.1668737241.git.research_trasio@irq.a4lg.com/","msgid":"<27a4301cbae3d6788c878924f55aa9a6ae910669.1668737241.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-18T02:07:52","name":"[v4,5/8] RISC-V: Complete tidying up with SCALL and SBREAK","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/27a4301cbae3d6788c878924f55aa9a6ae910669.1668737241.git.research_trasio@irq.a4lg.com/mbox/"},{"id":22058,"url":"https://patchwork.plctlab.org/api/1.2/patches/22058/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7f0ea4bf1af541504b72791b5217253b2450071c.1668737241.git.research_trasio@irq.a4lg.com/","msgid":"<7f0ea4bf1af541504b72791b5217253b2450071c.1668737241.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-18T02:07:53","name":"[v4,6/8] RISC-V: Tidying up with fmv.w.x and fmv.x.w","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7f0ea4bf1af541504b72791b5217253b2450071c.1668737241.git.research_trasio@irq.a4lg.com/mbox/"},{"id":22057,"url":"https://patchwork.plctlab.org/api/1.2/patches/22057/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e5d45f2c8d1bb5b2d9adbfa117a3fc7d32afd6c9.1668737241.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-11-18T02:07:54","name":"[v4,7/8] RISC-V: Make alias instructions aliases","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e5d45f2c8d1bb5b2d9adbfa117a3fc7d32afd6c9.1668737241.git.research_trasio@irq.a4lg.com/mbox/"},{"id":22054,"url":"https://patchwork.plctlab.org/api/1.2/patches/22054/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3c1e28e61eb0275d0fd02a7d9ff956cc4f589104.1668737241.git.research_trasio@irq.a4lg.com/","msgid":"<3c1e28e61eb0275d0fd02a7d9ff956cc4f589104.1668737241.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-18T02:07:55","name":"[v4,8/8] RISC-V: Use defined mask and match values","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3c1e28e61eb0275d0fd02a7d9ff956cc4f589104.1668737241.git.research_trasio@irq.a4lg.com/mbox/"},{"id":22215,"url":"https://patchwork.plctlab.org/api/1.2/patches/22215/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/028280ab-56ad-2380-6bdd-3c944695ec5f@suse.com/","msgid":"<028280ab-56ad-2380-6bdd-3c944695ec5f@suse.com>","list_archive_url":null,"date":"2022-11-18T09:12:10","name":"[v2,1/4] x86: instantiate i386_{op, reg}tab[] in gas instead of in libopcodes","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/028280ab-56ad-2380-6bdd-3c944695ec5f@suse.com/mbox/"},{"id":22216,"url":"https://patchwork.plctlab.org/api/1.2/patches/22216/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b9a2ae11-6e9c-e9a8-88f6-17c686f0b844@suse.com/","msgid":"","list_archive_url":null,"date":"2022-11-18T09:13:01","name":"[v2,2/4] x86: remove i386-opc.c","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b9a2ae11-6e9c-e9a8-88f6-17c686f0b844@suse.com/mbox/"},{"id":22217,"url":"https://patchwork.plctlab.org/api/1.2/patches/22217/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fad783e7-e00a-c3c1-cb6d-89b70816a737@suse.com/","msgid":"","list_archive_url":null,"date":"2022-11-18T09:13:24","name":"[v2,3/4] x86: break gas dependency on libopcodes","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fad783e7-e00a-c3c1-cb6d-89b70816a737@suse.com/mbox/"},{"id":22218,"url":"https://patchwork.plctlab.org/api/1.2/patches/22218/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e3d67085-1385-d576-8656-30454f9e4474@suse.com/","msgid":"","list_archive_url":null,"date":"2022-11-18T09:14:05","name":"[v2,4/4] x86: drop sentinel from i386_optab[]","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e3d67085-1385-d576-8656-30454f9e4474@suse.com/mbox/"},{"id":23223,"url":"https://patchwork.plctlab.org/api/1.2/patches/23223/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2e469b6dd7d8b93ffd3cac333dd58d172a8f28d6.1668841829.git.research_trasio@irq.a4lg.com/","msgid":"<2e469b6dd7d8b93ffd3cac333dd58d172a8f28d6.1668841829.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-19T07:10:33","name":"[1/2] RISC-V: Make .insn tests stricter","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2e469b6dd7d8b93ffd3cac333dd58d172a8f28d6.1668841829.git.research_trasio@irq.a4lg.com/mbox/"},{"id":23224,"url":"https://patchwork.plctlab.org/api/1.2/patches/23224/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ed49fad6bc6aa4f59d619fd6b445582331594e08.1668841829.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-11-19T07:10:34","name":"[2/2] RISC-V: Better support for long instructions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ed49fad6bc6aa4f59d619fd6b445582331594e08.1668841829.git.research_trasio@irq.a4lg.com/mbox/"},{"id":23362,"url":"https://patchwork.plctlab.org/api/1.2/patches/23362/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7487608537fcd71f322e56d40bfb2cc605cee89a.1668906514.git.research_trasio@irq.a4lg.com/","msgid":"<7487608537fcd71f322e56d40bfb2cc605cee89a.1668906514.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-20T01:08:40","name":"[1/3] RISC-V: Use faster hash table on disassembling","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7487608537fcd71f322e56d40bfb2cc605cee89a.1668906514.git.research_trasio@irq.a4lg.com/mbox/"},{"id":23361,"url":"https://patchwork.plctlab.org/api/1.2/patches/23361/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e984efaf6c2d42891fa466338d999bf8b292dd7d.1668906514.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-11-20T01:08:41","name":"[2/3] RISC-V: Fallback on faster hash table","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e984efaf6c2d42891fa466338d999bf8b292dd7d.1668906514.git.research_trasio@irq.a4lg.com/mbox/"},{"id":23366,"url":"https://patchwork.plctlab.org/api/1.2/patches/23366/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/844db363911065a3b5f0c5e4601f89ee1d7360c5.1668906514.git.research_trasio@irq.a4lg.com/","msgid":"<844db363911065a3b5f0c5e4601f89ee1d7360c5.1668906514.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-20T01:08:42","name":"[3/3] RISC-V: Cache instruction support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/844db363911065a3b5f0c5e4601f89ee1d7360c5.1668906514.git.research_trasio@irq.a4lg.com/mbox/"},{"id":23363,"url":"https://patchwork.plctlab.org/api/1.2/patches/23363/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/88793c204c9270376959c6276fb1b63275bef3c8.1668906599.git.research_trasio@irq.a4lg.com/","msgid":"<88793c204c9270376959c6276fb1b63275bef3c8.1668906599.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-20T01:10:07","name":"[1/3] RISC-V: Easy optimization on riscv_search_mapping_symbol","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/88793c204c9270376959c6276fb1b63275bef3c8.1668906599.git.research_trasio@irq.a4lg.com/mbox/"},{"id":23365,"url":"https://patchwork.plctlab.org/api/1.2/patches/23365/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/55a36e28e1cb3983c637b3019d48717278574591.1668906599.git.research_trasio@irq.a4lg.com/","msgid":"<55a36e28e1cb3983c637b3019d48717278574591.1668906599.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-20T01:10:08","name":"[2/3] RISC-V: Per-section private data initialization","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/55a36e28e1cb3983c637b3019d48717278574591.1668906599.git.research_trasio@irq.a4lg.com/mbox/"},{"id":23364,"url":"https://patchwork.plctlab.org/api/1.2/patches/23364/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d41edfbaf150abb20fd78e8518ca5a9e7e5eb74f.1668906599.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-11-20T01:10:09","name":"[3/3] RISC-V: Optimized search on mapping symbols","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d41edfbaf150abb20fd78e8518ca5a9e7e5eb74f.1668906599.git.research_trasio@irq.a4lg.com/mbox/"},{"id":23372,"url":"https://patchwork.plctlab.org/api/1.2/patches/23372/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/94304c8d9174ae7e9cf52abc3af6ccf5e3e0ecd9.1668910970.git.research_trasio@irq.a4lg.com/","msgid":"<94304c8d9174ae7e9cf52abc3af6ccf5e3e0ecd9.1668910970.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-20T02:23:27","name":"[v3,1/3] RISC-V: Make \"priv-spec\" overridable","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/94304c8d9174ae7e9cf52abc3af6ccf5e3e0ecd9.1668910970.git.research_trasio@irq.a4lg.com/mbox/"},{"id":23371,"url":"https://patchwork.plctlab.org/api/1.2/patches/23371/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9d6008e38402c4e60ada6f3d3db14b92815177d8.1668910970.git.research_trasio@irq.a4lg.com/","msgid":"<9d6008e38402c4e60ada6f3d3db14b92815177d8.1668910970.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-20T02:23:28","name":"[v3,2/3] RISC-V: Add \"arch\" disassembler option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9d6008e38402c4e60ada6f3d3db14b92815177d8.1668910970.git.research_trasio@irq.a4lg.com/mbox/"},{"id":23370,"url":"https://patchwork.plctlab.org/api/1.2/patches/23370/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/70a4ac1ba8c12101de56c24d3a47939a2f5ee542.1668910970.git.research_trasio@irq.a4lg.com/","msgid":"<70a4ac1ba8c12101de56c24d3a47939a2f5ee542.1668910970.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-20T02:23:29","name":"[v3,3/3] gdb/testsuite: RISC-V disassembler option tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/70a4ac1ba8c12101de56c24d3a47939a2f5ee542.1668910970.git.research_trasio@irq.a4lg.com/mbox/"},{"id":23667,"url":"https://patchwork.plctlab.org/api/1.2/patches/23667/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221121110926.124434-1-aleksandar.rikalo@syrmia.com/","msgid":"<20221121110926.124434-1-aleksandar.rikalo@syrmia.com>","list_archive_url":null,"date":"2022-11-21T11:09:26","name":"[v3] Add support for nanoMIPS architecture","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221121110926.124434-1-aleksandar.rikalo@syrmia.com/mbox/"},{"id":23697,"url":"https://patchwork.plctlab.org/api/1.2/patches/23697/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221121120037.19325-1-zengxiao@eswincomputing.com/","msgid":"<20221121120037.19325-1-zengxiao@eswincomputing.com>","list_archive_url":null,"date":"2022-11-21T12:00:37","name":"[v2] RISC-V: Make R_RISCV_SUB6 conforms to riscv ABI standard","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221121120037.19325-1-zengxiao@eswincomputing.com/mbox/"},{"id":23957,"url":"https://patchwork.plctlab.org/api/1.2/patches/23957/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221121171544.3291-1-shahab@synopsys.com/","msgid":"<20221121171544.3291-1-shahab@synopsys.com>","list_archive_url":null,"date":"2022-11-21T17:15:44","name":"opcodes: Correct address for ARC'\''s \"isa_config\" aux reg","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221121171544.3291-1-shahab@synopsys.com/mbox/"},{"id":24026,"url":"https://patchwork.plctlab.org/api/1.2/patches/24026/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y3vyL3UATztRRM8v@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-11-21T21:48:31","name":"PR29807, SIGSEGV when linking fuzzed PE object","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y3vyL3UATztRRM8v@squeak.grove.modra.org/mbox/"},{"id":24269,"url":"https://patchwork.plctlab.org/api/1.2/patches/24269/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221122110927.2328582-1-christoph.muellner@vrull.eu/","msgid":"<20221122110927.2328582-1-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2022-11-22T11:09:27","name":"[v3] riscv: Add AIA extension support (Smaia, Ssaia)","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221122110927.2328582-1-christoph.muellner@vrull.eu/mbox/"},{"id":24318,"url":"https://patchwork.plctlab.org/api/1.2/patches/24318/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221122120339.23186-1-shahab@synopsys.com/","msgid":"<20221122120339.23186-1-shahab@synopsys.com>","list_archive_url":null,"date":"2022-11-22T12:03:39","name":"[PUSHED] opcodes: Correct address for ARC'\''s \"isa_config\" aux reg","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221122120339.23186-1-shahab@synopsys.com/mbox/"},{"id":24501,"url":"https://patchwork.plctlab.org/api/1.2/patches/24501/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221122181927.251937-1-hjl.tools@gmail.com/","msgid":"<20221122181927.251937-1-hjl.tools@gmail.com>","list_archive_url":null,"date":"2022-11-22T18:19:27","name":"x86: Remove libopcodes dependency","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221122181927.251937-1-hjl.tools@gmail.com/mbox/"},{"id":24599,"url":"https://patchwork.plctlab.org/api/1.2/patches/24599/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y31GJLbFpb5DCn2F@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-11-22T21:59:00","name":"Don'\''t use \"long\" in readelf for file offsets","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y31GJLbFpb5DCn2F@squeak.grove.modra.org/mbox/"},{"id":24600,"url":"https://patchwork.plctlab.org/api/1.2/patches/24600/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221122220236.429230-1-hjl.tools@gmail.com/","msgid":"<20221122220236.429230-1-hjl.tools@gmail.com>","list_archive_url":null,"date":"2022-11-22T22:02:36","name":"x86: Don'\''t define _TLS_MODULE_BASE_ for ld -r","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221122220236.429230-1-hjl.tools@gmail.com/mbox/"},{"id":24605,"url":"https://patchwork.plctlab.org/api/1.2/patches/24605/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221122221028.2924195-1-indu.bhagat@oracle.com/","msgid":"<20221122221028.2924195-1-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-22T22:10:28","name":"sframe/doc: remove usage of xrefautomaticsectiontitle","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221122221028.2924195-1-indu.bhagat@oracle.com/mbox/"},{"id":24787,"url":"https://patchwork.plctlab.org/api/1.2/patches/24787/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fdcd78c77ec384da0cb74a6d91c1e7f00bdde6cf.1669192210.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-11-23T08:30:48","name":"[v2,1/2] RISC-V: Make .insn tests stricter","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fdcd78c77ec384da0cb74a6d91c1e7f00bdde6cf.1669192210.git.research_trasio@irq.a4lg.com/mbox/"},{"id":24789,"url":"https://patchwork.plctlab.org/api/1.2/patches/24789/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/cdd1f831660ce24353b47dc4098992f136e45bcc.1669192210.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-11-23T08:30:49","name":"[v2,2/2] RISC-V: Better support for long instructions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/cdd1f831660ce24353b47dc4098992f136e45bcc.1669192210.git.research_trasio@irq.a4lg.com/mbox/"},{"id":24873,"url":"https://patchwork.plctlab.org/api/1.2/patches/24873/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/40d1240c-154b-ecea-c391-9fab12129b2b@suse.com/","msgid":"<40d1240c-154b-ecea-c391-9fab12129b2b@suse.com>","list_archive_url":null,"date":"2022-11-23T10:33:38","name":"[1/3] x86: correct handling of LAR and LSL","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/40d1240c-154b-ecea-c391-9fab12129b2b@suse.com/mbox/"},{"id":24876,"url":"https://patchwork.plctlab.org/api/1.2/patches/24876/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3dbee940-c57e-f89f-fdb1-730b275c0c17@suse.com/","msgid":"<3dbee940-c57e-f89f-fdb1-730b275c0c17@suse.com>","list_archive_url":null,"date":"2022-11-23T10:34:34","name":"[2/3] x86: add missing CheckRegSize","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3dbee940-c57e-f89f-fdb1-730b275c0c17@suse.com/mbox/"},{"id":24882,"url":"https://patchwork.plctlab.org/api/1.2/patches/24882/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0168ba4a-766c-7cfe-7917-53259f846da0@suse.com/","msgid":"<0168ba4a-766c-7cfe-7917-53259f846da0@suse.com>","list_archive_url":null,"date":"2022-11-23T10:35:16","name":"[3/3] x86: widen applicability and use of CheckRegSize","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0168ba4a-766c-7cfe-7917-53259f846da0@suse.com/mbox/"},{"id":24939,"url":"https://patchwork.plctlab.org/api/1.2/patches/24939/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y34R4z7auiQd9V9m@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-11-23T12:28:19","name":"asan: NULL deref in filter_symbols","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y34R4z7auiQd9V9m@squeak.grove.modra.org/mbox/"},{"id":24943,"url":"https://patchwork.plctlab.org/api/1.2/patches/24943/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y34SFSgfRguI0pMs@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-11-23T12:29:09","name":"PR22509 - Null pointer dereference on coff_slurp_reloc_table","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y34SFSgfRguI0pMs@squeak.grove.modra.org/mbox/"},{"id":25150,"url":"https://patchwork.plctlab.org/api/1.2/patches/25150/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221123194330.21185-1-mark@harmstone.com/","msgid":"<20221123194330.21185-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-11-23T19:43:30","name":"gas: Disable --gcodeview on PE targets with no O_secrel","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221123194330.21185-1-mark@harmstone.com/mbox/"},{"id":25255,"url":"https://patchwork.plctlab.org/api/1.2/patches/25255/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221124002827.1915219-1-indu.bhagat@oracle.com/","msgid":"<20221124002827.1915219-1-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-24T00:28:27","name":"[V2] sframe/doc: remove usage of xrefautomaticsectiontitle","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221124002827.1915219-1-indu.bhagat@oracle.com/mbox/"},{"id":25302,"url":"https://patchwork.plctlab.org/api/1.2/patches/25302/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221124034051.11711-1-mark@harmstone.com/","msgid":"<20221124034051.11711-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-11-24T03:40:51","name":"ld: Generate PDB string table","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221124034051.11711-1-mark@harmstone.com/mbox/"},{"id":25339,"url":"https://patchwork.plctlab.org/api/1.2/patches/25339/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y38dhqK5vRWbfFEO@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-11-24T07:30:14","name":"PR16995, m68k coldfire emac immediate to macsr incorrect disassembly","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y38dhqK5vRWbfFEO@squeak.grove.modra.org/mbox/"},{"id":25340,"url":"https://patchwork.plctlab.org/api/1.2/patches/25340/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y38duAgksZJEg8Ca@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-11-24T07:31:04","name":"Constify nm format array","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y38duAgksZJEg8Ca@squeak.grove.modra.org/mbox/"},{"id":25341,"url":"https://patchwork.plctlab.org/api/1.2/patches/25341/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y38eF5ySbTaGA/Gm@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-11-24T07:32:39","name":"Tidy objdump printing of section size","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y38eF5ySbTaGA/Gm@squeak.grove.modra.org/mbox/"},{"id":25382,"url":"https://patchwork.plctlab.org/api/1.2/patches/25382/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ebd260da-8bc5-7672-f529-a6bb1d9e9c7f@suse.com/","msgid":"","list_archive_url":null,"date":"2022-11-24T08:57:24","name":"[1/3] x86: extend FPU test coverage for AT&T / Intel mnemonic differences","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ebd260da-8bc5-7672-f529-a6bb1d9e9c7f@suse.com/mbox/"},{"id":25384,"url":"https://patchwork.plctlab.org/api/1.2/patches/25384/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0ef86245-7f0d-ef4e-957a-4086eb54ef43@suse.com/","msgid":"<0ef86245-7f0d-ef4e-957a-4086eb54ef43@suse.com>","list_archive_url":null,"date":"2022-11-24T08:57:56","name":"[2/3] x86: drop FloatR","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0ef86245-7f0d-ef4e-957a-4086eb54ef43@suse.com/mbox/"},{"id":25385,"url":"https://patchwork.plctlab.org/api/1.2/patches/25385/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5dd8b2df-62f2-a551-4b35-f3df66d57e04@suse.com/","msgid":"<5dd8b2df-62f2-a551-4b35-f3df66d57e04@suse.com>","list_archive_url":null,"date":"2022-11-24T08:58:36","name":"[3/3] x86: clean up after removal of support for gcc <= 2.8.1","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5dd8b2df-62f2-a551-4b35-f3df66d57e04@suse.com/mbox/"},{"id":25492,"url":"https://patchwork.plctlab.org/api/1.2/patches/25492/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9790982d-5a3d-f711-b588-184edd41a0dd@suse.cz/","msgid":"<9790982d-5a3d-f711-b588-184edd41a0dd@suse.cz>","list_archive_url":null,"date":"2022-11-24T12:18:33","name":"[PUSHED] readelf: Do not require EI_OSABI for IFUNC.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9790982d-5a3d-f711-b588-184edd41a0dd@suse.cz/mbox/"},{"id":25494,"url":"https://patchwork.plctlab.org/api/1.2/patches/25494/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/874juopmb0.fsf@redhat.com/","msgid":"<874juopmb0.fsf@redhat.com>","list_archive_url":null,"date":"2022-11-24T12:30:11","name":"Commit: Fix compile time warnings in conftest.c files","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/874juopmb0.fsf@redhat.com/mbox/"},{"id":25627,"url":"https://patchwork.plctlab.org/api/1.2/patches/25627/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221124154531.903548-1-aleksandar.rikalo@syrmia.com/","msgid":"<20221124154531.903548-1-aleksandar.rikalo@syrmia.com>","list_archive_url":null,"date":"2022-11-24T15:45:31","name":"[v4] Add support for nanoMIPS architecture","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221124154531.903548-1-aleksandar.rikalo@syrmia.com/mbox/"},{"id":25784,"url":"https://patchwork.plctlab.org/api/1.2/patches/25784/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/66ca80358f78d66d66bbf390fc0be8bec8183e93.1669342633.git.research_trasio@irq.a4lg.com/","msgid":"<66ca80358f78d66d66bbf390fc0be8bec8183e93.1669342633.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-25T02:17:23","name":"[v3,1/2] RISC-V: Better support for long instructions (disassembler)","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/66ca80358f78d66d66bbf390fc0be8bec8183e93.1669342633.git.research_trasio@irq.a4lg.com/mbox/"},{"id":25785,"url":"https://patchwork.plctlab.org/api/1.2/patches/25785/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/47d1751320314f02bede4f6096c09b7f6585c94d.1669342633.git.research_trasio@irq.a4lg.com/","msgid":"<47d1751320314f02bede4f6096c09b7f6585c94d.1669342633.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-25T02:17:24","name":"[v3,2/2] RISC-V: Better support for long instructions (assembler)","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/47d1751320314f02bede4f6096c09b7f6585c94d.1669342633.git.research_trasio@irq.a4lg.com/mbox/"},{"id":25790,"url":"https://patchwork.plctlab.org/api/1.2/patches/25790/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221125025334.26665-1-mark@harmstone.com/","msgid":"<20221125025334.26665-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-11-25T02:53:34","name":"[v2] ld: Generate PDB string table","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221125025334.26665-1-mark@harmstone.com/mbox/"},{"id":25791,"url":"https://patchwork.plctlab.org/api/1.2/patches/25791/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221125025433.26818-1-mark@harmstone.com/","msgid":"<20221125025433.26818-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-11-25T02:54:33","name":"ld: Write DEBUG_S_FILECHKSMS entries in PDBs","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221125025433.26818-1-mark@harmstone.com/mbox/"},{"id":25914,"url":"https://patchwork.plctlab.org/api/1.2/patches/25914/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/457fc649-adf7-a35d-2ae1-8a9f1a00ce0a@suse.com/","msgid":"<457fc649-adf7-a35d-2ae1-8a9f1a00ce0a@suse.com>","list_archive_url":null,"date":"2022-11-25T10:09:58","name":"Arm: .noinit and .persistent are not supported for Linux targets","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/457fc649-adf7-a35d-2ae1-8a9f1a00ce0a@suse.com/mbox/"},{"id":25948,"url":"https://patchwork.plctlab.org/api/1.2/patches/25948/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2c04525e48f5fc135b6dcb35ca6f1fec4e9b122b.1669376496.git.research_trasio@irq.a4lg.com/","msgid":"<2c04525e48f5fc135b6dcb35ca6f1fec4e9b122b.1669376496.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-25T11:41:40","name":"[v3,1/3] RISC-V: Better support for long instructions (disassembler)","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2c04525e48f5fc135b6dcb35ca6f1fec4e9b122b.1669376496.git.research_trasio@irq.a4lg.com/mbox/"},{"id":25950,"url":"https://patchwork.plctlab.org/api/1.2/patches/25950/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2c04525e48f5fc135b6dcb35ca6f1fec4e9b122b.1669376539.git.research_trasio@irq.a4lg.com/","msgid":"<2c04525e48f5fc135b6dcb35ca6f1fec4e9b122b.1669376539.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-25T11:42:20","name":"[v4,1/3] RISC-V: Better support for long instructions (disassembler)","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2c04525e48f5fc135b6dcb35ca6f1fec4e9b122b.1669376539.git.research_trasio@irq.a4lg.com/mbox/"},{"id":25951,"url":"https://patchwork.plctlab.org/api/1.2/patches/25951/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d8d2cda8e4b1a82f93fd9e9daa57f705c582d06f.1669376539.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-11-25T11:42:21","name":"[v4,2/3] RISC-V: Better support for long instructions (assembler)","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d8d2cda8e4b1a82f93fd9e9daa57f705c582d06f.1669376539.git.research_trasio@irq.a4lg.com/mbox/"},{"id":25949,"url":"https://patchwork.plctlab.org/api/1.2/patches/25949/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/523d1243d28a817c7ab371daed61335ab1dd31bc.1669376539.git.research_trasio@irq.a4lg.com/","msgid":"<523d1243d28a817c7ab371daed61335ab1dd31bc.1669376539.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-25T11:42:22","name":"[v4,3/3] RISC-V: Better support for long instructions (tests)","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/523d1243d28a817c7ab371daed61335ab1dd31bc.1669376539.git.research_trasio@irq.a4lg.com/mbox/"},{"id":26085,"url":"https://patchwork.plctlab.org/api/1.2/patches/26085/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.LSU.2.20.2211251556330.24878@wotan.suse.de/","msgid":"","list_archive_url":null,"date":"2022-11-25T16:00:05","name":"Fix msp430 section name scribbling and tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.LSU.2.20.2211251556330.24878@wotan.suse.de/mbox/"},{"id":26086,"url":"https://patchwork.plctlab.org/api/1.2/patches/26086/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.LSU.2.20.2211251600280.24878@wotan.suse.de/","msgid":"","list_archive_url":null,"date":"2022-11-25T16:01:58","name":"Special case more simple patterns","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.LSU.2.20.2211251600280.24878@wotan.suse.de/mbox/"},{"id":26087,"url":"https://patchwork.plctlab.org/api/1.2/patches/26087/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.LSU.2.20.2211251602070.24878@wotan.suse.de/","msgid":"","list_archive_url":null,"date":"2022-11-25T16:04:51","name":"Only use wild_sort_fast","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.LSU.2.20.2211251602070.24878@wotan.suse.de/mbox/"},{"id":26094,"url":"https://patchwork.plctlab.org/api/1.2/patches/26094/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.LSU.2.20.2211251644290.24878@wotan.suse.de/","msgid":"","list_archive_url":null,"date":"2022-11-25T16:44:54","name":"[1/8] section-select: Lazily resolve section matches","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.LSU.2.20.2211251644290.24878@wotan.suse.de/mbox/"},{"id":26095,"url":"https://patchwork.plctlab.org/api/1.2/patches/26095/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.LSU.2.20.2211251645000.24878@wotan.suse.de/","msgid":"","list_archive_url":null,"date":"2022-11-25T16:46:41","name":"[2/8] section-select: Deal with sections added late","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.LSU.2.20.2211251645000.24878@wotan.suse.de/mbox/"},{"id":26096,"url":"https://patchwork.plctlab.org/api/1.2/patches/26096/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.LSU.2.20.2211251646510.24878@wotan.suse.de/","msgid":"","list_archive_url":null,"date":"2022-11-25T16:47:17","name":"[3/8] section-select: Implement a prefix-tree","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.LSU.2.20.2211251646510.24878@wotan.suse.de/mbox/"},{"id":26097,"url":"https://patchwork.plctlab.org/api/1.2/patches/26097/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.LSU.2.20.2211251647220.24878@wotan.suse.de/","msgid":"","list_archive_url":null,"date":"2022-11-25T16:55:12","name":"[4/8] section-select: Completely rebuild matches","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.LSU.2.20.2211251647220.24878@wotan.suse.de/mbox/"},{"id":26098,"url":"https://patchwork.plctlab.org/api/1.2/patches/26098/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.LSU.2.20.2211251655221.24878@wotan.suse.de/","msgid":"","list_archive_url":null,"date":"2022-11-25T16:55:36","name":"[5/8] section-select: Remove unused code","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.LSU.2.20.2211251655221.24878@wotan.suse.de/mbox/"},{"id":26099,"url":"https://patchwork.plctlab.org/api/1.2/patches/26099/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.LSU.2.20.2211251655420.24878@wotan.suse.de/","msgid":"","list_archive_url":null,"date":"2022-11-25T16:55:57","name":"[6/8] section-select: Cleanup","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.LSU.2.20.2211251655420.24878@wotan.suse.de/mbox/"},{"id":26100,"url":"https://patchwork.plctlab.org/api/1.2/patches/26100/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.LSU.2.20.2211251656020.24878@wotan.suse.de/","msgid":"","list_archive_url":null,"date":"2022-11-25T16:57:38","name":"[7/8] section-select: Remove bfd_max_section_id again","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.LSU.2.20.2211251656020.24878@wotan.suse.de/mbox/"},{"id":26101,"url":"https://patchwork.plctlab.org/api/1.2/patches/26101/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.LSU.2.20.2211251657410.24878@wotan.suse.de/","msgid":"","list_archive_url":null,"date":"2022-11-25T16:58:03","name":"[8/8] section-select: Fix exclude-file-3","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.LSU.2.20.2211251657410.24878@wotan.suse.de/mbox/"},{"id":26180,"url":"https://patchwork.plctlab.org/api/1.2/patches/26180/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c55d94343b1e04c73baf4db9d8b22111528f1b40.1669432329.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-11-26T03:13:51","name":"RISC-V: Allow merging '\''H'\'' extension","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c55d94343b1e04c73baf4db9d8b22111528f1b40.1669432329.git.research_trasio@irq.a4lg.com/mbox/"},{"id":26307,"url":"https://patchwork.plctlab.org/api/1.2/patches/26307/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221127023840.32080-1-mark@harmstone.com/","msgid":"<20221127023840.32080-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-11-27T02:38:39","name":"ld: Fix segfault in populate_publics_stream","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221127023840.32080-1-mark@harmstone.com/mbox/"},{"id":26308,"url":"https://patchwork.plctlab.org/api/1.2/patches/26308/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221127023840.32080-2-mark@harmstone.com/","msgid":"<20221127023840.32080-2-mark@harmstone.com>","list_archive_url":null,"date":"2022-11-27T02:38:40","name":"ld: Write DEBUG_S_LINES entries in PDB file","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221127023840.32080-2-mark@harmstone.com/mbox/"},{"id":26350,"url":"https://patchwork.plctlab.org/api/1.2/patches/26350/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221127125325.263577-1-brobecker@adacore.com/","msgid":"<20221127125325.263577-1-brobecker@adacore.com>","list_archive_url":null,"date":"2022-11-27T12:53:25","name":"[RFA] src-release.sh: Fix gdb source tarball build failure due to libsframe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221127125325.263577-1-brobecker@adacore.com/mbox/"},{"id":26493,"url":"https://patchwork.plctlab.org/api/1.2/patches/26493/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5965a4d1d20a33accd4a9872f87da9e0fd6c1747.1669610611.git.research_trasio@irq.a4lg.com/","msgid":"<5965a4d1d20a33accd4a9872f87da9e0fd6c1747.1669610611.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-28T04:43:36","name":"[v2,01/11] opcodes/riscv-dis.c: More tidying","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5965a4d1d20a33accd4a9872f87da9e0fd6c1747.1669610611.git.research_trasio@irq.a4lg.com/mbox/"},{"id":26494,"url":"https://patchwork.plctlab.org/api/1.2/patches/26494/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/761a39a87ef882c6d99d135988d251d18c2bf096.1669610611.git.research_trasio@irq.a4lg.com/","msgid":"<761a39a87ef882c6d99d135988d251d18c2bf096.1669610611.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-28T04:43:37","name":"[v2,02/11] RISC-V: Add test for '\''Zfinx'\'' register switching","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/761a39a87ef882c6d99d135988d251d18c2bf096.1669610611.git.research_trasio@irq.a4lg.com/mbox/"},{"id":26495,"url":"https://patchwork.plctlab.org/api/1.2/patches/26495/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c52af18da452a844c5fddf64b9b8e7b53f208111.1669610611.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-11-28T04:43:38","name":"[v2,03/11] RISC-V: Make mapping symbol checking consistent","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c52af18da452a844c5fddf64b9b8e7b53f208111.1669610611.git.research_trasio@irq.a4lg.com/mbox/"},{"id":26497,"url":"https://patchwork.plctlab.org/api/1.2/patches/26497/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/395973f56b805a000b0e2929c6b2ba6cd8fd140b.1669610611.git.research_trasio@irq.a4lg.com/","msgid":"<395973f56b805a000b0e2929c6b2ba6cd8fd140b.1669610611.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-28T04:43:39","name":"[v2,04/11] RISC-V: Split riscv_get_map_state into two steps","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/395973f56b805a000b0e2929c6b2ba6cd8fd140b.1669610611.git.research_trasio@irq.a4lg.com/mbox/"},{"id":26496,"url":"https://patchwork.plctlab.org/api/1.2/patches/26496/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/72c8e56861fccff6720a9b6ccefcecfd80e1adba.1669610611.git.research_trasio@irq.a4lg.com/","msgid":"<72c8e56861fccff6720a9b6ccefcecfd80e1adba.1669610611.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-28T04:43:40","name":"[v2,05/11] RISC-V: One time CSR hash table initialization","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/72c8e56861fccff6720a9b6ccefcecfd80e1adba.1669610611.git.research_trasio@irq.a4lg.com/mbox/"},{"id":26499,"url":"https://patchwork.plctlab.org/api/1.2/patches/26499/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/072cb269b90f85fdfd880a6513080a18ddde015d.1669610611.git.research_trasio@irq.a4lg.com/","msgid":"<072cb269b90f85fdfd880a6513080a18ddde015d.1669610611.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-28T04:43:41","name":"[v2,06/11] RISC-V: Use static xlen on ADDIW sequence","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/072cb269b90f85fdfd880a6513080a18ddde015d.1669610611.git.research_trasio@irq.a4lg.com/mbox/"},{"id":26503,"url":"https://patchwork.plctlab.org/api/1.2/patches/26503/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8f4167371bc52f2c4c7fc6f1a0fc3775e8e8de95.1669610611.git.research_trasio@irq.a4lg.com/","msgid":"<8f4167371bc52f2c4c7fc6f1a0fc3775e8e8de95.1669610611.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-28T04:43:42","name":"[v2,07/11] opcodes/riscv-dis.c: Add form feed for separation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8f4167371bc52f2c4c7fc6f1a0fc3775e8e8de95.1669610611.git.research_trasio@irq.a4lg.com/mbox/"},{"id":26498,"url":"https://patchwork.plctlab.org/api/1.2/patches/26498/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c30cdce491780153a7fe89b79ac4b5f1a03f6e5c.1669610611.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-11-28T04:43:43","name":"[v2,08/11] RISC-V: Split match/print steps on disassembler","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c30cdce491780153a7fe89b79ac4b5f1a03f6e5c.1669610611.git.research_trasio@irq.a4lg.com/mbox/"},{"id":26506,"url":"https://patchwork.plctlab.org/api/1.2/patches/26506/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a30d861f289af8dfaf7c80ff275980699aa78482.1669610611.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-11-28T04:43:44","name":"[v2,09/11] RISC-V: Reorganize disassembler state initialization","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a30d861f289af8dfaf7c80ff275980699aa78482.1669610611.git.research_trasio@irq.a4lg.com/mbox/"},{"id":26508,"url":"https://patchwork.plctlab.org/api/1.2/patches/26508/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0e328130d90af42f30e3632fadd6c48e422b7b82.1669610611.git.research_trasio@irq.a4lg.com/","msgid":"<0e328130d90af42f30e3632fadd6c48e422b7b82.1669610611.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-28T04:43:45","name":"[v2,10/11] RISC-V: Reorganize arch-related initialization and management","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0e328130d90af42f30e3632fadd6c48e422b7b82.1669610611.git.research_trasio@irq.a4lg.com/mbox/"},{"id":26500,"url":"https://patchwork.plctlab.org/api/1.2/patches/26500/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/75d9e5b0cfebcce34c855e4c98a956de4d7d7753.1669610611.git.research_trasio@irq.a4lg.com/","msgid":"<75d9e5b0cfebcce34c855e4c98a956de4d7d7753.1669610611.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-28T04:43:46","name":"[v2,11/11] RISC-V: Move disassembler private data initialization","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/75d9e5b0cfebcce34c855e4c98a956de4d7d7753.1669610611.git.research_trasio@irq.a4lg.com/mbox/"},{"id":26504,"url":"https://patchwork.plctlab.org/api/1.2/patches/26504/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a3f9238a36255d5bd251cc73cee6a47eea6b9b49.1669610780.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-11-28T04:46:20","name":"[v2,1/3] RISC-V: Use faster hash table on disassembling","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a3f9238a36255d5bd251cc73cee6a47eea6b9b49.1669610780.git.research_trasio@irq.a4lg.com/mbox/"},{"id":26507,"url":"https://patchwork.plctlab.org/api/1.2/patches/26507/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0cd0bbfa70f83db276facb842b9a7bca1aaa77a6.1669610780.git.research_trasio@irq.a4lg.com/","msgid":"<0cd0bbfa70f83db276facb842b9a7bca1aaa77a6.1669610780.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-28T04:46:21","name":"[v2,2/3] RISC-V: Fallback on faster hash table","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0cd0bbfa70f83db276facb842b9a7bca1aaa77a6.1669610780.git.research_trasio@irq.a4lg.com/mbox/"},{"id":26501,"url":"https://patchwork.plctlab.org/api/1.2/patches/26501/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5b561967091a59d0052bd717d1b9f3e31ef841cc.1669610780.git.research_trasio@irq.a4lg.com/","msgid":"<5b561967091a59d0052bd717d1b9f3e31ef841cc.1669610780.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-28T04:46:22","name":"[v2,3/3] RISC-V: Cache instruction support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5b561967091a59d0052bd717d1b9f3e31ef841cc.1669610780.git.research_trasio@irq.a4lg.com/mbox/"},{"id":26505,"url":"https://patchwork.plctlab.org/api/1.2/patches/26505/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c49e114f7ae383c0e1da452391f19ecf45a3896e.1669610841.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-11-28T04:47:21","name":"[v2,1/3] RISC-V: Easy optimization on riscv_search_mapping_symbol","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c49e114f7ae383c0e1da452391f19ecf45a3896e.1669610841.git.research_trasio@irq.a4lg.com/mbox/"},{"id":26509,"url":"https://patchwork.plctlab.org/api/1.2/patches/26509/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4b8fcca24b8897f382b6e32fd29337f0b6972e2f.1669610841.git.research_trasio@irq.a4lg.com/","msgid":"<4b8fcca24b8897f382b6e32fd29337f0b6972e2f.1669610841.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-28T04:47:22","name":"[v2,2/3] RISC-V: Per-section private data initialization","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4b8fcca24b8897f382b6e32fd29337f0b6972e2f.1669610841.git.research_trasio@irq.a4lg.com/mbox/"},{"id":26510,"url":"https://patchwork.plctlab.org/api/1.2/patches/26510/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f1cbc305ba19880fa0631ebe691b5c0984cbf111.1669610841.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-11-28T04:47:23","name":"[v2,3/3] RISC-V: Optimized search on mapping symbols","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f1cbc305ba19880fa0631ebe691b5c0984cbf111.1669610841.git.research_trasio@irq.a4lg.com/mbox/"},{"id":26531,"url":"https://patchwork.plctlab.org/api/1.2/patches/26531/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221128063532.1153605-1-jiawei@iscas.ac.cn/","msgid":"<20221128063532.1153605-1-jiawei@iscas.ac.cn>","list_archive_url":null,"date":"2022-11-28T06:35:32","name":"RISC-V: Add support for RISCV64 EFI(efi-*-riscv64)","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221128063532.1153605-1-jiawei@iscas.ac.cn/mbox/"},{"id":26532,"url":"https://patchwork.plctlab.org/api/1.2/patches/26532/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d1c4d243e6e33c6d0c681a7de3a8fb8be548c99d.1669617534.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-11-28T06:39:32","name":"[1/3] RISC-V: Allocate \"various\" operand type","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d1c4d243e6e33c6d0c681a7de3a8fb8be548c99d.1669617534.git.research_trasio@irq.a4lg.com/mbox/"},{"id":26533,"url":"https://patchwork.plctlab.org/api/1.2/patches/26533/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1a60e4b17f89e7aa94a6a41674f885398e5afd85.1669617534.git.research_trasio@irq.a4lg.com/","msgid":"<1a60e4b17f89e7aa94a6a41674f885398e5afd85.1669617534.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-28T06:39:33","name":"[2/3] RISC-V: Reorganize invalid rounding mode test","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1a60e4b17f89e7aa94a6a41674f885398e5afd85.1669617534.git.research_trasio@irq.a4lg.com/mbox/"},{"id":26534,"url":"https://patchwork.plctlab.org/api/1.2/patches/26534/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/354029278ac02efee0bf1f1dbc3514647f057424.1669617534.git.research_trasio@irq.a4lg.com/","msgid":"<354029278ac02efee0bf1f1dbc3514647f057424.1669617534.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-28T06:39:34","name":"[3/3] RISC-V: Rounding mode on widening instructions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/354029278ac02efee0bf1f1dbc3514647f057424.1669617534.git.research_trasio@irq.a4lg.com/mbox/"},{"id":26600,"url":"https://patchwork.plctlab.org/api/1.2/patches/26600/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y4SDJrb7d7HMtR7H@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-11-28T09:45:10","name":"asan: pef: buffer overflow","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y4SDJrb7d7HMtR7H@squeak.grove.modra.org/mbox/"},{"id":26601,"url":"https://patchwork.plctlab.org/api/1.2/patches/26601/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y4SDxVt7uN6m6oKA@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-11-28T09:47:49","name":"PR10368, ISO 8859 mentioned as 7bit encoding in strings documentation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y4SDxVt7uN6m6oKA@squeak.grove.modra.org/mbox/"},{"id":26634,"url":"https://patchwork.plctlab.org/api/1.2/patches/26634/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/da678d9e-b1eb-e599-ec0b-2a991d65e61c@suse.com/","msgid":"","list_archive_url":null,"date":"2022-11-28T11:30:46","name":"[v3,1/6] x86: instantiate i386_{op, reg}tab[] in gas instead of in libopcodes","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/da678d9e-b1eb-e599-ec0b-2a991d65e61c@suse.com/mbox/"},{"id":26636,"url":"https://patchwork.plctlab.org/api/1.2/patches/26636/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/851ace49-624f-c3bc-805f-59feeaf8a711@suse.com/","msgid":"<851ace49-624f-c3bc-805f-59feeaf8a711@suse.com>","list_archive_url":null,"date":"2022-11-28T11:31:20","name":"[v3,2/6] x86: remove i386-opc.c","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/851ace49-624f-c3bc-805f-59feeaf8a711@suse.com/mbox/"},{"id":26638,"url":"https://patchwork.plctlab.org/api/1.2/patches/26638/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2bf96982-d3d6-026a-ca1c-16b932d9630a@suse.com/","msgid":"<2bf96982-d3d6-026a-ca1c-16b932d9630a@suse.com>","list_archive_url":null,"date":"2022-11-28T11:31:44","name":"[v3,3/6] x86: break gas dependency on libopcodes","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2bf96982-d3d6-026a-ca1c-16b932d9630a@suse.com/mbox/"},{"id":26640,"url":"https://patchwork.plctlab.org/api/1.2/patches/26640/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c8f5780b-072e-b184-f153-3c2af7ea577e@suse.com/","msgid":"","list_archive_url":null,"date":"2022-11-28T11:32:07","name":"[v3,4/6] x86: add generated tables dependency check to gas","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c8f5780b-072e-b184-f153-3c2af7ea577e@suse.com/mbox/"},{"id":26643,"url":"https://patchwork.plctlab.org/api/1.2/patches/26643/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/414cbe39-9398-ddab-97f2-93d6c0bf9852@suse.com/","msgid":"<414cbe39-9398-ddab-97f2-93d6c0bf9852@suse.com>","list_archive_url":null,"date":"2022-11-28T11:32:40","name":"[v3,5/6] x86: drop sentinel from i386_optab[]","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/414cbe39-9398-ddab-97f2-93d6c0bf9852@suse.com/mbox/"},{"id":26644,"url":"https://patchwork.plctlab.org/api/1.2/patches/26644/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0387160b-8925-7515-e287-e1f240f93523@suse.com/","msgid":"<0387160b-8925-7515-e287-e1f240f93523@suse.com>","list_archive_url":null,"date":"2022-11-28T11:33:37","name":"[v3,6/6] x86: generate template sets data at build time","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0387160b-8925-7515-e287-e1f240f93523@suse.com/mbox/"},{"id":26794,"url":"https://patchwork.plctlab.org/api/1.2/patches/26794/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/67cc7870-f49c-08ed-afb3-e83f4378095a@arm.com/","msgid":"<67cc7870-f49c-08ed-afb3-e83f4378095a@arm.com>","list_archive_url":null,"date":"2022-11-28T14:13:12","name":"[1/2] gas: arm: Fix a further IT-predicated vcvt issue in the presense of MVE vcvtn","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/67cc7870-f49c-08ed-afb3-e83f4378095a@arm.com/mbox/"},{"id":26795,"url":"https://patchwork.plctlab.org/api/1.2/patches/26795/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b40e6dc8-9ff8-000c-f639-ee516c4ccab7@arm.com/","msgid":"","list_archive_url":null,"date":"2022-11-28T14:13:27","name":"[2/2] gas: arm: Change warning message to not reference specific A-class architecture revision","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b40e6dc8-9ff8-000c-f639-ee516c4ccab7@arm.com/mbox/"},{"id":26799,"url":"https://patchwork.plctlab.org/api/1.2/patches/26799/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/661d0e07-cc75-0fba-941b-88160dbcbb13@suse.com/","msgid":"<661d0e07-cc75-0fba-941b-88160dbcbb13@suse.com>","list_archive_url":null,"date":"2022-11-28T14:24:31","name":"x86/Intel: adjustment to restricted suffix derivation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/661d0e07-cc75-0fba-941b-88160dbcbb13@suse.com/mbox/"},{"id":26977,"url":"https://patchwork.plctlab.org/api/1.2/patches/26977/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/CAMe9rOpbKEZ=wSgTbDLEXgzj2sbAHp1uU0WSGy0qTPL1fakM0g@mail.gmail.com/","msgid":"","list_archive_url":null,"date":"2022-11-28T23:49:42","name":"[v2] x86: Remove libopcodes dependency","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/CAMe9rOpbKEZ=wSgTbDLEXgzj2sbAHp1uU0WSGy0qTPL1fakM0g@mail.gmail.com/mbox/"},{"id":26982,"url":"https://patchwork.plctlab.org/api/1.2/patches/26982/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221129001015.21775-1-mark@harmstone.com/","msgid":"<20221129001015.21775-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-11-29T00:10:13","name":"ld: Write types into TPI stream of PDB","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221129001015.21775-1-mark@harmstone.com/mbox/"},{"id":26981,"url":"https://patchwork.plctlab.org/api/1.2/patches/26981/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221129001015.21775-2-mark@harmstone.com/","msgid":"<20221129001015.21775-2-mark@harmstone.com>","list_archive_url":null,"date":"2022-11-29T00:10:14","name":"ld: Write types into IPI stream of PDB","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221129001015.21775-2-mark@harmstone.com/mbox/"},{"id":26983,"url":"https://patchwork.plctlab.org/api/1.2/patches/26983/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221129001015.21775-3-mark@harmstone.com/","msgid":"<20221129001015.21775-3-mark@harmstone.com>","list_archive_url":null,"date":"2022-11-29T00:10:15","name":"ld: Parse LF_UDT_SRC_LINE records when creating PDB file","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221129001015.21775-3-mark@harmstone.com/mbox/"},{"id":26994,"url":"https://patchwork.plctlab.org/api/1.2/patches/26994/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/daddde128db2f014de16a7cf8a229aed53074b02.1669684562.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-11-29T01:16:56","name":"[REVIEW,ONLY,1/1] UNRATIFIED RISC-V: Add '\''ZiCondOps'\'' extension","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/daddde128db2f014de16a7cf8a229aed53074b02.1669684562.git.research_trasio@irq.a4lg.com/mbox/"},{"id":26995,"url":"https://patchwork.plctlab.org/api/1.2/patches/26995/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/29f89ef04335561879d14d9cdb8e1e9a550bc811.1669684692.git.research_trasio@irq.a4lg.com/","msgid":"<29f89ef04335561879d14d9cdb8e1e9a550bc811.1669684692.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-29T01:18:15","name":"[REVIEW,ONLY,1/1] UNRATIFIED RISC-V: Add '\''Svadu'\'' extension","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/29f89ef04335561879d14d9cdb8e1e9a550bc811.1669684692.git.research_trasio@irq.a4lg.com/mbox/"},{"id":26996,"url":"https://patchwork.plctlab.org/api/1.2/patches/26996/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d32f305c187892c2a97fef6eebca220c90eac3b7.1669684774.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-11-29T01:19:53","name":"[REVIEW,ONLY,1/1] UNRATIFIED RISC-V: Add '\''Smclic'\'' extension and its CSRs","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d32f305c187892c2a97fef6eebca220c90eac3b7.1669684774.git.research_trasio@irq.a4lg.com/mbox/"},{"id":26997,"url":"https://patchwork.plctlab.org/api/1.2/patches/26997/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/54d777ce6e71c02b8b0f9426367e98d0f927ce40.1669684854.git.research_trasio@irq.a4lg.com/","msgid":"<54d777ce6e71c02b8b0f9426367e98d0f927ce40.1669684854.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-29T01:20:57","name":"[REVIEW,ONLY,1/2] UNRATIFIED RISC-V: Add '\''Sspmp'\'' extension and its TENTATIVE CSRs","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/54d777ce6e71c02b8b0f9426367e98d0f927ce40.1669684854.git.research_trasio@irq.a4lg.com/mbox/"},{"id":26998,"url":"https://patchwork.plctlab.org/api/1.2/patches/26998/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ee7c7490f10af1e9cc9c9475814e4d8a9b1a9304.1669684854.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-11-29T01:20:58","name":"[REVIEW,ONLY,2/2] TEST: Add instantiation script on CSR allocation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ee7c7490f10af1e9cc9c9475814e4d8a9b1a9304.1669684854.git.research_trasio@irq.a4lg.com/mbox/"},{"id":27004,"url":"https://patchwork.plctlab.org/api/1.2/patches/27004/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/03cbfeb6934c7bf653cbdfbafcc6ee5ce3cb519c.1669684907.git.research_trasio@irq.a4lg.com/","msgid":"<03cbfeb6934c7bf653cbdfbafcc6ee5ce3cb519c.1669684907.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-29T01:21:51","name":"[REVIEW,ONLY,1/1] UNRATIFIED RISC-V: Add '\''Smrnmi'\'' extension and its CSRs","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/03cbfeb6934c7bf653cbdfbafcc6ee5ce3cb519c.1669684907.git.research_trasio@irq.a4lg.com/mbox/"},{"id":27013,"url":"https://patchwork.plctlab.org/api/1.2/patches/27013/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0187562c00ee6c8ba82439bd61e46a1899b9f916.1669684988.git.research_trasio@irq.a4lg.com/","msgid":"<0187562c00ee6c8ba82439bd61e46a1899b9f916.1669684988.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-29T01:23:57","name":"[REVIEW,ONLY,1/3] RISC-V: Add \"XUN@S\" operand type","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0187562c00ee6c8ba82439bd61e46a1899b9f916.1669684988.git.research_trasio@irq.a4lg.com/mbox/"},{"id":27017,"url":"https://patchwork.plctlab.org/api/1.2/patches/27017/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/cae340b249629f0b05b527ae8aec3023b159b487.1669684988.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-11-29T01:23:58","name":"[REVIEW,ONLY,2/3] UNRATIFIED RISC-V: Add '\''Zisslpcfi'\'' extension and its TENTATIVE CSRs","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/cae340b249629f0b05b527ae8aec3023b159b487.1669684988.git.research_trasio@irq.a4lg.com/mbox/"},{"id":27018,"url":"https://patchwork.plctlab.org/api/1.2/patches/27018/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/73828cb4ccf8c03275b6af7e42872d661dea267f.1669684988.git.research_trasio@irq.a4lg.com/","msgid":"<73828cb4ccf8c03275b6af7e42872d661dea267f.1669684988.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-29T01:23:59","name":"[REVIEW,ONLY,3/3] TEST: Add instantiation script on CSR allocation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/73828cb4ccf8c03275b6af7e42872d661dea267f.1669684988.git.research_trasio@irq.a4lg.com/mbox/"},{"id":27030,"url":"https://patchwork.plctlab.org/api/1.2/patches/27030/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d6ee991833120682dc021b0269f5535c9ac3a806.1669687611.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-11-29T02:06:57","name":"[REVIEW,ONLY,v2,1/1] UNRATIFIED RISC-V: Add '\''ZiCondOps'\'' extension","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d6ee991833120682dc021b0269f5535c9ac3a806.1669687611.git.research_trasio@irq.a4lg.com/mbox/"},{"id":27035,"url":"https://patchwork.plctlab.org/api/1.2/patches/27035/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221129022520.2218851-1-jcmvbkbc@gmail.com/","msgid":"<20221129022520.2218851-1-jcmvbkbc@gmail.com>","list_archive_url":null,"date":"2022-11-29T02:25:20","name":"[COMMITTED] xtensa: allow dynamic configuration","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221129022520.2218851-1-jcmvbkbc@gmail.com/mbox/"},{"id":27161,"url":"https://patchwork.plctlab.org/api/1.2/patches/27161/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/01b77f18-8af3-4128-3645-2f1e05690197@suse.com/","msgid":"<01b77f18-8af3-4128-3645-2f1e05690197@suse.com>","list_archive_url":null,"date":"2022-11-29T10:36:21","name":"[1/5] gas: avoid inserting extra newline in buffer_and_nest()","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/01b77f18-8af3-4128-3645-2f1e05690197@suse.com/mbox/"},{"id":27163,"url":"https://patchwork.plctlab.org/api/1.2/patches/27163/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2ae84a68-29f3-d94d-1a12-c3d0c81f81a3@suse.com/","msgid":"<2ae84a68-29f3-d94d-1a12-c3d0c81f81a3@suse.com>","list_archive_url":null,"date":"2022-11-29T10:36:59","name":"[2/5] gas: squash (some) .linefile from listings","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2ae84a68-29f3-d94d-1a12-c3d0c81f81a3@suse.com/mbox/"},{"id":27164,"url":"https://patchwork.plctlab.org/api/1.2/patches/27164/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8b41d62d-8345-a2bd-ce90-27d79aefe2eb@suse.com/","msgid":"<8b41d62d-8345-a2bd-ce90-27d79aefe2eb@suse.com>","list_archive_url":null,"date":"2022-11-29T10:37:42","name":"[3/5] gas: add Dwarf line number test for .macro expansions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8b41d62d-8345-a2bd-ce90-27d79aefe2eb@suse.com/mbox/"},{"id":27165,"url":"https://patchwork.plctlab.org/api/1.2/patches/27165/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ca933e73-103d-0e9c-84b7-f0a1650dfa2f@suse.com/","msgid":"","list_archive_url":null,"date":"2022-11-29T10:38:52","name":"[4/5] Arm: avoid unhelpful use of .macro in testsuite","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ca933e73-103d-0e9c-84b7-f0a1650dfa2f@suse.com/mbox/"},{"id":27167,"url":"https://patchwork.plctlab.org/api/1.2/patches/27167/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1c75f3b4-14ac-fa39-fac8-2c98b4c4dbab@suse.com/","msgid":"<1c75f3b4-14ac-fa39-fac8-2c98b4c4dbab@suse.com>","list_archive_url":null,"date":"2022-11-29T10:44:51","name":"[5/5] gas: re-work line number tracking for macros and their expansions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1c75f3b4-14ac-fa39-fac8-2c98b4c4dbab@suse.com/mbox/"},{"id":27626,"url":"https://patchwork.plctlab.org/api/1.2/patches/27626/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y4cPz0nw9PS+slTj@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-11-30T08:09:51","name":"regen SRC-POTFILES.in","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y4cPz0nw9PS+slTj@squeak.grove.modra.org/mbox/"},{"id":27629,"url":"https://patchwork.plctlab.org/api/1.2/patches/27629/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y4cQAk+8VjJUNcAS@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-11-30T08:10:42","name":"Correct ordering problem in comm-data.exp","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y4cQAk+8VjJUNcAS@squeak.grove.modra.org/mbox/"},{"id":27689,"url":"https://patchwork.plctlab.org/api/1.2/patches/27689/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3d8c5353-723d-31ec-8efa-ee4fc994eaec@suse.com/","msgid":"<3d8c5353-723d-31ec-8efa-ee4fc994eaec@suse.com>","list_archive_url":null,"date":"2022-11-30T08:54:43","name":"[1/4] x86/Intel: restrict use of LONG_DOUBLE_MNEM_SUFFIX","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3d8c5353-723d-31ec-8efa-ee4fc994eaec@suse.com/mbox/"},{"id":27690,"url":"https://patchwork.plctlab.org/api/1.2/patches/27690/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/934cece1-77ed-b4ee-a61d-451d71680a9e@suse.com/","msgid":"<934cece1-77ed-b4ee-a61d-451d71680a9e@suse.com>","list_archive_url":null,"date":"2022-11-30T08:55:11","name":"[2/4] x86/Intel: drop LONG_DOUBLE_MNEM_SUFFIX","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/934cece1-77ed-b4ee-a61d-451d71680a9e@suse.com/mbox/"},{"id":27691,"url":"https://patchwork.plctlab.org/api/1.2/patches/27691/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f0d0c80a-1b30-6e13-ceff-d3a1061db2ea@suse.com/","msgid":"","list_archive_url":null,"date":"2022-11-30T08:55:43","name":"[3/4] x86: drop No_ldSuf","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f0d0c80a-1b30-6e13-ceff-d3a1061db2ea@suse.com/mbox/"},{"id":27692,"url":"https://patchwork.plctlab.org/api/1.2/patches/27692/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/787c0eff-5b73-ed04-6e06-e3f49d5a3ce1@suse.com/","msgid":"<787c0eff-5b73-ed04-6e06-e3f49d5a3ce1@suse.com>","list_archive_url":null,"date":"2022-11-30T08:56:52","name":"[4/4] x86: rework of match_template()'\''s suffix checking","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/787c0eff-5b73-ed04-6e06-e3f49d5a3ce1@suse.com/mbox/"}],"public":true,"mbox":"https://patchwork.plctlab.org/bundle/patchwork-bot/binutils-gdb_2022-11/mbox/"},{"id":12,"url":"https://patchwork.plctlab.org/api/1.2/bundles/12/","web_url":"https://patchwork.plctlab.org/bundle/patchwork-bot/binutils-gdb_2022-12/","project":{"id":2,"url":"https://patchwork.plctlab.org/api/1.2/projects/2/","name":"binutils-gdb","link_name":"binutils-gdb","list_id":"binutils.sourceware.org","list_email":"binutils@sourceware.org","web_url":"https://github.com/wangliu-iscas/Patchwork-Bundles/blob/main/binutils-gdb.md","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"name":"binutils-gdb_2022-12","owner":{"id":3,"url":"https://patchwork.plctlab.org/api/1.2/users/3/","username":"patchwork-bot","first_name":"","last_name":"","email":"ouuuleilei@gmail.com"},"patches":[{"id":28023,"url":"https://patchwork.plctlab.org/api/1.2/patches/28023/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221130214802.32340-1-hjl.tools@gmail.com/","msgid":"<20221130214802.32340-1-hjl.tools@gmail.com>","list_archive_url":null,"date":"2022-11-30T21:48:02","name":"opcodes: Remove i386-init.h and i386-tbl.h from HFILES","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221130214802.32340-1-hjl.tools@gmail.com/mbox/"},{"id":28172,"url":"https://patchwork.plctlab.org/api/1.2/patches/28172/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f6ef4412c1f0d5a7b0292f443ea5aee31c25056d.1669864784.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-12-01T03:20:31","name":"[REVIEW,ONLY,v3,1/1] UNRATIFIED RISC-V: Add '\''ZiCond'\'' extension","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f6ef4412c1f0d5a7b0292f443ea5aee31c25056d.1669864784.git.research_trasio@irq.a4lg.com/mbox/"},{"id":28257,"url":"https://patchwork.plctlab.org/api/1.2/patches/28257/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/673753a0-ab7b-6c44-844e-3addfcf01693@suse.com/","msgid":"<673753a0-ab7b-6c44-844e-3addfcf01693@suse.com>","list_archive_url":null,"date":"2022-12-01T09:09:26","name":"x86: also use D for XCHG and TEST","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/673753a0-ab7b-6c44-844e-3addfcf01693@suse.com/mbox/"},{"id":28258,"url":"https://patchwork.plctlab.org/api/1.2/patches/28258/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/35539292-53a8-292d-2f5d-f65ad02a36bb@suse.com/","msgid":"<35539292-53a8-292d-2f5d-f65ad02a36bb@suse.com>","list_archive_url":null,"date":"2022-12-01T09:11:50","name":"x86: simplify and slightly correct XCHG vs NOP checking","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/35539292-53a8-292d-2f5d-f65ad02a36bb@suse.com/mbox/"},{"id":28260,"url":"https://patchwork.plctlab.org/api/1.2/patches/28260/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b56e7b03-c15b-a932-bd6b-e026d9ae8675@suse.com/","msgid":"","list_archive_url":null,"date":"2022-12-01T09:20:24","name":"x86: drop most OPERAND_TYPE_* (and rework the rest)","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b56e7b03-c15b-a932-bd6b-e026d9ae8675@suse.com/mbox/"},{"id":28274,"url":"https://patchwork.plctlab.org/api/1.2/patches/28274/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221201094409.1982624-1-chigot@adacore.com/","msgid":"<20221201094409.1982624-1-chigot@adacore.com>","list_archive_url":null,"date":"2022-12-01T09:44:09","name":"binutils: improve holes detection in .debug_loclists.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221201094409.1982624-1-chigot@adacore.com/mbox/"},{"id":28448,"url":"https://patchwork.plctlab.org/api/1.2/patches/28448/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221201162038.421271-1-hjl.tools@gmail.com/","msgid":"<20221201162038.421271-1-hjl.tools@gmail.com>","list_archive_url":null,"date":"2022-12-01T16:20:38","name":"opcodes: Make i386-init.h depend on i386-tbl.h","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221201162038.421271-1-hjl.tools@gmail.com/mbox/"},{"id":28503,"url":"https://patchwork.plctlab.org/api/1.2/patches/28503/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y4jx62oUPn2PB3tC@gmail.com/","msgid":"","list_archive_url":null,"date":"2022-12-01T18:26:51","name":"[v3] x86: Remove libopcodes dependency","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y4jx62oUPn2PB3tC@gmail.com/mbox/"},{"id":28837,"url":"https://patchwork.plctlab.org/api/1.2/patches/28837/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/87mt8615k1.fsf@redhat.com/","msgid":"<87mt8615k1.fsf@redhat.com>","list_archive_url":null,"date":"2022-12-02T10:08:30","name":"Adding Jan Beulich as an x86_64 maintainer","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/87mt8615k1.fsf@redhat.com/mbox/"},{"id":28852,"url":"https://patchwork.plctlab.org/api/1.2/patches/28852/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8bfb1c56-8207-fe92-87ae-1b7ef26b3544@suse.com/","msgid":"<8bfb1c56-8207-fe92-87ae-1b7ef26b3544@suse.com>","list_archive_url":null,"date":"2022-12-02T10:18:00","name":"[v7,1/7] x86: constify parse_insn()'\''s input","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8bfb1c56-8207-fe92-87ae-1b7ef26b3544@suse.com/mbox/"},{"id":28855,"url":"https://patchwork.plctlab.org/api/1.2/patches/28855/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6043f9b3-1ea1-ea4a-59ae-dcccf129c241@suse.com/","msgid":"<6043f9b3-1ea1-ea4a-59ae-dcccf129c241@suse.com>","list_archive_url":null,"date":"2022-12-02T10:18:54","name":"[v7,2/7] x86: re-work insn/suffix recognition","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6043f9b3-1ea1-ea4a-59ae-dcccf129c241@suse.com/mbox/"},{"id":28856,"url":"https://patchwork.plctlab.org/api/1.2/patches/28856/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f7f77244-9782-0bc1-365c-e73d72045f36@suse.com/","msgid":"","list_archive_url":null,"date":"2022-12-02T10:19:32","name":"[v7,3/7] ix86: don'\''t recognize/derive Q suffix in the common case","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f7f77244-9782-0bc1-365c-e73d72045f36@suse.com/mbox/"},{"id":28857,"url":"https://patchwork.plctlab.org/api/1.2/patches/28857/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/77fa4300-e192-5b9d-d699-37255054d391@suse.com/","msgid":"<77fa4300-e192-5b9d-d699-37255054d391@suse.com>","list_archive_url":null,"date":"2022-12-02T10:20:06","name":"[v7,4/7] x86-64: allow HLE store of accumulator to absolute 32-bit address","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/77fa4300-e192-5b9d-d699-37255054d391@suse.com/mbox/"},{"id":28860,"url":"https://patchwork.plctlab.org/api/1.2/patches/28860/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b4c2d623-517c-f5e8-90d9-01e933a68a00@suse.com/","msgid":"","list_archive_url":null,"date":"2022-12-02T10:20:34","name":"[v7,5/7] x86: move bad-use-of-TLS-reloc check","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b4c2d623-517c-f5e8-90d9-01e933a68a00@suse.com/mbox/"},{"id":28859,"url":"https://patchwork.plctlab.org/api/1.2/patches/28859/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ac7e5911-4c5e-27c3-b0e5-cd3dcfa67155@suse.com/","msgid":"","list_archive_url":null,"date":"2022-12-02T10:21:02","name":"[v7,6/7] x86: drop (now) stray IsString","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ac7e5911-4c5e-27c3-b0e5-cd3dcfa67155@suse.com/mbox/"},{"id":28861,"url":"https://patchwork.plctlab.org/api/1.2/patches/28861/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/46702842-5bc7-113e-bab8-d67304f0f337@suse.com/","msgid":"<46702842-5bc7-113e-bab8-d67304f0f337@suse.com>","list_archive_url":null,"date":"2022-12-02T10:21:46","name":"[v7,7/7] x86: further re-work insn/suffix recognition to also cover MOVSX","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/46702842-5bc7-113e-bab8-d67304f0f337@suse.com/mbox/"},{"id":29215,"url":"https://patchwork.plctlab.org/api/1.2/patches/29215/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221203041307.34407-1-hjl.tools@gmail.com/","msgid":"<20221203041307.34407-1-hjl.tools@gmail.com>","list_archive_url":null,"date":"2022-12-03T04:13:07","name":"x86: Allow 16-bit register source for LAR and LSL","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221203041307.34407-1-hjl.tools@gmail.com/mbox/"},{"id":29241,"url":"https://patchwork.plctlab.org/api/1.2/patches/29241/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221203073435.1451856-1-mengqinggang@loongson.cn/","msgid":"<20221203073435.1451856-1-mengqinggang@loongson.cn>","list_archive_url":null,"date":"2022-12-03T07:34:35","name":"LoongArch: Fix dynamic reloc not generated bug in some cases.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221203073435.1451856-1-mengqinggang@loongson.cn/mbox/"},{"id":29297,"url":"https://patchwork.plctlab.org/api/1.2/patches/29297/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221203174330.682680-1-hjl.tools@gmail.com/","msgid":"<20221203174330.682680-1-hjl.tools@gmail.com>","list_archive_url":null,"date":"2022-12-03T17:43:30","name":"ld: Add .note.GNU-stack to ld-plugin/dummy.s","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221203174330.682680-1-hjl.tools@gmail.com/mbox/"},{"id":29299,"url":"https://patchwork.plctlab.org/api/1.2/patches/29299/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221203184408.866763-1-hjl.tools@gmail.com/","msgid":"<20221203184408.866763-1-hjl.tools@gmail.com>","list_archive_url":null,"date":"2022-12-03T18:44:08","name":"Revert \"ld: Add .note.GNU-stack to ld-plugin/dummy.s\"","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221203184408.866763-1-hjl.tools@gmail.com/mbox/"},{"id":29461,"url":"https://patchwork.plctlab.org/api/1.2/patches/29461/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y40WXnjN0f0LjrIt@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-12-04T21:51:26","name":"Renaming .debug to .zdebug and vice versa","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y40WXnjN0f0LjrIt@squeak.grove.modra.org/mbox/"},{"id":29462,"url":"https://patchwork.plctlab.org/api/1.2/patches/29462/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y40WfJl0V9ifv+fN@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-12-04T21:51:56","name":"COFF compressed debug support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y40WfJl0V9ifv+fN@squeak.grove.modra.org/mbox/"},{"id":29463,"url":"https://patchwork.plctlab.org/api/1.2/patches/29463/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y40WrrfotDOwKqZb@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-12-04T21:52:46","name":"PR29846, segmentation fault in objdump.c compare_symbols","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y40WrrfotDOwKqZb@squeak.grove.modra.org/mbox/"},{"id":29492,"url":"https://patchwork.plctlab.org/api/1.2/patches/29492/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221205015347.25781-1-mark@harmstone.com/","msgid":"<20221205015347.25781-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-12-05T01:53:45","name":"ld: Write globals stream in PDB","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221205015347.25781-1-mark@harmstone.com/mbox/"},{"id":29491,"url":"https://patchwork.plctlab.org/api/1.2/patches/29491/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221205015347.25781-2-mark@harmstone.com/","msgid":"<20221205015347.25781-2-mark@harmstone.com>","list_archive_url":null,"date":"2022-12-05T01:53:46","name":"ld: Copy other symbols into PDB file","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221205015347.25781-2-mark@harmstone.com/mbox/"},{"id":29490,"url":"https://patchwork.plctlab.org/api/1.2/patches/29490/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221205015347.25781-3-mark@harmstone.com/","msgid":"<20221205015347.25781-3-mark@harmstone.com>","list_archive_url":null,"date":"2022-12-05T01:53:47","name":"ld: Write linker symbols in PDB","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221205015347.25781-3-mark@harmstone.com/mbox/"},{"id":29502,"url":"https://patchwork.plctlab.org/api/1.2/patches/29502/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221205025311.73743-1-haochen.jiang@intel.com/","msgid":"<20221205025311.73743-1-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-12-05T02:53:11","name":"x86: Remove unnecessary vex.w check for xh_mode in disassembler","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221205025311.73743-1-haochen.jiang@intel.com/mbox/"},{"id":29578,"url":"https://patchwork.plctlab.org/api/1.2/patches/29578/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221205080453.1352069-2-mengqinggang@loongson.cn/","msgid":"<20221205080453.1352069-2-mengqinggang@loongson.cn>","list_archive_url":null,"date":"2022-12-05T08:04:48","name":"[v1,1/6] LoongArch: include: Add support for linker relaxation.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221205080453.1352069-2-mengqinggang@loongson.cn/mbox/"},{"id":29585,"url":"https://patchwork.plctlab.org/api/1.2/patches/29585/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221205080453.1352069-3-mengqinggang@loongson.cn/","msgid":"<20221205080453.1352069-3-mengqinggang@loongson.cn>","list_archive_url":null,"date":"2022-12-05T08:04:49","name":"[v1,2/6] LoongArch: bfd: Add support for linker relaxation.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221205080453.1352069-3-mengqinggang@loongson.cn/mbox/"},{"id":29577,"url":"https://patchwork.plctlab.org/api/1.2/patches/29577/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221205080453.1352069-4-mengqinggang@loongson.cn/","msgid":"<20221205080453.1352069-4-mengqinggang@loongson.cn>","list_archive_url":null,"date":"2022-12-05T08:04:50","name":"[v1,3/6] LoongArch: opcodes: Add support for linker relaxation.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221205080453.1352069-4-mengqinggang@loongson.cn/mbox/"},{"id":29580,"url":"https://patchwork.plctlab.org/api/1.2/patches/29580/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221205080453.1352069-5-mengqinggang@loongson.cn/","msgid":"<20221205080453.1352069-5-mengqinggang@loongson.cn>","list_archive_url":null,"date":"2022-12-05T08:04:51","name":"[v1,4/6] LoongArch: binutils: Add support for linker relaxation.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221205080453.1352069-5-mengqinggang@loongson.cn/mbox/"},{"id":29581,"url":"https://patchwork.plctlab.org/api/1.2/patches/29581/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221205080453.1352069-6-mengqinggang@loongson.cn/","msgid":"<20221205080453.1352069-6-mengqinggang@loongson.cn>","list_archive_url":null,"date":"2022-12-05T08:04:52","name":"[v1,5/6] LoongArch: gas: Add support for linker relaxation.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221205080453.1352069-6-mengqinggang@loongson.cn/mbox/"},{"id":29587,"url":"https://patchwork.plctlab.org/api/1.2/patches/29587/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221205080453.1352069-7-mengqinggang@loongson.cn/","msgid":"<20221205080453.1352069-7-mengqinggang@loongson.cn>","list_archive_url":null,"date":"2022-12-05T08:04:53","name":"[v1,6/6] LoongArch: ld: Add support for linker relaxation.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221205080453.1352069-7-mengqinggang@loongson.cn/mbox/"},{"id":29662,"url":"https://patchwork.plctlab.org/api/1.2/patches/29662/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/76253e84-a7c3-5d09-c6a7-422573ca2d37@suse.cz/","msgid":"<76253e84-a7c3-5d09-c6a7-422573ca2d37@suse.cz>","list_archive_url":null,"date":"2022-12-05T12:10:10","name":"testsuite: support mold linker","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/76253e84-a7c3-5d09-c6a7-422573ca2d37@suse.cz/mbox/"},{"id":29689,"url":"https://patchwork.plctlab.org/api/1.2/patches/29689/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e41a37eb-20ae-b5ef-9ab3-6e38682bfbd3@suse.cz/","msgid":"","list_archive_url":null,"date":"2022-12-05T13:48:16","name":"[V2] testsuite: support mold linker","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e41a37eb-20ae-b5ef-9ab3-6e38682bfbd3@suse.cz/mbox/"},{"id":29700,"url":"https://patchwork.plctlab.org/api/1.2/patches/29700/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2eb01f7a-2430-b0bc-9c58-d15d06ca6bf9@suse.cz/","msgid":"<2eb01f7a-2430-b0bc-9c58-d15d06ca6bf9@suse.cz>","list_archive_url":null,"date":"2022-12-05T14:41:04","name":"[V3] testsuite: support mold linker","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2eb01f7a-2430-b0bc-9c58-d15d06ca6bf9@suse.cz/mbox/"},{"id":30027,"url":"https://patchwork.plctlab.org/api/1.2/patches/30027/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y46GBCcdb5NKqOgS@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-12-06T00:00:04","name":"PR29855, ch_type in bfd_init_section_decompress_status can be uninitialized","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y46GBCcdb5NKqOgS@squeak.grove.modra.org/mbox/"},{"id":30082,"url":"https://patchwork.plctlab.org/api/1.2/patches/30082/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y47NCokv10HcVEpf@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-12-06T05:03:06","name":"Compression header enum","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y47NCokv10HcVEpf@squeak.grove.modra.org/mbox/"},{"id":30083,"url":"https://patchwork.plctlab.org/api/1.2/patches/30083/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y47NPN4wWWRZyL00@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-12-06T05:03:56","name":"Get rid of SEC_ELF_RENAME","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y47NPN4wWWRZyL00@squeak.grove.modra.org/mbox/"},{"id":30084,"url":"https://patchwork.plctlab.org/api/1.2/patches/30084/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y47NWJ/QfmCo4NNo@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-12-06T05:04:24","name":"Get rid of SEC_ELF_COMPRESS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y47NWJ/QfmCo4NNo@squeak.grove.modra.org/mbox/"},{"id":30085,"url":"https://patchwork.plctlab.org/api/1.2/patches/30085/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221206053947.821648-1-zengxiao@eswincomputing.com/","msgid":"<20221206053947.821648-1-zengxiao@eswincomputing.com>","list_archive_url":null,"date":"2022-12-06T05:39:47","name":"RISC-V: Correction of machine registers mapping to dwarf registers","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221206053947.821648-1-zengxiao@eswincomputing.com/mbox/"},{"id":30511,"url":"https://patchwork.plctlab.org/api/1.2/patches/30511/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221206211044.766653-1-hjl.tools@gmail.com/","msgid":"<20221206211044.766653-1-hjl.tools@gmail.com>","list_archive_url":null,"date":"2022-12-06T21:10:44","name":"x86-64: Remove BND from 64-bit IBT PLT","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221206211044.766653-1-hjl.tools@gmail.com/mbox/"},{"id":30519,"url":"https://patchwork.plctlab.org/api/1.2/patches/30519/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221206214444.799449-1-hjl.tools@gmail.com/","msgid":"<20221206214444.799449-1-hjl.tools@gmail.com>","list_archive_url":null,"date":"2022-12-06T21:44:44","name":"gold: Remove BND from 64-bit x86-64 IBT PLT","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221206214444.799449-1-hjl.tools@gmail.com/mbox/"},{"id":30606,"url":"https://patchwork.plctlab.org/api/1.2/patches/30606/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y4/+I/FAq0yyNLGs@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-12-07T02:44:51","name":"Compression tidy and fixes","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y4/+I/FAq0yyNLGs@squeak.grove.modra.org/mbox/"},{"id":30613,"url":"https://patchwork.plctlab.org/api/1.2/patches/30613/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y5ANBOjjh0d9TEW4@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-12-07T03:48:20","name":"bfd_compress_section_contents access to elf_section_data","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y5ANBOjjh0d9TEW4@squeak.grove.modra.org/mbox/"},{"id":30615,"url":"https://patchwork.plctlab.org/api/1.2/patches/30615/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y5AOFp9g+oujWvPw@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-12-07T03:52:54","name":"_bfd_elf_slurp_secondary_reloc_section sanity check","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y5AOFp9g+oujWvPw@squeak.grove.modra.org/mbox/"},{"id":30641,"url":"https://patchwork.plctlab.org/api/1.2/patches/30641/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y5ArCeLOXPteRDFk@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-12-07T05:56:25","name":"gas compress_debug tidy","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y5ArCeLOXPteRDFk@squeak.grove.modra.org/mbox/"},{"id":30643,"url":"https://patchwork.plctlab.org/api/1.2/patches/30643/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y5ArREIxkCA2Eoqb@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-12-07T05:57:24","name":"coff make_a_section_from_file tidy","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y5ArREIxkCA2Eoqb@squeak.grove.modra.org/mbox/"},{"id":30845,"url":"https://patchwork.plctlab.org/api/1.2/patches/30845/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221207133155.3052074-2-i.swmail@xen0n.name/","msgid":"<20221207133155.3052074-2-i.swmail@xen0n.name>","list_archive_url":null,"date":"2022-12-07T13:31:51","name":"[v2,1/5] opcodes/loongarch: remove unused code","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221207133155.3052074-2-i.swmail@xen0n.name/mbox/"},{"id":30847,"url":"https://patchwork.plctlab.org/api/1.2/patches/30847/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221207133155.3052074-3-i.swmail@xen0n.name/","msgid":"<20221207133155.3052074-3-i.swmail@xen0n.name>","list_archive_url":null,"date":"2022-12-07T13:31:52","name":"[v2,2/5] opcodes/loongarch: implement style support in the disassembler","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221207133155.3052074-3-i.swmail@xen0n.name/mbox/"},{"id":30848,"url":"https://patchwork.plctlab.org/api/1.2/patches/30848/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221207133155.3052074-4-i.swmail@xen0n.name/","msgid":"<20221207133155.3052074-4-i.swmail@xen0n.name>","list_archive_url":null,"date":"2022-12-07T13:31:53","name":"[v2,3/5] opcodes/loongarch: style disassembled address offsets as such","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221207133155.3052074-4-i.swmail@xen0n.name/mbox/"},{"id":30849,"url":"https://patchwork.plctlab.org/api/1.2/patches/30849/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221207133155.3052074-5-i.swmail@xen0n.name/","msgid":"<20221207133155.3052074-5-i.swmail@xen0n.name>","list_archive_url":null,"date":"2022-12-07T13:31:54","name":"[v2,4/5] opcodes/loongarch: do not print hex notation for signed immediates","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221207133155.3052074-5-i.swmail@xen0n.name/mbox/"},{"id":30846,"url":"https://patchwork.plctlab.org/api/1.2/patches/30846/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221207133155.3052074-6-i.swmail@xen0n.name/","msgid":"<20221207133155.3052074-6-i.swmail@xen0n.name>","list_archive_url":null,"date":"2022-12-07T13:31:55","name":"[v2,5/5] opcodes/loongarch: print unrecognized instruction words with .insn prefix","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221207133155.3052074-6-i.swmail@xen0n.name/mbox/"},{"id":30875,"url":"https://patchwork.plctlab.org/api/1.2/patches/30875/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221207141137.1527113-1-felix.willgerodt@intel.com/","msgid":"<20221207141137.1527113-1-felix.willgerodt@intel.com>","list_archive_url":null,"date":"2022-12-07T14:11:37","name":"[1/1] libctf: Fix double free in ctf_link_add_cu_mapping.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221207141137.1527113-1-felix.willgerodt@intel.com/mbox/"},{"id":30967,"url":"https://patchwork.plctlab.org/api/1.2/patches/30967/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9e57c8dc-481b-82d3-7bba-8e7bd9426a1f@linux.ibm.com/","msgid":"<9e57c8dc-481b-82d3-7bba-8e7bd9426a1f@linux.ibm.com>","list_archive_url":null,"date":"2022-12-07T17:59:19","name":"[COMMITTED] PowerPC: Add support for RFC02656 - Enhanced Load Store, with Length Instructions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9e57c8dc-481b-82d3-7bba-8e7bd9426a1f@linux.ibm.com/mbox/"},{"id":30973,"url":"https://patchwork.plctlab.org/api/1.2/patches/30973/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a1b16cc6-6e73-7d5f-ff38-564b0978243b@linux.ibm.com/","msgid":"","list_archive_url":null,"date":"2022-12-07T18:08:00","name":"[COMMITTED] PowerPC: Add support for RFC02655 - Saturating Subtract Instruction","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a1b16cc6-6e73-7d5f-ff38-564b0978243b@linux.ibm.com/mbox/"},{"id":31010,"url":"https://patchwork.plctlab.org/api/1.2/patches/31010/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221207195222.1182788-2-indu.bhagat@oracle.com/","msgid":"<20221207195222.1182788-2-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-12-07T19:52:17","name":"[1/6] libsframe: minor formatting nits","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221207195222.1182788-2-indu.bhagat@oracle.com/mbox/"},{"id":31011,"url":"https://patchwork.plctlab.org/api/1.2/patches/31011/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221207195222.1182788-3-indu.bhagat@oracle.com/","msgid":"<20221207195222.1182788-3-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-12-07T19:52:18","name":"[2/6] sframe.h: make some macros more precise","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221207195222.1182788-3-indu.bhagat@oracle.com/mbox/"},{"id":31013,"url":"https://patchwork.plctlab.org/api/1.2/patches/31013/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221207195222.1182788-4-indu.bhagat@oracle.com/","msgid":"<20221207195222.1182788-4-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-12-07T19:52:19","name":"[3/6] sframe: gas: libsframe: define constants and remove magic numbers","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221207195222.1182788-4-indu.bhagat@oracle.com/mbox/"},{"id":31012,"url":"https://patchwork.plctlab.org/api/1.2/patches/31012/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221207195222.1182788-5-indu.bhagat@oracle.com/","msgid":"<20221207195222.1182788-5-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-12-07T19:52:20","name":"[4/6] gas: sframe: fine tune the fragment fixup for SFrame func info","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221207195222.1182788-5-indu.bhagat@oracle.com/mbox/"},{"id":31014,"url":"https://patchwork.plctlab.org/api/1.2/patches/31014/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221207195222.1182788-6-indu.bhagat@oracle.com/","msgid":"<20221207195222.1182788-6-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-12-07T19:52:21","name":"[5/6] libsframe: rename API sframe_fde_func_info to sframe_fde_create_func_info","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221207195222.1182788-6-indu.bhagat@oracle.com/mbox/"},{"id":31015,"url":"https://patchwork.plctlab.org/api/1.2/patches/31015/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221207195222.1182788-7-indu.bhagat@oracle.com/","msgid":"<20221207195222.1182788-7-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-12-07T19:52:22","name":"[6/6] objdump: sframe: fix memory leaks","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221207195222.1182788-7-indu.bhagat@oracle.com/mbox/"},{"id":31198,"url":"https://patchwork.plctlab.org/api/1.2/patches/31198/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/aa0c1392-c3e1-53c4-45ce-4cee9af3b243@suse.cz/","msgid":"","list_archive_url":null,"date":"2022-12-08T08:21:54","name":"ld, gold: remove support for -z bndplt (MPX prefix)","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/aa0c1392-c3e1-53c4-45ce-4cee9af3b243@suse.cz/mbox/"},{"id":31490,"url":"https://patchwork.plctlab.org/api/1.2/patches/31490/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221208202649.2852852-1-indu.bhagat@oracle.com/","msgid":"<20221208202649.2852852-1-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-12-08T20:26:49","name":"[V2,2/6] sframe.h: make some macros more precise","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221208202649.2852852-1-indu.bhagat@oracle.com/mbox/"},{"id":31571,"url":"https://patchwork.plctlab.org/api/1.2/patches/31571/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221209015240.6348-1-mark@harmstone.com/","msgid":"<20221209015240.6348-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-12-09T01:52:31","name":"[01/10] ld: Generate PDB string table","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221209015240.6348-1-mark@harmstone.com/mbox/"},{"id":31572,"url":"https://patchwork.plctlab.org/api/1.2/patches/31572/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221209015240.6348-2-mark@harmstone.com/","msgid":"<20221209015240.6348-2-mark@harmstone.com>","list_archive_url":null,"date":"2022-12-09T01:52:32","name":"[02/10] ld: Write DEBUG_S_FILECHKSMS entries in PDBs","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221209015240.6348-2-mark@harmstone.com/mbox/"},{"id":31570,"url":"https://patchwork.plctlab.org/api/1.2/patches/31570/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221209015240.6348-3-mark@harmstone.com/","msgid":"<20221209015240.6348-3-mark@harmstone.com>","list_archive_url":null,"date":"2022-12-09T01:52:33","name":"[03/10] ld: Fix segfault in populate_publics_stream","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221209015240.6348-3-mark@harmstone.com/mbox/"},{"id":31573,"url":"https://patchwork.plctlab.org/api/1.2/patches/31573/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221209015240.6348-4-mark@harmstone.com/","msgid":"<20221209015240.6348-4-mark@harmstone.com>","list_archive_url":null,"date":"2022-12-09T01:52:34","name":"[04/10] ld: Write DEBUG_S_LINES entries in PDB file","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221209015240.6348-4-mark@harmstone.com/mbox/"},{"id":31584,"url":"https://patchwork.plctlab.org/api/1.2/patches/31584/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221209015240.6348-5-mark@harmstone.com/","msgid":"<20221209015240.6348-5-mark@harmstone.com>","list_archive_url":null,"date":"2022-12-09T01:52:35","name":"[05/10] ld: Write types into TPI stream of PDB","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221209015240.6348-5-mark@harmstone.com/mbox/"},{"id":31580,"url":"https://patchwork.plctlab.org/api/1.2/patches/31580/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221209015240.6348-6-mark@harmstone.com/","msgid":"<20221209015240.6348-6-mark@harmstone.com>","list_archive_url":null,"date":"2022-12-09T01:52:36","name":"[06/10] ld: Write types into IPI stream of PDB","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221209015240.6348-6-mark@harmstone.com/mbox/"},{"id":31579,"url":"https://patchwork.plctlab.org/api/1.2/patches/31579/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221209015240.6348-7-mark@harmstone.com/","msgid":"<20221209015240.6348-7-mark@harmstone.com>","list_archive_url":null,"date":"2022-12-09T01:52:37","name":"[07/10] ld: Parse LF_UDT_SRC_LINE records when creating PDB file","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221209015240.6348-7-mark@harmstone.com/mbox/"},{"id":31591,"url":"https://patchwork.plctlab.org/api/1.2/patches/31591/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221209015240.6348-8-mark@harmstone.com/","msgid":"<20221209015240.6348-8-mark@harmstone.com>","list_archive_url":null,"date":"2022-12-09T01:52:38","name":"[08/10] ld: Write globals stream in PDB","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221209015240.6348-8-mark@harmstone.com/mbox/"},{"id":31582,"url":"https://patchwork.plctlab.org/api/1.2/patches/31582/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221209015240.6348-9-mark@harmstone.com/","msgid":"<20221209015240.6348-9-mark@harmstone.com>","list_archive_url":null,"date":"2022-12-09T01:52:39","name":"[09/10] ld: Copy other symbols into PDB file","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221209015240.6348-9-mark@harmstone.com/mbox/"},{"id":31592,"url":"https://patchwork.plctlab.org/api/1.2/patches/31592/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221209015240.6348-10-mark@harmstone.com/","msgid":"<20221209015240.6348-10-mark@harmstone.com>","list_archive_url":null,"date":"2022-12-09T01:52:40","name":"[10/10] ld: Write linker symbols in PDB","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221209015240.6348-10-mark@harmstone.com/mbox/"},{"id":31705,"url":"https://patchwork.plctlab.org/api/1.2/patches/31705/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221209095719.193008-1-i.swmail@xen0n.name/","msgid":"<20221209095719.193008-1-i.swmail@xen0n.name>","list_archive_url":null,"date":"2022-12-09T09:57:19","name":"LoongArch: support disassembling certain pseudo-instructions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221209095719.193008-1-i.swmail@xen0n.name/mbox/"},{"id":31717,"url":"https://patchwork.plctlab.org/api/1.2/patches/31717/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b291b099-c0f2-e206-4296-1fcf040c32b1@suse.com/","msgid":"","list_archive_url":null,"date":"2022-12-09T10:49:20","name":"[v2,1/2] Arm: avoid unhelpful uses of .macro in testsuite","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b291b099-c0f2-e206-4296-1fcf040c32b1@suse.com/mbox/"},{"id":31720,"url":"https://patchwork.plctlab.org/api/1.2/patches/31720/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8eff1de6-871d-24cc-8804-9af7da0a86cf@suse.com/","msgid":"<8eff1de6-871d-24cc-8804-9af7da0a86cf@suse.com>","list_archive_url":null,"date":"2022-12-09T10:52:06","name":"[v2,2/2] gas: re-work line number tracking for macros and their expansions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8eff1de6-871d-24cc-8804-9af7da0a86cf@suse.com/mbox/"},{"id":31724,"url":"https://patchwork.plctlab.org/api/1.2/patches/31724/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y5MXFFPorfWbzTDZ@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-12-09T11:08:04","name":"PR28306, segfault in _bfd_mips_elf_reloc_unshuffle","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y5MXFFPorfWbzTDZ@squeak.grove.modra.org/mbox/"},{"id":31924,"url":"https://patchwork.plctlab.org/api/1.2/patches/31924/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221209202118.4106688-2-indu.bhagat@oracle.com/","msgid":"<20221209202118.4106688-2-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-12-09T20:21:17","name":"[1/2] libctf: remove unnecessary zlib constructs","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221209202118.4106688-2-indu.bhagat@oracle.com/mbox/"},{"id":31925,"url":"https://patchwork.plctlab.org/api/1.2/patches/31925/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221209202118.4106688-3-indu.bhagat@oracle.com/","msgid":"<20221209202118.4106688-3-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-12-09T20:21:18","name":"[2/2] libctf: remove AC_CONFIG_MACRO_DIR","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221209202118.4106688-3-indu.bhagat@oracle.com/mbox/"},{"id":32115,"url":"https://patchwork.plctlab.org/api/1.2/patches/32115/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221211001022.564137-2-indu.bhagat@oracle.com/","msgid":"<20221211001022.564137-2-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-12-11T00:10:21","name":"[V2,1/2] libctf: remove unnecessary zlib constructs","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221211001022.564137-2-indu.bhagat@oracle.com/mbox/"},{"id":32114,"url":"https://patchwork.plctlab.org/api/1.2/patches/32114/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221211001022.564137-3-indu.bhagat@oracle.com/","msgid":"<20221211001022.564137-3-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-12-11T00:10:22","name":"[V2,2/2] libctf: remove AC_CONFIG_MACRO_DIR","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221211001022.564137-3-indu.bhagat@oracle.com/mbox/"},{"id":32116,"url":"https://patchwork.plctlab.org/api/1.2/patches/32116/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221211002622.564875-1-indu.bhagat@oracle.com/","msgid":"<20221211002622.564875-1-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-12-11T00:26:22","name":"libctf: remove unnecessary zstd constructs","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221211002622.564875-1-indu.bhagat@oracle.com/mbox/"},{"id":32188,"url":"https://patchwork.plctlab.org/api/1.2/patches/32188/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y5XZZileMxvCEgnH@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-12-11T13:21:42","name":"PR29870, objdump SEGV in display_debug_lines_decoded dwarf.c:5524","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y5XZZileMxvCEgnH@squeak.grove.modra.org/mbox/"},{"id":32268,"url":"https://patchwork.plctlab.org/api/1.2/patches/32268/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y5btF1SICJIaR6s4@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-12-12T08:57:59","name":"PR29872, uninitialised value in display_debug_lines_decoded dwarf.c:5413","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y5btF1SICJIaR6s4@squeak.grove.modra.org/mbox/"},{"id":32269,"url":"https://patchwork.plctlab.org/api/1.2/patches/32269/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y5btNpE+vZlCyuFQ@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-12-12T08:58:30","name":"Lack of bounds checking in vms-alpha.c parse_module","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y5btNpE+vZlCyuFQ@squeak.grove.modra.org/mbox/"},{"id":32270,"url":"https://patchwork.plctlab.org/api/1.2/patches/32270/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y5btWGqMk2HBW0DG@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-12-12T08:59:04","name":"PR29892, Field file_table of struct module is uninitialized","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y5btWGqMk2HBW0DG@squeak.grove.modra.org/mbox/"},{"id":32366,"url":"https://patchwork.plctlab.org/api/1.2/patches/32366/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4a972040-5bdf-4c00-47db-7e26e603ff47@suse.com/","msgid":"<4a972040-5bdf-4c00-47db-7e26e603ff47@suse.com>","list_archive_url":null,"date":"2022-12-12T12:42:31","name":"x86: revert disassembler parts of \"x86: Allow 16-bit register source for LAR and LSL\"","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4a972040-5bdf-4c00-47db-7e26e603ff47@suse.com/mbox/"},{"id":32384,"url":"https://patchwork.plctlab.org/api/1.2/patches/32384/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2e6ab22e-9141-7209-5dcd-f10f2e20b0f0@suse.com/","msgid":"<2e6ab22e-9141-7209-5dcd-f10f2e20b0f0@suse.com>","list_archive_url":null,"date":"2022-12-12T13:12:43","name":"[1/2] x86: change representation of extension opcode","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2e6ab22e-9141-7209-5dcd-f10f2e20b0f0@suse.com/mbox/"},{"id":32387,"url":"https://patchwork.plctlab.org/api/1.2/patches/32387/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/90f8b494-64b2-fd9a-6b19-ded5f185ddd1@suse.com/","msgid":"<90f8b494-64b2-fd9a-6b19-ded5f185ddd1@suse.com>","list_archive_url":null,"date":"2022-12-12T13:14:13","name":"[2/2] x86: omit Cpu prefixes from opcode table","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/90f8b494-64b2-fd9a-6b19-ded5f185ddd1@suse.com/mbox/"},{"id":32407,"url":"https://patchwork.plctlab.org/api/1.2/patches/32407/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y5c2J0s2fgqvL61d@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-12-12T14:09:43","name":"PR29893, buffer overflow in display_debug_addr","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y5c2J0s2fgqvL61d@squeak.grove.modra.org/mbox/"},{"id":32596,"url":"https://patchwork.plctlab.org/api/1.2/patches/32596/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y5fj/uw/pAKASueh@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-12-13T02:31:26","name":"asan: mips_hi16_list segfault in bfd_get_section_limit_octets","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y5fj/uw/pAKASueh@squeak.grove.modra.org/mbox/"},{"id":32623,"url":"https://patchwork.plctlab.org/api/1.2/patches/32623/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221213043428.33155-1-xuli1@eswincomputing.com/","msgid":"<20221213043428.33155-1-xuli1@eswincomputing.com>","list_archive_url":null,"date":"2022-12-13T04:34:28","name":"RISC-V: Add string length check for operands in AS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221213043428.33155-1-xuli1@eswincomputing.com/mbox/"},{"id":32656,"url":"https://patchwork.plctlab.org/api/1.2/patches/32656/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221213065851.2777297-2-mengqinggang@loongson.cn/","msgid":"<20221213065851.2777297-2-mengqinggang@loongson.cn>","list_archive_url":null,"date":"2022-12-13T06:58:46","name":"[v2,1/6] LoongArch: include: Add support for linker relaxation.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221213065851.2777297-2-mengqinggang@loongson.cn/mbox/"},{"id":32660,"url":"https://patchwork.plctlab.org/api/1.2/patches/32660/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221213065851.2777297-3-mengqinggang@loongson.cn/","msgid":"<20221213065851.2777297-3-mengqinggang@loongson.cn>","list_archive_url":null,"date":"2022-12-13T06:58:47","name":"[v2,2/6] LoongArch: bfd: Add support for linker relaxation.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221213065851.2777297-3-mengqinggang@loongson.cn/mbox/"},{"id":32657,"url":"https://patchwork.plctlab.org/api/1.2/patches/32657/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221213065851.2777297-4-mengqinggang@loongson.cn/","msgid":"<20221213065851.2777297-4-mengqinggang@loongson.cn>","list_archive_url":null,"date":"2022-12-13T06:58:48","name":"[v2,3/6] LoongArch: opcodes: Add support for linker relaxation.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221213065851.2777297-4-mengqinggang@loongson.cn/mbox/"},{"id":32661,"url":"https://patchwork.plctlab.org/api/1.2/patches/32661/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221213065851.2777297-5-mengqinggang@loongson.cn/","msgid":"<20221213065851.2777297-5-mengqinggang@loongson.cn>","list_archive_url":null,"date":"2022-12-13T06:58:49","name":"[v2,4/6] LoongArch: binutils: Add support for linker relaxation.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221213065851.2777297-5-mengqinggang@loongson.cn/mbox/"},{"id":32659,"url":"https://patchwork.plctlab.org/api/1.2/patches/32659/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221213065851.2777297-6-mengqinggang@loongson.cn/","msgid":"<20221213065851.2777297-6-mengqinggang@loongson.cn>","list_archive_url":null,"date":"2022-12-13T06:58:50","name":"[v2,5/6] LoongArch: gas: Add support for linker relaxation.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221213065851.2777297-6-mengqinggang@loongson.cn/mbox/"},{"id":32658,"url":"https://patchwork.plctlab.org/api/1.2/patches/32658/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221213065851.2777297-7-mengqinggang@loongson.cn/","msgid":"<20221213065851.2777297-7-mengqinggang@loongson.cn>","list_archive_url":null,"date":"2022-12-13T06:58:51","name":"[v2,6/6] LoongArch: ld: Add support for linker relaxation.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221213065851.2777297-7-mengqinggang@loongson.cn/mbox/"},{"id":32855,"url":"https://patchwork.plctlab.org/api/1.2/patches/32855/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0adeda5c-0696-d3bf-499a-fd63e3a4f709@suse.com/","msgid":"<0adeda5c-0696-d3bf-499a-fd63e3a4f709@suse.com>","list_archive_url":null,"date":"2022-12-13T15:31:27","name":"Arm: break gas dependency on libopcodes","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0adeda5c-0696-d3bf-499a-fd63e3a4f709@suse.com/mbox/"},{"id":33035,"url":"https://patchwork.plctlab.org/api/1.2/patches/33035/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y5lEcMxUdytmdyC6@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-12-14T03:35:12","name":"Don'\''t access freed memory printing objcopy warning","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y5lEcMxUdytmdyC6@squeak.grove.modra.org/mbox/"},{"id":33036,"url":"https://patchwork.plctlab.org/api/1.2/patches/33036/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y5lEjrLPqV3l35Qf@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-12-14T03:35:42","name":"asan: signed integer overflow in display_debug_frames","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y5lEjrLPqV3l35Qf@squeak.grove.modra.org/mbox/"},{"id":33054,"url":"https://patchwork.plctlab.org/api/1.2/patches/33054/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221214054700.2889049-2-i.swmail@xen0n.name/","msgid":"<20221214054700.2889049-2-i.swmail@xen0n.name>","list_archive_url":null,"date":"2022-12-14T05:46:55","name":"[v3,1/6] LoongArch: support disassembling certain pseudo-instructions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221214054700.2889049-2-i.swmail@xen0n.name/mbox/"},{"id":33055,"url":"https://patchwork.plctlab.org/api/1.2/patches/33055/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221214054700.2889049-3-i.swmail@xen0n.name/","msgid":"<20221214054700.2889049-3-i.swmail@xen0n.name>","list_archive_url":null,"date":"2022-12-14T05:46:56","name":"[v3,2/6] opcodes/loongarch: remove unused code","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221214054700.2889049-3-i.swmail@xen0n.name/mbox/"},{"id":33057,"url":"https://patchwork.plctlab.org/api/1.2/patches/33057/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221214054700.2889049-4-i.swmail@xen0n.name/","msgid":"<20221214054700.2889049-4-i.swmail@xen0n.name>","list_archive_url":null,"date":"2022-12-14T05:46:57","name":"[v3,3/6] opcodes/loongarch: implement style support in the disassembler","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221214054700.2889049-4-i.swmail@xen0n.name/mbox/"},{"id":33058,"url":"https://patchwork.plctlab.org/api/1.2/patches/33058/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221214054700.2889049-5-i.swmail@xen0n.name/","msgid":"<20221214054700.2889049-5-i.swmail@xen0n.name>","list_archive_url":null,"date":"2022-12-14T05:46:58","name":"[v3,4/6] opcodes/loongarch: style disassembled address offsets as such","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221214054700.2889049-5-i.swmail@xen0n.name/mbox/"},{"id":33059,"url":"https://patchwork.plctlab.org/api/1.2/patches/33059/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221214054700.2889049-6-i.swmail@xen0n.name/","msgid":"<20221214054700.2889049-6-i.swmail@xen0n.name>","list_archive_url":null,"date":"2022-12-14T05:46:59","name":"[v3,5/6] opcodes/loongarch: do not print hex notation for signed immediates","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221214054700.2889049-6-i.swmail@xen0n.name/mbox/"},{"id":33056,"url":"https://patchwork.plctlab.org/api/1.2/patches/33056/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221214054700.2889049-7-i.swmail@xen0n.name/","msgid":"<20221214054700.2889049-7-i.swmail@xen0n.name>","list_archive_url":null,"date":"2022-12-14T05:47:00","name":"[v3,6/6] opcodes/loongarch: print unrecognized insn words with the .word directive","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221214054700.2889049-7-i.swmail@xen0n.name/mbox/"},{"id":33061,"url":"https://patchwork.plctlab.org/api/1.2/patches/33061/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221214055204.2890795-2-i.swmail@xen0n.name/","msgid":"<20221214055204.2890795-2-i.swmail@xen0n.name>","list_archive_url":null,"date":"2022-12-14T05:51:59","name":"[v3,1/6] LoongArch: support disassembling certain pseudo-instructions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221214055204.2890795-2-i.swmail@xen0n.name/mbox/"},{"id":33062,"url":"https://patchwork.plctlab.org/api/1.2/patches/33062/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221214055204.2890795-3-i.swmail@xen0n.name/","msgid":"<20221214055204.2890795-3-i.swmail@xen0n.name>","list_archive_url":null,"date":"2022-12-14T05:52:00","name":"[v3,2/6] opcodes/loongarch: remove unused code","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221214055204.2890795-3-i.swmail@xen0n.name/mbox/"},{"id":33060,"url":"https://patchwork.plctlab.org/api/1.2/patches/33060/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221214055204.2890795-4-i.swmail@xen0n.name/","msgid":"<20221214055204.2890795-4-i.swmail@xen0n.name>","list_archive_url":null,"date":"2022-12-14T05:52:01","name":"[v3,3/6] opcodes/loongarch: implement style support in the disassembler","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221214055204.2890795-4-i.swmail@xen0n.name/mbox/"},{"id":33063,"url":"https://patchwork.plctlab.org/api/1.2/patches/33063/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221214055204.2890795-5-i.swmail@xen0n.name/","msgid":"<20221214055204.2890795-5-i.swmail@xen0n.name>","list_archive_url":null,"date":"2022-12-14T05:52:02","name":"[v3,4/6] opcodes/loongarch: style disassembled address offsets as such","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221214055204.2890795-5-i.swmail@xen0n.name/mbox/"},{"id":33065,"url":"https://patchwork.plctlab.org/api/1.2/patches/33065/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221214055204.2890795-6-i.swmail@xen0n.name/","msgid":"<20221214055204.2890795-6-i.swmail@xen0n.name>","list_archive_url":null,"date":"2022-12-14T05:52:03","name":"[v3,5/6] opcodes/loongarch: do not print hex notation for signed immediates","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221214055204.2890795-6-i.swmail@xen0n.name/mbox/"},{"id":33064,"url":"https://patchwork.plctlab.org/api/1.2/patches/33064/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221214055204.2890795-7-i.swmail@xen0n.name/","msgid":"<20221214055204.2890795-7-i.swmail@xen0n.name>","list_archive_url":null,"date":"2022-12-14T05:52:04","name":"[v3,6/6] opcodes/loongarch: print unrecognized insn words with the .word directive","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221214055204.2890795-7-i.swmail@xen0n.name/mbox/"},{"id":33086,"url":"https://patchwork.plctlab.org/api/1.2/patches/33086/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221214073240.24973-1-xuli1@eswincomputing.com/","msgid":"<20221214073240.24973-1-xuli1@eswincomputing.com>","list_archive_url":null,"date":"2022-12-14T07:32:40","name":"[v2] RISC-V: Add string length check for operands in AS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221214073240.24973-1-xuli1@eswincomputing.com/mbox/"},{"id":33111,"url":"https://patchwork.plctlab.org/api/1.2/patches/33111/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/af826d86-8600-6a8b-f696-0b26c7774d45@suse.com/","msgid":"","list_archive_url":null,"date":"2022-12-14T09:07:07","name":"x86: adjust type checking constructs","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/af826d86-8600-6a8b-f696-0b26c7774d45@suse.com/mbox/"},{"id":33164,"url":"https://patchwork.plctlab.org/api/1.2/patches/33164/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y5m2zCJFXs1Ywa+M@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-12-14T11:43:08","name":"Fix haiku ld dependencies","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y5m2zCJFXs1Ywa+M@squeak.grove.modra.org/mbox/"},{"id":33165,"url":"https://patchwork.plctlab.org/api/1.2/patches/33165/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y5m285CXyYl9DPU6@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-12-14T11:43:47","name":"asan: buffer overflow in sh_reloc","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y5m285CXyYl9DPU6@squeak.grove.modra.org/mbox/"},{"id":33304,"url":"https://patchwork.plctlab.org/api/1.2/patches/33304/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221214195859.1233809-2-indu.bhagat@oracle.com/","msgid":"<20221214195859.1233809-2-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-12-14T19:58:54","name":"[1/6,1/6] sframe.h: add support for .cfi_negate_ra_state","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221214195859.1233809-2-indu.bhagat@oracle.com/mbox/"},{"id":33298,"url":"https://patchwork.plctlab.org/api/1.2/patches/33298/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221214195859.1233809-3-indu.bhagat@oracle.com/","msgid":"<20221214195859.1233809-3-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-12-14T19:58:55","name":"[2/6,2/6] gas: sframe: add support for .cfi_negate_ra_state","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221214195859.1233809-3-indu.bhagat@oracle.com/mbox/"},{"id":33299,"url":"https://patchwork.plctlab.org/api/1.2/patches/33299/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221214195859.1233809-4-indu.bhagat@oracle.com/","msgid":"<20221214195859.1233809-4-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-12-14T19:58:56","name":"[3/6,3/6] gas: sframe: testsuite: add testcase for .cfi_negate_ra_state","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221214195859.1233809-4-indu.bhagat@oracle.com/mbox/"},{"id":33313,"url":"https://patchwork.plctlab.org/api/1.2/patches/33313/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221214195859.1233809-5-indu.bhagat@oracle.com/","msgid":"<20221214195859.1233809-5-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-12-14T19:58:57","name":"[4/6,4/6] libsframe: provide new access API for mangled RA bit","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221214195859.1233809-5-indu.bhagat@oracle.com/mbox/"},{"id":33300,"url":"https://patchwork.plctlab.org/api/1.2/patches/33300/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221214195859.1233809-6-indu.bhagat@oracle.com/","msgid":"<20221214195859.1233809-6-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-12-14T19:58:58","name":"[5/6,5/6] objdump/readelf: sframe: emit marker for FREs with mangled RA","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221214195859.1233809-6-indu.bhagat@oracle.com/mbox/"},{"id":33307,"url":"https://patchwork.plctlab.org/api/1.2/patches/33307/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221214195859.1233809-7-indu.bhagat@oracle.com/","msgid":"<20221214195859.1233809-7-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-12-14T19:58:59","name":"[6/6,6/6] sframe: doc: update spec for the mangled-RA bit in FRE","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221214195859.1233809-7-indu.bhagat@oracle.com/mbox/"},{"id":33329,"url":"https://patchwork.plctlab.org/api/1.2/patches/33329/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221214200756.1234528-2-indu.bhagat@oracle.com/","msgid":"<20221214200756.1234528-2-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-12-14T20:07:52","name":"[1/5,1/5] sframe.h: add support for .cfi_b_key_frame","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221214200756.1234528-2-indu.bhagat@oracle.com/mbox/"},{"id":33336,"url":"https://patchwork.plctlab.org/api/1.2/patches/33336/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221214200756.1234528-3-indu.bhagat@oracle.com/","msgid":"<20221214200756.1234528-3-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-12-14T20:07:53","name":"[2/5,2/5] gas: sframe: add support for .cfi_b_key_frame","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221214200756.1234528-3-indu.bhagat@oracle.com/mbox/"},{"id":33334,"url":"https://patchwork.plctlab.org/api/1.2/patches/33334/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221214200756.1234528-4-indu.bhagat@oracle.com/","msgid":"<20221214200756.1234528-4-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-12-14T20:07:54","name":"[3/5,3/5] objdump/readelf: sframe: emit marker for SFrame FDE with B key","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221214200756.1234528-4-indu.bhagat@oracle.com/mbox/"},{"id":33331,"url":"https://patchwork.plctlab.org/api/1.2/patches/33331/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221214200756.1234528-5-indu.bhagat@oracle.com/","msgid":"<20221214200756.1234528-5-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-12-14T20:07:55","name":"[4/5,4/5] gas: sframe: testsuite: add testcase for .cfi_b_key_frame","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221214200756.1234528-5-indu.bhagat@oracle.com/mbox/"},{"id":33337,"url":"https://patchwork.plctlab.org/api/1.2/patches/33337/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221214200756.1234528-6-indu.bhagat@oracle.com/","msgid":"<20221214200756.1234528-6-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-12-14T20:07:56","name":"[5/5,5/5] sframe: doc: update documentation for pauth key in SFrame FDE","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221214200756.1234528-6-indu.bhagat@oracle.com/mbox/"},{"id":33412,"url":"https://patchwork.plctlab.org/api/1.2/patches/33412/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221214234310.1247719-1-indu.bhagat@oracle.com/","msgid":"<20221214234310.1247719-1-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-12-14T23:43:10","name":"[PR,29856] libsframe: avoid generating misaligned loads","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221214234310.1247719-1-indu.bhagat@oracle.com/mbox/"},{"id":33669,"url":"https://patchwork.plctlab.org/api/1.2/patches/33669/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/15b35aca-4b74-63ff-b6e9-831879fa7cfa@suse.com/","msgid":"<15b35aca-4b74-63ff-b6e9-831879fa7cfa@suse.com>","list_archive_url":null,"date":"2022-12-15T15:14:57","name":"gas: restore Dwarf info generation after macro diagnostic adjustments","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/15b35aca-4b74-63ff-b6e9-831879fa7cfa@suse.com/mbox/"},{"id":33836,"url":"https://patchwork.plctlab.org/api/1.2/patches/33836/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221216021400.22309-1-mark@harmstone.com/","msgid":"<20221216021400.22309-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-12-16T02:13:56","name":"[1/5] Fix size of external_reloc for pe-aarch64","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221216021400.22309-1-mark@harmstone.com/mbox/"},{"id":33839,"url":"https://patchwork.plctlab.org/api/1.2/patches/33839/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221216021400.22309-2-mark@harmstone.com/","msgid":"<20221216021400.22309-2-mark@harmstone.com>","list_archive_url":null,"date":"2022-12-16T02:13:57","name":"[2/5] Skip ELF-specific tests when targeting pe-aarch64","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221216021400.22309-2-mark@harmstone.com/mbox/"},{"id":33840,"url":"https://patchwork.plctlab.org/api/1.2/patches/33840/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221216021400.22309-3-mark@harmstone.com/","msgid":"<20221216021400.22309-3-mark@harmstone.com>","list_archive_url":null,"date":"2022-12-16T02:13:58","name":"[3/5] Add pe-aarch64 relocations","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221216021400.22309-3-mark@harmstone.com/mbox/"},{"id":33837,"url":"https://patchwork.plctlab.org/api/1.2/patches/33837/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221216021400.22309-4-mark@harmstone.com/","msgid":"<20221216021400.22309-4-mark@harmstone.com>","list_archive_url":null,"date":"2022-12-16T02:13:59","name":"[4/5] Add .secrel32 for pe-aarch64","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221216021400.22309-4-mark@harmstone.com/mbox/"},{"id":33838,"url":"https://patchwork.plctlab.org/api/1.2/patches/33838/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221216021400.22309-5-mark@harmstone.com/","msgid":"<20221216021400.22309-5-mark@harmstone.com>","list_archive_url":null,"date":"2022-12-16T02:14:00","name":"[5/5] Add aarch64-w64-mingw32 target","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221216021400.22309-5-mark@harmstone.com/mbox/"},{"id":33885,"url":"https://patchwork.plctlab.org/api/1.2/patches/33885/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221216072336.1087469-2-mengqinggang@loongson.cn/","msgid":"<20221216072336.1087469-2-mengqinggang@loongson.cn>","list_archive_url":null,"date":"2022-12-16T07:23:31","name":"[v3,1/6] LoongArch: include: Add support for linker relaxation.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221216072336.1087469-2-mengqinggang@loongson.cn/mbox/"},{"id":33886,"url":"https://patchwork.plctlab.org/api/1.2/patches/33886/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221216072336.1087469-3-mengqinggang@loongson.cn/","msgid":"<20221216072336.1087469-3-mengqinggang@loongson.cn>","list_archive_url":null,"date":"2022-12-16T07:23:32","name":"[v3,2/6] LoongArch: bfd: Add support for linker relaxation.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221216072336.1087469-3-mengqinggang@loongson.cn/mbox/"},{"id":33888,"url":"https://patchwork.plctlab.org/api/1.2/patches/33888/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221216072336.1087469-4-mengqinggang@loongson.cn/","msgid":"<20221216072336.1087469-4-mengqinggang@loongson.cn>","list_archive_url":null,"date":"2022-12-16T07:23:33","name":"[v3,3/6] LoongArch: opcodes: Add support for linker relaxation.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221216072336.1087469-4-mengqinggang@loongson.cn/mbox/"},{"id":33889,"url":"https://patchwork.plctlab.org/api/1.2/patches/33889/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221216072336.1087469-5-mengqinggang@loongson.cn/","msgid":"<20221216072336.1087469-5-mengqinggang@loongson.cn>","list_archive_url":null,"date":"2022-12-16T07:23:34","name":"[v3,4/6] LoongArch: binutils: Add support for linker relaxation.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221216072336.1087469-5-mengqinggang@loongson.cn/mbox/"},{"id":33887,"url":"https://patchwork.plctlab.org/api/1.2/patches/33887/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221216072336.1087469-6-mengqinggang@loongson.cn/","msgid":"<20221216072336.1087469-6-mengqinggang@loongson.cn>","list_archive_url":null,"date":"2022-12-16T07:23:35","name":"[v3,5/6] LoongArch: gas: Add support for linker relaxation.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221216072336.1087469-6-mengqinggang@loongson.cn/mbox/"},{"id":33890,"url":"https://patchwork.plctlab.org/api/1.2/patches/33890/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221216072336.1087469-7-mengqinggang@loongson.cn/","msgid":"<20221216072336.1087469-7-mengqinggang@loongson.cn>","list_archive_url":null,"date":"2022-12-16T07:23:36","name":"[v3,6/6] LoongArch: ld: Add support for linker relaxation.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221216072336.1087469-7-mengqinggang@loongson.cn/mbox/"},{"id":33895,"url":"https://patchwork.plctlab.org/api/1.2/patches/33895/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/98057a7f-d166-1940-f00f-d9c5d912328d@suse.com/","msgid":"<98057a7f-d166-1940-f00f-d9c5d912328d@suse.com>","list_archive_url":null,"date":"2022-12-16T08:07:29","name":"[v2] x86: omit Cpu prefixes from opcode table","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/98057a7f-d166-1940-f00f-d9c5d912328d@suse.com/mbox/"},{"id":33899,"url":"https://patchwork.plctlab.org/api/1.2/patches/33899/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/507f0d3f-c34e-9895-21bf-37525bf0a6fb@suse.com/","msgid":"<507f0d3f-c34e-9895-21bf-37525bf0a6fb@suse.com>","list_archive_url":null,"date":"2022-12-16T08:28:38","name":"[1/4] gprofng/testsuite: adjust linking of synprog","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/507f0d3f-c34e-9895-21bf-37525bf0a6fb@suse.com/mbox/"},{"id":33900,"url":"https://patchwork.plctlab.org/api/1.2/patches/33900/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/67f3d4e3-46dd-e39d-d154-49bf25dbafc8@suse.com/","msgid":"<67f3d4e3-46dd-e39d-d154-49bf25dbafc8@suse.com>","list_archive_url":null,"date":"2022-12-16T08:29:50","name":"[2/4] gprofng/testsuite: correct names for signal handling tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/67f3d4e3-46dd-e39d-d154-49bf25dbafc8@suse.com/mbox/"},{"id":33902,"url":"https://patchwork.plctlab.org/api/1.2/patches/33902/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/240a568e-ab05-b3b5-d004-c1fc6799c66f@suse.com/","msgid":"<240a568e-ab05-b3b5-d004-c1fc6799c66f@suse.com>","list_archive_url":null,"date":"2022-12-16T08:30:10","name":"[3/4] gprofng/testsuite: correct line continuation in endcases.c","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/240a568e-ab05-b3b5-d004-c1fc6799c66f@suse.com/mbox/"},{"id":33903,"url":"https://patchwork.plctlab.org/api/1.2/patches/33903/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f0679195-cfa8-6f87-2519-520f758e615e@suse.com/","msgid":"","list_archive_url":null,"date":"2022-12-16T08:30:30","name":"[4/4] gprofng/testsuite: eliminate bogus casts","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f0679195-cfa8-6f87-2519-520f758e615e@suse.com/mbox/"},{"id":33915,"url":"https://patchwork.plctlab.org/api/1.2/patches/33915/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0acc18cc-d246-9c2a-ba14-586c693b9e58@suse.com/","msgid":"<0acc18cc-d246-9c2a-ba14-586c693b9e58@suse.com>","list_archive_url":null,"date":"2022-12-16T09:13:36","name":"[5/4] gprofng/testsuite: skip Java test without JDK","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0acc18cc-d246-9c2a-ba14-586c693b9e58@suse.com/mbox/"},{"id":33950,"url":"https://patchwork.plctlab.org/api/1.2/patches/33950/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221216132541.45791-2-nick.alcock@oracle.com/","msgid":"<20221216132541.45791-2-nick.alcock@oracle.com>","list_archive_url":null,"date":"2022-12-16T13:25:38","name":"[1/4] ctf: fix various dreadful typos in the ctf_archive format comments","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221216132541.45791-2-nick.alcock@oracle.com/mbox/"},{"id":33951,"url":"https://patchwork.plctlab.org/api/1.2/patches/33951/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221216132541.45791-3-nick.alcock@oracle.com/","msgid":"<20221216132541.45791-3-nick.alcock@oracle.com>","list_archive_url":null,"date":"2022-12-16T13:25:39","name":"[2/4] libtool.m4: adjust kludge for ignoring syntax errors","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221216132541.45791-3-nick.alcock@oracle.com/mbox/"},{"id":33952,"url":"https://patchwork.plctlab.org/api/1.2/patches/33952/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221216132541.45791-4-nick.alcock@oracle.com/","msgid":"<20221216132541.45791-4-nick.alcock@oracle.com>","list_archive_url":null,"date":"2022-12-16T13:25:40","name":"[3/4] Regenerate affected configures.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221216132541.45791-4-nick.alcock@oracle.com/mbox/"},{"id":33953,"url":"https://patchwork.plctlab.org/api/1.2/patches/33953/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221216132541.45791-5-nick.alcock@oracle.com/","msgid":"<20221216132541.45791-5-nick.alcock@oracle.com>","list_archive_url":null,"date":"2022-12-16T13:25:41","name":"[4/4] libctf: skip the testsuite from inside dejagnu","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221216132541.45791-5-nick.alcock@oracle.com/mbox/"},{"id":34050,"url":"https://patchwork.plctlab.org/api/1.2/patches/34050/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221216185133.1342022-1-christoph.muellner@vrull.eu/","msgid":"<20221216185133.1342022-1-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2022-12-16T18:51:33","name":"RISC-V: Fix T-Head Fmv vendor extension encoding","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221216185133.1342022-1-christoph.muellner@vrull.eu/mbox/"},{"id":34093,"url":"https://patchwork.plctlab.org/api/1.2/patches/34093/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221216214310.13155-1-prabhakar.mahadev-lad.rj@bp.renesas.com/","msgid":"<20221216214310.13155-1-prabhakar.mahadev-lad.rj@bp.renesas.com>","list_archive_url":null,"date":"2022-12-16T21:43:10","name":"[RFC] ld/emulparams: elf32lriscv-defs: Add support tune the text segment start address","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221216214310.13155-1-prabhakar.mahadev-lad.rj@bp.renesas.com/mbox/"},{"id":34193,"url":"https://patchwork.plctlab.org/api/1.2/patches/34193/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221217064128.11326-2-indu.bhagat@oracle.com/","msgid":"<20221217064128.11326-2-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-12-17T06:41:23","name":"[COMMITTED,V2,1/6] sframe.h: add support for .cfi_negate_ra_state","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221217064128.11326-2-indu.bhagat@oracle.com/mbox/"},{"id":34188,"url":"https://patchwork.plctlab.org/api/1.2/patches/34188/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221217064128.11326-3-indu.bhagat@oracle.com/","msgid":"<20221217064128.11326-3-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-12-17T06:41:24","name":"[COMMITTED,V2,2/6] gas: sframe: add support for .cfi_negate_ra_state","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221217064128.11326-3-indu.bhagat@oracle.com/mbox/"},{"id":34187,"url":"https://patchwork.plctlab.org/api/1.2/patches/34187/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221217064128.11326-4-indu.bhagat@oracle.com/","msgid":"<20221217064128.11326-4-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-12-17T06:41:25","name":"[COMMITTED,V2,3/6] libsframe: provide new access API for mangled RA bit","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221217064128.11326-4-indu.bhagat@oracle.com/mbox/"},{"id":34189,"url":"https://patchwork.plctlab.org/api/1.2/patches/34189/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221217064128.11326-5-indu.bhagat@oracle.com/","msgid":"<20221217064128.11326-5-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-12-17T06:41:26","name":"[COMMITTED,V2,4/6] objdump/readelf: sframe: emit marker for FREs with mangled RA","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221217064128.11326-5-indu.bhagat@oracle.com/mbox/"},{"id":34195,"url":"https://patchwork.plctlab.org/api/1.2/patches/34195/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221217064128.11326-6-indu.bhagat@oracle.com/","msgid":"<20221217064128.11326-6-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-12-17T06:41:27","name":"[COMMITTED,V2,5/6] gas: sframe: testsuite: add testcase for .cfi_negate_ra_state","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221217064128.11326-6-indu.bhagat@oracle.com/mbox/"},{"id":34196,"url":"https://patchwork.plctlab.org/api/1.2/patches/34196/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221217064128.11326-7-indu.bhagat@oracle.com/","msgid":"<20221217064128.11326-7-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-12-17T06:41:28","name":"[COMMITTED,V2,6/6] sframe: doc: update spec for the mangled-RA bit in FRE","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221217064128.11326-7-indu.bhagat@oracle.com/mbox/"},{"id":34198,"url":"https://patchwork.plctlab.org/api/1.2/patches/34198/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y516F5Mqq4AgLz0T@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-12-17T08:13:11","name":"asan: elf.c:12621:18: applying zero offset to null pointer","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y516F5Mqq4AgLz0T@squeak.grove.modra.org/mbox/"},{"id":34199,"url":"https://patchwork.plctlab.org/api/1.2/patches/34199/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y516VfGAggasKzZE@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-12-17T08:14:13","name":"bfd_get_relocated_section_contents allow NULL data buffer","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y516VfGAggasKzZE@squeak.grove.modra.org/mbox/"},{"id":34204,"url":"https://patchwork.plctlab.org/api/1.2/patches/34204/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221217102842.3645997-1-torbjorn.svensson@foss.st.com/","msgid":"<20221217102842.3645997-1-torbjorn.svensson@foss.st.com>","list_archive_url":null,"date":"2022-12-17T10:28:42","name":"bfd: Discard region regardless of warning flag","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221217102842.3645997-1-torbjorn.svensson@foss.st.com/mbox/"},{"id":34302,"url":"https://patchwork.plctlab.org/api/1.2/patches/34302/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y57nSbf16Gc0Cm7u@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-12-18T10:11:21","name":"ld bootstrap test in build dir with path containing symlinks","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y57nSbf16Gc0Cm7u@squeak.grove.modra.org/mbox/"},{"id":34303,"url":"https://patchwork.plctlab.org/api/1.2/patches/34303/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y57nfEDqt/784poP@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-12-18T10:12:12","name":"Comment bfd_get_section_limit_octets and bfd_get_section_alloc_size","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y57nfEDqt/784poP@squeak.grove.modra.org/mbox/"},{"id":34459,"url":"https://patchwork.plctlab.org/api/1.2/patches/34459/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221219090346.213013-1-vladimir.mezentsev@oracle.com/","msgid":"<20221219090346.213013-1-vladimir.mezentsev@oracle.com>","list_archive_url":null,"date":"2022-12-19T09:03:46","name":"gprofng: PR29646 Various warnings","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221219090346.213013-1-vladimir.mezentsev@oracle.com/mbox/"},{"id":34460,"url":"https://patchwork.plctlab.org/api/1.2/patches/34460/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/63033af0-eb22-a8eb-c8cb-f268344c5a14@suse.com/","msgid":"<63033af0-eb22-a8eb-c8cb-f268344c5a14@suse.com>","list_archive_url":null,"date":"2022-12-19T10:44:40","name":"[01/10] x86: re-work ISA extension dependency handling","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/63033af0-eb22-a8eb-c8cb-f268344c5a14@suse.com/mbox/"},{"id":34461,"url":"https://patchwork.plctlab.org/api/1.2/patches/34461/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2cf259b7-9594-ed3f-f3f0-e7a232c03551@suse.com/","msgid":"<2cf259b7-9594-ed3f-f3f0-e7a232c03551@suse.com>","list_archive_url":null,"date":"2022-12-19T10:45:06","name":"[02/10] x86: correct what gets disabled by certain \".arch .no*\"","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2cf259b7-9594-ed3f-f3f0-e7a232c03551@suse.com/mbox/"},{"id":34462,"url":"https://patchwork.plctlab.org/api/1.2/patches/34462/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/141a0a8e-eb9f-f68f-0eb1-92d62e828f9e@suse.com/","msgid":"<141a0a8e-eb9f-f68f-0eb1-92d62e828f9e@suse.com>","list_archive_url":null,"date":"2022-12-19T10:45:36","name":"[03/10] x86: correct SSE dependencies","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/141a0a8e-eb9f-f68f-0eb1-92d62e828f9e@suse.com/mbox/"},{"id":34467,"url":"https://patchwork.plctlab.org/api/1.2/patches/34467/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ae514f08-6ed8-e30a-9077-c9e37d12bd46@suse.com/","msgid":"","list_archive_url":null,"date":"2022-12-19T10:45:55","name":"[04/10] x86: add dependencies on AVX2","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ae514f08-6ed8-e30a-9077-c9e37d12bd46@suse.com/mbox/"},{"id":34468,"url":"https://patchwork.plctlab.org/api/1.2/patches/34468/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0f352a12-4d8a-7658-0104-8537241b6b49@suse.com/","msgid":"<0f352a12-4d8a-7658-0104-8537241b6b49@suse.com>","list_archive_url":null,"date":"2022-12-19T10:46:24","name":"[05/10] x86: rework noavx512-1 testcase","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0f352a12-4d8a-7658-0104-8537241b6b49@suse.com/mbox/"},{"id":34464,"url":"https://patchwork.plctlab.org/api/1.2/patches/34464/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2176ff46-f9e9-19c5-576a-0e69d9d02c15@suse.com/","msgid":"<2176ff46-f9e9-19c5-576a-0e69d9d02c15@suse.com>","list_archive_url":null,"date":"2022-12-19T10:46:50","name":"[06/10] x86: correct dependencies of a few AVX512 sub-features","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2176ff46-f9e9-19c5-576a-0e69d9d02c15@suse.com/mbox/"},{"id":34466,"url":"https://patchwork.plctlab.org/api/1.2/patches/34466/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/70971dfa-e30a-ec90-d797-808ecf674cc5@suse.com/","msgid":"<70971dfa-e30a-ec90-d797-808ecf674cc5@suse.com>","list_archive_url":null,"date":"2022-12-19T10:47:18","name":"[07/10] x86: correct XSAVE* dependencies","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/70971dfa-e30a-ec90-d797-808ecf674cc5@suse.com/mbox/"},{"id":34471,"url":"https://patchwork.plctlab.org/api/1.2/patches/34471/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f29c5510-bc33-b0c3-aa25-27a02ba613ad@suse.com/","msgid":"","list_archive_url":null,"date":"2022-12-19T10:47:44","name":"[08/10] x86: add dependencies on VMX","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f29c5510-bc33-b0c3-aa25-27a02ba613ad@suse.com/mbox/"},{"id":34465,"url":"https://patchwork.plctlab.org/api/1.2/patches/34465/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0a930835-e8b4-40fa-34e5-bc29cde85200@suse.com/","msgid":"<0a930835-e8b4-40fa-34e5-bc29cde85200@suse.com>","list_archive_url":null,"date":"2022-12-19T10:48:11","name":"[09/10] x86: add dependencies on SVME","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0a930835-e8b4-40fa-34e5-bc29cde85200@suse.com/mbox/"},{"id":34472,"url":"https://patchwork.plctlab.org/api/1.2/patches/34472/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1b04fb35-1f99-7353-4e8c-d643e8ffa975@suse.com/","msgid":"<1b04fb35-1f99-7353-4e8c-d643e8ffa975@suse.com>","list_archive_url":null,"date":"2022-12-19T10:48:31","name":"[10/10] x86: correct/improve TSX controls","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1b04fb35-1f99-7353-4e8c-d643e8ffa975@suse.com/mbox/"},{"id":34470,"url":"https://patchwork.plctlab.org/api/1.2/patches/34470/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4a5ff47c-77cf-5ffa-ad7b-c8e0ae54b31c@suse.com/","msgid":"<4a5ff47c-77cf-5ffa-ad7b-c8e0ae54b31c@suse.com>","list_archive_url":null,"date":"2022-12-19T10:50:39","name":"x86: rename CheckRegSize to CheckOperandSize","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4a5ff47c-77cf-5ffa-ad7b-c8e0ae54b31c@suse.com/mbox/"},{"id":34473,"url":"https://patchwork.plctlab.org/api/1.2/patches/34473/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fdbff837-ebd9-7726-351c-1c43c619b4cb@suse.com/","msgid":"","list_archive_url":null,"date":"2022-12-19T10:53:19","name":"gas: re-arrange listing output for .irp and alike","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fdbff837-ebd9-7726-351c-1c43c619b4cb@suse.com/mbox/"},{"id":34476,"url":"https://patchwork.plctlab.org/api/1.2/patches/34476/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/87r0wvsl2q.fsf@redhat.com/","msgid":"<87r0wvsl2q.fsf@redhat.com>","list_archive_url":null,"date":"2022-12-19T11:13:17","name":"Commit: Add more tests for corrupt DWARF data","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/87r0wvsl2q.fsf@redhat.com/mbox/"},{"id":34538,"url":"https://patchwork.plctlab.org/api/1.2/patches/34538/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221219131149.2268979-1-luis.machado@arm.com/","msgid":"<20221219131149.2268979-1-luis.machado@arm.com>","list_archive_url":null,"date":"2022-12-19T13:11:49","name":"[aarch64/sme] binutils: Add new NT_ARM_ZA and NT_ARM_SSVE register set constants","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221219131149.2268979-1-luis.machado@arm.com/mbox/"},{"id":34542,"url":"https://patchwork.plctlab.org/api/1.2/patches/34542/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y6Bmt87TKcG5vugy@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-12-19T13:27:19","name":"Tidy PR29893 and PR29908 fix","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y6Bmt87TKcG5vugy@squeak.grove.modra.org/mbox/"},{"id":34553,"url":"https://patchwork.plctlab.org/api/1.2/patches/34553/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221219135303.116222-2-mpapini@redhat.com/","msgid":"<20221219135303.116222-2-mpapini@redhat.com>","list_archive_url":null,"date":"2022-12-19T13:53:02","name":"[1/2] addr2line: new option -n to add a newline at the end","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221219135303.116222-2-mpapini@redhat.com/mbox/"},{"id":34554,"url":"https://patchwork.plctlab.org/api/1.2/patches/34554/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221219135303.116222-3-mpapini@redhat.com/","msgid":"<20221219135303.116222-3-mpapini@redhat.com>","list_archive_url":null,"date":"2022-12-19T13:53:03","name":"[2/2] addr2line: test to check -n option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221219135303.116222-3-mpapini@redhat.com/mbox/"},{"id":34605,"url":"https://patchwork.plctlab.org/api/1.2/patches/34605/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f8cae085-3ed5-a6ec-cedf-f78d0c4b0ae1@suse.com/","msgid":"","list_archive_url":null,"date":"2022-12-19T15:06:26","name":"gprofng/testsuite: restrict testing to native configurations","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f8cae085-3ed5-a6ec-cedf-f78d0c4b0ae1@suse.com/mbox/"},{"id":34649,"url":"https://patchwork.plctlab.org/api/1.2/patches/34649/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221219164830.394274-1-tromey@adacore.com/","msgid":"<20221219164830.394274-1-tromey@adacore.com>","list_archive_url":null,"date":"2022-12-19T16:48:30","name":"[pushed] Avoid compiler warning in dwarf-do-refresh","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221219164830.394274-1-tromey@adacore.com/mbox/"},{"id":34689,"url":"https://patchwork.plctlab.org/api/1.2/patches/34689/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221219183450.3754890-1-torbjorn.svensson@foss.st.com/","msgid":"<20221219183450.3754890-1-torbjorn.svensson@foss.st.com>","list_archive_url":null,"date":"2022-12-19T18:34:51","name":"[v2] bfd: Discard region regardless of warning flag","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221219183450.3754890-1-torbjorn.svensson@foss.st.com/mbox/"},{"id":34751,"url":"https://patchwork.plctlab.org/api/1.2/patches/34751/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221219202328.1442022-2-indu.bhagat@oracle.com/","msgid":"<20221219202328.1442022-2-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-12-19T20:23:24","name":"[COMMITTED,V2,1/5,1/5] sframe.h: add support for .cfi_b_key_frame","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221219202328.1442022-2-indu.bhagat@oracle.com/mbox/"},{"id":34749,"url":"https://patchwork.plctlab.org/api/1.2/patches/34749/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221219202328.1442022-3-indu.bhagat@oracle.com/","msgid":"<20221219202328.1442022-3-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-12-19T20:23:25","name":"[COMMITTED,V2,2/5,2/5] gas: sframe: add support for .cfi_b_key_frame","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221219202328.1442022-3-indu.bhagat@oracle.com/mbox/"},{"id":34748,"url":"https://patchwork.plctlab.org/api/1.2/patches/34748/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221219202328.1442022-4-indu.bhagat@oracle.com/","msgid":"<20221219202328.1442022-4-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-12-19T20:23:26","name":"[COMMITTED,V2,3/5,3/5] objdump/readelf: sframe: emit marker for SFrame FDE with B key","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221219202328.1442022-4-indu.bhagat@oracle.com/mbox/"},{"id":34752,"url":"https://patchwork.plctlab.org/api/1.2/patches/34752/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221219202328.1442022-5-indu.bhagat@oracle.com/","msgid":"<20221219202328.1442022-5-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-12-19T20:23:27","name":"[COMMITTED,V2,4/5,4/5] gas: sframe: testsuite: add testcase for .cfi_b_key_frame","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221219202328.1442022-5-indu.bhagat@oracle.com/mbox/"},{"id":34750,"url":"https://patchwork.plctlab.org/api/1.2/patches/34750/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221219202328.1442022-6-indu.bhagat@oracle.com/","msgid":"<20221219202328.1442022-6-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-12-19T20:23:28","name":"[COMMITTED,V2,5/5,5/5] sframe: doc: update documentation for pauth key in SFrame FDE","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221219202328.1442022-6-indu.bhagat@oracle.com/mbox/"},{"id":34774,"url":"https://patchwork.plctlab.org/api/1.2/patches/34774/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221219211406.1443750-2-indu.bhagat@oracle.com/","msgid":"<20221219211406.1443750-2-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-12-19T21:14:02","name":"[V2,1/5,1/5] sframe.h: add support for .cfi_b_key_frame","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221219211406.1443750-2-indu.bhagat@oracle.com/mbox/"},{"id":34775,"url":"https://patchwork.plctlab.org/api/1.2/patches/34775/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221219211406.1443750-3-indu.bhagat@oracle.com/","msgid":"<20221219211406.1443750-3-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-12-19T21:14:03","name":"[V2,2/5,2/5] gas: sframe: add support for .cfi_b_key_frame","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221219211406.1443750-3-indu.bhagat@oracle.com/mbox/"},{"id":34776,"url":"https://patchwork.plctlab.org/api/1.2/patches/34776/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221219211406.1443750-4-indu.bhagat@oracle.com/","msgid":"<20221219211406.1443750-4-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-12-19T21:14:04","name":"[V2,3/5,3/5] objdump/readelf: sframe: emit marker for SFrame FDE with B key","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221219211406.1443750-4-indu.bhagat@oracle.com/mbox/"},{"id":34777,"url":"https://patchwork.plctlab.org/api/1.2/patches/34777/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221219211406.1443750-5-indu.bhagat@oracle.com/","msgid":"<20221219211406.1443750-5-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-12-19T21:14:05","name":"[V2,4/5,4/5] gas: sframe: testsuite: add testcase for .cfi_b_key_frame","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221219211406.1443750-5-indu.bhagat@oracle.com/mbox/"},{"id":34778,"url":"https://patchwork.plctlab.org/api/1.2/patches/34778/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221219211406.1443750-6-indu.bhagat@oracle.com/","msgid":"<20221219211406.1443750-6-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-12-19T21:14:06","name":"[V2,5/5,5/5] sframe: doc: update documentation for pauth key in SFrame FDE","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221219211406.1443750-6-indu.bhagat@oracle.com/mbox/"},{"id":34990,"url":"https://patchwork.plctlab.org/api/1.2/patches/34990/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y6FzlOKIrFOjqKVE@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-12-20T08:34:28","name":"PR29915, bfdio.c does not compile with mingw.org'\''s MinGW","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y6FzlOKIrFOjqKVE@squeak.grove.modra.org/mbox/"},{"id":35279,"url":"https://patchwork.plctlab.org/api/1.2/patches/35279/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y6K1tWIKWE+UA7+E@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-12-21T07:28:53","name":"PR29922, SHT_NOBITS section avoids section size sanity check","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y6K1tWIKWE+UA7+E@squeak.grove.modra.org/mbox/"},{"id":35280,"url":"https://patchwork.plctlab.org/api/1.2/patches/35280/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y6K17LKfvNSlmnbB@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-12-21T07:29:48","name":"enable-non-contiguous-regions warnings","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y6K17LKfvNSlmnbB@squeak.grove.modra.org/mbox/"},{"id":35347,"url":"https://patchwork.plctlab.org/api/1.2/patches/35347/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221221120934.45775-1-nelson@rivosinc.com/","msgid":"<20221221120934.45775-1-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-12-21T12:09:34","name":"RISC-V: Relax the order checking for the architecture string.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221221120934.45775-1-nelson@rivosinc.com/mbox/"},{"id":35432,"url":"https://patchwork.plctlab.org/api/1.2/patches/35432/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221221170706.2877188-2-christoph.muellner@vrull.eu/","msgid":"<20221221170706.2877188-2-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2022-12-21T17:07:01","name":"[RFC,1/6] RISC-V: Add Zvkb ISA extension support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221221170706.2877188-2-christoph.muellner@vrull.eu/mbox/"},{"id":35431,"url":"https://patchwork.plctlab.org/api/1.2/patches/35431/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221221170706.2877188-3-christoph.muellner@vrull.eu/","msgid":"<20221221170706.2877188-3-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2022-12-21T17:07:02","name":"[RFC,2/6] RISC-V: Add Zvkg ISA extension support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221221170706.2877188-3-christoph.muellner@vrull.eu/mbox/"},{"id":35434,"url":"https://patchwork.plctlab.org/api/1.2/patches/35434/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221221170706.2877188-4-christoph.muellner@vrull.eu/","msgid":"<20221221170706.2877188-4-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2022-12-21T17:07:03","name":"[RFC,3/6] RISC-V: Add Zvkh[a,b] ISA extension support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221221170706.2877188-4-christoph.muellner@vrull.eu/mbox/"},{"id":35435,"url":"https://patchwork.plctlab.org/api/1.2/patches/35435/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221221170706.2877188-5-christoph.muellner@vrull.eu/","msgid":"<20221221170706.2877188-5-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2022-12-21T17:07:04","name":"[RFC,4/6] RISC-V: Add Zvkn ISA extension support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221221170706.2877188-5-christoph.muellner@vrull.eu/mbox/"},{"id":35433,"url":"https://patchwork.plctlab.org/api/1.2/patches/35433/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221221170706.2877188-6-christoph.muellner@vrull.eu/","msgid":"<20221221170706.2877188-6-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2022-12-21T17:07:05","name":"[RFC,5/6] RISC-V: Add Zvksed ISA extension support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221221170706.2877188-6-christoph.muellner@vrull.eu/mbox/"},{"id":35437,"url":"https://patchwork.plctlab.org/api/1.2/patches/35437/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221221170706.2877188-7-christoph.muellner@vrull.eu/","msgid":"<20221221170706.2877188-7-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2022-12-21T17:07:06","name":"[RFC,6/6] RISC-V: Add Zvksh ISA extension support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221221170706.2877188-7-christoph.muellner@vrull.eu/mbox/"},{"id":35528,"url":"https://patchwork.plctlab.org/api/1.2/patches/35528/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y6N6cNwCN8q5hhHc@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-12-21T21:28:16","name":"PR29925, Memory leak in find_abstract_instance","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y6N6cNwCN8q5hhHc@squeak.grove.modra.org/mbox/"},{"id":35982,"url":"https://patchwork.plctlab.org/api/1.2/patches/35982/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221222225457.1095930-2-indu.bhagat@oracle.com/","msgid":"<20221222225457.1095930-2-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-12-22T22:54:56","name":"[1/2] libsframe: fix a memory leak in sframe_decode","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221222225457.1095930-2-indu.bhagat@oracle.com/mbox/"},{"id":35983,"url":"https://patchwork.plctlab.org/api/1.2/patches/35983/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221222225457.1095930-3-indu.bhagat@oracle.com/","msgid":"<20221222225457.1095930-3-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-12-22T22:54:57","name":"[2/2] libsframe: testsuite: fix memory leaks in testcases","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221222225457.1095930-3-indu.bhagat@oracle.com/mbox/"},{"id":36015,"url":"https://patchwork.plctlab.org/api/1.2/patches/36015/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y6TwpegMSaNdNc48@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-12-23T00:04:53","name":"COFF build-id writes uninitialised data to file","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y6TwpegMSaNdNc48@squeak.grove.modra.org/mbox/"},{"id":36206,"url":"https://patchwork.plctlab.org/api/1.2/patches/36206/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y6WIDO8tOPdLz0+5@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-12-23T10:50:52","name":"pdb build fixes","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y6WIDO8tOPdLz0+5@squeak.grove.modra.org/mbox/"},{"id":36281,"url":"https://patchwork.plctlab.org/api/1.2/patches/36281/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/98617b373993a3c6054b9389cddfde56b9aec7d1.camel@klomp.org/","msgid":"<98617b373993a3c6054b9389cddfde56b9aec7d1.camel@klomp.org>","list_archive_url":null,"date":"2022-12-23T14:22:38","name":"libsframe builder (Was: [PATCH 0/2] libsframe: fix some memory leaks)","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/98617b373993a3c6054b9389cddfde56b9aec7d1.camel@klomp.org/mbox/"},{"id":36442,"url":"https://patchwork.plctlab.org/api/1.2/patches/36442/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221224194012.1889405-1-indu.bhagat@oracle.com/","msgid":"<20221224194012.1889405-1-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-12-24T19:40:12","name":"libsframe: write out SFrame FRE start address correctly","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221224194012.1889405-1-indu.bhagat@oracle.com/mbox/"},{"id":36515,"url":"https://patchwork.plctlab.org/api/1.2/patches/36515/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y6j2+q32Gg+3rSGs@mars/","msgid":"","list_archive_url":null,"date":"2022-12-26T01:20:58","name":"Add support for x86_64-*-gnu-* targets to build x86_64 gnumach/hurd","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y6j2+q32Gg+3rSGs@mars/mbox/"},{"id":36605,"url":"https://patchwork.plctlab.org/api/1.2/patches/36605/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y6mS/HVlwxWvjyo9@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-12-26T12:26:36","name":"bfd/dwarf2.c: allow use of DWARF5 directory entry 0","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y6mS/HVlwxWvjyo9@squeak.grove.modra.org/mbox/"},{"id":36702,"url":"https://patchwork.plctlab.org/api/1.2/patches/36702/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221226204751.23761-1-mark@harmstone.com/","msgid":"<20221226204751.23761-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-12-26T20:47:49","name":"[1/3] ld: Handle extended-length data structures in PDB types","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221226204751.23761-1-mark@harmstone.com/mbox/"},{"id":36701,"url":"https://patchwork.plctlab.org/api/1.2/patches/36701/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221226204751.23761-2-mark@harmstone.com/","msgid":"<20221226204751.23761-2-mark@harmstone.com>","list_archive_url":null,"date":"2022-12-26T20:47:50","name":"[2/3] ld: Handle LF_VFTABLE types in PDBs","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221226204751.23761-2-mark@harmstone.com/mbox/"},{"id":36700,"url":"https://patchwork.plctlab.org/api/1.2/patches/36700/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221226204751.23761-3-mark@harmstone.com/","msgid":"<20221226204751.23761-3-mark@harmstone.com>","list_archive_url":null,"date":"2022-12-26T20:47:51","name":"[3/3] ld/testsuite: Don'\''t add index to sizes in pdb.exp","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221226204751.23761-3-mark@harmstone.com/mbox/"},{"id":36989,"url":"https://patchwork.plctlab.org/api/1.2/patches/36989/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221227194756.448332-1-hjl.tools@gmail.com/","msgid":"<20221227194756.448332-1-hjl.tools@gmail.com>","list_archive_url":null,"date":"2022-12-27T19:47:56","name":"x86-64: Allocate input section memory if needed","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221227194756.448332-1-hjl.tools@gmail.com/mbox/"},{"id":37100,"url":"https://patchwork.plctlab.org/api/1.2/patches/37100/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221228040649.810-1-shihua@iscas.ac.cn/","msgid":"<20221228040649.810-1-shihua@iscas.ac.cn>","list_archive_url":null,"date":"2022-12-28T04:06:49","name":"[RFC] Support RV64-ILP32","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221228040649.810-1-shihua@iscas.ac.cn/mbox/"},{"id":37293,"url":"https://patchwork.plctlab.org/api/1.2/patches/37293/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e6156a39f6be66c559443e890d8a3a9a592e63d6.1672285661.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-12-29T03:51:44","name":"RISC-V: Make T-Head testing pattern more generic","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e6156a39f6be66c559443e890d8a3a9a592e63d6.1672285661.git.research_trasio@irq.a4lg.com/mbox/"},{"id":37294,"url":"https://patchwork.plctlab.org/api/1.2/patches/37294/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c509db05e4f1500736f4de994ed2aede544234d5.1672286099.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-12-29T03:55:05","name":"[1/2] RISC-V: Simplify riscv_csr_address logic on state enable extensions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c509db05e4f1500736f4de994ed2aede544234d5.1672286099.git.research_trasio@irq.a4lg.com/mbox/"},{"id":37295,"url":"https://patchwork.plctlab.org/api/1.2/patches/37295/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e5ff96022a4144e49d9151946a2e6cb2bd7b8419.1672286099.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-12-29T03:55:06","name":"[2/2] RISC-V: Reorder CSR classes related to '\''Ssstateen'\''","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e5ff96022a4144e49d9151946a2e6cb2bd7b8419.1672286099.git.research_trasio@irq.a4lg.com/mbox/"},{"id":37548,"url":"https://patchwork.plctlab.org/api/1.2/patches/37548/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221230024055.31841-1-mark@harmstone.com/","msgid":"<20221230024055.31841-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-12-30T02:40:48","name":"[1/8] ld: Rename aarch64pe emulation target to arm64pe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221230024055.31841-1-mark@harmstone.com/mbox/"},{"id":37549,"url":"https://patchwork.plctlab.org/api/1.2/patches/37549/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221230024055.31841-2-mark@harmstone.com/","msgid":"<20221230024055.31841-2-mark@harmstone.com>","list_archive_url":null,"date":"2022-12-30T02:40:49","name":"[2/8] Fix size of external_reloc for pe-aarch64","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221230024055.31841-2-mark@harmstone.com/mbox/"},{"id":37551,"url":"https://patchwork.plctlab.org/api/1.2/patches/37551/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221230024055.31841-3-mark@harmstone.com/","msgid":"<20221230024055.31841-3-mark@harmstone.com>","list_archive_url":null,"date":"2022-12-30T02:40:50","name":"[3/8] Skip ELF-specific tests when targeting pe-aarch64","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221230024055.31841-3-mark@harmstone.com/mbox/"},{"id":37550,"url":"https://patchwork.plctlab.org/api/1.2/patches/37550/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221230024055.31841-4-mark@harmstone.com/","msgid":"<20221230024055.31841-4-mark@harmstone.com>","list_archive_url":null,"date":"2022-12-30T02:40:51","name":"[4/8] Skip big-obj test for pe-aarch64","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221230024055.31841-4-mark@harmstone.com/mbox/"},{"id":37554,"url":"https://patchwork.plctlab.org/api/1.2/patches/37554/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221230024055.31841-5-mark@harmstone.com/","msgid":"<20221230024055.31841-5-mark@harmstone.com>","list_archive_url":null,"date":"2022-12-30T02:40:52","name":"[5/8] Add pe-aarch64 relocations","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221230024055.31841-5-mark@harmstone.com/mbox/"},{"id":37553,"url":"https://patchwork.plctlab.org/api/1.2/patches/37553/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221230024055.31841-6-mark@harmstone.com/","msgid":"<20221230024055.31841-6-mark@harmstone.com>","list_archive_url":null,"date":"2022-12-30T02:40:53","name":"[6/8] Add .secrel32 for pe-aarch64","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221230024055.31841-6-mark@harmstone.com/mbox/"},{"id":37555,"url":"https://patchwork.plctlab.org/api/1.2/patches/37555/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221230024055.31841-7-mark@harmstone.com/","msgid":"<20221230024055.31841-7-mark@harmstone.com>","list_archive_url":null,"date":"2022-12-30T02:40:54","name":"[7/8] Add aarch64-w64-mingw32 target","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221230024055.31841-7-mark@harmstone.com/mbox/"},{"id":37552,"url":"https://patchwork.plctlab.org/api/1.2/patches/37552/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221230024055.31841-8-mark@harmstone.com/","msgid":"<20221230024055.31841-8-mark@harmstone.com>","list_archive_url":null,"date":"2022-12-30T02:40:55","name":"[8/8] gas: Restore tc_pe_dwarf2_emit_offset for pe-aarch64","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221230024055.31841-8-mark@harmstone.com/mbox/"},{"id":37656,"url":"https://patchwork.plctlab.org/api/1.2/patches/37656/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y67RWv4jQ93m2JzK@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-12-30T11:54:02","name":"PR29948, heap-buffer-overflow in display_debug_lines_decoded","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y67RWv4jQ93m2JzK@squeak.grove.modra.org/mbox/"},{"id":37836,"url":"https://patchwork.plctlab.org/api/1.2/patches/37836/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/87v8lr93ws.fsf@redhat.com/","msgid":"<87v8lr93ws.fsf@redhat.com>","list_archive_url":null,"date":"2022-12-31T12:02:59","name":"Commit: Sync libiberty sources with gcc mainline","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/87v8lr93ws.fsf@redhat.com/mbox/"}],"public":true,"mbox":"https://patchwork.plctlab.org/bundle/patchwork-bot/binutils-gdb_2022-12/mbox/"},{"id":13,"url":"https://patchwork.plctlab.org/api/1.2/bundles/13/","web_url":"https://patchwork.plctlab.org/bundle/patchwork-bot/binutils-gdb_2023-01/","project":{"id":2,"url":"https://patchwork.plctlab.org/api/1.2/projects/2/","name":"binutils-gdb","link_name":"binutils-gdb","list_id":"binutils.sourceware.org","list_email":"binutils@sourceware.org","web_url":"https://github.com/wangliu-iscas/Patchwork-Bundles/blob/main/binutils-gdb.md","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"name":"binutils-gdb_2023-01","owner":{"id":3,"url":"https://patchwork.plctlab.org/api/1.2/users/3/","username":"patchwork-bot","first_name":"","last_name":"","email":"ouuuleilei@gmail.com"},"patches":[{"id":37894,"url":"https://patchwork.plctlab.org/api/1.2/patches/37894/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221231205546.14330-1-mark@harmstone.com/","msgid":"<20221231205546.14330-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-12-31T20:55:46","name":"Avoid unaligned pointer reads in PEP .idata section","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221231205546.14330-1-mark@harmstone.com/mbox/"},{"id":37945,"url":"https://patchwork.plctlab.org/api/1.2/patches/37945/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y7FukAKCvmmsn7pb@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-01-01T11:29:20","name":"Update etc/update-copyright.py","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y7FukAKCvmmsn7pb@squeak.grove.modra.org/mbox/"},{"id":37992,"url":"https://patchwork.plctlab.org/api/1.2/patches/37992/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y7JSKtcK8QTgIQY5@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-01-02T03:40:26","name":"obsolete target tidy","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y7JSKtcK8QTgIQY5@squeak.grove.modra.org/mbox/"},{"id":38142,"url":"https://patchwork.plctlab.org/api/1.2/patches/38142/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230102160857.ABA7F2042C@pchp3.se.axis.com/","msgid":"<20230102160857.ABA7F2042C@pchp3.se.axis.com>","list_archive_url":null,"date":"2023-01-02T16:08:57","name":"Fix ld bloat introduced between binutils-2.38 and 2.39","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230102160857.ABA7F2042C@pchp3.se.axis.com/mbox/"},{"id":38247,"url":"https://patchwork.plctlab.org/api/1.2/patches/38247/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230103024119.12F182042C@pchp3.se.axis.com/","msgid":"<20230103024119.12F182042C@pchp3.se.axis.com>","list_archive_url":null,"date":"2023-01-03T02:41:19","name":"ARM: Fix ld bloat introduced between binutils-2.38 and 2.39","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230103024119.12F182042C@pchp3.se.axis.com/mbox/"},{"id":38355,"url":"https://patchwork.plctlab.org/api/1.2/patches/38355/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230103102251.89478-1-christophe.lyon@arm.com/","msgid":"<20230103102251.89478-1-christophe.lyon@arm.com>","list_archive_url":null,"date":"2023-01-03T10:22:50","name":"[arm] Fix PR18841 ifunc relocation ordering","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230103102251.89478-1-christophe.lyon@arm.com/mbox/"},{"id":38356,"url":"https://patchwork.plctlab.org/api/1.2/patches/38356/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230103102251.89478-2-christophe.lyon@arm.com/","msgid":"<20230103102251.89478-2-christophe.lyon@arm.com>","list_archive_url":null,"date":"2023-01-03T10:22:51","name":"[arm] Skip ld/pr23169 test on arm.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230103102251.89478-2-christophe.lyon@arm.com/mbox/"},{"id":38431,"url":"https://patchwork.plctlab.org/api/1.2/patches/38431/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230103135330.1225218-1-chigot@adacore.com/","msgid":"<20230103135330.1225218-1-chigot@adacore.com>","list_archive_url":null,"date":"2023-01-03T13:53:30","name":"configure: remove dependencies on gmp and mpfr when gdb is disabled","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230103135330.1225218-1-chigot@adacore.com/mbox/"},{"id":38506,"url":"https://patchwork.plctlab.org/api/1.2/patches/38506/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230103162543.2412854-1-chigot@adacore.com/","msgid":"<20230103162543.2412854-1-chigot@adacore.com>","list_archive_url":null,"date":"2023-01-03T16:25:43","name":"[v2] configure: remove dependencies on gmp and mpfr when gdb is disabled","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230103162543.2412854-1-chigot@adacore.com/mbox/"},{"id":38694,"url":"https://patchwork.plctlab.org/api/1.2/patches/38694/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230103214931.3320223-1-dilfridge@gentoo.org/","msgid":"<20230103214931.3320223-1-dilfridge@gentoo.org>","list_archive_url":null,"date":"2023-01-03T21:49:31","name":"ld testsuite: un-xfail pr19719 tests on aarch64, seems to succeed now","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230103214931.3320223-1-dilfridge@gentoo.org/mbox/"},{"id":38658,"url":"https://patchwork.plctlab.org/api/1.2/patches/38658/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230103215722.616744-1-jcmvbkbc@gmail.com/","msgid":"<20230103215722.616744-1-jcmvbkbc@gmail.com>","list_archive_url":null,"date":"2023-01-03T21:57:22","name":"[COMMITTED] opcodes: xtensa: implement styled disassembly","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230103215722.616744-1-jcmvbkbc@gmail.com/mbox/"},{"id":38659,"url":"https://patchwork.plctlab.org/api/1.2/patches/38659/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230103215746.616794-1-jcmvbkbc@gmail.com/","msgid":"<20230103215746.616794-1-jcmvbkbc@gmail.com>","list_archive_url":null,"date":"2023-01-03T21:57:46","name":"[COMMITTED] opcodes: xtensa: fix jump visualization for FLIX","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230103215746.616794-1-jcmvbkbc@gmail.com/mbox/"},{"id":38714,"url":"https://patchwork.plctlab.org/api/1.2/patches/38714/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230104011831.965647-1-indu.bhagat@oracle.com/","msgid":"<20230104011831.965647-1-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-01-04T01:18:31","name":"MAINTAINERS: add myself as maintainer of libsframe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230104011831.965647-1-indu.bhagat@oracle.com/mbox/"},{"id":38733,"url":"https://patchwork.plctlab.org/api/1.2/patches/38733/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230104041219.794237-1-guillermo.e.martinez@oracle.com/","msgid":"<20230104041219.794237-1-guillermo.e.martinez@oracle.com>","list_archive_url":null,"date":"2023-01-04T04:12:19","name":"Fix sim/testsuite/bpf due to linker warnings","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230104041219.794237-1-guillermo.e.martinez@oracle.com/mbox/"},{"id":38743,"url":"https://patchwork.plctlab.org/api/1.2/patches/38743/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230104055936.1130680-1-aurelien@aurel32.net/","msgid":"<20230104055936.1130680-1-aurelien@aurel32.net>","list_archive_url":null,"date":"2023-01-04T05:59:36","name":"RISC-V: fix JAL aliases ordering in opcode table","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230104055936.1130680-1-aurelien@aurel32.net/mbox/"},{"id":38774,"url":"https://patchwork.plctlab.org/api/1.2/patches/38774/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230104065611.377771-1-indu.bhagat@oracle.com/","msgid":"<20230104065611.377771-1-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-01-04T06:56:11","name":"libsframe: adjust an incorrect check in flip_sframe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230104065611.377771-1-indu.bhagat@oracle.com/mbox/"},{"id":38920,"url":"https://patchwork.plctlab.org/api/1.2/patches/38920/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y7V+MNgHYTpMBNw5@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-01-04T13:25:04","name":"addr2line out of memory on fuzzed file","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y7V+MNgHYTpMBNw5@squeak.grove.modra.org/mbox/"},{"id":38921,"url":"https://patchwork.plctlab.org/api/1.2/patches/38921/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y7V+U0bOlfYE++6E@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-01-04T13:25:39","name":"asan: segv in parse_module","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y7V+U0bOlfYE++6E@squeak.grove.modra.org/mbox/"},{"id":38922,"url":"https://patchwork.plctlab.org/api/1.2/patches/38922/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y7V+g16MZQvQAYgv@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-01-04T13:26:27","name":"fuzzed file timeout","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y7V+g16MZQvQAYgv@squeak.grove.modra.org/mbox/"},{"id":39067,"url":"https://patchwork.plctlab.org/api/1.2/patches/39067/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230104191414.149668-1-hjl.tools@gmail.com/","msgid":"<20230104191414.149668-1-hjl.tools@gmail.com>","list_archive_url":null,"date":"2023-01-04T19:14:14","name":"x86: Remove duplicated I386_PCREL_TYPE_P/X86_64_PCREL_TYPE_P","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230104191414.149668-1-hjl.tools@gmail.com/mbox/"},{"id":39123,"url":"https://patchwork.plctlab.org/api/1.2/patches/39123/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230104214109.51006-1-guillermo.e.martinez@oracle.com/","msgid":"<20230104214109.51006-1-guillermo.e.martinez@oracle.com>","list_archive_url":null,"date":"2023-01-04T21:41:09","name":"[PATCHv2] Fix sim/testsuite/bpf due to linker warnings","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230104214109.51006-1-guillermo.e.martinez@oracle.com/mbox/"},{"id":39188,"url":"https://patchwork.plctlab.org/api/1.2/patches/39188/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230105002743.25019-1-mark@harmstone.com/","msgid":"<20230105002743.25019-1-mark@harmstone.com>","list_archive_url":null,"date":"2023-01-05T00:27:43","name":"ld/testsuite: Fix test failures in pe.exp caused by 8819b236","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230105002743.25019-1-mark@harmstone.com/mbox/"},{"id":39795,"url":"https://patchwork.plctlab.org/api/1.2/patches/39795/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230105210542.3573076-1-maskray@google.com/","msgid":"<20230105210542.3573076-1-maskray@google.com>","list_archive_url":null,"date":"2023-01-05T21:05:42","name":"ld: Allow R_X86_64_GOTPCREL for call *__tls_get_addr@GOTPCREL(%rip)","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230105210542.3573076-1-maskray@google.com/mbox/"},{"id":39834,"url":"https://patchwork.plctlab.org/api/1.2/patches/39834/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230105230742.1097314-1-maskray@google.com/","msgid":"<20230105230742.1097314-1-maskray@google.com>","list_archive_url":null,"date":"2023-01-05T23:07:42","name":"ld: Allow R_386_GOT32 for call *__tls_get_addr@GOT(%reg)","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230105230742.1097314-1-maskray@google.com/mbox/"},{"id":39890,"url":"https://patchwork.plctlab.org/api/1.2/patches/39890/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230106012509.7918-1-mark@harmstone.com/","msgid":"<20230106012509.7918-1-mark@harmstone.com>","list_archive_url":null,"date":"2023-01-06T01:25:03","name":"[1/7] Fix size of external_reloc for pe-aarch64","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230106012509.7918-1-mark@harmstone.com/mbox/"},{"id":39891,"url":"https://patchwork.plctlab.org/api/1.2/patches/39891/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230106012509.7918-2-mark@harmstone.com/","msgid":"<20230106012509.7918-2-mark@harmstone.com>","list_archive_url":null,"date":"2023-01-06T01:25:04","name":"[2/7] Skip ELF-specific tests when targeting pe-aarch64","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230106012509.7918-2-mark@harmstone.com/mbox/"},{"id":39892,"url":"https://patchwork.plctlab.org/api/1.2/patches/39892/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230106012509.7918-3-mark@harmstone.com/","msgid":"<20230106012509.7918-3-mark@harmstone.com>","list_archive_url":null,"date":"2023-01-06T01:25:05","name":"[3/7] Skip big-obj test for pe-aarch64","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230106012509.7918-3-mark@harmstone.com/mbox/"},{"id":39896,"url":"https://patchwork.plctlab.org/api/1.2/patches/39896/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230106012509.7918-4-mark@harmstone.com/","msgid":"<20230106012509.7918-4-mark@harmstone.com>","list_archive_url":null,"date":"2023-01-06T01:25:06","name":"[4/7] Add pe-aarch64 relocations","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230106012509.7918-4-mark@harmstone.com/mbox/"},{"id":39894,"url":"https://patchwork.plctlab.org/api/1.2/patches/39894/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230106012509.7918-5-mark@harmstone.com/","msgid":"<20230106012509.7918-5-mark@harmstone.com>","list_archive_url":null,"date":"2023-01-06T01:25:07","name":"[5/7] Add .secrel32 for pe-aarch64","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230106012509.7918-5-mark@harmstone.com/mbox/"},{"id":39893,"url":"https://patchwork.plctlab.org/api/1.2/patches/39893/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230106012509.7918-6-mark@harmstone.com/","msgid":"<20230106012509.7918-6-mark@harmstone.com>","list_archive_url":null,"date":"2023-01-06T01:25:08","name":"[6/7] Add aarch64-w64-mingw32 target","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230106012509.7918-6-mark@harmstone.com/mbox/"},{"id":39895,"url":"https://patchwork.plctlab.org/api/1.2/patches/39895/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230106012509.7918-7-mark@harmstone.com/","msgid":"<20230106012509.7918-7-mark@harmstone.com>","list_archive_url":null,"date":"2023-01-06T01:25:09","name":"[7/7] gas: Restore tc_pe_dwarf2_emit_offset for pe-aarch64","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230106012509.7918-7-mark@harmstone.com/mbox/"},{"id":39967,"url":"https://patchwork.plctlab.org/api/1.2/patches/39967/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230106064053.984817-1-indu.bhagat@oracle.com/","msgid":"<20230106064053.984817-1-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-01-06T06:40:53","name":"sframe: fix the defined SFRAME_FRE_TYPE_*_LIMIT constants","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230106064053.984817-1-indu.bhagat@oracle.com/mbox/"},{"id":39979,"url":"https://patchwork.plctlab.org/api/1.2/patches/39979/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230106075816.387489-1-guillermo.e.martinez@oracle.com/","msgid":"<20230106075816.387489-1-guillermo.e.martinez@oracle.com>","list_archive_url":null,"date":"2023-01-06T07:58:16","name":"bpf: fix error conversion from long unsigned int to unsigned int [-Werror=overflow]","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230106075816.387489-1-guillermo.e.martinez@oracle.com/mbox/"},{"id":40061,"url":"https://patchwork.plctlab.org/api/1.2/patches/40061/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b7e9975b-086f-a9f6-ab6b-0181d50187e1@suse.com/","msgid":"","list_archive_url":null,"date":"2023-01-06T09:33:00","name":"ld: yet another PDB build fix (or workaround)","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b7e9975b-086f-a9f6-ab6b-0181d50187e1@suse.com/mbox/"},{"id":40085,"url":"https://patchwork.plctlab.org/api/1.2/patches/40085/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y7f7RLzDodzChR88@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-01-06T10:43:16","name":"Make coff backend data read-only","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y7f7RLzDodzChR88@squeak.grove.modra.org/mbox/"},{"id":40086,"url":"https://patchwork.plctlab.org/api/1.2/patches/40086/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y7f7chtgwRfAVNME@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-01-06T10:44:02","name":"Tidy pe flag in coff_data","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y7f7chtgwRfAVNME@squeak.grove.modra.org/mbox/"},{"id":40087,"url":"https://patchwork.plctlab.org/api/1.2/patches/40087/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y7f7lGQlMvLz157a@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-01-06T10:44:36","name":"Fix an aout memory leak","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y7f7lGQlMvLz157a@squeak.grove.modra.org/mbox/"},{"id":40114,"url":"https://patchwork.plctlab.org/api/1.2/patches/40114/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6c9f38b9-c582-3a1a-55ce-bb9966940a80@suse.com/","msgid":"<6c9f38b9-c582-3a1a-55ce-bb9966940a80@suse.com>","list_archive_url":null,"date":"2023-01-06T12:34:46","name":"gas/RISC-V: adjust assembler for opcode table re-ordering","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6c9f38b9-c582-3a1a-55ce-bb9966940a80@suse.com/mbox/"},{"id":40415,"url":"https://patchwork.plctlab.org/api/1.2/patches/40415/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230107154743.624854-1-guillermo.e.martinez@oracle.com/","msgid":"<20230107154743.624854-1-guillermo.e.martinez@oracle.com>","list_archive_url":null,"date":"2023-01-07T15:47:43","name":"bpf: fix error conversion from long unsigned int to unsigned int [-Werror=overflow]","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230107154743.624854-1-guillermo.e.martinez@oracle.com/mbox/"},{"id":40698,"url":"https://patchwork.plctlab.org/api/1.2/patches/40698/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230109083526.74448-1-mengqinggang@loongson.cn/","msgid":"<20230109083526.74448-1-mengqinggang@loongson.cn>","list_archive_url":null,"date":"2023-01-09T08:35:26","name":"LoongArch: ld: Fix hidden ifunc symbol linker error bug.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230109083526.74448-1-mengqinggang@loongson.cn/mbox/"},{"id":41215,"url":"https://patchwork.plctlab.org/api/1.2/patches/41215/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y7ygyYa8VydFJqaD@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-01-09T23:18:33","name":"Move bfd_init to bfd.c","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y7ygyYa8VydFJqaD@squeak.grove.modra.org/mbox/"},{"id":41216,"url":"https://patchwork.plctlab.org/api/1.2/patches/41216/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y7yg79B/YO6FUkMB@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-01-09T23:19:11","name":"Move mips_refhi_list to bfd tdata","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y7yg79B/YO6FUkMB@squeak.grove.modra.org/mbox/"},{"id":41226,"url":"https://patchwork.plctlab.org/api/1.2/patches/41226/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y7ylp96AC5XxPRgq@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-01-09T23:39:19","name":"peXXigen.c sanity checks","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y7ylp96AC5XxPRgq@squeak.grove.modra.org/mbox/"},{"id":41227,"url":"https://patchwork.plctlab.org/api/1.2/patches/41227/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y7yl1F46NAHWkWo5@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-01-09T23:40:04","name":"Set dwarf2 stash pointer earlier","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y7yl1F46NAHWkWo5@squeak.grove.modra.org/mbox/"},{"id":41452,"url":"https://patchwork.plctlab.org/api/1.2/patches/41452/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230110130050.366404-2-nick.alcock@oracle.com/","msgid":"<20230110130050.366404-2-nick.alcock@oracle.com>","list_archive_url":null,"date":"2023-01-10T13:00:48","name":"[v2,1/3] ctf: fix various dreadful typos in the ctf_archive format comments","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230110130050.366404-2-nick.alcock@oracle.com/mbox/"},{"id":41453,"url":"https://patchwork.plctlab.org/api/1.2/patches/41453/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230110130050.366404-3-nick.alcock@oracle.com/","msgid":"<20230110130050.366404-3-nick.alcock@oracle.com>","list_archive_url":null,"date":"2023-01-10T13:00:49","name":"[v2,2/3] libctf: skip the testsuite from inside dejagnu","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230110130050.366404-3-nick.alcock@oracle.com/mbox/"},{"id":41454,"url":"https://patchwork.plctlab.org/api/1.2/patches/41454/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230110130050.366404-4-nick.alcock@oracle.com/","msgid":"<20230110130050.366404-4-nick.alcock@oracle.com>","list_archive_url":null,"date":"2023-01-10T13:00:50","name":"[v2,3/3] libctf: ctf-link outdated input check faulty","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230110130050.366404-4-nick.alcock@oracle.com/mbox/"},{"id":41470,"url":"https://patchwork.plctlab.org/api/1.2/patches/41470/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230110133534.5295-1-stefansf@linux.ibm.com/","msgid":"<20230110133534.5295-1-stefansf@linux.ibm.com>","list_archive_url":null,"date":"2023-01-10T13:35:35","name":"IBM zSystems: Fix offset relative to static TLS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230110133534.5295-1-stefansf@linux.ibm.com/mbox/"},{"id":41571,"url":"https://patchwork.plctlab.org/api/1.2/patches/41571/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230110182745.3641128-1-indu.bhagat@oracle.com/","msgid":"<20230110182745.3641128-1-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-01-10T18:27:45","name":"libsframe: replace an strncat with strcat","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230110182745.3641128-1-indu.bhagat@oracle.com/mbox/"},{"id":41761,"url":"https://patchwork.plctlab.org/api/1.2/patches/41761/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y75R4sYOPg/8UuHm@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-01-11T06:06:26","name":"now_seg after closing output file","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y75R4sYOPg/8UuHm@squeak.grove.modra.org/mbox/"},{"id":41817,"url":"https://patchwork.plctlab.org/api/1.2/patches/41817/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y751L9gX14jBBlO0@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-01-11T08:37:03","name":"Tidy some global bfd state used by gas","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y751L9gX14jBBlO0@squeak.grove.modra.org/mbox/"},{"id":41974,"url":"https://patchwork.plctlab.org/api/1.2/patches/41974/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y762S0diPNqwWu1a@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-01-11T13:14:51","name":"Fix XPASS weak symbols on x86_64-mingw32","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y762S0diPNqwWu1a@squeak.grove.modra.org/mbox/"},{"id":42134,"url":"https://patchwork.plctlab.org/api/1.2/patches/42134/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230111183204.11600-1-mark@harmstone.com/","msgid":"<20230111183204.11600-1-mark@harmstone.com>","list_archive_url":null,"date":"2023-01-11T18:32:04","name":"Use subsystem to distinguish between pei-arm-little and pei-arm-wince-little","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230111183204.11600-1-mark@harmstone.com/mbox/"},{"id":42262,"url":"https://patchwork.plctlab.org/api/1.2/patches/42262/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y7+tQPYaY/skpLIf@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-01-12T06:48:32","name":"Remove myself as hppa32 maintainer","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y7+tQPYaY/skpLIf@squeak.grove.modra.org/mbox/"},{"id":42263,"url":"https://patchwork.plctlab.org/api/1.2/patches/42263/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y7+tkeiBByVJdca3@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-01-12T06:49:53","name":"Use __func__ rather than __FUNCTION__","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y7+tkeiBByVJdca3@squeak.grove.modra.org/mbox/"},{"id":42799,"url":"https://patchwork.plctlab.org/api/1.2/patches/42799/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230112205654.3456561-1-vladimir.mezentsev@oracle.com/","msgid":"<20230112205654.3456561-1-vladimir.mezentsev@oracle.com>","list_archive_url":null,"date":"2023-01-12T20:56:54","name":"gprofng: PR29987 bfd/archive.c:1447: undefined reference to `filename_ncmp'\''","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230112205654.3456561-1-vladimir.mezentsev@oracle.com/mbox/"},{"id":43131,"url":"https://patchwork.plctlab.org/api/1.2/patches/43131/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/95936261-d824-9128-1be9-ba7dfe12b042@suse.com/","msgid":"<95936261-d824-9128-1be9-ba7dfe12b042@suse.com>","list_archive_url":null,"date":"2023-01-13T10:19:19","name":"[1/3] RISC-V: prefer SLT{,U} aliases for SLTI{,U}","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/95936261-d824-9128-1be9-ba7dfe12b042@suse.com/mbox/"},{"id":43133,"url":"https://patchwork.plctlab.org/api/1.2/patches/43133/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/63fa0796-59e6-6429-6c86-b8707cc9f8d9@suse.com/","msgid":"<63fa0796-59e6-6429-6c86-b8707cc9f8d9@suse.com>","list_archive_url":null,"date":"2023-01-13T10:19:51","name":"[2/3] RISC-V: move OR and XOR aliases down","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/63fa0796-59e6-6429-6c86-b8707cc9f8d9@suse.com/mbox/"},{"id":43134,"url":"https://patchwork.plctlab.org/api/1.2/patches/43134/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/448243b9-8134-f981-8e66-635790d4e680@suse.com/","msgid":"<448243b9-8134-f981-8e66-635790d4e680@suse.com>","list_archive_url":null,"date":"2023-01-13T10:20:23","name":"[3/3] RISC-V: prefer FSRM/FSFLAGS aliases for FSRMI/FSFLAGSI","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/448243b9-8134-f981-8e66-635790d4e680@suse.com/mbox/"},{"id":43166,"url":"https://patchwork.plctlab.org/api/1.2/patches/43166/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/55dd0365-1b8c-45d0-cb85-fc8ebdc2ac21@suse.com/","msgid":"<55dd0365-1b8c-45d0-cb85-fc8ebdc2ac21@suse.com>","list_archive_url":null,"date":"2023-01-13T11:05:43","name":"[1/8] x86: abstract out obtaining of a template'\''s mnemonic","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/55dd0365-1b8c-45d0-cb85-fc8ebdc2ac21@suse.com/mbox/"},{"id":43167,"url":"https://patchwork.plctlab.org/api/1.2/patches/43167/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fa681978-5ee6-16ba-3f08-958f6d1cf805@suse.com/","msgid":"","list_archive_url":null,"date":"2023-01-13T11:06:32","name":"[1/8] x86: move insn mnemonics to a separate table","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fa681978-5ee6-16ba-3f08-958f6d1cf805@suse.com/mbox/"},{"id":43168,"url":"https://patchwork.plctlab.org/api/1.2/patches/43168/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d87c0ed5-4678-d8ea-9744-7447ff82a843@suse.com/","msgid":"","list_archive_url":null,"date":"2023-01-13T11:07:24","name":"[3/8] x86: re-use insn mnemonic strings as much as possible","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d87c0ed5-4678-d8ea-9744-7447ff82a843@suse.com/mbox/"},{"id":43169,"url":"https://patchwork.plctlab.org/api/1.2/patches/43169/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8f43bf06-9323-8838-bcdc-bfbf9a850ae2@suse.com/","msgid":"<8f43bf06-9323-8838-bcdc-bfbf9a850ae2@suse.com>","list_archive_url":null,"date":"2023-01-13T11:07:46","name":"[4/8] x86: absorb allocation in i386-gen","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8f43bf06-9323-8838-bcdc-bfbf9a850ae2@suse.com/mbox/"},{"id":43170,"url":"https://patchwork.plctlab.org/api/1.2/patches/43170/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c60483a9-14fc-f2f4-0185-80c2510e45a5@suse.com/","msgid":"","list_archive_url":null,"date":"2023-01-13T11:08:33","name":"[5/8] x86: avoid strcmp() in a few places","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c60483a9-14fc-f2f4-0185-80c2510e45a5@suse.com/mbox/"},{"id":43171,"url":"https://patchwork.plctlab.org/api/1.2/patches/43171/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1c763a63-05e0-33e8-c9c4-48a26cbc5db7@suse.com/","msgid":"<1c763a63-05e0-33e8-c9c4-48a26cbc5db7@suse.com>","list_archive_url":null,"date":"2023-01-13T11:10:03","name":"[6/8] x86: embed register names in reg_entry","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1c763a63-05e0-33e8-c9c4-48a26cbc5db7@suse.com/mbox/"},{"id":43172,"url":"https://patchwork.plctlab.org/api/1.2/patches/43172/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8a6f1fce-435a-b8fa-44a3-c7ae2c621968@suse.com/","msgid":"<8a6f1fce-435a-b8fa-44a3-c7ae2c621968@suse.com>","list_archive_url":null,"date":"2023-01-13T11:11:01","name":"[7/8] x86: embed register and alike names in disassembler","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8a6f1fce-435a-b8fa-44a3-c7ae2c621968@suse.com/mbox/"},{"id":43174,"url":"https://patchwork.plctlab.org/api/1.2/patches/43174/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1d538fdf-536a-37b0-556b-b4ca86b0a090@suse.com/","msgid":"<1d538fdf-536a-37b0-556b-b4ca86b0a090@suse.com>","list_archive_url":null,"date":"2023-01-13T11:11:37","name":"[8/8] x86: split i386-gen'\''s opcode hash entry struct","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1d538fdf-536a-37b0-556b-b4ca86b0a090@suse.com/mbox/"},{"id":43288,"url":"https://patchwork.plctlab.org/api/1.2/patches/43288/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230113125454.75744-1-cooper.qu@linux.alibaba.com/","msgid":"<20230113125454.75744-1-cooper.qu@linux.alibaba.com>","list_archive_url":null,"date":"2023-01-13T12:54:54","name":"C-SKY: Fix machine flag.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230113125454.75744-1-cooper.qu@linux.alibaba.com/mbox/"},{"id":43355,"url":"https://patchwork.plctlab.org/api/1.2/patches/43355/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/OS3P286MB2152AC3F96A88680022D57ADF0C29@OS3P286MB2152.JPNP286.PROD.OUTLOOK.COM/","msgid":"","list_archive_url":null,"date":"2023-01-13T14:42:32","name":"libctf: update regexp to allow makeinfo to build document","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/OS3P286MB2152AC3F96A88680022D57ADF0C29@OS3P286MB2152.JPNP286.PROD.OUTLOOK.COM/mbox/"},{"id":43695,"url":"https://patchwork.plctlab.org/api/1.2/patches/43695/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/OS3P286MB2152CCD151694D02E2A84D23F0C39@OS3P286MB2152.JPNP286.PROD.OUTLOOK.COM/","msgid":"","list_archive_url":null,"date":"2023-01-14T04:23:26","name":"[v2] libctf: update regexp to allow makeinfo to build document","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/OS3P286MB2152CCD151694D02E2A84D23F0C39@OS3P286MB2152.JPNP286.PROD.OUTLOOK.COM/mbox/"},{"id":44089,"url":"https://patchwork.plctlab.org/api/1.2/patches/44089/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y8U25YxsSHWBz8of@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-01-16T11:37:09","name":"PR29991, MicroMIPS flag erased after align directives","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y8U25YxsSHWBz8of@squeak.grove.modra.org/mbox/"},{"id":44107,"url":"https://patchwork.plctlab.org/api/1.2/patches/44107/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y8VJCZte0qnkPRWk@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-01-16T12:54:33","name":"COFF CALC_ADDEND comment","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y8VJCZte0qnkPRWk@squeak.grove.modra.org/mbox/"},{"id":44109,"url":"https://patchwork.plctlab.org/api/1.2/patches/44109/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y8VJdIvu7DGz4i7I@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-01-16T12:56:20","name":"Leftover hack from i960-coff","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y8VJdIvu7DGz4i7I@squeak.grove.modra.org/mbox/"},{"id":44111,"url":"https://patchwork.plctlab.org/api/1.2/patches/44111/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y8VJxpkPeEvO360+@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-01-16T12:57:42","name":"Tidy gas/expr.c static state","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y8VJxpkPeEvO360+@squeak.grove.modra.org/mbox/"},{"id":44146,"url":"https://patchwork.plctlab.org/api/1.2/patches/44146/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y8VRUsfXY5Vjk5A1@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-01-16T13:29:54","name":"Correct ld-pe/aarch64.d test output","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y8VRUsfXY5Vjk5A1@squeak.grove.modra.org/mbox/"},{"id":44218,"url":"https://patchwork.plctlab.org/api/1.2/patches/44218/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1ff07fee-24f1-7aeb-8fb6-44457af557c4@arm.com/","msgid":"<1ff07fee-24f1-7aeb-8fb6-44457af557c4@arm.com>","list_archive_url":null,"date":"2023-01-16T15:14:42","name":"[PING,1/2] gas: arm: Fix a further IT-predicated vcvt issue in the presense of MVE vcvtn","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1ff07fee-24f1-7aeb-8fb6-44457af557c4@arm.com/mbox/"},{"id":44219,"url":"https://patchwork.plctlab.org/api/1.2/patches/44219/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0b4d01ad-38b9-428e-39af-3ff452f94ef2@arm.com/","msgid":"<0b4d01ad-38b9-428e-39af-3ff452f94ef2@arm.com>","list_archive_url":null,"date":"2023-01-16T15:14:55","name":"[PING,2/2] gas: arm: Change warning message to not reference specific A-class architecture revision","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0b4d01ad-38b9-428e-39af-3ff452f94ef2@arm.com/mbox/"},{"id":44644,"url":"https://patchwork.plctlab.org/api/1.2/patches/44644/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/yddbkmx8kt8.fsf@CeBiTec.Uni-Bielefeld.DE/","msgid":"","list_archive_url":null,"date":"2023-01-17T11:25:23","name":"i386: Don'\''t emit unsupported TLS relocs on Solaris [PR13671]","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/yddbkmx8kt8.fsf@CeBiTec.Uni-Bielefeld.DE/mbox/"},{"id":44718,"url":"https://patchwork.plctlab.org/api/1.2/patches/44718/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230117154125.601189-1-hjl.tools@gmail.com/","msgid":"<20230117154125.601189-1-hjl.tools@gmail.com>","list_archive_url":null,"date":"2023-01-17T15:41:25","name":"ld: Use run_cc_link_tests for PR ld/26391 tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230117154125.601189-1-hjl.tools@gmail.com/mbox/"},{"id":44872,"url":"https://patchwork.plctlab.org/api/1.2/patches/44872/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230118001851.3467920-1-indu.bhagat@oracle.com/","msgid":"<20230118001851.3467920-1-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-01-18T00:18:51","name":"toplevel: Makefile.def: add install-strip dependency on libsframe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230118001851.3467920-1-indu.bhagat@oracle.com/mbox/"},{"id":44975,"url":"https://patchwork.plctlab.org/api/1.2/patches/44975/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230118051136.10243-1-mark@harmstone.com/","msgid":"<20230118051136.10243-1-mark@harmstone.com>","list_archive_url":null,"date":"2023-01-18T05:11:36","name":"ld: Fix ADDR32/64 incorrect outputs in pe-aarch64","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230118051136.10243-1-mark@harmstone.com/mbox/"},{"id":44995,"url":"https://patchwork.plctlab.org/api/1.2/patches/44995/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230118062657.1125934-2-amodra@gmail.com/","msgid":"<20230118062657.1125934-2-amodra@gmail.com>","list_archive_url":null,"date":"2023-01-18T06:26:54","name":"[1/4] howto install_addend","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230118062657.1125934-2-amodra@gmail.com/mbox/"},{"id":44994,"url":"https://patchwork.plctlab.org/api/1.2/patches/44994/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230118062657.1125934-3-amodra@gmail.com/","msgid":"<20230118062657.1125934-3-amodra@gmail.com>","list_archive_url":null,"date":"2023-01-18T06:26:55","name":"[2/4] coff-aarch64.c howtos","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230118062657.1125934-3-amodra@gmail.com/mbox/"},{"id":44999,"url":"https://patchwork.plctlab.org/api/1.2/patches/44999/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230118062657.1125934-4-amodra@gmail.com/","msgid":"<20230118062657.1125934-4-amodra@gmail.com>","list_archive_url":null,"date":"2023-01-18T06:26:56","name":"[3/4] Correct coff-aarch64 howtos and delete unnecessary special functions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230118062657.1125934-4-amodra@gmail.com/mbox/"},{"id":44998,"url":"https://patchwork.plctlab.org/api/1.2/patches/44998/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230118062657.1125934-5-amodra@gmail.com/","msgid":"<20230118062657.1125934-5-amodra@gmail.com>","list_archive_url":null,"date":"2023-01-18T06:26:57","name":"[4/4] The fuzzers have found the reloc special functions in coff-aarch64.c","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230118062657.1125934-5-amodra@gmail.com/mbox/"},{"id":45183,"url":"https://patchwork.plctlab.org/api/1.2/patches/45183/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/87y1q013k1.fsf@redhat.com/","msgid":"<87y1q013k1.fsf@redhat.com>","list_archive_url":null,"date":"2023-01-18T11:32:14","name":"Commit: Improve the performance of objcopy'\''s note merging algorithm","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/87y1q013k1.fsf@redhat.com/mbox/"},{"id":45396,"url":"https://patchwork.plctlab.org/api/1.2/patches/45396/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.LSU.2.20.2301181731360.30340@wotan.suse.de/","msgid":"","list_archive_url":null,"date":"2023-01-18T17:31:54","name":"[1/3] Faster string merging","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.LSU.2.20.2301181731360.30340@wotan.suse.de/mbox/"},{"id":45399,"url":"https://patchwork.plctlab.org/api/1.2/patches/45399/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.LSU.2.20.2301181731590.30340@wotan.suse.de/","msgid":"","list_archive_url":null,"date":"2023-01-18T17:32:09","name":"[2/3] arm32: Fix rodata-merge-map","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.LSU.2.20.2301181731590.30340@wotan.suse.de/mbox/"},{"id":45395,"url":"https://patchwork.plctlab.org/api/1.2/patches/45395/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.LSU.2.20.2301181732140.30340@wotan.suse.de/","msgid":"","list_archive_url":null,"date":"2023-01-18T17:32:24","name":"[3/3] Add testcase ld-elf/merge4","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.LSU.2.20.2301181732140.30340@wotan.suse.de/mbox/"},{"id":45571,"url":"https://patchwork.plctlab.org/api/1.2/patches/45571/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230119035126.1172654-1-raj.khem@gmail.com/","msgid":"<20230119035126.1172654-1-raj.khem@gmail.com>","list_archive_url":null,"date":"2023-01-19T03:51:26","name":"Remove duplicate pe-dll.o entry deom targ_extra_ofiles","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230119035126.1172654-1-raj.khem@gmail.com/mbox/"},{"id":45616,"url":"https://patchwork.plctlab.org/api/1.2/patches/45616/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y8juE1B+0XLFwkuv@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-01-19T07:15:31","name":"PR 30022, concurrent builds can fail","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y8juE1B+0XLFwkuv@squeak.grove.modra.org/mbox/"},{"id":45640,"url":"https://patchwork.plctlab.org/api/1.2/patches/45640/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y8j634999Uh3otCN@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-01-19T08:10:07","name":"Reinitialise macro_nest","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y8j634999Uh3otCN@squeak.grove.modra.org/mbox/"},{"id":45960,"url":"https://patchwork.plctlab.org/api/1.2/patches/45960/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230119205932.3025258-1-indu.bhagat@oracle.com/","msgid":"<20230119205932.3025258-1-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-01-19T20:59:32","name":"[COMMITTED] libsframe: Use AM_SILENT_RULES macro in configure.ac","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230119205932.3025258-1-indu.bhagat@oracle.com/mbox/"},{"id":45961,"url":"https://patchwork.plctlab.org/api/1.2/patches/45961/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y8mwO5KmTqXAtFhC@fedora/","msgid":"","list_archive_url":null,"date":"2023-01-19T21:03:55","name":"Add OpenBSD ARM GAS support.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y8mwO5KmTqXAtFhC@fedora/mbox/"},{"id":46019,"url":"https://patchwork.plctlab.org/api/1.2/patches/46019/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230119214728.3208371-1-indu.bhagat@oracle.com/","msgid":"<20230119214728.3208371-1-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-01-19T21:47:28","name":"doc: sframe: fix some warnings","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230119214728.3208371-1-indu.bhagat@oracle.com/mbox/"},{"id":46256,"url":"https://patchwork.plctlab.org/api/1.2/patches/46256/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/98a5c1d5-00c9-75b3-db8c-019e056d720c@suse.com/","msgid":"<98a5c1d5-00c9-75b3-db8c-019e056d720c@suse.com>","list_archive_url":null,"date":"2023-01-20T09:30:48","name":"[1/2] x86: remove internationalization from i386-gen.c","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/98a5c1d5-00c9-75b3-db8c-019e056d720c@suse.com/mbox/"},{"id":46257,"url":"https://patchwork.plctlab.org/api/1.2/patches/46257/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c2aea3ae-6280-ad3d-2657-ad54f5d5b6bc@suse.com/","msgid":"","list_archive_url":null,"date":"2023-01-20T09:31:27","name":"[2/2] opcodes: suppress internationalization on build helper tools","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c2aea3ae-6280-ad3d-2657-ad54f5d5b6bc@suse.com/mbox/"},{"id":46268,"url":"https://patchwork.plctlab.org/api/1.2/patches/46268/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b8481a70-fa06-a794-ba34-555e712d679f@suse.com/","msgid":"","list_archive_url":null,"date":"2023-01-20T09:55:26","name":"x86/Intel: improve special casing of certain insns","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b8481a70-fa06-a794-ba34-555e712d679f@suse.com/mbox/"},{"id":46274,"url":"https://patchwork.plctlab.org/api/1.2/patches/46274/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1299219c-8f54-8672-a898-3aa1acc2b9ec@suse.com/","msgid":"<1299219c-8f54-8672-a898-3aa1acc2b9ec@suse.com>","list_archive_url":null,"date":"2023-01-20T10:00:13","name":"[1/3] x86: use ModR/M for FPU insns with operands","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1299219c-8f54-8672-a898-3aa1acc2b9ec@suse.com/mbox/"},{"id":46276,"url":"https://patchwork.plctlab.org/api/1.2/patches/46276/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7882acac-b12c-ac86-77f7-063ecd07e799@suse.com/","msgid":"<7882acac-b12c-ac86-77f7-063ecd07e799@suse.com>","list_archive_url":null,"date":"2023-01-20T10:00:35","name":"[2/3] x86: drop dead SSE2AVX-related code","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7882acac-b12c-ac86-77f7-063ecd07e799@suse.com/mbox/"},{"id":46275,"url":"https://patchwork.plctlab.org/api/1.2/patches/46275/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/44a44856-b7b2-5236-9d5e-6c681fc0fb82@suse.com/","msgid":"<44a44856-b7b2-5236-9d5e-6c681fc0fb82@suse.com>","list_archive_url":null,"date":"2023-01-20T10:00:54","name":"[3/3] x86: move reg_operands adjustment","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/44a44856-b7b2-5236-9d5e-6c681fc0fb82@suse.com/mbox/"},{"id":46588,"url":"https://patchwork.plctlab.org/api/1.2/patches/46588/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230120191842.3799467-1-indu.bhagat@oracle.com/","msgid":"<20230120191842.3799467-1-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-01-20T19:18:42","name":"[COMMITTED] Upload SFrame spec files as well","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230120191842.3799467-1-indu.bhagat@oracle.com/mbox/"},{"id":46609,"url":"https://patchwork.plctlab.org/api/1.2/patches/46609/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230120195532.917113-2-christoph.muellner@vrull.eu/","msgid":"<20230120195532.917113-2-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2023-01-20T19:55:27","name":"[RFC,v2,1/6] RISC-V: Add Zvkb ISA extension support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230120195532.917113-2-christoph.muellner@vrull.eu/mbox/"},{"id":46608,"url":"https://patchwork.plctlab.org/api/1.2/patches/46608/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230120195532.917113-3-christoph.muellner@vrull.eu/","msgid":"<20230120195532.917113-3-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2023-01-20T19:55:28","name":"[RFC,v2,2/6] RISC-V: Add Zvkg ISA extension support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230120195532.917113-3-christoph.muellner@vrull.eu/mbox/"},{"id":46612,"url":"https://patchwork.plctlab.org/api/1.2/patches/46612/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230120195532.917113-4-christoph.muellner@vrull.eu/","msgid":"<20230120195532.917113-4-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2023-01-20T19:55:29","name":"[RFC,v2,3/6] RISC-V: Add Zvknh[a,b] ISA extension support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230120195532.917113-4-christoph.muellner@vrull.eu/mbox/"},{"id":46611,"url":"https://patchwork.plctlab.org/api/1.2/patches/46611/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230120195532.917113-5-christoph.muellner@vrull.eu/","msgid":"<20230120195532.917113-5-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2023-01-20T19:55:30","name":"[RFC,v2,4/6] RISC-V: Add Zvkns ISA extension support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230120195532.917113-5-christoph.muellner@vrull.eu/mbox/"},{"id":46610,"url":"https://patchwork.plctlab.org/api/1.2/patches/46610/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230120195532.917113-6-christoph.muellner@vrull.eu/","msgid":"<20230120195532.917113-6-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2023-01-20T19:55:31","name":"[RFC,v2,5/6] RISC-V: Add Zvksed ISA extension support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230120195532.917113-6-christoph.muellner@vrull.eu/mbox/"},{"id":46613,"url":"https://patchwork.plctlab.org/api/1.2/patches/46613/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230120195532.917113-7-christoph.muellner@vrull.eu/","msgid":"<20230120195532.917113-7-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2023-01-20T19:55:32","name":"[RFC,v2,6/6] RISC-V: Add Zvksh ISA extension support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230120195532.917113-7-christoph.muellner@vrull.eu/mbox/"},{"id":46737,"url":"https://patchwork.plctlab.org/api/1.2/patches/46737/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230121002935.1139281-1-philipp.tomsich@vrull.eu/","msgid":"<20230121002935.1139281-1-philipp.tomsich@vrull.eu>","list_archive_url":null,"date":"2023-01-21T00:29:34","name":"[RFC,v1] RISC-V: Support Zicond extension","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230121002935.1139281-1-philipp.tomsich@vrull.eu/mbox/"},{"id":46985,"url":"https://patchwork.plctlab.org/api/1.2/patches/46985/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230122180736.55917-1-och95@yandex.ru/","msgid":"<20230122180736.55917-1-och95@yandex.ru>","list_archive_url":null,"date":"2023-01-22T18:07:36","name":"objdump: Fix relocations objdumping for specific symbol","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230122180736.55917-1-och95@yandex.ru/mbox/"},{"id":47021,"url":"https://patchwork.plctlab.org/api/1.2/patches/47021/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230122235733.4160-1-mark@harmstone.com/","msgid":"<20230122235733.4160-1-mark@harmstone.com>","list_archive_url":null,"date":"2023-01-22T23:57:33","name":"ld: Set default subsystem for arm-pe to IMAGE_SUBSYSTEM_WINDOWS_GUI","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230122235733.4160-1-mark@harmstone.com/mbox/"},{"id":47022,"url":"https://patchwork.plctlab.org/api/1.2/patches/47022/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230123003231.3100-1-mark@harmstone.com/","msgid":"<20230123003231.3100-1-mark@harmstone.com>","list_archive_url":null,"date":"2023-01-23T00:32:31","name":"Add support for secidx relocations to aarch64-w64-mingw32","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230123003231.3100-1-mark@harmstone.com/mbox/"},{"id":47041,"url":"https://patchwork.plctlab.org/api/1.2/patches/47041/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230123045058.449255-1-vladimir.mezentsev@oracle.com/","msgid":"<20230123045058.449255-1-vladimir.mezentsev@oracle.com>","list_archive_url":null,"date":"2023-01-23T04:50:58","name":"gprofng: PR29521 [docs] man pages are not in the release tarball","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230123045058.449255-1-vladimir.mezentsev@oracle.com/mbox/"},{"id":47453,"url":"https://patchwork.plctlab.org/api/1.2/patches/47453/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230123230154.17957-1-mark@harmstone.com/","msgid":"<20230123230154.17957-1-mark@harmstone.com>","list_archive_url":null,"date":"2023-01-23T23:01:54","name":"ld: Add pdb support to aarch64-w64-mingw32","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230123230154.17957-1-mark@harmstone.com/mbox/"},{"id":47706,"url":"https://patchwork.plctlab.org/api/1.2/patches/47706/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230124133641.258195-1-och95@yandex.ru/","msgid":"<20230124133641.258195-1-och95@yandex.ru>","list_archive_url":null,"date":"2023-01-24T13:36:41","name":"Fix emit-relocs for aarch64 gold","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230124133641.258195-1-och95@yandex.ru/mbox/"},{"id":47709,"url":"https://patchwork.plctlab.org/api/1.2/patches/47709/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230124134202.2452845-1-felix.willgerodt@intel.com/","msgid":"<20230124134202.2452845-1-felix.willgerodt@intel.com>","list_archive_url":null,"date":"2023-01-24T13:42:02","name":"[1/1] bfd, gdb: fix missing \"Core was generated by\" when loading a x32 corefile.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230124134202.2452845-1-felix.willgerodt@intel.com/mbox/"},{"id":47742,"url":"https://patchwork.plctlab.org/api/1.2/patches/47742/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4e1ac6f6-8aa5-9605-0969-40f66549c181@suse.com/","msgid":"<4e1ac6f6-8aa5-9605-0969-40f66549c181@suse.com>","list_archive_url":null,"date":"2023-01-24T15:24:32","name":"RISC-V: make C-extension JAL available again for (32-bit) assembly","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4e1ac6f6-8aa5-9605-0969-40f66549c181@suse.com/mbox/"},{"id":47994,"url":"https://patchwork.plctlab.org/api/1.2/patches/47994/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230125012024.6317-1-mark@harmstone.com/","msgid":"<20230125012024.6317-1-mark@harmstone.com>","list_archive_url":null,"date":"2023-01-25T01:20:24","name":"ld/testsuite: Add missing targets to PDB tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230125012024.6317-1-mark@harmstone.com/mbox/"},{"id":48216,"url":"https://patchwork.plctlab.org/api/1.2/patches/48216/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230125170725.386430-1-hjl.tools@gmail.com/","msgid":"<20230125170725.386430-1-hjl.tools@gmail.com>","list_archive_url":null,"date":"2023-01-25T17:07:25","name":"i386: Pass -Wl,--no-as-needed to compiler as needed","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230125170725.386430-1-hjl.tools@gmail.com/mbox/"},{"id":48437,"url":"https://patchwork.plctlab.org/api/1.2/patches/48437/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230126003820.28482-1-mark@harmstone.com/","msgid":"<20230126003820.28482-1-mark@harmstone.com>","list_archive_url":null,"date":"2023-01-26T00:38:19","name":"[1/2] gas: Add CodeView constant for aarch64","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230126003820.28482-1-mark@harmstone.com/mbox/"},{"id":48438,"url":"https://patchwork.plctlab.org/api/1.2/patches/48438/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230126003820.28482-2-mark@harmstone.com/","msgid":"<20230126003820.28482-2-mark@harmstone.com>","list_archive_url":null,"date":"2023-01-26T00:38:20","name":"[2/2] gas/testsuite: Add -gcodeview test for aarch64-w64-mingw32","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230126003820.28482-2-mark@harmstone.com/mbox/"},{"id":48479,"url":"https://patchwork.plctlab.org/api/1.2/patches/48479/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230126032613.2446180-1-vladimir.mezentsev@oracle.com/","msgid":"<20230126032613.2446180-1-vladimir.mezentsev@oracle.com>","list_archive_url":null,"date":"2023-01-26T03:26:13","name":"gprofng: PR30043 libgprofng.so.* are installed to a wrong location","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230126032613.2446180-1-vladimir.mezentsev@oracle.com/mbox/"},{"id":48906,"url":"https://patchwork.plctlab.org/api/1.2/patches/48906/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y9L12EZ4fvTcwQj1@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-01-26T21:51:20","name":"segv in coff_aarch64_addr32nb_reloc","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y9L12EZ4fvTcwQj1@squeak.grove.modra.org/mbox/"},{"id":48909,"url":"https://patchwork.plctlab.org/api/1.2/patches/48909/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y9L2F1zkVoK5AqSW@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-01-26T21:52:23","name":"resolve gas shift expressions with large exponents to zero","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y9L2F1zkVoK5AqSW@squeak.grove.modra.org/mbox/"},{"id":48911,"url":"https://patchwork.plctlab.org/api/1.2/patches/48911/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y9L2O3TbmvhYyhsC@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-01-26T21:52:59","name":"Sanity check dwarf5 form of .file","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y9L2O3TbmvhYyhsC@squeak.grove.modra.org/mbox/"},{"id":48914,"url":"https://patchwork.plctlab.org/api/1.2/patches/48914/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y9L2WRS5mIZy8y43@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-01-26T21:53:29","name":"Free gas/dwarf2dbg.c dirs","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y9L2WRS5mIZy8y43@squeak.grove.modra.org/mbox/"},{"id":49109,"url":"https://patchwork.plctlab.org/api/1.2/patches/49109/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y9N2nkjI4TDjK9+4@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-01-27T07:00:46","name":"gas macro memory leaks","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y9N2nkjI4TDjK9+4@squeak.grove.modra.org/mbox/"},{"id":49110,"url":"https://patchwork.plctlab.org/api/1.2/patches/49110/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y9N2vclgJwnt0fbW@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-01-27T07:01:17","name":"Call bfd_close_all_done in output_file_close","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y9N2vclgJwnt0fbW@squeak.grove.modra.org/mbox/"},{"id":49112,"url":"https://patchwork.plctlab.org/api/1.2/patches/49112/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y9N25JqhQsKIRAtn@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-01-27T07:01:56","name":"Perform cleanup in bfd_close after errors","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y9N25JqhQsKIRAtn@squeak.grove.modra.org/mbox/"},{"id":49111,"url":"https://patchwork.plctlab.org/api/1.2/patches/49111/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y9N3ClMTDGAq08yV@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-01-27T07:02:34","name":"Call bfd_close_all_done in ld_cleanup","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y9N3ClMTDGAq08yV@squeak.grove.modra.org/mbox/"},{"id":49193,"url":"https://patchwork.plctlab.org/api/1.2/patches/49193/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/46af6fa7-e2c2-f771-47e2-05124675b096@suse.com/","msgid":"<46af6fa7-e2c2-f771-47e2-05124675b096@suse.com>","list_archive_url":null,"date":"2023-01-27T11:10:24","name":"x86-64: respect MOVABS when choosing alternative encodings","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/46af6fa7-e2c2-f771-47e2-05124675b096@suse.com/mbox/"},{"id":49266,"url":"https://patchwork.plctlab.org/api/1.2/patches/49266/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3162e04b-3063-ab0c-3596-963132fd6233@suse.com/","msgid":"<3162e04b-3063-ab0c-3596-963132fd6233@suse.com>","list_archive_url":null,"date":"2023-01-27T11:35:04","name":"[1/3] x86: respect {nooptimize} for LEA","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3162e04b-3063-ab0c-3596-963132fd6233@suse.com/mbox/"},{"id":49267,"url":"https://patchwork.plctlab.org/api/1.2/patches/49267/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fd4ad7a1-565d-12ea-c7e0-744d35d77aa6@suse.com/","msgid":"","list_archive_url":null,"date":"2023-01-27T11:35:33","name":"[2/3] x86-64: respect {nooptimize} when building VEX prefix","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fd4ad7a1-565d-12ea-c7e0-744d35d77aa6@suse.com/mbox/"},{"id":49268,"url":"https://patchwork.plctlab.org/api/1.2/patches/49268/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/44b896ee-5b03-1ed6-bda2-8cffec382810@suse.com/","msgid":"<44b896ee-5b03-1ed6-bda2-8cffec382810@suse.com>","list_archive_url":null,"date":"2023-01-27T11:36:02","name":"[3/3] x86: drop LOCK from XCHG when optimizing","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/44b896ee-5b03-1ed6-bda2-8cffec382810@suse.com/mbox/"},{"id":49386,"url":"https://patchwork.plctlab.org/api/1.2/patches/49386/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/dc521fdd-1462-0a4e-6d8e-5fa3f35c82b5@suse.com/","msgid":"","list_archive_url":null,"date":"2023-01-27T13:14:44","name":"RISC-V: don'\''t disassemble unrecognized insns as .byte","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/dc521fdd-1462-0a4e-6d8e-5fa3f35c82b5@suse.com/mbox/"},{"id":50004,"url":"https://patchwork.plctlab.org/api/1.2/patches/50004/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230129153207.944175-1-dimitar@dinux.eu/","msgid":"<20230129153207.944175-1-dimitar@dinux.eu>","list_archive_url":null,"date":"2023-01-29T15:32:06","name":"[1/2] ld: pru: Merge the bss input sections into data","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230129153207.944175-1-dimitar@dinux.eu/mbox/"},{"id":50008,"url":"https://patchwork.plctlab.org/api/1.2/patches/50008/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230129153820.944711-1-dimitar@dinux.eu/","msgid":"<20230129153820.944711-1-dimitar@dinux.eu>","list_archive_url":null,"date":"2023-01-29T15:38:20","name":"[2/2] ld: pru: Add optional section alignments","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230129153820.944711-1-dimitar@dinux.eu/mbox/"},{"id":50144,"url":"https://patchwork.plctlab.org/api/1.2/patches/50144/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c72a27dfcb254b72e542f3a292b387b16add7ef7.1675060487.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2023-01-30T06:35:29","name":"[v2,1/1] RISC-V: Add platform property/capability extensions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c72a27dfcb254b72e542f3a292b387b16add7ef7.1675060487.git.research_trasio@irq.a4lg.com/mbox/"},{"id":50162,"url":"https://patchwork.plctlab.org/api/1.2/patches/50162/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3d42328e6f41cce145063883e5a9f513f4570840.1675062682.git.research_trasio@irq.a4lg.com/","msgid":"<3d42328e6f41cce145063883e5a9f513f4570840.1675062682.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2023-01-30T07:11:31","name":"[v3,1/1] RISC-V: Add platform property/capability extensions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3d42328e6f41cce145063883e5a9f513f4570840.1675062682.git.research_trasio@irq.a4lg.com/mbox/"},{"id":50300,"url":"https://patchwork.plctlab.org/api/1.2/patches/50300/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b61869e7-8fd3-2bec-da2b-046066edc3f3@suse.com/","msgid":"","list_archive_url":null,"date":"2023-01-30T14:07:20","name":"[v2] RISC-V: make C-extension JAL available again for (32-bit) assembly","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b61869e7-8fd3-2bec-da2b-046066edc3f3@suse.com/mbox/"},{"id":50324,"url":"https://patchwork.plctlab.org/api/1.2/patches/50324/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ef8afeef-b35f-348c-7d4c-bac8081e9952@suse.com/","msgid":"","list_archive_url":null,"date":"2023-01-30T14:40:38","name":"[v2] RISC-V: don'\''t disassemble unrecognized insns as .byte","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ef8afeef-b35f-348c-7d4c-bac8081e9952@suse.com/mbox/"},{"id":50325,"url":"https://patchwork.plctlab.org/api/1.2/patches/50325/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/95d700d49f5cdd2239c44ec17dadd11652f7be93.1675091147.git.aburgess@redhat.com/","msgid":"<95d700d49f5cdd2239c44ec17dadd11652f7be93.1675091147.git.aburgess@redhat.com>","list_archive_url":null,"date":"2023-01-30T15:11:41","name":"gas/ppc: Additional tests for DFP instructions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/95d700d49f5cdd2239c44ec17dadd11652f7be93.1675091147.git.aburgess@redhat.com/mbox/"},{"id":50492,"url":"https://patchwork.plctlab.org/api/1.2/patches/50492/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230130210642.7579-1-palmer@rivosinc.com/","msgid":"<20230130210642.7579-1-palmer@rivosinc.com>","list_archive_url":null,"date":"2023-01-30T21:06:41","name":"[1/2] gas: RISC-V: Add a test for near->far branch conversion","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230130210642.7579-1-palmer@rivosinc.com/mbox/"},{"id":50493,"url":"https://patchwork.plctlab.org/api/1.2/patches/50493/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230130210642.7579-2-palmer@rivosinc.com/","msgid":"<20230130210642.7579-2-palmer@rivosinc.com>","list_archive_url":null,"date":"2023-01-30T21:06:42","name":"[2/2] ld: RISC-V: Test R_RISCV_BRANCH truncation errors","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230130210642.7579-2-palmer@rivosinc.com/mbox/"},{"id":50594,"url":"https://patchwork.plctlab.org/api/1.2/patches/50594/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y9id+58ffnaAfImy@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-01-31T04:50:03","name":"testsuite XPASSes","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y9id+58ffnaAfImy@squeak.grove.modra.org/mbox/"},{"id":50595,"url":"https://patchwork.plctlab.org/api/1.2/patches/50595/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y9ieVWMZ5oxFqZJJ@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-01-31T04:51:33","name":"PR30060, ASAN error in bfd_cache_close","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y9ieVWMZ5oxFqZJJ@squeak.grove.modra.org/mbox/"},{"id":50596,"url":"https://patchwork.plctlab.org/api/1.2/patches/50596/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y9iegPmzz6ZQLXCO@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-01-31T04:52:16","name":"Silence ubsan warning about 1<<31","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y9iegPmzz6ZQLXCO@squeak.grove.modra.org/mbox/"},{"id":50784,"url":"https://patchwork.plctlab.org/api/1.2/patches/50784/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230131114257.4585-1-tdevries@suse.de/","msgid":"<20230131114257.4585-1-tdevries@suse.de>","list_archive_url":null,"date":"2023-01-31T11:42:57","name":"[gas] Emit v2 .debug_line for -gdwarf-2","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230131114257.4585-1-tdevries@suse.de/mbox/"}],"public":true,"mbox":"https://patchwork.plctlab.org/bundle/patchwork-bot/binutils-gdb_2023-01/mbox/"},{"id":16,"url":"https://patchwork.plctlab.org/api/1.2/bundles/16/","web_url":"https://patchwork.plctlab.org/bundle/patchwork-bot/binutils-gdb_2023-02/","project":{"id":2,"url":"https://patchwork.plctlab.org/api/1.2/projects/2/","name":"binutils-gdb","link_name":"binutils-gdb","list_id":"binutils.sourceware.org","list_email":"binutils@sourceware.org","web_url":"https://github.com/wangliu-iscas/Patchwork-Bundles/blob/main/binutils-gdb.md","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"name":"binutils-gdb_2023-02","owner":{"id":3,"url":"https://patchwork.plctlab.org/api/1.2/users/3/","username":"patchwork-bot","first_name":"","last_name":"","email":"ouuuleilei@gmail.com"},"patches":[{"id":51097,"url":"https://patchwork.plctlab.org/api/1.2/patches/51097/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230131233429.3708328-2-indu.bhagat@oracle.com/","msgid":"<20230131233429.3708328-2-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-01-31T23:34:25","name":"[1/5] libsframe/doc: use \"stack trace\" instead of \"unwind\" for SFrame","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230131233429.3708328-2-indu.bhagat@oracle.com/mbox/"},{"id":51096,"url":"https://patchwork.plctlab.org/api/1.2/patches/51096/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230131233429.3708328-3-indu.bhagat@oracle.com/","msgid":"<20230131233429.3708328-3-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-01-31T23:34:26","name":"[2/5] sframe: use \"stack trace\" instead of \"unwind\" for SFrame","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230131233429.3708328-3-indu.bhagat@oracle.com/mbox/"},{"id":51099,"url":"https://patchwork.plctlab.org/api/1.2/patches/51099/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230131233429.3708328-4-indu.bhagat@oracle.com/","msgid":"<20230131233429.3708328-4-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-01-31T23:34:27","name":"[3/5] gas: use \"stack trace\" instead of \"unwind\" for SFrame","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230131233429.3708328-4-indu.bhagat@oracle.com/mbox/"},{"id":51098,"url":"https://patchwork.plctlab.org/api/1.2/patches/51098/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230131233429.3708328-5-indu.bhagat@oracle.com/","msgid":"<20230131233429.3708328-5-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-01-31T23:34:28","name":"[4/5] bfd: use \"stack trace\" instead of \"unwind\" for SFrame","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230131233429.3708328-5-indu.bhagat@oracle.com/mbox/"},{"id":51100,"url":"https://patchwork.plctlab.org/api/1.2/patches/51100/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230131233429.3708328-6-indu.bhagat@oracle.com/","msgid":"<20230131233429.3708328-6-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-01-31T23:34:29","name":"[5/5] ld/doc: use \"stack trace\" instead of \"unwind\" for SFrame","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230131233429.3708328-6-indu.bhagat@oracle.com/mbox/"},{"id":51183,"url":"https://patchwork.plctlab.org/api/1.2/patches/51183/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y9oIhhJR9qaUEmFI@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-02-01T06:36:54","name":"Recursion in as_info_where","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y9oIhhJR9qaUEmFI@squeak.grove.modra.org/mbox/"},{"id":51254,"url":"https://patchwork.plctlab.org/api/1.2/patches/51254/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/87lelhzpg3.fsf@redhat.com/","msgid":"<87lelhzpg3.fsf@redhat.com>","list_archive_url":null,"date":"2023-02-01T09:48:28","name":"Fix sanitization warning message building gas.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/87lelhzpg3.fsf@redhat.com/mbox/"},{"id":51529,"url":"https://patchwork.plctlab.org/api/1.2/patches/51529/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/patch-16852-tamar@arm.com/","msgid":"","list_archive_url":null,"date":"2023-02-01T19:25:23","name":"[Binutils] AArch64 gas: relax ordering constriants on enabling and disabling feature extensions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/patch-16852-tamar@arm.com/mbox/"},{"id":51590,"url":"https://patchwork.plctlab.org/api/1.2/patches/51590/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y9rrfysbgq2B456K@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-02-01T22:45:19","name":"gas obj_end","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y9rrfysbgq2B456K@squeak.grove.modra.org/mbox/"},{"id":51591,"url":"https://patchwork.plctlab.org/api/1.2/patches/51591/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y9rrosJRMXXJwzAo@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-02-01T22:45:54","name":"obj-elf.h BYTES_IN_WORD","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y9rrosJRMXXJwzAo@squeak.grove.modra.org/mbox/"},{"id":51640,"url":"https://patchwork.plctlab.org/api/1.2/patches/51640/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y9spf1UfzfEL5hKO@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-02-02T03:09:51","name":"ld-elf/merge test update","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y9spf1UfzfEL5hKO@squeak.grove.modra.org/mbox/"},{"id":51936,"url":"https://patchwork.plctlab.org/api/1.2/patches/51936/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230202140811.20373-1-tdevries@suse.de/","msgid":"<20230202140811.20373-1-tdevries@suse.de>","list_archive_url":null,"date":"2023-02-02T14:08:11","name":"[pushed,gas] Update .loc syntax comment in dwarf2dbg.c","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230202140811.20373-1-tdevries@suse.de/mbox/"},{"id":52314,"url":"https://patchwork.plctlab.org/api/1.2/patches/52314/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y9yeZbU4atFWrl5i@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-02-03T05:40:53","name":"Add ECOFF Symbolic Header sanity checks","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y9yeZbU4atFWrl5i@squeak.grove.modra.org/mbox/"},{"id":52352,"url":"https://patchwork.plctlab.org/api/1.2/patches/52352/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/06804163-be78-6130-b082-71661e50e876@suse.com/","msgid":"<06804163-be78-6130-b082-71661e50e876@suse.com>","list_archive_url":null,"date":"2023-02-03T07:32:13","name":"[1/3] x86: improve special casing of certain insns","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/06804163-be78-6130-b082-71661e50e876@suse.com/mbox/"},{"id":52353,"url":"https://patchwork.plctlab.org/api/1.2/patches/52353/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/645a01e0-8acf-f55d-1f5a-c9e8bbb1d10f@suse.com/","msgid":"<645a01e0-8acf-f55d-1f5a-c9e8bbb1d10f@suse.com>","list_archive_url":null,"date":"2023-02-03T07:32:33","name":"[2/3] x86: simplify a few expressions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/645a01e0-8acf-f55d-1f5a-c9e8bbb1d10f@suse.com/mbox/"},{"id":52354,"url":"https://patchwork.plctlab.org/api/1.2/patches/52354/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8aa94a23-664f-f3ed-fa90-2e0cfa963bd0@suse.com/","msgid":"<8aa94a23-664f-f3ed-fa90-2e0cfa963bd0@suse.com>","list_archive_url":null,"date":"2023-02-03T07:33:44","name":"[3/3] x86: move (and rename) opcodespace attribute","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8aa94a23-664f-f3ed-fa90-2e0cfa963bd0@suse.com/mbox/"},{"id":52367,"url":"https://patchwork.plctlab.org/api/1.2/patches/52367/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/573dd630-a3ca-52c6-846a-d7d18a7e3d52@suse.com/","msgid":"<573dd630-a3ca-52c6-846a-d7d18a7e3d52@suse.com>","list_archive_url":null,"date":"2023-02-03T07:44:56","name":"[1/3] x86: limit use of XOP2SOURCES","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/573dd630-a3ca-52c6-846a-d7d18a7e3d52@suse.com/mbox/"},{"id":52368,"url":"https://patchwork.plctlab.org/api/1.2/patches/52368/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/03deb7fa-cc01-a049-965e-4ee534aadc35@suse.com/","msgid":"<03deb7fa-cc01-a049-965e-4ee534aadc35@suse.com>","list_archive_url":null,"date":"2023-02-03T07:45:51","name":"[2/3] x86: drop use of XOP2SOURCES","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/03deb7fa-cc01-a049-965e-4ee534aadc35@suse.com/mbox/"},{"id":52370,"url":"https://patchwork.plctlab.org/api/1.2/patches/52370/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1364c0e8-5e91-4a92-c14c-072b2a1edf6d@suse.com/","msgid":"<1364c0e8-5e91-4a92-c14c-072b2a1edf6d@suse.com>","list_archive_url":null,"date":"2023-02-03T07:46:45","name":"[3/3] x86: drop use of VEX3SOURCES","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1364c0e8-5e91-4a92-c14c-072b2a1edf6d@suse.com/mbox/"},{"id":53113,"url":"https://patchwork.plctlab.org/api/1.2/patches/53113/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y+DKOkv+GiK5JKLG@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-02-06T09:36:58","name":"Resetting section vma after _bfd_dwarf2_find_nearest_line","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y+DKOkv+GiK5JKLG@squeak.grove.modra.org/mbox/"},{"id":53214,"url":"https://patchwork.plctlab.org/api/1.2/patches/53214/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y+DzhUGfFBaLPJiD@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-02-06T12:33:09","name":"Protect mips_hi16_list from fuzzed debug info","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y+DzhUGfFBaLPJiD@squeak.grove.modra.org/mbox/"},{"id":53216,"url":"https://patchwork.plctlab.org/api/1.2/patches/53216/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y+D0PyRzBoWRnzLq@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-02-06T12:36:15","name":"ppc32 and \"LOAD segment with RWX permissions\"","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y+D0PyRzBoWRnzLq@squeak.grove.modra.org/mbox/"},{"id":53418,"url":"https://patchwork.plctlab.org/api/1.2/patches/53418/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/BLAPR10MB52986899D13C84F0505C23CEABDA9@BLAPR10MB5298.namprd10.prod.outlook.com/","msgid":"","list_archive_url":null,"date":"2023-02-06T16:37:29","name":"gprofng SIGSEGV when processing unusual dwarf","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/BLAPR10MB52986899D13C84F0505C23CEABDA9@BLAPR10MB5298.namprd10.prod.outlook.com/mbox/"},{"id":53591,"url":"https://patchwork.plctlab.org/api/1.2/patches/53591/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230207015340.2021329-1-vladimir.mezentsev@oracle.com/","msgid":"<20230207015340.2021329-1-vladimir.mezentsev@oracle.com>","list_archive_url":null,"date":"2023-02-07T01:53:40","name":"gprofng: fix SIGSEGV when processing unusual dwarf","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230207015340.2021329-1-vladimir.mezentsev@oracle.com/mbox/"},{"id":53606,"url":"https://patchwork.plctlab.org/api/1.2/patches/53606/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230207024424.4000862-1-yunqiang.su@cipunited.com/","msgid":"<20230207024424.4000862-1-yunqiang.su@cipunited.com>","list_archive_url":null,"date":"2023-02-07T02:44:24","name":"MIPS: allow link o32 objects with mach mips64r6 and mips32r6","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230207024424.4000862-1-yunqiang.su@cipunited.com/mbox/"},{"id":54238,"url":"https://patchwork.plctlab.org/api/1.2/patches/54238/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230208071725.3668898-2-tom@tromey.com/","msgid":"<20230208071725.3668898-2-tom@tromey.com>","list_archive_url":null,"date":"2023-02-08T07:17:18","name":"[1/8] Remove H_CFLAGS from doc/local.mk","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230208071725.3668898-2-tom@tromey.com/mbox/"},{"id":54231,"url":"https://patchwork.plctlab.org/api/1.2/patches/54231/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230208071725.3668898-3-tom@tromey.com/","msgid":"<20230208071725.3668898-3-tom@tromey.com>","list_archive_url":null,"date":"2023-02-08T07:17:19","name":"[2/8] Simplify @node use in BFD documentation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230208071725.3668898-3-tom@tromey.com/mbox/"},{"id":54222,"url":"https://patchwork.plctlab.org/api/1.2/patches/54222/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230208071725.3668898-4-tom@tromey.com/","msgid":"<20230208071725.3668898-4-tom@tromey.com>","list_archive_url":null,"date":"2023-02-08T07:17:20","name":"[3/8] Add copyright headers to the .str files","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230208071725.3668898-4-tom@tromey.com/mbox/"},{"id":54226,"url":"https://patchwork.plctlab.org/api/1.2/patches/54226/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230208071725.3668898-5-tom@tromey.com/","msgid":"<20230208071725.3668898-5-tom@tromey.com>","list_archive_url":null,"date":"2023-02-08T07:17:21","name":"[4/8] Remove the paramstuff word","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230208071725.3668898-5-tom@tromey.com/mbox/"},{"id":54223,"url":"https://patchwork.plctlab.org/api/1.2/patches/54223/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230208071725.3668898-6-tom@tromey.com/","msgid":"<20230208071725.3668898-6-tom@tromey.com>","list_archive_url":null,"date":"2023-02-08T07:17:22","name":"[5/8] Use intptr_t rather than long in chew","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230208071725.3668898-6-tom@tromey.com/mbox/"},{"id":54232,"url":"https://patchwork.plctlab.org/api/1.2/patches/54232/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230208071725.3668898-7-tom@tromey.com/","msgid":"<20230208071725.3668898-7-tom@tromey.com>","list_archive_url":null,"date":"2023-02-08T07:17:23","name":"[6/8] Change internalmode to be an intrinsic variable","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230208071725.3668898-7-tom@tromey.com/mbox/"},{"id":54235,"url":"https://patchwork.plctlab.org/api/1.2/patches/54235/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230208071725.3668898-8-tom@tromey.com/","msgid":"<20230208071725.3668898-8-tom@tromey.com>","list_archive_url":null,"date":"2023-02-08T07:17:24","name":"[7/8] Use @deftypefn in chew output","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230208071725.3668898-8-tom@tromey.com/mbox/"},{"id":54227,"url":"https://patchwork.plctlab.org/api/1.2/patches/54227/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230208071725.3668898-9-tom@tromey.com/","msgid":"<20230208071725.3668898-9-tom@tromey.com>","list_archive_url":null,"date":"2023-02-08T07:17:25","name":"[8/8] Remove RETURNS from BFD chew comments","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230208071725.3668898-9-tom@tromey.com/mbox/"},{"id":54632,"url":"https://patchwork.plctlab.org/api/1.2/patches/54632/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y+QsUGAY7LQw0zQu@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-02-08T23:12:16","name":"Internal error at gas/expr.c:1814","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y+QsUGAY7LQw0zQu@squeak.grove.modra.org/mbox/"},{"id":54633,"url":"https://patchwork.plctlab.org/api/1.2/patches/54633/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y+QsheSWZko4+7vV@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-02-08T23:13:09","name":"Clear cached file size when bfd changed to BFD_IN_MEMORY","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y+QsheSWZko4+7vV@squeak.grove.modra.org/mbox/"},{"id":54634,"url":"https://patchwork.plctlab.org/api/1.2/patches/54634/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y+QsoGbCT4Ei4rlW@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-02-08T23:13:36","name":"Memory leak in bfd_init_section_compress_status","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y+QsoGbCT4Ei4rlW@squeak.grove.modra.org/mbox/"},{"id":54635,"url":"https://patchwork.plctlab.org/api/1.2/patches/54635/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y+QszzU2zl+ApZy4@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-02-08T23:14:23","name":"coff-sh.c keep_relocs, keep_contents and keep_syms","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y+QszzU2zl+ApZy4@squeak.grove.modra.org/mbox/"},{"id":54823,"url":"https://patchwork.plctlab.org/api/1.2/patches/54823/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y+S/4ej6hbSlHWUj@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-02-09T09:41:53","name":"coff keep_relocs and keep_contents","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y+S/4ej6hbSlHWUj@squeak.grove.modra.org/mbox/"},{"id":55093,"url":"https://patchwork.plctlab.org/api/1.2/patches/55093/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230209205040.1286063-1-tromey@adacore.com/","msgid":"<20230209205040.1286063-1-tromey@adacore.com>","list_archive_url":null,"date":"2023-02-09T20:50:40","name":"[pushed] Add full display feature to dwarf-mode.el","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230209205040.1286063-1-tromey@adacore.com/mbox/"},{"id":55172,"url":"https://patchwork.plctlab.org/api/1.2/patches/55172/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y+WWbsUP6DBus1sD@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-02-10T00:57:18","name":"objcopy of mach-o indirect symbols","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y+WWbsUP6DBus1sD@squeak.grove.modra.org/mbox/"},{"id":55284,"url":"https://patchwork.plctlab.org/api/1.2/patches/55284/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y+X07Mh4TUJM0qoV@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-02-10T07:40:28","name":"Local label checks in integer_constant","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y+X07Mh4TUJM0qoV@squeak.grove.modra.org/mbox/"},{"id":55314,"url":"https://patchwork.plctlab.org/api/1.2/patches/55314/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1d6f89f5-0e6e-6a8b-3a93-41dd26d09c0a@suse.com/","msgid":"<1d6f89f5-0e6e-6a8b-3a93-41dd26d09c0a@suse.com>","list_archive_url":null,"date":"2023-02-10T08:36:05","name":"[1/2] x86: optimize BT{,C,R,S} $imm,%reg","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1d6f89f5-0e6e-6a8b-3a93-41dd26d09c0a@suse.com/mbox/"},{"id":55315,"url":"https://patchwork.plctlab.org/api/1.2/patches/55315/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/58de4278-3b30-1e3b-f2da-551c47bca681@suse.com/","msgid":"<58de4278-3b30-1e3b-f2da-551c47bca681@suse.com>","list_archive_url":null,"date":"2023-02-10T08:36:40","name":"[2/2] x86: restrict insn templates accepting negative 8-bit immediates","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/58de4278-3b30-1e3b-f2da-551c47bca681@suse.com/mbox/"},{"id":55317,"url":"https://patchwork.plctlab.org/api/1.2/patches/55317/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b0c44651-1f3f-46c6-09ff-c12bf6026bdc@suse.com/","msgid":"","list_archive_url":null,"date":"2023-02-10T08:48:39","name":"[1/4] x86-64: LAR and LSL don'\''t need REX.W","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b0c44651-1f3f-46c6-09ff-c12bf6026bdc@suse.com/mbox/"},{"id":55318,"url":"https://patchwork.plctlab.org/api/1.2/patches/55318/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/623497d9-1367-d446-1cce-f9b0fe177699@suse.com/","msgid":"<623497d9-1367-d446-1cce-f9b0fe177699@suse.com>","list_archive_url":null,"date":"2023-02-10T08:49:18","name":"[2/4] x86: have insns acting on segment selector values allow for consistent operands","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/623497d9-1367-d446-1cce-f9b0fe177699@suse.com/mbox/"},{"id":55319,"url":"https://patchwork.plctlab.org/api/1.2/patches/55319/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3ab09feb-290d-693d-b43f-237022f3f6aa@suse.com/","msgid":"<3ab09feb-290d-693d-b43f-237022f3f6aa@suse.com>","list_archive_url":null,"date":"2023-02-10T08:50:25","name":"[3/4] x86-64: don'\''t permit LAHF/SAHF with \"generic64\"","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3ab09feb-290d-693d-b43f-237022f3f6aa@suse.com/mbox/"},{"id":55320,"url":"https://patchwork.plctlab.org/api/1.2/patches/55320/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/67715baf-b718-0d00-959a-fc4e70c0dff9@suse.com/","msgid":"<67715baf-b718-0d00-959a-fc4e70c0dff9@suse.com>","list_archive_url":null,"date":"2023-02-10T08:51:42","name":"[4/4] x86: MONITOR/MWAIT are not SSE3 insns","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/67715baf-b718-0d00-959a-fc4e70c0dff9@suse.com/mbox/"},{"id":55325,"url":"https://patchwork.plctlab.org/api/1.2/patches/55325/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d6e6f04a-d7d2-fffc-1672-89356d00888c@suse.com/","msgid":"","list_archive_url":null,"date":"2023-02-10T08:53:47","name":"x86: allow to request ModR/M encoding","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d6e6f04a-d7d2-fffc-1672-89356d00888c@suse.com/mbox/"},{"id":55358,"url":"https://patchwork.plctlab.org/api/1.2/patches/55358/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y+YW49ew8TrVHIVE@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-02-10T10:05:23","name":"Fix mmo memory leaks","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y+YW49ew8TrVHIVE@squeak.grove.modra.org/mbox/"},{"id":55383,"url":"https://patchwork.plctlab.org/api/1.2/patches/55383/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/26a512cf3d23fca9a71d4328d554f640d080e8a8.1676025351.git.research_trasio@irq.a4lg.com/","msgid":"<26a512cf3d23fca9a71d4328d554f640d080e8a8.1676025351.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2023-02-10T10:37:22","name":"RISC-V: Reduce effective linker relaxation passses","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/26a512cf3d23fca9a71d4328d554f640d080e8a8.1676025351.git.research_trasio@irq.a4lg.com/mbox/"},{"id":55502,"url":"https://patchwork.plctlab.org/api/1.2/patches/55502/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230210174404.3763-2-binutils@emagii.com/","msgid":"<20230210174404.3763-2-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-10T17:44:01","name":"[1/4] ldlex.l: Add ASCIZ token","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230210174404.3763-2-binutils@emagii.com/mbox/"},{"id":55503,"url":"https://patchwork.plctlab.org/api/1.2/patches/55503/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230210174404.3763-3-binutils@emagii.com/","msgid":"<20230210174404.3763-3-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-10T17:44:02","name":"[2/4] ldgram.y: Add '\''ASCIZ '\'' command","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230210174404.3763-3-binutils@emagii.com/mbox/"},{"id":55504,"url":"https://patchwork.plctlab.org/api/1.2/patches/55504/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230210174404.3763-4-binutils@emagii.com/","msgid":"<20230210174404.3763-4-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-10T17:44:03","name":"[3/4] Parse ASCIZ command","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230210174404.3763-4-binutils@emagii.com/mbox/"},{"id":55505,"url":"https://patchwork.plctlab.org/api/1.2/patches/55505/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230210174404.3763-5-binutils@emagii.com/","msgid":"<20230210174404.3763-5-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-10T17:44:04","name":"[4/4] Document the ASCIZ command","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230210174404.3763-5-binutils@emagii.com/mbox/"},{"id":55698,"url":"https://patchwork.plctlab.org/api/1.2/patches/55698/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y+cxtbhMXNT350aU@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-02-11T06:12:05","name":".debug sections without contents","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y+cxtbhMXNT350aU@squeak.grove.modra.org/mbox/"},{"id":55699,"url":"https://patchwork.plctlab.org/api/1.2/patches/55699/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y+cyCbQkCFHOPzaA@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-02-11T06:13:29","name":"objdump -D of bss sections and -s with -j","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y+cyCbQkCFHOPzaA@squeak.grove.modra.org/mbox/"},{"id":55977,"url":"https://patchwork.plctlab.org/api/1.2/patches/55977/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y+lm2hoJrZN/I1OO@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-02-12T22:23:22","name":"objcopy memory leaks","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y+lm2hoJrZN/I1OO@squeak.grove.modra.org/mbox/"},{"id":56071,"url":"https://patchwork.plctlab.org/api/1.2/patches/56071/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5003cbd5-448c-7f39-5219-ae3bfe50504f@suse.com/","msgid":"<5003cbd5-448c-7f39-5219-ae3bfe50504f@suse.com>","list_archive_url":null,"date":"2023-02-13T08:02:36","name":"[1/2] RISC-V: test for expected / no unexpected symbols","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5003cbd5-448c-7f39-5219-ae3bfe50504f@suse.com/mbox/"},{"id":56072,"url":"https://patchwork.plctlab.org/api/1.2/patches/56072/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3bb126f6-5bf1-dab0-f540-25c386b9507e@suse.com/","msgid":"<3bb126f6-5bf1-dab0-f540-25c386b9507e@suse.com>","list_archive_url":null,"date":"2023-02-13T08:02:58","name":"[2/2] RISC-V: adjust logic to avoid register name symbols","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3bb126f6-5bf1-dab0-f540-25c386b9507e@suse.com/mbox/"},{"id":56078,"url":"https://patchwork.plctlab.org/api/1.2/patches/56078/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/09ff32c5-3ebc-dda1-2eb5-be7851cb7c66@suse.com/","msgid":"<09ff32c5-3ebc-dda1-2eb5-be7851cb7c66@suse.com>","list_archive_url":null,"date":"2023-02-13T08:12:12","name":"[1/2] Arm64/gas: add missing prereq features","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/09ff32c5-3ebc-dda1-2eb5-be7851cb7c66@suse.com/mbox/"},{"id":56080,"url":"https://patchwork.plctlab.org/api/1.2/patches/56080/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c1e56cb2-a33f-59fd-a431-6a27460525cf@suse.com/","msgid":"","list_archive_url":null,"date":"2023-02-13T08:12:45","name":"[2/2] Arm64/gas: drop redundant feature prereqs","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c1e56cb2-a33f-59fd-a431-6a27460525cf@suse.com/mbox/"},{"id":56081,"url":"https://patchwork.plctlab.org/api/1.2/patches/56081/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/08d262e3-c736-85ff-c45e-db96e55cff4c@suse.com/","msgid":"<08d262e3-c736-85ff-c45e-db96e55cff4c@suse.com>","list_archive_url":null,"date":"2023-02-13T08:15:36","name":"gas: improve interaction between read_a_source_file() and s_linefile()","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/08d262e3-c736-85ff-c45e-db96e55cff4c@suse.com/mbox/"},{"id":56098,"url":"https://patchwork.plctlab.org/api/1.2/patches/56098/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8c7753dd-a5f5-f994-88ee-d4e053a20bc0@suse.com/","msgid":"<8c7753dd-a5f5-f994-88ee-d4e053a20bc0@suse.com>","list_archive_url":null,"date":"2023-02-13T08:42:20","name":"x86: {LD,ST}TILECFG use an extension opcode","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8c7753dd-a5f5-f994-88ee-d4e053a20bc0@suse.com/mbox/"},{"id":56162,"url":"https://patchwork.plctlab.org/api/1.2/patches/56162/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y+oSap1kQICg3JMp@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-02-13T10:35:22","name":"Split off gas init to functions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y+oSap1kQICg3JMp@squeak.grove.modra.org/mbox/"},{"id":56164,"url":"https://patchwork.plctlab.org/api/1.2/patches/56164/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y+oSkktwhytmt7rZ@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-02-13T10:36:02","name":"stabs.c static state","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y+oSkktwhytmt7rZ@squeak.grove.modra.org/mbox/"},{"id":56261,"url":"https://patchwork.plctlab.org/api/1.2/patches/56261/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230213122241.6144-2-binutils@emagii.com/","msgid":"<20230213122241.6144-2-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-13T12:22:37","name":"[v2,1/5] ldlex.l: Add ASCIZ token","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230213122241.6144-2-binutils@emagii.com/mbox/"},{"id":56262,"url":"https://patchwork.plctlab.org/api/1.2/patches/56262/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230213122241.6144-3-binutils@emagii.com/","msgid":"<20230213122241.6144-3-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-13T12:22:38","name":"[v2,2/5] ldgram.y: Add '\''ASCIZ '\'' command","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230213122241.6144-3-binutils@emagii.com/mbox/"},{"id":56263,"url":"https://patchwork.plctlab.org/api/1.2/patches/56263/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230213122241.6144-4-binutils@emagii.com/","msgid":"<20230213122241.6144-4-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-13T12:22:39","name":"[v2,3/5] Parse ASCIZ command","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230213122241.6144-4-binutils@emagii.com/mbox/"},{"id":56264,"url":"https://patchwork.plctlab.org/api/1.2/patches/56264/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230213122241.6144-5-binutils@emagii.com/","msgid":"<20230213122241.6144-5-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-13T12:22:40","name":"[v2,4/5] Document the ASCIZ command","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230213122241.6144-5-binutils@emagii.com/mbox/"},{"id":56265,"url":"https://patchwork.plctlab.org/api/1.2/patches/56265/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230213122241.6144-6-binutils@emagii.com/","msgid":"<20230213122241.6144-6-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-13T12:22:41","name":"[v2,5/5] Use lang_add_data","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230213122241.6144-6-binutils@emagii.com/mbox/"},{"id":56267,"url":"https://patchwork.plctlab.org/api/1.2/patches/56267/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y+ovRotGLLHQE09t@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-02-13T12:38:30","name":"_bfd_ecoff_slurp_symbol_table buffer overflow","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y+ovRotGLLHQE09t@squeak.grove.modra.org/mbox/"},{"id":56279,"url":"https://patchwork.plctlab.org/api/1.2/patches/56279/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.LSU.2.20.2302131301550.29328@wotan.suse.de/","msgid":"","list_archive_url":null,"date":"2023-02-13T13:04:14","name":"[obvious] Fix PR30079: abort on mingw","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.LSU.2.20.2302131301550.29328@wotan.suse.de/mbox/"},{"id":56293,"url":"https://patchwork.plctlab.org/api/1.2/patches/56293/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230213133949.3773320-2-christoph.muellner@vrull.eu/","msgid":"<20230213133949.3773320-2-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2023-02-13T13:39:42","name":"[RFC,v3,1/8] RISC-V: Add Zvkb ISA extension support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230213133949.3773320-2-christoph.muellner@vrull.eu/mbox/"},{"id":56296,"url":"https://patchwork.plctlab.org/api/1.2/patches/56296/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230213133949.3773320-3-christoph.muellner@vrull.eu/","msgid":"<20230213133949.3773320-3-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2023-02-13T13:39:43","name":"[RFC,v3,2/8] RISC-V: Add Zvkg ISA extension support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230213133949.3773320-3-christoph.muellner@vrull.eu/mbox/"},{"id":56297,"url":"https://patchwork.plctlab.org/api/1.2/patches/56297/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230213133949.3773320-4-christoph.muellner@vrull.eu/","msgid":"<20230213133949.3773320-4-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2023-02-13T13:39:44","name":"[RFC,v3,3/8] RISC-V: Add Zvkned ISA extension support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230213133949.3773320-4-christoph.muellner@vrull.eu/mbox/"},{"id":56294,"url":"https://patchwork.plctlab.org/api/1.2/patches/56294/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230213133949.3773320-5-christoph.muellner@vrull.eu/","msgid":"<20230213133949.3773320-5-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2023-02-13T13:39:45","name":"[RFC,v3,4/8] RISC-V: Add Zvknh[a,b] ISA extension support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230213133949.3773320-5-christoph.muellner@vrull.eu/mbox/"},{"id":56298,"url":"https://patchwork.plctlab.org/api/1.2/patches/56298/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230213133949.3773320-6-christoph.muellner@vrull.eu/","msgid":"<20230213133949.3773320-6-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2023-02-13T13:39:46","name":"[RFC,v3,5/8] RISC-V: Add Zvkn ISA extension support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230213133949.3773320-6-christoph.muellner@vrull.eu/mbox/"},{"id":56300,"url":"https://patchwork.plctlab.org/api/1.2/patches/56300/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230213133949.3773320-7-christoph.muellner@vrull.eu/","msgid":"<20230213133949.3773320-7-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2023-02-13T13:39:47","name":"[RFC,v3,6/8] RISC-V: Add Zvksed ISA extension support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230213133949.3773320-7-christoph.muellner@vrull.eu/mbox/"},{"id":56295,"url":"https://patchwork.plctlab.org/api/1.2/patches/56295/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230213133949.3773320-8-christoph.muellner@vrull.eu/","msgid":"<20230213133949.3773320-8-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2023-02-13T13:39:48","name":"[RFC,v3,7/8] RISC-V: Add Zvksh ISA extension support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230213133949.3773320-8-christoph.muellner@vrull.eu/mbox/"},{"id":56299,"url":"https://patchwork.plctlab.org/api/1.2/patches/56299/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230213133949.3773320-9-christoph.muellner@vrull.eu/","msgid":"<20230213133949.3773320-9-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2023-02-13T13:39:49","name":"[RFC,v3,8/8] RISC-V: Add Zvks ISA extension support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230213133949.3773320-9-christoph.muellner@vrull.eu/mbox/"},{"id":56326,"url":"https://patchwork.plctlab.org/api/1.2/patches/56326/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2096ddec-287a-de42-a2f6-58293af2fd48@suse.com/","msgid":"<2096ddec-287a-de42-a2f6-58293af2fd48@suse.com>","list_archive_url":null,"date":"2023-02-13T14:54:00","name":"gas: correct symbol name comparison in .startof./.sizeof. handling","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2096ddec-287a-de42-a2f6-58293af2fd48@suse.com/mbox/"},{"id":56363,"url":"https://patchwork.plctlab.org/api/1.2/patches/56363/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230213161124.15340-2-binutils@emagii.com/","msgid":"<20230213161124.15340-2-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-13T16:11:19","name":"[v3,1/6] Document the ASCIZ command","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230213161124.15340-2-binutils@emagii.com/mbox/"},{"id":56366,"url":"https://patchwork.plctlab.org/api/1.2/patches/56366/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230213161124.15340-3-binutils@emagii.com/","msgid":"<20230213161124.15340-3-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-13T16:11:20","name":"[v3,2/6] Add ASCIZ to NEWS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230213161124.15340-3-binutils@emagii.com/mbox/"},{"id":56365,"url":"https://patchwork.plctlab.org/api/1.2/patches/56365/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230213161124.15340-4-binutils@emagii.com/","msgid":"<20230213161124.15340-4-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-13T16:11:21","name":"[v3,3/6] Add ASCIZ to testsuite","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230213161124.15340-4-binutils@emagii.com/mbox/"},{"id":56364,"url":"https://patchwork.plctlab.org/api/1.2/patches/56364/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230213161124.15340-5-binutils@emagii.com/","msgid":"<20230213161124.15340-5-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-13T16:11:22","name":"[v3,4/6] ldlex.l: Add ASCIZ token","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230213161124.15340-5-binutils@emagii.com/mbox/"},{"id":56367,"url":"https://patchwork.plctlab.org/api/1.2/patches/56367/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230213161124.15340-6-binutils@emagii.com/","msgid":"<20230213161124.15340-6-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-13T16:11:23","name":"[v3,5/6] ldgram.y: Add '\''ASCIZ '\'' command","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230213161124.15340-6-binutils@emagii.com/mbox/"},{"id":56368,"url":"https://patchwork.plctlab.org/api/1.2/patches/56368/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230213161124.15340-7-binutils@emagii.com/","msgid":"<20230213161124.15340-7-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-13T16:11:24","name":"[v3,6/6] Parse ASCIZ command","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230213161124.15340-7-binutils@emagii.com/mbox/"},{"id":56372,"url":"https://patchwork.plctlab.org/api/1.2/patches/56372/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230213162009.15515-2-binutils@emagii.com/","msgid":"<20230213162009.15515-2-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-13T16:20:04","name":"[v4,1/6] Document the ASCIZ command","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230213162009.15515-2-binutils@emagii.com/mbox/"},{"id":56369,"url":"https://patchwork.plctlab.org/api/1.2/patches/56369/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230213162009.15515-3-binutils@emagii.com/","msgid":"<20230213162009.15515-3-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-13T16:20:05","name":"[v4,2/6] Add ASCIZ to NEWS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230213162009.15515-3-binutils@emagii.com/mbox/"},{"id":56370,"url":"https://patchwork.plctlab.org/api/1.2/patches/56370/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230213162009.15515-4-binutils@emagii.com/","msgid":"<20230213162009.15515-4-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-13T16:20:06","name":"[v4,3/6] Add ASCIZ to testsuite","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230213162009.15515-4-binutils@emagii.com/mbox/"},{"id":56371,"url":"https://patchwork.plctlab.org/api/1.2/patches/56371/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230213162009.15515-5-binutils@emagii.com/","msgid":"<20230213162009.15515-5-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-13T16:20:07","name":"[v4,4/6] ldlex.l: Add ASCIZ token","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230213162009.15515-5-binutils@emagii.com/mbox/"},{"id":56373,"url":"https://patchwork.plctlab.org/api/1.2/patches/56373/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230213162009.15515-6-binutils@emagii.com/","msgid":"<20230213162009.15515-6-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-13T16:20:08","name":"[v4,5/6] ldgram.y: Add '\''ASCIZ '\'' command","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230213162009.15515-6-binutils@emagii.com/mbox/"},{"id":56404,"url":"https://patchwork.plctlab.org/api/1.2/patches/56404/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.LSU.2.20.2302131741480.29328@wotan.suse.de/","msgid":"","list_archive_url":null,"date":"2023-02-13T17:42:58","name":"PR30120: fix x87 fucomp misassembled","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.LSU.2.20.2302131741480.29328@wotan.suse.de/mbox/"},{"id":56662,"url":"https://patchwork.plctlab.org/api/1.2/patches/56662/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230214050633.28910-6-binutils@emagii.com/","msgid":"<20230214050633.28910-6-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-14T05:06:33","name":"[v4,6/6] Parse ASCIZ command","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230214050633.28910-6-binutils@emagii.com/mbox/"},{"id":57082,"url":"https://patchwork.plctlab.org/api/1.2/patches/57082/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b876de99-e433-61b6-1645-e026f6c9dd80@suse.com/","msgid":"","list_archive_url":null,"date":"2023-02-14T15:53:10","name":"gas: buffer_and_nest() needs to pass nul-terminated string to temp_ilp()","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b876de99-e433-61b6-1645-e026f6c9dd80@suse.com/mbox/"},{"id":57344,"url":"https://patchwork.plctlab.org/api/1.2/patches/57344/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y+xE0Fa4HqQq/1p0@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-02-15T02:34:56","name":"binutils stabs type list","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y+xE0Fa4HqQq/1p0@squeak.grove.modra.org/mbox/"},{"id":57373,"url":"https://patchwork.plctlab.org/api/1.2/patches/57373/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y+x2gNcp9REGOj8e@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-02-15T06:06:56","name":"More ecoff sanity checks","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y+x2gNcp9REGOj8e@squeak.grove.modra.org/mbox/"},{"id":57417,"url":"https://patchwork.plctlab.org/api/1.2/patches/57417/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/56cd41d5-c0ba-d076-bf09-06612a2b54c3@suse.com/","msgid":"<56cd41d5-c0ba-d076-bf09-06612a2b54c3@suse.com>","list_archive_url":null,"date":"2023-02-15T07:44:24","name":"x86/gas: replace inappropriate assertion when parsing registers","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/56cd41d5-c0ba-d076-bf09-06612a2b54c3@suse.com/mbox/"},{"id":57485,"url":"https://patchwork.plctlab.org/api/1.2/patches/57485/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y+zDOBCppQShhWzW@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-02-15T11:34:16","name":"objdump -G memory leak","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y+zDOBCppQShhWzW@squeak.grove.modra.org/mbox/"},{"id":57486,"url":"https://patchwork.plctlab.org/api/1.2/patches/57486/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y+zDasJ/lS/QXsxw@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-02-15T11:35:06","name":"objdump read_section_stabs","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y+zDasJ/lS/QXsxw@squeak.grove.modra.org/mbox/"},{"id":57497,"url":"https://patchwork.plctlab.org/api/1.2/patches/57497/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230215114052.28292-2-binutils@emagii.com/","msgid":"<20230215114052.28292-2-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-15T11:40:47","name":"[v0,1/6] Add testsuite for ASCII command","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230215114052.28292-2-binutils@emagii.com/mbox/"},{"id":57488,"url":"https://patchwork.plctlab.org/api/1.2/patches/57488/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230215114052.28292-3-binutils@emagii.com/","msgid":"<20230215114052.28292-3-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-15T11:40:48","name":"[v0,2/6] Add ASCII command info to NEWS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230215114052.28292-3-binutils@emagii.com/mbox/"},{"id":57498,"url":"https://patchwork.plctlab.org/api/1.2/patches/57498/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230215114052.28292-4-binutils@emagii.com/","msgid":"<20230215114052.28292-4-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-15T11:40:49","name":"[v0,3/6] Add ASCII to info file","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230215114052.28292-4-binutils@emagii.com/mbox/"},{"id":57499,"url":"https://patchwork.plctlab.org/api/1.2/patches/57499/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230215114052.28292-5-binutils@emagii.com/","msgid":"<20230215114052.28292-5-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-15T11:40:50","name":"[v0,4/6] ldlex.l: add ASCII","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230215114052.28292-5-binutils@emagii.com/mbox/"},{"id":57490,"url":"https://patchwork.plctlab.org/api/1.2/patches/57490/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230215114052.28292-6-binutils@emagii.com/","msgid":"<20230215114052.28292-6-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-15T11:40:51","name":"[v0,5/6] ldgram.y: add ASCII","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230215114052.28292-6-binutils@emagii.com/mbox/"},{"id":57491,"url":"https://patchwork.plctlab.org/api/1.2/patches/57491/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230215114052.28292-7-binutils@emagii.com/","msgid":"<20230215114052.28292-7-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-15T11:40:52","name":"[v0,6/6] ldlang.*: parse ASCII command","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230215114052.28292-7-binutils@emagii.com/mbox/"},{"id":57650,"url":"https://patchwork.plctlab.org/api/1.2/patches/57650/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230215180303.620184-2-i.swmail@xen0n.name/","msgid":"<20230215180303.620184-2-i.swmail@xen0n.name>","list_archive_url":null,"date":"2023-02-15T18:02:58","name":"[v4,1/6] LoongArch: support disassembling certain pseudo-instructions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230215180303.620184-2-i.swmail@xen0n.name/mbox/"},{"id":57649,"url":"https://patchwork.plctlab.org/api/1.2/patches/57649/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230215180303.620184-3-i.swmail@xen0n.name/","msgid":"<20230215180303.620184-3-i.swmail@xen0n.name>","list_archive_url":null,"date":"2023-02-15T18:02:59","name":"[v4,2/6] opcodes/loongarch: remove unused code","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230215180303.620184-3-i.swmail@xen0n.name/mbox/"},{"id":57652,"url":"https://patchwork.plctlab.org/api/1.2/patches/57652/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230215180303.620184-4-i.swmail@xen0n.name/","msgid":"<20230215180303.620184-4-i.swmail@xen0n.name>","list_archive_url":null,"date":"2023-02-15T18:03:00","name":"[v4,3/6] opcodes/loongarch: implement style support in the disassembler","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230215180303.620184-4-i.swmail@xen0n.name/mbox/"},{"id":57651,"url":"https://patchwork.plctlab.org/api/1.2/patches/57651/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230215180303.620184-5-i.swmail@xen0n.name/","msgid":"<20230215180303.620184-5-i.swmail@xen0n.name>","list_archive_url":null,"date":"2023-02-15T18:03:01","name":"[v4,4/6] opcodes/loongarch: style disassembled address offsets as such","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230215180303.620184-5-i.swmail@xen0n.name/mbox/"},{"id":57654,"url":"https://patchwork.plctlab.org/api/1.2/patches/57654/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230215180303.620184-6-i.swmail@xen0n.name/","msgid":"<20230215180303.620184-6-i.swmail@xen0n.name>","list_archive_url":null,"date":"2023-02-15T18:03:02","name":"[v4,5/6] opcodes/loongarch: do not print hex notation for signed immediates","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230215180303.620184-6-i.swmail@xen0n.name/mbox/"},{"id":57653,"url":"https://patchwork.plctlab.org/api/1.2/patches/57653/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230215180303.620184-7-i.swmail@xen0n.name/","msgid":"<20230215180303.620184-7-i.swmail@xen0n.name>","list_archive_url":null,"date":"2023-02-15T18:03:03","name":"[v4,6/6] opcodes/loongarch: print unrecognized insn words with the .word directive","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230215180303.620184-7-i.swmail@xen0n.name/mbox/"},{"id":57811,"url":"https://patchwork.plctlab.org/api/1.2/patches/57811/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y+2O/JECc+OX2WWd@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-02-16T02:03:40","name":"gas_init","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y+2O/JECc+OX2WWd@squeak.grove.modra.org/mbox/"},{"id":57812,"url":"https://patchwork.plctlab.org/api/1.2/patches/57812/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y+2PQpJcZUJBOxco@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-02-16T02:04:50","name":"Delete PROGRESS macros","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y+2PQpJcZUJBOxco@squeak.grove.modra.org/mbox/"},{"id":57925,"url":"https://patchwork.plctlab.org/api/1.2/patches/57925/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f055cbdb-e706-3a74-ab63-725ed8a047fd@suse.com/","msgid":"","list_archive_url":null,"date":"2023-02-16T08:56:11","name":"RISC-V: as_warn() already emits a newline","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f055cbdb-e706-3a74-ab63-725ed8a047fd@suse.com/mbox/"},{"id":58064,"url":"https://patchwork.plctlab.org/api/1.2/patches/58064/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230216131905.1012-2-binutils@emagii.com/","msgid":"<20230216131905.1012-2-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-16T13:19:05","name":"[v0,1/1,RFC] Add support for CRC64 generation in linker","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230216131905.1012-2-binutils@emagii.com/mbox/"},{"id":58227,"url":"https://patchwork.plctlab.org/api/1.2/patches/58227/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230216204006.1977-2-binutils@emagii.com/","msgid":"<20230216204006.1977-2-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-16T20:40:01","name":"[v0,1/6] CRC64 header","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230216204006.1977-2-binutils@emagii.com/mbox/"},{"id":58228,"url":"https://patchwork.plctlab.org/api/1.2/patches/58228/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230216204006.1977-3-binutils@emagii.com/","msgid":"<20230216204006.1977-3-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-16T20:40:02","name":"[v0,2/6] ldlang.h: CRC64","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230216204006.1977-3-binutils@emagii.com/mbox/"},{"id":58229,"url":"https://patchwork.plctlab.org/api/1.2/patches/58229/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230216204006.1977-4-binutils@emagii.com/","msgid":"<20230216204006.1977-4-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-16T20:40:03","name":"[v0,3/6] ldlex.l: CRC64","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230216204006.1977-4-binutils@emagii.com/mbox/"},{"id":58230,"url":"https://patchwork.plctlab.org/api/1.2/patches/58230/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230216204006.1977-5-binutils@emagii.com/","msgid":"<20230216204006.1977-5-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-16T20:40:04","name":"[v0,4/6] ldgram.y: CRC64","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230216204006.1977-5-binutils@emagii.com/mbox/"},{"id":58232,"url":"https://patchwork.plctlab.org/api/1.2/patches/58232/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230216204006.1977-6-binutils@emagii.com/","msgid":"<20230216204006.1977-6-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-16T20:40:05","name":"[v0,5/6] ldlang.c: CRC64","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230216204006.1977-6-binutils@emagii.com/mbox/"},{"id":58231,"url":"https://patchwork.plctlab.org/api/1.2/patches/58231/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230216204006.1977-7-binutils@emagii.com/","msgid":"<20230216204006.1977-7-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-16T20:40:06","name":"[v0,6/6] ldlang.c: Try to get the .text section for checking CRC","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230216204006.1977-7-binutils@emagii.com/mbox/"},{"id":58259,"url":"https://patchwork.plctlab.org/api/1.2/patches/58259/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y+6nfaKgOuYb/KBD@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-02-16T22:00:29","name":"PR30046, power cmpi leads to unknown architecture","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y+6nfaKgOuYb/KBD@squeak.grove.modra.org/mbox/"},{"id":58321,"url":"https://patchwork.plctlab.org/api/1.2/patches/58321/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y+7ouisD+WH2nZn5@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-02-17T02:38:50","name":"Wild pointer reads in _bfd_ecoff_locate_line","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y+7ouisD+WH2nZn5@squeak.grove.modra.org/mbox/"},{"id":58346,"url":"https://patchwork.plctlab.org/api/1.2/patches/58346/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230217044033.2131866-1-vladimir.mezentsev@oracle.com/","msgid":"<20230217044033.2131866-1-vladimir.mezentsev@oracle.com>","list_archive_url":null,"date":"2023-02-17T04:40:33","name":"[1/2] gprofng: PR30036 Build failure on aarch64 w/ glibc: symbol `pwrite64'\'' is already defined","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230217044033.2131866-1-vladimir.mezentsev@oracle.com/mbox/"},{"id":58347,"url":"https://patchwork.plctlab.org/api/1.2/patches/58347/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230217044105.2133872-1-vladimir.mezentsev@oracle.com/","msgid":"<20230217044105.2133872-1-vladimir.mezentsev@oracle.com>","list_archive_url":null,"date":"2023-02-17T04:41:05","name":"[2/2] gprofng: fix Dwarf reader for DW_TAG_subprogram","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230217044105.2133872-1-vladimir.mezentsev@oracle.com/mbox/"},{"id":58348,"url":"https://patchwork.plctlab.org/api/1.2/patches/58348/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y+8HWSTBuPWN+K3i@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-02-17T04:49:29","name":"ld test asciz and ascii fails","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y+8HWSTBuPWN+K3i@squeak.grove.modra.org/mbox/"},{"id":58514,"url":"https://patchwork.plctlab.org/api/1.2/patches/58514/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230217112016.19718-2-binutils@emagii.com/","msgid":"<20230217112016.19718-2-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-17T11:20:12","name":"[v1,1/5] ldlex.l: CRC64","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230217112016.19718-2-binutils@emagii.com/mbox/"},{"id":58513,"url":"https://patchwork.plctlab.org/api/1.2/patches/58513/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230217112016.19718-3-binutils@emagii.com/","msgid":"<20230217112016.19718-3-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-17T11:20:13","name":"[v1,2/5] ldgram.y: CRC64","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230217112016.19718-3-binutils@emagii.com/mbox/"},{"id":58591,"url":"https://patchwork.plctlab.org/api/1.2/patches/58591/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230217135446.26053-2-binutils@emagii.com/","msgid":"<20230217135446.26053-2-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-17T13:54:42","name":"[v1,1/5] ldlex.l: CRC64","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230217135446.26053-2-binutils@emagii.com/mbox/"},{"id":58593,"url":"https://patchwork.plctlab.org/api/1.2/patches/58593/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230217135446.26053-3-binutils@emagii.com/","msgid":"<20230217135446.26053-3-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-17T13:54:43","name":"[v1,2/5] ldgram.y: CRC64","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230217135446.26053-3-binutils@emagii.com/mbox/"},{"id":58589,"url":"https://patchwork.plctlab.org/api/1.2/patches/58589/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230217135446.26053-4-binutils@emagii.com/","msgid":"<20230217135446.26053-4-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-17T13:54:44","name":"[v1,3/5] Calculate CRC64 over the .text area","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230217135446.26053-4-binutils@emagii.com/mbox/"},{"id":58590,"url":"https://patchwork.plctlab.org/api/1.2/patches/58590/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230217135446.26053-5-binutils@emagii.com/","msgid":"<20230217135446.26053-5-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-17T13:54:45","name":"[v1,4/5] CRC64 commands documentation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230217135446.26053-5-binutils@emagii.com/mbox/"},{"id":58592,"url":"https://patchwork.plctlab.org/api/1.2/patches/58592/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230217135446.26053-6-binutils@emagii.com/","msgid":"<20230217135446.26053-6-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-17T13:54:46","name":"[v1,5/5] CRC64 testsuite","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230217135446.26053-6-binutils@emagii.com/mbox/"},{"id":58650,"url":"https://patchwork.plctlab.org/api/1.2/patches/58650/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.LSU.2.20.2302171451390.16810@wotan.suse.de/","msgid":"","list_archive_url":null,"date":"2023-02-17T15:03:57","name":"[RFC] Move static archive dependencies into ld","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.LSU.2.20.2302171451390.16810@wotan.suse.de/mbox/"},{"id":58738,"url":"https://patchwork.plctlab.org/api/1.2/patches/58738/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230217174037.11911-2-binutils@emagii.com/","msgid":"<20230217174037.11911-2-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-17T17:40:33","name":"[v2,1/5] ldlex.l: CRC64","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230217174037.11911-2-binutils@emagii.com/mbox/"},{"id":58735,"url":"https://patchwork.plctlab.org/api/1.2/patches/58735/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230217174037.11911-3-binutils@emagii.com/","msgid":"<20230217174037.11911-3-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-17T17:40:34","name":"[v2,2/5] ldgram.y: CRC64","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230217174037.11911-3-binutils@emagii.com/mbox/"},{"id":58736,"url":"https://patchwork.plctlab.org/api/1.2/patches/58736/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230217174037.11911-4-binutils@emagii.com/","msgid":"<20230217174037.11911-4-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-17T17:40:35","name":"[v2,3/5] Calculate CRC64 over the .text area","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230217174037.11911-4-binutils@emagii.com/mbox/"},{"id":58734,"url":"https://patchwork.plctlab.org/api/1.2/patches/58734/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230217174037.11911-5-binutils@emagii.com/","msgid":"<20230217174037.11911-5-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-17T17:40:36","name":"[v2,4/5] CRC64 commands documentation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230217174037.11911-5-binutils@emagii.com/mbox/"},{"id":58737,"url":"https://patchwork.plctlab.org/api/1.2/patches/58737/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230217174037.11911-6-binutils@emagii.com/","msgid":"<20230217174037.11911-6-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-17T17:40:37","name":"[v2,5/5] CRC64 testsuite","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230217174037.11911-6-binutils@emagii.com/mbox/"},{"id":58757,"url":"https://patchwork.plctlab.org/api/1.2/patches/58757/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230217192905.3160819-2-tom@tromey.com/","msgid":"<20230217192905.3160819-2-tom@tromey.com>","list_archive_url":null,"date":"2023-02-17T19:29:02","name":"[1/4] Fix formatting of long function description in chew output","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230217192905.3160819-2-tom@tromey.com/mbox/"},{"id":58758,"url":"https://patchwork.plctlab.org/api/1.2/patches/58758/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230217192905.3160819-3-tom@tromey.com/","msgid":"<20230217192905.3160819-3-tom@tromey.com>","list_archive_url":null,"date":"2023-02-17T19:29:03","name":"[2/4] Don'\''t use chew comments for static functions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230217192905.3160819-3-tom@tromey.com/mbox/"},{"id":58756,"url":"https://patchwork.plctlab.org/api/1.2/patches/58756/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230217192905.3160819-4-tom@tromey.com/","msgid":"<20230217192905.3160819-4-tom@tromey.com>","list_archive_url":null,"date":"2023-02-17T19:29:04","name":"[3/4] Hoist the SECTION comment in opncls.c","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230217192905.3160819-4-tom@tromey.com/mbox/"},{"id":58755,"url":"https://patchwork.plctlab.org/api/1.2/patches/58755/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230217192905.3160819-5-tom@tromey.com/","msgid":"<20230217192905.3160819-5-tom@tromey.com>","list_archive_url":null,"date":"2023-02-17T19:29:05","name":"[4/4] Redefine FUNCTION in doc.str","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230217192905.3160819-5-tom@tromey.com/mbox/"},{"id":58951,"url":"https://patchwork.plctlab.org/api/1.2/patches/58951/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/877cwere3q.fsf@igel.home/","msgid":"<877cwere3q.fsf@igel.home>","list_archive_url":null,"date":"2023-02-18T19:02:49","name":"opcodes: style m68k disassembler output","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/877cwere3q.fsf@igel.home/mbox/"},{"id":59075,"url":"https://patchwork.plctlab.org/api/1.2/patches/59075/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y/GbxH+cM+iKG3WP@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-02-19T03:47:16","name":"Buffer overflow in evax_bfd_print_eobj","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y/GbxH+cM+iKG3WP@squeak.grove.modra.org/mbox/"},{"id":59334,"url":"https://patchwork.plctlab.org/api/1.2/patches/59334/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230219173450.25555-2-binutils@emagii.com/","msgid":"<20230219173450.25555-2-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-19T17:34:46","name":"[v3,1/5] CRC64 commands documentation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230219173450.25555-2-binutils@emagii.com/mbox/"},{"id":59332,"url":"https://patchwork.plctlab.org/api/1.2/patches/59332/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230219173450.25555-3-binutils@emagii.com/","msgid":"<20230219173450.25555-3-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-19T17:34:47","name":"[v3,2/5] CRC64 testsuite","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230219173450.25555-3-binutils@emagii.com/mbox/"},{"id":59333,"url":"https://patchwork.plctlab.org/api/1.2/patches/59333/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230219173450.25555-4-binutils@emagii.com/","msgid":"<20230219173450.25555-4-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-19T17:34:48","name":"[v3,3/5] ldlex.l: CRC64","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230219173450.25555-4-binutils@emagii.com/mbox/"},{"id":59331,"url":"https://patchwork.plctlab.org/api/1.2/patches/59331/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230219173450.25555-5-binutils@emagii.com/","msgid":"<20230219173450.25555-5-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-19T17:34:49","name":"[v3,4/5] ldgram.y: CRC64","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230219173450.25555-5-binutils@emagii.com/mbox/"},{"id":59340,"url":"https://patchwork.plctlab.org/api/1.2/patches/59340/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230219173450.25555-6-binutils@emagii.com/","msgid":"<20230219173450.25555-6-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-19T17:34:50","name":"[v3,5/5] Calculate CRC64 over the .text area","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230219173450.25555-6-binutils@emagii.com/mbox/"},{"id":59338,"url":"https://patchwork.plctlab.org/api/1.2/patches/59338/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230219194549.22554-2-binutils@emagii.com/","msgid":"<20230219194549.22554-2-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-19T19:45:45","name":"[v4,1/5] CRC64 commands documentation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230219194549.22554-2-binutils@emagii.com/mbox/"},{"id":59361,"url":"https://patchwork.plctlab.org/api/1.2/patches/59361/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230219194549.22554-3-binutils@emagii.com/","msgid":"<20230219194549.22554-3-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-19T19:45:46","name":"[v4,2/5] CRC64 testsuite","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230219194549.22554-3-binutils@emagii.com/mbox/"},{"id":59324,"url":"https://patchwork.plctlab.org/api/1.2/patches/59324/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230219194549.22554-4-binutils@emagii.com/","msgid":"<20230219194549.22554-4-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-19T19:45:47","name":"[v4,3/5] ldlex.l: CRC64","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230219194549.22554-4-binutils@emagii.com/mbox/"},{"id":59325,"url":"https://patchwork.plctlab.org/api/1.2/patches/59325/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230219194549.22554-5-binutils@emagii.com/","msgid":"<20230219194549.22554-5-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-19T19:45:48","name":"[v4,4/5] ldgram.y: CRC64","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230219194549.22554-5-binutils@emagii.com/mbox/"},{"id":59360,"url":"https://patchwork.plctlab.org/api/1.2/patches/59360/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230219194549.22554-6-binutils@emagii.com/","msgid":"<20230219194549.22554-6-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-19T19:45:49","name":"[v4,5/5] Calculate CRC64 over the .text area","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230219194549.22554-6-binutils@emagii.com/mbox/"},{"id":59371,"url":"https://patchwork.plctlab.org/api/1.2/patches/59371/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y/LTY//irZ06TbCl@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-02-20T01:56:51","name":"In-memory nested archives","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y/LTY//irZ06TbCl@squeak.grove.modra.org/mbox/"},{"id":59328,"url":"https://patchwork.plctlab.org/api/1.2/patches/59328/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230220082224.415968-1-chigot@adacore.com/","msgid":"<20230220082224.415968-1-chigot@adacore.com>","list_archive_url":null,"date":"2023-02-20T08:22:21","name":"[1/4] gas/testsuite: adjust a test for case insensitive file systems","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230220082224.415968-1-chigot@adacore.com/mbox/"},{"id":59350,"url":"https://patchwork.plctlab.org/api/1.2/patches/59350/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230220082224.415968-2-chigot@adacore.com/","msgid":"<20230220082224.415968-2-chigot@adacore.com>","list_archive_url":null,"date":"2023-02-20T08:22:22","name":"[2/4] ld/testsuite: don'\''t output to /dev/null on mingw hosts","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230220082224.415968-2-chigot@adacore.com/mbox/"},{"id":59358,"url":"https://patchwork.plctlab.org/api/1.2/patches/59358/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230220082224.415968-3-chigot@adacore.com/","msgid":"<20230220082224.415968-3-chigot@adacore.com>","list_archive_url":null,"date":"2023-02-20T08:22:23","name":"[3/4] ld/testsuite: adjust to Windows path separator.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230220082224.415968-3-chigot@adacore.com/mbox/"},{"id":59335,"url":"https://patchwork.plctlab.org/api/1.2/patches/59335/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230220082224.415968-4-chigot@adacore.com/","msgid":"<20230220082224.415968-4-chigot@adacore.com>","list_archive_url":null,"date":"2023-02-20T08:22:24","name":"[4/4] ld/testsuite: handle Windows drive letter in a noinit test","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230220082224.415968-4-chigot@adacore.com/mbox/"},{"id":59456,"url":"https://patchwork.plctlab.org/api/1.2/patches/59456/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230220141328.20441-1-mark@harmstone.com/","msgid":"<20230220141328.20441-1-mark@harmstone.com>","list_archive_url":null,"date":"2023-02-20T14:13:28","name":"ld: Sort section contributions in PDB files","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230220141328.20441-1-mark@harmstone.com/mbox/"},{"id":59466,"url":"https://patchwork.plctlab.org/api/1.2/patches/59466/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230220144302.1234792-1-chigot@adacore.com/","msgid":"<20230220144302.1234792-1-chigot@adacore.com>","list_archive_url":null,"date":"2023-02-20T14:43:02","name":"[v2] ld/testsuite: don'\''t output to /dev/null","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230220144302.1234792-1-chigot@adacore.com/mbox/"},{"id":59759,"url":"https://patchwork.plctlab.org/api/1.2/patches/59759/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230221040650.2337395-1-yunqiang.su@cipunited.com/","msgid":"<20230221040650.2337395-1-yunqiang.su@cipunited.com>","list_archive_url":null,"date":"2023-02-21T04:06:50","name":"MIPS: make mipsisa32 and mipsisa64 link more systematic","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230221040650.2337395-1-yunqiang.su@cipunited.com/mbox/"},{"id":59767,"url":"https://patchwork.plctlab.org/api/1.2/patches/59767/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y/RcPwp09t1wQTFF@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-02-21T05:53:03","name":"alpha-*-vms missing libraries","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y/RcPwp09t1wQTFF@squeak.grove.modra.org/mbox/"},{"id":59769,"url":"https://patchwork.plctlab.org/api/1.2/patches/59769/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y/RcV7KZ8EOf9LeQ@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-02-21T05:53:27","name":"ld-libs test on alpha-vms","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y/RcV7KZ8EOf9LeQ@squeak.grove.modra.org/mbox/"},{"id":59768,"url":"https://patchwork.plctlab.org/api/1.2/patches/59768/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y/RcdkYHUwcnAETA@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-02-21T05:53:58","name":"Both FAIL and PASS \"check sections 2\"?","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y/RcdkYHUwcnAETA@squeak.grove.modra.org/mbox/"},{"id":59807,"url":"https://patchwork.plctlab.org/api/1.2/patches/59807/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230221090331.559683-1-chigot@adacore.com/","msgid":"<20230221090331.559683-1-chigot@adacore.com>","list_archive_url":null,"date":"2023-02-21T09:03:31","name":"ld/testsuite: handle Windows drive letter in persistent section","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230221090331.559683-1-chigot@adacore.com/mbox/"},{"id":59864,"url":"https://patchwork.plctlab.org/api/1.2/patches/59864/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/87v8jv9snh.fsf@redhat.com/","msgid":"<87v8jv9snh.fsf@redhat.com>","list_archive_url":null,"date":"2023-02-21T11:14:58","name":"Commit: Update description of bfd_fill_in_gnu_debuglink_section","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/87v8jv9snh.fsf@redhat.com/mbox/"},{"id":60156,"url":"https://patchwork.plctlab.org/api/1.2/patches/60156/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230221161442.1554824-1-chigot@adacore.com/","msgid":"<20230221161442.1554824-1-chigot@adacore.com>","list_archive_url":null,"date":"2023-02-21T16:14:42","name":"testsuite: prune DOS drive letter in test outputs","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230221161442.1554824-1-chigot@adacore.com/mbox/"},{"id":60284,"url":"https://patchwork.plctlab.org/api/1.2/patches/60284/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y/VMwx4rDcB3csbz@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-02-21T22:59:15","name":"debug_link duplicate file size checks","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y/VMwx4rDcB3csbz@squeak.grove.modra.org/mbox/"},{"id":60522,"url":"https://patchwork.plctlab.org/api/1.2/patches/60522/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2767901e-2ebc-f42f-982b-1b9b6df3b18f@suse.com/","msgid":"<2767901e-2ebc-f42f-982b-1b9b6df3b18f@suse.com>","list_archive_url":null,"date":"2023-02-22T13:14:48","name":"x86: avoid .byte in testcases where possible","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2767901e-2ebc-f42f-982b-1b9b6df3b18f@suse.com/mbox/"},{"id":60572,"url":"https://patchwork.plctlab.org/api/1.2/patches/60572/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230222151639.588269-1-chigot@adacore.com/","msgid":"<20230222151639.588269-1-chigot@adacore.com>","list_archive_url":null,"date":"2023-02-22T15:16:39","name":"[v2] testsuite: prune DOS drive letter in test outputs","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230222151639.588269-1-chigot@adacore.com/mbox/"},{"id":60602,"url":"https://patchwork.plctlab.org/api/1.2/patches/60602/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230222161609.239928-2-binutils@emagii.com/","msgid":"<20230222161609.239928-2-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-22T16:16:00","name":"[v5,01/10] TIMESTAMP: ldlang: process","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230222161609.239928-2-binutils@emagii.com/mbox/"},{"id":60606,"url":"https://patchwork.plctlab.org/api/1.2/patches/60606/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230222161609.239928-3-binutils@emagii.com/","msgid":"<20230222161609.239928-3-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-22T16:16:01","name":"[v5,02/10] DIGEST: NEWS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230222161609.239928-3-binutils@emagii.com/mbox/"},{"id":60597,"url":"https://patchwork.plctlab.org/api/1.2/patches/60597/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230222161609.239928-4-binutils@emagii.com/","msgid":"<20230222161609.239928-4-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-22T16:16:02","name":"[v5,03/10] DIGEST: ld.texi","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230222161609.239928-4-binutils@emagii.com/mbox/"},{"id":60599,"url":"https://patchwork.plctlab.org/api/1.2/patches/60599/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230222161609.239928-5-binutils@emagii.com/","msgid":"<20230222161609.239928-5-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-22T16:16:03","name":"[v5,04/10] LIBCRC: license","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230222161609.239928-5-binutils@emagii.com/mbox/"},{"id":60604,"url":"https://patchwork.plctlab.org/api/1.2/patches/60604/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230222161609.239928-6-binutils@emagii.com/","msgid":"<20230222161609.239928-6-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-22T16:16:04","name":"[v5,05/10] DIGEST: ldlex.l","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230222161609.239928-6-binutils@emagii.com/mbox/"},{"id":60608,"url":"https://patchwork.plctlab.org/api/1.2/patches/60608/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230222161609.239928-7-binutils@emagii.com/","msgid":"<20230222161609.239928-7-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-22T16:16:05","name":"[v5,06/10] DIGEST: ldgram.y","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230222161609.239928-7-binutils@emagii.com/mbox/"},{"id":60609,"url":"https://patchwork.plctlab.org/api/1.2/patches/60609/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230222161609.239928-8-binutils@emagii.com/","msgid":"<20230222161609.239928-8-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-22T16:16:06","name":"[v5,07/10] DIGEST: Makefile.am: add new files","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230222161609.239928-8-binutils@emagii.com/mbox/"},{"id":60603,"url":"https://patchwork.plctlab.org/api/1.2/patches/60603/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230222161609.239928-9-binutils@emagii.com/","msgid":"<20230222161609.239928-9-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-22T16:16:07","name":"[v5,08/10] DIGEST: CRC-32/64 algorithms","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230222161609.239928-9-binutils@emagii.com/mbox/"},{"id":60605,"url":"https://patchwork.plctlab.org/api/1.2/patches/60605/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230222161609.239928-10-binutils@emagii.com/","msgid":"<20230222161609.239928-10-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-22T16:16:08","name":"[v5,09/10] DIGEST: ldmain.c: add CRC calculation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230222161609.239928-10-binutils@emagii.com/mbox/"},{"id":60607,"url":"https://patchwork.plctlab.org/api/1.2/patches/60607/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230222161609.239928-11-binutils@emagii.com/","msgid":"<20230222161609.239928-11-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-22T16:16:09","name":"[v5,10/10] DIGEST: testsuite","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230222161609.239928-11-binutils@emagii.com/mbox/"},{"id":60774,"url":"https://patchwork.plctlab.org/api/1.2/patches/60774/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y/biKm/PHgcgid9l@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-02-23T03:48:58","name":"Test SEC_HAS_CONTENTS before reading section contents","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y/biKm/PHgcgid9l@squeak.grove.modra.org/mbox/"},{"id":60775,"url":"https://patchwork.plctlab.org/api/1.2/patches/60775/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y/biSBwPDeTjESNU@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-02-23T03:49:28","name":"Test SEC_HAS_CONTENTS in relax routines","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y/biSBwPDeTjESNU@squeak.grove.modra.org/mbox/"},{"id":60776,"url":"https://patchwork.plctlab.org/api/1.2/patches/60776/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y/biZsHVn/HEmkal@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-02-23T03:49:58","name":"ip2k: don'\''t look at stab sections without relocs","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y/biZsHVn/HEmkal@squeak.grove.modra.org/mbox/"},{"id":60777,"url":"https://patchwork.plctlab.org/api/1.2/patches/60777/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y/bii4z1P2p0EwAC@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-02-23T03:50:35","name":"dwarf1 .line SEC_HAS_CONTENTS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y/bii4z1P2p0EwAC@squeak.grove.modra.org/mbox/"},{"id":60907,"url":"https://patchwork.plctlab.org/api/1.2/patches/60907/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230223110417.63915-1-chigot@adacore.com/","msgid":"<20230223110417.63915-1-chigot@adacore.com>","list_archive_url":null,"date":"2023-02-23T11:04:17","name":"[v3] testsuite: prune DOS drive letter in test outputs","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230223110417.63915-1-chigot@adacore.com/mbox/"},{"id":60908,"url":"https://patchwork.plctlab.org/api/1.2/patches/60908/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230223111115.3752443-1-yunqiang.su@cipunited.com/","msgid":"<20230223111115.3752443-1-yunqiang.su@cipunited.com>","list_archive_url":null,"date":"2023-02-23T11:11:15","name":"MIPS: support specify isa level when configure","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230223111115.3752443-1-yunqiang.su@cipunited.com/mbox/"},{"id":60954,"url":"https://patchwork.plctlab.org/api/1.2/patches/60954/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230223124519.4228-1-tdevries@suse.de/","msgid":"<20230223124519.4228-1-tdevries@suse.de>","list_archive_url":null,"date":"2023-02-23T12:45:19","name":"gas: Add --force-compress-debug-sections","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230223124519.4228-1-tdevries@suse.de/mbox/"},{"id":61014,"url":"https://patchwork.plctlab.org/api/1.2/patches/61014/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/877651c1-3d70-6985-54b3-e4416bed3048@arm.com/","msgid":"<877651c1-3d70-6985-54b3-e4416bed3048@arm.com>","list_archive_url":null,"date":"2023-02-23T15:18:03","name":"[GAS,Aarch64] Add Binutils support for MEC","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/877651c1-3d70-6985-54b3-e4416bed3048@arm.com/mbox/"},{"id":61037,"url":"https://patchwork.plctlab.org/api/1.2/patches/61037/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/87bklkths4.fsf@redhat.com/","msgid":"<87bklkths4.fsf@redhat.com>","list_archive_url":null,"date":"2023-02-23T17:26:19","name":"Commit: Better caching in elf_find_function","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/87bklkths4.fsf@redhat.com/mbox/"},{"id":61175,"url":"https://patchwork.plctlab.org/api/1.2/patches/61175/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y/htA80wwgArcHQ0@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-02-24T07:53:39","name":"PR30155, ld segfault in _bfd_nearby_section","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y/htA80wwgArcHQ0@squeak.grove.modra.org/mbox/"},{"id":61302,"url":"https://patchwork.plctlab.org/api/1.2/patches/61302/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fe210be6-76c8-155f-f151-15ce767b133f@suse.com/","msgid":"","list_archive_url":null,"date":"2023-02-24T13:02:22","name":"gas: default .debug section compression method adjustments","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fe210be6-76c8-155f-f151-15ce767b133f@suse.com/mbox/"},{"id":61306,"url":"https://patchwork.plctlab.org/api/1.2/patches/61306/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3dba3751-3fa1-0684-b98c-2c383f26c5a6@suse.com/","msgid":"<3dba3751-3fa1-0684-b98c-2c383f26c5a6@suse.com>","list_archive_url":null,"date":"2023-02-24T13:08:25","name":"[1/2] x86: drop redundant calculation of EVEX broadcast size","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3dba3751-3fa1-0684-b98c-2c383f26c5a6@suse.com/mbox/"},{"id":61307,"url":"https://patchwork.plctlab.org/api/1.2/patches/61307/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a68e2ee4-9198-664e-4e62-245ff29494fc@suse.com/","msgid":"","list_archive_url":null,"date":"2023-02-24T13:09:14","name":"[2/2] x86: use swap_2_operands() in build_vex_prefix()","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a68e2ee4-9198-664e-4e62-245ff29494fc@suse.com/mbox/"},{"id":61506,"url":"https://patchwork.plctlab.org/api/1.2/patches/61506/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/87ilfqjb5y.fsf@redhat.com/","msgid":"<87ilfqjb5y.fsf@redhat.com>","list_archive_url":null,"date":"2023-02-25T10:23:53","name":"[PUSHED] Enable styling for GDB (Was: [PATCH] opcodes: style m68k disassembler output)","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/87ilfqjb5y.fsf@redhat.com/mbox/"},{"id":61690,"url":"https://patchwork.plctlab.org/api/1.2/patches/61690/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230227005935.12270-1-mark@harmstone.com/","msgid":"<20230227005935.12270-1-mark@harmstone.com>","list_archive_url":null,"date":"2023-02-27T00:59:35","name":"[v2] ld: Sort section contributions in PDB files","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230227005935.12270-1-mark@harmstone.com/mbox/"},{"id":61924,"url":"https://patchwork.plctlab.org/api/1.2/patches/61924/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9eb9eaf6-2cff-360b-3de6-072d3f8185dc@suse.de/","msgid":"<9eb9eaf6-2cff-360b-3de6-072d3f8185dc@suse.de>","list_archive_url":null,"date":"2023-02-27T11:43:09","name":"gas: Add --compress-debug-sections=force","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9eb9eaf6-2cff-360b-3de6-072d3f8185dc@suse.de/mbox/"},{"id":61954,"url":"https://patchwork.plctlab.org/api/1.2/patches/61954/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230227134135.462271-1-chigot@adacore.com/","msgid":"<20230227134135.462271-1-chigot@adacore.com>","list_archive_url":null,"date":"2023-02-27T13:41:35","name":"gas/testsuite: adjust another test for case insensitive file systems","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230227134135.462271-1-chigot@adacore.com/mbox/"},{"id":62196,"url":"https://patchwork.plctlab.org/api/1.2/patches/62196/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y/1FKI3FT2qt6LnH@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-02-28T00:04:56","name":"Another PE SEC_HAS_CONTENTS test","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y/1FKI3FT2qt6LnH@squeak.grove.modra.org/mbox/"},{"id":62197,"url":"https://patchwork.plctlab.org/api/1.2/patches/62197/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y/1FWTrLectdFgCl@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-02-28T00:05:45","name":"Add some sanity checking in ECOFF lookup_line","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y/1FWTrLectdFgCl@squeak.grove.modra.org/mbox/"},{"id":62198,"url":"https://patchwork.plctlab.org/api/1.2/patches/62198/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y/1FjDQ7XxwI4Zxz@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-02-28T00:06:36","name":"Free ecoff debug info","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y/1FjDQ7XxwI4Zxz@squeak.grove.modra.org/mbox/"},{"id":62205,"url":"https://patchwork.plctlab.org/api/1.2/patches/62205/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230228001633.3602-1-tdevries@suse.de/","msgid":"<20230228001633.3602-1-tdevries@suse.de>","list_archive_url":null,"date":"2023-02-28T00:16:31","name":"[v2,1/3] gas: Unify parsing of --compress-debug-sections","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230228001633.3602-1-tdevries@suse.de/mbox/"},{"id":62206,"url":"https://patchwork.plctlab.org/api/1.2/patches/62206/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230228001633.3602-2-tdevries@suse.de/","msgid":"<20230228001633.3602-2-tdevries@suse.de>","list_archive_url":null,"date":"2023-02-28T00:16:32","name":"[v2,2/3] gas: Handle --compress-debug-sections=subopt1,subopt2","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230228001633.3602-2-tdevries@suse.de/mbox/"},{"id":62204,"url":"https://patchwork.plctlab.org/api/1.2/patches/62204/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230228001633.3602-3-tdevries@suse.de/","msgid":"<20230228001633.3602-3-tdevries@suse.de>","list_archive_url":null,"date":"2023-02-28T00:16:33","name":"[v2,3/3] gas: Add --compress-debug-sections={heuristic-always, heuristic-sizewin}","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230228001633.3602-3-tdevries@suse.de/mbox/"},{"id":62220,"url":"https://patchwork.plctlab.org/api/1.2/patches/62220/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y/1M54x/w6QMpPfQ@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-02-28T00:37:59","name":"chew.c printf of intptr_t","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y/1M54x/w6QMpPfQ@squeak.grove.modra.org/mbox/"},{"id":62640,"url":"https://patchwork.plctlab.org/api/1.2/patches/62640/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2efba8824df3f1bc782b9bd9aa598e2dae02f9ca.1677620627.git.aburgess@redhat.com/","msgid":"<2efba8824df3f1bc782b9bd9aa598e2dae02f9ca.1677620627.git.aburgess@redhat.com>","list_archive_url":null,"date":"2023-02-28T21:44:06","name":"opcodes/arm: adjust whitespace in cpsie instruction","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2efba8824df3f1bc782b9bd9aa598e2dae02f9ca.1677620627.git.aburgess@redhat.com/mbox/"},{"id":62664,"url":"https://patchwork.plctlab.org/api/1.2/patches/62664/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230228224937.3832887-1-dilfridge@gentoo.org/","msgid":"<20230228224937.3832887-1-dilfridge@gentoo.org>","list_archive_url":null,"date":"2023-02-28T22:49:37","name":"[needs,more,eyes] Relink also libopcodes and libgprofng to newly built libiberty.a","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230228224937.3832887-1-dilfridge@gentoo.org/mbox/"}],"public":true,"mbox":"https://patchwork.plctlab.org/bundle/patchwork-bot/binutils-gdb_2023-02/mbox/"},{"id":17,"url":"https://patchwork.plctlab.org/api/1.2/bundles/17/","web_url":"https://patchwork.plctlab.org/bundle/patchwork-bot/binutils-gdb_2023-03/","project":{"id":2,"url":"https://patchwork.plctlab.org/api/1.2/projects/2/","name":"binutils-gdb","link_name":"binutils-gdb","list_id":"binutils.sourceware.org","list_email":"binutils@sourceware.org","web_url":"https://github.com/wangliu-iscas/Patchwork-Bundles/blob/main/binutils-gdb.md","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"name":"binutils-gdb_2023-03","owner":{"id":3,"url":"https://patchwork.plctlab.org/api/1.2/users/3/","username":"patchwork-bot","first_name":"","last_name":"","email":"ouuuleilei@gmail.com"},"patches":[{"id":62751,"url":"https://patchwork.plctlab.org/api/1.2/patches/62751/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y/7Nlh7yA1PLiIvj@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-01T03:59:18","name":"Memory leak in gas do_repeat","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y/7Nlh7yA1PLiIvj@squeak.grove.modra.org/mbox/"},{"id":62752,"url":"https://patchwork.plctlab.org/api/1.2/patches/62752/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y/7Nw2XouT8JokFm@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-01T04:00:03","name":"gas s_fill caused internal error in frag_new","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y/7Nw2XouT8JokFm@squeak.grove.modra.org/mbox/"},{"id":62753,"url":"https://patchwork.plctlab.org/api/1.2/patches/62753/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y/7N5GnBecgnIXQx@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-01T04:00:36","name":"Catch overflow in gas s_space","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y/7N5GnBecgnIXQx@squeak.grove.modra.org/mbox/"},{"id":62932,"url":"https://patchwork.plctlab.org/api/1.2/patches/62932/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301144756.1847278-2-binutils@emagii.com/","msgid":"<20230301144756.1847278-2-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-01T14:47:46","name":"[v6,01/11] DIGEST: LICENSING","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301144756.1847278-2-binutils@emagii.com/mbox/"},{"id":62934,"url":"https://patchwork.plctlab.org/api/1.2/patches/62934/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301144756.1847278-3-binutils@emagii.com/","msgid":"<20230301144756.1847278-3-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-01T14:47:47","name":"[v6,02/11] DIGEST: NEWS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301144756.1847278-3-binutils@emagii.com/mbox/"},{"id":62935,"url":"https://patchwork.plctlab.org/api/1.2/patches/62935/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301144756.1847278-4-binutils@emagii.com/","msgid":"<20230301144756.1847278-4-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-01T14:47:48","name":"[v6,03/11] DIGEST: Documentation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301144756.1847278-4-binutils@emagii.com/mbox/"},{"id":62933,"url":"https://patchwork.plctlab.org/api/1.2/patches/62933/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301144756.1847278-5-binutils@emagii.com/","msgid":"<20230301144756.1847278-5-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-01T14:47:49","name":"[v6,04/11] DIGEST: testsuite","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301144756.1847278-5-binutils@emagii.com/mbox/"},{"id":62937,"url":"https://patchwork.plctlab.org/api/1.2/patches/62937/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301144756.1847278-6-binutils@emagii.com/","msgid":"<20230301144756.1847278-6-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-01T14:47:50","name":"[v6,05/11] DIGEST: ldlex.l","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301144756.1847278-6-binutils@emagii.com/mbox/"},{"id":62941,"url":"https://patchwork.plctlab.org/api/1.2/patches/62941/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301144756.1847278-7-binutils@emagii.com/","msgid":"<20230301144756.1847278-7-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-01T14:47:51","name":"[v6,06/11] DIGEST: ldgram.y","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301144756.1847278-7-binutils@emagii.com/mbox/"},{"id":62939,"url":"https://patchwork.plctlab.org/api/1.2/patches/62939/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301144756.1847278-8-binutils@emagii.com/","msgid":"<20230301144756.1847278-8-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-01T14:47:52","name":"[v6,07/11] DIGEST: ldmain.c","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301144756.1847278-8-binutils@emagii.com/mbox/"},{"id":62940,"url":"https://patchwork.plctlab.org/api/1.2/patches/62940/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301144756.1847278-9-binutils@emagii.com/","msgid":"<20230301144756.1847278-9-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-01T14:47:53","name":"[v6,08/11] DIGEST: ldlang.*: add timestamp","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301144756.1847278-9-binutils@emagii.com/mbox/"},{"id":62944,"url":"https://patchwork.plctlab.org/api/1.2/patches/62944/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301144756.1847278-10-binutils@emagii.com/","msgid":"<20230301144756.1847278-10-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-01T14:47:54","name":"[v6,09/11] DIGEST: calculation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301144756.1847278-10-binutils@emagii.com/mbox/"},{"id":62936,"url":"https://patchwork.plctlab.org/api/1.2/patches/62936/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301144756.1847278-11-binutils@emagii.com/","msgid":"<20230301144756.1847278-11-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-01T14:47:55","name":"[v6,10/11] DIGEST: Makefile.*","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301144756.1847278-11-binutils@emagii.com/mbox/"},{"id":62947,"url":"https://patchwork.plctlab.org/api/1.2/patches/62947/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301144756.1847278-12-binutils@emagii.com/","msgid":"<20230301144756.1847278-12-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-01T14:47:56","name":"[v6,11/11] Build ldint","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301144756.1847278-12-binutils@emagii.com/mbox/"},{"id":62967,"url":"https://patchwork.plctlab.org/api/1.2/patches/62967/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301154513.1850449-2-binutils@emagii.com/","msgid":"<20230301154513.1850449-2-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-01T15:45:03","name":"[v7,01/11] DIGEST: LICENSING","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301154513.1850449-2-binutils@emagii.com/mbox/"},{"id":62966,"url":"https://patchwork.plctlab.org/api/1.2/patches/62966/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301154513.1850449-3-binutils@emagii.com/","msgid":"<20230301154513.1850449-3-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-01T15:45:04","name":"[v7,02/11] DIGEST: NEWS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301154513.1850449-3-binutils@emagii.com/mbox/"},{"id":62971,"url":"https://patchwork.plctlab.org/api/1.2/patches/62971/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301154513.1850449-4-binutils@emagii.com/","msgid":"<20230301154513.1850449-4-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-01T15:45:05","name":"[v7,03/11] DIGEST: Documentation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301154513.1850449-4-binutils@emagii.com/mbox/"},{"id":62973,"url":"https://patchwork.plctlab.org/api/1.2/patches/62973/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301154513.1850449-5-binutils@emagii.com/","msgid":"<20230301154513.1850449-5-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-01T15:45:06","name":"[v7,04/11] DIGEST: testsuite","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301154513.1850449-5-binutils@emagii.com/mbox/"},{"id":62972,"url":"https://patchwork.plctlab.org/api/1.2/patches/62972/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301154513.1850449-6-binutils@emagii.com/","msgid":"<20230301154513.1850449-6-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-01T15:45:07","name":"[v7,05/11] DIGEST: ldlex.l","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301154513.1850449-6-binutils@emagii.com/mbox/"},{"id":62974,"url":"https://patchwork.plctlab.org/api/1.2/patches/62974/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301154513.1850449-7-binutils@emagii.com/","msgid":"<20230301154513.1850449-7-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-01T15:45:08","name":"[v7,06/11] DIGEST: ldgram.y","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301154513.1850449-7-binutils@emagii.com/mbox/"},{"id":62968,"url":"https://patchwork.plctlab.org/api/1.2/patches/62968/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301154513.1850449-8-binutils@emagii.com/","msgid":"<20230301154513.1850449-8-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-01T15:45:09","name":"[v7,07/11] DIGEST: ldmain.c","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301154513.1850449-8-binutils@emagii.com/mbox/"},{"id":62994,"url":"https://patchwork.plctlab.org/api/1.2/patches/62994/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301173022.1851188-8-binutils@emagii.com/","msgid":"<20230301173022.1851188-8-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-01T17:30:19","name":"[v7,08/11] DIGEST: ldlang.*: add timestamp","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301173022.1851188-8-binutils@emagii.com/mbox/"},{"id":62997,"url":"https://patchwork.plctlab.org/api/1.2/patches/62997/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301173022.1851188-9-binutils@emagii.com/","msgid":"<20230301173022.1851188-9-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-01T17:30:20","name":"[v7,09/11] DIGEST: calculation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301173022.1851188-9-binutils@emagii.com/mbox/"},{"id":62995,"url":"https://patchwork.plctlab.org/api/1.2/patches/62995/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301173022.1851188-10-binutils@emagii.com/","msgid":"<20230301173022.1851188-10-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-01T17:30:21","name":"[v7,10/11] DIGEST: Makefile.*","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301173022.1851188-10-binutils@emagii.com/mbox/"},{"id":62996,"url":"https://patchwork.plctlab.org/api/1.2/patches/62996/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301173022.1851188-11-binutils@emagii.com/","msgid":"<20230301173022.1851188-11-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-01T17:30:22","name":"[v7,11/11] Build ldint","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301173022.1851188-11-binutils@emagii.com/mbox/"},{"id":62999,"url":"https://patchwork.plctlab.org/api/1.2/patches/62999/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301174325.1858522-2-binutils@emagii.com/","msgid":"<20230301174325.1858522-2-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-01T17:43:15","name":"[v8,01/11] DIGEST: LICENSING","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301174325.1858522-2-binutils@emagii.com/mbox/"},{"id":63002,"url":"https://patchwork.plctlab.org/api/1.2/patches/63002/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301174325.1858522-3-binutils@emagii.com/","msgid":"<20230301174325.1858522-3-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-01T17:43:16","name":"[v8,02/11] DIGEST: NEWS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301174325.1858522-3-binutils@emagii.com/mbox/"},{"id":63000,"url":"https://patchwork.plctlab.org/api/1.2/patches/63000/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301174325.1858522-4-binutils@emagii.com/","msgid":"<20230301174325.1858522-4-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-01T17:43:17","name":"[v8,03/11] DIGEST: Documentation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301174325.1858522-4-binutils@emagii.com/mbox/"},{"id":63001,"url":"https://patchwork.plctlab.org/api/1.2/patches/63001/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301174325.1858522-5-binutils@emagii.com/","msgid":"<20230301174325.1858522-5-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-01T17:43:18","name":"[v8,04/11] DIGEST: testsuite","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301174325.1858522-5-binutils@emagii.com/mbox/"},{"id":63005,"url":"https://patchwork.plctlab.org/api/1.2/patches/63005/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301174325.1858522-6-binutils@emagii.com/","msgid":"<20230301174325.1858522-6-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-01T17:43:19","name":"[v8,05/11] DIGEST: ldlex.l","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301174325.1858522-6-binutils@emagii.com/mbox/"},{"id":63006,"url":"https://patchwork.plctlab.org/api/1.2/patches/63006/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301174325.1858522-7-binutils@emagii.com/","msgid":"<20230301174325.1858522-7-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-01T17:43:20","name":"[v8,06/11] DIGEST: ldgram.y","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301174325.1858522-7-binutils@emagii.com/mbox/"},{"id":63007,"url":"https://patchwork.plctlab.org/api/1.2/patches/63007/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301174325.1858522-8-binutils@emagii.com/","msgid":"<20230301174325.1858522-8-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-01T17:43:21","name":"[v8,07/11] DIGEST: ldmain.c","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301174325.1858522-8-binutils@emagii.com/mbox/"},{"id":63008,"url":"https://patchwork.plctlab.org/api/1.2/patches/63008/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301174325.1858522-9-binutils@emagii.com/","msgid":"<20230301174325.1858522-9-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-01T17:43:22","name":"[v8,08/11] DIGEST: ldlang.*: add timestamp","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301174325.1858522-9-binutils@emagii.com/mbox/"},{"id":63010,"url":"https://patchwork.plctlab.org/api/1.2/patches/63010/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301174325.1858522-10-binutils@emagii.com/","msgid":"<20230301174325.1858522-10-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-01T17:43:23","name":"[v8,09/11] DIGEST: calculation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301174325.1858522-10-binutils@emagii.com/mbox/"},{"id":63011,"url":"https://patchwork.plctlab.org/api/1.2/patches/63011/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301174325.1858522-11-binutils@emagii.com/","msgid":"<20230301174325.1858522-11-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-01T17:43:24","name":"[v8,10/11] DIGEST: Makefile.*","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301174325.1858522-11-binutils@emagii.com/mbox/"},{"id":63004,"url":"https://patchwork.plctlab.org/api/1.2/patches/63004/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301174325.1858522-12-binutils@emagii.com/","msgid":"<20230301174325.1858522-12-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-01T17:43:25","name":"[v8,11/11] Build ldint","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301174325.1858522-12-binutils@emagii.com/mbox/"},{"id":63103,"url":"https://patchwork.plctlab.org/api/1.2/patches/63103/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y//K/QCIk6YuuRF3@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-01T22:00:29","name":"Using .mri in assembly","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y//K/QCIk6YuuRF3@squeak.grove.modra.org/mbox/"},{"id":63104,"url":"https://patchwork.plctlab.org/api/1.2/patches/63104/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y//LGl4CuJ+YN+i5@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-01T22:00:58","name":"More bounds checking in macro_expand","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y//LGl4CuJ+YN+i5@squeak.grove.modra.org/mbox/"},{"id":63167,"url":"https://patchwork.plctlab.org/api/1.2/patches/63167/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230302015222.291088-1-yunqiang.su@cipunited.com/","msgid":"<20230302015222.291088-1-yunqiang.su@cipunited.com>","list_archive_url":null,"date":"2023-03-02T01:52:22","name":"[v2] MIPS: make mipsisa32 and mipsisa64 link more systematic","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230302015222.291088-1-yunqiang.su@cipunited.com/mbox/"},{"id":63263,"url":"https://patchwork.plctlab.org/api/1.2/patches/63263/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230302080137.3346439-1-i.swmail@xen0n.name/","msgid":"<20230302080137.3346439-1-i.swmail@xen0n.name>","list_archive_url":null,"date":"2023-03-02T08:01:37","name":"elfedit: add support for editing e_flags","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230302080137.3346439-1-i.swmail@xen0n.name/mbox/"},{"id":63267,"url":"https://patchwork.plctlab.org/api/1.2/patches/63267/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230302081452.3429908-1-i.swmail@xen0n.name/","msgid":"<20230302081452.3429908-1-i.swmail@xen0n.name>","list_archive_url":null,"date":"2023-03-02T08:14:52","name":"[RESEND] elfedit: add support for editing e_flags","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230302081452.3429908-1-i.swmail@xen0n.name/mbox/"},{"id":63360,"url":"https://patchwork.plctlab.org/api/1.2/patches/63360/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230302112531.200647-2-cupertino.miranda@oracle.com/","msgid":"<20230302112531.200647-2-cupertino.miranda@oracle.com>","list_archive_url":null,"date":"2023-03-02T11:25:31","name":"BPF relocations review / refactoring","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230302112531.200647-2-cupertino.miranda@oracle.com/mbox/"},{"id":63387,"url":"https://patchwork.plctlab.org/api/1.2/patches/63387/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZACQFdX4P07PysEc@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-02T12:01:25","name":"Don'\''t write zeros to a gap in the output file","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZACQFdX4P07PysEc@squeak.grove.modra.org/mbox/"},{"id":63554,"url":"https://patchwork.plctlab.org/api/1.2/patches/63554/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230302201029.vflqmyjxh7qnyxa3@google.com/","msgid":"<20230302201029.vflqmyjxh7qnyxa3@google.com>","list_archive_url":null,"date":"2023-03-02T20:10:29","name":"[v2] ld: Allow R_X86_64_GOTPCREL for call *__tls_get_addr@GOTPCREL(%rip)","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230302201029.vflqmyjxh7qnyxa3@google.com/mbox/"},{"id":63555,"url":"https://patchwork.plctlab.org/api/1.2/patches/63555/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230302201722.1304941-1-maskray@google.com/","msgid":"<20230302201722.1304941-1-maskray@google.com>","list_archive_url":null,"date":"2023-03-02T20:17:22","name":"[v2] ld: Allow R_386_GOT32 for call *__tls_get_addr@GOT(%reg)","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230302201722.1304941-1-maskray@google.com/mbox/"},{"id":63603,"url":"https://patchwork.plctlab.org/api/1.2/patches/63603/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230302220408.1925678-2-binutils@emagii.com/","msgid":"<20230302220408.1925678-2-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-02T22:03:58","name":"[v9,01/11,gdb/testsuite] Fix gdb.rust/watch.exp on ppc64le","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230302220408.1925678-2-binutils@emagii.com/mbox/"},{"id":63598,"url":"https://patchwork.plctlab.org/api/1.2/patches/63598/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230302220408.1925678-3-binutils@emagii.com/","msgid":"<20230302220408.1925678-3-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-02T22:03:59","name":"[v9,02/11] Remove value_in","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230302220408.1925678-3-binutils@emagii.com/mbox/"},{"id":63607,"url":"https://patchwork.plctlab.org/api/1.2/patches/63607/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230302220408.1925678-4-binutils@emagii.com/","msgid":"<20230302220408.1925678-4-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-02T22:04:00","name":"[v9,03/11,gdb/testsuite] Fix gdb.python/py-breakpoint.exp timeouts","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230302220408.1925678-4-binutils@emagii.com/mbox/"},{"id":63602,"url":"https://patchwork.plctlab.org/api/1.2/patches/63602/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230302220408.1925678-5-binutils@emagii.com/","msgid":"<20230302220408.1925678-5-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-02T22:04:01","name":"[v9,04/11] gdb: add HtabPrinter to gdb-gdb.py.in","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230302220408.1925678-5-binutils@emagii.com/mbox/"},{"id":63608,"url":"https://patchwork.plctlab.org/api/1.2/patches/63608/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230302220408.1925678-6-binutils@emagii.com/","msgid":"<20230302220408.1925678-6-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-02T22:04:02","name":"[v9,05/11] Automatic date update in version.in","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230302220408.1925678-6-binutils@emagii.com/mbox/"},{"id":63609,"url":"https://patchwork.plctlab.org/api/1.2/patches/63609/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230302220408.1925678-7-binutils@emagii.com/","msgid":"<20230302220408.1925678-7-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-02T22:04:03","name":"[v9,06/11] Memory leak in gas do_repeat","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230302220408.1925678-7-binutils@emagii.com/mbox/"},{"id":63599,"url":"https://patchwork.plctlab.org/api/1.2/patches/63599/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230302220408.1925678-8-binutils@emagii.com/","msgid":"<20230302220408.1925678-8-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-02T22:04:04","name":"[v9,07/11] gas s_fill caused internal error in frag_new","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230302220408.1925678-8-binutils@emagii.com/mbox/"},{"id":63610,"url":"https://patchwork.plctlab.org/api/1.2/patches/63610/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230302220408.1925678-9-binutils@emagii.com/","msgid":"<20230302220408.1925678-9-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-02T22:04:05","name":"[v9,08/11] Catch overflow in gas s_space","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230302220408.1925678-9-binutils@emagii.com/mbox/"},{"id":63606,"url":"https://patchwork.plctlab.org/api/1.2/patches/63606/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230302220408.1925678-10-binutils@emagii.com/","msgid":"<20230302220408.1925678-10-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-02T22:04:06","name":"[v9,09/11,gdb/testsuite] Add another xfail case in gdb.python/py-record-btrace.exp","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230302220408.1925678-10-binutils@emagii.com/mbox/"},{"id":63605,"url":"https://patchwork.plctlab.org/api/1.2/patches/63605/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230302220408.1925678-11-binutils@emagii.com/","msgid":"<20230302220408.1925678-11-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-02T22:04:07","name":"[v9,10/11] Fix btrace regression","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230302220408.1925678-11-binutils@emagii.com/mbox/"},{"id":63601,"url":"https://patchwork.plctlab.org/api/1.2/patches/63601/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230302220408.1925678-12-binutils@emagii.com/","msgid":"<20230302220408.1925678-12-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-02T22:04:08","name":"[v9,11/11] Fix typo with my email address","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230302220408.1925678-12-binutils@emagii.com/mbox/"},{"id":63630,"url":"https://patchwork.plctlab.org/api/1.2/patches/63630/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230302231051.1928782-2-binutils@emagii.com/","msgid":"<20230302231051.1928782-2-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-02T23:10:41","name":"[v10,01/11] DIGEST: LICENSING","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230302231051.1928782-2-binutils@emagii.com/mbox/"},{"id":63632,"url":"https://patchwork.plctlab.org/api/1.2/patches/63632/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230302231051.1928782-3-binutils@emagii.com/","msgid":"<20230302231051.1928782-3-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-02T23:10:42","name":"[v10,02/11] DIGEST: NEWS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230302231051.1928782-3-binutils@emagii.com/mbox/"},{"id":63635,"url":"https://patchwork.plctlab.org/api/1.2/patches/63635/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230302231051.1928782-4-binutils@emagii.com/","msgid":"<20230302231051.1928782-4-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-02T23:10:43","name":"[v10,03/11] DIGEST: Documentation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230302231051.1928782-4-binutils@emagii.com/mbox/"},{"id":63633,"url":"https://patchwork.plctlab.org/api/1.2/patches/63633/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230302231051.1928782-5-binutils@emagii.com/","msgid":"<20230302231051.1928782-5-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-02T23:10:44","name":"[v10,04/11] DIGEST: testsuite","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230302231051.1928782-5-binutils@emagii.com/mbox/"},{"id":63631,"url":"https://patchwork.plctlab.org/api/1.2/patches/63631/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230302231051.1928782-6-binutils@emagii.com/","msgid":"<20230302231051.1928782-6-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-02T23:10:45","name":"[v10,05/11] DIGEST: ldlex.l","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230302231051.1928782-6-binutils@emagii.com/mbox/"},{"id":63636,"url":"https://patchwork.plctlab.org/api/1.2/patches/63636/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230302231051.1928782-7-binutils@emagii.com/","msgid":"<20230302231051.1928782-7-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-02T23:10:46","name":"[v10,06/11] DIGEST: ldgram.y","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230302231051.1928782-7-binutils@emagii.com/mbox/"},{"id":63634,"url":"https://patchwork.plctlab.org/api/1.2/patches/63634/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230302231051.1928782-8-binutils@emagii.com/","msgid":"<20230302231051.1928782-8-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-02T23:10:47","name":"[v10,07/11] DIGEST: ldmain.c","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230302231051.1928782-8-binutils@emagii.com/mbox/"},{"id":63640,"url":"https://patchwork.plctlab.org/api/1.2/patches/63640/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230302231051.1928782-9-binutils@emagii.com/","msgid":"<20230302231051.1928782-9-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-02T23:10:48","name":"[v10,08/11] DIGEST: ldlang.*: add timestamp","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230302231051.1928782-9-binutils@emagii.com/mbox/"},{"id":63642,"url":"https://patchwork.plctlab.org/api/1.2/patches/63642/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230302231051.1928782-10-binutils@emagii.com/","msgid":"<20230302231051.1928782-10-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-02T23:10:49","name":"[v10,09/11] DIGEST: calculation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230302231051.1928782-10-binutils@emagii.com/mbox/"},{"id":63641,"url":"https://patchwork.plctlab.org/api/1.2/patches/63641/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230302231051.1928782-11-binutils@emagii.com/","msgid":"<20230302231051.1928782-11-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-02T23:10:50","name":"[v10,10/11] DIGEST: Makefile.*","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230302231051.1928782-11-binutils@emagii.com/mbox/"},{"id":63644,"url":"https://patchwork.plctlab.org/api/1.2/patches/63644/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230302231051.1928782-12-binutils@emagii.com/","msgid":"<20230302231051.1928782-12-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-02T23:10:51","name":"[v10,11/11] Build ldint","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230302231051.1928782-12-binutils@emagii.com/mbox/"},{"id":63749,"url":"https://patchwork.plctlab.org/api/1.2/patches/63749/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZAFthsObl5Xz7luZ@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-03T03:46:14","name":"binutils coff type list","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZAFthsObl5Xz7luZ@squeak.grove.modra.org/mbox/"},{"id":63750,"url":"https://patchwork.plctlab.org/api/1.2/patches/63750/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZAFtv3Y3nogpi2mk@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-03T03:47:11","name":"Tidy type handling in binutils/rdcoff.c","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZAFtv3Y3nogpi2mk@squeak.grove.modra.org/mbox/"},{"id":63885,"url":"https://patchwork.plctlab.org/api/1.2/patches/63885/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d42f8a58-0fb2-797e-2313-ba4c8a415b4b@suse.com/","msgid":"","list_archive_url":null,"date":"2023-03-03T12:56:20","name":"[01/18] x86: introduce .insn directive","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d42f8a58-0fb2-797e-2313-ba4c8a415b4b@suse.com/mbox/"},{"id":63887,"url":"https://patchwork.plctlab.org/api/1.2/patches/63887/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3bab7c05-755b-f494-8d7a-0183ab14563a@suse.com/","msgid":"<3bab7c05-755b-f494-8d7a-0183ab14563a@suse.com>","list_archive_url":null,"date":"2023-03-03T12:57:00","name":"[02/18] x86: parse VEX and alike specifiers for .insn","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3bab7c05-755b-f494-8d7a-0183ab14563a@suse.com/mbox/"},{"id":63889,"url":"https://patchwork.plctlab.org/api/1.2/patches/63889/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/242fa8c9-44f3-43e8-fbbd-4248a6abec18@suse.com/","msgid":"<242fa8c9-44f3-43e8-fbbd-4248a6abec18@suse.com>","list_archive_url":null,"date":"2023-03-03T12:57:39","name":"[03/18] x86: parse special opcode modifiers for .insn","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/242fa8c9-44f3-43e8-fbbd-4248a6abec18@suse.com/mbox/"},{"id":63892,"url":"https://patchwork.plctlab.org/api/1.2/patches/63892/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2ab58b70-a02f-cba3-8131-c54eb81b109a@suse.com/","msgid":"<2ab58b70-a02f-cba3-8131-c54eb81b109a@suse.com>","list_archive_url":null,"date":"2023-03-03T12:58:12","name":"[04/18] x86: use set_rex_vrex() also for short-form handling","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2ab58b70-a02f-cba3-8131-c54eb81b109a@suse.com/mbox/"},{"id":63893,"url":"https://patchwork.plctlab.org/api/1.2/patches/63893/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/34990244-84ae-bd27-04c3-1632ad5d7841@suse.com/","msgid":"<34990244-84ae-bd27-04c3-1632ad5d7841@suse.com>","list_archive_url":null,"date":"2023-03-03T12:58:33","name":"[05/18] x86: move more disp processing out of md_assemble()","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/34990244-84ae-bd27-04c3-1632ad5d7841@suse.com/mbox/"},{"id":63895,"url":"https://patchwork.plctlab.org/api/1.2/patches/63895/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/83d24f6c-14a1-2086-855e-453d5a9f3117@suse.com/","msgid":"<83d24f6c-14a1-2086-855e-453d5a9f3117@suse.com>","list_archive_url":null,"date":"2023-03-03T12:59:23","name":"[06/18] x86-64: adjust REX-prefix part of SSE2AVX test","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/83d24f6c-14a1-2086-855e-453d5a9f3117@suse.com/mbox/"},{"id":63896,"url":"https://patchwork.plctlab.org/api/1.2/patches/63896/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/462c093e-13a0-0aff-2dad-e4656180ea9c@suse.com/","msgid":"<462c093e-13a0-0aff-2dad-e4656180ea9c@suse.com>","list_archive_url":null,"date":"2023-03-03T13:00:05","name":"[07/18] x86: re-work build_modrm_byte()'\''s register assignment","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/462c093e-13a0-0aff-2dad-e4656180ea9c@suse.com/mbox/"},{"id":63897,"url":"https://patchwork.plctlab.org/api/1.2/patches/63897/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7a373ee5-4f74-0d63-3995-81b3dc05809c@suse.com/","msgid":"<7a373ee5-4f74-0d63-3995-81b3dc05809c@suse.com>","list_archive_url":null,"date":"2023-03-03T13:00:50","name":"[08/18] x86: VexVVVV is now merely a boolean","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7a373ee5-4f74-0d63-3995-81b3dc05809c@suse.com/mbox/"},{"id":63898,"url":"https://patchwork.plctlab.org/api/1.2/patches/63898/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5f7617d7-f545-cb43-e133-080abb5ede88@suse.com/","msgid":"<5f7617d7-f545-cb43-e133-080abb5ede88@suse.com>","list_archive_url":null,"date":"2023-03-03T13:01:14","name":"[09/18] x86: drop \"shimm\" special case template expansions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5f7617d7-f545-cb43-e133-080abb5ede88@suse.com/mbox/"},{"id":63899,"url":"https://patchwork.plctlab.org/api/1.2/patches/63899/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/42f27545-f571-c78f-415c-50817730faea@suse.com/","msgid":"<42f27545-f571-c78f-415c-50817730faea@suse.com>","list_archive_url":null,"date":"2023-03-03T13:01:41","name":"[10/18] x86/AT&T: restrict recognition of the \"absolute branch\" prefix character","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/42f27545-f571-c78f-415c-50817730faea@suse.com/mbox/"},{"id":63900,"url":"https://patchwork.plctlab.org/api/1.2/patches/63900/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c9bfa265-6d45-fc33-5b1b-db0b95824d92@suse.com/","msgid":"","list_archive_url":null,"date":"2023-03-03T13:02:44","name":"[11/18] x86: process instruction operands for .insn","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c9bfa265-6d45-fc33-5b1b-db0b95824d92@suse.com/mbox/"},{"id":63902,"url":"https://patchwork.plctlab.org/api/1.2/patches/63902/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/689eb629-ad65-4611-2a22-ac0dea62590d@suse.com/","msgid":"<689eb629-ad65-4611-2a22-ac0dea62590d@suse.com>","list_archive_url":null,"date":"2023-03-03T13:03:17","name":"[12/18] x86: decouple broadcast type and bytes fields","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/689eb629-ad65-4611-2a22-ac0dea62590d@suse.com/mbox/"},{"id":63903,"url":"https://patchwork.plctlab.org/api/1.2/patches/63903/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3bbf02eb-364b-88de-d6c5-3e63a79ee602@suse.com/","msgid":"<3bbf02eb-364b-88de-d6c5-3e63a79ee602@suse.com>","list_archive_url":null,"date":"2023-03-03T13:03:51","name":"[13/18] x86: handle EVEX Disp8 for .insn","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3bbf02eb-364b-88de-d6c5-3e63a79ee602@suse.com/mbox/"},{"id":63904,"url":"https://patchwork.plctlab.org/api/1.2/patches/63904/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/433b1d03-2e38-8b3f-be46-c859e678959f@suse.com/","msgid":"<433b1d03-2e38-8b3f-be46-c859e678959f@suse.com>","list_archive_url":null,"date":"2023-03-03T13:04:32","name":"[14/18] x86: allow for multiple immediates in output_disp()","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/433b1d03-2e38-8b3f-be46-c859e678959f@suse.com/mbox/"},{"id":63905,"url":"https://patchwork.plctlab.org/api/1.2/patches/63905/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d85d3d06-46e5-2f23-660a-0daaa9e5088f@suse.com/","msgid":"","list_archive_url":null,"date":"2023-03-03T13:05:00","name":"[15/18] x86: handle immediate operands for .insn","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d85d3d06-46e5-2f23-660a-0daaa9e5088f@suse.com/mbox/"},{"id":63906,"url":"https://patchwork.plctlab.org/api/1.2/patches/63906/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/14ee4656-f39a-59c4-48d0-c397b77ad969@suse.com/","msgid":"<14ee4656-f39a-59c4-48d0-c397b77ad969@suse.com>","list_archive_url":null,"date":"2023-03-03T13:05:36","name":"[16/18] x86: document .insn","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/14ee4656-f39a-59c4-48d0-c397b77ad969@suse.com/mbox/"},{"id":63907,"url":"https://patchwork.plctlab.org/api/1.2/patches/63907/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/10b9c1df-587e-e788-641b-43ccde48be21@suse.com/","msgid":"<10b9c1df-587e-e788-641b-43ccde48be21@suse.com>","list_archive_url":null,"date":"2023-03-03T13:06:25","name":"[17/18] x86: convert testcases to use .insn","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/10b9c1df-587e-e788-641b-43ccde48be21@suse.com/mbox/"},{"id":63908,"url":"https://patchwork.plctlab.org/api/1.2/patches/63908/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/390b97ee-c38a-4239-01a4-32d17ecdf44c@suse.com/","msgid":"<390b97ee-c38a-4239-01a4-32d17ecdf44c@suse.com>","list_archive_url":null,"date":"2023-03-03T13:06:56","name":"[RFC,18/18] x86: .insn example - VEX-encoded instructions of original Xeon Phi","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/390b97ee-c38a-4239-01a4-32d17ecdf44c@suse.com/mbox/"},{"id":63958,"url":"https://patchwork.plctlab.org/api/1.2/patches/63958/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230303144706.1977061-2-binutils@emagii.com/","msgid":"<20230303144706.1977061-2-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-03T14:46:56","name":"[v11,01/11] DIGEST: LICENSING","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230303144706.1977061-2-binutils@emagii.com/mbox/"},{"id":63953,"url":"https://patchwork.plctlab.org/api/1.2/patches/63953/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230303144706.1977061-3-binutils@emagii.com/","msgid":"<20230303144706.1977061-3-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-03T14:46:57","name":"[v11,02/11] DIGEST: NEWS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230303144706.1977061-3-binutils@emagii.com/mbox/"},{"id":63954,"url":"https://patchwork.plctlab.org/api/1.2/patches/63954/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230303144706.1977061-4-binutils@emagii.com/","msgid":"<20230303144706.1977061-4-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-03T14:46:58","name":"[v11,03/11] DIGEST: Documentation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230303144706.1977061-4-binutils@emagii.com/mbox/"},{"id":63966,"url":"https://patchwork.plctlab.org/api/1.2/patches/63966/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230303144706.1977061-5-binutils@emagii.com/","msgid":"<20230303144706.1977061-5-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-03T14:46:59","name":"[v11,04/11] DIGEST: testsuite","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230303144706.1977061-5-binutils@emagii.com/mbox/"},{"id":63962,"url":"https://patchwork.plctlab.org/api/1.2/patches/63962/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230303144706.1977061-6-binutils@emagii.com/","msgid":"<20230303144706.1977061-6-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-03T14:47:00","name":"[v11,05/11] DIGEST: ldlex.l","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230303144706.1977061-6-binutils@emagii.com/mbox/"},{"id":63960,"url":"https://patchwork.plctlab.org/api/1.2/patches/63960/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230303144706.1977061-7-binutils@emagii.com/","msgid":"<20230303144706.1977061-7-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-03T14:47:01","name":"[v11,06/11] DIGEST: ldgram.y","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230303144706.1977061-7-binutils@emagii.com/mbox/"},{"id":63964,"url":"https://patchwork.plctlab.org/api/1.2/patches/63964/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230303144706.1977061-8-binutils@emagii.com/","msgid":"<20230303144706.1977061-8-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-03T14:47:02","name":"[v11,07/11] DIGEST: ldmain.c","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230303144706.1977061-8-binutils@emagii.com/mbox/"},{"id":63961,"url":"https://patchwork.plctlab.org/api/1.2/patches/63961/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230303144706.1977061-9-binutils@emagii.com/","msgid":"<20230303144706.1977061-9-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-03T14:47:03","name":"[v11,08/11] DIGEST: ldlang.*: add timestamp","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230303144706.1977061-9-binutils@emagii.com/mbox/"},{"id":63955,"url":"https://patchwork.plctlab.org/api/1.2/patches/63955/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230303144706.1977061-10-binutils@emagii.com/","msgid":"<20230303144706.1977061-10-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-03T14:47:04","name":"[v11,09/11] DIGEST: calculation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230303144706.1977061-10-binutils@emagii.com/mbox/"},{"id":63967,"url":"https://patchwork.plctlab.org/api/1.2/patches/63967/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230303144706.1977061-11-binutils@emagii.com/","msgid":"<20230303144706.1977061-11-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-03T14:47:05","name":"[v11,10/11] DIGEST: Makefile.*","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230303144706.1977061-11-binutils@emagii.com/mbox/"},{"id":63965,"url":"https://patchwork.plctlab.org/api/1.2/patches/63965/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230303144706.1977061-12-binutils@emagii.com/","msgid":"<20230303144706.1977061-12-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-03T14:47:06","name":"[v11,11/11] Build ldint","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230303144706.1977061-12-binutils@emagii.com/mbox/"},{"id":64411,"url":"https://patchwork.plctlab.org/api/1.2/patches/64411/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZAVdsMx3t7PJx6/N@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-06T03:27:44","name":"Correct objdump command line error handling","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZAVdsMx3t7PJx6/N@squeak.grove.modra.org/mbox/"},{"id":64412,"url":"https://patchwork.plctlab.org/api/1.2/patches/64412/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZAVdzGu9AOUk0jwF@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-06T03:28:12","name":"Move nm.c cached line number info to bfd usrdata","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZAVdzGu9AOUk0jwF@squeak.grove.modra.org/mbox/"},{"id":64413,"url":"https://patchwork.plctlab.org/api/1.2/patches/64413/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZAVd75QsC9WDKjib@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-06T03:28:47","name":"Downgrade nm fatal errors to non-fatal","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZAVd75QsC9WDKjib@squeak.grove.modra.org/mbox/"},{"id":64414,"url":"https://patchwork.plctlab.org/api/1.2/patches/64414/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZAVeXfeOtW187hlw@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-06T03:30:37","name":"Downgrade addr2line fatal errors to non-fatal","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZAVeXfeOtW187hlw@squeak.grove.modra.org/mbox/"},{"id":64415,"url":"https://patchwork.plctlab.org/api/1.2/patches/64415/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZAVefjechteynu1f@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-06T03:31:10","name":"Downgrade objdump fatal errors to non-fatal","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZAVefjechteynu1f@squeak.grove.modra.org/mbox/"},{"id":64416,"url":"https://patchwork.plctlab.org/api/1.2/patches/64416/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZAVeo2/RNgqKm+AA@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-06T03:31:47","name":"Correct odd loop in ecoff lookup_line","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZAVeo2/RNgqKm+AA@squeak.grove.modra.org/mbox/"},{"id":64418,"url":"https://patchwork.plctlab.org/api/1.2/patches/64418/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZAVewBOf2ip1On9w@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-06T03:32:16","name":"More _bfd_ecoff_locate_line sanity checks","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZAVewBOf2ip1On9w@squeak.grove.modra.org/mbox/"},{"id":64417,"url":"https://patchwork.plctlab.org/api/1.2/patches/64417/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZAVe3UuTbz+f5v74@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-06T03:32:45","name":"PR30198, Assertion and segfault when linking x86_64 elf and coff","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZAVe3UuTbz+f5v74@squeak.grove.modra.org/mbox/"},{"id":64619,"url":"https://patchwork.plctlab.org/api/1.2/patches/64619/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZAXSk4uW7BEA153b@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-06T11:46:27","name":"macho null dereference read","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZAXSk4uW7BEA153b@squeak.grove.modra.org/mbox/"},{"id":64651,"url":"https://patchwork.plctlab.org/api/1.2/patches/64651/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230306133158.91917-2-binutils@emagii.com/","msgid":"<20230306133158.91917-2-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-06T13:31:48","name":"[v12,01/11] DIGEST: LICENSING","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230306133158.91917-2-binutils@emagii.com/mbox/"},{"id":64652,"url":"https://patchwork.plctlab.org/api/1.2/patches/64652/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230306133158.91917-3-binutils@emagii.com/","msgid":"<20230306133158.91917-3-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-06T13:31:49","name":"[v12,02/11] DIGEST: NEWS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230306133158.91917-3-binutils@emagii.com/mbox/"},{"id":64653,"url":"https://patchwork.plctlab.org/api/1.2/patches/64653/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230306133158.91917-4-binutils@emagii.com/","msgid":"<20230306133158.91917-4-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-06T13:31:50","name":"[v12,03/11] DIGEST: Documentation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230306133158.91917-4-binutils@emagii.com/mbox/"},{"id":64657,"url":"https://patchwork.plctlab.org/api/1.2/patches/64657/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230306133158.91917-5-binutils@emagii.com/","msgid":"<20230306133158.91917-5-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-06T13:31:51","name":"[v12,04/11] DIGEST: testsuite","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230306133158.91917-5-binutils@emagii.com/mbox/"},{"id":64654,"url":"https://patchwork.plctlab.org/api/1.2/patches/64654/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230306133158.91917-6-binutils@emagii.com/","msgid":"<20230306133158.91917-6-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-06T13:31:52","name":"[v12,05/11] DIGEST: ldlex.l","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230306133158.91917-6-binutils@emagii.com/mbox/"},{"id":64655,"url":"https://patchwork.plctlab.org/api/1.2/patches/64655/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230306133158.91917-7-binutils@emagii.com/","msgid":"<20230306133158.91917-7-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-06T13:31:53","name":"[v12,06/11] DIGEST: ldgram.y","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230306133158.91917-7-binutils@emagii.com/mbox/"},{"id":64656,"url":"https://patchwork.plctlab.org/api/1.2/patches/64656/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230306133158.91917-8-binutils@emagii.com/","msgid":"<20230306133158.91917-8-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-06T13:31:54","name":"[v12,07/11] DIGEST: ldmain.c","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230306133158.91917-8-binutils@emagii.com/mbox/"},{"id":64658,"url":"https://patchwork.plctlab.org/api/1.2/patches/64658/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230306133158.91917-9-binutils@emagii.com/","msgid":"<20230306133158.91917-9-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-06T13:31:55","name":"[v12,08/11] DIGEST: ldlang.*: add timestamp","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230306133158.91917-9-binutils@emagii.com/mbox/"},{"id":64661,"url":"https://patchwork.plctlab.org/api/1.2/patches/64661/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230306133158.91917-10-binutils@emagii.com/","msgid":"<20230306133158.91917-10-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-06T13:31:56","name":"[v12,09/11] DIGEST: calculation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230306133158.91917-10-binutils@emagii.com/mbox/"},{"id":64660,"url":"https://patchwork.plctlab.org/api/1.2/patches/64660/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230306133158.91917-11-binutils@emagii.com/","msgid":"<20230306133158.91917-11-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-06T13:31:57","name":"[v12,10/11] DIGEST: Makefile.*","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230306133158.91917-11-binutils@emagii.com/mbox/"},{"id":64659,"url":"https://patchwork.plctlab.org/api/1.2/patches/64659/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230306133158.91917-12-binutils@emagii.com/","msgid":"<20230306133158.91917-12-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-06T13:31:58","name":"[v12,11/11] Build ldint","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230306133158.91917-12-binutils@emagii.com/mbox/"},{"id":65273,"url":"https://patchwork.plctlab.org/api/1.2/patches/65273/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230307050431.288433-1-vladimir.mezentsev@oracle.com/","msgid":"<20230307050431.288433-1-vladimir.mezentsev@oracle.com>","list_archive_url":null,"date":"2023-03-07T05:04:31","name":"[Review,is,needed] gprofng: read Dwarf 5","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230307050431.288433-1-vladimir.mezentsev@oracle.com/mbox/"},{"id":65986,"url":"https://patchwork.plctlab.org/api/1.2/patches/65986/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZAf9qw1lk5r9MWOY@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-08T03:14:51","name":"z8 and z80 coff_reloc16_extra_cases sanity checks","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZAf9qw1lk5r9MWOY@squeak.grove.modra.org/mbox/"},{"id":65987,"url":"https://patchwork.plctlab.org/api/1.2/patches/65987/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZAf96/aiNOmLZEuS@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-08T03:15:55","name":"Regen potfiles","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZAf96/aiNOmLZEuS@squeak.grove.modra.org/mbox/"},{"id":66046,"url":"https://patchwork.plctlab.org/api/1.2/patches/66046/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZAg5M/tmFWFGCq2N@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-08T07:28:51","name":"Tidy pe_ILF_build_a_bfd a little","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZAg5M/tmFWFGCq2N@squeak.grove.modra.org/mbox/"},{"id":66183,"url":"https://patchwork.plctlab.org/api/1.2/patches/66183/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230308125441.356419-2-binutils@emagii.com/","msgid":"<20230308125441.356419-2-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-08T12:54:41","name":"[v1] DIGEST: Disable 64-bit CRC for 32-bit BFD","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230308125441.356419-2-binutils@emagii.com/mbox/"},{"id":66328,"url":"https://patchwork.plctlab.org/api/1.2/patches/66328/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a513b979-d455-eea6-ba19-1af0dff5d4e2@suse.com/","msgid":"","list_archive_url":null,"date":"2023-03-08T16:07:35","name":"[1/4] gas: drop function pointer parameter from macro_init()","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a513b979-d455-eea6-ba19-1af0dff5d4e2@suse.com/mbox/"},{"id":66329,"url":"https://patchwork.plctlab.org/api/1.2/patches/66329/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e7780d8a-ad1c-a738-a7f5-f5b70c46c6fe@suse.com/","msgid":"","list_archive_url":null,"date":"2023-03-08T16:08:17","name":"[2/4] gas: isolate macro_strip_at to macro.c","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e7780d8a-ad1c-a738-a7f5-f5b70c46c6fe@suse.com/mbox/"},{"id":66332,"url":"https://patchwork.plctlab.org/api/1.2/patches/66332/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0cdb6ff1-8f31-8222-629f-cb991a1efb63@suse.com/","msgid":"<0cdb6ff1-8f31-8222-629f-cb991a1efb63@suse.com>","list_archive_url":null,"date":"2023-03-08T16:08:39","name":"[3/4] gas: use flag_mri directly in macro processing","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0cdb6ff1-8f31-8222-629f-cb991a1efb63@suse.com/mbox/"},{"id":66336,"url":"https://patchwork.plctlab.org/api/1.2/patches/66336/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/06908d40-8d11-9540-6932-efb4f54dba0f@suse.com/","msgid":"<06908d40-8d11-9540-6932-efb4f54dba0f@suse.com>","list_archive_url":null,"date":"2023-03-08T16:09:22","name":"[4/4] gas: expose flag_macro_alternate globally","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/06908d40-8d11-9540-6932-efb4f54dba0f@suse.com/mbox/"},{"id":66649,"url":"https://patchwork.plctlab.org/api/1.2/patches/66649/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230309080446.24714-1-nelson@rivosinc.com/","msgid":"<20230309080446.24714-1-nelson@rivosinc.com>","list_archive_url":null,"date":"2023-03-09T08:04:46","name":"RISC-V: Segment fault in riscv_elf_append_rela.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230309080446.24714-1-nelson@rivosinc.com/mbox/"},{"id":66827,"url":"https://patchwork.plctlab.org/api/1.2/patches/66827/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZAnOJ6t4+ezsABPt@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-09T12:16:39","name":"Allow frag address wrapping in absolute section","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZAnOJ6t4+ezsABPt@squeak.grove.modra.org/mbox/"},{"id":66828,"url":"https://patchwork.plctlab.org/api/1.2/patches/66828/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZAnOVl9L363M77Cx@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-09T12:17:26","name":"objdump: report no section contents","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZAnOVl9L363M77Cx@squeak.grove.modra.org/mbox/"},{"id":67175,"url":"https://patchwork.plctlab.org/api/1.2/patches/67175/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230310000817.751962-2-binutils@emagii.com/","msgid":"<20230310000817.751962-2-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-10T00:08:11","name":"[v1,1/7] SECTOR: NEWS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230310000817.751962-2-binutils@emagii.com/mbox/"},{"id":67174,"url":"https://patchwork.plctlab.org/api/1.2/patches/67174/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230310000817.751962-3-binutils@emagii.com/","msgid":"<20230310000817.751962-3-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-10T00:08:12","name":"[v1,2/7] SECTOR: ld.texi","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230310000817.751962-3-binutils@emagii.com/mbox/"},{"id":67177,"url":"https://patchwork.plctlab.org/api/1.2/patches/67177/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230310000817.751962-4-binutils@emagii.com/","msgid":"<20230310000817.751962-4-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-10T00:08:13","name":"[v1,3/7] SECTOR: ldlex.l","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230310000817.751962-4-binutils@emagii.com/mbox/"},{"id":67179,"url":"https://patchwork.plctlab.org/api/1.2/patches/67179/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230310000817.751962-5-binutils@emagii.com/","msgid":"<20230310000817.751962-5-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-10T00:08:14","name":"[v1,4/7] SECTOR: ldgram.y","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230310000817.751962-5-binutils@emagii.com/mbox/"},{"id":67180,"url":"https://patchwork.plctlab.org/api/1.2/patches/67180/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230310000817.751962-6-binutils@emagii.com/","msgid":"<20230310000817.751962-6-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-10T00:08:15","name":"[v1,5/7] SECTOR: language additions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230310000817.751962-6-binutils@emagii.com/mbox/"},{"id":67176,"url":"https://patchwork.plctlab.org/api/1.2/patches/67176/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230310000817.751962-7-binutils@emagii.com/","msgid":"<20230310000817.751962-7-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-10T00:08:16","name":"[v1,6/7] SECTOR: add testsuite","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230310000817.751962-7-binutils@emagii.com/mbox/"},{"id":67178,"url":"https://patchwork.plctlab.org/api/1.2/patches/67178/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230310000817.751962-8-binutils@emagii.com/","msgid":"<20230310000817.751962-8-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-10T00:08:17","name":"[v1,7/7] SECTOR: Makefile.*","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230310000817.751962-8-binutils@emagii.com/mbox/"},{"id":67202,"url":"https://patchwork.plctlab.org/api/1.2/patches/67202/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZAqu271thSCsaKU3@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-10T04:15:23","name":"eh static data","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZAqu271thSCsaKU3@squeak.grove.modra.org/mbox/"},{"id":67293,"url":"https://patchwork.plctlab.org/api/1.2/patches/67293/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f1892080-b6fe-a164-73bb-91cd88302e0f@suse.com/","msgid":"","list_archive_url":null,"date":"2023-03-10T09:25:27","name":"[v2,1/7] RISC-V: minor effort reduction in relocation specifier parsing","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f1892080-b6fe-a164-73bb-91cd88302e0f@suse.com/mbox/"},{"id":67294,"url":"https://patchwork.plctlab.org/api/1.2/patches/67294/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/366e4dcf-e273-a321-dd38-7adf4212c901@suse.com/","msgid":"<366e4dcf-e273-a321-dd38-7adf4212c901@suse.com>","list_archive_url":null,"date":"2023-03-10T09:26:00","name":"[v2,2/7] RISC-V: drop \"percent_op\" parameter from my_getOpcodeExpression()","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/366e4dcf-e273-a321-dd38-7adf4212c901@suse.com/mbox/"},{"id":67296,"url":"https://patchwork.plctlab.org/api/1.2/patches/67296/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5352e5fd-d1c5-4267-c802-73d6074e80ca@suse.com/","msgid":"<5352e5fd-d1c5-4267-c802-73d6074e80ca@suse.com>","list_archive_url":null,"date":"2023-03-10T09:26:25","name":"[v2,3/7] RISC-V: avoid redundant and misleading/wrong error messages","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5352e5fd-d1c5-4267-c802-73d6074e80ca@suse.com/mbox/"},{"id":67297,"url":"https://patchwork.plctlab.org/api/1.2/patches/67297/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ebffbf50-fa83-8e7e-eedd-d9e9d1b4aa04@suse.com/","msgid":"","list_archive_url":null,"date":"2023-03-10T09:27:05","name":"[v2,4/7] RISC-V: don'\''t recognize bogus relocations","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ebffbf50-fa83-8e7e-eedd-d9e9d1b4aa04@suse.com/mbox/"},{"id":67302,"url":"https://patchwork.plctlab.org/api/1.2/patches/67302/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/89f892c8-e378-b81c-7b13-322a7876a252@suse.com/","msgid":"<89f892c8-e378-b81c-7b13-322a7876a252@suse.com>","list_archive_url":null,"date":"2023-03-10T09:27:26","name":"[v2,5/7] RISC-V: relax post-relocation-operator separator expectation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/89f892c8-e378-b81c-7b13-322a7876a252@suse.com/mbox/"},{"id":67301,"url":"https://patchwork.plctlab.org/api/1.2/patches/67301/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/756c5464-9bcb-d78f-c763-4bb5504eec92@suse.com/","msgid":"<756c5464-9bcb-d78f-c763-4bb5504eec92@suse.com>","list_archive_url":null,"date":"2023-03-10T09:27:58","name":"[v2,6/7] RISC-V: test for expected / no unexpected symbols","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/756c5464-9bcb-d78f-c763-4bb5504eec92@suse.com/mbox/"},{"id":67305,"url":"https://patchwork.plctlab.org/api/1.2/patches/67305/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/54b0d4cc-855a-78c7-5233-22f7d454c0c4@suse.com/","msgid":"<54b0d4cc-855a-78c7-5233-22f7d454c0c4@suse.com>","list_archive_url":null,"date":"2023-03-10T09:28:23","name":"[v2,7/7] RISC-V: adjust logic to avoid register name symbols","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/54b0d4cc-855a-78c7-5233-22f7d454c0c4@suse.com/mbox/"},{"id":67308,"url":"https://patchwork.plctlab.org/api/1.2/patches/67308/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/150b4184-62af-3f5c-c07b-24b0c2ae788f@suse.com/","msgid":"<150b4184-62af-3f5c-c07b-24b0c2ae788f@suse.com>","list_archive_url":null,"date":"2023-03-10T09:36:31","name":"[RFC] RISC-V: alter the special character used in FAKE_LABEL_NAME","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/150b4184-62af-3f5c-c07b-24b0c2ae788f@suse.com/mbox/"},{"id":67313,"url":"https://patchwork.plctlab.org/api/1.2/patches/67313/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c7f7f3a2-033c-da49-6e04-9a1df21eef6f@suse.com/","msgid":"","list_archive_url":null,"date":"2023-03-10T09:43:48","name":"gas: apply md_register_arithmetic also to unary '\''+'\''","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c7f7f3a2-033c-da49-6e04-9a1df21eef6f@suse.com/mbox/"},{"id":67317,"url":"https://patchwork.plctlab.org/api/1.2/patches/67317/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/312cb612-378a-be36-6f6c-62df7313975d@suse.com/","msgid":"<312cb612-378a-be36-6f6c-62df7313975d@suse.com>","list_archive_url":null,"date":"2023-03-10T10:11:28","name":"x86: drop identifier_chars[]","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/312cb612-378a-be36-6f6c-62df7313975d@suse.com/mbox/"},{"id":67319,"url":"https://patchwork.plctlab.org/api/1.2/patches/67319/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/97d9240d-2d1a-d7a4-35e4-7cec1f418f38@suse.com/","msgid":"<97d9240d-2d1a-d7a4-35e4-7cec1f418f38@suse.com>","list_archive_url":null,"date":"2023-03-10T10:19:22","name":"[v2,01/14] x86: introduce .insn directive","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/97d9240d-2d1a-d7a4-35e4-7cec1f418f38@suse.com/mbox/"},{"id":67320,"url":"https://patchwork.plctlab.org/api/1.2/patches/67320/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8df023f9-58a5-dca7-badd-f3354ed18442@suse.com/","msgid":"<8df023f9-58a5-dca7-badd-f3354ed18442@suse.com>","list_archive_url":null,"date":"2023-03-10T10:19:50","name":"[v2,02/14] x86: parse VEX and alike specifiers for .insn","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8df023f9-58a5-dca7-badd-f3354ed18442@suse.com/mbox/"},{"id":67321,"url":"https://patchwork.plctlab.org/api/1.2/patches/67321/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5771df73-12d8-e880-a051-86c09d6bdb06@suse.com/","msgid":"<5771df73-12d8-e880-a051-86c09d6bdb06@suse.com>","list_archive_url":null,"date":"2023-03-10T10:20:26","name":"[v2,03/14] x86: parse special opcode modifiers for .insn","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5771df73-12d8-e880-a051-86c09d6bdb06@suse.com/mbox/"},{"id":67322,"url":"https://patchwork.plctlab.org/api/1.2/patches/67322/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fba4e20a-8b63-652c-7766-8b0ba47f1672@suse.com/","msgid":"","list_archive_url":null,"date":"2023-03-10T10:21:11","name":"[v2,04/14] x86: re-work build_modrm_byte()'\''s register assignment","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fba4e20a-8b63-652c-7766-8b0ba47f1672@suse.com/mbox/"},{"id":67325,"url":"https://patchwork.plctlab.org/api/1.2/patches/67325/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/08829d31-820b-7dea-5609-de609bf69aa9@suse.com/","msgid":"<08829d31-820b-7dea-5609-de609bf69aa9@suse.com>","list_archive_url":null,"date":"2023-03-10T10:21:48","name":"[v2,05/14] x86: VexVVVV is now merely a boolean","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/08829d31-820b-7dea-5609-de609bf69aa9@suse.com/mbox/"},{"id":67323,"url":"https://patchwork.plctlab.org/api/1.2/patches/67323/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a4fdab7e-bc8f-ff75-6be2-559f053bef28@suse.com/","msgid":"","list_archive_url":null,"date":"2023-03-10T10:22:16","name":"[v2,06/14] x86: drop \"shimm\" special case template expansions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a4fdab7e-bc8f-ff75-6be2-559f053bef28@suse.com/mbox/"},{"id":67326,"url":"https://patchwork.plctlab.org/api/1.2/patches/67326/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/667d9ad0-3165-08cf-dead-efd27a5d267e@suse.com/","msgid":"<667d9ad0-3165-08cf-dead-efd27a5d267e@suse.com>","list_archive_url":null,"date":"2023-03-10T10:22:38","name":"[v2,07/14] x86/AT&T: restrict recognition of the \"absolute branch\" prefix character","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/667d9ad0-3165-08cf-dead-efd27a5d267e@suse.com/mbox/"},{"id":67327,"url":"https://patchwork.plctlab.org/api/1.2/patches/67327/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8d917f97-af55-11f3-a9f8-d5a209725336@suse.com/","msgid":"<8d917f97-af55-11f3-a9f8-d5a209725336@suse.com>","list_archive_url":null,"date":"2023-03-10T10:23:40","name":"[v2,08/14] x86: process instruction operands for .insn","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8d917f97-af55-11f3-a9f8-d5a209725336@suse.com/mbox/"},{"id":67328,"url":"https://patchwork.plctlab.org/api/1.2/patches/67328/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/010a5ae0-91a5-813b-8896-8fd11d5383d7@suse.com/","msgid":"<010a5ae0-91a5-813b-8896-8fd11d5383d7@suse.com>","list_archive_url":null,"date":"2023-03-10T10:24:03","name":"[v2,09/14] x86: handle EVEX Disp8 for .insn","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/010a5ae0-91a5-813b-8896-8fd11d5383d7@suse.com/mbox/"},{"id":67329,"url":"https://patchwork.plctlab.org/api/1.2/patches/67329/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/68848170-59cb-6546-6e7f-527f65a8c1fe@suse.com/","msgid":"<68848170-59cb-6546-6e7f-527f65a8c1fe@suse.com>","list_archive_url":null,"date":"2023-03-10T10:24:53","name":"[v2,10/14] x86: allow for multiple immediates in output_disp()","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/68848170-59cb-6546-6e7f-527f65a8c1fe@suse.com/mbox/"},{"id":67330,"url":"https://patchwork.plctlab.org/api/1.2/patches/67330/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a154c5f8-b5af-320d-f542-5dfccbefba3b@suse.com/","msgid":"","list_archive_url":null,"date":"2023-03-10T10:25:43","name":"[v2,11/14] x86: handle immediate operands for .insn","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a154c5f8-b5af-320d-f542-5dfccbefba3b@suse.com/mbox/"},{"id":67331,"url":"https://patchwork.plctlab.org/api/1.2/patches/67331/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e11eeb2e-0e16-886e-ee81-bf9a57f57965@suse.com/","msgid":"","list_archive_url":null,"date":"2023-03-10T10:26:03","name":"[v2,12/14] x86: document .insn","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e11eeb2e-0e16-886e-ee81-bf9a57f57965@suse.com/mbox/"},{"id":67332,"url":"https://patchwork.plctlab.org/api/1.2/patches/67332/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2b0ca132-9d85-86a8-8b91-828fa66881b8@suse.com/","msgid":"<2b0ca132-9d85-86a8-8b91-828fa66881b8@suse.com>","list_archive_url":null,"date":"2023-03-10T10:26:44","name":"[v2,13/14] x86: convert testcases to use .insn","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2b0ca132-9d85-86a8-8b91-828fa66881b8@suse.com/mbox/"},{"id":67333,"url":"https://patchwork.plctlab.org/api/1.2/patches/67333/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/df8e84be-1e77-07ee-aff6-d457e9b0f818@suse.com/","msgid":"","list_archive_url":null,"date":"2023-03-10T10:27:47","name":"[RFC,v2,14/14] x86: .insn example - VEX-encoded instructions of original Xeon Phi","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/df8e84be-1e77-07ee-aff6-d457e9b0f818@suse.com/mbox/"},{"id":68729,"url":"https://patchwork.plctlab.org/api/1.2/patches/68729/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230313102216.355828-1-och95@yandex.ru/","msgid":"<20230313102216.355828-1-och95@yandex.ru>","list_archive_url":null,"date":"2023-03-13T10:22:16","name":"Fix emit-relocs for aarch64 gold","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230313102216.355828-1-och95@yandex.ru/mbox/"},{"id":69242,"url":"https://patchwork.plctlab.org/api/1.2/patches/69242/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZA/V6rdHyBWRJeg/@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-14T02:03:22","name":"gas/compress-debug.c init all of strm","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZA/V6rdHyBWRJeg/@squeak.grove.modra.org/mbox/"},{"id":69243,"url":"https://patchwork.plctlab.org/api/1.2/patches/69243/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZA/WAkr1NO7joSsy@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-14T02:03:46","name":"gas/ecoff.c: don'\''t use zero struct copies to init","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZA/WAkr1NO7joSsy@squeak.grove.modra.org/mbox/"},{"id":69245,"url":"https://patchwork.plctlab.org/api/1.2/patches/69245/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZA/WGWSYR8IA1rJl@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-14T02:04:09","name":"gas/dwarf2dbg.c init more statics","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZA/WGWSYR8IA1rJl@squeak.grove.modra.org/mbox/"},{"id":69244,"url":"https://patchwork.plctlab.org/api/1.2/patches/69244/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZA/WNm1YCQpP7t+a@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-14T02:04:38","name":"gas .include and .incbin","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZA/WNm1YCQpP7t+a@squeak.grove.modra.org/mbox/"},{"id":69246,"url":"https://patchwork.plctlab.org/api/1.2/patches/69246/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZA/WTCOXOOCfB3kP@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-14T02:05:00","name":"gas/read.c: init more statics","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZA/WTCOXOOCfB3kP@squeak.grove.modra.org/mbox/"},{"id":69247,"url":"https://patchwork.plctlab.org/api/1.2/patches/69247/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZA/Wa/V9ZyhkIDlz@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-14T02:05:31","name":"Sanity check read_section_stabs_debugging_info","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZA/Wa/V9ZyhkIDlz@squeak.grove.modra.org/mbox/"},{"id":69248,"url":"https://patchwork.plctlab.org/api/1.2/patches/69248/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZA/WoJ/0CrDmzojB@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-14T02:06:24","name":"objdump segfault after symbol table error","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZA/WoJ/0CrDmzojB@squeak.grove.modra.org/mbox/"},{"id":69845,"url":"https://patchwork.plctlab.org/api/1.2/patches/69845/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230314220114.1117782-2-binutils@emagii.com/","msgid":"<20230314220114.1117782-2-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-14T22:01:12","name":"[v1,1/3] CHIP: ldlex.l","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230314220114.1117782-2-binutils@emagii.com/mbox/"},{"id":69843,"url":"https://patchwork.plctlab.org/api/1.2/patches/69843/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230314220114.1117782-3-binutils@emagii.com/","msgid":"<20230314220114.1117782-3-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-14T22:01:13","name":"[v1,2/3] CHIP: ldgram.y","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230314220114.1117782-3-binutils@emagii.com/mbox/"},{"id":69844,"url":"https://patchwork.plctlab.org/api/1.2/patches/69844/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230314220114.1117782-4-binutils@emagii.com/","msgid":"<20230314220114.1117782-4-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-14T22:01:14","name":"[v1,3/3] CHIP: language additions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230314220114.1117782-4-binutils@emagii.com/mbox/"},{"id":70532,"url":"https://patchwork.plctlab.org/api/1.2/patches/70532/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZBJprOGHAKOvXNTu@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-16T00:58:20","name":"PR30217, dynamic relocations using local dynamic symbols","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZBJprOGHAKOvXNTu@squeak.grove.modra.org/mbox/"},{"id":70595,"url":"https://patchwork.plctlab.org/api/1.2/patches/70595/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZBK+tK3Heqd68P3Y@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-16T07:01:08","name":"cpu/mem.opc whitespace tidy","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZBK+tK3Heqd68P3Y@squeak.grove.modra.org/mbox/"},{"id":70703,"url":"https://patchwork.plctlab.org/api/1.2/patches/70703/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230316101736.482737-2-chigot@adacore.com/","msgid":"<20230316101736.482737-2-chigot@adacore.com>","list_archive_url":null,"date":"2023-03-16T10:17:32","name":"[1/5] configure: add new target aarch64-*-nto*","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230316101736.482737-2-chigot@adacore.com/mbox/"},{"id":70705,"url":"https://patchwork.plctlab.org/api/1.2/patches/70705/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230316101736.482737-3-chigot@adacore.com/","msgid":"<20230316101736.482737-3-chigot@adacore.com>","list_archive_url":null,"date":"2023-03-16T10:17:33","name":"[2/5] readelf: add support for QNT_STACK note subsections","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230316101736.482737-3-chigot@adacore.com/mbox/"},{"id":70706,"url":"https://patchwork.plctlab.org/api/1.2/patches/70706/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230316101736.482737-4-chigot@adacore.com/","msgid":"<20230316101736.482737-4-chigot@adacore.com>","list_archive_url":null,"date":"2023-03-16T10:17:34","name":"[3/5] ld: add support of QNX stack arguments for aarch64nto","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230316101736.482737-4-chigot@adacore.com/mbox/"},{"id":70704,"url":"https://patchwork.plctlab.org/api/1.2/patches/70704/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230316101736.482737-5-chigot@adacore.com/","msgid":"<20230316101736.482737-5-chigot@adacore.com>","list_archive_url":null,"date":"2023-03-16T10:17:35","name":"[4/5] ld/testsuite: add aarch64nto to ld-aarch64","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230316101736.482737-5-chigot@adacore.com/mbox/"},{"id":70707,"url":"https://patchwork.plctlab.org/api/1.2/patches/70707/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230316101736.482737-6-chigot@adacore.com/","msgid":"<20230316101736.482737-6-chigot@adacore.com>","list_archive_url":null,"date":"2023-03-16T10:17:36","name":"[5/5] ld/testsuite: disable ilp32 tests for aarch64-qnx","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230316101736.482737-6-chigot@adacore.com/mbox/"},{"id":70782,"url":"https://patchwork.plctlab.org/api/1.2/patches/70782/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230316132101.205752-1-christophe.lyon@linaro.org/","msgid":"<20230316132101.205752-1-christophe.lyon@linaro.org>","list_archive_url":null,"date":"2023-03-16T13:21:01","name":"Re: Add --enable-linker-version option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230316132101.205752-1-christophe.lyon@linaro.org/mbox/"},{"id":71031,"url":"https://patchwork.plctlab.org/api/1.2/patches/71031/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230317015323.567132-1-jiawei@iscas.ac.cn/","msgid":"<20230317015323.567132-1-jiawei@iscas.ac.cn>","list_archive_url":null,"date":"2023-03-17T01:53:23","name":"RISC-V: Adjust the '\''print_insn'\'' return value of disassembling.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230317015323.567132-1-jiawei@iscas.ac.cn/mbox/"},{"id":71117,"url":"https://patchwork.plctlab.org/api/1.2/patches/71117/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZBQb0o0YlU860KEo@fedora/","msgid":"","list_archive_url":null,"date":"2023-03-17T07:50:42","name":"Add support to readelf for the PT_OPENBSD_MUTABLE segment type.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZBQb0o0YlU860KEo@fedora/mbox/"},{"id":71230,"url":"https://patchwork.plctlab.org/api/1.2/patches/71230/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZBRD1+lZYMBOT2i6@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-17T10:41:27","name":"strange segfault i386-dis.c:9815:28","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZBRD1+lZYMBOT2i6@squeak.grove.modra.org/mbox/"},{"id":71234,"url":"https://patchwork.plctlab.org/api/1.2/patches/71234/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZBRE2M3WrYfRkhVz@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-17T10:45:44","name":"Another source_sh","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZBRE2M3WrYfRkhVz@squeak.grove.modra.org/mbox/"},{"id":71237,"url":"https://patchwork.plctlab.org/api/1.2/patches/71237/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZBRE8g4zs0fVGz5o@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-17T10:46:10","name":"mach-o: out of memory in get_dynamic_reloc_upper_bound","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZBRE8g4zs0fVGz5o@squeak.grove.modra.org/mbox/"},{"id":71244,"url":"https://patchwork.plctlab.org/api/1.2/patches/71244/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230317105552.82190-1-nelson@rivosinc.com/","msgid":"<20230317105552.82190-1-nelson@rivosinc.com>","list_archive_url":null,"date":"2023-03-17T10:55:52","name":"RISC-V: Clarify link behaviors of R_RISCV_32/64 relocations with ABS symbol.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230317105552.82190-1-nelson@rivosinc.com/mbox/"},{"id":71345,"url":"https://patchwork.plctlab.org/api/1.2/patches/71345/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230317160045.502282-2-cupertino.miranda@oracle.com/","msgid":"<20230317160045.502282-2-cupertino.miranda@oracle.com>","list_archive_url":null,"date":"2023-03-17T16:00:44","name":"[1/2] Reloc howto access broken for BPF","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230317160045.502282-2-cupertino.miranda@oracle.com/mbox/"},{"id":71346,"url":"https://patchwork.plctlab.org/api/1.2/patches/71346/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230317160045.502282-3-cupertino.miranda@oracle.com/","msgid":"<20230317160045.502282-3-cupertino.miranda@oracle.com>","list_archive_url":null,"date":"2023-03-17T16:00:45","name":"[2/2] Changed ld and gas BPF tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230317160045.502282-3-cupertino.miranda@oracle.com/mbox/"},{"id":71521,"url":"https://patchwork.plctlab.org/api/1.2/patches/71521/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230317233448.1832535-1-vladimir.mezentsev@oracle.com/","msgid":"<20230317233448.1832535-1-vladimir.mezentsev@oracle.com>","list_archive_url":null,"date":"2023-03-17T23:34:48","name":"[Review,is,neded] gprofng: Use prototype to call libc functions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230317233448.1832535-1-vladimir.mezentsev@oracle.com/mbox/"},{"id":71749,"url":"https://patchwork.plctlab.org/api/1.2/patches/71749/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZBb3JpbiFebpIfHc@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-19T11:51:02","name":"ctf segfaults","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZBb3JpbiFebpIfHc@squeak.grove.modra.org/mbox/"},{"id":71751,"url":"https://patchwork.plctlab.org/api/1.2/patches/71751/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZBb3UOUJo8DAMRJy@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-19T11:51:44","name":"Another sanity check for read_section_stabs_debugging_info","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZBb3UOUJo8DAMRJy@squeak.grove.modra.org/mbox/"},{"id":71752,"url":"https://patchwork.plctlab.org/api/1.2/patches/71752/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZBb3eQ0ulZBDWzmK@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-19T11:52:25","name":"rewrite_elf_program_header and want_p_paddr_set_to_zero","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZBb3eQ0ulZBDWzmK@squeak.grove.modra.org/mbox/"},{"id":71753,"url":"https://patchwork.plctlab.org/api/1.2/patches/71753/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZBb3oOZ4J35lf6nK@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-19T11:53:04","name":"XCOFF archive sanity check","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZBb3oOZ4J35lf6nK@squeak.grove.modra.org/mbox/"},{"id":71754,"url":"https://patchwork.plctlab.org/api/1.2/patches/71754/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZBb3vmeOkA/l+tlY@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-19T11:53:34","name":"Regen ld/po/BLD-POTFILES.in","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZBb3vmeOkA/l+tlY@squeak.grove.modra.org/mbox/"},{"id":71942,"url":"https://patchwork.plctlab.org/api/1.2/patches/71942/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230320033444.2819-1-jiawei@iscas.ac.cn/","msgid":"<20230320033444.2819-1-jiawei@iscas.ac.cn>","list_archive_url":null,"date":"2023-03-20T03:34:44","name":"[v2] RISC-V: Fix disassemble fetch fail return value.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230320033444.2819-1-jiawei@iscas.ac.cn/mbox/"},{"id":72083,"url":"https://patchwork.plctlab.org/api/1.2/patches/72083/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZBg2d0PwGiSJ3tft@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-20T10:33:27","name":"libctf: unused variable","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZBg2d0PwGiSJ3tft@squeak.grove.modra.org/mbox/"},{"id":72295,"url":"https://patchwork.plctlab.org/api/1.2/patches/72295/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230320170313.354203-1-hjl.tools@gmail.com/","msgid":"<20230320170313.354203-1-hjl.tools@gmail.com>","list_archive_url":null,"date":"2023-03-20T17:03:13","name":"x86: Check unbalanced braces in memory reference","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230320170313.354203-1-hjl.tools@gmail.com/mbox/"},{"id":72904,"url":"https://patchwork.plctlab.org/api/1.2/patches/72904/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230321142839.672428-1-szabolcs.nagy@arm.com/","msgid":"<20230321142839.672428-1-szabolcs.nagy@arm.com>","list_archive_url":null,"date":"2023-03-21T14:28:39","name":"[1/3] bfd: aarch64: Refactor stub sizing code","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230321142839.672428-1-szabolcs.nagy@arm.com/mbox/"},{"id":72903,"url":"https://patchwork.plctlab.org/api/1.2/patches/72903/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230321142848.672474-1-szabolcs.nagy@arm.com/","msgid":"<20230321142848.672474-1-szabolcs.nagy@arm.com>","list_archive_url":null,"date":"2023-03-21T14:28:48","name":"[2/3] bfd: aarch64: Fix stubs that may break BTI PR30076","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230321142848.672474-1-szabolcs.nagy@arm.com/mbox/"},{"id":72905,"url":"https://patchwork.plctlab.org/api/1.2/patches/72905/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230321142857.672520-1-szabolcs.nagy@arm.com/","msgid":"<20230321142857.672520-1-szabolcs.nagy@arm.com>","list_archive_url":null,"date":"2023-03-21T14:28:57","name":"[3/3] bfd: aarch64: Optimize BTI stubs PR30076","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230321142857.672520-1-szabolcs.nagy@arm.com/mbox/"},{"id":73096,"url":"https://patchwork.plctlab.org/api/1.2/patches/73096/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZBoyS2GDkUCU6oU6@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-21T22:40:11","name":"gas: expand_irp memory leaks","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZBoyS2GDkUCU6oU6@squeak.grove.modra.org/mbox/"},{"id":73098,"url":"https://patchwork.plctlab.org/api/1.2/patches/73098/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZBoyeGHPA+1YemsH@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-21T22:40:56","name":"XCOFF: use bfd_coff_close_and_cleanup","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZBoyeGHPA+1YemsH@squeak.grove.modra.org/mbox/"},{"id":73100,"url":"https://patchwork.plctlab.org/api/1.2/patches/73100/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZBoyosqQBtXm4rI0@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-21T22:41:38","name":"PE fake section for C_SECTION syms","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZBoyosqQBtXm4rI0@squeak.grove.modra.org/mbox/"},{"id":73101,"url":"https://patchwork.plctlab.org/api/1.2/patches/73101/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZBoz7Wa4EHV+q9Gd@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-21T22:47:09","name":"PR17910 sym string offset check","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZBoz7Wa4EHV+q9Gd@squeak.grove.modra.org/mbox/"},{"id":73102,"url":"https://patchwork.plctlab.org/api/1.2/patches/73102/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZBo0ISexQkdavEpk@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-21T22:48:01","name":"Sanity check coff-sh and coff-mcore sym string offset","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZBo0ISexQkdavEpk@squeak.grove.modra.org/mbox/"},{"id":73105,"url":"https://patchwork.plctlab.org/api/1.2/patches/73105/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZBo5fIjQft2+fwJW@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-21T23:10:52","name":"Remove unnecessary memsets in sframe-dump.c","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZBo5fIjQft2+fwJW@squeak.grove.modra.org/mbox/"},{"id":73115,"url":"https://patchwork.plctlab.org/api/1.2/patches/73115/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZBpIM3lRdkoNAN+5@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-22T00:13:39","name":"coff_get_normalized_symtab bfd_release","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZBpIM3lRdkoNAN+5@squeak.grove.modra.org/mbox/"},{"id":73996,"url":"https://patchwork.plctlab.org/api/1.2/patches/73996/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230323105959.1449936-1-yunqiang.su@cipunited.com/","msgid":"<20230323105959.1449936-1-yunqiang.su@cipunited.com>","list_archive_url":null,"date":"2023-03-23T10:59:59","name":"MIPS: fix loongson3 llsc workaround","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230323105959.1449936-1-yunqiang.su@cipunited.com/mbox/"},{"id":74094,"url":"https://patchwork.plctlab.org/api/1.2/patches/74094/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/dc0f734f-9fba-7a7b-a746-49b4fc033dac@suse.com/","msgid":"","list_archive_url":null,"date":"2023-03-23T14:30:15","name":"Arm64/ELF: accept relocations against STN_UNDEF","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/dc0f734f-9fba-7a7b-a746-49b4fc033dac@suse.com/mbox/"},{"id":74480,"url":"https://patchwork.plctlab.org/api/1.2/patches/74480/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZB18Z0o3MG+6xpxp@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-24T10:33:11","name":"Tidy dwarf1 cached section contents","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZB18Z0o3MG+6xpxp@squeak.grove.modra.org/mbox/"},{"id":74481,"url":"https://patchwork.plctlab.org/api/1.2/patches/74481/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZB187ZhUAam/KJLp@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-24T10:35:25","name":"Tidy string_ptr increment","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZB187ZhUAam/KJLp@squeak.grove.modra.org/mbox/"},{"id":74544,"url":"https://patchwork.plctlab.org/api/1.2/patches/74544/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230324133625.450723-1-nick.alcock@oracle.com/","msgid":"<20230324133625.450723-1-nick.alcock@oracle.com>","list_archive_url":null,"date":"2023-03-24T13:36:22","name":"[1/4] libctf: fix assertion failure with no system qsort_r","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230324133625.450723-1-nick.alcock@oracle.com/mbox/"},{"id":74545,"url":"https://patchwork.plctlab.org/api/1.2/patches/74545/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230324133625.450723-2-nick.alcock@oracle.com/","msgid":"<20230324133625.450723-2-nick.alcock@oracle.com>","list_archive_url":null,"date":"2023-03-24T13:36:23","name":"[2/4] libctf: work around an uninitialized variable warning","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230324133625.450723-2-nick.alcock@oracle.com/mbox/"},{"id":74547,"url":"https://patchwork.plctlab.org/api/1.2/patches/74547/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230324133625.450723-3-nick.alcock@oracle.com/","msgid":"<20230324133625.450723-3-nick.alcock@oracle.com>","list_archive_url":null,"date":"2023-03-24T13:36:24","name":"[3/4] libctf: fix a comment typo","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230324133625.450723-3-nick.alcock@oracle.com/mbox/"},{"id":74546,"url":"https://patchwork.plctlab.org/api/1.2/patches/74546/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230324133625.450723-4-nick.alcock@oracle.com/","msgid":"<20230324133625.450723-4-nick.alcock@oracle.com>","list_archive_url":null,"date":"2023-03-24T13:36:25","name":"[4/4] libctf: get the offsets of fields of unnamed structs/unions right","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230324133625.450723-4-nick.alcock@oracle.com/mbox/"},{"id":74560,"url":"https://patchwork.plctlab.org/api/1.2/patches/74560/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ba77df02-5583-fb1d-5e1c-812106c2749f@redhat.com/","msgid":"","list_archive_url":null,"date":"2023-03-24T14:02:55","name":"[Bug,gold/30187] ld.bfd and ld.gold versions in .comment section of ELF files","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ba77df02-5583-fb1d-5e1c-812106c2749f@redhat.com/mbox/"},{"id":74795,"url":"https://patchwork.plctlab.org/api/1.2/patches/74795/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230325004113.22673-1-nelson@rivosinc.com/","msgid":"<20230325004113.22673-1-nelson@rivosinc.com>","list_archive_url":null,"date":"2023-03-25T00:41:11","name":"[1/3] RISC-V: Extract the ld code which are too complicated, and may be reused.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230325004113.22673-1-nelson@rivosinc.com/mbox/"},{"id":74798,"url":"https://patchwork.plctlab.org/api/1.2/patches/74798/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230325004113.22673-2-nelson@rivosinc.com/","msgid":"<20230325004113.22673-2-nelson@rivosinc.com>","list_archive_url":null,"date":"2023-03-25T00:41:12","name":"[2/3] RISC-V: Clarify link behaviors of R_RISCV_32/64 relocations with ABS symbol.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230325004113.22673-2-nelson@rivosinc.com/mbox/"},{"id":74796,"url":"https://patchwork.plctlab.org/api/1.2/patches/74796/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230325004113.22673-3-nelson@rivosinc.com/","msgid":"<20230325004113.22673-3-nelson@rivosinc.com>","list_archive_url":null,"date":"2023-03-25T00:41:13","name":"[3/3] RISC-V: PR28789, Reject R_RISCV_PCREL relocations with ABS symbol in PIC/PIE.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230325004113.22673-3-nelson@rivosinc.com/mbox/"},{"id":75166,"url":"https://patchwork.plctlab.org/api/1.2/patches/75166/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230326231111.3207581-1-vladimir.mezentsev@oracle.com/","msgid":"<20230326231111.3207581-1-vladimir.mezentsev@oracle.com>","list_archive_url":null,"date":"2023-03-26T23:11:11","name":"[Review,is,neded] gprofng: 30089 [display text] Invalid number of threads","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230326231111.3207581-1-vladimir.mezentsev@oracle.com/mbox/"},{"id":75242,"url":"https://patchwork.plctlab.org/api/1.2/patches/75242/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230327080107.3266866-2-christoph.muellner@vrull.eu/","msgid":"<20230327080107.3266866-2-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2023-03-27T08:01:06","name":"[RFC,v2,1/2] RISC-V: Allocate \"various\" operand type","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230327080107.3266866-2-christoph.muellner@vrull.eu/mbox/"},{"id":75245,"url":"https://patchwork.plctlab.org/api/1.2/patches/75245/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230327080107.3266866-3-christoph.muellner@vrull.eu/","msgid":"<20230327080107.3266866-3-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2023-03-27T08:01:07","name":"[RFC,v2,2/2] RISC-V: Add support for the Zfa extension","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230327080107.3266866-3-christoph.muellner@vrull.eu/mbox/"},{"id":75347,"url":"https://patchwork.plctlab.org/api/1.2/patches/75347/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZCF80Rw5CxmJnTxO@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-27T11:24:01","name":"XCOFF sanity check","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZCF80Rw5CxmJnTxO@squeak.grove.modra.org/mbox/"},{"id":75348,"url":"https://patchwork.plctlab.org/api/1.2/patches/75348/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZCF9NGTTWGGN5wkG@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-27T11:25:40","name":"Duplicate DW_AT_call_file leak","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZCF9NGTTWGGN5wkG@squeak.grove.modra.org/mbox/"},{"id":75350,"url":"https://patchwork.plctlab.org/api/1.2/patches/75350/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZCF9rPmAN9m9hcUD@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-27T11:27:40","name":"coffgrok access of u.auxent.x_sym.x_tagndx.p","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZCF9rPmAN9m9hcUD@squeak.grove.modra.org/mbox/"},{"id":75351,"url":"https://patchwork.plctlab.org/api/1.2/patches/75351/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZCF90abJaTld4Nn0@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-27T11:28:17","name":"Set proper union selector tag","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZCF90abJaTld4Nn0@squeak.grove.modra.org/mbox/"},{"id":75353,"url":"https://patchwork.plctlab.org/api/1.2/patches/75353/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZCF+rw8MIhhkeETH@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-27T11:31:59","name":"Use stdint types in coff internal_auxent","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZCF+rw8MIhhkeETH@squeak.grove.modra.org/mbox/"},{"id":75354,"url":"https://patchwork.plctlab.org/api/1.2/patches/75354/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZCF+2jvDqqXV1fVf@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-27T11:32:42","name":"Remove coff_pointerize_aux table_end param","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZCF+2jvDqqXV1fVf@squeak.grove.modra.org/mbox/"},{"id":75355,"url":"https://patchwork.plctlab.org/api/1.2/patches/75355/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZCF/CDC7SaaO4WhF@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-27T11:33:28","name":"Tidy tc-ppc.c XCOFF auxent access","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZCF/CDC7SaaO4WhF@squeak.grove.modra.org/mbox/"},{"id":75768,"url":"https://patchwork.plctlab.org/api/1.2/patches/75768/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZCJMUDd146mhNogB@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-28T02:09:20","name":"ubsan: elfnn-aarch64.c:4595:19: runtime error: load of value 190","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZCJMUDd146mhNogB@squeak.grove.modra.org/mbox/"},{"id":75974,"url":"https://patchwork.plctlab.org/api/1.2/patches/75974/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZCLDZsdo518WMpRM@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-28T10:37:26","name":"Avoid undefined behaviour in m68hc11 md_begin","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZCLDZsdo518WMpRM@squeak.grove.modra.org/mbox/"},{"id":76299,"url":"https://patchwork.plctlab.org/api/1.2/patches/76299/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230328230249.274759-2-david@davidgf.es/","msgid":"<20230328230249.274759-2-david@davidgf.es>","list_archive_url":null,"date":"2023-03-28T23:02:47","name":"[1/3] Add Allegrex CPU as a MIPS2-based CPU","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230328230249.274759-2-david@davidgf.es/mbox/"},{"id":76298,"url":"https://patchwork.plctlab.org/api/1.2/patches/76298/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230328230249.274759-3-david@davidgf.es/","msgid":"<20230328230249.274759-3-david@davidgf.es>","list_archive_url":null,"date":"2023-03-28T23:02:48","name":"[2/3] Add rotation instructions to allegrex CPU","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230328230249.274759-3-david@davidgf.es/mbox/"},{"id":76300,"url":"https://patchwork.plctlab.org/api/1.2/patches/76300/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230328230249.274759-4-david@davidgf.es/","msgid":"<20230328230249.274759-4-david@davidgf.es>","list_archive_url":null,"date":"2023-03-28T23:02:49","name":"[3/3] Adding more instructions to Allegrex CPU","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230328230249.274759-4-david@davidgf.es/mbox/"},{"id":76303,"url":"https://patchwork.plctlab.org/api/1.2/patches/76303/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZCN2J6V/OvvDMa3L@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-28T23:20:07","name":"ld testsuite CFLAGS_FOR_TARGET","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZCN2J6V/OvvDMa3L@squeak.grove.modra.org/mbox/"},{"id":76347,"url":"https://patchwork.plctlab.org/api/1.2/patches/76347/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZCOnk+1MgYLzyM65@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-29T02:50:59","name":"Sanity check section size in bfd_init_section_compress_status","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZCOnk+1MgYLzyM65@squeak.grove.modra.org/mbox/"},{"id":76561,"url":"https://patchwork.plctlab.org/api/1.2/patches/76561/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2a19f48f-2230-70c2-a6eb-de224028e8ae@embedded-brains.de/","msgid":"<2a19f48f-2230-70c2-a6eb-de224028e8ae@embedded-brains.de>","list_archive_url":null,"date":"2023-03-29T12:44:50","name":"RFC: Add ELF note for description with JSON data","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2a19f48f-2230-70c2-a6eb-de224028e8ae@embedded-brains.de/mbox/"},{"id":76636,"url":"https://patchwork.plctlab.org/api/1.2/patches/76636/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/87v8ijmxjh.fsf@redhat.com/","msgid":"<87v8ijmxjh.fsf@redhat.com>","list_archive_url":null,"date":"2023-03-29T14:39:46","name":"RFC: Can static executables contain relocations against symbols ?","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/87v8ijmxjh.fsf@redhat.com/mbox/"},{"id":76860,"url":"https://patchwork.plctlab.org/api/1.2/patches/76860/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/CAB=4xhrACo0JzK-VrnJfYoPxZOiwOYA48-OkShYOz26JPQ9YCA@mail.gmail.com/","msgid":"","list_archive_url":null,"date":"2023-03-30T00:08:03","name":"[COMMITTED] Fix typo in ld manual --enable-non-contiguous-regions example","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/CAB=4xhrACo0JzK-VrnJfYoPxZOiwOYA48-OkShYOz26JPQ9YCA@mail.gmail.com/mbox/"},{"id":76881,"url":"https://patchwork.plctlab.org/api/1.2/patches/76881/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZCUUuatLLu5VmpJx@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-30T04:48:57","name":"Tidy memory on addr2line failures","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZCUUuatLLu5VmpJx@squeak.grove.modra.org/mbox/"},{"id":76882,"url":"https://patchwork.plctlab.org/api/1.2/patches/76882/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZCUU2U5h4L4pOyCY@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-30T04:49:29","name":"Tidy leaked objcopy memory","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZCUU2U5h4L4pOyCY@squeak.grove.modra.org/mbox/"},{"id":76887,"url":"https://patchwork.plctlab.org/api/1.2/patches/76887/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZCUVAjKL5j0X5DTH@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-30T04:50:10","name":"Fix memory leak in bfd_get_debug_link_info_1","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZCUVAjKL5j0X5DTH@squeak.grove.modra.org/mbox/"},{"id":77007,"url":"https://patchwork.plctlab.org/api/1.2/patches/77007/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330101245.3327499-1-richard.sandiford@arm.com/","msgid":"<20230330101245.3327499-1-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:12:45","name":"aarch64: Add sme-i16i64 and sme-f64f64 aliases","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330101245.3327499-1-richard.sandiford@arm.com/mbox/"},{"id":77019,"url":"https://patchwork.plctlab.org/api/1.2/patches/77019/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-2-richard.sandiford@arm.com/","msgid":"<20230330102359.3327695-2-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:23:17","name":"[01/43] aarch64: Fix PSEL opcode mask","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-2-richard.sandiford@arm.com/mbox/"},{"id":77024,"url":"https://patchwork.plctlab.org/api/1.2/patches/77024/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-3-richard.sandiford@arm.com/","msgid":"<20230330102359.3327695-3-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:23:18","name":"[02/43] aarch64: Restrict range of PRFM opcodes","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-3-richard.sandiford@arm.com/mbox/"},{"id":77016,"url":"https://patchwork.plctlab.org/api/1.2/patches/77016/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-4-richard.sandiford@arm.com/","msgid":"<20230330102359.3327695-4-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:23:19","name":"[03/43] aarch64: Fix SVE2 register/immediate distinction","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-4-richard.sandiford@arm.com/mbox/"},{"id":77017,"url":"https://patchwork.plctlab.org/api/1.2/patches/77017/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-5-richard.sandiford@arm.com/","msgid":"<20230330102359.3327695-5-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:23:20","name":"[04/43] aarch64: Make SME instructions use F_STRICT","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-5-richard.sandiford@arm.com/mbox/"},{"id":77031,"url":"https://patchwork.plctlab.org/api/1.2/patches/77031/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-6-richard.sandiford@arm.com/","msgid":"<20230330102359.3327695-6-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:23:21","name":"[05/43] aarch64: Use aarch64_operand_error more widely","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-6-richard.sandiford@arm.com/mbox/"},{"id":77021,"url":"https://patchwork.plctlab.org/api/1.2/patches/77021/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-7-richard.sandiford@arm.com/","msgid":"<20230330102359.3327695-7-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:23:22","name":"[06/43] aarch64: Rename REG_TYPE_ZA* to REG_TYPE_ZAT*","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-7-richard.sandiford@arm.com/mbox/"},{"id":77018,"url":"https://patchwork.plctlab.org/api/1.2/patches/77018/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-8-richard.sandiford@arm.com/","msgid":"<20230330102359.3327695-8-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:23:23","name":"[07/43] aarch64: Add REG_TYPE_ZATHV","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-8-richard.sandiford@arm.com/mbox/"},{"id":77020,"url":"https://patchwork.plctlab.org/api/1.2/patches/77020/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-9-richard.sandiford@arm.com/","msgid":"<20230330102359.3327695-9-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:23:24","name":"[08/43] aarch64: Move vectype_to_qualifier further up","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-9-richard.sandiford@arm.com/mbox/"},{"id":77022,"url":"https://patchwork.plctlab.org/api/1.2/patches/77022/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-10-richard.sandiford@arm.com/","msgid":"<20230330102359.3327695-10-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:23:25","name":"[09/43] aarch64: Rework parse_typed_reg interface","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-10-richard.sandiford@arm.com/mbox/"},{"id":77027,"url":"https://patchwork.plctlab.org/api/1.2/patches/77027/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-11-richard.sandiford@arm.com/","msgid":"<20230330102359.3327695-11-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:23:26","name":"[10/43] aarch64: Reuse parse_typed_reg for ZA tiles","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-11-richard.sandiford@arm.com/mbox/"},{"id":77037,"url":"https://patchwork.plctlab.org/api/1.2/patches/77037/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-12-richard.sandiford@arm.com/","msgid":"<20230330102359.3327695-12-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:23:27","name":"[11/43] aarch64: Consolidate ZA tile range checks","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-12-richard.sandiford@arm.com/mbox/"},{"id":77034,"url":"https://patchwork.plctlab.org/api/1.2/patches/77034/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-13-richard.sandiford@arm.com/","msgid":"<20230330102359.3327695-13-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:23:28","name":"[12/43] aarch64: Treat ZA as a register","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-13-richard.sandiford@arm.com/mbox/"},{"id":77029,"url":"https://patchwork.plctlab.org/api/1.2/patches/77029/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-14-richard.sandiford@arm.com/","msgid":"<20230330102359.3327695-14-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:23:29","name":"[13/43] aarch64: Rename za_tile_vector to za_index","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-14-richard.sandiford@arm.com/mbox/"},{"id":77043,"url":"https://patchwork.plctlab.org/api/1.2/patches/77043/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-15-richard.sandiford@arm.com/","msgid":"<20230330102359.3327695-15-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:23:30","name":"[14/43] aarch64: Make indexed_za use 64-bit immediates","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-15-richard.sandiford@arm.com/mbox/"},{"id":77041,"url":"https://patchwork.plctlab.org/api/1.2/patches/77041/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-16-richard.sandiford@arm.com/","msgid":"<20230330102359.3327695-16-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:23:31","name":"[15/43] aarch64: Pass aarch64_indexed_za to parsers","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-16-richard.sandiford@arm.com/mbox/"},{"id":77045,"url":"https://patchwork.plctlab.org/api/1.2/patches/77045/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-17-richard.sandiford@arm.com/","msgid":"<20230330102359.3327695-17-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:23:32","name":"[16/43] aarch64: Move ZA range checks to aarch64-opc.c","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-17-richard.sandiford@arm.com/mbox/"},{"id":77048,"url":"https://patchwork.plctlab.org/api/1.2/patches/77048/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-18-richard.sandiford@arm.com/","msgid":"<20230330102359.3327695-18-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:23:33","name":"[17/43] aarch64: Consolidate ZA slice parsing","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-18-richard.sandiford@arm.com/mbox/"},{"id":77046,"url":"https://patchwork.plctlab.org/api/1.2/patches/77046/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-19-richard.sandiford@arm.com/","msgid":"<20230330102359.3327695-19-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:23:34","name":"[18/43] aarch64: Commonise index parsing","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-19-richard.sandiford@arm.com/mbox/"},{"id":77053,"url":"https://patchwork.plctlab.org/api/1.2/patches/77053/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-20-richard.sandiford@arm.com/","msgid":"<20230330102359.3327695-20-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:23:35","name":"[19/43] aarch64: Move w12-w15 range check to libopcodes","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-20-richard.sandiford@arm.com/mbox/"},{"id":77032,"url":"https://patchwork.plctlab.org/api/1.2/patches/77032/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-21-richard.sandiford@arm.com/","msgid":"<20230330102359.3327695-21-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:23:36","name":"[20/43] aarch64: Tweak error for missing immediate offset","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-21-richard.sandiford@arm.com/mbox/"},{"id":77058,"url":"https://patchwork.plctlab.org/api/1.2/patches/77058/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-22-richard.sandiford@arm.com/","msgid":"<20230330102359.3327695-22-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:23:37","name":"[21/43] aarch64: Tweak errors for base & offset registers","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-22-richard.sandiford@arm.com/mbox/"},{"id":77056,"url":"https://patchwork.plctlab.org/api/1.2/patches/77056/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-23-richard.sandiford@arm.com/","msgid":"<20230330102359.3327695-23-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:23:38","name":"[22/43] aarch64: Tweak parsing of integer & FP registers","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-23-richard.sandiford@arm.com/mbox/"},{"id":77052,"url":"https://patchwork.plctlab.org/api/1.2/patches/77052/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-24-richard.sandiford@arm.com/","msgid":"<20230330102359.3327695-24-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:23:39","name":"[23/43] aarch64: Improve errors for malformed register lists","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-24-richard.sandiford@arm.com/mbox/"},{"id":77064,"url":"https://patchwork.plctlab.org/api/1.2/patches/77064/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-25-richard.sandiford@arm.com/","msgid":"<20230330102359.3327695-25-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:23:40","name":"[24/43] aarch64: Try to avoid inappropriate default errors","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-25-richard.sandiford@arm.com/mbox/"},{"id":77070,"url":"https://patchwork.plctlab.org/api/1.2/patches/77070/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-26-richard.sandiford@arm.com/","msgid":"<20230330102359.3327695-26-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:23:41","name":"[25/43] aarch64: Rework reporting of failed register checks","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-26-richard.sandiford@arm.com/mbox/"},{"id":77050,"url":"https://patchwork.plctlab.org/api/1.2/patches/77050/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-27-richard.sandiford@arm.com/","msgid":"<20230330102359.3327695-27-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:23:42","name":"[26/43] aarch64: Update operand_mismatch_kind_names","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-27-richard.sandiford@arm.com/mbox/"},{"id":77054,"url":"https://patchwork.plctlab.org/api/1.2/patches/77054/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-28-richard.sandiford@arm.com/","msgid":"<20230330102359.3327695-28-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:23:43","name":"[27/43] aarch64: Deprioritise AARCH64_OPDE_REG_LIST","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-28-richard.sandiford@arm.com/mbox/"},{"id":77042,"url":"https://patchwork.plctlab.org/api/1.2/patches/77042/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-29-richard.sandiford@arm.com/","msgid":"<20230330102359.3327695-29-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:23:44","name":"[28/43] aarch64: Add an error code for out-of-range registers","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-29-richard.sandiford@arm.com/mbox/"},{"id":77060,"url":"https://patchwork.plctlab.org/api/1.2/patches/77060/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-30-richard.sandiford@arm.com/","msgid":"<20230330102359.3327695-30-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:23:45","name":"[29/43] aarch64: Commonise checks for index operands","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-30-richard.sandiford@arm.com/mbox/"},{"id":77066,"url":"https://patchwork.plctlab.org/api/1.2/patches/77066/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-31-richard.sandiford@arm.com/","msgid":"<20230330102359.3327695-31-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:23:46","name":"[30/43] aarch64: Add an operand class for SVE register lists","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-31-richard.sandiford@arm.com/mbox/"},{"id":77067,"url":"https://patchwork.plctlab.org/api/1.2/patches/77067/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-32-richard.sandiford@arm.com/","msgid":"<20230330102359.3327695-32-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:23:47","name":"[31/43] aarch64: Make AARCH64_OPDE_REG_LIST take a bitfield","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-32-richard.sandiford@arm.com/mbox/"},{"id":77047,"url":"https://patchwork.plctlab.org/api/1.2/patches/77047/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-33-richard.sandiford@arm.com/","msgid":"<20230330102359.3327695-33-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:23:48","name":"[32/43] aarch64: Tweak register list errors","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-33-richard.sandiford@arm.com/mbox/"},{"id":77072,"url":"https://patchwork.plctlab.org/api/1.2/patches/77072/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-34-richard.sandiford@arm.com/","msgid":"<20230330102359.3327695-34-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:23:49","name":"[33/43] aarch64: Try to report invalid variants against the closest match","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-34-richard.sandiford@arm.com/mbox/"},{"id":77051,"url":"https://patchwork.plctlab.org/api/1.2/patches/77051/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-35-richard.sandiford@arm.com/","msgid":"<20230330102359.3327695-35-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:23:50","name":"[34/43] aarch64: Tweak priorities of parsing-related errors","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-35-richard.sandiford@arm.com/mbox/"},{"id":77079,"url":"https://patchwork.plctlab.org/api/1.2/patches/77079/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-36-richard.sandiford@arm.com/","msgid":"<20230330102359.3327695-36-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:23:51","name":"[35/43] aarch64: Rename aarch64-tbl.h OP_SME_* macros","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-36-richard.sandiford@arm.com/mbox/"},{"id":77055,"url":"https://patchwork.plctlab.org/api/1.2/patches/77055/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-37-richard.sandiford@arm.com/","msgid":"<20230330102359.3327695-37-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:23:52","name":"[36/43] aarch64: Reorder some OP_SVE_* macros","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-37-richard.sandiford@arm.com/mbox/"},{"id":77082,"url":"https://patchwork.plctlab.org/api/1.2/patches/77082/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-38-richard.sandiford@arm.com/","msgid":"<20230330102359.3327695-38-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:23:53","name":"[37/43] aarch64: Add a aarch64_cpu_supports_inst_p helper","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-38-richard.sandiford@arm.com/mbox/"},{"id":77068,"url":"https://patchwork.plctlab.org/api/1.2/patches/77068/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-39-richard.sandiford@arm.com/","msgid":"<20230330102359.3327695-39-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:23:54","name":"[38/43] aarch64: Rename some of GAS'\''s REG_TYPE_* macros","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-39-richard.sandiford@arm.com/mbox/"},{"id":77073,"url":"https://patchwork.plctlab.org/api/1.2/patches/77073/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-40-richard.sandiford@arm.com/","msgid":"<20230330102359.3327695-40-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:23:55","name":"[39/43] aarch64: Regularise FLD_* suffixes","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-40-richard.sandiford@arm.com/mbox/"},{"id":77084,"url":"https://patchwork.plctlab.org/api/1.2/patches/77084/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-41-richard.sandiford@arm.com/","msgid":"<20230330102359.3327695-41-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:23:56","name":"[40/43] aarch64: Resync field names","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-41-richard.sandiford@arm.com/mbox/"},{"id":77077,"url":"https://patchwork.plctlab.org/api/1.2/patches/77077/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-42-richard.sandiford@arm.com/","msgid":"<20230330102359.3327695-42-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:23:57","name":"[41/43] aarch64: Sort fields alphanumerically","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-42-richard.sandiford@arm.com/mbox/"},{"id":77063,"url":"https://patchwork.plctlab.org/api/1.2/patches/77063/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-43-richard.sandiford@arm.com/","msgid":"<20230330102359.3327695-43-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:23:58","name":"[42/43] aarch64: Add support for strided register lists","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-43-richard.sandiford@arm.com/mbox/"},{"id":77078,"url":"https://patchwork.plctlab.org/api/1.2/patches/77078/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-44-richard.sandiford@arm.com/","msgid":"<20230330102359.3327695-44-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:23:59","name":"[43/43] aarch64: Prefer register ranges & support wrapping","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-44-richard.sandiford@arm.com/mbox/"},{"id":77086,"url":"https://patchwork.plctlab.org/api/1.2/patches/77086/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102646.3327818-2-richard.sandiford@arm.com/","msgid":"<20230330102646.3327818-2-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:26:16","name":"[01/31] aarch64: Add +sme2","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102646.3327818-2-richard.sandiford@arm.com/mbox/"},{"id":77090,"url":"https://patchwork.plctlab.org/api/1.2/patches/77090/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102646.3327818-3-richard.sandiford@arm.com/","msgid":"<20230330102646.3327818-3-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:26:17","name":"[02/31] aarch64: Add a _10 suffix to FLD_imm3","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102646.3327818-3-richard.sandiford@arm.com/mbox/"},{"id":77076,"url":"https://patchwork.plctlab.org/api/1.2/patches/77076/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102646.3327818-4-richard.sandiford@arm.com/","msgid":"<20230330102646.3327818-4-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:26:18","name":"[03/31] aarch64: Add _off4 suffix to AARCH64_OPND_SME_ZA_array","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102646.3327818-4-richard.sandiford@arm.com/mbox/"},{"id":77083,"url":"https://patchwork.plctlab.org/api/1.2/patches/77083/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102646.3327818-5-richard.sandiford@arm.com/","msgid":"<20230330102646.3327818-5-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:26:19","name":"[04/31] aarch64: Add support for vgx2 and vgx4","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102646.3327818-5-richard.sandiford@arm.com/mbox/"},{"id":77081,"url":"https://patchwork.plctlab.org/api/1.2/patches/77081/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102646.3327818-6-richard.sandiford@arm.com/","msgid":"<20230330102646.3327818-6-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:26:20","name":"[05/31] aarch64; Add support for vector offset ranges","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102646.3327818-6-richard.sandiford@arm.com/mbox/"},{"id":77085,"url":"https://patchwork.plctlab.org/api/1.2/patches/77085/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102646.3327818-8-richard.sandiford@arm.com/","msgid":"<20230330102646.3327818-8-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:26:22","name":"[07/31] aarch64: Add the SME2 MOVA instructions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102646.3327818-8-richard.sandiford@arm.com/mbox/"},{"id":77071,"url":"https://patchwork.plctlab.org/api/1.2/patches/77071/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102646.3327818-11-richard.sandiford@arm.com/","msgid":"<20230330102646.3327818-11-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:26:25","name":"[10/31] aarch64: Add the SME2 ZT0 instructions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102646.3327818-11-richard.sandiford@arm.com/mbox/"},{"id":77080,"url":"https://patchwork.plctlab.org/api/1.2/patches/77080/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102646.3327818-12-richard.sandiford@arm.com/","msgid":"<20230330102646.3327818-12-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:26:26","name":"[11/31] aarch64: Add the SME2 ADD and SUB instructions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102646.3327818-12-richard.sandiford@arm.com/mbox/"},{"id":77087,"url":"https://patchwork.plctlab.org/api/1.2/patches/77087/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102646.3327818-14-richard.sandiford@arm.com/","msgid":"<20230330102646.3327818-14-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:26:28","name":"[13/31] aarch64: Add the SME2 FMLA and FMLS instructions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102646.3327818-14-richard.sandiford@arm.com/mbox/"},{"id":77093,"url":"https://patchwork.plctlab.org/api/1.2/patches/77093/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102646.3327818-23-richard.sandiford@arm.com/","msgid":"<20230330102646.3327818-23-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:26:37","name":"[22/31] aarch64: Add the SME2 saturating conversion instructions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102646.3327818-23-richard.sandiford@arm.com/mbox/"},{"id":77091,"url":"https://patchwork.plctlab.org/api/1.2/patches/77091/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102646.3327818-24-richard.sandiford@arm.com/","msgid":"<20230330102646.3327818-24-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:26:38","name":"[23/31] aarch64: Add the SME2 shift instructions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102646.3327818-24-richard.sandiford@arm.com/mbox/"},{"id":77095,"url":"https://patchwork.plctlab.org/api/1.2/patches/77095/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102646.3327818-25-richard.sandiford@arm.com/","msgid":"<20230330102646.3327818-25-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:26:39","name":"[24/31] aarch64: Add the SME2 UNPK instructions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102646.3327818-25-richard.sandiford@arm.com/mbox/"},{"id":77092,"url":"https://patchwork.plctlab.org/api/1.2/patches/77092/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102646.3327818-26-richard.sandiford@arm.com/","msgid":"<20230330102646.3327818-26-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:26:40","name":"[25/31] aarch64: Add the SME2 UZP and ZIP instructions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102646.3327818-26-richard.sandiford@arm.com/mbox/"},{"id":77097,"url":"https://patchwork.plctlab.org/api/1.2/patches/77097/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330103528.3497996-2-christoph.muellner@vrull.eu/","msgid":"<20230330103528.3497996-2-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2023-03-30T10:35:27","name":"[RFC,v3,1/2] RISC-V: Allocate \"various\" operand type","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330103528.3497996-2-christoph.muellner@vrull.eu/mbox/"},{"id":77098,"url":"https://patchwork.plctlab.org/api/1.2/patches/77098/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330103528.3497996-3-christoph.muellner@vrull.eu/","msgid":"<20230330103528.3497996-3-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2023-03-30T10:35:28","name":"[RFC,v3,2/2] RISC-V: Add support for the Zfa extension","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330103528.3497996-3-christoph.muellner@vrull.eu/mbox/"},{"id":77244,"url":"https://patchwork.plctlab.org/api/1.2/patches/77244/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/mptsfdmut0x.fsf@arm.com/","msgid":"","list_archive_url":null,"date":"2023-03-30T16:02:22","name":"aarch64: Remove stray reglist variable","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/mptsfdmut0x.fsf@arm.com/mbox/"},{"id":77311,"url":"https://patchwork.plctlab.org/api/1.2/patches/77311/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330164214.735462-1-hjl.tools@gmail.com/","msgid":"<20230330164214.735462-1-hjl.tools@gmail.com>","list_archive_url":null,"date":"2023-03-30T16:42:14","name":"lto: Don'\''t add indirect symbols for versioned aliases in IR","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330164214.735462-1-hjl.tools@gmail.com/mbox/"},{"id":77350,"url":"https://patchwork.plctlab.org/api/1.2/patches/77350/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330175438.107102-2-christoph.muellner@vrull.eu/","msgid":"<20230330175438.107102-2-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2023-03-30T17:54:37","name":"[RFC,v4,1/2] RISC-V: Allocate \"various\" operand type","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330175438.107102-2-christoph.muellner@vrull.eu/mbox/"},{"id":77351,"url":"https://patchwork.plctlab.org/api/1.2/patches/77351/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330175438.107102-3-christoph.muellner@vrull.eu/","msgid":"<20230330175438.107102-3-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2023-03-30T17:54:38","name":"[RFC,v4,2/2] RISC-V: Add support for the Zfa extension","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330175438.107102-3-christoph.muellner@vrull.eu/mbox/"},{"id":77708,"url":"https://patchwork.plctlab.org/api/1.2/patches/77708/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/bcc26bf7-bb9f-6ffc-51e8-05b8ff9e05e1@suse.com/","msgid":"","list_archive_url":null,"date":"2023-03-31T10:04:54","name":"[1/3] x86: parse_real_register() does not alter the parsed string","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/bcc26bf7-bb9f-6ffc-51e8-05b8ff9e05e1@suse.com/mbox/"},{"id":77709,"url":"https://patchwork.plctlab.org/api/1.2/patches/77709/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e0e3ab15-50da-a92a-bcec-e392f09a9c37@suse.com/","msgid":"","list_archive_url":null,"date":"2023-03-31T10:05:53","name":"[2/3] x86: parse_register() must not alter the parsed string","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e0e3ab15-50da-a92a-bcec-e392f09a9c37@suse.com/mbox/"},{"id":77710,"url":"https://patchwork.plctlab.org/api/1.2/patches/77710/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b9ae928e-7e33-e158-bc2e-5e832c2f6032@suse.com/","msgid":"","list_archive_url":null,"date":"2023-03-31T10:07:04","name":"[3/3] gas: document that get_symbol_name() can clobber the input buffer","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b9ae928e-7e33-e158-bc2e-5e832c2f6032@suse.com/mbox/"},{"id":77794,"url":"https://patchwork.plctlab.org/api/1.2/patches/77794/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/efb685d2-b2cb-9baf-0352-d0aa7961c300@suse.com/","msgid":"","list_archive_url":null,"date":"2023-03-31T14:19:21","name":"bfd+ld: when / whether to generate .c files","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/efb685d2-b2cb-9baf-0352-d0aa7961c300@suse.com/mbox/"}],"public":true,"mbox":"https://patchwork.plctlab.org/bundle/patchwork-bot/binutils-gdb_2023-03/mbox/"},{"id":20,"url":"https://patchwork.plctlab.org/api/1.2/bundles/20/","web_url":"https://patchwork.plctlab.org/bundle/patchwork-bot/binutils-gdb_2023-04/","project":{"id":2,"url":"https://patchwork.plctlab.org/api/1.2/projects/2/","name":"binutils-gdb","link_name":"binutils-gdb","list_id":"binutils.sourceware.org","list_email":"binutils@sourceware.org","web_url":"https://github.com/wangliu-iscas/Patchwork-Bundles/blob/main/binutils-gdb.md","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"name":"binutils-gdb_2023-04","owner":{"id":3,"url":"https://patchwork.plctlab.org/api/1.2/users/3/","username":"patchwork-bot","first_name":"","last_name":"","email":"ouuuleilei@gmail.com"},"patches":[{"id":78307,"url":"https://patchwork.plctlab.org/api/1.2/patches/78307/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZCoAJjprIo2dA8lE@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-04-02T22:22:30","name":"Memory leak in process_abbrev_set","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZCoAJjprIo2dA8lE@squeak.grove.modra.org/mbox/"},{"id":78308,"url":"https://patchwork.plctlab.org/api/1.2/patches/78308/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZCoAR84jVZy97VzK@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-04-02T22:23:03","name":"rddbg.c stabs FIXMEs","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZCoAR84jVZy97VzK@squeak.grove.modra.org/mbox/"},{"id":78309,"url":"https://patchwork.plctlab.org/api/1.2/patches/78309/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZCoAZZg7Py/LwyZl@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-04-02T22:23:33","name":"ubsan: aarch64 parse_vector_reg_list","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZCoAZZg7Py/LwyZl@squeak.grove.modra.org/mbox/"},{"id":78310,"url":"https://patchwork.plctlab.org/api/1.2/patches/78310/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZCoAizHXDaTVgiFm@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-04-02T22:24:11","name":"asan: heap buffer overflow printing ecoff debug info file name","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZCoAizHXDaTVgiFm@squeak.grove.modra.org/mbox/"},{"id":78375,"url":"https://patchwork.plctlab.org/api/1.2/patches/78375/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230403071118.2097883-1-haochen.jiang@intel.com/","msgid":"<20230403071118.2097883-1-haochen.jiang@intel.com>","list_archive_url":null,"date":"2023-04-03T07:11:18","name":"Support Intel AMX-COMPLEX","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230403071118.2097883-1-haochen.jiang@intel.com/mbox/"},{"id":78496,"url":"https://patchwork.plctlab.org/api/1.2/patches/78496/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230403110635.23391-1-yunqiang.su@cipunited.com/","msgid":"<20230403110635.23391-1-yunqiang.su@cipunited.com>","list_archive_url":null,"date":"2023-04-03T11:06:35","name":"[v2] MIPS: the default output fellows triple and with-arch","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230403110635.23391-1-yunqiang.su@cipunited.com/mbox/"},{"id":78553,"url":"https://patchwork.plctlab.org/api/1.2/patches/78553/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZCrYJNj8VL4ZsHBV@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-04-03T13:44:04","name":"asan: csky floatformat_to_double uninitialised value","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZCrYJNj8VL4ZsHBV@squeak.grove.modra.org/mbox/"},{"id":78838,"url":"https://patchwork.plctlab.org/api/1.2/patches/78838/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZCueM3aNMfvEirla@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-04-04T03:49:07","name":"Use bfd_alloc memory for read_debugging_info storage","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZCueM3aNMfvEirla@squeak.grove.modra.org/mbox/"},{"id":78868,"url":"https://patchwork.plctlab.org/api/1.2/patches/78868/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9b770800-dc80-2c00-40a2-903cbe4ffb8c@suse.com/","msgid":"<9b770800-dc80-2c00-40a2-903cbe4ffb8c@suse.com>","list_archive_url":null,"date":"2023-04-04T06:58:15","name":"[1/8] x86: move fetch error handling into a helper function","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9b770800-dc80-2c00-40a2-903cbe4ffb8c@suse.com/mbox/"},{"id":78869,"url":"https://patchwork.plctlab.org/api/1.2/patches/78869/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/39b50a10-ad10-aca0-2ef1-4d32be787762@suse.com/","msgid":"<39b50a10-ad10-aca0-2ef1-4d32be787762@suse.com>","list_archive_url":null,"date":"2023-04-04T06:58:37","name":"[2/8] x86: change fetch error handling in top-level function","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/39b50a10-ad10-aca0-2ef1-4d32be787762@suse.com/mbox/"},{"id":78870,"url":"https://patchwork.plctlab.org/api/1.2/patches/78870/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/838292bd-8855-00af-59c8-fcf0acb34d5c@suse.com/","msgid":"<838292bd-8855-00af-59c8-fcf0acb34d5c@suse.com>","list_archive_url":null,"date":"2023-04-04T06:59:17","name":"[3/8] x86: change fetch error handling in ckprefix()","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/838292bd-8855-00af-59c8-fcf0acb34d5c@suse.com/mbox/"},{"id":78871,"url":"https://patchwork.plctlab.org/api/1.2/patches/78871/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b4c84a3d-5266-2395-ba72-97e5ec540b3c@suse.com/","msgid":"","list_archive_url":null,"date":"2023-04-04T06:59:49","name":"[4/8] x86: change fetch error handling in get_valid_dis386()","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b4c84a3d-5266-2395-ba72-97e5ec540b3c@suse.com/mbox/"},{"id":78872,"url":"https://patchwork.plctlab.org/api/1.2/patches/78872/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3231104b-ffc0-e471-79be-f18e14c3264e@suse.com/","msgid":"<3231104b-ffc0-e471-79be-f18e14c3264e@suse.com>","list_archive_url":null,"date":"2023-04-04T07:00:24","name":"[5/8] x86: change fetch error handling when processing operands","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3231104b-ffc0-e471-79be-f18e14c3264e@suse.com/mbox/"},{"id":78873,"url":"https://patchwork.plctlab.org/api/1.2/patches/78873/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a9e13e17-ecf2-8e96-5b48-870801faa750@suse.com/","msgid":"","list_archive_url":null,"date":"2023-04-04T07:00:46","name":"[6/8] x86: change fetch error handling for get()","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a9e13e17-ecf2-8e96-5b48-870801faa750@suse.com/mbox/"},{"id":78874,"url":"https://patchwork.plctlab.org/api/1.2/patches/78874/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9375ae85-ac76-2081-547d-55803c97aadf@suse.com/","msgid":"<9375ae85-ac76-2081-547d-55803c97aadf@suse.com>","list_archive_url":null,"date":"2023-04-04T07:01:04","name":"[7/8] x86: drop use of setjmp() from disassembler","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9375ae85-ac76-2081-547d-55803c97aadf@suse.com/mbox/"},{"id":78875,"url":"https://patchwork.plctlab.org/api/1.2/patches/78875/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4eed4c72-002f-268e-b5cd-0929bc57d6d2@suse.com/","msgid":"<4eed4c72-002f-268e-b5cd-0929bc57d6d2@suse.com>","list_archive_url":null,"date":"2023-04-04T07:01:31","name":"[8/8] x86: drop (explicit) BFD64 dependency from disassembler","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4eed4c72-002f-268e-b5cd-0929bc57d6d2@suse.com/mbox/"},{"id":79194,"url":"https://patchwork.plctlab.org/api/1.2/patches/79194/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/OS3P286MB2152D2B8F88B6EB24B91BD8BF0939@OS3P286MB2152.JPNP286.PROD.OUTLOOK.COM/","msgid":"","list_archive_url":null,"date":"2023-04-04T15:07:13","name":"bfd: add version check to makeinfo","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/OS3P286MB2152D2B8F88B6EB24B91BD8BF0939@OS3P286MB2152.JPNP286.PROD.OUTLOOK.COM/mbox/"},{"id":79999,"url":"https://patchwork.plctlab.org/api/1.2/patches/79999/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZC4RKePLqGKgQ3pO@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-04-06T00:24:09","name":"objcopy write_debugging_info memory leaks","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZC4RKePLqGKgQ3pO@squeak.grove.modra.org/mbox/"},{"id":80000,"url":"https://patchwork.plctlab.org/api/1.2/patches/80000/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZC4RRVFBYw/0n5Le@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-04-06T00:24:37","name":"gas/write.c use better types","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZC4RRVFBYw/0n5Le@squeak.grove.modra.org/mbox/"},{"id":80002,"url":"https://patchwork.plctlab.org/api/1.2/patches/80002/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZC4RdBr7BVn64YcM@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-04-06T00:25:24","name":"objdump -g on gcc COFF/PE files","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZC4RdBr7BVn64YcM@squeak.grove.modra.org/mbox/"},{"id":80003,"url":"https://patchwork.plctlab.org/api/1.2/patches/80003/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZC4RjLt+tU2D/RxY@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-04-06T00:25:48","name":"objdump print_debugging_info memory leaks","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZC4RjLt+tU2D/RxY@squeak.grove.modra.org/mbox/"},{"id":80108,"url":"https://patchwork.plctlab.org/api/1.2/patches/80108/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230406071732.2092853-1-haochen.jiang@intel.com/","msgid":"<20230406071732.2092853-1-haochen.jiang@intel.com>","list_archive_url":null,"date":"2023-04-06T07:17:32","name":"[v2] Support Intel AMX-COMPLEX","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230406071732.2092853-1-haochen.jiang@intel.com/mbox/"},{"id":80642,"url":"https://patchwork.plctlab.org/api/1.2/patches/80642/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230407032809.3763561-1-haochen.jiang@intel.com/","msgid":"<20230407032809.3763561-1-haochen.jiang@intel.com>","list_archive_url":null,"date":"2023-04-07T03:28:09","name":"x86: Add inval tests for AMX instructions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230407032809.3763561-1-haochen.jiang@intel.com/mbox/"},{"id":80675,"url":"https://patchwork.plctlab.org/api/1.2/patches/80675/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230407073501.66953-1-lidie@eswincomputing.com/","msgid":"<20230407073501.66953-1-lidie@eswincomputing.com>","list_archive_url":null,"date":"2023-04-07T07:35:01","name":"Add unclosed macros.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230407073501.66953-1-lidie@eswincomputing.com/mbox/"},{"id":81057,"url":"https://patchwork.plctlab.org/api/1.2/patches/81057/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230407220426.63786-1-nick.alcock@oracle.com/","msgid":"<20230407220426.63786-1-nick.alcock@oracle.com>","list_archive_url":null,"date":"2023-04-07T22:04:24","name":"[1/3] libctf, tests: do not assume host and target have identical field offsets","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230407220426.63786-1-nick.alcock@oracle.com/mbox/"},{"id":81059,"url":"https://patchwork.plctlab.org/api/1.2/patches/81059/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230407220426.63786-2-nick.alcock@oracle.com/","msgid":"<20230407220426.63786-2-nick.alcock@oracle.com>","list_archive_url":null,"date":"2023-04-07T22:04:25","name":"[2/3] libctf: propagate errors from parents correctly","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230407220426.63786-2-nick.alcock@oracle.com/mbox/"},{"id":81058,"url":"https://patchwork.plctlab.org/api/1.2/patches/81058/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230407220426.63786-3-nick.alcock@oracle.com/","msgid":"<20230407220426.63786-3-nick.alcock@oracle.com>","list_archive_url":null,"date":"2023-04-07T22:04:26","name":"[3/3] libctf, link: fix CU-mapped links with CTF_LINK_EMPTY_CU_MAPPINGS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230407220426.63786-3-nick.alcock@oracle.com/mbox/"},{"id":81328,"url":"https://patchwork.plctlab.org/api/1.2/patches/81328/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/745eb337-facd-244a-bd02-d9b8b1f653a5@acm.org/","msgid":"<745eb337-facd-244a-bd02-d9b8b1f653a5@acm.org>","list_archive_url":null,"date":"2023-04-09T22:55:13","name":"bfd: optimize bfd_elf_hash","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/745eb337-facd-244a-bd02-d9b8b1f653a5@acm.org/mbox/"},{"id":81368,"url":"https://patchwork.plctlab.org/api/1.2/patches/81368/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230410065101.822124-1-yunqiang.su@cipunited.com/","msgid":"<20230410065101.822124-1-yunqiang.su@cipunited.com>","list_archive_url":null,"date":"2023-04-10T06:51:01","name":"[v3] MIPS: make mipsisa32 and mipsisa64 link more systematic","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230410065101.822124-1-yunqiang.su@cipunited.com/mbox/"},{"id":82223,"url":"https://patchwork.plctlab.org/api/1.2/patches/82223/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZDYKGcHwDnuaixXL@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-04-12T01:32:09","name":"Comment typo fix","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZDYKGcHwDnuaixXL@squeak.grove.modra.org/mbox/"},{"id":82224,"url":"https://patchwork.plctlab.org/api/1.2/patches/82224/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZDYKPKZ4fcn/AF6v@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-04-12T01:32:44","name":"pe_ILF_object_p and bfd_check_format_matches","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZDYKPKZ4fcn/AF6v@squeak.grove.modra.org/mbox/"},{"id":82225,"url":"https://patchwork.plctlab.org/api/1.2/patches/82225/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZDYKWh5RnEtHftFe@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-04-12T01:33:14","name":"Fail of x86_64 AMX-COMPLEX insns (Intel disassembly)","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZDYKWh5RnEtHftFe@squeak.grove.modra.org/mbox/"},{"id":82226,"url":"https://patchwork.plctlab.org/api/1.2/patches/82226/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZDYKkMb0QCBGC1/F@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-04-12T01:34:08","name":"ubsan: dwarf2.c:2232:7: runtime error: index 16 out of bounds","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZDYKkMb0QCBGC1/F@squeak.grove.modra.org/mbox/"},{"id":82246,"url":"https://patchwork.plctlab.org/api/1.2/patches/82246/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZDY9jn6M1PdoXqNi@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-04-12T05:11:42","name":"PR30326, uninitialised value in objdump compare_relocs","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZDY9jn6M1PdoXqNi@squeak.grove.modra.org/mbox/"},{"id":82545,"url":"https://patchwork.plctlab.org/api/1.2/patches/82545/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230412154444.1741657-1-claziss@gmail.com/","msgid":"<20230412154444.1741657-1-claziss@gmail.com>","list_archive_url":null,"date":"2023-04-12T15:44:44","name":"[committed] arc: remove faulty instructions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230412154444.1741657-1-claziss@gmail.com/mbox/"},{"id":82801,"url":"https://patchwork.plctlab.org/api/1.2/patches/82801/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZDeVznw01giUi/SE@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-04-13T05:40:30","name":"Preserve a few more bfd fields in check_format_matches","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZDeVznw01giUi/SE@squeak.grove.modra.org/mbox/"},{"id":82831,"url":"https://patchwork.plctlab.org/api/1.2/patches/82831/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230413070544.1961068-1-claziss@gmail.com/","msgid":"<20230413070544.1961068-1-claziss@gmail.com>","list_archive_url":null,"date":"2023-04-13T07:05:44","name":"[committed] arc: Update GAS test","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230413070544.1961068-1-claziss@gmail.com/mbox/"},{"id":82839,"url":"https://patchwork.plctlab.org/api/1.2/patches/82839/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230413073144.1973667-1-claziss@gmail.com/","msgid":"<20230413073144.1973667-1-claziss@gmail.com>","list_archive_url":null,"date":"2023-04-13T07:31:44","name":"[committed] arc: Update ARC'\''s CFI tests.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230413073144.1973667-1-claziss@gmail.com/mbox/"},{"id":82843,"url":"https://patchwork.plctlab.org/api/1.2/patches/82843/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230413074914.354662-1-chigot@adacore.com/","msgid":"<20230413074914.354662-1-chigot@adacore.com>","list_archive_url":null,"date":"2023-04-13T07:49:14","name":"ld: build libdep plugin only when shared library support is enabled","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230413074914.354662-1-chigot@adacore.com/mbox/"},{"id":82854,"url":"https://patchwork.plctlab.org/api/1.2/patches/82854/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230413082502.2009382-1-claziss@gmail.com/","msgid":"<20230413082502.2009382-1-claziss@gmail.com>","list_archive_url":null,"date":"2023-04-13T08:25:02","name":"[committed] arc: Update ARC specific linker tests.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230413082502.2009382-1-claziss@gmail.com/mbox/"},{"id":82982,"url":"https://patchwork.plctlab.org/api/1.2/patches/82982/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230413133654.71247-1-christoph.muellner@vrull.eu/","msgid":"<20230413133654.71247-1-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2023-04-13T13:36:54","name":"[RFC,v5] RISC-V: Add support for the Zfa extension","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230413133654.71247-1-christoph.muellner@vrull.eu/mbox/"},{"id":83244,"url":"https://patchwork.plctlab.org/api/1.2/patches/83244/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230414061935.1252692-1-mengqinggang@loongson.cn/","msgid":"<20230414061935.1252692-1-mengqinggang@loongson.cn>","list_archive_url":null,"date":"2023-04-14T06:19:35","name":"Symbols with GOT relocatios do not fix adjustbale","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230414061935.1252692-1-mengqinggang@loongson.cn/mbox/"},{"id":83259,"url":"https://patchwork.plctlab.org/api/1.2/patches/83259/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230414072046.1639896-1-yunqiang.su@cipunited.com/","msgid":"<20230414072046.1639896-1-yunqiang.su@cipunited.com>","list_archive_url":null,"date":"2023-04-14T07:20:46","name":"[v3] MIPS: the default output fellows triple","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230414072046.1639896-1-yunqiang.su@cipunited.com/mbox/"},{"id":83780,"url":"https://patchwork.plctlab.org/api/1.2/patches/83780/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230416005921.3061576-1-vladimir.mezentsev@oracle.com/","msgid":"<20230416005921.3061576-1-vladimir.mezentsev@oracle.com>","list_archive_url":null,"date":"2023-04-16T00:59:21","name":"[Review,is,neded] gprofng: Update documentation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230416005921.3061576-1-vladimir.mezentsev@oracle.com/mbox/"},{"id":83922,"url":"https://patchwork.plctlab.org/api/1.2/patches/83922/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/baf3b8d6-a257-7bc7-5dfa-2a8f578c2c93@netcologne.de/","msgid":"","list_archive_url":null,"date":"2023-04-16T19:47:11","name":"[gas,documentation] Describe handling of opcodes for relaxation a bit better","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/baf3b8d6-a257-7bc7-5dfa-2a8f578c2c93@netcologne.de/mbox/"},{"id":83932,"url":"https://patchwork.plctlab.org/api/1.2/patches/83932/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230416210122.3363899-1-vladimir.mezentsev@oracle.com/","msgid":"<20230416210122.3363899-1-vladimir.mezentsev@oracle.com>","list_archive_url":null,"date":"2023-04-16T21:01:22","name":"[Review,is,neded] gprofng: 30360 Seg. Fault when application uses std::thread","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230416210122.3363899-1-vladimir.mezentsev@oracle.com/mbox/"},{"id":84106,"url":"https://patchwork.plctlab.org/api/1.2/patches/84106/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230417095443.73581-1-nelson@rivosinc.com/","msgid":"<20230417095443.73581-1-nelson@rivosinc.com>","list_archive_url":null,"date":"2023-04-17T09:54:43","name":"RISC-V: Optimize relaxation of gp with max_alignment.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230417095443.73581-1-nelson@rivosinc.com/mbox/"},{"id":84192,"url":"https://patchwork.plctlab.org/api/1.2/patches/84192/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230417121633.68761-1-kito.cheng@sifive.com/","msgid":"<20230417121633.68761-1-kito.cheng@sifive.com>","list_archive_url":null,"date":"2023-04-17T12:16:33","name":"RISC-V: Cache the latest mapping symbol and its boundary.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230417121633.68761-1-kito.cheng@sifive.com/mbox/"},{"id":84514,"url":"https://patchwork.plctlab.org/api/1.2/patches/84514/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZD3xccVokEyi/Cbv@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-04-18T01:25:05","name":"objdump buffer overflow in fetch_indexed_string","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZD3xccVokEyi/Cbv@squeak.grove.modra.org/mbox/"},{"id":84515,"url":"https://patchwork.plctlab.org/api/1.2/patches/84515/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZD3xnwW1LKQe7Oqe@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-04-18T01:25:51","name":"objdump use of uninitialised value in pr_string_field","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZD3xnwW1LKQe7Oqe@squeak.grove.modra.org/mbox/"},{"id":84879,"url":"https://patchwork.plctlab.org/api/1.2/patches/84879/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230418140019.2195551-1-yunqiang.su@cipunited.com/","msgid":"<20230418140019.2195551-1-yunqiang.su@cipunited.com>","list_archive_url":null,"date":"2023-04-18T14:00:18","name":"[v4,1/2] MIPS: support mips*64 as CPU and gnuabi64 as ABI","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230418140019.2195551-1-yunqiang.su@cipunited.com/mbox/"},{"id":84880,"url":"https://patchwork.plctlab.org/api/1.2/patches/84880/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230418140019.2195551-2-yunqiang.su@cipunited.com/","msgid":"<20230418140019.2195551-2-yunqiang.su@cipunited.com>","list_archive_url":null,"date":"2023-04-18T14:00:19","name":"[v4,2/2] MIPS: default output r6 obj if the triple is r6","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230418140019.2195551-2-yunqiang.su@cipunited.com/mbox/"},{"id":84915,"url":"https://patchwork.plctlab.org/api/1.2/patches/84915/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.LSU.2.20.2304181502360.3155@wotan.suse.de/","msgid":"","list_archive_url":null,"date":"2023-04-18T15:12:12","name":"section-select: Fix performance problem (PR30367)","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.LSU.2.20.2304181502360.3155@wotan.suse.de/mbox/"},{"id":85574,"url":"https://patchwork.plctlab.org/api/1.2/patches/85574/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230419221125.502883-2-indu.bhagat@oracle.com/","msgid":"<20230419221125.502883-2-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-04-19T22:11:20","name":"[COMMITTED,1/6] gas: sframe: use ATTRIBUTE_UNUSED consistently","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230419221125.502883-2-indu.bhagat@oracle.com/mbox/"},{"id":85578,"url":"https://patchwork.plctlab.org/api/1.2/patches/85578/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230419221125.502883-3-indu.bhagat@oracle.com/","msgid":"<20230419221125.502883-3-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-04-19T22:11:21","name":"[COMMITTED,2/6] gas: sframe: fix comment","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230419221125.502883-3-indu.bhagat@oracle.com/mbox/"},{"id":85575,"url":"https://patchwork.plctlab.org/api/1.2/patches/85575/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230419221125.502883-4-indu.bhagat@oracle.com/","msgid":"<20230419221125.502883-4-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-04-19T22:11:22","name":"[COMMITTED,3/6] libsframe: use return type of bool for predicate functions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230419221125.502883-4-indu.bhagat@oracle.com/mbox/"},{"id":85577,"url":"https://patchwork.plctlab.org/api/1.2/patches/85577/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230419221125.502883-5-indu.bhagat@oracle.com/","msgid":"<20230419221125.502883-5-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-04-19T22:11:23","name":"[COMMITTED,4/6] sframe: correct some typos","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230419221125.502883-5-indu.bhagat@oracle.com/mbox/"},{"id":85576,"url":"https://patchwork.plctlab.org/api/1.2/patches/85576/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230419221125.502883-6-indu.bhagat@oracle.com/","msgid":"<20230419221125.502883-6-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-04-19T22:11:24","name":"[COMMITTED,5/6] libsframe: use consistent function argument names","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230419221125.502883-6-indu.bhagat@oracle.com/mbox/"},{"id":85579,"url":"https://patchwork.plctlab.org/api/1.2/patches/85579/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230419221125.502883-7-indu.bhagat@oracle.com/","msgid":"<20230419221125.502883-7-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-04-19T22:11:25","name":"[COMMITTED,6/6] libsframe: minor formatting fixes in sframe_encoder_write_fre","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230419221125.502883-7-indu.bhagat@oracle.com/mbox/"},{"id":85638,"url":"https://patchwork.plctlab.org/api/1.2/patches/85638/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZEBzqwgJEiqZ3AaD@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-04-19T23:05:15","name":"buffer overflow in print_symname","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZEBzqwgJEiqZ3AaD@squeak.grove.modra.org/mbox/"},{"id":85639,"url":"https://patchwork.plctlab.org/api/1.2/patches/85639/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZEB0Nkp//9ZWvzA4@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-04-19T23:07:34","name":"Yet another out-of-memory fuzzed object","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZEB0Nkp//9ZWvzA4@squeak.grove.modra.org/mbox/"},{"id":85640,"url":"https://patchwork.plctlab.org/api/1.2/patches/85640/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZEB0XGn82KUoFAth@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-04-19T23:08:12","name":"ubsan: signed integer overflow in display_debug_lines_raw","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZEB0XGn82KUoFAth@squeak.grove.modra.org/mbox/"},{"id":85641,"url":"https://patchwork.plctlab.org/api/1.2/patches/85641/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZEB0yrc7sb7PgfVj@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-04-19T23:10:02","name":"PR30343 infrastructure","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZEB0yrc7sb7PgfVj@squeak.grove.modra.org/mbox/"},{"id":85642,"url":"https://patchwork.plctlab.org/api/1.2/patches/85642/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZEB1FHCdkVcnkby8@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-04-19T23:11:16","name":"sh4-linux segfaults running ld testsuite","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZEB1FHCdkVcnkby8@squeak.grove.modra.org/mbox/"},{"id":85912,"url":"https://patchwork.plctlab.org/api/1.2/patches/85912/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230420133102.2422583-1-yunqiang.su@cipunited.com/","msgid":"<20230420133102.2422583-1-yunqiang.su@cipunited.com>","list_archive_url":null,"date":"2023-04-20T13:31:01","name":"[v5,1/2] MIPS: support mips*64 as CPU and gnuabi64 as ABI","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230420133102.2422583-1-yunqiang.su@cipunited.com/mbox/"},{"id":85913,"url":"https://patchwork.plctlab.org/api/1.2/patches/85913/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230420133102.2422583-2-yunqiang.su@cipunited.com/","msgid":"<20230420133102.2422583-2-yunqiang.su@cipunited.com>","list_archive_url":null,"date":"2023-04-20T13:31:02","name":"[v5,2/2] MIPS: default output r6 obj if the triple is r6","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230420133102.2422583-2-yunqiang.su@cipunited.com/mbox/"},{"id":86103,"url":"https://patchwork.plctlab.org/api/1.2/patches/86103/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZEH3P5K8BQ4euUsQ@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-04-21T02:38:55","name":"Delete struct artdata archive_head","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZEH3P5K8BQ4euUsQ@squeak.grove.modra.org/mbox/"},{"id":86104,"url":"https://patchwork.plctlab.org/api/1.2/patches/86104/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZEH5tX5D6VSOFPit@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-04-21T02:49:25","name":"Keeping track of rs6000-coff archive element pointers","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZEH5tX5D6VSOFPit@squeak.grove.modra.org/mbox/"},{"id":86139,"url":"https://patchwork.plctlab.org/api/1.2/patches/86139/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/72cd2df6-f7dd-9217-aa03-e218631c879e@suse.com/","msgid":"<72cd2df6-f7dd-9217-aa03-e218631c879e@suse.com>","list_archive_url":null,"date":"2023-04-21T05:53:28","name":"ld: add missing period after @xref","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/72cd2df6-f7dd-9217-aa03-e218631c879e@suse.com/mbox/"},{"id":86171,"url":"https://patchwork.plctlab.org/api/1.2/patches/86171/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230421082839.41542-1-nelson@rivosinc.com/","msgid":"<20230421082839.41542-1-nelson@rivosinc.com>","list_archive_url":null,"date":"2023-04-21T08:28:38","name":"[1/2] RISC-V: Relax R_RISCV_[PCREL_]LO12_I/S to R_RISCV_GPREL_I/S for undefined weak.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230421082839.41542-1-nelson@rivosinc.com/mbox/"},{"id":86170,"url":"https://patchwork.plctlab.org/api/1.2/patches/86170/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230421082839.41542-2-nelson@rivosinc.com/","msgid":"<20230421082839.41542-2-nelson@rivosinc.com>","list_archive_url":null,"date":"2023-04-21T08:28:39","name":"[2/2] RISC-V: Enable x0 base relaxation for relax_pc even if --no-relax-gp.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230421082839.41542-2-nelson@rivosinc.com/mbox/"},{"id":86203,"url":"https://patchwork.plctlab.org/api/1.2/patches/86203/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230421094346.3017667-1-mengqinggang@loongson.cn/","msgid":"<20230421094346.3017667-1-mengqinggang@loongson.cn>","list_archive_url":null,"date":"2023-04-21T09:43:46","name":"LoongArch: Fix loongarch32 test fails","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230421094346.3017667-1-mengqinggang@loongson.cn/mbox/"},{"id":86214,"url":"https://patchwork.plctlab.org/api/1.2/patches/86214/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f339bf78-9ba2-594b-3dec-232edb0e7f70@suse.com/","msgid":"","list_archive_url":null,"date":"2023-04-21T10:05:16","name":"bfd: fix STRICT_PE_FORMAT build","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f339bf78-9ba2-594b-3dec-232edb0e7f70@suse.com/mbox/"},{"id":86221,"url":"https://patchwork.plctlab.org/api/1.2/patches/86221/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0ece83ad-f7a0-7951-374b-2c86cbafad36@suse.com/","msgid":"<0ece83ad-f7a0-7951-374b-2c86cbafad36@suse.com>","list_archive_url":null,"date":"2023-04-21T10:16:23","name":"[1/2] x86: rework AMX multiplication insn disassembly","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0ece83ad-f7a0-7951-374b-2c86cbafad36@suse.com/mbox/"},{"id":86222,"url":"https://patchwork.plctlab.org/api/1.2/patches/86222/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/657c81bd-2182-c663-04a4-c5e6962531ea@suse.com/","msgid":"<657c81bd-2182-c663-04a4-c5e6962531ea@suse.com>","list_archive_url":null,"date":"2023-04-21T10:16:59","name":"[2/2] x86: rework AMX control insn disassembly","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/657c81bd-2182-c663-04a4-c5e6962531ea@suse.com/mbox/"},{"id":86240,"url":"https://patchwork.plctlab.org/api/1.2/patches/86240/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/335d1933-a5dc-9183-cbe7-d8b139e232fc@suse.com/","msgid":"<335d1933-a5dc-9183-cbe7-d8b139e232fc@suse.com>","list_archive_url":null,"date":"2023-04-21T10:26:15","name":"gas: move shift count check","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/335d1933-a5dc-9183-cbe7-d8b139e232fc@suse.com/mbox/"},{"id":86274,"url":"https://patchwork.plctlab.org/api/1.2/patches/86274/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4c40b0d1-8375-9284-cfaf-ce63b8df1b9b@suse.com/","msgid":"<4c40b0d1-8375-9284-cfaf-ce63b8df1b9b@suse.com>","list_archive_url":null,"date":"2023-04-21T12:17:54","name":"gas: equates of registers","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4c40b0d1-8375-9284-cfaf-ce63b8df1b9b@suse.com/mbox/"},{"id":86301,"url":"https://patchwork.plctlab.org/api/1.2/patches/86301/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230421130802.2964785-1-tromey@adacore.com/","msgid":"<20230421130802.2964785-1-tromey@adacore.com>","list_archive_url":null,"date":"2023-04-21T13:08:02","name":"Fix -Wmaybe-uninitialized warning in opcodes/i386-dis.c","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230421130802.2964785-1-tromey@adacore.com/mbox/"},{"id":86651,"url":"https://patchwork.plctlab.org/api/1.2/patches/86651/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230423015546.2664272-1-mengqinggang@loongson.cn/","msgid":"<20230423015546.2664272-1-mengqinggang@loongson.cn>","list_archive_url":null,"date":"2023-04-23T01:55:46","name":"[v1] LoongArch: Fix loongarch32 test fails","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230423015546.2664272-1-mengqinggang@loongson.cn/mbox/"},{"id":86786,"url":"https://patchwork.plctlab.org/api/1.2/patches/86786/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230423173021.582102-1-och95@yandex.ru/","msgid":"<20230423173021.582102-1-och95@yandex.ru>","list_archive_url":null,"date":"2023-04-23T17:30:21","name":"Fix emit-relocs for aarch64 gold","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230423173021.582102-1-och95@yandex.ru/mbox/"},{"id":86885,"url":"https://patchwork.plctlab.org/api/1.2/patches/86885/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a475270f-97f0-4fc7-bd0c-eb99bd8b2b3c@suse.com/","msgid":"","list_archive_url":null,"date":"2023-04-24T07:34:27","name":"[1/3] x86: work around compiler diagnosing dangling pointer","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a475270f-97f0-4fc7-bd0c-eb99bd8b2b3c@suse.com/mbox/"},{"id":86886,"url":"https://patchwork.plctlab.org/api/1.2/patches/86886/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c26e2fcd-62aa-98f3-1b62-0c53ce7d16a5@suse.com/","msgid":"","list_archive_url":null,"date":"2023-04-24T07:35:05","name":"[2/3] x86: limit data passed to prefix_name()","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c26e2fcd-62aa-98f3-1b62-0c53ce7d16a5@suse.com/mbox/"},{"id":86887,"url":"https://patchwork.plctlab.org/api/1.2/patches/86887/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b3511736-584c-6c99-9046-331a18c60417@suse.com/","msgid":"","list_archive_url":null,"date":"2023-04-24T07:35:28","name":"[3/3] x86: limit data passed to i386_dis_printf()","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b3511736-584c-6c99-9046-331a18c60417@suse.com/mbox/"},{"id":86999,"url":"https://patchwork.plctlab.org/api/1.2/patches/86999/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZEZoqCKm+ebNL+I7@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-04-24T11:31:52","name":"objcopy of archives tidy","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZEZoqCKm+ebNL+I7@squeak.grove.modra.org/mbox/"},{"id":87000,"url":"https://patchwork.plctlab.org/api/1.2/patches/87000/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZEZo4oH/oT6Gu/5S@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-04-24T11:32:50","name":"asan: segfault in coff_mangle_symbols","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZEZo4oH/oT6Gu/5S@squeak.grove.modra.org/mbox/"},{"id":87259,"url":"https://patchwork.plctlab.org/api/1.2/patches/87259/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230425065626.3587754-1-yunqiang.su@cipunited.com/","msgid":"<20230425065626.3587754-1-yunqiang.su@cipunited.com>","list_archive_url":null,"date":"2023-04-25T06:56:26","name":"MIPS: add MT ASE support for micromips32","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230425065626.3587754-1-yunqiang.su@cipunited.com/mbox/"},{"id":87491,"url":"https://patchwork.plctlab.org/api/1.2/patches/87491/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/CACcXsZjbOetUzc5MOhWFJbqkkhuurqcDD7faHs9PJjM02Be9TA@mail.gmail.com/","msgid":"","list_archive_url":null,"date":"2023-04-25T16:48:11","name":"optimize handle_COMDAT","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/CACcXsZjbOetUzc5MOhWFJbqkkhuurqcDD7faHs9PJjM02Be9TA@mail.gmail.com/mbox/"},{"id":87591,"url":"https://patchwork.plctlab.org/api/1.2/patches/87591/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZEiNgqU+7bX6pfwL@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-04-26T02:33:38","name":"Avoid another -Werror=dangling-pointer","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZEiNgqU+7bX6pfwL@squeak.grove.modra.org/mbox/"},{"id":87592,"url":"https://patchwork.plctlab.org/api/1.2/patches/87592/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZEiN3mQ74ldcG/+R@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-04-26T02:35:10","name":"binutils runtest $CC","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZEiN3mQ74ldcG/+R@squeak.grove.modra.org/mbox/"},{"id":87598,"url":"https://patchwork.plctlab.org/api/1.2/patches/87598/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZEirEhA/zSf9YWhh@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-04-26T04:39:46","name":"i386-dis.c UB shift and other tidies","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZEirEhA/zSf9YWhh@squeak.grove.modra.org/mbox/"},{"id":87791,"url":"https://patchwork.plctlab.org/api/1.2/patches/87791/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230426101640.264902-1-yunqiang.su@cipunited.com/","msgid":"<20230426101640.264902-1-yunqiang.su@cipunited.com>","list_archive_url":null,"date":"2023-04-26T10:16:39","name":"[v2,1/2] MIPS: add MT ASE support for micromips32","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230426101640.264902-1-yunqiang.su@cipunited.com/mbox/"},{"id":87792,"url":"https://patchwork.plctlab.org/api/1.2/patches/87792/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230426101640.264902-2-yunqiang.su@cipunited.com/","msgid":"<20230426101640.264902-2-yunqiang.su@cipunited.com>","list_archive_url":null,"date":"2023-04-26T10:16:40","name":"[v2,2/2] MIPS: sync oprand char usage between mips and micromips","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230426101640.264902-2-yunqiang.su@cipunited.com/mbox/"},{"id":87865,"url":"https://patchwork.plctlab.org/api/1.2/patches/87865/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5aebce50-8b8a-26ee-b452-d9164668c145@suse.com/","msgid":"<5aebce50-8b8a-26ee-b452-d9164668c145@suse.com>","list_archive_url":null,"date":"2023-04-26T13:15:38","name":"x86/Intel: reduce ELF/PE conditional scope in x86_cons()","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5aebce50-8b8a-26ee-b452-d9164668c145@suse.com/mbox/"},{"id":87876,"url":"https://patchwork.plctlab.org/api/1.2/patches/87876/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.LSU.2.20.2304261416140.3155@wotan.suse.de/","msgid":"","list_archive_url":null,"date":"2023-04-26T14:16:55","name":"Fix PR30358, performance with --sort-section","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.LSU.2.20.2304261416140.3155@wotan.suse.de/mbox/"},{"id":87921,"url":"https://patchwork.plctlab.org/api/1.2/patches/87921/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230426173123.24564-1-jose.marchesi@oracle.com/","msgid":"<20230426173123.24564-1-jose.marchesi@oracle.com>","list_archive_url":null,"date":"2023-04-26T17:31:21","name":"[COMMITTED,1/3] gas: support for the BPF pseudo-c assembly syntax","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230426173123.24564-1-jose.marchesi@oracle.com/mbox/"},{"id":87924,"url":"https://patchwork.plctlab.org/api/1.2/patches/87924/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230426173123.24564-2-jose.marchesi@oracle.com/","msgid":"<20230426173123.24564-2-jose.marchesi@oracle.com>","list_archive_url":null,"date":"2023-04-26T17:31:22","name":"[COMMITTED,2/3] gas: BPF pseudo-c syntax tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230426173123.24564-2-jose.marchesi@oracle.com/mbox/"},{"id":87922,"url":"https://patchwork.plctlab.org/api/1.2/patches/87922/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230426173123.24564-3-jose.marchesi@oracle.com/","msgid":"<20230426173123.24564-3-jose.marchesi@oracle.com>","list_archive_url":null,"date":"2023-04-26T17:31:23","name":"[COMMITTED,3/3] gas: documentation for the BPF pseudo-c asm syntax","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230426173123.24564-3-jose.marchesi@oracle.com/mbox/"},{"id":87976,"url":"https://patchwork.plctlab.org/api/1.2/patches/87976/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9b903d19-c4b7-40a3-dce0-84d36e4ff32c@ventanamicro.com/","msgid":"<9b903d19-c4b7-40a3-dce0-84d36e4ff32c@ventanamicro.com>","list_archive_url":null,"date":"2023-04-26T20:28:40","name":"[committed] RISC-V: XVentanaCondops support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9b903d19-c4b7-40a3-dce0-84d36e4ff32c@ventanamicro.com/mbox/"},{"id":88220,"url":"https://patchwork.plctlab.org/api/1.2/patches/88220/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/87354lr0sz.fsf@redhat.com/","msgid":"<87354lr0sz.fsf@redhat.com>","list_archive_url":null,"date":"2023-04-27T12:01:48","name":"Commit: ld: Add ability to print hex values in the linker map","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/87354lr0sz.fsf@redhat.com/mbox/"},{"id":88258,"url":"https://patchwork.plctlab.org/api/1.2/patches/88258/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230427125607.362035-1-iii@linux.ibm.com/","msgid":"<20230427125607.362035-1-iii@linux.ibm.com>","list_archive_url":null,"date":"2023-04-27T12:56:07","name":"gas: fix building tc-bpf.c on s390x","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230427125607.362035-1-iii@linux.ibm.com/mbox/"},{"id":88359,"url":"https://patchwork.plctlab.org/api/1.2/patches/88359/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/CACcXsZjzrLPP5Ngo2bt20hkCQF+uvZ2syNvz5rW-bha_mDTfQw@mail.gmail.com/","msgid":"","list_archive_url":null,"date":"2023-04-27T18:24:48","name":"make coff_compute_checksum faster","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/CACcXsZjzrLPP5Ngo2bt20hkCQF+uvZ2syNvz5rW-bha_mDTfQw@mail.gmail.com/mbox/"},{"id":88408,"url":"https://patchwork.plctlab.org/api/1.2/patches/88408/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/CACcXsZi9c641-gEbCZbP0=Ni+sJKbEwW3gV6CMpT4wOjks85dg@mail.gmail.com/","msgid":"","list_archive_url":null,"date":"2023-04-27T23:35:20","name":"make ar faster","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/CACcXsZi9c641-gEbCZbP0=Ni+sJKbEwW3gV6CMpT4wOjks85dg@mail.gmail.com/mbox/"},{"id":88459,"url":"https://patchwork.plctlab.org/api/1.2/patches/88459/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZEtkW7ozVq5sX1e8@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-04-28T06:14:51","name":"Make bfd_byte an int8_t, flagword a uint32_t","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZEtkW7ozVq5sX1e8@squeak.grove.modra.org/mbox/"},{"id":88460,"url":"https://patchwork.plctlab.org/api/1.2/patches/88460/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZEtkeBiugmBcY34m@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-04-28T06:15:20","name":"Remove deprecated bfd_read","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZEtkeBiugmBcY34m@squeak.grove.modra.org/mbox/"},{"id":88639,"url":"https://patchwork.plctlab.org/api/1.2/patches/88639/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e1da592f-5c5b-418b-a25b-afeeb0691ea7@suse.com/","msgid":"","list_archive_url":null,"date":"2023-04-28T12:57:30","name":"RISC-V: tighten post-relocation-operator separator expectation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e1da592f-5c5b-418b-a25b-afeeb0691ea7@suse.com/mbox/"},{"id":88872,"url":"https://patchwork.plctlab.org/api/1.2/patches/88872/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/CACcXsZjWfeQR3_pC3nVtq+sAkq-QGfEnA3DE2K8rsDnK9edWrQ@mail.gmail.com/","msgid":"","list_archive_url":null,"date":"2023-04-29T11:19:26","name":"add section caches to coff_data_type","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/CACcXsZjWfeQR3_pC3nVtq+sAkq-QGfEnA3DE2K8rsDnK9edWrQ@mail.gmail.com/mbox/"},{"id":88907,"url":"https://patchwork.plctlab.org/api/1.2/patches/88907/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/541a3fba-3b07-d4e3-f913-f10d7163a59e@netcologne.de/","msgid":"<541a3fba-3b07-d4e3-f913-f10d7163a59e@netcologne.de>","list_archive_url":null,"date":"2023-04-30T10:16:23","name":"[gas,documentation] Some additional testsuite info","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/541a3fba-3b07-d4e3-f913-f10d7163a59e@netcologne.de/mbox/"}],"public":true,"mbox":"https://patchwork.plctlab.org/bundle/patchwork-bot/binutils-gdb_2023-04/mbox/"},{"id":22,"url":"https://patchwork.plctlab.org/api/1.2/bundles/22/","web_url":"https://patchwork.plctlab.org/bundle/patchwork-bot/binutils-gdb_2023-05/","project":{"id":2,"url":"https://patchwork.plctlab.org/api/1.2/projects/2/","name":"binutils-gdb","link_name":"binutils-gdb","list_id":"binutils.sourceware.org","list_email":"binutils@sourceware.org","web_url":"https://github.com/wangliu-iscas/Patchwork-Bundles/blob/main/binutils-gdb.md","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"name":"binutils-gdb_2023-05","owner":{"id":3,"url":"https://patchwork.plctlab.org/api/1.2/users/3/","username":"patchwork-bot","first_name":"","last_name":"","email":"ouuuleilei@gmail.com"},"patches":[{"id":89293,"url":"https://patchwork.plctlab.org/api/1.2/patches/89293/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3a7b6bb3-4ab0-15af-0c74-5d7798ac3793@suse.com/","msgid":"<3a7b6bb3-4ab0-15af-0c74-5d7798ac3793@suse.com>","list_archive_url":null,"date":"2023-05-02T09:04:28","name":"[v2] gas: equates of registers","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3a7b6bb3-4ab0-15af-0c74-5d7798ac3793@suse.com/mbox/"},{"id":89429,"url":"https://patchwork.plctlab.org/api/1.2/patches/89429/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3cdc56a8-62eb-d33c-3038-0af00d8a52ba@codesourcery.com/","msgid":"<3cdc56a8-62eb-d33c-3038-0af00d8a52ba@codesourcery.com>","list_archive_url":null,"date":"2023-05-02T17:19:14","name":"[RFC] Linker plugin - extend API for offloading corner case (aka: LDPT_REGISTER_CLAIM_FILE_HOOK_V2 linker plugin hook [GCC PR109128])","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3cdc56a8-62eb-d33c-3038-0af00d8a52ba@codesourcery.com/mbox/"},{"id":89523,"url":"https://patchwork.plctlab.org/api/1.2/patches/89523/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZFGkCFaFJysW0kh1@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-05-03T00:00:08","name":"_bfd_mips_elf_lo16_reloc vallo comment","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZFGkCFaFJysW0kh1@squeak.grove.modra.org/mbox/"},{"id":89569,"url":"https://patchwork.plctlab.org/api/1.2/patches/89569/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZFH4p/bxWZOU/b70@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-05-03T06:01:11","name":"Change signature of bfd crc functions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZFH4p/bxWZOU/b70@squeak.grove.modra.org/mbox/"},{"id":89570,"url":"https://patchwork.plctlab.org/api/1.2/patches/89570/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZFH4xh+ePb7tKT7Q@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-05-03T06:01:42","name":"libbfc.c: Use stdint types for unsigned char and unsigned long","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZFH4xh+ePb7tKT7Q@squeak.grove.modra.org/mbox/"},{"id":89571,"url":"https://patchwork.plctlab.org/api/1.2/patches/89571/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZFH44S/nfshKLrn9@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-05-03T06:02:09","name":"hash.c: replace some unsigned long with unsigned int","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZFH44S/nfshKLrn9@squeak.grove.modra.org/mbox/"},{"id":89572,"url":"https://patchwork.plctlab.org/api/1.2/patches/89572/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZFH5CJb/dZFBG9hD@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-05-03T06:02:48","name":"Move bfd_elf_bfd_from_remote_memory to opncls.c","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZFH5CJb/dZFBG9hD@squeak.grove.modra.org/mbox/"},{"id":89573,"url":"https://patchwork.plctlab.org/api/1.2/patches/89573/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZFH5Jt7SVTKp0rvP@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-05-03T06:03:18","name":"Move bfd_alloc, bfd_zalloc and bfd_release to libbfd.c","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZFH5Jt7SVTKp0rvP@squeak.grove.modra.org/mbox/"},{"id":89574,"url":"https://patchwork.plctlab.org/api/1.2/patches/89574/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZFH5gcFv4YXk03OL@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-05-03T06:04:49","name":"Generated docs and include files","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZFH5gcFv4YXk03OL@squeak.grove.modra.org/mbox/"},{"id":89577,"url":"https://patchwork.plctlab.org/api/1.2/patches/89577/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZFIAiF82oU/87le9@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-05-03T06:34:48","name":"Remove unused args from bfd_make_debug_symbol","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZFIAiF82oU/87le9@squeak.grove.modra.org/mbox/"},{"id":89732,"url":"https://patchwork.plctlab.org/api/1.2/patches/89732/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230503120210.564966-1-iii@linux.ibm.com/","msgid":"<20230503120210.564966-1-iii@linux.ibm.com>","list_archive_url":null,"date":"2023-05-03T12:02:10","name":"[v2] gas: fix building tc-bpf.c on s390x","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230503120210.564966-1-iii@linux.ibm.com/mbox/"},{"id":89794,"url":"https://patchwork.plctlab.org/api/1.2/patches/89794/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230503171124.6710-1-dimitar@dinux.eu/","msgid":"<20230503171124.6710-1-dimitar@dinux.eu>","list_archive_url":null,"date":"2023-05-03T17:11:24","name":"ld: pru: Place exception-handling sections correctly","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230503171124.6710-1-dimitar@dinux.eu/mbox/"},{"id":89976,"url":"https://patchwork.plctlab.org/api/1.2/patches/89976/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230504081452.50748-1-nelson@rivosinc.com/","msgid":"<20230504081452.50748-1-nelson@rivosinc.com>","list_archive_url":null,"date":"2023-05-04T08:14:52","name":"RISC-V: Minor improvements for dis-assembler.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230504081452.50748-1-nelson@rivosinc.com/mbox/"},{"id":90003,"url":"https://patchwork.plctlab.org/api/1.2/patches/90003/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230504090850.91004-1-nelson@rivosinc.com/","msgid":"<20230504090850.91004-1-nelson@rivosinc.com>","list_archive_url":null,"date":"2023-05-04T09:08:50","name":"[PR,ld/22263,PR,ld/25694] RISC-V: Avoid dynamic TLS relocs in PIE.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230504090850.91004-1-nelson@rivosinc.com/mbox/"},{"id":90380,"url":"https://patchwork.plctlab.org/api/1.2/patches/90380/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230505092316.1046472-1-aleksandar.rikalo@syrmia.com/","msgid":"<20230505092316.1046472-1-aleksandar.rikalo@syrmia.com>","list_archive_url":null,"date":"2023-05-05T09:23:16","name":"[v5] Add support for nanoMIPS architecture","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230505092316.1046472-1-aleksandar.rikalo@syrmia.com/mbox/"},{"id":90383,"url":"https://patchwork.plctlab.org/api/1.2/patches/90383/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230505092716.885338-1-yunqiang.su@cipunited.com/","msgid":"<20230505092716.885338-1-yunqiang.su@cipunited.com>","list_archive_url":null,"date":"2023-05-05T09:27:16","name":"gas: documents .gnu_attribute Tag_GNU_MIPS_ABI_MSA","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230505092716.885338-1-yunqiang.su@cipunited.com/mbox/"},{"id":90408,"url":"https://patchwork.plctlab.org/api/1.2/patches/90408/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a63ab9f1-6150-1948-c6e2-6a77855155e6@suse.com/","msgid":"","list_archive_url":null,"date":"2023-05-05T11:10:21","name":"x86: slightly simplify i386_parse_name()","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a63ab9f1-6150-1948-c6e2-6a77855155e6@suse.com/mbox/"},{"id":90410,"url":"https://patchwork.plctlab.org/api/1.2/patches/90410/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/52d14c6e-e232-efe3-d486-06cda1c19fdf@suse.com/","msgid":"<52d14c6e-e232-efe3-d486-06cda1c19fdf@suse.com>","list_archive_url":null,"date":"2023-05-05T11:12:44","name":"[1/2] x86: move get() disassembler helper functions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/52d14c6e-e232-efe3-d486-06cda1c19fdf@suse.com/mbox/"},{"id":90411,"url":"https://patchwork.plctlab.org/api/1.2/patches/90411/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/666d8c60-5ffe-a307-f260-0c4bbd674887@suse.com/","msgid":"<666d8c60-5ffe-a307-f260-0c4bbd674887@suse.com>","list_archive_url":null,"date":"2023-05-05T11:13:10","name":"[2/2] x86: move a few more disassembler helper functions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/666d8c60-5ffe-a307-f260-0c4bbd674887@suse.com/mbox/"},{"id":90430,"url":"https://patchwork.plctlab.org/api/1.2/patches/90430/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4735d366-fe31-0092-2edc-d166184b8567@suse.com/","msgid":"<4735d366-fe31-0092-2edc-d166184b8567@suse.com>","list_archive_url":null,"date":"2023-05-05T12:51:05","name":"[1/2] x86: don'\''t recognize quoted symbol names as registers or operators","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4735d366-fe31-0092-2edc-d166184b8567@suse.com/mbox/"},{"id":90431,"url":"https://patchwork.plctlab.org/api/1.2/patches/90431/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9d0f914a-5668-a09b-5993-16a2270cf059@suse.com/","msgid":"<9d0f914a-5668-a09b-5993-16a2270cf059@suse.com>","list_archive_url":null,"date":"2023-05-05T12:52:02","name":"[2/2] x86/Intel: address quoted-symbol related FIXMEs","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9d0f914a-5668-a09b-5993-16a2270cf059@suse.com/mbox/"},{"id":90432,"url":"https://patchwork.plctlab.org/api/1.2/patches/90432/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/168dfa6e-63d2-06d5-49d5-4d7a1797efb4@suse.com/","msgid":"<168dfa6e-63d2-06d5-49d5-4d7a1797efb4@suse.com>","list_archive_url":null,"date":"2023-05-05T13:01:10","name":"[1/4] x86: tighten extend-to-32bit-address conditions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/168dfa6e-63d2-06d5-49d5-4d7a1797efb4@suse.com/mbox/"},{"id":90434,"url":"https://patchwork.plctlab.org/api/1.2/patches/90434/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/905e0a5d-d49d-03a6-d441-302bc5c2da6a@suse.com/","msgid":"<905e0a5d-d49d-03a6-d441-302bc5c2da6a@suse.com>","list_archive_url":null,"date":"2023-05-05T13:01:57","name":"[2/4] gas: maintain O_constant signedness in more cases","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/905e0a5d-d49d-03a6-d441-302bc5c2da6a@suse.com/mbox/"},{"id":90435,"url":"https://patchwork.plctlab.org/api/1.2/patches/90435/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a766b568-5192-9660-34cd-2df6415a85c4@suse.com/","msgid":"","list_archive_url":null,"date":"2023-05-05T13:03:57","name":"[3/4] gas: invoke md_optimize_expr() also for unary expressions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a766b568-5192-9660-34cd-2df6415a85c4@suse.com/mbox/"},{"id":90436,"url":"https://patchwork.plctlab.org/api/1.2/patches/90436/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4f7d2d8d-d4fd-a799-9c8f-7a955a786d60@suse.com/","msgid":"<4f7d2d8d-d4fd-a799-9c8f-7a955a786d60@suse.com>","list_archive_url":null,"date":"2023-05-05T13:04:37","name":"[4/4] x86: further adjust extend-to-32bit-address conditions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4f7d2d8d-d4fd-a799-9c8f-7a955a786d60@suse.com/mbox/"},{"id":90707,"url":"https://patchwork.plctlab.org/api/1.2/patches/90707/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230506083718.3669965-1-yunqiang.su@cipunited.com/","msgid":"<20230506083718.3669965-1-yunqiang.su@cipunited.com>","list_archive_url":null,"date":"2023-05-06T08:37:18","name":"MIPS: gas: alter 64 or 32 for r6 triples if march is implicit","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230506083718.3669965-1-yunqiang.su@cipunited.com/mbox/"},{"id":90756,"url":"https://patchwork.plctlab.org/api/1.2/patches/90756/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/OS3P286MB2152C5D5037E18A71DEBF80BF0739@OS3P286MB2152.JPNP286.PROD.OUTLOOK.COM/","msgid":"","list_archive_url":null,"date":"2023-05-06T13:11:56","name":"Fix a typo in the README of binutils","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/OS3P286MB2152C5D5037E18A71DEBF80BF0739@OS3P286MB2152.JPNP286.PROD.OUTLOOK.COM/mbox/"},{"id":90933,"url":"https://patchwork.plctlab.org/api/1.2/patches/90933/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZFh73WJCS1aujdsO@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-05-08T04:34:37","name":"PR30343, LTO ignores linker reference to _pei386_runtime_relocator","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZFh73WJCS1aujdsO@squeak.grove.modra.org/mbox/"},{"id":90934,"url":"https://patchwork.plctlab.org/api/1.2/patches/90934/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZFh8AXXazWkP9+0w@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-05-08T04:35:13","name":"pe.em and pep.em make_import_fixup","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZFh8AXXazWkP9+0w@squeak.grove.modra.org/mbox/"},{"id":91322,"url":"https://patchwork.plctlab.org/api/1.2/patches/91322/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230509003247.24156-1-mark@harmstone.com/","msgid":"<20230509003247.24156-1-mark@harmstone.com>","list_archive_url":null,"date":"2023-05-09T00:32:46","name":"[1/2] pdb: Allow loading by gdb","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230509003247.24156-1-mark@harmstone.com/mbox/"},{"id":91323,"url":"https://patchwork.plctlab.org/api/1.2/patches/91323/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230509003247.24156-2-mark@harmstone.com/","msgid":"<20230509003247.24156-2-mark@harmstone.com>","list_archive_url":null,"date":"2023-05-09T00:32:47","name":"[2/2] gdb: Allow reading of enum definitions in PDB files","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230509003247.24156-2-mark@harmstone.com/mbox/"},{"id":91360,"url":"https://patchwork.plctlab.org/api/1.2/patches/91360/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZFnEez0cjGviUx4M@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-05-09T03:56:43","name":"alpha-vms reloc sanity check","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZFnEez0cjGviUx4M@squeak.grove.modra.org/mbox/"},{"id":91405,"url":"https://patchwork.plctlab.org/api/1.2/patches/91405/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZFn66p7K1lW/yNEL@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-05-09T07:48:58","name":"stack overflow in debug_write_type","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZFn66p7K1lW/yNEL@squeak.grove.modra.org/mbox/"},{"id":92148,"url":"https://patchwork.plctlab.org/api/1.2/patches/92148/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.LSU.2.20.2305101400000.13548@wotan.suse.de/","msgid":"","list_archive_url":null,"date":"2023-05-10T14:04:27","name":"PR30437 aarch64: make RELA relocs idempotent","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.LSU.2.20.2305101400000.13548@wotan.suse.de/mbox/"},{"id":92153,"url":"https://patchwork.plctlab.org/api/1.2/patches/92153/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230510141829.2748105-2-aleksandar.rikalo@syrmia.com/","msgid":"<20230510141829.2748105-2-aleksandar.rikalo@syrmia.com>","list_archive_url":null,"date":"2023-05-10T14:18:27","name":"[v6,1/3] BFD changes for nanoMIPS support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230510141829.2748105-2-aleksandar.rikalo@syrmia.com/mbox/"},{"id":92154,"url":"https://patchwork.plctlab.org/api/1.2/patches/92154/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230510141829.2748105-3-aleksandar.rikalo@syrmia.com/","msgid":"<20230510141829.2748105-3-aleksandar.rikalo@syrmia.com>","list_archive_url":null,"date":"2023-05-10T14:18:28","name":"[v6,2/3] Opcodes changes for nanoMIPS support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230510141829.2748105-3-aleksandar.rikalo@syrmia.com/mbox/"},{"id":92152,"url":"https://patchwork.plctlab.org/api/1.2/patches/92152/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230510141829.2748105-4-aleksandar.rikalo@syrmia.com/","msgid":"<20230510141829.2748105-4-aleksandar.rikalo@syrmia.com>","list_archive_url":null,"date":"2023-05-10T14:18:29","name":"[v6,3/3] Readelf for nanoMIPS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230510141829.2748105-4-aleksandar.rikalo@syrmia.com/mbox/"},{"id":92359,"url":"https://patchwork.plctlab.org/api/1.2/patches/92359/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/243D0799-E3D0-4938-A438-DD8725593F67@free.fr/","msgid":"<243D0799-E3D0-4938-A438-DD8725593F67@free.fr>","list_archive_url":null,"date":"2023-05-11T05:28:58","name":"pe/coff - add support for base64 encoded long section names","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/243D0799-E3D0-4938-A438-DD8725593F67@free.fr/mbox/"},{"id":92467,"url":"https://patchwork.plctlab.org/api/1.2/patches/92467/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230511100354.3995358-1-mengqinggang@loongson.cn/","msgid":"<20230511100354.3995358-1-mengqinggang@loongson.cn>","list_archive_url":null,"date":"2023-05-11T10:03:54","name":"LoongArch: Fix PLT entry generate bug","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230511100354.3995358-1-mengqinggang@loongson.cn/mbox/"},{"id":92629,"url":"https://patchwork.plctlab.org/api/1.2/patches/92629/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230511141351.18886-2-jose.marchesi@oracle.com/","msgid":"<20230511141351.18886-2-jose.marchesi@oracle.com>","list_archive_url":null,"date":"2023-05-11T14:13:48","name":"[1/4] opcodes: use CGEN_INSN_LGUINT for base instructions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230511141351.18886-2-jose.marchesi@oracle.com/mbox/"},{"id":92630,"url":"https://patchwork.plctlab.org/api/1.2/patches/92630/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230511141351.18886-3-jose.marchesi@oracle.com/","msgid":"<20230511141351.18886-3-jose.marchesi@oracle.com>","list_archive_url":null,"date":"2023-05-11T14:13:49","name":"[2/4] cpu: add V3 BPF atomic instructions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230511141351.18886-3-jose.marchesi@oracle.com/mbox/"},{"id":92634,"url":"https://patchwork.plctlab.org/api/1.2/patches/92634/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230511141351.18886-4-jose.marchesi@oracle.com/","msgid":"<20230511141351.18886-4-jose.marchesi@oracle.com>","list_archive_url":null,"date":"2023-05-11T14:13:50","name":"[3/4] gas: add tests for BPF V3 atomic instructions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230511141351.18886-4-jose.marchesi@oracle.com/mbox/"},{"id":92637,"url":"https://patchwork.plctlab.org/api/1.2/patches/92637/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230511141351.18886-5-jose.marchesi@oracle.com/","msgid":"<20230511141351.18886-5-jose.marchesi@oracle.com>","list_archive_url":null,"date":"2023-05-11T14:13:51","name":"[4/4] gas: document V3 BPF atomic instructions in the GAS manual","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230511141351.18886-5-jose.marchesi@oracle.com/mbox/"},{"id":92848,"url":"https://patchwork.plctlab.org/api/1.2/patches/92848/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230511210232.1491265-1-goldstein.w.n@gmail.com/","msgid":"<20230511210232.1491265-1-goldstein.w.n@gmail.com>","list_archive_url":null,"date":"2023-05-11T21:02:32","name":"[v1] gold: Make '\''--section-ordering-file'\'' also specifiable in env variable","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230511210232.1491265-1-goldstein.w.n@gmail.com/mbox/"},{"id":92935,"url":"https://patchwork.plctlab.org/api/1.2/patches/92935/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/de17e059-80f6-5aa9-b693-14bdac45f0a4@rivosinc.com/","msgid":"","list_archive_url":null,"date":"2023-05-12T03:44:43","name":"[RFC] RISC-V: Support Zacas extension.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/de17e059-80f6-5aa9-b693-14bdac45f0a4@rivosinc.com/mbox/"},{"id":92974,"url":"https://patchwork.plctlab.org/api/1.2/patches/92974/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230512071720.1880195-2-yunqiang.su@cipunited.com/","msgid":"<20230512071720.1880195-2-yunqiang.su@cipunited.com>","list_archive_url":null,"date":"2023-05-12T07:17:17","name":"[1/4] MIPS: gas: alter 64 or 32 for mipsisa triples if march is implicit","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230512071720.1880195-2-yunqiang.su@cipunited.com/mbox/"},{"id":92976,"url":"https://patchwork.plctlab.org/api/1.2/patches/92976/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230512071720.1880195-3-yunqiang.su@cipunited.com/","msgid":"<20230512071720.1880195-3-yunqiang.su@cipunited.com>","list_archive_url":null,"date":"2023-05-12T07:17:18","name":"[2/4] MIPS: default r6 if vendor is img","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230512071720.1880195-3-yunqiang.su@cipunited.com/mbox/"},{"id":92978,"url":"https://patchwork.plctlab.org/api/1.2/patches/92978/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230512071720.1880195-4-yunqiang.su@cipunited.com/","msgid":"<20230512071720.1880195-4-yunqiang.su@cipunited.com>","list_archive_url":null,"date":"2023-05-12T07:17:19","name":"[3/4] MIPS: fix r6 testsuites","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230512071720.1880195-4-yunqiang.su@cipunited.com/mbox/"},{"id":92975,"url":"https://patchwork.plctlab.org/api/1.2/patches/92975/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230512071720.1880195-5-yunqiang.su@cipunited.com/","msgid":"<20230512071720.1880195-5-yunqiang.su@cipunited.com>","list_archive_url":null,"date":"2023-05-12T07:17:20","name":"[4/4] MIPS: fix -gnuabi64 testsuite","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230512071720.1880195-5-yunqiang.su@cipunited.com/mbox/"},{"id":93018,"url":"https://patchwork.plctlab.org/api/1.2/patches/93018/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230512091558.83523-1-nelson@rivosinc.com/","msgid":"<20230512091558.83523-1-nelson@rivosinc.com>","list_archive_url":null,"date":"2023-05-12T09:15:58","name":"RISC-V: PR27566, consider ELF_MAXPAGESIZE/COMMONPAGESIZE for gp relaxations.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230512091558.83523-1-nelson@rivosinc.com/mbox/"},{"id":93504,"url":"https://patchwork.plctlab.org/api/1.2/patches/93504/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZF9w7hthSZx+ryOw@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-05-13T11:13:50","name":"PR28902, -T script with INSERT ordering","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZF9w7hthSZx+ryOw@squeak.grove.modra.org/mbox/"},{"id":93505,"url":"https://patchwork.plctlab.org/api/1.2/patches/93505/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZF9x6S6gsYrA1lYO@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-05-13T11:18:01","name":"PR28955 mips gas segfault","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZF9x6S6gsYrA1lYO@squeak.grove.modra.org/mbox/"},{"id":93544,"url":"https://patchwork.plctlab.org/api/1.2/patches/93544/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230513172938.2831329-1-vladimir.mezentsev@oracle.com/","msgid":"<20230513172938.2831329-1-vladimir.mezentsev@oracle.com>","list_archive_url":null,"date":"2023-05-13T17:29:38","name":"[Review,is,neded] gprofng: include a new function in the right place","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230513172938.2831329-1-vladimir.mezentsev@oracle.com/mbox/"},{"id":93971,"url":"https://patchwork.plctlab.org/api/1.2/patches/93971/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/DU0P190MB200294640D702757F760A53383789@DU0P190MB2002.EURP190.PROD.OUTLOOK.COM/","msgid":"","list_archive_url":null,"date":"2023-05-15T08:50:27","name":"Decorated symbols in import libs (BUG 30421)","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/DU0P190MB200294640D702757F760A53383789@DU0P190MB2002.EURP190.PROD.OUTLOOK.COM/mbox/"},{"id":94420,"url":"https://patchwork.plctlab.org/api/1.2/patches/94420/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230516025426.2334478-2-yunqiang.su@cipunited.com/","msgid":"<20230516025426.2334478-2-yunqiang.su@cipunited.com>","list_archive_url":null,"date":"2023-05-16T02:54:22","name":"[v2,1/5] MIPS: gas: alter 64 or 32 for mipsisa triples if march is implicit","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230516025426.2334478-2-yunqiang.su@cipunited.com/mbox/"},{"id":94421,"url":"https://patchwork.plctlab.org/api/1.2/patches/94421/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230516025426.2334478-3-yunqiang.su@cipunited.com/","msgid":"<20230516025426.2334478-3-yunqiang.su@cipunited.com>","list_archive_url":null,"date":"2023-05-16T02:54:23","name":"[v2,2/5] MIPS: default r6 if vendor is img","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230516025426.2334478-3-yunqiang.su@cipunited.com/mbox/"},{"id":94425,"url":"https://patchwork.plctlab.org/api/1.2/patches/94425/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230516025426.2334478-4-yunqiang.su@cipunited.com/","msgid":"<20230516025426.2334478-4-yunqiang.su@cipunited.com>","list_archive_url":null,"date":"2023-05-16T02:54:24","name":"[v2,3/5] MIPS: fix r6 testsuites","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230516025426.2334478-4-yunqiang.su@cipunited.com/mbox/"},{"id":94423,"url":"https://patchwork.plctlab.org/api/1.2/patches/94423/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230516025426.2334478-5-yunqiang.su@cipunited.com/","msgid":"<20230516025426.2334478-5-yunqiang.su@cipunited.com>","list_archive_url":null,"date":"2023-05-16T02:54:25","name":"[v2,4/5] MIPS: fix -gnuabi64 testsuite","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230516025426.2334478-5-yunqiang.su@cipunited.com/mbox/"},{"id":94424,"url":"https://patchwork.plctlab.org/api/1.2/patches/94424/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230516025426.2334478-6-yunqiang.su@cipunited.com/","msgid":"<20230516025426.2334478-6-yunqiang.su@cipunited.com>","list_archive_url":null,"date":"2023-05-16T02:54:26","name":"[v2,5/5] MIPS: fix some ld testcases with compiler","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230516025426.2334478-6-yunqiang.su@cipunited.com/mbox/"},{"id":94985,"url":"https://patchwork.plctlab.org/api/1.2/patches/94985/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZGQXmQ+tAKqUC/IX@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-05-16T23:54:01","name":"gcc-4.5 build fixes","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZGQXmQ+tAKqUC/IX@squeak.grove.modra.org/mbox/"},{"id":94992,"url":"https://patchwork.plctlab.org/api/1.2/patches/94992/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZGQlZ4KofqcYiJX1@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-05-17T00:52:55","name":"PR29189, dlltool delaylibs corrupt float/double arguments","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZGQlZ4KofqcYiJX1@squeak.grove.modra.org/mbox/"},{"id":94997,"url":"https://patchwork.plctlab.org/api/1.2/patches/94997/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZGQzE2Ak4W5y2Xn9@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-05-17T01:51:15","name":"PR29961, plugin-api.h: \"Could not detect architecture endianess\"","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZGQzE2Ak4W5y2Xn9@squeak.grove.modra.org/mbox/"},{"id":95160,"url":"https://patchwork.plctlab.org/api/1.2/patches/95160/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/61663a6c-a5a4-812a-1110-06e0122aabba@suse.com/","msgid":"<61663a6c-a5a4-812a-1110-06e0122aabba@suse.com>","list_archive_url":null,"date":"2023-05-17T11:00:04","name":"x86: permit all relational operators in insn operands","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/61663a6c-a5a4-812a-1110-06e0122aabba@suse.com/mbox/"},{"id":95625,"url":"https://patchwork.plctlab.org/api/1.2/patches/95625/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZGWS/0oFOMVSyf+m@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-05-18T02:52:47","name":"PR11601, Solaris assembler compatibility doesn'\''t work","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZGWS/0oFOMVSyf+m@squeak.grove.modra.org/mbox/"},{"id":95637,"url":"https://patchwork.plctlab.org/api/1.2/patches/95637/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230518034102.1747564-1-jun.zhang@intel.com/","msgid":"<20230518034102.1747564-1-jun.zhang@intel.com>","list_archive_url":null,"date":"2023-05-18T03:41:02","name":"Support Intel FRED LKGS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230518034102.1747564-1-jun.zhang@intel.com/mbox/"},{"id":95667,"url":"https://patchwork.plctlab.org/api/1.2/patches/95667/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230518062025.1535847-1-indu.bhagat@oracle.com/","msgid":"<20230518062025.1535847-1-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-05-18T06:20:24","name":"[COMMITTED] libsframe: testsuite: add new tests for sframe_find_fre API","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230518062025.1535847-1-indu.bhagat@oracle.com/mbox/"},{"id":95668,"url":"https://patchwork.plctlab.org/api/1.2/patches/95668/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230518062025.1535847-2-indu.bhagat@oracle.com/","msgid":"<20230518062025.1535847-2-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-05-18T06:20:25","name":"[COMMITTED] libsframe: testsuite: add tests for sframe_get_funcdesc_with_addr API","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230518062025.1535847-2-indu.bhagat@oracle.com/mbox/"},{"id":95674,"url":"https://patchwork.plctlab.org/api/1.2/patches/95674/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230518065950.6166-1-xuli1@eswincomputing.com/","msgid":"<20230518065950.6166-1-xuli1@eswincomputing.com>","list_archive_url":null,"date":"2023-05-18T06:59:50","name":"RISC-V: Warn in AS if vsew/vlmul/vtype is reserved.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230518065950.6166-1-xuli1@eswincomputing.com/mbox/"},{"id":95717,"url":"https://patchwork.plctlab.org/api/1.2/patches/95717/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230518085739.2195035-1-lei.wang@oss.cipunited.com/","msgid":"<20230518085739.2195035-1-lei.wang@oss.cipunited.com>","list_archive_url":null,"date":"2023-05-18T08:57:50","name":"Add GINV(+VIRT) ASE for MIPSr6","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230518085739.2195035-1-lei.wang@oss.cipunited.com/mbox/"},{"id":95721,"url":"https://patchwork.plctlab.org/api/1.2/patches/95721/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230518092246.2450-1-nelson@rivosinc.com/","msgid":"<20230518092246.2450-1-nelson@rivosinc.com>","list_archive_url":null,"date":"2023-05-18T09:22:46","name":"RISC-V: Support subtraction of .uleb128.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230518092246.2450-1-nelson@rivosinc.com/mbox/"},{"id":96167,"url":"https://patchwork.plctlab.org/api/1.2/patches/96167/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230519021448.30120-1-xuli1@eswincomputing.com/","msgid":"<20230519021448.30120-1-xuli1@eswincomputing.com>","list_archive_url":null,"date":"2023-05-19T02:14:48","name":"RISC-V: Warn in AS if vsew/vlmul/vtype is reserved.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230519021448.30120-1-xuli1@eswincomputing.com/mbox/"},{"id":96176,"url":"https://patchwork.plctlab.org/api/1.2/patches/96176/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230519034835.664-2-shihua@iscas.ac.cn/","msgid":"<20230519034835.664-2-shihua@iscas.ac.cn>","list_archive_url":null,"date":"2023-05-19T03:48:32","name":"[RFC,1/4] RISC-V : Remove checking when -march=rv64XX and -mabi=ilp32X","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230519034835.664-2-shihua@iscas.ac.cn/mbox/"},{"id":96178,"url":"https://patchwork.plctlab.org/api/1.2/patches/96178/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230519034835.664-3-shihua@iscas.ac.cn/","msgid":"<20230519034835.664-3-shihua@iscas.ac.cn>","list_archive_url":null,"date":"2023-05-19T03:48:33","name":"[RFC,2/4] RISC-V : Add support for rv64 arch using ilp32 abi","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230519034835.664-3-shihua@iscas.ac.cn/mbox/"},{"id":96177,"url":"https://patchwork.plctlab.org/api/1.2/patches/96177/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230519034835.664-4-shihua@iscas.ac.cn/","msgid":"<20230519034835.664-4-shihua@iscas.ac.cn>","list_archive_url":null,"date":"2023-05-19T03:48:34","name":"[RFC,3/4] RISC-V : Add rv64 ilp32 support in disassemble","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230519034835.664-4-shihua@iscas.ac.cn/mbox/"},{"id":96180,"url":"https://patchwork.plctlab.org/api/1.2/patches/96180/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230519034835.664-5-shihua@iscas.ac.cn/","msgid":"<20230519034835.664-5-shihua@iscas.ac.cn>","list_archive_url":null,"date":"2023-05-19T03:48:35","name":"[RFC,4/4] gdb/riscv : Add rv64 ilp32 support in gdb","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230519034835.664-5-shihua@iscas.ac.cn/mbox/"},{"id":96420,"url":"https://patchwork.plctlab.org/api/1.2/patches/96420/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/54c5d383-28bc-c61d-48b2-93b2b40a444c@suse.com/","msgid":"<54c5d383-28bc-c61d-48b2-93b2b40a444c@suse.com>","list_archive_url":null,"date":"2023-05-19T13:24:05","name":"ld: drop stray blank from ld.texi","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/54c5d383-28bc-c61d-48b2-93b2b40a444c@suse.com/mbox/"},{"id":96421,"url":"https://patchwork.plctlab.org/api/1.2/patches/96421/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b660dcfd-4a87-d6a4-a737-572b1b555f7c@suse.com/","msgid":"","list_archive_url":null,"date":"2023-05-19T13:30:57","name":"[1/2] x86: de-duplicate operand_special_chars[] wrt extra_symbol_chars[]","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b660dcfd-4a87-d6a4-a737-572b1b555f7c@suse.com/mbox/"},{"id":96422,"url":"https://patchwork.plctlab.org/api/1.2/patches/96422/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/83c328ec-3eab-767c-e65c-0d83183fd18a@suse.com/","msgid":"<83c328ec-3eab-767c-e65c-0d83183fd18a@suse.com>","list_archive_url":null,"date":"2023-05-19T13:31:28","name":"[2/2] x86: figure braces aren'\''t really part of mnemonics","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/83c328ec-3eab-767c-e65c-0d83183fd18a@suse.com/mbox/"},{"id":96432,"url":"https://patchwork.plctlab.org/api/1.2/patches/96432/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4989461e-c6fe-b102-2be1-6806e28abbb2@suse.com/","msgid":"<4989461e-c6fe-b102-2be1-6806e28abbb2@suse.com>","list_archive_url":null,"date":"2023-05-19T13:51:24","name":"[1/4] x86: split gas testsuite .exp file","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4989461e-c6fe-b102-2be1-6806e28abbb2@suse.com/mbox/"},{"id":96433,"url":"https://patchwork.plctlab.org/api/1.2/patches/96433/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/da25f556-06a6-9b64-f333-04953812fcaa@suse.com/","msgid":"","list_archive_url":null,"date":"2023-05-19T13:51:57","name":"[2/4] x86-64: conditionalize tests using --32","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/da25f556-06a6-9b64-f333-04953812fcaa@suse.com/mbox/"},{"id":96434,"url":"https://patchwork.plctlab.org/api/1.2/patches/96434/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/778a4bcd-ac39-6512-38d2-782e4eb1eea9@suse.com/","msgid":"<778a4bcd-ac39-6512-38d2-782e4eb1eea9@suse.com>","list_archive_url":null,"date":"2023-05-19T13:52:18","name":"[3/4] x86-64: improve gas diagnostic when no 32-bit target is configured","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/778a4bcd-ac39-6512-38d2-782e4eb1eea9@suse.com/mbox/"},{"id":96435,"url":"https://patchwork.plctlab.org/api/1.2/patches/96435/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d5ebeef6-ea62-b26b-bd67-ea24a21582d8@suse.com/","msgid":"","list_archive_url":null,"date":"2023-05-19T13:52:57","name":"[4/4] iamcu: suppress tests which can'\''t possibly work","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d5ebeef6-ea62-b26b-bd67-ea24a21582d8@suse.com/mbox/"},{"id":96442,"url":"https://patchwork.plctlab.org/api/1.2/patches/96442/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2274d914-c77f-37e7-5589-870a647e24a0@suse.com/","msgid":"<2274d914-c77f-37e7-5589-870a647e24a0@suse.com>","list_archive_url":null,"date":"2023-05-19T14:06:31","name":"[1/3] x86: use fixed-width type for codep and friends","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2274d914-c77f-37e7-5589-870a647e24a0@suse.com/mbox/"},{"id":96443,"url":"https://patchwork.plctlab.org/api/1.2/patches/96443/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/65393035-8006-1a66-deae-70a88ed29077@suse.com/","msgid":"<65393035-8006-1a66-deae-70a88ed29077@suse.com>","list_archive_url":null,"date":"2023-05-19T14:06:57","name":"[2/3] x86: disassembling over-long insns","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/65393035-8006-1a66-deae-70a88ed29077@suse.com/mbox/"},{"id":96444,"url":"https://patchwork.plctlab.org/api/1.2/patches/96444/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/51d38635-479f-831f-e678-3da1a1c9acae@suse.com/","msgid":"<51d38635-479f-831f-e678-3da1a1c9acae@suse.com>","list_archive_url":null,"date":"2023-05-19T14:07:25","name":"[3/3] x86: convert two pointers to (indexing) integers","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/51d38635-479f-831f-e678-3da1a1c9acae@suse.com/mbox/"},{"id":96697,"url":"https://patchwork.plctlab.org/api/1.2/patches/96697/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZGgfi5EKNdCyxFOt@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-05-20T01:16:59","name":"tic54x set_arch_mach","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZGgfi5EKNdCyxFOt@squeak.grove.modra.org/mbox/"},{"id":96698,"url":"https://patchwork.plctlab.org/api/1.2/patches/96698/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZGgf5d2KsCwesZbD@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-05-20T01:18:29","name":"coffcode.h handle_COMDAT tidy","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZGgf5d2KsCwesZbD@squeak.grove.modra.org/mbox/"},{"id":96762,"url":"https://patchwork.plctlab.org/api/1.2/patches/96762/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZGiyriwnKNKJqiJV@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-05-20T11:44:46","name":"coff-mips refhi list","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZGiyriwnKNKJqiJV@squeak.grove.modra.org/mbox/"},{"id":96951,"url":"https://patchwork.plctlab.org/api/1.2/patches/96951/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230522013441.3074776-2-mengqinggang@loongson.cn/","msgid":"<20230522013441.3074776-2-mengqinggang@loongson.cn>","list_archive_url":null,"date":"2023-05-22T01:34:36","name":"[v4,1/6] LoongArch: include: Add support for linker relaxation.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230522013441.3074776-2-mengqinggang@loongson.cn/mbox/"},{"id":96954,"url":"https://patchwork.plctlab.org/api/1.2/patches/96954/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230522013441.3074776-3-mengqinggang@loongson.cn/","msgid":"<20230522013441.3074776-3-mengqinggang@loongson.cn>","list_archive_url":null,"date":"2023-05-22T01:34:37","name":"[v4,2/6] LoongArch: bfd: Add support for linker relaxation.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230522013441.3074776-3-mengqinggang@loongson.cn/mbox/"},{"id":96952,"url":"https://patchwork.plctlab.org/api/1.2/patches/96952/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230522013441.3074776-4-mengqinggang@loongson.cn/","msgid":"<20230522013441.3074776-4-mengqinggang@loongson.cn>","list_archive_url":null,"date":"2023-05-22T01:34:38","name":"[v4,3/6] LoongArch: opcodes: Add support for linker relaxation.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230522013441.3074776-4-mengqinggang@loongson.cn/mbox/"},{"id":96955,"url":"https://patchwork.plctlab.org/api/1.2/patches/96955/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230522013441.3074776-5-mengqinggang@loongson.cn/","msgid":"<20230522013441.3074776-5-mengqinggang@loongson.cn>","list_archive_url":null,"date":"2023-05-22T01:34:39","name":"[v4,4/6] LoongArch: binutils: Add support for linker relaxation.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230522013441.3074776-5-mengqinggang@loongson.cn/mbox/"},{"id":96956,"url":"https://patchwork.plctlab.org/api/1.2/patches/96956/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230522013441.3074776-6-mengqinggang@loongson.cn/","msgid":"<20230522013441.3074776-6-mengqinggang@loongson.cn>","list_archive_url":null,"date":"2023-05-22T01:34:40","name":"[v4,5/6] LoongArch: gas: Add support for linker relaxation.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230522013441.3074776-6-mengqinggang@loongson.cn/mbox/"},{"id":96957,"url":"https://patchwork.plctlab.org/api/1.2/patches/96957/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230522013441.3074776-7-mengqinggang@loongson.cn/","msgid":"<20230522013441.3074776-7-mengqinggang@loongson.cn>","list_archive_url":null,"date":"2023-05-22T01:34:41","name":"[v4,6/6] LoongArch: ld: Add support for linker relaxation.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230522013441.3074776-7-mengqinggang@loongson.cn/mbox/"},{"id":97053,"url":"https://patchwork.plctlab.org/api/1.2/patches/97053/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230522060030.100976-1-jun.zhang@intel.com/","msgid":"<20230522060030.100976-1-jun.zhang@intel.com>","list_archive_url":null,"date":"2023-05-22T06:00:30","name":"[v2] Support Intel FRED LKGS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230522060030.100976-1-jun.zhang@intel.com/mbox/"},{"id":97056,"url":"https://patchwork.plctlab.org/api/1.2/patches/97056/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230522060726.101037-1-jun.zhang@intel.com/","msgid":"<20230522060726.101037-1-jun.zhang@intel.com>","list_archive_url":null,"date":"2023-05-22T06:07:26","name":"[v2] Support Intel FRED LKGS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230522060726.101037-1-jun.zhang@intel.com/mbox/"},{"id":97175,"url":"https://patchwork.plctlab.org/api/1.2/patches/97175/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZGsqFcGAvyznqFbB@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-05-22T08:38:45","name":"PowerPC64 report number of stub iterations","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZGsqFcGAvyznqFbB@squeak.grove.modra.org/mbox/"},{"id":97480,"url":"https://patchwork.plctlab.org/api/1.2/patches/97480/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230522142036.199490-1-jun.zhang@intel.com/","msgid":"<20230522142036.199490-1-jun.zhang@intel.com>","list_archive_url":null,"date":"2023-05-22T14:20:36","name":"[v3] Support Intel FRED LKGS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230522142036.199490-1-jun.zhang@intel.com/mbox/"},{"id":97571,"url":"https://patchwork.plctlab.org/api/1.2/patches/97571/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b0750b7e-fc76-d5ed-cd26-1a1bb6a1f2db@free.fr/","msgid":"","list_archive_url":null,"date":"2023-05-22T19:48:22","name":"[v2] pe/coff - add support for base64 encoded long section names","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b0750b7e-fc76-d5ed-cd26-1a1bb6a1f2db@free.fr/mbox/"},{"id":99104,"url":"https://patchwork.plctlab.org/api/1.2/patches/99104/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/871qj41iw5.fsf@redhat.com/","msgid":"<871qj41iw5.fsf@redhat.com>","list_archive_url":null,"date":"2023-05-25T16:21:46","name":"RFC: Objdump: Dumping PE specific headers","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/871qj41iw5.fsf@redhat.com/mbox/"},{"id":99146,"url":"https://patchwork.plctlab.org/api/1.2/patches/99146/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/87y1lcxpj0.fsf@igel.home/","msgid":"<87y1lcxpj0.fsf@igel.home>","list_archive_url":null,"date":"2023-05-25T17:57:23","name":"Remove duplicate definition","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/87y1lcxpj0.fsf@igel.home/mbox/"},{"id":99271,"url":"https://patchwork.plctlab.org/api/1.2/patches/99271/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZHAjjvo+Ldk5OyAQ@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-05-26T03:12:14","name":"PR22263 ld test, riscv fail","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZHAjjvo+Ldk5OyAQ@squeak.grove.modra.org/mbox/"},{"id":99314,"url":"https://patchwork.plctlab.org/api/1.2/patches/99314/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230526070132.4185600-1-indu.bhagat@oracle.com/","msgid":"<20230526070132.4185600-1-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-05-26T07:01:29","name":"[COMMITTED] libsframe: use uint8_t data type for FRE info related stubs","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230526070132.4185600-1-indu.bhagat@oracle.com/mbox/"},{"id":99315,"url":"https://patchwork.plctlab.org/api/1.2/patches/99315/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230526070132.4185600-2-indu.bhagat@oracle.com/","msgid":"<20230526070132.4185600-2-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-05-26T07:01:30","name":"[COMMITTED] libsframe: use const char * consistently for immutable FRE buffers","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230526070132.4185600-2-indu.bhagat@oracle.com/mbox/"},{"id":99316,"url":"https://patchwork.plctlab.org/api/1.2/patches/99316/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230526070132.4185600-3-indu.bhagat@oracle.com/","msgid":"<20230526070132.4185600-3-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-05-26T07:01:31","name":"[COMMITTED] libsframe: revisit sframe_find_fre API","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230526070132.4185600-3-indu.bhagat@oracle.com/mbox/"},{"id":99317,"url":"https://patchwork.plctlab.org/api/1.2/patches/99317/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230526070132.4185600-4-indu.bhagat@oracle.com/","msgid":"<20230526070132.4185600-4-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-05-26T07:01:32","name":"[COMMITTED] sframe/doc: minor improvements for readability","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230526070132.4185600-4-indu.bhagat@oracle.com/mbox/"},{"id":99387,"url":"https://patchwork.plctlab.org/api/1.2/patches/99387/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230526073833.3933735-2-mengqinggang@loongson.cn/","msgid":"<20230526073833.3933735-2-mengqinggang@loongson.cn>","list_archive_url":null,"date":"2023-05-26T07:38:28","name":"[v5,1/6] LoongArch: include: Add support for linker relaxation.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230526073833.3933735-2-mengqinggang@loongson.cn/mbox/"},{"id":99397,"url":"https://patchwork.plctlab.org/api/1.2/patches/99397/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230526073833.3933735-3-mengqinggang@loongson.cn/","msgid":"<20230526073833.3933735-3-mengqinggang@loongson.cn>","list_archive_url":null,"date":"2023-05-26T07:38:29","name":"[v5,2/6] LoongArch: bfd: Add support for linker relaxation.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230526073833.3933735-3-mengqinggang@loongson.cn/mbox/"},{"id":99391,"url":"https://patchwork.plctlab.org/api/1.2/patches/99391/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230526073833.3933735-4-mengqinggang@loongson.cn/","msgid":"<20230526073833.3933735-4-mengqinggang@loongson.cn>","list_archive_url":null,"date":"2023-05-26T07:38:30","name":"[v5,3/6] LoongArch: opcodes: Add support for linker relaxation.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230526073833.3933735-4-mengqinggang@loongson.cn/mbox/"},{"id":99393,"url":"https://patchwork.plctlab.org/api/1.2/patches/99393/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230526073833.3933735-5-mengqinggang@loongson.cn/","msgid":"<20230526073833.3933735-5-mengqinggang@loongson.cn>","list_archive_url":null,"date":"2023-05-26T07:38:31","name":"[v5,4/6] LoongArch: binutils: Add support for linker relaxation.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230526073833.3933735-5-mengqinggang@loongson.cn/mbox/"},{"id":99385,"url":"https://patchwork.plctlab.org/api/1.2/patches/99385/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230526073833.3933735-6-mengqinggang@loongson.cn/","msgid":"<20230526073833.3933735-6-mengqinggang@loongson.cn>","list_archive_url":null,"date":"2023-05-26T07:38:32","name":"[v5,5/6] LoongArch: gas: Add support for linker relaxation.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230526073833.3933735-6-mengqinggang@loongson.cn/mbox/"},{"id":99370,"url":"https://patchwork.plctlab.org/api/1.2/patches/99370/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230526073833.3933735-7-mengqinggang@loongson.cn/","msgid":"<20230526073833.3933735-7-mengqinggang@loongson.cn>","list_archive_url":null,"date":"2023-05-26T07:38:33","name":"[v5,6/6] LoongArch: ld: Add support for linker relaxation.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230526073833.3933735-7-mengqinggang@loongson.cn/mbox/"},{"id":99406,"url":"https://patchwork.plctlab.org/api/1.2/patches/99406/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230526082648.1503574-1-haochen.jiang@intel.com/","msgid":"<20230526082648.1503574-1-haochen.jiang@intel.com>","list_archive_url":null,"date":"2023-05-26T08:26:48","name":"x86: Add Evw to emit w suffix for several instrctions for word ptr","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230526082648.1503574-1-haochen.jiang@intel.com/mbox/"},{"id":99429,"url":"https://patchwork.plctlab.org/api/1.2/patches/99429/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230526101358.787593-1-jun.zhang@intel.com/","msgid":"<20230526101358.787593-1-jun.zhang@intel.com>","list_archive_url":null,"date":"2023-05-26T10:13:58","name":"Enable x86-64-fred-intel and x86-64-lkgs-intel test.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230526101358.787593-1-jun.zhang@intel.com/mbox/"},{"id":99644,"url":"https://patchwork.plctlab.org/api/1.2/patches/99644/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230526195407.2663991-1-vladimir.mezentsev@oracle.com/","msgid":"<20230526195407.2663991-1-vladimir.mezentsev@oracle.com>","list_archive_url":null,"date":"2023-05-26T19:54:07","name":"gprofng: 29470 The test suite should be made more flexible","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230526195407.2663991-1-vladimir.mezentsev@oracle.com/mbox/"},{"id":99645,"url":"https://patchwork.plctlab.org/api/1.2/patches/99645/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230526195518.2664720-1-vladimir.mezentsev@oracle.com/","msgid":"<20230526195518.2664720-1-vladimir.mezentsev@oracle.com>","list_archive_url":null,"date":"2023-05-26T19:55:18","name":"gprofng: Fix -Wsign-compare warning","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230526195518.2664720-1-vladimir.mezentsev@oracle.com/mbox/"},{"id":99734,"url":"https://patchwork.plctlab.org/api/1.2/patches/99734/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230527013620.65127-1-nelson@rivosinc.com/","msgid":"<20230527013620.65127-1-nelson@rivosinc.com>","list_archive_url":null,"date":"2023-05-27T01:36:20","name":"[PR,ld/22263] RISC-V: Avoid spurious R_RISCV_NONE for pr22263-1 test.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230527013620.65127-1-nelson@rivosinc.com/mbox/"},{"id":100526,"url":"https://patchwork.plctlab.org/api/1.2/patches/100526/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZHV5vB0C7IPf7sCX@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-05-30T04:21:16","name":"Regen binutils POTFILES.in","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZHV5vB0C7IPf7sCX@squeak.grove.modra.org/mbox/"},{"id":100527,"url":"https://patchwork.plctlab.org/api/1.2/patches/100527/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZHV544m6nKA2ck7Q@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-05-30T04:21:55","name":"Delete include/aout/encap.h","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZHV544m6nKA2ck7Q@squeak.grove.modra.org/mbox/"},{"id":100529,"url":"https://patchwork.plctlab.org/api/1.2/patches/100529/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZHV5/28XpXf2d9Wd@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-05-30T04:22:23","name":"Don'\''t define COFF_MAGIC","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZHV5/28XpXf2d9Wd@squeak.grove.modra.org/mbox/"},{"id":100528,"url":"https://patchwork.plctlab.org/api/1.2/patches/100528/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZHV6I0KUQQFhewlR@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-05-30T04:22:59","name":"Define IMAGE_FILE_MACHINE_ARMNT","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZHV6I0KUQQFhewlR@squeak.grove.modra.org/mbox/"},{"id":100530,"url":"https://patchwork.plctlab.org/api/1.2/patches/100530/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZHV6WtRazoQ6jCEo@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-05-30T04:23:54","name":"arm-pe objdump -P","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZHV6WtRazoQ6jCEo@squeak.grove.modra.org/mbox/"},{"id":101020,"url":"https://patchwork.plctlab.org/api/1.2/patches/101020/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230530171252.269552-2-hjl.tools@gmail.com/","msgid":"<20230530171252.269552-2-hjl.tools@gmail.com>","list_archive_url":null,"date":"2023-05-30T17:12:47","name":"[1/6] ELF: Strip section header in ELF objects","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230530171252.269552-2-hjl.tools@gmail.com/mbox/"},{"id":101025,"url":"https://patchwork.plctlab.org/api/1.2/patches/101025/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230530171252.269552-3-hjl.tools@gmail.com/","msgid":"<20230530171252.269552-3-hjl.tools@gmail.com>","list_archive_url":null,"date":"2023-05-30T17:12:48","name":"[2/6] bfd: Improve nm and objdump without section header","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230530171252.269552-3-hjl.tools@gmail.com/mbox/"},{"id":101028,"url":"https://patchwork.plctlab.org/api/1.2/patches/101028/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230530171252.269552-4-hjl.tools@gmail.com/","msgid":"<20230530171252.269552-4-hjl.tools@gmail.com>","list_archive_url":null,"date":"2023-05-30T17:12:49","name":"[3/6] ld: Add a simple test for -z nosectionheader","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230530171252.269552-4-hjl.tools@gmail.com/mbox/"},{"id":101022,"url":"https://patchwork.plctlab.org/api/1.2/patches/101022/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230530171252.269552-5-hjl.tools@gmail.com/","msgid":"<20230530171252.269552-5-hjl.tools@gmail.com>","list_archive_url":null,"date":"2023-05-30T17:12:50","name":"[4/6] binutils: Add a --strip-sections test","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230530171252.269552-5-hjl.tools@gmail.com/mbox/"},{"id":101027,"url":"https://patchwork.plctlab.org/api/1.2/patches/101027/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230530171252.269552-6-hjl.tools@gmail.com/","msgid":"<20230530171252.269552-6-hjl.tools@gmail.com>","list_archive_url":null,"date":"2023-05-30T17:12:51","name":"[5/6] ld: Add tests for -z nosectionheader and --strip-sections","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230530171252.269552-6-hjl.tools@gmail.com/mbox/"},{"id":101021,"url":"https://patchwork.plctlab.org/api/1.2/patches/101021/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230530171252.269552-7-hjl.tools@gmail.com/","msgid":"<20230530171252.269552-7-hjl.tools@gmail.com>","list_archive_url":null,"date":"2023-05-30T17:12:52","name":"[6/6] ld: Add -z nosectionheader test to bootstrap.exp","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230530171252.269552-7-hjl.tools@gmail.com/mbox/"},{"id":101296,"url":"https://patchwork.plctlab.org/api/1.2/patches/101296/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/87a5xkua9s.fsf@redhat.com/","msgid":"<87a5xkua9s.fsf@redhat.com>","list_archive_url":null,"date":"2023-05-31T09:21:03","name":"Commit: elfxx-loongarch64.c: Fix printf formatting issues.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/87a5xkua9s.fsf@redhat.com/mbox/"}],"public":true,"mbox":"https://patchwork.plctlab.org/bundle/patchwork-bot/binutils-gdb_2023-05/mbox/"},{"id":23,"url":"https://patchwork.plctlab.org/api/1.2/bundles/23/","web_url":"https://patchwork.plctlab.org/bundle/patchwork-bot/binutils-gdb_2023-06/","project":{"id":2,"url":"https://patchwork.plctlab.org/api/1.2/projects/2/","name":"binutils-gdb","link_name":"binutils-gdb","list_id":"binutils.sourceware.org","list_email":"binutils@sourceware.org","web_url":"https://github.com/wangliu-iscas/Patchwork-Bundles/blob/main/binutils-gdb.md","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"name":"binutils-gdb_2023-06","owner":{"id":3,"url":"https://patchwork.plctlab.org/api/1.2/users/3/","username":"patchwork-bot","first_name":"","last_name":"","email":"ouuuleilei@gmail.com"},"patches":[{"id":101537,"url":"https://patchwork.plctlab.org/api/1.2/patches/101537/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230531162856.48916-1-gianluca@rivosinc.com/","msgid":"<20230531162856.48916-1-gianluca@rivosinc.com>","list_archive_url":null,"date":"2023-05-31T16:28:56","name":"[RFC,v2] RISC-V: Support Zacas extension.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230531162856.48916-1-gianluca@rivosinc.com/mbox/"},{"id":101579,"url":"https://patchwork.plctlab.org/api/1.2/patches/101579/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230531200617.951996-2-hjl.tools@gmail.com/","msgid":"<20230531200617.951996-2-hjl.tools@gmail.com>","list_archive_url":null,"date":"2023-05-31T20:06:11","name":"[v2,1/7] ELF: Strip section header in ELF objects","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230531200617.951996-2-hjl.tools@gmail.com/mbox/"},{"id":101576,"url":"https://patchwork.plctlab.org/api/1.2/patches/101576/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230531200617.951996-3-hjl.tools@gmail.com/","msgid":"<20230531200617.951996-3-hjl.tools@gmail.com>","list_archive_url":null,"date":"2023-05-31T20:06:12","name":"[v2,2/7] ELF: Discard non-alloc sections without section header","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230531200617.951996-3-hjl.tools@gmail.com/mbox/"},{"id":101578,"url":"https://patchwork.plctlab.org/api/1.2/patches/101578/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230531200617.951996-4-hjl.tools@gmail.com/","msgid":"<20230531200617.951996-4-hjl.tools@gmail.com>","list_archive_url":null,"date":"2023-05-31T20:06:13","name":"[v2,3/7] bfd: Improve nm and objdump without section header","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230531200617.951996-4-hjl.tools@gmail.com/mbox/"},{"id":101572,"url":"https://patchwork.plctlab.org/api/1.2/patches/101572/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230531200617.951996-5-hjl.tools@gmail.com/","msgid":"<20230531200617.951996-5-hjl.tools@gmail.com>","list_archive_url":null,"date":"2023-05-31T20:06:14","name":"[v2,4/7] ld: Add a simple test for -z nosectionheader","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230531200617.951996-5-hjl.tools@gmail.com/mbox/"},{"id":101573,"url":"https://patchwork.plctlab.org/api/1.2/patches/101573/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230531200617.951996-6-hjl.tools@gmail.com/","msgid":"<20230531200617.951996-6-hjl.tools@gmail.com>","list_archive_url":null,"date":"2023-05-31T20:06:15","name":"[v2,5/7] binutils: Add a --strip-section-headers test","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230531200617.951996-6-hjl.tools@gmail.com/mbox/"},{"id":101580,"url":"https://patchwork.plctlab.org/api/1.2/patches/101580/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230531200617.951996-7-hjl.tools@gmail.com/","msgid":"<20230531200617.951996-7-hjl.tools@gmail.com>","list_archive_url":null,"date":"2023-05-31T20:06:16","name":"[v2,6/7] ld: Add tests for -z nosectionheader and --strip-section-headers","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230531200617.951996-7-hjl.tools@gmail.com/mbox/"},{"id":101574,"url":"https://patchwork.plctlab.org/api/1.2/patches/101574/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230531200617.951996-8-hjl.tools@gmail.com/","msgid":"<20230531200617.951996-8-hjl.tools@gmail.com>","list_archive_url":null,"date":"2023-05-31T20:06:17","name":"[v2,7/7] ld: Add -z nosectionheader test to bootstrap.exp","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230531200617.951996-8-hjl.tools@gmail.com/mbox/"},{"id":101625,"url":"https://patchwork.plctlab.org/api/1.2/patches/101625/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZHfmQsTZbxX1yUIq@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-06-01T00:28:50","name":"Remove BFD_FAIL in cpu-sh.c","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZHfmQsTZbxX1yUIq@squeak.grove.modra.org/mbox/"},{"id":101626,"url":"https://patchwork.plctlab.org/api/1.2/patches/101626/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZHfmjU0Ft5Jrcj3c@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-06-01T00:30:05","name":"section_by_target_index memory leak","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZHfmjU0Ft5Jrcj3c@squeak.grove.modra.org/mbox/"},{"id":101627,"url":"https://patchwork.plctlab.org/api/1.2/patches/101627/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZHfm5/WNQaE4NSYR@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-06-01T00:31:35","name":"bfd_close and target free_cached_memory","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZHfm5/WNQaE4NSYR@squeak.grove.modra.org/mbox/"},{"id":101628,"url":"https://patchwork.plctlab.org/api/1.2/patches/101628/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZHfnQckZnox2uLOu@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-06-01T00:33:05","name":"Harden PowerPC64 OPD handling against fuzzers","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZHfnQckZnox2uLOu@squeak.grove.modra.org/mbox/"},{"id":101754,"url":"https://patchwork.plctlab.org/api/1.2/patches/101754/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230601061610.2614564-1-indu.bhagat@oracle.com/","msgid":"<20230601061610.2614564-1-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-06-01T06:16:10","name":"[COMMITTED] libsframe: minor fixups in flip_fre related functions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230601061610.2614564-1-indu.bhagat@oracle.com/mbox/"},{"id":102114,"url":"https://patchwork.plctlab.org/api/1.2/patches/102114/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230601173312.3176329-1-indu.bhagat@oracle.com/","msgid":"<20230601173312.3176329-1-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-06-01T17:33:12","name":"[COMMITTED] libsframe: avoid using magic number","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230601173312.3176329-1-indu.bhagat@oracle.com/mbox/"},{"id":102244,"url":"https://patchwork.plctlab.org/api/1.2/patches/102244/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZHkxDSYR0EtVi6dY@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-06-02T00:00:13","name":"Minor objcopy optimisation for copy_relocations_in_section","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZHkxDSYR0EtVi6dY@squeak.grove.modra.org/mbox/"},{"id":102245,"url":"https://patchwork.plctlab.org/api/1.2/patches/102245/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZHkxOZ+7zNpFcAUv@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-06-02T00:00:57","name":"loongarch readelf support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZHkxOZ+7zNpFcAUv@squeak.grove.modra.org/mbox/"},{"id":102407,"url":"https://patchwork.plctlab.org/api/1.2/patches/102407/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230602092410.2841184-1-mengqinggang@loongson.cn/","msgid":"<20230602092410.2841184-1-mengqinggang@loongson.cn>","list_archive_url":null,"date":"2023-06-02T09:24:10","name":"LoongArch: gas: Relocations simplification when -mno-relax","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230602092410.2841184-1-mengqinggang@loongson.cn/mbox/"},{"id":102680,"url":"https://patchwork.plctlab.org/api/1.2/patches/102680/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230602192527.1532280-1-hjl.tools@gmail.com/","msgid":"<20230602192527.1532280-1-hjl.tools@gmail.com>","list_archive_url":null,"date":"2023-06-02T19:25:27","name":"ELF: Don'\''t warn an empty PT_LOAD with the program headers","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230602192527.1532280-1-hjl.tools@gmail.com/mbox/"},{"id":102961,"url":"https://patchwork.plctlab.org/api/1.2/patches/102961/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/221f70cf-5cff-6053-7499-499d4202e90b@debian.org/","msgid":"<221f70cf-5cff-6053-7499-499d4202e90b@debian.org>","list_archive_url":null,"date":"2023-06-04T06:44:45","name":"ignore lto-wrapper warnings for lto builds","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/221f70cf-5cff-6053-7499-499d4202e90b@debian.org/mbox/"},{"id":103136,"url":"https://patchwork.plctlab.org/api/1.2/patches/103136/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZH2Mwib11IEH7JDu@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-06-05T07:20:34","name":"Yet another ecoff fuzzed object fix","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZH2Mwib11IEH7JDu@squeak.grove.modra.org/mbox/"},{"id":103138,"url":"https://patchwork.plctlab.org/api/1.2/patches/103138/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZH2NDLgf5atBfB7S@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-06-05T07:21:48","name":"bfd_error_on_input messages","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZH2NDLgf5atBfB7S@squeak.grove.modra.org/mbox/"},{"id":103197,"url":"https://patchwork.plctlab.org/api/1.2/patches/103197/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230605102225.3566958-1-yunqiang.su@cipunited.com/","msgid":"<20230605102225.3566958-1-yunqiang.su@cipunited.com>","list_archive_url":null,"date":"2023-06-05T10:22:24","name":"[1/2] MIPS: Add n32 VECs to non-vendor elf targets","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230605102225.3566958-1-yunqiang.su@cipunited.com/mbox/"},{"id":103198,"url":"https://patchwork.plctlab.org/api/1.2/patches/103198/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230605102225.3566958-2-yunqiang.su@cipunited.com/","msgid":"<20230605102225.3566958-2-yunqiang.su@cipunited.com>","list_archive_url":null,"date":"2023-06-05T10:22:25","name":"[2/2] MIPS: fix Irix gas testcases","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230605102225.3566958-2-yunqiang.su@cipunited.com/mbox/"},{"id":103356,"url":"https://patchwork.plctlab.org/api/1.2/patches/103356/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230605153222.1728119-2-hjl.tools@gmail.com/","msgid":"<20230605153222.1728119-2-hjl.tools@gmail.com>","list_archive_url":null,"date":"2023-06-05T15:32:16","name":"[v3,1/7] ELF: Strip section header in ELF objects","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230605153222.1728119-2-hjl.tools@gmail.com/mbox/"},{"id":103349,"url":"https://patchwork.plctlab.org/api/1.2/patches/103349/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230605153222.1728119-3-hjl.tools@gmail.com/","msgid":"<20230605153222.1728119-3-hjl.tools@gmail.com>","list_archive_url":null,"date":"2023-06-05T15:32:17","name":"[v3,2/7] ELF: Discard non-alloc sections without section header","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230605153222.1728119-3-hjl.tools@gmail.com/mbox/"},{"id":103354,"url":"https://patchwork.plctlab.org/api/1.2/patches/103354/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230605153222.1728119-4-hjl.tools@gmail.com/","msgid":"<20230605153222.1728119-4-hjl.tools@gmail.com>","list_archive_url":null,"date":"2023-06-05T15:32:18","name":"[v3,3/7] bfd: Improve nm and objdump without section header","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230605153222.1728119-4-hjl.tools@gmail.com/mbox/"},{"id":103351,"url":"https://patchwork.plctlab.org/api/1.2/patches/103351/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230605153222.1728119-5-hjl.tools@gmail.com/","msgid":"<20230605153222.1728119-5-hjl.tools@gmail.com>","list_archive_url":null,"date":"2023-06-05T15:32:19","name":"[v3,4/7] ld: Add a simple test for -z nosectionheader","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230605153222.1728119-5-hjl.tools@gmail.com/mbox/"},{"id":103353,"url":"https://patchwork.plctlab.org/api/1.2/patches/103353/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230605153222.1728119-6-hjl.tools@gmail.com/","msgid":"<20230605153222.1728119-6-hjl.tools@gmail.com>","list_archive_url":null,"date":"2023-06-05T15:32:20","name":"[v3,5/7] binutils: Add a --strip-section-headers test","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230605153222.1728119-6-hjl.tools@gmail.com/mbox/"},{"id":103355,"url":"https://patchwork.plctlab.org/api/1.2/patches/103355/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230605153222.1728119-7-hjl.tools@gmail.com/","msgid":"<20230605153222.1728119-7-hjl.tools@gmail.com>","list_archive_url":null,"date":"2023-06-05T15:32:21","name":"[v3,6/7] ld: Add tests for -z nosectionheader and --strip-section-headers","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230605153222.1728119-7-hjl.tools@gmail.com/mbox/"},{"id":103350,"url":"https://patchwork.plctlab.org/api/1.2/patches/103350/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230605153222.1728119-8-hjl.tools@gmail.com/","msgid":"<20230605153222.1728119-8-hjl.tools@gmail.com>","list_archive_url":null,"date":"2023-06-05T15:32:22","name":"[v3,7/7] ld: Add -z nosectionheader test to bootstrap.exp","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230605153222.1728119-8-hjl.tools@gmail.com/mbox/"},{"id":103383,"url":"https://patchwork.plctlab.org/api/1.2/patches/103383/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230605163327.1864428-1-hjl.tools@gmail.com/","msgid":"<20230605163327.1864428-1-hjl.tools@gmail.com>","list_archive_url":null,"date":"2023-06-05T16:33:27","name":"ELF: Add \"#pass\" to ld-elf/pr30508.d","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230605163327.1864428-1-hjl.tools@gmail.com/mbox/"},{"id":103509,"url":"https://patchwork.plctlab.org/api/1.2/patches/103509/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230605214658.693003-1-indu.bhagat@oracle.com/","msgid":"<20230605214658.693003-1-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-06-05T21:46:58","name":"[COMMITTED] libsframe: avoid unnecessary type casts","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230605214658.693003-1-indu.bhagat@oracle.com/mbox/"},{"id":103542,"url":"https://patchwork.plctlab.org/api/1.2/patches/103542/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230606040315.4000351-1-yunqiang.su@cipunited.com/","msgid":"<20230606040315.4000351-1-yunqiang.su@cipunited.com>","list_archive_url":null,"date":"2023-06-06T04:03:13","name":"[v2,1/3] MIPS: disable fix-rm7000-2 and llpscp-64 if not has_newabi","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230606040315.4000351-1-yunqiang.su@cipunited.com/mbox/"},{"id":103543,"url":"https://patchwork.plctlab.org/api/1.2/patches/103543/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230606040315.4000351-2-yunqiang.su@cipunited.com/","msgid":"<20230606040315.4000351-2-yunqiang.su@cipunited.com>","list_archive_url":null,"date":"2023-06-06T04:03:14","name":"[v2,2/3] MIPS: Ignore the symbol index for comdat-reloc-r6.d","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230606040315.4000351-2-yunqiang.su@cipunited.com/mbox/"},{"id":103544,"url":"https://patchwork.plctlab.org/api/1.2/patches/103544/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230606040315.4000351-3-yunqiang.su@cipunited.com/","msgid":"<20230606040315.4000351-3-yunqiang.su@cipunited.com>","list_archive_url":null,"date":"2023-06-06T04:03:15","name":"[v2,3/3] MIPS: Fix Irix gas testcases","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230606040315.4000351-3-yunqiang.su@cipunited.com/mbox/"},{"id":103614,"url":"https://patchwork.plctlab.org/api/1.2/patches/103614/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230606074856.3463253-1-lei.wang@oss.cipunited.com/","msgid":"<20230606074856.3463253-1-lei.wang@oss.cipunited.com>","list_archive_url":null,"date":"2023-06-06T07:49:13","name":"[v2] Add GINV(+VIRT) ASE for MIPSr6","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230606074856.3463253-1-lei.wang@oss.cipunited.com/mbox/"},{"id":104005,"url":"https://patchwork.plctlab.org/api/1.2/patches/104005/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230606175846.399377-2-hjl.tools@gmail.com/","msgid":"<20230606175846.399377-2-hjl.tools@gmail.com>","list_archive_url":null,"date":"2023-06-06T17:58:40","name":"[v4,1/7] ELF: Strip section header in ELF objects","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230606175846.399377-2-hjl.tools@gmail.com/mbox/"},{"id":104004,"url":"https://patchwork.plctlab.org/api/1.2/patches/104004/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230606175846.399377-3-hjl.tools@gmail.com/","msgid":"<20230606175846.399377-3-hjl.tools@gmail.com>","list_archive_url":null,"date":"2023-06-06T17:58:41","name":"[v4,2/7] ELF: Discard non-alloc sections without section header","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230606175846.399377-3-hjl.tools@gmail.com/mbox/"},{"id":104009,"url":"https://patchwork.plctlab.org/api/1.2/patches/104009/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230606175846.399377-4-hjl.tools@gmail.com/","msgid":"<20230606175846.399377-4-hjl.tools@gmail.com>","list_archive_url":null,"date":"2023-06-06T17:58:42","name":"[v4,3/7] bfd: Improve nm and objdump without section header","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230606175846.399377-4-hjl.tools@gmail.com/mbox/"},{"id":104008,"url":"https://patchwork.plctlab.org/api/1.2/patches/104008/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230606175846.399377-5-hjl.tools@gmail.com/","msgid":"<20230606175846.399377-5-hjl.tools@gmail.com>","list_archive_url":null,"date":"2023-06-06T17:58:43","name":"[v4,4/7] ld: Add simple tests for -z nosectionheader","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230606175846.399377-5-hjl.tools@gmail.com/mbox/"},{"id":104006,"url":"https://patchwork.plctlab.org/api/1.2/patches/104006/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230606175846.399377-6-hjl.tools@gmail.com/","msgid":"<20230606175846.399377-6-hjl.tools@gmail.com>","list_archive_url":null,"date":"2023-06-06T17:58:44","name":"[v4,5/7] binutils: Add a --strip-section-headers test","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230606175846.399377-6-hjl.tools@gmail.com/mbox/"},{"id":104010,"url":"https://patchwork.plctlab.org/api/1.2/patches/104010/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230606175846.399377-7-hjl.tools@gmail.com/","msgid":"<20230606175846.399377-7-hjl.tools@gmail.com>","list_archive_url":null,"date":"2023-06-06T17:58:45","name":"[v4,6/7] ld: Add tests for -z nosectionheader and --strip-section-headers","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230606175846.399377-7-hjl.tools@gmail.com/mbox/"},{"id":104007,"url":"https://patchwork.plctlab.org/api/1.2/patches/104007/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230606175846.399377-8-hjl.tools@gmail.com/","msgid":"<20230606175846.399377-8-hjl.tools@gmail.com>","list_archive_url":null,"date":"2023-06-06T17:58:46","name":"[v4,7/7] ld: Add -z nosectionheader test to bootstrap.exp","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230606175846.399377-8-hjl.tools@gmail.com/mbox/"},{"id":104157,"url":"https://patchwork.plctlab.org/api/1.2/patches/104157/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230607001219.1262641-1-indu.bhagat@oracle.com/","msgid":"<20230607001219.1262641-1-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-06-07T00:12:19","name":"[COMMITTED] libsframe: fix cosmetic issues and typos","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230607001219.1262641-1-indu.bhagat@oracle.com/mbox/"},{"id":104187,"url":"https://patchwork.plctlab.org/api/1.2/patches/104187/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZH/kqvEBzDihSIXm@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-06-07T02:00:10","name":"objcopy memory leaks after errors","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZH/kqvEBzDihSIXm@squeak.grove.modra.org/mbox/"},{"id":104188,"url":"https://patchwork.plctlab.org/api/1.2/patches/104188/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZH/kzy91Kw/7oe/D@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-06-07T02:00:47","name":"bfd/elf.c strtab memory leak","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZH/kzy91Kw/7oe/D@squeak.grove.modra.org/mbox/"},{"id":104189,"url":"https://patchwork.plctlab.org/api/1.2/patches/104189/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZH/lDst5YNSnH53k@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-06-07T02:01:50","name":"Memory leaks in bfd/vms-lib.c","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZH/lDst5YNSnH53k@squeak.grove.modra.org/mbox/"},{"id":104228,"url":"https://patchwork.plctlab.org/api/1.2/patches/104228/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZIANNwcg5+tkbCiv@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-06-07T04:53:11","name":"_bfd_free_cached_info","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZIANNwcg5+tkbCiv@squeak.grove.modra.org/mbox/"},{"id":104370,"url":"https://patchwork.plctlab.org/api/1.2/patches/104370/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZIBPFJst5wp+jM/O@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-06-07T09:34:12","name":"ld-elf/eh5 remove xfail hppa64","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZIBPFJst5wp+jM/O@squeak.grove.modra.org/mbox/"},{"id":104777,"url":"https://patchwork.plctlab.org/api/1.2/patches/104777/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230607235757.4174552-1-indu.bhagat@oracle.com/","msgid":"<20230607235757.4174552-1-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-06-07T23:57:57","name":"[COMMITTED] libsframe: reuse static function sframe_decoder_get_funcdesc_at_index","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230607235757.4174552-1-indu.bhagat@oracle.com/mbox/"},{"id":104818,"url":"https://patchwork.plctlab.org/api/1.2/patches/104818/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230608044935.4183325-2-indu.bhagat@oracle.com/","msgid":"<20230608044935.4183325-2-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-06-08T04:49:34","name":"[1/2] libsframe: update the semantics of sframe_fre_get_ra_offset","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230608044935.4183325-2-indu.bhagat@oracle.com/mbox/"},{"id":104819,"url":"https://patchwork.plctlab.org/api/1.2/patches/104819/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230608044935.4183325-3-indu.bhagat@oracle.com/","msgid":"<20230608044935.4183325-3-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-06-08T04:49:35","name":"[2/2] libsframe: update the semantics of sframe_fre_get_fp_offset","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230608044935.4183325-3-indu.bhagat@oracle.com/mbox/"},{"id":105015,"url":"https://patchwork.plctlab.org/api/1.2/patches/105015/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230608155214.32435-1-palmer@rivosinc.com/","msgid":"<20230608155214.32435-1-palmer@rivosinc.com>","list_archive_url":null,"date":"2023-06-08T15:52:14","name":"RISC-V: Move __global_pointer$ to .sdata","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230608155214.32435-1-palmer@rivosinc.com/mbox/"},{"id":105186,"url":"https://patchwork.plctlab.org/api/1.2/patches/105186/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230609004717.30486-1-nelson@rivosinc.com/","msgid":"<20230609004717.30486-1-nelson@rivosinc.com>","list_archive_url":null,"date":"2023-06-09T00:47:17","name":"RISC-V: PR29823, defined the missing elf_backend_obj_attrs_handle_unknown.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230609004717.30486-1-nelson@rivosinc.com/mbox/"},{"id":105286,"url":"https://patchwork.plctlab.org/api/1.2/patches/105286/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZILCF8nLyVb4FoJ4@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-06-09T06:09:27","name":"ecoff find_nearest_line and final link leaks","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZILCF8nLyVb4FoJ4@squeak.grove.modra.org/mbox/"},{"id":105287,"url":"https://patchwork.plctlab.org/api/1.2/patches/105287/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZILCNa0O8HoJZZAo@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-06-09T06:09:57","name":"readelf/objdump remember_state memory leaks","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZILCNa0O8HoJZZAo@squeak.grove.modra.org/mbox/"},{"id":105603,"url":"https://patchwork.plctlab.org/api/1.2/patches/105603/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ad4cdc08-a78e-49ee-d650-bd5a8ebc164b@suse.com/","msgid":"","list_archive_url":null,"date":"2023-06-09T12:30:26","name":"x86: shrink Masking insn attribute to a single bit (boolean)","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ad4cdc08-a78e-49ee-d650-bd5a8ebc164b@suse.com/mbox/"},{"id":105785,"url":"https://patchwork.plctlab.org/api/1.2/patches/105785/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230609192822.2471957-1-indu.bhagat@oracle.com/","msgid":"<20230609192822.2471957-1-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-06-09T19:28:21","name":"[COMMITTED] libsframe: fix sframe_find_fre for pltN entries","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230609192822.2471957-1-indu.bhagat@oracle.com/mbox/"},{"id":105786,"url":"https://patchwork.plctlab.org/api/1.2/patches/105786/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230609192822.2471957-2-indu.bhagat@oracle.com/","msgid":"<20230609192822.2471957-2-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-06-09T19:28:22","name":"[COMMITTED] libsframe: testsuite: add sframe_find_fre tests for pltN entries","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230609192822.2471957-2-indu.bhagat@oracle.com/mbox/"},{"id":106323,"url":"https://patchwork.plctlab.org/api/1.2/patches/106323/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230612083649.907511-1-chenfeiyang@loongson.cn/","msgid":"<20230612083649.907511-1-chenfeiyang@loongson.cn>","list_archive_url":null,"date":"2023-06-12T08:36:49","name":"LoongArch: Add fcsr register names support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230612083649.907511-1-chenfeiyang@loongson.cn/mbox/"},{"id":107171,"url":"https://patchwork.plctlab.org/api/1.2/patches/107171/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230613080712.1651120-1-mengqinggang@loongson.cn/","msgid":"<20230613080712.1651120-1-mengqinggang@loongson.cn>","list_archive_url":null,"date":"2023-06-13T08:07:12","name":"LoongArch: Fix ld \"undefined reference\" error with --enable-shared","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230613080712.1651120-1-mengqinggang@loongson.cn/mbox/"},{"id":107373,"url":"https://patchwork.plctlab.org/api/1.2/patches/107373/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230613132342.783814-2-jiawei@iscas.ac.cn/","msgid":"<20230613132342.783814-2-jiawei@iscas.ac.cn>","list_archive_url":null,"date":"2023-06-13T13:23:39","name":"[1/4] RISC-V: Minimal support of ZC extensions.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230613132342.783814-2-jiawei@iscas.ac.cn/mbox/"},{"id":107375,"url":"https://patchwork.plctlab.org/api/1.2/patches/107375/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230613132342.783814-3-jiawei@iscas.ac.cn/","msgid":"<20230613132342.783814-3-jiawei@iscas.ac.cn>","list_archive_url":null,"date":"2023-06-13T13:23:40","name":"[2/4] RISC-V: Add Zca extension testcases.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230613132342.783814-3-jiawei@iscas.ac.cn/mbox/"},{"id":107377,"url":"https://patchwork.plctlab.org/api/1.2/patches/107377/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230613132342.783814-4-jiawei@iscas.ac.cn/","msgid":"<20230613132342.783814-4-jiawei@iscas.ac.cn>","list_archive_url":null,"date":"2023-06-13T13:23:41","name":"[3/4] RISC-V: Add Zcf extension testcases.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230613132342.783814-4-jiawei@iscas.ac.cn/mbox/"},{"id":107378,"url":"https://patchwork.plctlab.org/api/1.2/patches/107378/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230613132342.783814-5-jiawei@iscas.ac.cn/","msgid":"<20230613132342.783814-5-jiawei@iscas.ac.cn>","list_archive_url":null,"date":"2023-06-13T13:23:42","name":"[4/4] RISC-V: Add Zcd extension testcases.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230613132342.783814-5-jiawei@iscas.ac.cn/mbox/"},{"id":107381,"url":"https://patchwork.plctlab.org/api/1.2/patches/107381/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230613133851.786238-1-jiawei@iscas.ac.cn/","msgid":"<20230613133851.786238-1-jiawei@iscas.ac.cn>","list_archive_url":null,"date":"2023-06-13T13:38:50","name":"[1/2] RISC-V: Add Zcb extension supports.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230613133851.786238-1-jiawei@iscas.ac.cn/mbox/"},{"id":107380,"url":"https://patchwork.plctlab.org/api/1.2/patches/107380/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230613133851.786238-2-jiawei@iscas.ac.cn/","msgid":"<20230613133851.786238-2-jiawei@iscas.ac.cn>","list_archive_url":null,"date":"2023-06-13T13:38:51","name":"[2/2] RISC-V: Add Zcb extension testcases.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230613133851.786238-2-jiawei@iscas.ac.cn/mbox/"},{"id":107632,"url":"https://patchwork.plctlab.org/api/1.2/patches/107632/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230614000148.10989-2-david@davidgf.es/","msgid":"<20230614000148.10989-2-david@davidgf.es>","list_archive_url":null,"date":"2023-06-14T00:01:46","name":"[v2,1/3] Add MIPS Allegrex CPU as a MIPS2-based CPU","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230614000148.10989-2-david@davidgf.es/mbox/"},{"id":107631,"url":"https://patchwork.plctlab.org/api/1.2/patches/107631/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230614000148.10989-3-david@davidgf.es/","msgid":"<20230614000148.10989-3-david@davidgf.es>","list_archive_url":null,"date":"2023-06-14T00:01:47","name":"[v2,2/3] Add rotation instructions to MIPS Allegrex CPU","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230614000148.10989-3-david@davidgf.es/mbox/"},{"id":107630,"url":"https://patchwork.plctlab.org/api/1.2/patches/107630/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230614000148.10989-4-david@davidgf.es/","msgid":"<20230614000148.10989-4-david@davidgf.es>","list_archive_url":null,"date":"2023-06-14T00:01:48","name":"[v2,3/3] Add additional missing Allegrex CPU instructions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230614000148.10989-4-david@davidgf.es/mbox/"},{"id":107698,"url":"https://patchwork.plctlab.org/api/1.2/patches/107698/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZIlIv23B00XAlvGU@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-06-14T04:57:35","name":"asprintf memory leaks","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZIlIv23B00XAlvGU@squeak.grove.modra.org/mbox/"},{"id":107914,"url":"https://patchwork.plctlab.org/api/1.2/patches/107914/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/mvma5x245vb.fsf@suse.de/","msgid":"","list_archive_url":null,"date":"2023-06-14T11:53:44","name":"riscv: Use run-time endianess for floating point literals","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/mvma5x245vb.fsf@suse.de/mbox/"},{"id":107999,"url":"https://patchwork.plctlab.org/api/1.2/patches/107999/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/87ttva3xik.fsf@redhat.com/","msgid":"<87ttva3xik.fsf@redhat.com>","list_archive_url":null,"date":"2023-06-14T14:54:11","name":"commit: Add expected failures for some bfin linker tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/87ttva3xik.fsf@redhat.com/mbox/"},{"id":108238,"url":"https://patchwork.plctlab.org/api/1.2/patches/108238/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZIp6D6Of0QqK1XT0@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-06-15T02:40:15","name":"vms write_archive memory leaks","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZIp6D6Of0QqK1XT0@squeak.grove.modra.org/mbox/"},{"id":108244,"url":"https://patchwork.plctlab.org/api/1.2/patches/108244/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.DEB.2.21.2306150402280.64925@angie.orcam.me.uk/","msgid":"","list_archive_url":null,"date":"2023-06-15T03:50:33","name":"[committed] GAS/doc: Correct Tag_GNU_MIPS_ABI_MSA attribute description","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.DEB.2.21.2306150402280.64925@angie.orcam.me.uk/mbox/"},{"id":108247,"url":"https://patchwork.plctlab.org/api/1.2/patches/108247/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.DEB.2.21.2306150403370.64925@angie.orcam.me.uk/","msgid":"","list_archive_url":null,"date":"2023-06-15T03:51:53","name":"[committed] MIPS/GAS/testsuite: Fix `-modd-spreg'\''/`-mno-odd-spreg'\'' test invocations","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.DEB.2.21.2306150403370.64925@angie.orcam.me.uk/mbox/"},{"id":108432,"url":"https://patchwork.plctlab.org/api/1.2/patches/108432/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/AM6PR03MB49843D0F7C0438ADEB19172E985BA@AM6PR03MB4984.eurprd03.prod.outlook.com/","msgid":"","list_archive_url":null,"date":"2023-06-15T11:09:26","name":"[0/2] riscv: Fix gas when encoding BE floats/doubles","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/AM6PR03MB49843D0F7C0438ADEB19172E985BA@AM6PR03MB4984.eurprd03.prod.outlook.com/mbox/"},{"id":108551,"url":"https://patchwork.plctlab.org/api/1.2/patches/108551/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.DEB.2.21.2306151520460.64925@angie.orcam.me.uk/","msgid":"","list_archive_url":null,"date":"2023-06-15T14:24:56","name":"[committed] binutils/NEWS: Mention Sony Allegrex MIPS CPU support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.DEB.2.21.2306151520460.64925@angie.orcam.me.uk/mbox/"},{"id":108800,"url":"https://patchwork.plctlab.org/api/1.2/patches/108800/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230616031610.3982906-1-chenfeiyang@loongson.cn/","msgid":"<20230616031610.3982906-1-chenfeiyang@loongson.cn>","list_archive_url":null,"date":"2023-06-16T03:16:10","name":"[v2] LoongArch: Support referring to FCSRs as $fcsrX","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230616031610.3982906-1-chenfeiyang@loongson.cn/mbox/"},{"id":108836,"url":"https://patchwork.plctlab.org/api/1.2/patches/108836/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230616062504.1713904-2-yunqiang.su@cipunited.com/","msgid":"<20230616062504.1713904-2-yunqiang.su@cipunited.com>","list_archive_url":null,"date":"2023-06-16T06:24:54","name":"[v3,1/7] MIPS: Gas: alter 64 or 32 for mipsisa triples if march is implicit","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230616062504.1713904-2-yunqiang.su@cipunited.com/mbox/"},{"id":108840,"url":"https://patchwork.plctlab.org/api/1.2/patches/108840/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230616062504.1713904-3-yunqiang.su@cipunited.com/","msgid":"<20230616062504.1713904-3-yunqiang.su@cipunited.com>","list_archive_url":null,"date":"2023-06-16T06:24:55","name":"[v3,2/7] MIPS: default r6 if vendor is img","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230616062504.1713904-3-yunqiang.su@cipunited.com/mbox/"},{"id":108842,"url":"https://patchwork.plctlab.org/api/1.2/patches/108842/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230616062504.1713904-4-yunqiang.su@cipunited.com/","msgid":"<20230616062504.1713904-4-yunqiang.su@cipunited.com>","list_archive_url":null,"date":"2023-06-16T06:24:56","name":"[v3,2/7] MIPS: Set r6 as default arch if vendor is img","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230616062504.1713904-4-yunqiang.su@cipunited.com/mbox/"},{"id":108847,"url":"https://patchwork.plctlab.org/api/1.2/patches/108847/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230616062504.1713904-5-yunqiang.su@cipunited.com/","msgid":"<20230616062504.1713904-5-yunqiang.su@cipunited.com>","list_archive_url":null,"date":"2023-06-16T06:24:57","name":"[v3,3/7] MIPS: fix r6 testsuites","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230616062504.1713904-5-yunqiang.su@cipunited.com/mbox/"},{"id":108843,"url":"https://patchwork.plctlab.org/api/1.2/patches/108843/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230616062504.1713904-6-yunqiang.su@cipunited.com/","msgid":"<20230616062504.1713904-6-yunqiang.su@cipunited.com>","list_archive_url":null,"date":"2023-06-16T06:24:58","name":"[v3,3/7] MIPS: Fix r6 testsuites","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230616062504.1713904-6-yunqiang.su@cipunited.com/mbox/"},{"id":108851,"url":"https://patchwork.plctlab.org/api/1.2/patches/108851/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230616062504.1713904-7-yunqiang.su@cipunited.com/","msgid":"<20230616062504.1713904-7-yunqiang.su@cipunited.com>","list_archive_url":null,"date":"2023-06-16T06:24:59","name":"[v3,4/7] MIPS: fix -gnuabi64 testsuite","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230616062504.1713904-7-yunqiang.su@cipunited.com/mbox/"},{"id":108844,"url":"https://patchwork.plctlab.org/api/1.2/patches/108844/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230616062504.1713904-8-yunqiang.su@cipunited.com/","msgid":"<20230616062504.1713904-8-yunqiang.su@cipunited.com>","list_archive_url":null,"date":"2023-06-16T06:25:00","name":"[v3,4/7] MIPS: Fix -gnuabi64 testsuite","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230616062504.1713904-8-yunqiang.su@cipunited.com/mbox/"},{"id":108848,"url":"https://patchwork.plctlab.org/api/1.2/patches/108848/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230616062504.1713904-9-yunqiang.su@cipunited.com/","msgid":"<20230616062504.1713904-9-yunqiang.su@cipunited.com>","list_archive_url":null,"date":"2023-06-16T06:25:01","name":"[v3,5/7] MIPS: fix some ld testcases with compiler","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230616062504.1713904-9-yunqiang.su@cipunited.com/mbox/"},{"id":108846,"url":"https://patchwork.plctlab.org/api/1.2/patches/108846/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230616062504.1713904-10-yunqiang.su@cipunited.com/","msgid":"<20230616062504.1713904-10-yunqiang.su@cipunited.com>","list_archive_url":null,"date":"2023-06-16T06:25:02","name":"[v3,5/7] MIPS: Fix some ld testcases with compiler","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230616062504.1713904-10-yunqiang.su@cipunited.com/mbox/"},{"id":108857,"url":"https://patchwork.plctlab.org/api/1.2/patches/108857/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230616062504.1713904-11-yunqiang.su@cipunited.com/","msgid":"<20230616062504.1713904-11-yunqiang.su@cipunited.com>","list_archive_url":null,"date":"2023-06-16T06:25:03","name":"[v3,6/7] MIPS: disable fix-rm7000-2 and llpscp-64 if not has_newabi","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230616062504.1713904-11-yunqiang.su@cipunited.com/mbox/"},{"id":108863,"url":"https://patchwork.plctlab.org/api/1.2/patches/108863/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230616062504.1713904-12-yunqiang.su@cipunited.com/","msgid":"<20230616062504.1713904-12-yunqiang.su@cipunited.com>","list_archive_url":null,"date":"2023-06-16T06:25:04","name":"[v3,7/7] MIPS: Fix Irix gas testcases","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230616062504.1713904-12-yunqiang.su@cipunited.com/mbox/"},{"id":108869,"url":"https://patchwork.plctlab.org/api/1.2/patches/108869/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230616063412.1715024-2-yunqiang.su@cipunited.com/","msgid":"<20230616063412.1715024-2-yunqiang.su@cipunited.com>","list_archive_url":null,"date":"2023-06-16T06:34:06","name":"[v4,1/7] MIPS: Gas: alter 64 or 32 for mipsisa triples if march is implicit","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230616063412.1715024-2-yunqiang.su@cipunited.com/mbox/"},{"id":108870,"url":"https://patchwork.plctlab.org/api/1.2/patches/108870/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230616063412.1715024-3-yunqiang.su@cipunited.com/","msgid":"<20230616063412.1715024-3-yunqiang.su@cipunited.com>","list_archive_url":null,"date":"2023-06-16T06:34:07","name":"[v4,2/7] MIPS: Set r6 as default arch if vendor is img","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230616063412.1715024-3-yunqiang.su@cipunited.com/mbox/"},{"id":108878,"url":"https://patchwork.plctlab.org/api/1.2/patches/108878/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230616063412.1715024-4-yunqiang.su@cipunited.com/","msgid":"<20230616063412.1715024-4-yunqiang.su@cipunited.com>","list_archive_url":null,"date":"2023-06-16T06:34:08","name":"[v4,3/7] MIPS: Fix r6 testsuites","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230616063412.1715024-4-yunqiang.su@cipunited.com/mbox/"},{"id":108875,"url":"https://patchwork.plctlab.org/api/1.2/patches/108875/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230616063412.1715024-5-yunqiang.su@cipunited.com/","msgid":"<20230616063412.1715024-5-yunqiang.su@cipunited.com>","list_archive_url":null,"date":"2023-06-16T06:34:09","name":"[v4,4/7] MIPS: Fix -gnuabi64 testsuite","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230616063412.1715024-5-yunqiang.su@cipunited.com/mbox/"},{"id":108876,"url":"https://patchwork.plctlab.org/api/1.2/patches/108876/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230616063412.1715024-6-yunqiang.su@cipunited.com/","msgid":"<20230616063412.1715024-6-yunqiang.su@cipunited.com>","list_archive_url":null,"date":"2023-06-16T06:34:10","name":"[v4,5/7] MIPS: Fix some ld testcases with compiler","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230616063412.1715024-6-yunqiang.su@cipunited.com/mbox/"},{"id":108874,"url":"https://patchwork.plctlab.org/api/1.2/patches/108874/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230616063412.1715024-7-yunqiang.su@cipunited.com/","msgid":"<20230616063412.1715024-7-yunqiang.su@cipunited.com>","list_archive_url":null,"date":"2023-06-16T06:34:11","name":"[v4,6/7] MIPS: Disable fix-rm7000-2 and llpscp-64 if not has_newabi","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230616063412.1715024-7-yunqiang.su@cipunited.com/mbox/"},{"id":108877,"url":"https://patchwork.plctlab.org/api/1.2/patches/108877/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230616063412.1715024-8-yunqiang.su@cipunited.com/","msgid":"<20230616063412.1715024-8-yunqiang.su@cipunited.com>","list_archive_url":null,"date":"2023-06-16T06:34:12","name":"[v4,7/7] MIPS: Fix Irix gas testcases","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230616063412.1715024-8-yunqiang.su@cipunited.com/mbox/"},{"id":108891,"url":"https://patchwork.plctlab.org/api/1.2/patches/108891/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230616072536.1805704-1-yunqiang.su@cipunited.com/","msgid":"<20230616072536.1805704-1-yunqiang.su@cipunited.com>","list_archive_url":null,"date":"2023-06-16T07:25:35","name":"[v3,1/2] MIPS: Add MT ASE support for micromips32","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230616072536.1805704-1-yunqiang.su@cipunited.com/mbox/"},{"id":108892,"url":"https://patchwork.plctlab.org/api/1.2/patches/108892/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230616072536.1805704-2-yunqiang.su@cipunited.com/","msgid":"<20230616072536.1805704-2-yunqiang.su@cipunited.com>","list_archive_url":null,"date":"2023-06-16T07:25:36","name":"[v3,2/2] MIPS: Sync oprand char usage between mips and micromips","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230616072536.1805704-2-yunqiang.su@cipunited.com/mbox/"},{"id":108895,"url":"https://patchwork.plctlab.org/api/1.2/patches/108895/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/503caac8-8824-823a-81c2-762cba207cb6@suse.com/","msgid":"<503caac8-8824-823a-81c2-762cba207cb6@suse.com>","list_archive_url":null,"date":"2023-06-16T07:30:41","name":"[1/4] x86: optimize pre-AVX512 {,V}PCMPEQQ with identical sources","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/503caac8-8824-823a-81c2-762cba207cb6@suse.com/mbox/"},{"id":108896,"url":"https://patchwork.plctlab.org/api/1.2/patches/108896/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7141b586-9711-aef0-7f28-5d4489478f1b@suse.com/","msgid":"<7141b586-9711-aef0-7f28-5d4489478f1b@suse.com>","list_archive_url":null,"date":"2023-06-16T07:31:12","name":"[2/4] x86: optimize pre-AVX512 {,V}PCMPGT* with identical sources","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7141b586-9711-aef0-7f28-5d4489478f1b@suse.com/mbox/"},{"id":108899,"url":"https://patchwork.plctlab.org/api/1.2/patches/108899/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3e1b884e-7312-8546-ebdc-ac513a199858@suse.com/","msgid":"<3e1b884e-7312-8546-ebdc-ac513a199858@suse.com>","list_archive_url":null,"date":"2023-06-16T07:31:41","name":"[3/4] x86: optimize 128-bit VPBROADCASTQ to VPUNPCKLQDQ","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3e1b884e-7312-8546-ebdc-ac513a199858@suse.com/mbox/"},{"id":108900,"url":"https://patchwork.plctlab.org/api/1.2/patches/108900/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/08bf9dc9-5616-7dce-a094-d2ea799c92bf@suse.com/","msgid":"<08bf9dc9-5616-7dce-a094-d2ea799c92bf@suse.com>","list_archive_url":null,"date":"2023-06-16T07:32:40","name":"[4/4] x86: provide a 128-bit VBROADCASTSD pseudo","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/08bf9dc9-5616-7dce-a094-d2ea799c92bf@suse.com/mbox/"},{"id":109009,"url":"https://patchwork.plctlab.org/api/1.2/patches/109009/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f8f64771-eb63-2df3-b03b-8ed1cf3b4310@suse.com/","msgid":"","list_archive_url":null,"date":"2023-06-16T10:15:29","name":"[1/5] x86: re-work EVEX-z-without-masking check","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f8f64771-eb63-2df3-b03b-8ed1cf3b4310@suse.com/mbox/"},{"id":109010,"url":"https://patchwork.plctlab.org/api/1.2/patches/109010/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c7e5b576-f830-7493-74c1-66c05155fbec@suse.com/","msgid":"","list_archive_url":null,"date":"2023-06-16T10:15:55","name":"[2/5] x86: flag EVEX.z set when destination is a mask register","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c7e5b576-f830-7493-74c1-66c05155fbec@suse.com/mbox/"},{"id":109011,"url":"https://patchwork.plctlab.org/api/1.2/patches/109011/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/65872bf7-36c2-0a0a-8992-38a0843a897d@suse.com/","msgid":"<65872bf7-36c2-0a0a-8992-38a0843a897d@suse.com>","list_archive_url":null,"date":"2023-06-16T10:16:20","name":"[3/5] x86: flag EVEX.z set when destination is memory","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/65872bf7-36c2-0a0a-8992-38a0843a897d@suse.com/mbox/"},{"id":109013,"url":"https://patchwork.plctlab.org/api/1.2/patches/109013/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2574a7d2-68aa-70e3-c5da-fc726c952c22@suse.com/","msgid":"<2574a7d2-68aa-70e3-c5da-fc726c952c22@suse.com>","list_archive_url":null,"date":"2023-06-16T10:16:44","name":"[4/5] x86: flag EVEX masking when destination is GPR(-like)","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2574a7d2-68aa-70e3-c5da-fc726c952c22@suse.com/mbox/"},{"id":109017,"url":"https://patchwork.plctlab.org/api/1.2/patches/109017/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/33c2fa9f-1f8e-bed0-8653-39eb876fb0b3@suse.com/","msgid":"<33c2fa9f-1f8e-bed0-8653-39eb876fb0b3@suse.com>","list_archive_url":null,"date":"2023-06-16T10:17:26","name":"[5/5] x86: flag bad EVEX masking for miscellaneous insns","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/33c2fa9f-1f8e-bed0-8653-39eb876fb0b3@suse.com/mbox/"},{"id":109088,"url":"https://patchwork.plctlab.org/api/1.2/patches/109088/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/bd3adbb3-02d0-3fea-f154-ece44bed7b60@suse.com/","msgid":"","list_archive_url":null,"date":"2023-06-16T12:34:06","name":"x86: fix expansion of %XV","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/bd3adbb3-02d0-3fea-f154-ece44bed7b60@suse.com/mbox/"},{"id":109639,"url":"https://patchwork.plctlab.org/api/1.2/patches/109639/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/648f4180.a70a0220.a7021.407c@mx.google.com/","msgid":"<648f4180.a70a0220.a7021.407c@mx.google.com>","list_archive_url":null,"date":"2023-06-18T17:40:13","name":"[V3] optimize handle_COMDAT","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/648f4180.a70a0220.a7021.407c@mx.google.com/mbox/"},{"id":110435,"url":"https://patchwork.plctlab.org/api/1.2/patches/110435/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/AM6PR03MB49848E63E54AAB7B7C0D80E4985CA@AM6PR03MB4984.eurprd03.prod.outlook.com/","msgid":"","list_archive_url":null,"date":"2023-06-20T11:43:07","name":"[0/1] riscv: Ensure LE instruction fetching","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/AM6PR03MB49848E63E54AAB7B7C0D80E4985CA@AM6PR03MB4984.eurprd03.prod.outlook.com/mbox/"},{"id":110613,"url":"https://patchwork.plctlab.org/api/1.2/patches/110613/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230620164436.432481-1-hjl.tools@gmail.com/","msgid":"<20230620164436.432481-1-hjl.tools@gmail.com>","list_archive_url":null,"date":"2023-06-20T16:44:36","name":"x86: Don'\''t check if AVX512 template requires AVX512VL","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230620164436.432481-1-hjl.tools@gmail.com/mbox/"},{"id":110703,"url":"https://patchwork.plctlab.org/api/1.2/patches/110703/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230620223204.629663-1-hjl.tools@gmail.com/","msgid":"<20230620223204.629663-1-hjl.tools@gmail.com>","list_archive_url":null,"date":"2023-06-20T22:32:04","name":"x86: Free the symbol buffer and the relocation buffer after use","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230620223204.629663-1-hjl.tools@gmail.com/mbox/"},{"id":110789,"url":"https://patchwork.plctlab.org/api/1.2/patches/110789/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZJKWtMcKv3ZBw0Cq@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-06-21T06:20:36","name":"macho-o.c don'\''t leak strtab","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZJKWtMcKv3ZBw0Cq@squeak.grove.modra.org/mbox/"},{"id":110790,"url":"https://patchwork.plctlab.org/api/1.2/patches/110790/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZJKW2M//EO8S5UUV@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-06-21T06:21:12","name":"elf32_arm_get_synthetic_symtab memory leak","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZJKW2M//EO8S5UUV@squeak.grove.modra.org/mbox/"},{"id":110832,"url":"https://patchwork.plctlab.org/api/1.2/patches/110832/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230621072732.1652861-1-lili.cui@intel.com/","msgid":"<20230621072732.1652861-1-lili.cui@intel.com>","list_archive_url":null,"date":"2023-06-21T07:27:32","name":"gprofng: Update intel url","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230621072732.1652861-1-lili.cui@intel.com/mbox/"},{"id":110979,"url":"https://patchwork.plctlab.org/api/1.2/patches/110979/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/87352l6qjc.fsf@redhat.com/","msgid":"<87352l6qjc.fsf@redhat.com>","list_archive_url":null,"date":"2023-06-21T10:47:03","name":"Commit: Fix PR 29072 test with --enable-default-execstack=no","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/87352l6qjc.fsf@redhat.com/mbox/"},{"id":110983,"url":"https://patchwork.plctlab.org/api/1.2/patches/110983/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/87zg4t5awt.fsf@redhat.com/","msgid":"<87zg4t5awt.fsf@redhat.com>","list_archive_url":null,"date":"2023-06-21T11:09:54","name":"Commit: Prune warnings about -z execstack when --enable-warn-execstack=yes has been used","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/87zg4t5awt.fsf@redhat.com/mbox/"},{"id":111025,"url":"https://patchwork.plctlab.org/api/1.2/patches/111025/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZJL9LBr/Zuvjc+Yv@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-06-21T13:37:48","name":"[GOLD] PR30536, ppc64el gold linker produces unusable clang-16 binary","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZJL9LBr/Zuvjc+Yv@squeak.grove.modra.org/mbox/"},{"id":111790,"url":"https://patchwork.plctlab.org/api/1.2/patches/111790/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230622193759.737009-1-hjl.tools@gmail.com/","msgid":"<20230622193759.737009-1-hjl.tools@gmail.com>","list_archive_url":null,"date":"2023-06-22T19:37:59","name":"Revert \"x86: Don'\''t check if AVX512 template requires AVX512VL\"","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230622193759.737009-1-hjl.tools@gmail.com/mbox/"},{"id":111837,"url":"https://patchwork.plctlab.org/api/1.2/patches/111837/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230622232510.49099-1-david@davidgf.es/","msgid":"<20230622232510.49099-1-david@davidgf.es>","list_archive_url":null,"date":"2023-06-22T23:25:09","name":"[1/2] Exclude trap instructions for MIPS Allegrex","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230622232510.49099-1-david@davidgf.es/mbox/"},{"id":111838,"url":"https://patchwork.plctlab.org/api/1.2/patches/111838/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230622232510.49099-2-david@davidgf.es/","msgid":"<20230622232510.49099-2-david@davidgf.es>","list_archive_url":null,"date":"2023-06-22T23:25:10","name":"[2/2] Adding missing MIPS Allegrex instruction","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230622232510.49099-2-david@davidgf.es/mbox/"},{"id":111911,"url":"https://patchwork.plctlab.org/api/1.2/patches/111911/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230623044448.2617101-2-indu.bhagat@oracle.com/","msgid":"<20230623044448.2617101-2-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-06-23T04:44:39","name":"[01/10] libsframe: add library versioning","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230623044448.2617101-2-indu.bhagat@oracle.com/mbox/"},{"id":111910,"url":"https://patchwork.plctlab.org/api/1.2/patches/111910/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230623044448.2617101-3-indu.bhagat@oracle.com/","msgid":"<20230623044448.2617101-3-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-06-23T04:44:40","name":"[02/10] libsframe: remove sframe_get_funcdesc_with_addr API","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230623044448.2617101-3-indu.bhagat@oracle.com/mbox/"},{"id":111917,"url":"https://patchwork.plctlab.org/api/1.2/patches/111917/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230623044448.2617101-4-indu.bhagat@oracle.com/","msgid":"<20230623044448.2617101-4-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-06-23T04:44:41","name":"[03/10] libsframe: add symbol versioning","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230623044448.2617101-4-indu.bhagat@oracle.com/mbox/"},{"id":111913,"url":"https://patchwork.plctlab.org/api/1.2/patches/111913/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230623044448.2617101-5-indu.bhagat@oracle.com/","msgid":"<20230623044448.2617101-5-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-06-23T04:44:42","name":"[04/10] libsframe: update the semantics of sframe_fre_get_ra_offset","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230623044448.2617101-5-indu.bhagat@oracle.com/mbox/"},{"id":111912,"url":"https://patchwork.plctlab.org/api/1.2/patches/111912/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230623044448.2617101-6-indu.bhagat@oracle.com/","msgid":"<20230623044448.2617101-6-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-06-23T04:44:43","name":"[05/10] libsframe: update the semantics of sframe_fre_get_fp_offset","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230623044448.2617101-6-indu.bhagat@oracle.com/mbox/"},{"id":111916,"url":"https://patchwork.plctlab.org/api/1.2/patches/111916/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230623044448.2617101-7-indu.bhagat@oracle.com/","msgid":"<20230623044448.2617101-7-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-06-23T04:44:44","name":"[06/10] libsframe: use uint32_t for fre_type and fde_type function args","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230623044448.2617101-7-indu.bhagat@oracle.com/mbox/"},{"id":111919,"url":"https://patchwork.plctlab.org/api/1.2/patches/111919/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230623044448.2617101-8-indu.bhagat@oracle.com/","msgid":"<20230623044448.2617101-8-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-06-23T04:44:45","name":"[07/10] bfd: libsframe: use uint32_t for return type of sframe_calc_fre_type","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230623044448.2617101-8-indu.bhagat@oracle.com/mbox/"},{"id":111914,"url":"https://patchwork.plctlab.org/api/1.2/patches/111914/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230623044448.2617101-9-indu.bhagat@oracle.com/","msgid":"<20230623044448.2617101-9-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-06-23T04:44:46","name":"[08/10] libsframe: use uint8_t instead of unsigned char for abi_arch","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230623044448.2617101-9-indu.bhagat@oracle.com/mbox/"},{"id":111915,"url":"https://patchwork.plctlab.org/api/1.2/patches/111915/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230623044448.2617101-10-indu.bhagat@oracle.com/","msgid":"<20230623044448.2617101-10-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-06-23T04:44:47","name":"[09/10] libsframe: use uint8_t for return type of sframe_fre_get_base_reg_id","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230623044448.2617101-10-indu.bhagat@oracle.com/mbox/"},{"id":111918,"url":"https://patchwork.plctlab.org/api/1.2/patches/111918/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230623044448.2617101-11-indu.bhagat@oracle.com/","msgid":"<20230623044448.2617101-11-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-06-23T04:44:48","name":"[10/10] binutils/NEWS: add note about upcoming libsframe changes","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230623044448.2617101-11-indu.bhagat@oracle.com/mbox/"},{"id":112090,"url":"https://patchwork.plctlab.org/api/1.2/patches/112090/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZJWCzBxYkM7kIEJT@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-06-23T11:32:28","name":"lto test fails with -fno-inline in CFLAGS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZJWCzBxYkM7kIEJT@squeak.grove.modra.org/mbox/"},{"id":112092,"url":"https://patchwork.plctlab.org/api/1.2/patches/112092/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZJWDWhpXisjeWfPg@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-06-23T11:34:50","name":"[GOLD] powerpc DT_RELACOUNT","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZJWDWhpXisjeWfPg@squeak.grove.modra.org/mbox/"},{"id":112093,"url":"https://patchwork.plctlab.org/api/1.2/patches/112093/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZJWEWYg0ZOpwoMSq@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-06-23T11:39:05","name":"[GOLD] Support setting DT_RELACOUNT late","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZJWEWYg0ZOpwoMSq@squeak.grove.modra.org/mbox/"},{"id":112094,"url":"https://patchwork.plctlab.org/api/1.2/patches/112094/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZJWEtp7jDRVNckRK@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-06-23T11:40:38","name":"[GOLD] PowerPC64 huge branch dynamic relocs","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZJWEtp7jDRVNckRK@squeak.grove.modra.org/mbox/"},{"id":112524,"url":"https://patchwork.plctlab.org/api/1.2/patches/112524/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230625083850.1028642-2-mengqinggang@loongson.cn/","msgid":"<20230625083850.1028642-2-mengqinggang@loongson.cn>","list_archive_url":null,"date":"2023-06-25T08:38:49","name":"[v0,1/2] LoongArch: gas: Add LSX and LASX instructions support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230625083850.1028642-2-mengqinggang@loongson.cn/mbox/"},{"id":112523,"url":"https://patchwork.plctlab.org/api/1.2/patches/112523/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230625083850.1028642-3-mengqinggang@loongson.cn/","msgid":"<20230625083850.1028642-3-mengqinggang@loongson.cn>","list_archive_url":null,"date":"2023-06-25T08:38:50","name":"[v0,2/2] LoongArch: gas: Add LSX and LASX instructions test","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230625083850.1028642-3-mengqinggang@loongson.cn/mbox/"},{"id":112533,"url":"https://patchwork.plctlab.org/api/1.2/patches/112533/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230625095540.1202120-1-mengqinggang@loongson.cn/","msgid":"<20230625095540.1202120-1-mengqinggang@loongson.cn>","list_archive_url":null,"date":"2023-06-25T09:55:40","name":"LoongArch: Add R_LARCH_64_PCREL relocation support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230625095540.1202120-1-mengqinggang@loongson.cn/mbox/"},{"id":112807,"url":"https://patchwork.plctlab.org/api/1.2/patches/112807/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230626091656.31782-1-krebbel@linux.ibm.com/","msgid":"<20230626091656.31782-1-krebbel@linux.ibm.com>","list_archive_url":null,"date":"2023-06-26T09:16:56","name":"ld - Add SYMBOL_ABI_ALIGNMENT variable and apply to __bss_start","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230626091656.31782-1-krebbel@linux.ibm.com/mbox/"},{"id":112947,"url":"https://patchwork.plctlab.org/api/1.2/patches/112947/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/87sfaez7ut.fsf@redhat.com/","msgid":"<87sfaez7ut.fsf@redhat.com>","list_archive_url":null,"date":"2023-06-26T13:11:22","name":"Commit: Sync config.sub and config.guess","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/87sfaez7ut.fsf@redhat.com/mbox/"},{"id":112954,"url":"https://patchwork.plctlab.org/api/1.2/patches/112954/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/bf42815b-bc8c-dc64-9393-43cdbb6fbb76@e124511.cambridge.arm.com/","msgid":"","list_archive_url":null,"date":"2023-06-26T13:50:57","name":"aarch64: Remove version dependencies from features","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/bf42815b-bc8c-dc64-9393-43cdbb6fbb76@e124511.cambridge.arm.com/mbox/"},{"id":112991,"url":"https://patchwork.plctlab.org/api/1.2/patches/112991/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/87pm5iz3fu.fsf@redhat.com/","msgid":"<87pm5iz3fu.fsf@redhat.com>","list_archive_url":null,"date":"2023-06-26T14:46:45","name":"Commit: Update libiberty sources","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/87pm5iz3fu.fsf@redhat.com/mbox/"},{"id":113014,"url":"https://patchwork.plctlab.org/api/1.2/patches/113014/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.LSU.2.20.2306261532320.13548@wotan.suse.de/","msgid":"","list_archive_url":null,"date":"2023-06-26T15:35:09","name":"section-match: Check parent archive name as well","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.LSU.2.20.2306261532320.13548@wotan.suse.de/mbox/"},{"id":113046,"url":"https://patchwork.plctlab.org/api/1.2/patches/113046/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/87mt0myyc2.fsf@redhat.com/","msgid":"<87mt0myyc2.fsf@redhat.com>","list_archive_url":null,"date":"2023-06-26T16:37:01","name":"Commit: Fix gas testsuite failures for non-ELF AArch64 toolchains","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/87mt0myyc2.fsf@redhat.com/mbox/"},{"id":113129,"url":"https://patchwork.plctlab.org/api/1.2/patches/113129/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230626214619.1808676-1-vladimir.mezentsev@oracle.com/","msgid":"<20230626214619.1808676-1-vladimir.mezentsev@oracle.com>","list_archive_url":null,"date":"2023-06-26T21:46:19","name":"gprofng: Add new tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230626214619.1808676-1-vladimir.mezentsev@oracle.com/mbox/"},{"id":113414,"url":"https://patchwork.plctlab.org/api/1.2/patches/113414/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230627124728.3563-1-lidie@eswincomputing.com/","msgid":"<20230627124728.3563-1-lidie@eswincomputing.com>","list_archive_url":null,"date":"2023-06-27T12:47:28","name":"[RISC-V] Optimize GP-relative addressing for linker.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230627124728.3563-1-lidie@eswincomputing.com/mbox/"},{"id":113448,"url":"https://patchwork.plctlab.org/api/1.2/patches/113448/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230627144250.16818-1-palmer@rivosinc.com/","msgid":"<20230627144250.16818-1-palmer@rivosinc.com>","list_archive_url":null,"date":"2023-06-27T14:42:50","name":"gas: NEWS: Add the latest RISC-V extensions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230627144250.16818-1-palmer@rivosinc.com/mbox/"},{"id":113562,"url":"https://patchwork.plctlab.org/api/1.2/patches/113562/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230627195126.1955051-1-indu.bhagat@oracle.com/","msgid":"<20230627195126.1955051-1-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-06-27T19:51:15","name":"[COMMITTED] libsframe: add library versioning","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230627195126.1955051-1-indu.bhagat@oracle.com/mbox/"},{"id":113563,"url":"https://patchwork.plctlab.org/api/1.2/patches/113563/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230627195126.1955051-2-indu.bhagat@oracle.com/","msgid":"<20230627195126.1955051-2-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-06-27T19:51:16","name":"[COMMITTED] libsframe: remove sframe_get_funcdesc_with_addr API","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230627195126.1955051-2-indu.bhagat@oracle.com/mbox/"},{"id":113574,"url":"https://patchwork.plctlab.org/api/1.2/patches/113574/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230627195126.1955051-3-indu.bhagat@oracle.com/","msgid":"<20230627195126.1955051-3-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-06-27T19:51:17","name":"[COMMITTED] libsframe: add symbol versioning","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230627195126.1955051-3-indu.bhagat@oracle.com/mbox/"},{"id":113569,"url":"https://patchwork.plctlab.org/api/1.2/patches/113569/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230627195126.1955051-4-indu.bhagat@oracle.com/","msgid":"<20230627195126.1955051-4-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-06-27T19:51:18","name":"[COMMITTED] libsframe: update the semantics of sframe_fre_get_ra_offset","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230627195126.1955051-4-indu.bhagat@oracle.com/mbox/"},{"id":113572,"url":"https://patchwork.plctlab.org/api/1.2/patches/113572/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230627195126.1955051-5-indu.bhagat@oracle.com/","msgid":"<20230627195126.1955051-5-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-06-27T19:51:19","name":"[COMMITTED] libsframe: update the semantics of sframe_fre_get_fp_offset","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230627195126.1955051-5-indu.bhagat@oracle.com/mbox/"},{"id":113570,"url":"https://patchwork.plctlab.org/api/1.2/patches/113570/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230627195126.1955051-6-indu.bhagat@oracle.com/","msgid":"<20230627195126.1955051-6-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-06-27T19:51:20","name":"[COMMITTED] libsframe: use uint32_t for fre_type and fde_type function args","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230627195126.1955051-6-indu.bhagat@oracle.com/mbox/"},{"id":113577,"url":"https://patchwork.plctlab.org/api/1.2/patches/113577/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230627195126.1955051-7-indu.bhagat@oracle.com/","msgid":"<20230627195126.1955051-7-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-06-27T19:51:21","name":"[COMMITTED] libsframe: bfd: use uint32_t for return type of sframe_calc_fre_type","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230627195126.1955051-7-indu.bhagat@oracle.com/mbox/"},{"id":113573,"url":"https://patchwork.plctlab.org/api/1.2/patches/113573/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230627195126.1955051-8-indu.bhagat@oracle.com/","msgid":"<20230627195126.1955051-8-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-06-27T19:51:22","name":"[COMMITTED] libsframe: use uint8_t instead of unsigned char for abi_arch","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230627195126.1955051-8-indu.bhagat@oracle.com/mbox/"},{"id":113564,"url":"https://patchwork.plctlab.org/api/1.2/patches/113564/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230627195126.1955051-9-indu.bhagat@oracle.com/","msgid":"<20230627195126.1955051-9-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-06-27T19:51:23","name":"[COMMITTED] libsframe: use uint8_t for return type of sframe_fre_get_base_reg_id","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230627195126.1955051-9-indu.bhagat@oracle.com/mbox/"},{"id":113565,"url":"https://patchwork.plctlab.org/api/1.2/patches/113565/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230627195126.1955051-10-indu.bhagat@oracle.com/","msgid":"<20230627195126.1955051-10-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-06-27T19:51:24","name":"[COMMITTED] libsframe: use appropriate data types for args of sframe_encode","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230627195126.1955051-10-indu.bhagat@oracle.com/mbox/"},{"id":113576,"url":"https://patchwork.plctlab.org/api/1.2/patches/113576/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230627195126.1955051-11-indu.bhagat@oracle.com/","msgid":"<20230627195126.1955051-11-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-06-27T19:51:25","name":"[COMMITTED] libsframe: bfd: use uint32_t for return type of get_num_fidx APIs","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230627195126.1955051-11-indu.bhagat@oracle.com/mbox/"},{"id":113578,"url":"https://patchwork.plctlab.org/api/1.2/patches/113578/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230627195126.1955051-12-indu.bhagat@oracle.com/","msgid":"<20230627195126.1955051-12-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-06-27T19:51:26","name":"[COMMITTED] binutils/NEWS: add note about upcoming libsframe changes","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230627195126.1955051-12-indu.bhagat@oracle.com/mbox/"},{"id":113614,"url":"https://patchwork.plctlab.org/api/1.2/patches/113614/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230627212028.2138604-2-indu.bhagat@oracle.com/","msgid":"<20230627212028.2138604-2-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-06-27T21:20:17","name":"[01/12] sframe.h: format bump to SFrame version 2","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230627212028.2138604-2-indu.bhagat@oracle.com/mbox/"},{"id":113611,"url":"https://patchwork.plctlab.org/api/1.2/patches/113611/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230627212028.2138604-3-indu.bhagat@oracle.com/","msgid":"<20230627212028.2138604-3-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-06-27T21:20:18","name":"[02/12] gas: generate SFrame section with version SFRAME_VERSION_2","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230627212028.2138604-3-indu.bhagat@oracle.com/mbox/"},{"id":113615,"url":"https://patchwork.plctlab.org/api/1.2/patches/113615/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230627212028.2138604-4-indu.bhagat@oracle.com/","msgid":"<20230627212028.2138604-4-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-06-27T21:20:19","name":"[03/12] libsframe: add new APIs to get SFrame version","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230627212028.2138604-4-indu.bhagat@oracle.com/mbox/"},{"id":113612,"url":"https://patchwork.plctlab.org/api/1.2/patches/113612/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230627212028.2138604-5-indu.bhagat@oracle.com/","msgid":"<20230627212028.2138604-5-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-06-27T21:20:20","name":"[04/12] libsframe: add new APIs to add and get SFrame FDE in SFrame version 2","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230627212028.2138604-5-indu.bhagat@oracle.com/mbox/"},{"id":113618,"url":"https://patchwork.plctlab.org/api/1.2/patches/113618/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230627212028.2138604-6-indu.bhagat@oracle.com/","msgid":"<20230627212028.2138604-6-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-06-27T21:20:21","name":"[05/12] libsframe: adjust version check in sframe_header_sanity_check_p","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230627212028.2138604-6-indu.bhagat@oracle.com/mbox/"},{"id":113616,"url":"https://patchwork.plctlab.org/api/1.2/patches/113616/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230627212028.2138604-7-indu.bhagat@oracle.com/","msgid":"<20230627212028.2138604-7-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-06-27T21:20:22","name":"[06/12] libsframe: testsuite: fixes for SFRAME_VERSION_2","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230627212028.2138604-7-indu.bhagat@oracle.com/mbox/"},{"id":113619,"url":"https://patchwork.plctlab.org/api/1.2/patches/113619/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230627212028.2138604-8-indu.bhagat@oracle.com/","msgid":"<20230627212028.2138604-8-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-06-27T21:20:23","name":"[07/12] bfd: linker: add support for rep_block_size for pltN entries","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230627212028.2138604-8-indu.bhagat@oracle.com/mbox/"},{"id":113622,"url":"https://patchwork.plctlab.org/api/1.2/patches/113622/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230627212028.2138604-9-indu.bhagat@oracle.com/","msgid":"<20230627212028.2138604-9-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-06-27T21:20:24","name":"[08/12] bfd: linker: generate SFrame sections with version SFRAME_VERSION_2","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230627212028.2138604-9-indu.bhagat@oracle.com/mbox/"},{"id":113613,"url":"https://patchwork.plctlab.org/api/1.2/patches/113613/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230627212028.2138604-10-indu.bhagat@oracle.com/","msgid":"<20230627212028.2138604-10-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-06-27T21:20:25","name":"[09/12] objdump/readelf: adjust for SFRAME_VERSION_2","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230627212028.2138604-10-indu.bhagat@oracle.com/mbox/"},{"id":113617,"url":"https://patchwork.plctlab.org/api/1.2/patches/113617/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230627212028.2138604-11-indu.bhagat@oracle.com/","msgid":"<20230627212028.2138604-11-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-06-27T21:20:26","name":"[10/12] doc: sframe: update specification for SFRAME_VERSION_2","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230627212028.2138604-11-indu.bhagat@oracle.com/mbox/"},{"id":113620,"url":"https://patchwork.plctlab.org/api/1.2/patches/113620/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230627212028.2138604-12-indu.bhagat@oracle.com/","msgid":"<20230627212028.2138604-12-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-06-27T21:20:27","name":"[11/12] doc: sframe: add details about alignment in the SFrame format","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230627212028.2138604-12-indu.bhagat@oracle.com/mbox/"},{"id":113621,"url":"https://patchwork.plctlab.org/api/1.2/patches/113621/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230627212028.2138604-13-indu.bhagat@oracle.com/","msgid":"<20230627212028.2138604-13-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-06-27T21:20:28","name":"[12/12] binutils/NEWS: announce SFrame version 2 as the new default","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230627212028.2138604-13-indu.bhagat@oracle.com/mbox/"},{"id":113643,"url":"https://patchwork.plctlab.org/api/1.2/patches/113643/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230628010634.1147958-1-maskray@google.com/","msgid":"<20230628010634.1147958-1-maskray@google.com>","list_archive_url":null,"date":"2023-06-28T01:06:34","name":"PR30592 objcopy: allow --set-section-flags to add or remove SHF_X86_64_LARGE","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230628010634.1147958-1-maskray@google.com/mbox/"},{"id":113816,"url":"https://patchwork.plctlab.org/api/1.2/patches/113816/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230628115103.3440262-2-i.swmail@xen0n.name/","msgid":"<20230628115103.3440262-2-i.swmail@xen0n.name>","list_archive_url":null,"date":"2023-06-28T11:50:58","name":"[v5,1/6] LoongArch: support disassembling certain pseudo-instructions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230628115103.3440262-2-i.swmail@xen0n.name/mbox/"},{"id":113815,"url":"https://patchwork.plctlab.org/api/1.2/patches/113815/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230628115103.3440262-3-i.swmail@xen0n.name/","msgid":"<20230628115103.3440262-3-i.swmail@xen0n.name>","list_archive_url":null,"date":"2023-06-28T11:50:59","name":"[v5,2/6] opcodes/loongarch: remove unused code","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230628115103.3440262-3-i.swmail@xen0n.name/mbox/"},{"id":113817,"url":"https://patchwork.plctlab.org/api/1.2/patches/113817/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230628115103.3440262-4-i.swmail@xen0n.name/","msgid":"<20230628115103.3440262-4-i.swmail@xen0n.name>","list_archive_url":null,"date":"2023-06-28T11:51:00","name":"[v5,3/6] opcodes/loongarch: implement style support in the disassembler","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230628115103.3440262-4-i.swmail@xen0n.name/mbox/"},{"id":113818,"url":"https://patchwork.plctlab.org/api/1.2/patches/113818/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230628115103.3440262-5-i.swmail@xen0n.name/","msgid":"<20230628115103.3440262-5-i.swmail@xen0n.name>","list_archive_url":null,"date":"2023-06-28T11:51:01","name":"[v5,4/6] opcodes/loongarch: style disassembled address offsets as such","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230628115103.3440262-5-i.swmail@xen0n.name/mbox/"},{"id":113820,"url":"https://patchwork.plctlab.org/api/1.2/patches/113820/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230628115103.3440262-6-i.swmail@xen0n.name/","msgid":"<20230628115103.3440262-6-i.swmail@xen0n.name>","list_archive_url":null,"date":"2023-06-28T11:51:02","name":"[v5,5/6] opcodes/loongarch: do not print hex notation for signed immediates","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230628115103.3440262-6-i.swmail@xen0n.name/mbox/"},{"id":113821,"url":"https://patchwork.plctlab.org/api/1.2/patches/113821/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230628115103.3440262-7-i.swmail@xen0n.name/","msgid":"<20230628115103.3440262-7-i.swmail@xen0n.name>","list_archive_url":null,"date":"2023-06-28T11:51:03","name":"[v5,6/6] opcodes/loongarch: print unrecognized insn words with the .word directive","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230628115103.3440262-7-i.swmail@xen0n.name/mbox/"},{"id":113857,"url":"https://patchwork.plctlab.org/api/1.2/patches/113857/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230628131311.3895731-1-i.swmail@xen0n.name/","msgid":"<20230628131311.3895731-1-i.swmail@xen0n.name>","list_archive_url":null,"date":"2023-06-28T13:13:11","name":"[v2] LoongArch: Deprecate $v[01], $fv[01] and $x names per spec","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230628131311.3895731-1-i.swmail@xen0n.name/mbox/"},{"id":114109,"url":"https://patchwork.plctlab.org/api/1.2/patches/114109/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230628231610.220112-1-maskray@google.com/","msgid":"<20230628231610.220112-1-maskray@google.com>","list_archive_url":null,"date":"2023-06-28T23:16:10","name":"[v2] PR30592 objcopy: allow --set-section-flags to add or remove SHF_X86_64_LARGE","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230628231610.220112-1-maskray@google.com/mbox/"},{"id":114173,"url":"https://patchwork.plctlab.org/api/1.2/patches/114173/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629061029.29773-2-i.swmail@xen0n.name/","msgid":"<20230629061029.29773-2-i.swmail@xen0n.name>","list_archive_url":null,"date":"2023-06-29T06:10:23","name":"[v6,1/7] LoongArch: support disassembling certain pseudo-instructions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629061029.29773-2-i.swmail@xen0n.name/mbox/"},{"id":114170,"url":"https://patchwork.plctlab.org/api/1.2/patches/114170/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629061029.29773-3-i.swmail@xen0n.name/","msgid":"<20230629061029.29773-3-i.swmail@xen0n.name>","list_archive_url":null,"date":"2023-06-29T06:10:24","name":"[v6,2/7] opcodes/loongarch: remove unused code","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629061029.29773-3-i.swmail@xen0n.name/mbox/"},{"id":114175,"url":"https://patchwork.plctlab.org/api/1.2/patches/114175/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629061029.29773-4-i.swmail@xen0n.name/","msgid":"<20230629061029.29773-4-i.swmail@xen0n.name>","list_archive_url":null,"date":"2023-06-29T06:10:25","name":"[v6,3/7] opcodes/loongarch: implement style support in the disassembler","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629061029.29773-4-i.swmail@xen0n.name/mbox/"},{"id":114171,"url":"https://patchwork.plctlab.org/api/1.2/patches/114171/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629061029.29773-5-i.swmail@xen0n.name/","msgid":"<20230629061029.29773-5-i.swmail@xen0n.name>","list_archive_url":null,"date":"2023-06-29T06:10:26","name":"[v6,4/7] opcodes/loongarch: style disassembled address offsets as such","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629061029.29773-5-i.swmail@xen0n.name/mbox/"},{"id":114172,"url":"https://patchwork.plctlab.org/api/1.2/patches/114172/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629061029.29773-6-i.swmail@xen0n.name/","msgid":"<20230629061029.29773-6-i.swmail@xen0n.name>","list_archive_url":null,"date":"2023-06-29T06:10:27","name":"[v6,5/7] opcodes/loongarch: do not print hex notation for signed immediates","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629061029.29773-6-i.swmail@xen0n.name/mbox/"},{"id":114176,"url":"https://patchwork.plctlab.org/api/1.2/patches/114176/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629061029.29773-7-i.swmail@xen0n.name/","msgid":"<20230629061029.29773-7-i.swmail@xen0n.name>","list_archive_url":null,"date":"2023-06-29T06:10:28","name":"[v6,6/7] opcodes/loongarch: print unrecognized insn words with the .word directive","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629061029.29773-7-i.swmail@xen0n.name/mbox/"},{"id":114174,"url":"https://patchwork.plctlab.org/api/1.2/patches/114174/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629061029.29773-8-i.swmail@xen0n.name/","msgid":"<20230629061029.29773-8-i.swmail@xen0n.name>","list_archive_url":null,"date":"2023-06-29T06:10:29","name":"[v6,7/7] LoongArch: Deprecate $v[01], $fv[01] and $x names per spec","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629061029.29773-8-i.swmail@xen0n.name/mbox/"},{"id":114246,"url":"https://patchwork.plctlab.org/api/1.2/patches/114246/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629090831.2579210-1-mengqinggang@loongson.cn/","msgid":"<20230629090831.2579210-1-mengqinggang@loongson.cn>","list_archive_url":null,"date":"2023-06-29T09:08:31","name":"LoongArch: gas: Add LVZ and LBT instructions support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629090831.2579210-1-mengqinggang@loongson.cn/mbox/"},{"id":114357,"url":"https://patchwork.plctlab.org/api/1.2/patches/114357/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629163504.1331025-2-i.swmail@xen0n.name/","msgid":"<20230629163504.1331025-2-i.swmail@xen0n.name>","list_archive_url":null,"date":"2023-06-29T16:34:58","name":"[v7,1/7] LoongArch: support disassembling certain pseudo-instructions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629163504.1331025-2-i.swmail@xen0n.name/mbox/"},{"id":114359,"url":"https://patchwork.plctlab.org/api/1.2/patches/114359/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629163504.1331025-3-i.swmail@xen0n.name/","msgid":"<20230629163504.1331025-3-i.swmail@xen0n.name>","list_archive_url":null,"date":"2023-06-29T16:34:59","name":"[v7,2/7] opcodes/loongarch: remove unused code","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629163504.1331025-3-i.swmail@xen0n.name/mbox/"},{"id":114356,"url":"https://patchwork.plctlab.org/api/1.2/patches/114356/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629163504.1331025-4-i.swmail@xen0n.name/","msgid":"<20230629163504.1331025-4-i.swmail@xen0n.name>","list_archive_url":null,"date":"2023-06-29T16:35:00","name":"[v7,3/7] opcodes/loongarch: implement style support in the disassembler","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629163504.1331025-4-i.swmail@xen0n.name/mbox/"},{"id":114363,"url":"https://patchwork.plctlab.org/api/1.2/patches/114363/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629163504.1331025-5-i.swmail@xen0n.name/","msgid":"<20230629163504.1331025-5-i.swmail@xen0n.name>","list_archive_url":null,"date":"2023-06-29T16:35:01","name":"[v7,4/7] opcodes/loongarch: style disassembled address offsets as such","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629163504.1331025-5-i.swmail@xen0n.name/mbox/"},{"id":114362,"url":"https://patchwork.plctlab.org/api/1.2/patches/114362/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629163504.1331025-6-i.swmail@xen0n.name/","msgid":"<20230629163504.1331025-6-i.swmail@xen0n.name>","list_archive_url":null,"date":"2023-06-29T16:35:02","name":"[v7,5/7] opcodes/loongarch: do not print hex notation for signed immediates","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629163504.1331025-6-i.swmail@xen0n.name/mbox/"},{"id":114360,"url":"https://patchwork.plctlab.org/api/1.2/patches/114360/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629163504.1331025-7-i.swmail@xen0n.name/","msgid":"<20230629163504.1331025-7-i.swmail@xen0n.name>","list_archive_url":null,"date":"2023-06-29T16:35:03","name":"[v7,6/7] opcodes/loongarch: print unrecognized insn words with the .word directive","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629163504.1331025-7-i.swmail@xen0n.name/mbox/"},{"id":114364,"url":"https://patchwork.plctlab.org/api/1.2/patches/114364/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629163504.1331025-8-i.swmail@xen0n.name/","msgid":"<20230629163504.1331025-8-i.swmail@xen0n.name>","list_archive_url":null,"date":"2023-06-29T16:35:04","name":"[v7,7/7] LoongArch: Deprecate $v[01], $fv[01] and $x names per spec","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629163504.1331025-8-i.swmail@xen0n.name/mbox/"},{"id":114368,"url":"https://patchwork.plctlab.org/api/1.2/patches/114368/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629171839.573187-2-nhuck@google.com/","msgid":"<20230629171839.573187-2-nhuck@google.com>","list_archive_url":null,"date":"2023-06-29T17:18:26","name":"[01/14] Add support for the Zvbb ISA extension.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629171839.573187-2-nhuck@google.com/mbox/"},{"id":114371,"url":"https://patchwork.plctlab.org/api/1.2/patches/114371/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629171839.573187-3-nhuck@google.com/","msgid":"<20230629171839.573187-3-nhuck@google.com>","list_archive_url":null,"date":"2023-06-29T17:18:27","name":"[02/14] Add support for the Zvbc ISA extension.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629171839.573187-3-nhuck@google.com/mbox/"},{"id":114374,"url":"https://patchwork.plctlab.org/api/1.2/patches/114374/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629171839.573187-4-nhuck@google.com/","msgid":"<20230629171839.573187-4-nhuck@google.com>","list_archive_url":null,"date":"2023-06-29T17:18:28","name":"[03/14] Add support for the Zvkg ISA extension.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629171839.573187-4-nhuck@google.com/mbox/"},{"id":114369,"url":"https://patchwork.plctlab.org/api/1.2/patches/114369/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629171839.573187-5-nhuck@google.com/","msgid":"<20230629171839.573187-5-nhuck@google.com>","list_archive_url":null,"date":"2023-06-29T17:18:29","name":"[04/14] Add support for the Zvkned ISA extension.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629171839.573187-5-nhuck@google.com/mbox/"},{"id":114373,"url":"https://patchwork.plctlab.org/api/1.2/patches/114373/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629171839.573187-6-nhuck@google.com/","msgid":"<20230629171839.573187-6-nhuck@google.com>","list_archive_url":null,"date":"2023-06-29T17:18:30","name":"[05/14] Add support for the Zvknh[a,b] ISA extensions.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629171839.573187-6-nhuck@google.com/mbox/"},{"id":114376,"url":"https://patchwork.plctlab.org/api/1.2/patches/114376/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629171839.573187-7-nhuck@google.com/","msgid":"<20230629171839.573187-7-nhuck@google.com>","list_archive_url":null,"date":"2023-06-29T17:18:31","name":"[06/14] Add support for the Zvksed ISA extension.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629171839.573187-7-nhuck@google.com/mbox/"},{"id":114370,"url":"https://patchwork.plctlab.org/api/1.2/patches/114370/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629171839.573187-8-nhuck@google.com/","msgid":"<20230629171839.573187-8-nhuck@google.com>","list_archive_url":null,"date":"2023-06-29T17:18:32","name":"[07/14] Adds support for the Zvksh ISA extension.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629171839.573187-8-nhuck@google.com/mbox/"},{"id":114377,"url":"https://patchwork.plctlab.org/api/1.2/patches/114377/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629171839.573187-9-nhuck@google.com/","msgid":"<20230629171839.573187-9-nhuck@google.com>","list_archive_url":null,"date":"2023-06-29T17:18:33","name":"[08/14] Add support for the Zvkn ISA extension.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629171839.573187-9-nhuck@google.com/mbox/"},{"id":114381,"url":"https://patchwork.plctlab.org/api/1.2/patches/114381/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629171839.573187-10-nhuck@google.com/","msgid":"<20230629171839.573187-10-nhuck@google.com>","list_archive_url":null,"date":"2023-06-29T17:18:34","name":"[09/14] Allow nested implications for extensions.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629171839.573187-10-nhuck@google.com/mbox/"},{"id":114382,"url":"https://patchwork.plctlab.org/api/1.2/patches/114382/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629171839.573187-11-nhuck@google.com/","msgid":"<20230629171839.573187-11-nhuck@google.com>","list_archive_url":null,"date":"2023-06-29T17:18:35","name":"[10/14] Add support for the Zvkng ISA extension.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629171839.573187-11-nhuck@google.com/mbox/"},{"id":114372,"url":"https://patchwork.plctlab.org/api/1.2/patches/114372/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629171839.573187-12-nhuck@google.com/","msgid":"<20230629171839.573187-12-nhuck@google.com>","list_archive_url":null,"date":"2023-06-29T17:18:36","name":"[11/14] Add support for the Zvks ISA extension.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629171839.573187-12-nhuck@google.com/mbox/"},{"id":114375,"url":"https://patchwork.plctlab.org/api/1.2/patches/114375/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629171839.573187-13-nhuck@google.com/","msgid":"<20230629171839.573187-13-nhuck@google.com>","list_archive_url":null,"date":"2023-06-29T17:18:37","name":"[12/14] Add support for the Zvksg ISA extension.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629171839.573187-13-nhuck@google.com/mbox/"},{"id":114378,"url":"https://patchwork.plctlab.org/api/1.2/patches/114378/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629171839.573187-14-nhuck@google.com/","msgid":"<20230629171839.573187-14-nhuck@google.com>","list_archive_url":null,"date":"2023-06-29T17:18:38","name":"[13/14] Add support for the Zvknc ISA extension.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629171839.573187-14-nhuck@google.com/mbox/"},{"id":114383,"url":"https://patchwork.plctlab.org/api/1.2/patches/114383/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629171839.573187-15-nhuck@google.com/","msgid":"<20230629171839.573187-15-nhuck@google.com>","list_archive_url":null,"date":"2023-06-29T17:18:39","name":"[14/14] Add support for the Zvksc ISA extension.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629171839.573187-15-nhuck@google.com/mbox/"},{"id":114391,"url":"https://patchwork.plctlab.org/api/1.2/patches/114391/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629182618.2351051-1-indu.bhagat@oracle.com/","msgid":"<20230629182618.2351051-1-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-06-29T18:26:18","name":"[COMMITTED] libsframe: fix sframe_find_fre for pltN entries","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629182618.2351051-1-indu.bhagat@oracle.com/mbox/"},{"id":114494,"url":"https://patchwork.plctlab.org/api/1.2/patches/114494/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629235326.1167898-1-indu.bhagat@oracle.com/","msgid":"<20230629235326.1167898-1-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-06-29T23:53:23","name":"[COMMITTED] libsframe: add new APIs to get SFrame version","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629235326.1167898-1-indu.bhagat@oracle.com/mbox/"},{"id":114496,"url":"https://patchwork.plctlab.org/api/1.2/patches/114496/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629235326.1167898-2-indu.bhagat@oracle.com/","msgid":"<20230629235326.1167898-2-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-06-29T23:53:24","name":"[COMMITTED] sframe: bfd: gas: ld: format bump to SFrame version 2","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629235326.1167898-2-indu.bhagat@oracle.com/mbox/"},{"id":114492,"url":"https://patchwork.plctlab.org/api/1.2/patches/114492/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629235326.1167898-3-indu.bhagat@oracle.com/","msgid":"<20230629235326.1167898-3-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-06-29T23:53:25","name":"[COMMITTED] doc: sframe: update specification for SFRAME_VERSION_2","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629235326.1167898-3-indu.bhagat@oracle.com/mbox/"},{"id":114491,"url":"https://patchwork.plctlab.org/api/1.2/patches/114491/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629235326.1167898-4-indu.bhagat@oracle.com/","msgid":"<20230629235326.1167898-4-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-06-29T23:53:26","name":"[COMMITTED] binutils/NEWS: announce SFrame version 2 as the new default","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629235326.1167898-4-indu.bhagat@oracle.com/mbox/"},{"id":114538,"url":"https://patchwork.plctlab.org/api/1.2/patches/114538/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230630025308.3258293-1-vladimir.mezentsev@oracle.com/","msgid":"<20230630025308.3258293-1-vladimir.mezentsev@oracle.com>","list_archive_url":null,"date":"2023-06-30T02:53:08","name":"gprofng: fix data race","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230630025308.3258293-1-vladimir.mezentsev@oracle.com/mbox/"},{"id":114543,"url":"https://patchwork.plctlab.org/api/1.2/patches/114543/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230630033443.2359278-2-mengqinggang@loongson.cn/","msgid":"<20230630033443.2359278-2-mengqinggang@loongson.cn>","list_archive_url":null,"date":"2023-06-30T03:34:42","name":"[v1,1/2] LoongArch: gas: Add LVZ and LBT instructions support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230630033443.2359278-2-mengqinggang@loongson.cn/mbox/"},{"id":114544,"url":"https://patchwork.plctlab.org/api/1.2/patches/114544/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230630033443.2359278-3-mengqinggang@loongson.cn/","msgid":"<20230630033443.2359278-3-mengqinggang@loongson.cn>","list_archive_url":null,"date":"2023-06-30T03:34:43","name":"[v1,2/2] LoongArch: gas: Fix code style issues","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230630033443.2359278-3-mengqinggang@loongson.cn/mbox/"},{"id":114557,"url":"https://patchwork.plctlab.org/api/1.2/patches/114557/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230630051451.1867944-1-yunqiang.su@cipunited.com/","msgid":"<20230630051451.1867944-1-yunqiang.su@cipunited.com>","list_archive_url":null,"date":"2023-06-30T05:14:51","name":"ld: Use [list ] syntax to define run_tests in indirect.exp","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230630051451.1867944-1-yunqiang.su@cipunited.com/mbox/"},{"id":114580,"url":"https://patchwork.plctlab.org/api/1.2/patches/114580/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230630060757.2006878-1-yunqiang.su@cipunited.com/","msgid":"<20230630060757.2006878-1-yunqiang.su@cipunited.com>","list_archive_url":null,"date":"2023-06-30T06:07:57","name":"ld: Use run_host_cmd_yesno in indirect.exp instead of catch exec","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230630060757.2006878-1-yunqiang.su@cipunited.com/mbox/"},{"id":114592,"url":"https://patchwork.plctlab.org/api/1.2/patches/114592/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230630064559.2282365-1-yunqiang.su@cipunited.com/","msgid":"<20230630064559.2282365-1-yunqiang.su@cipunited.com>","list_archive_url":null,"date":"2023-06-30T06:45:59","name":"MIPS: N64, mark .interp as INITIAL_READONLY_SECTIONS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230630064559.2282365-1-yunqiang.su@cipunited.com/mbox/"},{"id":114606,"url":"https://patchwork.plctlab.org/api/1.2/patches/114606/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/CAP2b4GMYH=czD31TwmNrqOjnRH1dOsPVo8Be9VN=_EiFQWitoQ@mail.gmail.com/","msgid":"","list_archive_url":null,"date":"2023-06-30T07:53:13","name":"Add the .seh_ifrepeat and .seh_ifnrepeat directives","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/CAP2b4GMYH=czD31TwmNrqOjnRH1dOsPVo8Be9VN=_EiFQWitoQ@mail.gmail.com/mbox/"},{"id":114625,"url":"https://patchwork.plctlab.org/api/1.2/patches/114625/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230630090416.3051425-2-mengqinggang@loongson.cn/","msgid":"<20230630090416.3051425-2-mengqinggang@loongson.cn>","list_archive_url":null,"date":"2023-06-30T09:04:15","name":"[v2,1/2] LoongArch: gas: Add LVZ and LBT instructions support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230630090416.3051425-2-mengqinggang@loongson.cn/mbox/"},{"id":114627,"url":"https://patchwork.plctlab.org/api/1.2/patches/114627/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230630090416.3051425-3-mengqinggang@loongson.cn/","msgid":"<20230630090416.3051425-3-mengqinggang@loongson.cn>","list_archive_url":null,"date":"2023-06-30T09:04:16","name":"[v2,2/2] LoongArch: gas: Fix code style issues","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230630090416.3051425-3-mengqinggang@loongson.cn/mbox/"},{"id":114639,"url":"https://patchwork.plctlab.org/api/1.2/patches/114639/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/878rc1707w.fsf@redhat.com/","msgid":"<878rc1707w.fsf@redhat.com>","list_archive_url":null,"date":"2023-06-30T09:45:07","name":"Commit: Fix used before initialised warnings from Clang 16","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/878rc1707w.fsf@redhat.com/mbox/"},{"id":114709,"url":"https://patchwork.plctlab.org/api/1.2/patches/114709/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230630123259.1900571-1-i.swmail@xen0n.name/","msgid":"<20230630123259.1900571-1-i.swmail@xen0n.name>","list_archive_url":null,"date":"2023-06-30T12:32:59","name":"opcodes/loongarch: Mark address offset operands of LVZ/LBT insns as such","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230630123259.1900571-1-i.swmail@xen0n.name/mbox/"},{"id":114726,"url":"https://patchwork.plctlab.org/api/1.2/patches/114726/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230630134436.1237733-1-luis.machado@arm.com/","msgid":"<20230630134436.1237733-1-luis.machado@arm.com>","list_archive_url":null,"date":"2023-06-30T13:44:36","name":"[aarch64] sme: Core file support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230630134436.1237733-1-luis.machado@arm.com/mbox/"},{"id":114727,"url":"https://patchwork.plctlab.org/api/1.2/patches/114727/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230630134519.1237879-1-luis.machado@arm.com/","msgid":"<20230630134519.1237879-1-luis.machado@arm.com>","list_archive_url":null,"date":"2023-06-30T13:45:19","name":"[aarch64] sme2: Teach binutils/BFD about the NT_ARM_ZT register set","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230630134519.1237879-1-luis.machado@arm.com/mbox/"}],"public":true,"mbox":"https://patchwork.plctlab.org/bundle/patchwork-bot/binutils-gdb_2023-06/mbox/"},{"id":26,"url":"https://patchwork.plctlab.org/api/1.2/bundles/26/","web_url":"https://patchwork.plctlab.org/bundle/patchwork-bot/binutils-gdb_2023-07/","project":{"id":2,"url":"https://patchwork.plctlab.org/api/1.2/projects/2/","name":"binutils-gdb","link_name":"binutils-gdb","list_id":"binutils.sourceware.org","list_email":"binutils@sourceware.org","web_url":"https://github.com/wangliu-iscas/Patchwork-Bundles/blob/main/binutils-gdb.md","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"name":"binutils-gdb_2023-07","owner":{"id":3,"url":"https://patchwork.plctlab.org/api/1.2/users/3/","username":"patchwork-bot","first_name":"","last_name":"","email":"ouuuleilei@gmail.com"},"patches":[{"id":114893,"url":"https://patchwork.plctlab.org/api/1.2/patches/114893/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230630215725.3725876-2-christoph.muellner@vrull.eu/","msgid":"<20230630215725.3725876-2-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2023-06-30T21:57:11","name":"[v5,01/15] RISC-V: Add support for the Zvbb ISA extension","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230630215725.3725876-2-christoph.muellner@vrull.eu/mbox/"},{"id":114888,"url":"https://patchwork.plctlab.org/api/1.2/patches/114888/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230630215725.3725876-3-christoph.muellner@vrull.eu/","msgid":"<20230630215725.3725876-3-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2023-06-30T21:57:12","name":"[v5,02/15] RISC-V: Add support for the Zvbc extension","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230630215725.3725876-3-christoph.muellner@vrull.eu/mbox/"},{"id":114896,"url":"https://patchwork.plctlab.org/api/1.2/patches/114896/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230630215725.3725876-4-christoph.muellner@vrull.eu/","msgid":"<20230630215725.3725876-4-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2023-06-30T21:57:13","name":"[v5,03/15] RISC-V: Add support for the Zvkg ISA extension","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230630215725.3725876-4-christoph.muellner@vrull.eu/mbox/"},{"id":114889,"url":"https://patchwork.plctlab.org/api/1.2/patches/114889/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230630215725.3725876-5-christoph.muellner@vrull.eu/","msgid":"<20230630215725.3725876-5-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2023-06-30T21:57:14","name":"[v5,04/15] RISC-V: Add support for the Zvkned ISA extension","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230630215725.3725876-5-christoph.muellner@vrull.eu/mbox/"},{"id":114890,"url":"https://patchwork.plctlab.org/api/1.2/patches/114890/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230630215725.3725876-6-christoph.muellner@vrull.eu/","msgid":"<20230630215725.3725876-6-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2023-06-30T21:57:15","name":"[v5,05/15] RISC-V: Add support for the Zvknh[a, b] ISA extensions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230630215725.3725876-6-christoph.muellner@vrull.eu/mbox/"},{"id":114899,"url":"https://patchwork.plctlab.org/api/1.2/patches/114899/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230630215725.3725876-7-christoph.muellner@vrull.eu/","msgid":"<20230630215725.3725876-7-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2023-06-30T21:57:16","name":"[v5,06/15] RISC-V: Add support for the Zvksed ISA extension","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230630215725.3725876-7-christoph.muellner@vrull.eu/mbox/"},{"id":114892,"url":"https://patchwork.plctlab.org/api/1.2/patches/114892/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230630215725.3725876-8-christoph.muellner@vrull.eu/","msgid":"<20230630215725.3725876-8-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2023-06-30T21:57:17","name":"[v5,07/15] RISC-V: Add support for the Zvksh ISA extension","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230630215725.3725876-8-christoph.muellner@vrull.eu/mbox/"},{"id":114895,"url":"https://patchwork.plctlab.org/api/1.2/patches/114895/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230630215725.3725876-9-christoph.muellner@vrull.eu/","msgid":"<20230630215725.3725876-9-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2023-06-30T21:57:18","name":"[v5,08/15] RISC-V: Add support for the Zvkn ISA extension","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230630215725.3725876-9-christoph.muellner@vrull.eu/mbox/"},{"id":114901,"url":"https://patchwork.plctlab.org/api/1.2/patches/114901/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230630215725.3725876-10-christoph.muellner@vrull.eu/","msgid":"<20230630215725.3725876-10-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2023-06-30T21:57:19","name":"[v5,09/15] RISC-V: Allow nested implications for extensions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230630215725.3725876-10-christoph.muellner@vrull.eu/mbox/"},{"id":114894,"url":"https://patchwork.plctlab.org/api/1.2/patches/114894/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230630215725.3725876-11-christoph.muellner@vrull.eu/","msgid":"<20230630215725.3725876-11-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2023-06-30T21:57:20","name":"[v5,10/15] RISC-V: Add support for the Zvkng ISA extension","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230630215725.3725876-11-christoph.muellner@vrull.eu/mbox/"},{"id":114897,"url":"https://patchwork.plctlab.org/api/1.2/patches/114897/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230630215725.3725876-12-christoph.muellner@vrull.eu/","msgid":"<20230630215725.3725876-12-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2023-06-30T21:57:21","name":"[v5,11/15] RISC-V: Add support for the Zvks ISA extension","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230630215725.3725876-12-christoph.muellner@vrull.eu/mbox/"},{"id":114903,"url":"https://patchwork.plctlab.org/api/1.2/patches/114903/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230630215725.3725876-13-christoph.muellner@vrull.eu/","msgid":"<20230630215725.3725876-13-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2023-06-30T21:57:22","name":"[v5,12/15] RISC-V: Add support for the Zvksg ISA extension","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230630215725.3725876-13-christoph.muellner@vrull.eu/mbox/"},{"id":114898,"url":"https://patchwork.plctlab.org/api/1.2/patches/114898/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230630215725.3725876-14-christoph.muellner@vrull.eu/","msgid":"<20230630215725.3725876-14-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2023-06-30T21:57:23","name":"[v5,13/15] RISC-V: Add support for the Zvknc ISA extension","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230630215725.3725876-14-christoph.muellner@vrull.eu/mbox/"},{"id":114900,"url":"https://patchwork.plctlab.org/api/1.2/patches/114900/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230630215725.3725876-15-christoph.muellner@vrull.eu/","msgid":"<20230630215725.3725876-15-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2023-06-30T21:57:24","name":"[v5,14/15] RISC-V: Add support for the Zvksc ISA extension","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230630215725.3725876-15-christoph.muellner@vrull.eu/mbox/"},{"id":114902,"url":"https://patchwork.plctlab.org/api/1.2/patches/114902/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230630215725.3725876-16-christoph.muellner@vrull.eu/","msgid":"<20230630215725.3725876-16-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2023-06-30T21:57:25","name":"[v5,15/15] binutils: NEWS: Announce new RISC-V vector crypto extensions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230630215725.3725876-16-christoph.muellner@vrull.eu/mbox/"},{"id":114949,"url":"https://patchwork.plctlab.org/api/1.2/patches/114949/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230701052104.4018352-2-christoph.muellner@vrull.eu/","msgid":"<20230701052104.4018352-2-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2023-07-01T05:20:50","name":"[v6,01/15] RISC-V: Add support for the Zvbb ISA extension","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230701052104.4018352-2-christoph.muellner@vrull.eu/mbox/"},{"id":114952,"url":"https://patchwork.plctlab.org/api/1.2/patches/114952/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230701052104.4018352-3-christoph.muellner@vrull.eu/","msgid":"<20230701052104.4018352-3-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2023-07-01T05:20:51","name":"[v6,02/15] RISC-V: Add support for the Zvbc extension","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230701052104.4018352-3-christoph.muellner@vrull.eu/mbox/"},{"id":114955,"url":"https://patchwork.plctlab.org/api/1.2/patches/114955/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230701052104.4018352-4-christoph.muellner@vrull.eu/","msgid":"<20230701052104.4018352-4-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2023-07-01T05:20:52","name":"[v6,03/15] RISC-V: Add support for the Zvkg ISA extension","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230701052104.4018352-4-christoph.muellner@vrull.eu/mbox/"},{"id":114958,"url":"https://patchwork.plctlab.org/api/1.2/patches/114958/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230701052104.4018352-5-christoph.muellner@vrull.eu/","msgid":"<20230701052104.4018352-5-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2023-07-01T05:20:53","name":"[v6,04/15] RISC-V: Add support for the Zvkned ISA extension","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230701052104.4018352-5-christoph.muellner@vrull.eu/mbox/"},{"id":114953,"url":"https://patchwork.plctlab.org/api/1.2/patches/114953/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230701052104.4018352-6-christoph.muellner@vrull.eu/","msgid":"<20230701052104.4018352-6-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2023-07-01T05:20:54","name":"[v6,05/15] RISC-V: Add support for the Zvknh[a, b] ISA extensions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230701052104.4018352-6-christoph.muellner@vrull.eu/mbox/"},{"id":114950,"url":"https://patchwork.plctlab.org/api/1.2/patches/114950/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230701052104.4018352-7-christoph.muellner@vrull.eu/","msgid":"<20230701052104.4018352-7-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2023-07-01T05:20:55","name":"[v6,06/15] RISC-V: Add support for the Zvksed ISA extension","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230701052104.4018352-7-christoph.muellner@vrull.eu/mbox/"},{"id":114956,"url":"https://patchwork.plctlab.org/api/1.2/patches/114956/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230701052104.4018352-8-christoph.muellner@vrull.eu/","msgid":"<20230701052104.4018352-8-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2023-07-01T05:20:56","name":"[v6,07/15] RISC-V: Add support for the Zvksh ISA extension","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230701052104.4018352-8-christoph.muellner@vrull.eu/mbox/"},{"id":114954,"url":"https://patchwork.plctlab.org/api/1.2/patches/114954/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230701052104.4018352-9-christoph.muellner@vrull.eu/","msgid":"<20230701052104.4018352-9-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2023-07-01T05:20:57","name":"[v6,08/15] RISC-V: Add support for the Zvkn ISA extension","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230701052104.4018352-9-christoph.muellner@vrull.eu/mbox/"},{"id":114960,"url":"https://patchwork.plctlab.org/api/1.2/patches/114960/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230701052104.4018352-10-christoph.muellner@vrull.eu/","msgid":"<20230701052104.4018352-10-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2023-07-01T05:20:58","name":"[v6,09/15] RISC-V: Allow nested implications for extensions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230701052104.4018352-10-christoph.muellner@vrull.eu/mbox/"},{"id":114951,"url":"https://patchwork.plctlab.org/api/1.2/patches/114951/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230701052104.4018352-11-christoph.muellner@vrull.eu/","msgid":"<20230701052104.4018352-11-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2023-07-01T05:20:59","name":"[v6,10/15] RISC-V: Add support for the Zvkng ISA extension","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230701052104.4018352-11-christoph.muellner@vrull.eu/mbox/"},{"id":114962,"url":"https://patchwork.plctlab.org/api/1.2/patches/114962/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230701052104.4018352-12-christoph.muellner@vrull.eu/","msgid":"<20230701052104.4018352-12-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2023-07-01T05:21:00","name":"[v6,11/15] RISC-V: Add support for the Zvks ISA extension","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230701052104.4018352-12-christoph.muellner@vrull.eu/mbox/"},{"id":114957,"url":"https://patchwork.plctlab.org/api/1.2/patches/114957/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230701052104.4018352-13-christoph.muellner@vrull.eu/","msgid":"<20230701052104.4018352-13-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2023-07-01T05:21:01","name":"[v6,12/15] RISC-V: Add support for the Zvksg ISA extension","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230701052104.4018352-13-christoph.muellner@vrull.eu/mbox/"},{"id":114963,"url":"https://patchwork.plctlab.org/api/1.2/patches/114963/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230701052104.4018352-14-christoph.muellner@vrull.eu/","msgid":"<20230701052104.4018352-14-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2023-07-01T05:21:02","name":"[v6,13/15] RISC-V: Add support for the Zvknc ISA extension","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230701052104.4018352-14-christoph.muellner@vrull.eu/mbox/"},{"id":114961,"url":"https://patchwork.plctlab.org/api/1.2/patches/114961/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230701052104.4018352-15-christoph.muellner@vrull.eu/","msgid":"<20230701052104.4018352-15-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2023-07-01T05:21:03","name":"[v6,14/15] RISC-V: Add support for the Zvksc ISA extension","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230701052104.4018352-15-christoph.muellner@vrull.eu/mbox/"},{"id":114964,"url":"https://patchwork.plctlab.org/api/1.2/patches/114964/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230701052104.4018352-16-christoph.muellner@vrull.eu/","msgid":"<20230701052104.4018352-16-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2023-07-01T05:21:04","name":"[v6,15/15] binutils: NEWS: Announce new RISC-V vector crypto extensions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230701052104.4018352-16-christoph.muellner@vrull.eu/mbox/"},{"id":115075,"url":"https://patchwork.plctlab.org/api/1.2/patches/115075/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230702101422.762791-1-i.swmail@xen0n.name/","msgid":"<20230702101422.762791-1-i.swmail@xen0n.name>","list_archive_url":null,"date":"2023-07-02T10:14:22","name":"LoongArch: gas: Fix shared builds","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230702101422.762791-1-i.swmail@xen0n.name/mbox/"},{"id":115076,"url":"https://patchwork.plctlab.org/api/1.2/patches/115076/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/CAP2b4GOzcaewq1dZjnN5=jR-pZ4cRwvnCm=giYxKZ90zSGD85w@mail.gmail.com/","msgid":"","list_archive_url":null,"date":"2023-07-02T10:16:07","name":"Reimplement the .seh_scope directive","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/CAP2b4GOzcaewq1dZjnN5=jR-pZ4cRwvnCm=giYxKZ90zSGD85w@mail.gmail.com/mbox/"},{"id":115077,"url":"https://patchwork.plctlab.org/api/1.2/patches/115077/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/CAP2b4GN6AvihQ9W0ebCMgH1ozEvYKjb41Te9HfQg4k=e9ejhSw@mail.gmail.com/","msgid":"","list_archive_url":null,"date":"2023-07-02T10:18:31","name":"Reimplement the .seh_scope directive","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/CAP2b4GN6AvihQ9W0ebCMgH1ozEvYKjb41Te9HfQg4k=e9ejhSw@mail.gmail.com/mbox/"},{"id":115083,"url":"https://patchwork.plctlab.org/api/1.2/patches/115083/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230702111053.815399-1-i.swmail@xen0n.name/","msgid":"<20230702111053.815399-1-i.swmail@xen0n.name>","list_archive_url":null,"date":"2023-07-02T11:10:52","name":"[1/2] binutils: NEWS: Announce LoongArch changes in the 2.41 cycle","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230702111053.815399-1-i.swmail@xen0n.name/mbox/"},{"id":115082,"url":"https://patchwork.plctlab.org/api/1.2/patches/115082/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230702111053.815399-2-i.swmail@xen0n.name/","msgid":"<20230702111053.815399-2-i.swmail@xen0n.name>","list_archive_url":null,"date":"2023-07-02T11:10:53","name":"[2/2] gas: NEWS: Announce LoongArch changes in the 2.41 cycle","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230702111053.815399-2-i.swmail@xen0n.name/mbox/"},{"id":115188,"url":"https://patchwork.plctlab.org/api/1.2/patches/115188/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230703044321.2951358-1-yunqiang.su@cipunited.com/","msgid":"<20230703044321.2951358-1-yunqiang.su@cipunited.com>","list_archive_url":null,"date":"2023-07-03T04:43:21","name":"ld: fix plugin tests for MIPS PIC","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230703044321.2951358-1-yunqiang.su@cipunited.com/mbox/"},{"id":115284,"url":"https://patchwork.plctlab.org/api/1.2/patches/115284/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230703101047.2589341-1-christoph.muellner@vrull.eu/","msgid":"<20230703101047.2589341-1-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2023-07-03T10:10:47","name":"RISC-V: Zvkh[a,b]: Remove individual instruction class","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230703101047.2589341-1-christoph.muellner@vrull.eu/mbox/"},{"id":115301,"url":"https://patchwork.plctlab.org/api/1.2/patches/115301/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230703103647.3162351-1-yunqiang.su@cipunited.com/","msgid":"<20230703103647.3162351-1-yunqiang.su@cipunited.com>","list_archive_url":null,"date":"2023-07-03T10:36:47","name":"MIPS: Don'\''t __gnu_lto_slim to .scommon","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230703103647.3162351-1-yunqiang.su@cipunited.com/mbox/"},{"id":115305,"url":"https://patchwork.plctlab.org/api/1.2/patches/115305/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230703105034.3163572-1-yunqiang.su@cipunited.com/","msgid":"<20230703105034.3163572-1-yunqiang.su@cipunited.com>","list_archive_url":null,"date":"2023-07-03T10:50:34","name":"[v2] MIPS: Don'\''t move __gnu_lto_slim to .scommon","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230703105034.3163572-1-yunqiang.su@cipunited.com/mbox/"},{"id":115445,"url":"https://patchwork.plctlab.org/api/1.2/patches/115445/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230703181052.41059-1-krebbel@linux.ibm.com/","msgid":"<20230703181052.41059-1-krebbel@linux.ibm.com>","list_archive_url":null,"date":"2023-07-03T18:10:52","name":"[Committed] IBM Z: Fix pcrel relocs for symA-symB expressions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230703181052.41059-1-krebbel@linux.ibm.com/mbox/"},{"id":115692,"url":"https://patchwork.plctlab.org/api/1.2/patches/115692/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230704102703.650038-1-claziss@gmail.com/","msgid":"<20230704102703.650038-1-claziss@gmail.com>","list_archive_url":null,"date":"2023-07-04T10:27:02","name":"[committed,1/2] arc: Update neg<.f> 0,b encoding","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230704102703.650038-1-claziss@gmail.com/mbox/"},{"id":115691,"url":"https://patchwork.plctlab.org/api/1.2/patches/115691/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230704102703.650038-2-claziss@gmail.com/","msgid":"<20230704102703.650038-2-claziss@gmail.com>","list_archive_url":null,"date":"2023-07-04T10:27:03","name":"[committed,2/2] arc: Update default target CPU to match GCC defaults","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230704102703.650038-2-claziss@gmail.com/mbox/"},{"id":115742,"url":"https://patchwork.plctlab.org/api/1.2/patches/115742/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230704121832.222400-1-krebbel@linux.ibm.com/","msgid":"<20230704121832.222400-1-krebbel@linux.ibm.com>","list_archive_url":null,"date":"2023-07-04T12:18:32","name":"Align linkerscript symbols according to ABI","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230704121832.222400-1-krebbel@linux.ibm.com/mbox/"},{"id":115827,"url":"https://patchwork.plctlab.org/api/1.2/patches/115827/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e098654c-98dd-1b2f-e876-6ba910260492@suse.com/","msgid":"","list_archive_url":null,"date":"2023-07-04T15:18:32","name":"[01/10] x86: fold certain legacy/VEX table entries","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e098654c-98dd-1b2f-e876-6ba910260492@suse.com/mbox/"},{"id":115828,"url":"https://patchwork.plctlab.org/api/1.2/patches/115828/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/18221c8c-4d6e-f0f1-3738-785023be1268@suse.com/","msgid":"<18221c8c-4d6e-f0f1-3738-785023be1268@suse.com>","list_archive_url":null,"date":"2023-07-04T15:19:53","name":"[02/10] x86: fold legacy/VEX {,V}MOV{H,L}* entries","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/18221c8c-4d6e-f0f1-3738-785023be1268@suse.com/mbox/"},{"id":115829,"url":"https://patchwork.plctlab.org/api/1.2/patches/115829/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/46594eee-305a-8913-c407-806158fbbe8f@suse.com/","msgid":"<46594eee-305a-8913-c407-806158fbbe8f@suse.com>","list_archive_url":null,"date":"2023-07-04T15:20:35","name":"[03/10] x86: {,V}MOVNT* don'\''t need to go through mod_table[]","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/46594eee-305a-8913-c407-806158fbbe8f@suse.com/mbox/"},{"id":115830,"url":"https://patchwork.plctlab.org/api/1.2/patches/115830/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/02a1aabf-4759-009b-5718-f567ed39b81c@suse.com/","msgid":"<02a1aabf-4759-009b-5718-f567ed39b81c@suse.com>","list_archive_url":null,"date":"2023-07-04T15:21:02","name":"[04/10] x86: misc further memory-only insns don'\''t need to go through mod_table[]","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/02a1aabf-4759-009b-5718-f567ed39b81c@suse.com/mbox/"},{"id":115832,"url":"https://patchwork.plctlab.org/api/1.2/patches/115832/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/96a500b4-1b68-520b-bccc-01d78f8e6f6c@suse.com/","msgid":"<96a500b4-1b68-520b-bccc-01d78f8e6f6c@suse.com>","list_archive_url":null,"date":"2023-07-04T15:21:38","name":"[05/10] x86: SIMD shift-by-immediate don'\''t need to go through mod_table[]","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/96a500b4-1b68-520b-bccc-01d78f8e6f6c@suse.com/mbox/"},{"id":115834,"url":"https://patchwork.plctlab.org/api/1.2/patches/115834/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d9842149-1c2b-2ff9-531d-87cae64e4b78@suse.com/","msgid":"","list_archive_url":null,"date":"2023-07-04T15:22:06","name":"[06/10] x86: slightly rework handling of some register-only insns","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d9842149-1c2b-2ff9-531d-87cae64e4b78@suse.com/mbox/"},{"id":115835,"url":"https://patchwork.plctlab.org/api/1.2/patches/115835/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/25535360-ad14-8ed2-bd86-b96f97306e43@suse.com/","msgid":"<25535360-ad14-8ed2-bd86-b96f97306e43@suse.com>","list_archive_url":null,"date":"2023-07-04T15:22:31","name":"[07/10] x86: various operations on mask registers can avoid going through mod_table[]","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/25535360-ad14-8ed2-bd86-b96f97306e43@suse.com/mbox/"},{"id":115833,"url":"https://patchwork.plctlab.org/api/1.2/patches/115833/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/54b1c54f-ddad-4d5a-f5d0-e585cd3aaa3e@suse.com/","msgid":"<54b1c54f-ddad-4d5a-f5d0-e585cd3aaa3e@suse.com>","list_archive_url":null,"date":"2023-07-04T15:22:59","name":"[08/10] x86: misc further register-only insns don'\''t need to go through mod_table[]","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/54b1c54f-ddad-4d5a-f5d0-e585cd3aaa3e@suse.com/mbox/"},{"id":115837,"url":"https://patchwork.plctlab.org/api/1.2/patches/115837/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ec881a0e-05b2-556b-8e21-a1c38429e465@suse.com/","msgid":"","list_archive_url":null,"date":"2023-07-04T15:23:25","name":"[09/10] x86: convert 0FXOP to just XOP in enumerator names","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ec881a0e-05b2-556b-8e21-a1c38429e465@suse.com/mbox/"},{"id":115836,"url":"https://patchwork.plctlab.org/api/1.2/patches/115836/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/126aeaee-40ae-34aa-5e30-9579264d6336@suse.com/","msgid":"<126aeaee-40ae-34aa-5e30-9579264d6336@suse.com>","list_archive_url":null,"date":"2023-07-04T15:24:08","name":"[10/10] x86: simplify table-referencing macros","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/126aeaee-40ae-34aa-5e30-9579264d6336@suse.com/mbox/"},{"id":116027,"url":"https://patchwork.plctlab.org/api/1.2/patches/116027/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230705084213.91043-1-lidie@eswincomputing.com/","msgid":"<20230705084213.91043-1-lidie@eswincomputing.com>","list_archive_url":null,"date":"2023-07-05T08:42:13","name":"[RISC-V] Fix the valid gp range for gp relax.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230705084213.91043-1-lidie@eswincomputing.com/mbox/"},{"id":116978,"url":"https://patchwork.plctlab.org/api/1.2/patches/116978/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230707054306.2810080-1-maskray@google.com/","msgid":"<20230707054306.2810080-1-maskray@google.com>","list_archive_url":null,"date":"2023-07-07T05:43:06","name":"[v3] PR30592 objcopy: allow --set-section-flags to add or remove SHF_X86_64_LARGE","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230707054306.2810080-1-maskray@google.com/mbox/"},{"id":117059,"url":"https://patchwork.plctlab.org/api/1.2/patches/117059/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230707101024.2863421-1-claziss@gmail.com/","msgid":"<20230707101024.2863421-1-claziss@gmail.com>","list_archive_url":null,"date":"2023-07-07T10:10:24","name":"[committed] arc: Update/Add ARCv3 support.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230707101024.2863421-1-claziss@gmail.com/mbox/"},{"id":117125,"url":"https://patchwork.plctlab.org/api/1.2/patches/117125/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d8cb6772-092f-b79e-421b-1da61ce020ac@suse.com/","msgid":"","list_archive_url":null,"date":"2023-07-07T12:01:07","name":"ld: fix build with old glibc / gcc","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d8cb6772-092f-b79e-421b-1da61ce020ac@suse.com/mbox/"},{"id":117135,"url":"https://patchwork.plctlab.org/api/1.2/patches/117135/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/88c2fb96-185d-ae27-c025-ed025ed54641@suse.com/","msgid":"<88c2fb96-185d-ae27-c025-ed025ed54641@suse.com>","list_archive_url":null,"date":"2023-07-07T13:47:35","name":"ld/PDB: fix off-by-1 in add_globals_ref()","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/88c2fb96-185d-ae27-c025-ed025ed54641@suse.com/mbox/"},{"id":117306,"url":"https://patchwork.plctlab.org/api/1.2/patches/117306/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/878rbrgzoz.fsf@gmail.com/","msgid":"<878rbrgzoz.fsf@gmail.com>","list_archive_url":null,"date":"2023-07-07T21:47:48","name":"objdump: Round ASCII art lines in jump visualization","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/878rbrgzoz.fsf@gmail.com/mbox/"},{"id":117387,"url":"https://patchwork.plctlab.org/api/1.2/patches/117387/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230708053035.528911-1-maskray@google.com/","msgid":"<20230708053035.528911-1-maskray@google.com>","list_archive_url":null,"date":"2023-07-08T05:30:35","name":"[v4] PR30592 objcopy: allow --set-section-flags to add or remove SHF_X86_64_LARGE","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230708053035.528911-1-maskray@google.com/mbox/"},{"id":118315,"url":"https://patchwork.plctlab.org/api/1.2/patches/118315/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230711083214.689474-1-jiawei@iscas.ac.cn/","msgid":"<20230711083214.689474-1-jiawei@iscas.ac.cn>","list_archive_url":null,"date":"2023-07-11T08:32:14","name":"[v2] RISC-V: Support Zca/f/d extensions.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230711083214.689474-1-jiawei@iscas.ac.cn/mbox/"},{"id":118324,"url":"https://patchwork.plctlab.org/api/1.2/patches/118324/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230711084931.18978-1-hejinyang@loongson.cn/","msgid":"<20230711084931.18978-1-hejinyang@loongson.cn>","list_archive_url":null,"date":"2023-07-11T08:49:30","name":"[1/2] LoongArch: bfd: Remove elf_seg_map condition in loongarch_elf_relax_section","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230711084931.18978-1-hejinyang@loongson.cn/mbox/"},{"id":118325,"url":"https://patchwork.plctlab.org/api/1.2/patches/118325/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230711084931.18978-2-hejinyang@loongson.cn/","msgid":"<20230711084931.18978-2-hejinyang@loongson.cn>","list_archive_url":null,"date":"2023-07-11T08:49:31","name":"[2/2] LoongArch: bfd: Add counter to get real relax region","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230711084931.18978-2-hejinyang@loongson.cn/mbox/"},{"id":118766,"url":"https://patchwork.plctlab.org/api/1.2/patches/118766/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZK4EFMJYmIzmJnh5@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-07-12T01:38:28","name":".noinit and .persistent alignment","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZK4EFMJYmIzmJnh5@squeak.grove.modra.org/mbox/"},{"id":118767,"url":"https://patchwork.plctlab.org/api/1.2/patches/118767/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZK4EZ3/IKANDAvI0@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-07-12T01:39:51","name":".noinit and .persistent for msp430","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZK4EZ3/IKANDAvI0@squeak.grove.modra.org/mbox/"},{"id":118801,"url":"https://patchwork.plctlab.org/api/1.2/patches/118801/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZK4j+R81iVz44wvm@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-07-12T03:54:33","name":"Support NEXT_SECTION in ALIGNOF and SIZEOF","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZK4j+R81iVz44wvm@squeak.grove.modra.org/mbox/"},{"id":119149,"url":"https://patchwork.plctlab.org/api/1.2/patches/119149/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230712124036.3385283-1-jiawei@iscas.ac.cn/","msgid":"<20230712124036.3385283-1-jiawei@iscas.ac.cn>","list_archive_url":null,"date":"2023-07-12T12:40:36","name":"[v2] RISC-V: Supports Zcb extension.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230712124036.3385283-1-jiawei@iscas.ac.cn/mbox/"},{"id":119190,"url":"https://patchwork.plctlab.org/api/1.2/patches/119190/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.LSU.2.20.2307121351250.13548@wotan.suse.de/","msgid":"","list_archive_url":null,"date":"2023-07-12T13:56:54","name":"Let '\''^'\'' through the lexer","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.LSU.2.20.2307121351250.13548@wotan.suse.de/mbox/"},{"id":119481,"url":"https://patchwork.plctlab.org/api/1.2/patches/119481/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/62b68369-0d02-3472-bbe6-cb627661252e@oracle.com/","msgid":"<62b68369-0d02-3472-bbe6-cb627661252e@oracle.com>","list_archive_url":null,"date":"2023-07-13T02:35:06","name":"Patch for version.texi?","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/62b68369-0d02-3472-bbe6-cb627661252e@oracle.com/mbox/"},{"id":119567,"url":"https://patchwork.plctlab.org/api/1.2/patches/119567/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230713063303.205862-2-haochen.jiang@intel.com/","msgid":"<20230713063303.205862-2-haochen.jiang@intel.com>","list_archive_url":null,"date":"2023-07-13T06:32:59","name":"[1/5] Support Intel AVX-VNNI-INT16","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230713063303.205862-2-haochen.jiang@intel.com/mbox/"},{"id":119565,"url":"https://patchwork.plctlab.org/api/1.2/patches/119565/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230713063303.205862-3-haochen.jiang@intel.com/","msgid":"<20230713063303.205862-3-haochen.jiang@intel.com>","list_archive_url":null,"date":"2023-07-13T06:33:00","name":"[2/5] Support Intel SHA512","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230713063303.205862-3-haochen.jiang@intel.com/mbox/"},{"id":119563,"url":"https://patchwork.plctlab.org/api/1.2/patches/119563/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230713063303.205862-4-haochen.jiang@intel.com/","msgid":"<20230713063303.205862-4-haochen.jiang@intel.com>","list_archive_url":null,"date":"2023-07-13T06:33:01","name":"[3/5] Support Intel SM3","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230713063303.205862-4-haochen.jiang@intel.com/mbox/"},{"id":119566,"url":"https://patchwork.plctlab.org/api/1.2/patches/119566/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230713063303.205862-5-haochen.jiang@intel.com/","msgid":"<20230713063303.205862-5-haochen.jiang@intel.com>","list_archive_url":null,"date":"2023-07-13T06:33:02","name":"[4/5] Support Intel SM4","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230713063303.205862-5-haochen.jiang@intel.com/mbox/"},{"id":119562,"url":"https://patchwork.plctlab.org/api/1.2/patches/119562/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230713063303.205862-6-haochen.jiang@intel.com/","msgid":"<20230713063303.205862-6-haochen.jiang@intel.com>","list_archive_url":null,"date":"2023-07-13T06:33:03","name":"[5/5] Support Intel PBNDKB","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230713063303.205862-6-haochen.jiang@intel.com/mbox/"},{"id":119993,"url":"https://patchwork.plctlab.org/api/1.2/patches/119993/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230713153738.2638727-1-vladimir.mezentsev@oracle.com/","msgid":"<20230713153738.2638727-1-vladimir.mezentsev@oracle.com>","list_archive_url":null,"date":"2023-07-13T15:37:38","name":"gprofng: 30602 [2.41] gprofng test hangs on i686-linux-gnu","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230713153738.2638727-1-vladimir.mezentsev@oracle.com/mbox/"},{"id":120205,"url":"https://patchwork.plctlab.org/api/1.2/patches/120205/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZLDCUfzWq0bZSyB4@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-07-14T03:34:41","name":"AIX_WEAK_SUPPORT","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZLDCUfzWq0bZSyB4@squeak.grove.modra.org/mbox/"},{"id":120206,"url":"https://patchwork.plctlab.org/api/1.2/patches/120206/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZLDCeFLsD6g+d1sB@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-07-14T03:35:20","name":"More tidies to objcopy archive handling","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZLDCeFLsD6g+d1sB@squeak.grove.modra.org/mbox/"},{"id":120207,"url":"https://patchwork.plctlab.org/api/1.2/patches/120207/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZLDClMEw/UQCGSPZ@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-07-14T03:35:48","name":"Fix loongarch build with gcc-4.5","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZLDClMEw/UQCGSPZ@squeak.grove.modra.org/mbox/"},{"id":120208,"url":"https://patchwork.plctlab.org/api/1.2/patches/120208/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZLDC03FCE+2lGiIo@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-07-14T03:36:51","name":"Make the default gas symbol hash table larger","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZLDC03FCE+2lGiIo@squeak.grove.modra.org/mbox/"},{"id":120326,"url":"https://patchwork.plctlab.org/api/1.2/patches/120326/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2350928d-ed93-91ed-8bcd-fce9902914b1@codesourcery.com/","msgid":"<2350928d-ed93-91ed-8bcd-fce9902914b1@codesourcery.com>","list_archive_url":null,"date":"2023-07-14T08:22:56","name":"'\''make pdf'\'' fails due to: [PATCH] Let '\''^'\'' through the lexer]","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2350928d-ed93-91ed-8bcd-fce9902914b1@codesourcery.com/mbox/"},{"id":120394,"url":"https://patchwork.plctlab.org/api/1.2/patches/120394/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/40ab94c5-d0c4-ee01-a53b-dbc6e5f3f9d2@suse.com/","msgid":"<40ab94c5-d0c4-ee01-a53b-dbc6e5f3f9d2@suse.com>","list_archive_url":null,"date":"2023-07-14T10:02:17","name":"[1/2] x86: simplify disassembly of LAR/LSL","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/40ab94c5-d0c4-ee01-a53b-dbc6e5f3f9d2@suse.com/mbox/"},{"id":120395,"url":"https://patchwork.plctlab.org/api/1.2/patches/120395/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7cc1eda0-713d-9172-c3ed-078e0899b0c4@suse.com/","msgid":"<7cc1eda0-713d-9172-c3ed-078e0899b0c4@suse.com>","list_archive_url":null,"date":"2023-07-14T10:02:39","name":"[2/2] x86: adjust disassembly of insns operating on selector values","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7cc1eda0-713d-9172-c3ed-078e0899b0c4@suse.com/mbox/"},{"id":120981,"url":"https://patchwork.plctlab.org/api/1.2/patches/120981/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZLR4TfHSewLy67fu@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-07-16T23:07:57","name":"PR10957, Missing option to really print section+offset","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZLR4TfHSewLy67fu@squeak.grove.modra.org/mbox/"},{"id":121117,"url":"https://patchwork.plctlab.org/api/1.2/patches/121117/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230717082229.2149099-1-mengqinggang@loongson.cn/","msgid":"<20230717082229.2149099-1-mengqinggang@loongson.cn>","list_archive_url":null,"date":"2023-07-17T08:22:28","name":"[1/2] LoongArch: Fix instruction immediate bug caused by sign-extend","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230717082229.2149099-1-mengqinggang@loongson.cn/mbox/"},{"id":121118,"url":"https://patchwork.plctlab.org/api/1.2/patches/121118/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230717082229.2149099-2-mengqinggang@loongson.cn/","msgid":"<20230717082229.2149099-2-mengqinggang@loongson.cn>","list_archive_url":null,"date":"2023-07-17T08:22:29","name":"[2/2] LoongArch: Fix immediate overflow check bug","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230717082229.2149099-2-mengqinggang@loongson.cn/mbox/"},{"id":121130,"url":"https://patchwork.plctlab.org/api/1.2/patches/121130/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230717084146.7978-1-tdevries@suse.de/","msgid":"<20230717084146.7978-1-tdevries@suse.de>","list_archive_url":null,"date":"2023-07-17T08:41:46","name":"[gdb/build] Fix Wlto-type-mismatch in opcodes/ft32-dis.c","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230717084146.7978-1-tdevries@suse.de/mbox/"},{"id":121835,"url":"https://patchwork.plctlab.org/api/1.2/patches/121835/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230718075412.1304548-1-haochen.jiang@intel.com/","msgid":"<20230718075412.1304548-1-haochen.jiang@intel.com>","list_archive_url":null,"date":"2023-07-18T07:54:12","name":"[v2] Support Intel SHA512","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230718075412.1304548-1-haochen.jiang@intel.com/mbox/"},{"id":121848,"url":"https://patchwork.plctlab.org/api/1.2/patches/121848/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230718080915.1391780-1-haochen.jiang@intel.com/","msgid":"<20230718080915.1391780-1-haochen.jiang@intel.com>","list_archive_url":null,"date":"2023-07-18T08:09:15","name":"[v2] Support Intel SM3","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230718080915.1391780-1-haochen.jiang@intel.com/mbox/"},{"id":121854,"url":"https://patchwork.plctlab.org/api/1.2/patches/121854/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230718081358.1394673-1-haochen.jiang@intel.com/","msgid":"<20230718081358.1394673-1-haochen.jiang@intel.com>","list_archive_url":null,"date":"2023-07-18T08:13:58","name":"[v2] Support Intel SM4","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230718081358.1394673-1-haochen.jiang@intel.com/mbox/"},{"id":122353,"url":"https://patchwork.plctlab.org/api/1.2/patches/122353/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZLc+98Th9pmqLTGc@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-07-19T01:40:07","name":"gas 32-bit host compile warnings","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZLc+98Th9pmqLTGc@squeak.grove.modra.org/mbox/"},{"id":122354,"url":"https://patchwork.plctlab.org/api/1.2/patches/122354/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZLc/HcP8ynwWNpO3@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-07-19T01:40:45","name":"Build all the objdump extensions with --enable-targets=all","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZLc/HcP8ynwWNpO3@squeak.grove.modra.org/mbox/"},{"id":122355,"url":"https://patchwork.plctlab.org/api/1.2/patches/122355/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZLc/RaA7zPjQQ2Sl@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-07-19T01:41:25","name":"Tidy binutils configure","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZLc/RaA7zPjQQ2Sl@squeak.grove.modra.org/mbox/"},{"id":122356,"url":"https://patchwork.plctlab.org/api/1.2/patches/122356/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZLc/ckC/wa90hisa@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-07-19T01:42:10","name":"[GOLD,PowerPC64] Debug info relocation overflow","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZLc/ckC/wa90hisa@squeak.grove.modra.org/mbox/"},{"id":122359,"url":"https://patchwork.plctlab.org/api/1.2/patches/122359/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230719021721.776961-1-mengqinggang@loongson.cn/","msgid":"<20230719021721.776961-1-mengqinggang@loongson.cn>","list_archive_url":null,"date":"2023-07-19T02:17:21","name":"LoongArch: ld: Simplify inserting IRELATIVE relocations to .rela.dyn","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230719021721.776961-1-mengqinggang@loongson.cn/mbox/"},{"id":122541,"url":"https://patchwork.plctlab.org/api/1.2/patches/122541/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0c22e147-aa0c-12ae-24e0-4f770948054d@debian.org/","msgid":"<0c22e147-aa0c-12ae-24e0-4f770948054d@debian.org>","list_archive_url":null,"date":"2023-07-19T10:54:58","name":"objcopy embeds the current time and ignores SOURCE_DATE_EPOCH making the output unreproducible","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0c22e147-aa0c-12ae-24e0-4f770948054d@debian.org/mbox/"},{"id":123087,"url":"https://patchwork.plctlab.org/api/1.2/patches/123087/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230720083213.2280286-1-haochen.jiang@intel.com/","msgid":"<20230720083213.2280286-1-haochen.jiang@intel.com>","list_archive_url":null,"date":"2023-07-20T08:32:13","name":"Support Intel SHA512","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230720083213.2280286-1-haochen.jiang@intel.com/mbox/"},{"id":123319,"url":"https://patchwork.plctlab.org/api/1.2/patches/123319/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/efa3944b8dddd45e171baa8c3939e8636ab2d6b8.camel@espressif.com/","msgid":"","list_archive_url":null,"date":"2023-07-20T14:39:14","name":"xtensa: add dynconfig option for ld/gas","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/efa3944b8dddd45e171baa8c3939e8636ab2d6b8.camel@espressif.com/mbox/"},{"id":123564,"url":"https://patchwork.plctlab.org/api/1.2/patches/123564/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230721053218.16817-1-hau.hsu@sifive.com/","msgid":"<20230721053218.16817-1-hau.hsu@sifive.com>","list_archive_url":null,"date":"2023-07-21T05:32:18","name":"RISC-V: Fix wrongly inserted IRELATIVE relocs","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230721053218.16817-1-hau.hsu@sifive.com/mbox/"},{"id":123611,"url":"https://patchwork.plctlab.org/api/1.2/patches/123611/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/32719c54-c66a-384e-d570-ebefe607e3e9@suse.com/","msgid":"<32719c54-c66a-384e-d570-ebefe607e3e9@suse.com>","list_archive_url":null,"date":"2023-07-21T07:12:50","name":"[RFC] x86: pack CPU flags in opcode table","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/32719c54-c66a-384e-d570-ebefe607e3e9@suse.com/mbox/"},{"id":123632,"url":"https://patchwork.plctlab.org/api/1.2/patches/123632/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230721074956.7188-2-piannetta@kalrayinc.com/","msgid":"<20230721074956.7188-2-piannetta@kalrayinc.com>","list_archive_url":null,"date":"2023-07-21T07:49:50","name":"[1/7] kvx: Add bf files.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230721074956.7188-2-piannetta@kalrayinc.com/mbox/"},{"id":123627,"url":"https://patchwork.plctlab.org/api/1.2/patches/123627/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230721074956.7188-3-piannetta@kalrayinc.com/","msgid":"<20230721074956.7188-3-piannetta@kalrayinc.com>","list_archive_url":null,"date":"2023-07-21T07:49:51","name":"[2/7] kvx: Add binutils files.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230721074956.7188-3-piannetta@kalrayinc.com/mbox/"},{"id":123629,"url":"https://patchwork.plctlab.org/api/1.2/patches/123629/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230721074956.7188-5-piannetta@kalrayinc.com/","msgid":"<20230721074956.7188-5-piannetta@kalrayinc.com>","list_archive_url":null,"date":"2023-07-21T07:49:53","name":"[4/7] kvx: Add ld files.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230721074956.7188-5-piannetta@kalrayinc.com/mbox/"},{"id":123635,"url":"https://patchwork.plctlab.org/api/1.2/patches/123635/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230721074956.7188-6-piannetta@kalrayinc.com/","msgid":"<20230721074956.7188-6-piannetta@kalrayinc.com>","list_archive_url":null,"date":"2023-07-21T07:49:54","name":"[5/7] kvx: Add include files.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230721074956.7188-6-piannetta@kalrayinc.com/mbox/"},{"id":123631,"url":"https://patchwork.plctlab.org/api/1.2/patches/123631/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230721074956.7188-8-piannetta@kalrayinc.com/","msgid":"<20230721074956.7188-8-piannetta@kalrayinc.com>","list_archive_url":null,"date":"2023-07-21T07:49:56","name":"[7/7] kvx: Add toplevel files.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230721074956.7188-8-piannetta@kalrayinc.com/mbox/"}],"public":true,"mbox":"https://patchwork.plctlab.org/bundle/patchwork-bot/binutils-gdb_2023-07/mbox/"}]' ++ jq -rc '.[].name' ++ echo '[{"id":6,"url":"https://patchwork.plctlab.org/api/1.2/bundles/6/","web_url":"https://patchwork.plctlab.org/bundle/patchwork-bot/binutils-gdb_2022-10/","project":{"id":2,"url":"https://patchwork.plctlab.org/api/1.2/projects/2/","name":"binutils-gdb","link_name":"binutils-gdb","list_id":"binutils.sourceware.org","list_email":"binutils@sourceware.org","web_url":"https://github.com/wangliu-iscas/Patchwork-Bundles/blob/main/binutils-gdb.md","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"name":"binutils-gdb_2022-10","owner":{"id":3,"url":"https://patchwork.plctlab.org/api/1.2/users/3/","username":"patchwork-bot","first_name":"","last_name":"","email":"ouuuleilei@gmail.com"},"patches":[{"id":1592,"url":"https://patchwork.plctlab.org/api/1.2/patches/1592/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/385d01fd-7e57-1f3f-1bae-30aa0c313d63@suse.com/","msgid":"<385d01fd-7e57-1f3f-1bae-30aa0c313d63@suse.com>","list_archive_url":null,"date":"2022-09-30T11:59:45","name":"[3/4] RISC-V/gas: don'\''t open-code insn_length()","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/385d01fd-7e57-1f3f-1bae-30aa0c313d63@suse.com/mbox/"},{"id":1594,"url":"https://patchwork.plctlab.org/api/1.2/patches/1594/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f5757acf-7b90-a0e3-5eea-3b97cc226930@suse.com/","msgid":"","list_archive_url":null,"date":"2022-09-30T12:00:12","name":"[4/4] RISC-V/gas: allow generating up to 176-bit instructions with .insn","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f5757acf-7b90-a0e3-5eea-3b97cc226930@suse.com/mbox/"},{"id":1596,"url":"https://patchwork.plctlab.org/api/1.2/patches/1596/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930140503.38233-1-chigot@adacore.com/","msgid":"<20220930140503.38233-1-chigot@adacore.com>","list_archive_url":null,"date":"2022-09-30T14:05:03","name":"ld/testsuite: consistently add board_ldflags when linking with GCC","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930140503.38233-1-chigot@adacore.com/mbox/"},{"id":1619,"url":"https://patchwork.plctlab.org/api/1.2/patches/1619/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221001014451.532772-1-maskray@google.com/","msgid":"<20221001014451.532772-1-maskray@google.com>","list_archive_url":null,"date":"2022-10-01T01:44:51","name":"gold, dwp: support zstd compressed input debug sections [PR 29641]","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221001014451.532772-1-maskray@google.com/mbox/"},{"id":1620,"url":"https://patchwork.plctlab.org/api/1.2/patches/1620/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221001023846.590825-1-maskray@google.com/","msgid":"<20221001023846.590825-1-maskray@google.com>","list_archive_url":null,"date":"2022-10-01T02:38:46","name":"gold: add --compress-debug-sections=zstd [PR 29641]","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221001023846.590825-1-maskray@google.com/mbox/"},{"id":1623,"url":"https://patchwork.plctlab.org/api/1.2/patches/1623/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b4477c7f666bdeb7f8e998633c7b0cb62310b9ef.1664599545.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-01T04:45:52","name":"[RFC,1/1] RISC-V: Implement common register pair framework","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b4477c7f666bdeb7f8e998633c7b0cb62310b9ef.1664599545.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1625,"url":"https://patchwork.plctlab.org/api/1.2/patches/1625/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/53a265a1f14d17a6f7b106082f610994c5d546e0.1664602025.git.research_trasio@irq.a4lg.com/","msgid":"<53a265a1f14d17a6f7b106082f610994c5d546e0.1664602025.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-01T05:27:31","name":"[RFC,1/1] RISC-V: Implement extension variants","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/53a265a1f14d17a6f7b106082f610994c5d546e0.1664602025.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1626,"url":"https://patchwork.plctlab.org/api/1.2/patches/1626/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8db04962aba9c780f133840a8934353a58f223fe.1664602716.git.research_trasio@irq.a4lg.com/","msgid":"<8db04962aba9c780f133840a8934353a58f223fe.1664602716.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-01T05:39:26","name":"[1/1] RISC-V: Move supervisor instructions after all unprivileged ones","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8db04962aba9c780f133840a8934353a58f223fe.1664602716.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1627,"url":"https://patchwork.plctlab.org/api/1.2/patches/1627/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221001062057.681440-1-maskray@google.com/","msgid":"<20221001062057.681440-1-maskray@google.com>","list_archive_url":null,"date":"2022-10-01T06:20:57","name":"readelf: support zstd compressed debug sections [PR 29640]","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221001062057.681440-1-maskray@google.com/mbox/"},{"id":1631,"url":"https://patchwork.plctlab.org/api/1.2/patches/1631/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/619f112539c0bdecd58e25664f1250a3479a37f5.1664707612.git.aburgess@redhat.com/","msgid":"<619f112539c0bdecd58e25664f1250a3479a37f5.1664707612.git.aburgess@redhat.com>","list_archive_url":null,"date":"2022-10-02T10:47:52","name":"[PATCHv2,2/2] opcodes/arm: add disassembler styling for arm","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/619f112539c0bdecd58e25664f1250a3479a37f5.1664707612.git.aburgess@redhat.com/mbox/"},{"id":1635,"url":"https://patchwork.plctlab.org/api/1.2/patches/1635/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221002185433.gl7dvytfh5wthifx@lug-owl.de/","msgid":"<20221002185433.gl7dvytfh5wthifx@lug-owl.de>","list_archive_url":null,"date":"2022-10-02T18:54:33","name":"diagnostics.h: GCC 13 got -Wself-move, breaks GDB build","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221002185433.gl7dvytfh5wthifx@lug-owl.de/mbox/"},{"id":1637,"url":"https://patchwork.plctlab.org/api/1.2/patches/1637/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003014313.28766-1-mark@harmstone.com/","msgid":"<20221003014313.28766-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-03T01:43:12","name":"[1/2] ld: Add --pdb option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003014313.28766-1-mark@harmstone.com/mbox/"},{"id":1638,"url":"https://patchwork.plctlab.org/api/1.2/patches/1638/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003014313.28766-2-mark@harmstone.com/","msgid":"<20221003014313.28766-2-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-03T01:43:13","name":"[2/2] ld: Add minimal pdb generation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003014313.28766-2-mark@harmstone.com/mbox/"},{"id":1640,"url":"https://patchwork.plctlab.org/api/1.2/patches/1640/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/597ed978-d121-220c-b56b-2ffb94bd091c@suse.cz/","msgid":"<597ed978-d121-220c-b56b-2ffb94bd091c@suse.cz>","list_archive_url":null,"date":"2022-10-03T07:50:38","name":"[1/2] refactor usage of compressed_debug_section_type","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/597ed978-d121-220c-b56b-2ffb94bd091c@suse.cz/mbox/"},{"id":1641,"url":"https://patchwork.plctlab.org/api/1.2/patches/1641/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b8acdd83-f33a-74b8-e21a-23719a0b1a60@suse.cz/","msgid":"","list_archive_url":null,"date":"2022-10-03T07:50:44","name":"[2/2] add --enable-default-compressed-debug-sections-algorithm configure option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b8acdd83-f33a-74b8-e21a-23719a0b1a60@suse.cz/mbox/"},{"id":1642,"url":"https://patchwork.plctlab.org/api/1.2/patches/1642/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003101328.1790113-1-aburgess@redhat.com/","msgid":"<20221003101328.1790113-1-aburgess@redhat.com>","list_archive_url":null,"date":"2022-10-03T10:13:28","name":"opcodes/riscv: style csr names as registers","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003101328.1790113-1-aburgess@redhat.com/mbox/"},{"id":1643,"url":"https://patchwork.plctlab.org/api/1.2/patches/1643/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7ba14fc4472ce97d4f7a4433cad8a571e89f82f4.1664793840.git.research_trasio@irq.a4lg.com/","msgid":"<7ba14fc4472ce97d4f7a4433cad8a571e89f82f4.1664793840.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-03T10:43:59","name":"[v3,1/6] RISC-V: Fix immediates to have \"immediate\" style","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7ba14fc4472ce97d4f7a4433cad8a571e89f82f4.1664793840.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1644,"url":"https://patchwork.plctlab.org/api/1.2/patches/1644/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a498bec37c1fd1dcda57cbf95e5f8cfba09b31d3.1664793840.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-03T10:44:00","name":"[v3,2/6] RISC-V: Fix printf argument types corresponding %x","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a498bec37c1fd1dcda57cbf95e5f8cfba09b31d3.1664793840.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1647,"url":"https://patchwork.plctlab.org/api/1.2/patches/1647/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0002ea716713ace4998a33dde0b81f4f890d10bf.1664793840.git.research_trasio@irq.a4lg.com/","msgid":"<0002ea716713ace4998a33dde0b81f4f890d10bf.1664793840.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-03T10:44:01","name":"[v3,3/6] RISC-V: Optimize riscv_disassemble_data printf","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0002ea716713ace4998a33dde0b81f4f890d10bf.1664793840.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1646,"url":"https://patchwork.plctlab.org/api/1.2/patches/1646/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c65fc3e9aa58965d6768a28c9fd7467fea9897a5.1664793840.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-03T10:44:02","name":"[v3,4/6] RISC-V: Print comma and tabs as the \"text\" style","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c65fc3e9aa58965d6768a28c9fd7467fea9897a5.1664793840.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1648,"url":"https://patchwork.plctlab.org/api/1.2/patches/1648/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5abe1d8a7694417b990e11d8f6cd6789573872e5.1664793840.git.research_trasio@irq.a4lg.com/","msgid":"<5abe1d8a7694417b990e11d8f6cd6789573872e5.1664793840.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-03T10:44:03","name":"[v3,5/6] RISC-V: Fix T-Head immediate types on printing","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5abe1d8a7694417b990e11d8f6cd6789573872e5.1664793840.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1649,"url":"https://patchwork.plctlab.org/api/1.2/patches/1649/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0b68af932117258c908db62cf87c3a15d3cdec41.1664793840.git.research_trasio@irq.a4lg.com/","msgid":"<0b68af932117258c908db62cf87c3a15d3cdec41.1664793840.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-03T10:44:04","name":"[v3,6/6] RISC-V: Print XTheadMemPair literal as \"immediate\"","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0b68af932117258c908db62cf87c3a15d3cdec41.1664793840.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1656,"url":"https://patchwork.plctlab.org/api/1.2/patches/1656/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/87lepxcd6x.fsf@redhat.com/","msgid":"<87lepxcd6x.fsf@redhat.com>","list_archive_url":null,"date":"2022-10-03T12:19:02","name":"Commit: readelf: Do not load section data from offset 0","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/87lepxcd6x.fsf@redhat.com/mbox/"},{"id":1659,"url":"https://patchwork.plctlab.org/api/1.2/patches/1659/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e0d369d419da9c0441f415da7f54352aead8f655.1664707612.git.aburgess@redhat.com/","msgid":"","list_archive_url":null,"date":"2022-10-03T16:37:36","name":"[PATCHv2,1/2] opcodes/arm: use '\''@'\'' consistently for the comment character","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e0d369d419da9c0441f415da7f54352aead8f655.1664707612.git.aburgess@redhat.com/mbox/"},{"id":1660,"url":"https://patchwork.plctlab.org/api/1.2/patches/1660/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003165848.11142-1-palmer@rivosinc.com/","msgid":"<20221003165848.11142-1-palmer@rivosinc.com>","list_archive_url":null,"date":"2022-10-03T16:58:48","name":"gas: NEWS: Mention the T-Head extensions that were recently added","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003165848.11142-1-palmer@rivosinc.com/mbox/"},{"id":1671,"url":"https://patchwork.plctlab.org/api/1.2/patches/1671/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/YzvrMEdkXjIn5Lfz@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-04T08:13:36","name":"Support objcopy changing compression to or from zstd","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/YzvrMEdkXjIn5Lfz@squeak.grove.modra.org/mbox/"},{"id":1673,"url":"https://patchwork.plctlab.org/api/1.2/patches/1673/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0bc857d306bb7c8130e5328dbe6b9ed2fed3ef87.1664873933.git.research_trasio@irq.a4lg.com/","msgid":"<0bc857d306bb7c8130e5328dbe6b9ed2fed3ef87.1664873933.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-04T08:59:07","name":"[1/2] RISC-V: Fix buffer overflow on print_insn_riscv","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0bc857d306bb7c8130e5328dbe6b9ed2fed3ef87.1664873933.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1672,"url":"https://patchwork.plctlab.org/api/1.2/patches/1672/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/89612fe01d902007bf84a7dfb0df5f85d5c166e4.1664873933.git.research_trasio@irq.a4lg.com/","msgid":"<89612fe01d902007bf84a7dfb0df5f85d5c166e4.1664873933.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-04T08:59:08","name":"[2/2] gdb/riscv: Fix buffer overflow on riscv_insn::fetch_instruction","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/89612fe01d902007bf84a7dfb0df5f85d5c166e4.1664873933.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1676,"url":"https://patchwork.plctlab.org/api/1.2/patches/1676/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fc849c94f4adcac1c4ccc5508c7a145a2f13b2a9.1664876744.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-04T09:45:49","name":"[v2,1/2] RISC-V: Fix buffer overflow on print_insn_riscv","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fc849c94f4adcac1c4ccc5508c7a145a2f13b2a9.1664876744.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1677,"url":"https://patchwork.plctlab.org/api/1.2/patches/1677/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4eb6e59ae2e790dbbf2bc92477edd281648d8814.1664876744.git.research_trasio@irq.a4lg.com/","msgid":"<4eb6e59ae2e790dbbf2bc92477edd281648d8814.1664876744.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-04T09:45:50","name":"[v2,2/2] gdb/riscv: Partial support for instructions up to 176-bits","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4eb6e59ae2e790dbbf2bc92477edd281648d8814.1664876744.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1678,"url":"https://patchwork.plctlab.org/api/1.2/patches/1678/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ebf16f9e1f45115d0793952ccb4a94d4233303f9.1664882725.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-04T11:25:56","name":"[v3,1/2] RISC-V: Fix buffer overflow on print_insn_riscv","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ebf16f9e1f45115d0793952ccb4a94d4233303f9.1664882725.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1679,"url":"https://patchwork.plctlab.org/api/1.2/patches/1679/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/83464b09b8649525259c69c853dfa2c9575a204b.1664882725.git.research_trasio@irq.a4lg.com/","msgid":"<83464b09b8649525259c69c853dfa2c9575a204b.1664882725.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-04T11:25:57","name":"[v3,2/2] gdb/riscv: Partial support for instructions up to 176-bit","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/83464b09b8649525259c69c853dfa2c9575a204b.1664882725.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1681,"url":"https://patchwork.plctlab.org/api/1.2/patches/1681/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ffa9c1d7-e8c2-a62b-ef3e-b565c0ffbe5b@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-04T13:56:27","name":"RISC-V: Zicbo{m,p,z} adjustments to riscv_multi_subset_supports_ext()","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ffa9c1d7-e8c2-a62b-ef3e-b565c0ffbe5b@suse.com/mbox/"},{"id":1690,"url":"https://patchwork.plctlab.org/api/1.2/patches/1690/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221004161720.1963953-1-vladimir.mezentsev@oracle.com/","msgid":"<20221004161720.1963953-1-vladimir.mezentsev@oracle.com>","list_archive_url":null,"date":"2022-10-04T16:17:20","name":"gprofng: fix build with --enable-pgo-build=lto","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221004161720.1963953-1-vladimir.mezentsev@oracle.com/mbox/"},{"id":1691,"url":"https://patchwork.plctlab.org/api/1.2/patches/1691/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c0211bc9c57be6c79c6d878ce147f63b657f461d.camel@espressif.com/","msgid":"","list_archive_url":null,"date":"2022-10-04T16:22:05","name":"bfd: xtensa: fix __stop_SECTION literal drop,","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c0211bc9c57be6c79c6d878ce147f63b657f461d.camel@espressif.com/mbox/"},{"id":1702,"url":"https://patchwork.plctlab.org/api/1.2/patches/1702/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5f482299-6c60-b2b3-9abe-f4a55a5a26c5@univ-grenoble-alpes.fr/","msgid":"<5f482299-6c60-b2b3-9abe-f4a55a5a26c5@univ-grenoble-alpes.fr>","list_archive_url":null,"date":"2022-10-04T20:03:20","name":"[RFC] bfd: use bfd_vma for the 64-bit version of put[lb] and get[lb]","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5f482299-6c60-b2b3-9abe-f4a55a5a26c5@univ-grenoble-alpes.fr/mbox/"},{"id":1711,"url":"https://patchwork.plctlab.org/api/1.2/patches/1711/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Yz0Gsxdxe0TePbJT@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-05T04:23:15","name":"PR29647, objdump -S looping","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Yz0Gsxdxe0TePbJT@squeak.grove.modra.org/mbox/"},{"id":1712,"url":"https://patchwork.plctlab.org/api/1.2/patches/1712/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/02d747d2-f57b-0fb5-b893-842b6cc41f2f@suse.com/","msgid":"<02d747d2-f57b-0fb5-b893-842b6cc41f2f@suse.com>","list_archive_url":null,"date":"2022-10-05T07:20:47","name":"[v3,1/7] x86: constify parse_insn()'\''s input","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/02d747d2-f57b-0fb5-b893-842b6cc41f2f@suse.com/mbox/"},{"id":1713,"url":"https://patchwork.plctlab.org/api/1.2/patches/1713/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/925cb740-4e1b-abc4-8526-aaab6faae5e1@suse.com/","msgid":"<925cb740-4e1b-abc4-8526-aaab6faae5e1@suse.com>","list_archive_url":null,"date":"2022-10-05T07:22:19","name":"[v3,2/7] x86: introduce Pass2 insn attribute","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/925cb740-4e1b-abc4-8526-aaab6faae5e1@suse.com/mbox/"},{"id":1714,"url":"https://patchwork.plctlab.org/api/1.2/patches/1714/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e16d3e78-39ca-f715-508f-a4104b8ab9a9@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-05T07:23:51","name":"[v3,3/7] x86: re-work insn/suffix recognition","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e16d3e78-39ca-f715-508f-a4104b8ab9a9@suse.com/mbox/"},{"id":1715,"url":"https://patchwork.plctlab.org/api/1.2/patches/1715/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e4e4b80b-794c-7485-1997-685adab8fb27@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-05T07:24:20","name":"[v3,4/7] x86-64: further re-work insn/suffix recognition to also cover MOVSL","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e4e4b80b-794c-7485-1997-685adab8fb27@suse.com/mbox/"},{"id":1716,"url":"https://patchwork.plctlab.org/api/1.2/patches/1716/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/540678fc-8bff-ec68-c97c-478d2631998c@suse.com/","msgid":"<540678fc-8bff-ec68-c97c-478d2631998c@suse.com>","list_archive_url":null,"date":"2022-10-05T07:24:55","name":"[v3,5/7] ix86: don'\''t recognize/derive Q suffix in the common case","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/540678fc-8bff-ec68-c97c-478d2631998c@suse.com/mbox/"},{"id":1718,"url":"https://patchwork.plctlab.org/api/1.2/patches/1718/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e4692495-7d3d-074d-14f9-364d4a9a998c@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-05T07:25:25","name":"[v3,6/7] x86-64: allow HLE store of accumulator to absolute 32-bit address","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e4692495-7d3d-074d-14f9-364d4a9a998c@suse.com/mbox/"},{"id":1717,"url":"https://patchwork.plctlab.org/api/1.2/patches/1717/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e8014ebd-d16b-17a7-9f34-3700fc164136@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-05T07:25:57","name":"[v3,7/7] x86: move bad-use-of-TLS-reloc check","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e8014ebd-d16b-17a7-9f34-3700fc164136@suse.com/mbox/"},{"id":1719,"url":"https://patchwork.plctlab.org/api/1.2/patches/1719/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1266f001-4511-2662-dba9-14b4d0317c57@suse.com/","msgid":"<1266f001-4511-2662-dba9-14b4d0317c57@suse.com>","list_archive_url":null,"date":"2022-10-05T07:40:50","name":"x86: drop \"regmask\" static variable","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1266f001-4511-2662-dba9-14b4d0317c57@suse.com/mbox/"},{"id":1751,"url":"https://patchwork.plctlab.org/api/1.2/patches/1751/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/af45c5d57c221e43101c2aa38b14f4b4ac12d011.1665031170.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-06T04:40:15","name":"[v2,1/2] RISC-V: Fallback for instructions longer than 64b","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/af45c5d57c221e43101c2aa38b14f4b4ac12d011.1665031170.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1752,"url":"https://patchwork.plctlab.org/api/1.2/patches/1752/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c6e55781245dd3e8e9b8debd6130fc5449dfbd55.1665031170.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-06T04:40:16","name":"[v2,2/2] RISC-V: Improve \"bits undefined\" diagnostics","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c6e55781245dd3e8e9b8debd6130fc5449dfbd55.1665031170.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1776,"url":"https://patchwork.plctlab.org/api/1.2/patches/1776/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d52952119e15357c0e823f8a2398999359588b4d.1665050099.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-06T09:56:30","name":"[v3,1/2] RISC-V: Fallback for instructions longer than 64b","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d52952119e15357c0e823f8a2398999359588b4d.1665050099.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1777,"url":"https://patchwork.plctlab.org/api/1.2/patches/1777/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d907b1997f60ff7823c4a23e281ec9d8ddcbf3f1.1665050099.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-06T09:56:31","name":"[v3,2/2] RISC-V: Improve \"bits undefined\" diagnostics","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d907b1997f60ff7823c4a23e281ec9d8ddcbf3f1.1665050099.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1781,"url":"https://patchwork.plctlab.org/api/1.2/patches/1781/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221006114628.304185-1-chigot@adacore.com/","msgid":"<20221006114628.304185-1-chigot@adacore.com>","list_archive_url":null,"date":"2022-10-06T11:46:28","name":"RISC-V: fix linker message when relaxation deletes bytes","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221006114628.304185-1-chigot@adacore.com/mbox/"},{"id":1801,"url":"https://patchwork.plctlab.org/api/1.2/patches/1801/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Yz+Yhyg7UewC9/kp@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-07T03:09:59","name":"PR29653, objcopy/strip: fuzzed small input file induces large output file","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Yz+Yhyg7UewC9/kp@squeak.grove.modra.org/mbox/"},{"id":1803,"url":"https://patchwork.plctlab.org/api/1.2/patches/1803/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/PH1P110MB16505D9D39EC5B1DE22FE3D5EC5F9@PH1P110MB1650.NAMP110.PROD.OUTLOOK.COM/","msgid":"","list_archive_url":null,"date":"2022-10-07T04:10:07","name":"@CPP_FOR_BUILD@ problem since binutils-2.38","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/PH1P110MB16505D9D39EC5B1DE22FE3D5EC5F9@PH1P110MB1650.NAMP110.PROD.OUTLOOK.COM/mbox/"},{"id":1827,"url":"https://patchwork.plctlab.org/api/1.2/patches/1827/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8e13bce108ac10a0c1dd911e23ec572926f7ae44.1665203374.git.research_trasio@irq.a4lg.com/","msgid":"<8e13bce108ac10a0c1dd911e23ec572926f7ae44.1665203374.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-08T04:29:53","name":"[v2,1/1] RISC-V: Test DWARF register numbers for \"fp\"","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8e13bce108ac10a0c1dd911e23ec572926f7ae44.1665203374.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1828,"url":"https://patchwork.plctlab.org/api/1.2/patches/1828/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0883001b3572e54d3fba264429c7ade2adb66610.1665203441.git.research_trasio@irq.a4lg.com/","msgid":"<0883001b3572e54d3fba264429c7ade2adb66610.1665203441.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-08T04:31:15","name":"[1/1] RISC-V: Move standard hints before all instructions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0883001b3572e54d3fba264429c7ade2adb66610.1665203441.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1829,"url":"https://patchwork.plctlab.org/api/1.2/patches/1829/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/58e16a241d7376fcae2515c6bd5a2b41d275eeba.1665203531.git.research_trasio@irq.a4lg.com/","msgid":"<58e16a241d7376fcae2515c6bd5a2b41d275eeba.1665203531.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-08T04:32:18","name":"[RFC,1/1] RISC-V: Imply '\''Zicsr'\'' from privileged extensions with CSRs","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/58e16a241d7376fcae2515c6bd5a2b41d275eeba.1665203531.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1830,"url":"https://patchwork.plctlab.org/api/1.2/patches/1830/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/cb5076fc96e8f2097779a3abcde843dcdd660031.1665203660.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-08T04:34:23","name":"[1/5] opcodes/riscv-dis.c: Tidying with comments/clarity","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/cb5076fc96e8f2097779a3abcde843dcdd660031.1665203660.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1832,"url":"https://patchwork.plctlab.org/api/1.2/patches/1832/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1f1aa0838bf9c4f10a45fcfe3c682f7efc79d9ae.1665203660.git.research_trasio@irq.a4lg.com/","msgid":"<1f1aa0838bf9c4f10a45fcfe3c682f7efc79d9ae.1665203660.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-08T04:34:24","name":"[2/5] opcodes/riscv-dis.c: Tidying with spacing","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1f1aa0838bf9c4f10a45fcfe3c682f7efc79d9ae.1665203660.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1831,"url":"https://patchwork.plctlab.org/api/1.2/patches/1831/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/740bc5e2d2618d236519b39fedd1a1d7ae4e05da.1665203660.git.research_trasio@irq.a4lg.com/","msgid":"<740bc5e2d2618d236519b39fedd1a1d7ae4e05da.1665203660.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-08T04:34:25","name":"[3/5] opcodes/riscv-dis.c: Use bool type whenever possible","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/740bc5e2d2618d236519b39fedd1a1d7ae4e05da.1665203660.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1833,"url":"https://patchwork.plctlab.org/api/1.2/patches/1833/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6e3a9c235e317f441b4383b3daa68f2051bdc149.1665203660.git.research_trasio@irq.a4lg.com/","msgid":"<6e3a9c235e317f441b4383b3daa68f2051bdc149.1665203660.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-08T04:34:26","name":"[4/5] opcodes/riscv-dis.c: Make XLEN variable static","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6e3a9c235e317f441b4383b3daa68f2051bdc149.1665203660.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1834,"url":"https://patchwork.plctlab.org/api/1.2/patches/1834/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ad929233a62d887495122721340b2f9c80392963.1665203660.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-08T04:34:27","name":"[5/5] opcodes/riscv-dis.c: Remove last_map_state","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ad929233a62d887495122721340b2f9c80392963.1665203660.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1836,"url":"https://patchwork.plctlab.org/api/1.2/patches/1836/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d07e2b6f36ea2fd5830924a9bfeda941b774b687.1665290422.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-09T05:09:22","name":"RISC-V: Move certain arrays to riscv-opc.c","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d07e2b6f36ea2fd5830924a9bfeda941b774b687.1665290422.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1844,"url":"https://patchwork.plctlab.org/api/1.2/patches/1844/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010004623.16582-1-mark@harmstone.com/","msgid":"<20221010004623.16582-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-10T00:46:22","name":"[v2,1/2] ld: Add --pdb option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010004623.16582-1-mark@harmstone.com/mbox/"},{"id":1845,"url":"https://patchwork.plctlab.org/api/1.2/patches/1845/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010004623.16582-2-mark@harmstone.com/","msgid":"<20221010004623.16582-2-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-10T00:46:23","name":"[v2,2/2] ld: Add minimal pdb generation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010004623.16582-2-mark@harmstone.com/mbox/"},{"id":1890,"url":"https://patchwork.plctlab.org/api/1.2/patches/1890/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010200433.414320-1-vladimir.mezentsev@oracle.com/","msgid":"<20221010200433.414320-1-vladimir.mezentsev@oracle.com>","list_archive_url":null,"date":"2022-10-10T20:04:33","name":"gprofng: run tests without installation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010200433.414320-1-vladimir.mezentsev@oracle.com/mbox/"},{"id":1893,"url":"https://patchwork.plctlab.org/api/1.2/patches/1893/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010230426.719238-1-vladimir.mezentsev@oracle.com/","msgid":"<20221010230426.719238-1-vladimir.mezentsev@oracle.com>","list_archive_url":null,"date":"2022-10-10T23:04:26","name":"[2/2] gprofng: use the --libdir path to find libraries","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010230426.719238-1-vladimir.mezentsev@oracle.com/mbox/"},{"id":1894,"url":"https://patchwork.plctlab.org/api/1.2/patches/1894/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010235155.842469-1-vladimir.mezentsev@oracle.com/","msgid":"<20221010235155.842469-1-vladimir.mezentsev@oracle.com>","list_archive_url":null,"date":"2022-10-10T23:51:55","name":"[3/3] gprofng: no need to build version.texi","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010235155.842469-1-vladimir.mezentsev@oracle.com/mbox/"},{"id":1895,"url":"https://patchwork.plctlab.org/api/1.2/patches/1895/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011003702.4287-1-mark@harmstone.com/","msgid":"<20221011003702.4287-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-11T00:37:01","name":"[v3,1/2] ld: Add --pdb option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011003702.4287-1-mark@harmstone.com/mbox/"},{"id":1897,"url":"https://patchwork.plctlab.org/api/1.2/patches/1897/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011003702.4287-2-mark@harmstone.com/","msgid":"<20221011003702.4287-2-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-11T00:37:02","name":"[v3,2/2] ld: Add minimal pdb generation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011003702.4287-2-mark@harmstone.com/mbox/"},{"id":1928,"url":"https://patchwork.plctlab.org/api/1.2/patches/1928/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011175332.17156-1-mark@harmstone.com/","msgid":"<20221011175332.17156-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-11T17:53:31","name":"[v4,1/2] ld: Add --pdb option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011175332.17156-1-mark@harmstone.com/mbox/"},{"id":1929,"url":"https://patchwork.plctlab.org/api/1.2/patches/1929/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011175332.17156-2-mark@harmstone.com/","msgid":"<20221011175332.17156-2-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-11T17:53:32","name":"[v4,2/2] ld: Add minimal pdb generation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011175332.17156-2-mark@harmstone.com/mbox/"},{"id":1941,"url":"https://patchwork.plctlab.org/api/1.2/patches/1941/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221012031005.237446-1-simon.marchi@polymtl.ca/","msgid":"<20221012031005.237446-1-simon.marchi@polymtl.ca>","list_archive_url":null,"date":"2022-10-12T03:10:05","name":"[pushed] Re-apply \"Pass PKG_CONFIG_PATH down from top-level Makefile\"","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221012031005.237446-1-simon.marchi@polymtl.ca/mbox/"},{"id":1976,"url":"https://patchwork.plctlab.org/api/1.2/patches/1976/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1216a3f8-2273-8681-f528-9493a66891f0@suse.com/","msgid":"<1216a3f8-2273-8681-f528-9493a66891f0@suse.com>","list_archive_url":null,"date":"2022-10-13T08:16:49","name":"[v4,1/8] x86: constify parse_insn()'\''s input","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1216a3f8-2273-8681-f528-9493a66891f0@suse.com/mbox/"},{"id":1977,"url":"https://patchwork.plctlab.org/api/1.2/patches/1977/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/11599bbe-c779-aa9f-4d5d-c2243f0e69dc@suse.com/","msgid":"<11599bbe-c779-aa9f-4d5d-c2243f0e69dc@suse.com>","list_archive_url":null,"date":"2022-10-13T08:17:17","name":"[v4,2/8] x86: introduce Pass2 insn attribute","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/11599bbe-c779-aa9f-4d5d-c2243f0e69dc@suse.com/mbox/"},{"id":1978,"url":"https://patchwork.plctlab.org/api/1.2/patches/1978/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/357273a3-060c-23db-72da-3fc9d1be3d2a@suse.com/","msgid":"<357273a3-060c-23db-72da-3fc9d1be3d2a@suse.com>","list_archive_url":null,"date":"2022-10-13T08:18:09","name":"[v4,3/8] x86: re-work insn/suffix recognition","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/357273a3-060c-23db-72da-3fc9d1be3d2a@suse.com/mbox/"},{"id":1979,"url":"https://patchwork.plctlab.org/api/1.2/patches/1979/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0ec0587f-6a7b-45b6-8346-e5d774e73636@suse.com/","msgid":"<0ec0587f-6a7b-45b6-8346-e5d774e73636@suse.com>","list_archive_url":null,"date":"2022-10-13T08:18:39","name":"[v4,4/8] x86-64: further re-work insn/suffix recognition to also cover MOVSL","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0ec0587f-6a7b-45b6-8346-e5d774e73636@suse.com/mbox/"},{"id":1980,"url":"https://patchwork.plctlab.org/api/1.2/patches/1980/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fb617d0b-8759-3169-5a65-1178b7fef3d7@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-13T08:19:34","name":"[v4,5/8] ix86: don'\''t recognize/derive Q suffix in the common case","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fb617d0b-8759-3169-5a65-1178b7fef3d7@suse.com/mbox/"},{"id":1981,"url":"https://patchwork.plctlab.org/api/1.2/patches/1981/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1df3bd01-99c5-f56c-d937-970edd42b2b8@suse.com/","msgid":"<1df3bd01-99c5-f56c-d937-970edd42b2b8@suse.com>","list_archive_url":null,"date":"2022-10-13T08:20:14","name":"[v4,6/8] x86-64: allow HLE store of accumulator to absolute 32-bit address","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1df3bd01-99c5-f56c-d937-970edd42b2b8@suse.com/mbox/"},{"id":1982,"url":"https://patchwork.plctlab.org/api/1.2/patches/1982/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8486a218-39ec-16b2-5c6c-5037196b93cf@suse.com/","msgid":"<8486a218-39ec-16b2-5c6c-5037196b93cf@suse.com>","list_archive_url":null,"date":"2022-10-13T08:21:00","name":"[v4,7/8] x86: move bad-use-of-TLS-reloc check","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8486a218-39ec-16b2-5c6c-5037196b93cf@suse.com/mbox/"},{"id":1983,"url":"https://patchwork.plctlab.org/api/1.2/patches/1983/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7d82692d-93df-fbee-9efb-2f44e8a91df3@suse.com/","msgid":"<7d82692d-93df-fbee-9efb-2f44e8a91df3@suse.com>","list_archive_url":null,"date":"2022-10-13T08:22:00","name":"[v4,8/8] x86: drop (now) stray IsString","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7d82692d-93df-fbee-9efb-2f44e8a91df3@suse.com/mbox/"},{"id":2013,"url":"https://patchwork.plctlab.org/api/1.2/patches/2013/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8ab93d7a617ad480dd786210f46db0e5aa07d1ac.1665655719.git.research_trasio@irq.a4lg.com/","msgid":"<8ab93d7a617ad480dd786210f46db0e5aa07d1ac.1665655719.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-13T10:11:41","name":"include: Declare getopt function on old GNU libc","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8ab93d7a617ad480dd786210f46db0e5aa07d1ac.1665655719.git.research_trasio@irq.a4lg.com/mbox/"},{"id":2352,"url":"https://patchwork.plctlab.org/api/1.2/patches/2352/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221013201332.2747246-1-maskray@google.com/","msgid":"<20221013201332.2747246-1-maskray@google.com>","list_archive_url":null,"date":"2022-10-13T20:13:32","name":"ld: Add --undefined-version","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221013201332.2747246-1-maskray@google.com/mbox/"},{"id":2532,"url":"https://patchwork.plctlab.org/api/1.2/patches/2532/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014063520.1428330-2-zengxiao@eswincomputing.com/","msgid":"<20221014063520.1428330-2-zengxiao@eswincomputing.com>","list_archive_url":null,"date":"2022-10-14T06:35:20","name":"[1/1] RISC-V: Make R_RISCV_SUB6 conforms to riscv abi standard","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014063520.1428330-2-zengxiao@eswincomputing.com/mbox/"},{"id":2560,"url":"https://patchwork.plctlab.org/api/1.2/patches/2560/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/027ae69a-636b-6757-297a-eec42936401e@linaro.org/","msgid":"<027ae69a-636b-6757-297a-eec42936401e@linaro.org>","list_archive_url":null,"date":"2022-10-14T07:58:22","name":"[v3] aarch64-pe support for LD, GAS and BFD","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/027ae69a-636b-6757-297a-eec42936401e@linaro.org/mbox/"},{"id":2602,"url":"https://patchwork.plctlab.org/api/1.2/patches/2602/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-2-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-2-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:39","name":"[01/10] Support Intel AVX-IFMA","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-2-haochen.jiang@intel.com/mbox/"},{"id":2608,"url":"https://patchwork.plctlab.org/api/1.2/patches/2608/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-3-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-3-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:40","name":"[02/10] Support Intel AVX-VNNI-INT8","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-3-haochen.jiang@intel.com/mbox/"},{"id":2611,"url":"https://patchwork.plctlab.org/api/1.2/patches/2611/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-4-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-4-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:41","name":"[03/10] Support Intel AVX-NE-CONVERT","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-4-haochen.jiang@intel.com/mbox/"},{"id":2610,"url":"https://patchwork.plctlab.org/api/1.2/patches/2610/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-5-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-5-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:42","name":"[04/10] Support Intel CMPccXADD","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-5-haochen.jiang@intel.com/mbox/"},{"id":2601,"url":"https://patchwork.plctlab.org/api/1.2/patches/2601/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-6-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-6-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:43","name":"[05/10] Add handler for more i386_cpu_flags","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-6-haochen.jiang@intel.com/mbox/"},{"id":2606,"url":"https://patchwork.plctlab.org/api/1.2/patches/2606/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-7-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-7-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:44","name":"[06/10] Support Intel RAO-INT","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-7-haochen.jiang@intel.com/mbox/"},{"id":2609,"url":"https://patchwork.plctlab.org/api/1.2/patches/2609/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-8-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-8-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:45","name":"[07/10] Support Intel WRMSRNS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-8-haochen.jiang@intel.com/mbox/"},{"id":2605,"url":"https://patchwork.plctlab.org/api/1.2/patches/2605/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-9-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-9-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:46","name":"[08/10] Support Intel MSRLIST","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-9-haochen.jiang@intel.com/mbox/"},{"id":2607,"url":"https://patchwork.plctlab.org/api/1.2/patches/2607/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-10-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-10-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:47","name":"[09/10] Support Intel AMX-FP16","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-10-haochen.jiang@intel.com/mbox/"},{"id":2604,"url":"https://patchwork.plctlab.org/api/1.2/patches/2604/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-11-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-11-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:48","name":"[10/10] Support Intel PREFETCHI","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-11-haochen.jiang@intel.com/mbox/"},{"id":2643,"url":"https://patchwork.plctlab.org/api/1.2/patches/2643/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7bac66be-535e-9051-d674-f2f5ba180e17@suse.com/","msgid":"<7bac66be-535e-9051-d674-f2f5ba180e17@suse.com>","list_archive_url":null,"date":"2022-10-14T10:22:34","name":"x86: fold AVX512-VNNI disassembler entries with AVX-VNNI ones","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7bac66be-535e-9051-d674-f2f5ba180e17@suse.com/mbox/"},{"id":2654,"url":"https://patchwork.plctlab.org/api/1.2/patches/2654/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0lIo5+ncY/MqBEq@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-14T11:31:47","name":"PR29677, Field `the_bfd` of `asymbol` is uninitialised","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0lIo5+ncY/MqBEq@squeak.grove.modra.org/mbox/"},{"id":2656,"url":"https://patchwork.plctlab.org/api/1.2/patches/2656/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0lJksn49ZpABY89@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-14T11:35:46","name":"e200 LSP support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0lJksn49ZpABY89@squeak.grove.modra.org/mbox/"},{"id":2657,"url":"https://patchwork.plctlab.org/api/1.2/patches/2657/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0lJxxYoeD5iDYAD@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-14T11:36:39","name":"PowerPC SPE disassembly and tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0lJxxYoeD5iDYAD@squeak.grove.modra.org/mbox/"},{"id":2695,"url":"https://patchwork.plctlab.org/api/1.2/patches/2695/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/DM6PR12MB4219611F6CC2A0702884A602E7249@DM6PR12MB4219.namprd12.prod.outlook.com/","msgid":"","list_archive_url":null,"date":"2022-10-14T13:29:40","name":"Binutils: Adding new testcase for addr2line.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/DM6PR12MB4219611F6CC2A0702884A602E7249@DM6PR12MB4219.namprd12.prod.outlook.com/mbox/"},{"id":2700,"url":"https://patchwork.plctlab.org/api/1.2/patches/2700/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9fd2c88d-98b2-99a4-419f-c7235b2cf960@suse.com/","msgid":"<9fd2c88d-98b2-99a4-419f-c7235b2cf960@suse.com>","list_archive_url":null,"date":"2022-10-14T14:11:35","name":"x86: properly decode EVEX.W for AVX512_4{FMAPS,VNNIW} insns","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9fd2c88d-98b2-99a4-419f-c7235b2cf960@suse.com/mbox/"},{"id":2981,"url":"https://patchwork.plctlab.org/api/1.2/patches/2981/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0uLzalqjm4C87GN@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-16T04:42:53","name":"PowerPC se_rfmci and VLE, SPE2 and LSP insns with -many","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0uLzalqjm4C87GN@squeak.grove.modra.org/mbox/"},{"id":3152,"url":"https://patchwork.plctlab.org/api/1.2/patches/3152/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221016232419.1135-1-mark@harmstone.com/","msgid":"<20221016232419.1135-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-16T23:24:18","name":"[v5,1/2] ld: Add --pdb option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221016232419.1135-1-mark@harmstone.com/mbox/"},{"id":3151,"url":"https://patchwork.plctlab.org/api/1.2/patches/3151/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221016232419.1135-2-mark@harmstone.com/","msgid":"<20221016232419.1135-2-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-16T23:24:19","name":"[v5,2/2] ld: Add minimal pdb generation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221016232419.1135-2-mark@harmstone.com/mbox/"},{"id":3258,"url":"https://patchwork.plctlab.org/api/1.2/patches/3258/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/19c08747-fa5b-1e67-3dd2-c891a2c0c1fa@suse.com/","msgid":"<19c08747-fa5b-1e67-3dd2-c891a2c0c1fa@suse.com>","list_archive_url":null,"date":"2022-10-17T07:44:51","name":"x86: correct CPU_AMX_{BF16,INT8}_FLAGS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/19c08747-fa5b-1e67-3dd2-c891a2c0c1fa@suse.com/mbox/"},{"id":3272,"url":"https://patchwork.plctlab.org/api/1.2/patches/3272/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/85dd526c-d3a7-72dc-5444-ed5573eebec1@suse.com/","msgid":"<85dd526c-d3a7-72dc-5444-ed5573eebec1@suse.com>","list_archive_url":null,"date":"2022-10-17T08:30:12","name":"x86: generalize gas documentation for disabling of ISA extensions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/85dd526c-d3a7-72dc-5444-ed5573eebec1@suse.com/mbox/"},{"id":3759,"url":"https://patchwork.plctlab.org/api/1.2/patches/3759/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-2-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-2-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:15:58","name":"[V2,01/15] sframe.h: Add SFrame format definition","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-2-indu.bhagat@oracle.com/mbox/"},{"id":3762,"url":"https://patchwork.plctlab.org/api/1.2/patches/3762/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-3-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-3-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:15:59","name":"[V2,02/15] gas: add new command line option --gsframe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-3-indu.bhagat@oracle.com/mbox/"},{"id":3761,"url":"https://patchwork.plctlab.org/api/1.2/patches/3761/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-4-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-4-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:00","name":"[V2,03/15] gas: generate .sframe from CFI directives","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-4-indu.bhagat@oracle.com/mbox/"},{"id":3760,"url":"https://patchwork.plctlab.org/api/1.2/patches/3760/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-5-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-5-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:01","name":"[V2,04/15] gas: testsuite: add new tests for SFrame unwind info","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-5-indu.bhagat@oracle.com/mbox/"},{"id":3764,"url":"https://patchwork.plctlab.org/api/1.2/patches/3764/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-6-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-6-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:02","name":"[V2,05/15] libsframe: add the SFrame library","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-6-indu.bhagat@oracle.com/mbox/"},{"id":3766,"url":"https://patchwork.plctlab.org/api/1.2/patches/3766/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-7-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-7-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:03","name":"[V2,06/15] bfd: linker: merge .sframe sections","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-7-indu.bhagat@oracle.com/mbox/"},{"id":3763,"url":"https://patchwork.plctlab.org/api/1.2/patches/3763/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-8-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-8-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:04","name":"[V2,07/15] readelf/objdump: support for SFrame section","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-8-indu.bhagat@oracle.com/mbox/"},{"id":3765,"url":"https://patchwork.plctlab.org/api/1.2/patches/3765/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-9-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-9-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:05","name":"[V2,08/15] unwinder: generate backtrace using SFrame format","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-9-indu.bhagat@oracle.com/mbox/"},{"id":3770,"url":"https://patchwork.plctlab.org/api/1.2/patches/3770/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-10-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-10-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:06","name":"[V2,09/15] unwinder: Add SFrame unwinder tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-10-indu.bhagat@oracle.com/mbox/"},{"id":3769,"url":"https://patchwork.plctlab.org/api/1.2/patches/3769/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-11-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-11-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:07","name":"[V2,10/15] gdb: sim: buildsystem changes to accommodate libsframe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-11-indu.bhagat@oracle.com/mbox/"},{"id":3771,"url":"https://patchwork.plctlab.org/api/1.2/patches/3771/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-12-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-12-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:08","name":"[V2,11/15] libctf: add libsframe to LDFLAGS and LIBS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-12-indu.bhagat@oracle.com/mbox/"},{"id":3768,"url":"https://patchwork.plctlab.org/api/1.2/patches/3768/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-13-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-13-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:09","name":"[V2,12/15] src-release.sh: Add libsframe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-13-indu.bhagat@oracle.com/mbox/"},{"id":3767,"url":"https://patchwork.plctlab.org/api/1.2/patches/3767/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-14-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-14-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:10","name":"[V2,13/15] binutils/NEWS: add text for SFrame support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-14-indu.bhagat@oracle.com/mbox/"},{"id":3772,"url":"https://patchwork.plctlab.org/api/1.2/patches/3772/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-15-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-15-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:11","name":"[V2,14/15] gas/NEWS: add text about new command line option and SFrame support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-15-indu.bhagat@oracle.com/mbox/"},{"id":3773,"url":"https://patchwork.plctlab.org/api/1.2/patches/3773/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-16-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-16-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:12","name":"[V2,15/15] doc: add SFrame spec file","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-16-indu.bhagat@oracle.com/mbox/"},{"id":3999,"url":"https://patchwork.plctlab.org/api/1.2/patches/3999/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221018081205.17880-1-krebbel@linux.ibm.com/","msgid":"<20221018081205.17880-1-krebbel@linux.ibm.com>","list_archive_url":null,"date":"2022-10-18T08:12:05","name":"[1/1] IBM zSystems: Issue error for *DBL relocs on misaligned symbols","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221018081205.17880-1-krebbel@linux.ibm.com/mbox/"},{"id":4141,"url":"https://patchwork.plctlab.org/api/1.2/patches/4141/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/baffaf673f17692b7bcbd604b31800b189988596.camel@espressif.com/","msgid":"","list_archive_url":null,"date":"2022-10-18T12:12:07","name":"xtensa: use definitions from xtensa-config.h","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/baffaf673f17692b7bcbd604b31800b189988596.camel@espressif.com/mbox/"},{"id":4272,"url":"https://patchwork.plctlab.org/api/1.2/patches/4272/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221018174914.470062-1-hjl.tools@gmail.com/","msgid":"<20221018174914.470062-1-hjl.tools@gmail.com>","list_archive_url":null,"date":"2022-10-18T17:49:14","name":"x86: Disable AVX-VNNI when disabling AVX2","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221018174914.470062-1-hjl.tools@gmail.com/mbox/"},{"id":4998,"url":"https://patchwork.plctlab.org/api/1.2/patches/4998/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c2f76e95-09f6-1d92-7ef4-38a3c2955fcd@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-19T09:52:46","name":"x86: re-work AVX-VNNI support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c2f76e95-09f6-1d92-7ef4-38a3c2955fcd@suse.com/mbox/"},{"id":5276,"url":"https://patchwork.plctlab.org/api/1.2/patches/5276/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0/lLtlKqqsmAx0s@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-19T11:53:18","name":"Fix addr2line test for ppc64 elfv1 and mingw","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0/lLtlKqqsmAx0s@squeak.grove.modra.org/mbox/"},{"id":5424,"url":"https://patchwork.plctlab.org/api/1.2/patches/5424/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/07bfebbf3843b47e13d82d4fa16eb14fec942ef7.1666184962.git.research_trasio@irq.a4lg.com/","msgid":"<07bfebbf3843b47e13d82d4fa16eb14fec942ef7.1666184962.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:09:54","name":"binutils: Remove unused substitution PROGRAM","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/07bfebbf3843b47e13d82d4fa16eb14fec942ef7.1666184962.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5433,"url":"https://patchwork.plctlab.org/api/1.2/patches/5433/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2fa7ff719223232402e82a9c91331aea22ace1bb.1666185116.git.research_trasio@irq.a4lg.com/","msgid":"<2fa7ff719223232402e82a9c91331aea22ace1bb.1666185116.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:11:55","name":"[v2,1/8] RISC-V: Add a space at the end of pinfo","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2fa7ff719223232402e82a9c91331aea22ace1bb.1666185116.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5435,"url":"https://patchwork.plctlab.org/api/1.2/patches/5435/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1b30cce5db2cce3b8edca42ab5da114d0b8c9e93.1666185116.git.research_trasio@irq.a4lg.com/","msgid":"<1b30cce5db2cce3b8edca42ab5da114d0b8c9e93.1666185116.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:11:56","name":"[v2,2/8] RISC-V: Fix obvious misalignments ('\''Zbb'\''/'\''Zba'\'')","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1b30cce5db2cce3b8edca42ab5da114d0b8c9e93.1666185116.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5437,"url":"https://patchwork.plctlab.org/api/1.2/patches/5437/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6b0857aa1a2d15ca1cf00b4dcaae0032efbb88ff.1666185116.git.research_trasio@irq.a4lg.com/","msgid":"<6b0857aa1a2d15ca1cf00b4dcaae0032efbb88ff.1666185116.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:11:57","name":"[v2,3/8] RISC-V: Remove spaces in opcode entries","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6b0857aa1a2d15ca1cf00b4dcaae0032efbb88ff.1666185116.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5436,"url":"https://patchwork.plctlab.org/api/1.2/patches/5436/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/889d956caac0f2e95543a14afaeed97188ce384c.1666185116.git.research_trasio@irq.a4lg.com/","msgid":"<889d956caac0f2e95543a14afaeed97188ce384c.1666185116.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:11:58","name":"[v2,4/8] RISC-V: Remove unused instruction macros","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/889d956caac0f2e95543a14afaeed97188ce384c.1666185116.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5440,"url":"https://patchwork.plctlab.org/api/1.2/patches/5440/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8f226ee20d8a5ef6ad7b6c4408b44794a99d542a.1666185116.git.research_trasio@irq.a4lg.com/","msgid":"<8f226ee20d8a5ef6ad7b6c4408b44794a99d542a.1666185116.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:11:59","name":"[v2,5/8] RISC-V: Complete tidying up with SCALL and SBREAK","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8f226ee20d8a5ef6ad7b6c4408b44794a99d542a.1666185116.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5442,"url":"https://patchwork.plctlab.org/api/1.2/patches/5442/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4070184c454a05a39adf0790951e5856e6b2ecb6.1666185116.git.research_trasio@irq.a4lg.com/","msgid":"<4070184c454a05a39adf0790951e5856e6b2ecb6.1666185116.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:12:00","name":"[v2,6/8] RISC-V: Tidying up with fmv.w.x and fmv.x.w","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4070184c454a05a39adf0790951e5856e6b2ecb6.1666185116.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5438,"url":"https://patchwork.plctlab.org/api/1.2/patches/5438/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c1ccda3e7c8fb297eda46dab3936d5c5977178fc.1666185116.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-19T13:12:01","name":"[v2,7/8] RISC-V: Make alias instructions aliases","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c1ccda3e7c8fb297eda46dab3936d5c5977178fc.1666185116.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5441,"url":"https://patchwork.plctlab.org/api/1.2/patches/5441/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/413cfca82c7e8d8a2e977dfda9135903c9cb7c57.1666185116.git.research_trasio@irq.a4lg.com/","msgid":"<413cfca82c7e8d8a2e977dfda9135903c9cb7c57.1666185116.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:12:02","name":"[v2,8/8] RISC-V: Use defined mask and match values","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/413cfca82c7e8d8a2e977dfda9135903c9cb7c57.1666185116.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5439,"url":"https://patchwork.plctlab.org/api/1.2/patches/5439/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/345c5c3b3a53eab04a1e6e91197de2642095c94f.1666185237.git.research_trasio@irq.a4lg.com/","msgid":"<345c5c3b3a53eab04a1e6e91197de2642095c94f.1666185237.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:14:01","name":"RISC-V: Remove RV32EF conflict","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/345c5c3b3a53eab04a1e6e91197de2642095c94f.1666185237.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5616,"url":"https://patchwork.plctlab.org/api/1.2/patches/5616/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019145608.45213-5-haochen.jiang@intel.com/","msgid":"<20221019145608.45213-5-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T14:56:02","name":"[04/10] Support Intel CMPccXADD","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019145608.45213-5-haochen.jiang@intel.com/mbox/"},{"id":5614,"url":"https://patchwork.plctlab.org/api/1.2/patches/5614/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019145608.45213-6-haochen.jiang@intel.com/","msgid":"<20221019145608.45213-6-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T14:56:03","name":"[05/10] Add handler for more i386_cpu_flags","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019145608.45213-6-haochen.jiang@intel.com/mbox/"},{"id":5672,"url":"https://patchwork.plctlab.org/api/1.2/patches/5672/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-2-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-2-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:25","name":"[01/10] Support Intel AVX-IFMA","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-2-haochen.jiang@intel.com/mbox/"},{"id":5691,"url":"https://patchwork.plctlab.org/api/1.2/patches/5691/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-3-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-3-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:26","name":"[02/10] Support Intel AVX-VNNI-INT8","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-3-haochen.jiang@intel.com/mbox/"},{"id":5690,"url":"https://patchwork.plctlab.org/api/1.2/patches/5690/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-4-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-4-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:27","name":"[03/10] Support Intel AVX-NE-CONVERT","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-4-haochen.jiang@intel.com/mbox/"},{"id":5689,"url":"https://patchwork.plctlab.org/api/1.2/patches/5689/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-5-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-5-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:28","name":"[04/10] Support Intel CMPccXADD","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-5-haochen.jiang@intel.com/mbox/"},{"id":5676,"url":"https://patchwork.plctlab.org/api/1.2/patches/5676/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-6-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-6-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:29","name":"[05/10] Add handler for more i386_cpu_flags","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-6-haochen.jiang@intel.com/mbox/"},{"id":5677,"url":"https://patchwork.plctlab.org/api/1.2/patches/5677/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-7-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-7-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:30","name":"[06/10] Support Intel RAO-INT","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-7-haochen.jiang@intel.com/mbox/"},{"id":5681,"url":"https://patchwork.plctlab.org/api/1.2/patches/5681/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-8-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-8-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:31","name":"[07/10] Support Intel WRMSRNS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-8-haochen.jiang@intel.com/mbox/"},{"id":5682,"url":"https://patchwork.plctlab.org/api/1.2/patches/5682/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-9-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-9-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:32","name":"[08/10] Support Intel MSRLIST","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-9-haochen.jiang@intel.com/mbox/"},{"id":5673,"url":"https://patchwork.plctlab.org/api/1.2/patches/5673/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-10-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-10-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:33","name":"[09/10] Support Intel AMX-FP16","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-10-haochen.jiang@intel.com/mbox/"},{"id":5686,"url":"https://patchwork.plctlab.org/api/1.2/patches/5686/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-11-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-11-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:34","name":"[10/10] Support Intel PREFETCHI","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-11-haochen.jiang@intel.com/mbox/"},{"id":5940,"url":"https://patchwork.plctlab.org/api/1.2/patches/5940/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1CMrFUC8d9lC/NL@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-19T23:47:56","name":"Obsolete beos","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1CMrFUC8d9lC/NL@squeak.grove.modra.org/mbox/"},{"id":6080,"url":"https://patchwork.plctlab.org/api/1.2/patches/6080/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8b99d666e78ba5b9d32c7889a2161c70b3da88df.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<8b99d666e78ba5b9d32c7889a2161c70b3da88df.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:25:47","name":"[01/40] gdb/unittests: PR28413, suppress warnings generated by Gnulib","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8b99d666e78ba5b9d32c7889a2161c70b3da88df.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6081,"url":"https://patchwork.plctlab.org/api/1.2/patches/6081/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b05adb17e401d621dbdad791281bc7af7806906e.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-20T09:25:48","name":"[02/40] sim: Check known getrusage declaration existence","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b05adb17e401d621dbdad791281bc7af7806906e.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6083,"url":"https://patchwork.plctlab.org/api/1.2/patches/6083/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/796962a87e569feeafb5ef636de3c79000ae152c.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<796962a87e569feeafb5ef636de3c79000ae152c.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:25:49","name":"[03/40] sim/aarch64: Remove unused functions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/796962a87e569feeafb5ef636de3c79000ae152c.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6084,"url":"https://patchwork.plctlab.org/api/1.2/patches/6084/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/65223c79fdfd7faf132275415cd9da9852c5bec3.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<65223c79fdfd7faf132275415cd9da9852c5bec3.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:25:50","name":"[04/40] cpu/cris: Initialize some variables on CRIS CPU","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/65223c79fdfd7faf132275415cd9da9852c5bec3.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6082,"url":"https://patchwork.plctlab.org/api/1.2/patches/6082/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/24baefe92148f4b7968115ba13de9b0c863a65f6.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<24baefe92148f4b7968115ba13de9b0c863a65f6.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:25:51","name":"[05/40] cpu/cris: Add u-stall virtual unit to CRIS v32","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/24baefe92148f4b7968115ba13de9b0c863a65f6.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6087,"url":"https://patchwork.plctlab.org/api/1.2/patches/6087/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3904a5c3e80f8548150d8088a92059dd728c7ff8.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<3904a5c3e80f8548150d8088a92059dd728c7ff8.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:25:52","name":"[06/40] sim/cris: Move declarations of f_specific_init","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3904a5c3e80f8548150d8088a92059dd728c7ff8.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6091,"url":"https://patchwork.plctlab.org/api/1.2/patches/6091/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/69ef2d7dd519ed572511890a215a0f6d74e53384.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<69ef2d7dd519ed572511890a215a0f6d74e53384.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:25:53","name":"[07/40] sim/cris: Regenerate with CGEN","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/69ef2d7dd519ed572511890a215a0f6d74e53384.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6085,"url":"https://patchwork.plctlab.org/api/1.2/patches/6085/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/26a3eaf4f5d2e0db6977738ddfd65d82b36e38b2.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<26a3eaf4f5d2e0db6977738ddfd65d82b36e38b2.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:25:54","name":"[08/40] sim/erc32: Insert void parameter","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/26a3eaf4f5d2e0db6977738ddfd65d82b36e38b2.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6086,"url":"https://patchwork.plctlab.org/api/1.2/patches/6086/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/057c2f8392410494c3bc5dc98052246508e6a73e.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<057c2f8392410494c3bc5dc98052246508e6a73e.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:25:55","name":"[09/40] sim/erc32: Use int32_t as event callback argument","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/057c2f8392410494c3bc5dc98052246508e6a73e.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6090,"url":"https://patchwork.plctlab.org/api/1.2/patches/6090/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8c05aec20557191434485be347d37177a2ec5ff2.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<8c05aec20557191434485be347d37177a2ec5ff2.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:25:56","name":"[10/40] sim/erc32: Use int32_t as IRQ callback argument","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8c05aec20557191434485be347d37177a2ec5ff2.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6089,"url":"https://patchwork.plctlab.org/api/1.2/patches/6089/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/afd7757aae21743c29f2aa4135a23b31d4959e9b.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-20T09:25:57","name":"[11/40] cpu/frv: Initialize some variables","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/afd7757aae21743c29f2aa4135a23b31d4959e9b.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6088,"url":"https://patchwork.plctlab.org/api/1.2/patches/6088/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/021dbd238af5dfe74523ed229d2156a155a6bb9e.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<021dbd238af5dfe74523ed229d2156a155a6bb9e.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:25:58","name":"[12/40] sim/frv: Initialize nesr variable","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/021dbd238af5dfe74523ed229d2156a155a6bb9e.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6093,"url":"https://patchwork.plctlab.org/api/1.2/patches/6093/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/51a03f7097921cc48954210cf99e370ae8982ec8.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<51a03f7097921cc48954210cf99e370ae8982ec8.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:25:59","name":"[13/40] sim/frv: Initialize some variables","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/51a03f7097921cc48954210cf99e370ae8982ec8.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6092,"url":"https://patchwork.plctlab.org/api/1.2/patches/6092/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e1baa1be3601612266dc6ae0bdde8426ff2a42c8.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-20T09:26:00","name":"[14/40] sim/frv: Add explicit casts","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e1baa1be3601612266dc6ae0bdde8426ff2a42c8.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6095,"url":"https://patchwork.plctlab.org/api/1.2/patches/6095/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5ab303a5bdfc1da7832f8fa22f57678c9ef1a5fa.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<5ab303a5bdfc1da7832f8fa22f57678c9ef1a5fa.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:26:01","name":"[15/40] sim/h8300: Add \"+ 0x0\" to avoid self-assignments","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5ab303a5bdfc1da7832f8fa22f57678c9ef1a5fa.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6101,"url":"https://patchwork.plctlab.org/api/1.2/patches/6101/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ddff80db3328a2286fe6fbc1240d2abc1e3813eb.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-20T09:26:02","name":"[16/40] sim/lm32: fix some missing function declaration warnings","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ddff80db3328a2286fe6fbc1240d2abc1e3813eb.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6094,"url":"https://patchwork.plctlab.org/api/1.2/patches/6094/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e094b1379231d9ffb59a78cfebbcc84634c779c6.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-20T09:26:03","name":"[17/40] sim/lm32: Add explicit casts","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e094b1379231d9ffb59a78cfebbcc84634c779c6.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6141,"url":"https://patchwork.plctlab.org/api/1.2/patches/6141/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/cabebead-489b-528c-580e-933832417474@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-20T10:25:51","name":"[1/3] x86: emit {evex} prefix when disassembling ambiguous AVX512VL insns","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/cabebead-489b-528c-580e-933832417474@suse.com/mbox/"},{"id":6143,"url":"https://patchwork.plctlab.org/api/1.2/patches/6143/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a032d61c-63a0-23d1-331f-619a2b8bbde3@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-20T10:26:15","name":"[2/3] x86: consolidate VAES tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a032d61c-63a0-23d1-331f-619a2b8bbde3@suse.com/mbox/"},{"id":6142,"url":"https://patchwork.plctlab.org/api/1.2/patches/6142/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7ff09c86-2de7-dc34-3183-5187de3df5ac@suse.com/","msgid":"<7ff09c86-2de7-dc34-3183-5187de3df5ac@suse.com>","list_archive_url":null,"date":"2022-10-20T10:26:40","name":"[3/3] x86: consolidate VPCLMUL tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7ff09c86-2de7-dc34-3183-5187de3df5ac@suse.com/mbox/"},{"id":6228,"url":"https://patchwork.plctlab.org/api/1.2/patches/6228/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.LSU.2.20.2210201432170.29399@wotan.suse.de/","msgid":"","list_archive_url":null,"date":"2022-10-20T14:42:25","name":"x86-64: Use only one default max-page-size","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.LSU.2.20.2210201432170.29399@wotan.suse.de/mbox/"},{"id":6229,"url":"https://patchwork.plctlab.org/api/1.2/patches/6229/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221020144351.1398099-1-chigot@adacore.com/","msgid":"<20221020144351.1398099-1-chigot@adacore.com>","list_archive_url":null,"date":"2022-10-20T14:43:50","name":"[1/2] ld/testsuite: skip ld-elf/exclude when -shared is not supported","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221020144351.1398099-1-chigot@adacore.com/mbox/"},{"id":6230,"url":"https://patchwork.plctlab.org/api/1.2/patches/6230/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221020144351.1398099-2-chigot@adacore.com/","msgid":"<20221020144351.1398099-2-chigot@adacore.com>","list_archive_url":null,"date":"2022-10-20T14:43:51","name":"[2/2] ld/testsuite: adjust ld-arm to run shared tests only when supported","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221020144351.1398099-2-chigot@adacore.com/mbox/"},{"id":6236,"url":"https://patchwork.plctlab.org/api/1.2/patches/6236/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221020151027.GA1300@delia.home/","msgid":"<20221020151027.GA1300@delia.home>","list_archive_url":null,"date":"2022-10-20T15:10:28","name":"[RFC,top-level] Add configure test-case","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221020151027.GA1300@delia.home/mbox/"},{"id":6286,"url":"https://patchwork.plctlab.org/api/1.2/patches/6286/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221020162911.1113338-1-hjl.tools@gmail.com/","msgid":"<20221020162911.1113338-1-hjl.tools@gmail.com>","list_archive_url":null,"date":"2022-10-20T16:29:11","name":"x86: Check VEX/EVEX encoding before checking vector operands","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221020162911.1113338-1-hjl.tools@gmail.com/mbox/"},{"id":7884,"url":"https://patchwork.plctlab.org/api/1.2/patches/7884/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7e53b7980f2b3b74d2250bc87f5db94b1d888a2d.camel@espressif.com/","msgid":"<7e53b7980f2b3b74d2250bc87f5db94b1d888a2d.camel@espressif.com>","list_archive_url":null,"date":"2022-10-22T12:53:54","name":"[1/5] bfd: xtensa: move common code from ld and gas","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7e53b7980f2b3b74d2250bc87f5db94b1d888a2d.camel@espressif.com/mbox/"},{"id":7885,"url":"https://patchwork.plctlab.org/api/1.2/patches/7885/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/63f2699e6ef3e6d1ca415a6ed1187d4f64297521.camel@espressif.com/","msgid":"<63f2699e6ef3e6d1ca415a6ed1187d4f64297521.camel@espressif.com>","list_archive_url":null,"date":"2022-10-22T12:55:16","name":"[2/5] gas: xtensa: add endianness, loops, booleans options","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/63f2699e6ef3e6d1ca415a6ed1187d4f64297521.camel@espressif.com/mbox/"},{"id":7886,"url":"https://patchwork.plctlab.org/api/1.2/patches/7886/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/34d2f747237aeeda595560cfded8096d9bd1c28c.camel@espressif.com/","msgid":"<34d2f747237aeeda595560cfded8096d9bd1c28c.camel@espressif.com>","list_archive_url":null,"date":"2022-10-22T12:56:02","name":"[3/5] ld: xtensa: use default LD command line options for endianness","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/34d2f747237aeeda595560cfded8096d9bd1c28c.camel@espressif.com/mbox/"},{"id":7891,"url":"https://patchwork.plctlab.org/api/1.2/patches/7891/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/535b6208c1718b9acf3258575e1ebc0a65af9f07.camel@espressif.com/","msgid":"<535b6208c1718b9acf3258575e1ebc0a65af9f07.camel@espressif.com>","list_archive_url":null,"date":"2022-10-22T13:56:44","name":"[5/5] gdb: xtensa: add support for esp32, esp32s2, esp32s3 isa-modules","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/535b6208c1718b9acf3258575e1ebc0a65af9f07.camel@espressif.com/mbox/"},{"id":10456,"url":"https://patchwork.plctlab.org/api/1.2/patches/10456/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221025013347.68282-1-nelson@rivosinc.com/","msgid":"<20221025013347.68282-1-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-10-25T01:33:46","name":"[committed,1/2] RISC-V: Improve link time complexity.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221025013347.68282-1-nelson@rivosinc.com/mbox/"},{"id":10454,"url":"https://patchwork.plctlab.org/api/1.2/patches/10454/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221025013347.68282-2-nelson@rivosinc.com/","msgid":"<20221025013347.68282-2-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-10-25T01:33:47","name":"[committed,2/2] RISC-V: Should reset `again'\'' flag for _bfd_riscv_relax_pc.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221025013347.68282-2-nelson@rivosinc.com/mbox/"},{"id":10536,"url":"https://patchwork.plctlab.org/api/1.2/patches/10536/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/bb7b87e4-1893-5c86-4a14-92bafc818b03@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-25T07:24:56","name":"[v5,1/8] x86: constify parse_insn()'\''s input","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/bb7b87e4-1893-5c86-4a14-92bafc818b03@suse.com/mbox/"},{"id":10537,"url":"https://patchwork.plctlab.org/api/1.2/patches/10537/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b9273ae6-0218-54f8-5374-b265ed13b71a@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-25T07:25:26","name":"[v5,1/8] x86: introduce Pass2 insn attribute","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b9273ae6-0218-54f8-5374-b265ed13b71a@suse.com/mbox/"},{"id":10541,"url":"https://patchwork.plctlab.org/api/1.2/patches/10541/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7250dab9-e218-e6dd-4c74-23da9f611ab4@suse.com/","msgid":"<7250dab9-e218-e6dd-4c74-23da9f611ab4@suse.com>","list_archive_url":null,"date":"2022-10-25T07:26:11","name":"[v5,3/8] x86: re-work insn/suffix recognition","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7250dab9-e218-e6dd-4c74-23da9f611ab4@suse.com/mbox/"},{"id":10540,"url":"https://patchwork.plctlab.org/api/1.2/patches/10540/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/13fc630f-e116-0099-5c9e-2697df6519d7@suse.com/","msgid":"<13fc630f-e116-0099-5c9e-2697df6519d7@suse.com>","list_archive_url":null,"date":"2022-10-25T07:26:40","name":"[v5,4/8] ix86: don'\''t recognize/derive Q suffix in the common case","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/13fc630f-e116-0099-5c9e-2697df6519d7@suse.com/mbox/"},{"id":10543,"url":"https://patchwork.plctlab.org/api/1.2/patches/10543/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/74db429d-d203-eab8-4ae1-18b9ad416b02@suse.com/","msgid":"<74db429d-d203-eab8-4ae1-18b9ad416b02@suse.com>","list_archive_url":null,"date":"2022-10-25T07:27:11","name":"[v5,5/8] x86-64: allow HLE store of accumulator to absolute 32-bit address","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/74db429d-d203-eab8-4ae1-18b9ad416b02@suse.com/mbox/"},{"id":10542,"url":"https://patchwork.plctlab.org/api/1.2/patches/10542/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2e2f7841-de4e-b5de-e8d9-a47a6a4113c8@suse.com/","msgid":"<2e2f7841-de4e-b5de-e8d9-a47a6a4113c8@suse.com>","list_archive_url":null,"date":"2022-10-25T07:27:35","name":"[v5,6/8] x86: move bad-use-of-TLS-reloc check","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2e2f7841-de4e-b5de-e8d9-a47a6a4113c8@suse.com/mbox/"},{"id":10545,"url":"https://patchwork.plctlab.org/api/1.2/patches/10545/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/421bc96e-7591-6980-48e9-5af8c8b0775a@suse.com/","msgid":"<421bc96e-7591-6980-48e9-5af8c8b0775a@suse.com>","list_archive_url":null,"date":"2022-10-25T07:28:27","name":"[v5,7/8] x86: drop (now) stray IsString","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/421bc96e-7591-6980-48e9-5af8c8b0775a@suse.com/mbox/"},{"id":10546,"url":"https://patchwork.plctlab.org/api/1.2/patches/10546/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/06ff83d4-4633-a07b-70e5-a8e049981dd4@suse.com/","msgid":"<06ff83d4-4633-a07b-70e5-a8e049981dd4@suse.com>","list_archive_url":null,"date":"2022-10-25T07:29:18","name":"[v5,8/8] x86: further re-work insn/suffix recognition to also cover MOVSX","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/06ff83d4-4633-a07b-70e5-a8e049981dd4@suse.com/mbox/"},{"id":10777,"url":"https://patchwork.plctlab.org/api/1.2/patches/10777/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6a8e7a71acccd0efb9789dfb3edfa307e83bdaa1.1666702934.git.research_trasio@irq.a4lg.com/","msgid":"<6a8e7a71acccd0efb9789dfb3edfa307e83bdaa1.1666702934.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-25T13:04:02","name":"[RFC] RISC-V: Allocate \"various\" operand type","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6a8e7a71acccd0efb9789dfb3edfa307e83bdaa1.1666702934.git.research_trasio@irq.a4lg.com/mbox/"},{"id":11062,"url":"https://patchwork.plctlab.org/api/1.2/patches/11062/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jAhwbXhxJHL66v@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-26T05:07:19","name":"PR29720, objdump -S crashes if build-id is missing","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jAhwbXhxJHL66v@squeak.grove.modra.org/mbox/"},{"id":11063,"url":"https://patchwork.plctlab.org/api/1.2/patches/11063/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jAxD+NxpMIah6s@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-26T05:08:20","name":"som.c buffer overflow","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jAxD+NxpMIah6s@squeak.grove.modra.org/mbox/"},{"id":11064,"url":"https://patchwork.plctlab.org/api/1.2/patches/11064/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jBYw4lfRQfOZhi@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-26T05:10:59","name":"som.c reloc sanity checking","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jBYw4lfRQfOZhi@squeak.grove.modra.org/mbox/"},{"id":11080,"url":"https://patchwork.plctlab.org/api/1.2/patches/11080/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jY7hygm01PelCY@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-26T06:51:26","name":"segfault in objdump.c reloc_at","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jY7hygm01PelCY@squeak.grove.modra.org/mbox/"},{"id":11081,"url":"https://patchwork.plctlab.org/api/1.2/patches/11081/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jZWIeIvCCYm9/g@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-26T06:53:12","name":"Correct ELF reloc size sanity check","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jZWIeIvCCYm9/g@squeak.grove.modra.org/mbox/"},{"id":11082,"url":"https://patchwork.plctlab.org/api/1.2/patches/11082/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221026070009.3663574-1-ysato@users.sourceforge.jp/","msgid":"<20221026070009.3663574-1-ysato@users.sourceforge.jp>","list_archive_url":null,"date":"2022-10-26T07:00:09","name":"opcodes: RX fix invalid output.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221026070009.3663574-1-ysato@users.sourceforge.jp/mbox/"},{"id":11089,"url":"https://patchwork.plctlab.org/api/1.2/patches/11089/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jhW48kuVC8Ig2d@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-26T07:27:23","name":"buffer overflow in _bfd_XX_print_ce_compressed_pdata","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jhW48kuVC8Ig2d@squeak.grove.modra.org/mbox/"},{"id":11157,"url":"https://patchwork.plctlab.org/api/1.2/patches/11157/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c52dbd16-7e1b-c356-7a92-1ff089564ef7@suse.cz/","msgid":"","list_archive_url":null,"date":"2022-10-26T08:47:09","name":"tests: use canonical option name","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c52dbd16-7e1b-c356-7a92-1ff089564ef7@suse.cz/mbox/"},{"id":11526,"url":"https://patchwork.plctlab.org/api/1.2/patches/11526/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027031915.4013-1-lifang_xia@linux.alibaba.com/","msgid":"<20221027031915.4013-1-lifang_xia@linux.alibaba.com>","list_archive_url":null,"date":"2022-10-27T03:19:15","name":"[v2] RISC-V: Optimize relax of GP/call with max_alignment.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027031915.4013-1-lifang_xia@linux.alibaba.com/mbox/"},{"id":11619,"url":"https://patchwork.plctlab.org/api/1.2/patches/11619/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9df9d9e5bb4c7594b76c40613a349b4d2364e9c5.1666854355.git.research_trasio@irq.a4lg.com/","msgid":"<9df9d9e5bb4c7594b76c40613a349b4d2364e9c5.1666854355.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-27T07:06:01","name":"include: Define macro to ignore -Wdeprecated-declarations on GCC","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9df9d9e5bb4c7594b76c40613a349b4d2364e9c5.1666854355.git.research_trasio@irq.a4lg.com/mbox/"},{"id":11627,"url":"https://patchwork.plctlab.org/api/1.2/patches/11627/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1o06O9Pp8ncCsOw@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-27T07:36:08","name":"Fuzzed files in archives","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1o06O9Pp8ncCsOw@squeak.grove.modra.org/mbox/"},{"id":11658,"url":"https://patchwork.plctlab.org/api/1.2/patches/11658/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027084808.37252-1-nelson@rivosinc.com/","msgid":"<20221027084808.37252-1-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-10-27T08:48:08","name":"[committed] RISC-V: Fix build failures for -Werror=sign-compare.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027084808.37252-1-nelson@rivosinc.com/mbox/"},{"id":11921,"url":"https://patchwork.plctlab.org/api/1.2/patches/11921/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027190052.10536-1-mark@harmstone.com/","msgid":"<20221027190052.10536-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-27T19:00:51","name":"[1/2] ld: Add section header stream to PDB files","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027190052.10536-1-mark@harmstone.com/mbox/"},{"id":11922,"url":"https://patchwork.plctlab.org/api/1.2/patches/11922/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027190052.10536-2-mark@harmstone.com/","msgid":"<20221027190052.10536-2-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-27T19:00:52","name":"[2/2] ld: Add publics stream to PDB files","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027190052.10536-2-mark@harmstone.com/mbox/"},{"id":11965,"url":"https://patchwork.plctlab.org/api/1.2/patches/11965/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027202719.32497-1-palmer@rivosinc.com/","msgid":"<20221027202719.32497-1-palmer@rivosinc.com>","list_archive_url":null,"date":"2022-10-27T20:27:18","name":"[1/2] gas: NEWS: Add a missing newline","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027202719.32497-1-palmer@rivosinc.com/mbox/"},{"id":11966,"url":"https://patchwork.plctlab.org/api/1.2/patches/11966/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027202719.32497-2-palmer@rivosinc.com/","msgid":"<20221027202719.32497-2-palmer@rivosinc.com>","list_archive_url":null,"date":"2022-10-27T20:27:19","name":"[2/2] gas: NEWS: Note support for RISC-V Zawrs","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027202719.32497-2-palmer@rivosinc.com/mbox/"},{"id":12016,"url":"https://patchwork.plctlab.org/api/1.2/patches/12016/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/21ec9a18-fa89-0828-f625-499680022ec7@linux.ibm.com/","msgid":"<21ec9a18-fa89-0828-f625-499680022ec7@linux.ibm.com>","list_archive_url":null,"date":"2022-10-28T00:35:19","name":"[COMMITTED] PowerPC: Add support for RFC02653 - Dense Math Facility","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/21ec9a18-fa89-0828-f625-499680022ec7@linux.ibm.com/mbox/"},{"id":12017,"url":"https://patchwork.plctlab.org/api/1.2/patches/12017/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fd94047d-a070-45a6-3840-c105391718e0@linux.ibm.com/","msgid":"","list_archive_url":null,"date":"2022-10-28T00:37:18","name":"[COMMITTED] PowerPC: Add support for RFC02658 - MMA+ Outer-Product, Instructions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fd94047d-a070-45a6-3840-c105391718e0@linux.ibm.com/mbox/"},{"id":12122,"url":"https://patchwork.plctlab.org/api/1.2/patches/12122/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ac4f3f3c7115a824f73aca6935789b14d33c9a58.1666939920.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-28T06:53:02","name":"RISC-V: Fix build failure for -Werror=maybe-uninitialized","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ac4f3f3c7115a824f73aca6935789b14d33c9a58.1666939920.git.research_trasio@irq.a4lg.com/mbox/"},{"id":12181,"url":"https://patchwork.plctlab.org/api/1.2/patches/12181/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221028093840.19164-1-nelson@rivosinc.com/","msgid":"<20221028093840.19164-1-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-10-28T09:38:40","name":"RISC-V: Added SiFive custom cache control extensions.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221028093840.19164-1-nelson@rivosinc.com/mbox/"},{"id":12211,"url":"https://patchwork.plctlab.org/api/1.2/patches/12211/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4a280588-a85b-6ed3-634b-2b9cbc128f86@suse.com/","msgid":"<4a280588-a85b-6ed3-634b-2b9cbc128f86@suse.com>","list_archive_url":null,"date":"2022-10-28T10:06:35","name":"RISC-V/gas: fix build with certain gcc versions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4a280588-a85b-6ed3-634b-2b9cbc128f86@suse.com/mbox/"},{"id":12249,"url":"https://patchwork.plctlab.org/api/1.2/patches/12249/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/eb0e1bff-675e-72db-b8b1-b0f0e50b7121@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-28T12:35:35","name":"x86: minor improvements to optimize_imm() (part III)","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/eb0e1bff-675e-72db-b8b1-b0f0e50b7121@suse.com/mbox/"},{"id":12382,"url":"https://patchwork.plctlab.org/api/1.2/patches/12382/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/17f57574936af82be381a1451eac56b3709b60bb.1666968673.git.research_trasio@irq.a4lg.com/","msgid":"<17f57574936af82be381a1451eac56b3709b60bb.1666968673.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-28T14:52:12","name":"RISC-V: Emit mapping symbol with ISA string if non-default arch is used","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/17f57574936af82be381a1451eac56b3709b60bb.1666968673.git.research_trasio@irq.a4lg.com/mbox/"},{"id":12627,"url":"https://patchwork.plctlab.org/api/1.2/patches/12627/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221029034432.49859-1-nelson@rivosinc.com/","msgid":"<20221029034432.49859-1-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-10-29T03:44:32","name":"[committed] RISC-V: Always generate mapping symbols at the start of the sections.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221029034432.49859-1-nelson@rivosinc.com/mbox/"},{"id":12629,"url":"https://patchwork.plctlab.org/api/1.2/patches/12629/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1yxgzNJg5M48uPI@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-29T04:52:19","name":"NULL dereference read in som_write_object_contents","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1yxgzNJg5M48uPI@squeak.grove.modra.org/mbox/"},{"id":12630,"url":"https://patchwork.plctlab.org/api/1.2/patches/12630/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1yxnSHLY+FeB5DQ@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-29T04:52:45","name":"Fix small objcopy memory leak","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1yxnSHLY+FeB5DQ@squeak.grove.modra.org/mbox/"},{"id":12631,"url":"https://patchwork.plctlab.org/api/1.2/patches/12631/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1yxxfpJz+Jx4KTh@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-29T04:53:25","name":"pef: sanity check before malloc","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1yxxfpJz+Jx4KTh@squeak.grove.modra.org/mbox/"},{"id":12950,"url":"https://patchwork.plctlab.org/api/1.2/patches/12950/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-2-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-2-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:36","name":"[V3,01/15] sframe.h: Add SFrame format definition","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-2-indu.bhagat@oracle.com/mbox/"},{"id":12952,"url":"https://patchwork.plctlab.org/api/1.2/patches/12952/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-3-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-3-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:37","name":"[V3,02/15] gas: add new command line option --gsframe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-3-indu.bhagat@oracle.com/mbox/"},{"id":12951,"url":"https://patchwork.plctlab.org/api/1.2/patches/12951/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-4-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-4-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:38","name":"[V3,03/15] gas: generate .sframe from CFI directives","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-4-indu.bhagat@oracle.com/mbox/"},{"id":12956,"url":"https://patchwork.plctlab.org/api/1.2/patches/12956/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-5-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-5-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:39","name":"[V3,04/15] gas: testsuite: add new tests for SFrame unwind info","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-5-indu.bhagat@oracle.com/mbox/"},{"id":12955,"url":"https://patchwork.plctlab.org/api/1.2/patches/12955/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-6-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-6-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:40","name":"[V3,05/15] libsframe: add the SFrame library","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-6-indu.bhagat@oracle.com/mbox/"},{"id":12959,"url":"https://patchwork.plctlab.org/api/1.2/patches/12959/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-7-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-7-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:41","name":"[V3,06/15] bfd: linker: merge .sframe sections","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-7-indu.bhagat@oracle.com/mbox/"},{"id":12961,"url":"https://patchwork.plctlab.org/api/1.2/patches/12961/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-8-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-8-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:42","name":"[V3,07/15] readelf/objdump: support for SFrame section","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-8-indu.bhagat@oracle.com/mbox/"},{"id":12962,"url":"https://patchwork.plctlab.org/api/1.2/patches/12962/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-9-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-9-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:43","name":"[V3,08/15] unwinder: generate backtrace using SFrame format","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-9-indu.bhagat@oracle.com/mbox/"},{"id":12963,"url":"https://patchwork.plctlab.org/api/1.2/patches/12963/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-10-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-10-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:44","name":"[V3,09/15] unwinder: Add SFrame unwinder tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-10-indu.bhagat@oracle.com/mbox/"},{"id":12964,"url":"https://patchwork.plctlab.org/api/1.2/patches/12964/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-11-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-11-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:45","name":"[V3,10/15] gdb: sim: buildsystem changes to accommodate libsframe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-11-indu.bhagat@oracle.com/mbox/"},{"id":12957,"url":"https://patchwork.plctlab.org/api/1.2/patches/12957/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-12-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-12-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:46","name":"[V3,11/15] libctf: add libsframe to LDFLAGS and LIBS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-12-indu.bhagat@oracle.com/mbox/"},{"id":12960,"url":"https://patchwork.plctlab.org/api/1.2/patches/12960/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-13-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-13-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:47","name":"[V3,12/15] src-release.sh: Add libsframe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-13-indu.bhagat@oracle.com/mbox/"},{"id":12953,"url":"https://patchwork.plctlab.org/api/1.2/patches/12953/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-14-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-14-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:48","name":"[V3,13/15] binutils/NEWS: add text for SFrame support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-14-indu.bhagat@oracle.com/mbox/"},{"id":12954,"url":"https://patchwork.plctlab.org/api/1.2/patches/12954/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-15-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-15-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:49","name":"[V3,14/15] gas/NEWS: add text about new command line option and SFrame support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-15-indu.bhagat@oracle.com/mbox/"},{"id":12958,"url":"https://patchwork.plctlab.org/api/1.2/patches/12958/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-16-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-16-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:50","name":"[V3,15/15] doc: add SFrame spec file","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-16-indu.bhagat@oracle.com/mbox/"},{"id":12988,"url":"https://patchwork.plctlab.org/api/1.2/patches/12988/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y15KFY32CyFhh/+u@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-30T09:55:33","name":"Pool section entries for DWP version 1","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y15KFY32CyFhh/+u@squeak.grove.modra.org/mbox/"},{"id":13076,"url":"https://patchwork.plctlab.org/api/1.2/patches/13076/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031001554.14615-1-mark@harmstone.com/","msgid":"<20221031001554.14615-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-31T00:15:52","name":"[v2,1/3] ld: Use %E in einfo in pdb.c","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031001554.14615-1-mark@harmstone.com/mbox/"},{"id":13078,"url":"https://patchwork.plctlab.org/api/1.2/patches/13078/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031001554.14615-2-mark@harmstone.com/","msgid":"<20221031001554.14615-2-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-31T00:15:53","name":"[v2,2/3] ld: Add section header stream to PDB files","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031001554.14615-2-mark@harmstone.com/mbox/"},{"id":13077,"url":"https://patchwork.plctlab.org/api/1.2/patches/13077/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031001554.14615-3-mark@harmstone.com/","msgid":"<20221031001554.14615-3-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-31T00:15:54","name":"[v2,3/3] ld: Add publics stream to PDB files","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031001554.14615-3-mark@harmstone.com/mbox/"},{"id":13106,"url":"https://patchwork.plctlab.org/api/1.2/patches/13106/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031030507.35588-2-haochen.jiang@intel.com/","msgid":"<20221031030507.35588-2-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-31T03:05:02","name":"[1/6] Support Intel AVX-IFMA","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031030507.35588-2-haochen.jiang@intel.com/mbox/"},{"id":13105,"url":"https://patchwork.plctlab.org/api/1.2/patches/13105/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031030507.35588-3-haochen.jiang@intel.com/","msgid":"<20221031030507.35588-3-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-31T03:05:03","name":"[2/6] Support Intel AVX-VNNI-INT8","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031030507.35588-3-haochen.jiang@intel.com/mbox/"},{"id":13103,"url":"https://patchwork.plctlab.org/api/1.2/patches/13103/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031030507.35588-4-haochen.jiang@intel.com/","msgid":"<20221031030507.35588-4-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-31T03:05:04","name":"[3/6] Support Intel CMPccXADD","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031030507.35588-4-haochen.jiang@intel.com/mbox/"},{"id":13101,"url":"https://patchwork.plctlab.org/api/1.2/patches/13101/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031030507.35588-5-haochen.jiang@intel.com/","msgid":"<20221031030507.35588-5-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-31T03:05:05","name":"[4/6] Add handler for more i386_cpu_flags","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031030507.35588-5-haochen.jiang@intel.com/mbox/"},{"id":13104,"url":"https://patchwork.plctlab.org/api/1.2/patches/13104/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031030507.35588-6-haochen.jiang@intel.com/","msgid":"<20221031030507.35588-6-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-31T03:05:06","name":"[5/6] Support Intel WRMSRNS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031030507.35588-6-haochen.jiang@intel.com/mbox/"},{"id":13102,"url":"https://patchwork.plctlab.org/api/1.2/patches/13102/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031030507.35588-7-haochen.jiang@intel.com/","msgid":"<20221031030507.35588-7-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-31T03:05:07","name":"[6/6] Support Intel MSRLIST","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031030507.35588-7-haochen.jiang@intel.com/mbox/"},{"id":13120,"url":"https://patchwork.plctlab.org/api/1.2/patches/13120/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031060601.38460-2-haochen.jiang@intel.com/","msgid":"<20221031060601.38460-2-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-31T06:06:00","name":"[1/2] i386: Add and ","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031060601.38460-2-haochen.jiang@intel.com/mbox/"},{"id":13121,"url":"https://patchwork.plctlab.org/api/1.2/patches/13121/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031060601.38460-3-haochen.jiang@intel.com/","msgid":"<20221031060601.38460-3-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-31T06:06:01","name":"[2/2] Support Intel AVX-NE-CONVERT","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031060601.38460-3-haochen.jiang@intel.com/mbox/"},{"id":13188,"url":"https://patchwork.plctlab.org/api/1.2/patches/13188/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9f6f8888-4dc1-a6b0-0590-35fc8a276369@suse.com/","msgid":"<9f6f8888-4dc1-a6b0-0590-35fc8a276369@suse.com>","list_archive_url":null,"date":"2022-10-31T10:18:20","name":"x86: drop bogus Tbyte","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9f6f8888-4dc1-a6b0-0590-35fc8a276369@suse.com/mbox/"},{"id":13213,"url":"https://patchwork.plctlab.org/api/1.2/patches/13213/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4f1aac95-fea5-2279-cb18-dfcdb51a2589@arm.com/","msgid":"<4f1aac95-fea5-2279-cb18-dfcdb51a2589@arm.com>","list_archive_url":null,"date":"2022-10-31T11:14:44","name":"aarch64: Add support for Common Short Sequence Compression extension","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4f1aac95-fea5-2279-cb18-dfcdb51a2589@arm.com/mbox/"}],"public":true,"mbox":"https://patchwork.plctlab.org/bundle/patchwork-bot/binutils-gdb_2022-10/mbox/"},{"id":7,"url":"https://patchwork.plctlab.org/api/1.2/bundles/7/","web_url":"https://patchwork.plctlab.org/bundle/patchwork-bot/binutils-gdb_2022-09/","project":{"id":2,"url":"https://patchwork.plctlab.org/api/1.2/projects/2/","name":"binutils-gdb","link_name":"binutils-gdb","list_id":"binutils.sourceware.org","list_email":"binutils@sourceware.org","web_url":"https://github.com/wangliu-iscas/Patchwork-Bundles/blob/main/binutils-gdb.md","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"name":"binutils-gdb_2022-09","owner":{"id":3,"url":"https://patchwork.plctlab.org/api/1.2/users/3/","username":"patchwork-bot","first_name":"","last_name":"","email":"ouuuleilei@gmail.com"},"patches":[{"id":1573,"url":"https://patchwork.plctlab.org/api/1.2/patches/1573/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930073211.2634-1-jiawei@iscas.ac.cn/","msgid":"<20220930073211.2634-1-jiawei@iscas.ac.cn>","list_archive_url":null,"date":"2022-09-30T07:32:11","name":"[V2] RISC-V: Add Smepmp CSR '\''mseccfg'\'' define and testcases.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930073211.2634-1-jiawei@iscas.ac.cn/mbox/"},{"id":1577,"url":"https://patchwork.plctlab.org/api/1.2/patches/1577/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/76fa0c3c-2303-ebdf-a765-ac4731581517@suse.com/","msgid":"<76fa0c3c-2303-ebdf-a765-ac4731581517@suse.com>","list_archive_url":null,"date":"2022-09-30T08:54:18","name":"objcopy: avoid \"shadowing\" of remove() function name","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/76fa0c3c-2303-ebdf-a765-ac4731581517@suse.com/mbox/"},{"id":1579,"url":"https://patchwork.plctlab.org/api/1.2/patches/1579/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930085852.71213-1-nelson@rivosinc.com/","msgid":"<20220930085852.71213-1-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-09-30T08:58:51","name":"[1/2] RISC-V: Output mapping symbols with ISA string.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930085852.71213-1-nelson@rivosinc.com/mbox/"},{"id":1578,"url":"https://patchwork.plctlab.org/api/1.2/patches/1578/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930085852.71213-2-nelson@rivosinc.com/","msgid":"<20220930085852.71213-2-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-09-30T08:58:52","name":"[2/2] RISC-V: Refer mapping symbol to R_RISCV_RELAX for rvc relaxations.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930085852.71213-2-nelson@rivosinc.com/mbox/"},{"id":1581,"url":"https://patchwork.plctlab.org/api/1.2/patches/1581/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930092058.71286-1-nelson@rivosinc.com/","msgid":"<20220930092058.71286-1-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-09-30T09:20:57","name":"[1/2] RISC-V: Output mapping symbols with ISA string.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930092058.71286-1-nelson@rivosinc.com/mbox/"},{"id":1580,"url":"https://patchwork.plctlab.org/api/1.2/patches/1580/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930092058.71286-2-nelson@rivosinc.com/","msgid":"<20220930092058.71286-2-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-09-30T09:20:58","name":"[2/2] RISC-V: Refer mapping symbol to R_RISCV_RELAX for rvc relaxations.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930092058.71286-2-nelson@rivosinc.com/mbox/"},{"id":1582,"url":"https://patchwork.plctlab.org/api/1.2/patches/1582/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5874dd79-0cf5-d65c-7ea2-13adfc799c0f@suse.com/","msgid":"<5874dd79-0cf5-d65c-7ea2-13adfc799c0f@suse.com>","list_archive_url":null,"date":"2022-09-30T09:41:29","name":"RISC-V: fix build after \"Add support for arbitrary immediate encoding formats\"","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5874dd79-0cf5-d65c-7ea2-13adfc799c0f@suse.com/mbox/"},{"id":1583,"url":"https://patchwork.plctlab.org/api/1.2/patches/1583/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/57d8ac2a-5757-3776-9924-99c17ca69938@suse.com/","msgid":"<57d8ac2a-5757-3776-9924-99c17ca69938@suse.com>","list_archive_url":null,"date":"2022-09-30T09:42:08","name":"RISC-V: fallout from \"re-arrange opcode table for consistent alias handling\"","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/57d8ac2a-5757-3776-9924-99c17ca69938@suse.com/mbox/"},{"id":1584,"url":"https://patchwork.plctlab.org/api/1.2/patches/1584/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e76ef8f7-72b9-5103-cb43-9608af01d017@suse.com/","msgid":"","list_archive_url":null,"date":"2022-09-30T09:42:50","name":"RISC-V: don'\''t cast expressions'\'' X_add_number to long in diagnostics","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e76ef8f7-72b9-5103-cb43-9608af01d017@suse.com/mbox/"},{"id":1585,"url":"https://patchwork.plctlab.org/api/1.2/patches/1585/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/61355429-24b3-17d0-ab03-6fa57ee861d5@suse.cz/","msgid":"<61355429-24b3-17d0-ab03-6fa57ee861d5@suse.cz>","list_archive_url":null,"date":"2022-09-30T09:48:52","name":"[RFC] add --enable-zstd-compressed-debug-sections configure option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/61355429-24b3-17d0-ab03-6fa57ee861d5@suse.cz/mbox/"},{"id":1586,"url":"https://patchwork.plctlab.org/api/1.2/patches/1586/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930103919.323690-1-christoph.muellner@vrull.eu/","msgid":"<20220930103919.323690-1-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2022-09-30T10:39:19","name":"RISC-V: Eliminate long-casts of X_add_number in diagnostics","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930103919.323690-1-christoph.muellner@vrull.eu/mbox/"},{"id":1590,"url":"https://patchwork.plctlab.org/api/1.2/patches/1590/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/DM6PR12MB4219C943049C6D883DEA3E55E7569@DM6PR12MB4219.namprd12.prod.outlook.com/","msgid":"","list_archive_url":null,"date":"2022-09-30T11:41:37","name":"[V2] Ignore DWARF debug information for -gsplit-dwarf with dwarf-5.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/DM6PR12MB4219C943049C6D883DEA3E55E7569@DM6PR12MB4219.namprd12.prod.outlook.com/mbox/"},{"id":1591,"url":"https://patchwork.plctlab.org/api/1.2/patches/1591/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c10321f9-d289-ef84-d263-bc278fb3d31b@suse.com/","msgid":"","list_archive_url":null,"date":"2022-09-30T11:59:04","name":"[1/4] RISC-V/gas: drop riscv_subsets static variable","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c10321f9-d289-ef84-d263-bc278fb3d31b@suse.com/mbox/"},{"id":1593,"url":"https://patchwork.plctlab.org/api/1.2/patches/1593/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3244eea0-c18c-e49a-4588-d69423130226@suse.com/","msgid":"<3244eea0-c18c-e49a-4588-d69423130226@suse.com>","list_archive_url":null,"date":"2022-09-30T11:59:23","name":"[2/4] RISC-V/gas: drop stray call to install_insn()","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3244eea0-c18c-e49a-4588-d69423130226@suse.com/mbox/"},{"id":1592,"url":"https://patchwork.plctlab.org/api/1.2/patches/1592/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/385d01fd-7e57-1f3f-1bae-30aa0c313d63@suse.com/","msgid":"<385d01fd-7e57-1f3f-1bae-30aa0c313d63@suse.com>","list_archive_url":null,"date":"2022-09-30T11:59:45","name":"[3/4] RISC-V/gas: don'\''t open-code insn_length()","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/385d01fd-7e57-1f3f-1bae-30aa0c313d63@suse.com/mbox/"},{"id":1594,"url":"https://patchwork.plctlab.org/api/1.2/patches/1594/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f5757acf-7b90-a0e3-5eea-3b97cc226930@suse.com/","msgid":"","list_archive_url":null,"date":"2022-09-30T12:00:12","name":"[4/4] RISC-V/gas: allow generating up to 176-bit instructions with .insn","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f5757acf-7b90-a0e3-5eea-3b97cc226930@suse.com/mbox/"},{"id":1596,"url":"https://patchwork.plctlab.org/api/1.2/patches/1596/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930140503.38233-1-chigot@adacore.com/","msgid":"<20220930140503.38233-1-chigot@adacore.com>","list_archive_url":null,"date":"2022-09-30T14:05:03","name":"ld/testsuite: consistently add board_ldflags when linking with GCC","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930140503.38233-1-chigot@adacore.com/mbox/"}],"public":true,"mbox":"https://patchwork.plctlab.org/bundle/patchwork-bot/binutils-gdb_2022-09/mbox/"},{"id":9,"url":"https://patchwork.plctlab.org/api/1.2/bundles/9/","web_url":"https://patchwork.plctlab.org/bundle/patchwork-bot/binutils-gdb_2022-11/","project":{"id":2,"url":"https://patchwork.plctlab.org/api/1.2/projects/2/","name":"binutils-gdb","link_name":"binutils-gdb","list_id":"binutils.sourceware.org","list_email":"binutils@sourceware.org","web_url":"https://github.com/wangliu-iscas/Patchwork-Bundles/blob/main/binutils-gdb.md","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"name":"binutils-gdb_2022-11","owner":{"id":3,"url":"https://patchwork.plctlab.org/api/1.2/users/3/","username":"patchwork-bot","first_name":"","last_name":"","email":"ouuuleilei@gmail.com"},"patches":[{"id":13337,"url":"https://patchwork.plctlab.org/api/1.2/patches/13337/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031160625.684434-1-hjl.tools@gmail.com/","msgid":"<20221031160625.684434-1-hjl.tools@gmail.com>","list_archive_url":null,"date":"2022-10-31T16:06:25","name":"x86: Silence GCC 12 warning on tc-i386.c","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031160625.684434-1-hjl.tools@gmail.com/mbox/"},{"id":13350,"url":"https://patchwork.plctlab.org/api/1.2/patches/13350/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c8d25b29-37fe-9623-a799-e67e1f991743@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-31T17:00:56","name":"x86: simplify expressions in update_imm()","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c8d25b29-37fe-9623-a799-e67e1f991743@suse.com/mbox/"},{"id":13487,"url":"https://patchwork.plctlab.org/api/1.2/patches/13487/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/CAMe9rOohVjin92PTeeiu_dvAtzYJn4dGtu5E=OxYfbyteraZWw@mail.gmail.com/","msgid":"","list_archive_url":null,"date":"2022-11-01T00:08:04","name":"binutils: Run PR binutils/26160 test","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/CAMe9rOohVjin92PTeeiu_dvAtzYJn4dGtu5E=OxYfbyteraZWw@mail.gmail.com/mbox/"},{"id":13621,"url":"https://patchwork.plctlab.org/api/1.2/patches/13621/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221101105724.1527333-1-aburgess@redhat.com/","msgid":"<20221101105724.1527333-1-aburgess@redhat.com>","list_archive_url":null,"date":"2022-11-01T10:57:24","name":"[PUSHED] opcodes/arm: silence compiler warning about uninitialized variable use","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221101105724.1527333-1-aburgess@redhat.com/mbox/"},{"id":13628,"url":"https://patchwork.plctlab.org/api/1.2/patches/13628/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221101111802.1532080-1-aburgess@redhat.com/","msgid":"<20221101111802.1532080-1-aburgess@redhat.com>","list_archive_url":null,"date":"2022-11-01T11:18:02","name":"[PUSHED] opcodes/arm: don'\''t pass non-string literal to printf like function","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221101111802.1532080-1-aburgess@redhat.com/mbox/"},{"id":13747,"url":"https://patchwork.plctlab.org/api/1.2/patches/13747/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/yw8jbkpqk6vw.fsf@arm.com/","msgid":"","list_archive_url":null,"date":"2022-11-01T15:54:11","name":"[Binutils-2.39,backport,GAS] arm: Use DWARF numbering convention for pseudo-register representation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/yw8jbkpqk6vw.fsf@arm.com/mbox/"},{"id":13993,"url":"https://patchwork.plctlab.org/api/1.2/patches/13993/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221102020752.24441-1-mark@harmstone.com/","msgid":"<20221102020752.24441-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-11-02T02:07:52","name":"ld: Add module information substream to PDB files","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221102020752.24441-1-mark@harmstone.com/mbox/"},{"id":14028,"url":"https://patchwork.plctlab.org/api/1.2/patches/14028/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221102050430.1053-1-nelson@rivosinc.com/","msgid":"<20221102050430.1053-1-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-11-02T05:04:30","name":"[committed] RISC-V: Fixed the missing $x+arch when adding odd paddings for alignment.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221102050430.1053-1-nelson@rivosinc.com/mbox/"},{"id":14043,"url":"https://patchwork.plctlab.org/api/1.2/patches/14043/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221102063046.31551-1-rjiejie@linux.alibaba.com/","msgid":"<20221102063046.31551-1-rjiejie@linux.alibaba.com>","list_archive_url":null,"date":"2022-11-02T06:30:46","name":"gas/doc/internals.texi: fix typo","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221102063046.31551-1-rjiejie@linux.alibaba.com/mbox/"},{"id":14069,"url":"https://patchwork.plctlab.org/api/1.2/patches/14069/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221102080112.33378-1-rjiejie@linux.alibaba.com/","msgid":"<20221102080112.33378-1-rjiejie@linux.alibaba.com>","list_archive_url":null,"date":"2022-11-02T08:01:12","name":"[v2] Support multiple .eh_frame sections","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221102080112.33378-1-rjiejie@linux.alibaba.com/mbox/"},{"id":14409,"url":"https://patchwork.plctlab.org/api/1.2/patches/14409/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221102172923.4009281-1-christophe.lyon@arm.com/","msgid":"<20221102172923.4009281-1-christophe.lyon@arm.com>","list_archive_url":null,"date":"2022-11-02T17:29:23","name":"arm: PR 29739 Fix typo where '\''; '\'' should not have been replaced with '\''@'\''","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221102172923.4009281-1-christophe.lyon@arm.com/mbox/"},{"id":14588,"url":"https://patchwork.plctlab.org/api/1.2/patches/14588/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221103020409.37322-1-rjiejie@linux.alibaba.com/","msgid":"<20221103020409.37322-1-rjiejie@linux.alibaba.com>","list_archive_url":null,"date":"2022-11-03T02:04:09","name":"[v3] Support multiple .eh_frame sections","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221103020409.37322-1-rjiejie@linux.alibaba.com/mbox/"},{"id":14602,"url":"https://patchwork.plctlab.org/api/1.2/patches/14602/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221103024604.614-1-mark@harmstone.com/","msgid":"<20221103024604.614-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-11-03T02:46:04","name":"[v2] ld: Add module information substream to PDB files","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221103024604.614-1-mark@harmstone.com/mbox/"},{"id":14706,"url":"https://patchwork.plctlab.org/api/1.2/patches/14706/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221103071519.3510462-1-luis.machado@arm.com/","msgid":"<20221103071519.3510462-1-luis.machado@arm.com>","list_archive_url":null,"date":"2022-11-03T07:15:19","name":"[opcodes/arm] Fix potential null pointer dereferences","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221103071519.3510462-1-luis.machado@arm.com/mbox/"},{"id":14840,"url":"https://patchwork.plctlab.org/api/1.2/patches/14840/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/283a86ebf0941f0f63dc1a590ec3d547bd5d69e8.1667478033.git.research_trasio@irq.a4lg.com/","msgid":"<283a86ebf0941f0f63dc1a590ec3d547bd5d69e8.1667478033.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-03T12:26:28","name":"[REVIEW,ONLY,1/2] NEAR-RATIFICATION RISC-V: Add '\''Ssstateen'\'' extension and its CSRs","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/283a86ebf0941f0f63dc1a590ec3d547bd5d69e8.1667478033.git.research_trasio@irq.a4lg.com/mbox/"},{"id":14841,"url":"https://patchwork.plctlab.org/api/1.2/patches/14841/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8083ad9d5339afdeb7f1ba88ee6af0665dcc76d5.1667478033.git.research_trasio@irq.a4lg.com/","msgid":"<8083ad9d5339afdeb7f1ba88ee6af0665dcc76d5.1667478033.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-03T12:26:29","name":"[REVIEW,ONLY,2/2] NEAR-RATIFICATION RISC-V: Add platform property/capability extensions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8083ad9d5339afdeb7f1ba88ee6af0665dcc76d5.1667478033.git.research_trasio@irq.a4lg.com/mbox/"},{"id":14894,"url":"https://patchwork.plctlab.org/api/1.2/patches/14894/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e53fbf5025e59fe6a3481b9c1fe37e4f6cf6e03d.1667483581.git.aburgess@redhat.com/","msgid":"","list_archive_url":null,"date":"2022-11-03T13:58:12","name":"[1/2] opcodes/mips: use .word/.short for undefined instructions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e53fbf5025e59fe6a3481b9c1fe37e4f6cf6e03d.1667483581.git.aburgess@redhat.com/mbox/"},{"id":14893,"url":"https://patchwork.plctlab.org/api/1.2/patches/14893/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ca81edb86580566b1641ad140eb2bed385160ab7.1667483581.git.aburgess@redhat.com/","msgid":"","list_archive_url":null,"date":"2022-11-03T13:58:13","name":"[2/2] libopcodes/mips: add support for disassembler styling","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ca81edb86580566b1641ad140eb2bed385160ab7.1667483581.git.aburgess@redhat.com/mbox/"},{"id":15465,"url":"https://patchwork.plctlab.org/api/1.2/patches/15465/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/926e5154-b40b-9df8-d770-a8bf7d40e40e@suse.com/","msgid":"<926e5154-b40b-9df8-d770-a8bf7d40e40e@suse.com>","list_archive_url":null,"date":"2022-11-04T10:50:38","name":"[v6,1/7] x86: constify parse_insn()'\''s input","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/926e5154-b40b-9df8-d770-a8bf7d40e40e@suse.com/mbox/"},{"id":15466,"url":"https://patchwork.plctlab.org/api/1.2/patches/15466/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/07ef67fd-752c-ad1f-b8cb-4eaec1f420fc@suse.com/","msgid":"<07ef67fd-752c-ad1f-b8cb-4eaec1f420fc@suse.com>","list_archive_url":null,"date":"2022-11-04T10:51:34","name":"[v6,2/7] x86: re-work insn/suffix recognition","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/07ef67fd-752c-ad1f-b8cb-4eaec1f420fc@suse.com/mbox/"},{"id":15467,"url":"https://patchwork.plctlab.org/api/1.2/patches/15467/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ee8fd655-19a5-d944-0f5e-4351b88a59f9@suse.com/","msgid":"","list_archive_url":null,"date":"2022-11-04T10:52:02","name":"[v6,3/7] ix86: don'\''t recognize/derive Q suffix in the common case","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ee8fd655-19a5-d944-0f5e-4351b88a59f9@suse.com/mbox/"},{"id":15468,"url":"https://patchwork.plctlab.org/api/1.2/patches/15468/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/15ab2cf5-f1ac-e882-c415-6318f1bcc7f0@suse.com/","msgid":"<15ab2cf5-f1ac-e882-c415-6318f1bcc7f0@suse.com>","list_archive_url":null,"date":"2022-11-04T10:52:31","name":"[v6,4/7] x86-64: allow HLE store of accumulator to absolute 32-bit address","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/15ab2cf5-f1ac-e882-c415-6318f1bcc7f0@suse.com/mbox/"},{"id":15470,"url":"https://patchwork.plctlab.org/api/1.2/patches/15470/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/352d1e49-ac9f-ee86-7e9d-74f79744268b@suse.com/","msgid":"<352d1e49-ac9f-ee86-7e9d-74f79744268b@suse.com>","list_archive_url":null,"date":"2022-11-04T10:53:14","name":"[v6,5/7] x86: move bad-use-of-TLS-reloc check","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/352d1e49-ac9f-ee86-7e9d-74f79744268b@suse.com/mbox/"},{"id":15469,"url":"https://patchwork.plctlab.org/api/1.2/patches/15469/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c1913bf6-7328-e45f-69f1-20da1954af43@suse.com/","msgid":"","list_archive_url":null,"date":"2022-11-04T10:53:52","name":"[v6,6/7] x86: drop (now) stray IsString","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c1913bf6-7328-e45f-69f1-20da1954af43@suse.com/mbox/"},{"id":15471,"url":"https://patchwork.plctlab.org/api/1.2/patches/15471/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2baf6a9d-c1bf-660d-bbca-99b1604f5478@suse.com/","msgid":"<2baf6a9d-c1bf-660d-bbca-99b1604f5478@suse.com>","list_archive_url":null,"date":"2022-11-04T10:54:30","name":"[v6,7/7] x86: further re-work insn/suffix recognition to also cover MOVSX","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2baf6a9d-c1bf-660d-bbca-99b1604f5478@suse.com/mbox/"},{"id":15472,"url":"https://patchwork.plctlab.org/api/1.2/patches/15472/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104110132.694984-1-aburgess@redhat.com/","msgid":"<20221104110132.694984-1-aburgess@redhat.com>","list_archive_url":null,"date":"2022-11-04T11:01:32","name":"[PUSHED] opcodes/arm: silence compiler warning about uninitialized variable use","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104110132.694984-1-aburgess@redhat.com/mbox/"},{"id":15473,"url":"https://patchwork.plctlab.org/api/1.2/patches/15473/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104110214.129095-1-christophe.lyon@arm.com/","msgid":"<20221104110214.129095-1-christophe.lyon@arm.com>","list_archive_url":null,"date":"2022-11-04T11:02:14","name":"configure: require libzstd >= 1.4.0","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104110214.129095-1-christophe.lyon@arm.com/mbox/"},{"id":15485,"url":"https://patchwork.plctlab.org/api/1.2/patches/15485/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104115038.8957-1-nelson@rivosinc.com/","msgid":"<20221104115038.8957-1-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-11-04T11:50:37","name":"[1/2] RISC-V: File-level architecture shouldn'\''t be affected by section-level ones.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104115038.8957-1-nelson@rivosinc.com/mbox/"},{"id":15486,"url":"https://patchwork.plctlab.org/api/1.2/patches/15486/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104115038.8957-2-nelson@rivosinc.com/","msgid":"<20221104115038.8957-2-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-11-04T11:50:38","name":"[2/2] RISC-V: Clarify the suppress rule of mapping symbol with architecture string.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104115038.8957-2-nelson@rivosinc.com/mbox/"},{"id":15509,"url":"https://patchwork.plctlab.org/api/1.2/patches/15509/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/cc133c88-9ce9-5e3a-a8f7-ad72766862b9@suse.com/","msgid":"","list_archive_url":null,"date":"2022-11-04T13:12:07","name":"x86: adjust recently introduced testcases","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/cc133c88-9ce9-5e3a-a8f7-ad72766862b9@suse.com/mbox/"},{"id":15679,"url":"https://patchwork.plctlab.org/api/1.2/patches/15679/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104163328.2274371-1-chigot@adacore.com/","msgid":"<20221104163328.2274371-1-chigot@adacore.com>","list_archive_url":null,"date":"2022-11-04T16:33:28","name":"ld/testsuite: skip tests related to -shared when disabled","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104163328.2274371-1-chigot@adacore.com/mbox/"},{"id":15751,"url":"https://patchwork.plctlab.org/api/1.2/patches/15751/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104190216.1352855-1-indu.bhagat@oracle.com/","msgid":"<20221104190216.1352855-1-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-04T19:02:16","name":"[V3.1,11/15] libctf: add libsframe to LDFLAGS and LIBS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104190216.1352855-1-indu.bhagat@oracle.com/mbox/"},{"id":15792,"url":"https://patchwork.plctlab.org/api/1.2/patches/15792/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104205547.3728827-1-hjl.tools@gmail.com/","msgid":"<20221104205547.3728827-1-hjl.tools@gmail.com>","list_archive_url":null,"date":"2022-11-04T20:55:47","name":"i386: Check invalid (%dx) usage","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104205547.3728827-1-hjl.tools@gmail.com/mbox/"},{"id":15794,"url":"https://patchwork.plctlab.org/api/1.2/patches/15794/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104210134.1721620-1-indu.bhagat@oracle.com/","msgid":"<20221104210134.1721620-1-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-04T21:01:34","name":"[V3.2,11/15] libctf: add libsframe to LDFLAGS and LIBS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104210134.1721620-1-indu.bhagat@oracle.com/mbox/"},{"id":15959,"url":"https://patchwork.plctlab.org/api/1.2/patches/15959/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c620070e3e335df2b487d3836e20d251dac37525.1667651354.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-11-05T12:29:07","name":"[01/12] RISC-V: Remove unnecessary empty matching file","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c620070e3e335df2b487d3836e20d251dac37525.1667651354.git.research_trasio@irq.a4lg.com/mbox/"},{"id":15961,"url":"https://patchwork.plctlab.org/api/1.2/patches/15961/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4496235002a396043598ab9755bd8eda5c077b1f.1667651354.git.research_trasio@irq.a4lg.com/","msgid":"<4496235002a396043598ab9755bd8eda5c077b1f.1667651354.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-05T12:29:08","name":"[02/12] RISC-V: Tidy disassembler corner case tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4496235002a396043598ab9755bd8eda5c077b1f.1667651354.git.research_trasio@irq.a4lg.com/mbox/"},{"id":15960,"url":"https://patchwork.plctlab.org/api/1.2/patches/15960/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a9229a2798480f00bf12ac3c435b3ef57f867022.1667651354.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-11-05T12:29:09","name":"[03/12] RISC-V: Tidying related to '\''Zfinx'\'' disassembler test","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a9229a2798480f00bf12ac3c435b3ef57f867022.1667651354.git.research_trasio@irq.a4lg.com/mbox/"},{"id":15962,"url":"https://patchwork.plctlab.org/api/1.2/patches/15962/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6a020edd0e114a003edbaafe1088a040e9fa07e7.1667651354.git.research_trasio@irq.a4lg.com/","msgid":"<6a020edd0e114a003edbaafe1088a040e9fa07e7.1667651354.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-05T12:29:10","name":"[04/12] RISC-V: GAS: Add basic shared test utilities","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6a020edd0e114a003edbaafe1088a040e9fa07e7.1667651354.git.research_trasio@irq.a4lg.com/mbox/"},{"id":15966,"url":"https://patchwork.plctlab.org/api/1.2/patches/15966/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6fc2851a4161edc429089bd2bbd9c2bb4c0c118f.1667651354.git.research_trasio@irq.a4lg.com/","msgid":"<6fc2851a4161edc429089bd2bbd9c2bb4c0c118f.1667651354.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-05T12:29:11","name":"[05/12] RISC-V: Redefine \"nop\" test","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6fc2851a4161edc429089bd2bbd9c2bb4c0c118f.1667651354.git.research_trasio@irq.a4lg.com/mbox/"},{"id":15963,"url":"https://patchwork.plctlab.org/api/1.2/patches/15963/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7311ed3d2429000e18877d7af594890da170a7a3.1667651354.git.research_trasio@irq.a4lg.com/","msgid":"<7311ed3d2429000e18877d7af594890da170a7a3.1667651354.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-05T12:29:12","name":"[06/12] RISC-V: Reorganize/enhance {sign, zero}-extension instructions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7311ed3d2429000e18877d7af594890da170a7a3.1667651354.git.research_trasio@irq.a4lg.com/mbox/"},{"id":15968,"url":"https://patchwork.plctlab.org/api/1.2/patches/15968/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ac99c9696c156207f06c18f2d6bf423c96c5876b.1667651354.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-11-05T12:29:13","name":"[07/12] RISC-V: Combine complex extension error handling tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ac99c9696c156207f06c18f2d6bf423c96c5876b.1667651354.git.research_trasio@irq.a4lg.com/mbox/"},{"id":15970,"url":"https://patchwork.plctlab.org/api/1.2/patches/15970/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9378b9505e3e230e0a690c56e67d253e2a0f5864.1667651354.git.research_trasio@irq.a4lg.com/","msgid":"<9378b9505e3e230e0a690c56e67d253e2a0f5864.1667651354.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-05T12:29:14","name":"[08/12] RISC-V: Refine/enhance '\''M'\''/'\''Zmmul'\'' extension tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9378b9505e3e230e0a690c56e67d253e2a0f5864.1667651354.git.research_trasio@irq.a4lg.com/mbox/"},{"id":15964,"url":"https://patchwork.plctlab.org/api/1.2/patches/15964/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/82832a67f240d5857fd502d4b74fd7d841ee2d6e.1667651354.git.research_trasio@irq.a4lg.com/","msgid":"<82832a67f240d5857fd502d4b74fd7d841ee2d6e.1667651354.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-05T12:29:15","name":"[09/12] RISC-V: Combine/enhance '\''Zicbo[mz]'\'' extension tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/82832a67f240d5857fd502d4b74fd7d841ee2d6e.1667651354.git.research_trasio@irq.a4lg.com/mbox/"},{"id":15965,"url":"https://patchwork.plctlab.org/api/1.2/patches/15965/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9c47e59868a64b13e5a7bb487e3619d4f1497d78.1667651354.git.research_trasio@irq.a4lg.com/","msgid":"<9c47e59868a64b13e5a7bb487e3619d4f1497d78.1667651354.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-05T12:29:16","name":"[10/12] RISC-V: Enhance '\''Zicbop'\'' testcases","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9c47e59868a64b13e5a7bb487e3619d4f1497d78.1667651354.git.research_trasio@irq.a4lg.com/mbox/"},{"id":15967,"url":"https://patchwork.plctlab.org/api/1.2/patches/15967/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2d9befc5bc5eed80b6bd7da6d092a61b1162ecac.1667651354.git.research_trasio@irq.a4lg.com/","msgid":"<2d9befc5bc5eed80b6bd7da6d092a61b1162ecac.1667651354.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-05T12:29:17","name":"[11/12] RISC-V: Reorganize/enhance '\''Zb*'\'' extension tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2d9befc5bc5eed80b6bd7da6d092a61b1162ecac.1667651354.git.research_trasio@irq.a4lg.com/mbox/"},{"id":15969,"url":"https://patchwork.plctlab.org/api/1.2/patches/15969/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f1c5589ab606b74eeac98e3dafd4a7903450d3b2.1667651354.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-11-05T12:29:18","name":"[12/12] RISC-V: Combine/enhance '\''Zk*'\''/'\''Zbk*'\'' extension tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f1c5589ab606b74eeac98e3dafd4a7903450d3b2.1667651354.git.research_trasio@irq.a4lg.com/mbox/"},{"id":16066,"url":"https://patchwork.plctlab.org/api/1.2/patches/16066/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221106053640.1649752-1-indu.bhagat@oracle.com/","msgid":"<20221106053640.1649752-1-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-06T05:36:40","name":"[V3.1,03/15] gas: generate .sframe from CFI directives","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221106053640.1649752-1-indu.bhagat@oracle.com/mbox/"},{"id":16379,"url":"https://patchwork.plctlab.org/api/1.2/patches/16379/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221107112805.3332619-1-och95@yandex.ru/","msgid":"<20221107112805.3332619-1-och95@yandex.ru>","list_archive_url":null,"date":"2022-11-07T11:28:05","name":"gold/aarch64: Fix adrp distance check","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221107112805.3332619-1-och95@yandex.ru/mbox/"},{"id":16400,"url":"https://patchwork.plctlab.org/api/1.2/patches/16400/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221107124620.1271470-1-christoph.muellner@vrull.eu/","msgid":"<20221107124620.1271470-1-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2022-11-07T12:46:20","name":"RISC-V: xtheadfmemidx: Use fp register in mnemonics","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221107124620.1271470-1-christoph.muellner@vrull.eu/mbox/"},{"id":16594,"url":"https://patchwork.plctlab.org/api/1.2/patches/16594/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/CACVBkZ+kM2xcpwk5zHQ4bqDV7dbPjZ6cMU9tR-h62+tDTgi3Tw@mail.gmail.com/","msgid":"","list_archive_url":null,"date":"2022-11-07T17:53:35","name":"GAS fix section alignment for aarch64-pe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/CACVBkZ+kM2xcpwk5zHQ4bqDV7dbPjZ6cMU9tR-h62+tDTgi3Tw@mail.gmail.com/mbox/"},{"id":16744,"url":"https://patchwork.plctlab.org/api/1.2/patches/16744/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221107222809.924195-1-indu.bhagat@oracle.com/","msgid":"<20221107222809.924195-1-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-07T22:28:09","name":"[V3.3,11/15] libctf: add libsframe to LDFLAGS and LIBS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221107222809.924195-1-indu.bhagat@oracle.com/mbox/"},{"id":16797,"url":"https://patchwork.plctlab.org/api/1.2/patches/16797/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221108012556.66467-1-haochen.jiang@intel.com/","msgid":"<20221108012556.66467-1-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-11-08T01:25:56","name":"x86: Correct wrong comments in vex_w_table","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221108012556.66467-1-haochen.jiang@intel.com/mbox/"},{"id":16884,"url":"https://patchwork.plctlab.org/api/1.2/patches/16884/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221108054530.796968-1-markus.t.metzger@intel.com/","msgid":"<20221108054530.796968-1-markus.t.metzger@intel.com>","list_archive_url":null,"date":"2022-11-08T05:45:29","name":"[1/2] gprofng: make cpu identification available to others","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221108054530.796968-1-markus.t.metzger@intel.com/mbox/"},{"id":16885,"url":"https://patchwork.plctlab.org/api/1.2/patches/16885/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221108054530.796968-2-markus.t.metzger@intel.com/","msgid":"<20221108054530.796968-2-markus.t.metzger@intel.com>","list_archive_url":null,"date":"2022-11-08T05:45:30","name":"[2/2] gdb, btrace: use cpuident.h to implement btrace_this_cpu","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221108054530.796968-2-markus.t.metzger@intel.com/mbox/"},{"id":16995,"url":"https://patchwork.plctlab.org/api/1.2/patches/16995/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ea0daf08-4923-ebfa-dcfe-699c43d63822@suse.com/","msgid":"","list_archive_url":null,"date":"2022-11-08T11:29:40","name":"x86/Intel: don'\''t accept malformed EXTRQ / INSERTQ","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ea0daf08-4923-ebfa-dcfe-699c43d63822@suse.com/mbox/"},{"id":17057,"url":"https://patchwork.plctlab.org/api/1.2/patches/17057/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221108141352.6613-1-jwilk@jwilk.net/","msgid":"<20221108141352.6613-1-jwilk@jwilk.net>","list_archive_url":null,"date":"2022-11-08T14:13:52","name":"Fix typos in the list of objdump options","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221108141352.6613-1-jwilk@jwilk.net/mbox/"},{"id":17117,"url":"https://patchwork.plctlab.org/api/1.2/patches/17117/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1667924955-9218-1-git-send-email-apinski@marvell.com/","msgid":"<1667924955-9218-1-git-send-email-apinski@marvell.com>","list_archive_url":null,"date":"2022-11-08T16:29:15","name":"Use toplevel configure for GMP and MPFR for gdb","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1667924955-9218-1-git-send-email-apinski@marvell.com/mbox/"},{"id":17160,"url":"https://patchwork.plctlab.org/api/1.2/patches/17160/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/27382086-397f-060f-6cf6-c1d36ff6b812@linux.ibm.com/","msgid":"<27382086-397f-060f-6cf6-c1d36ff6b812@linux.ibm.com>","list_archive_url":null,"date":"2022-11-08T18:23:32","name":"[COMMITTED] PowerPC: Add XSP operand define","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/27382086-397f-060f-6cf6-c1d36ff6b812@linux.ibm.com/mbox/"},{"id":17202,"url":"https://patchwork.plctlab.org/api/1.2/patches/17202/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221108192248.1622627-1-indu.bhagat@oracle.com/","msgid":"<20221108192248.1622627-1-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-08T19:22:48","name":"libctf: use libtool for link test in configure","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221108192248.1622627-1-indu.bhagat@oracle.com/mbox/"},{"id":17262,"url":"https://patchwork.plctlab.org/api/1.2/patches/17262/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221108225030.371817-1-hjl.tools@gmail.com/","msgid":"<20221108225030.371817-1-hjl.tools@gmail.com>","list_archive_url":null,"date":"2022-11-08T22:50:30","name":"ld: Always output local symbol for relocatable link","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221108225030.371817-1-hjl.tools@gmail.com/mbox/"},{"id":17399,"url":"https://patchwork.plctlab.org/api/1.2/patches/17399/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-2-indu.bhagat@oracle.com/","msgid":"<20221109084244.261296-2-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-09T08:42:34","name":"[V4,01/11] sframe.h: Add SFrame format definition","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-2-indu.bhagat@oracle.com/mbox/"},{"id":17398,"url":"https://patchwork.plctlab.org/api/1.2/patches/17398/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-3-indu.bhagat@oracle.com/","msgid":"<20221109084244.261296-3-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-09T08:42:35","name":"[V4,02/11] gas: add new command line option --gsframe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-3-indu.bhagat@oracle.com/mbox/"},{"id":17400,"url":"https://patchwork.plctlab.org/api/1.2/patches/17400/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-4-indu.bhagat@oracle.com/","msgid":"<20221109084244.261296-4-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-09T08:42:36","name":"[V4,03/11] gas: generate .sframe from CFI directives","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-4-indu.bhagat@oracle.com/mbox/"},{"id":17403,"url":"https://patchwork.plctlab.org/api/1.2/patches/17403/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-5-indu.bhagat@oracle.com/","msgid":"<20221109084244.261296-5-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-09T08:42:37","name":"[V4,04/11] gas: testsuite: add new tests for SFrame unwind info","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-5-indu.bhagat@oracle.com/mbox/"},{"id":17407,"url":"https://patchwork.plctlab.org/api/1.2/patches/17407/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-6-indu.bhagat@oracle.com/","msgid":"<20221109084244.261296-6-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-09T08:42:38","name":"[V4,05/11] libsframe: add the SFrame library","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-6-indu.bhagat@oracle.com/mbox/"},{"id":17406,"url":"https://patchwork.plctlab.org/api/1.2/patches/17406/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-7-indu.bhagat@oracle.com/","msgid":"<20221109084244.261296-7-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-09T08:42:39","name":"[V4,06/11] bfd: linker: merge .sframe sections","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-7-indu.bhagat@oracle.com/mbox/"},{"id":17402,"url":"https://patchwork.plctlab.org/api/1.2/patches/17402/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-8-indu.bhagat@oracle.com/","msgid":"<20221109084244.261296-8-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-09T08:42:40","name":"[V4,07/11] readelf/objdump: support for SFrame section","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-8-indu.bhagat@oracle.com/mbox/"},{"id":17401,"url":"https://patchwork.plctlab.org/api/1.2/patches/17401/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-9-indu.bhagat@oracle.com/","msgid":"<20221109084244.261296-9-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-09T08:42:41","name":"[V4,08/11] src-release.sh: Add libsframe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-9-indu.bhagat@oracle.com/mbox/"},{"id":17404,"url":"https://patchwork.plctlab.org/api/1.2/patches/17404/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-10-indu.bhagat@oracle.com/","msgid":"<20221109084244.261296-10-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-09T08:42:42","name":"[V4,09/11] binutils/NEWS: add text for SFrame support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-10-indu.bhagat@oracle.com/mbox/"},{"id":17405,"url":"https://patchwork.plctlab.org/api/1.2/patches/17405/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-11-indu.bhagat@oracle.com/","msgid":"<20221109084244.261296-11-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-09T08:42:43","name":"[V4,10/11] gas/NEWS: add text about new command line option and SFrame support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-11-indu.bhagat@oracle.com/mbox/"},{"id":17418,"url":"https://patchwork.plctlab.org/api/1.2/patches/17418/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-12-indu.bhagat@oracle.com/","msgid":"<20221109084244.261296-12-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-09T08:42:44","name":"[V4,11/11] doc: add SFrame spec file","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-12-indu.bhagat@oracle.com/mbox/"},{"id":17662,"url":"https://patchwork.plctlab.org/api/1.2/patches/17662/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109162611.760465-1-chigot@adacore.com/","msgid":"<20221109162611.760465-1-chigot@adacore.com>","list_archive_url":null,"date":"2022-11-09T16:26:11","name":"ld/testsuite: skip ld-size when -shared is not supported","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109162611.760465-1-chigot@adacore.com/mbox/"},{"id":17804,"url":"https://patchwork.plctlab.org/api/1.2/patches/17804/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109202129.475283-1-hjl.tools@gmail.com/","msgid":"<20221109202129.475283-1-hjl.tools@gmail.com>","list_archive_url":null,"date":"2022-11-09T20:21:29","name":"[v2] i386: Check invalid (%dx) usage","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109202129.475283-1-hjl.tools@gmail.com/mbox/"},{"id":18043,"url":"https://patchwork.plctlab.org/api/1.2/patches/18043/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y2zOaxv1jkhwTIAi@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-11-10T10:11:55","name":"Sanity check reloc count in get_reloc_upper_bound","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y2zOaxv1jkhwTIAi@squeak.grove.modra.org/mbox/"},{"id":18044,"url":"https://patchwork.plctlab.org/api/1.2/patches/18044/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y2zOkpGuKAn+V2Tk@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-11-10T10:12:34","name":"mach-o reloc size overflow","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y2zOkpGuKAn+V2Tk@squeak.grove.modra.org/mbox/"},{"id":18045,"url":"https://patchwork.plctlab.org/api/1.2/patches/18045/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fddbca08-756a-4d78-b117-3e82dc40df8d@AZ-NEU-EX04.Arm.com/","msgid":"","list_archive_url":null,"date":"2022-11-10T10:17:38","name":"[BINTUILS] arm: Add support for Cortex-X1C CPU.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fddbca08-756a-4d78-b117-3e82dc40df8d@AZ-NEU-EX04.Arm.com/mbox/"},{"id":18051,"url":"https://patchwork.plctlab.org/api/1.2/patches/18051/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1518b510-2124-cbcb-9dcb-059dcfdc6cd4@suse.com/","msgid":"<1518b510-2124-cbcb-9dcb-059dcfdc6cd4@suse.com>","list_archive_url":null,"date":"2022-11-10T10:24:31","name":"x86: drop stray IsString from PadLock insns","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1518b510-2124-cbcb-9dcb-059dcfdc6cd4@suse.com/mbox/"},{"id":18088,"url":"https://patchwork.plctlab.org/api/1.2/patches/18088/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/25e8786d-289e-0521-baa2-2f2b85124dfe@suse.com/","msgid":"<25e8786d-289e-0521-baa2-2f2b85124dfe@suse.com>","list_archive_url":null,"date":"2022-11-10T12:12:46","name":"[v2] x86: drop stray IsString from PadLock insns","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/25e8786d-289e-0521-baa2-2f2b85124dfe@suse.com/mbox/"},{"id":18130,"url":"https://patchwork.plctlab.org/api/1.2/patches/18130/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9bb8ebe7-9e49-d60b-d586-e4d98242acda@suse.com/","msgid":"<9bb8ebe7-9e49-d60b-d586-e4d98242acda@suse.com>","list_archive_url":null,"date":"2022-11-10T13:36:16","name":"x86: drop duplicate sse4a entry from cpu_arch[]","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9bb8ebe7-9e49-d60b-d586-e4d98242acda@suse.com/mbox/"},{"id":18135,"url":"https://patchwork.plctlab.org/api/1.2/patches/18135/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/21665493-a9f9-3429-c9ae-ea69bc7751e2@suse.com/","msgid":"<21665493-a9f9-3429-c9ae-ea69bc7751e2@suse.com>","list_archive_url":null,"date":"2022-11-10T13:45:30","name":"x86: fold special-operand insn attributes into a single enum","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/21665493-a9f9-3429-c9ae-ea69bc7751e2@suse.com/mbox/"},{"id":18284,"url":"https://patchwork.plctlab.org/api/1.2/patches/18284/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1668107159-16961-1-git-send-email-apinski@marvell.com/","msgid":"<1668107159-16961-1-git-send-email-apinski@marvell.com>","list_archive_url":null,"date":"2022-11-10T19:05:59","name":"[PATCHv2] Use toplevel configure for GMP and MPFR for gdb","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1668107159-16961-1-git-send-email-apinski@marvell.com/mbox/"},{"id":18337,"url":"https://patchwork.plctlab.org/api/1.2/patches/18337/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221110224002.3798725-1-vladimir.mezentsev@oracle.com/","msgid":"<20221110224002.3798725-1-vladimir.mezentsev@oracle.com>","list_archive_url":null,"date":"2022-11-10T22:40:02","name":"gprofng: fix typo in configure.ac","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221110224002.3798725-1-vladimir.mezentsev@oracle.com/mbox/"},{"id":18424,"url":"https://patchwork.plctlab.org/api/1.2/patches/18424/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221111033040.23115-1-mark@harmstone.com/","msgid":"<20221111033040.23115-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-11-11T03:30:40","name":"ld: Add section contributions substream to PDB files","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221111033040.23115-1-mark@harmstone.com/mbox/"},{"id":18513,"url":"https://patchwork.plctlab.org/api/1.2/patches/18513/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/40e89395-1438-6cbe-aa37-1a04a724c8c7@suse.com/","msgid":"<40e89395-1438-6cbe-aa37-1a04a724c8c7@suse.com>","list_archive_url":null,"date":"2022-11-11T07:32:17","name":"gas: accept custom \".linefile .\"","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/40e89395-1438-6cbe-aa37-1a04a724c8c7@suse.com/mbox/"},{"id":18517,"url":"https://patchwork.plctlab.org/api/1.2/patches/18517/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y23642YK4HTWnn3X@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-11-11T07:33:55","name":"Sanity check SHT_MIPS_OPTIONS size","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y23642YK4HTWnn3X@squeak.grove.modra.org/mbox/"},{"id":18519,"url":"https://patchwork.plctlab.org/api/1.2/patches/18519/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y237HYVYLWv1R4b/@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-11-11T07:34:53","name":"PR28834, PR26946 sanity checking section size","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y237HYVYLWv1R4b/@squeak.grove.modra.org/mbox/"},{"id":18670,"url":"https://patchwork.plctlab.org/api/1.2/patches/18670/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c5ab35f0-595a-439c-b120-f93bd109ab96@AZ-NEU-EX04.Arm.com/","msgid":"","list_archive_url":null,"date":"2022-11-11T10:51:43","name":"[Binutils,gas] arm: Add support for new unwinder directive \".pacspval\".","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c5ab35f0-595a-439c-b120-f93bd109ab96@AZ-NEU-EX04.Arm.com/mbox/"},{"id":18672,"url":"https://patchwork.plctlab.org/api/1.2/patches/18672/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/33eb9aff-d813-44c5-8315-aeb3e339b3f2@AZ-NEU-EX04.Arm.com/","msgid":"<33eb9aff-d813-44c5-8315-aeb3e339b3f2@AZ-NEU-EX04.Arm.com>","list_archive_url":null,"date":"2022-11-11T10:53:55","name":"[Binutils,readelf] arm: Support for new pacbti unwind opcode 0xb5.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/33eb9aff-d813-44c5-8315-aeb3e339b3f2@AZ-NEU-EX04.Arm.com/mbox/"},{"id":19116,"url":"https://patchwork.plctlab.org/api/1.2/patches/19116/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y29EZ/ykU1Qe6AAw@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-11-12T06:59:51","name":"PowerPC64 paddi -Mraw","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y29EZ/ykU1Qe6AAw@squeak.grove.modra.org/mbox/"},{"id":19138,"url":"https://patchwork.plctlab.org/api/1.2/patches/19138/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221112091217.558020-1-dimitar@dinux.eu/","msgid":"<20221112091217.558020-1-dimitar@dinux.eu>","list_archive_url":null,"date":"2022-11-12T09:12:17","name":"pru: bfd: Correct default to no execstack","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221112091217.558020-1-dimitar@dinux.eu/mbox/"},{"id":19173,"url":"https://patchwork.plctlab.org/api/1.2/patches/19173/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221112124441.5084-1-patrick@monnerat.net/","msgid":"<20221112124441.5084-1-patrick@monnerat.net>","list_archive_url":null,"date":"2022-11-12T12:44:41","name":"binutils/objcopy: keep relocation while renaming a section with explicit flags","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221112124441.5084-1-patrick@monnerat.net/mbox/"},{"id":19377,"url":"https://patchwork.plctlab.org/api/1.2/patches/19377/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221113155921.1445808-1-christoph.muellner@vrull.eu/","msgid":"<20221113155921.1445808-1-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2022-11-13T15:59:20","name":"[1/2] RISC-V: Add T-Head Fmv vendor extension","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221113155921.1445808-1-christoph.muellner@vrull.eu/mbox/"},{"id":19378,"url":"https://patchwork.plctlab.org/api/1.2/patches/19378/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221113155921.1445808-2-christoph.muellner@vrull.eu/","msgid":"<20221113155921.1445808-2-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2022-11-13T15:59:21","name":"[2/2] RISC-V: Add T-Head Int vendor extension","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221113155921.1445808-2-christoph.muellner@vrull.eu/mbox/"},{"id":19850,"url":"https://patchwork.plctlab.org/api/1.2/patches/19850/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221114150348.112815-1-bwerl.dev@gmail.com/","msgid":"<20221114150348.112815-1-bwerl.dev@gmail.com>","list_archive_url":null,"date":"2022-11-14T15:03:48","name":"readelf: use fseeko for elf files >= 2 GiB on x86_64-mingw32","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221114150348.112815-1-bwerl.dev@gmail.com/mbox/"},{"id":19866,"url":"https://patchwork.plctlab.org/api/1.2/patches/19866/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3dd1c6f9-a773-c05f-44d7-12b7947072d2@suse.com/","msgid":"<3dd1c6f9-a773-c05f-44d7-12b7947072d2@suse.com>","list_archive_url":null,"date":"2022-11-14T16:12:26","name":"x86: infer No_*Suf from other insn attributes","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3dd1c6f9-a773-c05f-44d7-12b7947072d2@suse.com/mbox/"},{"id":19934,"url":"https://patchwork.plctlab.org/api/1.2/patches/19934/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f659dfbb-b84b-af86-bd8c-d177900af779@linaro.org/","msgid":"","list_archive_url":null,"date":"2022-11-14T17:24:23","name":"[V2] GAS fix alignment for aarch64-pe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f659dfbb-b84b-af86-bd8c-d177900af779@linaro.org/mbox/"},{"id":20111,"url":"https://patchwork.plctlab.org/api/1.2/patches/20111/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221115010409.24214-1-mark@harmstone.com/","msgid":"<20221115010409.24214-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-11-15T01:04:09","name":"gas: Add --gcodeview option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221115010409.24214-1-mark@harmstone.com/mbox/"},{"id":20174,"url":"https://patchwork.plctlab.org/api/1.2/patches/20174/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d305cd6178975195b025828561d59e505524ea45.1668486687.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-11-15T04:31:22","name":"[v3,1/8] RISC-V: Add a space at the end of pinfo","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d305cd6178975195b025828561d59e505524ea45.1668486687.git.research_trasio@irq.a4lg.com/mbox/"},{"id":20177,"url":"https://patchwork.plctlab.org/api/1.2/patches/20177/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2627dd5e18e59b6d976a8e6f1be39336e8a12cc3.1668486687.git.research_trasio@irq.a4lg.com/","msgid":"<2627dd5e18e59b6d976a8e6f1be39336e8a12cc3.1668486687.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-15T04:31:23","name":"[v3,2/8] RISC-V: Fix obvious misalignments ('\''Zbb'\''/'\''Zba'\'')","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2627dd5e18e59b6d976a8e6f1be39336e8a12cc3.1668486687.git.research_trasio@irq.a4lg.com/mbox/"},{"id":20173,"url":"https://patchwork.plctlab.org/api/1.2/patches/20173/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9d110279505cf502900a000a07e6e82b50f12adc.1668486687.git.research_trasio@irq.a4lg.com/","msgid":"<9d110279505cf502900a000a07e6e82b50f12adc.1668486687.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-15T04:31:24","name":"[v3,3/8] RISC-V: Remove spaces in opcode entries","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9d110279505cf502900a000a07e6e82b50f12adc.1668486687.git.research_trasio@irq.a4lg.com/mbox/"},{"id":20179,"url":"https://patchwork.plctlab.org/api/1.2/patches/20179/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8f77aa968ed9457ce1bce0a1f6449a287d0e6a18.1668486687.git.research_trasio@irq.a4lg.com/","msgid":"<8f77aa968ed9457ce1bce0a1f6449a287d0e6a18.1668486687.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-15T04:31:25","name":"[v3,4/8] RISC-V: Remove unused instruction macros","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8f77aa968ed9457ce1bce0a1f6449a287d0e6a18.1668486687.git.research_trasio@irq.a4lg.com/mbox/"},{"id":20176,"url":"https://patchwork.plctlab.org/api/1.2/patches/20176/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b43454773d597c1bc51741ef09aac960fecdfbd5.1668486687.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-11-15T04:31:26","name":"[v3,5/8] RISC-V: Complete tidying up with SCALL and SBREAK","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b43454773d597c1bc51741ef09aac960fecdfbd5.1668486687.git.research_trasio@irq.a4lg.com/mbox/"},{"id":20178,"url":"https://patchwork.plctlab.org/api/1.2/patches/20178/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/58cfec431ff2535aeb0c3fd9213933cf28864cb9.1668486687.git.research_trasio@irq.a4lg.com/","msgid":"<58cfec431ff2535aeb0c3fd9213933cf28864cb9.1668486687.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-15T04:31:27","name":"[v3,6/8] RISC-V: Tidying up with fmv.w.x and fmv.x.w","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/58cfec431ff2535aeb0c3fd9213933cf28864cb9.1668486687.git.research_trasio@irq.a4lg.com/mbox/"},{"id":20180,"url":"https://patchwork.plctlab.org/api/1.2/patches/20180/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/192f62be797f7c46a03acadb7d1bcdb83a7e9d6e.1668486687.git.research_trasio@irq.a4lg.com/","msgid":"<192f62be797f7c46a03acadb7d1bcdb83a7e9d6e.1668486687.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-15T04:31:28","name":"[v3,7/8] RISC-V: Make alias instructions aliases","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/192f62be797f7c46a03acadb7d1bcdb83a7e9d6e.1668486687.git.research_trasio@irq.a4lg.com/mbox/"},{"id":20175,"url":"https://patchwork.plctlab.org/api/1.2/patches/20175/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c89919c84067e1c2105b1857937df6405aec70fa.1668486687.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-11-15T04:31:29","name":"[v3,8/8] RISC-V: Use defined mask and match values","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c89919c84067e1c2105b1857937df6405aec70fa.1668486687.git.research_trasio@irq.a4lg.com/mbox/"},{"id":20185,"url":"https://patchwork.plctlab.org/api/1.2/patches/20185/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ebc1e98ae09f2c209ebaed2b81d5b418ce2c5128.1668487922.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-11-15T04:52:44","name":"[01/11] opcodes/riscv-dis.c: More tidying","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ebc1e98ae09f2c209ebaed2b81d5b418ce2c5128.1668487922.git.research_trasio@irq.a4lg.com/mbox/"},{"id":20188,"url":"https://patchwork.plctlab.org/api/1.2/patches/20188/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9795298f970f0b8a02796edc2c4249417614103b.1668487922.git.research_trasio@irq.a4lg.com/","msgid":"<9795298f970f0b8a02796edc2c4249417614103b.1668487922.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-15T04:52:45","name":"[02/11] RISC-V: Add test for '\''Zfinx'\'' register switching","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9795298f970f0b8a02796edc2c4249417614103b.1668487922.git.research_trasio@irq.a4lg.com/mbox/"},{"id":20186,"url":"https://patchwork.plctlab.org/api/1.2/patches/20186/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6c6c644515c6bc2751062543097eb14ee98e97c8.1668487922.git.research_trasio@irq.a4lg.com/","msgid":"<6c6c644515c6bc2751062543097eb14ee98e97c8.1668487922.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-15T04:52:46","name":"[03/11] RISC-V: Make mapping symbol checking consistent","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6c6c644515c6bc2751062543097eb14ee98e97c8.1668487922.git.research_trasio@irq.a4lg.com/mbox/"},{"id":20187,"url":"https://patchwork.plctlab.org/api/1.2/patches/20187/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b5b5ce7e34544c7934b775062413e0fe07dcd6e6.1668487922.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-11-15T04:52:47","name":"[04/11] RISC-V: Split riscv_get_map_state into two steps","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b5b5ce7e34544c7934b775062413e0fe07dcd6e6.1668487922.git.research_trasio@irq.a4lg.com/mbox/"},{"id":20192,"url":"https://patchwork.plctlab.org/api/1.2/patches/20192/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c143088cbaf7a19a992e008689420d95a90f3fab.1668487922.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-11-15T04:52:48","name":"[05/11] RISC-V: One time CSR hash table initialization","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c143088cbaf7a19a992e008689420d95a90f3fab.1668487922.git.research_trasio@irq.a4lg.com/mbox/"},{"id":20193,"url":"https://patchwork.plctlab.org/api/1.2/patches/20193/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9734125736efc8b63be17df87d38cf24bb14a156.1668487922.git.research_trasio@irq.a4lg.com/","msgid":"<9734125736efc8b63be17df87d38cf24bb14a156.1668487922.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-15T04:52:49","name":"[06/11] RISC-V: Use static xlen on ADDIW sequence","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9734125736efc8b63be17df87d38cf24bb14a156.1668487922.git.research_trasio@irq.a4lg.com/mbox/"},{"id":20191,"url":"https://patchwork.plctlab.org/api/1.2/patches/20191/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/34dbd0c82de0af284887a3bff649c8c53d67e752.1668487922.git.research_trasio@irq.a4lg.com/","msgid":"<34dbd0c82de0af284887a3bff649c8c53d67e752.1668487922.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-15T04:52:50","name":"[07/11] opcodes/riscv-dis.c: Add form feed for separation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/34dbd0c82de0af284887a3bff649c8c53d67e752.1668487922.git.research_trasio@irq.a4lg.com/mbox/"},{"id":20190,"url":"https://patchwork.plctlab.org/api/1.2/patches/20190/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1352fb8c63539727204df94651f371ed09bbce4c.1668487922.git.research_trasio@irq.a4lg.com/","msgid":"<1352fb8c63539727204df94651f371ed09bbce4c.1668487922.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-15T04:52:51","name":"[08/11] RISC-V: Split match/print steps on disassembler","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1352fb8c63539727204df94651f371ed09bbce4c.1668487922.git.research_trasio@irq.a4lg.com/mbox/"},{"id":20189,"url":"https://patchwork.plctlab.org/api/1.2/patches/20189/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/12cd8820841f695708875206b6461b6322c74428.1668487922.git.research_trasio@irq.a4lg.com/","msgid":"<12cd8820841f695708875206b6461b6322c74428.1668487922.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-15T04:52:52","name":"[09/11] RISC-V: Reorganize disassembler state initialization","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/12cd8820841f695708875206b6461b6322c74428.1668487922.git.research_trasio@irq.a4lg.com/mbox/"},{"id":20194,"url":"https://patchwork.plctlab.org/api/1.2/patches/20194/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6aade17e12ce2a928d044d9f148c874cf9922da8.1668487922.git.research_trasio@irq.a4lg.com/","msgid":"<6aade17e12ce2a928d044d9f148c874cf9922da8.1668487922.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-15T04:52:53","name":"[10/11] RISC-V: Reorganize arch-related initialization and management","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6aade17e12ce2a928d044d9f148c874cf9922da8.1668487922.git.research_trasio@irq.a4lg.com/mbox/"},{"id":20195,"url":"https://patchwork.plctlab.org/api/1.2/patches/20195/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a239fb0682bd24d4f1eb3014685eed78f9ea779a.1668487922.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-11-15T04:52:54","name":"[11/11] RISC-V: Move disassembler private data initialization","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a239fb0682bd24d4f1eb3014685eed78f9ea779a.1668487922.git.research_trasio@irq.a4lg.com/mbox/"},{"id":20236,"url":"https://patchwork.plctlab.org/api/1.2/patches/20236/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221115081455.2354987-2-zengxiao@eswincomputing.com/","msgid":"<20221115081455.2354987-2-zengxiao@eswincomputing.com>","list_archive_url":null,"date":"2022-11-15T08:14:55","name":"[v1,1/1] RISC-V: Make R_RISCV_SUB6 conforms to riscv abi standard","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221115081455.2354987-2-zengxiao@eswincomputing.com/mbox/"},{"id":20422,"url":"https://patchwork.plctlab.org/api/1.2/patches/20422/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221115145717.64948-1-bwerl.dev@gmail.com/","msgid":"<20221115145717.64948-1-bwerl.dev@gmail.com>","list_archive_url":null,"date":"2022-11-15T14:57:17","name":"readelf: use fseeko64 or fseeko if possible","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221115145717.64948-1-bwerl.dev@gmail.com/mbox/"},{"id":20600,"url":"https://patchwork.plctlab.org/api/1.2/patches/20600/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y3QKUwDn748CbDIs@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-11-15T21:53:23","name":"aarch64-pe can'\''t fill 16 bytes in section .text","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y3QKUwDn748CbDIs@squeak.grove.modra.org/mbox/"},{"id":20720,"url":"https://patchwork.plctlab.org/api/1.2/patches/20720/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221116053326.1337432-1-vladimir.mezentsev@oracle.com/","msgid":"<20221116053326.1337432-1-vladimir.mezentsev@oracle.com>","list_archive_url":null,"date":"2022-11-16T05:33:26","name":"PR29788, gprofng cannot display Java'\''s generated assembly code","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221116053326.1337432-1-vladimir.mezentsev@oracle.com/mbox/"},{"id":21321,"url":"https://patchwork.plctlab.org/api/1.2/patches/21321/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221116232039.1793148-1-hjl.tools@gmail.com/","msgid":"<20221116232039.1793148-1-hjl.tools@gmail.com>","list_archive_url":null,"date":"2022-11-16T23:20:39","name":"ld: Always call elf_backend_output_arch_local_syms","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221116232039.1793148-1-hjl.tools@gmail.com/mbox/"},{"id":21322,"url":"https://patchwork.plctlab.org/api/1.2/patches/21322/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221116232132.1009459-1-indu.bhagat@oracle.com/","msgid":"<20221116232132.1009459-1-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-16T23:21:32","name":"[gas,aarch64] : fix build breakage for aarch64-pe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221116232132.1009459-1-indu.bhagat@oracle.com/mbox/"},{"id":21449,"url":"https://patchwork.plctlab.org/api/1.2/patches/21449/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221117060234.1771025-1-indu.bhagat@oracle.com/","msgid":"<20221117060234.1771025-1-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-17T06:02:34","name":"[V2,gas,aarch64] : fix build breakage for aarch64-pe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221117060234.1771025-1-indu.bhagat@oracle.com/mbox/"},{"id":21662,"url":"https://patchwork.plctlab.org/api/1.2/patches/21662/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a050b8da-b978-d443-eee0-32b5a7836bb4@suse.com/","msgid":"","list_archive_url":null,"date":"2022-11-17T13:29:02","name":"[1/2] x86: instantiate i386_{op, reg}tab[] in gas instead of in libopcodes","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a050b8da-b978-d443-eee0-32b5a7836bb4@suse.com/mbox/"},{"id":21663,"url":"https://patchwork.plctlab.org/api/1.2/patches/21663/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d9b5137b-3bc0-8496-4533-03402ac00628@suse.com/","msgid":"","list_archive_url":null,"date":"2022-11-17T13:29:36","name":"[2/2] x86: break gas dependency on libopcodes","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d9b5137b-3bc0-8496-4533-03402ac00628@suse.com/mbox/"},{"id":21682,"url":"https://patchwork.plctlab.org/api/1.2/patches/21682/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221117143419.19571-1-bwerl.dev@gmail.com/","msgid":"<20221117143419.19571-1-bwerl.dev@gmail.com>","list_archive_url":null,"date":"2022-11-17T14:34:19","name":"readelf: use fseeko64 or fseeko if possible","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221117143419.19571-1-bwerl.dev@gmail.com/mbox/"},{"id":21850,"url":"https://patchwork.plctlab.org/api/1.2/patches/21850/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221117170546.1941945-1-hjl.tools@gmail.com/","msgid":"<20221117170546.1941945-1-hjl.tools@gmail.com>","list_archive_url":null,"date":"2022-11-17T17:05:46","name":"i386: Move i386_seg_prefixes to gas","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221117170546.1941945-1-hjl.tools@gmail.com/mbox/"},{"id":21858,"url":"https://patchwork.plctlab.org/api/1.2/patches/21858/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/CAPOVtOvi0D-u7MKAuO97-q241JZFojD8xppn3GdF2kH57iT+TA@mail.gmail.com/","msgid":"","list_archive_url":null,"date":"2022-11-17T17:44:00","name":"binutils: partially revert 17c6c3b99156fe82c1e637e1a5fd9f163ac788c8","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/CAPOVtOvi0D-u7MKAuO97-q241JZFojD8xppn3GdF2kH57iT+TA@mail.gmail.com/mbox/"},{"id":21992,"url":"https://patchwork.plctlab.org/api/1.2/patches/21992/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221118003212.3628771-1-christoph.muellner@vrull.eu/","msgid":"<20221118003212.3628771-1-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2022-11-18T00:32:12","name":"riscv: Add AIA extension support (Smaia, Ssaia)","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221118003212.3628771-1-christoph.muellner@vrull.eu/mbox/"},{"id":22004,"url":"https://patchwork.plctlab.org/api/1.2/patches/22004/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y3bZt50nhFXkf2WU@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-11-18T01:02:47","name":"go32 sanity check","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y3bZt50nhFXkf2WU@squeak.grove.modra.org/mbox/"},{"id":22005,"url":"https://patchwork.plctlab.org/api/1.2/patches/22005/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y3bZ0x42eeZFSqXt@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-11-18T01:03:15","name":"PR29799 heap buffer overflow in display_gdb_index dwarf.c:10548","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y3bZ0x42eeZFSqXt@squeak.grove.modra.org/mbox/"},{"id":22050,"url":"https://patchwork.plctlab.org/api/1.2/patches/22050/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4c45925619ab51261ca87d309883c9aa7cd05240.1668736896.git.research_trasio@irq.a4lg.com/","msgid":"<4c45925619ab51261ca87d309883c9aa7cd05240.1668736896.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-18T02:02:21","name":"RISC-V: Add INSN_DREF to memory read/write instructions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4c45925619ab51261ca87d309883c9aa7cd05240.1668736896.git.research_trasio@irq.a4lg.com/mbox/"},{"id":22053,"url":"https://patchwork.plctlab.org/api/1.2/patches/22053/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/13809b68ae60e912f3cb8e9bedd8eedf3899b547.1668737241.git.research_trasio@irq.a4lg.com/","msgid":"<13809b68ae60e912f3cb8e9bedd8eedf3899b547.1668737241.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-18T02:07:48","name":"[v4,1/8] RISC-V: Add a space at the end of pinfo","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/13809b68ae60e912f3cb8e9bedd8eedf3899b547.1668737241.git.research_trasio@irq.a4lg.com/mbox/"},{"id":22051,"url":"https://patchwork.plctlab.org/api/1.2/patches/22051/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9abf4696a17c5407a75d87b3c200fb9958ff227e.1668737241.git.research_trasio@irq.a4lg.com/","msgid":"<9abf4696a17c5407a75d87b3c200fb9958ff227e.1668737241.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-18T02:07:49","name":"[v4,2/8] RISC-V: Fix obvious misalignments ('\''Zbb'\''/'\''Zba'\'')","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9abf4696a17c5407a75d87b3c200fb9958ff227e.1668737241.git.research_trasio@irq.a4lg.com/mbox/"},{"id":22052,"url":"https://patchwork.plctlab.org/api/1.2/patches/22052/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/80185b54704af681ba81c6f84b6ce099cc3b5970.1668737241.git.research_trasio@irq.a4lg.com/","msgid":"<80185b54704af681ba81c6f84b6ce099cc3b5970.1668737241.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-18T02:07:50","name":"[v4,3/8] RISC-V: Remove spaces in opcode entries","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/80185b54704af681ba81c6f84b6ce099cc3b5970.1668737241.git.research_trasio@irq.a4lg.com/mbox/"},{"id":22055,"url":"https://patchwork.plctlab.org/api/1.2/patches/22055/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5d675a4132e2f6160d3294563e16f5093b5b1e20.1668737241.git.research_trasio@irq.a4lg.com/","msgid":"<5d675a4132e2f6160d3294563e16f5093b5b1e20.1668737241.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-18T02:07:51","name":"[v4,4/8] RISC-V: Remove unused instruction macros","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5d675a4132e2f6160d3294563e16f5093b5b1e20.1668737241.git.research_trasio@irq.a4lg.com/mbox/"},{"id":22056,"url":"https://patchwork.plctlab.org/api/1.2/patches/22056/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/27a4301cbae3d6788c878924f55aa9a6ae910669.1668737241.git.research_trasio@irq.a4lg.com/","msgid":"<27a4301cbae3d6788c878924f55aa9a6ae910669.1668737241.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-18T02:07:52","name":"[v4,5/8] RISC-V: Complete tidying up with SCALL and SBREAK","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/27a4301cbae3d6788c878924f55aa9a6ae910669.1668737241.git.research_trasio@irq.a4lg.com/mbox/"},{"id":22058,"url":"https://patchwork.plctlab.org/api/1.2/patches/22058/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7f0ea4bf1af541504b72791b5217253b2450071c.1668737241.git.research_trasio@irq.a4lg.com/","msgid":"<7f0ea4bf1af541504b72791b5217253b2450071c.1668737241.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-18T02:07:53","name":"[v4,6/8] RISC-V: Tidying up with fmv.w.x and fmv.x.w","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7f0ea4bf1af541504b72791b5217253b2450071c.1668737241.git.research_trasio@irq.a4lg.com/mbox/"},{"id":22057,"url":"https://patchwork.plctlab.org/api/1.2/patches/22057/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e5d45f2c8d1bb5b2d9adbfa117a3fc7d32afd6c9.1668737241.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-11-18T02:07:54","name":"[v4,7/8] RISC-V: Make alias instructions aliases","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e5d45f2c8d1bb5b2d9adbfa117a3fc7d32afd6c9.1668737241.git.research_trasio@irq.a4lg.com/mbox/"},{"id":22054,"url":"https://patchwork.plctlab.org/api/1.2/patches/22054/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3c1e28e61eb0275d0fd02a7d9ff956cc4f589104.1668737241.git.research_trasio@irq.a4lg.com/","msgid":"<3c1e28e61eb0275d0fd02a7d9ff956cc4f589104.1668737241.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-18T02:07:55","name":"[v4,8/8] RISC-V: Use defined mask and match values","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3c1e28e61eb0275d0fd02a7d9ff956cc4f589104.1668737241.git.research_trasio@irq.a4lg.com/mbox/"},{"id":22215,"url":"https://patchwork.plctlab.org/api/1.2/patches/22215/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/028280ab-56ad-2380-6bdd-3c944695ec5f@suse.com/","msgid":"<028280ab-56ad-2380-6bdd-3c944695ec5f@suse.com>","list_archive_url":null,"date":"2022-11-18T09:12:10","name":"[v2,1/4] x86: instantiate i386_{op, reg}tab[] in gas instead of in libopcodes","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/028280ab-56ad-2380-6bdd-3c944695ec5f@suse.com/mbox/"},{"id":22216,"url":"https://patchwork.plctlab.org/api/1.2/patches/22216/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b9a2ae11-6e9c-e9a8-88f6-17c686f0b844@suse.com/","msgid":"","list_archive_url":null,"date":"2022-11-18T09:13:01","name":"[v2,2/4] x86: remove i386-opc.c","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b9a2ae11-6e9c-e9a8-88f6-17c686f0b844@suse.com/mbox/"},{"id":22217,"url":"https://patchwork.plctlab.org/api/1.2/patches/22217/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fad783e7-e00a-c3c1-cb6d-89b70816a737@suse.com/","msgid":"","list_archive_url":null,"date":"2022-11-18T09:13:24","name":"[v2,3/4] x86: break gas dependency on libopcodes","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fad783e7-e00a-c3c1-cb6d-89b70816a737@suse.com/mbox/"},{"id":22218,"url":"https://patchwork.plctlab.org/api/1.2/patches/22218/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e3d67085-1385-d576-8656-30454f9e4474@suse.com/","msgid":"","list_archive_url":null,"date":"2022-11-18T09:14:05","name":"[v2,4/4] x86: drop sentinel from i386_optab[]","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e3d67085-1385-d576-8656-30454f9e4474@suse.com/mbox/"},{"id":23223,"url":"https://patchwork.plctlab.org/api/1.2/patches/23223/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2e469b6dd7d8b93ffd3cac333dd58d172a8f28d6.1668841829.git.research_trasio@irq.a4lg.com/","msgid":"<2e469b6dd7d8b93ffd3cac333dd58d172a8f28d6.1668841829.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-19T07:10:33","name":"[1/2] RISC-V: Make .insn tests stricter","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2e469b6dd7d8b93ffd3cac333dd58d172a8f28d6.1668841829.git.research_trasio@irq.a4lg.com/mbox/"},{"id":23224,"url":"https://patchwork.plctlab.org/api/1.2/patches/23224/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ed49fad6bc6aa4f59d619fd6b445582331594e08.1668841829.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-11-19T07:10:34","name":"[2/2] RISC-V: Better support for long instructions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ed49fad6bc6aa4f59d619fd6b445582331594e08.1668841829.git.research_trasio@irq.a4lg.com/mbox/"},{"id":23362,"url":"https://patchwork.plctlab.org/api/1.2/patches/23362/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7487608537fcd71f322e56d40bfb2cc605cee89a.1668906514.git.research_trasio@irq.a4lg.com/","msgid":"<7487608537fcd71f322e56d40bfb2cc605cee89a.1668906514.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-20T01:08:40","name":"[1/3] RISC-V: Use faster hash table on disassembling","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7487608537fcd71f322e56d40bfb2cc605cee89a.1668906514.git.research_trasio@irq.a4lg.com/mbox/"},{"id":23361,"url":"https://patchwork.plctlab.org/api/1.2/patches/23361/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e984efaf6c2d42891fa466338d999bf8b292dd7d.1668906514.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-11-20T01:08:41","name":"[2/3] RISC-V: Fallback on faster hash table","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e984efaf6c2d42891fa466338d999bf8b292dd7d.1668906514.git.research_trasio@irq.a4lg.com/mbox/"},{"id":23366,"url":"https://patchwork.plctlab.org/api/1.2/patches/23366/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/844db363911065a3b5f0c5e4601f89ee1d7360c5.1668906514.git.research_trasio@irq.a4lg.com/","msgid":"<844db363911065a3b5f0c5e4601f89ee1d7360c5.1668906514.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-20T01:08:42","name":"[3/3] RISC-V: Cache instruction support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/844db363911065a3b5f0c5e4601f89ee1d7360c5.1668906514.git.research_trasio@irq.a4lg.com/mbox/"},{"id":23363,"url":"https://patchwork.plctlab.org/api/1.2/patches/23363/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/88793c204c9270376959c6276fb1b63275bef3c8.1668906599.git.research_trasio@irq.a4lg.com/","msgid":"<88793c204c9270376959c6276fb1b63275bef3c8.1668906599.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-20T01:10:07","name":"[1/3] RISC-V: Easy optimization on riscv_search_mapping_symbol","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/88793c204c9270376959c6276fb1b63275bef3c8.1668906599.git.research_trasio@irq.a4lg.com/mbox/"},{"id":23365,"url":"https://patchwork.plctlab.org/api/1.2/patches/23365/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/55a36e28e1cb3983c637b3019d48717278574591.1668906599.git.research_trasio@irq.a4lg.com/","msgid":"<55a36e28e1cb3983c637b3019d48717278574591.1668906599.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-20T01:10:08","name":"[2/3] RISC-V: Per-section private data initialization","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/55a36e28e1cb3983c637b3019d48717278574591.1668906599.git.research_trasio@irq.a4lg.com/mbox/"},{"id":23364,"url":"https://patchwork.plctlab.org/api/1.2/patches/23364/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d41edfbaf150abb20fd78e8518ca5a9e7e5eb74f.1668906599.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-11-20T01:10:09","name":"[3/3] RISC-V: Optimized search on mapping symbols","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d41edfbaf150abb20fd78e8518ca5a9e7e5eb74f.1668906599.git.research_trasio@irq.a4lg.com/mbox/"},{"id":23372,"url":"https://patchwork.plctlab.org/api/1.2/patches/23372/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/94304c8d9174ae7e9cf52abc3af6ccf5e3e0ecd9.1668910970.git.research_trasio@irq.a4lg.com/","msgid":"<94304c8d9174ae7e9cf52abc3af6ccf5e3e0ecd9.1668910970.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-20T02:23:27","name":"[v3,1/3] RISC-V: Make \"priv-spec\" overridable","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/94304c8d9174ae7e9cf52abc3af6ccf5e3e0ecd9.1668910970.git.research_trasio@irq.a4lg.com/mbox/"},{"id":23371,"url":"https://patchwork.plctlab.org/api/1.2/patches/23371/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9d6008e38402c4e60ada6f3d3db14b92815177d8.1668910970.git.research_trasio@irq.a4lg.com/","msgid":"<9d6008e38402c4e60ada6f3d3db14b92815177d8.1668910970.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-20T02:23:28","name":"[v3,2/3] RISC-V: Add \"arch\" disassembler option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9d6008e38402c4e60ada6f3d3db14b92815177d8.1668910970.git.research_trasio@irq.a4lg.com/mbox/"},{"id":23370,"url":"https://patchwork.plctlab.org/api/1.2/patches/23370/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/70a4ac1ba8c12101de56c24d3a47939a2f5ee542.1668910970.git.research_trasio@irq.a4lg.com/","msgid":"<70a4ac1ba8c12101de56c24d3a47939a2f5ee542.1668910970.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-20T02:23:29","name":"[v3,3/3] gdb/testsuite: RISC-V disassembler option tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/70a4ac1ba8c12101de56c24d3a47939a2f5ee542.1668910970.git.research_trasio@irq.a4lg.com/mbox/"},{"id":23667,"url":"https://patchwork.plctlab.org/api/1.2/patches/23667/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221121110926.124434-1-aleksandar.rikalo@syrmia.com/","msgid":"<20221121110926.124434-1-aleksandar.rikalo@syrmia.com>","list_archive_url":null,"date":"2022-11-21T11:09:26","name":"[v3] Add support for nanoMIPS architecture","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221121110926.124434-1-aleksandar.rikalo@syrmia.com/mbox/"},{"id":23697,"url":"https://patchwork.plctlab.org/api/1.2/patches/23697/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221121120037.19325-1-zengxiao@eswincomputing.com/","msgid":"<20221121120037.19325-1-zengxiao@eswincomputing.com>","list_archive_url":null,"date":"2022-11-21T12:00:37","name":"[v2] RISC-V: Make R_RISCV_SUB6 conforms to riscv ABI standard","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221121120037.19325-1-zengxiao@eswincomputing.com/mbox/"},{"id":23957,"url":"https://patchwork.plctlab.org/api/1.2/patches/23957/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221121171544.3291-1-shahab@synopsys.com/","msgid":"<20221121171544.3291-1-shahab@synopsys.com>","list_archive_url":null,"date":"2022-11-21T17:15:44","name":"opcodes: Correct address for ARC'\''s \"isa_config\" aux reg","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221121171544.3291-1-shahab@synopsys.com/mbox/"},{"id":24026,"url":"https://patchwork.plctlab.org/api/1.2/patches/24026/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y3vyL3UATztRRM8v@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-11-21T21:48:31","name":"PR29807, SIGSEGV when linking fuzzed PE object","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y3vyL3UATztRRM8v@squeak.grove.modra.org/mbox/"},{"id":24269,"url":"https://patchwork.plctlab.org/api/1.2/patches/24269/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221122110927.2328582-1-christoph.muellner@vrull.eu/","msgid":"<20221122110927.2328582-1-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2022-11-22T11:09:27","name":"[v3] riscv: Add AIA extension support (Smaia, Ssaia)","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221122110927.2328582-1-christoph.muellner@vrull.eu/mbox/"},{"id":24318,"url":"https://patchwork.plctlab.org/api/1.2/patches/24318/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221122120339.23186-1-shahab@synopsys.com/","msgid":"<20221122120339.23186-1-shahab@synopsys.com>","list_archive_url":null,"date":"2022-11-22T12:03:39","name":"[PUSHED] opcodes: Correct address for ARC'\''s \"isa_config\" aux reg","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221122120339.23186-1-shahab@synopsys.com/mbox/"},{"id":24501,"url":"https://patchwork.plctlab.org/api/1.2/patches/24501/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221122181927.251937-1-hjl.tools@gmail.com/","msgid":"<20221122181927.251937-1-hjl.tools@gmail.com>","list_archive_url":null,"date":"2022-11-22T18:19:27","name":"x86: Remove libopcodes dependency","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221122181927.251937-1-hjl.tools@gmail.com/mbox/"},{"id":24599,"url":"https://patchwork.plctlab.org/api/1.2/patches/24599/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y31GJLbFpb5DCn2F@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-11-22T21:59:00","name":"Don'\''t use \"long\" in readelf for file offsets","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y31GJLbFpb5DCn2F@squeak.grove.modra.org/mbox/"},{"id":24600,"url":"https://patchwork.plctlab.org/api/1.2/patches/24600/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221122220236.429230-1-hjl.tools@gmail.com/","msgid":"<20221122220236.429230-1-hjl.tools@gmail.com>","list_archive_url":null,"date":"2022-11-22T22:02:36","name":"x86: Don'\''t define _TLS_MODULE_BASE_ for ld -r","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221122220236.429230-1-hjl.tools@gmail.com/mbox/"},{"id":24605,"url":"https://patchwork.plctlab.org/api/1.2/patches/24605/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221122221028.2924195-1-indu.bhagat@oracle.com/","msgid":"<20221122221028.2924195-1-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-22T22:10:28","name":"sframe/doc: remove usage of xrefautomaticsectiontitle","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221122221028.2924195-1-indu.bhagat@oracle.com/mbox/"},{"id":24787,"url":"https://patchwork.plctlab.org/api/1.2/patches/24787/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fdcd78c77ec384da0cb74a6d91c1e7f00bdde6cf.1669192210.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-11-23T08:30:48","name":"[v2,1/2] RISC-V: Make .insn tests stricter","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fdcd78c77ec384da0cb74a6d91c1e7f00bdde6cf.1669192210.git.research_trasio@irq.a4lg.com/mbox/"},{"id":24789,"url":"https://patchwork.plctlab.org/api/1.2/patches/24789/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/cdd1f831660ce24353b47dc4098992f136e45bcc.1669192210.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-11-23T08:30:49","name":"[v2,2/2] RISC-V: Better support for long instructions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/cdd1f831660ce24353b47dc4098992f136e45bcc.1669192210.git.research_trasio@irq.a4lg.com/mbox/"},{"id":24873,"url":"https://patchwork.plctlab.org/api/1.2/patches/24873/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/40d1240c-154b-ecea-c391-9fab12129b2b@suse.com/","msgid":"<40d1240c-154b-ecea-c391-9fab12129b2b@suse.com>","list_archive_url":null,"date":"2022-11-23T10:33:38","name":"[1/3] x86: correct handling of LAR and LSL","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/40d1240c-154b-ecea-c391-9fab12129b2b@suse.com/mbox/"},{"id":24876,"url":"https://patchwork.plctlab.org/api/1.2/patches/24876/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3dbee940-c57e-f89f-fdb1-730b275c0c17@suse.com/","msgid":"<3dbee940-c57e-f89f-fdb1-730b275c0c17@suse.com>","list_archive_url":null,"date":"2022-11-23T10:34:34","name":"[2/3] x86: add missing CheckRegSize","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3dbee940-c57e-f89f-fdb1-730b275c0c17@suse.com/mbox/"},{"id":24882,"url":"https://patchwork.plctlab.org/api/1.2/patches/24882/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0168ba4a-766c-7cfe-7917-53259f846da0@suse.com/","msgid":"<0168ba4a-766c-7cfe-7917-53259f846da0@suse.com>","list_archive_url":null,"date":"2022-11-23T10:35:16","name":"[3/3] x86: widen applicability and use of CheckRegSize","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0168ba4a-766c-7cfe-7917-53259f846da0@suse.com/mbox/"},{"id":24939,"url":"https://patchwork.plctlab.org/api/1.2/patches/24939/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y34R4z7auiQd9V9m@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-11-23T12:28:19","name":"asan: NULL deref in filter_symbols","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y34R4z7auiQd9V9m@squeak.grove.modra.org/mbox/"},{"id":24943,"url":"https://patchwork.plctlab.org/api/1.2/patches/24943/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y34SFSgfRguI0pMs@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-11-23T12:29:09","name":"PR22509 - Null pointer dereference on coff_slurp_reloc_table","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y34SFSgfRguI0pMs@squeak.grove.modra.org/mbox/"},{"id":25150,"url":"https://patchwork.plctlab.org/api/1.2/patches/25150/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221123194330.21185-1-mark@harmstone.com/","msgid":"<20221123194330.21185-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-11-23T19:43:30","name":"gas: Disable --gcodeview on PE targets with no O_secrel","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221123194330.21185-1-mark@harmstone.com/mbox/"},{"id":25255,"url":"https://patchwork.plctlab.org/api/1.2/patches/25255/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221124002827.1915219-1-indu.bhagat@oracle.com/","msgid":"<20221124002827.1915219-1-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-24T00:28:27","name":"[V2] sframe/doc: remove usage of xrefautomaticsectiontitle","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221124002827.1915219-1-indu.bhagat@oracle.com/mbox/"},{"id":25302,"url":"https://patchwork.plctlab.org/api/1.2/patches/25302/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221124034051.11711-1-mark@harmstone.com/","msgid":"<20221124034051.11711-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-11-24T03:40:51","name":"ld: Generate PDB string table","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221124034051.11711-1-mark@harmstone.com/mbox/"},{"id":25339,"url":"https://patchwork.plctlab.org/api/1.2/patches/25339/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y38dhqK5vRWbfFEO@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-11-24T07:30:14","name":"PR16995, m68k coldfire emac immediate to macsr incorrect disassembly","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y38dhqK5vRWbfFEO@squeak.grove.modra.org/mbox/"},{"id":25340,"url":"https://patchwork.plctlab.org/api/1.2/patches/25340/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y38duAgksZJEg8Ca@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-11-24T07:31:04","name":"Constify nm format array","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y38duAgksZJEg8Ca@squeak.grove.modra.org/mbox/"},{"id":25341,"url":"https://patchwork.plctlab.org/api/1.2/patches/25341/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y38eF5ySbTaGA/Gm@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-11-24T07:32:39","name":"Tidy objdump printing of section size","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y38eF5ySbTaGA/Gm@squeak.grove.modra.org/mbox/"},{"id":25382,"url":"https://patchwork.plctlab.org/api/1.2/patches/25382/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ebd260da-8bc5-7672-f529-a6bb1d9e9c7f@suse.com/","msgid":"","list_archive_url":null,"date":"2022-11-24T08:57:24","name":"[1/3] x86: extend FPU test coverage for AT&T / Intel mnemonic differences","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ebd260da-8bc5-7672-f529-a6bb1d9e9c7f@suse.com/mbox/"},{"id":25384,"url":"https://patchwork.plctlab.org/api/1.2/patches/25384/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0ef86245-7f0d-ef4e-957a-4086eb54ef43@suse.com/","msgid":"<0ef86245-7f0d-ef4e-957a-4086eb54ef43@suse.com>","list_archive_url":null,"date":"2022-11-24T08:57:56","name":"[2/3] x86: drop FloatR","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0ef86245-7f0d-ef4e-957a-4086eb54ef43@suse.com/mbox/"},{"id":25385,"url":"https://patchwork.plctlab.org/api/1.2/patches/25385/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5dd8b2df-62f2-a551-4b35-f3df66d57e04@suse.com/","msgid":"<5dd8b2df-62f2-a551-4b35-f3df66d57e04@suse.com>","list_archive_url":null,"date":"2022-11-24T08:58:36","name":"[3/3] x86: clean up after removal of support for gcc <= 2.8.1","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5dd8b2df-62f2-a551-4b35-f3df66d57e04@suse.com/mbox/"},{"id":25492,"url":"https://patchwork.plctlab.org/api/1.2/patches/25492/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9790982d-5a3d-f711-b588-184edd41a0dd@suse.cz/","msgid":"<9790982d-5a3d-f711-b588-184edd41a0dd@suse.cz>","list_archive_url":null,"date":"2022-11-24T12:18:33","name":"[PUSHED] readelf: Do not require EI_OSABI for IFUNC.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9790982d-5a3d-f711-b588-184edd41a0dd@suse.cz/mbox/"},{"id":25494,"url":"https://patchwork.plctlab.org/api/1.2/patches/25494/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/874juopmb0.fsf@redhat.com/","msgid":"<874juopmb0.fsf@redhat.com>","list_archive_url":null,"date":"2022-11-24T12:30:11","name":"Commit: Fix compile time warnings in conftest.c files","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/874juopmb0.fsf@redhat.com/mbox/"},{"id":25627,"url":"https://patchwork.plctlab.org/api/1.2/patches/25627/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221124154531.903548-1-aleksandar.rikalo@syrmia.com/","msgid":"<20221124154531.903548-1-aleksandar.rikalo@syrmia.com>","list_archive_url":null,"date":"2022-11-24T15:45:31","name":"[v4] Add support for nanoMIPS architecture","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221124154531.903548-1-aleksandar.rikalo@syrmia.com/mbox/"},{"id":25784,"url":"https://patchwork.plctlab.org/api/1.2/patches/25784/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/66ca80358f78d66d66bbf390fc0be8bec8183e93.1669342633.git.research_trasio@irq.a4lg.com/","msgid":"<66ca80358f78d66d66bbf390fc0be8bec8183e93.1669342633.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-25T02:17:23","name":"[v3,1/2] RISC-V: Better support for long instructions (disassembler)","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/66ca80358f78d66d66bbf390fc0be8bec8183e93.1669342633.git.research_trasio@irq.a4lg.com/mbox/"},{"id":25785,"url":"https://patchwork.plctlab.org/api/1.2/patches/25785/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/47d1751320314f02bede4f6096c09b7f6585c94d.1669342633.git.research_trasio@irq.a4lg.com/","msgid":"<47d1751320314f02bede4f6096c09b7f6585c94d.1669342633.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-25T02:17:24","name":"[v3,2/2] RISC-V: Better support for long instructions (assembler)","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/47d1751320314f02bede4f6096c09b7f6585c94d.1669342633.git.research_trasio@irq.a4lg.com/mbox/"},{"id":25790,"url":"https://patchwork.plctlab.org/api/1.2/patches/25790/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221125025334.26665-1-mark@harmstone.com/","msgid":"<20221125025334.26665-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-11-25T02:53:34","name":"[v2] ld: Generate PDB string table","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221125025334.26665-1-mark@harmstone.com/mbox/"},{"id":25791,"url":"https://patchwork.plctlab.org/api/1.2/patches/25791/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221125025433.26818-1-mark@harmstone.com/","msgid":"<20221125025433.26818-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-11-25T02:54:33","name":"ld: Write DEBUG_S_FILECHKSMS entries in PDBs","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221125025433.26818-1-mark@harmstone.com/mbox/"},{"id":25914,"url":"https://patchwork.plctlab.org/api/1.2/patches/25914/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/457fc649-adf7-a35d-2ae1-8a9f1a00ce0a@suse.com/","msgid":"<457fc649-adf7-a35d-2ae1-8a9f1a00ce0a@suse.com>","list_archive_url":null,"date":"2022-11-25T10:09:58","name":"Arm: .noinit and .persistent are not supported for Linux targets","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/457fc649-adf7-a35d-2ae1-8a9f1a00ce0a@suse.com/mbox/"},{"id":25948,"url":"https://patchwork.plctlab.org/api/1.2/patches/25948/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2c04525e48f5fc135b6dcb35ca6f1fec4e9b122b.1669376496.git.research_trasio@irq.a4lg.com/","msgid":"<2c04525e48f5fc135b6dcb35ca6f1fec4e9b122b.1669376496.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-25T11:41:40","name":"[v3,1/3] RISC-V: Better support for long instructions (disassembler)","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2c04525e48f5fc135b6dcb35ca6f1fec4e9b122b.1669376496.git.research_trasio@irq.a4lg.com/mbox/"},{"id":25950,"url":"https://patchwork.plctlab.org/api/1.2/patches/25950/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2c04525e48f5fc135b6dcb35ca6f1fec4e9b122b.1669376539.git.research_trasio@irq.a4lg.com/","msgid":"<2c04525e48f5fc135b6dcb35ca6f1fec4e9b122b.1669376539.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-25T11:42:20","name":"[v4,1/3] RISC-V: Better support for long instructions (disassembler)","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2c04525e48f5fc135b6dcb35ca6f1fec4e9b122b.1669376539.git.research_trasio@irq.a4lg.com/mbox/"},{"id":25951,"url":"https://patchwork.plctlab.org/api/1.2/patches/25951/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d8d2cda8e4b1a82f93fd9e9daa57f705c582d06f.1669376539.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-11-25T11:42:21","name":"[v4,2/3] RISC-V: Better support for long instructions (assembler)","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d8d2cda8e4b1a82f93fd9e9daa57f705c582d06f.1669376539.git.research_trasio@irq.a4lg.com/mbox/"},{"id":25949,"url":"https://patchwork.plctlab.org/api/1.2/patches/25949/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/523d1243d28a817c7ab371daed61335ab1dd31bc.1669376539.git.research_trasio@irq.a4lg.com/","msgid":"<523d1243d28a817c7ab371daed61335ab1dd31bc.1669376539.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-25T11:42:22","name":"[v4,3/3] RISC-V: Better support for long instructions (tests)","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/523d1243d28a817c7ab371daed61335ab1dd31bc.1669376539.git.research_trasio@irq.a4lg.com/mbox/"},{"id":26085,"url":"https://patchwork.plctlab.org/api/1.2/patches/26085/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.LSU.2.20.2211251556330.24878@wotan.suse.de/","msgid":"","list_archive_url":null,"date":"2022-11-25T16:00:05","name":"Fix msp430 section name scribbling and tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.LSU.2.20.2211251556330.24878@wotan.suse.de/mbox/"},{"id":26086,"url":"https://patchwork.plctlab.org/api/1.2/patches/26086/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.LSU.2.20.2211251600280.24878@wotan.suse.de/","msgid":"","list_archive_url":null,"date":"2022-11-25T16:01:58","name":"Special case more simple patterns","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.LSU.2.20.2211251600280.24878@wotan.suse.de/mbox/"},{"id":26087,"url":"https://patchwork.plctlab.org/api/1.2/patches/26087/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.LSU.2.20.2211251602070.24878@wotan.suse.de/","msgid":"","list_archive_url":null,"date":"2022-11-25T16:04:51","name":"Only use wild_sort_fast","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.LSU.2.20.2211251602070.24878@wotan.suse.de/mbox/"},{"id":26094,"url":"https://patchwork.plctlab.org/api/1.2/patches/26094/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.LSU.2.20.2211251644290.24878@wotan.suse.de/","msgid":"","list_archive_url":null,"date":"2022-11-25T16:44:54","name":"[1/8] section-select: Lazily resolve section matches","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.LSU.2.20.2211251644290.24878@wotan.suse.de/mbox/"},{"id":26095,"url":"https://patchwork.plctlab.org/api/1.2/patches/26095/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.LSU.2.20.2211251645000.24878@wotan.suse.de/","msgid":"","list_archive_url":null,"date":"2022-11-25T16:46:41","name":"[2/8] section-select: Deal with sections added late","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.LSU.2.20.2211251645000.24878@wotan.suse.de/mbox/"},{"id":26096,"url":"https://patchwork.plctlab.org/api/1.2/patches/26096/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.LSU.2.20.2211251646510.24878@wotan.suse.de/","msgid":"","list_archive_url":null,"date":"2022-11-25T16:47:17","name":"[3/8] section-select: Implement a prefix-tree","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.LSU.2.20.2211251646510.24878@wotan.suse.de/mbox/"},{"id":26097,"url":"https://patchwork.plctlab.org/api/1.2/patches/26097/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.LSU.2.20.2211251647220.24878@wotan.suse.de/","msgid":"","list_archive_url":null,"date":"2022-11-25T16:55:12","name":"[4/8] section-select: Completely rebuild matches","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.LSU.2.20.2211251647220.24878@wotan.suse.de/mbox/"},{"id":26098,"url":"https://patchwork.plctlab.org/api/1.2/patches/26098/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.LSU.2.20.2211251655221.24878@wotan.suse.de/","msgid":"","list_archive_url":null,"date":"2022-11-25T16:55:36","name":"[5/8] section-select: Remove unused code","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.LSU.2.20.2211251655221.24878@wotan.suse.de/mbox/"},{"id":26099,"url":"https://patchwork.plctlab.org/api/1.2/patches/26099/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.LSU.2.20.2211251655420.24878@wotan.suse.de/","msgid":"","list_archive_url":null,"date":"2022-11-25T16:55:57","name":"[6/8] section-select: Cleanup","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.LSU.2.20.2211251655420.24878@wotan.suse.de/mbox/"},{"id":26100,"url":"https://patchwork.plctlab.org/api/1.2/patches/26100/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.LSU.2.20.2211251656020.24878@wotan.suse.de/","msgid":"","list_archive_url":null,"date":"2022-11-25T16:57:38","name":"[7/8] section-select: Remove bfd_max_section_id again","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.LSU.2.20.2211251656020.24878@wotan.suse.de/mbox/"},{"id":26101,"url":"https://patchwork.plctlab.org/api/1.2/patches/26101/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.LSU.2.20.2211251657410.24878@wotan.suse.de/","msgid":"","list_archive_url":null,"date":"2022-11-25T16:58:03","name":"[8/8] section-select: Fix exclude-file-3","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.LSU.2.20.2211251657410.24878@wotan.suse.de/mbox/"},{"id":26180,"url":"https://patchwork.plctlab.org/api/1.2/patches/26180/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c55d94343b1e04c73baf4db9d8b22111528f1b40.1669432329.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-11-26T03:13:51","name":"RISC-V: Allow merging '\''H'\'' extension","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c55d94343b1e04c73baf4db9d8b22111528f1b40.1669432329.git.research_trasio@irq.a4lg.com/mbox/"},{"id":26307,"url":"https://patchwork.plctlab.org/api/1.2/patches/26307/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221127023840.32080-1-mark@harmstone.com/","msgid":"<20221127023840.32080-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-11-27T02:38:39","name":"ld: Fix segfault in populate_publics_stream","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221127023840.32080-1-mark@harmstone.com/mbox/"},{"id":26308,"url":"https://patchwork.plctlab.org/api/1.2/patches/26308/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221127023840.32080-2-mark@harmstone.com/","msgid":"<20221127023840.32080-2-mark@harmstone.com>","list_archive_url":null,"date":"2022-11-27T02:38:40","name":"ld: Write DEBUG_S_LINES entries in PDB file","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221127023840.32080-2-mark@harmstone.com/mbox/"},{"id":26350,"url":"https://patchwork.plctlab.org/api/1.2/patches/26350/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221127125325.263577-1-brobecker@adacore.com/","msgid":"<20221127125325.263577-1-brobecker@adacore.com>","list_archive_url":null,"date":"2022-11-27T12:53:25","name":"[RFA] src-release.sh: Fix gdb source tarball build failure due to libsframe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221127125325.263577-1-brobecker@adacore.com/mbox/"},{"id":26493,"url":"https://patchwork.plctlab.org/api/1.2/patches/26493/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5965a4d1d20a33accd4a9872f87da9e0fd6c1747.1669610611.git.research_trasio@irq.a4lg.com/","msgid":"<5965a4d1d20a33accd4a9872f87da9e0fd6c1747.1669610611.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-28T04:43:36","name":"[v2,01/11] opcodes/riscv-dis.c: More tidying","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5965a4d1d20a33accd4a9872f87da9e0fd6c1747.1669610611.git.research_trasio@irq.a4lg.com/mbox/"},{"id":26494,"url":"https://patchwork.plctlab.org/api/1.2/patches/26494/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/761a39a87ef882c6d99d135988d251d18c2bf096.1669610611.git.research_trasio@irq.a4lg.com/","msgid":"<761a39a87ef882c6d99d135988d251d18c2bf096.1669610611.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-28T04:43:37","name":"[v2,02/11] RISC-V: Add test for '\''Zfinx'\'' register switching","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/761a39a87ef882c6d99d135988d251d18c2bf096.1669610611.git.research_trasio@irq.a4lg.com/mbox/"},{"id":26495,"url":"https://patchwork.plctlab.org/api/1.2/patches/26495/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c52af18da452a844c5fddf64b9b8e7b53f208111.1669610611.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-11-28T04:43:38","name":"[v2,03/11] RISC-V: Make mapping symbol checking consistent","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c52af18da452a844c5fddf64b9b8e7b53f208111.1669610611.git.research_trasio@irq.a4lg.com/mbox/"},{"id":26497,"url":"https://patchwork.plctlab.org/api/1.2/patches/26497/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/395973f56b805a000b0e2929c6b2ba6cd8fd140b.1669610611.git.research_trasio@irq.a4lg.com/","msgid":"<395973f56b805a000b0e2929c6b2ba6cd8fd140b.1669610611.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-28T04:43:39","name":"[v2,04/11] RISC-V: Split riscv_get_map_state into two steps","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/395973f56b805a000b0e2929c6b2ba6cd8fd140b.1669610611.git.research_trasio@irq.a4lg.com/mbox/"},{"id":26496,"url":"https://patchwork.plctlab.org/api/1.2/patches/26496/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/72c8e56861fccff6720a9b6ccefcecfd80e1adba.1669610611.git.research_trasio@irq.a4lg.com/","msgid":"<72c8e56861fccff6720a9b6ccefcecfd80e1adba.1669610611.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-28T04:43:40","name":"[v2,05/11] RISC-V: One time CSR hash table initialization","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/72c8e56861fccff6720a9b6ccefcecfd80e1adba.1669610611.git.research_trasio@irq.a4lg.com/mbox/"},{"id":26499,"url":"https://patchwork.plctlab.org/api/1.2/patches/26499/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/072cb269b90f85fdfd880a6513080a18ddde015d.1669610611.git.research_trasio@irq.a4lg.com/","msgid":"<072cb269b90f85fdfd880a6513080a18ddde015d.1669610611.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-28T04:43:41","name":"[v2,06/11] RISC-V: Use static xlen on ADDIW sequence","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/072cb269b90f85fdfd880a6513080a18ddde015d.1669610611.git.research_trasio@irq.a4lg.com/mbox/"},{"id":26503,"url":"https://patchwork.plctlab.org/api/1.2/patches/26503/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8f4167371bc52f2c4c7fc6f1a0fc3775e8e8de95.1669610611.git.research_trasio@irq.a4lg.com/","msgid":"<8f4167371bc52f2c4c7fc6f1a0fc3775e8e8de95.1669610611.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-28T04:43:42","name":"[v2,07/11] opcodes/riscv-dis.c: Add form feed for separation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8f4167371bc52f2c4c7fc6f1a0fc3775e8e8de95.1669610611.git.research_trasio@irq.a4lg.com/mbox/"},{"id":26498,"url":"https://patchwork.plctlab.org/api/1.2/patches/26498/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c30cdce491780153a7fe89b79ac4b5f1a03f6e5c.1669610611.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-11-28T04:43:43","name":"[v2,08/11] RISC-V: Split match/print steps on disassembler","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c30cdce491780153a7fe89b79ac4b5f1a03f6e5c.1669610611.git.research_trasio@irq.a4lg.com/mbox/"},{"id":26506,"url":"https://patchwork.plctlab.org/api/1.2/patches/26506/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a30d861f289af8dfaf7c80ff275980699aa78482.1669610611.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-11-28T04:43:44","name":"[v2,09/11] RISC-V: Reorganize disassembler state initialization","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a30d861f289af8dfaf7c80ff275980699aa78482.1669610611.git.research_trasio@irq.a4lg.com/mbox/"},{"id":26508,"url":"https://patchwork.plctlab.org/api/1.2/patches/26508/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0e328130d90af42f30e3632fadd6c48e422b7b82.1669610611.git.research_trasio@irq.a4lg.com/","msgid":"<0e328130d90af42f30e3632fadd6c48e422b7b82.1669610611.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-28T04:43:45","name":"[v2,10/11] RISC-V: Reorganize arch-related initialization and management","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0e328130d90af42f30e3632fadd6c48e422b7b82.1669610611.git.research_trasio@irq.a4lg.com/mbox/"},{"id":26500,"url":"https://patchwork.plctlab.org/api/1.2/patches/26500/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/75d9e5b0cfebcce34c855e4c98a956de4d7d7753.1669610611.git.research_trasio@irq.a4lg.com/","msgid":"<75d9e5b0cfebcce34c855e4c98a956de4d7d7753.1669610611.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-28T04:43:46","name":"[v2,11/11] RISC-V: Move disassembler private data initialization","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/75d9e5b0cfebcce34c855e4c98a956de4d7d7753.1669610611.git.research_trasio@irq.a4lg.com/mbox/"},{"id":26504,"url":"https://patchwork.plctlab.org/api/1.2/patches/26504/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a3f9238a36255d5bd251cc73cee6a47eea6b9b49.1669610780.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-11-28T04:46:20","name":"[v2,1/3] RISC-V: Use faster hash table on disassembling","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a3f9238a36255d5bd251cc73cee6a47eea6b9b49.1669610780.git.research_trasio@irq.a4lg.com/mbox/"},{"id":26507,"url":"https://patchwork.plctlab.org/api/1.2/patches/26507/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0cd0bbfa70f83db276facb842b9a7bca1aaa77a6.1669610780.git.research_trasio@irq.a4lg.com/","msgid":"<0cd0bbfa70f83db276facb842b9a7bca1aaa77a6.1669610780.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-28T04:46:21","name":"[v2,2/3] RISC-V: Fallback on faster hash table","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0cd0bbfa70f83db276facb842b9a7bca1aaa77a6.1669610780.git.research_trasio@irq.a4lg.com/mbox/"},{"id":26501,"url":"https://patchwork.plctlab.org/api/1.2/patches/26501/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5b561967091a59d0052bd717d1b9f3e31ef841cc.1669610780.git.research_trasio@irq.a4lg.com/","msgid":"<5b561967091a59d0052bd717d1b9f3e31ef841cc.1669610780.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-28T04:46:22","name":"[v2,3/3] RISC-V: Cache instruction support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5b561967091a59d0052bd717d1b9f3e31ef841cc.1669610780.git.research_trasio@irq.a4lg.com/mbox/"},{"id":26505,"url":"https://patchwork.plctlab.org/api/1.2/patches/26505/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c49e114f7ae383c0e1da452391f19ecf45a3896e.1669610841.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-11-28T04:47:21","name":"[v2,1/3] RISC-V: Easy optimization on riscv_search_mapping_symbol","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c49e114f7ae383c0e1da452391f19ecf45a3896e.1669610841.git.research_trasio@irq.a4lg.com/mbox/"},{"id":26509,"url":"https://patchwork.plctlab.org/api/1.2/patches/26509/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4b8fcca24b8897f382b6e32fd29337f0b6972e2f.1669610841.git.research_trasio@irq.a4lg.com/","msgid":"<4b8fcca24b8897f382b6e32fd29337f0b6972e2f.1669610841.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-28T04:47:22","name":"[v2,2/3] RISC-V: Per-section private data initialization","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4b8fcca24b8897f382b6e32fd29337f0b6972e2f.1669610841.git.research_trasio@irq.a4lg.com/mbox/"},{"id":26510,"url":"https://patchwork.plctlab.org/api/1.2/patches/26510/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f1cbc305ba19880fa0631ebe691b5c0984cbf111.1669610841.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-11-28T04:47:23","name":"[v2,3/3] RISC-V: Optimized search on mapping symbols","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f1cbc305ba19880fa0631ebe691b5c0984cbf111.1669610841.git.research_trasio@irq.a4lg.com/mbox/"},{"id":26531,"url":"https://patchwork.plctlab.org/api/1.2/patches/26531/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221128063532.1153605-1-jiawei@iscas.ac.cn/","msgid":"<20221128063532.1153605-1-jiawei@iscas.ac.cn>","list_archive_url":null,"date":"2022-11-28T06:35:32","name":"RISC-V: Add support for RISCV64 EFI(efi-*-riscv64)","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221128063532.1153605-1-jiawei@iscas.ac.cn/mbox/"},{"id":26532,"url":"https://patchwork.plctlab.org/api/1.2/patches/26532/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d1c4d243e6e33c6d0c681a7de3a8fb8be548c99d.1669617534.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-11-28T06:39:32","name":"[1/3] RISC-V: Allocate \"various\" operand type","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d1c4d243e6e33c6d0c681a7de3a8fb8be548c99d.1669617534.git.research_trasio@irq.a4lg.com/mbox/"},{"id":26533,"url":"https://patchwork.plctlab.org/api/1.2/patches/26533/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1a60e4b17f89e7aa94a6a41674f885398e5afd85.1669617534.git.research_trasio@irq.a4lg.com/","msgid":"<1a60e4b17f89e7aa94a6a41674f885398e5afd85.1669617534.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-28T06:39:33","name":"[2/3] RISC-V: Reorganize invalid rounding mode test","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1a60e4b17f89e7aa94a6a41674f885398e5afd85.1669617534.git.research_trasio@irq.a4lg.com/mbox/"},{"id":26534,"url":"https://patchwork.plctlab.org/api/1.2/patches/26534/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/354029278ac02efee0bf1f1dbc3514647f057424.1669617534.git.research_trasio@irq.a4lg.com/","msgid":"<354029278ac02efee0bf1f1dbc3514647f057424.1669617534.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-28T06:39:34","name":"[3/3] RISC-V: Rounding mode on widening instructions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/354029278ac02efee0bf1f1dbc3514647f057424.1669617534.git.research_trasio@irq.a4lg.com/mbox/"},{"id":26600,"url":"https://patchwork.plctlab.org/api/1.2/patches/26600/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y4SDJrb7d7HMtR7H@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-11-28T09:45:10","name":"asan: pef: buffer overflow","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y4SDJrb7d7HMtR7H@squeak.grove.modra.org/mbox/"},{"id":26601,"url":"https://patchwork.plctlab.org/api/1.2/patches/26601/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y4SDxVt7uN6m6oKA@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-11-28T09:47:49","name":"PR10368, ISO 8859 mentioned as 7bit encoding in strings documentation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y4SDxVt7uN6m6oKA@squeak.grove.modra.org/mbox/"},{"id":26634,"url":"https://patchwork.plctlab.org/api/1.2/patches/26634/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/da678d9e-b1eb-e599-ec0b-2a991d65e61c@suse.com/","msgid":"","list_archive_url":null,"date":"2022-11-28T11:30:46","name":"[v3,1/6] x86: instantiate i386_{op, reg}tab[] in gas instead of in libopcodes","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/da678d9e-b1eb-e599-ec0b-2a991d65e61c@suse.com/mbox/"},{"id":26636,"url":"https://patchwork.plctlab.org/api/1.2/patches/26636/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/851ace49-624f-c3bc-805f-59feeaf8a711@suse.com/","msgid":"<851ace49-624f-c3bc-805f-59feeaf8a711@suse.com>","list_archive_url":null,"date":"2022-11-28T11:31:20","name":"[v3,2/6] x86: remove i386-opc.c","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/851ace49-624f-c3bc-805f-59feeaf8a711@suse.com/mbox/"},{"id":26638,"url":"https://patchwork.plctlab.org/api/1.2/patches/26638/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2bf96982-d3d6-026a-ca1c-16b932d9630a@suse.com/","msgid":"<2bf96982-d3d6-026a-ca1c-16b932d9630a@suse.com>","list_archive_url":null,"date":"2022-11-28T11:31:44","name":"[v3,3/6] x86: break gas dependency on libopcodes","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2bf96982-d3d6-026a-ca1c-16b932d9630a@suse.com/mbox/"},{"id":26640,"url":"https://patchwork.plctlab.org/api/1.2/patches/26640/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c8f5780b-072e-b184-f153-3c2af7ea577e@suse.com/","msgid":"","list_archive_url":null,"date":"2022-11-28T11:32:07","name":"[v3,4/6] x86: add generated tables dependency check to gas","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c8f5780b-072e-b184-f153-3c2af7ea577e@suse.com/mbox/"},{"id":26643,"url":"https://patchwork.plctlab.org/api/1.2/patches/26643/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/414cbe39-9398-ddab-97f2-93d6c0bf9852@suse.com/","msgid":"<414cbe39-9398-ddab-97f2-93d6c0bf9852@suse.com>","list_archive_url":null,"date":"2022-11-28T11:32:40","name":"[v3,5/6] x86: drop sentinel from i386_optab[]","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/414cbe39-9398-ddab-97f2-93d6c0bf9852@suse.com/mbox/"},{"id":26644,"url":"https://patchwork.plctlab.org/api/1.2/patches/26644/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0387160b-8925-7515-e287-e1f240f93523@suse.com/","msgid":"<0387160b-8925-7515-e287-e1f240f93523@suse.com>","list_archive_url":null,"date":"2022-11-28T11:33:37","name":"[v3,6/6] x86: generate template sets data at build time","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0387160b-8925-7515-e287-e1f240f93523@suse.com/mbox/"},{"id":26794,"url":"https://patchwork.plctlab.org/api/1.2/patches/26794/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/67cc7870-f49c-08ed-afb3-e83f4378095a@arm.com/","msgid":"<67cc7870-f49c-08ed-afb3-e83f4378095a@arm.com>","list_archive_url":null,"date":"2022-11-28T14:13:12","name":"[1/2] gas: arm: Fix a further IT-predicated vcvt issue in the presense of MVE vcvtn","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/67cc7870-f49c-08ed-afb3-e83f4378095a@arm.com/mbox/"},{"id":26795,"url":"https://patchwork.plctlab.org/api/1.2/patches/26795/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b40e6dc8-9ff8-000c-f639-ee516c4ccab7@arm.com/","msgid":"","list_archive_url":null,"date":"2022-11-28T14:13:27","name":"[2/2] gas: arm: Change warning message to not reference specific A-class architecture revision","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b40e6dc8-9ff8-000c-f639-ee516c4ccab7@arm.com/mbox/"},{"id":26799,"url":"https://patchwork.plctlab.org/api/1.2/patches/26799/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/661d0e07-cc75-0fba-941b-88160dbcbb13@suse.com/","msgid":"<661d0e07-cc75-0fba-941b-88160dbcbb13@suse.com>","list_archive_url":null,"date":"2022-11-28T14:24:31","name":"x86/Intel: adjustment to restricted suffix derivation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/661d0e07-cc75-0fba-941b-88160dbcbb13@suse.com/mbox/"},{"id":26977,"url":"https://patchwork.plctlab.org/api/1.2/patches/26977/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/CAMe9rOpbKEZ=wSgTbDLEXgzj2sbAHp1uU0WSGy0qTPL1fakM0g@mail.gmail.com/","msgid":"","list_archive_url":null,"date":"2022-11-28T23:49:42","name":"[v2] x86: Remove libopcodes dependency","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/CAMe9rOpbKEZ=wSgTbDLEXgzj2sbAHp1uU0WSGy0qTPL1fakM0g@mail.gmail.com/mbox/"},{"id":26982,"url":"https://patchwork.plctlab.org/api/1.2/patches/26982/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221129001015.21775-1-mark@harmstone.com/","msgid":"<20221129001015.21775-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-11-29T00:10:13","name":"ld: Write types into TPI stream of PDB","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221129001015.21775-1-mark@harmstone.com/mbox/"},{"id":26981,"url":"https://patchwork.plctlab.org/api/1.2/patches/26981/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221129001015.21775-2-mark@harmstone.com/","msgid":"<20221129001015.21775-2-mark@harmstone.com>","list_archive_url":null,"date":"2022-11-29T00:10:14","name":"ld: Write types into IPI stream of PDB","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221129001015.21775-2-mark@harmstone.com/mbox/"},{"id":26983,"url":"https://patchwork.plctlab.org/api/1.2/patches/26983/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221129001015.21775-3-mark@harmstone.com/","msgid":"<20221129001015.21775-3-mark@harmstone.com>","list_archive_url":null,"date":"2022-11-29T00:10:15","name":"ld: Parse LF_UDT_SRC_LINE records when creating PDB file","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221129001015.21775-3-mark@harmstone.com/mbox/"},{"id":26994,"url":"https://patchwork.plctlab.org/api/1.2/patches/26994/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/daddde128db2f014de16a7cf8a229aed53074b02.1669684562.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-11-29T01:16:56","name":"[REVIEW,ONLY,1/1] UNRATIFIED RISC-V: Add '\''ZiCondOps'\'' extension","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/daddde128db2f014de16a7cf8a229aed53074b02.1669684562.git.research_trasio@irq.a4lg.com/mbox/"},{"id":26995,"url":"https://patchwork.plctlab.org/api/1.2/patches/26995/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/29f89ef04335561879d14d9cdb8e1e9a550bc811.1669684692.git.research_trasio@irq.a4lg.com/","msgid":"<29f89ef04335561879d14d9cdb8e1e9a550bc811.1669684692.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-29T01:18:15","name":"[REVIEW,ONLY,1/1] UNRATIFIED RISC-V: Add '\''Svadu'\'' extension","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/29f89ef04335561879d14d9cdb8e1e9a550bc811.1669684692.git.research_trasio@irq.a4lg.com/mbox/"},{"id":26996,"url":"https://patchwork.plctlab.org/api/1.2/patches/26996/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d32f305c187892c2a97fef6eebca220c90eac3b7.1669684774.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-11-29T01:19:53","name":"[REVIEW,ONLY,1/1] UNRATIFIED RISC-V: Add '\''Smclic'\'' extension and its CSRs","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d32f305c187892c2a97fef6eebca220c90eac3b7.1669684774.git.research_trasio@irq.a4lg.com/mbox/"},{"id":26997,"url":"https://patchwork.plctlab.org/api/1.2/patches/26997/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/54d777ce6e71c02b8b0f9426367e98d0f927ce40.1669684854.git.research_trasio@irq.a4lg.com/","msgid":"<54d777ce6e71c02b8b0f9426367e98d0f927ce40.1669684854.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-29T01:20:57","name":"[REVIEW,ONLY,1/2] UNRATIFIED RISC-V: Add '\''Sspmp'\'' extension and its TENTATIVE CSRs","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/54d777ce6e71c02b8b0f9426367e98d0f927ce40.1669684854.git.research_trasio@irq.a4lg.com/mbox/"},{"id":26998,"url":"https://patchwork.plctlab.org/api/1.2/patches/26998/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ee7c7490f10af1e9cc9c9475814e4d8a9b1a9304.1669684854.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-11-29T01:20:58","name":"[REVIEW,ONLY,2/2] TEST: Add instantiation script on CSR allocation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ee7c7490f10af1e9cc9c9475814e4d8a9b1a9304.1669684854.git.research_trasio@irq.a4lg.com/mbox/"},{"id":27004,"url":"https://patchwork.plctlab.org/api/1.2/patches/27004/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/03cbfeb6934c7bf653cbdfbafcc6ee5ce3cb519c.1669684907.git.research_trasio@irq.a4lg.com/","msgid":"<03cbfeb6934c7bf653cbdfbafcc6ee5ce3cb519c.1669684907.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-29T01:21:51","name":"[REVIEW,ONLY,1/1] UNRATIFIED RISC-V: Add '\''Smrnmi'\'' extension and its CSRs","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/03cbfeb6934c7bf653cbdfbafcc6ee5ce3cb519c.1669684907.git.research_trasio@irq.a4lg.com/mbox/"},{"id":27013,"url":"https://patchwork.plctlab.org/api/1.2/patches/27013/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0187562c00ee6c8ba82439bd61e46a1899b9f916.1669684988.git.research_trasio@irq.a4lg.com/","msgid":"<0187562c00ee6c8ba82439bd61e46a1899b9f916.1669684988.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-29T01:23:57","name":"[REVIEW,ONLY,1/3] RISC-V: Add \"XUN@S\" operand type","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0187562c00ee6c8ba82439bd61e46a1899b9f916.1669684988.git.research_trasio@irq.a4lg.com/mbox/"},{"id":27017,"url":"https://patchwork.plctlab.org/api/1.2/patches/27017/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/cae340b249629f0b05b527ae8aec3023b159b487.1669684988.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-11-29T01:23:58","name":"[REVIEW,ONLY,2/3] UNRATIFIED RISC-V: Add '\''Zisslpcfi'\'' extension and its TENTATIVE CSRs","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/cae340b249629f0b05b527ae8aec3023b159b487.1669684988.git.research_trasio@irq.a4lg.com/mbox/"},{"id":27018,"url":"https://patchwork.plctlab.org/api/1.2/patches/27018/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/73828cb4ccf8c03275b6af7e42872d661dea267f.1669684988.git.research_trasio@irq.a4lg.com/","msgid":"<73828cb4ccf8c03275b6af7e42872d661dea267f.1669684988.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-29T01:23:59","name":"[REVIEW,ONLY,3/3] TEST: Add instantiation script on CSR allocation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/73828cb4ccf8c03275b6af7e42872d661dea267f.1669684988.git.research_trasio@irq.a4lg.com/mbox/"},{"id":27030,"url":"https://patchwork.plctlab.org/api/1.2/patches/27030/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d6ee991833120682dc021b0269f5535c9ac3a806.1669687611.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-11-29T02:06:57","name":"[REVIEW,ONLY,v2,1/1] UNRATIFIED RISC-V: Add '\''ZiCondOps'\'' extension","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d6ee991833120682dc021b0269f5535c9ac3a806.1669687611.git.research_trasio@irq.a4lg.com/mbox/"},{"id":27035,"url":"https://patchwork.plctlab.org/api/1.2/patches/27035/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221129022520.2218851-1-jcmvbkbc@gmail.com/","msgid":"<20221129022520.2218851-1-jcmvbkbc@gmail.com>","list_archive_url":null,"date":"2022-11-29T02:25:20","name":"[COMMITTED] xtensa: allow dynamic configuration","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221129022520.2218851-1-jcmvbkbc@gmail.com/mbox/"},{"id":27161,"url":"https://patchwork.plctlab.org/api/1.2/patches/27161/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/01b77f18-8af3-4128-3645-2f1e05690197@suse.com/","msgid":"<01b77f18-8af3-4128-3645-2f1e05690197@suse.com>","list_archive_url":null,"date":"2022-11-29T10:36:21","name":"[1/5] gas: avoid inserting extra newline in buffer_and_nest()","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/01b77f18-8af3-4128-3645-2f1e05690197@suse.com/mbox/"},{"id":27163,"url":"https://patchwork.plctlab.org/api/1.2/patches/27163/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2ae84a68-29f3-d94d-1a12-c3d0c81f81a3@suse.com/","msgid":"<2ae84a68-29f3-d94d-1a12-c3d0c81f81a3@suse.com>","list_archive_url":null,"date":"2022-11-29T10:36:59","name":"[2/5] gas: squash (some) .linefile from listings","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2ae84a68-29f3-d94d-1a12-c3d0c81f81a3@suse.com/mbox/"},{"id":27164,"url":"https://patchwork.plctlab.org/api/1.2/patches/27164/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8b41d62d-8345-a2bd-ce90-27d79aefe2eb@suse.com/","msgid":"<8b41d62d-8345-a2bd-ce90-27d79aefe2eb@suse.com>","list_archive_url":null,"date":"2022-11-29T10:37:42","name":"[3/5] gas: add Dwarf line number test for .macro expansions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8b41d62d-8345-a2bd-ce90-27d79aefe2eb@suse.com/mbox/"},{"id":27165,"url":"https://patchwork.plctlab.org/api/1.2/patches/27165/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ca933e73-103d-0e9c-84b7-f0a1650dfa2f@suse.com/","msgid":"","list_archive_url":null,"date":"2022-11-29T10:38:52","name":"[4/5] Arm: avoid unhelpful use of .macro in testsuite","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ca933e73-103d-0e9c-84b7-f0a1650dfa2f@suse.com/mbox/"},{"id":27167,"url":"https://patchwork.plctlab.org/api/1.2/patches/27167/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1c75f3b4-14ac-fa39-fac8-2c98b4c4dbab@suse.com/","msgid":"<1c75f3b4-14ac-fa39-fac8-2c98b4c4dbab@suse.com>","list_archive_url":null,"date":"2022-11-29T10:44:51","name":"[5/5] gas: re-work line number tracking for macros and their expansions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1c75f3b4-14ac-fa39-fac8-2c98b4c4dbab@suse.com/mbox/"},{"id":27626,"url":"https://patchwork.plctlab.org/api/1.2/patches/27626/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y4cPz0nw9PS+slTj@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-11-30T08:09:51","name":"regen SRC-POTFILES.in","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y4cPz0nw9PS+slTj@squeak.grove.modra.org/mbox/"},{"id":27629,"url":"https://patchwork.plctlab.org/api/1.2/patches/27629/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y4cQAk+8VjJUNcAS@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-11-30T08:10:42","name":"Correct ordering problem in comm-data.exp","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y4cQAk+8VjJUNcAS@squeak.grove.modra.org/mbox/"},{"id":27689,"url":"https://patchwork.plctlab.org/api/1.2/patches/27689/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3d8c5353-723d-31ec-8efa-ee4fc994eaec@suse.com/","msgid":"<3d8c5353-723d-31ec-8efa-ee4fc994eaec@suse.com>","list_archive_url":null,"date":"2022-11-30T08:54:43","name":"[1/4] x86/Intel: restrict use of LONG_DOUBLE_MNEM_SUFFIX","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3d8c5353-723d-31ec-8efa-ee4fc994eaec@suse.com/mbox/"},{"id":27690,"url":"https://patchwork.plctlab.org/api/1.2/patches/27690/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/934cece1-77ed-b4ee-a61d-451d71680a9e@suse.com/","msgid":"<934cece1-77ed-b4ee-a61d-451d71680a9e@suse.com>","list_archive_url":null,"date":"2022-11-30T08:55:11","name":"[2/4] x86/Intel: drop LONG_DOUBLE_MNEM_SUFFIX","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/934cece1-77ed-b4ee-a61d-451d71680a9e@suse.com/mbox/"},{"id":27691,"url":"https://patchwork.plctlab.org/api/1.2/patches/27691/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f0d0c80a-1b30-6e13-ceff-d3a1061db2ea@suse.com/","msgid":"","list_archive_url":null,"date":"2022-11-30T08:55:43","name":"[3/4] x86: drop No_ldSuf","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f0d0c80a-1b30-6e13-ceff-d3a1061db2ea@suse.com/mbox/"},{"id":27692,"url":"https://patchwork.plctlab.org/api/1.2/patches/27692/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/787c0eff-5b73-ed04-6e06-e3f49d5a3ce1@suse.com/","msgid":"<787c0eff-5b73-ed04-6e06-e3f49d5a3ce1@suse.com>","list_archive_url":null,"date":"2022-11-30T08:56:52","name":"[4/4] x86: rework of match_template()'\''s suffix checking","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/787c0eff-5b73-ed04-6e06-e3f49d5a3ce1@suse.com/mbox/"}],"public":true,"mbox":"https://patchwork.plctlab.org/bundle/patchwork-bot/binutils-gdb_2022-11/mbox/"},{"id":12,"url":"https://patchwork.plctlab.org/api/1.2/bundles/12/","web_url":"https://patchwork.plctlab.org/bundle/patchwork-bot/binutils-gdb_2022-12/","project":{"id":2,"url":"https://patchwork.plctlab.org/api/1.2/projects/2/","name":"binutils-gdb","link_name":"binutils-gdb","list_id":"binutils.sourceware.org","list_email":"binutils@sourceware.org","web_url":"https://github.com/wangliu-iscas/Patchwork-Bundles/blob/main/binutils-gdb.md","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"name":"binutils-gdb_2022-12","owner":{"id":3,"url":"https://patchwork.plctlab.org/api/1.2/users/3/","username":"patchwork-bot","first_name":"","last_name":"","email":"ouuuleilei@gmail.com"},"patches":[{"id":28023,"url":"https://patchwork.plctlab.org/api/1.2/patches/28023/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221130214802.32340-1-hjl.tools@gmail.com/","msgid":"<20221130214802.32340-1-hjl.tools@gmail.com>","list_archive_url":null,"date":"2022-11-30T21:48:02","name":"opcodes: Remove i386-init.h and i386-tbl.h from HFILES","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221130214802.32340-1-hjl.tools@gmail.com/mbox/"},{"id":28172,"url":"https://patchwork.plctlab.org/api/1.2/patches/28172/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f6ef4412c1f0d5a7b0292f443ea5aee31c25056d.1669864784.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-12-01T03:20:31","name":"[REVIEW,ONLY,v3,1/1] UNRATIFIED RISC-V: Add '\''ZiCond'\'' extension","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f6ef4412c1f0d5a7b0292f443ea5aee31c25056d.1669864784.git.research_trasio@irq.a4lg.com/mbox/"},{"id":28257,"url":"https://patchwork.plctlab.org/api/1.2/patches/28257/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/673753a0-ab7b-6c44-844e-3addfcf01693@suse.com/","msgid":"<673753a0-ab7b-6c44-844e-3addfcf01693@suse.com>","list_archive_url":null,"date":"2022-12-01T09:09:26","name":"x86: also use D for XCHG and TEST","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/673753a0-ab7b-6c44-844e-3addfcf01693@suse.com/mbox/"},{"id":28258,"url":"https://patchwork.plctlab.org/api/1.2/patches/28258/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/35539292-53a8-292d-2f5d-f65ad02a36bb@suse.com/","msgid":"<35539292-53a8-292d-2f5d-f65ad02a36bb@suse.com>","list_archive_url":null,"date":"2022-12-01T09:11:50","name":"x86: simplify and slightly correct XCHG vs NOP checking","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/35539292-53a8-292d-2f5d-f65ad02a36bb@suse.com/mbox/"},{"id":28260,"url":"https://patchwork.plctlab.org/api/1.2/patches/28260/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b56e7b03-c15b-a932-bd6b-e026d9ae8675@suse.com/","msgid":"","list_archive_url":null,"date":"2022-12-01T09:20:24","name":"x86: drop most OPERAND_TYPE_* (and rework the rest)","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b56e7b03-c15b-a932-bd6b-e026d9ae8675@suse.com/mbox/"},{"id":28274,"url":"https://patchwork.plctlab.org/api/1.2/patches/28274/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221201094409.1982624-1-chigot@adacore.com/","msgid":"<20221201094409.1982624-1-chigot@adacore.com>","list_archive_url":null,"date":"2022-12-01T09:44:09","name":"binutils: improve holes detection in .debug_loclists.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221201094409.1982624-1-chigot@adacore.com/mbox/"},{"id":28448,"url":"https://patchwork.plctlab.org/api/1.2/patches/28448/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221201162038.421271-1-hjl.tools@gmail.com/","msgid":"<20221201162038.421271-1-hjl.tools@gmail.com>","list_archive_url":null,"date":"2022-12-01T16:20:38","name":"opcodes: Make i386-init.h depend on i386-tbl.h","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221201162038.421271-1-hjl.tools@gmail.com/mbox/"},{"id":28503,"url":"https://patchwork.plctlab.org/api/1.2/patches/28503/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y4jx62oUPn2PB3tC@gmail.com/","msgid":"","list_archive_url":null,"date":"2022-12-01T18:26:51","name":"[v3] x86: Remove libopcodes dependency","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y4jx62oUPn2PB3tC@gmail.com/mbox/"},{"id":28837,"url":"https://patchwork.plctlab.org/api/1.2/patches/28837/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/87mt8615k1.fsf@redhat.com/","msgid":"<87mt8615k1.fsf@redhat.com>","list_archive_url":null,"date":"2022-12-02T10:08:30","name":"Adding Jan Beulich as an x86_64 maintainer","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/87mt8615k1.fsf@redhat.com/mbox/"},{"id":28852,"url":"https://patchwork.plctlab.org/api/1.2/patches/28852/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8bfb1c56-8207-fe92-87ae-1b7ef26b3544@suse.com/","msgid":"<8bfb1c56-8207-fe92-87ae-1b7ef26b3544@suse.com>","list_archive_url":null,"date":"2022-12-02T10:18:00","name":"[v7,1/7] x86: constify parse_insn()'\''s input","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8bfb1c56-8207-fe92-87ae-1b7ef26b3544@suse.com/mbox/"},{"id":28855,"url":"https://patchwork.plctlab.org/api/1.2/patches/28855/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6043f9b3-1ea1-ea4a-59ae-dcccf129c241@suse.com/","msgid":"<6043f9b3-1ea1-ea4a-59ae-dcccf129c241@suse.com>","list_archive_url":null,"date":"2022-12-02T10:18:54","name":"[v7,2/7] x86: re-work insn/suffix recognition","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6043f9b3-1ea1-ea4a-59ae-dcccf129c241@suse.com/mbox/"},{"id":28856,"url":"https://patchwork.plctlab.org/api/1.2/patches/28856/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f7f77244-9782-0bc1-365c-e73d72045f36@suse.com/","msgid":"","list_archive_url":null,"date":"2022-12-02T10:19:32","name":"[v7,3/7] ix86: don'\''t recognize/derive Q suffix in the common case","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f7f77244-9782-0bc1-365c-e73d72045f36@suse.com/mbox/"},{"id":28857,"url":"https://patchwork.plctlab.org/api/1.2/patches/28857/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/77fa4300-e192-5b9d-d699-37255054d391@suse.com/","msgid":"<77fa4300-e192-5b9d-d699-37255054d391@suse.com>","list_archive_url":null,"date":"2022-12-02T10:20:06","name":"[v7,4/7] x86-64: allow HLE store of accumulator to absolute 32-bit address","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/77fa4300-e192-5b9d-d699-37255054d391@suse.com/mbox/"},{"id":28860,"url":"https://patchwork.plctlab.org/api/1.2/patches/28860/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b4c2d623-517c-f5e8-90d9-01e933a68a00@suse.com/","msgid":"","list_archive_url":null,"date":"2022-12-02T10:20:34","name":"[v7,5/7] x86: move bad-use-of-TLS-reloc check","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b4c2d623-517c-f5e8-90d9-01e933a68a00@suse.com/mbox/"},{"id":28859,"url":"https://patchwork.plctlab.org/api/1.2/patches/28859/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ac7e5911-4c5e-27c3-b0e5-cd3dcfa67155@suse.com/","msgid":"","list_archive_url":null,"date":"2022-12-02T10:21:02","name":"[v7,6/7] x86: drop (now) stray IsString","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ac7e5911-4c5e-27c3-b0e5-cd3dcfa67155@suse.com/mbox/"},{"id":28861,"url":"https://patchwork.plctlab.org/api/1.2/patches/28861/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/46702842-5bc7-113e-bab8-d67304f0f337@suse.com/","msgid":"<46702842-5bc7-113e-bab8-d67304f0f337@suse.com>","list_archive_url":null,"date":"2022-12-02T10:21:46","name":"[v7,7/7] x86: further re-work insn/suffix recognition to also cover MOVSX","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/46702842-5bc7-113e-bab8-d67304f0f337@suse.com/mbox/"},{"id":29215,"url":"https://patchwork.plctlab.org/api/1.2/patches/29215/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221203041307.34407-1-hjl.tools@gmail.com/","msgid":"<20221203041307.34407-1-hjl.tools@gmail.com>","list_archive_url":null,"date":"2022-12-03T04:13:07","name":"x86: Allow 16-bit register source for LAR and LSL","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221203041307.34407-1-hjl.tools@gmail.com/mbox/"},{"id":29241,"url":"https://patchwork.plctlab.org/api/1.2/patches/29241/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221203073435.1451856-1-mengqinggang@loongson.cn/","msgid":"<20221203073435.1451856-1-mengqinggang@loongson.cn>","list_archive_url":null,"date":"2022-12-03T07:34:35","name":"LoongArch: Fix dynamic reloc not generated bug in some cases.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221203073435.1451856-1-mengqinggang@loongson.cn/mbox/"},{"id":29297,"url":"https://patchwork.plctlab.org/api/1.2/patches/29297/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221203174330.682680-1-hjl.tools@gmail.com/","msgid":"<20221203174330.682680-1-hjl.tools@gmail.com>","list_archive_url":null,"date":"2022-12-03T17:43:30","name":"ld: Add .note.GNU-stack to ld-plugin/dummy.s","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221203174330.682680-1-hjl.tools@gmail.com/mbox/"},{"id":29299,"url":"https://patchwork.plctlab.org/api/1.2/patches/29299/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221203184408.866763-1-hjl.tools@gmail.com/","msgid":"<20221203184408.866763-1-hjl.tools@gmail.com>","list_archive_url":null,"date":"2022-12-03T18:44:08","name":"Revert \"ld: Add .note.GNU-stack to ld-plugin/dummy.s\"","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221203184408.866763-1-hjl.tools@gmail.com/mbox/"},{"id":29461,"url":"https://patchwork.plctlab.org/api/1.2/patches/29461/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y40WXnjN0f0LjrIt@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-12-04T21:51:26","name":"Renaming .debug to .zdebug and vice versa","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y40WXnjN0f0LjrIt@squeak.grove.modra.org/mbox/"},{"id":29462,"url":"https://patchwork.plctlab.org/api/1.2/patches/29462/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y40WfJl0V9ifv+fN@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-12-04T21:51:56","name":"COFF compressed debug support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y40WfJl0V9ifv+fN@squeak.grove.modra.org/mbox/"},{"id":29463,"url":"https://patchwork.plctlab.org/api/1.2/patches/29463/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y40WrrfotDOwKqZb@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-12-04T21:52:46","name":"PR29846, segmentation fault in objdump.c compare_symbols","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y40WrrfotDOwKqZb@squeak.grove.modra.org/mbox/"},{"id":29492,"url":"https://patchwork.plctlab.org/api/1.2/patches/29492/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221205015347.25781-1-mark@harmstone.com/","msgid":"<20221205015347.25781-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-12-05T01:53:45","name":"ld: Write globals stream in PDB","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221205015347.25781-1-mark@harmstone.com/mbox/"},{"id":29491,"url":"https://patchwork.plctlab.org/api/1.2/patches/29491/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221205015347.25781-2-mark@harmstone.com/","msgid":"<20221205015347.25781-2-mark@harmstone.com>","list_archive_url":null,"date":"2022-12-05T01:53:46","name":"ld: Copy other symbols into PDB file","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221205015347.25781-2-mark@harmstone.com/mbox/"},{"id":29490,"url":"https://patchwork.plctlab.org/api/1.2/patches/29490/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221205015347.25781-3-mark@harmstone.com/","msgid":"<20221205015347.25781-3-mark@harmstone.com>","list_archive_url":null,"date":"2022-12-05T01:53:47","name":"ld: Write linker symbols in PDB","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221205015347.25781-3-mark@harmstone.com/mbox/"},{"id":29502,"url":"https://patchwork.plctlab.org/api/1.2/patches/29502/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221205025311.73743-1-haochen.jiang@intel.com/","msgid":"<20221205025311.73743-1-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-12-05T02:53:11","name":"x86: Remove unnecessary vex.w check for xh_mode in disassembler","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221205025311.73743-1-haochen.jiang@intel.com/mbox/"},{"id":29578,"url":"https://patchwork.plctlab.org/api/1.2/patches/29578/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221205080453.1352069-2-mengqinggang@loongson.cn/","msgid":"<20221205080453.1352069-2-mengqinggang@loongson.cn>","list_archive_url":null,"date":"2022-12-05T08:04:48","name":"[v1,1/6] LoongArch: include: Add support for linker relaxation.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221205080453.1352069-2-mengqinggang@loongson.cn/mbox/"},{"id":29585,"url":"https://patchwork.plctlab.org/api/1.2/patches/29585/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221205080453.1352069-3-mengqinggang@loongson.cn/","msgid":"<20221205080453.1352069-3-mengqinggang@loongson.cn>","list_archive_url":null,"date":"2022-12-05T08:04:49","name":"[v1,2/6] LoongArch: bfd: Add support for linker relaxation.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221205080453.1352069-3-mengqinggang@loongson.cn/mbox/"},{"id":29577,"url":"https://patchwork.plctlab.org/api/1.2/patches/29577/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221205080453.1352069-4-mengqinggang@loongson.cn/","msgid":"<20221205080453.1352069-4-mengqinggang@loongson.cn>","list_archive_url":null,"date":"2022-12-05T08:04:50","name":"[v1,3/6] LoongArch: opcodes: Add support for linker relaxation.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221205080453.1352069-4-mengqinggang@loongson.cn/mbox/"},{"id":29580,"url":"https://patchwork.plctlab.org/api/1.2/patches/29580/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221205080453.1352069-5-mengqinggang@loongson.cn/","msgid":"<20221205080453.1352069-5-mengqinggang@loongson.cn>","list_archive_url":null,"date":"2022-12-05T08:04:51","name":"[v1,4/6] LoongArch: binutils: Add support for linker relaxation.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221205080453.1352069-5-mengqinggang@loongson.cn/mbox/"},{"id":29581,"url":"https://patchwork.plctlab.org/api/1.2/patches/29581/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221205080453.1352069-6-mengqinggang@loongson.cn/","msgid":"<20221205080453.1352069-6-mengqinggang@loongson.cn>","list_archive_url":null,"date":"2022-12-05T08:04:52","name":"[v1,5/6] LoongArch: gas: Add support for linker relaxation.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221205080453.1352069-6-mengqinggang@loongson.cn/mbox/"},{"id":29587,"url":"https://patchwork.plctlab.org/api/1.2/patches/29587/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221205080453.1352069-7-mengqinggang@loongson.cn/","msgid":"<20221205080453.1352069-7-mengqinggang@loongson.cn>","list_archive_url":null,"date":"2022-12-05T08:04:53","name":"[v1,6/6] LoongArch: ld: Add support for linker relaxation.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221205080453.1352069-7-mengqinggang@loongson.cn/mbox/"},{"id":29662,"url":"https://patchwork.plctlab.org/api/1.2/patches/29662/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/76253e84-a7c3-5d09-c6a7-422573ca2d37@suse.cz/","msgid":"<76253e84-a7c3-5d09-c6a7-422573ca2d37@suse.cz>","list_archive_url":null,"date":"2022-12-05T12:10:10","name":"testsuite: support mold linker","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/76253e84-a7c3-5d09-c6a7-422573ca2d37@suse.cz/mbox/"},{"id":29689,"url":"https://patchwork.plctlab.org/api/1.2/patches/29689/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e41a37eb-20ae-b5ef-9ab3-6e38682bfbd3@suse.cz/","msgid":"","list_archive_url":null,"date":"2022-12-05T13:48:16","name":"[V2] testsuite: support mold linker","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e41a37eb-20ae-b5ef-9ab3-6e38682bfbd3@suse.cz/mbox/"},{"id":29700,"url":"https://patchwork.plctlab.org/api/1.2/patches/29700/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2eb01f7a-2430-b0bc-9c58-d15d06ca6bf9@suse.cz/","msgid":"<2eb01f7a-2430-b0bc-9c58-d15d06ca6bf9@suse.cz>","list_archive_url":null,"date":"2022-12-05T14:41:04","name":"[V3] testsuite: support mold linker","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2eb01f7a-2430-b0bc-9c58-d15d06ca6bf9@suse.cz/mbox/"},{"id":30027,"url":"https://patchwork.plctlab.org/api/1.2/patches/30027/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y46GBCcdb5NKqOgS@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-12-06T00:00:04","name":"PR29855, ch_type in bfd_init_section_decompress_status can be uninitialized","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y46GBCcdb5NKqOgS@squeak.grove.modra.org/mbox/"},{"id":30082,"url":"https://patchwork.plctlab.org/api/1.2/patches/30082/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y47NCokv10HcVEpf@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-12-06T05:03:06","name":"Compression header enum","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y47NCokv10HcVEpf@squeak.grove.modra.org/mbox/"},{"id":30083,"url":"https://patchwork.plctlab.org/api/1.2/patches/30083/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y47NPN4wWWRZyL00@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-12-06T05:03:56","name":"Get rid of SEC_ELF_RENAME","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y47NPN4wWWRZyL00@squeak.grove.modra.org/mbox/"},{"id":30084,"url":"https://patchwork.plctlab.org/api/1.2/patches/30084/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y47NWJ/QfmCo4NNo@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-12-06T05:04:24","name":"Get rid of SEC_ELF_COMPRESS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y47NWJ/QfmCo4NNo@squeak.grove.modra.org/mbox/"},{"id":30085,"url":"https://patchwork.plctlab.org/api/1.2/patches/30085/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221206053947.821648-1-zengxiao@eswincomputing.com/","msgid":"<20221206053947.821648-1-zengxiao@eswincomputing.com>","list_archive_url":null,"date":"2022-12-06T05:39:47","name":"RISC-V: Correction of machine registers mapping to dwarf registers","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221206053947.821648-1-zengxiao@eswincomputing.com/mbox/"},{"id":30511,"url":"https://patchwork.plctlab.org/api/1.2/patches/30511/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221206211044.766653-1-hjl.tools@gmail.com/","msgid":"<20221206211044.766653-1-hjl.tools@gmail.com>","list_archive_url":null,"date":"2022-12-06T21:10:44","name":"x86-64: Remove BND from 64-bit IBT PLT","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221206211044.766653-1-hjl.tools@gmail.com/mbox/"},{"id":30519,"url":"https://patchwork.plctlab.org/api/1.2/patches/30519/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221206214444.799449-1-hjl.tools@gmail.com/","msgid":"<20221206214444.799449-1-hjl.tools@gmail.com>","list_archive_url":null,"date":"2022-12-06T21:44:44","name":"gold: Remove BND from 64-bit x86-64 IBT PLT","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221206214444.799449-1-hjl.tools@gmail.com/mbox/"},{"id":30606,"url":"https://patchwork.plctlab.org/api/1.2/patches/30606/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y4/+I/FAq0yyNLGs@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-12-07T02:44:51","name":"Compression tidy and fixes","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y4/+I/FAq0yyNLGs@squeak.grove.modra.org/mbox/"},{"id":30613,"url":"https://patchwork.plctlab.org/api/1.2/patches/30613/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y5ANBOjjh0d9TEW4@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-12-07T03:48:20","name":"bfd_compress_section_contents access to elf_section_data","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y5ANBOjjh0d9TEW4@squeak.grove.modra.org/mbox/"},{"id":30615,"url":"https://patchwork.plctlab.org/api/1.2/patches/30615/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y5AOFp9g+oujWvPw@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-12-07T03:52:54","name":"_bfd_elf_slurp_secondary_reloc_section sanity check","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y5AOFp9g+oujWvPw@squeak.grove.modra.org/mbox/"},{"id":30641,"url":"https://patchwork.plctlab.org/api/1.2/patches/30641/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y5ArCeLOXPteRDFk@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-12-07T05:56:25","name":"gas compress_debug tidy","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y5ArCeLOXPteRDFk@squeak.grove.modra.org/mbox/"},{"id":30643,"url":"https://patchwork.plctlab.org/api/1.2/patches/30643/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y5ArREIxkCA2Eoqb@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-12-07T05:57:24","name":"coff make_a_section_from_file tidy","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y5ArREIxkCA2Eoqb@squeak.grove.modra.org/mbox/"},{"id":30845,"url":"https://patchwork.plctlab.org/api/1.2/patches/30845/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221207133155.3052074-2-i.swmail@xen0n.name/","msgid":"<20221207133155.3052074-2-i.swmail@xen0n.name>","list_archive_url":null,"date":"2022-12-07T13:31:51","name":"[v2,1/5] opcodes/loongarch: remove unused code","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221207133155.3052074-2-i.swmail@xen0n.name/mbox/"},{"id":30847,"url":"https://patchwork.plctlab.org/api/1.2/patches/30847/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221207133155.3052074-3-i.swmail@xen0n.name/","msgid":"<20221207133155.3052074-3-i.swmail@xen0n.name>","list_archive_url":null,"date":"2022-12-07T13:31:52","name":"[v2,2/5] opcodes/loongarch: implement style support in the disassembler","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221207133155.3052074-3-i.swmail@xen0n.name/mbox/"},{"id":30848,"url":"https://patchwork.plctlab.org/api/1.2/patches/30848/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221207133155.3052074-4-i.swmail@xen0n.name/","msgid":"<20221207133155.3052074-4-i.swmail@xen0n.name>","list_archive_url":null,"date":"2022-12-07T13:31:53","name":"[v2,3/5] opcodes/loongarch: style disassembled address offsets as such","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221207133155.3052074-4-i.swmail@xen0n.name/mbox/"},{"id":30849,"url":"https://patchwork.plctlab.org/api/1.2/patches/30849/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221207133155.3052074-5-i.swmail@xen0n.name/","msgid":"<20221207133155.3052074-5-i.swmail@xen0n.name>","list_archive_url":null,"date":"2022-12-07T13:31:54","name":"[v2,4/5] opcodes/loongarch: do not print hex notation for signed immediates","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221207133155.3052074-5-i.swmail@xen0n.name/mbox/"},{"id":30846,"url":"https://patchwork.plctlab.org/api/1.2/patches/30846/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221207133155.3052074-6-i.swmail@xen0n.name/","msgid":"<20221207133155.3052074-6-i.swmail@xen0n.name>","list_archive_url":null,"date":"2022-12-07T13:31:55","name":"[v2,5/5] opcodes/loongarch: print unrecognized instruction words with .insn prefix","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221207133155.3052074-6-i.swmail@xen0n.name/mbox/"},{"id":30875,"url":"https://patchwork.plctlab.org/api/1.2/patches/30875/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221207141137.1527113-1-felix.willgerodt@intel.com/","msgid":"<20221207141137.1527113-1-felix.willgerodt@intel.com>","list_archive_url":null,"date":"2022-12-07T14:11:37","name":"[1/1] libctf: Fix double free in ctf_link_add_cu_mapping.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221207141137.1527113-1-felix.willgerodt@intel.com/mbox/"},{"id":30967,"url":"https://patchwork.plctlab.org/api/1.2/patches/30967/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9e57c8dc-481b-82d3-7bba-8e7bd9426a1f@linux.ibm.com/","msgid":"<9e57c8dc-481b-82d3-7bba-8e7bd9426a1f@linux.ibm.com>","list_archive_url":null,"date":"2022-12-07T17:59:19","name":"[COMMITTED] PowerPC: Add support for RFC02656 - Enhanced Load Store, with Length Instructions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9e57c8dc-481b-82d3-7bba-8e7bd9426a1f@linux.ibm.com/mbox/"},{"id":30973,"url":"https://patchwork.plctlab.org/api/1.2/patches/30973/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a1b16cc6-6e73-7d5f-ff38-564b0978243b@linux.ibm.com/","msgid":"","list_archive_url":null,"date":"2022-12-07T18:08:00","name":"[COMMITTED] PowerPC: Add support for RFC02655 - Saturating Subtract Instruction","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a1b16cc6-6e73-7d5f-ff38-564b0978243b@linux.ibm.com/mbox/"},{"id":31010,"url":"https://patchwork.plctlab.org/api/1.2/patches/31010/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221207195222.1182788-2-indu.bhagat@oracle.com/","msgid":"<20221207195222.1182788-2-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-12-07T19:52:17","name":"[1/6] libsframe: minor formatting nits","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221207195222.1182788-2-indu.bhagat@oracle.com/mbox/"},{"id":31011,"url":"https://patchwork.plctlab.org/api/1.2/patches/31011/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221207195222.1182788-3-indu.bhagat@oracle.com/","msgid":"<20221207195222.1182788-3-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-12-07T19:52:18","name":"[2/6] sframe.h: make some macros more precise","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221207195222.1182788-3-indu.bhagat@oracle.com/mbox/"},{"id":31013,"url":"https://patchwork.plctlab.org/api/1.2/patches/31013/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221207195222.1182788-4-indu.bhagat@oracle.com/","msgid":"<20221207195222.1182788-4-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-12-07T19:52:19","name":"[3/6] sframe: gas: libsframe: define constants and remove magic numbers","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221207195222.1182788-4-indu.bhagat@oracle.com/mbox/"},{"id":31012,"url":"https://patchwork.plctlab.org/api/1.2/patches/31012/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221207195222.1182788-5-indu.bhagat@oracle.com/","msgid":"<20221207195222.1182788-5-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-12-07T19:52:20","name":"[4/6] gas: sframe: fine tune the fragment fixup for SFrame func info","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221207195222.1182788-5-indu.bhagat@oracle.com/mbox/"},{"id":31014,"url":"https://patchwork.plctlab.org/api/1.2/patches/31014/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221207195222.1182788-6-indu.bhagat@oracle.com/","msgid":"<20221207195222.1182788-6-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-12-07T19:52:21","name":"[5/6] libsframe: rename API sframe_fde_func_info to sframe_fde_create_func_info","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221207195222.1182788-6-indu.bhagat@oracle.com/mbox/"},{"id":31015,"url":"https://patchwork.plctlab.org/api/1.2/patches/31015/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221207195222.1182788-7-indu.bhagat@oracle.com/","msgid":"<20221207195222.1182788-7-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-12-07T19:52:22","name":"[6/6] objdump: sframe: fix memory leaks","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221207195222.1182788-7-indu.bhagat@oracle.com/mbox/"},{"id":31198,"url":"https://patchwork.plctlab.org/api/1.2/patches/31198/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/aa0c1392-c3e1-53c4-45ce-4cee9af3b243@suse.cz/","msgid":"","list_archive_url":null,"date":"2022-12-08T08:21:54","name":"ld, gold: remove support for -z bndplt (MPX prefix)","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/aa0c1392-c3e1-53c4-45ce-4cee9af3b243@suse.cz/mbox/"},{"id":31490,"url":"https://patchwork.plctlab.org/api/1.2/patches/31490/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221208202649.2852852-1-indu.bhagat@oracle.com/","msgid":"<20221208202649.2852852-1-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-12-08T20:26:49","name":"[V2,2/6] sframe.h: make some macros more precise","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221208202649.2852852-1-indu.bhagat@oracle.com/mbox/"},{"id":31571,"url":"https://patchwork.plctlab.org/api/1.2/patches/31571/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221209015240.6348-1-mark@harmstone.com/","msgid":"<20221209015240.6348-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-12-09T01:52:31","name":"[01/10] ld: Generate PDB string table","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221209015240.6348-1-mark@harmstone.com/mbox/"},{"id":31572,"url":"https://patchwork.plctlab.org/api/1.2/patches/31572/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221209015240.6348-2-mark@harmstone.com/","msgid":"<20221209015240.6348-2-mark@harmstone.com>","list_archive_url":null,"date":"2022-12-09T01:52:32","name":"[02/10] ld: Write DEBUG_S_FILECHKSMS entries in PDBs","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221209015240.6348-2-mark@harmstone.com/mbox/"},{"id":31570,"url":"https://patchwork.plctlab.org/api/1.2/patches/31570/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221209015240.6348-3-mark@harmstone.com/","msgid":"<20221209015240.6348-3-mark@harmstone.com>","list_archive_url":null,"date":"2022-12-09T01:52:33","name":"[03/10] ld: Fix segfault in populate_publics_stream","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221209015240.6348-3-mark@harmstone.com/mbox/"},{"id":31573,"url":"https://patchwork.plctlab.org/api/1.2/patches/31573/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221209015240.6348-4-mark@harmstone.com/","msgid":"<20221209015240.6348-4-mark@harmstone.com>","list_archive_url":null,"date":"2022-12-09T01:52:34","name":"[04/10] ld: Write DEBUG_S_LINES entries in PDB file","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221209015240.6348-4-mark@harmstone.com/mbox/"},{"id":31584,"url":"https://patchwork.plctlab.org/api/1.2/patches/31584/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221209015240.6348-5-mark@harmstone.com/","msgid":"<20221209015240.6348-5-mark@harmstone.com>","list_archive_url":null,"date":"2022-12-09T01:52:35","name":"[05/10] ld: Write types into TPI stream of PDB","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221209015240.6348-5-mark@harmstone.com/mbox/"},{"id":31580,"url":"https://patchwork.plctlab.org/api/1.2/patches/31580/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221209015240.6348-6-mark@harmstone.com/","msgid":"<20221209015240.6348-6-mark@harmstone.com>","list_archive_url":null,"date":"2022-12-09T01:52:36","name":"[06/10] ld: Write types into IPI stream of PDB","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221209015240.6348-6-mark@harmstone.com/mbox/"},{"id":31579,"url":"https://patchwork.plctlab.org/api/1.2/patches/31579/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221209015240.6348-7-mark@harmstone.com/","msgid":"<20221209015240.6348-7-mark@harmstone.com>","list_archive_url":null,"date":"2022-12-09T01:52:37","name":"[07/10] ld: Parse LF_UDT_SRC_LINE records when creating PDB file","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221209015240.6348-7-mark@harmstone.com/mbox/"},{"id":31591,"url":"https://patchwork.plctlab.org/api/1.2/patches/31591/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221209015240.6348-8-mark@harmstone.com/","msgid":"<20221209015240.6348-8-mark@harmstone.com>","list_archive_url":null,"date":"2022-12-09T01:52:38","name":"[08/10] ld: Write globals stream in PDB","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221209015240.6348-8-mark@harmstone.com/mbox/"},{"id":31582,"url":"https://patchwork.plctlab.org/api/1.2/patches/31582/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221209015240.6348-9-mark@harmstone.com/","msgid":"<20221209015240.6348-9-mark@harmstone.com>","list_archive_url":null,"date":"2022-12-09T01:52:39","name":"[09/10] ld: Copy other symbols into PDB file","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221209015240.6348-9-mark@harmstone.com/mbox/"},{"id":31592,"url":"https://patchwork.plctlab.org/api/1.2/patches/31592/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221209015240.6348-10-mark@harmstone.com/","msgid":"<20221209015240.6348-10-mark@harmstone.com>","list_archive_url":null,"date":"2022-12-09T01:52:40","name":"[10/10] ld: Write linker symbols in PDB","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221209015240.6348-10-mark@harmstone.com/mbox/"},{"id":31705,"url":"https://patchwork.plctlab.org/api/1.2/patches/31705/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221209095719.193008-1-i.swmail@xen0n.name/","msgid":"<20221209095719.193008-1-i.swmail@xen0n.name>","list_archive_url":null,"date":"2022-12-09T09:57:19","name":"LoongArch: support disassembling certain pseudo-instructions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221209095719.193008-1-i.swmail@xen0n.name/mbox/"},{"id":31717,"url":"https://patchwork.plctlab.org/api/1.2/patches/31717/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b291b099-c0f2-e206-4296-1fcf040c32b1@suse.com/","msgid":"","list_archive_url":null,"date":"2022-12-09T10:49:20","name":"[v2,1/2] Arm: avoid unhelpful uses of .macro in testsuite","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b291b099-c0f2-e206-4296-1fcf040c32b1@suse.com/mbox/"},{"id":31720,"url":"https://patchwork.plctlab.org/api/1.2/patches/31720/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8eff1de6-871d-24cc-8804-9af7da0a86cf@suse.com/","msgid":"<8eff1de6-871d-24cc-8804-9af7da0a86cf@suse.com>","list_archive_url":null,"date":"2022-12-09T10:52:06","name":"[v2,2/2] gas: re-work line number tracking for macros and their expansions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8eff1de6-871d-24cc-8804-9af7da0a86cf@suse.com/mbox/"},{"id":31724,"url":"https://patchwork.plctlab.org/api/1.2/patches/31724/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y5MXFFPorfWbzTDZ@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-12-09T11:08:04","name":"PR28306, segfault in _bfd_mips_elf_reloc_unshuffle","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y5MXFFPorfWbzTDZ@squeak.grove.modra.org/mbox/"},{"id":31924,"url":"https://patchwork.plctlab.org/api/1.2/patches/31924/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221209202118.4106688-2-indu.bhagat@oracle.com/","msgid":"<20221209202118.4106688-2-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-12-09T20:21:17","name":"[1/2] libctf: remove unnecessary zlib constructs","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221209202118.4106688-2-indu.bhagat@oracle.com/mbox/"},{"id":31925,"url":"https://patchwork.plctlab.org/api/1.2/patches/31925/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221209202118.4106688-3-indu.bhagat@oracle.com/","msgid":"<20221209202118.4106688-3-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-12-09T20:21:18","name":"[2/2] libctf: remove AC_CONFIG_MACRO_DIR","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221209202118.4106688-3-indu.bhagat@oracle.com/mbox/"},{"id":32115,"url":"https://patchwork.plctlab.org/api/1.2/patches/32115/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221211001022.564137-2-indu.bhagat@oracle.com/","msgid":"<20221211001022.564137-2-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-12-11T00:10:21","name":"[V2,1/2] libctf: remove unnecessary zlib constructs","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221211001022.564137-2-indu.bhagat@oracle.com/mbox/"},{"id":32114,"url":"https://patchwork.plctlab.org/api/1.2/patches/32114/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221211001022.564137-3-indu.bhagat@oracle.com/","msgid":"<20221211001022.564137-3-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-12-11T00:10:22","name":"[V2,2/2] libctf: remove AC_CONFIG_MACRO_DIR","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221211001022.564137-3-indu.bhagat@oracle.com/mbox/"},{"id":32116,"url":"https://patchwork.plctlab.org/api/1.2/patches/32116/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221211002622.564875-1-indu.bhagat@oracle.com/","msgid":"<20221211002622.564875-1-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-12-11T00:26:22","name":"libctf: remove unnecessary zstd constructs","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221211002622.564875-1-indu.bhagat@oracle.com/mbox/"},{"id":32188,"url":"https://patchwork.plctlab.org/api/1.2/patches/32188/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y5XZZileMxvCEgnH@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-12-11T13:21:42","name":"PR29870, objdump SEGV in display_debug_lines_decoded dwarf.c:5524","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y5XZZileMxvCEgnH@squeak.grove.modra.org/mbox/"},{"id":32268,"url":"https://patchwork.plctlab.org/api/1.2/patches/32268/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y5btF1SICJIaR6s4@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-12-12T08:57:59","name":"PR29872, uninitialised value in display_debug_lines_decoded dwarf.c:5413","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y5btF1SICJIaR6s4@squeak.grove.modra.org/mbox/"},{"id":32269,"url":"https://patchwork.plctlab.org/api/1.2/patches/32269/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y5btNpE+vZlCyuFQ@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-12-12T08:58:30","name":"Lack of bounds checking in vms-alpha.c parse_module","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y5btNpE+vZlCyuFQ@squeak.grove.modra.org/mbox/"},{"id":32270,"url":"https://patchwork.plctlab.org/api/1.2/patches/32270/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y5btWGqMk2HBW0DG@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-12-12T08:59:04","name":"PR29892, Field file_table of struct module is uninitialized","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y5btWGqMk2HBW0DG@squeak.grove.modra.org/mbox/"},{"id":32366,"url":"https://patchwork.plctlab.org/api/1.2/patches/32366/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4a972040-5bdf-4c00-47db-7e26e603ff47@suse.com/","msgid":"<4a972040-5bdf-4c00-47db-7e26e603ff47@suse.com>","list_archive_url":null,"date":"2022-12-12T12:42:31","name":"x86: revert disassembler parts of \"x86: Allow 16-bit register source for LAR and LSL\"","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4a972040-5bdf-4c00-47db-7e26e603ff47@suse.com/mbox/"},{"id":32384,"url":"https://patchwork.plctlab.org/api/1.2/patches/32384/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2e6ab22e-9141-7209-5dcd-f10f2e20b0f0@suse.com/","msgid":"<2e6ab22e-9141-7209-5dcd-f10f2e20b0f0@suse.com>","list_archive_url":null,"date":"2022-12-12T13:12:43","name":"[1/2] x86: change representation of extension opcode","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2e6ab22e-9141-7209-5dcd-f10f2e20b0f0@suse.com/mbox/"},{"id":32387,"url":"https://patchwork.plctlab.org/api/1.2/patches/32387/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/90f8b494-64b2-fd9a-6b19-ded5f185ddd1@suse.com/","msgid":"<90f8b494-64b2-fd9a-6b19-ded5f185ddd1@suse.com>","list_archive_url":null,"date":"2022-12-12T13:14:13","name":"[2/2] x86: omit Cpu prefixes from opcode table","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/90f8b494-64b2-fd9a-6b19-ded5f185ddd1@suse.com/mbox/"},{"id":32407,"url":"https://patchwork.plctlab.org/api/1.2/patches/32407/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y5c2J0s2fgqvL61d@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-12-12T14:09:43","name":"PR29893, buffer overflow in display_debug_addr","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y5c2J0s2fgqvL61d@squeak.grove.modra.org/mbox/"},{"id":32596,"url":"https://patchwork.plctlab.org/api/1.2/patches/32596/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y5fj/uw/pAKASueh@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-12-13T02:31:26","name":"asan: mips_hi16_list segfault in bfd_get_section_limit_octets","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y5fj/uw/pAKASueh@squeak.grove.modra.org/mbox/"},{"id":32623,"url":"https://patchwork.plctlab.org/api/1.2/patches/32623/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221213043428.33155-1-xuli1@eswincomputing.com/","msgid":"<20221213043428.33155-1-xuli1@eswincomputing.com>","list_archive_url":null,"date":"2022-12-13T04:34:28","name":"RISC-V: Add string length check for operands in AS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221213043428.33155-1-xuli1@eswincomputing.com/mbox/"},{"id":32656,"url":"https://patchwork.plctlab.org/api/1.2/patches/32656/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221213065851.2777297-2-mengqinggang@loongson.cn/","msgid":"<20221213065851.2777297-2-mengqinggang@loongson.cn>","list_archive_url":null,"date":"2022-12-13T06:58:46","name":"[v2,1/6] LoongArch: include: Add support for linker relaxation.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221213065851.2777297-2-mengqinggang@loongson.cn/mbox/"},{"id":32660,"url":"https://patchwork.plctlab.org/api/1.2/patches/32660/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221213065851.2777297-3-mengqinggang@loongson.cn/","msgid":"<20221213065851.2777297-3-mengqinggang@loongson.cn>","list_archive_url":null,"date":"2022-12-13T06:58:47","name":"[v2,2/6] LoongArch: bfd: Add support for linker relaxation.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221213065851.2777297-3-mengqinggang@loongson.cn/mbox/"},{"id":32657,"url":"https://patchwork.plctlab.org/api/1.2/patches/32657/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221213065851.2777297-4-mengqinggang@loongson.cn/","msgid":"<20221213065851.2777297-4-mengqinggang@loongson.cn>","list_archive_url":null,"date":"2022-12-13T06:58:48","name":"[v2,3/6] LoongArch: opcodes: Add support for linker relaxation.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221213065851.2777297-4-mengqinggang@loongson.cn/mbox/"},{"id":32661,"url":"https://patchwork.plctlab.org/api/1.2/patches/32661/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221213065851.2777297-5-mengqinggang@loongson.cn/","msgid":"<20221213065851.2777297-5-mengqinggang@loongson.cn>","list_archive_url":null,"date":"2022-12-13T06:58:49","name":"[v2,4/6] LoongArch: binutils: Add support for linker relaxation.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221213065851.2777297-5-mengqinggang@loongson.cn/mbox/"},{"id":32659,"url":"https://patchwork.plctlab.org/api/1.2/patches/32659/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221213065851.2777297-6-mengqinggang@loongson.cn/","msgid":"<20221213065851.2777297-6-mengqinggang@loongson.cn>","list_archive_url":null,"date":"2022-12-13T06:58:50","name":"[v2,5/6] LoongArch: gas: Add support for linker relaxation.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221213065851.2777297-6-mengqinggang@loongson.cn/mbox/"},{"id":32658,"url":"https://patchwork.plctlab.org/api/1.2/patches/32658/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221213065851.2777297-7-mengqinggang@loongson.cn/","msgid":"<20221213065851.2777297-7-mengqinggang@loongson.cn>","list_archive_url":null,"date":"2022-12-13T06:58:51","name":"[v2,6/6] LoongArch: ld: Add support for linker relaxation.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221213065851.2777297-7-mengqinggang@loongson.cn/mbox/"},{"id":32855,"url":"https://patchwork.plctlab.org/api/1.2/patches/32855/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0adeda5c-0696-d3bf-499a-fd63e3a4f709@suse.com/","msgid":"<0adeda5c-0696-d3bf-499a-fd63e3a4f709@suse.com>","list_archive_url":null,"date":"2022-12-13T15:31:27","name":"Arm: break gas dependency on libopcodes","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0adeda5c-0696-d3bf-499a-fd63e3a4f709@suse.com/mbox/"},{"id":33035,"url":"https://patchwork.plctlab.org/api/1.2/patches/33035/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y5lEcMxUdytmdyC6@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-12-14T03:35:12","name":"Don'\''t access freed memory printing objcopy warning","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y5lEcMxUdytmdyC6@squeak.grove.modra.org/mbox/"},{"id":33036,"url":"https://patchwork.plctlab.org/api/1.2/patches/33036/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y5lEjrLPqV3l35Qf@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-12-14T03:35:42","name":"asan: signed integer overflow in display_debug_frames","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y5lEjrLPqV3l35Qf@squeak.grove.modra.org/mbox/"},{"id":33054,"url":"https://patchwork.plctlab.org/api/1.2/patches/33054/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221214054700.2889049-2-i.swmail@xen0n.name/","msgid":"<20221214054700.2889049-2-i.swmail@xen0n.name>","list_archive_url":null,"date":"2022-12-14T05:46:55","name":"[v3,1/6] LoongArch: support disassembling certain pseudo-instructions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221214054700.2889049-2-i.swmail@xen0n.name/mbox/"},{"id":33055,"url":"https://patchwork.plctlab.org/api/1.2/patches/33055/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221214054700.2889049-3-i.swmail@xen0n.name/","msgid":"<20221214054700.2889049-3-i.swmail@xen0n.name>","list_archive_url":null,"date":"2022-12-14T05:46:56","name":"[v3,2/6] opcodes/loongarch: remove unused code","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221214054700.2889049-3-i.swmail@xen0n.name/mbox/"},{"id":33057,"url":"https://patchwork.plctlab.org/api/1.2/patches/33057/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221214054700.2889049-4-i.swmail@xen0n.name/","msgid":"<20221214054700.2889049-4-i.swmail@xen0n.name>","list_archive_url":null,"date":"2022-12-14T05:46:57","name":"[v3,3/6] opcodes/loongarch: implement style support in the disassembler","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221214054700.2889049-4-i.swmail@xen0n.name/mbox/"},{"id":33058,"url":"https://patchwork.plctlab.org/api/1.2/patches/33058/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221214054700.2889049-5-i.swmail@xen0n.name/","msgid":"<20221214054700.2889049-5-i.swmail@xen0n.name>","list_archive_url":null,"date":"2022-12-14T05:46:58","name":"[v3,4/6] opcodes/loongarch: style disassembled address offsets as such","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221214054700.2889049-5-i.swmail@xen0n.name/mbox/"},{"id":33059,"url":"https://patchwork.plctlab.org/api/1.2/patches/33059/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221214054700.2889049-6-i.swmail@xen0n.name/","msgid":"<20221214054700.2889049-6-i.swmail@xen0n.name>","list_archive_url":null,"date":"2022-12-14T05:46:59","name":"[v3,5/6] opcodes/loongarch: do not print hex notation for signed immediates","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221214054700.2889049-6-i.swmail@xen0n.name/mbox/"},{"id":33056,"url":"https://patchwork.plctlab.org/api/1.2/patches/33056/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221214054700.2889049-7-i.swmail@xen0n.name/","msgid":"<20221214054700.2889049-7-i.swmail@xen0n.name>","list_archive_url":null,"date":"2022-12-14T05:47:00","name":"[v3,6/6] opcodes/loongarch: print unrecognized insn words with the .word directive","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221214054700.2889049-7-i.swmail@xen0n.name/mbox/"},{"id":33061,"url":"https://patchwork.plctlab.org/api/1.2/patches/33061/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221214055204.2890795-2-i.swmail@xen0n.name/","msgid":"<20221214055204.2890795-2-i.swmail@xen0n.name>","list_archive_url":null,"date":"2022-12-14T05:51:59","name":"[v3,1/6] LoongArch: support disassembling certain pseudo-instructions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221214055204.2890795-2-i.swmail@xen0n.name/mbox/"},{"id":33062,"url":"https://patchwork.plctlab.org/api/1.2/patches/33062/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221214055204.2890795-3-i.swmail@xen0n.name/","msgid":"<20221214055204.2890795-3-i.swmail@xen0n.name>","list_archive_url":null,"date":"2022-12-14T05:52:00","name":"[v3,2/6] opcodes/loongarch: remove unused code","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221214055204.2890795-3-i.swmail@xen0n.name/mbox/"},{"id":33060,"url":"https://patchwork.plctlab.org/api/1.2/patches/33060/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221214055204.2890795-4-i.swmail@xen0n.name/","msgid":"<20221214055204.2890795-4-i.swmail@xen0n.name>","list_archive_url":null,"date":"2022-12-14T05:52:01","name":"[v3,3/6] opcodes/loongarch: implement style support in the disassembler","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221214055204.2890795-4-i.swmail@xen0n.name/mbox/"},{"id":33063,"url":"https://patchwork.plctlab.org/api/1.2/patches/33063/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221214055204.2890795-5-i.swmail@xen0n.name/","msgid":"<20221214055204.2890795-5-i.swmail@xen0n.name>","list_archive_url":null,"date":"2022-12-14T05:52:02","name":"[v3,4/6] opcodes/loongarch: style disassembled address offsets as such","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221214055204.2890795-5-i.swmail@xen0n.name/mbox/"},{"id":33065,"url":"https://patchwork.plctlab.org/api/1.2/patches/33065/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221214055204.2890795-6-i.swmail@xen0n.name/","msgid":"<20221214055204.2890795-6-i.swmail@xen0n.name>","list_archive_url":null,"date":"2022-12-14T05:52:03","name":"[v3,5/6] opcodes/loongarch: do not print hex notation for signed immediates","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221214055204.2890795-6-i.swmail@xen0n.name/mbox/"},{"id":33064,"url":"https://patchwork.plctlab.org/api/1.2/patches/33064/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221214055204.2890795-7-i.swmail@xen0n.name/","msgid":"<20221214055204.2890795-7-i.swmail@xen0n.name>","list_archive_url":null,"date":"2022-12-14T05:52:04","name":"[v3,6/6] opcodes/loongarch: print unrecognized insn words with the .word directive","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221214055204.2890795-7-i.swmail@xen0n.name/mbox/"},{"id":33086,"url":"https://patchwork.plctlab.org/api/1.2/patches/33086/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221214073240.24973-1-xuli1@eswincomputing.com/","msgid":"<20221214073240.24973-1-xuli1@eswincomputing.com>","list_archive_url":null,"date":"2022-12-14T07:32:40","name":"[v2] RISC-V: Add string length check for operands in AS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221214073240.24973-1-xuli1@eswincomputing.com/mbox/"},{"id":33111,"url":"https://patchwork.plctlab.org/api/1.2/patches/33111/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/af826d86-8600-6a8b-f696-0b26c7774d45@suse.com/","msgid":"","list_archive_url":null,"date":"2022-12-14T09:07:07","name":"x86: adjust type checking constructs","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/af826d86-8600-6a8b-f696-0b26c7774d45@suse.com/mbox/"},{"id":33164,"url":"https://patchwork.plctlab.org/api/1.2/patches/33164/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y5m2zCJFXs1Ywa+M@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-12-14T11:43:08","name":"Fix haiku ld dependencies","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y5m2zCJFXs1Ywa+M@squeak.grove.modra.org/mbox/"},{"id":33165,"url":"https://patchwork.plctlab.org/api/1.2/patches/33165/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y5m285CXyYl9DPU6@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-12-14T11:43:47","name":"asan: buffer overflow in sh_reloc","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y5m285CXyYl9DPU6@squeak.grove.modra.org/mbox/"},{"id":33304,"url":"https://patchwork.plctlab.org/api/1.2/patches/33304/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221214195859.1233809-2-indu.bhagat@oracle.com/","msgid":"<20221214195859.1233809-2-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-12-14T19:58:54","name":"[1/6,1/6] sframe.h: add support for .cfi_negate_ra_state","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221214195859.1233809-2-indu.bhagat@oracle.com/mbox/"},{"id":33298,"url":"https://patchwork.plctlab.org/api/1.2/patches/33298/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221214195859.1233809-3-indu.bhagat@oracle.com/","msgid":"<20221214195859.1233809-3-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-12-14T19:58:55","name":"[2/6,2/6] gas: sframe: add support for .cfi_negate_ra_state","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221214195859.1233809-3-indu.bhagat@oracle.com/mbox/"},{"id":33299,"url":"https://patchwork.plctlab.org/api/1.2/patches/33299/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221214195859.1233809-4-indu.bhagat@oracle.com/","msgid":"<20221214195859.1233809-4-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-12-14T19:58:56","name":"[3/6,3/6] gas: sframe: testsuite: add testcase for .cfi_negate_ra_state","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221214195859.1233809-4-indu.bhagat@oracle.com/mbox/"},{"id":33313,"url":"https://patchwork.plctlab.org/api/1.2/patches/33313/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221214195859.1233809-5-indu.bhagat@oracle.com/","msgid":"<20221214195859.1233809-5-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-12-14T19:58:57","name":"[4/6,4/6] libsframe: provide new access API for mangled RA bit","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221214195859.1233809-5-indu.bhagat@oracle.com/mbox/"},{"id":33300,"url":"https://patchwork.plctlab.org/api/1.2/patches/33300/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221214195859.1233809-6-indu.bhagat@oracle.com/","msgid":"<20221214195859.1233809-6-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-12-14T19:58:58","name":"[5/6,5/6] objdump/readelf: sframe: emit marker for FREs with mangled RA","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221214195859.1233809-6-indu.bhagat@oracle.com/mbox/"},{"id":33307,"url":"https://patchwork.plctlab.org/api/1.2/patches/33307/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221214195859.1233809-7-indu.bhagat@oracle.com/","msgid":"<20221214195859.1233809-7-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-12-14T19:58:59","name":"[6/6,6/6] sframe: doc: update spec for the mangled-RA bit in FRE","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221214195859.1233809-7-indu.bhagat@oracle.com/mbox/"},{"id":33329,"url":"https://patchwork.plctlab.org/api/1.2/patches/33329/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221214200756.1234528-2-indu.bhagat@oracle.com/","msgid":"<20221214200756.1234528-2-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-12-14T20:07:52","name":"[1/5,1/5] sframe.h: add support for .cfi_b_key_frame","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221214200756.1234528-2-indu.bhagat@oracle.com/mbox/"},{"id":33336,"url":"https://patchwork.plctlab.org/api/1.2/patches/33336/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221214200756.1234528-3-indu.bhagat@oracle.com/","msgid":"<20221214200756.1234528-3-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-12-14T20:07:53","name":"[2/5,2/5] gas: sframe: add support for .cfi_b_key_frame","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221214200756.1234528-3-indu.bhagat@oracle.com/mbox/"},{"id":33334,"url":"https://patchwork.plctlab.org/api/1.2/patches/33334/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221214200756.1234528-4-indu.bhagat@oracle.com/","msgid":"<20221214200756.1234528-4-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-12-14T20:07:54","name":"[3/5,3/5] objdump/readelf: sframe: emit marker for SFrame FDE with B key","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221214200756.1234528-4-indu.bhagat@oracle.com/mbox/"},{"id":33331,"url":"https://patchwork.plctlab.org/api/1.2/patches/33331/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221214200756.1234528-5-indu.bhagat@oracle.com/","msgid":"<20221214200756.1234528-5-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-12-14T20:07:55","name":"[4/5,4/5] gas: sframe: testsuite: add testcase for .cfi_b_key_frame","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221214200756.1234528-5-indu.bhagat@oracle.com/mbox/"},{"id":33337,"url":"https://patchwork.plctlab.org/api/1.2/patches/33337/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221214200756.1234528-6-indu.bhagat@oracle.com/","msgid":"<20221214200756.1234528-6-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-12-14T20:07:56","name":"[5/5,5/5] sframe: doc: update documentation for pauth key in SFrame FDE","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221214200756.1234528-6-indu.bhagat@oracle.com/mbox/"},{"id":33412,"url":"https://patchwork.plctlab.org/api/1.2/patches/33412/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221214234310.1247719-1-indu.bhagat@oracle.com/","msgid":"<20221214234310.1247719-1-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-12-14T23:43:10","name":"[PR,29856] libsframe: avoid generating misaligned loads","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221214234310.1247719-1-indu.bhagat@oracle.com/mbox/"},{"id":33669,"url":"https://patchwork.plctlab.org/api/1.2/patches/33669/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/15b35aca-4b74-63ff-b6e9-831879fa7cfa@suse.com/","msgid":"<15b35aca-4b74-63ff-b6e9-831879fa7cfa@suse.com>","list_archive_url":null,"date":"2022-12-15T15:14:57","name":"gas: restore Dwarf info generation after macro diagnostic adjustments","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/15b35aca-4b74-63ff-b6e9-831879fa7cfa@suse.com/mbox/"},{"id":33836,"url":"https://patchwork.plctlab.org/api/1.2/patches/33836/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221216021400.22309-1-mark@harmstone.com/","msgid":"<20221216021400.22309-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-12-16T02:13:56","name":"[1/5] Fix size of external_reloc for pe-aarch64","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221216021400.22309-1-mark@harmstone.com/mbox/"},{"id":33839,"url":"https://patchwork.plctlab.org/api/1.2/patches/33839/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221216021400.22309-2-mark@harmstone.com/","msgid":"<20221216021400.22309-2-mark@harmstone.com>","list_archive_url":null,"date":"2022-12-16T02:13:57","name":"[2/5] Skip ELF-specific tests when targeting pe-aarch64","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221216021400.22309-2-mark@harmstone.com/mbox/"},{"id":33840,"url":"https://patchwork.plctlab.org/api/1.2/patches/33840/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221216021400.22309-3-mark@harmstone.com/","msgid":"<20221216021400.22309-3-mark@harmstone.com>","list_archive_url":null,"date":"2022-12-16T02:13:58","name":"[3/5] Add pe-aarch64 relocations","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221216021400.22309-3-mark@harmstone.com/mbox/"},{"id":33837,"url":"https://patchwork.plctlab.org/api/1.2/patches/33837/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221216021400.22309-4-mark@harmstone.com/","msgid":"<20221216021400.22309-4-mark@harmstone.com>","list_archive_url":null,"date":"2022-12-16T02:13:59","name":"[4/5] Add .secrel32 for pe-aarch64","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221216021400.22309-4-mark@harmstone.com/mbox/"},{"id":33838,"url":"https://patchwork.plctlab.org/api/1.2/patches/33838/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221216021400.22309-5-mark@harmstone.com/","msgid":"<20221216021400.22309-5-mark@harmstone.com>","list_archive_url":null,"date":"2022-12-16T02:14:00","name":"[5/5] Add aarch64-w64-mingw32 target","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221216021400.22309-5-mark@harmstone.com/mbox/"},{"id":33885,"url":"https://patchwork.plctlab.org/api/1.2/patches/33885/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221216072336.1087469-2-mengqinggang@loongson.cn/","msgid":"<20221216072336.1087469-2-mengqinggang@loongson.cn>","list_archive_url":null,"date":"2022-12-16T07:23:31","name":"[v3,1/6] LoongArch: include: Add support for linker relaxation.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221216072336.1087469-2-mengqinggang@loongson.cn/mbox/"},{"id":33886,"url":"https://patchwork.plctlab.org/api/1.2/patches/33886/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221216072336.1087469-3-mengqinggang@loongson.cn/","msgid":"<20221216072336.1087469-3-mengqinggang@loongson.cn>","list_archive_url":null,"date":"2022-12-16T07:23:32","name":"[v3,2/6] LoongArch: bfd: Add support for linker relaxation.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221216072336.1087469-3-mengqinggang@loongson.cn/mbox/"},{"id":33888,"url":"https://patchwork.plctlab.org/api/1.2/patches/33888/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221216072336.1087469-4-mengqinggang@loongson.cn/","msgid":"<20221216072336.1087469-4-mengqinggang@loongson.cn>","list_archive_url":null,"date":"2022-12-16T07:23:33","name":"[v3,3/6] LoongArch: opcodes: Add support for linker relaxation.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221216072336.1087469-4-mengqinggang@loongson.cn/mbox/"},{"id":33889,"url":"https://patchwork.plctlab.org/api/1.2/patches/33889/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221216072336.1087469-5-mengqinggang@loongson.cn/","msgid":"<20221216072336.1087469-5-mengqinggang@loongson.cn>","list_archive_url":null,"date":"2022-12-16T07:23:34","name":"[v3,4/6] LoongArch: binutils: Add support for linker relaxation.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221216072336.1087469-5-mengqinggang@loongson.cn/mbox/"},{"id":33887,"url":"https://patchwork.plctlab.org/api/1.2/patches/33887/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221216072336.1087469-6-mengqinggang@loongson.cn/","msgid":"<20221216072336.1087469-6-mengqinggang@loongson.cn>","list_archive_url":null,"date":"2022-12-16T07:23:35","name":"[v3,5/6] LoongArch: gas: Add support for linker relaxation.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221216072336.1087469-6-mengqinggang@loongson.cn/mbox/"},{"id":33890,"url":"https://patchwork.plctlab.org/api/1.2/patches/33890/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221216072336.1087469-7-mengqinggang@loongson.cn/","msgid":"<20221216072336.1087469-7-mengqinggang@loongson.cn>","list_archive_url":null,"date":"2022-12-16T07:23:36","name":"[v3,6/6] LoongArch: ld: Add support for linker relaxation.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221216072336.1087469-7-mengqinggang@loongson.cn/mbox/"},{"id":33895,"url":"https://patchwork.plctlab.org/api/1.2/patches/33895/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/98057a7f-d166-1940-f00f-d9c5d912328d@suse.com/","msgid":"<98057a7f-d166-1940-f00f-d9c5d912328d@suse.com>","list_archive_url":null,"date":"2022-12-16T08:07:29","name":"[v2] x86: omit Cpu prefixes from opcode table","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/98057a7f-d166-1940-f00f-d9c5d912328d@suse.com/mbox/"},{"id":33899,"url":"https://patchwork.plctlab.org/api/1.2/patches/33899/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/507f0d3f-c34e-9895-21bf-37525bf0a6fb@suse.com/","msgid":"<507f0d3f-c34e-9895-21bf-37525bf0a6fb@suse.com>","list_archive_url":null,"date":"2022-12-16T08:28:38","name":"[1/4] gprofng/testsuite: adjust linking of synprog","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/507f0d3f-c34e-9895-21bf-37525bf0a6fb@suse.com/mbox/"},{"id":33900,"url":"https://patchwork.plctlab.org/api/1.2/patches/33900/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/67f3d4e3-46dd-e39d-d154-49bf25dbafc8@suse.com/","msgid":"<67f3d4e3-46dd-e39d-d154-49bf25dbafc8@suse.com>","list_archive_url":null,"date":"2022-12-16T08:29:50","name":"[2/4] gprofng/testsuite: correct names for signal handling tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/67f3d4e3-46dd-e39d-d154-49bf25dbafc8@suse.com/mbox/"},{"id":33902,"url":"https://patchwork.plctlab.org/api/1.2/patches/33902/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/240a568e-ab05-b3b5-d004-c1fc6799c66f@suse.com/","msgid":"<240a568e-ab05-b3b5-d004-c1fc6799c66f@suse.com>","list_archive_url":null,"date":"2022-12-16T08:30:10","name":"[3/4] gprofng/testsuite: correct line continuation in endcases.c","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/240a568e-ab05-b3b5-d004-c1fc6799c66f@suse.com/mbox/"},{"id":33903,"url":"https://patchwork.plctlab.org/api/1.2/patches/33903/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f0679195-cfa8-6f87-2519-520f758e615e@suse.com/","msgid":"","list_archive_url":null,"date":"2022-12-16T08:30:30","name":"[4/4] gprofng/testsuite: eliminate bogus casts","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f0679195-cfa8-6f87-2519-520f758e615e@suse.com/mbox/"},{"id":33915,"url":"https://patchwork.plctlab.org/api/1.2/patches/33915/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0acc18cc-d246-9c2a-ba14-586c693b9e58@suse.com/","msgid":"<0acc18cc-d246-9c2a-ba14-586c693b9e58@suse.com>","list_archive_url":null,"date":"2022-12-16T09:13:36","name":"[5/4] gprofng/testsuite: skip Java test without JDK","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0acc18cc-d246-9c2a-ba14-586c693b9e58@suse.com/mbox/"},{"id":33950,"url":"https://patchwork.plctlab.org/api/1.2/patches/33950/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221216132541.45791-2-nick.alcock@oracle.com/","msgid":"<20221216132541.45791-2-nick.alcock@oracle.com>","list_archive_url":null,"date":"2022-12-16T13:25:38","name":"[1/4] ctf: fix various dreadful typos in the ctf_archive format comments","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221216132541.45791-2-nick.alcock@oracle.com/mbox/"},{"id":33951,"url":"https://patchwork.plctlab.org/api/1.2/patches/33951/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221216132541.45791-3-nick.alcock@oracle.com/","msgid":"<20221216132541.45791-3-nick.alcock@oracle.com>","list_archive_url":null,"date":"2022-12-16T13:25:39","name":"[2/4] libtool.m4: adjust kludge for ignoring syntax errors","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221216132541.45791-3-nick.alcock@oracle.com/mbox/"},{"id":33952,"url":"https://patchwork.plctlab.org/api/1.2/patches/33952/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221216132541.45791-4-nick.alcock@oracle.com/","msgid":"<20221216132541.45791-4-nick.alcock@oracle.com>","list_archive_url":null,"date":"2022-12-16T13:25:40","name":"[3/4] Regenerate affected configures.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221216132541.45791-4-nick.alcock@oracle.com/mbox/"},{"id":33953,"url":"https://patchwork.plctlab.org/api/1.2/patches/33953/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221216132541.45791-5-nick.alcock@oracle.com/","msgid":"<20221216132541.45791-5-nick.alcock@oracle.com>","list_archive_url":null,"date":"2022-12-16T13:25:41","name":"[4/4] libctf: skip the testsuite from inside dejagnu","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221216132541.45791-5-nick.alcock@oracle.com/mbox/"},{"id":34050,"url":"https://patchwork.plctlab.org/api/1.2/patches/34050/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221216185133.1342022-1-christoph.muellner@vrull.eu/","msgid":"<20221216185133.1342022-1-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2022-12-16T18:51:33","name":"RISC-V: Fix T-Head Fmv vendor extension encoding","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221216185133.1342022-1-christoph.muellner@vrull.eu/mbox/"},{"id":34093,"url":"https://patchwork.plctlab.org/api/1.2/patches/34093/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221216214310.13155-1-prabhakar.mahadev-lad.rj@bp.renesas.com/","msgid":"<20221216214310.13155-1-prabhakar.mahadev-lad.rj@bp.renesas.com>","list_archive_url":null,"date":"2022-12-16T21:43:10","name":"[RFC] ld/emulparams: elf32lriscv-defs: Add support tune the text segment start address","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221216214310.13155-1-prabhakar.mahadev-lad.rj@bp.renesas.com/mbox/"},{"id":34193,"url":"https://patchwork.plctlab.org/api/1.2/patches/34193/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221217064128.11326-2-indu.bhagat@oracle.com/","msgid":"<20221217064128.11326-2-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-12-17T06:41:23","name":"[COMMITTED,V2,1/6] sframe.h: add support for .cfi_negate_ra_state","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221217064128.11326-2-indu.bhagat@oracle.com/mbox/"},{"id":34188,"url":"https://patchwork.plctlab.org/api/1.2/patches/34188/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221217064128.11326-3-indu.bhagat@oracle.com/","msgid":"<20221217064128.11326-3-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-12-17T06:41:24","name":"[COMMITTED,V2,2/6] gas: sframe: add support for .cfi_negate_ra_state","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221217064128.11326-3-indu.bhagat@oracle.com/mbox/"},{"id":34187,"url":"https://patchwork.plctlab.org/api/1.2/patches/34187/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221217064128.11326-4-indu.bhagat@oracle.com/","msgid":"<20221217064128.11326-4-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-12-17T06:41:25","name":"[COMMITTED,V2,3/6] libsframe: provide new access API for mangled RA bit","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221217064128.11326-4-indu.bhagat@oracle.com/mbox/"},{"id":34189,"url":"https://patchwork.plctlab.org/api/1.2/patches/34189/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221217064128.11326-5-indu.bhagat@oracle.com/","msgid":"<20221217064128.11326-5-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-12-17T06:41:26","name":"[COMMITTED,V2,4/6] objdump/readelf: sframe: emit marker for FREs with mangled RA","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221217064128.11326-5-indu.bhagat@oracle.com/mbox/"},{"id":34195,"url":"https://patchwork.plctlab.org/api/1.2/patches/34195/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221217064128.11326-6-indu.bhagat@oracle.com/","msgid":"<20221217064128.11326-6-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-12-17T06:41:27","name":"[COMMITTED,V2,5/6] gas: sframe: testsuite: add testcase for .cfi_negate_ra_state","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221217064128.11326-6-indu.bhagat@oracle.com/mbox/"},{"id":34196,"url":"https://patchwork.plctlab.org/api/1.2/patches/34196/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221217064128.11326-7-indu.bhagat@oracle.com/","msgid":"<20221217064128.11326-7-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-12-17T06:41:28","name":"[COMMITTED,V2,6/6] sframe: doc: update spec for the mangled-RA bit in FRE","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221217064128.11326-7-indu.bhagat@oracle.com/mbox/"},{"id":34198,"url":"https://patchwork.plctlab.org/api/1.2/patches/34198/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y516F5Mqq4AgLz0T@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-12-17T08:13:11","name":"asan: elf.c:12621:18: applying zero offset to null pointer","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y516F5Mqq4AgLz0T@squeak.grove.modra.org/mbox/"},{"id":34199,"url":"https://patchwork.plctlab.org/api/1.2/patches/34199/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y516VfGAggasKzZE@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-12-17T08:14:13","name":"bfd_get_relocated_section_contents allow NULL data buffer","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y516VfGAggasKzZE@squeak.grove.modra.org/mbox/"},{"id":34204,"url":"https://patchwork.plctlab.org/api/1.2/patches/34204/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221217102842.3645997-1-torbjorn.svensson@foss.st.com/","msgid":"<20221217102842.3645997-1-torbjorn.svensson@foss.st.com>","list_archive_url":null,"date":"2022-12-17T10:28:42","name":"bfd: Discard region regardless of warning flag","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221217102842.3645997-1-torbjorn.svensson@foss.st.com/mbox/"},{"id":34302,"url":"https://patchwork.plctlab.org/api/1.2/patches/34302/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y57nSbf16Gc0Cm7u@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-12-18T10:11:21","name":"ld bootstrap test in build dir with path containing symlinks","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y57nSbf16Gc0Cm7u@squeak.grove.modra.org/mbox/"},{"id":34303,"url":"https://patchwork.plctlab.org/api/1.2/patches/34303/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y57nfEDqt/784poP@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-12-18T10:12:12","name":"Comment bfd_get_section_limit_octets and bfd_get_section_alloc_size","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y57nfEDqt/784poP@squeak.grove.modra.org/mbox/"},{"id":34459,"url":"https://patchwork.plctlab.org/api/1.2/patches/34459/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221219090346.213013-1-vladimir.mezentsev@oracle.com/","msgid":"<20221219090346.213013-1-vladimir.mezentsev@oracle.com>","list_archive_url":null,"date":"2022-12-19T09:03:46","name":"gprofng: PR29646 Various warnings","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221219090346.213013-1-vladimir.mezentsev@oracle.com/mbox/"},{"id":34460,"url":"https://patchwork.plctlab.org/api/1.2/patches/34460/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/63033af0-eb22-a8eb-c8cb-f268344c5a14@suse.com/","msgid":"<63033af0-eb22-a8eb-c8cb-f268344c5a14@suse.com>","list_archive_url":null,"date":"2022-12-19T10:44:40","name":"[01/10] x86: re-work ISA extension dependency handling","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/63033af0-eb22-a8eb-c8cb-f268344c5a14@suse.com/mbox/"},{"id":34461,"url":"https://patchwork.plctlab.org/api/1.2/patches/34461/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2cf259b7-9594-ed3f-f3f0-e7a232c03551@suse.com/","msgid":"<2cf259b7-9594-ed3f-f3f0-e7a232c03551@suse.com>","list_archive_url":null,"date":"2022-12-19T10:45:06","name":"[02/10] x86: correct what gets disabled by certain \".arch .no*\"","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2cf259b7-9594-ed3f-f3f0-e7a232c03551@suse.com/mbox/"},{"id":34462,"url":"https://patchwork.plctlab.org/api/1.2/patches/34462/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/141a0a8e-eb9f-f68f-0eb1-92d62e828f9e@suse.com/","msgid":"<141a0a8e-eb9f-f68f-0eb1-92d62e828f9e@suse.com>","list_archive_url":null,"date":"2022-12-19T10:45:36","name":"[03/10] x86: correct SSE dependencies","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/141a0a8e-eb9f-f68f-0eb1-92d62e828f9e@suse.com/mbox/"},{"id":34467,"url":"https://patchwork.plctlab.org/api/1.2/patches/34467/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ae514f08-6ed8-e30a-9077-c9e37d12bd46@suse.com/","msgid":"","list_archive_url":null,"date":"2022-12-19T10:45:55","name":"[04/10] x86: add dependencies on AVX2","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ae514f08-6ed8-e30a-9077-c9e37d12bd46@suse.com/mbox/"},{"id":34468,"url":"https://patchwork.plctlab.org/api/1.2/patches/34468/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0f352a12-4d8a-7658-0104-8537241b6b49@suse.com/","msgid":"<0f352a12-4d8a-7658-0104-8537241b6b49@suse.com>","list_archive_url":null,"date":"2022-12-19T10:46:24","name":"[05/10] x86: rework noavx512-1 testcase","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0f352a12-4d8a-7658-0104-8537241b6b49@suse.com/mbox/"},{"id":34464,"url":"https://patchwork.plctlab.org/api/1.2/patches/34464/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2176ff46-f9e9-19c5-576a-0e69d9d02c15@suse.com/","msgid":"<2176ff46-f9e9-19c5-576a-0e69d9d02c15@suse.com>","list_archive_url":null,"date":"2022-12-19T10:46:50","name":"[06/10] x86: correct dependencies of a few AVX512 sub-features","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2176ff46-f9e9-19c5-576a-0e69d9d02c15@suse.com/mbox/"},{"id":34466,"url":"https://patchwork.plctlab.org/api/1.2/patches/34466/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/70971dfa-e30a-ec90-d797-808ecf674cc5@suse.com/","msgid":"<70971dfa-e30a-ec90-d797-808ecf674cc5@suse.com>","list_archive_url":null,"date":"2022-12-19T10:47:18","name":"[07/10] x86: correct XSAVE* dependencies","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/70971dfa-e30a-ec90-d797-808ecf674cc5@suse.com/mbox/"},{"id":34471,"url":"https://patchwork.plctlab.org/api/1.2/patches/34471/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f29c5510-bc33-b0c3-aa25-27a02ba613ad@suse.com/","msgid":"","list_archive_url":null,"date":"2022-12-19T10:47:44","name":"[08/10] x86: add dependencies on VMX","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f29c5510-bc33-b0c3-aa25-27a02ba613ad@suse.com/mbox/"},{"id":34465,"url":"https://patchwork.plctlab.org/api/1.2/patches/34465/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0a930835-e8b4-40fa-34e5-bc29cde85200@suse.com/","msgid":"<0a930835-e8b4-40fa-34e5-bc29cde85200@suse.com>","list_archive_url":null,"date":"2022-12-19T10:48:11","name":"[09/10] x86: add dependencies on SVME","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0a930835-e8b4-40fa-34e5-bc29cde85200@suse.com/mbox/"},{"id":34472,"url":"https://patchwork.plctlab.org/api/1.2/patches/34472/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1b04fb35-1f99-7353-4e8c-d643e8ffa975@suse.com/","msgid":"<1b04fb35-1f99-7353-4e8c-d643e8ffa975@suse.com>","list_archive_url":null,"date":"2022-12-19T10:48:31","name":"[10/10] x86: correct/improve TSX controls","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1b04fb35-1f99-7353-4e8c-d643e8ffa975@suse.com/mbox/"},{"id":34470,"url":"https://patchwork.plctlab.org/api/1.2/patches/34470/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4a5ff47c-77cf-5ffa-ad7b-c8e0ae54b31c@suse.com/","msgid":"<4a5ff47c-77cf-5ffa-ad7b-c8e0ae54b31c@suse.com>","list_archive_url":null,"date":"2022-12-19T10:50:39","name":"x86: rename CheckRegSize to CheckOperandSize","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4a5ff47c-77cf-5ffa-ad7b-c8e0ae54b31c@suse.com/mbox/"},{"id":34473,"url":"https://patchwork.plctlab.org/api/1.2/patches/34473/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fdbff837-ebd9-7726-351c-1c43c619b4cb@suse.com/","msgid":"","list_archive_url":null,"date":"2022-12-19T10:53:19","name":"gas: re-arrange listing output for .irp and alike","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fdbff837-ebd9-7726-351c-1c43c619b4cb@suse.com/mbox/"},{"id":34476,"url":"https://patchwork.plctlab.org/api/1.2/patches/34476/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/87r0wvsl2q.fsf@redhat.com/","msgid":"<87r0wvsl2q.fsf@redhat.com>","list_archive_url":null,"date":"2022-12-19T11:13:17","name":"Commit: Add more tests for corrupt DWARF data","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/87r0wvsl2q.fsf@redhat.com/mbox/"},{"id":34538,"url":"https://patchwork.plctlab.org/api/1.2/patches/34538/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221219131149.2268979-1-luis.machado@arm.com/","msgid":"<20221219131149.2268979-1-luis.machado@arm.com>","list_archive_url":null,"date":"2022-12-19T13:11:49","name":"[aarch64/sme] binutils: Add new NT_ARM_ZA and NT_ARM_SSVE register set constants","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221219131149.2268979-1-luis.machado@arm.com/mbox/"},{"id":34542,"url":"https://patchwork.plctlab.org/api/1.2/patches/34542/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y6Bmt87TKcG5vugy@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-12-19T13:27:19","name":"Tidy PR29893 and PR29908 fix","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y6Bmt87TKcG5vugy@squeak.grove.modra.org/mbox/"},{"id":34553,"url":"https://patchwork.plctlab.org/api/1.2/patches/34553/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221219135303.116222-2-mpapini@redhat.com/","msgid":"<20221219135303.116222-2-mpapini@redhat.com>","list_archive_url":null,"date":"2022-12-19T13:53:02","name":"[1/2] addr2line: new option -n to add a newline at the end","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221219135303.116222-2-mpapini@redhat.com/mbox/"},{"id":34554,"url":"https://patchwork.plctlab.org/api/1.2/patches/34554/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221219135303.116222-3-mpapini@redhat.com/","msgid":"<20221219135303.116222-3-mpapini@redhat.com>","list_archive_url":null,"date":"2022-12-19T13:53:03","name":"[2/2] addr2line: test to check -n option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221219135303.116222-3-mpapini@redhat.com/mbox/"},{"id":34605,"url":"https://patchwork.plctlab.org/api/1.2/patches/34605/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f8cae085-3ed5-a6ec-cedf-f78d0c4b0ae1@suse.com/","msgid":"","list_archive_url":null,"date":"2022-12-19T15:06:26","name":"gprofng/testsuite: restrict testing to native configurations","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f8cae085-3ed5-a6ec-cedf-f78d0c4b0ae1@suse.com/mbox/"},{"id":34649,"url":"https://patchwork.plctlab.org/api/1.2/patches/34649/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221219164830.394274-1-tromey@adacore.com/","msgid":"<20221219164830.394274-1-tromey@adacore.com>","list_archive_url":null,"date":"2022-12-19T16:48:30","name":"[pushed] Avoid compiler warning in dwarf-do-refresh","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221219164830.394274-1-tromey@adacore.com/mbox/"},{"id":34689,"url":"https://patchwork.plctlab.org/api/1.2/patches/34689/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221219183450.3754890-1-torbjorn.svensson@foss.st.com/","msgid":"<20221219183450.3754890-1-torbjorn.svensson@foss.st.com>","list_archive_url":null,"date":"2022-12-19T18:34:51","name":"[v2] bfd: Discard region regardless of warning flag","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221219183450.3754890-1-torbjorn.svensson@foss.st.com/mbox/"},{"id":34751,"url":"https://patchwork.plctlab.org/api/1.2/patches/34751/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221219202328.1442022-2-indu.bhagat@oracle.com/","msgid":"<20221219202328.1442022-2-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-12-19T20:23:24","name":"[COMMITTED,V2,1/5,1/5] sframe.h: add support for .cfi_b_key_frame","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221219202328.1442022-2-indu.bhagat@oracle.com/mbox/"},{"id":34749,"url":"https://patchwork.plctlab.org/api/1.2/patches/34749/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221219202328.1442022-3-indu.bhagat@oracle.com/","msgid":"<20221219202328.1442022-3-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-12-19T20:23:25","name":"[COMMITTED,V2,2/5,2/5] gas: sframe: add support for .cfi_b_key_frame","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221219202328.1442022-3-indu.bhagat@oracle.com/mbox/"},{"id":34748,"url":"https://patchwork.plctlab.org/api/1.2/patches/34748/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221219202328.1442022-4-indu.bhagat@oracle.com/","msgid":"<20221219202328.1442022-4-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-12-19T20:23:26","name":"[COMMITTED,V2,3/5,3/5] objdump/readelf: sframe: emit marker for SFrame FDE with B key","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221219202328.1442022-4-indu.bhagat@oracle.com/mbox/"},{"id":34752,"url":"https://patchwork.plctlab.org/api/1.2/patches/34752/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221219202328.1442022-5-indu.bhagat@oracle.com/","msgid":"<20221219202328.1442022-5-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-12-19T20:23:27","name":"[COMMITTED,V2,4/5,4/5] gas: sframe: testsuite: add testcase for .cfi_b_key_frame","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221219202328.1442022-5-indu.bhagat@oracle.com/mbox/"},{"id":34750,"url":"https://patchwork.plctlab.org/api/1.2/patches/34750/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221219202328.1442022-6-indu.bhagat@oracle.com/","msgid":"<20221219202328.1442022-6-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-12-19T20:23:28","name":"[COMMITTED,V2,5/5,5/5] sframe: doc: update documentation for pauth key in SFrame FDE","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221219202328.1442022-6-indu.bhagat@oracle.com/mbox/"},{"id":34774,"url":"https://patchwork.plctlab.org/api/1.2/patches/34774/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221219211406.1443750-2-indu.bhagat@oracle.com/","msgid":"<20221219211406.1443750-2-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-12-19T21:14:02","name":"[V2,1/5,1/5] sframe.h: add support for .cfi_b_key_frame","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221219211406.1443750-2-indu.bhagat@oracle.com/mbox/"},{"id":34775,"url":"https://patchwork.plctlab.org/api/1.2/patches/34775/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221219211406.1443750-3-indu.bhagat@oracle.com/","msgid":"<20221219211406.1443750-3-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-12-19T21:14:03","name":"[V2,2/5,2/5] gas: sframe: add support for .cfi_b_key_frame","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221219211406.1443750-3-indu.bhagat@oracle.com/mbox/"},{"id":34776,"url":"https://patchwork.plctlab.org/api/1.2/patches/34776/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221219211406.1443750-4-indu.bhagat@oracle.com/","msgid":"<20221219211406.1443750-4-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-12-19T21:14:04","name":"[V2,3/5,3/5] objdump/readelf: sframe: emit marker for SFrame FDE with B key","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221219211406.1443750-4-indu.bhagat@oracle.com/mbox/"},{"id":34777,"url":"https://patchwork.plctlab.org/api/1.2/patches/34777/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221219211406.1443750-5-indu.bhagat@oracle.com/","msgid":"<20221219211406.1443750-5-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-12-19T21:14:05","name":"[V2,4/5,4/5] gas: sframe: testsuite: add testcase for .cfi_b_key_frame","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221219211406.1443750-5-indu.bhagat@oracle.com/mbox/"},{"id":34778,"url":"https://patchwork.plctlab.org/api/1.2/patches/34778/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221219211406.1443750-6-indu.bhagat@oracle.com/","msgid":"<20221219211406.1443750-6-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-12-19T21:14:06","name":"[V2,5/5,5/5] sframe: doc: update documentation for pauth key in SFrame FDE","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221219211406.1443750-6-indu.bhagat@oracle.com/mbox/"},{"id":34990,"url":"https://patchwork.plctlab.org/api/1.2/patches/34990/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y6FzlOKIrFOjqKVE@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-12-20T08:34:28","name":"PR29915, bfdio.c does not compile with mingw.org'\''s MinGW","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y6FzlOKIrFOjqKVE@squeak.grove.modra.org/mbox/"},{"id":35279,"url":"https://patchwork.plctlab.org/api/1.2/patches/35279/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y6K1tWIKWE+UA7+E@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-12-21T07:28:53","name":"PR29922, SHT_NOBITS section avoids section size sanity check","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y6K1tWIKWE+UA7+E@squeak.grove.modra.org/mbox/"},{"id":35280,"url":"https://patchwork.plctlab.org/api/1.2/patches/35280/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y6K17LKfvNSlmnbB@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-12-21T07:29:48","name":"enable-non-contiguous-regions warnings","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y6K17LKfvNSlmnbB@squeak.grove.modra.org/mbox/"},{"id":35347,"url":"https://patchwork.plctlab.org/api/1.2/patches/35347/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221221120934.45775-1-nelson@rivosinc.com/","msgid":"<20221221120934.45775-1-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-12-21T12:09:34","name":"RISC-V: Relax the order checking for the architecture string.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221221120934.45775-1-nelson@rivosinc.com/mbox/"},{"id":35432,"url":"https://patchwork.plctlab.org/api/1.2/patches/35432/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221221170706.2877188-2-christoph.muellner@vrull.eu/","msgid":"<20221221170706.2877188-2-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2022-12-21T17:07:01","name":"[RFC,1/6] RISC-V: Add Zvkb ISA extension support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221221170706.2877188-2-christoph.muellner@vrull.eu/mbox/"},{"id":35431,"url":"https://patchwork.plctlab.org/api/1.2/patches/35431/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221221170706.2877188-3-christoph.muellner@vrull.eu/","msgid":"<20221221170706.2877188-3-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2022-12-21T17:07:02","name":"[RFC,2/6] RISC-V: Add Zvkg ISA extension support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221221170706.2877188-3-christoph.muellner@vrull.eu/mbox/"},{"id":35434,"url":"https://patchwork.plctlab.org/api/1.2/patches/35434/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221221170706.2877188-4-christoph.muellner@vrull.eu/","msgid":"<20221221170706.2877188-4-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2022-12-21T17:07:03","name":"[RFC,3/6] RISC-V: Add Zvkh[a,b] ISA extension support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221221170706.2877188-4-christoph.muellner@vrull.eu/mbox/"},{"id":35435,"url":"https://patchwork.plctlab.org/api/1.2/patches/35435/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221221170706.2877188-5-christoph.muellner@vrull.eu/","msgid":"<20221221170706.2877188-5-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2022-12-21T17:07:04","name":"[RFC,4/6] RISC-V: Add Zvkn ISA extension support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221221170706.2877188-5-christoph.muellner@vrull.eu/mbox/"},{"id":35433,"url":"https://patchwork.plctlab.org/api/1.2/patches/35433/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221221170706.2877188-6-christoph.muellner@vrull.eu/","msgid":"<20221221170706.2877188-6-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2022-12-21T17:07:05","name":"[RFC,5/6] RISC-V: Add Zvksed ISA extension support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221221170706.2877188-6-christoph.muellner@vrull.eu/mbox/"},{"id":35437,"url":"https://patchwork.plctlab.org/api/1.2/patches/35437/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221221170706.2877188-7-christoph.muellner@vrull.eu/","msgid":"<20221221170706.2877188-7-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2022-12-21T17:07:06","name":"[RFC,6/6] RISC-V: Add Zvksh ISA extension support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221221170706.2877188-7-christoph.muellner@vrull.eu/mbox/"},{"id":35528,"url":"https://patchwork.plctlab.org/api/1.2/patches/35528/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y6N6cNwCN8q5hhHc@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-12-21T21:28:16","name":"PR29925, Memory leak in find_abstract_instance","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y6N6cNwCN8q5hhHc@squeak.grove.modra.org/mbox/"},{"id":35982,"url":"https://patchwork.plctlab.org/api/1.2/patches/35982/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221222225457.1095930-2-indu.bhagat@oracle.com/","msgid":"<20221222225457.1095930-2-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-12-22T22:54:56","name":"[1/2] libsframe: fix a memory leak in sframe_decode","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221222225457.1095930-2-indu.bhagat@oracle.com/mbox/"},{"id":35983,"url":"https://patchwork.plctlab.org/api/1.2/patches/35983/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221222225457.1095930-3-indu.bhagat@oracle.com/","msgid":"<20221222225457.1095930-3-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-12-22T22:54:57","name":"[2/2] libsframe: testsuite: fix memory leaks in testcases","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221222225457.1095930-3-indu.bhagat@oracle.com/mbox/"},{"id":36015,"url":"https://patchwork.plctlab.org/api/1.2/patches/36015/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y6TwpegMSaNdNc48@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-12-23T00:04:53","name":"COFF build-id writes uninitialised data to file","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y6TwpegMSaNdNc48@squeak.grove.modra.org/mbox/"},{"id":36206,"url":"https://patchwork.plctlab.org/api/1.2/patches/36206/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y6WIDO8tOPdLz0+5@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-12-23T10:50:52","name":"pdb build fixes","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y6WIDO8tOPdLz0+5@squeak.grove.modra.org/mbox/"},{"id":36281,"url":"https://patchwork.plctlab.org/api/1.2/patches/36281/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/98617b373993a3c6054b9389cddfde56b9aec7d1.camel@klomp.org/","msgid":"<98617b373993a3c6054b9389cddfde56b9aec7d1.camel@klomp.org>","list_archive_url":null,"date":"2022-12-23T14:22:38","name":"libsframe builder (Was: [PATCH 0/2] libsframe: fix some memory leaks)","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/98617b373993a3c6054b9389cddfde56b9aec7d1.camel@klomp.org/mbox/"},{"id":36442,"url":"https://patchwork.plctlab.org/api/1.2/patches/36442/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221224194012.1889405-1-indu.bhagat@oracle.com/","msgid":"<20221224194012.1889405-1-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-12-24T19:40:12","name":"libsframe: write out SFrame FRE start address correctly","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221224194012.1889405-1-indu.bhagat@oracle.com/mbox/"},{"id":36515,"url":"https://patchwork.plctlab.org/api/1.2/patches/36515/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y6j2+q32Gg+3rSGs@mars/","msgid":"","list_archive_url":null,"date":"2022-12-26T01:20:58","name":"Add support for x86_64-*-gnu-* targets to build x86_64 gnumach/hurd","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y6j2+q32Gg+3rSGs@mars/mbox/"},{"id":36605,"url":"https://patchwork.plctlab.org/api/1.2/patches/36605/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y6mS/HVlwxWvjyo9@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-12-26T12:26:36","name":"bfd/dwarf2.c: allow use of DWARF5 directory entry 0","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y6mS/HVlwxWvjyo9@squeak.grove.modra.org/mbox/"},{"id":36702,"url":"https://patchwork.plctlab.org/api/1.2/patches/36702/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221226204751.23761-1-mark@harmstone.com/","msgid":"<20221226204751.23761-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-12-26T20:47:49","name":"[1/3] ld: Handle extended-length data structures in PDB types","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221226204751.23761-1-mark@harmstone.com/mbox/"},{"id":36701,"url":"https://patchwork.plctlab.org/api/1.2/patches/36701/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221226204751.23761-2-mark@harmstone.com/","msgid":"<20221226204751.23761-2-mark@harmstone.com>","list_archive_url":null,"date":"2022-12-26T20:47:50","name":"[2/3] ld: Handle LF_VFTABLE types in PDBs","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221226204751.23761-2-mark@harmstone.com/mbox/"},{"id":36700,"url":"https://patchwork.plctlab.org/api/1.2/patches/36700/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221226204751.23761-3-mark@harmstone.com/","msgid":"<20221226204751.23761-3-mark@harmstone.com>","list_archive_url":null,"date":"2022-12-26T20:47:51","name":"[3/3] ld/testsuite: Don'\''t add index to sizes in pdb.exp","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221226204751.23761-3-mark@harmstone.com/mbox/"},{"id":36989,"url":"https://patchwork.plctlab.org/api/1.2/patches/36989/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221227194756.448332-1-hjl.tools@gmail.com/","msgid":"<20221227194756.448332-1-hjl.tools@gmail.com>","list_archive_url":null,"date":"2022-12-27T19:47:56","name":"x86-64: Allocate input section memory if needed","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221227194756.448332-1-hjl.tools@gmail.com/mbox/"},{"id":37100,"url":"https://patchwork.plctlab.org/api/1.2/patches/37100/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221228040649.810-1-shihua@iscas.ac.cn/","msgid":"<20221228040649.810-1-shihua@iscas.ac.cn>","list_archive_url":null,"date":"2022-12-28T04:06:49","name":"[RFC] Support RV64-ILP32","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221228040649.810-1-shihua@iscas.ac.cn/mbox/"},{"id":37293,"url":"https://patchwork.plctlab.org/api/1.2/patches/37293/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e6156a39f6be66c559443e890d8a3a9a592e63d6.1672285661.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-12-29T03:51:44","name":"RISC-V: Make T-Head testing pattern more generic","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e6156a39f6be66c559443e890d8a3a9a592e63d6.1672285661.git.research_trasio@irq.a4lg.com/mbox/"},{"id":37294,"url":"https://patchwork.plctlab.org/api/1.2/patches/37294/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c509db05e4f1500736f4de994ed2aede544234d5.1672286099.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-12-29T03:55:05","name":"[1/2] RISC-V: Simplify riscv_csr_address logic on state enable extensions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c509db05e4f1500736f4de994ed2aede544234d5.1672286099.git.research_trasio@irq.a4lg.com/mbox/"},{"id":37295,"url":"https://patchwork.plctlab.org/api/1.2/patches/37295/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e5ff96022a4144e49d9151946a2e6cb2bd7b8419.1672286099.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-12-29T03:55:06","name":"[2/2] RISC-V: Reorder CSR classes related to '\''Ssstateen'\''","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e5ff96022a4144e49d9151946a2e6cb2bd7b8419.1672286099.git.research_trasio@irq.a4lg.com/mbox/"},{"id":37548,"url":"https://patchwork.plctlab.org/api/1.2/patches/37548/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221230024055.31841-1-mark@harmstone.com/","msgid":"<20221230024055.31841-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-12-30T02:40:48","name":"[1/8] ld: Rename aarch64pe emulation target to arm64pe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221230024055.31841-1-mark@harmstone.com/mbox/"},{"id":37549,"url":"https://patchwork.plctlab.org/api/1.2/patches/37549/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221230024055.31841-2-mark@harmstone.com/","msgid":"<20221230024055.31841-2-mark@harmstone.com>","list_archive_url":null,"date":"2022-12-30T02:40:49","name":"[2/8] Fix size of external_reloc for pe-aarch64","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221230024055.31841-2-mark@harmstone.com/mbox/"},{"id":37551,"url":"https://patchwork.plctlab.org/api/1.2/patches/37551/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221230024055.31841-3-mark@harmstone.com/","msgid":"<20221230024055.31841-3-mark@harmstone.com>","list_archive_url":null,"date":"2022-12-30T02:40:50","name":"[3/8] Skip ELF-specific tests when targeting pe-aarch64","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221230024055.31841-3-mark@harmstone.com/mbox/"},{"id":37550,"url":"https://patchwork.plctlab.org/api/1.2/patches/37550/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221230024055.31841-4-mark@harmstone.com/","msgid":"<20221230024055.31841-4-mark@harmstone.com>","list_archive_url":null,"date":"2022-12-30T02:40:51","name":"[4/8] Skip big-obj test for pe-aarch64","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221230024055.31841-4-mark@harmstone.com/mbox/"},{"id":37554,"url":"https://patchwork.plctlab.org/api/1.2/patches/37554/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221230024055.31841-5-mark@harmstone.com/","msgid":"<20221230024055.31841-5-mark@harmstone.com>","list_archive_url":null,"date":"2022-12-30T02:40:52","name":"[5/8] Add pe-aarch64 relocations","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221230024055.31841-5-mark@harmstone.com/mbox/"},{"id":37553,"url":"https://patchwork.plctlab.org/api/1.2/patches/37553/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221230024055.31841-6-mark@harmstone.com/","msgid":"<20221230024055.31841-6-mark@harmstone.com>","list_archive_url":null,"date":"2022-12-30T02:40:53","name":"[6/8] Add .secrel32 for pe-aarch64","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221230024055.31841-6-mark@harmstone.com/mbox/"},{"id":37555,"url":"https://patchwork.plctlab.org/api/1.2/patches/37555/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221230024055.31841-7-mark@harmstone.com/","msgid":"<20221230024055.31841-7-mark@harmstone.com>","list_archive_url":null,"date":"2022-12-30T02:40:54","name":"[7/8] Add aarch64-w64-mingw32 target","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221230024055.31841-7-mark@harmstone.com/mbox/"},{"id":37552,"url":"https://patchwork.plctlab.org/api/1.2/patches/37552/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221230024055.31841-8-mark@harmstone.com/","msgid":"<20221230024055.31841-8-mark@harmstone.com>","list_archive_url":null,"date":"2022-12-30T02:40:55","name":"[8/8] gas: Restore tc_pe_dwarf2_emit_offset for pe-aarch64","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221230024055.31841-8-mark@harmstone.com/mbox/"},{"id":37656,"url":"https://patchwork.plctlab.org/api/1.2/patches/37656/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y67RWv4jQ93m2JzK@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-12-30T11:54:02","name":"PR29948, heap-buffer-overflow in display_debug_lines_decoded","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y67RWv4jQ93m2JzK@squeak.grove.modra.org/mbox/"},{"id":37836,"url":"https://patchwork.plctlab.org/api/1.2/patches/37836/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/87v8lr93ws.fsf@redhat.com/","msgid":"<87v8lr93ws.fsf@redhat.com>","list_archive_url":null,"date":"2022-12-31T12:02:59","name":"Commit: Sync libiberty sources with gcc mainline","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/87v8lr93ws.fsf@redhat.com/mbox/"}],"public":true,"mbox":"https://patchwork.plctlab.org/bundle/patchwork-bot/binutils-gdb_2022-12/mbox/"},{"id":13,"url":"https://patchwork.plctlab.org/api/1.2/bundles/13/","web_url":"https://patchwork.plctlab.org/bundle/patchwork-bot/binutils-gdb_2023-01/","project":{"id":2,"url":"https://patchwork.plctlab.org/api/1.2/projects/2/","name":"binutils-gdb","link_name":"binutils-gdb","list_id":"binutils.sourceware.org","list_email":"binutils@sourceware.org","web_url":"https://github.com/wangliu-iscas/Patchwork-Bundles/blob/main/binutils-gdb.md","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"name":"binutils-gdb_2023-01","owner":{"id":3,"url":"https://patchwork.plctlab.org/api/1.2/users/3/","username":"patchwork-bot","first_name":"","last_name":"","email":"ouuuleilei@gmail.com"},"patches":[{"id":37894,"url":"https://patchwork.plctlab.org/api/1.2/patches/37894/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221231205546.14330-1-mark@harmstone.com/","msgid":"<20221231205546.14330-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-12-31T20:55:46","name":"Avoid unaligned pointer reads in PEP .idata section","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221231205546.14330-1-mark@harmstone.com/mbox/"},{"id":37945,"url":"https://patchwork.plctlab.org/api/1.2/patches/37945/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y7FukAKCvmmsn7pb@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-01-01T11:29:20","name":"Update etc/update-copyright.py","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y7FukAKCvmmsn7pb@squeak.grove.modra.org/mbox/"},{"id":37992,"url":"https://patchwork.plctlab.org/api/1.2/patches/37992/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y7JSKtcK8QTgIQY5@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-01-02T03:40:26","name":"obsolete target tidy","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y7JSKtcK8QTgIQY5@squeak.grove.modra.org/mbox/"},{"id":38142,"url":"https://patchwork.plctlab.org/api/1.2/patches/38142/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230102160857.ABA7F2042C@pchp3.se.axis.com/","msgid":"<20230102160857.ABA7F2042C@pchp3.se.axis.com>","list_archive_url":null,"date":"2023-01-02T16:08:57","name":"Fix ld bloat introduced between binutils-2.38 and 2.39","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230102160857.ABA7F2042C@pchp3.se.axis.com/mbox/"},{"id":38247,"url":"https://patchwork.plctlab.org/api/1.2/patches/38247/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230103024119.12F182042C@pchp3.se.axis.com/","msgid":"<20230103024119.12F182042C@pchp3.se.axis.com>","list_archive_url":null,"date":"2023-01-03T02:41:19","name":"ARM: Fix ld bloat introduced between binutils-2.38 and 2.39","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230103024119.12F182042C@pchp3.se.axis.com/mbox/"},{"id":38355,"url":"https://patchwork.plctlab.org/api/1.2/patches/38355/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230103102251.89478-1-christophe.lyon@arm.com/","msgid":"<20230103102251.89478-1-christophe.lyon@arm.com>","list_archive_url":null,"date":"2023-01-03T10:22:50","name":"[arm] Fix PR18841 ifunc relocation ordering","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230103102251.89478-1-christophe.lyon@arm.com/mbox/"},{"id":38356,"url":"https://patchwork.plctlab.org/api/1.2/patches/38356/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230103102251.89478-2-christophe.lyon@arm.com/","msgid":"<20230103102251.89478-2-christophe.lyon@arm.com>","list_archive_url":null,"date":"2023-01-03T10:22:51","name":"[arm] Skip ld/pr23169 test on arm.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230103102251.89478-2-christophe.lyon@arm.com/mbox/"},{"id":38431,"url":"https://patchwork.plctlab.org/api/1.2/patches/38431/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230103135330.1225218-1-chigot@adacore.com/","msgid":"<20230103135330.1225218-1-chigot@adacore.com>","list_archive_url":null,"date":"2023-01-03T13:53:30","name":"configure: remove dependencies on gmp and mpfr when gdb is disabled","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230103135330.1225218-1-chigot@adacore.com/mbox/"},{"id":38506,"url":"https://patchwork.plctlab.org/api/1.2/patches/38506/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230103162543.2412854-1-chigot@adacore.com/","msgid":"<20230103162543.2412854-1-chigot@adacore.com>","list_archive_url":null,"date":"2023-01-03T16:25:43","name":"[v2] configure: remove dependencies on gmp and mpfr when gdb is disabled","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230103162543.2412854-1-chigot@adacore.com/mbox/"},{"id":38694,"url":"https://patchwork.plctlab.org/api/1.2/patches/38694/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230103214931.3320223-1-dilfridge@gentoo.org/","msgid":"<20230103214931.3320223-1-dilfridge@gentoo.org>","list_archive_url":null,"date":"2023-01-03T21:49:31","name":"ld testsuite: un-xfail pr19719 tests on aarch64, seems to succeed now","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230103214931.3320223-1-dilfridge@gentoo.org/mbox/"},{"id":38658,"url":"https://patchwork.plctlab.org/api/1.2/patches/38658/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230103215722.616744-1-jcmvbkbc@gmail.com/","msgid":"<20230103215722.616744-1-jcmvbkbc@gmail.com>","list_archive_url":null,"date":"2023-01-03T21:57:22","name":"[COMMITTED] opcodes: xtensa: implement styled disassembly","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230103215722.616744-1-jcmvbkbc@gmail.com/mbox/"},{"id":38659,"url":"https://patchwork.plctlab.org/api/1.2/patches/38659/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230103215746.616794-1-jcmvbkbc@gmail.com/","msgid":"<20230103215746.616794-1-jcmvbkbc@gmail.com>","list_archive_url":null,"date":"2023-01-03T21:57:46","name":"[COMMITTED] opcodes: xtensa: fix jump visualization for FLIX","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230103215746.616794-1-jcmvbkbc@gmail.com/mbox/"},{"id":38714,"url":"https://patchwork.plctlab.org/api/1.2/patches/38714/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230104011831.965647-1-indu.bhagat@oracle.com/","msgid":"<20230104011831.965647-1-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-01-04T01:18:31","name":"MAINTAINERS: add myself as maintainer of libsframe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230104011831.965647-1-indu.bhagat@oracle.com/mbox/"},{"id":38733,"url":"https://patchwork.plctlab.org/api/1.2/patches/38733/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230104041219.794237-1-guillermo.e.martinez@oracle.com/","msgid":"<20230104041219.794237-1-guillermo.e.martinez@oracle.com>","list_archive_url":null,"date":"2023-01-04T04:12:19","name":"Fix sim/testsuite/bpf due to linker warnings","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230104041219.794237-1-guillermo.e.martinez@oracle.com/mbox/"},{"id":38743,"url":"https://patchwork.plctlab.org/api/1.2/patches/38743/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230104055936.1130680-1-aurelien@aurel32.net/","msgid":"<20230104055936.1130680-1-aurelien@aurel32.net>","list_archive_url":null,"date":"2023-01-04T05:59:36","name":"RISC-V: fix JAL aliases ordering in opcode table","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230104055936.1130680-1-aurelien@aurel32.net/mbox/"},{"id":38774,"url":"https://patchwork.plctlab.org/api/1.2/patches/38774/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230104065611.377771-1-indu.bhagat@oracle.com/","msgid":"<20230104065611.377771-1-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-01-04T06:56:11","name":"libsframe: adjust an incorrect check in flip_sframe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230104065611.377771-1-indu.bhagat@oracle.com/mbox/"},{"id":38920,"url":"https://patchwork.plctlab.org/api/1.2/patches/38920/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y7V+MNgHYTpMBNw5@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-01-04T13:25:04","name":"addr2line out of memory on fuzzed file","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y7V+MNgHYTpMBNw5@squeak.grove.modra.org/mbox/"},{"id":38921,"url":"https://patchwork.plctlab.org/api/1.2/patches/38921/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y7V+U0bOlfYE++6E@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-01-04T13:25:39","name":"asan: segv in parse_module","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y7V+U0bOlfYE++6E@squeak.grove.modra.org/mbox/"},{"id":38922,"url":"https://patchwork.plctlab.org/api/1.2/patches/38922/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y7V+g16MZQvQAYgv@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-01-04T13:26:27","name":"fuzzed file timeout","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y7V+g16MZQvQAYgv@squeak.grove.modra.org/mbox/"},{"id":39067,"url":"https://patchwork.plctlab.org/api/1.2/patches/39067/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230104191414.149668-1-hjl.tools@gmail.com/","msgid":"<20230104191414.149668-1-hjl.tools@gmail.com>","list_archive_url":null,"date":"2023-01-04T19:14:14","name":"x86: Remove duplicated I386_PCREL_TYPE_P/X86_64_PCREL_TYPE_P","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230104191414.149668-1-hjl.tools@gmail.com/mbox/"},{"id":39123,"url":"https://patchwork.plctlab.org/api/1.2/patches/39123/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230104214109.51006-1-guillermo.e.martinez@oracle.com/","msgid":"<20230104214109.51006-1-guillermo.e.martinez@oracle.com>","list_archive_url":null,"date":"2023-01-04T21:41:09","name":"[PATCHv2] Fix sim/testsuite/bpf due to linker warnings","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230104214109.51006-1-guillermo.e.martinez@oracle.com/mbox/"},{"id":39188,"url":"https://patchwork.plctlab.org/api/1.2/patches/39188/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230105002743.25019-1-mark@harmstone.com/","msgid":"<20230105002743.25019-1-mark@harmstone.com>","list_archive_url":null,"date":"2023-01-05T00:27:43","name":"ld/testsuite: Fix test failures in pe.exp caused by 8819b236","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230105002743.25019-1-mark@harmstone.com/mbox/"},{"id":39795,"url":"https://patchwork.plctlab.org/api/1.2/patches/39795/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230105210542.3573076-1-maskray@google.com/","msgid":"<20230105210542.3573076-1-maskray@google.com>","list_archive_url":null,"date":"2023-01-05T21:05:42","name":"ld: Allow R_X86_64_GOTPCREL for call *__tls_get_addr@GOTPCREL(%rip)","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230105210542.3573076-1-maskray@google.com/mbox/"},{"id":39834,"url":"https://patchwork.plctlab.org/api/1.2/patches/39834/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230105230742.1097314-1-maskray@google.com/","msgid":"<20230105230742.1097314-1-maskray@google.com>","list_archive_url":null,"date":"2023-01-05T23:07:42","name":"ld: Allow R_386_GOT32 for call *__tls_get_addr@GOT(%reg)","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230105230742.1097314-1-maskray@google.com/mbox/"},{"id":39890,"url":"https://patchwork.plctlab.org/api/1.2/patches/39890/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230106012509.7918-1-mark@harmstone.com/","msgid":"<20230106012509.7918-1-mark@harmstone.com>","list_archive_url":null,"date":"2023-01-06T01:25:03","name":"[1/7] Fix size of external_reloc for pe-aarch64","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230106012509.7918-1-mark@harmstone.com/mbox/"},{"id":39891,"url":"https://patchwork.plctlab.org/api/1.2/patches/39891/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230106012509.7918-2-mark@harmstone.com/","msgid":"<20230106012509.7918-2-mark@harmstone.com>","list_archive_url":null,"date":"2023-01-06T01:25:04","name":"[2/7] Skip ELF-specific tests when targeting pe-aarch64","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230106012509.7918-2-mark@harmstone.com/mbox/"},{"id":39892,"url":"https://patchwork.plctlab.org/api/1.2/patches/39892/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230106012509.7918-3-mark@harmstone.com/","msgid":"<20230106012509.7918-3-mark@harmstone.com>","list_archive_url":null,"date":"2023-01-06T01:25:05","name":"[3/7] Skip big-obj test for pe-aarch64","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230106012509.7918-3-mark@harmstone.com/mbox/"},{"id":39896,"url":"https://patchwork.plctlab.org/api/1.2/patches/39896/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230106012509.7918-4-mark@harmstone.com/","msgid":"<20230106012509.7918-4-mark@harmstone.com>","list_archive_url":null,"date":"2023-01-06T01:25:06","name":"[4/7] Add pe-aarch64 relocations","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230106012509.7918-4-mark@harmstone.com/mbox/"},{"id":39894,"url":"https://patchwork.plctlab.org/api/1.2/patches/39894/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230106012509.7918-5-mark@harmstone.com/","msgid":"<20230106012509.7918-5-mark@harmstone.com>","list_archive_url":null,"date":"2023-01-06T01:25:07","name":"[5/7] Add .secrel32 for pe-aarch64","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230106012509.7918-5-mark@harmstone.com/mbox/"},{"id":39893,"url":"https://patchwork.plctlab.org/api/1.2/patches/39893/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230106012509.7918-6-mark@harmstone.com/","msgid":"<20230106012509.7918-6-mark@harmstone.com>","list_archive_url":null,"date":"2023-01-06T01:25:08","name":"[6/7] Add aarch64-w64-mingw32 target","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230106012509.7918-6-mark@harmstone.com/mbox/"},{"id":39895,"url":"https://patchwork.plctlab.org/api/1.2/patches/39895/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230106012509.7918-7-mark@harmstone.com/","msgid":"<20230106012509.7918-7-mark@harmstone.com>","list_archive_url":null,"date":"2023-01-06T01:25:09","name":"[7/7] gas: Restore tc_pe_dwarf2_emit_offset for pe-aarch64","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230106012509.7918-7-mark@harmstone.com/mbox/"},{"id":39967,"url":"https://patchwork.plctlab.org/api/1.2/patches/39967/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230106064053.984817-1-indu.bhagat@oracle.com/","msgid":"<20230106064053.984817-1-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-01-06T06:40:53","name":"sframe: fix the defined SFRAME_FRE_TYPE_*_LIMIT constants","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230106064053.984817-1-indu.bhagat@oracle.com/mbox/"},{"id":39979,"url":"https://patchwork.plctlab.org/api/1.2/patches/39979/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230106075816.387489-1-guillermo.e.martinez@oracle.com/","msgid":"<20230106075816.387489-1-guillermo.e.martinez@oracle.com>","list_archive_url":null,"date":"2023-01-06T07:58:16","name":"bpf: fix error conversion from long unsigned int to unsigned int [-Werror=overflow]","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230106075816.387489-1-guillermo.e.martinez@oracle.com/mbox/"},{"id":40061,"url":"https://patchwork.plctlab.org/api/1.2/patches/40061/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b7e9975b-086f-a9f6-ab6b-0181d50187e1@suse.com/","msgid":"","list_archive_url":null,"date":"2023-01-06T09:33:00","name":"ld: yet another PDB build fix (or workaround)","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b7e9975b-086f-a9f6-ab6b-0181d50187e1@suse.com/mbox/"},{"id":40085,"url":"https://patchwork.plctlab.org/api/1.2/patches/40085/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y7f7RLzDodzChR88@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-01-06T10:43:16","name":"Make coff backend data read-only","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y7f7RLzDodzChR88@squeak.grove.modra.org/mbox/"},{"id":40086,"url":"https://patchwork.plctlab.org/api/1.2/patches/40086/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y7f7chtgwRfAVNME@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-01-06T10:44:02","name":"Tidy pe flag in coff_data","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y7f7chtgwRfAVNME@squeak.grove.modra.org/mbox/"},{"id":40087,"url":"https://patchwork.plctlab.org/api/1.2/patches/40087/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y7f7lGQlMvLz157a@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-01-06T10:44:36","name":"Fix an aout memory leak","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y7f7lGQlMvLz157a@squeak.grove.modra.org/mbox/"},{"id":40114,"url":"https://patchwork.plctlab.org/api/1.2/patches/40114/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6c9f38b9-c582-3a1a-55ce-bb9966940a80@suse.com/","msgid":"<6c9f38b9-c582-3a1a-55ce-bb9966940a80@suse.com>","list_archive_url":null,"date":"2023-01-06T12:34:46","name":"gas/RISC-V: adjust assembler for opcode table re-ordering","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6c9f38b9-c582-3a1a-55ce-bb9966940a80@suse.com/mbox/"},{"id":40415,"url":"https://patchwork.plctlab.org/api/1.2/patches/40415/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230107154743.624854-1-guillermo.e.martinez@oracle.com/","msgid":"<20230107154743.624854-1-guillermo.e.martinez@oracle.com>","list_archive_url":null,"date":"2023-01-07T15:47:43","name":"bpf: fix error conversion from long unsigned int to unsigned int [-Werror=overflow]","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230107154743.624854-1-guillermo.e.martinez@oracle.com/mbox/"},{"id":40698,"url":"https://patchwork.plctlab.org/api/1.2/patches/40698/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230109083526.74448-1-mengqinggang@loongson.cn/","msgid":"<20230109083526.74448-1-mengqinggang@loongson.cn>","list_archive_url":null,"date":"2023-01-09T08:35:26","name":"LoongArch: ld: Fix hidden ifunc symbol linker error bug.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230109083526.74448-1-mengqinggang@loongson.cn/mbox/"},{"id":41215,"url":"https://patchwork.plctlab.org/api/1.2/patches/41215/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y7ygyYa8VydFJqaD@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-01-09T23:18:33","name":"Move bfd_init to bfd.c","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y7ygyYa8VydFJqaD@squeak.grove.modra.org/mbox/"},{"id":41216,"url":"https://patchwork.plctlab.org/api/1.2/patches/41216/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y7yg79B/YO6FUkMB@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-01-09T23:19:11","name":"Move mips_refhi_list to bfd tdata","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y7yg79B/YO6FUkMB@squeak.grove.modra.org/mbox/"},{"id":41226,"url":"https://patchwork.plctlab.org/api/1.2/patches/41226/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y7ylp96AC5XxPRgq@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-01-09T23:39:19","name":"peXXigen.c sanity checks","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y7ylp96AC5XxPRgq@squeak.grove.modra.org/mbox/"},{"id":41227,"url":"https://patchwork.plctlab.org/api/1.2/patches/41227/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y7yl1F46NAHWkWo5@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-01-09T23:40:04","name":"Set dwarf2 stash pointer earlier","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y7yl1F46NAHWkWo5@squeak.grove.modra.org/mbox/"},{"id":41452,"url":"https://patchwork.plctlab.org/api/1.2/patches/41452/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230110130050.366404-2-nick.alcock@oracle.com/","msgid":"<20230110130050.366404-2-nick.alcock@oracle.com>","list_archive_url":null,"date":"2023-01-10T13:00:48","name":"[v2,1/3] ctf: fix various dreadful typos in the ctf_archive format comments","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230110130050.366404-2-nick.alcock@oracle.com/mbox/"},{"id":41453,"url":"https://patchwork.plctlab.org/api/1.2/patches/41453/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230110130050.366404-3-nick.alcock@oracle.com/","msgid":"<20230110130050.366404-3-nick.alcock@oracle.com>","list_archive_url":null,"date":"2023-01-10T13:00:49","name":"[v2,2/3] libctf: skip the testsuite from inside dejagnu","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230110130050.366404-3-nick.alcock@oracle.com/mbox/"},{"id":41454,"url":"https://patchwork.plctlab.org/api/1.2/patches/41454/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230110130050.366404-4-nick.alcock@oracle.com/","msgid":"<20230110130050.366404-4-nick.alcock@oracle.com>","list_archive_url":null,"date":"2023-01-10T13:00:50","name":"[v2,3/3] libctf: ctf-link outdated input check faulty","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230110130050.366404-4-nick.alcock@oracle.com/mbox/"},{"id":41470,"url":"https://patchwork.plctlab.org/api/1.2/patches/41470/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230110133534.5295-1-stefansf@linux.ibm.com/","msgid":"<20230110133534.5295-1-stefansf@linux.ibm.com>","list_archive_url":null,"date":"2023-01-10T13:35:35","name":"IBM zSystems: Fix offset relative to static TLS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230110133534.5295-1-stefansf@linux.ibm.com/mbox/"},{"id":41571,"url":"https://patchwork.plctlab.org/api/1.2/patches/41571/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230110182745.3641128-1-indu.bhagat@oracle.com/","msgid":"<20230110182745.3641128-1-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-01-10T18:27:45","name":"libsframe: replace an strncat with strcat","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230110182745.3641128-1-indu.bhagat@oracle.com/mbox/"},{"id":41761,"url":"https://patchwork.plctlab.org/api/1.2/patches/41761/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y75R4sYOPg/8UuHm@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-01-11T06:06:26","name":"now_seg after closing output file","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y75R4sYOPg/8UuHm@squeak.grove.modra.org/mbox/"},{"id":41817,"url":"https://patchwork.plctlab.org/api/1.2/patches/41817/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y751L9gX14jBBlO0@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-01-11T08:37:03","name":"Tidy some global bfd state used by gas","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y751L9gX14jBBlO0@squeak.grove.modra.org/mbox/"},{"id":41974,"url":"https://patchwork.plctlab.org/api/1.2/patches/41974/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y762S0diPNqwWu1a@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-01-11T13:14:51","name":"Fix XPASS weak symbols on x86_64-mingw32","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y762S0diPNqwWu1a@squeak.grove.modra.org/mbox/"},{"id":42134,"url":"https://patchwork.plctlab.org/api/1.2/patches/42134/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230111183204.11600-1-mark@harmstone.com/","msgid":"<20230111183204.11600-1-mark@harmstone.com>","list_archive_url":null,"date":"2023-01-11T18:32:04","name":"Use subsystem to distinguish between pei-arm-little and pei-arm-wince-little","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230111183204.11600-1-mark@harmstone.com/mbox/"},{"id":42262,"url":"https://patchwork.plctlab.org/api/1.2/patches/42262/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y7+tQPYaY/skpLIf@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-01-12T06:48:32","name":"Remove myself as hppa32 maintainer","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y7+tQPYaY/skpLIf@squeak.grove.modra.org/mbox/"},{"id":42263,"url":"https://patchwork.plctlab.org/api/1.2/patches/42263/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y7+tkeiBByVJdca3@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-01-12T06:49:53","name":"Use __func__ rather than __FUNCTION__","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y7+tkeiBByVJdca3@squeak.grove.modra.org/mbox/"},{"id":42799,"url":"https://patchwork.plctlab.org/api/1.2/patches/42799/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230112205654.3456561-1-vladimir.mezentsev@oracle.com/","msgid":"<20230112205654.3456561-1-vladimir.mezentsev@oracle.com>","list_archive_url":null,"date":"2023-01-12T20:56:54","name":"gprofng: PR29987 bfd/archive.c:1447: undefined reference to `filename_ncmp'\''","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230112205654.3456561-1-vladimir.mezentsev@oracle.com/mbox/"},{"id":43131,"url":"https://patchwork.plctlab.org/api/1.2/patches/43131/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/95936261-d824-9128-1be9-ba7dfe12b042@suse.com/","msgid":"<95936261-d824-9128-1be9-ba7dfe12b042@suse.com>","list_archive_url":null,"date":"2023-01-13T10:19:19","name":"[1/3] RISC-V: prefer SLT{,U} aliases for SLTI{,U}","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/95936261-d824-9128-1be9-ba7dfe12b042@suse.com/mbox/"},{"id":43133,"url":"https://patchwork.plctlab.org/api/1.2/patches/43133/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/63fa0796-59e6-6429-6c86-b8707cc9f8d9@suse.com/","msgid":"<63fa0796-59e6-6429-6c86-b8707cc9f8d9@suse.com>","list_archive_url":null,"date":"2023-01-13T10:19:51","name":"[2/3] RISC-V: move OR and XOR aliases down","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/63fa0796-59e6-6429-6c86-b8707cc9f8d9@suse.com/mbox/"},{"id":43134,"url":"https://patchwork.plctlab.org/api/1.2/patches/43134/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/448243b9-8134-f981-8e66-635790d4e680@suse.com/","msgid":"<448243b9-8134-f981-8e66-635790d4e680@suse.com>","list_archive_url":null,"date":"2023-01-13T10:20:23","name":"[3/3] RISC-V: prefer FSRM/FSFLAGS aliases for FSRMI/FSFLAGSI","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/448243b9-8134-f981-8e66-635790d4e680@suse.com/mbox/"},{"id":43166,"url":"https://patchwork.plctlab.org/api/1.2/patches/43166/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/55dd0365-1b8c-45d0-cb85-fc8ebdc2ac21@suse.com/","msgid":"<55dd0365-1b8c-45d0-cb85-fc8ebdc2ac21@suse.com>","list_archive_url":null,"date":"2023-01-13T11:05:43","name":"[1/8] x86: abstract out obtaining of a template'\''s mnemonic","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/55dd0365-1b8c-45d0-cb85-fc8ebdc2ac21@suse.com/mbox/"},{"id":43167,"url":"https://patchwork.plctlab.org/api/1.2/patches/43167/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fa681978-5ee6-16ba-3f08-958f6d1cf805@suse.com/","msgid":"","list_archive_url":null,"date":"2023-01-13T11:06:32","name":"[1/8] x86: move insn mnemonics to a separate table","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fa681978-5ee6-16ba-3f08-958f6d1cf805@suse.com/mbox/"},{"id":43168,"url":"https://patchwork.plctlab.org/api/1.2/patches/43168/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d87c0ed5-4678-d8ea-9744-7447ff82a843@suse.com/","msgid":"","list_archive_url":null,"date":"2023-01-13T11:07:24","name":"[3/8] x86: re-use insn mnemonic strings as much as possible","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d87c0ed5-4678-d8ea-9744-7447ff82a843@suse.com/mbox/"},{"id":43169,"url":"https://patchwork.plctlab.org/api/1.2/patches/43169/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8f43bf06-9323-8838-bcdc-bfbf9a850ae2@suse.com/","msgid":"<8f43bf06-9323-8838-bcdc-bfbf9a850ae2@suse.com>","list_archive_url":null,"date":"2023-01-13T11:07:46","name":"[4/8] x86: absorb allocation in i386-gen","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8f43bf06-9323-8838-bcdc-bfbf9a850ae2@suse.com/mbox/"},{"id":43170,"url":"https://patchwork.plctlab.org/api/1.2/patches/43170/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c60483a9-14fc-f2f4-0185-80c2510e45a5@suse.com/","msgid":"","list_archive_url":null,"date":"2023-01-13T11:08:33","name":"[5/8] x86: avoid strcmp() in a few places","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c60483a9-14fc-f2f4-0185-80c2510e45a5@suse.com/mbox/"},{"id":43171,"url":"https://patchwork.plctlab.org/api/1.2/patches/43171/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1c763a63-05e0-33e8-c9c4-48a26cbc5db7@suse.com/","msgid":"<1c763a63-05e0-33e8-c9c4-48a26cbc5db7@suse.com>","list_archive_url":null,"date":"2023-01-13T11:10:03","name":"[6/8] x86: embed register names in reg_entry","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1c763a63-05e0-33e8-c9c4-48a26cbc5db7@suse.com/mbox/"},{"id":43172,"url":"https://patchwork.plctlab.org/api/1.2/patches/43172/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8a6f1fce-435a-b8fa-44a3-c7ae2c621968@suse.com/","msgid":"<8a6f1fce-435a-b8fa-44a3-c7ae2c621968@suse.com>","list_archive_url":null,"date":"2023-01-13T11:11:01","name":"[7/8] x86: embed register and alike names in disassembler","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8a6f1fce-435a-b8fa-44a3-c7ae2c621968@suse.com/mbox/"},{"id":43174,"url":"https://patchwork.plctlab.org/api/1.2/patches/43174/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1d538fdf-536a-37b0-556b-b4ca86b0a090@suse.com/","msgid":"<1d538fdf-536a-37b0-556b-b4ca86b0a090@suse.com>","list_archive_url":null,"date":"2023-01-13T11:11:37","name":"[8/8] x86: split i386-gen'\''s opcode hash entry struct","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1d538fdf-536a-37b0-556b-b4ca86b0a090@suse.com/mbox/"},{"id":43288,"url":"https://patchwork.plctlab.org/api/1.2/patches/43288/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230113125454.75744-1-cooper.qu@linux.alibaba.com/","msgid":"<20230113125454.75744-1-cooper.qu@linux.alibaba.com>","list_archive_url":null,"date":"2023-01-13T12:54:54","name":"C-SKY: Fix machine flag.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230113125454.75744-1-cooper.qu@linux.alibaba.com/mbox/"},{"id":43355,"url":"https://patchwork.plctlab.org/api/1.2/patches/43355/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/OS3P286MB2152AC3F96A88680022D57ADF0C29@OS3P286MB2152.JPNP286.PROD.OUTLOOK.COM/","msgid":"","list_archive_url":null,"date":"2023-01-13T14:42:32","name":"libctf: update regexp to allow makeinfo to build document","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/OS3P286MB2152AC3F96A88680022D57ADF0C29@OS3P286MB2152.JPNP286.PROD.OUTLOOK.COM/mbox/"},{"id":43695,"url":"https://patchwork.plctlab.org/api/1.2/patches/43695/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/OS3P286MB2152CCD151694D02E2A84D23F0C39@OS3P286MB2152.JPNP286.PROD.OUTLOOK.COM/","msgid":"","list_archive_url":null,"date":"2023-01-14T04:23:26","name":"[v2] libctf: update regexp to allow makeinfo to build document","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/OS3P286MB2152CCD151694D02E2A84D23F0C39@OS3P286MB2152.JPNP286.PROD.OUTLOOK.COM/mbox/"},{"id":44089,"url":"https://patchwork.plctlab.org/api/1.2/patches/44089/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y8U25YxsSHWBz8of@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-01-16T11:37:09","name":"PR29991, MicroMIPS flag erased after align directives","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y8U25YxsSHWBz8of@squeak.grove.modra.org/mbox/"},{"id":44107,"url":"https://patchwork.plctlab.org/api/1.2/patches/44107/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y8VJCZte0qnkPRWk@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-01-16T12:54:33","name":"COFF CALC_ADDEND comment","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y8VJCZte0qnkPRWk@squeak.grove.modra.org/mbox/"},{"id":44109,"url":"https://patchwork.plctlab.org/api/1.2/patches/44109/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y8VJdIvu7DGz4i7I@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-01-16T12:56:20","name":"Leftover hack from i960-coff","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y8VJdIvu7DGz4i7I@squeak.grove.modra.org/mbox/"},{"id":44111,"url":"https://patchwork.plctlab.org/api/1.2/patches/44111/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y8VJxpkPeEvO360+@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-01-16T12:57:42","name":"Tidy gas/expr.c static state","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y8VJxpkPeEvO360+@squeak.grove.modra.org/mbox/"},{"id":44146,"url":"https://patchwork.plctlab.org/api/1.2/patches/44146/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y8VRUsfXY5Vjk5A1@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-01-16T13:29:54","name":"Correct ld-pe/aarch64.d test output","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y8VRUsfXY5Vjk5A1@squeak.grove.modra.org/mbox/"},{"id":44218,"url":"https://patchwork.plctlab.org/api/1.2/patches/44218/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1ff07fee-24f1-7aeb-8fb6-44457af557c4@arm.com/","msgid":"<1ff07fee-24f1-7aeb-8fb6-44457af557c4@arm.com>","list_archive_url":null,"date":"2023-01-16T15:14:42","name":"[PING,1/2] gas: arm: Fix a further IT-predicated vcvt issue in the presense of MVE vcvtn","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1ff07fee-24f1-7aeb-8fb6-44457af557c4@arm.com/mbox/"},{"id":44219,"url":"https://patchwork.plctlab.org/api/1.2/patches/44219/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0b4d01ad-38b9-428e-39af-3ff452f94ef2@arm.com/","msgid":"<0b4d01ad-38b9-428e-39af-3ff452f94ef2@arm.com>","list_archive_url":null,"date":"2023-01-16T15:14:55","name":"[PING,2/2] gas: arm: Change warning message to not reference specific A-class architecture revision","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0b4d01ad-38b9-428e-39af-3ff452f94ef2@arm.com/mbox/"},{"id":44644,"url":"https://patchwork.plctlab.org/api/1.2/patches/44644/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/yddbkmx8kt8.fsf@CeBiTec.Uni-Bielefeld.DE/","msgid":"","list_archive_url":null,"date":"2023-01-17T11:25:23","name":"i386: Don'\''t emit unsupported TLS relocs on Solaris [PR13671]","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/yddbkmx8kt8.fsf@CeBiTec.Uni-Bielefeld.DE/mbox/"},{"id":44718,"url":"https://patchwork.plctlab.org/api/1.2/patches/44718/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230117154125.601189-1-hjl.tools@gmail.com/","msgid":"<20230117154125.601189-1-hjl.tools@gmail.com>","list_archive_url":null,"date":"2023-01-17T15:41:25","name":"ld: Use run_cc_link_tests for PR ld/26391 tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230117154125.601189-1-hjl.tools@gmail.com/mbox/"},{"id":44872,"url":"https://patchwork.plctlab.org/api/1.2/patches/44872/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230118001851.3467920-1-indu.bhagat@oracle.com/","msgid":"<20230118001851.3467920-1-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-01-18T00:18:51","name":"toplevel: Makefile.def: add install-strip dependency on libsframe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230118001851.3467920-1-indu.bhagat@oracle.com/mbox/"},{"id":44975,"url":"https://patchwork.plctlab.org/api/1.2/patches/44975/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230118051136.10243-1-mark@harmstone.com/","msgid":"<20230118051136.10243-1-mark@harmstone.com>","list_archive_url":null,"date":"2023-01-18T05:11:36","name":"ld: Fix ADDR32/64 incorrect outputs in pe-aarch64","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230118051136.10243-1-mark@harmstone.com/mbox/"},{"id":44995,"url":"https://patchwork.plctlab.org/api/1.2/patches/44995/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230118062657.1125934-2-amodra@gmail.com/","msgid":"<20230118062657.1125934-2-amodra@gmail.com>","list_archive_url":null,"date":"2023-01-18T06:26:54","name":"[1/4] howto install_addend","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230118062657.1125934-2-amodra@gmail.com/mbox/"},{"id":44994,"url":"https://patchwork.plctlab.org/api/1.2/patches/44994/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230118062657.1125934-3-amodra@gmail.com/","msgid":"<20230118062657.1125934-3-amodra@gmail.com>","list_archive_url":null,"date":"2023-01-18T06:26:55","name":"[2/4] coff-aarch64.c howtos","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230118062657.1125934-3-amodra@gmail.com/mbox/"},{"id":44999,"url":"https://patchwork.plctlab.org/api/1.2/patches/44999/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230118062657.1125934-4-amodra@gmail.com/","msgid":"<20230118062657.1125934-4-amodra@gmail.com>","list_archive_url":null,"date":"2023-01-18T06:26:56","name":"[3/4] Correct coff-aarch64 howtos and delete unnecessary special functions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230118062657.1125934-4-amodra@gmail.com/mbox/"},{"id":44998,"url":"https://patchwork.plctlab.org/api/1.2/patches/44998/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230118062657.1125934-5-amodra@gmail.com/","msgid":"<20230118062657.1125934-5-amodra@gmail.com>","list_archive_url":null,"date":"2023-01-18T06:26:57","name":"[4/4] The fuzzers have found the reloc special functions in coff-aarch64.c","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230118062657.1125934-5-amodra@gmail.com/mbox/"},{"id":45183,"url":"https://patchwork.plctlab.org/api/1.2/patches/45183/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/87y1q013k1.fsf@redhat.com/","msgid":"<87y1q013k1.fsf@redhat.com>","list_archive_url":null,"date":"2023-01-18T11:32:14","name":"Commit: Improve the performance of objcopy'\''s note merging algorithm","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/87y1q013k1.fsf@redhat.com/mbox/"},{"id":45396,"url":"https://patchwork.plctlab.org/api/1.2/patches/45396/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.LSU.2.20.2301181731360.30340@wotan.suse.de/","msgid":"","list_archive_url":null,"date":"2023-01-18T17:31:54","name":"[1/3] Faster string merging","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.LSU.2.20.2301181731360.30340@wotan.suse.de/mbox/"},{"id":45399,"url":"https://patchwork.plctlab.org/api/1.2/patches/45399/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.LSU.2.20.2301181731590.30340@wotan.suse.de/","msgid":"","list_archive_url":null,"date":"2023-01-18T17:32:09","name":"[2/3] arm32: Fix rodata-merge-map","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.LSU.2.20.2301181731590.30340@wotan.suse.de/mbox/"},{"id":45395,"url":"https://patchwork.plctlab.org/api/1.2/patches/45395/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.LSU.2.20.2301181732140.30340@wotan.suse.de/","msgid":"","list_archive_url":null,"date":"2023-01-18T17:32:24","name":"[3/3] Add testcase ld-elf/merge4","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.LSU.2.20.2301181732140.30340@wotan.suse.de/mbox/"},{"id":45571,"url":"https://patchwork.plctlab.org/api/1.2/patches/45571/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230119035126.1172654-1-raj.khem@gmail.com/","msgid":"<20230119035126.1172654-1-raj.khem@gmail.com>","list_archive_url":null,"date":"2023-01-19T03:51:26","name":"Remove duplicate pe-dll.o entry deom targ_extra_ofiles","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230119035126.1172654-1-raj.khem@gmail.com/mbox/"},{"id":45616,"url":"https://patchwork.plctlab.org/api/1.2/patches/45616/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y8juE1B+0XLFwkuv@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-01-19T07:15:31","name":"PR 30022, concurrent builds can fail","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y8juE1B+0XLFwkuv@squeak.grove.modra.org/mbox/"},{"id":45640,"url":"https://patchwork.plctlab.org/api/1.2/patches/45640/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y8j634999Uh3otCN@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-01-19T08:10:07","name":"Reinitialise macro_nest","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y8j634999Uh3otCN@squeak.grove.modra.org/mbox/"},{"id":45960,"url":"https://patchwork.plctlab.org/api/1.2/patches/45960/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230119205932.3025258-1-indu.bhagat@oracle.com/","msgid":"<20230119205932.3025258-1-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-01-19T20:59:32","name":"[COMMITTED] libsframe: Use AM_SILENT_RULES macro in configure.ac","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230119205932.3025258-1-indu.bhagat@oracle.com/mbox/"},{"id":45961,"url":"https://patchwork.plctlab.org/api/1.2/patches/45961/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y8mwO5KmTqXAtFhC@fedora/","msgid":"","list_archive_url":null,"date":"2023-01-19T21:03:55","name":"Add OpenBSD ARM GAS support.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y8mwO5KmTqXAtFhC@fedora/mbox/"},{"id":46019,"url":"https://patchwork.plctlab.org/api/1.2/patches/46019/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230119214728.3208371-1-indu.bhagat@oracle.com/","msgid":"<20230119214728.3208371-1-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-01-19T21:47:28","name":"doc: sframe: fix some warnings","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230119214728.3208371-1-indu.bhagat@oracle.com/mbox/"},{"id":46256,"url":"https://patchwork.plctlab.org/api/1.2/patches/46256/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/98a5c1d5-00c9-75b3-db8c-019e056d720c@suse.com/","msgid":"<98a5c1d5-00c9-75b3-db8c-019e056d720c@suse.com>","list_archive_url":null,"date":"2023-01-20T09:30:48","name":"[1/2] x86: remove internationalization from i386-gen.c","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/98a5c1d5-00c9-75b3-db8c-019e056d720c@suse.com/mbox/"},{"id":46257,"url":"https://patchwork.plctlab.org/api/1.2/patches/46257/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c2aea3ae-6280-ad3d-2657-ad54f5d5b6bc@suse.com/","msgid":"","list_archive_url":null,"date":"2023-01-20T09:31:27","name":"[2/2] opcodes: suppress internationalization on build helper tools","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c2aea3ae-6280-ad3d-2657-ad54f5d5b6bc@suse.com/mbox/"},{"id":46268,"url":"https://patchwork.plctlab.org/api/1.2/patches/46268/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b8481a70-fa06-a794-ba34-555e712d679f@suse.com/","msgid":"","list_archive_url":null,"date":"2023-01-20T09:55:26","name":"x86/Intel: improve special casing of certain insns","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b8481a70-fa06-a794-ba34-555e712d679f@suse.com/mbox/"},{"id":46274,"url":"https://patchwork.plctlab.org/api/1.2/patches/46274/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1299219c-8f54-8672-a898-3aa1acc2b9ec@suse.com/","msgid":"<1299219c-8f54-8672-a898-3aa1acc2b9ec@suse.com>","list_archive_url":null,"date":"2023-01-20T10:00:13","name":"[1/3] x86: use ModR/M for FPU insns with operands","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1299219c-8f54-8672-a898-3aa1acc2b9ec@suse.com/mbox/"},{"id":46276,"url":"https://patchwork.plctlab.org/api/1.2/patches/46276/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7882acac-b12c-ac86-77f7-063ecd07e799@suse.com/","msgid":"<7882acac-b12c-ac86-77f7-063ecd07e799@suse.com>","list_archive_url":null,"date":"2023-01-20T10:00:35","name":"[2/3] x86: drop dead SSE2AVX-related code","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7882acac-b12c-ac86-77f7-063ecd07e799@suse.com/mbox/"},{"id":46275,"url":"https://patchwork.plctlab.org/api/1.2/patches/46275/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/44a44856-b7b2-5236-9d5e-6c681fc0fb82@suse.com/","msgid":"<44a44856-b7b2-5236-9d5e-6c681fc0fb82@suse.com>","list_archive_url":null,"date":"2023-01-20T10:00:54","name":"[3/3] x86: move reg_operands adjustment","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/44a44856-b7b2-5236-9d5e-6c681fc0fb82@suse.com/mbox/"},{"id":46588,"url":"https://patchwork.plctlab.org/api/1.2/patches/46588/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230120191842.3799467-1-indu.bhagat@oracle.com/","msgid":"<20230120191842.3799467-1-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-01-20T19:18:42","name":"[COMMITTED] Upload SFrame spec files as well","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230120191842.3799467-1-indu.bhagat@oracle.com/mbox/"},{"id":46609,"url":"https://patchwork.plctlab.org/api/1.2/patches/46609/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230120195532.917113-2-christoph.muellner@vrull.eu/","msgid":"<20230120195532.917113-2-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2023-01-20T19:55:27","name":"[RFC,v2,1/6] RISC-V: Add Zvkb ISA extension support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230120195532.917113-2-christoph.muellner@vrull.eu/mbox/"},{"id":46608,"url":"https://patchwork.plctlab.org/api/1.2/patches/46608/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230120195532.917113-3-christoph.muellner@vrull.eu/","msgid":"<20230120195532.917113-3-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2023-01-20T19:55:28","name":"[RFC,v2,2/6] RISC-V: Add Zvkg ISA extension support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230120195532.917113-3-christoph.muellner@vrull.eu/mbox/"},{"id":46612,"url":"https://patchwork.plctlab.org/api/1.2/patches/46612/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230120195532.917113-4-christoph.muellner@vrull.eu/","msgid":"<20230120195532.917113-4-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2023-01-20T19:55:29","name":"[RFC,v2,3/6] RISC-V: Add Zvknh[a,b] ISA extension support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230120195532.917113-4-christoph.muellner@vrull.eu/mbox/"},{"id":46611,"url":"https://patchwork.plctlab.org/api/1.2/patches/46611/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230120195532.917113-5-christoph.muellner@vrull.eu/","msgid":"<20230120195532.917113-5-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2023-01-20T19:55:30","name":"[RFC,v2,4/6] RISC-V: Add Zvkns ISA extension support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230120195532.917113-5-christoph.muellner@vrull.eu/mbox/"},{"id":46610,"url":"https://patchwork.plctlab.org/api/1.2/patches/46610/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230120195532.917113-6-christoph.muellner@vrull.eu/","msgid":"<20230120195532.917113-6-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2023-01-20T19:55:31","name":"[RFC,v2,5/6] RISC-V: Add Zvksed ISA extension support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230120195532.917113-6-christoph.muellner@vrull.eu/mbox/"},{"id":46613,"url":"https://patchwork.plctlab.org/api/1.2/patches/46613/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230120195532.917113-7-christoph.muellner@vrull.eu/","msgid":"<20230120195532.917113-7-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2023-01-20T19:55:32","name":"[RFC,v2,6/6] RISC-V: Add Zvksh ISA extension support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230120195532.917113-7-christoph.muellner@vrull.eu/mbox/"},{"id":46737,"url":"https://patchwork.plctlab.org/api/1.2/patches/46737/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230121002935.1139281-1-philipp.tomsich@vrull.eu/","msgid":"<20230121002935.1139281-1-philipp.tomsich@vrull.eu>","list_archive_url":null,"date":"2023-01-21T00:29:34","name":"[RFC,v1] RISC-V: Support Zicond extension","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230121002935.1139281-1-philipp.tomsich@vrull.eu/mbox/"},{"id":46985,"url":"https://patchwork.plctlab.org/api/1.2/patches/46985/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230122180736.55917-1-och95@yandex.ru/","msgid":"<20230122180736.55917-1-och95@yandex.ru>","list_archive_url":null,"date":"2023-01-22T18:07:36","name":"objdump: Fix relocations objdumping for specific symbol","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230122180736.55917-1-och95@yandex.ru/mbox/"},{"id":47021,"url":"https://patchwork.plctlab.org/api/1.2/patches/47021/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230122235733.4160-1-mark@harmstone.com/","msgid":"<20230122235733.4160-1-mark@harmstone.com>","list_archive_url":null,"date":"2023-01-22T23:57:33","name":"ld: Set default subsystem for arm-pe to IMAGE_SUBSYSTEM_WINDOWS_GUI","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230122235733.4160-1-mark@harmstone.com/mbox/"},{"id":47022,"url":"https://patchwork.plctlab.org/api/1.2/patches/47022/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230123003231.3100-1-mark@harmstone.com/","msgid":"<20230123003231.3100-1-mark@harmstone.com>","list_archive_url":null,"date":"2023-01-23T00:32:31","name":"Add support for secidx relocations to aarch64-w64-mingw32","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230123003231.3100-1-mark@harmstone.com/mbox/"},{"id":47041,"url":"https://patchwork.plctlab.org/api/1.2/patches/47041/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230123045058.449255-1-vladimir.mezentsev@oracle.com/","msgid":"<20230123045058.449255-1-vladimir.mezentsev@oracle.com>","list_archive_url":null,"date":"2023-01-23T04:50:58","name":"gprofng: PR29521 [docs] man pages are not in the release tarball","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230123045058.449255-1-vladimir.mezentsev@oracle.com/mbox/"},{"id":47453,"url":"https://patchwork.plctlab.org/api/1.2/patches/47453/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230123230154.17957-1-mark@harmstone.com/","msgid":"<20230123230154.17957-1-mark@harmstone.com>","list_archive_url":null,"date":"2023-01-23T23:01:54","name":"ld: Add pdb support to aarch64-w64-mingw32","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230123230154.17957-1-mark@harmstone.com/mbox/"},{"id":47706,"url":"https://patchwork.plctlab.org/api/1.2/patches/47706/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230124133641.258195-1-och95@yandex.ru/","msgid":"<20230124133641.258195-1-och95@yandex.ru>","list_archive_url":null,"date":"2023-01-24T13:36:41","name":"Fix emit-relocs for aarch64 gold","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230124133641.258195-1-och95@yandex.ru/mbox/"},{"id":47709,"url":"https://patchwork.plctlab.org/api/1.2/patches/47709/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230124134202.2452845-1-felix.willgerodt@intel.com/","msgid":"<20230124134202.2452845-1-felix.willgerodt@intel.com>","list_archive_url":null,"date":"2023-01-24T13:42:02","name":"[1/1] bfd, gdb: fix missing \"Core was generated by\" when loading a x32 corefile.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230124134202.2452845-1-felix.willgerodt@intel.com/mbox/"},{"id":47742,"url":"https://patchwork.plctlab.org/api/1.2/patches/47742/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4e1ac6f6-8aa5-9605-0969-40f66549c181@suse.com/","msgid":"<4e1ac6f6-8aa5-9605-0969-40f66549c181@suse.com>","list_archive_url":null,"date":"2023-01-24T15:24:32","name":"RISC-V: make C-extension JAL available again for (32-bit) assembly","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4e1ac6f6-8aa5-9605-0969-40f66549c181@suse.com/mbox/"},{"id":47994,"url":"https://patchwork.plctlab.org/api/1.2/patches/47994/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230125012024.6317-1-mark@harmstone.com/","msgid":"<20230125012024.6317-1-mark@harmstone.com>","list_archive_url":null,"date":"2023-01-25T01:20:24","name":"ld/testsuite: Add missing targets to PDB tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230125012024.6317-1-mark@harmstone.com/mbox/"},{"id":48216,"url":"https://patchwork.plctlab.org/api/1.2/patches/48216/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230125170725.386430-1-hjl.tools@gmail.com/","msgid":"<20230125170725.386430-1-hjl.tools@gmail.com>","list_archive_url":null,"date":"2023-01-25T17:07:25","name":"i386: Pass -Wl,--no-as-needed to compiler as needed","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230125170725.386430-1-hjl.tools@gmail.com/mbox/"},{"id":48437,"url":"https://patchwork.plctlab.org/api/1.2/patches/48437/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230126003820.28482-1-mark@harmstone.com/","msgid":"<20230126003820.28482-1-mark@harmstone.com>","list_archive_url":null,"date":"2023-01-26T00:38:19","name":"[1/2] gas: Add CodeView constant for aarch64","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230126003820.28482-1-mark@harmstone.com/mbox/"},{"id":48438,"url":"https://patchwork.plctlab.org/api/1.2/patches/48438/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230126003820.28482-2-mark@harmstone.com/","msgid":"<20230126003820.28482-2-mark@harmstone.com>","list_archive_url":null,"date":"2023-01-26T00:38:20","name":"[2/2] gas/testsuite: Add -gcodeview test for aarch64-w64-mingw32","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230126003820.28482-2-mark@harmstone.com/mbox/"},{"id":48479,"url":"https://patchwork.plctlab.org/api/1.2/patches/48479/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230126032613.2446180-1-vladimir.mezentsev@oracle.com/","msgid":"<20230126032613.2446180-1-vladimir.mezentsev@oracle.com>","list_archive_url":null,"date":"2023-01-26T03:26:13","name":"gprofng: PR30043 libgprofng.so.* are installed to a wrong location","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230126032613.2446180-1-vladimir.mezentsev@oracle.com/mbox/"},{"id":48906,"url":"https://patchwork.plctlab.org/api/1.2/patches/48906/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y9L12EZ4fvTcwQj1@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-01-26T21:51:20","name":"segv in coff_aarch64_addr32nb_reloc","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y9L12EZ4fvTcwQj1@squeak.grove.modra.org/mbox/"},{"id":48909,"url":"https://patchwork.plctlab.org/api/1.2/patches/48909/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y9L2F1zkVoK5AqSW@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-01-26T21:52:23","name":"resolve gas shift expressions with large exponents to zero","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y9L2F1zkVoK5AqSW@squeak.grove.modra.org/mbox/"},{"id":48911,"url":"https://patchwork.plctlab.org/api/1.2/patches/48911/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y9L2O3TbmvhYyhsC@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-01-26T21:52:59","name":"Sanity check dwarf5 form of .file","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y9L2O3TbmvhYyhsC@squeak.grove.modra.org/mbox/"},{"id":48914,"url":"https://patchwork.plctlab.org/api/1.2/patches/48914/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y9L2WRS5mIZy8y43@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-01-26T21:53:29","name":"Free gas/dwarf2dbg.c dirs","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y9L2WRS5mIZy8y43@squeak.grove.modra.org/mbox/"},{"id":49109,"url":"https://patchwork.plctlab.org/api/1.2/patches/49109/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y9N2nkjI4TDjK9+4@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-01-27T07:00:46","name":"gas macro memory leaks","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y9N2nkjI4TDjK9+4@squeak.grove.modra.org/mbox/"},{"id":49110,"url":"https://patchwork.plctlab.org/api/1.2/patches/49110/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y9N2vclgJwnt0fbW@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-01-27T07:01:17","name":"Call bfd_close_all_done in output_file_close","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y9N2vclgJwnt0fbW@squeak.grove.modra.org/mbox/"},{"id":49112,"url":"https://patchwork.plctlab.org/api/1.2/patches/49112/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y9N25JqhQsKIRAtn@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-01-27T07:01:56","name":"Perform cleanup in bfd_close after errors","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y9N25JqhQsKIRAtn@squeak.grove.modra.org/mbox/"},{"id":49111,"url":"https://patchwork.plctlab.org/api/1.2/patches/49111/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y9N3ClMTDGAq08yV@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-01-27T07:02:34","name":"Call bfd_close_all_done in ld_cleanup","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y9N3ClMTDGAq08yV@squeak.grove.modra.org/mbox/"},{"id":49193,"url":"https://patchwork.plctlab.org/api/1.2/patches/49193/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/46af6fa7-e2c2-f771-47e2-05124675b096@suse.com/","msgid":"<46af6fa7-e2c2-f771-47e2-05124675b096@suse.com>","list_archive_url":null,"date":"2023-01-27T11:10:24","name":"x86-64: respect MOVABS when choosing alternative encodings","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/46af6fa7-e2c2-f771-47e2-05124675b096@suse.com/mbox/"},{"id":49266,"url":"https://patchwork.plctlab.org/api/1.2/patches/49266/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3162e04b-3063-ab0c-3596-963132fd6233@suse.com/","msgid":"<3162e04b-3063-ab0c-3596-963132fd6233@suse.com>","list_archive_url":null,"date":"2023-01-27T11:35:04","name":"[1/3] x86: respect {nooptimize} for LEA","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3162e04b-3063-ab0c-3596-963132fd6233@suse.com/mbox/"},{"id":49267,"url":"https://patchwork.plctlab.org/api/1.2/patches/49267/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fd4ad7a1-565d-12ea-c7e0-744d35d77aa6@suse.com/","msgid":"","list_archive_url":null,"date":"2023-01-27T11:35:33","name":"[2/3] x86-64: respect {nooptimize} when building VEX prefix","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fd4ad7a1-565d-12ea-c7e0-744d35d77aa6@suse.com/mbox/"},{"id":49268,"url":"https://patchwork.plctlab.org/api/1.2/patches/49268/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/44b896ee-5b03-1ed6-bda2-8cffec382810@suse.com/","msgid":"<44b896ee-5b03-1ed6-bda2-8cffec382810@suse.com>","list_archive_url":null,"date":"2023-01-27T11:36:02","name":"[3/3] x86: drop LOCK from XCHG when optimizing","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/44b896ee-5b03-1ed6-bda2-8cffec382810@suse.com/mbox/"},{"id":49386,"url":"https://patchwork.plctlab.org/api/1.2/patches/49386/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/dc521fdd-1462-0a4e-6d8e-5fa3f35c82b5@suse.com/","msgid":"","list_archive_url":null,"date":"2023-01-27T13:14:44","name":"RISC-V: don'\''t disassemble unrecognized insns as .byte","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/dc521fdd-1462-0a4e-6d8e-5fa3f35c82b5@suse.com/mbox/"},{"id":50004,"url":"https://patchwork.plctlab.org/api/1.2/patches/50004/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230129153207.944175-1-dimitar@dinux.eu/","msgid":"<20230129153207.944175-1-dimitar@dinux.eu>","list_archive_url":null,"date":"2023-01-29T15:32:06","name":"[1/2] ld: pru: Merge the bss input sections into data","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230129153207.944175-1-dimitar@dinux.eu/mbox/"},{"id":50008,"url":"https://patchwork.plctlab.org/api/1.2/patches/50008/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230129153820.944711-1-dimitar@dinux.eu/","msgid":"<20230129153820.944711-1-dimitar@dinux.eu>","list_archive_url":null,"date":"2023-01-29T15:38:20","name":"[2/2] ld: pru: Add optional section alignments","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230129153820.944711-1-dimitar@dinux.eu/mbox/"},{"id":50144,"url":"https://patchwork.plctlab.org/api/1.2/patches/50144/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c72a27dfcb254b72e542f3a292b387b16add7ef7.1675060487.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2023-01-30T06:35:29","name":"[v2,1/1] RISC-V: Add platform property/capability extensions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c72a27dfcb254b72e542f3a292b387b16add7ef7.1675060487.git.research_trasio@irq.a4lg.com/mbox/"},{"id":50162,"url":"https://patchwork.plctlab.org/api/1.2/patches/50162/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3d42328e6f41cce145063883e5a9f513f4570840.1675062682.git.research_trasio@irq.a4lg.com/","msgid":"<3d42328e6f41cce145063883e5a9f513f4570840.1675062682.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2023-01-30T07:11:31","name":"[v3,1/1] RISC-V: Add platform property/capability extensions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3d42328e6f41cce145063883e5a9f513f4570840.1675062682.git.research_trasio@irq.a4lg.com/mbox/"},{"id":50300,"url":"https://patchwork.plctlab.org/api/1.2/patches/50300/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b61869e7-8fd3-2bec-da2b-046066edc3f3@suse.com/","msgid":"","list_archive_url":null,"date":"2023-01-30T14:07:20","name":"[v2] RISC-V: make C-extension JAL available again for (32-bit) assembly","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b61869e7-8fd3-2bec-da2b-046066edc3f3@suse.com/mbox/"},{"id":50324,"url":"https://patchwork.plctlab.org/api/1.2/patches/50324/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ef8afeef-b35f-348c-7d4c-bac8081e9952@suse.com/","msgid":"","list_archive_url":null,"date":"2023-01-30T14:40:38","name":"[v2] RISC-V: don'\''t disassemble unrecognized insns as .byte","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ef8afeef-b35f-348c-7d4c-bac8081e9952@suse.com/mbox/"},{"id":50325,"url":"https://patchwork.plctlab.org/api/1.2/patches/50325/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/95d700d49f5cdd2239c44ec17dadd11652f7be93.1675091147.git.aburgess@redhat.com/","msgid":"<95d700d49f5cdd2239c44ec17dadd11652f7be93.1675091147.git.aburgess@redhat.com>","list_archive_url":null,"date":"2023-01-30T15:11:41","name":"gas/ppc: Additional tests for DFP instructions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/95d700d49f5cdd2239c44ec17dadd11652f7be93.1675091147.git.aburgess@redhat.com/mbox/"},{"id":50492,"url":"https://patchwork.plctlab.org/api/1.2/patches/50492/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230130210642.7579-1-palmer@rivosinc.com/","msgid":"<20230130210642.7579-1-palmer@rivosinc.com>","list_archive_url":null,"date":"2023-01-30T21:06:41","name":"[1/2] gas: RISC-V: Add a test for near->far branch conversion","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230130210642.7579-1-palmer@rivosinc.com/mbox/"},{"id":50493,"url":"https://patchwork.plctlab.org/api/1.2/patches/50493/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230130210642.7579-2-palmer@rivosinc.com/","msgid":"<20230130210642.7579-2-palmer@rivosinc.com>","list_archive_url":null,"date":"2023-01-30T21:06:42","name":"[2/2] ld: RISC-V: Test R_RISCV_BRANCH truncation errors","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230130210642.7579-2-palmer@rivosinc.com/mbox/"},{"id":50594,"url":"https://patchwork.plctlab.org/api/1.2/patches/50594/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y9id+58ffnaAfImy@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-01-31T04:50:03","name":"testsuite XPASSes","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y9id+58ffnaAfImy@squeak.grove.modra.org/mbox/"},{"id":50595,"url":"https://patchwork.plctlab.org/api/1.2/patches/50595/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y9ieVWMZ5oxFqZJJ@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-01-31T04:51:33","name":"PR30060, ASAN error in bfd_cache_close","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y9ieVWMZ5oxFqZJJ@squeak.grove.modra.org/mbox/"},{"id":50596,"url":"https://patchwork.plctlab.org/api/1.2/patches/50596/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y9iegPmzz6ZQLXCO@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-01-31T04:52:16","name":"Silence ubsan warning about 1<<31","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y9iegPmzz6ZQLXCO@squeak.grove.modra.org/mbox/"},{"id":50784,"url":"https://patchwork.plctlab.org/api/1.2/patches/50784/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230131114257.4585-1-tdevries@suse.de/","msgid":"<20230131114257.4585-1-tdevries@suse.de>","list_archive_url":null,"date":"2023-01-31T11:42:57","name":"[gas] Emit v2 .debug_line for -gdwarf-2","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230131114257.4585-1-tdevries@suse.de/mbox/"}],"public":true,"mbox":"https://patchwork.plctlab.org/bundle/patchwork-bot/binutils-gdb_2023-01/mbox/"},{"id":16,"url":"https://patchwork.plctlab.org/api/1.2/bundles/16/","web_url":"https://patchwork.plctlab.org/bundle/patchwork-bot/binutils-gdb_2023-02/","project":{"id":2,"url":"https://patchwork.plctlab.org/api/1.2/projects/2/","name":"binutils-gdb","link_name":"binutils-gdb","list_id":"binutils.sourceware.org","list_email":"binutils@sourceware.org","web_url":"https://github.com/wangliu-iscas/Patchwork-Bundles/blob/main/binutils-gdb.md","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"name":"binutils-gdb_2023-02","owner":{"id":3,"url":"https://patchwork.plctlab.org/api/1.2/users/3/","username":"patchwork-bot","first_name":"","last_name":"","email":"ouuuleilei@gmail.com"},"patches":[{"id":51097,"url":"https://patchwork.plctlab.org/api/1.2/patches/51097/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230131233429.3708328-2-indu.bhagat@oracle.com/","msgid":"<20230131233429.3708328-2-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-01-31T23:34:25","name":"[1/5] libsframe/doc: use \"stack trace\" instead of \"unwind\" for SFrame","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230131233429.3708328-2-indu.bhagat@oracle.com/mbox/"},{"id":51096,"url":"https://patchwork.plctlab.org/api/1.2/patches/51096/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230131233429.3708328-3-indu.bhagat@oracle.com/","msgid":"<20230131233429.3708328-3-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-01-31T23:34:26","name":"[2/5] sframe: use \"stack trace\" instead of \"unwind\" for SFrame","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230131233429.3708328-3-indu.bhagat@oracle.com/mbox/"},{"id":51099,"url":"https://patchwork.plctlab.org/api/1.2/patches/51099/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230131233429.3708328-4-indu.bhagat@oracle.com/","msgid":"<20230131233429.3708328-4-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-01-31T23:34:27","name":"[3/5] gas: use \"stack trace\" instead of \"unwind\" for SFrame","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230131233429.3708328-4-indu.bhagat@oracle.com/mbox/"},{"id":51098,"url":"https://patchwork.plctlab.org/api/1.2/patches/51098/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230131233429.3708328-5-indu.bhagat@oracle.com/","msgid":"<20230131233429.3708328-5-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-01-31T23:34:28","name":"[4/5] bfd: use \"stack trace\" instead of \"unwind\" for SFrame","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230131233429.3708328-5-indu.bhagat@oracle.com/mbox/"},{"id":51100,"url":"https://patchwork.plctlab.org/api/1.2/patches/51100/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230131233429.3708328-6-indu.bhagat@oracle.com/","msgid":"<20230131233429.3708328-6-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-01-31T23:34:29","name":"[5/5] ld/doc: use \"stack trace\" instead of \"unwind\" for SFrame","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230131233429.3708328-6-indu.bhagat@oracle.com/mbox/"},{"id":51183,"url":"https://patchwork.plctlab.org/api/1.2/patches/51183/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y9oIhhJR9qaUEmFI@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-02-01T06:36:54","name":"Recursion in as_info_where","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y9oIhhJR9qaUEmFI@squeak.grove.modra.org/mbox/"},{"id":51254,"url":"https://patchwork.plctlab.org/api/1.2/patches/51254/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/87lelhzpg3.fsf@redhat.com/","msgid":"<87lelhzpg3.fsf@redhat.com>","list_archive_url":null,"date":"2023-02-01T09:48:28","name":"Fix sanitization warning message building gas.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/87lelhzpg3.fsf@redhat.com/mbox/"},{"id":51529,"url":"https://patchwork.plctlab.org/api/1.2/patches/51529/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/patch-16852-tamar@arm.com/","msgid":"","list_archive_url":null,"date":"2023-02-01T19:25:23","name":"[Binutils] AArch64 gas: relax ordering constriants on enabling and disabling feature extensions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/patch-16852-tamar@arm.com/mbox/"},{"id":51590,"url":"https://patchwork.plctlab.org/api/1.2/patches/51590/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y9rrfysbgq2B456K@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-02-01T22:45:19","name":"gas obj_end","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y9rrfysbgq2B456K@squeak.grove.modra.org/mbox/"},{"id":51591,"url":"https://patchwork.plctlab.org/api/1.2/patches/51591/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y9rrosJRMXXJwzAo@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-02-01T22:45:54","name":"obj-elf.h BYTES_IN_WORD","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y9rrosJRMXXJwzAo@squeak.grove.modra.org/mbox/"},{"id":51640,"url":"https://patchwork.plctlab.org/api/1.2/patches/51640/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y9spf1UfzfEL5hKO@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-02-02T03:09:51","name":"ld-elf/merge test update","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y9spf1UfzfEL5hKO@squeak.grove.modra.org/mbox/"},{"id":51936,"url":"https://patchwork.plctlab.org/api/1.2/patches/51936/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230202140811.20373-1-tdevries@suse.de/","msgid":"<20230202140811.20373-1-tdevries@suse.de>","list_archive_url":null,"date":"2023-02-02T14:08:11","name":"[pushed,gas] Update .loc syntax comment in dwarf2dbg.c","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230202140811.20373-1-tdevries@suse.de/mbox/"},{"id":52314,"url":"https://patchwork.plctlab.org/api/1.2/patches/52314/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y9yeZbU4atFWrl5i@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-02-03T05:40:53","name":"Add ECOFF Symbolic Header sanity checks","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y9yeZbU4atFWrl5i@squeak.grove.modra.org/mbox/"},{"id":52352,"url":"https://patchwork.plctlab.org/api/1.2/patches/52352/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/06804163-be78-6130-b082-71661e50e876@suse.com/","msgid":"<06804163-be78-6130-b082-71661e50e876@suse.com>","list_archive_url":null,"date":"2023-02-03T07:32:13","name":"[1/3] x86: improve special casing of certain insns","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/06804163-be78-6130-b082-71661e50e876@suse.com/mbox/"},{"id":52353,"url":"https://patchwork.plctlab.org/api/1.2/patches/52353/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/645a01e0-8acf-f55d-1f5a-c9e8bbb1d10f@suse.com/","msgid":"<645a01e0-8acf-f55d-1f5a-c9e8bbb1d10f@suse.com>","list_archive_url":null,"date":"2023-02-03T07:32:33","name":"[2/3] x86: simplify a few expressions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/645a01e0-8acf-f55d-1f5a-c9e8bbb1d10f@suse.com/mbox/"},{"id":52354,"url":"https://patchwork.plctlab.org/api/1.2/patches/52354/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8aa94a23-664f-f3ed-fa90-2e0cfa963bd0@suse.com/","msgid":"<8aa94a23-664f-f3ed-fa90-2e0cfa963bd0@suse.com>","list_archive_url":null,"date":"2023-02-03T07:33:44","name":"[3/3] x86: move (and rename) opcodespace attribute","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8aa94a23-664f-f3ed-fa90-2e0cfa963bd0@suse.com/mbox/"},{"id":52367,"url":"https://patchwork.plctlab.org/api/1.2/patches/52367/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/573dd630-a3ca-52c6-846a-d7d18a7e3d52@suse.com/","msgid":"<573dd630-a3ca-52c6-846a-d7d18a7e3d52@suse.com>","list_archive_url":null,"date":"2023-02-03T07:44:56","name":"[1/3] x86: limit use of XOP2SOURCES","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/573dd630-a3ca-52c6-846a-d7d18a7e3d52@suse.com/mbox/"},{"id":52368,"url":"https://patchwork.plctlab.org/api/1.2/patches/52368/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/03deb7fa-cc01-a049-965e-4ee534aadc35@suse.com/","msgid":"<03deb7fa-cc01-a049-965e-4ee534aadc35@suse.com>","list_archive_url":null,"date":"2023-02-03T07:45:51","name":"[2/3] x86: drop use of XOP2SOURCES","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/03deb7fa-cc01-a049-965e-4ee534aadc35@suse.com/mbox/"},{"id":52370,"url":"https://patchwork.plctlab.org/api/1.2/patches/52370/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1364c0e8-5e91-4a92-c14c-072b2a1edf6d@suse.com/","msgid":"<1364c0e8-5e91-4a92-c14c-072b2a1edf6d@suse.com>","list_archive_url":null,"date":"2023-02-03T07:46:45","name":"[3/3] x86: drop use of VEX3SOURCES","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1364c0e8-5e91-4a92-c14c-072b2a1edf6d@suse.com/mbox/"},{"id":53113,"url":"https://patchwork.plctlab.org/api/1.2/patches/53113/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y+DKOkv+GiK5JKLG@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-02-06T09:36:58","name":"Resetting section vma after _bfd_dwarf2_find_nearest_line","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y+DKOkv+GiK5JKLG@squeak.grove.modra.org/mbox/"},{"id":53214,"url":"https://patchwork.plctlab.org/api/1.2/patches/53214/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y+DzhUGfFBaLPJiD@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-02-06T12:33:09","name":"Protect mips_hi16_list from fuzzed debug info","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y+DzhUGfFBaLPJiD@squeak.grove.modra.org/mbox/"},{"id":53216,"url":"https://patchwork.plctlab.org/api/1.2/patches/53216/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y+D0PyRzBoWRnzLq@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-02-06T12:36:15","name":"ppc32 and \"LOAD segment with RWX permissions\"","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y+D0PyRzBoWRnzLq@squeak.grove.modra.org/mbox/"},{"id":53418,"url":"https://patchwork.plctlab.org/api/1.2/patches/53418/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/BLAPR10MB52986899D13C84F0505C23CEABDA9@BLAPR10MB5298.namprd10.prod.outlook.com/","msgid":"","list_archive_url":null,"date":"2023-02-06T16:37:29","name":"gprofng SIGSEGV when processing unusual dwarf","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/BLAPR10MB52986899D13C84F0505C23CEABDA9@BLAPR10MB5298.namprd10.prod.outlook.com/mbox/"},{"id":53591,"url":"https://patchwork.plctlab.org/api/1.2/patches/53591/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230207015340.2021329-1-vladimir.mezentsev@oracle.com/","msgid":"<20230207015340.2021329-1-vladimir.mezentsev@oracle.com>","list_archive_url":null,"date":"2023-02-07T01:53:40","name":"gprofng: fix SIGSEGV when processing unusual dwarf","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230207015340.2021329-1-vladimir.mezentsev@oracle.com/mbox/"},{"id":53606,"url":"https://patchwork.plctlab.org/api/1.2/patches/53606/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230207024424.4000862-1-yunqiang.su@cipunited.com/","msgid":"<20230207024424.4000862-1-yunqiang.su@cipunited.com>","list_archive_url":null,"date":"2023-02-07T02:44:24","name":"MIPS: allow link o32 objects with mach mips64r6 and mips32r6","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230207024424.4000862-1-yunqiang.su@cipunited.com/mbox/"},{"id":54238,"url":"https://patchwork.plctlab.org/api/1.2/patches/54238/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230208071725.3668898-2-tom@tromey.com/","msgid":"<20230208071725.3668898-2-tom@tromey.com>","list_archive_url":null,"date":"2023-02-08T07:17:18","name":"[1/8] Remove H_CFLAGS from doc/local.mk","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230208071725.3668898-2-tom@tromey.com/mbox/"},{"id":54231,"url":"https://patchwork.plctlab.org/api/1.2/patches/54231/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230208071725.3668898-3-tom@tromey.com/","msgid":"<20230208071725.3668898-3-tom@tromey.com>","list_archive_url":null,"date":"2023-02-08T07:17:19","name":"[2/8] Simplify @node use in BFD documentation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230208071725.3668898-3-tom@tromey.com/mbox/"},{"id":54222,"url":"https://patchwork.plctlab.org/api/1.2/patches/54222/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230208071725.3668898-4-tom@tromey.com/","msgid":"<20230208071725.3668898-4-tom@tromey.com>","list_archive_url":null,"date":"2023-02-08T07:17:20","name":"[3/8] Add copyright headers to the .str files","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230208071725.3668898-4-tom@tromey.com/mbox/"},{"id":54226,"url":"https://patchwork.plctlab.org/api/1.2/patches/54226/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230208071725.3668898-5-tom@tromey.com/","msgid":"<20230208071725.3668898-5-tom@tromey.com>","list_archive_url":null,"date":"2023-02-08T07:17:21","name":"[4/8] Remove the paramstuff word","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230208071725.3668898-5-tom@tromey.com/mbox/"},{"id":54223,"url":"https://patchwork.plctlab.org/api/1.2/patches/54223/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230208071725.3668898-6-tom@tromey.com/","msgid":"<20230208071725.3668898-6-tom@tromey.com>","list_archive_url":null,"date":"2023-02-08T07:17:22","name":"[5/8] Use intptr_t rather than long in chew","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230208071725.3668898-6-tom@tromey.com/mbox/"},{"id":54232,"url":"https://patchwork.plctlab.org/api/1.2/patches/54232/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230208071725.3668898-7-tom@tromey.com/","msgid":"<20230208071725.3668898-7-tom@tromey.com>","list_archive_url":null,"date":"2023-02-08T07:17:23","name":"[6/8] Change internalmode to be an intrinsic variable","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230208071725.3668898-7-tom@tromey.com/mbox/"},{"id":54235,"url":"https://patchwork.plctlab.org/api/1.2/patches/54235/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230208071725.3668898-8-tom@tromey.com/","msgid":"<20230208071725.3668898-8-tom@tromey.com>","list_archive_url":null,"date":"2023-02-08T07:17:24","name":"[7/8] Use @deftypefn in chew output","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230208071725.3668898-8-tom@tromey.com/mbox/"},{"id":54227,"url":"https://patchwork.plctlab.org/api/1.2/patches/54227/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230208071725.3668898-9-tom@tromey.com/","msgid":"<20230208071725.3668898-9-tom@tromey.com>","list_archive_url":null,"date":"2023-02-08T07:17:25","name":"[8/8] Remove RETURNS from BFD chew comments","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230208071725.3668898-9-tom@tromey.com/mbox/"},{"id":54632,"url":"https://patchwork.plctlab.org/api/1.2/patches/54632/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y+QsUGAY7LQw0zQu@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-02-08T23:12:16","name":"Internal error at gas/expr.c:1814","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y+QsUGAY7LQw0zQu@squeak.grove.modra.org/mbox/"},{"id":54633,"url":"https://patchwork.plctlab.org/api/1.2/patches/54633/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y+QsheSWZko4+7vV@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-02-08T23:13:09","name":"Clear cached file size when bfd changed to BFD_IN_MEMORY","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y+QsheSWZko4+7vV@squeak.grove.modra.org/mbox/"},{"id":54634,"url":"https://patchwork.plctlab.org/api/1.2/patches/54634/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y+QsoGbCT4Ei4rlW@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-02-08T23:13:36","name":"Memory leak in bfd_init_section_compress_status","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y+QsoGbCT4Ei4rlW@squeak.grove.modra.org/mbox/"},{"id":54635,"url":"https://patchwork.plctlab.org/api/1.2/patches/54635/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y+QszzU2zl+ApZy4@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-02-08T23:14:23","name":"coff-sh.c keep_relocs, keep_contents and keep_syms","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y+QszzU2zl+ApZy4@squeak.grove.modra.org/mbox/"},{"id":54823,"url":"https://patchwork.plctlab.org/api/1.2/patches/54823/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y+S/4ej6hbSlHWUj@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-02-09T09:41:53","name":"coff keep_relocs and keep_contents","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y+S/4ej6hbSlHWUj@squeak.grove.modra.org/mbox/"},{"id":55093,"url":"https://patchwork.plctlab.org/api/1.2/patches/55093/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230209205040.1286063-1-tromey@adacore.com/","msgid":"<20230209205040.1286063-1-tromey@adacore.com>","list_archive_url":null,"date":"2023-02-09T20:50:40","name":"[pushed] Add full display feature to dwarf-mode.el","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230209205040.1286063-1-tromey@adacore.com/mbox/"},{"id":55172,"url":"https://patchwork.plctlab.org/api/1.2/patches/55172/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y+WWbsUP6DBus1sD@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-02-10T00:57:18","name":"objcopy of mach-o indirect symbols","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y+WWbsUP6DBus1sD@squeak.grove.modra.org/mbox/"},{"id":55284,"url":"https://patchwork.plctlab.org/api/1.2/patches/55284/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y+X07Mh4TUJM0qoV@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-02-10T07:40:28","name":"Local label checks in integer_constant","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y+X07Mh4TUJM0qoV@squeak.grove.modra.org/mbox/"},{"id":55314,"url":"https://patchwork.plctlab.org/api/1.2/patches/55314/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1d6f89f5-0e6e-6a8b-3a93-41dd26d09c0a@suse.com/","msgid":"<1d6f89f5-0e6e-6a8b-3a93-41dd26d09c0a@suse.com>","list_archive_url":null,"date":"2023-02-10T08:36:05","name":"[1/2] x86: optimize BT{,C,R,S} $imm,%reg","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1d6f89f5-0e6e-6a8b-3a93-41dd26d09c0a@suse.com/mbox/"},{"id":55315,"url":"https://patchwork.plctlab.org/api/1.2/patches/55315/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/58de4278-3b30-1e3b-f2da-551c47bca681@suse.com/","msgid":"<58de4278-3b30-1e3b-f2da-551c47bca681@suse.com>","list_archive_url":null,"date":"2023-02-10T08:36:40","name":"[2/2] x86: restrict insn templates accepting negative 8-bit immediates","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/58de4278-3b30-1e3b-f2da-551c47bca681@suse.com/mbox/"},{"id":55317,"url":"https://patchwork.plctlab.org/api/1.2/patches/55317/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b0c44651-1f3f-46c6-09ff-c12bf6026bdc@suse.com/","msgid":"","list_archive_url":null,"date":"2023-02-10T08:48:39","name":"[1/4] x86-64: LAR and LSL don'\''t need REX.W","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b0c44651-1f3f-46c6-09ff-c12bf6026bdc@suse.com/mbox/"},{"id":55318,"url":"https://patchwork.plctlab.org/api/1.2/patches/55318/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/623497d9-1367-d446-1cce-f9b0fe177699@suse.com/","msgid":"<623497d9-1367-d446-1cce-f9b0fe177699@suse.com>","list_archive_url":null,"date":"2023-02-10T08:49:18","name":"[2/4] x86: have insns acting on segment selector values allow for consistent operands","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/623497d9-1367-d446-1cce-f9b0fe177699@suse.com/mbox/"},{"id":55319,"url":"https://patchwork.plctlab.org/api/1.2/patches/55319/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3ab09feb-290d-693d-b43f-237022f3f6aa@suse.com/","msgid":"<3ab09feb-290d-693d-b43f-237022f3f6aa@suse.com>","list_archive_url":null,"date":"2023-02-10T08:50:25","name":"[3/4] x86-64: don'\''t permit LAHF/SAHF with \"generic64\"","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3ab09feb-290d-693d-b43f-237022f3f6aa@suse.com/mbox/"},{"id":55320,"url":"https://patchwork.plctlab.org/api/1.2/patches/55320/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/67715baf-b718-0d00-959a-fc4e70c0dff9@suse.com/","msgid":"<67715baf-b718-0d00-959a-fc4e70c0dff9@suse.com>","list_archive_url":null,"date":"2023-02-10T08:51:42","name":"[4/4] x86: MONITOR/MWAIT are not SSE3 insns","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/67715baf-b718-0d00-959a-fc4e70c0dff9@suse.com/mbox/"},{"id":55325,"url":"https://patchwork.plctlab.org/api/1.2/patches/55325/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d6e6f04a-d7d2-fffc-1672-89356d00888c@suse.com/","msgid":"","list_archive_url":null,"date":"2023-02-10T08:53:47","name":"x86: allow to request ModR/M encoding","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d6e6f04a-d7d2-fffc-1672-89356d00888c@suse.com/mbox/"},{"id":55358,"url":"https://patchwork.plctlab.org/api/1.2/patches/55358/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y+YW49ew8TrVHIVE@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-02-10T10:05:23","name":"Fix mmo memory leaks","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y+YW49ew8TrVHIVE@squeak.grove.modra.org/mbox/"},{"id":55383,"url":"https://patchwork.plctlab.org/api/1.2/patches/55383/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/26a512cf3d23fca9a71d4328d554f640d080e8a8.1676025351.git.research_trasio@irq.a4lg.com/","msgid":"<26a512cf3d23fca9a71d4328d554f640d080e8a8.1676025351.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2023-02-10T10:37:22","name":"RISC-V: Reduce effective linker relaxation passses","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/26a512cf3d23fca9a71d4328d554f640d080e8a8.1676025351.git.research_trasio@irq.a4lg.com/mbox/"},{"id":55502,"url":"https://patchwork.plctlab.org/api/1.2/patches/55502/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230210174404.3763-2-binutils@emagii.com/","msgid":"<20230210174404.3763-2-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-10T17:44:01","name":"[1/4] ldlex.l: Add ASCIZ token","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230210174404.3763-2-binutils@emagii.com/mbox/"},{"id":55503,"url":"https://patchwork.plctlab.org/api/1.2/patches/55503/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230210174404.3763-3-binutils@emagii.com/","msgid":"<20230210174404.3763-3-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-10T17:44:02","name":"[2/4] ldgram.y: Add '\''ASCIZ '\'' command","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230210174404.3763-3-binutils@emagii.com/mbox/"},{"id":55504,"url":"https://patchwork.plctlab.org/api/1.2/patches/55504/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230210174404.3763-4-binutils@emagii.com/","msgid":"<20230210174404.3763-4-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-10T17:44:03","name":"[3/4] Parse ASCIZ command","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230210174404.3763-4-binutils@emagii.com/mbox/"},{"id":55505,"url":"https://patchwork.plctlab.org/api/1.2/patches/55505/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230210174404.3763-5-binutils@emagii.com/","msgid":"<20230210174404.3763-5-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-10T17:44:04","name":"[4/4] Document the ASCIZ command","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230210174404.3763-5-binutils@emagii.com/mbox/"},{"id":55698,"url":"https://patchwork.plctlab.org/api/1.2/patches/55698/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y+cxtbhMXNT350aU@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-02-11T06:12:05","name":".debug sections without contents","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y+cxtbhMXNT350aU@squeak.grove.modra.org/mbox/"},{"id":55699,"url":"https://patchwork.plctlab.org/api/1.2/patches/55699/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y+cyCbQkCFHOPzaA@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-02-11T06:13:29","name":"objdump -D of bss sections and -s with -j","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y+cyCbQkCFHOPzaA@squeak.grove.modra.org/mbox/"},{"id":55977,"url":"https://patchwork.plctlab.org/api/1.2/patches/55977/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y+lm2hoJrZN/I1OO@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-02-12T22:23:22","name":"objcopy memory leaks","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y+lm2hoJrZN/I1OO@squeak.grove.modra.org/mbox/"},{"id":56071,"url":"https://patchwork.plctlab.org/api/1.2/patches/56071/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5003cbd5-448c-7f39-5219-ae3bfe50504f@suse.com/","msgid":"<5003cbd5-448c-7f39-5219-ae3bfe50504f@suse.com>","list_archive_url":null,"date":"2023-02-13T08:02:36","name":"[1/2] RISC-V: test for expected / no unexpected symbols","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5003cbd5-448c-7f39-5219-ae3bfe50504f@suse.com/mbox/"},{"id":56072,"url":"https://patchwork.plctlab.org/api/1.2/patches/56072/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3bb126f6-5bf1-dab0-f540-25c386b9507e@suse.com/","msgid":"<3bb126f6-5bf1-dab0-f540-25c386b9507e@suse.com>","list_archive_url":null,"date":"2023-02-13T08:02:58","name":"[2/2] RISC-V: adjust logic to avoid register name symbols","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3bb126f6-5bf1-dab0-f540-25c386b9507e@suse.com/mbox/"},{"id":56078,"url":"https://patchwork.plctlab.org/api/1.2/patches/56078/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/09ff32c5-3ebc-dda1-2eb5-be7851cb7c66@suse.com/","msgid":"<09ff32c5-3ebc-dda1-2eb5-be7851cb7c66@suse.com>","list_archive_url":null,"date":"2023-02-13T08:12:12","name":"[1/2] Arm64/gas: add missing prereq features","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/09ff32c5-3ebc-dda1-2eb5-be7851cb7c66@suse.com/mbox/"},{"id":56080,"url":"https://patchwork.plctlab.org/api/1.2/patches/56080/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c1e56cb2-a33f-59fd-a431-6a27460525cf@suse.com/","msgid":"","list_archive_url":null,"date":"2023-02-13T08:12:45","name":"[2/2] Arm64/gas: drop redundant feature prereqs","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c1e56cb2-a33f-59fd-a431-6a27460525cf@suse.com/mbox/"},{"id":56081,"url":"https://patchwork.plctlab.org/api/1.2/patches/56081/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/08d262e3-c736-85ff-c45e-db96e55cff4c@suse.com/","msgid":"<08d262e3-c736-85ff-c45e-db96e55cff4c@suse.com>","list_archive_url":null,"date":"2023-02-13T08:15:36","name":"gas: improve interaction between read_a_source_file() and s_linefile()","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/08d262e3-c736-85ff-c45e-db96e55cff4c@suse.com/mbox/"},{"id":56098,"url":"https://patchwork.plctlab.org/api/1.2/patches/56098/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8c7753dd-a5f5-f994-88ee-d4e053a20bc0@suse.com/","msgid":"<8c7753dd-a5f5-f994-88ee-d4e053a20bc0@suse.com>","list_archive_url":null,"date":"2023-02-13T08:42:20","name":"x86: {LD,ST}TILECFG use an extension opcode","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8c7753dd-a5f5-f994-88ee-d4e053a20bc0@suse.com/mbox/"},{"id":56162,"url":"https://patchwork.plctlab.org/api/1.2/patches/56162/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y+oSap1kQICg3JMp@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-02-13T10:35:22","name":"Split off gas init to functions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y+oSap1kQICg3JMp@squeak.grove.modra.org/mbox/"},{"id":56164,"url":"https://patchwork.plctlab.org/api/1.2/patches/56164/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y+oSkktwhytmt7rZ@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-02-13T10:36:02","name":"stabs.c static state","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y+oSkktwhytmt7rZ@squeak.grove.modra.org/mbox/"},{"id":56261,"url":"https://patchwork.plctlab.org/api/1.2/patches/56261/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230213122241.6144-2-binutils@emagii.com/","msgid":"<20230213122241.6144-2-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-13T12:22:37","name":"[v2,1/5] ldlex.l: Add ASCIZ token","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230213122241.6144-2-binutils@emagii.com/mbox/"},{"id":56262,"url":"https://patchwork.plctlab.org/api/1.2/patches/56262/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230213122241.6144-3-binutils@emagii.com/","msgid":"<20230213122241.6144-3-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-13T12:22:38","name":"[v2,2/5] ldgram.y: Add '\''ASCIZ '\'' command","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230213122241.6144-3-binutils@emagii.com/mbox/"},{"id":56263,"url":"https://patchwork.plctlab.org/api/1.2/patches/56263/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230213122241.6144-4-binutils@emagii.com/","msgid":"<20230213122241.6144-4-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-13T12:22:39","name":"[v2,3/5] Parse ASCIZ command","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230213122241.6144-4-binutils@emagii.com/mbox/"},{"id":56264,"url":"https://patchwork.plctlab.org/api/1.2/patches/56264/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230213122241.6144-5-binutils@emagii.com/","msgid":"<20230213122241.6144-5-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-13T12:22:40","name":"[v2,4/5] Document the ASCIZ command","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230213122241.6144-5-binutils@emagii.com/mbox/"},{"id":56265,"url":"https://patchwork.plctlab.org/api/1.2/patches/56265/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230213122241.6144-6-binutils@emagii.com/","msgid":"<20230213122241.6144-6-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-13T12:22:41","name":"[v2,5/5] Use lang_add_data","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230213122241.6144-6-binutils@emagii.com/mbox/"},{"id":56267,"url":"https://patchwork.plctlab.org/api/1.2/patches/56267/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y+ovRotGLLHQE09t@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-02-13T12:38:30","name":"_bfd_ecoff_slurp_symbol_table buffer overflow","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y+ovRotGLLHQE09t@squeak.grove.modra.org/mbox/"},{"id":56279,"url":"https://patchwork.plctlab.org/api/1.2/patches/56279/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.LSU.2.20.2302131301550.29328@wotan.suse.de/","msgid":"","list_archive_url":null,"date":"2023-02-13T13:04:14","name":"[obvious] Fix PR30079: abort on mingw","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.LSU.2.20.2302131301550.29328@wotan.suse.de/mbox/"},{"id":56293,"url":"https://patchwork.plctlab.org/api/1.2/patches/56293/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230213133949.3773320-2-christoph.muellner@vrull.eu/","msgid":"<20230213133949.3773320-2-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2023-02-13T13:39:42","name":"[RFC,v3,1/8] RISC-V: Add Zvkb ISA extension support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230213133949.3773320-2-christoph.muellner@vrull.eu/mbox/"},{"id":56296,"url":"https://patchwork.plctlab.org/api/1.2/patches/56296/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230213133949.3773320-3-christoph.muellner@vrull.eu/","msgid":"<20230213133949.3773320-3-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2023-02-13T13:39:43","name":"[RFC,v3,2/8] RISC-V: Add Zvkg ISA extension support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230213133949.3773320-3-christoph.muellner@vrull.eu/mbox/"},{"id":56297,"url":"https://patchwork.plctlab.org/api/1.2/patches/56297/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230213133949.3773320-4-christoph.muellner@vrull.eu/","msgid":"<20230213133949.3773320-4-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2023-02-13T13:39:44","name":"[RFC,v3,3/8] RISC-V: Add Zvkned ISA extension support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230213133949.3773320-4-christoph.muellner@vrull.eu/mbox/"},{"id":56294,"url":"https://patchwork.plctlab.org/api/1.2/patches/56294/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230213133949.3773320-5-christoph.muellner@vrull.eu/","msgid":"<20230213133949.3773320-5-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2023-02-13T13:39:45","name":"[RFC,v3,4/8] RISC-V: Add Zvknh[a,b] ISA extension support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230213133949.3773320-5-christoph.muellner@vrull.eu/mbox/"},{"id":56298,"url":"https://patchwork.plctlab.org/api/1.2/patches/56298/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230213133949.3773320-6-christoph.muellner@vrull.eu/","msgid":"<20230213133949.3773320-6-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2023-02-13T13:39:46","name":"[RFC,v3,5/8] RISC-V: Add Zvkn ISA extension support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230213133949.3773320-6-christoph.muellner@vrull.eu/mbox/"},{"id":56300,"url":"https://patchwork.plctlab.org/api/1.2/patches/56300/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230213133949.3773320-7-christoph.muellner@vrull.eu/","msgid":"<20230213133949.3773320-7-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2023-02-13T13:39:47","name":"[RFC,v3,6/8] RISC-V: Add Zvksed ISA extension support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230213133949.3773320-7-christoph.muellner@vrull.eu/mbox/"},{"id":56295,"url":"https://patchwork.plctlab.org/api/1.2/patches/56295/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230213133949.3773320-8-christoph.muellner@vrull.eu/","msgid":"<20230213133949.3773320-8-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2023-02-13T13:39:48","name":"[RFC,v3,7/8] RISC-V: Add Zvksh ISA extension support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230213133949.3773320-8-christoph.muellner@vrull.eu/mbox/"},{"id":56299,"url":"https://patchwork.plctlab.org/api/1.2/patches/56299/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230213133949.3773320-9-christoph.muellner@vrull.eu/","msgid":"<20230213133949.3773320-9-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2023-02-13T13:39:49","name":"[RFC,v3,8/8] RISC-V: Add Zvks ISA extension support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230213133949.3773320-9-christoph.muellner@vrull.eu/mbox/"},{"id":56326,"url":"https://patchwork.plctlab.org/api/1.2/patches/56326/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2096ddec-287a-de42-a2f6-58293af2fd48@suse.com/","msgid":"<2096ddec-287a-de42-a2f6-58293af2fd48@suse.com>","list_archive_url":null,"date":"2023-02-13T14:54:00","name":"gas: correct symbol name comparison in .startof./.sizeof. handling","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2096ddec-287a-de42-a2f6-58293af2fd48@suse.com/mbox/"},{"id":56363,"url":"https://patchwork.plctlab.org/api/1.2/patches/56363/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230213161124.15340-2-binutils@emagii.com/","msgid":"<20230213161124.15340-2-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-13T16:11:19","name":"[v3,1/6] Document the ASCIZ command","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230213161124.15340-2-binutils@emagii.com/mbox/"},{"id":56366,"url":"https://patchwork.plctlab.org/api/1.2/patches/56366/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230213161124.15340-3-binutils@emagii.com/","msgid":"<20230213161124.15340-3-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-13T16:11:20","name":"[v3,2/6] Add ASCIZ to NEWS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230213161124.15340-3-binutils@emagii.com/mbox/"},{"id":56365,"url":"https://patchwork.plctlab.org/api/1.2/patches/56365/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230213161124.15340-4-binutils@emagii.com/","msgid":"<20230213161124.15340-4-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-13T16:11:21","name":"[v3,3/6] Add ASCIZ to testsuite","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230213161124.15340-4-binutils@emagii.com/mbox/"},{"id":56364,"url":"https://patchwork.plctlab.org/api/1.2/patches/56364/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230213161124.15340-5-binutils@emagii.com/","msgid":"<20230213161124.15340-5-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-13T16:11:22","name":"[v3,4/6] ldlex.l: Add ASCIZ token","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230213161124.15340-5-binutils@emagii.com/mbox/"},{"id":56367,"url":"https://patchwork.plctlab.org/api/1.2/patches/56367/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230213161124.15340-6-binutils@emagii.com/","msgid":"<20230213161124.15340-6-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-13T16:11:23","name":"[v3,5/6] ldgram.y: Add '\''ASCIZ '\'' command","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230213161124.15340-6-binutils@emagii.com/mbox/"},{"id":56368,"url":"https://patchwork.plctlab.org/api/1.2/patches/56368/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230213161124.15340-7-binutils@emagii.com/","msgid":"<20230213161124.15340-7-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-13T16:11:24","name":"[v3,6/6] Parse ASCIZ command","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230213161124.15340-7-binutils@emagii.com/mbox/"},{"id":56372,"url":"https://patchwork.plctlab.org/api/1.2/patches/56372/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230213162009.15515-2-binutils@emagii.com/","msgid":"<20230213162009.15515-2-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-13T16:20:04","name":"[v4,1/6] Document the ASCIZ command","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230213162009.15515-2-binutils@emagii.com/mbox/"},{"id":56369,"url":"https://patchwork.plctlab.org/api/1.2/patches/56369/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230213162009.15515-3-binutils@emagii.com/","msgid":"<20230213162009.15515-3-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-13T16:20:05","name":"[v4,2/6] Add ASCIZ to NEWS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230213162009.15515-3-binutils@emagii.com/mbox/"},{"id":56370,"url":"https://patchwork.plctlab.org/api/1.2/patches/56370/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230213162009.15515-4-binutils@emagii.com/","msgid":"<20230213162009.15515-4-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-13T16:20:06","name":"[v4,3/6] Add ASCIZ to testsuite","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230213162009.15515-4-binutils@emagii.com/mbox/"},{"id":56371,"url":"https://patchwork.plctlab.org/api/1.2/patches/56371/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230213162009.15515-5-binutils@emagii.com/","msgid":"<20230213162009.15515-5-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-13T16:20:07","name":"[v4,4/6] ldlex.l: Add ASCIZ token","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230213162009.15515-5-binutils@emagii.com/mbox/"},{"id":56373,"url":"https://patchwork.plctlab.org/api/1.2/patches/56373/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230213162009.15515-6-binutils@emagii.com/","msgid":"<20230213162009.15515-6-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-13T16:20:08","name":"[v4,5/6] ldgram.y: Add '\''ASCIZ '\'' command","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230213162009.15515-6-binutils@emagii.com/mbox/"},{"id":56404,"url":"https://patchwork.plctlab.org/api/1.2/patches/56404/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.LSU.2.20.2302131741480.29328@wotan.suse.de/","msgid":"","list_archive_url":null,"date":"2023-02-13T17:42:58","name":"PR30120: fix x87 fucomp misassembled","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.LSU.2.20.2302131741480.29328@wotan.suse.de/mbox/"},{"id":56662,"url":"https://patchwork.plctlab.org/api/1.2/patches/56662/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230214050633.28910-6-binutils@emagii.com/","msgid":"<20230214050633.28910-6-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-14T05:06:33","name":"[v4,6/6] Parse ASCIZ command","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230214050633.28910-6-binutils@emagii.com/mbox/"},{"id":57082,"url":"https://patchwork.plctlab.org/api/1.2/patches/57082/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b876de99-e433-61b6-1645-e026f6c9dd80@suse.com/","msgid":"","list_archive_url":null,"date":"2023-02-14T15:53:10","name":"gas: buffer_and_nest() needs to pass nul-terminated string to temp_ilp()","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b876de99-e433-61b6-1645-e026f6c9dd80@suse.com/mbox/"},{"id":57344,"url":"https://patchwork.plctlab.org/api/1.2/patches/57344/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y+xE0Fa4HqQq/1p0@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-02-15T02:34:56","name":"binutils stabs type list","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y+xE0Fa4HqQq/1p0@squeak.grove.modra.org/mbox/"},{"id":57373,"url":"https://patchwork.plctlab.org/api/1.2/patches/57373/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y+x2gNcp9REGOj8e@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-02-15T06:06:56","name":"More ecoff sanity checks","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y+x2gNcp9REGOj8e@squeak.grove.modra.org/mbox/"},{"id":57417,"url":"https://patchwork.plctlab.org/api/1.2/patches/57417/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/56cd41d5-c0ba-d076-bf09-06612a2b54c3@suse.com/","msgid":"<56cd41d5-c0ba-d076-bf09-06612a2b54c3@suse.com>","list_archive_url":null,"date":"2023-02-15T07:44:24","name":"x86/gas: replace inappropriate assertion when parsing registers","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/56cd41d5-c0ba-d076-bf09-06612a2b54c3@suse.com/mbox/"},{"id":57485,"url":"https://patchwork.plctlab.org/api/1.2/patches/57485/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y+zDOBCppQShhWzW@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-02-15T11:34:16","name":"objdump -G memory leak","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y+zDOBCppQShhWzW@squeak.grove.modra.org/mbox/"},{"id":57486,"url":"https://patchwork.plctlab.org/api/1.2/patches/57486/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y+zDasJ/lS/QXsxw@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-02-15T11:35:06","name":"objdump read_section_stabs","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y+zDasJ/lS/QXsxw@squeak.grove.modra.org/mbox/"},{"id":57497,"url":"https://patchwork.plctlab.org/api/1.2/patches/57497/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230215114052.28292-2-binutils@emagii.com/","msgid":"<20230215114052.28292-2-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-15T11:40:47","name":"[v0,1/6] Add testsuite for ASCII command","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230215114052.28292-2-binutils@emagii.com/mbox/"},{"id":57488,"url":"https://patchwork.plctlab.org/api/1.2/patches/57488/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230215114052.28292-3-binutils@emagii.com/","msgid":"<20230215114052.28292-3-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-15T11:40:48","name":"[v0,2/6] Add ASCII command info to NEWS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230215114052.28292-3-binutils@emagii.com/mbox/"},{"id":57498,"url":"https://patchwork.plctlab.org/api/1.2/patches/57498/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230215114052.28292-4-binutils@emagii.com/","msgid":"<20230215114052.28292-4-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-15T11:40:49","name":"[v0,3/6] Add ASCII to info file","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230215114052.28292-4-binutils@emagii.com/mbox/"},{"id":57499,"url":"https://patchwork.plctlab.org/api/1.2/patches/57499/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230215114052.28292-5-binutils@emagii.com/","msgid":"<20230215114052.28292-5-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-15T11:40:50","name":"[v0,4/6] ldlex.l: add ASCII","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230215114052.28292-5-binutils@emagii.com/mbox/"},{"id":57490,"url":"https://patchwork.plctlab.org/api/1.2/patches/57490/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230215114052.28292-6-binutils@emagii.com/","msgid":"<20230215114052.28292-6-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-15T11:40:51","name":"[v0,5/6] ldgram.y: add ASCII","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230215114052.28292-6-binutils@emagii.com/mbox/"},{"id":57491,"url":"https://patchwork.plctlab.org/api/1.2/patches/57491/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230215114052.28292-7-binutils@emagii.com/","msgid":"<20230215114052.28292-7-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-15T11:40:52","name":"[v0,6/6] ldlang.*: parse ASCII command","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230215114052.28292-7-binutils@emagii.com/mbox/"},{"id":57650,"url":"https://patchwork.plctlab.org/api/1.2/patches/57650/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230215180303.620184-2-i.swmail@xen0n.name/","msgid":"<20230215180303.620184-2-i.swmail@xen0n.name>","list_archive_url":null,"date":"2023-02-15T18:02:58","name":"[v4,1/6] LoongArch: support disassembling certain pseudo-instructions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230215180303.620184-2-i.swmail@xen0n.name/mbox/"},{"id":57649,"url":"https://patchwork.plctlab.org/api/1.2/patches/57649/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230215180303.620184-3-i.swmail@xen0n.name/","msgid":"<20230215180303.620184-3-i.swmail@xen0n.name>","list_archive_url":null,"date":"2023-02-15T18:02:59","name":"[v4,2/6] opcodes/loongarch: remove unused code","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230215180303.620184-3-i.swmail@xen0n.name/mbox/"},{"id":57652,"url":"https://patchwork.plctlab.org/api/1.2/patches/57652/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230215180303.620184-4-i.swmail@xen0n.name/","msgid":"<20230215180303.620184-4-i.swmail@xen0n.name>","list_archive_url":null,"date":"2023-02-15T18:03:00","name":"[v4,3/6] opcodes/loongarch: implement style support in the disassembler","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230215180303.620184-4-i.swmail@xen0n.name/mbox/"},{"id":57651,"url":"https://patchwork.plctlab.org/api/1.2/patches/57651/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230215180303.620184-5-i.swmail@xen0n.name/","msgid":"<20230215180303.620184-5-i.swmail@xen0n.name>","list_archive_url":null,"date":"2023-02-15T18:03:01","name":"[v4,4/6] opcodes/loongarch: style disassembled address offsets as such","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230215180303.620184-5-i.swmail@xen0n.name/mbox/"},{"id":57654,"url":"https://patchwork.plctlab.org/api/1.2/patches/57654/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230215180303.620184-6-i.swmail@xen0n.name/","msgid":"<20230215180303.620184-6-i.swmail@xen0n.name>","list_archive_url":null,"date":"2023-02-15T18:03:02","name":"[v4,5/6] opcodes/loongarch: do not print hex notation for signed immediates","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230215180303.620184-6-i.swmail@xen0n.name/mbox/"},{"id":57653,"url":"https://patchwork.plctlab.org/api/1.2/patches/57653/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230215180303.620184-7-i.swmail@xen0n.name/","msgid":"<20230215180303.620184-7-i.swmail@xen0n.name>","list_archive_url":null,"date":"2023-02-15T18:03:03","name":"[v4,6/6] opcodes/loongarch: print unrecognized insn words with the .word directive","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230215180303.620184-7-i.swmail@xen0n.name/mbox/"},{"id":57811,"url":"https://patchwork.plctlab.org/api/1.2/patches/57811/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y+2O/JECc+OX2WWd@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-02-16T02:03:40","name":"gas_init","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y+2O/JECc+OX2WWd@squeak.grove.modra.org/mbox/"},{"id":57812,"url":"https://patchwork.plctlab.org/api/1.2/patches/57812/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y+2PQpJcZUJBOxco@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-02-16T02:04:50","name":"Delete PROGRESS macros","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y+2PQpJcZUJBOxco@squeak.grove.modra.org/mbox/"},{"id":57925,"url":"https://patchwork.plctlab.org/api/1.2/patches/57925/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f055cbdb-e706-3a74-ab63-725ed8a047fd@suse.com/","msgid":"","list_archive_url":null,"date":"2023-02-16T08:56:11","name":"RISC-V: as_warn() already emits a newline","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f055cbdb-e706-3a74-ab63-725ed8a047fd@suse.com/mbox/"},{"id":58064,"url":"https://patchwork.plctlab.org/api/1.2/patches/58064/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230216131905.1012-2-binutils@emagii.com/","msgid":"<20230216131905.1012-2-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-16T13:19:05","name":"[v0,1/1,RFC] Add support for CRC64 generation in linker","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230216131905.1012-2-binutils@emagii.com/mbox/"},{"id":58227,"url":"https://patchwork.plctlab.org/api/1.2/patches/58227/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230216204006.1977-2-binutils@emagii.com/","msgid":"<20230216204006.1977-2-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-16T20:40:01","name":"[v0,1/6] CRC64 header","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230216204006.1977-2-binutils@emagii.com/mbox/"},{"id":58228,"url":"https://patchwork.plctlab.org/api/1.2/patches/58228/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230216204006.1977-3-binutils@emagii.com/","msgid":"<20230216204006.1977-3-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-16T20:40:02","name":"[v0,2/6] ldlang.h: CRC64","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230216204006.1977-3-binutils@emagii.com/mbox/"},{"id":58229,"url":"https://patchwork.plctlab.org/api/1.2/patches/58229/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230216204006.1977-4-binutils@emagii.com/","msgid":"<20230216204006.1977-4-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-16T20:40:03","name":"[v0,3/6] ldlex.l: CRC64","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230216204006.1977-4-binutils@emagii.com/mbox/"},{"id":58230,"url":"https://patchwork.plctlab.org/api/1.2/patches/58230/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230216204006.1977-5-binutils@emagii.com/","msgid":"<20230216204006.1977-5-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-16T20:40:04","name":"[v0,4/6] ldgram.y: CRC64","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230216204006.1977-5-binutils@emagii.com/mbox/"},{"id":58232,"url":"https://patchwork.plctlab.org/api/1.2/patches/58232/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230216204006.1977-6-binutils@emagii.com/","msgid":"<20230216204006.1977-6-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-16T20:40:05","name":"[v0,5/6] ldlang.c: CRC64","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230216204006.1977-6-binutils@emagii.com/mbox/"},{"id":58231,"url":"https://patchwork.plctlab.org/api/1.2/patches/58231/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230216204006.1977-7-binutils@emagii.com/","msgid":"<20230216204006.1977-7-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-16T20:40:06","name":"[v0,6/6] ldlang.c: Try to get the .text section for checking CRC","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230216204006.1977-7-binutils@emagii.com/mbox/"},{"id":58259,"url":"https://patchwork.plctlab.org/api/1.2/patches/58259/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y+6nfaKgOuYb/KBD@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-02-16T22:00:29","name":"PR30046, power cmpi leads to unknown architecture","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y+6nfaKgOuYb/KBD@squeak.grove.modra.org/mbox/"},{"id":58321,"url":"https://patchwork.plctlab.org/api/1.2/patches/58321/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y+7ouisD+WH2nZn5@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-02-17T02:38:50","name":"Wild pointer reads in _bfd_ecoff_locate_line","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y+7ouisD+WH2nZn5@squeak.grove.modra.org/mbox/"},{"id":58346,"url":"https://patchwork.plctlab.org/api/1.2/patches/58346/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230217044033.2131866-1-vladimir.mezentsev@oracle.com/","msgid":"<20230217044033.2131866-1-vladimir.mezentsev@oracle.com>","list_archive_url":null,"date":"2023-02-17T04:40:33","name":"[1/2] gprofng: PR30036 Build failure on aarch64 w/ glibc: symbol `pwrite64'\'' is already defined","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230217044033.2131866-1-vladimir.mezentsev@oracle.com/mbox/"},{"id":58347,"url":"https://patchwork.plctlab.org/api/1.2/patches/58347/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230217044105.2133872-1-vladimir.mezentsev@oracle.com/","msgid":"<20230217044105.2133872-1-vladimir.mezentsev@oracle.com>","list_archive_url":null,"date":"2023-02-17T04:41:05","name":"[2/2] gprofng: fix Dwarf reader for DW_TAG_subprogram","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230217044105.2133872-1-vladimir.mezentsev@oracle.com/mbox/"},{"id":58348,"url":"https://patchwork.plctlab.org/api/1.2/patches/58348/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y+8HWSTBuPWN+K3i@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-02-17T04:49:29","name":"ld test asciz and ascii fails","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y+8HWSTBuPWN+K3i@squeak.grove.modra.org/mbox/"},{"id":58514,"url":"https://patchwork.plctlab.org/api/1.2/patches/58514/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230217112016.19718-2-binutils@emagii.com/","msgid":"<20230217112016.19718-2-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-17T11:20:12","name":"[v1,1/5] ldlex.l: CRC64","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230217112016.19718-2-binutils@emagii.com/mbox/"},{"id":58513,"url":"https://patchwork.plctlab.org/api/1.2/patches/58513/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230217112016.19718-3-binutils@emagii.com/","msgid":"<20230217112016.19718-3-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-17T11:20:13","name":"[v1,2/5] ldgram.y: CRC64","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230217112016.19718-3-binutils@emagii.com/mbox/"},{"id":58591,"url":"https://patchwork.plctlab.org/api/1.2/patches/58591/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230217135446.26053-2-binutils@emagii.com/","msgid":"<20230217135446.26053-2-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-17T13:54:42","name":"[v1,1/5] ldlex.l: CRC64","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230217135446.26053-2-binutils@emagii.com/mbox/"},{"id":58593,"url":"https://patchwork.plctlab.org/api/1.2/patches/58593/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230217135446.26053-3-binutils@emagii.com/","msgid":"<20230217135446.26053-3-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-17T13:54:43","name":"[v1,2/5] ldgram.y: CRC64","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230217135446.26053-3-binutils@emagii.com/mbox/"},{"id":58589,"url":"https://patchwork.plctlab.org/api/1.2/patches/58589/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230217135446.26053-4-binutils@emagii.com/","msgid":"<20230217135446.26053-4-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-17T13:54:44","name":"[v1,3/5] Calculate CRC64 over the .text area","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230217135446.26053-4-binutils@emagii.com/mbox/"},{"id":58590,"url":"https://patchwork.plctlab.org/api/1.2/patches/58590/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230217135446.26053-5-binutils@emagii.com/","msgid":"<20230217135446.26053-5-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-17T13:54:45","name":"[v1,4/5] CRC64 commands documentation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230217135446.26053-5-binutils@emagii.com/mbox/"},{"id":58592,"url":"https://patchwork.plctlab.org/api/1.2/patches/58592/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230217135446.26053-6-binutils@emagii.com/","msgid":"<20230217135446.26053-6-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-17T13:54:46","name":"[v1,5/5] CRC64 testsuite","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230217135446.26053-6-binutils@emagii.com/mbox/"},{"id":58650,"url":"https://patchwork.plctlab.org/api/1.2/patches/58650/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.LSU.2.20.2302171451390.16810@wotan.suse.de/","msgid":"","list_archive_url":null,"date":"2023-02-17T15:03:57","name":"[RFC] Move static archive dependencies into ld","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.LSU.2.20.2302171451390.16810@wotan.suse.de/mbox/"},{"id":58738,"url":"https://patchwork.plctlab.org/api/1.2/patches/58738/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230217174037.11911-2-binutils@emagii.com/","msgid":"<20230217174037.11911-2-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-17T17:40:33","name":"[v2,1/5] ldlex.l: CRC64","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230217174037.11911-2-binutils@emagii.com/mbox/"},{"id":58735,"url":"https://patchwork.plctlab.org/api/1.2/patches/58735/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230217174037.11911-3-binutils@emagii.com/","msgid":"<20230217174037.11911-3-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-17T17:40:34","name":"[v2,2/5] ldgram.y: CRC64","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230217174037.11911-3-binutils@emagii.com/mbox/"},{"id":58736,"url":"https://patchwork.plctlab.org/api/1.2/patches/58736/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230217174037.11911-4-binutils@emagii.com/","msgid":"<20230217174037.11911-4-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-17T17:40:35","name":"[v2,3/5] Calculate CRC64 over the .text area","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230217174037.11911-4-binutils@emagii.com/mbox/"},{"id":58734,"url":"https://patchwork.plctlab.org/api/1.2/patches/58734/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230217174037.11911-5-binutils@emagii.com/","msgid":"<20230217174037.11911-5-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-17T17:40:36","name":"[v2,4/5] CRC64 commands documentation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230217174037.11911-5-binutils@emagii.com/mbox/"},{"id":58737,"url":"https://patchwork.plctlab.org/api/1.2/patches/58737/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230217174037.11911-6-binutils@emagii.com/","msgid":"<20230217174037.11911-6-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-17T17:40:37","name":"[v2,5/5] CRC64 testsuite","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230217174037.11911-6-binutils@emagii.com/mbox/"},{"id":58757,"url":"https://patchwork.plctlab.org/api/1.2/patches/58757/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230217192905.3160819-2-tom@tromey.com/","msgid":"<20230217192905.3160819-2-tom@tromey.com>","list_archive_url":null,"date":"2023-02-17T19:29:02","name":"[1/4] Fix formatting of long function description in chew output","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230217192905.3160819-2-tom@tromey.com/mbox/"},{"id":58758,"url":"https://patchwork.plctlab.org/api/1.2/patches/58758/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230217192905.3160819-3-tom@tromey.com/","msgid":"<20230217192905.3160819-3-tom@tromey.com>","list_archive_url":null,"date":"2023-02-17T19:29:03","name":"[2/4] Don'\''t use chew comments for static functions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230217192905.3160819-3-tom@tromey.com/mbox/"},{"id":58756,"url":"https://patchwork.plctlab.org/api/1.2/patches/58756/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230217192905.3160819-4-tom@tromey.com/","msgid":"<20230217192905.3160819-4-tom@tromey.com>","list_archive_url":null,"date":"2023-02-17T19:29:04","name":"[3/4] Hoist the SECTION comment in opncls.c","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230217192905.3160819-4-tom@tromey.com/mbox/"},{"id":58755,"url":"https://patchwork.plctlab.org/api/1.2/patches/58755/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230217192905.3160819-5-tom@tromey.com/","msgid":"<20230217192905.3160819-5-tom@tromey.com>","list_archive_url":null,"date":"2023-02-17T19:29:05","name":"[4/4] Redefine FUNCTION in doc.str","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230217192905.3160819-5-tom@tromey.com/mbox/"},{"id":58951,"url":"https://patchwork.plctlab.org/api/1.2/patches/58951/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/877cwere3q.fsf@igel.home/","msgid":"<877cwere3q.fsf@igel.home>","list_archive_url":null,"date":"2023-02-18T19:02:49","name":"opcodes: style m68k disassembler output","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/877cwere3q.fsf@igel.home/mbox/"},{"id":59075,"url":"https://patchwork.plctlab.org/api/1.2/patches/59075/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y/GbxH+cM+iKG3WP@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-02-19T03:47:16","name":"Buffer overflow in evax_bfd_print_eobj","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y/GbxH+cM+iKG3WP@squeak.grove.modra.org/mbox/"},{"id":59334,"url":"https://patchwork.plctlab.org/api/1.2/patches/59334/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230219173450.25555-2-binutils@emagii.com/","msgid":"<20230219173450.25555-2-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-19T17:34:46","name":"[v3,1/5] CRC64 commands documentation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230219173450.25555-2-binutils@emagii.com/mbox/"},{"id":59332,"url":"https://patchwork.plctlab.org/api/1.2/patches/59332/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230219173450.25555-3-binutils@emagii.com/","msgid":"<20230219173450.25555-3-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-19T17:34:47","name":"[v3,2/5] CRC64 testsuite","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230219173450.25555-3-binutils@emagii.com/mbox/"},{"id":59333,"url":"https://patchwork.plctlab.org/api/1.2/patches/59333/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230219173450.25555-4-binutils@emagii.com/","msgid":"<20230219173450.25555-4-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-19T17:34:48","name":"[v3,3/5] ldlex.l: CRC64","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230219173450.25555-4-binutils@emagii.com/mbox/"},{"id":59331,"url":"https://patchwork.plctlab.org/api/1.2/patches/59331/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230219173450.25555-5-binutils@emagii.com/","msgid":"<20230219173450.25555-5-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-19T17:34:49","name":"[v3,4/5] ldgram.y: CRC64","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230219173450.25555-5-binutils@emagii.com/mbox/"},{"id":59340,"url":"https://patchwork.plctlab.org/api/1.2/patches/59340/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230219173450.25555-6-binutils@emagii.com/","msgid":"<20230219173450.25555-6-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-19T17:34:50","name":"[v3,5/5] Calculate CRC64 over the .text area","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230219173450.25555-6-binutils@emagii.com/mbox/"},{"id":59338,"url":"https://patchwork.plctlab.org/api/1.2/patches/59338/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230219194549.22554-2-binutils@emagii.com/","msgid":"<20230219194549.22554-2-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-19T19:45:45","name":"[v4,1/5] CRC64 commands documentation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230219194549.22554-2-binutils@emagii.com/mbox/"},{"id":59361,"url":"https://patchwork.plctlab.org/api/1.2/patches/59361/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230219194549.22554-3-binutils@emagii.com/","msgid":"<20230219194549.22554-3-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-19T19:45:46","name":"[v4,2/5] CRC64 testsuite","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230219194549.22554-3-binutils@emagii.com/mbox/"},{"id":59324,"url":"https://patchwork.plctlab.org/api/1.2/patches/59324/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230219194549.22554-4-binutils@emagii.com/","msgid":"<20230219194549.22554-4-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-19T19:45:47","name":"[v4,3/5] ldlex.l: CRC64","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230219194549.22554-4-binutils@emagii.com/mbox/"},{"id":59325,"url":"https://patchwork.plctlab.org/api/1.2/patches/59325/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230219194549.22554-5-binutils@emagii.com/","msgid":"<20230219194549.22554-5-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-19T19:45:48","name":"[v4,4/5] ldgram.y: CRC64","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230219194549.22554-5-binutils@emagii.com/mbox/"},{"id":59360,"url":"https://patchwork.plctlab.org/api/1.2/patches/59360/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230219194549.22554-6-binutils@emagii.com/","msgid":"<20230219194549.22554-6-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-19T19:45:49","name":"[v4,5/5] Calculate CRC64 over the .text area","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230219194549.22554-6-binutils@emagii.com/mbox/"},{"id":59371,"url":"https://patchwork.plctlab.org/api/1.2/patches/59371/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y/LTY//irZ06TbCl@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-02-20T01:56:51","name":"In-memory nested archives","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y/LTY//irZ06TbCl@squeak.grove.modra.org/mbox/"},{"id":59328,"url":"https://patchwork.plctlab.org/api/1.2/patches/59328/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230220082224.415968-1-chigot@adacore.com/","msgid":"<20230220082224.415968-1-chigot@adacore.com>","list_archive_url":null,"date":"2023-02-20T08:22:21","name":"[1/4] gas/testsuite: adjust a test for case insensitive file systems","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230220082224.415968-1-chigot@adacore.com/mbox/"},{"id":59350,"url":"https://patchwork.plctlab.org/api/1.2/patches/59350/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230220082224.415968-2-chigot@adacore.com/","msgid":"<20230220082224.415968-2-chigot@adacore.com>","list_archive_url":null,"date":"2023-02-20T08:22:22","name":"[2/4] ld/testsuite: don'\''t output to /dev/null on mingw hosts","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230220082224.415968-2-chigot@adacore.com/mbox/"},{"id":59358,"url":"https://patchwork.plctlab.org/api/1.2/patches/59358/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230220082224.415968-3-chigot@adacore.com/","msgid":"<20230220082224.415968-3-chigot@adacore.com>","list_archive_url":null,"date":"2023-02-20T08:22:23","name":"[3/4] ld/testsuite: adjust to Windows path separator.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230220082224.415968-3-chigot@adacore.com/mbox/"},{"id":59335,"url":"https://patchwork.plctlab.org/api/1.2/patches/59335/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230220082224.415968-4-chigot@adacore.com/","msgid":"<20230220082224.415968-4-chigot@adacore.com>","list_archive_url":null,"date":"2023-02-20T08:22:24","name":"[4/4] ld/testsuite: handle Windows drive letter in a noinit test","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230220082224.415968-4-chigot@adacore.com/mbox/"},{"id":59456,"url":"https://patchwork.plctlab.org/api/1.2/patches/59456/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230220141328.20441-1-mark@harmstone.com/","msgid":"<20230220141328.20441-1-mark@harmstone.com>","list_archive_url":null,"date":"2023-02-20T14:13:28","name":"ld: Sort section contributions in PDB files","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230220141328.20441-1-mark@harmstone.com/mbox/"},{"id":59466,"url":"https://patchwork.plctlab.org/api/1.2/patches/59466/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230220144302.1234792-1-chigot@adacore.com/","msgid":"<20230220144302.1234792-1-chigot@adacore.com>","list_archive_url":null,"date":"2023-02-20T14:43:02","name":"[v2] ld/testsuite: don'\''t output to /dev/null","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230220144302.1234792-1-chigot@adacore.com/mbox/"},{"id":59759,"url":"https://patchwork.plctlab.org/api/1.2/patches/59759/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230221040650.2337395-1-yunqiang.su@cipunited.com/","msgid":"<20230221040650.2337395-1-yunqiang.su@cipunited.com>","list_archive_url":null,"date":"2023-02-21T04:06:50","name":"MIPS: make mipsisa32 and mipsisa64 link more systematic","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230221040650.2337395-1-yunqiang.su@cipunited.com/mbox/"},{"id":59767,"url":"https://patchwork.plctlab.org/api/1.2/patches/59767/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y/RcPwp09t1wQTFF@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-02-21T05:53:03","name":"alpha-*-vms missing libraries","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y/RcPwp09t1wQTFF@squeak.grove.modra.org/mbox/"},{"id":59769,"url":"https://patchwork.plctlab.org/api/1.2/patches/59769/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y/RcV7KZ8EOf9LeQ@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-02-21T05:53:27","name":"ld-libs test on alpha-vms","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y/RcV7KZ8EOf9LeQ@squeak.grove.modra.org/mbox/"},{"id":59768,"url":"https://patchwork.plctlab.org/api/1.2/patches/59768/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y/RcdkYHUwcnAETA@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-02-21T05:53:58","name":"Both FAIL and PASS \"check sections 2\"?","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y/RcdkYHUwcnAETA@squeak.grove.modra.org/mbox/"},{"id":59807,"url":"https://patchwork.plctlab.org/api/1.2/patches/59807/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230221090331.559683-1-chigot@adacore.com/","msgid":"<20230221090331.559683-1-chigot@adacore.com>","list_archive_url":null,"date":"2023-02-21T09:03:31","name":"ld/testsuite: handle Windows drive letter in persistent section","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230221090331.559683-1-chigot@adacore.com/mbox/"},{"id":59864,"url":"https://patchwork.plctlab.org/api/1.2/patches/59864/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/87v8jv9snh.fsf@redhat.com/","msgid":"<87v8jv9snh.fsf@redhat.com>","list_archive_url":null,"date":"2023-02-21T11:14:58","name":"Commit: Update description of bfd_fill_in_gnu_debuglink_section","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/87v8jv9snh.fsf@redhat.com/mbox/"},{"id":60156,"url":"https://patchwork.plctlab.org/api/1.2/patches/60156/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230221161442.1554824-1-chigot@adacore.com/","msgid":"<20230221161442.1554824-1-chigot@adacore.com>","list_archive_url":null,"date":"2023-02-21T16:14:42","name":"testsuite: prune DOS drive letter in test outputs","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230221161442.1554824-1-chigot@adacore.com/mbox/"},{"id":60284,"url":"https://patchwork.plctlab.org/api/1.2/patches/60284/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y/VMwx4rDcB3csbz@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-02-21T22:59:15","name":"debug_link duplicate file size checks","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y/VMwx4rDcB3csbz@squeak.grove.modra.org/mbox/"},{"id":60522,"url":"https://patchwork.plctlab.org/api/1.2/patches/60522/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2767901e-2ebc-f42f-982b-1b9b6df3b18f@suse.com/","msgid":"<2767901e-2ebc-f42f-982b-1b9b6df3b18f@suse.com>","list_archive_url":null,"date":"2023-02-22T13:14:48","name":"x86: avoid .byte in testcases where possible","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2767901e-2ebc-f42f-982b-1b9b6df3b18f@suse.com/mbox/"},{"id":60572,"url":"https://patchwork.plctlab.org/api/1.2/patches/60572/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230222151639.588269-1-chigot@adacore.com/","msgid":"<20230222151639.588269-1-chigot@adacore.com>","list_archive_url":null,"date":"2023-02-22T15:16:39","name":"[v2] testsuite: prune DOS drive letter in test outputs","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230222151639.588269-1-chigot@adacore.com/mbox/"},{"id":60602,"url":"https://patchwork.plctlab.org/api/1.2/patches/60602/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230222161609.239928-2-binutils@emagii.com/","msgid":"<20230222161609.239928-2-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-22T16:16:00","name":"[v5,01/10] TIMESTAMP: ldlang: process","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230222161609.239928-2-binutils@emagii.com/mbox/"},{"id":60606,"url":"https://patchwork.plctlab.org/api/1.2/patches/60606/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230222161609.239928-3-binutils@emagii.com/","msgid":"<20230222161609.239928-3-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-22T16:16:01","name":"[v5,02/10] DIGEST: NEWS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230222161609.239928-3-binutils@emagii.com/mbox/"},{"id":60597,"url":"https://patchwork.plctlab.org/api/1.2/patches/60597/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230222161609.239928-4-binutils@emagii.com/","msgid":"<20230222161609.239928-4-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-22T16:16:02","name":"[v5,03/10] DIGEST: ld.texi","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230222161609.239928-4-binutils@emagii.com/mbox/"},{"id":60599,"url":"https://patchwork.plctlab.org/api/1.2/patches/60599/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230222161609.239928-5-binutils@emagii.com/","msgid":"<20230222161609.239928-5-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-22T16:16:03","name":"[v5,04/10] LIBCRC: license","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230222161609.239928-5-binutils@emagii.com/mbox/"},{"id":60604,"url":"https://patchwork.plctlab.org/api/1.2/patches/60604/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230222161609.239928-6-binutils@emagii.com/","msgid":"<20230222161609.239928-6-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-22T16:16:04","name":"[v5,05/10] DIGEST: ldlex.l","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230222161609.239928-6-binutils@emagii.com/mbox/"},{"id":60608,"url":"https://patchwork.plctlab.org/api/1.2/patches/60608/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230222161609.239928-7-binutils@emagii.com/","msgid":"<20230222161609.239928-7-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-22T16:16:05","name":"[v5,06/10] DIGEST: ldgram.y","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230222161609.239928-7-binutils@emagii.com/mbox/"},{"id":60609,"url":"https://patchwork.plctlab.org/api/1.2/patches/60609/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230222161609.239928-8-binutils@emagii.com/","msgid":"<20230222161609.239928-8-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-22T16:16:06","name":"[v5,07/10] DIGEST: Makefile.am: add new files","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230222161609.239928-8-binutils@emagii.com/mbox/"},{"id":60603,"url":"https://patchwork.plctlab.org/api/1.2/patches/60603/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230222161609.239928-9-binutils@emagii.com/","msgid":"<20230222161609.239928-9-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-22T16:16:07","name":"[v5,08/10] DIGEST: CRC-32/64 algorithms","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230222161609.239928-9-binutils@emagii.com/mbox/"},{"id":60605,"url":"https://patchwork.plctlab.org/api/1.2/patches/60605/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230222161609.239928-10-binutils@emagii.com/","msgid":"<20230222161609.239928-10-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-22T16:16:08","name":"[v5,09/10] DIGEST: ldmain.c: add CRC calculation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230222161609.239928-10-binutils@emagii.com/mbox/"},{"id":60607,"url":"https://patchwork.plctlab.org/api/1.2/patches/60607/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230222161609.239928-11-binutils@emagii.com/","msgid":"<20230222161609.239928-11-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-22T16:16:09","name":"[v5,10/10] DIGEST: testsuite","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230222161609.239928-11-binutils@emagii.com/mbox/"},{"id":60774,"url":"https://patchwork.plctlab.org/api/1.2/patches/60774/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y/biKm/PHgcgid9l@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-02-23T03:48:58","name":"Test SEC_HAS_CONTENTS before reading section contents","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y/biKm/PHgcgid9l@squeak.grove.modra.org/mbox/"},{"id":60775,"url":"https://patchwork.plctlab.org/api/1.2/patches/60775/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y/biSBwPDeTjESNU@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-02-23T03:49:28","name":"Test SEC_HAS_CONTENTS in relax routines","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y/biSBwPDeTjESNU@squeak.grove.modra.org/mbox/"},{"id":60776,"url":"https://patchwork.plctlab.org/api/1.2/patches/60776/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y/biZsHVn/HEmkal@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-02-23T03:49:58","name":"ip2k: don'\''t look at stab sections without relocs","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y/biZsHVn/HEmkal@squeak.grove.modra.org/mbox/"},{"id":60777,"url":"https://patchwork.plctlab.org/api/1.2/patches/60777/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y/bii4z1P2p0EwAC@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-02-23T03:50:35","name":"dwarf1 .line SEC_HAS_CONTENTS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y/bii4z1P2p0EwAC@squeak.grove.modra.org/mbox/"},{"id":60907,"url":"https://patchwork.plctlab.org/api/1.2/patches/60907/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230223110417.63915-1-chigot@adacore.com/","msgid":"<20230223110417.63915-1-chigot@adacore.com>","list_archive_url":null,"date":"2023-02-23T11:04:17","name":"[v3] testsuite: prune DOS drive letter in test outputs","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230223110417.63915-1-chigot@adacore.com/mbox/"},{"id":60908,"url":"https://patchwork.plctlab.org/api/1.2/patches/60908/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230223111115.3752443-1-yunqiang.su@cipunited.com/","msgid":"<20230223111115.3752443-1-yunqiang.su@cipunited.com>","list_archive_url":null,"date":"2023-02-23T11:11:15","name":"MIPS: support specify isa level when configure","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230223111115.3752443-1-yunqiang.su@cipunited.com/mbox/"},{"id":60954,"url":"https://patchwork.plctlab.org/api/1.2/patches/60954/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230223124519.4228-1-tdevries@suse.de/","msgid":"<20230223124519.4228-1-tdevries@suse.de>","list_archive_url":null,"date":"2023-02-23T12:45:19","name":"gas: Add --force-compress-debug-sections","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230223124519.4228-1-tdevries@suse.de/mbox/"},{"id":61014,"url":"https://patchwork.plctlab.org/api/1.2/patches/61014/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/877651c1-3d70-6985-54b3-e4416bed3048@arm.com/","msgid":"<877651c1-3d70-6985-54b3-e4416bed3048@arm.com>","list_archive_url":null,"date":"2023-02-23T15:18:03","name":"[GAS,Aarch64] Add Binutils support for MEC","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/877651c1-3d70-6985-54b3-e4416bed3048@arm.com/mbox/"},{"id":61037,"url":"https://patchwork.plctlab.org/api/1.2/patches/61037/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/87bklkths4.fsf@redhat.com/","msgid":"<87bklkths4.fsf@redhat.com>","list_archive_url":null,"date":"2023-02-23T17:26:19","name":"Commit: Better caching in elf_find_function","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/87bklkths4.fsf@redhat.com/mbox/"},{"id":61175,"url":"https://patchwork.plctlab.org/api/1.2/patches/61175/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y/htA80wwgArcHQ0@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-02-24T07:53:39","name":"PR30155, ld segfault in _bfd_nearby_section","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y/htA80wwgArcHQ0@squeak.grove.modra.org/mbox/"},{"id":61302,"url":"https://patchwork.plctlab.org/api/1.2/patches/61302/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fe210be6-76c8-155f-f151-15ce767b133f@suse.com/","msgid":"","list_archive_url":null,"date":"2023-02-24T13:02:22","name":"gas: default .debug section compression method adjustments","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fe210be6-76c8-155f-f151-15ce767b133f@suse.com/mbox/"},{"id":61306,"url":"https://patchwork.plctlab.org/api/1.2/patches/61306/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3dba3751-3fa1-0684-b98c-2c383f26c5a6@suse.com/","msgid":"<3dba3751-3fa1-0684-b98c-2c383f26c5a6@suse.com>","list_archive_url":null,"date":"2023-02-24T13:08:25","name":"[1/2] x86: drop redundant calculation of EVEX broadcast size","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3dba3751-3fa1-0684-b98c-2c383f26c5a6@suse.com/mbox/"},{"id":61307,"url":"https://patchwork.plctlab.org/api/1.2/patches/61307/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a68e2ee4-9198-664e-4e62-245ff29494fc@suse.com/","msgid":"","list_archive_url":null,"date":"2023-02-24T13:09:14","name":"[2/2] x86: use swap_2_operands() in build_vex_prefix()","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a68e2ee4-9198-664e-4e62-245ff29494fc@suse.com/mbox/"},{"id":61506,"url":"https://patchwork.plctlab.org/api/1.2/patches/61506/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/87ilfqjb5y.fsf@redhat.com/","msgid":"<87ilfqjb5y.fsf@redhat.com>","list_archive_url":null,"date":"2023-02-25T10:23:53","name":"[PUSHED] Enable styling for GDB (Was: [PATCH] opcodes: style m68k disassembler output)","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/87ilfqjb5y.fsf@redhat.com/mbox/"},{"id":61690,"url":"https://patchwork.plctlab.org/api/1.2/patches/61690/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230227005935.12270-1-mark@harmstone.com/","msgid":"<20230227005935.12270-1-mark@harmstone.com>","list_archive_url":null,"date":"2023-02-27T00:59:35","name":"[v2] ld: Sort section contributions in PDB files","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230227005935.12270-1-mark@harmstone.com/mbox/"},{"id":61924,"url":"https://patchwork.plctlab.org/api/1.2/patches/61924/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9eb9eaf6-2cff-360b-3de6-072d3f8185dc@suse.de/","msgid":"<9eb9eaf6-2cff-360b-3de6-072d3f8185dc@suse.de>","list_archive_url":null,"date":"2023-02-27T11:43:09","name":"gas: Add --compress-debug-sections=force","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9eb9eaf6-2cff-360b-3de6-072d3f8185dc@suse.de/mbox/"},{"id":61954,"url":"https://patchwork.plctlab.org/api/1.2/patches/61954/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230227134135.462271-1-chigot@adacore.com/","msgid":"<20230227134135.462271-1-chigot@adacore.com>","list_archive_url":null,"date":"2023-02-27T13:41:35","name":"gas/testsuite: adjust another test for case insensitive file systems","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230227134135.462271-1-chigot@adacore.com/mbox/"},{"id":62196,"url":"https://patchwork.plctlab.org/api/1.2/patches/62196/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y/1FKI3FT2qt6LnH@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-02-28T00:04:56","name":"Another PE SEC_HAS_CONTENTS test","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y/1FKI3FT2qt6LnH@squeak.grove.modra.org/mbox/"},{"id":62197,"url":"https://patchwork.plctlab.org/api/1.2/patches/62197/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y/1FWTrLectdFgCl@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-02-28T00:05:45","name":"Add some sanity checking in ECOFF lookup_line","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y/1FWTrLectdFgCl@squeak.grove.modra.org/mbox/"},{"id":62198,"url":"https://patchwork.plctlab.org/api/1.2/patches/62198/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y/1FjDQ7XxwI4Zxz@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-02-28T00:06:36","name":"Free ecoff debug info","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y/1FjDQ7XxwI4Zxz@squeak.grove.modra.org/mbox/"},{"id":62205,"url":"https://patchwork.plctlab.org/api/1.2/patches/62205/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230228001633.3602-1-tdevries@suse.de/","msgid":"<20230228001633.3602-1-tdevries@suse.de>","list_archive_url":null,"date":"2023-02-28T00:16:31","name":"[v2,1/3] gas: Unify parsing of --compress-debug-sections","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230228001633.3602-1-tdevries@suse.de/mbox/"},{"id":62206,"url":"https://patchwork.plctlab.org/api/1.2/patches/62206/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230228001633.3602-2-tdevries@suse.de/","msgid":"<20230228001633.3602-2-tdevries@suse.de>","list_archive_url":null,"date":"2023-02-28T00:16:32","name":"[v2,2/3] gas: Handle --compress-debug-sections=subopt1,subopt2","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230228001633.3602-2-tdevries@suse.de/mbox/"},{"id":62204,"url":"https://patchwork.plctlab.org/api/1.2/patches/62204/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230228001633.3602-3-tdevries@suse.de/","msgid":"<20230228001633.3602-3-tdevries@suse.de>","list_archive_url":null,"date":"2023-02-28T00:16:33","name":"[v2,3/3] gas: Add --compress-debug-sections={heuristic-always, heuristic-sizewin}","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230228001633.3602-3-tdevries@suse.de/mbox/"},{"id":62220,"url":"https://patchwork.plctlab.org/api/1.2/patches/62220/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y/1M54x/w6QMpPfQ@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-02-28T00:37:59","name":"chew.c printf of intptr_t","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y/1M54x/w6QMpPfQ@squeak.grove.modra.org/mbox/"},{"id":62640,"url":"https://patchwork.plctlab.org/api/1.2/patches/62640/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2efba8824df3f1bc782b9bd9aa598e2dae02f9ca.1677620627.git.aburgess@redhat.com/","msgid":"<2efba8824df3f1bc782b9bd9aa598e2dae02f9ca.1677620627.git.aburgess@redhat.com>","list_archive_url":null,"date":"2023-02-28T21:44:06","name":"opcodes/arm: adjust whitespace in cpsie instruction","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2efba8824df3f1bc782b9bd9aa598e2dae02f9ca.1677620627.git.aburgess@redhat.com/mbox/"},{"id":62664,"url":"https://patchwork.plctlab.org/api/1.2/patches/62664/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230228224937.3832887-1-dilfridge@gentoo.org/","msgid":"<20230228224937.3832887-1-dilfridge@gentoo.org>","list_archive_url":null,"date":"2023-02-28T22:49:37","name":"[needs,more,eyes] Relink also libopcodes and libgprofng to newly built libiberty.a","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230228224937.3832887-1-dilfridge@gentoo.org/mbox/"}],"public":true,"mbox":"https://patchwork.plctlab.org/bundle/patchwork-bot/binutils-gdb_2023-02/mbox/"},{"id":17,"url":"https://patchwork.plctlab.org/api/1.2/bundles/17/","web_url":"https://patchwork.plctlab.org/bundle/patchwork-bot/binutils-gdb_2023-03/","project":{"id":2,"url":"https://patchwork.plctlab.org/api/1.2/projects/2/","name":"binutils-gdb","link_name":"binutils-gdb","list_id":"binutils.sourceware.org","list_email":"binutils@sourceware.org","web_url":"https://github.com/wangliu-iscas/Patchwork-Bundles/blob/main/binutils-gdb.md","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"name":"binutils-gdb_2023-03","owner":{"id":3,"url":"https://patchwork.plctlab.org/api/1.2/users/3/","username":"patchwork-bot","first_name":"","last_name":"","email":"ouuuleilei@gmail.com"},"patches":[{"id":62751,"url":"https://patchwork.plctlab.org/api/1.2/patches/62751/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y/7Nlh7yA1PLiIvj@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-01T03:59:18","name":"Memory leak in gas do_repeat","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y/7Nlh7yA1PLiIvj@squeak.grove.modra.org/mbox/"},{"id":62752,"url":"https://patchwork.plctlab.org/api/1.2/patches/62752/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y/7Nw2XouT8JokFm@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-01T04:00:03","name":"gas s_fill caused internal error in frag_new","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y/7Nw2XouT8JokFm@squeak.grove.modra.org/mbox/"},{"id":62753,"url":"https://patchwork.plctlab.org/api/1.2/patches/62753/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y/7N5GnBecgnIXQx@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-01T04:00:36","name":"Catch overflow in gas s_space","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y/7N5GnBecgnIXQx@squeak.grove.modra.org/mbox/"},{"id":62932,"url":"https://patchwork.plctlab.org/api/1.2/patches/62932/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301144756.1847278-2-binutils@emagii.com/","msgid":"<20230301144756.1847278-2-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-01T14:47:46","name":"[v6,01/11] DIGEST: LICENSING","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301144756.1847278-2-binutils@emagii.com/mbox/"},{"id":62934,"url":"https://patchwork.plctlab.org/api/1.2/patches/62934/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301144756.1847278-3-binutils@emagii.com/","msgid":"<20230301144756.1847278-3-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-01T14:47:47","name":"[v6,02/11] DIGEST: NEWS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301144756.1847278-3-binutils@emagii.com/mbox/"},{"id":62935,"url":"https://patchwork.plctlab.org/api/1.2/patches/62935/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301144756.1847278-4-binutils@emagii.com/","msgid":"<20230301144756.1847278-4-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-01T14:47:48","name":"[v6,03/11] DIGEST: Documentation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301144756.1847278-4-binutils@emagii.com/mbox/"},{"id":62933,"url":"https://patchwork.plctlab.org/api/1.2/patches/62933/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301144756.1847278-5-binutils@emagii.com/","msgid":"<20230301144756.1847278-5-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-01T14:47:49","name":"[v6,04/11] DIGEST: testsuite","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301144756.1847278-5-binutils@emagii.com/mbox/"},{"id":62937,"url":"https://patchwork.plctlab.org/api/1.2/patches/62937/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301144756.1847278-6-binutils@emagii.com/","msgid":"<20230301144756.1847278-6-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-01T14:47:50","name":"[v6,05/11] DIGEST: ldlex.l","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301144756.1847278-6-binutils@emagii.com/mbox/"},{"id":62941,"url":"https://patchwork.plctlab.org/api/1.2/patches/62941/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301144756.1847278-7-binutils@emagii.com/","msgid":"<20230301144756.1847278-7-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-01T14:47:51","name":"[v6,06/11] DIGEST: ldgram.y","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301144756.1847278-7-binutils@emagii.com/mbox/"},{"id":62939,"url":"https://patchwork.plctlab.org/api/1.2/patches/62939/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301144756.1847278-8-binutils@emagii.com/","msgid":"<20230301144756.1847278-8-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-01T14:47:52","name":"[v6,07/11] DIGEST: ldmain.c","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301144756.1847278-8-binutils@emagii.com/mbox/"},{"id":62940,"url":"https://patchwork.plctlab.org/api/1.2/patches/62940/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301144756.1847278-9-binutils@emagii.com/","msgid":"<20230301144756.1847278-9-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-01T14:47:53","name":"[v6,08/11] DIGEST: ldlang.*: add timestamp","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301144756.1847278-9-binutils@emagii.com/mbox/"},{"id":62944,"url":"https://patchwork.plctlab.org/api/1.2/patches/62944/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301144756.1847278-10-binutils@emagii.com/","msgid":"<20230301144756.1847278-10-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-01T14:47:54","name":"[v6,09/11] DIGEST: calculation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301144756.1847278-10-binutils@emagii.com/mbox/"},{"id":62936,"url":"https://patchwork.plctlab.org/api/1.2/patches/62936/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301144756.1847278-11-binutils@emagii.com/","msgid":"<20230301144756.1847278-11-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-01T14:47:55","name":"[v6,10/11] DIGEST: Makefile.*","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301144756.1847278-11-binutils@emagii.com/mbox/"},{"id":62947,"url":"https://patchwork.plctlab.org/api/1.2/patches/62947/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301144756.1847278-12-binutils@emagii.com/","msgid":"<20230301144756.1847278-12-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-01T14:47:56","name":"[v6,11/11] Build ldint","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301144756.1847278-12-binutils@emagii.com/mbox/"},{"id":62967,"url":"https://patchwork.plctlab.org/api/1.2/patches/62967/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301154513.1850449-2-binutils@emagii.com/","msgid":"<20230301154513.1850449-2-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-01T15:45:03","name":"[v7,01/11] DIGEST: LICENSING","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301154513.1850449-2-binutils@emagii.com/mbox/"},{"id":62966,"url":"https://patchwork.plctlab.org/api/1.2/patches/62966/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301154513.1850449-3-binutils@emagii.com/","msgid":"<20230301154513.1850449-3-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-01T15:45:04","name":"[v7,02/11] DIGEST: NEWS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301154513.1850449-3-binutils@emagii.com/mbox/"},{"id":62971,"url":"https://patchwork.plctlab.org/api/1.2/patches/62971/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301154513.1850449-4-binutils@emagii.com/","msgid":"<20230301154513.1850449-4-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-01T15:45:05","name":"[v7,03/11] DIGEST: Documentation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301154513.1850449-4-binutils@emagii.com/mbox/"},{"id":62973,"url":"https://patchwork.plctlab.org/api/1.2/patches/62973/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301154513.1850449-5-binutils@emagii.com/","msgid":"<20230301154513.1850449-5-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-01T15:45:06","name":"[v7,04/11] DIGEST: testsuite","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301154513.1850449-5-binutils@emagii.com/mbox/"},{"id":62972,"url":"https://patchwork.plctlab.org/api/1.2/patches/62972/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301154513.1850449-6-binutils@emagii.com/","msgid":"<20230301154513.1850449-6-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-01T15:45:07","name":"[v7,05/11] DIGEST: ldlex.l","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301154513.1850449-6-binutils@emagii.com/mbox/"},{"id":62974,"url":"https://patchwork.plctlab.org/api/1.2/patches/62974/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301154513.1850449-7-binutils@emagii.com/","msgid":"<20230301154513.1850449-7-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-01T15:45:08","name":"[v7,06/11] DIGEST: ldgram.y","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301154513.1850449-7-binutils@emagii.com/mbox/"},{"id":62968,"url":"https://patchwork.plctlab.org/api/1.2/patches/62968/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301154513.1850449-8-binutils@emagii.com/","msgid":"<20230301154513.1850449-8-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-01T15:45:09","name":"[v7,07/11] DIGEST: ldmain.c","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301154513.1850449-8-binutils@emagii.com/mbox/"},{"id":62994,"url":"https://patchwork.plctlab.org/api/1.2/patches/62994/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301173022.1851188-8-binutils@emagii.com/","msgid":"<20230301173022.1851188-8-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-01T17:30:19","name":"[v7,08/11] DIGEST: ldlang.*: add timestamp","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301173022.1851188-8-binutils@emagii.com/mbox/"},{"id":62997,"url":"https://patchwork.plctlab.org/api/1.2/patches/62997/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301173022.1851188-9-binutils@emagii.com/","msgid":"<20230301173022.1851188-9-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-01T17:30:20","name":"[v7,09/11] DIGEST: calculation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301173022.1851188-9-binutils@emagii.com/mbox/"},{"id":62995,"url":"https://patchwork.plctlab.org/api/1.2/patches/62995/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301173022.1851188-10-binutils@emagii.com/","msgid":"<20230301173022.1851188-10-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-01T17:30:21","name":"[v7,10/11] DIGEST: Makefile.*","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301173022.1851188-10-binutils@emagii.com/mbox/"},{"id":62996,"url":"https://patchwork.plctlab.org/api/1.2/patches/62996/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301173022.1851188-11-binutils@emagii.com/","msgid":"<20230301173022.1851188-11-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-01T17:30:22","name":"[v7,11/11] Build ldint","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301173022.1851188-11-binutils@emagii.com/mbox/"},{"id":62999,"url":"https://patchwork.plctlab.org/api/1.2/patches/62999/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301174325.1858522-2-binutils@emagii.com/","msgid":"<20230301174325.1858522-2-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-01T17:43:15","name":"[v8,01/11] DIGEST: LICENSING","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301174325.1858522-2-binutils@emagii.com/mbox/"},{"id":63002,"url":"https://patchwork.plctlab.org/api/1.2/patches/63002/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301174325.1858522-3-binutils@emagii.com/","msgid":"<20230301174325.1858522-3-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-01T17:43:16","name":"[v8,02/11] DIGEST: NEWS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301174325.1858522-3-binutils@emagii.com/mbox/"},{"id":63000,"url":"https://patchwork.plctlab.org/api/1.2/patches/63000/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301174325.1858522-4-binutils@emagii.com/","msgid":"<20230301174325.1858522-4-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-01T17:43:17","name":"[v8,03/11] DIGEST: Documentation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301174325.1858522-4-binutils@emagii.com/mbox/"},{"id":63001,"url":"https://patchwork.plctlab.org/api/1.2/patches/63001/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301174325.1858522-5-binutils@emagii.com/","msgid":"<20230301174325.1858522-5-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-01T17:43:18","name":"[v8,04/11] DIGEST: testsuite","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301174325.1858522-5-binutils@emagii.com/mbox/"},{"id":63005,"url":"https://patchwork.plctlab.org/api/1.2/patches/63005/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301174325.1858522-6-binutils@emagii.com/","msgid":"<20230301174325.1858522-6-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-01T17:43:19","name":"[v8,05/11] DIGEST: ldlex.l","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301174325.1858522-6-binutils@emagii.com/mbox/"},{"id":63006,"url":"https://patchwork.plctlab.org/api/1.2/patches/63006/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301174325.1858522-7-binutils@emagii.com/","msgid":"<20230301174325.1858522-7-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-01T17:43:20","name":"[v8,06/11] DIGEST: ldgram.y","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301174325.1858522-7-binutils@emagii.com/mbox/"},{"id":63007,"url":"https://patchwork.plctlab.org/api/1.2/patches/63007/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301174325.1858522-8-binutils@emagii.com/","msgid":"<20230301174325.1858522-8-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-01T17:43:21","name":"[v8,07/11] DIGEST: ldmain.c","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301174325.1858522-8-binutils@emagii.com/mbox/"},{"id":63008,"url":"https://patchwork.plctlab.org/api/1.2/patches/63008/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301174325.1858522-9-binutils@emagii.com/","msgid":"<20230301174325.1858522-9-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-01T17:43:22","name":"[v8,08/11] DIGEST: ldlang.*: add timestamp","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301174325.1858522-9-binutils@emagii.com/mbox/"},{"id":63010,"url":"https://patchwork.plctlab.org/api/1.2/patches/63010/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301174325.1858522-10-binutils@emagii.com/","msgid":"<20230301174325.1858522-10-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-01T17:43:23","name":"[v8,09/11] DIGEST: calculation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301174325.1858522-10-binutils@emagii.com/mbox/"},{"id":63011,"url":"https://patchwork.plctlab.org/api/1.2/patches/63011/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301174325.1858522-11-binutils@emagii.com/","msgid":"<20230301174325.1858522-11-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-01T17:43:24","name":"[v8,10/11] DIGEST: Makefile.*","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301174325.1858522-11-binutils@emagii.com/mbox/"},{"id":63004,"url":"https://patchwork.plctlab.org/api/1.2/patches/63004/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301174325.1858522-12-binutils@emagii.com/","msgid":"<20230301174325.1858522-12-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-01T17:43:25","name":"[v8,11/11] Build ldint","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301174325.1858522-12-binutils@emagii.com/mbox/"},{"id":63103,"url":"https://patchwork.plctlab.org/api/1.2/patches/63103/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y//K/QCIk6YuuRF3@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-01T22:00:29","name":"Using .mri in assembly","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y//K/QCIk6YuuRF3@squeak.grove.modra.org/mbox/"},{"id":63104,"url":"https://patchwork.plctlab.org/api/1.2/patches/63104/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y//LGl4CuJ+YN+i5@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-01T22:00:58","name":"More bounds checking in macro_expand","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y//LGl4CuJ+YN+i5@squeak.grove.modra.org/mbox/"},{"id":63167,"url":"https://patchwork.plctlab.org/api/1.2/patches/63167/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230302015222.291088-1-yunqiang.su@cipunited.com/","msgid":"<20230302015222.291088-1-yunqiang.su@cipunited.com>","list_archive_url":null,"date":"2023-03-02T01:52:22","name":"[v2] MIPS: make mipsisa32 and mipsisa64 link more systematic","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230302015222.291088-1-yunqiang.su@cipunited.com/mbox/"},{"id":63263,"url":"https://patchwork.plctlab.org/api/1.2/patches/63263/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230302080137.3346439-1-i.swmail@xen0n.name/","msgid":"<20230302080137.3346439-1-i.swmail@xen0n.name>","list_archive_url":null,"date":"2023-03-02T08:01:37","name":"elfedit: add support for editing e_flags","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230302080137.3346439-1-i.swmail@xen0n.name/mbox/"},{"id":63267,"url":"https://patchwork.plctlab.org/api/1.2/patches/63267/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230302081452.3429908-1-i.swmail@xen0n.name/","msgid":"<20230302081452.3429908-1-i.swmail@xen0n.name>","list_archive_url":null,"date":"2023-03-02T08:14:52","name":"[RESEND] elfedit: add support for editing e_flags","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230302081452.3429908-1-i.swmail@xen0n.name/mbox/"},{"id":63360,"url":"https://patchwork.plctlab.org/api/1.2/patches/63360/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230302112531.200647-2-cupertino.miranda@oracle.com/","msgid":"<20230302112531.200647-2-cupertino.miranda@oracle.com>","list_archive_url":null,"date":"2023-03-02T11:25:31","name":"BPF relocations review / refactoring","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230302112531.200647-2-cupertino.miranda@oracle.com/mbox/"},{"id":63387,"url":"https://patchwork.plctlab.org/api/1.2/patches/63387/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZACQFdX4P07PysEc@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-02T12:01:25","name":"Don'\''t write zeros to a gap in the output file","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZACQFdX4P07PysEc@squeak.grove.modra.org/mbox/"},{"id":63554,"url":"https://patchwork.plctlab.org/api/1.2/patches/63554/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230302201029.vflqmyjxh7qnyxa3@google.com/","msgid":"<20230302201029.vflqmyjxh7qnyxa3@google.com>","list_archive_url":null,"date":"2023-03-02T20:10:29","name":"[v2] ld: Allow R_X86_64_GOTPCREL for call *__tls_get_addr@GOTPCREL(%rip)","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230302201029.vflqmyjxh7qnyxa3@google.com/mbox/"},{"id":63555,"url":"https://patchwork.plctlab.org/api/1.2/patches/63555/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230302201722.1304941-1-maskray@google.com/","msgid":"<20230302201722.1304941-1-maskray@google.com>","list_archive_url":null,"date":"2023-03-02T20:17:22","name":"[v2] ld: Allow R_386_GOT32 for call *__tls_get_addr@GOT(%reg)","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230302201722.1304941-1-maskray@google.com/mbox/"},{"id":63603,"url":"https://patchwork.plctlab.org/api/1.2/patches/63603/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230302220408.1925678-2-binutils@emagii.com/","msgid":"<20230302220408.1925678-2-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-02T22:03:58","name":"[v9,01/11,gdb/testsuite] Fix gdb.rust/watch.exp on ppc64le","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230302220408.1925678-2-binutils@emagii.com/mbox/"},{"id":63598,"url":"https://patchwork.plctlab.org/api/1.2/patches/63598/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230302220408.1925678-3-binutils@emagii.com/","msgid":"<20230302220408.1925678-3-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-02T22:03:59","name":"[v9,02/11] Remove value_in","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230302220408.1925678-3-binutils@emagii.com/mbox/"},{"id":63607,"url":"https://patchwork.plctlab.org/api/1.2/patches/63607/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230302220408.1925678-4-binutils@emagii.com/","msgid":"<20230302220408.1925678-4-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-02T22:04:00","name":"[v9,03/11,gdb/testsuite] Fix gdb.python/py-breakpoint.exp timeouts","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230302220408.1925678-4-binutils@emagii.com/mbox/"},{"id":63602,"url":"https://patchwork.plctlab.org/api/1.2/patches/63602/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230302220408.1925678-5-binutils@emagii.com/","msgid":"<20230302220408.1925678-5-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-02T22:04:01","name":"[v9,04/11] gdb: add HtabPrinter to gdb-gdb.py.in","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230302220408.1925678-5-binutils@emagii.com/mbox/"},{"id":63608,"url":"https://patchwork.plctlab.org/api/1.2/patches/63608/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230302220408.1925678-6-binutils@emagii.com/","msgid":"<20230302220408.1925678-6-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-02T22:04:02","name":"[v9,05/11] Automatic date update in version.in","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230302220408.1925678-6-binutils@emagii.com/mbox/"},{"id":63609,"url":"https://patchwork.plctlab.org/api/1.2/patches/63609/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230302220408.1925678-7-binutils@emagii.com/","msgid":"<20230302220408.1925678-7-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-02T22:04:03","name":"[v9,06/11] Memory leak in gas do_repeat","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230302220408.1925678-7-binutils@emagii.com/mbox/"},{"id":63599,"url":"https://patchwork.plctlab.org/api/1.2/patches/63599/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230302220408.1925678-8-binutils@emagii.com/","msgid":"<20230302220408.1925678-8-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-02T22:04:04","name":"[v9,07/11] gas s_fill caused internal error in frag_new","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230302220408.1925678-8-binutils@emagii.com/mbox/"},{"id":63610,"url":"https://patchwork.plctlab.org/api/1.2/patches/63610/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230302220408.1925678-9-binutils@emagii.com/","msgid":"<20230302220408.1925678-9-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-02T22:04:05","name":"[v9,08/11] Catch overflow in gas s_space","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230302220408.1925678-9-binutils@emagii.com/mbox/"},{"id":63606,"url":"https://patchwork.plctlab.org/api/1.2/patches/63606/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230302220408.1925678-10-binutils@emagii.com/","msgid":"<20230302220408.1925678-10-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-02T22:04:06","name":"[v9,09/11,gdb/testsuite] Add another xfail case in gdb.python/py-record-btrace.exp","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230302220408.1925678-10-binutils@emagii.com/mbox/"},{"id":63605,"url":"https://patchwork.plctlab.org/api/1.2/patches/63605/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230302220408.1925678-11-binutils@emagii.com/","msgid":"<20230302220408.1925678-11-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-02T22:04:07","name":"[v9,10/11] Fix btrace regression","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230302220408.1925678-11-binutils@emagii.com/mbox/"},{"id":63601,"url":"https://patchwork.plctlab.org/api/1.2/patches/63601/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230302220408.1925678-12-binutils@emagii.com/","msgid":"<20230302220408.1925678-12-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-02T22:04:08","name":"[v9,11/11] Fix typo with my email address","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230302220408.1925678-12-binutils@emagii.com/mbox/"},{"id":63630,"url":"https://patchwork.plctlab.org/api/1.2/patches/63630/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230302231051.1928782-2-binutils@emagii.com/","msgid":"<20230302231051.1928782-2-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-02T23:10:41","name":"[v10,01/11] DIGEST: LICENSING","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230302231051.1928782-2-binutils@emagii.com/mbox/"},{"id":63632,"url":"https://patchwork.plctlab.org/api/1.2/patches/63632/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230302231051.1928782-3-binutils@emagii.com/","msgid":"<20230302231051.1928782-3-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-02T23:10:42","name":"[v10,02/11] DIGEST: NEWS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230302231051.1928782-3-binutils@emagii.com/mbox/"},{"id":63635,"url":"https://patchwork.plctlab.org/api/1.2/patches/63635/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230302231051.1928782-4-binutils@emagii.com/","msgid":"<20230302231051.1928782-4-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-02T23:10:43","name":"[v10,03/11] DIGEST: Documentation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230302231051.1928782-4-binutils@emagii.com/mbox/"},{"id":63633,"url":"https://patchwork.plctlab.org/api/1.2/patches/63633/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230302231051.1928782-5-binutils@emagii.com/","msgid":"<20230302231051.1928782-5-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-02T23:10:44","name":"[v10,04/11] DIGEST: testsuite","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230302231051.1928782-5-binutils@emagii.com/mbox/"},{"id":63631,"url":"https://patchwork.plctlab.org/api/1.2/patches/63631/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230302231051.1928782-6-binutils@emagii.com/","msgid":"<20230302231051.1928782-6-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-02T23:10:45","name":"[v10,05/11] DIGEST: ldlex.l","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230302231051.1928782-6-binutils@emagii.com/mbox/"},{"id":63636,"url":"https://patchwork.plctlab.org/api/1.2/patches/63636/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230302231051.1928782-7-binutils@emagii.com/","msgid":"<20230302231051.1928782-7-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-02T23:10:46","name":"[v10,06/11] DIGEST: ldgram.y","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230302231051.1928782-7-binutils@emagii.com/mbox/"},{"id":63634,"url":"https://patchwork.plctlab.org/api/1.2/patches/63634/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230302231051.1928782-8-binutils@emagii.com/","msgid":"<20230302231051.1928782-8-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-02T23:10:47","name":"[v10,07/11] DIGEST: ldmain.c","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230302231051.1928782-8-binutils@emagii.com/mbox/"},{"id":63640,"url":"https://patchwork.plctlab.org/api/1.2/patches/63640/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230302231051.1928782-9-binutils@emagii.com/","msgid":"<20230302231051.1928782-9-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-02T23:10:48","name":"[v10,08/11] DIGEST: ldlang.*: add timestamp","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230302231051.1928782-9-binutils@emagii.com/mbox/"},{"id":63642,"url":"https://patchwork.plctlab.org/api/1.2/patches/63642/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230302231051.1928782-10-binutils@emagii.com/","msgid":"<20230302231051.1928782-10-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-02T23:10:49","name":"[v10,09/11] DIGEST: calculation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230302231051.1928782-10-binutils@emagii.com/mbox/"},{"id":63641,"url":"https://patchwork.plctlab.org/api/1.2/patches/63641/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230302231051.1928782-11-binutils@emagii.com/","msgid":"<20230302231051.1928782-11-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-02T23:10:50","name":"[v10,10/11] DIGEST: Makefile.*","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230302231051.1928782-11-binutils@emagii.com/mbox/"},{"id":63644,"url":"https://patchwork.plctlab.org/api/1.2/patches/63644/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230302231051.1928782-12-binutils@emagii.com/","msgid":"<20230302231051.1928782-12-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-02T23:10:51","name":"[v10,11/11] Build ldint","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230302231051.1928782-12-binutils@emagii.com/mbox/"},{"id":63749,"url":"https://patchwork.plctlab.org/api/1.2/patches/63749/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZAFthsObl5Xz7luZ@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-03T03:46:14","name":"binutils coff type list","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZAFthsObl5Xz7luZ@squeak.grove.modra.org/mbox/"},{"id":63750,"url":"https://patchwork.plctlab.org/api/1.2/patches/63750/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZAFtv3Y3nogpi2mk@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-03T03:47:11","name":"Tidy type handling in binutils/rdcoff.c","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZAFtv3Y3nogpi2mk@squeak.grove.modra.org/mbox/"},{"id":63885,"url":"https://patchwork.plctlab.org/api/1.2/patches/63885/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d42f8a58-0fb2-797e-2313-ba4c8a415b4b@suse.com/","msgid":"","list_archive_url":null,"date":"2023-03-03T12:56:20","name":"[01/18] x86: introduce .insn directive","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d42f8a58-0fb2-797e-2313-ba4c8a415b4b@suse.com/mbox/"},{"id":63887,"url":"https://patchwork.plctlab.org/api/1.2/patches/63887/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3bab7c05-755b-f494-8d7a-0183ab14563a@suse.com/","msgid":"<3bab7c05-755b-f494-8d7a-0183ab14563a@suse.com>","list_archive_url":null,"date":"2023-03-03T12:57:00","name":"[02/18] x86: parse VEX and alike specifiers for .insn","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3bab7c05-755b-f494-8d7a-0183ab14563a@suse.com/mbox/"},{"id":63889,"url":"https://patchwork.plctlab.org/api/1.2/patches/63889/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/242fa8c9-44f3-43e8-fbbd-4248a6abec18@suse.com/","msgid":"<242fa8c9-44f3-43e8-fbbd-4248a6abec18@suse.com>","list_archive_url":null,"date":"2023-03-03T12:57:39","name":"[03/18] x86: parse special opcode modifiers for .insn","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/242fa8c9-44f3-43e8-fbbd-4248a6abec18@suse.com/mbox/"},{"id":63892,"url":"https://patchwork.plctlab.org/api/1.2/patches/63892/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2ab58b70-a02f-cba3-8131-c54eb81b109a@suse.com/","msgid":"<2ab58b70-a02f-cba3-8131-c54eb81b109a@suse.com>","list_archive_url":null,"date":"2023-03-03T12:58:12","name":"[04/18] x86: use set_rex_vrex() also for short-form handling","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2ab58b70-a02f-cba3-8131-c54eb81b109a@suse.com/mbox/"},{"id":63893,"url":"https://patchwork.plctlab.org/api/1.2/patches/63893/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/34990244-84ae-bd27-04c3-1632ad5d7841@suse.com/","msgid":"<34990244-84ae-bd27-04c3-1632ad5d7841@suse.com>","list_archive_url":null,"date":"2023-03-03T12:58:33","name":"[05/18] x86: move more disp processing out of md_assemble()","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/34990244-84ae-bd27-04c3-1632ad5d7841@suse.com/mbox/"},{"id":63895,"url":"https://patchwork.plctlab.org/api/1.2/patches/63895/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/83d24f6c-14a1-2086-855e-453d5a9f3117@suse.com/","msgid":"<83d24f6c-14a1-2086-855e-453d5a9f3117@suse.com>","list_archive_url":null,"date":"2023-03-03T12:59:23","name":"[06/18] x86-64: adjust REX-prefix part of SSE2AVX test","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/83d24f6c-14a1-2086-855e-453d5a9f3117@suse.com/mbox/"},{"id":63896,"url":"https://patchwork.plctlab.org/api/1.2/patches/63896/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/462c093e-13a0-0aff-2dad-e4656180ea9c@suse.com/","msgid":"<462c093e-13a0-0aff-2dad-e4656180ea9c@suse.com>","list_archive_url":null,"date":"2023-03-03T13:00:05","name":"[07/18] x86: re-work build_modrm_byte()'\''s register assignment","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/462c093e-13a0-0aff-2dad-e4656180ea9c@suse.com/mbox/"},{"id":63897,"url":"https://patchwork.plctlab.org/api/1.2/patches/63897/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7a373ee5-4f74-0d63-3995-81b3dc05809c@suse.com/","msgid":"<7a373ee5-4f74-0d63-3995-81b3dc05809c@suse.com>","list_archive_url":null,"date":"2023-03-03T13:00:50","name":"[08/18] x86: VexVVVV is now merely a boolean","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7a373ee5-4f74-0d63-3995-81b3dc05809c@suse.com/mbox/"},{"id":63898,"url":"https://patchwork.plctlab.org/api/1.2/patches/63898/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5f7617d7-f545-cb43-e133-080abb5ede88@suse.com/","msgid":"<5f7617d7-f545-cb43-e133-080abb5ede88@suse.com>","list_archive_url":null,"date":"2023-03-03T13:01:14","name":"[09/18] x86: drop \"shimm\" special case template expansions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5f7617d7-f545-cb43-e133-080abb5ede88@suse.com/mbox/"},{"id":63899,"url":"https://patchwork.plctlab.org/api/1.2/patches/63899/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/42f27545-f571-c78f-415c-50817730faea@suse.com/","msgid":"<42f27545-f571-c78f-415c-50817730faea@suse.com>","list_archive_url":null,"date":"2023-03-03T13:01:41","name":"[10/18] x86/AT&T: restrict recognition of the \"absolute branch\" prefix character","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/42f27545-f571-c78f-415c-50817730faea@suse.com/mbox/"},{"id":63900,"url":"https://patchwork.plctlab.org/api/1.2/patches/63900/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c9bfa265-6d45-fc33-5b1b-db0b95824d92@suse.com/","msgid":"","list_archive_url":null,"date":"2023-03-03T13:02:44","name":"[11/18] x86: process instruction operands for .insn","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c9bfa265-6d45-fc33-5b1b-db0b95824d92@suse.com/mbox/"},{"id":63902,"url":"https://patchwork.plctlab.org/api/1.2/patches/63902/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/689eb629-ad65-4611-2a22-ac0dea62590d@suse.com/","msgid":"<689eb629-ad65-4611-2a22-ac0dea62590d@suse.com>","list_archive_url":null,"date":"2023-03-03T13:03:17","name":"[12/18] x86: decouple broadcast type and bytes fields","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/689eb629-ad65-4611-2a22-ac0dea62590d@suse.com/mbox/"},{"id":63903,"url":"https://patchwork.plctlab.org/api/1.2/patches/63903/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3bbf02eb-364b-88de-d6c5-3e63a79ee602@suse.com/","msgid":"<3bbf02eb-364b-88de-d6c5-3e63a79ee602@suse.com>","list_archive_url":null,"date":"2023-03-03T13:03:51","name":"[13/18] x86: handle EVEX Disp8 for .insn","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3bbf02eb-364b-88de-d6c5-3e63a79ee602@suse.com/mbox/"},{"id":63904,"url":"https://patchwork.plctlab.org/api/1.2/patches/63904/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/433b1d03-2e38-8b3f-be46-c859e678959f@suse.com/","msgid":"<433b1d03-2e38-8b3f-be46-c859e678959f@suse.com>","list_archive_url":null,"date":"2023-03-03T13:04:32","name":"[14/18] x86: allow for multiple immediates in output_disp()","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/433b1d03-2e38-8b3f-be46-c859e678959f@suse.com/mbox/"},{"id":63905,"url":"https://patchwork.plctlab.org/api/1.2/patches/63905/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d85d3d06-46e5-2f23-660a-0daaa9e5088f@suse.com/","msgid":"","list_archive_url":null,"date":"2023-03-03T13:05:00","name":"[15/18] x86: handle immediate operands for .insn","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d85d3d06-46e5-2f23-660a-0daaa9e5088f@suse.com/mbox/"},{"id":63906,"url":"https://patchwork.plctlab.org/api/1.2/patches/63906/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/14ee4656-f39a-59c4-48d0-c397b77ad969@suse.com/","msgid":"<14ee4656-f39a-59c4-48d0-c397b77ad969@suse.com>","list_archive_url":null,"date":"2023-03-03T13:05:36","name":"[16/18] x86: document .insn","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/14ee4656-f39a-59c4-48d0-c397b77ad969@suse.com/mbox/"},{"id":63907,"url":"https://patchwork.plctlab.org/api/1.2/patches/63907/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/10b9c1df-587e-e788-641b-43ccde48be21@suse.com/","msgid":"<10b9c1df-587e-e788-641b-43ccde48be21@suse.com>","list_archive_url":null,"date":"2023-03-03T13:06:25","name":"[17/18] x86: convert testcases to use .insn","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/10b9c1df-587e-e788-641b-43ccde48be21@suse.com/mbox/"},{"id":63908,"url":"https://patchwork.plctlab.org/api/1.2/patches/63908/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/390b97ee-c38a-4239-01a4-32d17ecdf44c@suse.com/","msgid":"<390b97ee-c38a-4239-01a4-32d17ecdf44c@suse.com>","list_archive_url":null,"date":"2023-03-03T13:06:56","name":"[RFC,18/18] x86: .insn example - VEX-encoded instructions of original Xeon Phi","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/390b97ee-c38a-4239-01a4-32d17ecdf44c@suse.com/mbox/"},{"id":63958,"url":"https://patchwork.plctlab.org/api/1.2/patches/63958/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230303144706.1977061-2-binutils@emagii.com/","msgid":"<20230303144706.1977061-2-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-03T14:46:56","name":"[v11,01/11] DIGEST: LICENSING","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230303144706.1977061-2-binutils@emagii.com/mbox/"},{"id":63953,"url":"https://patchwork.plctlab.org/api/1.2/patches/63953/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230303144706.1977061-3-binutils@emagii.com/","msgid":"<20230303144706.1977061-3-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-03T14:46:57","name":"[v11,02/11] DIGEST: NEWS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230303144706.1977061-3-binutils@emagii.com/mbox/"},{"id":63954,"url":"https://patchwork.plctlab.org/api/1.2/patches/63954/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230303144706.1977061-4-binutils@emagii.com/","msgid":"<20230303144706.1977061-4-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-03T14:46:58","name":"[v11,03/11] DIGEST: Documentation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230303144706.1977061-4-binutils@emagii.com/mbox/"},{"id":63966,"url":"https://patchwork.plctlab.org/api/1.2/patches/63966/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230303144706.1977061-5-binutils@emagii.com/","msgid":"<20230303144706.1977061-5-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-03T14:46:59","name":"[v11,04/11] DIGEST: testsuite","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230303144706.1977061-5-binutils@emagii.com/mbox/"},{"id":63962,"url":"https://patchwork.plctlab.org/api/1.2/patches/63962/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230303144706.1977061-6-binutils@emagii.com/","msgid":"<20230303144706.1977061-6-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-03T14:47:00","name":"[v11,05/11] DIGEST: ldlex.l","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230303144706.1977061-6-binutils@emagii.com/mbox/"},{"id":63960,"url":"https://patchwork.plctlab.org/api/1.2/patches/63960/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230303144706.1977061-7-binutils@emagii.com/","msgid":"<20230303144706.1977061-7-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-03T14:47:01","name":"[v11,06/11] DIGEST: ldgram.y","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230303144706.1977061-7-binutils@emagii.com/mbox/"},{"id":63964,"url":"https://patchwork.plctlab.org/api/1.2/patches/63964/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230303144706.1977061-8-binutils@emagii.com/","msgid":"<20230303144706.1977061-8-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-03T14:47:02","name":"[v11,07/11] DIGEST: ldmain.c","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230303144706.1977061-8-binutils@emagii.com/mbox/"},{"id":63961,"url":"https://patchwork.plctlab.org/api/1.2/patches/63961/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230303144706.1977061-9-binutils@emagii.com/","msgid":"<20230303144706.1977061-9-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-03T14:47:03","name":"[v11,08/11] DIGEST: ldlang.*: add timestamp","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230303144706.1977061-9-binutils@emagii.com/mbox/"},{"id":63955,"url":"https://patchwork.plctlab.org/api/1.2/patches/63955/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230303144706.1977061-10-binutils@emagii.com/","msgid":"<20230303144706.1977061-10-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-03T14:47:04","name":"[v11,09/11] DIGEST: calculation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230303144706.1977061-10-binutils@emagii.com/mbox/"},{"id":63967,"url":"https://patchwork.plctlab.org/api/1.2/patches/63967/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230303144706.1977061-11-binutils@emagii.com/","msgid":"<20230303144706.1977061-11-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-03T14:47:05","name":"[v11,10/11] DIGEST: Makefile.*","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230303144706.1977061-11-binutils@emagii.com/mbox/"},{"id":63965,"url":"https://patchwork.plctlab.org/api/1.2/patches/63965/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230303144706.1977061-12-binutils@emagii.com/","msgid":"<20230303144706.1977061-12-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-03T14:47:06","name":"[v11,11/11] Build ldint","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230303144706.1977061-12-binutils@emagii.com/mbox/"},{"id":64411,"url":"https://patchwork.plctlab.org/api/1.2/patches/64411/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZAVdsMx3t7PJx6/N@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-06T03:27:44","name":"Correct objdump command line error handling","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZAVdsMx3t7PJx6/N@squeak.grove.modra.org/mbox/"},{"id":64412,"url":"https://patchwork.plctlab.org/api/1.2/patches/64412/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZAVdzGu9AOUk0jwF@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-06T03:28:12","name":"Move nm.c cached line number info to bfd usrdata","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZAVdzGu9AOUk0jwF@squeak.grove.modra.org/mbox/"},{"id":64413,"url":"https://patchwork.plctlab.org/api/1.2/patches/64413/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZAVd75QsC9WDKjib@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-06T03:28:47","name":"Downgrade nm fatal errors to non-fatal","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZAVd75QsC9WDKjib@squeak.grove.modra.org/mbox/"},{"id":64414,"url":"https://patchwork.plctlab.org/api/1.2/patches/64414/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZAVeXfeOtW187hlw@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-06T03:30:37","name":"Downgrade addr2line fatal errors to non-fatal","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZAVeXfeOtW187hlw@squeak.grove.modra.org/mbox/"},{"id":64415,"url":"https://patchwork.plctlab.org/api/1.2/patches/64415/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZAVefjechteynu1f@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-06T03:31:10","name":"Downgrade objdump fatal errors to non-fatal","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZAVefjechteynu1f@squeak.grove.modra.org/mbox/"},{"id":64416,"url":"https://patchwork.plctlab.org/api/1.2/patches/64416/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZAVeo2/RNgqKm+AA@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-06T03:31:47","name":"Correct odd loop in ecoff lookup_line","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZAVeo2/RNgqKm+AA@squeak.grove.modra.org/mbox/"},{"id":64418,"url":"https://patchwork.plctlab.org/api/1.2/patches/64418/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZAVewBOf2ip1On9w@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-06T03:32:16","name":"More _bfd_ecoff_locate_line sanity checks","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZAVewBOf2ip1On9w@squeak.grove.modra.org/mbox/"},{"id":64417,"url":"https://patchwork.plctlab.org/api/1.2/patches/64417/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZAVe3UuTbz+f5v74@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-06T03:32:45","name":"PR30198, Assertion and segfault when linking x86_64 elf and coff","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZAVe3UuTbz+f5v74@squeak.grove.modra.org/mbox/"},{"id":64619,"url":"https://patchwork.plctlab.org/api/1.2/patches/64619/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZAXSk4uW7BEA153b@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-06T11:46:27","name":"macho null dereference read","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZAXSk4uW7BEA153b@squeak.grove.modra.org/mbox/"},{"id":64651,"url":"https://patchwork.plctlab.org/api/1.2/patches/64651/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230306133158.91917-2-binutils@emagii.com/","msgid":"<20230306133158.91917-2-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-06T13:31:48","name":"[v12,01/11] DIGEST: LICENSING","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230306133158.91917-2-binutils@emagii.com/mbox/"},{"id":64652,"url":"https://patchwork.plctlab.org/api/1.2/patches/64652/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230306133158.91917-3-binutils@emagii.com/","msgid":"<20230306133158.91917-3-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-06T13:31:49","name":"[v12,02/11] DIGEST: NEWS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230306133158.91917-3-binutils@emagii.com/mbox/"},{"id":64653,"url":"https://patchwork.plctlab.org/api/1.2/patches/64653/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230306133158.91917-4-binutils@emagii.com/","msgid":"<20230306133158.91917-4-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-06T13:31:50","name":"[v12,03/11] DIGEST: Documentation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230306133158.91917-4-binutils@emagii.com/mbox/"},{"id":64657,"url":"https://patchwork.plctlab.org/api/1.2/patches/64657/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230306133158.91917-5-binutils@emagii.com/","msgid":"<20230306133158.91917-5-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-06T13:31:51","name":"[v12,04/11] DIGEST: testsuite","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230306133158.91917-5-binutils@emagii.com/mbox/"},{"id":64654,"url":"https://patchwork.plctlab.org/api/1.2/patches/64654/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230306133158.91917-6-binutils@emagii.com/","msgid":"<20230306133158.91917-6-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-06T13:31:52","name":"[v12,05/11] DIGEST: ldlex.l","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230306133158.91917-6-binutils@emagii.com/mbox/"},{"id":64655,"url":"https://patchwork.plctlab.org/api/1.2/patches/64655/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230306133158.91917-7-binutils@emagii.com/","msgid":"<20230306133158.91917-7-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-06T13:31:53","name":"[v12,06/11] DIGEST: ldgram.y","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230306133158.91917-7-binutils@emagii.com/mbox/"},{"id":64656,"url":"https://patchwork.plctlab.org/api/1.2/patches/64656/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230306133158.91917-8-binutils@emagii.com/","msgid":"<20230306133158.91917-8-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-06T13:31:54","name":"[v12,07/11] DIGEST: ldmain.c","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230306133158.91917-8-binutils@emagii.com/mbox/"},{"id":64658,"url":"https://patchwork.plctlab.org/api/1.2/patches/64658/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230306133158.91917-9-binutils@emagii.com/","msgid":"<20230306133158.91917-9-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-06T13:31:55","name":"[v12,08/11] DIGEST: ldlang.*: add timestamp","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230306133158.91917-9-binutils@emagii.com/mbox/"},{"id":64661,"url":"https://patchwork.plctlab.org/api/1.2/patches/64661/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230306133158.91917-10-binutils@emagii.com/","msgid":"<20230306133158.91917-10-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-06T13:31:56","name":"[v12,09/11] DIGEST: calculation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230306133158.91917-10-binutils@emagii.com/mbox/"},{"id":64660,"url":"https://patchwork.plctlab.org/api/1.2/patches/64660/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230306133158.91917-11-binutils@emagii.com/","msgid":"<20230306133158.91917-11-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-06T13:31:57","name":"[v12,10/11] DIGEST: Makefile.*","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230306133158.91917-11-binutils@emagii.com/mbox/"},{"id":64659,"url":"https://patchwork.plctlab.org/api/1.2/patches/64659/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230306133158.91917-12-binutils@emagii.com/","msgid":"<20230306133158.91917-12-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-06T13:31:58","name":"[v12,11/11] Build ldint","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230306133158.91917-12-binutils@emagii.com/mbox/"},{"id":65273,"url":"https://patchwork.plctlab.org/api/1.2/patches/65273/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230307050431.288433-1-vladimir.mezentsev@oracle.com/","msgid":"<20230307050431.288433-1-vladimir.mezentsev@oracle.com>","list_archive_url":null,"date":"2023-03-07T05:04:31","name":"[Review,is,needed] gprofng: read Dwarf 5","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230307050431.288433-1-vladimir.mezentsev@oracle.com/mbox/"},{"id":65986,"url":"https://patchwork.plctlab.org/api/1.2/patches/65986/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZAf9qw1lk5r9MWOY@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-08T03:14:51","name":"z8 and z80 coff_reloc16_extra_cases sanity checks","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZAf9qw1lk5r9MWOY@squeak.grove.modra.org/mbox/"},{"id":65987,"url":"https://patchwork.plctlab.org/api/1.2/patches/65987/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZAf96/aiNOmLZEuS@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-08T03:15:55","name":"Regen potfiles","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZAf96/aiNOmLZEuS@squeak.grove.modra.org/mbox/"},{"id":66046,"url":"https://patchwork.plctlab.org/api/1.2/patches/66046/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZAg5M/tmFWFGCq2N@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-08T07:28:51","name":"Tidy pe_ILF_build_a_bfd a little","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZAg5M/tmFWFGCq2N@squeak.grove.modra.org/mbox/"},{"id":66183,"url":"https://patchwork.plctlab.org/api/1.2/patches/66183/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230308125441.356419-2-binutils@emagii.com/","msgid":"<20230308125441.356419-2-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-08T12:54:41","name":"[v1] DIGEST: Disable 64-bit CRC for 32-bit BFD","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230308125441.356419-2-binutils@emagii.com/mbox/"},{"id":66328,"url":"https://patchwork.plctlab.org/api/1.2/patches/66328/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a513b979-d455-eea6-ba19-1af0dff5d4e2@suse.com/","msgid":"","list_archive_url":null,"date":"2023-03-08T16:07:35","name":"[1/4] gas: drop function pointer parameter from macro_init()","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a513b979-d455-eea6-ba19-1af0dff5d4e2@suse.com/mbox/"},{"id":66329,"url":"https://patchwork.plctlab.org/api/1.2/patches/66329/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e7780d8a-ad1c-a738-a7f5-f5b70c46c6fe@suse.com/","msgid":"","list_archive_url":null,"date":"2023-03-08T16:08:17","name":"[2/4] gas: isolate macro_strip_at to macro.c","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e7780d8a-ad1c-a738-a7f5-f5b70c46c6fe@suse.com/mbox/"},{"id":66332,"url":"https://patchwork.plctlab.org/api/1.2/patches/66332/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0cdb6ff1-8f31-8222-629f-cb991a1efb63@suse.com/","msgid":"<0cdb6ff1-8f31-8222-629f-cb991a1efb63@suse.com>","list_archive_url":null,"date":"2023-03-08T16:08:39","name":"[3/4] gas: use flag_mri directly in macro processing","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0cdb6ff1-8f31-8222-629f-cb991a1efb63@suse.com/mbox/"},{"id":66336,"url":"https://patchwork.plctlab.org/api/1.2/patches/66336/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/06908d40-8d11-9540-6932-efb4f54dba0f@suse.com/","msgid":"<06908d40-8d11-9540-6932-efb4f54dba0f@suse.com>","list_archive_url":null,"date":"2023-03-08T16:09:22","name":"[4/4] gas: expose flag_macro_alternate globally","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/06908d40-8d11-9540-6932-efb4f54dba0f@suse.com/mbox/"},{"id":66649,"url":"https://patchwork.plctlab.org/api/1.2/patches/66649/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230309080446.24714-1-nelson@rivosinc.com/","msgid":"<20230309080446.24714-1-nelson@rivosinc.com>","list_archive_url":null,"date":"2023-03-09T08:04:46","name":"RISC-V: Segment fault in riscv_elf_append_rela.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230309080446.24714-1-nelson@rivosinc.com/mbox/"},{"id":66827,"url":"https://patchwork.plctlab.org/api/1.2/patches/66827/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZAnOJ6t4+ezsABPt@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-09T12:16:39","name":"Allow frag address wrapping in absolute section","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZAnOJ6t4+ezsABPt@squeak.grove.modra.org/mbox/"},{"id":66828,"url":"https://patchwork.plctlab.org/api/1.2/patches/66828/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZAnOVl9L363M77Cx@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-09T12:17:26","name":"objdump: report no section contents","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZAnOVl9L363M77Cx@squeak.grove.modra.org/mbox/"},{"id":67175,"url":"https://patchwork.plctlab.org/api/1.2/patches/67175/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230310000817.751962-2-binutils@emagii.com/","msgid":"<20230310000817.751962-2-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-10T00:08:11","name":"[v1,1/7] SECTOR: NEWS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230310000817.751962-2-binutils@emagii.com/mbox/"},{"id":67174,"url":"https://patchwork.plctlab.org/api/1.2/patches/67174/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230310000817.751962-3-binutils@emagii.com/","msgid":"<20230310000817.751962-3-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-10T00:08:12","name":"[v1,2/7] SECTOR: ld.texi","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230310000817.751962-3-binutils@emagii.com/mbox/"},{"id":67177,"url":"https://patchwork.plctlab.org/api/1.2/patches/67177/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230310000817.751962-4-binutils@emagii.com/","msgid":"<20230310000817.751962-4-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-10T00:08:13","name":"[v1,3/7] SECTOR: ldlex.l","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230310000817.751962-4-binutils@emagii.com/mbox/"},{"id":67179,"url":"https://patchwork.plctlab.org/api/1.2/patches/67179/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230310000817.751962-5-binutils@emagii.com/","msgid":"<20230310000817.751962-5-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-10T00:08:14","name":"[v1,4/7] SECTOR: ldgram.y","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230310000817.751962-5-binutils@emagii.com/mbox/"},{"id":67180,"url":"https://patchwork.plctlab.org/api/1.2/patches/67180/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230310000817.751962-6-binutils@emagii.com/","msgid":"<20230310000817.751962-6-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-10T00:08:15","name":"[v1,5/7] SECTOR: language additions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230310000817.751962-6-binutils@emagii.com/mbox/"},{"id":67176,"url":"https://patchwork.plctlab.org/api/1.2/patches/67176/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230310000817.751962-7-binutils@emagii.com/","msgid":"<20230310000817.751962-7-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-10T00:08:16","name":"[v1,6/7] SECTOR: add testsuite","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230310000817.751962-7-binutils@emagii.com/mbox/"},{"id":67178,"url":"https://patchwork.plctlab.org/api/1.2/patches/67178/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230310000817.751962-8-binutils@emagii.com/","msgid":"<20230310000817.751962-8-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-10T00:08:17","name":"[v1,7/7] SECTOR: Makefile.*","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230310000817.751962-8-binutils@emagii.com/mbox/"},{"id":67202,"url":"https://patchwork.plctlab.org/api/1.2/patches/67202/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZAqu271thSCsaKU3@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-10T04:15:23","name":"eh static data","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZAqu271thSCsaKU3@squeak.grove.modra.org/mbox/"},{"id":67293,"url":"https://patchwork.plctlab.org/api/1.2/patches/67293/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f1892080-b6fe-a164-73bb-91cd88302e0f@suse.com/","msgid":"","list_archive_url":null,"date":"2023-03-10T09:25:27","name":"[v2,1/7] RISC-V: minor effort reduction in relocation specifier parsing","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f1892080-b6fe-a164-73bb-91cd88302e0f@suse.com/mbox/"},{"id":67294,"url":"https://patchwork.plctlab.org/api/1.2/patches/67294/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/366e4dcf-e273-a321-dd38-7adf4212c901@suse.com/","msgid":"<366e4dcf-e273-a321-dd38-7adf4212c901@suse.com>","list_archive_url":null,"date":"2023-03-10T09:26:00","name":"[v2,2/7] RISC-V: drop \"percent_op\" parameter from my_getOpcodeExpression()","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/366e4dcf-e273-a321-dd38-7adf4212c901@suse.com/mbox/"},{"id":67296,"url":"https://patchwork.plctlab.org/api/1.2/patches/67296/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5352e5fd-d1c5-4267-c802-73d6074e80ca@suse.com/","msgid":"<5352e5fd-d1c5-4267-c802-73d6074e80ca@suse.com>","list_archive_url":null,"date":"2023-03-10T09:26:25","name":"[v2,3/7] RISC-V: avoid redundant and misleading/wrong error messages","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5352e5fd-d1c5-4267-c802-73d6074e80ca@suse.com/mbox/"},{"id":67297,"url":"https://patchwork.plctlab.org/api/1.2/patches/67297/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ebffbf50-fa83-8e7e-eedd-d9e9d1b4aa04@suse.com/","msgid":"","list_archive_url":null,"date":"2023-03-10T09:27:05","name":"[v2,4/7] RISC-V: don'\''t recognize bogus relocations","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ebffbf50-fa83-8e7e-eedd-d9e9d1b4aa04@suse.com/mbox/"},{"id":67302,"url":"https://patchwork.plctlab.org/api/1.2/patches/67302/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/89f892c8-e378-b81c-7b13-322a7876a252@suse.com/","msgid":"<89f892c8-e378-b81c-7b13-322a7876a252@suse.com>","list_archive_url":null,"date":"2023-03-10T09:27:26","name":"[v2,5/7] RISC-V: relax post-relocation-operator separator expectation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/89f892c8-e378-b81c-7b13-322a7876a252@suse.com/mbox/"},{"id":67301,"url":"https://patchwork.plctlab.org/api/1.2/patches/67301/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/756c5464-9bcb-d78f-c763-4bb5504eec92@suse.com/","msgid":"<756c5464-9bcb-d78f-c763-4bb5504eec92@suse.com>","list_archive_url":null,"date":"2023-03-10T09:27:58","name":"[v2,6/7] RISC-V: test for expected / no unexpected symbols","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/756c5464-9bcb-d78f-c763-4bb5504eec92@suse.com/mbox/"},{"id":67305,"url":"https://patchwork.plctlab.org/api/1.2/patches/67305/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/54b0d4cc-855a-78c7-5233-22f7d454c0c4@suse.com/","msgid":"<54b0d4cc-855a-78c7-5233-22f7d454c0c4@suse.com>","list_archive_url":null,"date":"2023-03-10T09:28:23","name":"[v2,7/7] RISC-V: adjust logic to avoid register name symbols","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/54b0d4cc-855a-78c7-5233-22f7d454c0c4@suse.com/mbox/"},{"id":67308,"url":"https://patchwork.plctlab.org/api/1.2/patches/67308/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/150b4184-62af-3f5c-c07b-24b0c2ae788f@suse.com/","msgid":"<150b4184-62af-3f5c-c07b-24b0c2ae788f@suse.com>","list_archive_url":null,"date":"2023-03-10T09:36:31","name":"[RFC] RISC-V: alter the special character used in FAKE_LABEL_NAME","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/150b4184-62af-3f5c-c07b-24b0c2ae788f@suse.com/mbox/"},{"id":67313,"url":"https://patchwork.plctlab.org/api/1.2/patches/67313/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c7f7f3a2-033c-da49-6e04-9a1df21eef6f@suse.com/","msgid":"","list_archive_url":null,"date":"2023-03-10T09:43:48","name":"gas: apply md_register_arithmetic also to unary '\''+'\''","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c7f7f3a2-033c-da49-6e04-9a1df21eef6f@suse.com/mbox/"},{"id":67317,"url":"https://patchwork.plctlab.org/api/1.2/patches/67317/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/312cb612-378a-be36-6f6c-62df7313975d@suse.com/","msgid":"<312cb612-378a-be36-6f6c-62df7313975d@suse.com>","list_archive_url":null,"date":"2023-03-10T10:11:28","name":"x86: drop identifier_chars[]","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/312cb612-378a-be36-6f6c-62df7313975d@suse.com/mbox/"},{"id":67319,"url":"https://patchwork.plctlab.org/api/1.2/patches/67319/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/97d9240d-2d1a-d7a4-35e4-7cec1f418f38@suse.com/","msgid":"<97d9240d-2d1a-d7a4-35e4-7cec1f418f38@suse.com>","list_archive_url":null,"date":"2023-03-10T10:19:22","name":"[v2,01/14] x86: introduce .insn directive","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/97d9240d-2d1a-d7a4-35e4-7cec1f418f38@suse.com/mbox/"},{"id":67320,"url":"https://patchwork.plctlab.org/api/1.2/patches/67320/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8df023f9-58a5-dca7-badd-f3354ed18442@suse.com/","msgid":"<8df023f9-58a5-dca7-badd-f3354ed18442@suse.com>","list_archive_url":null,"date":"2023-03-10T10:19:50","name":"[v2,02/14] x86: parse VEX and alike specifiers for .insn","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8df023f9-58a5-dca7-badd-f3354ed18442@suse.com/mbox/"},{"id":67321,"url":"https://patchwork.plctlab.org/api/1.2/patches/67321/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5771df73-12d8-e880-a051-86c09d6bdb06@suse.com/","msgid":"<5771df73-12d8-e880-a051-86c09d6bdb06@suse.com>","list_archive_url":null,"date":"2023-03-10T10:20:26","name":"[v2,03/14] x86: parse special opcode modifiers for .insn","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5771df73-12d8-e880-a051-86c09d6bdb06@suse.com/mbox/"},{"id":67322,"url":"https://patchwork.plctlab.org/api/1.2/patches/67322/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fba4e20a-8b63-652c-7766-8b0ba47f1672@suse.com/","msgid":"","list_archive_url":null,"date":"2023-03-10T10:21:11","name":"[v2,04/14] x86: re-work build_modrm_byte()'\''s register assignment","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fba4e20a-8b63-652c-7766-8b0ba47f1672@suse.com/mbox/"},{"id":67325,"url":"https://patchwork.plctlab.org/api/1.2/patches/67325/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/08829d31-820b-7dea-5609-de609bf69aa9@suse.com/","msgid":"<08829d31-820b-7dea-5609-de609bf69aa9@suse.com>","list_archive_url":null,"date":"2023-03-10T10:21:48","name":"[v2,05/14] x86: VexVVVV is now merely a boolean","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/08829d31-820b-7dea-5609-de609bf69aa9@suse.com/mbox/"},{"id":67323,"url":"https://patchwork.plctlab.org/api/1.2/patches/67323/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a4fdab7e-bc8f-ff75-6be2-559f053bef28@suse.com/","msgid":"","list_archive_url":null,"date":"2023-03-10T10:22:16","name":"[v2,06/14] x86: drop \"shimm\" special case template expansions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a4fdab7e-bc8f-ff75-6be2-559f053bef28@suse.com/mbox/"},{"id":67326,"url":"https://patchwork.plctlab.org/api/1.2/patches/67326/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/667d9ad0-3165-08cf-dead-efd27a5d267e@suse.com/","msgid":"<667d9ad0-3165-08cf-dead-efd27a5d267e@suse.com>","list_archive_url":null,"date":"2023-03-10T10:22:38","name":"[v2,07/14] x86/AT&T: restrict recognition of the \"absolute branch\" prefix character","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/667d9ad0-3165-08cf-dead-efd27a5d267e@suse.com/mbox/"},{"id":67327,"url":"https://patchwork.plctlab.org/api/1.2/patches/67327/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8d917f97-af55-11f3-a9f8-d5a209725336@suse.com/","msgid":"<8d917f97-af55-11f3-a9f8-d5a209725336@suse.com>","list_archive_url":null,"date":"2023-03-10T10:23:40","name":"[v2,08/14] x86: process instruction operands for .insn","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8d917f97-af55-11f3-a9f8-d5a209725336@suse.com/mbox/"},{"id":67328,"url":"https://patchwork.plctlab.org/api/1.2/patches/67328/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/010a5ae0-91a5-813b-8896-8fd11d5383d7@suse.com/","msgid":"<010a5ae0-91a5-813b-8896-8fd11d5383d7@suse.com>","list_archive_url":null,"date":"2023-03-10T10:24:03","name":"[v2,09/14] x86: handle EVEX Disp8 for .insn","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/010a5ae0-91a5-813b-8896-8fd11d5383d7@suse.com/mbox/"},{"id":67329,"url":"https://patchwork.plctlab.org/api/1.2/patches/67329/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/68848170-59cb-6546-6e7f-527f65a8c1fe@suse.com/","msgid":"<68848170-59cb-6546-6e7f-527f65a8c1fe@suse.com>","list_archive_url":null,"date":"2023-03-10T10:24:53","name":"[v2,10/14] x86: allow for multiple immediates in output_disp()","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/68848170-59cb-6546-6e7f-527f65a8c1fe@suse.com/mbox/"},{"id":67330,"url":"https://patchwork.plctlab.org/api/1.2/patches/67330/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a154c5f8-b5af-320d-f542-5dfccbefba3b@suse.com/","msgid":"","list_archive_url":null,"date":"2023-03-10T10:25:43","name":"[v2,11/14] x86: handle immediate operands for .insn","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a154c5f8-b5af-320d-f542-5dfccbefba3b@suse.com/mbox/"},{"id":67331,"url":"https://patchwork.plctlab.org/api/1.2/patches/67331/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e11eeb2e-0e16-886e-ee81-bf9a57f57965@suse.com/","msgid":"","list_archive_url":null,"date":"2023-03-10T10:26:03","name":"[v2,12/14] x86: document .insn","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e11eeb2e-0e16-886e-ee81-bf9a57f57965@suse.com/mbox/"},{"id":67332,"url":"https://patchwork.plctlab.org/api/1.2/patches/67332/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2b0ca132-9d85-86a8-8b91-828fa66881b8@suse.com/","msgid":"<2b0ca132-9d85-86a8-8b91-828fa66881b8@suse.com>","list_archive_url":null,"date":"2023-03-10T10:26:44","name":"[v2,13/14] x86: convert testcases to use .insn","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2b0ca132-9d85-86a8-8b91-828fa66881b8@suse.com/mbox/"},{"id":67333,"url":"https://patchwork.plctlab.org/api/1.2/patches/67333/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/df8e84be-1e77-07ee-aff6-d457e9b0f818@suse.com/","msgid":"","list_archive_url":null,"date":"2023-03-10T10:27:47","name":"[RFC,v2,14/14] x86: .insn example - VEX-encoded instructions of original Xeon Phi","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/df8e84be-1e77-07ee-aff6-d457e9b0f818@suse.com/mbox/"},{"id":68729,"url":"https://patchwork.plctlab.org/api/1.2/patches/68729/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230313102216.355828-1-och95@yandex.ru/","msgid":"<20230313102216.355828-1-och95@yandex.ru>","list_archive_url":null,"date":"2023-03-13T10:22:16","name":"Fix emit-relocs for aarch64 gold","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230313102216.355828-1-och95@yandex.ru/mbox/"},{"id":69242,"url":"https://patchwork.plctlab.org/api/1.2/patches/69242/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZA/V6rdHyBWRJeg/@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-14T02:03:22","name":"gas/compress-debug.c init all of strm","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZA/V6rdHyBWRJeg/@squeak.grove.modra.org/mbox/"},{"id":69243,"url":"https://patchwork.plctlab.org/api/1.2/patches/69243/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZA/WAkr1NO7joSsy@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-14T02:03:46","name":"gas/ecoff.c: don'\''t use zero struct copies to init","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZA/WAkr1NO7joSsy@squeak.grove.modra.org/mbox/"},{"id":69245,"url":"https://patchwork.plctlab.org/api/1.2/patches/69245/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZA/WGWSYR8IA1rJl@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-14T02:04:09","name":"gas/dwarf2dbg.c init more statics","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZA/WGWSYR8IA1rJl@squeak.grove.modra.org/mbox/"},{"id":69244,"url":"https://patchwork.plctlab.org/api/1.2/patches/69244/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZA/WNm1YCQpP7t+a@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-14T02:04:38","name":"gas .include and .incbin","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZA/WNm1YCQpP7t+a@squeak.grove.modra.org/mbox/"},{"id":69246,"url":"https://patchwork.plctlab.org/api/1.2/patches/69246/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZA/WTCOXOOCfB3kP@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-14T02:05:00","name":"gas/read.c: init more statics","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZA/WTCOXOOCfB3kP@squeak.grove.modra.org/mbox/"},{"id":69247,"url":"https://patchwork.plctlab.org/api/1.2/patches/69247/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZA/Wa/V9ZyhkIDlz@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-14T02:05:31","name":"Sanity check read_section_stabs_debugging_info","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZA/Wa/V9ZyhkIDlz@squeak.grove.modra.org/mbox/"},{"id":69248,"url":"https://patchwork.plctlab.org/api/1.2/patches/69248/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZA/WoJ/0CrDmzojB@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-14T02:06:24","name":"objdump segfault after symbol table error","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZA/WoJ/0CrDmzojB@squeak.grove.modra.org/mbox/"},{"id":69845,"url":"https://patchwork.plctlab.org/api/1.2/patches/69845/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230314220114.1117782-2-binutils@emagii.com/","msgid":"<20230314220114.1117782-2-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-14T22:01:12","name":"[v1,1/3] CHIP: ldlex.l","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230314220114.1117782-2-binutils@emagii.com/mbox/"},{"id":69843,"url":"https://patchwork.plctlab.org/api/1.2/patches/69843/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230314220114.1117782-3-binutils@emagii.com/","msgid":"<20230314220114.1117782-3-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-14T22:01:13","name":"[v1,2/3] CHIP: ldgram.y","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230314220114.1117782-3-binutils@emagii.com/mbox/"},{"id":69844,"url":"https://patchwork.plctlab.org/api/1.2/patches/69844/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230314220114.1117782-4-binutils@emagii.com/","msgid":"<20230314220114.1117782-4-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-14T22:01:14","name":"[v1,3/3] CHIP: language additions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230314220114.1117782-4-binutils@emagii.com/mbox/"},{"id":70532,"url":"https://patchwork.plctlab.org/api/1.2/patches/70532/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZBJprOGHAKOvXNTu@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-16T00:58:20","name":"PR30217, dynamic relocations using local dynamic symbols","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZBJprOGHAKOvXNTu@squeak.grove.modra.org/mbox/"},{"id":70595,"url":"https://patchwork.plctlab.org/api/1.2/patches/70595/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZBK+tK3Heqd68P3Y@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-16T07:01:08","name":"cpu/mem.opc whitespace tidy","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZBK+tK3Heqd68P3Y@squeak.grove.modra.org/mbox/"},{"id":70703,"url":"https://patchwork.plctlab.org/api/1.2/patches/70703/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230316101736.482737-2-chigot@adacore.com/","msgid":"<20230316101736.482737-2-chigot@adacore.com>","list_archive_url":null,"date":"2023-03-16T10:17:32","name":"[1/5] configure: add new target aarch64-*-nto*","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230316101736.482737-2-chigot@adacore.com/mbox/"},{"id":70705,"url":"https://patchwork.plctlab.org/api/1.2/patches/70705/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230316101736.482737-3-chigot@adacore.com/","msgid":"<20230316101736.482737-3-chigot@adacore.com>","list_archive_url":null,"date":"2023-03-16T10:17:33","name":"[2/5] readelf: add support for QNT_STACK note subsections","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230316101736.482737-3-chigot@adacore.com/mbox/"},{"id":70706,"url":"https://patchwork.plctlab.org/api/1.2/patches/70706/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230316101736.482737-4-chigot@adacore.com/","msgid":"<20230316101736.482737-4-chigot@adacore.com>","list_archive_url":null,"date":"2023-03-16T10:17:34","name":"[3/5] ld: add support of QNX stack arguments for aarch64nto","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230316101736.482737-4-chigot@adacore.com/mbox/"},{"id":70704,"url":"https://patchwork.plctlab.org/api/1.2/patches/70704/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230316101736.482737-5-chigot@adacore.com/","msgid":"<20230316101736.482737-5-chigot@adacore.com>","list_archive_url":null,"date":"2023-03-16T10:17:35","name":"[4/5] ld/testsuite: add aarch64nto to ld-aarch64","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230316101736.482737-5-chigot@adacore.com/mbox/"},{"id":70707,"url":"https://patchwork.plctlab.org/api/1.2/patches/70707/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230316101736.482737-6-chigot@adacore.com/","msgid":"<20230316101736.482737-6-chigot@adacore.com>","list_archive_url":null,"date":"2023-03-16T10:17:36","name":"[5/5] ld/testsuite: disable ilp32 tests for aarch64-qnx","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230316101736.482737-6-chigot@adacore.com/mbox/"},{"id":70782,"url":"https://patchwork.plctlab.org/api/1.2/patches/70782/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230316132101.205752-1-christophe.lyon@linaro.org/","msgid":"<20230316132101.205752-1-christophe.lyon@linaro.org>","list_archive_url":null,"date":"2023-03-16T13:21:01","name":"Re: Add --enable-linker-version option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230316132101.205752-1-christophe.lyon@linaro.org/mbox/"},{"id":71031,"url":"https://patchwork.plctlab.org/api/1.2/patches/71031/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230317015323.567132-1-jiawei@iscas.ac.cn/","msgid":"<20230317015323.567132-1-jiawei@iscas.ac.cn>","list_archive_url":null,"date":"2023-03-17T01:53:23","name":"RISC-V: Adjust the '\''print_insn'\'' return value of disassembling.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230317015323.567132-1-jiawei@iscas.ac.cn/mbox/"},{"id":71117,"url":"https://patchwork.plctlab.org/api/1.2/patches/71117/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZBQb0o0YlU860KEo@fedora/","msgid":"","list_archive_url":null,"date":"2023-03-17T07:50:42","name":"Add support to readelf for the PT_OPENBSD_MUTABLE segment type.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZBQb0o0YlU860KEo@fedora/mbox/"},{"id":71230,"url":"https://patchwork.plctlab.org/api/1.2/patches/71230/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZBRD1+lZYMBOT2i6@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-17T10:41:27","name":"strange segfault i386-dis.c:9815:28","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZBRD1+lZYMBOT2i6@squeak.grove.modra.org/mbox/"},{"id":71234,"url":"https://patchwork.plctlab.org/api/1.2/patches/71234/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZBRE2M3WrYfRkhVz@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-17T10:45:44","name":"Another source_sh","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZBRE2M3WrYfRkhVz@squeak.grove.modra.org/mbox/"},{"id":71237,"url":"https://patchwork.plctlab.org/api/1.2/patches/71237/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZBRE8g4zs0fVGz5o@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-17T10:46:10","name":"mach-o: out of memory in get_dynamic_reloc_upper_bound","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZBRE8g4zs0fVGz5o@squeak.grove.modra.org/mbox/"},{"id":71244,"url":"https://patchwork.plctlab.org/api/1.2/patches/71244/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230317105552.82190-1-nelson@rivosinc.com/","msgid":"<20230317105552.82190-1-nelson@rivosinc.com>","list_archive_url":null,"date":"2023-03-17T10:55:52","name":"RISC-V: Clarify link behaviors of R_RISCV_32/64 relocations with ABS symbol.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230317105552.82190-1-nelson@rivosinc.com/mbox/"},{"id":71345,"url":"https://patchwork.plctlab.org/api/1.2/patches/71345/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230317160045.502282-2-cupertino.miranda@oracle.com/","msgid":"<20230317160045.502282-2-cupertino.miranda@oracle.com>","list_archive_url":null,"date":"2023-03-17T16:00:44","name":"[1/2] Reloc howto access broken for BPF","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230317160045.502282-2-cupertino.miranda@oracle.com/mbox/"},{"id":71346,"url":"https://patchwork.plctlab.org/api/1.2/patches/71346/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230317160045.502282-3-cupertino.miranda@oracle.com/","msgid":"<20230317160045.502282-3-cupertino.miranda@oracle.com>","list_archive_url":null,"date":"2023-03-17T16:00:45","name":"[2/2] Changed ld and gas BPF tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230317160045.502282-3-cupertino.miranda@oracle.com/mbox/"},{"id":71521,"url":"https://patchwork.plctlab.org/api/1.2/patches/71521/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230317233448.1832535-1-vladimir.mezentsev@oracle.com/","msgid":"<20230317233448.1832535-1-vladimir.mezentsev@oracle.com>","list_archive_url":null,"date":"2023-03-17T23:34:48","name":"[Review,is,neded] gprofng: Use prototype to call libc functions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230317233448.1832535-1-vladimir.mezentsev@oracle.com/mbox/"},{"id":71749,"url":"https://patchwork.plctlab.org/api/1.2/patches/71749/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZBb3JpbiFebpIfHc@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-19T11:51:02","name":"ctf segfaults","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZBb3JpbiFebpIfHc@squeak.grove.modra.org/mbox/"},{"id":71751,"url":"https://patchwork.plctlab.org/api/1.2/patches/71751/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZBb3UOUJo8DAMRJy@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-19T11:51:44","name":"Another sanity check for read_section_stabs_debugging_info","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZBb3UOUJo8DAMRJy@squeak.grove.modra.org/mbox/"},{"id":71752,"url":"https://patchwork.plctlab.org/api/1.2/patches/71752/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZBb3eQ0ulZBDWzmK@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-19T11:52:25","name":"rewrite_elf_program_header and want_p_paddr_set_to_zero","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZBb3eQ0ulZBDWzmK@squeak.grove.modra.org/mbox/"},{"id":71753,"url":"https://patchwork.plctlab.org/api/1.2/patches/71753/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZBb3oOZ4J35lf6nK@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-19T11:53:04","name":"XCOFF archive sanity check","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZBb3oOZ4J35lf6nK@squeak.grove.modra.org/mbox/"},{"id":71754,"url":"https://patchwork.plctlab.org/api/1.2/patches/71754/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZBb3vmeOkA/l+tlY@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-19T11:53:34","name":"Regen ld/po/BLD-POTFILES.in","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZBb3vmeOkA/l+tlY@squeak.grove.modra.org/mbox/"},{"id":71942,"url":"https://patchwork.plctlab.org/api/1.2/patches/71942/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230320033444.2819-1-jiawei@iscas.ac.cn/","msgid":"<20230320033444.2819-1-jiawei@iscas.ac.cn>","list_archive_url":null,"date":"2023-03-20T03:34:44","name":"[v2] RISC-V: Fix disassemble fetch fail return value.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230320033444.2819-1-jiawei@iscas.ac.cn/mbox/"},{"id":72083,"url":"https://patchwork.plctlab.org/api/1.2/patches/72083/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZBg2d0PwGiSJ3tft@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-20T10:33:27","name":"libctf: unused variable","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZBg2d0PwGiSJ3tft@squeak.grove.modra.org/mbox/"},{"id":72295,"url":"https://patchwork.plctlab.org/api/1.2/patches/72295/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230320170313.354203-1-hjl.tools@gmail.com/","msgid":"<20230320170313.354203-1-hjl.tools@gmail.com>","list_archive_url":null,"date":"2023-03-20T17:03:13","name":"x86: Check unbalanced braces in memory reference","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230320170313.354203-1-hjl.tools@gmail.com/mbox/"},{"id":72904,"url":"https://patchwork.plctlab.org/api/1.2/patches/72904/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230321142839.672428-1-szabolcs.nagy@arm.com/","msgid":"<20230321142839.672428-1-szabolcs.nagy@arm.com>","list_archive_url":null,"date":"2023-03-21T14:28:39","name":"[1/3] bfd: aarch64: Refactor stub sizing code","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230321142839.672428-1-szabolcs.nagy@arm.com/mbox/"},{"id":72903,"url":"https://patchwork.plctlab.org/api/1.2/patches/72903/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230321142848.672474-1-szabolcs.nagy@arm.com/","msgid":"<20230321142848.672474-1-szabolcs.nagy@arm.com>","list_archive_url":null,"date":"2023-03-21T14:28:48","name":"[2/3] bfd: aarch64: Fix stubs that may break BTI PR30076","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230321142848.672474-1-szabolcs.nagy@arm.com/mbox/"},{"id":72905,"url":"https://patchwork.plctlab.org/api/1.2/patches/72905/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230321142857.672520-1-szabolcs.nagy@arm.com/","msgid":"<20230321142857.672520-1-szabolcs.nagy@arm.com>","list_archive_url":null,"date":"2023-03-21T14:28:57","name":"[3/3] bfd: aarch64: Optimize BTI stubs PR30076","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230321142857.672520-1-szabolcs.nagy@arm.com/mbox/"},{"id":73096,"url":"https://patchwork.plctlab.org/api/1.2/patches/73096/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZBoyS2GDkUCU6oU6@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-21T22:40:11","name":"gas: expand_irp memory leaks","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZBoyS2GDkUCU6oU6@squeak.grove.modra.org/mbox/"},{"id":73098,"url":"https://patchwork.plctlab.org/api/1.2/patches/73098/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZBoyeGHPA+1YemsH@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-21T22:40:56","name":"XCOFF: use bfd_coff_close_and_cleanup","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZBoyeGHPA+1YemsH@squeak.grove.modra.org/mbox/"},{"id":73100,"url":"https://patchwork.plctlab.org/api/1.2/patches/73100/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZBoyosqQBtXm4rI0@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-21T22:41:38","name":"PE fake section for C_SECTION syms","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZBoyosqQBtXm4rI0@squeak.grove.modra.org/mbox/"},{"id":73101,"url":"https://patchwork.plctlab.org/api/1.2/patches/73101/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZBoz7Wa4EHV+q9Gd@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-21T22:47:09","name":"PR17910 sym string offset check","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZBoz7Wa4EHV+q9Gd@squeak.grove.modra.org/mbox/"},{"id":73102,"url":"https://patchwork.plctlab.org/api/1.2/patches/73102/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZBo0ISexQkdavEpk@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-21T22:48:01","name":"Sanity check coff-sh and coff-mcore sym string offset","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZBo0ISexQkdavEpk@squeak.grove.modra.org/mbox/"},{"id":73105,"url":"https://patchwork.plctlab.org/api/1.2/patches/73105/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZBo5fIjQft2+fwJW@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-21T23:10:52","name":"Remove unnecessary memsets in sframe-dump.c","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZBo5fIjQft2+fwJW@squeak.grove.modra.org/mbox/"},{"id":73115,"url":"https://patchwork.plctlab.org/api/1.2/patches/73115/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZBpIM3lRdkoNAN+5@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-22T00:13:39","name":"coff_get_normalized_symtab bfd_release","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZBpIM3lRdkoNAN+5@squeak.grove.modra.org/mbox/"},{"id":73996,"url":"https://patchwork.plctlab.org/api/1.2/patches/73996/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230323105959.1449936-1-yunqiang.su@cipunited.com/","msgid":"<20230323105959.1449936-1-yunqiang.su@cipunited.com>","list_archive_url":null,"date":"2023-03-23T10:59:59","name":"MIPS: fix loongson3 llsc workaround","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230323105959.1449936-1-yunqiang.su@cipunited.com/mbox/"},{"id":74094,"url":"https://patchwork.plctlab.org/api/1.2/patches/74094/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/dc0f734f-9fba-7a7b-a746-49b4fc033dac@suse.com/","msgid":"","list_archive_url":null,"date":"2023-03-23T14:30:15","name":"Arm64/ELF: accept relocations against STN_UNDEF","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/dc0f734f-9fba-7a7b-a746-49b4fc033dac@suse.com/mbox/"},{"id":74480,"url":"https://patchwork.plctlab.org/api/1.2/patches/74480/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZB18Z0o3MG+6xpxp@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-24T10:33:11","name":"Tidy dwarf1 cached section contents","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZB18Z0o3MG+6xpxp@squeak.grove.modra.org/mbox/"},{"id":74481,"url":"https://patchwork.plctlab.org/api/1.2/patches/74481/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZB187ZhUAam/KJLp@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-24T10:35:25","name":"Tidy string_ptr increment","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZB187ZhUAam/KJLp@squeak.grove.modra.org/mbox/"},{"id":74544,"url":"https://patchwork.plctlab.org/api/1.2/patches/74544/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230324133625.450723-1-nick.alcock@oracle.com/","msgid":"<20230324133625.450723-1-nick.alcock@oracle.com>","list_archive_url":null,"date":"2023-03-24T13:36:22","name":"[1/4] libctf: fix assertion failure with no system qsort_r","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230324133625.450723-1-nick.alcock@oracle.com/mbox/"},{"id":74545,"url":"https://patchwork.plctlab.org/api/1.2/patches/74545/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230324133625.450723-2-nick.alcock@oracle.com/","msgid":"<20230324133625.450723-2-nick.alcock@oracle.com>","list_archive_url":null,"date":"2023-03-24T13:36:23","name":"[2/4] libctf: work around an uninitialized variable warning","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230324133625.450723-2-nick.alcock@oracle.com/mbox/"},{"id":74547,"url":"https://patchwork.plctlab.org/api/1.2/patches/74547/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230324133625.450723-3-nick.alcock@oracle.com/","msgid":"<20230324133625.450723-3-nick.alcock@oracle.com>","list_archive_url":null,"date":"2023-03-24T13:36:24","name":"[3/4] libctf: fix a comment typo","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230324133625.450723-3-nick.alcock@oracle.com/mbox/"},{"id":74546,"url":"https://patchwork.plctlab.org/api/1.2/patches/74546/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230324133625.450723-4-nick.alcock@oracle.com/","msgid":"<20230324133625.450723-4-nick.alcock@oracle.com>","list_archive_url":null,"date":"2023-03-24T13:36:25","name":"[4/4] libctf: get the offsets of fields of unnamed structs/unions right","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230324133625.450723-4-nick.alcock@oracle.com/mbox/"},{"id":74560,"url":"https://patchwork.plctlab.org/api/1.2/patches/74560/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ba77df02-5583-fb1d-5e1c-812106c2749f@redhat.com/","msgid":"","list_archive_url":null,"date":"2023-03-24T14:02:55","name":"[Bug,gold/30187] ld.bfd and ld.gold versions in .comment section of ELF files","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ba77df02-5583-fb1d-5e1c-812106c2749f@redhat.com/mbox/"},{"id":74795,"url":"https://patchwork.plctlab.org/api/1.2/patches/74795/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230325004113.22673-1-nelson@rivosinc.com/","msgid":"<20230325004113.22673-1-nelson@rivosinc.com>","list_archive_url":null,"date":"2023-03-25T00:41:11","name":"[1/3] RISC-V: Extract the ld code which are too complicated, and may be reused.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230325004113.22673-1-nelson@rivosinc.com/mbox/"},{"id":74798,"url":"https://patchwork.plctlab.org/api/1.2/patches/74798/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230325004113.22673-2-nelson@rivosinc.com/","msgid":"<20230325004113.22673-2-nelson@rivosinc.com>","list_archive_url":null,"date":"2023-03-25T00:41:12","name":"[2/3] RISC-V: Clarify link behaviors of R_RISCV_32/64 relocations with ABS symbol.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230325004113.22673-2-nelson@rivosinc.com/mbox/"},{"id":74796,"url":"https://patchwork.plctlab.org/api/1.2/patches/74796/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230325004113.22673-3-nelson@rivosinc.com/","msgid":"<20230325004113.22673-3-nelson@rivosinc.com>","list_archive_url":null,"date":"2023-03-25T00:41:13","name":"[3/3] RISC-V: PR28789, Reject R_RISCV_PCREL relocations with ABS symbol in PIC/PIE.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230325004113.22673-3-nelson@rivosinc.com/mbox/"},{"id":75166,"url":"https://patchwork.plctlab.org/api/1.2/patches/75166/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230326231111.3207581-1-vladimir.mezentsev@oracle.com/","msgid":"<20230326231111.3207581-1-vladimir.mezentsev@oracle.com>","list_archive_url":null,"date":"2023-03-26T23:11:11","name":"[Review,is,neded] gprofng: 30089 [display text] Invalid number of threads","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230326231111.3207581-1-vladimir.mezentsev@oracle.com/mbox/"},{"id":75242,"url":"https://patchwork.plctlab.org/api/1.2/patches/75242/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230327080107.3266866-2-christoph.muellner@vrull.eu/","msgid":"<20230327080107.3266866-2-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2023-03-27T08:01:06","name":"[RFC,v2,1/2] RISC-V: Allocate \"various\" operand type","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230327080107.3266866-2-christoph.muellner@vrull.eu/mbox/"},{"id":75245,"url":"https://patchwork.plctlab.org/api/1.2/patches/75245/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230327080107.3266866-3-christoph.muellner@vrull.eu/","msgid":"<20230327080107.3266866-3-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2023-03-27T08:01:07","name":"[RFC,v2,2/2] RISC-V: Add support for the Zfa extension","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230327080107.3266866-3-christoph.muellner@vrull.eu/mbox/"},{"id":75347,"url":"https://patchwork.plctlab.org/api/1.2/patches/75347/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZCF80Rw5CxmJnTxO@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-27T11:24:01","name":"XCOFF sanity check","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZCF80Rw5CxmJnTxO@squeak.grove.modra.org/mbox/"},{"id":75348,"url":"https://patchwork.plctlab.org/api/1.2/patches/75348/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZCF9NGTTWGGN5wkG@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-27T11:25:40","name":"Duplicate DW_AT_call_file leak","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZCF9NGTTWGGN5wkG@squeak.grove.modra.org/mbox/"},{"id":75350,"url":"https://patchwork.plctlab.org/api/1.2/patches/75350/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZCF9rPmAN9m9hcUD@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-27T11:27:40","name":"coffgrok access of u.auxent.x_sym.x_tagndx.p","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZCF9rPmAN9m9hcUD@squeak.grove.modra.org/mbox/"},{"id":75351,"url":"https://patchwork.plctlab.org/api/1.2/patches/75351/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZCF90abJaTld4Nn0@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-27T11:28:17","name":"Set proper union selector tag","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZCF90abJaTld4Nn0@squeak.grove.modra.org/mbox/"},{"id":75353,"url":"https://patchwork.plctlab.org/api/1.2/patches/75353/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZCF+rw8MIhhkeETH@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-27T11:31:59","name":"Use stdint types in coff internal_auxent","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZCF+rw8MIhhkeETH@squeak.grove.modra.org/mbox/"},{"id":75354,"url":"https://patchwork.plctlab.org/api/1.2/patches/75354/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZCF+2jvDqqXV1fVf@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-27T11:32:42","name":"Remove coff_pointerize_aux table_end param","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZCF+2jvDqqXV1fVf@squeak.grove.modra.org/mbox/"},{"id":75355,"url":"https://patchwork.plctlab.org/api/1.2/patches/75355/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZCF/CDC7SaaO4WhF@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-27T11:33:28","name":"Tidy tc-ppc.c XCOFF auxent access","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZCF/CDC7SaaO4WhF@squeak.grove.modra.org/mbox/"},{"id":75768,"url":"https://patchwork.plctlab.org/api/1.2/patches/75768/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZCJMUDd146mhNogB@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-28T02:09:20","name":"ubsan: elfnn-aarch64.c:4595:19: runtime error: load of value 190","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZCJMUDd146mhNogB@squeak.grove.modra.org/mbox/"},{"id":75974,"url":"https://patchwork.plctlab.org/api/1.2/patches/75974/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZCLDZsdo518WMpRM@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-28T10:37:26","name":"Avoid undefined behaviour in m68hc11 md_begin","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZCLDZsdo518WMpRM@squeak.grove.modra.org/mbox/"},{"id":76299,"url":"https://patchwork.plctlab.org/api/1.2/patches/76299/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230328230249.274759-2-david@davidgf.es/","msgid":"<20230328230249.274759-2-david@davidgf.es>","list_archive_url":null,"date":"2023-03-28T23:02:47","name":"[1/3] Add Allegrex CPU as a MIPS2-based CPU","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230328230249.274759-2-david@davidgf.es/mbox/"},{"id":76298,"url":"https://patchwork.plctlab.org/api/1.2/patches/76298/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230328230249.274759-3-david@davidgf.es/","msgid":"<20230328230249.274759-3-david@davidgf.es>","list_archive_url":null,"date":"2023-03-28T23:02:48","name":"[2/3] Add rotation instructions to allegrex CPU","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230328230249.274759-3-david@davidgf.es/mbox/"},{"id":76300,"url":"https://patchwork.plctlab.org/api/1.2/patches/76300/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230328230249.274759-4-david@davidgf.es/","msgid":"<20230328230249.274759-4-david@davidgf.es>","list_archive_url":null,"date":"2023-03-28T23:02:49","name":"[3/3] Adding more instructions to Allegrex CPU","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230328230249.274759-4-david@davidgf.es/mbox/"},{"id":76303,"url":"https://patchwork.plctlab.org/api/1.2/patches/76303/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZCN2J6V/OvvDMa3L@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-28T23:20:07","name":"ld testsuite CFLAGS_FOR_TARGET","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZCN2J6V/OvvDMa3L@squeak.grove.modra.org/mbox/"},{"id":76347,"url":"https://patchwork.plctlab.org/api/1.2/patches/76347/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZCOnk+1MgYLzyM65@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-29T02:50:59","name":"Sanity check section size in bfd_init_section_compress_status","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZCOnk+1MgYLzyM65@squeak.grove.modra.org/mbox/"},{"id":76561,"url":"https://patchwork.plctlab.org/api/1.2/patches/76561/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2a19f48f-2230-70c2-a6eb-de224028e8ae@embedded-brains.de/","msgid":"<2a19f48f-2230-70c2-a6eb-de224028e8ae@embedded-brains.de>","list_archive_url":null,"date":"2023-03-29T12:44:50","name":"RFC: Add ELF note for description with JSON data","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2a19f48f-2230-70c2-a6eb-de224028e8ae@embedded-brains.de/mbox/"},{"id":76636,"url":"https://patchwork.plctlab.org/api/1.2/patches/76636/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/87v8ijmxjh.fsf@redhat.com/","msgid":"<87v8ijmxjh.fsf@redhat.com>","list_archive_url":null,"date":"2023-03-29T14:39:46","name":"RFC: Can static executables contain relocations against symbols ?","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/87v8ijmxjh.fsf@redhat.com/mbox/"},{"id":76860,"url":"https://patchwork.plctlab.org/api/1.2/patches/76860/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/CAB=4xhrACo0JzK-VrnJfYoPxZOiwOYA48-OkShYOz26JPQ9YCA@mail.gmail.com/","msgid":"","list_archive_url":null,"date":"2023-03-30T00:08:03","name":"[COMMITTED] Fix typo in ld manual --enable-non-contiguous-regions example","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/CAB=4xhrACo0JzK-VrnJfYoPxZOiwOYA48-OkShYOz26JPQ9YCA@mail.gmail.com/mbox/"},{"id":76881,"url":"https://patchwork.plctlab.org/api/1.2/patches/76881/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZCUUuatLLu5VmpJx@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-30T04:48:57","name":"Tidy memory on addr2line failures","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZCUUuatLLu5VmpJx@squeak.grove.modra.org/mbox/"},{"id":76882,"url":"https://patchwork.plctlab.org/api/1.2/patches/76882/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZCUU2U5h4L4pOyCY@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-30T04:49:29","name":"Tidy leaked objcopy memory","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZCUU2U5h4L4pOyCY@squeak.grove.modra.org/mbox/"},{"id":76887,"url":"https://patchwork.plctlab.org/api/1.2/patches/76887/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZCUVAjKL5j0X5DTH@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-30T04:50:10","name":"Fix memory leak in bfd_get_debug_link_info_1","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZCUVAjKL5j0X5DTH@squeak.grove.modra.org/mbox/"},{"id":77007,"url":"https://patchwork.plctlab.org/api/1.2/patches/77007/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330101245.3327499-1-richard.sandiford@arm.com/","msgid":"<20230330101245.3327499-1-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:12:45","name":"aarch64: Add sme-i16i64 and sme-f64f64 aliases","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330101245.3327499-1-richard.sandiford@arm.com/mbox/"},{"id":77019,"url":"https://patchwork.plctlab.org/api/1.2/patches/77019/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-2-richard.sandiford@arm.com/","msgid":"<20230330102359.3327695-2-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:23:17","name":"[01/43] aarch64: Fix PSEL opcode mask","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-2-richard.sandiford@arm.com/mbox/"},{"id":77024,"url":"https://patchwork.plctlab.org/api/1.2/patches/77024/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-3-richard.sandiford@arm.com/","msgid":"<20230330102359.3327695-3-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:23:18","name":"[02/43] aarch64: Restrict range of PRFM opcodes","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-3-richard.sandiford@arm.com/mbox/"},{"id":77016,"url":"https://patchwork.plctlab.org/api/1.2/patches/77016/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-4-richard.sandiford@arm.com/","msgid":"<20230330102359.3327695-4-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:23:19","name":"[03/43] aarch64: Fix SVE2 register/immediate distinction","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-4-richard.sandiford@arm.com/mbox/"},{"id":77017,"url":"https://patchwork.plctlab.org/api/1.2/patches/77017/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-5-richard.sandiford@arm.com/","msgid":"<20230330102359.3327695-5-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:23:20","name":"[04/43] aarch64: Make SME instructions use F_STRICT","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-5-richard.sandiford@arm.com/mbox/"},{"id":77031,"url":"https://patchwork.plctlab.org/api/1.2/patches/77031/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-6-richard.sandiford@arm.com/","msgid":"<20230330102359.3327695-6-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:23:21","name":"[05/43] aarch64: Use aarch64_operand_error more widely","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-6-richard.sandiford@arm.com/mbox/"},{"id":77021,"url":"https://patchwork.plctlab.org/api/1.2/patches/77021/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-7-richard.sandiford@arm.com/","msgid":"<20230330102359.3327695-7-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:23:22","name":"[06/43] aarch64: Rename REG_TYPE_ZA* to REG_TYPE_ZAT*","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-7-richard.sandiford@arm.com/mbox/"},{"id":77018,"url":"https://patchwork.plctlab.org/api/1.2/patches/77018/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-8-richard.sandiford@arm.com/","msgid":"<20230330102359.3327695-8-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:23:23","name":"[07/43] aarch64: Add REG_TYPE_ZATHV","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-8-richard.sandiford@arm.com/mbox/"},{"id":77020,"url":"https://patchwork.plctlab.org/api/1.2/patches/77020/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-9-richard.sandiford@arm.com/","msgid":"<20230330102359.3327695-9-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:23:24","name":"[08/43] aarch64: Move vectype_to_qualifier further up","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-9-richard.sandiford@arm.com/mbox/"},{"id":77022,"url":"https://patchwork.plctlab.org/api/1.2/patches/77022/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-10-richard.sandiford@arm.com/","msgid":"<20230330102359.3327695-10-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:23:25","name":"[09/43] aarch64: Rework parse_typed_reg interface","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-10-richard.sandiford@arm.com/mbox/"},{"id":77027,"url":"https://patchwork.plctlab.org/api/1.2/patches/77027/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-11-richard.sandiford@arm.com/","msgid":"<20230330102359.3327695-11-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:23:26","name":"[10/43] aarch64: Reuse parse_typed_reg for ZA tiles","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-11-richard.sandiford@arm.com/mbox/"},{"id":77037,"url":"https://patchwork.plctlab.org/api/1.2/patches/77037/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-12-richard.sandiford@arm.com/","msgid":"<20230330102359.3327695-12-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:23:27","name":"[11/43] aarch64: Consolidate ZA tile range checks","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-12-richard.sandiford@arm.com/mbox/"},{"id":77034,"url":"https://patchwork.plctlab.org/api/1.2/patches/77034/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-13-richard.sandiford@arm.com/","msgid":"<20230330102359.3327695-13-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:23:28","name":"[12/43] aarch64: Treat ZA as a register","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-13-richard.sandiford@arm.com/mbox/"},{"id":77029,"url":"https://patchwork.plctlab.org/api/1.2/patches/77029/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-14-richard.sandiford@arm.com/","msgid":"<20230330102359.3327695-14-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:23:29","name":"[13/43] aarch64: Rename za_tile_vector to za_index","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-14-richard.sandiford@arm.com/mbox/"},{"id":77043,"url":"https://patchwork.plctlab.org/api/1.2/patches/77043/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-15-richard.sandiford@arm.com/","msgid":"<20230330102359.3327695-15-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:23:30","name":"[14/43] aarch64: Make indexed_za use 64-bit immediates","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-15-richard.sandiford@arm.com/mbox/"},{"id":77041,"url":"https://patchwork.plctlab.org/api/1.2/patches/77041/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-16-richard.sandiford@arm.com/","msgid":"<20230330102359.3327695-16-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:23:31","name":"[15/43] aarch64: Pass aarch64_indexed_za to parsers","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-16-richard.sandiford@arm.com/mbox/"},{"id":77045,"url":"https://patchwork.plctlab.org/api/1.2/patches/77045/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-17-richard.sandiford@arm.com/","msgid":"<20230330102359.3327695-17-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:23:32","name":"[16/43] aarch64: Move ZA range checks to aarch64-opc.c","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-17-richard.sandiford@arm.com/mbox/"},{"id":77048,"url":"https://patchwork.plctlab.org/api/1.2/patches/77048/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-18-richard.sandiford@arm.com/","msgid":"<20230330102359.3327695-18-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:23:33","name":"[17/43] aarch64: Consolidate ZA slice parsing","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-18-richard.sandiford@arm.com/mbox/"},{"id":77046,"url":"https://patchwork.plctlab.org/api/1.2/patches/77046/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-19-richard.sandiford@arm.com/","msgid":"<20230330102359.3327695-19-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:23:34","name":"[18/43] aarch64: Commonise index parsing","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-19-richard.sandiford@arm.com/mbox/"},{"id":77053,"url":"https://patchwork.plctlab.org/api/1.2/patches/77053/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-20-richard.sandiford@arm.com/","msgid":"<20230330102359.3327695-20-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:23:35","name":"[19/43] aarch64: Move w12-w15 range check to libopcodes","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-20-richard.sandiford@arm.com/mbox/"},{"id":77032,"url":"https://patchwork.plctlab.org/api/1.2/patches/77032/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-21-richard.sandiford@arm.com/","msgid":"<20230330102359.3327695-21-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:23:36","name":"[20/43] aarch64: Tweak error for missing immediate offset","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-21-richard.sandiford@arm.com/mbox/"},{"id":77058,"url":"https://patchwork.plctlab.org/api/1.2/patches/77058/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-22-richard.sandiford@arm.com/","msgid":"<20230330102359.3327695-22-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:23:37","name":"[21/43] aarch64: Tweak errors for base & offset registers","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-22-richard.sandiford@arm.com/mbox/"},{"id":77056,"url":"https://patchwork.plctlab.org/api/1.2/patches/77056/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-23-richard.sandiford@arm.com/","msgid":"<20230330102359.3327695-23-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:23:38","name":"[22/43] aarch64: Tweak parsing of integer & FP registers","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-23-richard.sandiford@arm.com/mbox/"},{"id":77052,"url":"https://patchwork.plctlab.org/api/1.2/patches/77052/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-24-richard.sandiford@arm.com/","msgid":"<20230330102359.3327695-24-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:23:39","name":"[23/43] aarch64: Improve errors for malformed register lists","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-24-richard.sandiford@arm.com/mbox/"},{"id":77064,"url":"https://patchwork.plctlab.org/api/1.2/patches/77064/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-25-richard.sandiford@arm.com/","msgid":"<20230330102359.3327695-25-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:23:40","name":"[24/43] aarch64: Try to avoid inappropriate default errors","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-25-richard.sandiford@arm.com/mbox/"},{"id":77070,"url":"https://patchwork.plctlab.org/api/1.2/patches/77070/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-26-richard.sandiford@arm.com/","msgid":"<20230330102359.3327695-26-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:23:41","name":"[25/43] aarch64: Rework reporting of failed register checks","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-26-richard.sandiford@arm.com/mbox/"},{"id":77050,"url":"https://patchwork.plctlab.org/api/1.2/patches/77050/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-27-richard.sandiford@arm.com/","msgid":"<20230330102359.3327695-27-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:23:42","name":"[26/43] aarch64: Update operand_mismatch_kind_names","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-27-richard.sandiford@arm.com/mbox/"},{"id":77054,"url":"https://patchwork.plctlab.org/api/1.2/patches/77054/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-28-richard.sandiford@arm.com/","msgid":"<20230330102359.3327695-28-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:23:43","name":"[27/43] aarch64: Deprioritise AARCH64_OPDE_REG_LIST","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-28-richard.sandiford@arm.com/mbox/"},{"id":77042,"url":"https://patchwork.plctlab.org/api/1.2/patches/77042/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-29-richard.sandiford@arm.com/","msgid":"<20230330102359.3327695-29-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:23:44","name":"[28/43] aarch64: Add an error code for out-of-range registers","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-29-richard.sandiford@arm.com/mbox/"},{"id":77060,"url":"https://patchwork.plctlab.org/api/1.2/patches/77060/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-30-richard.sandiford@arm.com/","msgid":"<20230330102359.3327695-30-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:23:45","name":"[29/43] aarch64: Commonise checks for index operands","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-30-richard.sandiford@arm.com/mbox/"},{"id":77066,"url":"https://patchwork.plctlab.org/api/1.2/patches/77066/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-31-richard.sandiford@arm.com/","msgid":"<20230330102359.3327695-31-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:23:46","name":"[30/43] aarch64: Add an operand class for SVE register lists","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-31-richard.sandiford@arm.com/mbox/"},{"id":77067,"url":"https://patchwork.plctlab.org/api/1.2/patches/77067/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-32-richard.sandiford@arm.com/","msgid":"<20230330102359.3327695-32-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:23:47","name":"[31/43] aarch64: Make AARCH64_OPDE_REG_LIST take a bitfield","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-32-richard.sandiford@arm.com/mbox/"},{"id":77047,"url":"https://patchwork.plctlab.org/api/1.2/patches/77047/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-33-richard.sandiford@arm.com/","msgid":"<20230330102359.3327695-33-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:23:48","name":"[32/43] aarch64: Tweak register list errors","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-33-richard.sandiford@arm.com/mbox/"},{"id":77072,"url":"https://patchwork.plctlab.org/api/1.2/patches/77072/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-34-richard.sandiford@arm.com/","msgid":"<20230330102359.3327695-34-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:23:49","name":"[33/43] aarch64: Try to report invalid variants against the closest match","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-34-richard.sandiford@arm.com/mbox/"},{"id":77051,"url":"https://patchwork.plctlab.org/api/1.2/patches/77051/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-35-richard.sandiford@arm.com/","msgid":"<20230330102359.3327695-35-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:23:50","name":"[34/43] aarch64: Tweak priorities of parsing-related errors","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-35-richard.sandiford@arm.com/mbox/"},{"id":77079,"url":"https://patchwork.plctlab.org/api/1.2/patches/77079/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-36-richard.sandiford@arm.com/","msgid":"<20230330102359.3327695-36-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:23:51","name":"[35/43] aarch64: Rename aarch64-tbl.h OP_SME_* macros","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-36-richard.sandiford@arm.com/mbox/"},{"id":77055,"url":"https://patchwork.plctlab.org/api/1.2/patches/77055/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-37-richard.sandiford@arm.com/","msgid":"<20230330102359.3327695-37-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:23:52","name":"[36/43] aarch64: Reorder some OP_SVE_* macros","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-37-richard.sandiford@arm.com/mbox/"},{"id":77082,"url":"https://patchwork.plctlab.org/api/1.2/patches/77082/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-38-richard.sandiford@arm.com/","msgid":"<20230330102359.3327695-38-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:23:53","name":"[37/43] aarch64: Add a aarch64_cpu_supports_inst_p helper","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-38-richard.sandiford@arm.com/mbox/"},{"id":77068,"url":"https://patchwork.plctlab.org/api/1.2/patches/77068/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-39-richard.sandiford@arm.com/","msgid":"<20230330102359.3327695-39-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:23:54","name":"[38/43] aarch64: Rename some of GAS'\''s REG_TYPE_* macros","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-39-richard.sandiford@arm.com/mbox/"},{"id":77073,"url":"https://patchwork.plctlab.org/api/1.2/patches/77073/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-40-richard.sandiford@arm.com/","msgid":"<20230330102359.3327695-40-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:23:55","name":"[39/43] aarch64: Regularise FLD_* suffixes","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-40-richard.sandiford@arm.com/mbox/"},{"id":77084,"url":"https://patchwork.plctlab.org/api/1.2/patches/77084/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-41-richard.sandiford@arm.com/","msgid":"<20230330102359.3327695-41-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:23:56","name":"[40/43] aarch64: Resync field names","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-41-richard.sandiford@arm.com/mbox/"},{"id":77077,"url":"https://patchwork.plctlab.org/api/1.2/patches/77077/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-42-richard.sandiford@arm.com/","msgid":"<20230330102359.3327695-42-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:23:57","name":"[41/43] aarch64: Sort fields alphanumerically","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-42-richard.sandiford@arm.com/mbox/"},{"id":77063,"url":"https://patchwork.plctlab.org/api/1.2/patches/77063/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-43-richard.sandiford@arm.com/","msgid":"<20230330102359.3327695-43-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:23:58","name":"[42/43] aarch64: Add support for strided register lists","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-43-richard.sandiford@arm.com/mbox/"},{"id":77078,"url":"https://patchwork.plctlab.org/api/1.2/patches/77078/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-44-richard.sandiford@arm.com/","msgid":"<20230330102359.3327695-44-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:23:59","name":"[43/43] aarch64: Prefer register ranges & support wrapping","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-44-richard.sandiford@arm.com/mbox/"},{"id":77086,"url":"https://patchwork.plctlab.org/api/1.2/patches/77086/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102646.3327818-2-richard.sandiford@arm.com/","msgid":"<20230330102646.3327818-2-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:26:16","name":"[01/31] aarch64: Add +sme2","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102646.3327818-2-richard.sandiford@arm.com/mbox/"},{"id":77090,"url":"https://patchwork.plctlab.org/api/1.2/patches/77090/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102646.3327818-3-richard.sandiford@arm.com/","msgid":"<20230330102646.3327818-3-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:26:17","name":"[02/31] aarch64: Add a _10 suffix to FLD_imm3","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102646.3327818-3-richard.sandiford@arm.com/mbox/"},{"id":77076,"url":"https://patchwork.plctlab.org/api/1.2/patches/77076/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102646.3327818-4-richard.sandiford@arm.com/","msgid":"<20230330102646.3327818-4-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:26:18","name":"[03/31] aarch64: Add _off4 suffix to AARCH64_OPND_SME_ZA_array","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102646.3327818-4-richard.sandiford@arm.com/mbox/"},{"id":77083,"url":"https://patchwork.plctlab.org/api/1.2/patches/77083/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102646.3327818-5-richard.sandiford@arm.com/","msgid":"<20230330102646.3327818-5-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:26:19","name":"[04/31] aarch64: Add support for vgx2 and vgx4","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102646.3327818-5-richard.sandiford@arm.com/mbox/"},{"id":77081,"url":"https://patchwork.plctlab.org/api/1.2/patches/77081/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102646.3327818-6-richard.sandiford@arm.com/","msgid":"<20230330102646.3327818-6-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:26:20","name":"[05/31] aarch64; Add support for vector offset ranges","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102646.3327818-6-richard.sandiford@arm.com/mbox/"},{"id":77085,"url":"https://patchwork.plctlab.org/api/1.2/patches/77085/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102646.3327818-8-richard.sandiford@arm.com/","msgid":"<20230330102646.3327818-8-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:26:22","name":"[07/31] aarch64: Add the SME2 MOVA instructions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102646.3327818-8-richard.sandiford@arm.com/mbox/"},{"id":77071,"url":"https://patchwork.plctlab.org/api/1.2/patches/77071/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102646.3327818-11-richard.sandiford@arm.com/","msgid":"<20230330102646.3327818-11-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:26:25","name":"[10/31] aarch64: Add the SME2 ZT0 instructions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102646.3327818-11-richard.sandiford@arm.com/mbox/"},{"id":77080,"url":"https://patchwork.plctlab.org/api/1.2/patches/77080/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102646.3327818-12-richard.sandiford@arm.com/","msgid":"<20230330102646.3327818-12-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:26:26","name":"[11/31] aarch64: Add the SME2 ADD and SUB instructions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102646.3327818-12-richard.sandiford@arm.com/mbox/"},{"id":77087,"url":"https://patchwork.plctlab.org/api/1.2/patches/77087/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102646.3327818-14-richard.sandiford@arm.com/","msgid":"<20230330102646.3327818-14-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:26:28","name":"[13/31] aarch64: Add the SME2 FMLA and FMLS instructions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102646.3327818-14-richard.sandiford@arm.com/mbox/"},{"id":77093,"url":"https://patchwork.plctlab.org/api/1.2/patches/77093/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102646.3327818-23-richard.sandiford@arm.com/","msgid":"<20230330102646.3327818-23-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:26:37","name":"[22/31] aarch64: Add the SME2 saturating conversion instructions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102646.3327818-23-richard.sandiford@arm.com/mbox/"},{"id":77091,"url":"https://patchwork.plctlab.org/api/1.2/patches/77091/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102646.3327818-24-richard.sandiford@arm.com/","msgid":"<20230330102646.3327818-24-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:26:38","name":"[23/31] aarch64: Add the SME2 shift instructions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102646.3327818-24-richard.sandiford@arm.com/mbox/"},{"id":77095,"url":"https://patchwork.plctlab.org/api/1.2/patches/77095/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102646.3327818-25-richard.sandiford@arm.com/","msgid":"<20230330102646.3327818-25-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:26:39","name":"[24/31] aarch64: Add the SME2 UNPK instructions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102646.3327818-25-richard.sandiford@arm.com/mbox/"},{"id":77092,"url":"https://patchwork.plctlab.org/api/1.2/patches/77092/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102646.3327818-26-richard.sandiford@arm.com/","msgid":"<20230330102646.3327818-26-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:26:40","name":"[25/31] aarch64: Add the SME2 UZP and ZIP instructions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102646.3327818-26-richard.sandiford@arm.com/mbox/"},{"id":77097,"url":"https://patchwork.plctlab.org/api/1.2/patches/77097/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330103528.3497996-2-christoph.muellner@vrull.eu/","msgid":"<20230330103528.3497996-2-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2023-03-30T10:35:27","name":"[RFC,v3,1/2] RISC-V: Allocate \"various\" operand type","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330103528.3497996-2-christoph.muellner@vrull.eu/mbox/"},{"id":77098,"url":"https://patchwork.plctlab.org/api/1.2/patches/77098/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330103528.3497996-3-christoph.muellner@vrull.eu/","msgid":"<20230330103528.3497996-3-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2023-03-30T10:35:28","name":"[RFC,v3,2/2] RISC-V: Add support for the Zfa extension","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330103528.3497996-3-christoph.muellner@vrull.eu/mbox/"},{"id":77244,"url":"https://patchwork.plctlab.org/api/1.2/patches/77244/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/mptsfdmut0x.fsf@arm.com/","msgid":"","list_archive_url":null,"date":"2023-03-30T16:02:22","name":"aarch64: Remove stray reglist variable","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/mptsfdmut0x.fsf@arm.com/mbox/"},{"id":77311,"url":"https://patchwork.plctlab.org/api/1.2/patches/77311/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330164214.735462-1-hjl.tools@gmail.com/","msgid":"<20230330164214.735462-1-hjl.tools@gmail.com>","list_archive_url":null,"date":"2023-03-30T16:42:14","name":"lto: Don'\''t add indirect symbols for versioned aliases in IR","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330164214.735462-1-hjl.tools@gmail.com/mbox/"},{"id":77350,"url":"https://patchwork.plctlab.org/api/1.2/patches/77350/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330175438.107102-2-christoph.muellner@vrull.eu/","msgid":"<20230330175438.107102-2-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2023-03-30T17:54:37","name":"[RFC,v4,1/2] RISC-V: Allocate \"various\" operand type","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330175438.107102-2-christoph.muellner@vrull.eu/mbox/"},{"id":77351,"url":"https://patchwork.plctlab.org/api/1.2/patches/77351/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330175438.107102-3-christoph.muellner@vrull.eu/","msgid":"<20230330175438.107102-3-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2023-03-30T17:54:38","name":"[RFC,v4,2/2] RISC-V: Add support for the Zfa extension","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330175438.107102-3-christoph.muellner@vrull.eu/mbox/"},{"id":77708,"url":"https://patchwork.plctlab.org/api/1.2/patches/77708/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/bcc26bf7-bb9f-6ffc-51e8-05b8ff9e05e1@suse.com/","msgid":"","list_archive_url":null,"date":"2023-03-31T10:04:54","name":"[1/3] x86: parse_real_register() does not alter the parsed string","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/bcc26bf7-bb9f-6ffc-51e8-05b8ff9e05e1@suse.com/mbox/"},{"id":77709,"url":"https://patchwork.plctlab.org/api/1.2/patches/77709/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e0e3ab15-50da-a92a-bcec-e392f09a9c37@suse.com/","msgid":"","list_archive_url":null,"date":"2023-03-31T10:05:53","name":"[2/3] x86: parse_register() must not alter the parsed string","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e0e3ab15-50da-a92a-bcec-e392f09a9c37@suse.com/mbox/"},{"id":77710,"url":"https://patchwork.plctlab.org/api/1.2/patches/77710/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b9ae928e-7e33-e158-bc2e-5e832c2f6032@suse.com/","msgid":"","list_archive_url":null,"date":"2023-03-31T10:07:04","name":"[3/3] gas: document that get_symbol_name() can clobber the input buffer","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b9ae928e-7e33-e158-bc2e-5e832c2f6032@suse.com/mbox/"},{"id":77794,"url":"https://patchwork.plctlab.org/api/1.2/patches/77794/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/efb685d2-b2cb-9baf-0352-d0aa7961c300@suse.com/","msgid":"","list_archive_url":null,"date":"2023-03-31T14:19:21","name":"bfd+ld: when / whether to generate .c files","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/efb685d2-b2cb-9baf-0352-d0aa7961c300@suse.com/mbox/"}],"public":true,"mbox":"https://patchwork.plctlab.org/bundle/patchwork-bot/binutils-gdb_2023-03/mbox/"},{"id":20,"url":"https://patchwork.plctlab.org/api/1.2/bundles/20/","web_url":"https://patchwork.plctlab.org/bundle/patchwork-bot/binutils-gdb_2023-04/","project":{"id":2,"url":"https://patchwork.plctlab.org/api/1.2/projects/2/","name":"binutils-gdb","link_name":"binutils-gdb","list_id":"binutils.sourceware.org","list_email":"binutils@sourceware.org","web_url":"https://github.com/wangliu-iscas/Patchwork-Bundles/blob/main/binutils-gdb.md","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"name":"binutils-gdb_2023-04","owner":{"id":3,"url":"https://patchwork.plctlab.org/api/1.2/users/3/","username":"patchwork-bot","first_name":"","last_name":"","email":"ouuuleilei@gmail.com"},"patches":[{"id":78307,"url":"https://patchwork.plctlab.org/api/1.2/patches/78307/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZCoAJjprIo2dA8lE@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-04-02T22:22:30","name":"Memory leak in process_abbrev_set","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZCoAJjprIo2dA8lE@squeak.grove.modra.org/mbox/"},{"id":78308,"url":"https://patchwork.plctlab.org/api/1.2/patches/78308/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZCoAR84jVZy97VzK@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-04-02T22:23:03","name":"rddbg.c stabs FIXMEs","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZCoAR84jVZy97VzK@squeak.grove.modra.org/mbox/"},{"id":78309,"url":"https://patchwork.plctlab.org/api/1.2/patches/78309/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZCoAZZg7Py/LwyZl@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-04-02T22:23:33","name":"ubsan: aarch64 parse_vector_reg_list","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZCoAZZg7Py/LwyZl@squeak.grove.modra.org/mbox/"},{"id":78310,"url":"https://patchwork.plctlab.org/api/1.2/patches/78310/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZCoAizHXDaTVgiFm@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-04-02T22:24:11","name":"asan: heap buffer overflow printing ecoff debug info file name","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZCoAizHXDaTVgiFm@squeak.grove.modra.org/mbox/"},{"id":78375,"url":"https://patchwork.plctlab.org/api/1.2/patches/78375/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230403071118.2097883-1-haochen.jiang@intel.com/","msgid":"<20230403071118.2097883-1-haochen.jiang@intel.com>","list_archive_url":null,"date":"2023-04-03T07:11:18","name":"Support Intel AMX-COMPLEX","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230403071118.2097883-1-haochen.jiang@intel.com/mbox/"},{"id":78496,"url":"https://patchwork.plctlab.org/api/1.2/patches/78496/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230403110635.23391-1-yunqiang.su@cipunited.com/","msgid":"<20230403110635.23391-1-yunqiang.su@cipunited.com>","list_archive_url":null,"date":"2023-04-03T11:06:35","name":"[v2] MIPS: the default output fellows triple and with-arch","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230403110635.23391-1-yunqiang.su@cipunited.com/mbox/"},{"id":78553,"url":"https://patchwork.plctlab.org/api/1.2/patches/78553/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZCrYJNj8VL4ZsHBV@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-04-03T13:44:04","name":"asan: csky floatformat_to_double uninitialised value","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZCrYJNj8VL4ZsHBV@squeak.grove.modra.org/mbox/"},{"id":78838,"url":"https://patchwork.plctlab.org/api/1.2/patches/78838/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZCueM3aNMfvEirla@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-04-04T03:49:07","name":"Use bfd_alloc memory for read_debugging_info storage","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZCueM3aNMfvEirla@squeak.grove.modra.org/mbox/"},{"id":78868,"url":"https://patchwork.plctlab.org/api/1.2/patches/78868/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9b770800-dc80-2c00-40a2-903cbe4ffb8c@suse.com/","msgid":"<9b770800-dc80-2c00-40a2-903cbe4ffb8c@suse.com>","list_archive_url":null,"date":"2023-04-04T06:58:15","name":"[1/8] x86: move fetch error handling into a helper function","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9b770800-dc80-2c00-40a2-903cbe4ffb8c@suse.com/mbox/"},{"id":78869,"url":"https://patchwork.plctlab.org/api/1.2/patches/78869/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/39b50a10-ad10-aca0-2ef1-4d32be787762@suse.com/","msgid":"<39b50a10-ad10-aca0-2ef1-4d32be787762@suse.com>","list_archive_url":null,"date":"2023-04-04T06:58:37","name":"[2/8] x86: change fetch error handling in top-level function","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/39b50a10-ad10-aca0-2ef1-4d32be787762@suse.com/mbox/"},{"id":78870,"url":"https://patchwork.plctlab.org/api/1.2/patches/78870/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/838292bd-8855-00af-59c8-fcf0acb34d5c@suse.com/","msgid":"<838292bd-8855-00af-59c8-fcf0acb34d5c@suse.com>","list_archive_url":null,"date":"2023-04-04T06:59:17","name":"[3/8] x86: change fetch error handling in ckprefix()","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/838292bd-8855-00af-59c8-fcf0acb34d5c@suse.com/mbox/"},{"id":78871,"url":"https://patchwork.plctlab.org/api/1.2/patches/78871/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b4c84a3d-5266-2395-ba72-97e5ec540b3c@suse.com/","msgid":"","list_archive_url":null,"date":"2023-04-04T06:59:49","name":"[4/8] x86: change fetch error handling in get_valid_dis386()","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b4c84a3d-5266-2395-ba72-97e5ec540b3c@suse.com/mbox/"},{"id":78872,"url":"https://patchwork.plctlab.org/api/1.2/patches/78872/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3231104b-ffc0-e471-79be-f18e14c3264e@suse.com/","msgid":"<3231104b-ffc0-e471-79be-f18e14c3264e@suse.com>","list_archive_url":null,"date":"2023-04-04T07:00:24","name":"[5/8] x86: change fetch error handling when processing operands","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3231104b-ffc0-e471-79be-f18e14c3264e@suse.com/mbox/"},{"id":78873,"url":"https://patchwork.plctlab.org/api/1.2/patches/78873/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a9e13e17-ecf2-8e96-5b48-870801faa750@suse.com/","msgid":"","list_archive_url":null,"date":"2023-04-04T07:00:46","name":"[6/8] x86: change fetch error handling for get()","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a9e13e17-ecf2-8e96-5b48-870801faa750@suse.com/mbox/"},{"id":78874,"url":"https://patchwork.plctlab.org/api/1.2/patches/78874/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9375ae85-ac76-2081-547d-55803c97aadf@suse.com/","msgid":"<9375ae85-ac76-2081-547d-55803c97aadf@suse.com>","list_archive_url":null,"date":"2023-04-04T07:01:04","name":"[7/8] x86: drop use of setjmp() from disassembler","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9375ae85-ac76-2081-547d-55803c97aadf@suse.com/mbox/"},{"id":78875,"url":"https://patchwork.plctlab.org/api/1.2/patches/78875/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4eed4c72-002f-268e-b5cd-0929bc57d6d2@suse.com/","msgid":"<4eed4c72-002f-268e-b5cd-0929bc57d6d2@suse.com>","list_archive_url":null,"date":"2023-04-04T07:01:31","name":"[8/8] x86: drop (explicit) BFD64 dependency from disassembler","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4eed4c72-002f-268e-b5cd-0929bc57d6d2@suse.com/mbox/"},{"id":79194,"url":"https://patchwork.plctlab.org/api/1.2/patches/79194/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/OS3P286MB2152D2B8F88B6EB24B91BD8BF0939@OS3P286MB2152.JPNP286.PROD.OUTLOOK.COM/","msgid":"","list_archive_url":null,"date":"2023-04-04T15:07:13","name":"bfd: add version check to makeinfo","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/OS3P286MB2152D2B8F88B6EB24B91BD8BF0939@OS3P286MB2152.JPNP286.PROD.OUTLOOK.COM/mbox/"},{"id":79999,"url":"https://patchwork.plctlab.org/api/1.2/patches/79999/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZC4RKePLqGKgQ3pO@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-04-06T00:24:09","name":"objcopy write_debugging_info memory leaks","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZC4RKePLqGKgQ3pO@squeak.grove.modra.org/mbox/"},{"id":80000,"url":"https://patchwork.plctlab.org/api/1.2/patches/80000/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZC4RRVFBYw/0n5Le@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-04-06T00:24:37","name":"gas/write.c use better types","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZC4RRVFBYw/0n5Le@squeak.grove.modra.org/mbox/"},{"id":80002,"url":"https://patchwork.plctlab.org/api/1.2/patches/80002/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZC4RdBr7BVn64YcM@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-04-06T00:25:24","name":"objdump -g on gcc COFF/PE files","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZC4RdBr7BVn64YcM@squeak.grove.modra.org/mbox/"},{"id":80003,"url":"https://patchwork.plctlab.org/api/1.2/patches/80003/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZC4RjLt+tU2D/RxY@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-04-06T00:25:48","name":"objdump print_debugging_info memory leaks","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZC4RjLt+tU2D/RxY@squeak.grove.modra.org/mbox/"},{"id":80108,"url":"https://patchwork.plctlab.org/api/1.2/patches/80108/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230406071732.2092853-1-haochen.jiang@intel.com/","msgid":"<20230406071732.2092853-1-haochen.jiang@intel.com>","list_archive_url":null,"date":"2023-04-06T07:17:32","name":"[v2] Support Intel AMX-COMPLEX","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230406071732.2092853-1-haochen.jiang@intel.com/mbox/"},{"id":80642,"url":"https://patchwork.plctlab.org/api/1.2/patches/80642/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230407032809.3763561-1-haochen.jiang@intel.com/","msgid":"<20230407032809.3763561-1-haochen.jiang@intel.com>","list_archive_url":null,"date":"2023-04-07T03:28:09","name":"x86: Add inval tests for AMX instructions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230407032809.3763561-1-haochen.jiang@intel.com/mbox/"},{"id":80675,"url":"https://patchwork.plctlab.org/api/1.2/patches/80675/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230407073501.66953-1-lidie@eswincomputing.com/","msgid":"<20230407073501.66953-1-lidie@eswincomputing.com>","list_archive_url":null,"date":"2023-04-07T07:35:01","name":"Add unclosed macros.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230407073501.66953-1-lidie@eswincomputing.com/mbox/"},{"id":81057,"url":"https://patchwork.plctlab.org/api/1.2/patches/81057/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230407220426.63786-1-nick.alcock@oracle.com/","msgid":"<20230407220426.63786-1-nick.alcock@oracle.com>","list_archive_url":null,"date":"2023-04-07T22:04:24","name":"[1/3] libctf, tests: do not assume host and target have identical field offsets","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230407220426.63786-1-nick.alcock@oracle.com/mbox/"},{"id":81059,"url":"https://patchwork.plctlab.org/api/1.2/patches/81059/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230407220426.63786-2-nick.alcock@oracle.com/","msgid":"<20230407220426.63786-2-nick.alcock@oracle.com>","list_archive_url":null,"date":"2023-04-07T22:04:25","name":"[2/3] libctf: propagate errors from parents correctly","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230407220426.63786-2-nick.alcock@oracle.com/mbox/"},{"id":81058,"url":"https://patchwork.plctlab.org/api/1.2/patches/81058/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230407220426.63786-3-nick.alcock@oracle.com/","msgid":"<20230407220426.63786-3-nick.alcock@oracle.com>","list_archive_url":null,"date":"2023-04-07T22:04:26","name":"[3/3] libctf, link: fix CU-mapped links with CTF_LINK_EMPTY_CU_MAPPINGS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230407220426.63786-3-nick.alcock@oracle.com/mbox/"},{"id":81328,"url":"https://patchwork.plctlab.org/api/1.2/patches/81328/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/745eb337-facd-244a-bd02-d9b8b1f653a5@acm.org/","msgid":"<745eb337-facd-244a-bd02-d9b8b1f653a5@acm.org>","list_archive_url":null,"date":"2023-04-09T22:55:13","name":"bfd: optimize bfd_elf_hash","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/745eb337-facd-244a-bd02-d9b8b1f653a5@acm.org/mbox/"},{"id":81368,"url":"https://patchwork.plctlab.org/api/1.2/patches/81368/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230410065101.822124-1-yunqiang.su@cipunited.com/","msgid":"<20230410065101.822124-1-yunqiang.su@cipunited.com>","list_archive_url":null,"date":"2023-04-10T06:51:01","name":"[v3] MIPS: make mipsisa32 and mipsisa64 link more systematic","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230410065101.822124-1-yunqiang.su@cipunited.com/mbox/"},{"id":82223,"url":"https://patchwork.plctlab.org/api/1.2/patches/82223/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZDYKGcHwDnuaixXL@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-04-12T01:32:09","name":"Comment typo fix","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZDYKGcHwDnuaixXL@squeak.grove.modra.org/mbox/"},{"id":82224,"url":"https://patchwork.plctlab.org/api/1.2/patches/82224/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZDYKPKZ4fcn/AF6v@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-04-12T01:32:44","name":"pe_ILF_object_p and bfd_check_format_matches","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZDYKPKZ4fcn/AF6v@squeak.grove.modra.org/mbox/"},{"id":82225,"url":"https://patchwork.plctlab.org/api/1.2/patches/82225/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZDYKWh5RnEtHftFe@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-04-12T01:33:14","name":"Fail of x86_64 AMX-COMPLEX insns (Intel disassembly)","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZDYKWh5RnEtHftFe@squeak.grove.modra.org/mbox/"},{"id":82226,"url":"https://patchwork.plctlab.org/api/1.2/patches/82226/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZDYKkMb0QCBGC1/F@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-04-12T01:34:08","name":"ubsan: dwarf2.c:2232:7: runtime error: index 16 out of bounds","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZDYKkMb0QCBGC1/F@squeak.grove.modra.org/mbox/"},{"id":82246,"url":"https://patchwork.plctlab.org/api/1.2/patches/82246/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZDY9jn6M1PdoXqNi@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-04-12T05:11:42","name":"PR30326, uninitialised value in objdump compare_relocs","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZDY9jn6M1PdoXqNi@squeak.grove.modra.org/mbox/"},{"id":82545,"url":"https://patchwork.plctlab.org/api/1.2/patches/82545/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230412154444.1741657-1-claziss@gmail.com/","msgid":"<20230412154444.1741657-1-claziss@gmail.com>","list_archive_url":null,"date":"2023-04-12T15:44:44","name":"[committed] arc: remove faulty instructions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230412154444.1741657-1-claziss@gmail.com/mbox/"},{"id":82801,"url":"https://patchwork.plctlab.org/api/1.2/patches/82801/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZDeVznw01giUi/SE@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-04-13T05:40:30","name":"Preserve a few more bfd fields in check_format_matches","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZDeVznw01giUi/SE@squeak.grove.modra.org/mbox/"},{"id":82831,"url":"https://patchwork.plctlab.org/api/1.2/patches/82831/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230413070544.1961068-1-claziss@gmail.com/","msgid":"<20230413070544.1961068-1-claziss@gmail.com>","list_archive_url":null,"date":"2023-04-13T07:05:44","name":"[committed] arc: Update GAS test","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230413070544.1961068-1-claziss@gmail.com/mbox/"},{"id":82839,"url":"https://patchwork.plctlab.org/api/1.2/patches/82839/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230413073144.1973667-1-claziss@gmail.com/","msgid":"<20230413073144.1973667-1-claziss@gmail.com>","list_archive_url":null,"date":"2023-04-13T07:31:44","name":"[committed] arc: Update ARC'\''s CFI tests.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230413073144.1973667-1-claziss@gmail.com/mbox/"},{"id":82843,"url":"https://patchwork.plctlab.org/api/1.2/patches/82843/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230413074914.354662-1-chigot@adacore.com/","msgid":"<20230413074914.354662-1-chigot@adacore.com>","list_archive_url":null,"date":"2023-04-13T07:49:14","name":"ld: build libdep plugin only when shared library support is enabled","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230413074914.354662-1-chigot@adacore.com/mbox/"},{"id":82854,"url":"https://patchwork.plctlab.org/api/1.2/patches/82854/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230413082502.2009382-1-claziss@gmail.com/","msgid":"<20230413082502.2009382-1-claziss@gmail.com>","list_archive_url":null,"date":"2023-04-13T08:25:02","name":"[committed] arc: Update ARC specific linker tests.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230413082502.2009382-1-claziss@gmail.com/mbox/"},{"id":82982,"url":"https://patchwork.plctlab.org/api/1.2/patches/82982/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230413133654.71247-1-christoph.muellner@vrull.eu/","msgid":"<20230413133654.71247-1-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2023-04-13T13:36:54","name":"[RFC,v5] RISC-V: Add support for the Zfa extension","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230413133654.71247-1-christoph.muellner@vrull.eu/mbox/"},{"id":83244,"url":"https://patchwork.plctlab.org/api/1.2/patches/83244/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230414061935.1252692-1-mengqinggang@loongson.cn/","msgid":"<20230414061935.1252692-1-mengqinggang@loongson.cn>","list_archive_url":null,"date":"2023-04-14T06:19:35","name":"Symbols with GOT relocatios do not fix adjustbale","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230414061935.1252692-1-mengqinggang@loongson.cn/mbox/"},{"id":83259,"url":"https://patchwork.plctlab.org/api/1.2/patches/83259/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230414072046.1639896-1-yunqiang.su@cipunited.com/","msgid":"<20230414072046.1639896-1-yunqiang.su@cipunited.com>","list_archive_url":null,"date":"2023-04-14T07:20:46","name":"[v3] MIPS: the default output fellows triple","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230414072046.1639896-1-yunqiang.su@cipunited.com/mbox/"},{"id":83780,"url":"https://patchwork.plctlab.org/api/1.2/patches/83780/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230416005921.3061576-1-vladimir.mezentsev@oracle.com/","msgid":"<20230416005921.3061576-1-vladimir.mezentsev@oracle.com>","list_archive_url":null,"date":"2023-04-16T00:59:21","name":"[Review,is,neded] gprofng: Update documentation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230416005921.3061576-1-vladimir.mezentsev@oracle.com/mbox/"},{"id":83922,"url":"https://patchwork.plctlab.org/api/1.2/patches/83922/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/baf3b8d6-a257-7bc7-5dfa-2a8f578c2c93@netcologne.de/","msgid":"","list_archive_url":null,"date":"2023-04-16T19:47:11","name":"[gas,documentation] Describe handling of opcodes for relaxation a bit better","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/baf3b8d6-a257-7bc7-5dfa-2a8f578c2c93@netcologne.de/mbox/"},{"id":83932,"url":"https://patchwork.plctlab.org/api/1.2/patches/83932/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230416210122.3363899-1-vladimir.mezentsev@oracle.com/","msgid":"<20230416210122.3363899-1-vladimir.mezentsev@oracle.com>","list_archive_url":null,"date":"2023-04-16T21:01:22","name":"[Review,is,neded] gprofng: 30360 Seg. Fault when application uses std::thread","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230416210122.3363899-1-vladimir.mezentsev@oracle.com/mbox/"},{"id":84106,"url":"https://patchwork.plctlab.org/api/1.2/patches/84106/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230417095443.73581-1-nelson@rivosinc.com/","msgid":"<20230417095443.73581-1-nelson@rivosinc.com>","list_archive_url":null,"date":"2023-04-17T09:54:43","name":"RISC-V: Optimize relaxation of gp with max_alignment.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230417095443.73581-1-nelson@rivosinc.com/mbox/"},{"id":84192,"url":"https://patchwork.plctlab.org/api/1.2/patches/84192/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230417121633.68761-1-kito.cheng@sifive.com/","msgid":"<20230417121633.68761-1-kito.cheng@sifive.com>","list_archive_url":null,"date":"2023-04-17T12:16:33","name":"RISC-V: Cache the latest mapping symbol and its boundary.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230417121633.68761-1-kito.cheng@sifive.com/mbox/"},{"id":84514,"url":"https://patchwork.plctlab.org/api/1.2/patches/84514/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZD3xccVokEyi/Cbv@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-04-18T01:25:05","name":"objdump buffer overflow in fetch_indexed_string","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZD3xccVokEyi/Cbv@squeak.grove.modra.org/mbox/"},{"id":84515,"url":"https://patchwork.plctlab.org/api/1.2/patches/84515/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZD3xnwW1LKQe7Oqe@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-04-18T01:25:51","name":"objdump use of uninitialised value in pr_string_field","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZD3xnwW1LKQe7Oqe@squeak.grove.modra.org/mbox/"},{"id":84879,"url":"https://patchwork.plctlab.org/api/1.2/patches/84879/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230418140019.2195551-1-yunqiang.su@cipunited.com/","msgid":"<20230418140019.2195551-1-yunqiang.su@cipunited.com>","list_archive_url":null,"date":"2023-04-18T14:00:18","name":"[v4,1/2] MIPS: support mips*64 as CPU and gnuabi64 as ABI","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230418140019.2195551-1-yunqiang.su@cipunited.com/mbox/"},{"id":84880,"url":"https://patchwork.plctlab.org/api/1.2/patches/84880/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230418140019.2195551-2-yunqiang.su@cipunited.com/","msgid":"<20230418140019.2195551-2-yunqiang.su@cipunited.com>","list_archive_url":null,"date":"2023-04-18T14:00:19","name":"[v4,2/2] MIPS: default output r6 obj if the triple is r6","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230418140019.2195551-2-yunqiang.su@cipunited.com/mbox/"},{"id":84915,"url":"https://patchwork.plctlab.org/api/1.2/patches/84915/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.LSU.2.20.2304181502360.3155@wotan.suse.de/","msgid":"","list_archive_url":null,"date":"2023-04-18T15:12:12","name":"section-select: Fix performance problem (PR30367)","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.LSU.2.20.2304181502360.3155@wotan.suse.de/mbox/"},{"id":85574,"url":"https://patchwork.plctlab.org/api/1.2/patches/85574/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230419221125.502883-2-indu.bhagat@oracle.com/","msgid":"<20230419221125.502883-2-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-04-19T22:11:20","name":"[COMMITTED,1/6] gas: sframe: use ATTRIBUTE_UNUSED consistently","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230419221125.502883-2-indu.bhagat@oracle.com/mbox/"},{"id":85578,"url":"https://patchwork.plctlab.org/api/1.2/patches/85578/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230419221125.502883-3-indu.bhagat@oracle.com/","msgid":"<20230419221125.502883-3-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-04-19T22:11:21","name":"[COMMITTED,2/6] gas: sframe: fix comment","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230419221125.502883-3-indu.bhagat@oracle.com/mbox/"},{"id":85575,"url":"https://patchwork.plctlab.org/api/1.2/patches/85575/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230419221125.502883-4-indu.bhagat@oracle.com/","msgid":"<20230419221125.502883-4-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-04-19T22:11:22","name":"[COMMITTED,3/6] libsframe: use return type of bool for predicate functions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230419221125.502883-4-indu.bhagat@oracle.com/mbox/"},{"id":85577,"url":"https://patchwork.plctlab.org/api/1.2/patches/85577/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230419221125.502883-5-indu.bhagat@oracle.com/","msgid":"<20230419221125.502883-5-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-04-19T22:11:23","name":"[COMMITTED,4/6] sframe: correct some typos","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230419221125.502883-5-indu.bhagat@oracle.com/mbox/"},{"id":85576,"url":"https://patchwork.plctlab.org/api/1.2/patches/85576/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230419221125.502883-6-indu.bhagat@oracle.com/","msgid":"<20230419221125.502883-6-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-04-19T22:11:24","name":"[COMMITTED,5/6] libsframe: use consistent function argument names","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230419221125.502883-6-indu.bhagat@oracle.com/mbox/"},{"id":85579,"url":"https://patchwork.plctlab.org/api/1.2/patches/85579/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230419221125.502883-7-indu.bhagat@oracle.com/","msgid":"<20230419221125.502883-7-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-04-19T22:11:25","name":"[COMMITTED,6/6] libsframe: minor formatting fixes in sframe_encoder_write_fre","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230419221125.502883-7-indu.bhagat@oracle.com/mbox/"},{"id":85638,"url":"https://patchwork.plctlab.org/api/1.2/patches/85638/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZEBzqwgJEiqZ3AaD@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-04-19T23:05:15","name":"buffer overflow in print_symname","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZEBzqwgJEiqZ3AaD@squeak.grove.modra.org/mbox/"},{"id":85639,"url":"https://patchwork.plctlab.org/api/1.2/patches/85639/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZEB0Nkp//9ZWvzA4@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-04-19T23:07:34","name":"Yet another out-of-memory fuzzed object","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZEB0Nkp//9ZWvzA4@squeak.grove.modra.org/mbox/"},{"id":85640,"url":"https://patchwork.plctlab.org/api/1.2/patches/85640/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZEB0XGn82KUoFAth@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-04-19T23:08:12","name":"ubsan: signed integer overflow in display_debug_lines_raw","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZEB0XGn82KUoFAth@squeak.grove.modra.org/mbox/"},{"id":85641,"url":"https://patchwork.plctlab.org/api/1.2/patches/85641/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZEB0yrc7sb7PgfVj@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-04-19T23:10:02","name":"PR30343 infrastructure","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZEB0yrc7sb7PgfVj@squeak.grove.modra.org/mbox/"},{"id":85642,"url":"https://patchwork.plctlab.org/api/1.2/patches/85642/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZEB1FHCdkVcnkby8@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-04-19T23:11:16","name":"sh4-linux segfaults running ld testsuite","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZEB1FHCdkVcnkby8@squeak.grove.modra.org/mbox/"},{"id":85912,"url":"https://patchwork.plctlab.org/api/1.2/patches/85912/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230420133102.2422583-1-yunqiang.su@cipunited.com/","msgid":"<20230420133102.2422583-1-yunqiang.su@cipunited.com>","list_archive_url":null,"date":"2023-04-20T13:31:01","name":"[v5,1/2] MIPS: support mips*64 as CPU and gnuabi64 as ABI","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230420133102.2422583-1-yunqiang.su@cipunited.com/mbox/"},{"id":85913,"url":"https://patchwork.plctlab.org/api/1.2/patches/85913/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230420133102.2422583-2-yunqiang.su@cipunited.com/","msgid":"<20230420133102.2422583-2-yunqiang.su@cipunited.com>","list_archive_url":null,"date":"2023-04-20T13:31:02","name":"[v5,2/2] MIPS: default output r6 obj if the triple is r6","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230420133102.2422583-2-yunqiang.su@cipunited.com/mbox/"},{"id":86103,"url":"https://patchwork.plctlab.org/api/1.2/patches/86103/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZEH3P5K8BQ4euUsQ@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-04-21T02:38:55","name":"Delete struct artdata archive_head","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZEH3P5K8BQ4euUsQ@squeak.grove.modra.org/mbox/"},{"id":86104,"url":"https://patchwork.plctlab.org/api/1.2/patches/86104/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZEH5tX5D6VSOFPit@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-04-21T02:49:25","name":"Keeping track of rs6000-coff archive element pointers","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZEH5tX5D6VSOFPit@squeak.grove.modra.org/mbox/"},{"id":86139,"url":"https://patchwork.plctlab.org/api/1.2/patches/86139/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/72cd2df6-f7dd-9217-aa03-e218631c879e@suse.com/","msgid":"<72cd2df6-f7dd-9217-aa03-e218631c879e@suse.com>","list_archive_url":null,"date":"2023-04-21T05:53:28","name":"ld: add missing period after @xref","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/72cd2df6-f7dd-9217-aa03-e218631c879e@suse.com/mbox/"},{"id":86171,"url":"https://patchwork.plctlab.org/api/1.2/patches/86171/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230421082839.41542-1-nelson@rivosinc.com/","msgid":"<20230421082839.41542-1-nelson@rivosinc.com>","list_archive_url":null,"date":"2023-04-21T08:28:38","name":"[1/2] RISC-V: Relax R_RISCV_[PCREL_]LO12_I/S to R_RISCV_GPREL_I/S for undefined weak.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230421082839.41542-1-nelson@rivosinc.com/mbox/"},{"id":86170,"url":"https://patchwork.plctlab.org/api/1.2/patches/86170/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230421082839.41542-2-nelson@rivosinc.com/","msgid":"<20230421082839.41542-2-nelson@rivosinc.com>","list_archive_url":null,"date":"2023-04-21T08:28:39","name":"[2/2] RISC-V: Enable x0 base relaxation for relax_pc even if --no-relax-gp.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230421082839.41542-2-nelson@rivosinc.com/mbox/"},{"id":86203,"url":"https://patchwork.plctlab.org/api/1.2/patches/86203/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230421094346.3017667-1-mengqinggang@loongson.cn/","msgid":"<20230421094346.3017667-1-mengqinggang@loongson.cn>","list_archive_url":null,"date":"2023-04-21T09:43:46","name":"LoongArch: Fix loongarch32 test fails","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230421094346.3017667-1-mengqinggang@loongson.cn/mbox/"},{"id":86214,"url":"https://patchwork.plctlab.org/api/1.2/patches/86214/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f339bf78-9ba2-594b-3dec-232edb0e7f70@suse.com/","msgid":"","list_archive_url":null,"date":"2023-04-21T10:05:16","name":"bfd: fix STRICT_PE_FORMAT build","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f339bf78-9ba2-594b-3dec-232edb0e7f70@suse.com/mbox/"},{"id":86221,"url":"https://patchwork.plctlab.org/api/1.2/patches/86221/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0ece83ad-f7a0-7951-374b-2c86cbafad36@suse.com/","msgid":"<0ece83ad-f7a0-7951-374b-2c86cbafad36@suse.com>","list_archive_url":null,"date":"2023-04-21T10:16:23","name":"[1/2] x86: rework AMX multiplication insn disassembly","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0ece83ad-f7a0-7951-374b-2c86cbafad36@suse.com/mbox/"},{"id":86222,"url":"https://patchwork.plctlab.org/api/1.2/patches/86222/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/657c81bd-2182-c663-04a4-c5e6962531ea@suse.com/","msgid":"<657c81bd-2182-c663-04a4-c5e6962531ea@suse.com>","list_archive_url":null,"date":"2023-04-21T10:16:59","name":"[2/2] x86: rework AMX control insn disassembly","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/657c81bd-2182-c663-04a4-c5e6962531ea@suse.com/mbox/"},{"id":86240,"url":"https://patchwork.plctlab.org/api/1.2/patches/86240/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/335d1933-a5dc-9183-cbe7-d8b139e232fc@suse.com/","msgid":"<335d1933-a5dc-9183-cbe7-d8b139e232fc@suse.com>","list_archive_url":null,"date":"2023-04-21T10:26:15","name":"gas: move shift count check","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/335d1933-a5dc-9183-cbe7-d8b139e232fc@suse.com/mbox/"},{"id":86274,"url":"https://patchwork.plctlab.org/api/1.2/patches/86274/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4c40b0d1-8375-9284-cfaf-ce63b8df1b9b@suse.com/","msgid":"<4c40b0d1-8375-9284-cfaf-ce63b8df1b9b@suse.com>","list_archive_url":null,"date":"2023-04-21T12:17:54","name":"gas: equates of registers","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4c40b0d1-8375-9284-cfaf-ce63b8df1b9b@suse.com/mbox/"},{"id":86301,"url":"https://patchwork.plctlab.org/api/1.2/patches/86301/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230421130802.2964785-1-tromey@adacore.com/","msgid":"<20230421130802.2964785-1-tromey@adacore.com>","list_archive_url":null,"date":"2023-04-21T13:08:02","name":"Fix -Wmaybe-uninitialized warning in opcodes/i386-dis.c","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230421130802.2964785-1-tromey@adacore.com/mbox/"},{"id":86651,"url":"https://patchwork.plctlab.org/api/1.2/patches/86651/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230423015546.2664272-1-mengqinggang@loongson.cn/","msgid":"<20230423015546.2664272-1-mengqinggang@loongson.cn>","list_archive_url":null,"date":"2023-04-23T01:55:46","name":"[v1] LoongArch: Fix loongarch32 test fails","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230423015546.2664272-1-mengqinggang@loongson.cn/mbox/"},{"id":86786,"url":"https://patchwork.plctlab.org/api/1.2/patches/86786/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230423173021.582102-1-och95@yandex.ru/","msgid":"<20230423173021.582102-1-och95@yandex.ru>","list_archive_url":null,"date":"2023-04-23T17:30:21","name":"Fix emit-relocs for aarch64 gold","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230423173021.582102-1-och95@yandex.ru/mbox/"},{"id":86885,"url":"https://patchwork.plctlab.org/api/1.2/patches/86885/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a475270f-97f0-4fc7-bd0c-eb99bd8b2b3c@suse.com/","msgid":"","list_archive_url":null,"date":"2023-04-24T07:34:27","name":"[1/3] x86: work around compiler diagnosing dangling pointer","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a475270f-97f0-4fc7-bd0c-eb99bd8b2b3c@suse.com/mbox/"},{"id":86886,"url":"https://patchwork.plctlab.org/api/1.2/patches/86886/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c26e2fcd-62aa-98f3-1b62-0c53ce7d16a5@suse.com/","msgid":"","list_archive_url":null,"date":"2023-04-24T07:35:05","name":"[2/3] x86: limit data passed to prefix_name()","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c26e2fcd-62aa-98f3-1b62-0c53ce7d16a5@suse.com/mbox/"},{"id":86887,"url":"https://patchwork.plctlab.org/api/1.2/patches/86887/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b3511736-584c-6c99-9046-331a18c60417@suse.com/","msgid":"","list_archive_url":null,"date":"2023-04-24T07:35:28","name":"[3/3] x86: limit data passed to i386_dis_printf()","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b3511736-584c-6c99-9046-331a18c60417@suse.com/mbox/"},{"id":86999,"url":"https://patchwork.plctlab.org/api/1.2/patches/86999/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZEZoqCKm+ebNL+I7@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-04-24T11:31:52","name":"objcopy of archives tidy","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZEZoqCKm+ebNL+I7@squeak.grove.modra.org/mbox/"},{"id":87000,"url":"https://patchwork.plctlab.org/api/1.2/patches/87000/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZEZo4oH/oT6Gu/5S@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-04-24T11:32:50","name":"asan: segfault in coff_mangle_symbols","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZEZo4oH/oT6Gu/5S@squeak.grove.modra.org/mbox/"},{"id":87259,"url":"https://patchwork.plctlab.org/api/1.2/patches/87259/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230425065626.3587754-1-yunqiang.su@cipunited.com/","msgid":"<20230425065626.3587754-1-yunqiang.su@cipunited.com>","list_archive_url":null,"date":"2023-04-25T06:56:26","name":"MIPS: add MT ASE support for micromips32","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230425065626.3587754-1-yunqiang.su@cipunited.com/mbox/"},{"id":87491,"url":"https://patchwork.plctlab.org/api/1.2/patches/87491/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/CACcXsZjbOetUzc5MOhWFJbqkkhuurqcDD7faHs9PJjM02Be9TA@mail.gmail.com/","msgid":"","list_archive_url":null,"date":"2023-04-25T16:48:11","name":"optimize handle_COMDAT","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/CACcXsZjbOetUzc5MOhWFJbqkkhuurqcDD7faHs9PJjM02Be9TA@mail.gmail.com/mbox/"},{"id":87591,"url":"https://patchwork.plctlab.org/api/1.2/patches/87591/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZEiNgqU+7bX6pfwL@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-04-26T02:33:38","name":"Avoid another -Werror=dangling-pointer","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZEiNgqU+7bX6pfwL@squeak.grove.modra.org/mbox/"},{"id":87592,"url":"https://patchwork.plctlab.org/api/1.2/patches/87592/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZEiN3mQ74ldcG/+R@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-04-26T02:35:10","name":"binutils runtest $CC","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZEiN3mQ74ldcG/+R@squeak.grove.modra.org/mbox/"},{"id":87598,"url":"https://patchwork.plctlab.org/api/1.2/patches/87598/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZEirEhA/zSf9YWhh@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-04-26T04:39:46","name":"i386-dis.c UB shift and other tidies","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZEirEhA/zSf9YWhh@squeak.grove.modra.org/mbox/"},{"id":87791,"url":"https://patchwork.plctlab.org/api/1.2/patches/87791/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230426101640.264902-1-yunqiang.su@cipunited.com/","msgid":"<20230426101640.264902-1-yunqiang.su@cipunited.com>","list_archive_url":null,"date":"2023-04-26T10:16:39","name":"[v2,1/2] MIPS: add MT ASE support for micromips32","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230426101640.264902-1-yunqiang.su@cipunited.com/mbox/"},{"id":87792,"url":"https://patchwork.plctlab.org/api/1.2/patches/87792/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230426101640.264902-2-yunqiang.su@cipunited.com/","msgid":"<20230426101640.264902-2-yunqiang.su@cipunited.com>","list_archive_url":null,"date":"2023-04-26T10:16:40","name":"[v2,2/2] MIPS: sync oprand char usage between mips and micromips","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230426101640.264902-2-yunqiang.su@cipunited.com/mbox/"},{"id":87865,"url":"https://patchwork.plctlab.org/api/1.2/patches/87865/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5aebce50-8b8a-26ee-b452-d9164668c145@suse.com/","msgid":"<5aebce50-8b8a-26ee-b452-d9164668c145@suse.com>","list_archive_url":null,"date":"2023-04-26T13:15:38","name":"x86/Intel: reduce ELF/PE conditional scope in x86_cons()","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5aebce50-8b8a-26ee-b452-d9164668c145@suse.com/mbox/"},{"id":87876,"url":"https://patchwork.plctlab.org/api/1.2/patches/87876/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.LSU.2.20.2304261416140.3155@wotan.suse.de/","msgid":"","list_archive_url":null,"date":"2023-04-26T14:16:55","name":"Fix PR30358, performance with --sort-section","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.LSU.2.20.2304261416140.3155@wotan.suse.de/mbox/"},{"id":87921,"url":"https://patchwork.plctlab.org/api/1.2/patches/87921/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230426173123.24564-1-jose.marchesi@oracle.com/","msgid":"<20230426173123.24564-1-jose.marchesi@oracle.com>","list_archive_url":null,"date":"2023-04-26T17:31:21","name":"[COMMITTED,1/3] gas: support for the BPF pseudo-c assembly syntax","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230426173123.24564-1-jose.marchesi@oracle.com/mbox/"},{"id":87924,"url":"https://patchwork.plctlab.org/api/1.2/patches/87924/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230426173123.24564-2-jose.marchesi@oracle.com/","msgid":"<20230426173123.24564-2-jose.marchesi@oracle.com>","list_archive_url":null,"date":"2023-04-26T17:31:22","name":"[COMMITTED,2/3] gas: BPF pseudo-c syntax tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230426173123.24564-2-jose.marchesi@oracle.com/mbox/"},{"id":87922,"url":"https://patchwork.plctlab.org/api/1.2/patches/87922/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230426173123.24564-3-jose.marchesi@oracle.com/","msgid":"<20230426173123.24564-3-jose.marchesi@oracle.com>","list_archive_url":null,"date":"2023-04-26T17:31:23","name":"[COMMITTED,3/3] gas: documentation for the BPF pseudo-c asm syntax","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230426173123.24564-3-jose.marchesi@oracle.com/mbox/"},{"id":87976,"url":"https://patchwork.plctlab.org/api/1.2/patches/87976/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9b903d19-c4b7-40a3-dce0-84d36e4ff32c@ventanamicro.com/","msgid":"<9b903d19-c4b7-40a3-dce0-84d36e4ff32c@ventanamicro.com>","list_archive_url":null,"date":"2023-04-26T20:28:40","name":"[committed] RISC-V: XVentanaCondops support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9b903d19-c4b7-40a3-dce0-84d36e4ff32c@ventanamicro.com/mbox/"},{"id":88220,"url":"https://patchwork.plctlab.org/api/1.2/patches/88220/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/87354lr0sz.fsf@redhat.com/","msgid":"<87354lr0sz.fsf@redhat.com>","list_archive_url":null,"date":"2023-04-27T12:01:48","name":"Commit: ld: Add ability to print hex values in the linker map","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/87354lr0sz.fsf@redhat.com/mbox/"},{"id":88258,"url":"https://patchwork.plctlab.org/api/1.2/patches/88258/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230427125607.362035-1-iii@linux.ibm.com/","msgid":"<20230427125607.362035-1-iii@linux.ibm.com>","list_archive_url":null,"date":"2023-04-27T12:56:07","name":"gas: fix building tc-bpf.c on s390x","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230427125607.362035-1-iii@linux.ibm.com/mbox/"},{"id":88359,"url":"https://patchwork.plctlab.org/api/1.2/patches/88359/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/CACcXsZjzrLPP5Ngo2bt20hkCQF+uvZ2syNvz5rW-bha_mDTfQw@mail.gmail.com/","msgid":"","list_archive_url":null,"date":"2023-04-27T18:24:48","name":"make coff_compute_checksum faster","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/CACcXsZjzrLPP5Ngo2bt20hkCQF+uvZ2syNvz5rW-bha_mDTfQw@mail.gmail.com/mbox/"},{"id":88408,"url":"https://patchwork.plctlab.org/api/1.2/patches/88408/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/CACcXsZi9c641-gEbCZbP0=Ni+sJKbEwW3gV6CMpT4wOjks85dg@mail.gmail.com/","msgid":"","list_archive_url":null,"date":"2023-04-27T23:35:20","name":"make ar faster","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/CACcXsZi9c641-gEbCZbP0=Ni+sJKbEwW3gV6CMpT4wOjks85dg@mail.gmail.com/mbox/"},{"id":88459,"url":"https://patchwork.plctlab.org/api/1.2/patches/88459/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZEtkW7ozVq5sX1e8@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-04-28T06:14:51","name":"Make bfd_byte an int8_t, flagword a uint32_t","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZEtkW7ozVq5sX1e8@squeak.grove.modra.org/mbox/"},{"id":88460,"url":"https://patchwork.plctlab.org/api/1.2/patches/88460/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZEtkeBiugmBcY34m@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-04-28T06:15:20","name":"Remove deprecated bfd_read","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZEtkeBiugmBcY34m@squeak.grove.modra.org/mbox/"},{"id":88639,"url":"https://patchwork.plctlab.org/api/1.2/patches/88639/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e1da592f-5c5b-418b-a25b-afeeb0691ea7@suse.com/","msgid":"","list_archive_url":null,"date":"2023-04-28T12:57:30","name":"RISC-V: tighten post-relocation-operator separator expectation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e1da592f-5c5b-418b-a25b-afeeb0691ea7@suse.com/mbox/"},{"id":88872,"url":"https://patchwork.plctlab.org/api/1.2/patches/88872/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/CACcXsZjWfeQR3_pC3nVtq+sAkq-QGfEnA3DE2K8rsDnK9edWrQ@mail.gmail.com/","msgid":"","list_archive_url":null,"date":"2023-04-29T11:19:26","name":"add section caches to coff_data_type","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/CACcXsZjWfeQR3_pC3nVtq+sAkq-QGfEnA3DE2K8rsDnK9edWrQ@mail.gmail.com/mbox/"},{"id":88907,"url":"https://patchwork.plctlab.org/api/1.2/patches/88907/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/541a3fba-3b07-d4e3-f913-f10d7163a59e@netcologne.de/","msgid":"<541a3fba-3b07-d4e3-f913-f10d7163a59e@netcologne.de>","list_archive_url":null,"date":"2023-04-30T10:16:23","name":"[gas,documentation] Some additional testsuite info","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/541a3fba-3b07-d4e3-f913-f10d7163a59e@netcologne.de/mbox/"}],"public":true,"mbox":"https://patchwork.plctlab.org/bundle/patchwork-bot/binutils-gdb_2023-04/mbox/"},{"id":22,"url":"https://patchwork.plctlab.org/api/1.2/bundles/22/","web_url":"https://patchwork.plctlab.org/bundle/patchwork-bot/binutils-gdb_2023-05/","project":{"id":2,"url":"https://patchwork.plctlab.org/api/1.2/projects/2/","name":"binutils-gdb","link_name":"binutils-gdb","list_id":"binutils.sourceware.org","list_email":"binutils@sourceware.org","web_url":"https://github.com/wangliu-iscas/Patchwork-Bundles/blob/main/binutils-gdb.md","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"name":"binutils-gdb_2023-05","owner":{"id":3,"url":"https://patchwork.plctlab.org/api/1.2/users/3/","username":"patchwork-bot","first_name":"","last_name":"","email":"ouuuleilei@gmail.com"},"patches":[{"id":89293,"url":"https://patchwork.plctlab.org/api/1.2/patches/89293/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3a7b6bb3-4ab0-15af-0c74-5d7798ac3793@suse.com/","msgid":"<3a7b6bb3-4ab0-15af-0c74-5d7798ac3793@suse.com>","list_archive_url":null,"date":"2023-05-02T09:04:28","name":"[v2] gas: equates of registers","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3a7b6bb3-4ab0-15af-0c74-5d7798ac3793@suse.com/mbox/"},{"id":89429,"url":"https://patchwork.plctlab.org/api/1.2/patches/89429/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3cdc56a8-62eb-d33c-3038-0af00d8a52ba@codesourcery.com/","msgid":"<3cdc56a8-62eb-d33c-3038-0af00d8a52ba@codesourcery.com>","list_archive_url":null,"date":"2023-05-02T17:19:14","name":"[RFC] Linker plugin - extend API for offloading corner case (aka: LDPT_REGISTER_CLAIM_FILE_HOOK_V2 linker plugin hook [GCC PR109128])","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3cdc56a8-62eb-d33c-3038-0af00d8a52ba@codesourcery.com/mbox/"},{"id":89523,"url":"https://patchwork.plctlab.org/api/1.2/patches/89523/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZFGkCFaFJysW0kh1@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-05-03T00:00:08","name":"_bfd_mips_elf_lo16_reloc vallo comment","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZFGkCFaFJysW0kh1@squeak.grove.modra.org/mbox/"},{"id":89569,"url":"https://patchwork.plctlab.org/api/1.2/patches/89569/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZFH4p/bxWZOU/b70@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-05-03T06:01:11","name":"Change signature of bfd crc functions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZFH4p/bxWZOU/b70@squeak.grove.modra.org/mbox/"},{"id":89570,"url":"https://patchwork.plctlab.org/api/1.2/patches/89570/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZFH4xh+ePb7tKT7Q@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-05-03T06:01:42","name":"libbfc.c: Use stdint types for unsigned char and unsigned long","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZFH4xh+ePb7tKT7Q@squeak.grove.modra.org/mbox/"},{"id":89571,"url":"https://patchwork.plctlab.org/api/1.2/patches/89571/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZFH44S/nfshKLrn9@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-05-03T06:02:09","name":"hash.c: replace some unsigned long with unsigned int","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZFH44S/nfshKLrn9@squeak.grove.modra.org/mbox/"},{"id":89572,"url":"https://patchwork.plctlab.org/api/1.2/patches/89572/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZFH5CJb/dZFBG9hD@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-05-03T06:02:48","name":"Move bfd_elf_bfd_from_remote_memory to opncls.c","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZFH5CJb/dZFBG9hD@squeak.grove.modra.org/mbox/"},{"id":89573,"url":"https://patchwork.plctlab.org/api/1.2/patches/89573/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZFH5Jt7SVTKp0rvP@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-05-03T06:03:18","name":"Move bfd_alloc, bfd_zalloc and bfd_release to libbfd.c","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZFH5Jt7SVTKp0rvP@squeak.grove.modra.org/mbox/"},{"id":89574,"url":"https://patchwork.plctlab.org/api/1.2/patches/89574/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZFH5gcFv4YXk03OL@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-05-03T06:04:49","name":"Generated docs and include files","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZFH5gcFv4YXk03OL@squeak.grove.modra.org/mbox/"},{"id":89577,"url":"https://patchwork.plctlab.org/api/1.2/patches/89577/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZFIAiF82oU/87le9@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-05-03T06:34:48","name":"Remove unused args from bfd_make_debug_symbol","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZFIAiF82oU/87le9@squeak.grove.modra.org/mbox/"},{"id":89732,"url":"https://patchwork.plctlab.org/api/1.2/patches/89732/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230503120210.564966-1-iii@linux.ibm.com/","msgid":"<20230503120210.564966-1-iii@linux.ibm.com>","list_archive_url":null,"date":"2023-05-03T12:02:10","name":"[v2] gas: fix building tc-bpf.c on s390x","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230503120210.564966-1-iii@linux.ibm.com/mbox/"},{"id":89794,"url":"https://patchwork.plctlab.org/api/1.2/patches/89794/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230503171124.6710-1-dimitar@dinux.eu/","msgid":"<20230503171124.6710-1-dimitar@dinux.eu>","list_archive_url":null,"date":"2023-05-03T17:11:24","name":"ld: pru: Place exception-handling sections correctly","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230503171124.6710-1-dimitar@dinux.eu/mbox/"},{"id":89976,"url":"https://patchwork.plctlab.org/api/1.2/patches/89976/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230504081452.50748-1-nelson@rivosinc.com/","msgid":"<20230504081452.50748-1-nelson@rivosinc.com>","list_archive_url":null,"date":"2023-05-04T08:14:52","name":"RISC-V: Minor improvements for dis-assembler.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230504081452.50748-1-nelson@rivosinc.com/mbox/"},{"id":90003,"url":"https://patchwork.plctlab.org/api/1.2/patches/90003/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230504090850.91004-1-nelson@rivosinc.com/","msgid":"<20230504090850.91004-1-nelson@rivosinc.com>","list_archive_url":null,"date":"2023-05-04T09:08:50","name":"[PR,ld/22263,PR,ld/25694] RISC-V: Avoid dynamic TLS relocs in PIE.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230504090850.91004-1-nelson@rivosinc.com/mbox/"},{"id":90380,"url":"https://patchwork.plctlab.org/api/1.2/patches/90380/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230505092316.1046472-1-aleksandar.rikalo@syrmia.com/","msgid":"<20230505092316.1046472-1-aleksandar.rikalo@syrmia.com>","list_archive_url":null,"date":"2023-05-05T09:23:16","name":"[v5] Add support for nanoMIPS architecture","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230505092316.1046472-1-aleksandar.rikalo@syrmia.com/mbox/"},{"id":90383,"url":"https://patchwork.plctlab.org/api/1.2/patches/90383/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230505092716.885338-1-yunqiang.su@cipunited.com/","msgid":"<20230505092716.885338-1-yunqiang.su@cipunited.com>","list_archive_url":null,"date":"2023-05-05T09:27:16","name":"gas: documents .gnu_attribute Tag_GNU_MIPS_ABI_MSA","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230505092716.885338-1-yunqiang.su@cipunited.com/mbox/"},{"id":90408,"url":"https://patchwork.plctlab.org/api/1.2/patches/90408/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a63ab9f1-6150-1948-c6e2-6a77855155e6@suse.com/","msgid":"","list_archive_url":null,"date":"2023-05-05T11:10:21","name":"x86: slightly simplify i386_parse_name()","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a63ab9f1-6150-1948-c6e2-6a77855155e6@suse.com/mbox/"},{"id":90410,"url":"https://patchwork.plctlab.org/api/1.2/patches/90410/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/52d14c6e-e232-efe3-d486-06cda1c19fdf@suse.com/","msgid":"<52d14c6e-e232-efe3-d486-06cda1c19fdf@suse.com>","list_archive_url":null,"date":"2023-05-05T11:12:44","name":"[1/2] x86: move get() disassembler helper functions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/52d14c6e-e232-efe3-d486-06cda1c19fdf@suse.com/mbox/"},{"id":90411,"url":"https://patchwork.plctlab.org/api/1.2/patches/90411/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/666d8c60-5ffe-a307-f260-0c4bbd674887@suse.com/","msgid":"<666d8c60-5ffe-a307-f260-0c4bbd674887@suse.com>","list_archive_url":null,"date":"2023-05-05T11:13:10","name":"[2/2] x86: move a few more disassembler helper functions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/666d8c60-5ffe-a307-f260-0c4bbd674887@suse.com/mbox/"},{"id":90430,"url":"https://patchwork.plctlab.org/api/1.2/patches/90430/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4735d366-fe31-0092-2edc-d166184b8567@suse.com/","msgid":"<4735d366-fe31-0092-2edc-d166184b8567@suse.com>","list_archive_url":null,"date":"2023-05-05T12:51:05","name":"[1/2] x86: don'\''t recognize quoted symbol names as registers or operators","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4735d366-fe31-0092-2edc-d166184b8567@suse.com/mbox/"},{"id":90431,"url":"https://patchwork.plctlab.org/api/1.2/patches/90431/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9d0f914a-5668-a09b-5993-16a2270cf059@suse.com/","msgid":"<9d0f914a-5668-a09b-5993-16a2270cf059@suse.com>","list_archive_url":null,"date":"2023-05-05T12:52:02","name":"[2/2] x86/Intel: address quoted-symbol related FIXMEs","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9d0f914a-5668-a09b-5993-16a2270cf059@suse.com/mbox/"},{"id":90432,"url":"https://patchwork.plctlab.org/api/1.2/patches/90432/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/168dfa6e-63d2-06d5-49d5-4d7a1797efb4@suse.com/","msgid":"<168dfa6e-63d2-06d5-49d5-4d7a1797efb4@suse.com>","list_archive_url":null,"date":"2023-05-05T13:01:10","name":"[1/4] x86: tighten extend-to-32bit-address conditions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/168dfa6e-63d2-06d5-49d5-4d7a1797efb4@suse.com/mbox/"},{"id":90434,"url":"https://patchwork.plctlab.org/api/1.2/patches/90434/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/905e0a5d-d49d-03a6-d441-302bc5c2da6a@suse.com/","msgid":"<905e0a5d-d49d-03a6-d441-302bc5c2da6a@suse.com>","list_archive_url":null,"date":"2023-05-05T13:01:57","name":"[2/4] gas: maintain O_constant signedness in more cases","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/905e0a5d-d49d-03a6-d441-302bc5c2da6a@suse.com/mbox/"},{"id":90435,"url":"https://patchwork.plctlab.org/api/1.2/patches/90435/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a766b568-5192-9660-34cd-2df6415a85c4@suse.com/","msgid":"","list_archive_url":null,"date":"2023-05-05T13:03:57","name":"[3/4] gas: invoke md_optimize_expr() also for unary expressions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a766b568-5192-9660-34cd-2df6415a85c4@suse.com/mbox/"},{"id":90436,"url":"https://patchwork.plctlab.org/api/1.2/patches/90436/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4f7d2d8d-d4fd-a799-9c8f-7a955a786d60@suse.com/","msgid":"<4f7d2d8d-d4fd-a799-9c8f-7a955a786d60@suse.com>","list_archive_url":null,"date":"2023-05-05T13:04:37","name":"[4/4] x86: further adjust extend-to-32bit-address conditions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4f7d2d8d-d4fd-a799-9c8f-7a955a786d60@suse.com/mbox/"},{"id":90707,"url":"https://patchwork.plctlab.org/api/1.2/patches/90707/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230506083718.3669965-1-yunqiang.su@cipunited.com/","msgid":"<20230506083718.3669965-1-yunqiang.su@cipunited.com>","list_archive_url":null,"date":"2023-05-06T08:37:18","name":"MIPS: gas: alter 64 or 32 for r6 triples if march is implicit","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230506083718.3669965-1-yunqiang.su@cipunited.com/mbox/"},{"id":90756,"url":"https://patchwork.plctlab.org/api/1.2/patches/90756/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/OS3P286MB2152C5D5037E18A71DEBF80BF0739@OS3P286MB2152.JPNP286.PROD.OUTLOOK.COM/","msgid":"","list_archive_url":null,"date":"2023-05-06T13:11:56","name":"Fix a typo in the README of binutils","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/OS3P286MB2152C5D5037E18A71DEBF80BF0739@OS3P286MB2152.JPNP286.PROD.OUTLOOK.COM/mbox/"},{"id":90933,"url":"https://patchwork.plctlab.org/api/1.2/patches/90933/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZFh73WJCS1aujdsO@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-05-08T04:34:37","name":"PR30343, LTO ignores linker reference to _pei386_runtime_relocator","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZFh73WJCS1aujdsO@squeak.grove.modra.org/mbox/"},{"id":90934,"url":"https://patchwork.plctlab.org/api/1.2/patches/90934/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZFh8AXXazWkP9+0w@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-05-08T04:35:13","name":"pe.em and pep.em make_import_fixup","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZFh8AXXazWkP9+0w@squeak.grove.modra.org/mbox/"},{"id":91322,"url":"https://patchwork.plctlab.org/api/1.2/patches/91322/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230509003247.24156-1-mark@harmstone.com/","msgid":"<20230509003247.24156-1-mark@harmstone.com>","list_archive_url":null,"date":"2023-05-09T00:32:46","name":"[1/2] pdb: Allow loading by gdb","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230509003247.24156-1-mark@harmstone.com/mbox/"},{"id":91323,"url":"https://patchwork.plctlab.org/api/1.2/patches/91323/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230509003247.24156-2-mark@harmstone.com/","msgid":"<20230509003247.24156-2-mark@harmstone.com>","list_archive_url":null,"date":"2023-05-09T00:32:47","name":"[2/2] gdb: Allow reading of enum definitions in PDB files","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230509003247.24156-2-mark@harmstone.com/mbox/"},{"id":91360,"url":"https://patchwork.plctlab.org/api/1.2/patches/91360/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZFnEez0cjGviUx4M@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-05-09T03:56:43","name":"alpha-vms reloc sanity check","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZFnEez0cjGviUx4M@squeak.grove.modra.org/mbox/"},{"id":91405,"url":"https://patchwork.plctlab.org/api/1.2/patches/91405/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZFn66p7K1lW/yNEL@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-05-09T07:48:58","name":"stack overflow in debug_write_type","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZFn66p7K1lW/yNEL@squeak.grove.modra.org/mbox/"},{"id":92148,"url":"https://patchwork.plctlab.org/api/1.2/patches/92148/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.LSU.2.20.2305101400000.13548@wotan.suse.de/","msgid":"","list_archive_url":null,"date":"2023-05-10T14:04:27","name":"PR30437 aarch64: make RELA relocs idempotent","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.LSU.2.20.2305101400000.13548@wotan.suse.de/mbox/"},{"id":92153,"url":"https://patchwork.plctlab.org/api/1.2/patches/92153/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230510141829.2748105-2-aleksandar.rikalo@syrmia.com/","msgid":"<20230510141829.2748105-2-aleksandar.rikalo@syrmia.com>","list_archive_url":null,"date":"2023-05-10T14:18:27","name":"[v6,1/3] BFD changes for nanoMIPS support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230510141829.2748105-2-aleksandar.rikalo@syrmia.com/mbox/"},{"id":92154,"url":"https://patchwork.plctlab.org/api/1.2/patches/92154/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230510141829.2748105-3-aleksandar.rikalo@syrmia.com/","msgid":"<20230510141829.2748105-3-aleksandar.rikalo@syrmia.com>","list_archive_url":null,"date":"2023-05-10T14:18:28","name":"[v6,2/3] Opcodes changes for nanoMIPS support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230510141829.2748105-3-aleksandar.rikalo@syrmia.com/mbox/"},{"id":92152,"url":"https://patchwork.plctlab.org/api/1.2/patches/92152/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230510141829.2748105-4-aleksandar.rikalo@syrmia.com/","msgid":"<20230510141829.2748105-4-aleksandar.rikalo@syrmia.com>","list_archive_url":null,"date":"2023-05-10T14:18:29","name":"[v6,3/3] Readelf for nanoMIPS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230510141829.2748105-4-aleksandar.rikalo@syrmia.com/mbox/"},{"id":92359,"url":"https://patchwork.plctlab.org/api/1.2/patches/92359/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/243D0799-E3D0-4938-A438-DD8725593F67@free.fr/","msgid":"<243D0799-E3D0-4938-A438-DD8725593F67@free.fr>","list_archive_url":null,"date":"2023-05-11T05:28:58","name":"pe/coff - add support for base64 encoded long section names","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/243D0799-E3D0-4938-A438-DD8725593F67@free.fr/mbox/"},{"id":92467,"url":"https://patchwork.plctlab.org/api/1.2/patches/92467/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230511100354.3995358-1-mengqinggang@loongson.cn/","msgid":"<20230511100354.3995358-1-mengqinggang@loongson.cn>","list_archive_url":null,"date":"2023-05-11T10:03:54","name":"LoongArch: Fix PLT entry generate bug","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230511100354.3995358-1-mengqinggang@loongson.cn/mbox/"},{"id":92629,"url":"https://patchwork.plctlab.org/api/1.2/patches/92629/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230511141351.18886-2-jose.marchesi@oracle.com/","msgid":"<20230511141351.18886-2-jose.marchesi@oracle.com>","list_archive_url":null,"date":"2023-05-11T14:13:48","name":"[1/4] opcodes: use CGEN_INSN_LGUINT for base instructions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230511141351.18886-2-jose.marchesi@oracle.com/mbox/"},{"id":92630,"url":"https://patchwork.plctlab.org/api/1.2/patches/92630/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230511141351.18886-3-jose.marchesi@oracle.com/","msgid":"<20230511141351.18886-3-jose.marchesi@oracle.com>","list_archive_url":null,"date":"2023-05-11T14:13:49","name":"[2/4] cpu: add V3 BPF atomic instructions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230511141351.18886-3-jose.marchesi@oracle.com/mbox/"},{"id":92634,"url":"https://patchwork.plctlab.org/api/1.2/patches/92634/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230511141351.18886-4-jose.marchesi@oracle.com/","msgid":"<20230511141351.18886-4-jose.marchesi@oracle.com>","list_archive_url":null,"date":"2023-05-11T14:13:50","name":"[3/4] gas: add tests for BPF V3 atomic instructions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230511141351.18886-4-jose.marchesi@oracle.com/mbox/"},{"id":92637,"url":"https://patchwork.plctlab.org/api/1.2/patches/92637/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230511141351.18886-5-jose.marchesi@oracle.com/","msgid":"<20230511141351.18886-5-jose.marchesi@oracle.com>","list_archive_url":null,"date":"2023-05-11T14:13:51","name":"[4/4] gas: document V3 BPF atomic instructions in the GAS manual","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230511141351.18886-5-jose.marchesi@oracle.com/mbox/"},{"id":92848,"url":"https://patchwork.plctlab.org/api/1.2/patches/92848/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230511210232.1491265-1-goldstein.w.n@gmail.com/","msgid":"<20230511210232.1491265-1-goldstein.w.n@gmail.com>","list_archive_url":null,"date":"2023-05-11T21:02:32","name":"[v1] gold: Make '\''--section-ordering-file'\'' also specifiable in env variable","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230511210232.1491265-1-goldstein.w.n@gmail.com/mbox/"},{"id":92935,"url":"https://patchwork.plctlab.org/api/1.2/patches/92935/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/de17e059-80f6-5aa9-b693-14bdac45f0a4@rivosinc.com/","msgid":"","list_archive_url":null,"date":"2023-05-12T03:44:43","name":"[RFC] RISC-V: Support Zacas extension.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/de17e059-80f6-5aa9-b693-14bdac45f0a4@rivosinc.com/mbox/"},{"id":92974,"url":"https://patchwork.plctlab.org/api/1.2/patches/92974/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230512071720.1880195-2-yunqiang.su@cipunited.com/","msgid":"<20230512071720.1880195-2-yunqiang.su@cipunited.com>","list_archive_url":null,"date":"2023-05-12T07:17:17","name":"[1/4] MIPS: gas: alter 64 or 32 for mipsisa triples if march is implicit","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230512071720.1880195-2-yunqiang.su@cipunited.com/mbox/"},{"id":92976,"url":"https://patchwork.plctlab.org/api/1.2/patches/92976/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230512071720.1880195-3-yunqiang.su@cipunited.com/","msgid":"<20230512071720.1880195-3-yunqiang.su@cipunited.com>","list_archive_url":null,"date":"2023-05-12T07:17:18","name":"[2/4] MIPS: default r6 if vendor is img","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230512071720.1880195-3-yunqiang.su@cipunited.com/mbox/"},{"id":92978,"url":"https://patchwork.plctlab.org/api/1.2/patches/92978/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230512071720.1880195-4-yunqiang.su@cipunited.com/","msgid":"<20230512071720.1880195-4-yunqiang.su@cipunited.com>","list_archive_url":null,"date":"2023-05-12T07:17:19","name":"[3/4] MIPS: fix r6 testsuites","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230512071720.1880195-4-yunqiang.su@cipunited.com/mbox/"},{"id":92975,"url":"https://patchwork.plctlab.org/api/1.2/patches/92975/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230512071720.1880195-5-yunqiang.su@cipunited.com/","msgid":"<20230512071720.1880195-5-yunqiang.su@cipunited.com>","list_archive_url":null,"date":"2023-05-12T07:17:20","name":"[4/4] MIPS: fix -gnuabi64 testsuite","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230512071720.1880195-5-yunqiang.su@cipunited.com/mbox/"},{"id":93018,"url":"https://patchwork.plctlab.org/api/1.2/patches/93018/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230512091558.83523-1-nelson@rivosinc.com/","msgid":"<20230512091558.83523-1-nelson@rivosinc.com>","list_archive_url":null,"date":"2023-05-12T09:15:58","name":"RISC-V: PR27566, consider ELF_MAXPAGESIZE/COMMONPAGESIZE for gp relaxations.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230512091558.83523-1-nelson@rivosinc.com/mbox/"},{"id":93504,"url":"https://patchwork.plctlab.org/api/1.2/patches/93504/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZF9w7hthSZx+ryOw@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-05-13T11:13:50","name":"PR28902, -T script with INSERT ordering","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZF9w7hthSZx+ryOw@squeak.grove.modra.org/mbox/"},{"id":93505,"url":"https://patchwork.plctlab.org/api/1.2/patches/93505/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZF9x6S6gsYrA1lYO@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-05-13T11:18:01","name":"PR28955 mips gas segfault","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZF9x6S6gsYrA1lYO@squeak.grove.modra.org/mbox/"},{"id":93544,"url":"https://patchwork.plctlab.org/api/1.2/patches/93544/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230513172938.2831329-1-vladimir.mezentsev@oracle.com/","msgid":"<20230513172938.2831329-1-vladimir.mezentsev@oracle.com>","list_archive_url":null,"date":"2023-05-13T17:29:38","name":"[Review,is,neded] gprofng: include a new function in the right place","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230513172938.2831329-1-vladimir.mezentsev@oracle.com/mbox/"},{"id":93971,"url":"https://patchwork.plctlab.org/api/1.2/patches/93971/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/DU0P190MB200294640D702757F760A53383789@DU0P190MB2002.EURP190.PROD.OUTLOOK.COM/","msgid":"","list_archive_url":null,"date":"2023-05-15T08:50:27","name":"Decorated symbols in import libs (BUG 30421)","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/DU0P190MB200294640D702757F760A53383789@DU0P190MB2002.EURP190.PROD.OUTLOOK.COM/mbox/"},{"id":94420,"url":"https://patchwork.plctlab.org/api/1.2/patches/94420/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230516025426.2334478-2-yunqiang.su@cipunited.com/","msgid":"<20230516025426.2334478-2-yunqiang.su@cipunited.com>","list_archive_url":null,"date":"2023-05-16T02:54:22","name":"[v2,1/5] MIPS: gas: alter 64 or 32 for mipsisa triples if march is implicit","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230516025426.2334478-2-yunqiang.su@cipunited.com/mbox/"},{"id":94421,"url":"https://patchwork.plctlab.org/api/1.2/patches/94421/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230516025426.2334478-3-yunqiang.su@cipunited.com/","msgid":"<20230516025426.2334478-3-yunqiang.su@cipunited.com>","list_archive_url":null,"date":"2023-05-16T02:54:23","name":"[v2,2/5] MIPS: default r6 if vendor is img","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230516025426.2334478-3-yunqiang.su@cipunited.com/mbox/"},{"id":94425,"url":"https://patchwork.plctlab.org/api/1.2/patches/94425/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230516025426.2334478-4-yunqiang.su@cipunited.com/","msgid":"<20230516025426.2334478-4-yunqiang.su@cipunited.com>","list_archive_url":null,"date":"2023-05-16T02:54:24","name":"[v2,3/5] MIPS: fix r6 testsuites","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230516025426.2334478-4-yunqiang.su@cipunited.com/mbox/"},{"id":94423,"url":"https://patchwork.plctlab.org/api/1.2/patches/94423/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230516025426.2334478-5-yunqiang.su@cipunited.com/","msgid":"<20230516025426.2334478-5-yunqiang.su@cipunited.com>","list_archive_url":null,"date":"2023-05-16T02:54:25","name":"[v2,4/5] MIPS: fix -gnuabi64 testsuite","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230516025426.2334478-5-yunqiang.su@cipunited.com/mbox/"},{"id":94424,"url":"https://patchwork.plctlab.org/api/1.2/patches/94424/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230516025426.2334478-6-yunqiang.su@cipunited.com/","msgid":"<20230516025426.2334478-6-yunqiang.su@cipunited.com>","list_archive_url":null,"date":"2023-05-16T02:54:26","name":"[v2,5/5] MIPS: fix some ld testcases with compiler","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230516025426.2334478-6-yunqiang.su@cipunited.com/mbox/"},{"id":94985,"url":"https://patchwork.plctlab.org/api/1.2/patches/94985/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZGQXmQ+tAKqUC/IX@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-05-16T23:54:01","name":"gcc-4.5 build fixes","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZGQXmQ+tAKqUC/IX@squeak.grove.modra.org/mbox/"},{"id":94992,"url":"https://patchwork.plctlab.org/api/1.2/patches/94992/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZGQlZ4KofqcYiJX1@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-05-17T00:52:55","name":"PR29189, dlltool delaylibs corrupt float/double arguments","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZGQlZ4KofqcYiJX1@squeak.grove.modra.org/mbox/"},{"id":94997,"url":"https://patchwork.plctlab.org/api/1.2/patches/94997/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZGQzE2Ak4W5y2Xn9@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-05-17T01:51:15","name":"PR29961, plugin-api.h: \"Could not detect architecture endianess\"","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZGQzE2Ak4W5y2Xn9@squeak.grove.modra.org/mbox/"},{"id":95160,"url":"https://patchwork.plctlab.org/api/1.2/patches/95160/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/61663a6c-a5a4-812a-1110-06e0122aabba@suse.com/","msgid":"<61663a6c-a5a4-812a-1110-06e0122aabba@suse.com>","list_archive_url":null,"date":"2023-05-17T11:00:04","name":"x86: permit all relational operators in insn operands","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/61663a6c-a5a4-812a-1110-06e0122aabba@suse.com/mbox/"},{"id":95625,"url":"https://patchwork.plctlab.org/api/1.2/patches/95625/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZGWS/0oFOMVSyf+m@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-05-18T02:52:47","name":"PR11601, Solaris assembler compatibility doesn'\''t work","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZGWS/0oFOMVSyf+m@squeak.grove.modra.org/mbox/"},{"id":95637,"url":"https://patchwork.plctlab.org/api/1.2/patches/95637/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230518034102.1747564-1-jun.zhang@intel.com/","msgid":"<20230518034102.1747564-1-jun.zhang@intel.com>","list_archive_url":null,"date":"2023-05-18T03:41:02","name":"Support Intel FRED LKGS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230518034102.1747564-1-jun.zhang@intel.com/mbox/"},{"id":95667,"url":"https://patchwork.plctlab.org/api/1.2/patches/95667/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230518062025.1535847-1-indu.bhagat@oracle.com/","msgid":"<20230518062025.1535847-1-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-05-18T06:20:24","name":"[COMMITTED] libsframe: testsuite: add new tests for sframe_find_fre API","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230518062025.1535847-1-indu.bhagat@oracle.com/mbox/"},{"id":95668,"url":"https://patchwork.plctlab.org/api/1.2/patches/95668/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230518062025.1535847-2-indu.bhagat@oracle.com/","msgid":"<20230518062025.1535847-2-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-05-18T06:20:25","name":"[COMMITTED] libsframe: testsuite: add tests for sframe_get_funcdesc_with_addr API","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230518062025.1535847-2-indu.bhagat@oracle.com/mbox/"},{"id":95674,"url":"https://patchwork.plctlab.org/api/1.2/patches/95674/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230518065950.6166-1-xuli1@eswincomputing.com/","msgid":"<20230518065950.6166-1-xuli1@eswincomputing.com>","list_archive_url":null,"date":"2023-05-18T06:59:50","name":"RISC-V: Warn in AS if vsew/vlmul/vtype is reserved.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230518065950.6166-1-xuli1@eswincomputing.com/mbox/"},{"id":95717,"url":"https://patchwork.plctlab.org/api/1.2/patches/95717/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230518085739.2195035-1-lei.wang@oss.cipunited.com/","msgid":"<20230518085739.2195035-1-lei.wang@oss.cipunited.com>","list_archive_url":null,"date":"2023-05-18T08:57:50","name":"Add GINV(+VIRT) ASE for MIPSr6","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230518085739.2195035-1-lei.wang@oss.cipunited.com/mbox/"},{"id":95721,"url":"https://patchwork.plctlab.org/api/1.2/patches/95721/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230518092246.2450-1-nelson@rivosinc.com/","msgid":"<20230518092246.2450-1-nelson@rivosinc.com>","list_archive_url":null,"date":"2023-05-18T09:22:46","name":"RISC-V: Support subtraction of .uleb128.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230518092246.2450-1-nelson@rivosinc.com/mbox/"},{"id":96167,"url":"https://patchwork.plctlab.org/api/1.2/patches/96167/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230519021448.30120-1-xuli1@eswincomputing.com/","msgid":"<20230519021448.30120-1-xuli1@eswincomputing.com>","list_archive_url":null,"date":"2023-05-19T02:14:48","name":"RISC-V: Warn in AS if vsew/vlmul/vtype is reserved.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230519021448.30120-1-xuli1@eswincomputing.com/mbox/"},{"id":96176,"url":"https://patchwork.plctlab.org/api/1.2/patches/96176/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230519034835.664-2-shihua@iscas.ac.cn/","msgid":"<20230519034835.664-2-shihua@iscas.ac.cn>","list_archive_url":null,"date":"2023-05-19T03:48:32","name":"[RFC,1/4] RISC-V : Remove checking when -march=rv64XX and -mabi=ilp32X","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230519034835.664-2-shihua@iscas.ac.cn/mbox/"},{"id":96178,"url":"https://patchwork.plctlab.org/api/1.2/patches/96178/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230519034835.664-3-shihua@iscas.ac.cn/","msgid":"<20230519034835.664-3-shihua@iscas.ac.cn>","list_archive_url":null,"date":"2023-05-19T03:48:33","name":"[RFC,2/4] RISC-V : Add support for rv64 arch using ilp32 abi","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230519034835.664-3-shihua@iscas.ac.cn/mbox/"},{"id":96177,"url":"https://patchwork.plctlab.org/api/1.2/patches/96177/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230519034835.664-4-shihua@iscas.ac.cn/","msgid":"<20230519034835.664-4-shihua@iscas.ac.cn>","list_archive_url":null,"date":"2023-05-19T03:48:34","name":"[RFC,3/4] RISC-V : Add rv64 ilp32 support in disassemble","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230519034835.664-4-shihua@iscas.ac.cn/mbox/"},{"id":96180,"url":"https://patchwork.plctlab.org/api/1.2/patches/96180/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230519034835.664-5-shihua@iscas.ac.cn/","msgid":"<20230519034835.664-5-shihua@iscas.ac.cn>","list_archive_url":null,"date":"2023-05-19T03:48:35","name":"[RFC,4/4] gdb/riscv : Add rv64 ilp32 support in gdb","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230519034835.664-5-shihua@iscas.ac.cn/mbox/"},{"id":96420,"url":"https://patchwork.plctlab.org/api/1.2/patches/96420/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/54c5d383-28bc-c61d-48b2-93b2b40a444c@suse.com/","msgid":"<54c5d383-28bc-c61d-48b2-93b2b40a444c@suse.com>","list_archive_url":null,"date":"2023-05-19T13:24:05","name":"ld: drop stray blank from ld.texi","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/54c5d383-28bc-c61d-48b2-93b2b40a444c@suse.com/mbox/"},{"id":96421,"url":"https://patchwork.plctlab.org/api/1.2/patches/96421/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b660dcfd-4a87-d6a4-a737-572b1b555f7c@suse.com/","msgid":"","list_archive_url":null,"date":"2023-05-19T13:30:57","name":"[1/2] x86: de-duplicate operand_special_chars[] wrt extra_symbol_chars[]","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b660dcfd-4a87-d6a4-a737-572b1b555f7c@suse.com/mbox/"},{"id":96422,"url":"https://patchwork.plctlab.org/api/1.2/patches/96422/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/83c328ec-3eab-767c-e65c-0d83183fd18a@suse.com/","msgid":"<83c328ec-3eab-767c-e65c-0d83183fd18a@suse.com>","list_archive_url":null,"date":"2023-05-19T13:31:28","name":"[2/2] x86: figure braces aren'\''t really part of mnemonics","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/83c328ec-3eab-767c-e65c-0d83183fd18a@suse.com/mbox/"},{"id":96432,"url":"https://patchwork.plctlab.org/api/1.2/patches/96432/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4989461e-c6fe-b102-2be1-6806e28abbb2@suse.com/","msgid":"<4989461e-c6fe-b102-2be1-6806e28abbb2@suse.com>","list_archive_url":null,"date":"2023-05-19T13:51:24","name":"[1/4] x86: split gas testsuite .exp file","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4989461e-c6fe-b102-2be1-6806e28abbb2@suse.com/mbox/"},{"id":96433,"url":"https://patchwork.plctlab.org/api/1.2/patches/96433/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/da25f556-06a6-9b64-f333-04953812fcaa@suse.com/","msgid":"","list_archive_url":null,"date":"2023-05-19T13:51:57","name":"[2/4] x86-64: conditionalize tests using --32","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/da25f556-06a6-9b64-f333-04953812fcaa@suse.com/mbox/"},{"id":96434,"url":"https://patchwork.plctlab.org/api/1.2/patches/96434/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/778a4bcd-ac39-6512-38d2-782e4eb1eea9@suse.com/","msgid":"<778a4bcd-ac39-6512-38d2-782e4eb1eea9@suse.com>","list_archive_url":null,"date":"2023-05-19T13:52:18","name":"[3/4] x86-64: improve gas diagnostic when no 32-bit target is configured","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/778a4bcd-ac39-6512-38d2-782e4eb1eea9@suse.com/mbox/"},{"id":96435,"url":"https://patchwork.plctlab.org/api/1.2/patches/96435/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d5ebeef6-ea62-b26b-bd67-ea24a21582d8@suse.com/","msgid":"","list_archive_url":null,"date":"2023-05-19T13:52:57","name":"[4/4] iamcu: suppress tests which can'\''t possibly work","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d5ebeef6-ea62-b26b-bd67-ea24a21582d8@suse.com/mbox/"},{"id":96442,"url":"https://patchwork.plctlab.org/api/1.2/patches/96442/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2274d914-c77f-37e7-5589-870a647e24a0@suse.com/","msgid":"<2274d914-c77f-37e7-5589-870a647e24a0@suse.com>","list_archive_url":null,"date":"2023-05-19T14:06:31","name":"[1/3] x86: use fixed-width type for codep and friends","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2274d914-c77f-37e7-5589-870a647e24a0@suse.com/mbox/"},{"id":96443,"url":"https://patchwork.plctlab.org/api/1.2/patches/96443/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/65393035-8006-1a66-deae-70a88ed29077@suse.com/","msgid":"<65393035-8006-1a66-deae-70a88ed29077@suse.com>","list_archive_url":null,"date":"2023-05-19T14:06:57","name":"[2/3] x86: disassembling over-long insns","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/65393035-8006-1a66-deae-70a88ed29077@suse.com/mbox/"},{"id":96444,"url":"https://patchwork.plctlab.org/api/1.2/patches/96444/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/51d38635-479f-831f-e678-3da1a1c9acae@suse.com/","msgid":"<51d38635-479f-831f-e678-3da1a1c9acae@suse.com>","list_archive_url":null,"date":"2023-05-19T14:07:25","name":"[3/3] x86: convert two pointers to (indexing) integers","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/51d38635-479f-831f-e678-3da1a1c9acae@suse.com/mbox/"},{"id":96697,"url":"https://patchwork.plctlab.org/api/1.2/patches/96697/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZGgfi5EKNdCyxFOt@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-05-20T01:16:59","name":"tic54x set_arch_mach","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZGgfi5EKNdCyxFOt@squeak.grove.modra.org/mbox/"},{"id":96698,"url":"https://patchwork.plctlab.org/api/1.2/patches/96698/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZGgf5d2KsCwesZbD@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-05-20T01:18:29","name":"coffcode.h handle_COMDAT tidy","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZGgf5d2KsCwesZbD@squeak.grove.modra.org/mbox/"},{"id":96762,"url":"https://patchwork.plctlab.org/api/1.2/patches/96762/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZGiyriwnKNKJqiJV@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-05-20T11:44:46","name":"coff-mips refhi list","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZGiyriwnKNKJqiJV@squeak.grove.modra.org/mbox/"},{"id":96951,"url":"https://patchwork.plctlab.org/api/1.2/patches/96951/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230522013441.3074776-2-mengqinggang@loongson.cn/","msgid":"<20230522013441.3074776-2-mengqinggang@loongson.cn>","list_archive_url":null,"date":"2023-05-22T01:34:36","name":"[v4,1/6] LoongArch: include: Add support for linker relaxation.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230522013441.3074776-2-mengqinggang@loongson.cn/mbox/"},{"id":96954,"url":"https://patchwork.plctlab.org/api/1.2/patches/96954/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230522013441.3074776-3-mengqinggang@loongson.cn/","msgid":"<20230522013441.3074776-3-mengqinggang@loongson.cn>","list_archive_url":null,"date":"2023-05-22T01:34:37","name":"[v4,2/6] LoongArch: bfd: Add support for linker relaxation.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230522013441.3074776-3-mengqinggang@loongson.cn/mbox/"},{"id":96952,"url":"https://patchwork.plctlab.org/api/1.2/patches/96952/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230522013441.3074776-4-mengqinggang@loongson.cn/","msgid":"<20230522013441.3074776-4-mengqinggang@loongson.cn>","list_archive_url":null,"date":"2023-05-22T01:34:38","name":"[v4,3/6] LoongArch: opcodes: Add support for linker relaxation.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230522013441.3074776-4-mengqinggang@loongson.cn/mbox/"},{"id":96955,"url":"https://patchwork.plctlab.org/api/1.2/patches/96955/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230522013441.3074776-5-mengqinggang@loongson.cn/","msgid":"<20230522013441.3074776-5-mengqinggang@loongson.cn>","list_archive_url":null,"date":"2023-05-22T01:34:39","name":"[v4,4/6] LoongArch: binutils: Add support for linker relaxation.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230522013441.3074776-5-mengqinggang@loongson.cn/mbox/"},{"id":96956,"url":"https://patchwork.plctlab.org/api/1.2/patches/96956/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230522013441.3074776-6-mengqinggang@loongson.cn/","msgid":"<20230522013441.3074776-6-mengqinggang@loongson.cn>","list_archive_url":null,"date":"2023-05-22T01:34:40","name":"[v4,5/6] LoongArch: gas: Add support for linker relaxation.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230522013441.3074776-6-mengqinggang@loongson.cn/mbox/"},{"id":96957,"url":"https://patchwork.plctlab.org/api/1.2/patches/96957/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230522013441.3074776-7-mengqinggang@loongson.cn/","msgid":"<20230522013441.3074776-7-mengqinggang@loongson.cn>","list_archive_url":null,"date":"2023-05-22T01:34:41","name":"[v4,6/6] LoongArch: ld: Add support for linker relaxation.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230522013441.3074776-7-mengqinggang@loongson.cn/mbox/"},{"id":97053,"url":"https://patchwork.plctlab.org/api/1.2/patches/97053/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230522060030.100976-1-jun.zhang@intel.com/","msgid":"<20230522060030.100976-1-jun.zhang@intel.com>","list_archive_url":null,"date":"2023-05-22T06:00:30","name":"[v2] Support Intel FRED LKGS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230522060030.100976-1-jun.zhang@intel.com/mbox/"},{"id":97056,"url":"https://patchwork.plctlab.org/api/1.2/patches/97056/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230522060726.101037-1-jun.zhang@intel.com/","msgid":"<20230522060726.101037-1-jun.zhang@intel.com>","list_archive_url":null,"date":"2023-05-22T06:07:26","name":"[v2] Support Intel FRED LKGS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230522060726.101037-1-jun.zhang@intel.com/mbox/"},{"id":97175,"url":"https://patchwork.plctlab.org/api/1.2/patches/97175/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZGsqFcGAvyznqFbB@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-05-22T08:38:45","name":"PowerPC64 report number of stub iterations","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZGsqFcGAvyznqFbB@squeak.grove.modra.org/mbox/"},{"id":97480,"url":"https://patchwork.plctlab.org/api/1.2/patches/97480/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230522142036.199490-1-jun.zhang@intel.com/","msgid":"<20230522142036.199490-1-jun.zhang@intel.com>","list_archive_url":null,"date":"2023-05-22T14:20:36","name":"[v3] Support Intel FRED LKGS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230522142036.199490-1-jun.zhang@intel.com/mbox/"},{"id":97571,"url":"https://patchwork.plctlab.org/api/1.2/patches/97571/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b0750b7e-fc76-d5ed-cd26-1a1bb6a1f2db@free.fr/","msgid":"","list_archive_url":null,"date":"2023-05-22T19:48:22","name":"[v2] pe/coff - add support for base64 encoded long section names","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b0750b7e-fc76-d5ed-cd26-1a1bb6a1f2db@free.fr/mbox/"},{"id":99104,"url":"https://patchwork.plctlab.org/api/1.2/patches/99104/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/871qj41iw5.fsf@redhat.com/","msgid":"<871qj41iw5.fsf@redhat.com>","list_archive_url":null,"date":"2023-05-25T16:21:46","name":"RFC: Objdump: Dumping PE specific headers","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/871qj41iw5.fsf@redhat.com/mbox/"},{"id":99146,"url":"https://patchwork.plctlab.org/api/1.2/patches/99146/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/87y1lcxpj0.fsf@igel.home/","msgid":"<87y1lcxpj0.fsf@igel.home>","list_archive_url":null,"date":"2023-05-25T17:57:23","name":"Remove duplicate definition","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/87y1lcxpj0.fsf@igel.home/mbox/"},{"id":99271,"url":"https://patchwork.plctlab.org/api/1.2/patches/99271/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZHAjjvo+Ldk5OyAQ@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-05-26T03:12:14","name":"PR22263 ld test, riscv fail","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZHAjjvo+Ldk5OyAQ@squeak.grove.modra.org/mbox/"},{"id":99314,"url":"https://patchwork.plctlab.org/api/1.2/patches/99314/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230526070132.4185600-1-indu.bhagat@oracle.com/","msgid":"<20230526070132.4185600-1-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-05-26T07:01:29","name":"[COMMITTED] libsframe: use uint8_t data type for FRE info related stubs","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230526070132.4185600-1-indu.bhagat@oracle.com/mbox/"},{"id":99315,"url":"https://patchwork.plctlab.org/api/1.2/patches/99315/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230526070132.4185600-2-indu.bhagat@oracle.com/","msgid":"<20230526070132.4185600-2-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-05-26T07:01:30","name":"[COMMITTED] libsframe: use const char * consistently for immutable FRE buffers","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230526070132.4185600-2-indu.bhagat@oracle.com/mbox/"},{"id":99316,"url":"https://patchwork.plctlab.org/api/1.2/patches/99316/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230526070132.4185600-3-indu.bhagat@oracle.com/","msgid":"<20230526070132.4185600-3-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-05-26T07:01:31","name":"[COMMITTED] libsframe: revisit sframe_find_fre API","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230526070132.4185600-3-indu.bhagat@oracle.com/mbox/"},{"id":99317,"url":"https://patchwork.plctlab.org/api/1.2/patches/99317/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230526070132.4185600-4-indu.bhagat@oracle.com/","msgid":"<20230526070132.4185600-4-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-05-26T07:01:32","name":"[COMMITTED] sframe/doc: minor improvements for readability","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230526070132.4185600-4-indu.bhagat@oracle.com/mbox/"},{"id":99387,"url":"https://patchwork.plctlab.org/api/1.2/patches/99387/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230526073833.3933735-2-mengqinggang@loongson.cn/","msgid":"<20230526073833.3933735-2-mengqinggang@loongson.cn>","list_archive_url":null,"date":"2023-05-26T07:38:28","name":"[v5,1/6] LoongArch: include: Add support for linker relaxation.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230526073833.3933735-2-mengqinggang@loongson.cn/mbox/"},{"id":99397,"url":"https://patchwork.plctlab.org/api/1.2/patches/99397/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230526073833.3933735-3-mengqinggang@loongson.cn/","msgid":"<20230526073833.3933735-3-mengqinggang@loongson.cn>","list_archive_url":null,"date":"2023-05-26T07:38:29","name":"[v5,2/6] LoongArch: bfd: Add support for linker relaxation.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230526073833.3933735-3-mengqinggang@loongson.cn/mbox/"},{"id":99391,"url":"https://patchwork.plctlab.org/api/1.2/patches/99391/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230526073833.3933735-4-mengqinggang@loongson.cn/","msgid":"<20230526073833.3933735-4-mengqinggang@loongson.cn>","list_archive_url":null,"date":"2023-05-26T07:38:30","name":"[v5,3/6] LoongArch: opcodes: Add support for linker relaxation.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230526073833.3933735-4-mengqinggang@loongson.cn/mbox/"},{"id":99393,"url":"https://patchwork.plctlab.org/api/1.2/patches/99393/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230526073833.3933735-5-mengqinggang@loongson.cn/","msgid":"<20230526073833.3933735-5-mengqinggang@loongson.cn>","list_archive_url":null,"date":"2023-05-26T07:38:31","name":"[v5,4/6] LoongArch: binutils: Add support for linker relaxation.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230526073833.3933735-5-mengqinggang@loongson.cn/mbox/"},{"id":99385,"url":"https://patchwork.plctlab.org/api/1.2/patches/99385/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230526073833.3933735-6-mengqinggang@loongson.cn/","msgid":"<20230526073833.3933735-6-mengqinggang@loongson.cn>","list_archive_url":null,"date":"2023-05-26T07:38:32","name":"[v5,5/6] LoongArch: gas: Add support for linker relaxation.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230526073833.3933735-6-mengqinggang@loongson.cn/mbox/"},{"id":99370,"url":"https://patchwork.plctlab.org/api/1.2/patches/99370/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230526073833.3933735-7-mengqinggang@loongson.cn/","msgid":"<20230526073833.3933735-7-mengqinggang@loongson.cn>","list_archive_url":null,"date":"2023-05-26T07:38:33","name":"[v5,6/6] LoongArch: ld: Add support for linker relaxation.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230526073833.3933735-7-mengqinggang@loongson.cn/mbox/"},{"id":99406,"url":"https://patchwork.plctlab.org/api/1.2/patches/99406/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230526082648.1503574-1-haochen.jiang@intel.com/","msgid":"<20230526082648.1503574-1-haochen.jiang@intel.com>","list_archive_url":null,"date":"2023-05-26T08:26:48","name":"x86: Add Evw to emit w suffix for several instrctions for word ptr","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230526082648.1503574-1-haochen.jiang@intel.com/mbox/"},{"id":99429,"url":"https://patchwork.plctlab.org/api/1.2/patches/99429/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230526101358.787593-1-jun.zhang@intel.com/","msgid":"<20230526101358.787593-1-jun.zhang@intel.com>","list_archive_url":null,"date":"2023-05-26T10:13:58","name":"Enable x86-64-fred-intel and x86-64-lkgs-intel test.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230526101358.787593-1-jun.zhang@intel.com/mbox/"},{"id":99644,"url":"https://patchwork.plctlab.org/api/1.2/patches/99644/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230526195407.2663991-1-vladimir.mezentsev@oracle.com/","msgid":"<20230526195407.2663991-1-vladimir.mezentsev@oracle.com>","list_archive_url":null,"date":"2023-05-26T19:54:07","name":"gprofng: 29470 The test suite should be made more flexible","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230526195407.2663991-1-vladimir.mezentsev@oracle.com/mbox/"},{"id":99645,"url":"https://patchwork.plctlab.org/api/1.2/patches/99645/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230526195518.2664720-1-vladimir.mezentsev@oracle.com/","msgid":"<20230526195518.2664720-1-vladimir.mezentsev@oracle.com>","list_archive_url":null,"date":"2023-05-26T19:55:18","name":"gprofng: Fix -Wsign-compare warning","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230526195518.2664720-1-vladimir.mezentsev@oracle.com/mbox/"},{"id":99734,"url":"https://patchwork.plctlab.org/api/1.2/patches/99734/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230527013620.65127-1-nelson@rivosinc.com/","msgid":"<20230527013620.65127-1-nelson@rivosinc.com>","list_archive_url":null,"date":"2023-05-27T01:36:20","name":"[PR,ld/22263] RISC-V: Avoid spurious R_RISCV_NONE for pr22263-1 test.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230527013620.65127-1-nelson@rivosinc.com/mbox/"},{"id":100526,"url":"https://patchwork.plctlab.org/api/1.2/patches/100526/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZHV5vB0C7IPf7sCX@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-05-30T04:21:16","name":"Regen binutils POTFILES.in","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZHV5vB0C7IPf7sCX@squeak.grove.modra.org/mbox/"},{"id":100527,"url":"https://patchwork.plctlab.org/api/1.2/patches/100527/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZHV544m6nKA2ck7Q@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-05-30T04:21:55","name":"Delete include/aout/encap.h","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZHV544m6nKA2ck7Q@squeak.grove.modra.org/mbox/"},{"id":100529,"url":"https://patchwork.plctlab.org/api/1.2/patches/100529/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZHV5/28XpXf2d9Wd@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-05-30T04:22:23","name":"Don'\''t define COFF_MAGIC","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZHV5/28XpXf2d9Wd@squeak.grove.modra.org/mbox/"},{"id":100528,"url":"https://patchwork.plctlab.org/api/1.2/patches/100528/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZHV6I0KUQQFhewlR@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-05-30T04:22:59","name":"Define IMAGE_FILE_MACHINE_ARMNT","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZHV6I0KUQQFhewlR@squeak.grove.modra.org/mbox/"},{"id":100530,"url":"https://patchwork.plctlab.org/api/1.2/patches/100530/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZHV6WtRazoQ6jCEo@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-05-30T04:23:54","name":"arm-pe objdump -P","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZHV6WtRazoQ6jCEo@squeak.grove.modra.org/mbox/"},{"id":101020,"url":"https://patchwork.plctlab.org/api/1.2/patches/101020/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230530171252.269552-2-hjl.tools@gmail.com/","msgid":"<20230530171252.269552-2-hjl.tools@gmail.com>","list_archive_url":null,"date":"2023-05-30T17:12:47","name":"[1/6] ELF: Strip section header in ELF objects","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230530171252.269552-2-hjl.tools@gmail.com/mbox/"},{"id":101025,"url":"https://patchwork.plctlab.org/api/1.2/patches/101025/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230530171252.269552-3-hjl.tools@gmail.com/","msgid":"<20230530171252.269552-3-hjl.tools@gmail.com>","list_archive_url":null,"date":"2023-05-30T17:12:48","name":"[2/6] bfd: Improve nm and objdump without section header","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230530171252.269552-3-hjl.tools@gmail.com/mbox/"},{"id":101028,"url":"https://patchwork.plctlab.org/api/1.2/patches/101028/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230530171252.269552-4-hjl.tools@gmail.com/","msgid":"<20230530171252.269552-4-hjl.tools@gmail.com>","list_archive_url":null,"date":"2023-05-30T17:12:49","name":"[3/6] ld: Add a simple test for -z nosectionheader","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230530171252.269552-4-hjl.tools@gmail.com/mbox/"},{"id":101022,"url":"https://patchwork.plctlab.org/api/1.2/patches/101022/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230530171252.269552-5-hjl.tools@gmail.com/","msgid":"<20230530171252.269552-5-hjl.tools@gmail.com>","list_archive_url":null,"date":"2023-05-30T17:12:50","name":"[4/6] binutils: Add a --strip-sections test","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230530171252.269552-5-hjl.tools@gmail.com/mbox/"},{"id":101027,"url":"https://patchwork.plctlab.org/api/1.2/patches/101027/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230530171252.269552-6-hjl.tools@gmail.com/","msgid":"<20230530171252.269552-6-hjl.tools@gmail.com>","list_archive_url":null,"date":"2023-05-30T17:12:51","name":"[5/6] ld: Add tests for -z nosectionheader and --strip-sections","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230530171252.269552-6-hjl.tools@gmail.com/mbox/"},{"id":101021,"url":"https://patchwork.plctlab.org/api/1.2/patches/101021/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230530171252.269552-7-hjl.tools@gmail.com/","msgid":"<20230530171252.269552-7-hjl.tools@gmail.com>","list_archive_url":null,"date":"2023-05-30T17:12:52","name":"[6/6] ld: Add -z nosectionheader test to bootstrap.exp","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230530171252.269552-7-hjl.tools@gmail.com/mbox/"},{"id":101296,"url":"https://patchwork.plctlab.org/api/1.2/patches/101296/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/87a5xkua9s.fsf@redhat.com/","msgid":"<87a5xkua9s.fsf@redhat.com>","list_archive_url":null,"date":"2023-05-31T09:21:03","name":"Commit: elfxx-loongarch64.c: Fix printf formatting issues.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/87a5xkua9s.fsf@redhat.com/mbox/"}],"public":true,"mbox":"https://patchwork.plctlab.org/bundle/patchwork-bot/binutils-gdb_2023-05/mbox/"},{"id":23,"url":"https://patchwork.plctlab.org/api/1.2/bundles/23/","web_url":"https://patchwork.plctlab.org/bundle/patchwork-bot/binutils-gdb_2023-06/","project":{"id":2,"url":"https://patchwork.plctlab.org/api/1.2/projects/2/","name":"binutils-gdb","link_name":"binutils-gdb","list_id":"binutils.sourceware.org","list_email":"binutils@sourceware.org","web_url":"https://github.com/wangliu-iscas/Patchwork-Bundles/blob/main/binutils-gdb.md","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"name":"binutils-gdb_2023-06","owner":{"id":3,"url":"https://patchwork.plctlab.org/api/1.2/users/3/","username":"patchwork-bot","first_name":"","last_name":"","email":"ouuuleilei@gmail.com"},"patches":[{"id":101537,"url":"https://patchwork.plctlab.org/api/1.2/patches/101537/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230531162856.48916-1-gianluca@rivosinc.com/","msgid":"<20230531162856.48916-1-gianluca@rivosinc.com>","list_archive_url":null,"date":"2023-05-31T16:28:56","name":"[RFC,v2] RISC-V: Support Zacas extension.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230531162856.48916-1-gianluca@rivosinc.com/mbox/"},{"id":101579,"url":"https://patchwork.plctlab.org/api/1.2/patches/101579/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230531200617.951996-2-hjl.tools@gmail.com/","msgid":"<20230531200617.951996-2-hjl.tools@gmail.com>","list_archive_url":null,"date":"2023-05-31T20:06:11","name":"[v2,1/7] ELF: Strip section header in ELF objects","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230531200617.951996-2-hjl.tools@gmail.com/mbox/"},{"id":101576,"url":"https://patchwork.plctlab.org/api/1.2/patches/101576/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230531200617.951996-3-hjl.tools@gmail.com/","msgid":"<20230531200617.951996-3-hjl.tools@gmail.com>","list_archive_url":null,"date":"2023-05-31T20:06:12","name":"[v2,2/7] ELF: Discard non-alloc sections without section header","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230531200617.951996-3-hjl.tools@gmail.com/mbox/"},{"id":101578,"url":"https://patchwork.plctlab.org/api/1.2/patches/101578/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230531200617.951996-4-hjl.tools@gmail.com/","msgid":"<20230531200617.951996-4-hjl.tools@gmail.com>","list_archive_url":null,"date":"2023-05-31T20:06:13","name":"[v2,3/7] bfd: Improve nm and objdump without section header","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230531200617.951996-4-hjl.tools@gmail.com/mbox/"},{"id":101572,"url":"https://patchwork.plctlab.org/api/1.2/patches/101572/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230531200617.951996-5-hjl.tools@gmail.com/","msgid":"<20230531200617.951996-5-hjl.tools@gmail.com>","list_archive_url":null,"date":"2023-05-31T20:06:14","name":"[v2,4/7] ld: Add a simple test for -z nosectionheader","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230531200617.951996-5-hjl.tools@gmail.com/mbox/"},{"id":101573,"url":"https://patchwork.plctlab.org/api/1.2/patches/101573/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230531200617.951996-6-hjl.tools@gmail.com/","msgid":"<20230531200617.951996-6-hjl.tools@gmail.com>","list_archive_url":null,"date":"2023-05-31T20:06:15","name":"[v2,5/7] binutils: Add a --strip-section-headers test","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230531200617.951996-6-hjl.tools@gmail.com/mbox/"},{"id":101580,"url":"https://patchwork.plctlab.org/api/1.2/patches/101580/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230531200617.951996-7-hjl.tools@gmail.com/","msgid":"<20230531200617.951996-7-hjl.tools@gmail.com>","list_archive_url":null,"date":"2023-05-31T20:06:16","name":"[v2,6/7] ld: Add tests for -z nosectionheader and --strip-section-headers","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230531200617.951996-7-hjl.tools@gmail.com/mbox/"},{"id":101574,"url":"https://patchwork.plctlab.org/api/1.2/patches/101574/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230531200617.951996-8-hjl.tools@gmail.com/","msgid":"<20230531200617.951996-8-hjl.tools@gmail.com>","list_archive_url":null,"date":"2023-05-31T20:06:17","name":"[v2,7/7] ld: Add -z nosectionheader test to bootstrap.exp","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230531200617.951996-8-hjl.tools@gmail.com/mbox/"},{"id":101625,"url":"https://patchwork.plctlab.org/api/1.2/patches/101625/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZHfmQsTZbxX1yUIq@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-06-01T00:28:50","name":"Remove BFD_FAIL in cpu-sh.c","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZHfmQsTZbxX1yUIq@squeak.grove.modra.org/mbox/"},{"id":101626,"url":"https://patchwork.plctlab.org/api/1.2/patches/101626/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZHfmjU0Ft5Jrcj3c@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-06-01T00:30:05","name":"section_by_target_index memory leak","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZHfmjU0Ft5Jrcj3c@squeak.grove.modra.org/mbox/"},{"id":101627,"url":"https://patchwork.plctlab.org/api/1.2/patches/101627/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZHfm5/WNQaE4NSYR@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-06-01T00:31:35","name":"bfd_close and target free_cached_memory","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZHfm5/WNQaE4NSYR@squeak.grove.modra.org/mbox/"},{"id":101628,"url":"https://patchwork.plctlab.org/api/1.2/patches/101628/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZHfnQckZnox2uLOu@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-06-01T00:33:05","name":"Harden PowerPC64 OPD handling against fuzzers","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZHfnQckZnox2uLOu@squeak.grove.modra.org/mbox/"},{"id":101754,"url":"https://patchwork.plctlab.org/api/1.2/patches/101754/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230601061610.2614564-1-indu.bhagat@oracle.com/","msgid":"<20230601061610.2614564-1-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-06-01T06:16:10","name":"[COMMITTED] libsframe: minor fixups in flip_fre related functions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230601061610.2614564-1-indu.bhagat@oracle.com/mbox/"},{"id":102114,"url":"https://patchwork.plctlab.org/api/1.2/patches/102114/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230601173312.3176329-1-indu.bhagat@oracle.com/","msgid":"<20230601173312.3176329-1-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-06-01T17:33:12","name":"[COMMITTED] libsframe: avoid using magic number","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230601173312.3176329-1-indu.bhagat@oracle.com/mbox/"},{"id":102244,"url":"https://patchwork.plctlab.org/api/1.2/patches/102244/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZHkxDSYR0EtVi6dY@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-06-02T00:00:13","name":"Minor objcopy optimisation for copy_relocations_in_section","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZHkxDSYR0EtVi6dY@squeak.grove.modra.org/mbox/"},{"id":102245,"url":"https://patchwork.plctlab.org/api/1.2/patches/102245/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZHkxOZ+7zNpFcAUv@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-06-02T00:00:57","name":"loongarch readelf support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZHkxOZ+7zNpFcAUv@squeak.grove.modra.org/mbox/"},{"id":102407,"url":"https://patchwork.plctlab.org/api/1.2/patches/102407/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230602092410.2841184-1-mengqinggang@loongson.cn/","msgid":"<20230602092410.2841184-1-mengqinggang@loongson.cn>","list_archive_url":null,"date":"2023-06-02T09:24:10","name":"LoongArch: gas: Relocations simplification when -mno-relax","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230602092410.2841184-1-mengqinggang@loongson.cn/mbox/"},{"id":102680,"url":"https://patchwork.plctlab.org/api/1.2/patches/102680/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230602192527.1532280-1-hjl.tools@gmail.com/","msgid":"<20230602192527.1532280-1-hjl.tools@gmail.com>","list_archive_url":null,"date":"2023-06-02T19:25:27","name":"ELF: Don'\''t warn an empty PT_LOAD with the program headers","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230602192527.1532280-1-hjl.tools@gmail.com/mbox/"},{"id":102961,"url":"https://patchwork.plctlab.org/api/1.2/patches/102961/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/221f70cf-5cff-6053-7499-499d4202e90b@debian.org/","msgid":"<221f70cf-5cff-6053-7499-499d4202e90b@debian.org>","list_archive_url":null,"date":"2023-06-04T06:44:45","name":"ignore lto-wrapper warnings for lto builds","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/221f70cf-5cff-6053-7499-499d4202e90b@debian.org/mbox/"},{"id":103136,"url":"https://patchwork.plctlab.org/api/1.2/patches/103136/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZH2Mwib11IEH7JDu@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-06-05T07:20:34","name":"Yet another ecoff fuzzed object fix","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZH2Mwib11IEH7JDu@squeak.grove.modra.org/mbox/"},{"id":103138,"url":"https://patchwork.plctlab.org/api/1.2/patches/103138/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZH2NDLgf5atBfB7S@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-06-05T07:21:48","name":"bfd_error_on_input messages","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZH2NDLgf5atBfB7S@squeak.grove.modra.org/mbox/"},{"id":103197,"url":"https://patchwork.plctlab.org/api/1.2/patches/103197/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230605102225.3566958-1-yunqiang.su@cipunited.com/","msgid":"<20230605102225.3566958-1-yunqiang.su@cipunited.com>","list_archive_url":null,"date":"2023-06-05T10:22:24","name":"[1/2] MIPS: Add n32 VECs to non-vendor elf targets","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230605102225.3566958-1-yunqiang.su@cipunited.com/mbox/"},{"id":103198,"url":"https://patchwork.plctlab.org/api/1.2/patches/103198/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230605102225.3566958-2-yunqiang.su@cipunited.com/","msgid":"<20230605102225.3566958-2-yunqiang.su@cipunited.com>","list_archive_url":null,"date":"2023-06-05T10:22:25","name":"[2/2] MIPS: fix Irix gas testcases","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230605102225.3566958-2-yunqiang.su@cipunited.com/mbox/"},{"id":103356,"url":"https://patchwork.plctlab.org/api/1.2/patches/103356/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230605153222.1728119-2-hjl.tools@gmail.com/","msgid":"<20230605153222.1728119-2-hjl.tools@gmail.com>","list_archive_url":null,"date":"2023-06-05T15:32:16","name":"[v3,1/7] ELF: Strip section header in ELF objects","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230605153222.1728119-2-hjl.tools@gmail.com/mbox/"},{"id":103349,"url":"https://patchwork.plctlab.org/api/1.2/patches/103349/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230605153222.1728119-3-hjl.tools@gmail.com/","msgid":"<20230605153222.1728119-3-hjl.tools@gmail.com>","list_archive_url":null,"date":"2023-06-05T15:32:17","name":"[v3,2/7] ELF: Discard non-alloc sections without section header","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230605153222.1728119-3-hjl.tools@gmail.com/mbox/"},{"id":103354,"url":"https://patchwork.plctlab.org/api/1.2/patches/103354/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230605153222.1728119-4-hjl.tools@gmail.com/","msgid":"<20230605153222.1728119-4-hjl.tools@gmail.com>","list_archive_url":null,"date":"2023-06-05T15:32:18","name":"[v3,3/7] bfd: Improve nm and objdump without section header","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230605153222.1728119-4-hjl.tools@gmail.com/mbox/"},{"id":103351,"url":"https://patchwork.plctlab.org/api/1.2/patches/103351/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230605153222.1728119-5-hjl.tools@gmail.com/","msgid":"<20230605153222.1728119-5-hjl.tools@gmail.com>","list_archive_url":null,"date":"2023-06-05T15:32:19","name":"[v3,4/7] ld: Add a simple test for -z nosectionheader","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230605153222.1728119-5-hjl.tools@gmail.com/mbox/"},{"id":103353,"url":"https://patchwork.plctlab.org/api/1.2/patches/103353/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230605153222.1728119-6-hjl.tools@gmail.com/","msgid":"<20230605153222.1728119-6-hjl.tools@gmail.com>","list_archive_url":null,"date":"2023-06-05T15:32:20","name":"[v3,5/7] binutils: Add a --strip-section-headers test","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230605153222.1728119-6-hjl.tools@gmail.com/mbox/"},{"id":103355,"url":"https://patchwork.plctlab.org/api/1.2/patches/103355/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230605153222.1728119-7-hjl.tools@gmail.com/","msgid":"<20230605153222.1728119-7-hjl.tools@gmail.com>","list_archive_url":null,"date":"2023-06-05T15:32:21","name":"[v3,6/7] ld: Add tests for -z nosectionheader and --strip-section-headers","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230605153222.1728119-7-hjl.tools@gmail.com/mbox/"},{"id":103350,"url":"https://patchwork.plctlab.org/api/1.2/patches/103350/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230605153222.1728119-8-hjl.tools@gmail.com/","msgid":"<20230605153222.1728119-8-hjl.tools@gmail.com>","list_archive_url":null,"date":"2023-06-05T15:32:22","name":"[v3,7/7] ld: Add -z nosectionheader test to bootstrap.exp","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230605153222.1728119-8-hjl.tools@gmail.com/mbox/"},{"id":103383,"url":"https://patchwork.plctlab.org/api/1.2/patches/103383/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230605163327.1864428-1-hjl.tools@gmail.com/","msgid":"<20230605163327.1864428-1-hjl.tools@gmail.com>","list_archive_url":null,"date":"2023-06-05T16:33:27","name":"ELF: Add \"#pass\" to ld-elf/pr30508.d","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230605163327.1864428-1-hjl.tools@gmail.com/mbox/"},{"id":103509,"url":"https://patchwork.plctlab.org/api/1.2/patches/103509/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230605214658.693003-1-indu.bhagat@oracle.com/","msgid":"<20230605214658.693003-1-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-06-05T21:46:58","name":"[COMMITTED] libsframe: avoid unnecessary type casts","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230605214658.693003-1-indu.bhagat@oracle.com/mbox/"},{"id":103542,"url":"https://patchwork.plctlab.org/api/1.2/patches/103542/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230606040315.4000351-1-yunqiang.su@cipunited.com/","msgid":"<20230606040315.4000351-1-yunqiang.su@cipunited.com>","list_archive_url":null,"date":"2023-06-06T04:03:13","name":"[v2,1/3] MIPS: disable fix-rm7000-2 and llpscp-64 if not has_newabi","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230606040315.4000351-1-yunqiang.su@cipunited.com/mbox/"},{"id":103543,"url":"https://patchwork.plctlab.org/api/1.2/patches/103543/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230606040315.4000351-2-yunqiang.su@cipunited.com/","msgid":"<20230606040315.4000351-2-yunqiang.su@cipunited.com>","list_archive_url":null,"date":"2023-06-06T04:03:14","name":"[v2,2/3] MIPS: Ignore the symbol index for comdat-reloc-r6.d","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230606040315.4000351-2-yunqiang.su@cipunited.com/mbox/"},{"id":103544,"url":"https://patchwork.plctlab.org/api/1.2/patches/103544/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230606040315.4000351-3-yunqiang.su@cipunited.com/","msgid":"<20230606040315.4000351-3-yunqiang.su@cipunited.com>","list_archive_url":null,"date":"2023-06-06T04:03:15","name":"[v2,3/3] MIPS: Fix Irix gas testcases","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230606040315.4000351-3-yunqiang.su@cipunited.com/mbox/"},{"id":103614,"url":"https://patchwork.plctlab.org/api/1.2/patches/103614/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230606074856.3463253-1-lei.wang@oss.cipunited.com/","msgid":"<20230606074856.3463253-1-lei.wang@oss.cipunited.com>","list_archive_url":null,"date":"2023-06-06T07:49:13","name":"[v2] Add GINV(+VIRT) ASE for MIPSr6","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230606074856.3463253-1-lei.wang@oss.cipunited.com/mbox/"},{"id":104005,"url":"https://patchwork.plctlab.org/api/1.2/patches/104005/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230606175846.399377-2-hjl.tools@gmail.com/","msgid":"<20230606175846.399377-2-hjl.tools@gmail.com>","list_archive_url":null,"date":"2023-06-06T17:58:40","name":"[v4,1/7] ELF: Strip section header in ELF objects","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230606175846.399377-2-hjl.tools@gmail.com/mbox/"},{"id":104004,"url":"https://patchwork.plctlab.org/api/1.2/patches/104004/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230606175846.399377-3-hjl.tools@gmail.com/","msgid":"<20230606175846.399377-3-hjl.tools@gmail.com>","list_archive_url":null,"date":"2023-06-06T17:58:41","name":"[v4,2/7] ELF: Discard non-alloc sections without section header","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230606175846.399377-3-hjl.tools@gmail.com/mbox/"},{"id":104009,"url":"https://patchwork.plctlab.org/api/1.2/patches/104009/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230606175846.399377-4-hjl.tools@gmail.com/","msgid":"<20230606175846.399377-4-hjl.tools@gmail.com>","list_archive_url":null,"date":"2023-06-06T17:58:42","name":"[v4,3/7] bfd: Improve nm and objdump without section header","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230606175846.399377-4-hjl.tools@gmail.com/mbox/"},{"id":104008,"url":"https://patchwork.plctlab.org/api/1.2/patches/104008/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230606175846.399377-5-hjl.tools@gmail.com/","msgid":"<20230606175846.399377-5-hjl.tools@gmail.com>","list_archive_url":null,"date":"2023-06-06T17:58:43","name":"[v4,4/7] ld: Add simple tests for -z nosectionheader","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230606175846.399377-5-hjl.tools@gmail.com/mbox/"},{"id":104006,"url":"https://patchwork.plctlab.org/api/1.2/patches/104006/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230606175846.399377-6-hjl.tools@gmail.com/","msgid":"<20230606175846.399377-6-hjl.tools@gmail.com>","list_archive_url":null,"date":"2023-06-06T17:58:44","name":"[v4,5/7] binutils: Add a --strip-section-headers test","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230606175846.399377-6-hjl.tools@gmail.com/mbox/"},{"id":104010,"url":"https://patchwork.plctlab.org/api/1.2/patches/104010/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230606175846.399377-7-hjl.tools@gmail.com/","msgid":"<20230606175846.399377-7-hjl.tools@gmail.com>","list_archive_url":null,"date":"2023-06-06T17:58:45","name":"[v4,6/7] ld: Add tests for -z nosectionheader and --strip-section-headers","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230606175846.399377-7-hjl.tools@gmail.com/mbox/"},{"id":104007,"url":"https://patchwork.plctlab.org/api/1.2/patches/104007/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230606175846.399377-8-hjl.tools@gmail.com/","msgid":"<20230606175846.399377-8-hjl.tools@gmail.com>","list_archive_url":null,"date":"2023-06-06T17:58:46","name":"[v4,7/7] ld: Add -z nosectionheader test to bootstrap.exp","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230606175846.399377-8-hjl.tools@gmail.com/mbox/"},{"id":104157,"url":"https://patchwork.plctlab.org/api/1.2/patches/104157/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230607001219.1262641-1-indu.bhagat@oracle.com/","msgid":"<20230607001219.1262641-1-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-06-07T00:12:19","name":"[COMMITTED] libsframe: fix cosmetic issues and typos","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230607001219.1262641-1-indu.bhagat@oracle.com/mbox/"},{"id":104187,"url":"https://patchwork.plctlab.org/api/1.2/patches/104187/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZH/kqvEBzDihSIXm@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-06-07T02:00:10","name":"objcopy memory leaks after errors","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZH/kqvEBzDihSIXm@squeak.grove.modra.org/mbox/"},{"id":104188,"url":"https://patchwork.plctlab.org/api/1.2/patches/104188/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZH/kzy91Kw/7oe/D@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-06-07T02:00:47","name":"bfd/elf.c strtab memory leak","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZH/kzy91Kw/7oe/D@squeak.grove.modra.org/mbox/"},{"id":104189,"url":"https://patchwork.plctlab.org/api/1.2/patches/104189/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZH/lDst5YNSnH53k@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-06-07T02:01:50","name":"Memory leaks in bfd/vms-lib.c","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZH/lDst5YNSnH53k@squeak.grove.modra.org/mbox/"},{"id":104228,"url":"https://patchwork.plctlab.org/api/1.2/patches/104228/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZIANNwcg5+tkbCiv@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-06-07T04:53:11","name":"_bfd_free_cached_info","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZIANNwcg5+tkbCiv@squeak.grove.modra.org/mbox/"},{"id":104370,"url":"https://patchwork.plctlab.org/api/1.2/patches/104370/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZIBPFJst5wp+jM/O@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-06-07T09:34:12","name":"ld-elf/eh5 remove xfail hppa64","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZIBPFJst5wp+jM/O@squeak.grove.modra.org/mbox/"},{"id":104777,"url":"https://patchwork.plctlab.org/api/1.2/patches/104777/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230607235757.4174552-1-indu.bhagat@oracle.com/","msgid":"<20230607235757.4174552-1-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-06-07T23:57:57","name":"[COMMITTED] libsframe: reuse static function sframe_decoder_get_funcdesc_at_index","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230607235757.4174552-1-indu.bhagat@oracle.com/mbox/"},{"id":104818,"url":"https://patchwork.plctlab.org/api/1.2/patches/104818/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230608044935.4183325-2-indu.bhagat@oracle.com/","msgid":"<20230608044935.4183325-2-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-06-08T04:49:34","name":"[1/2] libsframe: update the semantics of sframe_fre_get_ra_offset","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230608044935.4183325-2-indu.bhagat@oracle.com/mbox/"},{"id":104819,"url":"https://patchwork.plctlab.org/api/1.2/patches/104819/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230608044935.4183325-3-indu.bhagat@oracle.com/","msgid":"<20230608044935.4183325-3-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-06-08T04:49:35","name":"[2/2] libsframe: update the semantics of sframe_fre_get_fp_offset","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230608044935.4183325-3-indu.bhagat@oracle.com/mbox/"},{"id":105015,"url":"https://patchwork.plctlab.org/api/1.2/patches/105015/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230608155214.32435-1-palmer@rivosinc.com/","msgid":"<20230608155214.32435-1-palmer@rivosinc.com>","list_archive_url":null,"date":"2023-06-08T15:52:14","name":"RISC-V: Move __global_pointer$ to .sdata","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230608155214.32435-1-palmer@rivosinc.com/mbox/"},{"id":105186,"url":"https://patchwork.plctlab.org/api/1.2/patches/105186/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230609004717.30486-1-nelson@rivosinc.com/","msgid":"<20230609004717.30486-1-nelson@rivosinc.com>","list_archive_url":null,"date":"2023-06-09T00:47:17","name":"RISC-V: PR29823, defined the missing elf_backend_obj_attrs_handle_unknown.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230609004717.30486-1-nelson@rivosinc.com/mbox/"},{"id":105286,"url":"https://patchwork.plctlab.org/api/1.2/patches/105286/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZILCF8nLyVb4FoJ4@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-06-09T06:09:27","name":"ecoff find_nearest_line and final link leaks","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZILCF8nLyVb4FoJ4@squeak.grove.modra.org/mbox/"},{"id":105287,"url":"https://patchwork.plctlab.org/api/1.2/patches/105287/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZILCNa0O8HoJZZAo@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-06-09T06:09:57","name":"readelf/objdump remember_state memory leaks","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZILCNa0O8HoJZZAo@squeak.grove.modra.org/mbox/"},{"id":105603,"url":"https://patchwork.plctlab.org/api/1.2/patches/105603/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ad4cdc08-a78e-49ee-d650-bd5a8ebc164b@suse.com/","msgid":"","list_archive_url":null,"date":"2023-06-09T12:30:26","name":"x86: shrink Masking insn attribute to a single bit (boolean)","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ad4cdc08-a78e-49ee-d650-bd5a8ebc164b@suse.com/mbox/"},{"id":105785,"url":"https://patchwork.plctlab.org/api/1.2/patches/105785/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230609192822.2471957-1-indu.bhagat@oracle.com/","msgid":"<20230609192822.2471957-1-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-06-09T19:28:21","name":"[COMMITTED] libsframe: fix sframe_find_fre for pltN entries","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230609192822.2471957-1-indu.bhagat@oracle.com/mbox/"},{"id":105786,"url":"https://patchwork.plctlab.org/api/1.2/patches/105786/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230609192822.2471957-2-indu.bhagat@oracle.com/","msgid":"<20230609192822.2471957-2-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-06-09T19:28:22","name":"[COMMITTED] libsframe: testsuite: add sframe_find_fre tests for pltN entries","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230609192822.2471957-2-indu.bhagat@oracle.com/mbox/"},{"id":106323,"url":"https://patchwork.plctlab.org/api/1.2/patches/106323/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230612083649.907511-1-chenfeiyang@loongson.cn/","msgid":"<20230612083649.907511-1-chenfeiyang@loongson.cn>","list_archive_url":null,"date":"2023-06-12T08:36:49","name":"LoongArch: Add fcsr register names support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230612083649.907511-1-chenfeiyang@loongson.cn/mbox/"},{"id":107171,"url":"https://patchwork.plctlab.org/api/1.2/patches/107171/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230613080712.1651120-1-mengqinggang@loongson.cn/","msgid":"<20230613080712.1651120-1-mengqinggang@loongson.cn>","list_archive_url":null,"date":"2023-06-13T08:07:12","name":"LoongArch: Fix ld \"undefined reference\" error with --enable-shared","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230613080712.1651120-1-mengqinggang@loongson.cn/mbox/"},{"id":107373,"url":"https://patchwork.plctlab.org/api/1.2/patches/107373/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230613132342.783814-2-jiawei@iscas.ac.cn/","msgid":"<20230613132342.783814-2-jiawei@iscas.ac.cn>","list_archive_url":null,"date":"2023-06-13T13:23:39","name":"[1/4] RISC-V: Minimal support of ZC extensions.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230613132342.783814-2-jiawei@iscas.ac.cn/mbox/"},{"id":107375,"url":"https://patchwork.plctlab.org/api/1.2/patches/107375/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230613132342.783814-3-jiawei@iscas.ac.cn/","msgid":"<20230613132342.783814-3-jiawei@iscas.ac.cn>","list_archive_url":null,"date":"2023-06-13T13:23:40","name":"[2/4] RISC-V: Add Zca extension testcases.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230613132342.783814-3-jiawei@iscas.ac.cn/mbox/"},{"id":107377,"url":"https://patchwork.plctlab.org/api/1.2/patches/107377/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230613132342.783814-4-jiawei@iscas.ac.cn/","msgid":"<20230613132342.783814-4-jiawei@iscas.ac.cn>","list_archive_url":null,"date":"2023-06-13T13:23:41","name":"[3/4] RISC-V: Add Zcf extension testcases.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230613132342.783814-4-jiawei@iscas.ac.cn/mbox/"},{"id":107378,"url":"https://patchwork.plctlab.org/api/1.2/patches/107378/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230613132342.783814-5-jiawei@iscas.ac.cn/","msgid":"<20230613132342.783814-5-jiawei@iscas.ac.cn>","list_archive_url":null,"date":"2023-06-13T13:23:42","name":"[4/4] RISC-V: Add Zcd extension testcases.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230613132342.783814-5-jiawei@iscas.ac.cn/mbox/"},{"id":107381,"url":"https://patchwork.plctlab.org/api/1.2/patches/107381/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230613133851.786238-1-jiawei@iscas.ac.cn/","msgid":"<20230613133851.786238-1-jiawei@iscas.ac.cn>","list_archive_url":null,"date":"2023-06-13T13:38:50","name":"[1/2] RISC-V: Add Zcb extension supports.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230613133851.786238-1-jiawei@iscas.ac.cn/mbox/"},{"id":107380,"url":"https://patchwork.plctlab.org/api/1.2/patches/107380/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230613133851.786238-2-jiawei@iscas.ac.cn/","msgid":"<20230613133851.786238-2-jiawei@iscas.ac.cn>","list_archive_url":null,"date":"2023-06-13T13:38:51","name":"[2/2] RISC-V: Add Zcb extension testcases.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230613133851.786238-2-jiawei@iscas.ac.cn/mbox/"},{"id":107632,"url":"https://patchwork.plctlab.org/api/1.2/patches/107632/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230614000148.10989-2-david@davidgf.es/","msgid":"<20230614000148.10989-2-david@davidgf.es>","list_archive_url":null,"date":"2023-06-14T00:01:46","name":"[v2,1/3] Add MIPS Allegrex CPU as a MIPS2-based CPU","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230614000148.10989-2-david@davidgf.es/mbox/"},{"id":107631,"url":"https://patchwork.plctlab.org/api/1.2/patches/107631/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230614000148.10989-3-david@davidgf.es/","msgid":"<20230614000148.10989-3-david@davidgf.es>","list_archive_url":null,"date":"2023-06-14T00:01:47","name":"[v2,2/3] Add rotation instructions to MIPS Allegrex CPU","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230614000148.10989-3-david@davidgf.es/mbox/"},{"id":107630,"url":"https://patchwork.plctlab.org/api/1.2/patches/107630/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230614000148.10989-4-david@davidgf.es/","msgid":"<20230614000148.10989-4-david@davidgf.es>","list_archive_url":null,"date":"2023-06-14T00:01:48","name":"[v2,3/3] Add additional missing Allegrex CPU instructions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230614000148.10989-4-david@davidgf.es/mbox/"},{"id":107698,"url":"https://patchwork.plctlab.org/api/1.2/patches/107698/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZIlIv23B00XAlvGU@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-06-14T04:57:35","name":"asprintf memory leaks","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZIlIv23B00XAlvGU@squeak.grove.modra.org/mbox/"},{"id":107914,"url":"https://patchwork.plctlab.org/api/1.2/patches/107914/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/mvma5x245vb.fsf@suse.de/","msgid":"","list_archive_url":null,"date":"2023-06-14T11:53:44","name":"riscv: Use run-time endianess for floating point literals","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/mvma5x245vb.fsf@suse.de/mbox/"},{"id":107999,"url":"https://patchwork.plctlab.org/api/1.2/patches/107999/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/87ttva3xik.fsf@redhat.com/","msgid":"<87ttva3xik.fsf@redhat.com>","list_archive_url":null,"date":"2023-06-14T14:54:11","name":"commit: Add expected failures for some bfin linker tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/87ttva3xik.fsf@redhat.com/mbox/"},{"id":108238,"url":"https://patchwork.plctlab.org/api/1.2/patches/108238/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZIp6D6Of0QqK1XT0@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-06-15T02:40:15","name":"vms write_archive memory leaks","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZIp6D6Of0QqK1XT0@squeak.grove.modra.org/mbox/"},{"id":108244,"url":"https://patchwork.plctlab.org/api/1.2/patches/108244/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.DEB.2.21.2306150402280.64925@angie.orcam.me.uk/","msgid":"","list_archive_url":null,"date":"2023-06-15T03:50:33","name":"[committed] GAS/doc: Correct Tag_GNU_MIPS_ABI_MSA attribute description","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.DEB.2.21.2306150402280.64925@angie.orcam.me.uk/mbox/"},{"id":108247,"url":"https://patchwork.plctlab.org/api/1.2/patches/108247/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.DEB.2.21.2306150403370.64925@angie.orcam.me.uk/","msgid":"","list_archive_url":null,"date":"2023-06-15T03:51:53","name":"[committed] MIPS/GAS/testsuite: Fix `-modd-spreg'\''/`-mno-odd-spreg'\'' test invocations","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.DEB.2.21.2306150403370.64925@angie.orcam.me.uk/mbox/"},{"id":108432,"url":"https://patchwork.plctlab.org/api/1.2/patches/108432/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/AM6PR03MB49843D0F7C0438ADEB19172E985BA@AM6PR03MB4984.eurprd03.prod.outlook.com/","msgid":"","list_archive_url":null,"date":"2023-06-15T11:09:26","name":"[0/2] riscv: Fix gas when encoding BE floats/doubles","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/AM6PR03MB49843D0F7C0438ADEB19172E985BA@AM6PR03MB4984.eurprd03.prod.outlook.com/mbox/"},{"id":108551,"url":"https://patchwork.plctlab.org/api/1.2/patches/108551/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.DEB.2.21.2306151520460.64925@angie.orcam.me.uk/","msgid":"","list_archive_url":null,"date":"2023-06-15T14:24:56","name":"[committed] binutils/NEWS: Mention Sony Allegrex MIPS CPU support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.DEB.2.21.2306151520460.64925@angie.orcam.me.uk/mbox/"},{"id":108800,"url":"https://patchwork.plctlab.org/api/1.2/patches/108800/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230616031610.3982906-1-chenfeiyang@loongson.cn/","msgid":"<20230616031610.3982906-1-chenfeiyang@loongson.cn>","list_archive_url":null,"date":"2023-06-16T03:16:10","name":"[v2] LoongArch: Support referring to FCSRs as $fcsrX","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230616031610.3982906-1-chenfeiyang@loongson.cn/mbox/"},{"id":108836,"url":"https://patchwork.plctlab.org/api/1.2/patches/108836/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230616062504.1713904-2-yunqiang.su@cipunited.com/","msgid":"<20230616062504.1713904-2-yunqiang.su@cipunited.com>","list_archive_url":null,"date":"2023-06-16T06:24:54","name":"[v3,1/7] MIPS: Gas: alter 64 or 32 for mipsisa triples if march is implicit","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230616062504.1713904-2-yunqiang.su@cipunited.com/mbox/"},{"id":108840,"url":"https://patchwork.plctlab.org/api/1.2/patches/108840/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230616062504.1713904-3-yunqiang.su@cipunited.com/","msgid":"<20230616062504.1713904-3-yunqiang.su@cipunited.com>","list_archive_url":null,"date":"2023-06-16T06:24:55","name":"[v3,2/7] MIPS: default r6 if vendor is img","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230616062504.1713904-3-yunqiang.su@cipunited.com/mbox/"},{"id":108842,"url":"https://patchwork.plctlab.org/api/1.2/patches/108842/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230616062504.1713904-4-yunqiang.su@cipunited.com/","msgid":"<20230616062504.1713904-4-yunqiang.su@cipunited.com>","list_archive_url":null,"date":"2023-06-16T06:24:56","name":"[v3,2/7] MIPS: Set r6 as default arch if vendor is img","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230616062504.1713904-4-yunqiang.su@cipunited.com/mbox/"},{"id":108847,"url":"https://patchwork.plctlab.org/api/1.2/patches/108847/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230616062504.1713904-5-yunqiang.su@cipunited.com/","msgid":"<20230616062504.1713904-5-yunqiang.su@cipunited.com>","list_archive_url":null,"date":"2023-06-16T06:24:57","name":"[v3,3/7] MIPS: fix r6 testsuites","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230616062504.1713904-5-yunqiang.su@cipunited.com/mbox/"},{"id":108843,"url":"https://patchwork.plctlab.org/api/1.2/patches/108843/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230616062504.1713904-6-yunqiang.su@cipunited.com/","msgid":"<20230616062504.1713904-6-yunqiang.su@cipunited.com>","list_archive_url":null,"date":"2023-06-16T06:24:58","name":"[v3,3/7] MIPS: Fix r6 testsuites","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230616062504.1713904-6-yunqiang.su@cipunited.com/mbox/"},{"id":108851,"url":"https://patchwork.plctlab.org/api/1.2/patches/108851/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230616062504.1713904-7-yunqiang.su@cipunited.com/","msgid":"<20230616062504.1713904-7-yunqiang.su@cipunited.com>","list_archive_url":null,"date":"2023-06-16T06:24:59","name":"[v3,4/7] MIPS: fix -gnuabi64 testsuite","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230616062504.1713904-7-yunqiang.su@cipunited.com/mbox/"},{"id":108844,"url":"https://patchwork.plctlab.org/api/1.2/patches/108844/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230616062504.1713904-8-yunqiang.su@cipunited.com/","msgid":"<20230616062504.1713904-8-yunqiang.su@cipunited.com>","list_archive_url":null,"date":"2023-06-16T06:25:00","name":"[v3,4/7] MIPS: Fix -gnuabi64 testsuite","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230616062504.1713904-8-yunqiang.su@cipunited.com/mbox/"},{"id":108848,"url":"https://patchwork.plctlab.org/api/1.2/patches/108848/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230616062504.1713904-9-yunqiang.su@cipunited.com/","msgid":"<20230616062504.1713904-9-yunqiang.su@cipunited.com>","list_archive_url":null,"date":"2023-06-16T06:25:01","name":"[v3,5/7] MIPS: fix some ld testcases with compiler","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230616062504.1713904-9-yunqiang.su@cipunited.com/mbox/"},{"id":108846,"url":"https://patchwork.plctlab.org/api/1.2/patches/108846/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230616062504.1713904-10-yunqiang.su@cipunited.com/","msgid":"<20230616062504.1713904-10-yunqiang.su@cipunited.com>","list_archive_url":null,"date":"2023-06-16T06:25:02","name":"[v3,5/7] MIPS: Fix some ld testcases with compiler","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230616062504.1713904-10-yunqiang.su@cipunited.com/mbox/"},{"id":108857,"url":"https://patchwork.plctlab.org/api/1.2/patches/108857/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230616062504.1713904-11-yunqiang.su@cipunited.com/","msgid":"<20230616062504.1713904-11-yunqiang.su@cipunited.com>","list_archive_url":null,"date":"2023-06-16T06:25:03","name":"[v3,6/7] MIPS: disable fix-rm7000-2 and llpscp-64 if not has_newabi","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230616062504.1713904-11-yunqiang.su@cipunited.com/mbox/"},{"id":108863,"url":"https://patchwork.plctlab.org/api/1.2/patches/108863/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230616062504.1713904-12-yunqiang.su@cipunited.com/","msgid":"<20230616062504.1713904-12-yunqiang.su@cipunited.com>","list_archive_url":null,"date":"2023-06-16T06:25:04","name":"[v3,7/7] MIPS: Fix Irix gas testcases","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230616062504.1713904-12-yunqiang.su@cipunited.com/mbox/"},{"id":108869,"url":"https://patchwork.plctlab.org/api/1.2/patches/108869/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230616063412.1715024-2-yunqiang.su@cipunited.com/","msgid":"<20230616063412.1715024-2-yunqiang.su@cipunited.com>","list_archive_url":null,"date":"2023-06-16T06:34:06","name":"[v4,1/7] MIPS: Gas: alter 64 or 32 for mipsisa triples if march is implicit","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230616063412.1715024-2-yunqiang.su@cipunited.com/mbox/"},{"id":108870,"url":"https://patchwork.plctlab.org/api/1.2/patches/108870/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230616063412.1715024-3-yunqiang.su@cipunited.com/","msgid":"<20230616063412.1715024-3-yunqiang.su@cipunited.com>","list_archive_url":null,"date":"2023-06-16T06:34:07","name":"[v4,2/7] MIPS: Set r6 as default arch if vendor is img","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230616063412.1715024-3-yunqiang.su@cipunited.com/mbox/"},{"id":108878,"url":"https://patchwork.plctlab.org/api/1.2/patches/108878/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230616063412.1715024-4-yunqiang.su@cipunited.com/","msgid":"<20230616063412.1715024-4-yunqiang.su@cipunited.com>","list_archive_url":null,"date":"2023-06-16T06:34:08","name":"[v4,3/7] MIPS: Fix r6 testsuites","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230616063412.1715024-4-yunqiang.su@cipunited.com/mbox/"},{"id":108875,"url":"https://patchwork.plctlab.org/api/1.2/patches/108875/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230616063412.1715024-5-yunqiang.su@cipunited.com/","msgid":"<20230616063412.1715024-5-yunqiang.su@cipunited.com>","list_archive_url":null,"date":"2023-06-16T06:34:09","name":"[v4,4/7] MIPS: Fix -gnuabi64 testsuite","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230616063412.1715024-5-yunqiang.su@cipunited.com/mbox/"},{"id":108876,"url":"https://patchwork.plctlab.org/api/1.2/patches/108876/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230616063412.1715024-6-yunqiang.su@cipunited.com/","msgid":"<20230616063412.1715024-6-yunqiang.su@cipunited.com>","list_archive_url":null,"date":"2023-06-16T06:34:10","name":"[v4,5/7] MIPS: Fix some ld testcases with compiler","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230616063412.1715024-6-yunqiang.su@cipunited.com/mbox/"},{"id":108874,"url":"https://patchwork.plctlab.org/api/1.2/patches/108874/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230616063412.1715024-7-yunqiang.su@cipunited.com/","msgid":"<20230616063412.1715024-7-yunqiang.su@cipunited.com>","list_archive_url":null,"date":"2023-06-16T06:34:11","name":"[v4,6/7] MIPS: Disable fix-rm7000-2 and llpscp-64 if not has_newabi","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230616063412.1715024-7-yunqiang.su@cipunited.com/mbox/"},{"id":108877,"url":"https://patchwork.plctlab.org/api/1.2/patches/108877/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230616063412.1715024-8-yunqiang.su@cipunited.com/","msgid":"<20230616063412.1715024-8-yunqiang.su@cipunited.com>","list_archive_url":null,"date":"2023-06-16T06:34:12","name":"[v4,7/7] MIPS: Fix Irix gas testcases","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230616063412.1715024-8-yunqiang.su@cipunited.com/mbox/"},{"id":108891,"url":"https://patchwork.plctlab.org/api/1.2/patches/108891/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230616072536.1805704-1-yunqiang.su@cipunited.com/","msgid":"<20230616072536.1805704-1-yunqiang.su@cipunited.com>","list_archive_url":null,"date":"2023-06-16T07:25:35","name":"[v3,1/2] MIPS: Add MT ASE support for micromips32","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230616072536.1805704-1-yunqiang.su@cipunited.com/mbox/"},{"id":108892,"url":"https://patchwork.plctlab.org/api/1.2/patches/108892/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230616072536.1805704-2-yunqiang.su@cipunited.com/","msgid":"<20230616072536.1805704-2-yunqiang.su@cipunited.com>","list_archive_url":null,"date":"2023-06-16T07:25:36","name":"[v3,2/2] MIPS: Sync oprand char usage between mips and micromips","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230616072536.1805704-2-yunqiang.su@cipunited.com/mbox/"},{"id":108895,"url":"https://patchwork.plctlab.org/api/1.2/patches/108895/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/503caac8-8824-823a-81c2-762cba207cb6@suse.com/","msgid":"<503caac8-8824-823a-81c2-762cba207cb6@suse.com>","list_archive_url":null,"date":"2023-06-16T07:30:41","name":"[1/4] x86: optimize pre-AVX512 {,V}PCMPEQQ with identical sources","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/503caac8-8824-823a-81c2-762cba207cb6@suse.com/mbox/"},{"id":108896,"url":"https://patchwork.plctlab.org/api/1.2/patches/108896/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7141b586-9711-aef0-7f28-5d4489478f1b@suse.com/","msgid":"<7141b586-9711-aef0-7f28-5d4489478f1b@suse.com>","list_archive_url":null,"date":"2023-06-16T07:31:12","name":"[2/4] x86: optimize pre-AVX512 {,V}PCMPGT* with identical sources","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7141b586-9711-aef0-7f28-5d4489478f1b@suse.com/mbox/"},{"id":108899,"url":"https://patchwork.plctlab.org/api/1.2/patches/108899/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3e1b884e-7312-8546-ebdc-ac513a199858@suse.com/","msgid":"<3e1b884e-7312-8546-ebdc-ac513a199858@suse.com>","list_archive_url":null,"date":"2023-06-16T07:31:41","name":"[3/4] x86: optimize 128-bit VPBROADCASTQ to VPUNPCKLQDQ","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3e1b884e-7312-8546-ebdc-ac513a199858@suse.com/mbox/"},{"id":108900,"url":"https://patchwork.plctlab.org/api/1.2/patches/108900/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/08bf9dc9-5616-7dce-a094-d2ea799c92bf@suse.com/","msgid":"<08bf9dc9-5616-7dce-a094-d2ea799c92bf@suse.com>","list_archive_url":null,"date":"2023-06-16T07:32:40","name":"[4/4] x86: provide a 128-bit VBROADCASTSD pseudo","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/08bf9dc9-5616-7dce-a094-d2ea799c92bf@suse.com/mbox/"},{"id":109009,"url":"https://patchwork.plctlab.org/api/1.2/patches/109009/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f8f64771-eb63-2df3-b03b-8ed1cf3b4310@suse.com/","msgid":"","list_archive_url":null,"date":"2023-06-16T10:15:29","name":"[1/5] x86: re-work EVEX-z-without-masking check","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f8f64771-eb63-2df3-b03b-8ed1cf3b4310@suse.com/mbox/"},{"id":109010,"url":"https://patchwork.plctlab.org/api/1.2/patches/109010/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c7e5b576-f830-7493-74c1-66c05155fbec@suse.com/","msgid":"","list_archive_url":null,"date":"2023-06-16T10:15:55","name":"[2/5] x86: flag EVEX.z set when destination is a mask register","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c7e5b576-f830-7493-74c1-66c05155fbec@suse.com/mbox/"},{"id":109011,"url":"https://patchwork.plctlab.org/api/1.2/patches/109011/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/65872bf7-36c2-0a0a-8992-38a0843a897d@suse.com/","msgid":"<65872bf7-36c2-0a0a-8992-38a0843a897d@suse.com>","list_archive_url":null,"date":"2023-06-16T10:16:20","name":"[3/5] x86: flag EVEX.z set when destination is memory","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/65872bf7-36c2-0a0a-8992-38a0843a897d@suse.com/mbox/"},{"id":109013,"url":"https://patchwork.plctlab.org/api/1.2/patches/109013/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2574a7d2-68aa-70e3-c5da-fc726c952c22@suse.com/","msgid":"<2574a7d2-68aa-70e3-c5da-fc726c952c22@suse.com>","list_archive_url":null,"date":"2023-06-16T10:16:44","name":"[4/5] x86: flag EVEX masking when destination is GPR(-like)","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2574a7d2-68aa-70e3-c5da-fc726c952c22@suse.com/mbox/"},{"id":109017,"url":"https://patchwork.plctlab.org/api/1.2/patches/109017/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/33c2fa9f-1f8e-bed0-8653-39eb876fb0b3@suse.com/","msgid":"<33c2fa9f-1f8e-bed0-8653-39eb876fb0b3@suse.com>","list_archive_url":null,"date":"2023-06-16T10:17:26","name":"[5/5] x86: flag bad EVEX masking for miscellaneous insns","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/33c2fa9f-1f8e-bed0-8653-39eb876fb0b3@suse.com/mbox/"},{"id":109088,"url":"https://patchwork.plctlab.org/api/1.2/patches/109088/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/bd3adbb3-02d0-3fea-f154-ece44bed7b60@suse.com/","msgid":"","list_archive_url":null,"date":"2023-06-16T12:34:06","name":"x86: fix expansion of %XV","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/bd3adbb3-02d0-3fea-f154-ece44bed7b60@suse.com/mbox/"},{"id":109639,"url":"https://patchwork.plctlab.org/api/1.2/patches/109639/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/648f4180.a70a0220.a7021.407c@mx.google.com/","msgid":"<648f4180.a70a0220.a7021.407c@mx.google.com>","list_archive_url":null,"date":"2023-06-18T17:40:13","name":"[V3] optimize handle_COMDAT","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/648f4180.a70a0220.a7021.407c@mx.google.com/mbox/"},{"id":110435,"url":"https://patchwork.plctlab.org/api/1.2/patches/110435/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/AM6PR03MB49848E63E54AAB7B7C0D80E4985CA@AM6PR03MB4984.eurprd03.prod.outlook.com/","msgid":"","list_archive_url":null,"date":"2023-06-20T11:43:07","name":"[0/1] riscv: Ensure LE instruction fetching","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/AM6PR03MB49848E63E54AAB7B7C0D80E4985CA@AM6PR03MB4984.eurprd03.prod.outlook.com/mbox/"},{"id":110613,"url":"https://patchwork.plctlab.org/api/1.2/patches/110613/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230620164436.432481-1-hjl.tools@gmail.com/","msgid":"<20230620164436.432481-1-hjl.tools@gmail.com>","list_archive_url":null,"date":"2023-06-20T16:44:36","name":"x86: Don'\''t check if AVX512 template requires AVX512VL","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230620164436.432481-1-hjl.tools@gmail.com/mbox/"},{"id":110703,"url":"https://patchwork.plctlab.org/api/1.2/patches/110703/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230620223204.629663-1-hjl.tools@gmail.com/","msgid":"<20230620223204.629663-1-hjl.tools@gmail.com>","list_archive_url":null,"date":"2023-06-20T22:32:04","name":"x86: Free the symbol buffer and the relocation buffer after use","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230620223204.629663-1-hjl.tools@gmail.com/mbox/"},{"id":110789,"url":"https://patchwork.plctlab.org/api/1.2/patches/110789/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZJKWtMcKv3ZBw0Cq@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-06-21T06:20:36","name":"macho-o.c don'\''t leak strtab","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZJKWtMcKv3ZBw0Cq@squeak.grove.modra.org/mbox/"},{"id":110790,"url":"https://patchwork.plctlab.org/api/1.2/patches/110790/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZJKW2M//EO8S5UUV@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-06-21T06:21:12","name":"elf32_arm_get_synthetic_symtab memory leak","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZJKW2M//EO8S5UUV@squeak.grove.modra.org/mbox/"},{"id":110832,"url":"https://patchwork.plctlab.org/api/1.2/patches/110832/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230621072732.1652861-1-lili.cui@intel.com/","msgid":"<20230621072732.1652861-1-lili.cui@intel.com>","list_archive_url":null,"date":"2023-06-21T07:27:32","name":"gprofng: Update intel url","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230621072732.1652861-1-lili.cui@intel.com/mbox/"},{"id":110979,"url":"https://patchwork.plctlab.org/api/1.2/patches/110979/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/87352l6qjc.fsf@redhat.com/","msgid":"<87352l6qjc.fsf@redhat.com>","list_archive_url":null,"date":"2023-06-21T10:47:03","name":"Commit: Fix PR 29072 test with --enable-default-execstack=no","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/87352l6qjc.fsf@redhat.com/mbox/"},{"id":110983,"url":"https://patchwork.plctlab.org/api/1.2/patches/110983/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/87zg4t5awt.fsf@redhat.com/","msgid":"<87zg4t5awt.fsf@redhat.com>","list_archive_url":null,"date":"2023-06-21T11:09:54","name":"Commit: Prune warnings about -z execstack when --enable-warn-execstack=yes has been used","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/87zg4t5awt.fsf@redhat.com/mbox/"},{"id":111025,"url":"https://patchwork.plctlab.org/api/1.2/patches/111025/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZJL9LBr/Zuvjc+Yv@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-06-21T13:37:48","name":"[GOLD] PR30536, ppc64el gold linker produces unusable clang-16 binary","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZJL9LBr/Zuvjc+Yv@squeak.grove.modra.org/mbox/"},{"id":111790,"url":"https://patchwork.plctlab.org/api/1.2/patches/111790/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230622193759.737009-1-hjl.tools@gmail.com/","msgid":"<20230622193759.737009-1-hjl.tools@gmail.com>","list_archive_url":null,"date":"2023-06-22T19:37:59","name":"Revert \"x86: Don'\''t check if AVX512 template requires AVX512VL\"","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230622193759.737009-1-hjl.tools@gmail.com/mbox/"},{"id":111837,"url":"https://patchwork.plctlab.org/api/1.2/patches/111837/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230622232510.49099-1-david@davidgf.es/","msgid":"<20230622232510.49099-1-david@davidgf.es>","list_archive_url":null,"date":"2023-06-22T23:25:09","name":"[1/2] Exclude trap instructions for MIPS Allegrex","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230622232510.49099-1-david@davidgf.es/mbox/"},{"id":111838,"url":"https://patchwork.plctlab.org/api/1.2/patches/111838/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230622232510.49099-2-david@davidgf.es/","msgid":"<20230622232510.49099-2-david@davidgf.es>","list_archive_url":null,"date":"2023-06-22T23:25:10","name":"[2/2] Adding missing MIPS Allegrex instruction","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230622232510.49099-2-david@davidgf.es/mbox/"},{"id":111911,"url":"https://patchwork.plctlab.org/api/1.2/patches/111911/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230623044448.2617101-2-indu.bhagat@oracle.com/","msgid":"<20230623044448.2617101-2-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-06-23T04:44:39","name":"[01/10] libsframe: add library versioning","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230623044448.2617101-2-indu.bhagat@oracle.com/mbox/"},{"id":111910,"url":"https://patchwork.plctlab.org/api/1.2/patches/111910/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230623044448.2617101-3-indu.bhagat@oracle.com/","msgid":"<20230623044448.2617101-3-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-06-23T04:44:40","name":"[02/10] libsframe: remove sframe_get_funcdesc_with_addr API","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230623044448.2617101-3-indu.bhagat@oracle.com/mbox/"},{"id":111917,"url":"https://patchwork.plctlab.org/api/1.2/patches/111917/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230623044448.2617101-4-indu.bhagat@oracle.com/","msgid":"<20230623044448.2617101-4-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-06-23T04:44:41","name":"[03/10] libsframe: add symbol versioning","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230623044448.2617101-4-indu.bhagat@oracle.com/mbox/"},{"id":111913,"url":"https://patchwork.plctlab.org/api/1.2/patches/111913/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230623044448.2617101-5-indu.bhagat@oracle.com/","msgid":"<20230623044448.2617101-5-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-06-23T04:44:42","name":"[04/10] libsframe: update the semantics of sframe_fre_get_ra_offset","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230623044448.2617101-5-indu.bhagat@oracle.com/mbox/"},{"id":111912,"url":"https://patchwork.plctlab.org/api/1.2/patches/111912/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230623044448.2617101-6-indu.bhagat@oracle.com/","msgid":"<20230623044448.2617101-6-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-06-23T04:44:43","name":"[05/10] libsframe: update the semantics of sframe_fre_get_fp_offset","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230623044448.2617101-6-indu.bhagat@oracle.com/mbox/"},{"id":111916,"url":"https://patchwork.plctlab.org/api/1.2/patches/111916/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230623044448.2617101-7-indu.bhagat@oracle.com/","msgid":"<20230623044448.2617101-7-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-06-23T04:44:44","name":"[06/10] libsframe: use uint32_t for fre_type and fde_type function args","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230623044448.2617101-7-indu.bhagat@oracle.com/mbox/"},{"id":111919,"url":"https://patchwork.plctlab.org/api/1.2/patches/111919/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230623044448.2617101-8-indu.bhagat@oracle.com/","msgid":"<20230623044448.2617101-8-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-06-23T04:44:45","name":"[07/10] bfd: libsframe: use uint32_t for return type of sframe_calc_fre_type","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230623044448.2617101-8-indu.bhagat@oracle.com/mbox/"},{"id":111914,"url":"https://patchwork.plctlab.org/api/1.2/patches/111914/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230623044448.2617101-9-indu.bhagat@oracle.com/","msgid":"<20230623044448.2617101-9-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-06-23T04:44:46","name":"[08/10] libsframe: use uint8_t instead of unsigned char for abi_arch","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230623044448.2617101-9-indu.bhagat@oracle.com/mbox/"},{"id":111915,"url":"https://patchwork.plctlab.org/api/1.2/patches/111915/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230623044448.2617101-10-indu.bhagat@oracle.com/","msgid":"<20230623044448.2617101-10-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-06-23T04:44:47","name":"[09/10] libsframe: use uint8_t for return type of sframe_fre_get_base_reg_id","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230623044448.2617101-10-indu.bhagat@oracle.com/mbox/"},{"id":111918,"url":"https://patchwork.plctlab.org/api/1.2/patches/111918/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230623044448.2617101-11-indu.bhagat@oracle.com/","msgid":"<20230623044448.2617101-11-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-06-23T04:44:48","name":"[10/10] binutils/NEWS: add note about upcoming libsframe changes","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230623044448.2617101-11-indu.bhagat@oracle.com/mbox/"},{"id":112090,"url":"https://patchwork.plctlab.org/api/1.2/patches/112090/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZJWCzBxYkM7kIEJT@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-06-23T11:32:28","name":"lto test fails with -fno-inline in CFLAGS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZJWCzBxYkM7kIEJT@squeak.grove.modra.org/mbox/"},{"id":112092,"url":"https://patchwork.plctlab.org/api/1.2/patches/112092/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZJWDWhpXisjeWfPg@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-06-23T11:34:50","name":"[GOLD] powerpc DT_RELACOUNT","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZJWDWhpXisjeWfPg@squeak.grove.modra.org/mbox/"},{"id":112093,"url":"https://patchwork.plctlab.org/api/1.2/patches/112093/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZJWEWYg0ZOpwoMSq@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-06-23T11:39:05","name":"[GOLD] Support setting DT_RELACOUNT late","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZJWEWYg0ZOpwoMSq@squeak.grove.modra.org/mbox/"},{"id":112094,"url":"https://patchwork.plctlab.org/api/1.2/patches/112094/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZJWEtp7jDRVNckRK@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-06-23T11:40:38","name":"[GOLD] PowerPC64 huge branch dynamic relocs","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZJWEtp7jDRVNckRK@squeak.grove.modra.org/mbox/"},{"id":112524,"url":"https://patchwork.plctlab.org/api/1.2/patches/112524/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230625083850.1028642-2-mengqinggang@loongson.cn/","msgid":"<20230625083850.1028642-2-mengqinggang@loongson.cn>","list_archive_url":null,"date":"2023-06-25T08:38:49","name":"[v0,1/2] LoongArch: gas: Add LSX and LASX instructions support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230625083850.1028642-2-mengqinggang@loongson.cn/mbox/"},{"id":112523,"url":"https://patchwork.plctlab.org/api/1.2/patches/112523/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230625083850.1028642-3-mengqinggang@loongson.cn/","msgid":"<20230625083850.1028642-3-mengqinggang@loongson.cn>","list_archive_url":null,"date":"2023-06-25T08:38:50","name":"[v0,2/2] LoongArch: gas: Add LSX and LASX instructions test","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230625083850.1028642-3-mengqinggang@loongson.cn/mbox/"},{"id":112533,"url":"https://patchwork.plctlab.org/api/1.2/patches/112533/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230625095540.1202120-1-mengqinggang@loongson.cn/","msgid":"<20230625095540.1202120-1-mengqinggang@loongson.cn>","list_archive_url":null,"date":"2023-06-25T09:55:40","name":"LoongArch: Add R_LARCH_64_PCREL relocation support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230625095540.1202120-1-mengqinggang@loongson.cn/mbox/"},{"id":112807,"url":"https://patchwork.plctlab.org/api/1.2/patches/112807/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230626091656.31782-1-krebbel@linux.ibm.com/","msgid":"<20230626091656.31782-1-krebbel@linux.ibm.com>","list_archive_url":null,"date":"2023-06-26T09:16:56","name":"ld - Add SYMBOL_ABI_ALIGNMENT variable and apply to __bss_start","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230626091656.31782-1-krebbel@linux.ibm.com/mbox/"},{"id":112947,"url":"https://patchwork.plctlab.org/api/1.2/patches/112947/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/87sfaez7ut.fsf@redhat.com/","msgid":"<87sfaez7ut.fsf@redhat.com>","list_archive_url":null,"date":"2023-06-26T13:11:22","name":"Commit: Sync config.sub and config.guess","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/87sfaez7ut.fsf@redhat.com/mbox/"},{"id":112954,"url":"https://patchwork.plctlab.org/api/1.2/patches/112954/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/bf42815b-bc8c-dc64-9393-43cdbb6fbb76@e124511.cambridge.arm.com/","msgid":"","list_archive_url":null,"date":"2023-06-26T13:50:57","name":"aarch64: Remove version dependencies from features","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/bf42815b-bc8c-dc64-9393-43cdbb6fbb76@e124511.cambridge.arm.com/mbox/"},{"id":112991,"url":"https://patchwork.plctlab.org/api/1.2/patches/112991/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/87pm5iz3fu.fsf@redhat.com/","msgid":"<87pm5iz3fu.fsf@redhat.com>","list_archive_url":null,"date":"2023-06-26T14:46:45","name":"Commit: Update libiberty sources","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/87pm5iz3fu.fsf@redhat.com/mbox/"},{"id":113014,"url":"https://patchwork.plctlab.org/api/1.2/patches/113014/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.LSU.2.20.2306261532320.13548@wotan.suse.de/","msgid":"","list_archive_url":null,"date":"2023-06-26T15:35:09","name":"section-match: Check parent archive name as well","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.LSU.2.20.2306261532320.13548@wotan.suse.de/mbox/"},{"id":113046,"url":"https://patchwork.plctlab.org/api/1.2/patches/113046/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/87mt0myyc2.fsf@redhat.com/","msgid":"<87mt0myyc2.fsf@redhat.com>","list_archive_url":null,"date":"2023-06-26T16:37:01","name":"Commit: Fix gas testsuite failures for non-ELF AArch64 toolchains","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/87mt0myyc2.fsf@redhat.com/mbox/"},{"id":113129,"url":"https://patchwork.plctlab.org/api/1.2/patches/113129/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230626214619.1808676-1-vladimir.mezentsev@oracle.com/","msgid":"<20230626214619.1808676-1-vladimir.mezentsev@oracle.com>","list_archive_url":null,"date":"2023-06-26T21:46:19","name":"gprofng: Add new tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230626214619.1808676-1-vladimir.mezentsev@oracle.com/mbox/"},{"id":113414,"url":"https://patchwork.plctlab.org/api/1.2/patches/113414/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230627124728.3563-1-lidie@eswincomputing.com/","msgid":"<20230627124728.3563-1-lidie@eswincomputing.com>","list_archive_url":null,"date":"2023-06-27T12:47:28","name":"[RISC-V] Optimize GP-relative addressing for linker.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230627124728.3563-1-lidie@eswincomputing.com/mbox/"},{"id":113448,"url":"https://patchwork.plctlab.org/api/1.2/patches/113448/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230627144250.16818-1-palmer@rivosinc.com/","msgid":"<20230627144250.16818-1-palmer@rivosinc.com>","list_archive_url":null,"date":"2023-06-27T14:42:50","name":"gas: NEWS: Add the latest RISC-V extensions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230627144250.16818-1-palmer@rivosinc.com/mbox/"},{"id":113562,"url":"https://patchwork.plctlab.org/api/1.2/patches/113562/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230627195126.1955051-1-indu.bhagat@oracle.com/","msgid":"<20230627195126.1955051-1-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-06-27T19:51:15","name":"[COMMITTED] libsframe: add library versioning","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230627195126.1955051-1-indu.bhagat@oracle.com/mbox/"},{"id":113563,"url":"https://patchwork.plctlab.org/api/1.2/patches/113563/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230627195126.1955051-2-indu.bhagat@oracle.com/","msgid":"<20230627195126.1955051-2-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-06-27T19:51:16","name":"[COMMITTED] libsframe: remove sframe_get_funcdesc_with_addr API","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230627195126.1955051-2-indu.bhagat@oracle.com/mbox/"},{"id":113574,"url":"https://patchwork.plctlab.org/api/1.2/patches/113574/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230627195126.1955051-3-indu.bhagat@oracle.com/","msgid":"<20230627195126.1955051-3-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-06-27T19:51:17","name":"[COMMITTED] libsframe: add symbol versioning","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230627195126.1955051-3-indu.bhagat@oracle.com/mbox/"},{"id":113569,"url":"https://patchwork.plctlab.org/api/1.2/patches/113569/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230627195126.1955051-4-indu.bhagat@oracle.com/","msgid":"<20230627195126.1955051-4-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-06-27T19:51:18","name":"[COMMITTED] libsframe: update the semantics of sframe_fre_get_ra_offset","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230627195126.1955051-4-indu.bhagat@oracle.com/mbox/"},{"id":113572,"url":"https://patchwork.plctlab.org/api/1.2/patches/113572/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230627195126.1955051-5-indu.bhagat@oracle.com/","msgid":"<20230627195126.1955051-5-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-06-27T19:51:19","name":"[COMMITTED] libsframe: update the semantics of sframe_fre_get_fp_offset","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230627195126.1955051-5-indu.bhagat@oracle.com/mbox/"},{"id":113570,"url":"https://patchwork.plctlab.org/api/1.2/patches/113570/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230627195126.1955051-6-indu.bhagat@oracle.com/","msgid":"<20230627195126.1955051-6-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-06-27T19:51:20","name":"[COMMITTED] libsframe: use uint32_t for fre_type and fde_type function args","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230627195126.1955051-6-indu.bhagat@oracle.com/mbox/"},{"id":113577,"url":"https://patchwork.plctlab.org/api/1.2/patches/113577/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230627195126.1955051-7-indu.bhagat@oracle.com/","msgid":"<20230627195126.1955051-7-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-06-27T19:51:21","name":"[COMMITTED] libsframe: bfd: use uint32_t for return type of sframe_calc_fre_type","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230627195126.1955051-7-indu.bhagat@oracle.com/mbox/"},{"id":113573,"url":"https://patchwork.plctlab.org/api/1.2/patches/113573/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230627195126.1955051-8-indu.bhagat@oracle.com/","msgid":"<20230627195126.1955051-8-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-06-27T19:51:22","name":"[COMMITTED] libsframe: use uint8_t instead of unsigned char for abi_arch","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230627195126.1955051-8-indu.bhagat@oracle.com/mbox/"},{"id":113564,"url":"https://patchwork.plctlab.org/api/1.2/patches/113564/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230627195126.1955051-9-indu.bhagat@oracle.com/","msgid":"<20230627195126.1955051-9-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-06-27T19:51:23","name":"[COMMITTED] libsframe: use uint8_t for return type of sframe_fre_get_base_reg_id","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230627195126.1955051-9-indu.bhagat@oracle.com/mbox/"},{"id":113565,"url":"https://patchwork.plctlab.org/api/1.2/patches/113565/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230627195126.1955051-10-indu.bhagat@oracle.com/","msgid":"<20230627195126.1955051-10-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-06-27T19:51:24","name":"[COMMITTED] libsframe: use appropriate data types for args of sframe_encode","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230627195126.1955051-10-indu.bhagat@oracle.com/mbox/"},{"id":113576,"url":"https://patchwork.plctlab.org/api/1.2/patches/113576/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230627195126.1955051-11-indu.bhagat@oracle.com/","msgid":"<20230627195126.1955051-11-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-06-27T19:51:25","name":"[COMMITTED] libsframe: bfd: use uint32_t for return type of get_num_fidx APIs","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230627195126.1955051-11-indu.bhagat@oracle.com/mbox/"},{"id":113578,"url":"https://patchwork.plctlab.org/api/1.2/patches/113578/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230627195126.1955051-12-indu.bhagat@oracle.com/","msgid":"<20230627195126.1955051-12-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-06-27T19:51:26","name":"[COMMITTED] binutils/NEWS: add note about upcoming libsframe changes","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230627195126.1955051-12-indu.bhagat@oracle.com/mbox/"},{"id":113614,"url":"https://patchwork.plctlab.org/api/1.2/patches/113614/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230627212028.2138604-2-indu.bhagat@oracle.com/","msgid":"<20230627212028.2138604-2-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-06-27T21:20:17","name":"[01/12] sframe.h: format bump to SFrame version 2","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230627212028.2138604-2-indu.bhagat@oracle.com/mbox/"},{"id":113611,"url":"https://patchwork.plctlab.org/api/1.2/patches/113611/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230627212028.2138604-3-indu.bhagat@oracle.com/","msgid":"<20230627212028.2138604-3-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-06-27T21:20:18","name":"[02/12] gas: generate SFrame section with version SFRAME_VERSION_2","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230627212028.2138604-3-indu.bhagat@oracle.com/mbox/"},{"id":113615,"url":"https://patchwork.plctlab.org/api/1.2/patches/113615/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230627212028.2138604-4-indu.bhagat@oracle.com/","msgid":"<20230627212028.2138604-4-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-06-27T21:20:19","name":"[03/12] libsframe: add new APIs to get SFrame version","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230627212028.2138604-4-indu.bhagat@oracle.com/mbox/"},{"id":113612,"url":"https://patchwork.plctlab.org/api/1.2/patches/113612/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230627212028.2138604-5-indu.bhagat@oracle.com/","msgid":"<20230627212028.2138604-5-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-06-27T21:20:20","name":"[04/12] libsframe: add new APIs to add and get SFrame FDE in SFrame version 2","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230627212028.2138604-5-indu.bhagat@oracle.com/mbox/"},{"id":113618,"url":"https://patchwork.plctlab.org/api/1.2/patches/113618/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230627212028.2138604-6-indu.bhagat@oracle.com/","msgid":"<20230627212028.2138604-6-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-06-27T21:20:21","name":"[05/12] libsframe: adjust version check in sframe_header_sanity_check_p","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230627212028.2138604-6-indu.bhagat@oracle.com/mbox/"},{"id":113616,"url":"https://patchwork.plctlab.org/api/1.2/patches/113616/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230627212028.2138604-7-indu.bhagat@oracle.com/","msgid":"<20230627212028.2138604-7-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-06-27T21:20:22","name":"[06/12] libsframe: testsuite: fixes for SFRAME_VERSION_2","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230627212028.2138604-7-indu.bhagat@oracle.com/mbox/"},{"id":113619,"url":"https://patchwork.plctlab.org/api/1.2/patches/113619/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230627212028.2138604-8-indu.bhagat@oracle.com/","msgid":"<20230627212028.2138604-8-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-06-27T21:20:23","name":"[07/12] bfd: linker: add support for rep_block_size for pltN entries","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230627212028.2138604-8-indu.bhagat@oracle.com/mbox/"},{"id":113622,"url":"https://patchwork.plctlab.org/api/1.2/patches/113622/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230627212028.2138604-9-indu.bhagat@oracle.com/","msgid":"<20230627212028.2138604-9-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-06-27T21:20:24","name":"[08/12] bfd: linker: generate SFrame sections with version SFRAME_VERSION_2","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230627212028.2138604-9-indu.bhagat@oracle.com/mbox/"},{"id":113613,"url":"https://patchwork.plctlab.org/api/1.2/patches/113613/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230627212028.2138604-10-indu.bhagat@oracle.com/","msgid":"<20230627212028.2138604-10-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-06-27T21:20:25","name":"[09/12] objdump/readelf: adjust for SFRAME_VERSION_2","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230627212028.2138604-10-indu.bhagat@oracle.com/mbox/"},{"id":113617,"url":"https://patchwork.plctlab.org/api/1.2/patches/113617/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230627212028.2138604-11-indu.bhagat@oracle.com/","msgid":"<20230627212028.2138604-11-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-06-27T21:20:26","name":"[10/12] doc: sframe: update specification for SFRAME_VERSION_2","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230627212028.2138604-11-indu.bhagat@oracle.com/mbox/"},{"id":113620,"url":"https://patchwork.plctlab.org/api/1.2/patches/113620/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230627212028.2138604-12-indu.bhagat@oracle.com/","msgid":"<20230627212028.2138604-12-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-06-27T21:20:27","name":"[11/12] doc: sframe: add details about alignment in the SFrame format","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230627212028.2138604-12-indu.bhagat@oracle.com/mbox/"},{"id":113621,"url":"https://patchwork.plctlab.org/api/1.2/patches/113621/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230627212028.2138604-13-indu.bhagat@oracle.com/","msgid":"<20230627212028.2138604-13-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-06-27T21:20:28","name":"[12/12] binutils/NEWS: announce SFrame version 2 as the new default","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230627212028.2138604-13-indu.bhagat@oracle.com/mbox/"},{"id":113643,"url":"https://patchwork.plctlab.org/api/1.2/patches/113643/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230628010634.1147958-1-maskray@google.com/","msgid":"<20230628010634.1147958-1-maskray@google.com>","list_archive_url":null,"date":"2023-06-28T01:06:34","name":"PR30592 objcopy: allow --set-section-flags to add or remove SHF_X86_64_LARGE","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230628010634.1147958-1-maskray@google.com/mbox/"},{"id":113816,"url":"https://patchwork.plctlab.org/api/1.2/patches/113816/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230628115103.3440262-2-i.swmail@xen0n.name/","msgid":"<20230628115103.3440262-2-i.swmail@xen0n.name>","list_archive_url":null,"date":"2023-06-28T11:50:58","name":"[v5,1/6] LoongArch: support disassembling certain pseudo-instructions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230628115103.3440262-2-i.swmail@xen0n.name/mbox/"},{"id":113815,"url":"https://patchwork.plctlab.org/api/1.2/patches/113815/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230628115103.3440262-3-i.swmail@xen0n.name/","msgid":"<20230628115103.3440262-3-i.swmail@xen0n.name>","list_archive_url":null,"date":"2023-06-28T11:50:59","name":"[v5,2/6] opcodes/loongarch: remove unused code","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230628115103.3440262-3-i.swmail@xen0n.name/mbox/"},{"id":113817,"url":"https://patchwork.plctlab.org/api/1.2/patches/113817/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230628115103.3440262-4-i.swmail@xen0n.name/","msgid":"<20230628115103.3440262-4-i.swmail@xen0n.name>","list_archive_url":null,"date":"2023-06-28T11:51:00","name":"[v5,3/6] opcodes/loongarch: implement style support in the disassembler","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230628115103.3440262-4-i.swmail@xen0n.name/mbox/"},{"id":113818,"url":"https://patchwork.plctlab.org/api/1.2/patches/113818/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230628115103.3440262-5-i.swmail@xen0n.name/","msgid":"<20230628115103.3440262-5-i.swmail@xen0n.name>","list_archive_url":null,"date":"2023-06-28T11:51:01","name":"[v5,4/6] opcodes/loongarch: style disassembled address offsets as such","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230628115103.3440262-5-i.swmail@xen0n.name/mbox/"},{"id":113820,"url":"https://patchwork.plctlab.org/api/1.2/patches/113820/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230628115103.3440262-6-i.swmail@xen0n.name/","msgid":"<20230628115103.3440262-6-i.swmail@xen0n.name>","list_archive_url":null,"date":"2023-06-28T11:51:02","name":"[v5,5/6] opcodes/loongarch: do not print hex notation for signed immediates","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230628115103.3440262-6-i.swmail@xen0n.name/mbox/"},{"id":113821,"url":"https://patchwork.plctlab.org/api/1.2/patches/113821/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230628115103.3440262-7-i.swmail@xen0n.name/","msgid":"<20230628115103.3440262-7-i.swmail@xen0n.name>","list_archive_url":null,"date":"2023-06-28T11:51:03","name":"[v5,6/6] opcodes/loongarch: print unrecognized insn words with the .word directive","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230628115103.3440262-7-i.swmail@xen0n.name/mbox/"},{"id":113857,"url":"https://patchwork.plctlab.org/api/1.2/patches/113857/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230628131311.3895731-1-i.swmail@xen0n.name/","msgid":"<20230628131311.3895731-1-i.swmail@xen0n.name>","list_archive_url":null,"date":"2023-06-28T13:13:11","name":"[v2] LoongArch: Deprecate $v[01], $fv[01] and $x names per spec","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230628131311.3895731-1-i.swmail@xen0n.name/mbox/"},{"id":114109,"url":"https://patchwork.plctlab.org/api/1.2/patches/114109/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230628231610.220112-1-maskray@google.com/","msgid":"<20230628231610.220112-1-maskray@google.com>","list_archive_url":null,"date":"2023-06-28T23:16:10","name":"[v2] PR30592 objcopy: allow --set-section-flags to add or remove SHF_X86_64_LARGE","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230628231610.220112-1-maskray@google.com/mbox/"},{"id":114173,"url":"https://patchwork.plctlab.org/api/1.2/patches/114173/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629061029.29773-2-i.swmail@xen0n.name/","msgid":"<20230629061029.29773-2-i.swmail@xen0n.name>","list_archive_url":null,"date":"2023-06-29T06:10:23","name":"[v6,1/7] LoongArch: support disassembling certain pseudo-instructions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629061029.29773-2-i.swmail@xen0n.name/mbox/"},{"id":114170,"url":"https://patchwork.plctlab.org/api/1.2/patches/114170/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629061029.29773-3-i.swmail@xen0n.name/","msgid":"<20230629061029.29773-3-i.swmail@xen0n.name>","list_archive_url":null,"date":"2023-06-29T06:10:24","name":"[v6,2/7] opcodes/loongarch: remove unused code","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629061029.29773-3-i.swmail@xen0n.name/mbox/"},{"id":114175,"url":"https://patchwork.plctlab.org/api/1.2/patches/114175/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629061029.29773-4-i.swmail@xen0n.name/","msgid":"<20230629061029.29773-4-i.swmail@xen0n.name>","list_archive_url":null,"date":"2023-06-29T06:10:25","name":"[v6,3/7] opcodes/loongarch: implement style support in the disassembler","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629061029.29773-4-i.swmail@xen0n.name/mbox/"},{"id":114171,"url":"https://patchwork.plctlab.org/api/1.2/patches/114171/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629061029.29773-5-i.swmail@xen0n.name/","msgid":"<20230629061029.29773-5-i.swmail@xen0n.name>","list_archive_url":null,"date":"2023-06-29T06:10:26","name":"[v6,4/7] opcodes/loongarch: style disassembled address offsets as such","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629061029.29773-5-i.swmail@xen0n.name/mbox/"},{"id":114172,"url":"https://patchwork.plctlab.org/api/1.2/patches/114172/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629061029.29773-6-i.swmail@xen0n.name/","msgid":"<20230629061029.29773-6-i.swmail@xen0n.name>","list_archive_url":null,"date":"2023-06-29T06:10:27","name":"[v6,5/7] opcodes/loongarch: do not print hex notation for signed immediates","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629061029.29773-6-i.swmail@xen0n.name/mbox/"},{"id":114176,"url":"https://patchwork.plctlab.org/api/1.2/patches/114176/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629061029.29773-7-i.swmail@xen0n.name/","msgid":"<20230629061029.29773-7-i.swmail@xen0n.name>","list_archive_url":null,"date":"2023-06-29T06:10:28","name":"[v6,6/7] opcodes/loongarch: print unrecognized insn words with the .word directive","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629061029.29773-7-i.swmail@xen0n.name/mbox/"},{"id":114174,"url":"https://patchwork.plctlab.org/api/1.2/patches/114174/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629061029.29773-8-i.swmail@xen0n.name/","msgid":"<20230629061029.29773-8-i.swmail@xen0n.name>","list_archive_url":null,"date":"2023-06-29T06:10:29","name":"[v6,7/7] LoongArch: Deprecate $v[01], $fv[01] and $x names per spec","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629061029.29773-8-i.swmail@xen0n.name/mbox/"},{"id":114246,"url":"https://patchwork.plctlab.org/api/1.2/patches/114246/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629090831.2579210-1-mengqinggang@loongson.cn/","msgid":"<20230629090831.2579210-1-mengqinggang@loongson.cn>","list_archive_url":null,"date":"2023-06-29T09:08:31","name":"LoongArch: gas: Add LVZ and LBT instructions support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629090831.2579210-1-mengqinggang@loongson.cn/mbox/"},{"id":114357,"url":"https://patchwork.plctlab.org/api/1.2/patches/114357/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629163504.1331025-2-i.swmail@xen0n.name/","msgid":"<20230629163504.1331025-2-i.swmail@xen0n.name>","list_archive_url":null,"date":"2023-06-29T16:34:58","name":"[v7,1/7] LoongArch: support disassembling certain pseudo-instructions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629163504.1331025-2-i.swmail@xen0n.name/mbox/"},{"id":114359,"url":"https://patchwork.plctlab.org/api/1.2/patches/114359/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629163504.1331025-3-i.swmail@xen0n.name/","msgid":"<20230629163504.1331025-3-i.swmail@xen0n.name>","list_archive_url":null,"date":"2023-06-29T16:34:59","name":"[v7,2/7] opcodes/loongarch: remove unused code","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629163504.1331025-3-i.swmail@xen0n.name/mbox/"},{"id":114356,"url":"https://patchwork.plctlab.org/api/1.2/patches/114356/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629163504.1331025-4-i.swmail@xen0n.name/","msgid":"<20230629163504.1331025-4-i.swmail@xen0n.name>","list_archive_url":null,"date":"2023-06-29T16:35:00","name":"[v7,3/7] opcodes/loongarch: implement style support in the disassembler","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629163504.1331025-4-i.swmail@xen0n.name/mbox/"},{"id":114363,"url":"https://patchwork.plctlab.org/api/1.2/patches/114363/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629163504.1331025-5-i.swmail@xen0n.name/","msgid":"<20230629163504.1331025-5-i.swmail@xen0n.name>","list_archive_url":null,"date":"2023-06-29T16:35:01","name":"[v7,4/7] opcodes/loongarch: style disassembled address offsets as such","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629163504.1331025-5-i.swmail@xen0n.name/mbox/"},{"id":114362,"url":"https://patchwork.plctlab.org/api/1.2/patches/114362/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629163504.1331025-6-i.swmail@xen0n.name/","msgid":"<20230629163504.1331025-6-i.swmail@xen0n.name>","list_archive_url":null,"date":"2023-06-29T16:35:02","name":"[v7,5/7] opcodes/loongarch: do not print hex notation for signed immediates","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629163504.1331025-6-i.swmail@xen0n.name/mbox/"},{"id":114360,"url":"https://patchwork.plctlab.org/api/1.2/patches/114360/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629163504.1331025-7-i.swmail@xen0n.name/","msgid":"<20230629163504.1331025-7-i.swmail@xen0n.name>","list_archive_url":null,"date":"2023-06-29T16:35:03","name":"[v7,6/7] opcodes/loongarch: print unrecognized insn words with the .word directive","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629163504.1331025-7-i.swmail@xen0n.name/mbox/"},{"id":114364,"url":"https://patchwork.plctlab.org/api/1.2/patches/114364/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629163504.1331025-8-i.swmail@xen0n.name/","msgid":"<20230629163504.1331025-8-i.swmail@xen0n.name>","list_archive_url":null,"date":"2023-06-29T16:35:04","name":"[v7,7/7] LoongArch: Deprecate $v[01], $fv[01] and $x names per spec","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629163504.1331025-8-i.swmail@xen0n.name/mbox/"},{"id":114368,"url":"https://patchwork.plctlab.org/api/1.2/patches/114368/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629171839.573187-2-nhuck@google.com/","msgid":"<20230629171839.573187-2-nhuck@google.com>","list_archive_url":null,"date":"2023-06-29T17:18:26","name":"[01/14] Add support for the Zvbb ISA extension.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629171839.573187-2-nhuck@google.com/mbox/"},{"id":114371,"url":"https://patchwork.plctlab.org/api/1.2/patches/114371/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629171839.573187-3-nhuck@google.com/","msgid":"<20230629171839.573187-3-nhuck@google.com>","list_archive_url":null,"date":"2023-06-29T17:18:27","name":"[02/14] Add support for the Zvbc ISA extension.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629171839.573187-3-nhuck@google.com/mbox/"},{"id":114374,"url":"https://patchwork.plctlab.org/api/1.2/patches/114374/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629171839.573187-4-nhuck@google.com/","msgid":"<20230629171839.573187-4-nhuck@google.com>","list_archive_url":null,"date":"2023-06-29T17:18:28","name":"[03/14] Add support for the Zvkg ISA extension.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629171839.573187-4-nhuck@google.com/mbox/"},{"id":114369,"url":"https://patchwork.plctlab.org/api/1.2/patches/114369/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629171839.573187-5-nhuck@google.com/","msgid":"<20230629171839.573187-5-nhuck@google.com>","list_archive_url":null,"date":"2023-06-29T17:18:29","name":"[04/14] Add support for the Zvkned ISA extension.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629171839.573187-5-nhuck@google.com/mbox/"},{"id":114373,"url":"https://patchwork.plctlab.org/api/1.2/patches/114373/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629171839.573187-6-nhuck@google.com/","msgid":"<20230629171839.573187-6-nhuck@google.com>","list_archive_url":null,"date":"2023-06-29T17:18:30","name":"[05/14] Add support for the Zvknh[a,b] ISA extensions.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629171839.573187-6-nhuck@google.com/mbox/"},{"id":114376,"url":"https://patchwork.plctlab.org/api/1.2/patches/114376/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629171839.573187-7-nhuck@google.com/","msgid":"<20230629171839.573187-7-nhuck@google.com>","list_archive_url":null,"date":"2023-06-29T17:18:31","name":"[06/14] Add support for the Zvksed ISA extension.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629171839.573187-7-nhuck@google.com/mbox/"},{"id":114370,"url":"https://patchwork.plctlab.org/api/1.2/patches/114370/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629171839.573187-8-nhuck@google.com/","msgid":"<20230629171839.573187-8-nhuck@google.com>","list_archive_url":null,"date":"2023-06-29T17:18:32","name":"[07/14] Adds support for the Zvksh ISA extension.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629171839.573187-8-nhuck@google.com/mbox/"},{"id":114377,"url":"https://patchwork.plctlab.org/api/1.2/patches/114377/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629171839.573187-9-nhuck@google.com/","msgid":"<20230629171839.573187-9-nhuck@google.com>","list_archive_url":null,"date":"2023-06-29T17:18:33","name":"[08/14] Add support for the Zvkn ISA extension.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629171839.573187-9-nhuck@google.com/mbox/"},{"id":114381,"url":"https://patchwork.plctlab.org/api/1.2/patches/114381/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629171839.573187-10-nhuck@google.com/","msgid":"<20230629171839.573187-10-nhuck@google.com>","list_archive_url":null,"date":"2023-06-29T17:18:34","name":"[09/14] Allow nested implications for extensions.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629171839.573187-10-nhuck@google.com/mbox/"},{"id":114382,"url":"https://patchwork.plctlab.org/api/1.2/patches/114382/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629171839.573187-11-nhuck@google.com/","msgid":"<20230629171839.573187-11-nhuck@google.com>","list_archive_url":null,"date":"2023-06-29T17:18:35","name":"[10/14] Add support for the Zvkng ISA extension.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629171839.573187-11-nhuck@google.com/mbox/"},{"id":114372,"url":"https://patchwork.plctlab.org/api/1.2/patches/114372/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629171839.573187-12-nhuck@google.com/","msgid":"<20230629171839.573187-12-nhuck@google.com>","list_archive_url":null,"date":"2023-06-29T17:18:36","name":"[11/14] Add support for the Zvks ISA extension.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629171839.573187-12-nhuck@google.com/mbox/"},{"id":114375,"url":"https://patchwork.plctlab.org/api/1.2/patches/114375/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629171839.573187-13-nhuck@google.com/","msgid":"<20230629171839.573187-13-nhuck@google.com>","list_archive_url":null,"date":"2023-06-29T17:18:37","name":"[12/14] Add support for the Zvksg ISA extension.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629171839.573187-13-nhuck@google.com/mbox/"},{"id":114378,"url":"https://patchwork.plctlab.org/api/1.2/patches/114378/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629171839.573187-14-nhuck@google.com/","msgid":"<20230629171839.573187-14-nhuck@google.com>","list_archive_url":null,"date":"2023-06-29T17:18:38","name":"[13/14] Add support for the Zvknc ISA extension.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629171839.573187-14-nhuck@google.com/mbox/"},{"id":114383,"url":"https://patchwork.plctlab.org/api/1.2/patches/114383/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629171839.573187-15-nhuck@google.com/","msgid":"<20230629171839.573187-15-nhuck@google.com>","list_archive_url":null,"date":"2023-06-29T17:18:39","name":"[14/14] Add support for the Zvksc ISA extension.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629171839.573187-15-nhuck@google.com/mbox/"},{"id":114391,"url":"https://patchwork.plctlab.org/api/1.2/patches/114391/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629182618.2351051-1-indu.bhagat@oracle.com/","msgid":"<20230629182618.2351051-1-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-06-29T18:26:18","name":"[COMMITTED] libsframe: fix sframe_find_fre for pltN entries","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629182618.2351051-1-indu.bhagat@oracle.com/mbox/"},{"id":114494,"url":"https://patchwork.plctlab.org/api/1.2/patches/114494/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629235326.1167898-1-indu.bhagat@oracle.com/","msgid":"<20230629235326.1167898-1-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-06-29T23:53:23","name":"[COMMITTED] libsframe: add new APIs to get SFrame version","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629235326.1167898-1-indu.bhagat@oracle.com/mbox/"},{"id":114496,"url":"https://patchwork.plctlab.org/api/1.2/patches/114496/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629235326.1167898-2-indu.bhagat@oracle.com/","msgid":"<20230629235326.1167898-2-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-06-29T23:53:24","name":"[COMMITTED] sframe: bfd: gas: ld: format bump to SFrame version 2","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629235326.1167898-2-indu.bhagat@oracle.com/mbox/"},{"id":114492,"url":"https://patchwork.plctlab.org/api/1.2/patches/114492/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629235326.1167898-3-indu.bhagat@oracle.com/","msgid":"<20230629235326.1167898-3-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-06-29T23:53:25","name":"[COMMITTED] doc: sframe: update specification for SFRAME_VERSION_2","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629235326.1167898-3-indu.bhagat@oracle.com/mbox/"},{"id":114491,"url":"https://patchwork.plctlab.org/api/1.2/patches/114491/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629235326.1167898-4-indu.bhagat@oracle.com/","msgid":"<20230629235326.1167898-4-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-06-29T23:53:26","name":"[COMMITTED] binutils/NEWS: announce SFrame version 2 as the new default","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629235326.1167898-4-indu.bhagat@oracle.com/mbox/"},{"id":114538,"url":"https://patchwork.plctlab.org/api/1.2/patches/114538/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230630025308.3258293-1-vladimir.mezentsev@oracle.com/","msgid":"<20230630025308.3258293-1-vladimir.mezentsev@oracle.com>","list_archive_url":null,"date":"2023-06-30T02:53:08","name":"gprofng: fix data race","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230630025308.3258293-1-vladimir.mezentsev@oracle.com/mbox/"},{"id":114543,"url":"https://patchwork.plctlab.org/api/1.2/patches/114543/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230630033443.2359278-2-mengqinggang@loongson.cn/","msgid":"<20230630033443.2359278-2-mengqinggang@loongson.cn>","list_archive_url":null,"date":"2023-06-30T03:34:42","name":"[v1,1/2] LoongArch: gas: Add LVZ and LBT instructions support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230630033443.2359278-2-mengqinggang@loongson.cn/mbox/"},{"id":114544,"url":"https://patchwork.plctlab.org/api/1.2/patches/114544/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230630033443.2359278-3-mengqinggang@loongson.cn/","msgid":"<20230630033443.2359278-3-mengqinggang@loongson.cn>","list_archive_url":null,"date":"2023-06-30T03:34:43","name":"[v1,2/2] LoongArch: gas: Fix code style issues","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230630033443.2359278-3-mengqinggang@loongson.cn/mbox/"},{"id":114557,"url":"https://patchwork.plctlab.org/api/1.2/patches/114557/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230630051451.1867944-1-yunqiang.su@cipunited.com/","msgid":"<20230630051451.1867944-1-yunqiang.su@cipunited.com>","list_archive_url":null,"date":"2023-06-30T05:14:51","name":"ld: Use [list ] syntax to define run_tests in indirect.exp","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230630051451.1867944-1-yunqiang.su@cipunited.com/mbox/"},{"id":114580,"url":"https://patchwork.plctlab.org/api/1.2/patches/114580/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230630060757.2006878-1-yunqiang.su@cipunited.com/","msgid":"<20230630060757.2006878-1-yunqiang.su@cipunited.com>","list_archive_url":null,"date":"2023-06-30T06:07:57","name":"ld: Use run_host_cmd_yesno in indirect.exp instead of catch exec","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230630060757.2006878-1-yunqiang.su@cipunited.com/mbox/"},{"id":114592,"url":"https://patchwork.plctlab.org/api/1.2/patches/114592/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230630064559.2282365-1-yunqiang.su@cipunited.com/","msgid":"<20230630064559.2282365-1-yunqiang.su@cipunited.com>","list_archive_url":null,"date":"2023-06-30T06:45:59","name":"MIPS: N64, mark .interp as INITIAL_READONLY_SECTIONS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230630064559.2282365-1-yunqiang.su@cipunited.com/mbox/"},{"id":114606,"url":"https://patchwork.plctlab.org/api/1.2/patches/114606/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/CAP2b4GMYH=czD31TwmNrqOjnRH1dOsPVo8Be9VN=_EiFQWitoQ@mail.gmail.com/","msgid":"","list_archive_url":null,"date":"2023-06-30T07:53:13","name":"Add the .seh_ifrepeat and .seh_ifnrepeat directives","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/CAP2b4GMYH=czD31TwmNrqOjnRH1dOsPVo8Be9VN=_EiFQWitoQ@mail.gmail.com/mbox/"},{"id":114625,"url":"https://patchwork.plctlab.org/api/1.2/patches/114625/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230630090416.3051425-2-mengqinggang@loongson.cn/","msgid":"<20230630090416.3051425-2-mengqinggang@loongson.cn>","list_archive_url":null,"date":"2023-06-30T09:04:15","name":"[v2,1/2] LoongArch: gas: Add LVZ and LBT instructions support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230630090416.3051425-2-mengqinggang@loongson.cn/mbox/"},{"id":114627,"url":"https://patchwork.plctlab.org/api/1.2/patches/114627/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230630090416.3051425-3-mengqinggang@loongson.cn/","msgid":"<20230630090416.3051425-3-mengqinggang@loongson.cn>","list_archive_url":null,"date":"2023-06-30T09:04:16","name":"[v2,2/2] LoongArch: gas: Fix code style issues","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230630090416.3051425-3-mengqinggang@loongson.cn/mbox/"},{"id":114639,"url":"https://patchwork.plctlab.org/api/1.2/patches/114639/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/878rc1707w.fsf@redhat.com/","msgid":"<878rc1707w.fsf@redhat.com>","list_archive_url":null,"date":"2023-06-30T09:45:07","name":"Commit: Fix used before initialised warnings from Clang 16","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/878rc1707w.fsf@redhat.com/mbox/"},{"id":114709,"url":"https://patchwork.plctlab.org/api/1.2/patches/114709/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230630123259.1900571-1-i.swmail@xen0n.name/","msgid":"<20230630123259.1900571-1-i.swmail@xen0n.name>","list_archive_url":null,"date":"2023-06-30T12:32:59","name":"opcodes/loongarch: Mark address offset operands of LVZ/LBT insns as such","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230630123259.1900571-1-i.swmail@xen0n.name/mbox/"},{"id":114726,"url":"https://patchwork.plctlab.org/api/1.2/patches/114726/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230630134436.1237733-1-luis.machado@arm.com/","msgid":"<20230630134436.1237733-1-luis.machado@arm.com>","list_archive_url":null,"date":"2023-06-30T13:44:36","name":"[aarch64] sme: Core file support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230630134436.1237733-1-luis.machado@arm.com/mbox/"},{"id":114727,"url":"https://patchwork.plctlab.org/api/1.2/patches/114727/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230630134519.1237879-1-luis.machado@arm.com/","msgid":"<20230630134519.1237879-1-luis.machado@arm.com>","list_archive_url":null,"date":"2023-06-30T13:45:19","name":"[aarch64] sme2: Teach binutils/BFD about the NT_ARM_ZT register set","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230630134519.1237879-1-luis.machado@arm.com/mbox/"}],"public":true,"mbox":"https://patchwork.plctlab.org/bundle/patchwork-bot/binutils-gdb_2023-06/mbox/"},{"id":26,"url":"https://patchwork.plctlab.org/api/1.2/bundles/26/","web_url":"https://patchwork.plctlab.org/bundle/patchwork-bot/binutils-gdb_2023-07/","project":{"id":2,"url":"https://patchwork.plctlab.org/api/1.2/projects/2/","name":"binutils-gdb","link_name":"binutils-gdb","list_id":"binutils.sourceware.org","list_email":"binutils@sourceware.org","web_url":"https://github.com/wangliu-iscas/Patchwork-Bundles/blob/main/binutils-gdb.md","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"name":"binutils-gdb_2023-07","owner":{"id":3,"url":"https://patchwork.plctlab.org/api/1.2/users/3/","username":"patchwork-bot","first_name":"","last_name":"","email":"ouuuleilei@gmail.com"},"patches":[{"id":114893,"url":"https://patchwork.plctlab.org/api/1.2/patches/114893/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230630215725.3725876-2-christoph.muellner@vrull.eu/","msgid":"<20230630215725.3725876-2-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2023-06-30T21:57:11","name":"[v5,01/15] RISC-V: Add support for the Zvbb ISA extension","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230630215725.3725876-2-christoph.muellner@vrull.eu/mbox/"},{"id":114888,"url":"https://patchwork.plctlab.org/api/1.2/patches/114888/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230630215725.3725876-3-christoph.muellner@vrull.eu/","msgid":"<20230630215725.3725876-3-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2023-06-30T21:57:12","name":"[v5,02/15] RISC-V: Add support for the Zvbc extension","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230630215725.3725876-3-christoph.muellner@vrull.eu/mbox/"},{"id":114896,"url":"https://patchwork.plctlab.org/api/1.2/patches/114896/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230630215725.3725876-4-christoph.muellner@vrull.eu/","msgid":"<20230630215725.3725876-4-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2023-06-30T21:57:13","name":"[v5,03/15] RISC-V: Add support for the Zvkg ISA extension","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230630215725.3725876-4-christoph.muellner@vrull.eu/mbox/"},{"id":114889,"url":"https://patchwork.plctlab.org/api/1.2/patches/114889/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230630215725.3725876-5-christoph.muellner@vrull.eu/","msgid":"<20230630215725.3725876-5-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2023-06-30T21:57:14","name":"[v5,04/15] RISC-V: Add support for the Zvkned ISA extension","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230630215725.3725876-5-christoph.muellner@vrull.eu/mbox/"},{"id":114890,"url":"https://patchwork.plctlab.org/api/1.2/patches/114890/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230630215725.3725876-6-christoph.muellner@vrull.eu/","msgid":"<20230630215725.3725876-6-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2023-06-30T21:57:15","name":"[v5,05/15] RISC-V: Add support for the Zvknh[a, b] ISA extensions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230630215725.3725876-6-christoph.muellner@vrull.eu/mbox/"},{"id":114899,"url":"https://patchwork.plctlab.org/api/1.2/patches/114899/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230630215725.3725876-7-christoph.muellner@vrull.eu/","msgid":"<20230630215725.3725876-7-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2023-06-30T21:57:16","name":"[v5,06/15] RISC-V: Add support for the Zvksed ISA extension","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230630215725.3725876-7-christoph.muellner@vrull.eu/mbox/"},{"id":114892,"url":"https://patchwork.plctlab.org/api/1.2/patches/114892/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230630215725.3725876-8-christoph.muellner@vrull.eu/","msgid":"<20230630215725.3725876-8-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2023-06-30T21:57:17","name":"[v5,07/15] RISC-V: Add support for the Zvksh ISA extension","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230630215725.3725876-8-christoph.muellner@vrull.eu/mbox/"},{"id":114895,"url":"https://patchwork.plctlab.org/api/1.2/patches/114895/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230630215725.3725876-9-christoph.muellner@vrull.eu/","msgid":"<20230630215725.3725876-9-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2023-06-30T21:57:18","name":"[v5,08/15] RISC-V: Add support for the Zvkn ISA extension","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230630215725.3725876-9-christoph.muellner@vrull.eu/mbox/"},{"id":114901,"url":"https://patchwork.plctlab.org/api/1.2/patches/114901/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230630215725.3725876-10-christoph.muellner@vrull.eu/","msgid":"<20230630215725.3725876-10-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2023-06-30T21:57:19","name":"[v5,09/15] RISC-V: Allow nested implications for extensions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230630215725.3725876-10-christoph.muellner@vrull.eu/mbox/"},{"id":114894,"url":"https://patchwork.plctlab.org/api/1.2/patches/114894/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230630215725.3725876-11-christoph.muellner@vrull.eu/","msgid":"<20230630215725.3725876-11-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2023-06-30T21:57:20","name":"[v5,10/15] RISC-V: Add support for the Zvkng ISA extension","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230630215725.3725876-11-christoph.muellner@vrull.eu/mbox/"},{"id":114897,"url":"https://patchwork.plctlab.org/api/1.2/patches/114897/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230630215725.3725876-12-christoph.muellner@vrull.eu/","msgid":"<20230630215725.3725876-12-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2023-06-30T21:57:21","name":"[v5,11/15] RISC-V: Add support for the Zvks ISA extension","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230630215725.3725876-12-christoph.muellner@vrull.eu/mbox/"},{"id":114903,"url":"https://patchwork.plctlab.org/api/1.2/patches/114903/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230630215725.3725876-13-christoph.muellner@vrull.eu/","msgid":"<20230630215725.3725876-13-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2023-06-30T21:57:22","name":"[v5,12/15] RISC-V: Add support for the Zvksg ISA extension","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230630215725.3725876-13-christoph.muellner@vrull.eu/mbox/"},{"id":114898,"url":"https://patchwork.plctlab.org/api/1.2/patches/114898/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230630215725.3725876-14-christoph.muellner@vrull.eu/","msgid":"<20230630215725.3725876-14-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2023-06-30T21:57:23","name":"[v5,13/15] RISC-V: Add support for the Zvknc ISA extension","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230630215725.3725876-14-christoph.muellner@vrull.eu/mbox/"},{"id":114900,"url":"https://patchwork.plctlab.org/api/1.2/patches/114900/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230630215725.3725876-15-christoph.muellner@vrull.eu/","msgid":"<20230630215725.3725876-15-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2023-06-30T21:57:24","name":"[v5,14/15] RISC-V: Add support for the Zvksc ISA extension","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230630215725.3725876-15-christoph.muellner@vrull.eu/mbox/"},{"id":114902,"url":"https://patchwork.plctlab.org/api/1.2/patches/114902/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230630215725.3725876-16-christoph.muellner@vrull.eu/","msgid":"<20230630215725.3725876-16-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2023-06-30T21:57:25","name":"[v5,15/15] binutils: NEWS: Announce new RISC-V vector crypto extensions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230630215725.3725876-16-christoph.muellner@vrull.eu/mbox/"},{"id":114949,"url":"https://patchwork.plctlab.org/api/1.2/patches/114949/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230701052104.4018352-2-christoph.muellner@vrull.eu/","msgid":"<20230701052104.4018352-2-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2023-07-01T05:20:50","name":"[v6,01/15] RISC-V: Add support for the Zvbb ISA extension","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230701052104.4018352-2-christoph.muellner@vrull.eu/mbox/"},{"id":114952,"url":"https://patchwork.plctlab.org/api/1.2/patches/114952/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230701052104.4018352-3-christoph.muellner@vrull.eu/","msgid":"<20230701052104.4018352-3-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2023-07-01T05:20:51","name":"[v6,02/15] RISC-V: Add support for the Zvbc extension","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230701052104.4018352-3-christoph.muellner@vrull.eu/mbox/"},{"id":114955,"url":"https://patchwork.plctlab.org/api/1.2/patches/114955/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230701052104.4018352-4-christoph.muellner@vrull.eu/","msgid":"<20230701052104.4018352-4-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2023-07-01T05:20:52","name":"[v6,03/15] RISC-V: Add support for the Zvkg ISA extension","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230701052104.4018352-4-christoph.muellner@vrull.eu/mbox/"},{"id":114958,"url":"https://patchwork.plctlab.org/api/1.2/patches/114958/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230701052104.4018352-5-christoph.muellner@vrull.eu/","msgid":"<20230701052104.4018352-5-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2023-07-01T05:20:53","name":"[v6,04/15] RISC-V: Add support for the Zvkned ISA extension","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230701052104.4018352-5-christoph.muellner@vrull.eu/mbox/"},{"id":114953,"url":"https://patchwork.plctlab.org/api/1.2/patches/114953/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230701052104.4018352-6-christoph.muellner@vrull.eu/","msgid":"<20230701052104.4018352-6-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2023-07-01T05:20:54","name":"[v6,05/15] RISC-V: Add support for the Zvknh[a, b] ISA extensions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230701052104.4018352-6-christoph.muellner@vrull.eu/mbox/"},{"id":114950,"url":"https://patchwork.plctlab.org/api/1.2/patches/114950/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230701052104.4018352-7-christoph.muellner@vrull.eu/","msgid":"<20230701052104.4018352-7-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2023-07-01T05:20:55","name":"[v6,06/15] RISC-V: Add support for the Zvksed ISA extension","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230701052104.4018352-7-christoph.muellner@vrull.eu/mbox/"},{"id":114956,"url":"https://patchwork.plctlab.org/api/1.2/patches/114956/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230701052104.4018352-8-christoph.muellner@vrull.eu/","msgid":"<20230701052104.4018352-8-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2023-07-01T05:20:56","name":"[v6,07/15] RISC-V: Add support for the Zvksh ISA extension","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230701052104.4018352-8-christoph.muellner@vrull.eu/mbox/"},{"id":114954,"url":"https://patchwork.plctlab.org/api/1.2/patches/114954/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230701052104.4018352-9-christoph.muellner@vrull.eu/","msgid":"<20230701052104.4018352-9-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2023-07-01T05:20:57","name":"[v6,08/15] RISC-V: Add support for the Zvkn ISA extension","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230701052104.4018352-9-christoph.muellner@vrull.eu/mbox/"},{"id":114960,"url":"https://patchwork.plctlab.org/api/1.2/patches/114960/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230701052104.4018352-10-christoph.muellner@vrull.eu/","msgid":"<20230701052104.4018352-10-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2023-07-01T05:20:58","name":"[v6,09/15] RISC-V: Allow nested implications for extensions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230701052104.4018352-10-christoph.muellner@vrull.eu/mbox/"},{"id":114951,"url":"https://patchwork.plctlab.org/api/1.2/patches/114951/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230701052104.4018352-11-christoph.muellner@vrull.eu/","msgid":"<20230701052104.4018352-11-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2023-07-01T05:20:59","name":"[v6,10/15] RISC-V: Add support for the Zvkng ISA extension","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230701052104.4018352-11-christoph.muellner@vrull.eu/mbox/"},{"id":114962,"url":"https://patchwork.plctlab.org/api/1.2/patches/114962/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230701052104.4018352-12-christoph.muellner@vrull.eu/","msgid":"<20230701052104.4018352-12-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2023-07-01T05:21:00","name":"[v6,11/15] RISC-V: Add support for the Zvks ISA extension","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230701052104.4018352-12-christoph.muellner@vrull.eu/mbox/"},{"id":114957,"url":"https://patchwork.plctlab.org/api/1.2/patches/114957/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230701052104.4018352-13-christoph.muellner@vrull.eu/","msgid":"<20230701052104.4018352-13-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2023-07-01T05:21:01","name":"[v6,12/15] RISC-V: Add support for the Zvksg ISA extension","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230701052104.4018352-13-christoph.muellner@vrull.eu/mbox/"},{"id":114963,"url":"https://patchwork.plctlab.org/api/1.2/patches/114963/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230701052104.4018352-14-christoph.muellner@vrull.eu/","msgid":"<20230701052104.4018352-14-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2023-07-01T05:21:02","name":"[v6,13/15] RISC-V: Add support for the Zvknc ISA extension","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230701052104.4018352-14-christoph.muellner@vrull.eu/mbox/"},{"id":114961,"url":"https://patchwork.plctlab.org/api/1.2/patches/114961/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230701052104.4018352-15-christoph.muellner@vrull.eu/","msgid":"<20230701052104.4018352-15-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2023-07-01T05:21:03","name":"[v6,14/15] RISC-V: Add support for the Zvksc ISA extension","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230701052104.4018352-15-christoph.muellner@vrull.eu/mbox/"},{"id":114964,"url":"https://patchwork.plctlab.org/api/1.2/patches/114964/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230701052104.4018352-16-christoph.muellner@vrull.eu/","msgid":"<20230701052104.4018352-16-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2023-07-01T05:21:04","name":"[v6,15/15] binutils: NEWS: Announce new RISC-V vector crypto extensions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230701052104.4018352-16-christoph.muellner@vrull.eu/mbox/"},{"id":115075,"url":"https://patchwork.plctlab.org/api/1.2/patches/115075/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230702101422.762791-1-i.swmail@xen0n.name/","msgid":"<20230702101422.762791-1-i.swmail@xen0n.name>","list_archive_url":null,"date":"2023-07-02T10:14:22","name":"LoongArch: gas: Fix shared builds","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230702101422.762791-1-i.swmail@xen0n.name/mbox/"},{"id":115076,"url":"https://patchwork.plctlab.org/api/1.2/patches/115076/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/CAP2b4GOzcaewq1dZjnN5=jR-pZ4cRwvnCm=giYxKZ90zSGD85w@mail.gmail.com/","msgid":"","list_archive_url":null,"date":"2023-07-02T10:16:07","name":"Reimplement the .seh_scope directive","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/CAP2b4GOzcaewq1dZjnN5=jR-pZ4cRwvnCm=giYxKZ90zSGD85w@mail.gmail.com/mbox/"},{"id":115077,"url":"https://patchwork.plctlab.org/api/1.2/patches/115077/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/CAP2b4GN6AvihQ9W0ebCMgH1ozEvYKjb41Te9HfQg4k=e9ejhSw@mail.gmail.com/","msgid":"","list_archive_url":null,"date":"2023-07-02T10:18:31","name":"Reimplement the .seh_scope directive","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/CAP2b4GN6AvihQ9W0ebCMgH1ozEvYKjb41Te9HfQg4k=e9ejhSw@mail.gmail.com/mbox/"},{"id":115083,"url":"https://patchwork.plctlab.org/api/1.2/patches/115083/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230702111053.815399-1-i.swmail@xen0n.name/","msgid":"<20230702111053.815399-1-i.swmail@xen0n.name>","list_archive_url":null,"date":"2023-07-02T11:10:52","name":"[1/2] binutils: NEWS: Announce LoongArch changes in the 2.41 cycle","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230702111053.815399-1-i.swmail@xen0n.name/mbox/"},{"id":115082,"url":"https://patchwork.plctlab.org/api/1.2/patches/115082/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230702111053.815399-2-i.swmail@xen0n.name/","msgid":"<20230702111053.815399-2-i.swmail@xen0n.name>","list_archive_url":null,"date":"2023-07-02T11:10:53","name":"[2/2] gas: NEWS: Announce LoongArch changes in the 2.41 cycle","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230702111053.815399-2-i.swmail@xen0n.name/mbox/"},{"id":115188,"url":"https://patchwork.plctlab.org/api/1.2/patches/115188/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230703044321.2951358-1-yunqiang.su@cipunited.com/","msgid":"<20230703044321.2951358-1-yunqiang.su@cipunited.com>","list_archive_url":null,"date":"2023-07-03T04:43:21","name":"ld: fix plugin tests for MIPS PIC","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230703044321.2951358-1-yunqiang.su@cipunited.com/mbox/"},{"id":115284,"url":"https://patchwork.plctlab.org/api/1.2/patches/115284/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230703101047.2589341-1-christoph.muellner@vrull.eu/","msgid":"<20230703101047.2589341-1-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2023-07-03T10:10:47","name":"RISC-V: Zvkh[a,b]: Remove individual instruction class","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230703101047.2589341-1-christoph.muellner@vrull.eu/mbox/"},{"id":115301,"url":"https://patchwork.plctlab.org/api/1.2/patches/115301/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230703103647.3162351-1-yunqiang.su@cipunited.com/","msgid":"<20230703103647.3162351-1-yunqiang.su@cipunited.com>","list_archive_url":null,"date":"2023-07-03T10:36:47","name":"MIPS: Don'\''t __gnu_lto_slim to .scommon","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230703103647.3162351-1-yunqiang.su@cipunited.com/mbox/"},{"id":115305,"url":"https://patchwork.plctlab.org/api/1.2/patches/115305/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230703105034.3163572-1-yunqiang.su@cipunited.com/","msgid":"<20230703105034.3163572-1-yunqiang.su@cipunited.com>","list_archive_url":null,"date":"2023-07-03T10:50:34","name":"[v2] MIPS: Don'\''t move __gnu_lto_slim to .scommon","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230703105034.3163572-1-yunqiang.su@cipunited.com/mbox/"},{"id":115445,"url":"https://patchwork.plctlab.org/api/1.2/patches/115445/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230703181052.41059-1-krebbel@linux.ibm.com/","msgid":"<20230703181052.41059-1-krebbel@linux.ibm.com>","list_archive_url":null,"date":"2023-07-03T18:10:52","name":"[Committed] IBM Z: Fix pcrel relocs for symA-symB expressions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230703181052.41059-1-krebbel@linux.ibm.com/mbox/"},{"id":115692,"url":"https://patchwork.plctlab.org/api/1.2/patches/115692/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230704102703.650038-1-claziss@gmail.com/","msgid":"<20230704102703.650038-1-claziss@gmail.com>","list_archive_url":null,"date":"2023-07-04T10:27:02","name":"[committed,1/2] arc: Update neg<.f> 0,b encoding","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230704102703.650038-1-claziss@gmail.com/mbox/"},{"id":115691,"url":"https://patchwork.plctlab.org/api/1.2/patches/115691/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230704102703.650038-2-claziss@gmail.com/","msgid":"<20230704102703.650038-2-claziss@gmail.com>","list_archive_url":null,"date":"2023-07-04T10:27:03","name":"[committed,2/2] arc: Update default target CPU to match GCC defaults","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230704102703.650038-2-claziss@gmail.com/mbox/"},{"id":115742,"url":"https://patchwork.plctlab.org/api/1.2/patches/115742/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230704121832.222400-1-krebbel@linux.ibm.com/","msgid":"<20230704121832.222400-1-krebbel@linux.ibm.com>","list_archive_url":null,"date":"2023-07-04T12:18:32","name":"Align linkerscript symbols according to ABI","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230704121832.222400-1-krebbel@linux.ibm.com/mbox/"},{"id":115827,"url":"https://patchwork.plctlab.org/api/1.2/patches/115827/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e098654c-98dd-1b2f-e876-6ba910260492@suse.com/","msgid":"","list_archive_url":null,"date":"2023-07-04T15:18:32","name":"[01/10] x86: fold certain legacy/VEX table entries","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e098654c-98dd-1b2f-e876-6ba910260492@suse.com/mbox/"},{"id":115828,"url":"https://patchwork.plctlab.org/api/1.2/patches/115828/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/18221c8c-4d6e-f0f1-3738-785023be1268@suse.com/","msgid":"<18221c8c-4d6e-f0f1-3738-785023be1268@suse.com>","list_archive_url":null,"date":"2023-07-04T15:19:53","name":"[02/10] x86: fold legacy/VEX {,V}MOV{H,L}* entries","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/18221c8c-4d6e-f0f1-3738-785023be1268@suse.com/mbox/"},{"id":115829,"url":"https://patchwork.plctlab.org/api/1.2/patches/115829/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/46594eee-305a-8913-c407-806158fbbe8f@suse.com/","msgid":"<46594eee-305a-8913-c407-806158fbbe8f@suse.com>","list_archive_url":null,"date":"2023-07-04T15:20:35","name":"[03/10] x86: {,V}MOVNT* don'\''t need to go through mod_table[]","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/46594eee-305a-8913-c407-806158fbbe8f@suse.com/mbox/"},{"id":115830,"url":"https://patchwork.plctlab.org/api/1.2/patches/115830/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/02a1aabf-4759-009b-5718-f567ed39b81c@suse.com/","msgid":"<02a1aabf-4759-009b-5718-f567ed39b81c@suse.com>","list_archive_url":null,"date":"2023-07-04T15:21:02","name":"[04/10] x86: misc further memory-only insns don'\''t need to go through mod_table[]","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/02a1aabf-4759-009b-5718-f567ed39b81c@suse.com/mbox/"},{"id":115832,"url":"https://patchwork.plctlab.org/api/1.2/patches/115832/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/96a500b4-1b68-520b-bccc-01d78f8e6f6c@suse.com/","msgid":"<96a500b4-1b68-520b-bccc-01d78f8e6f6c@suse.com>","list_archive_url":null,"date":"2023-07-04T15:21:38","name":"[05/10] x86: SIMD shift-by-immediate don'\''t need to go through mod_table[]","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/96a500b4-1b68-520b-bccc-01d78f8e6f6c@suse.com/mbox/"},{"id":115834,"url":"https://patchwork.plctlab.org/api/1.2/patches/115834/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d9842149-1c2b-2ff9-531d-87cae64e4b78@suse.com/","msgid":"","list_archive_url":null,"date":"2023-07-04T15:22:06","name":"[06/10] x86: slightly rework handling of some register-only insns","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d9842149-1c2b-2ff9-531d-87cae64e4b78@suse.com/mbox/"},{"id":115835,"url":"https://patchwork.plctlab.org/api/1.2/patches/115835/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/25535360-ad14-8ed2-bd86-b96f97306e43@suse.com/","msgid":"<25535360-ad14-8ed2-bd86-b96f97306e43@suse.com>","list_archive_url":null,"date":"2023-07-04T15:22:31","name":"[07/10] x86: various operations on mask registers can avoid going through mod_table[]","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/25535360-ad14-8ed2-bd86-b96f97306e43@suse.com/mbox/"},{"id":115833,"url":"https://patchwork.plctlab.org/api/1.2/patches/115833/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/54b1c54f-ddad-4d5a-f5d0-e585cd3aaa3e@suse.com/","msgid":"<54b1c54f-ddad-4d5a-f5d0-e585cd3aaa3e@suse.com>","list_archive_url":null,"date":"2023-07-04T15:22:59","name":"[08/10] x86: misc further register-only insns don'\''t need to go through mod_table[]","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/54b1c54f-ddad-4d5a-f5d0-e585cd3aaa3e@suse.com/mbox/"},{"id":115837,"url":"https://patchwork.plctlab.org/api/1.2/patches/115837/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ec881a0e-05b2-556b-8e21-a1c38429e465@suse.com/","msgid":"","list_archive_url":null,"date":"2023-07-04T15:23:25","name":"[09/10] x86: convert 0FXOP to just XOP in enumerator names","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ec881a0e-05b2-556b-8e21-a1c38429e465@suse.com/mbox/"},{"id":115836,"url":"https://patchwork.plctlab.org/api/1.2/patches/115836/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/126aeaee-40ae-34aa-5e30-9579264d6336@suse.com/","msgid":"<126aeaee-40ae-34aa-5e30-9579264d6336@suse.com>","list_archive_url":null,"date":"2023-07-04T15:24:08","name":"[10/10] x86: simplify table-referencing macros","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/126aeaee-40ae-34aa-5e30-9579264d6336@suse.com/mbox/"},{"id":116027,"url":"https://patchwork.plctlab.org/api/1.2/patches/116027/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230705084213.91043-1-lidie@eswincomputing.com/","msgid":"<20230705084213.91043-1-lidie@eswincomputing.com>","list_archive_url":null,"date":"2023-07-05T08:42:13","name":"[RISC-V] Fix the valid gp range for gp relax.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230705084213.91043-1-lidie@eswincomputing.com/mbox/"},{"id":116978,"url":"https://patchwork.plctlab.org/api/1.2/patches/116978/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230707054306.2810080-1-maskray@google.com/","msgid":"<20230707054306.2810080-1-maskray@google.com>","list_archive_url":null,"date":"2023-07-07T05:43:06","name":"[v3] PR30592 objcopy: allow --set-section-flags to add or remove SHF_X86_64_LARGE","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230707054306.2810080-1-maskray@google.com/mbox/"},{"id":117059,"url":"https://patchwork.plctlab.org/api/1.2/patches/117059/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230707101024.2863421-1-claziss@gmail.com/","msgid":"<20230707101024.2863421-1-claziss@gmail.com>","list_archive_url":null,"date":"2023-07-07T10:10:24","name":"[committed] arc: Update/Add ARCv3 support.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230707101024.2863421-1-claziss@gmail.com/mbox/"},{"id":117125,"url":"https://patchwork.plctlab.org/api/1.2/patches/117125/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d8cb6772-092f-b79e-421b-1da61ce020ac@suse.com/","msgid":"","list_archive_url":null,"date":"2023-07-07T12:01:07","name":"ld: fix build with old glibc / gcc","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d8cb6772-092f-b79e-421b-1da61ce020ac@suse.com/mbox/"},{"id":117135,"url":"https://patchwork.plctlab.org/api/1.2/patches/117135/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/88c2fb96-185d-ae27-c025-ed025ed54641@suse.com/","msgid":"<88c2fb96-185d-ae27-c025-ed025ed54641@suse.com>","list_archive_url":null,"date":"2023-07-07T13:47:35","name":"ld/PDB: fix off-by-1 in add_globals_ref()","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/88c2fb96-185d-ae27-c025-ed025ed54641@suse.com/mbox/"},{"id":117306,"url":"https://patchwork.plctlab.org/api/1.2/patches/117306/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/878rbrgzoz.fsf@gmail.com/","msgid":"<878rbrgzoz.fsf@gmail.com>","list_archive_url":null,"date":"2023-07-07T21:47:48","name":"objdump: Round ASCII art lines in jump visualization","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/878rbrgzoz.fsf@gmail.com/mbox/"},{"id":117387,"url":"https://patchwork.plctlab.org/api/1.2/patches/117387/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230708053035.528911-1-maskray@google.com/","msgid":"<20230708053035.528911-1-maskray@google.com>","list_archive_url":null,"date":"2023-07-08T05:30:35","name":"[v4] PR30592 objcopy: allow --set-section-flags to add or remove SHF_X86_64_LARGE","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230708053035.528911-1-maskray@google.com/mbox/"},{"id":118315,"url":"https://patchwork.plctlab.org/api/1.2/patches/118315/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230711083214.689474-1-jiawei@iscas.ac.cn/","msgid":"<20230711083214.689474-1-jiawei@iscas.ac.cn>","list_archive_url":null,"date":"2023-07-11T08:32:14","name":"[v2] RISC-V: Support Zca/f/d extensions.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230711083214.689474-1-jiawei@iscas.ac.cn/mbox/"},{"id":118324,"url":"https://patchwork.plctlab.org/api/1.2/patches/118324/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230711084931.18978-1-hejinyang@loongson.cn/","msgid":"<20230711084931.18978-1-hejinyang@loongson.cn>","list_archive_url":null,"date":"2023-07-11T08:49:30","name":"[1/2] LoongArch: bfd: Remove elf_seg_map condition in loongarch_elf_relax_section","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230711084931.18978-1-hejinyang@loongson.cn/mbox/"},{"id":118325,"url":"https://patchwork.plctlab.org/api/1.2/patches/118325/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230711084931.18978-2-hejinyang@loongson.cn/","msgid":"<20230711084931.18978-2-hejinyang@loongson.cn>","list_archive_url":null,"date":"2023-07-11T08:49:31","name":"[2/2] LoongArch: bfd: Add counter to get real relax region","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230711084931.18978-2-hejinyang@loongson.cn/mbox/"},{"id":118766,"url":"https://patchwork.plctlab.org/api/1.2/patches/118766/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZK4EFMJYmIzmJnh5@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-07-12T01:38:28","name":".noinit and .persistent alignment","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZK4EFMJYmIzmJnh5@squeak.grove.modra.org/mbox/"},{"id":118767,"url":"https://patchwork.plctlab.org/api/1.2/patches/118767/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZK4EZ3/IKANDAvI0@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-07-12T01:39:51","name":".noinit and .persistent for msp430","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZK4EZ3/IKANDAvI0@squeak.grove.modra.org/mbox/"},{"id":118801,"url":"https://patchwork.plctlab.org/api/1.2/patches/118801/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZK4j+R81iVz44wvm@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-07-12T03:54:33","name":"Support NEXT_SECTION in ALIGNOF and SIZEOF","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZK4j+R81iVz44wvm@squeak.grove.modra.org/mbox/"},{"id":119149,"url":"https://patchwork.plctlab.org/api/1.2/patches/119149/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230712124036.3385283-1-jiawei@iscas.ac.cn/","msgid":"<20230712124036.3385283-1-jiawei@iscas.ac.cn>","list_archive_url":null,"date":"2023-07-12T12:40:36","name":"[v2] RISC-V: Supports Zcb extension.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230712124036.3385283-1-jiawei@iscas.ac.cn/mbox/"},{"id":119190,"url":"https://patchwork.plctlab.org/api/1.2/patches/119190/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.LSU.2.20.2307121351250.13548@wotan.suse.de/","msgid":"","list_archive_url":null,"date":"2023-07-12T13:56:54","name":"Let '\''^'\'' through the lexer","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.LSU.2.20.2307121351250.13548@wotan.suse.de/mbox/"},{"id":119481,"url":"https://patchwork.plctlab.org/api/1.2/patches/119481/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/62b68369-0d02-3472-bbe6-cb627661252e@oracle.com/","msgid":"<62b68369-0d02-3472-bbe6-cb627661252e@oracle.com>","list_archive_url":null,"date":"2023-07-13T02:35:06","name":"Patch for version.texi?","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/62b68369-0d02-3472-bbe6-cb627661252e@oracle.com/mbox/"},{"id":119567,"url":"https://patchwork.plctlab.org/api/1.2/patches/119567/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230713063303.205862-2-haochen.jiang@intel.com/","msgid":"<20230713063303.205862-2-haochen.jiang@intel.com>","list_archive_url":null,"date":"2023-07-13T06:32:59","name":"[1/5] Support Intel AVX-VNNI-INT16","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230713063303.205862-2-haochen.jiang@intel.com/mbox/"},{"id":119565,"url":"https://patchwork.plctlab.org/api/1.2/patches/119565/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230713063303.205862-3-haochen.jiang@intel.com/","msgid":"<20230713063303.205862-3-haochen.jiang@intel.com>","list_archive_url":null,"date":"2023-07-13T06:33:00","name":"[2/5] Support Intel SHA512","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230713063303.205862-3-haochen.jiang@intel.com/mbox/"},{"id":119563,"url":"https://patchwork.plctlab.org/api/1.2/patches/119563/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230713063303.205862-4-haochen.jiang@intel.com/","msgid":"<20230713063303.205862-4-haochen.jiang@intel.com>","list_archive_url":null,"date":"2023-07-13T06:33:01","name":"[3/5] Support Intel SM3","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230713063303.205862-4-haochen.jiang@intel.com/mbox/"},{"id":119566,"url":"https://patchwork.plctlab.org/api/1.2/patches/119566/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230713063303.205862-5-haochen.jiang@intel.com/","msgid":"<20230713063303.205862-5-haochen.jiang@intel.com>","list_archive_url":null,"date":"2023-07-13T06:33:02","name":"[4/5] Support Intel SM4","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230713063303.205862-5-haochen.jiang@intel.com/mbox/"},{"id":119562,"url":"https://patchwork.plctlab.org/api/1.2/patches/119562/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230713063303.205862-6-haochen.jiang@intel.com/","msgid":"<20230713063303.205862-6-haochen.jiang@intel.com>","list_archive_url":null,"date":"2023-07-13T06:33:03","name":"[5/5] Support Intel PBNDKB","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230713063303.205862-6-haochen.jiang@intel.com/mbox/"},{"id":119993,"url":"https://patchwork.plctlab.org/api/1.2/patches/119993/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230713153738.2638727-1-vladimir.mezentsev@oracle.com/","msgid":"<20230713153738.2638727-1-vladimir.mezentsev@oracle.com>","list_archive_url":null,"date":"2023-07-13T15:37:38","name":"gprofng: 30602 [2.41] gprofng test hangs on i686-linux-gnu","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230713153738.2638727-1-vladimir.mezentsev@oracle.com/mbox/"},{"id":120205,"url":"https://patchwork.plctlab.org/api/1.2/patches/120205/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZLDCUfzWq0bZSyB4@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-07-14T03:34:41","name":"AIX_WEAK_SUPPORT","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZLDCUfzWq0bZSyB4@squeak.grove.modra.org/mbox/"},{"id":120206,"url":"https://patchwork.plctlab.org/api/1.2/patches/120206/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZLDCeFLsD6g+d1sB@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-07-14T03:35:20","name":"More tidies to objcopy archive handling","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZLDCeFLsD6g+d1sB@squeak.grove.modra.org/mbox/"},{"id":120207,"url":"https://patchwork.plctlab.org/api/1.2/patches/120207/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZLDClMEw/UQCGSPZ@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-07-14T03:35:48","name":"Fix loongarch build with gcc-4.5","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZLDClMEw/UQCGSPZ@squeak.grove.modra.org/mbox/"},{"id":120208,"url":"https://patchwork.plctlab.org/api/1.2/patches/120208/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZLDC03FCE+2lGiIo@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-07-14T03:36:51","name":"Make the default gas symbol hash table larger","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZLDC03FCE+2lGiIo@squeak.grove.modra.org/mbox/"},{"id":120326,"url":"https://patchwork.plctlab.org/api/1.2/patches/120326/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2350928d-ed93-91ed-8bcd-fce9902914b1@codesourcery.com/","msgid":"<2350928d-ed93-91ed-8bcd-fce9902914b1@codesourcery.com>","list_archive_url":null,"date":"2023-07-14T08:22:56","name":"'\''make pdf'\'' fails due to: [PATCH] Let '\''^'\'' through the lexer]","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2350928d-ed93-91ed-8bcd-fce9902914b1@codesourcery.com/mbox/"},{"id":120394,"url":"https://patchwork.plctlab.org/api/1.2/patches/120394/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/40ab94c5-d0c4-ee01-a53b-dbc6e5f3f9d2@suse.com/","msgid":"<40ab94c5-d0c4-ee01-a53b-dbc6e5f3f9d2@suse.com>","list_archive_url":null,"date":"2023-07-14T10:02:17","name":"[1/2] x86: simplify disassembly of LAR/LSL","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/40ab94c5-d0c4-ee01-a53b-dbc6e5f3f9d2@suse.com/mbox/"},{"id":120395,"url":"https://patchwork.plctlab.org/api/1.2/patches/120395/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7cc1eda0-713d-9172-c3ed-078e0899b0c4@suse.com/","msgid":"<7cc1eda0-713d-9172-c3ed-078e0899b0c4@suse.com>","list_archive_url":null,"date":"2023-07-14T10:02:39","name":"[2/2] x86: adjust disassembly of insns operating on selector values","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7cc1eda0-713d-9172-c3ed-078e0899b0c4@suse.com/mbox/"},{"id":120981,"url":"https://patchwork.plctlab.org/api/1.2/patches/120981/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZLR4TfHSewLy67fu@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-07-16T23:07:57","name":"PR10957, Missing option to really print section+offset","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZLR4TfHSewLy67fu@squeak.grove.modra.org/mbox/"},{"id":121117,"url":"https://patchwork.plctlab.org/api/1.2/patches/121117/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230717082229.2149099-1-mengqinggang@loongson.cn/","msgid":"<20230717082229.2149099-1-mengqinggang@loongson.cn>","list_archive_url":null,"date":"2023-07-17T08:22:28","name":"[1/2] LoongArch: Fix instruction immediate bug caused by sign-extend","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230717082229.2149099-1-mengqinggang@loongson.cn/mbox/"},{"id":121118,"url":"https://patchwork.plctlab.org/api/1.2/patches/121118/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230717082229.2149099-2-mengqinggang@loongson.cn/","msgid":"<20230717082229.2149099-2-mengqinggang@loongson.cn>","list_archive_url":null,"date":"2023-07-17T08:22:29","name":"[2/2] LoongArch: Fix immediate overflow check bug","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230717082229.2149099-2-mengqinggang@loongson.cn/mbox/"},{"id":121130,"url":"https://patchwork.plctlab.org/api/1.2/patches/121130/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230717084146.7978-1-tdevries@suse.de/","msgid":"<20230717084146.7978-1-tdevries@suse.de>","list_archive_url":null,"date":"2023-07-17T08:41:46","name":"[gdb/build] Fix Wlto-type-mismatch in opcodes/ft32-dis.c","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230717084146.7978-1-tdevries@suse.de/mbox/"},{"id":121835,"url":"https://patchwork.plctlab.org/api/1.2/patches/121835/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230718075412.1304548-1-haochen.jiang@intel.com/","msgid":"<20230718075412.1304548-1-haochen.jiang@intel.com>","list_archive_url":null,"date":"2023-07-18T07:54:12","name":"[v2] Support Intel SHA512","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230718075412.1304548-1-haochen.jiang@intel.com/mbox/"},{"id":121848,"url":"https://patchwork.plctlab.org/api/1.2/patches/121848/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230718080915.1391780-1-haochen.jiang@intel.com/","msgid":"<20230718080915.1391780-1-haochen.jiang@intel.com>","list_archive_url":null,"date":"2023-07-18T08:09:15","name":"[v2] Support Intel SM3","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230718080915.1391780-1-haochen.jiang@intel.com/mbox/"},{"id":121854,"url":"https://patchwork.plctlab.org/api/1.2/patches/121854/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230718081358.1394673-1-haochen.jiang@intel.com/","msgid":"<20230718081358.1394673-1-haochen.jiang@intel.com>","list_archive_url":null,"date":"2023-07-18T08:13:58","name":"[v2] Support Intel SM4","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230718081358.1394673-1-haochen.jiang@intel.com/mbox/"},{"id":122353,"url":"https://patchwork.plctlab.org/api/1.2/patches/122353/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZLc+98Th9pmqLTGc@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-07-19T01:40:07","name":"gas 32-bit host compile warnings","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZLc+98Th9pmqLTGc@squeak.grove.modra.org/mbox/"},{"id":122354,"url":"https://patchwork.plctlab.org/api/1.2/patches/122354/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZLc/HcP8ynwWNpO3@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-07-19T01:40:45","name":"Build all the objdump extensions with --enable-targets=all","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZLc/HcP8ynwWNpO3@squeak.grove.modra.org/mbox/"},{"id":122355,"url":"https://patchwork.plctlab.org/api/1.2/patches/122355/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZLc/RaA7zPjQQ2Sl@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-07-19T01:41:25","name":"Tidy binutils configure","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZLc/RaA7zPjQQ2Sl@squeak.grove.modra.org/mbox/"},{"id":122356,"url":"https://patchwork.plctlab.org/api/1.2/patches/122356/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZLc/ckC/wa90hisa@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-07-19T01:42:10","name":"[GOLD,PowerPC64] Debug info relocation overflow","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZLc/ckC/wa90hisa@squeak.grove.modra.org/mbox/"},{"id":122359,"url":"https://patchwork.plctlab.org/api/1.2/patches/122359/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230719021721.776961-1-mengqinggang@loongson.cn/","msgid":"<20230719021721.776961-1-mengqinggang@loongson.cn>","list_archive_url":null,"date":"2023-07-19T02:17:21","name":"LoongArch: ld: Simplify inserting IRELATIVE relocations to .rela.dyn","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230719021721.776961-1-mengqinggang@loongson.cn/mbox/"},{"id":122541,"url":"https://patchwork.plctlab.org/api/1.2/patches/122541/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0c22e147-aa0c-12ae-24e0-4f770948054d@debian.org/","msgid":"<0c22e147-aa0c-12ae-24e0-4f770948054d@debian.org>","list_archive_url":null,"date":"2023-07-19T10:54:58","name":"objcopy embeds the current time and ignores SOURCE_DATE_EPOCH making the output unreproducible","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0c22e147-aa0c-12ae-24e0-4f770948054d@debian.org/mbox/"},{"id":123087,"url":"https://patchwork.plctlab.org/api/1.2/patches/123087/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230720083213.2280286-1-haochen.jiang@intel.com/","msgid":"<20230720083213.2280286-1-haochen.jiang@intel.com>","list_archive_url":null,"date":"2023-07-20T08:32:13","name":"Support Intel SHA512","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230720083213.2280286-1-haochen.jiang@intel.com/mbox/"},{"id":123319,"url":"https://patchwork.plctlab.org/api/1.2/patches/123319/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/efa3944b8dddd45e171baa8c3939e8636ab2d6b8.camel@espressif.com/","msgid":"","list_archive_url":null,"date":"2023-07-20T14:39:14","name":"xtensa: add dynconfig option for ld/gas","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/efa3944b8dddd45e171baa8c3939e8636ab2d6b8.camel@espressif.com/mbox/"},{"id":123564,"url":"https://patchwork.plctlab.org/api/1.2/patches/123564/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230721053218.16817-1-hau.hsu@sifive.com/","msgid":"<20230721053218.16817-1-hau.hsu@sifive.com>","list_archive_url":null,"date":"2023-07-21T05:32:18","name":"RISC-V: Fix wrongly inserted IRELATIVE relocs","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230721053218.16817-1-hau.hsu@sifive.com/mbox/"},{"id":123611,"url":"https://patchwork.plctlab.org/api/1.2/patches/123611/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/32719c54-c66a-384e-d570-ebefe607e3e9@suse.com/","msgid":"<32719c54-c66a-384e-d570-ebefe607e3e9@suse.com>","list_archive_url":null,"date":"2023-07-21T07:12:50","name":"[RFC] x86: pack CPU flags in opcode table","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/32719c54-c66a-384e-d570-ebefe607e3e9@suse.com/mbox/"},{"id":123632,"url":"https://patchwork.plctlab.org/api/1.2/patches/123632/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230721074956.7188-2-piannetta@kalrayinc.com/","msgid":"<20230721074956.7188-2-piannetta@kalrayinc.com>","list_archive_url":null,"date":"2023-07-21T07:49:50","name":"[1/7] kvx: Add bf files.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230721074956.7188-2-piannetta@kalrayinc.com/mbox/"},{"id":123627,"url":"https://patchwork.plctlab.org/api/1.2/patches/123627/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230721074956.7188-3-piannetta@kalrayinc.com/","msgid":"<20230721074956.7188-3-piannetta@kalrayinc.com>","list_archive_url":null,"date":"2023-07-21T07:49:51","name":"[2/7] kvx: Add binutils files.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230721074956.7188-3-piannetta@kalrayinc.com/mbox/"},{"id":123629,"url":"https://patchwork.plctlab.org/api/1.2/patches/123629/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230721074956.7188-5-piannetta@kalrayinc.com/","msgid":"<20230721074956.7188-5-piannetta@kalrayinc.com>","list_archive_url":null,"date":"2023-07-21T07:49:53","name":"[4/7] kvx: Add ld files.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230721074956.7188-5-piannetta@kalrayinc.com/mbox/"},{"id":123635,"url":"https://patchwork.plctlab.org/api/1.2/patches/123635/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230721074956.7188-6-piannetta@kalrayinc.com/","msgid":"<20230721074956.7188-6-piannetta@kalrayinc.com>","list_archive_url":null,"date":"2023-07-21T07:49:54","name":"[5/7] kvx: Add include files.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230721074956.7188-6-piannetta@kalrayinc.com/mbox/"},{"id":123631,"url":"https://patchwork.plctlab.org/api/1.2/patches/123631/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230721074956.7188-8-piannetta@kalrayinc.com/","msgid":"<20230721074956.7188-8-piannetta@kalrayinc.com>","list_archive_url":null,"date":"2023-07-21T07:49:56","name":"[7/7] kvx: Add toplevel files.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230721074956.7188-8-piannetta@kalrayinc.com/mbox/"}],"public":true,"mbox":"https://patchwork.plctlab.org/bundle/patchwork-bot/binutils-gdb_2023-07/mbox/"}]' + bundle_name_list='binutils-gdb_2022-10 binutils-gdb_2022-09 binutils-gdb_2022-11 binutils-gdb_2022-12 binutils-gdb_2023-01 binutils-gdb_2023-02 binutils-gdb_2023-03 binutils-gdb_2023-04 binutils-gdb_2023-05 binutils-gdb_2023-06 binutils-gdb_2023-07' + [[ binutils-gdb_2022-10 binutils-gdb_2022-09 binutils-gdb_2022-11 binutils-gdb_2022-12 binutils-gdb_2023-01 binutils-gdb_2023-02 binutils-gdb_2023-03 binutils-gdb_2023-04 binutils-gdb_2023-05 binutils-gdb_2023-06 binutils-gdb_2023-07 =~ 2023-07 ]] ++ jq -rc --arg bundle_name binutils-gdb_2023-07 '.[] | select(.name==$bundle_name) | (.id|tostring)' ++ echo '[{"id":6,"url":"https://patchwork.plctlab.org/api/1.2/bundles/6/","web_url":"https://patchwork.plctlab.org/bundle/patchwork-bot/binutils-gdb_2022-10/","project":{"id":2,"url":"https://patchwork.plctlab.org/api/1.2/projects/2/","name":"binutils-gdb","link_name":"binutils-gdb","list_id":"binutils.sourceware.org","list_email":"binutils@sourceware.org","web_url":"https://github.com/wangliu-iscas/Patchwork-Bundles/blob/main/binutils-gdb.md","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"name":"binutils-gdb_2022-10","owner":{"id":3,"url":"https://patchwork.plctlab.org/api/1.2/users/3/","username":"patchwork-bot","first_name":"","last_name":"","email":"ouuuleilei@gmail.com"},"patches":[{"id":1592,"url":"https://patchwork.plctlab.org/api/1.2/patches/1592/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/385d01fd-7e57-1f3f-1bae-30aa0c313d63@suse.com/","msgid":"<385d01fd-7e57-1f3f-1bae-30aa0c313d63@suse.com>","list_archive_url":null,"date":"2022-09-30T11:59:45","name":"[3/4] RISC-V/gas: don'\''t open-code insn_length()","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/385d01fd-7e57-1f3f-1bae-30aa0c313d63@suse.com/mbox/"},{"id":1594,"url":"https://patchwork.plctlab.org/api/1.2/patches/1594/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f5757acf-7b90-a0e3-5eea-3b97cc226930@suse.com/","msgid":"","list_archive_url":null,"date":"2022-09-30T12:00:12","name":"[4/4] RISC-V/gas: allow generating up to 176-bit instructions with .insn","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f5757acf-7b90-a0e3-5eea-3b97cc226930@suse.com/mbox/"},{"id":1596,"url":"https://patchwork.plctlab.org/api/1.2/patches/1596/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930140503.38233-1-chigot@adacore.com/","msgid":"<20220930140503.38233-1-chigot@adacore.com>","list_archive_url":null,"date":"2022-09-30T14:05:03","name":"ld/testsuite: consistently add board_ldflags when linking with GCC","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930140503.38233-1-chigot@adacore.com/mbox/"},{"id":1619,"url":"https://patchwork.plctlab.org/api/1.2/patches/1619/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221001014451.532772-1-maskray@google.com/","msgid":"<20221001014451.532772-1-maskray@google.com>","list_archive_url":null,"date":"2022-10-01T01:44:51","name":"gold, dwp: support zstd compressed input debug sections [PR 29641]","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221001014451.532772-1-maskray@google.com/mbox/"},{"id":1620,"url":"https://patchwork.plctlab.org/api/1.2/patches/1620/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221001023846.590825-1-maskray@google.com/","msgid":"<20221001023846.590825-1-maskray@google.com>","list_archive_url":null,"date":"2022-10-01T02:38:46","name":"gold: add --compress-debug-sections=zstd [PR 29641]","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221001023846.590825-1-maskray@google.com/mbox/"},{"id":1623,"url":"https://patchwork.plctlab.org/api/1.2/patches/1623/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b4477c7f666bdeb7f8e998633c7b0cb62310b9ef.1664599545.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-01T04:45:52","name":"[RFC,1/1] RISC-V: Implement common register pair framework","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b4477c7f666bdeb7f8e998633c7b0cb62310b9ef.1664599545.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1625,"url":"https://patchwork.plctlab.org/api/1.2/patches/1625/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/53a265a1f14d17a6f7b106082f610994c5d546e0.1664602025.git.research_trasio@irq.a4lg.com/","msgid":"<53a265a1f14d17a6f7b106082f610994c5d546e0.1664602025.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-01T05:27:31","name":"[RFC,1/1] RISC-V: Implement extension variants","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/53a265a1f14d17a6f7b106082f610994c5d546e0.1664602025.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1626,"url":"https://patchwork.plctlab.org/api/1.2/patches/1626/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8db04962aba9c780f133840a8934353a58f223fe.1664602716.git.research_trasio@irq.a4lg.com/","msgid":"<8db04962aba9c780f133840a8934353a58f223fe.1664602716.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-01T05:39:26","name":"[1/1] RISC-V: Move supervisor instructions after all unprivileged ones","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8db04962aba9c780f133840a8934353a58f223fe.1664602716.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1627,"url":"https://patchwork.plctlab.org/api/1.2/patches/1627/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221001062057.681440-1-maskray@google.com/","msgid":"<20221001062057.681440-1-maskray@google.com>","list_archive_url":null,"date":"2022-10-01T06:20:57","name":"readelf: support zstd compressed debug sections [PR 29640]","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221001062057.681440-1-maskray@google.com/mbox/"},{"id":1631,"url":"https://patchwork.plctlab.org/api/1.2/patches/1631/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/619f112539c0bdecd58e25664f1250a3479a37f5.1664707612.git.aburgess@redhat.com/","msgid":"<619f112539c0bdecd58e25664f1250a3479a37f5.1664707612.git.aburgess@redhat.com>","list_archive_url":null,"date":"2022-10-02T10:47:52","name":"[PATCHv2,2/2] opcodes/arm: add disassembler styling for arm","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/619f112539c0bdecd58e25664f1250a3479a37f5.1664707612.git.aburgess@redhat.com/mbox/"},{"id":1635,"url":"https://patchwork.plctlab.org/api/1.2/patches/1635/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221002185433.gl7dvytfh5wthifx@lug-owl.de/","msgid":"<20221002185433.gl7dvytfh5wthifx@lug-owl.de>","list_archive_url":null,"date":"2022-10-02T18:54:33","name":"diagnostics.h: GCC 13 got -Wself-move, breaks GDB build","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221002185433.gl7dvytfh5wthifx@lug-owl.de/mbox/"},{"id":1637,"url":"https://patchwork.plctlab.org/api/1.2/patches/1637/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003014313.28766-1-mark@harmstone.com/","msgid":"<20221003014313.28766-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-03T01:43:12","name":"[1/2] ld: Add --pdb option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003014313.28766-1-mark@harmstone.com/mbox/"},{"id":1638,"url":"https://patchwork.plctlab.org/api/1.2/patches/1638/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003014313.28766-2-mark@harmstone.com/","msgid":"<20221003014313.28766-2-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-03T01:43:13","name":"[2/2] ld: Add minimal pdb generation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003014313.28766-2-mark@harmstone.com/mbox/"},{"id":1640,"url":"https://patchwork.plctlab.org/api/1.2/patches/1640/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/597ed978-d121-220c-b56b-2ffb94bd091c@suse.cz/","msgid":"<597ed978-d121-220c-b56b-2ffb94bd091c@suse.cz>","list_archive_url":null,"date":"2022-10-03T07:50:38","name":"[1/2] refactor usage of compressed_debug_section_type","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/597ed978-d121-220c-b56b-2ffb94bd091c@suse.cz/mbox/"},{"id":1641,"url":"https://patchwork.plctlab.org/api/1.2/patches/1641/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b8acdd83-f33a-74b8-e21a-23719a0b1a60@suse.cz/","msgid":"","list_archive_url":null,"date":"2022-10-03T07:50:44","name":"[2/2] add --enable-default-compressed-debug-sections-algorithm configure option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b8acdd83-f33a-74b8-e21a-23719a0b1a60@suse.cz/mbox/"},{"id":1642,"url":"https://patchwork.plctlab.org/api/1.2/patches/1642/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003101328.1790113-1-aburgess@redhat.com/","msgid":"<20221003101328.1790113-1-aburgess@redhat.com>","list_archive_url":null,"date":"2022-10-03T10:13:28","name":"opcodes/riscv: style csr names as registers","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003101328.1790113-1-aburgess@redhat.com/mbox/"},{"id":1643,"url":"https://patchwork.plctlab.org/api/1.2/patches/1643/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7ba14fc4472ce97d4f7a4433cad8a571e89f82f4.1664793840.git.research_trasio@irq.a4lg.com/","msgid":"<7ba14fc4472ce97d4f7a4433cad8a571e89f82f4.1664793840.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-03T10:43:59","name":"[v3,1/6] RISC-V: Fix immediates to have \"immediate\" style","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7ba14fc4472ce97d4f7a4433cad8a571e89f82f4.1664793840.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1644,"url":"https://patchwork.plctlab.org/api/1.2/patches/1644/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a498bec37c1fd1dcda57cbf95e5f8cfba09b31d3.1664793840.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-03T10:44:00","name":"[v3,2/6] RISC-V: Fix printf argument types corresponding %x","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a498bec37c1fd1dcda57cbf95e5f8cfba09b31d3.1664793840.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1647,"url":"https://patchwork.plctlab.org/api/1.2/patches/1647/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0002ea716713ace4998a33dde0b81f4f890d10bf.1664793840.git.research_trasio@irq.a4lg.com/","msgid":"<0002ea716713ace4998a33dde0b81f4f890d10bf.1664793840.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-03T10:44:01","name":"[v3,3/6] RISC-V: Optimize riscv_disassemble_data printf","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0002ea716713ace4998a33dde0b81f4f890d10bf.1664793840.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1646,"url":"https://patchwork.plctlab.org/api/1.2/patches/1646/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c65fc3e9aa58965d6768a28c9fd7467fea9897a5.1664793840.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-03T10:44:02","name":"[v3,4/6] RISC-V: Print comma and tabs as the \"text\" style","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c65fc3e9aa58965d6768a28c9fd7467fea9897a5.1664793840.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1648,"url":"https://patchwork.plctlab.org/api/1.2/patches/1648/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5abe1d8a7694417b990e11d8f6cd6789573872e5.1664793840.git.research_trasio@irq.a4lg.com/","msgid":"<5abe1d8a7694417b990e11d8f6cd6789573872e5.1664793840.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-03T10:44:03","name":"[v3,5/6] RISC-V: Fix T-Head immediate types on printing","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5abe1d8a7694417b990e11d8f6cd6789573872e5.1664793840.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1649,"url":"https://patchwork.plctlab.org/api/1.2/patches/1649/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0b68af932117258c908db62cf87c3a15d3cdec41.1664793840.git.research_trasio@irq.a4lg.com/","msgid":"<0b68af932117258c908db62cf87c3a15d3cdec41.1664793840.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-03T10:44:04","name":"[v3,6/6] RISC-V: Print XTheadMemPair literal as \"immediate\"","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0b68af932117258c908db62cf87c3a15d3cdec41.1664793840.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1656,"url":"https://patchwork.plctlab.org/api/1.2/patches/1656/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/87lepxcd6x.fsf@redhat.com/","msgid":"<87lepxcd6x.fsf@redhat.com>","list_archive_url":null,"date":"2022-10-03T12:19:02","name":"Commit: readelf: Do not load section data from offset 0","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/87lepxcd6x.fsf@redhat.com/mbox/"},{"id":1659,"url":"https://patchwork.plctlab.org/api/1.2/patches/1659/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e0d369d419da9c0441f415da7f54352aead8f655.1664707612.git.aburgess@redhat.com/","msgid":"","list_archive_url":null,"date":"2022-10-03T16:37:36","name":"[PATCHv2,1/2] opcodes/arm: use '\''@'\'' consistently for the comment character","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e0d369d419da9c0441f415da7f54352aead8f655.1664707612.git.aburgess@redhat.com/mbox/"},{"id":1660,"url":"https://patchwork.plctlab.org/api/1.2/patches/1660/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003165848.11142-1-palmer@rivosinc.com/","msgid":"<20221003165848.11142-1-palmer@rivosinc.com>","list_archive_url":null,"date":"2022-10-03T16:58:48","name":"gas: NEWS: Mention the T-Head extensions that were recently added","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003165848.11142-1-palmer@rivosinc.com/mbox/"},{"id":1671,"url":"https://patchwork.plctlab.org/api/1.2/patches/1671/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/YzvrMEdkXjIn5Lfz@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-04T08:13:36","name":"Support objcopy changing compression to or from zstd","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/YzvrMEdkXjIn5Lfz@squeak.grove.modra.org/mbox/"},{"id":1673,"url":"https://patchwork.plctlab.org/api/1.2/patches/1673/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0bc857d306bb7c8130e5328dbe6b9ed2fed3ef87.1664873933.git.research_trasio@irq.a4lg.com/","msgid":"<0bc857d306bb7c8130e5328dbe6b9ed2fed3ef87.1664873933.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-04T08:59:07","name":"[1/2] RISC-V: Fix buffer overflow on print_insn_riscv","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0bc857d306bb7c8130e5328dbe6b9ed2fed3ef87.1664873933.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1672,"url":"https://patchwork.plctlab.org/api/1.2/patches/1672/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/89612fe01d902007bf84a7dfb0df5f85d5c166e4.1664873933.git.research_trasio@irq.a4lg.com/","msgid":"<89612fe01d902007bf84a7dfb0df5f85d5c166e4.1664873933.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-04T08:59:08","name":"[2/2] gdb/riscv: Fix buffer overflow on riscv_insn::fetch_instruction","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/89612fe01d902007bf84a7dfb0df5f85d5c166e4.1664873933.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1676,"url":"https://patchwork.plctlab.org/api/1.2/patches/1676/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fc849c94f4adcac1c4ccc5508c7a145a2f13b2a9.1664876744.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-04T09:45:49","name":"[v2,1/2] RISC-V: Fix buffer overflow on print_insn_riscv","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fc849c94f4adcac1c4ccc5508c7a145a2f13b2a9.1664876744.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1677,"url":"https://patchwork.plctlab.org/api/1.2/patches/1677/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4eb6e59ae2e790dbbf2bc92477edd281648d8814.1664876744.git.research_trasio@irq.a4lg.com/","msgid":"<4eb6e59ae2e790dbbf2bc92477edd281648d8814.1664876744.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-04T09:45:50","name":"[v2,2/2] gdb/riscv: Partial support for instructions up to 176-bits","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4eb6e59ae2e790dbbf2bc92477edd281648d8814.1664876744.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1678,"url":"https://patchwork.plctlab.org/api/1.2/patches/1678/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ebf16f9e1f45115d0793952ccb4a94d4233303f9.1664882725.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-04T11:25:56","name":"[v3,1/2] RISC-V: Fix buffer overflow on print_insn_riscv","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ebf16f9e1f45115d0793952ccb4a94d4233303f9.1664882725.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1679,"url":"https://patchwork.plctlab.org/api/1.2/patches/1679/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/83464b09b8649525259c69c853dfa2c9575a204b.1664882725.git.research_trasio@irq.a4lg.com/","msgid":"<83464b09b8649525259c69c853dfa2c9575a204b.1664882725.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-04T11:25:57","name":"[v3,2/2] gdb/riscv: Partial support for instructions up to 176-bit","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/83464b09b8649525259c69c853dfa2c9575a204b.1664882725.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1681,"url":"https://patchwork.plctlab.org/api/1.2/patches/1681/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ffa9c1d7-e8c2-a62b-ef3e-b565c0ffbe5b@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-04T13:56:27","name":"RISC-V: Zicbo{m,p,z} adjustments to riscv_multi_subset_supports_ext()","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ffa9c1d7-e8c2-a62b-ef3e-b565c0ffbe5b@suse.com/mbox/"},{"id":1690,"url":"https://patchwork.plctlab.org/api/1.2/patches/1690/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221004161720.1963953-1-vladimir.mezentsev@oracle.com/","msgid":"<20221004161720.1963953-1-vladimir.mezentsev@oracle.com>","list_archive_url":null,"date":"2022-10-04T16:17:20","name":"gprofng: fix build with --enable-pgo-build=lto","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221004161720.1963953-1-vladimir.mezentsev@oracle.com/mbox/"},{"id":1691,"url":"https://patchwork.plctlab.org/api/1.2/patches/1691/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c0211bc9c57be6c79c6d878ce147f63b657f461d.camel@espressif.com/","msgid":"","list_archive_url":null,"date":"2022-10-04T16:22:05","name":"bfd: xtensa: fix __stop_SECTION literal drop,","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c0211bc9c57be6c79c6d878ce147f63b657f461d.camel@espressif.com/mbox/"},{"id":1702,"url":"https://patchwork.plctlab.org/api/1.2/patches/1702/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5f482299-6c60-b2b3-9abe-f4a55a5a26c5@univ-grenoble-alpes.fr/","msgid":"<5f482299-6c60-b2b3-9abe-f4a55a5a26c5@univ-grenoble-alpes.fr>","list_archive_url":null,"date":"2022-10-04T20:03:20","name":"[RFC] bfd: use bfd_vma for the 64-bit version of put[lb] and get[lb]","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5f482299-6c60-b2b3-9abe-f4a55a5a26c5@univ-grenoble-alpes.fr/mbox/"},{"id":1711,"url":"https://patchwork.plctlab.org/api/1.2/patches/1711/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Yz0Gsxdxe0TePbJT@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-05T04:23:15","name":"PR29647, objdump -S looping","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Yz0Gsxdxe0TePbJT@squeak.grove.modra.org/mbox/"},{"id":1712,"url":"https://patchwork.plctlab.org/api/1.2/patches/1712/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/02d747d2-f57b-0fb5-b893-842b6cc41f2f@suse.com/","msgid":"<02d747d2-f57b-0fb5-b893-842b6cc41f2f@suse.com>","list_archive_url":null,"date":"2022-10-05T07:20:47","name":"[v3,1/7] x86: constify parse_insn()'\''s input","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/02d747d2-f57b-0fb5-b893-842b6cc41f2f@suse.com/mbox/"},{"id":1713,"url":"https://patchwork.plctlab.org/api/1.2/patches/1713/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/925cb740-4e1b-abc4-8526-aaab6faae5e1@suse.com/","msgid":"<925cb740-4e1b-abc4-8526-aaab6faae5e1@suse.com>","list_archive_url":null,"date":"2022-10-05T07:22:19","name":"[v3,2/7] x86: introduce Pass2 insn attribute","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/925cb740-4e1b-abc4-8526-aaab6faae5e1@suse.com/mbox/"},{"id":1714,"url":"https://patchwork.plctlab.org/api/1.2/patches/1714/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e16d3e78-39ca-f715-508f-a4104b8ab9a9@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-05T07:23:51","name":"[v3,3/7] x86: re-work insn/suffix recognition","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e16d3e78-39ca-f715-508f-a4104b8ab9a9@suse.com/mbox/"},{"id":1715,"url":"https://patchwork.plctlab.org/api/1.2/patches/1715/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e4e4b80b-794c-7485-1997-685adab8fb27@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-05T07:24:20","name":"[v3,4/7] x86-64: further re-work insn/suffix recognition to also cover MOVSL","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e4e4b80b-794c-7485-1997-685adab8fb27@suse.com/mbox/"},{"id":1716,"url":"https://patchwork.plctlab.org/api/1.2/patches/1716/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/540678fc-8bff-ec68-c97c-478d2631998c@suse.com/","msgid":"<540678fc-8bff-ec68-c97c-478d2631998c@suse.com>","list_archive_url":null,"date":"2022-10-05T07:24:55","name":"[v3,5/7] ix86: don'\''t recognize/derive Q suffix in the common case","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/540678fc-8bff-ec68-c97c-478d2631998c@suse.com/mbox/"},{"id":1718,"url":"https://patchwork.plctlab.org/api/1.2/patches/1718/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e4692495-7d3d-074d-14f9-364d4a9a998c@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-05T07:25:25","name":"[v3,6/7] x86-64: allow HLE store of accumulator to absolute 32-bit address","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e4692495-7d3d-074d-14f9-364d4a9a998c@suse.com/mbox/"},{"id":1717,"url":"https://patchwork.plctlab.org/api/1.2/patches/1717/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e8014ebd-d16b-17a7-9f34-3700fc164136@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-05T07:25:57","name":"[v3,7/7] x86: move bad-use-of-TLS-reloc check","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e8014ebd-d16b-17a7-9f34-3700fc164136@suse.com/mbox/"},{"id":1719,"url":"https://patchwork.plctlab.org/api/1.2/patches/1719/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1266f001-4511-2662-dba9-14b4d0317c57@suse.com/","msgid":"<1266f001-4511-2662-dba9-14b4d0317c57@suse.com>","list_archive_url":null,"date":"2022-10-05T07:40:50","name":"x86: drop \"regmask\" static variable","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1266f001-4511-2662-dba9-14b4d0317c57@suse.com/mbox/"},{"id":1751,"url":"https://patchwork.plctlab.org/api/1.2/patches/1751/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/af45c5d57c221e43101c2aa38b14f4b4ac12d011.1665031170.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-06T04:40:15","name":"[v2,1/2] RISC-V: Fallback for instructions longer than 64b","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/af45c5d57c221e43101c2aa38b14f4b4ac12d011.1665031170.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1752,"url":"https://patchwork.plctlab.org/api/1.2/patches/1752/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c6e55781245dd3e8e9b8debd6130fc5449dfbd55.1665031170.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-06T04:40:16","name":"[v2,2/2] RISC-V: Improve \"bits undefined\" diagnostics","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c6e55781245dd3e8e9b8debd6130fc5449dfbd55.1665031170.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1776,"url":"https://patchwork.plctlab.org/api/1.2/patches/1776/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d52952119e15357c0e823f8a2398999359588b4d.1665050099.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-06T09:56:30","name":"[v3,1/2] RISC-V: Fallback for instructions longer than 64b","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d52952119e15357c0e823f8a2398999359588b4d.1665050099.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1777,"url":"https://patchwork.plctlab.org/api/1.2/patches/1777/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d907b1997f60ff7823c4a23e281ec9d8ddcbf3f1.1665050099.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-06T09:56:31","name":"[v3,2/2] RISC-V: Improve \"bits undefined\" diagnostics","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d907b1997f60ff7823c4a23e281ec9d8ddcbf3f1.1665050099.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1781,"url":"https://patchwork.plctlab.org/api/1.2/patches/1781/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221006114628.304185-1-chigot@adacore.com/","msgid":"<20221006114628.304185-1-chigot@adacore.com>","list_archive_url":null,"date":"2022-10-06T11:46:28","name":"RISC-V: fix linker message when relaxation deletes bytes","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221006114628.304185-1-chigot@adacore.com/mbox/"},{"id":1801,"url":"https://patchwork.plctlab.org/api/1.2/patches/1801/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Yz+Yhyg7UewC9/kp@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-07T03:09:59","name":"PR29653, objcopy/strip: fuzzed small input file induces large output file","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Yz+Yhyg7UewC9/kp@squeak.grove.modra.org/mbox/"},{"id":1803,"url":"https://patchwork.plctlab.org/api/1.2/patches/1803/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/PH1P110MB16505D9D39EC5B1DE22FE3D5EC5F9@PH1P110MB1650.NAMP110.PROD.OUTLOOK.COM/","msgid":"","list_archive_url":null,"date":"2022-10-07T04:10:07","name":"@CPP_FOR_BUILD@ problem since binutils-2.38","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/PH1P110MB16505D9D39EC5B1DE22FE3D5EC5F9@PH1P110MB1650.NAMP110.PROD.OUTLOOK.COM/mbox/"},{"id":1827,"url":"https://patchwork.plctlab.org/api/1.2/patches/1827/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8e13bce108ac10a0c1dd911e23ec572926f7ae44.1665203374.git.research_trasio@irq.a4lg.com/","msgid":"<8e13bce108ac10a0c1dd911e23ec572926f7ae44.1665203374.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-08T04:29:53","name":"[v2,1/1] RISC-V: Test DWARF register numbers for \"fp\"","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8e13bce108ac10a0c1dd911e23ec572926f7ae44.1665203374.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1828,"url":"https://patchwork.plctlab.org/api/1.2/patches/1828/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0883001b3572e54d3fba264429c7ade2adb66610.1665203441.git.research_trasio@irq.a4lg.com/","msgid":"<0883001b3572e54d3fba264429c7ade2adb66610.1665203441.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-08T04:31:15","name":"[1/1] RISC-V: Move standard hints before all instructions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0883001b3572e54d3fba264429c7ade2adb66610.1665203441.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1829,"url":"https://patchwork.plctlab.org/api/1.2/patches/1829/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/58e16a241d7376fcae2515c6bd5a2b41d275eeba.1665203531.git.research_trasio@irq.a4lg.com/","msgid":"<58e16a241d7376fcae2515c6bd5a2b41d275eeba.1665203531.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-08T04:32:18","name":"[RFC,1/1] RISC-V: Imply '\''Zicsr'\'' from privileged extensions with CSRs","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/58e16a241d7376fcae2515c6bd5a2b41d275eeba.1665203531.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1830,"url":"https://patchwork.plctlab.org/api/1.2/patches/1830/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/cb5076fc96e8f2097779a3abcde843dcdd660031.1665203660.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-08T04:34:23","name":"[1/5] opcodes/riscv-dis.c: Tidying with comments/clarity","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/cb5076fc96e8f2097779a3abcde843dcdd660031.1665203660.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1832,"url":"https://patchwork.plctlab.org/api/1.2/patches/1832/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1f1aa0838bf9c4f10a45fcfe3c682f7efc79d9ae.1665203660.git.research_trasio@irq.a4lg.com/","msgid":"<1f1aa0838bf9c4f10a45fcfe3c682f7efc79d9ae.1665203660.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-08T04:34:24","name":"[2/5] opcodes/riscv-dis.c: Tidying with spacing","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1f1aa0838bf9c4f10a45fcfe3c682f7efc79d9ae.1665203660.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1831,"url":"https://patchwork.plctlab.org/api/1.2/patches/1831/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/740bc5e2d2618d236519b39fedd1a1d7ae4e05da.1665203660.git.research_trasio@irq.a4lg.com/","msgid":"<740bc5e2d2618d236519b39fedd1a1d7ae4e05da.1665203660.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-08T04:34:25","name":"[3/5] opcodes/riscv-dis.c: Use bool type whenever possible","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/740bc5e2d2618d236519b39fedd1a1d7ae4e05da.1665203660.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1833,"url":"https://patchwork.plctlab.org/api/1.2/patches/1833/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6e3a9c235e317f441b4383b3daa68f2051bdc149.1665203660.git.research_trasio@irq.a4lg.com/","msgid":"<6e3a9c235e317f441b4383b3daa68f2051bdc149.1665203660.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-08T04:34:26","name":"[4/5] opcodes/riscv-dis.c: Make XLEN variable static","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6e3a9c235e317f441b4383b3daa68f2051bdc149.1665203660.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1834,"url":"https://patchwork.plctlab.org/api/1.2/patches/1834/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ad929233a62d887495122721340b2f9c80392963.1665203660.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-08T04:34:27","name":"[5/5] opcodes/riscv-dis.c: Remove last_map_state","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ad929233a62d887495122721340b2f9c80392963.1665203660.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1836,"url":"https://patchwork.plctlab.org/api/1.2/patches/1836/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d07e2b6f36ea2fd5830924a9bfeda941b774b687.1665290422.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-09T05:09:22","name":"RISC-V: Move certain arrays to riscv-opc.c","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d07e2b6f36ea2fd5830924a9bfeda941b774b687.1665290422.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1844,"url":"https://patchwork.plctlab.org/api/1.2/patches/1844/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010004623.16582-1-mark@harmstone.com/","msgid":"<20221010004623.16582-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-10T00:46:22","name":"[v2,1/2] ld: Add --pdb option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010004623.16582-1-mark@harmstone.com/mbox/"},{"id":1845,"url":"https://patchwork.plctlab.org/api/1.2/patches/1845/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010004623.16582-2-mark@harmstone.com/","msgid":"<20221010004623.16582-2-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-10T00:46:23","name":"[v2,2/2] ld: Add minimal pdb generation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010004623.16582-2-mark@harmstone.com/mbox/"},{"id":1890,"url":"https://patchwork.plctlab.org/api/1.2/patches/1890/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010200433.414320-1-vladimir.mezentsev@oracle.com/","msgid":"<20221010200433.414320-1-vladimir.mezentsev@oracle.com>","list_archive_url":null,"date":"2022-10-10T20:04:33","name":"gprofng: run tests without installation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010200433.414320-1-vladimir.mezentsev@oracle.com/mbox/"},{"id":1893,"url":"https://patchwork.plctlab.org/api/1.2/patches/1893/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010230426.719238-1-vladimir.mezentsev@oracle.com/","msgid":"<20221010230426.719238-1-vladimir.mezentsev@oracle.com>","list_archive_url":null,"date":"2022-10-10T23:04:26","name":"[2/2] gprofng: use the --libdir path to find libraries","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010230426.719238-1-vladimir.mezentsev@oracle.com/mbox/"},{"id":1894,"url":"https://patchwork.plctlab.org/api/1.2/patches/1894/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010235155.842469-1-vladimir.mezentsev@oracle.com/","msgid":"<20221010235155.842469-1-vladimir.mezentsev@oracle.com>","list_archive_url":null,"date":"2022-10-10T23:51:55","name":"[3/3] gprofng: no need to build version.texi","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010235155.842469-1-vladimir.mezentsev@oracle.com/mbox/"},{"id":1895,"url":"https://patchwork.plctlab.org/api/1.2/patches/1895/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011003702.4287-1-mark@harmstone.com/","msgid":"<20221011003702.4287-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-11T00:37:01","name":"[v3,1/2] ld: Add --pdb option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011003702.4287-1-mark@harmstone.com/mbox/"},{"id":1897,"url":"https://patchwork.plctlab.org/api/1.2/patches/1897/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011003702.4287-2-mark@harmstone.com/","msgid":"<20221011003702.4287-2-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-11T00:37:02","name":"[v3,2/2] ld: Add minimal pdb generation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011003702.4287-2-mark@harmstone.com/mbox/"},{"id":1928,"url":"https://patchwork.plctlab.org/api/1.2/patches/1928/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011175332.17156-1-mark@harmstone.com/","msgid":"<20221011175332.17156-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-11T17:53:31","name":"[v4,1/2] ld: Add --pdb option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011175332.17156-1-mark@harmstone.com/mbox/"},{"id":1929,"url":"https://patchwork.plctlab.org/api/1.2/patches/1929/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011175332.17156-2-mark@harmstone.com/","msgid":"<20221011175332.17156-2-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-11T17:53:32","name":"[v4,2/2] ld: Add minimal pdb generation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011175332.17156-2-mark@harmstone.com/mbox/"},{"id":1941,"url":"https://patchwork.plctlab.org/api/1.2/patches/1941/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221012031005.237446-1-simon.marchi@polymtl.ca/","msgid":"<20221012031005.237446-1-simon.marchi@polymtl.ca>","list_archive_url":null,"date":"2022-10-12T03:10:05","name":"[pushed] Re-apply \"Pass PKG_CONFIG_PATH down from top-level Makefile\"","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221012031005.237446-1-simon.marchi@polymtl.ca/mbox/"},{"id":1976,"url":"https://patchwork.plctlab.org/api/1.2/patches/1976/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1216a3f8-2273-8681-f528-9493a66891f0@suse.com/","msgid":"<1216a3f8-2273-8681-f528-9493a66891f0@suse.com>","list_archive_url":null,"date":"2022-10-13T08:16:49","name":"[v4,1/8] x86: constify parse_insn()'\''s input","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1216a3f8-2273-8681-f528-9493a66891f0@suse.com/mbox/"},{"id":1977,"url":"https://patchwork.plctlab.org/api/1.2/patches/1977/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/11599bbe-c779-aa9f-4d5d-c2243f0e69dc@suse.com/","msgid":"<11599bbe-c779-aa9f-4d5d-c2243f0e69dc@suse.com>","list_archive_url":null,"date":"2022-10-13T08:17:17","name":"[v4,2/8] x86: introduce Pass2 insn attribute","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/11599bbe-c779-aa9f-4d5d-c2243f0e69dc@suse.com/mbox/"},{"id":1978,"url":"https://patchwork.plctlab.org/api/1.2/patches/1978/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/357273a3-060c-23db-72da-3fc9d1be3d2a@suse.com/","msgid":"<357273a3-060c-23db-72da-3fc9d1be3d2a@suse.com>","list_archive_url":null,"date":"2022-10-13T08:18:09","name":"[v4,3/8] x86: re-work insn/suffix recognition","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/357273a3-060c-23db-72da-3fc9d1be3d2a@suse.com/mbox/"},{"id":1979,"url":"https://patchwork.plctlab.org/api/1.2/patches/1979/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0ec0587f-6a7b-45b6-8346-e5d774e73636@suse.com/","msgid":"<0ec0587f-6a7b-45b6-8346-e5d774e73636@suse.com>","list_archive_url":null,"date":"2022-10-13T08:18:39","name":"[v4,4/8] x86-64: further re-work insn/suffix recognition to also cover MOVSL","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0ec0587f-6a7b-45b6-8346-e5d774e73636@suse.com/mbox/"},{"id":1980,"url":"https://patchwork.plctlab.org/api/1.2/patches/1980/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fb617d0b-8759-3169-5a65-1178b7fef3d7@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-13T08:19:34","name":"[v4,5/8] ix86: don'\''t recognize/derive Q suffix in the common case","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fb617d0b-8759-3169-5a65-1178b7fef3d7@suse.com/mbox/"},{"id":1981,"url":"https://patchwork.plctlab.org/api/1.2/patches/1981/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1df3bd01-99c5-f56c-d937-970edd42b2b8@suse.com/","msgid":"<1df3bd01-99c5-f56c-d937-970edd42b2b8@suse.com>","list_archive_url":null,"date":"2022-10-13T08:20:14","name":"[v4,6/8] x86-64: allow HLE store of accumulator to absolute 32-bit address","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1df3bd01-99c5-f56c-d937-970edd42b2b8@suse.com/mbox/"},{"id":1982,"url":"https://patchwork.plctlab.org/api/1.2/patches/1982/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8486a218-39ec-16b2-5c6c-5037196b93cf@suse.com/","msgid":"<8486a218-39ec-16b2-5c6c-5037196b93cf@suse.com>","list_archive_url":null,"date":"2022-10-13T08:21:00","name":"[v4,7/8] x86: move bad-use-of-TLS-reloc check","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8486a218-39ec-16b2-5c6c-5037196b93cf@suse.com/mbox/"},{"id":1983,"url":"https://patchwork.plctlab.org/api/1.2/patches/1983/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7d82692d-93df-fbee-9efb-2f44e8a91df3@suse.com/","msgid":"<7d82692d-93df-fbee-9efb-2f44e8a91df3@suse.com>","list_archive_url":null,"date":"2022-10-13T08:22:00","name":"[v4,8/8] x86: drop (now) stray IsString","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7d82692d-93df-fbee-9efb-2f44e8a91df3@suse.com/mbox/"},{"id":2013,"url":"https://patchwork.plctlab.org/api/1.2/patches/2013/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8ab93d7a617ad480dd786210f46db0e5aa07d1ac.1665655719.git.research_trasio@irq.a4lg.com/","msgid":"<8ab93d7a617ad480dd786210f46db0e5aa07d1ac.1665655719.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-13T10:11:41","name":"include: Declare getopt function on old GNU libc","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8ab93d7a617ad480dd786210f46db0e5aa07d1ac.1665655719.git.research_trasio@irq.a4lg.com/mbox/"},{"id":2352,"url":"https://patchwork.plctlab.org/api/1.2/patches/2352/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221013201332.2747246-1-maskray@google.com/","msgid":"<20221013201332.2747246-1-maskray@google.com>","list_archive_url":null,"date":"2022-10-13T20:13:32","name":"ld: Add --undefined-version","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221013201332.2747246-1-maskray@google.com/mbox/"},{"id":2532,"url":"https://patchwork.plctlab.org/api/1.2/patches/2532/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014063520.1428330-2-zengxiao@eswincomputing.com/","msgid":"<20221014063520.1428330-2-zengxiao@eswincomputing.com>","list_archive_url":null,"date":"2022-10-14T06:35:20","name":"[1/1] RISC-V: Make R_RISCV_SUB6 conforms to riscv abi standard","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014063520.1428330-2-zengxiao@eswincomputing.com/mbox/"},{"id":2560,"url":"https://patchwork.plctlab.org/api/1.2/patches/2560/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/027ae69a-636b-6757-297a-eec42936401e@linaro.org/","msgid":"<027ae69a-636b-6757-297a-eec42936401e@linaro.org>","list_archive_url":null,"date":"2022-10-14T07:58:22","name":"[v3] aarch64-pe support for LD, GAS and BFD","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/027ae69a-636b-6757-297a-eec42936401e@linaro.org/mbox/"},{"id":2602,"url":"https://patchwork.plctlab.org/api/1.2/patches/2602/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-2-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-2-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:39","name":"[01/10] Support Intel AVX-IFMA","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-2-haochen.jiang@intel.com/mbox/"},{"id":2608,"url":"https://patchwork.plctlab.org/api/1.2/patches/2608/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-3-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-3-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:40","name":"[02/10] Support Intel AVX-VNNI-INT8","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-3-haochen.jiang@intel.com/mbox/"},{"id":2611,"url":"https://patchwork.plctlab.org/api/1.2/patches/2611/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-4-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-4-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:41","name":"[03/10] Support Intel AVX-NE-CONVERT","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-4-haochen.jiang@intel.com/mbox/"},{"id":2610,"url":"https://patchwork.plctlab.org/api/1.2/patches/2610/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-5-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-5-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:42","name":"[04/10] Support Intel CMPccXADD","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-5-haochen.jiang@intel.com/mbox/"},{"id":2601,"url":"https://patchwork.plctlab.org/api/1.2/patches/2601/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-6-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-6-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:43","name":"[05/10] Add handler for more i386_cpu_flags","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-6-haochen.jiang@intel.com/mbox/"},{"id":2606,"url":"https://patchwork.plctlab.org/api/1.2/patches/2606/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-7-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-7-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:44","name":"[06/10] Support Intel RAO-INT","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-7-haochen.jiang@intel.com/mbox/"},{"id":2609,"url":"https://patchwork.plctlab.org/api/1.2/patches/2609/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-8-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-8-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:45","name":"[07/10] Support Intel WRMSRNS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-8-haochen.jiang@intel.com/mbox/"},{"id":2605,"url":"https://patchwork.plctlab.org/api/1.2/patches/2605/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-9-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-9-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:46","name":"[08/10] Support Intel MSRLIST","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-9-haochen.jiang@intel.com/mbox/"},{"id":2607,"url":"https://patchwork.plctlab.org/api/1.2/patches/2607/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-10-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-10-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:47","name":"[09/10] Support Intel AMX-FP16","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-10-haochen.jiang@intel.com/mbox/"},{"id":2604,"url":"https://patchwork.plctlab.org/api/1.2/patches/2604/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-11-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-11-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:48","name":"[10/10] Support Intel PREFETCHI","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-11-haochen.jiang@intel.com/mbox/"},{"id":2643,"url":"https://patchwork.plctlab.org/api/1.2/patches/2643/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7bac66be-535e-9051-d674-f2f5ba180e17@suse.com/","msgid":"<7bac66be-535e-9051-d674-f2f5ba180e17@suse.com>","list_archive_url":null,"date":"2022-10-14T10:22:34","name":"x86: fold AVX512-VNNI disassembler entries with AVX-VNNI ones","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7bac66be-535e-9051-d674-f2f5ba180e17@suse.com/mbox/"},{"id":2654,"url":"https://patchwork.plctlab.org/api/1.2/patches/2654/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0lIo5+ncY/MqBEq@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-14T11:31:47","name":"PR29677, Field `the_bfd` of `asymbol` is uninitialised","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0lIo5+ncY/MqBEq@squeak.grove.modra.org/mbox/"},{"id":2656,"url":"https://patchwork.plctlab.org/api/1.2/patches/2656/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0lJksn49ZpABY89@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-14T11:35:46","name":"e200 LSP support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0lJksn49ZpABY89@squeak.grove.modra.org/mbox/"},{"id":2657,"url":"https://patchwork.plctlab.org/api/1.2/patches/2657/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0lJxxYoeD5iDYAD@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-14T11:36:39","name":"PowerPC SPE disassembly and tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0lJxxYoeD5iDYAD@squeak.grove.modra.org/mbox/"},{"id":2695,"url":"https://patchwork.plctlab.org/api/1.2/patches/2695/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/DM6PR12MB4219611F6CC2A0702884A602E7249@DM6PR12MB4219.namprd12.prod.outlook.com/","msgid":"","list_archive_url":null,"date":"2022-10-14T13:29:40","name":"Binutils: Adding new testcase for addr2line.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/DM6PR12MB4219611F6CC2A0702884A602E7249@DM6PR12MB4219.namprd12.prod.outlook.com/mbox/"},{"id":2700,"url":"https://patchwork.plctlab.org/api/1.2/patches/2700/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9fd2c88d-98b2-99a4-419f-c7235b2cf960@suse.com/","msgid":"<9fd2c88d-98b2-99a4-419f-c7235b2cf960@suse.com>","list_archive_url":null,"date":"2022-10-14T14:11:35","name":"x86: properly decode EVEX.W for AVX512_4{FMAPS,VNNIW} insns","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9fd2c88d-98b2-99a4-419f-c7235b2cf960@suse.com/mbox/"},{"id":2981,"url":"https://patchwork.plctlab.org/api/1.2/patches/2981/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0uLzalqjm4C87GN@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-16T04:42:53","name":"PowerPC se_rfmci and VLE, SPE2 and LSP insns with -many","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0uLzalqjm4C87GN@squeak.grove.modra.org/mbox/"},{"id":3152,"url":"https://patchwork.plctlab.org/api/1.2/patches/3152/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221016232419.1135-1-mark@harmstone.com/","msgid":"<20221016232419.1135-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-16T23:24:18","name":"[v5,1/2] ld: Add --pdb option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221016232419.1135-1-mark@harmstone.com/mbox/"},{"id":3151,"url":"https://patchwork.plctlab.org/api/1.2/patches/3151/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221016232419.1135-2-mark@harmstone.com/","msgid":"<20221016232419.1135-2-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-16T23:24:19","name":"[v5,2/2] ld: Add minimal pdb generation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221016232419.1135-2-mark@harmstone.com/mbox/"},{"id":3258,"url":"https://patchwork.plctlab.org/api/1.2/patches/3258/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/19c08747-fa5b-1e67-3dd2-c891a2c0c1fa@suse.com/","msgid":"<19c08747-fa5b-1e67-3dd2-c891a2c0c1fa@suse.com>","list_archive_url":null,"date":"2022-10-17T07:44:51","name":"x86: correct CPU_AMX_{BF16,INT8}_FLAGS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/19c08747-fa5b-1e67-3dd2-c891a2c0c1fa@suse.com/mbox/"},{"id":3272,"url":"https://patchwork.plctlab.org/api/1.2/patches/3272/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/85dd526c-d3a7-72dc-5444-ed5573eebec1@suse.com/","msgid":"<85dd526c-d3a7-72dc-5444-ed5573eebec1@suse.com>","list_archive_url":null,"date":"2022-10-17T08:30:12","name":"x86: generalize gas documentation for disabling of ISA extensions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/85dd526c-d3a7-72dc-5444-ed5573eebec1@suse.com/mbox/"},{"id":3759,"url":"https://patchwork.plctlab.org/api/1.2/patches/3759/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-2-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-2-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:15:58","name":"[V2,01/15] sframe.h: Add SFrame format definition","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-2-indu.bhagat@oracle.com/mbox/"},{"id":3762,"url":"https://patchwork.plctlab.org/api/1.2/patches/3762/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-3-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-3-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:15:59","name":"[V2,02/15] gas: add new command line option --gsframe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-3-indu.bhagat@oracle.com/mbox/"},{"id":3761,"url":"https://patchwork.plctlab.org/api/1.2/patches/3761/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-4-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-4-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:00","name":"[V2,03/15] gas: generate .sframe from CFI directives","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-4-indu.bhagat@oracle.com/mbox/"},{"id":3760,"url":"https://patchwork.plctlab.org/api/1.2/patches/3760/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-5-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-5-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:01","name":"[V2,04/15] gas: testsuite: add new tests for SFrame unwind info","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-5-indu.bhagat@oracle.com/mbox/"},{"id":3764,"url":"https://patchwork.plctlab.org/api/1.2/patches/3764/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-6-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-6-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:02","name":"[V2,05/15] libsframe: add the SFrame library","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-6-indu.bhagat@oracle.com/mbox/"},{"id":3766,"url":"https://patchwork.plctlab.org/api/1.2/patches/3766/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-7-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-7-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:03","name":"[V2,06/15] bfd: linker: merge .sframe sections","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-7-indu.bhagat@oracle.com/mbox/"},{"id":3763,"url":"https://patchwork.plctlab.org/api/1.2/patches/3763/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-8-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-8-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:04","name":"[V2,07/15] readelf/objdump: support for SFrame section","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-8-indu.bhagat@oracle.com/mbox/"},{"id":3765,"url":"https://patchwork.plctlab.org/api/1.2/patches/3765/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-9-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-9-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:05","name":"[V2,08/15] unwinder: generate backtrace using SFrame format","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-9-indu.bhagat@oracle.com/mbox/"},{"id":3770,"url":"https://patchwork.plctlab.org/api/1.2/patches/3770/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-10-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-10-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:06","name":"[V2,09/15] unwinder: Add SFrame unwinder tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-10-indu.bhagat@oracle.com/mbox/"},{"id":3769,"url":"https://patchwork.plctlab.org/api/1.2/patches/3769/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-11-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-11-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:07","name":"[V2,10/15] gdb: sim: buildsystem changes to accommodate libsframe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-11-indu.bhagat@oracle.com/mbox/"},{"id":3771,"url":"https://patchwork.plctlab.org/api/1.2/patches/3771/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-12-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-12-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:08","name":"[V2,11/15] libctf: add libsframe to LDFLAGS and LIBS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-12-indu.bhagat@oracle.com/mbox/"},{"id":3768,"url":"https://patchwork.plctlab.org/api/1.2/patches/3768/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-13-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-13-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:09","name":"[V2,12/15] src-release.sh: Add libsframe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-13-indu.bhagat@oracle.com/mbox/"},{"id":3767,"url":"https://patchwork.plctlab.org/api/1.2/patches/3767/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-14-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-14-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:10","name":"[V2,13/15] binutils/NEWS: add text for SFrame support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-14-indu.bhagat@oracle.com/mbox/"},{"id":3772,"url":"https://patchwork.plctlab.org/api/1.2/patches/3772/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-15-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-15-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:11","name":"[V2,14/15] gas/NEWS: add text about new command line option and SFrame support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-15-indu.bhagat@oracle.com/mbox/"},{"id":3773,"url":"https://patchwork.plctlab.org/api/1.2/patches/3773/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-16-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-16-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:12","name":"[V2,15/15] doc: add SFrame spec file","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-16-indu.bhagat@oracle.com/mbox/"},{"id":3999,"url":"https://patchwork.plctlab.org/api/1.2/patches/3999/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221018081205.17880-1-krebbel@linux.ibm.com/","msgid":"<20221018081205.17880-1-krebbel@linux.ibm.com>","list_archive_url":null,"date":"2022-10-18T08:12:05","name":"[1/1] IBM zSystems: Issue error for *DBL relocs on misaligned symbols","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221018081205.17880-1-krebbel@linux.ibm.com/mbox/"},{"id":4141,"url":"https://patchwork.plctlab.org/api/1.2/patches/4141/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/baffaf673f17692b7bcbd604b31800b189988596.camel@espressif.com/","msgid":"","list_archive_url":null,"date":"2022-10-18T12:12:07","name":"xtensa: use definitions from xtensa-config.h","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/baffaf673f17692b7bcbd604b31800b189988596.camel@espressif.com/mbox/"},{"id":4272,"url":"https://patchwork.plctlab.org/api/1.2/patches/4272/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221018174914.470062-1-hjl.tools@gmail.com/","msgid":"<20221018174914.470062-1-hjl.tools@gmail.com>","list_archive_url":null,"date":"2022-10-18T17:49:14","name":"x86: Disable AVX-VNNI when disabling AVX2","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221018174914.470062-1-hjl.tools@gmail.com/mbox/"},{"id":4998,"url":"https://patchwork.plctlab.org/api/1.2/patches/4998/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c2f76e95-09f6-1d92-7ef4-38a3c2955fcd@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-19T09:52:46","name":"x86: re-work AVX-VNNI support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c2f76e95-09f6-1d92-7ef4-38a3c2955fcd@suse.com/mbox/"},{"id":5276,"url":"https://patchwork.plctlab.org/api/1.2/patches/5276/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0/lLtlKqqsmAx0s@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-19T11:53:18","name":"Fix addr2line test for ppc64 elfv1 and mingw","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0/lLtlKqqsmAx0s@squeak.grove.modra.org/mbox/"},{"id":5424,"url":"https://patchwork.plctlab.org/api/1.2/patches/5424/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/07bfebbf3843b47e13d82d4fa16eb14fec942ef7.1666184962.git.research_trasio@irq.a4lg.com/","msgid":"<07bfebbf3843b47e13d82d4fa16eb14fec942ef7.1666184962.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:09:54","name":"binutils: Remove unused substitution PROGRAM","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/07bfebbf3843b47e13d82d4fa16eb14fec942ef7.1666184962.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5433,"url":"https://patchwork.plctlab.org/api/1.2/patches/5433/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2fa7ff719223232402e82a9c91331aea22ace1bb.1666185116.git.research_trasio@irq.a4lg.com/","msgid":"<2fa7ff719223232402e82a9c91331aea22ace1bb.1666185116.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:11:55","name":"[v2,1/8] RISC-V: Add a space at the end of pinfo","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2fa7ff719223232402e82a9c91331aea22ace1bb.1666185116.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5435,"url":"https://patchwork.plctlab.org/api/1.2/patches/5435/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1b30cce5db2cce3b8edca42ab5da114d0b8c9e93.1666185116.git.research_trasio@irq.a4lg.com/","msgid":"<1b30cce5db2cce3b8edca42ab5da114d0b8c9e93.1666185116.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:11:56","name":"[v2,2/8] RISC-V: Fix obvious misalignments ('\''Zbb'\''/'\''Zba'\'')","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1b30cce5db2cce3b8edca42ab5da114d0b8c9e93.1666185116.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5437,"url":"https://patchwork.plctlab.org/api/1.2/patches/5437/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6b0857aa1a2d15ca1cf00b4dcaae0032efbb88ff.1666185116.git.research_trasio@irq.a4lg.com/","msgid":"<6b0857aa1a2d15ca1cf00b4dcaae0032efbb88ff.1666185116.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:11:57","name":"[v2,3/8] RISC-V: Remove spaces in opcode entries","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6b0857aa1a2d15ca1cf00b4dcaae0032efbb88ff.1666185116.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5436,"url":"https://patchwork.plctlab.org/api/1.2/patches/5436/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/889d956caac0f2e95543a14afaeed97188ce384c.1666185116.git.research_trasio@irq.a4lg.com/","msgid":"<889d956caac0f2e95543a14afaeed97188ce384c.1666185116.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:11:58","name":"[v2,4/8] RISC-V: Remove unused instruction macros","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/889d956caac0f2e95543a14afaeed97188ce384c.1666185116.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5440,"url":"https://patchwork.plctlab.org/api/1.2/patches/5440/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8f226ee20d8a5ef6ad7b6c4408b44794a99d542a.1666185116.git.research_trasio@irq.a4lg.com/","msgid":"<8f226ee20d8a5ef6ad7b6c4408b44794a99d542a.1666185116.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:11:59","name":"[v2,5/8] RISC-V: Complete tidying up with SCALL and SBREAK","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8f226ee20d8a5ef6ad7b6c4408b44794a99d542a.1666185116.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5442,"url":"https://patchwork.plctlab.org/api/1.2/patches/5442/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4070184c454a05a39adf0790951e5856e6b2ecb6.1666185116.git.research_trasio@irq.a4lg.com/","msgid":"<4070184c454a05a39adf0790951e5856e6b2ecb6.1666185116.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:12:00","name":"[v2,6/8] RISC-V: Tidying up with fmv.w.x and fmv.x.w","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4070184c454a05a39adf0790951e5856e6b2ecb6.1666185116.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5438,"url":"https://patchwork.plctlab.org/api/1.2/patches/5438/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c1ccda3e7c8fb297eda46dab3936d5c5977178fc.1666185116.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-19T13:12:01","name":"[v2,7/8] RISC-V: Make alias instructions aliases","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c1ccda3e7c8fb297eda46dab3936d5c5977178fc.1666185116.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5441,"url":"https://patchwork.plctlab.org/api/1.2/patches/5441/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/413cfca82c7e8d8a2e977dfda9135903c9cb7c57.1666185116.git.research_trasio@irq.a4lg.com/","msgid":"<413cfca82c7e8d8a2e977dfda9135903c9cb7c57.1666185116.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:12:02","name":"[v2,8/8] RISC-V: Use defined mask and match values","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/413cfca82c7e8d8a2e977dfda9135903c9cb7c57.1666185116.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5439,"url":"https://patchwork.plctlab.org/api/1.2/patches/5439/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/345c5c3b3a53eab04a1e6e91197de2642095c94f.1666185237.git.research_trasio@irq.a4lg.com/","msgid":"<345c5c3b3a53eab04a1e6e91197de2642095c94f.1666185237.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:14:01","name":"RISC-V: Remove RV32EF conflict","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/345c5c3b3a53eab04a1e6e91197de2642095c94f.1666185237.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5616,"url":"https://patchwork.plctlab.org/api/1.2/patches/5616/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019145608.45213-5-haochen.jiang@intel.com/","msgid":"<20221019145608.45213-5-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T14:56:02","name":"[04/10] Support Intel CMPccXADD","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019145608.45213-5-haochen.jiang@intel.com/mbox/"},{"id":5614,"url":"https://patchwork.plctlab.org/api/1.2/patches/5614/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019145608.45213-6-haochen.jiang@intel.com/","msgid":"<20221019145608.45213-6-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T14:56:03","name":"[05/10] Add handler for more i386_cpu_flags","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019145608.45213-6-haochen.jiang@intel.com/mbox/"},{"id":5672,"url":"https://patchwork.plctlab.org/api/1.2/patches/5672/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-2-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-2-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:25","name":"[01/10] Support Intel AVX-IFMA","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-2-haochen.jiang@intel.com/mbox/"},{"id":5691,"url":"https://patchwork.plctlab.org/api/1.2/patches/5691/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-3-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-3-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:26","name":"[02/10] Support Intel AVX-VNNI-INT8","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-3-haochen.jiang@intel.com/mbox/"},{"id":5690,"url":"https://patchwork.plctlab.org/api/1.2/patches/5690/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-4-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-4-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:27","name":"[03/10] Support Intel AVX-NE-CONVERT","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-4-haochen.jiang@intel.com/mbox/"},{"id":5689,"url":"https://patchwork.plctlab.org/api/1.2/patches/5689/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-5-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-5-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:28","name":"[04/10] Support Intel CMPccXADD","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-5-haochen.jiang@intel.com/mbox/"},{"id":5676,"url":"https://patchwork.plctlab.org/api/1.2/patches/5676/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-6-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-6-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:29","name":"[05/10] Add handler for more i386_cpu_flags","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-6-haochen.jiang@intel.com/mbox/"},{"id":5677,"url":"https://patchwork.plctlab.org/api/1.2/patches/5677/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-7-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-7-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:30","name":"[06/10] Support Intel RAO-INT","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-7-haochen.jiang@intel.com/mbox/"},{"id":5681,"url":"https://patchwork.plctlab.org/api/1.2/patches/5681/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-8-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-8-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:31","name":"[07/10] Support Intel WRMSRNS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-8-haochen.jiang@intel.com/mbox/"},{"id":5682,"url":"https://patchwork.plctlab.org/api/1.2/patches/5682/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-9-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-9-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:32","name":"[08/10] Support Intel MSRLIST","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-9-haochen.jiang@intel.com/mbox/"},{"id":5673,"url":"https://patchwork.plctlab.org/api/1.2/patches/5673/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-10-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-10-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:33","name":"[09/10] Support Intel AMX-FP16","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-10-haochen.jiang@intel.com/mbox/"},{"id":5686,"url":"https://patchwork.plctlab.org/api/1.2/patches/5686/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-11-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-11-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:34","name":"[10/10] Support Intel PREFETCHI","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-11-haochen.jiang@intel.com/mbox/"},{"id":5940,"url":"https://patchwork.plctlab.org/api/1.2/patches/5940/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1CMrFUC8d9lC/NL@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-19T23:47:56","name":"Obsolete beos","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1CMrFUC8d9lC/NL@squeak.grove.modra.org/mbox/"},{"id":6080,"url":"https://patchwork.plctlab.org/api/1.2/patches/6080/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8b99d666e78ba5b9d32c7889a2161c70b3da88df.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<8b99d666e78ba5b9d32c7889a2161c70b3da88df.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:25:47","name":"[01/40] gdb/unittests: PR28413, suppress warnings generated by Gnulib","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8b99d666e78ba5b9d32c7889a2161c70b3da88df.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6081,"url":"https://patchwork.plctlab.org/api/1.2/patches/6081/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b05adb17e401d621dbdad791281bc7af7806906e.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-20T09:25:48","name":"[02/40] sim: Check known getrusage declaration existence","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b05adb17e401d621dbdad791281bc7af7806906e.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6083,"url":"https://patchwork.plctlab.org/api/1.2/patches/6083/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/796962a87e569feeafb5ef636de3c79000ae152c.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<796962a87e569feeafb5ef636de3c79000ae152c.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:25:49","name":"[03/40] sim/aarch64: Remove unused functions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/796962a87e569feeafb5ef636de3c79000ae152c.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6084,"url":"https://patchwork.plctlab.org/api/1.2/patches/6084/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/65223c79fdfd7faf132275415cd9da9852c5bec3.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<65223c79fdfd7faf132275415cd9da9852c5bec3.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:25:50","name":"[04/40] cpu/cris: Initialize some variables on CRIS CPU","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/65223c79fdfd7faf132275415cd9da9852c5bec3.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6082,"url":"https://patchwork.plctlab.org/api/1.2/patches/6082/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/24baefe92148f4b7968115ba13de9b0c863a65f6.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<24baefe92148f4b7968115ba13de9b0c863a65f6.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:25:51","name":"[05/40] cpu/cris: Add u-stall virtual unit to CRIS v32","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/24baefe92148f4b7968115ba13de9b0c863a65f6.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6087,"url":"https://patchwork.plctlab.org/api/1.2/patches/6087/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3904a5c3e80f8548150d8088a92059dd728c7ff8.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<3904a5c3e80f8548150d8088a92059dd728c7ff8.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:25:52","name":"[06/40] sim/cris: Move declarations of f_specific_init","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3904a5c3e80f8548150d8088a92059dd728c7ff8.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6091,"url":"https://patchwork.plctlab.org/api/1.2/patches/6091/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/69ef2d7dd519ed572511890a215a0f6d74e53384.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<69ef2d7dd519ed572511890a215a0f6d74e53384.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:25:53","name":"[07/40] sim/cris: Regenerate with CGEN","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/69ef2d7dd519ed572511890a215a0f6d74e53384.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6085,"url":"https://patchwork.plctlab.org/api/1.2/patches/6085/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/26a3eaf4f5d2e0db6977738ddfd65d82b36e38b2.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<26a3eaf4f5d2e0db6977738ddfd65d82b36e38b2.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:25:54","name":"[08/40] sim/erc32: Insert void parameter","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/26a3eaf4f5d2e0db6977738ddfd65d82b36e38b2.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6086,"url":"https://patchwork.plctlab.org/api/1.2/patches/6086/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/057c2f8392410494c3bc5dc98052246508e6a73e.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<057c2f8392410494c3bc5dc98052246508e6a73e.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:25:55","name":"[09/40] sim/erc32: Use int32_t as event callback argument","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/057c2f8392410494c3bc5dc98052246508e6a73e.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6090,"url":"https://patchwork.plctlab.org/api/1.2/patches/6090/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8c05aec20557191434485be347d37177a2ec5ff2.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<8c05aec20557191434485be347d37177a2ec5ff2.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:25:56","name":"[10/40] sim/erc32: Use int32_t as IRQ callback argument","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8c05aec20557191434485be347d37177a2ec5ff2.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6089,"url":"https://patchwork.plctlab.org/api/1.2/patches/6089/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/afd7757aae21743c29f2aa4135a23b31d4959e9b.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-20T09:25:57","name":"[11/40] cpu/frv: Initialize some variables","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/afd7757aae21743c29f2aa4135a23b31d4959e9b.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6088,"url":"https://patchwork.plctlab.org/api/1.2/patches/6088/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/021dbd238af5dfe74523ed229d2156a155a6bb9e.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<021dbd238af5dfe74523ed229d2156a155a6bb9e.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:25:58","name":"[12/40] sim/frv: Initialize nesr variable","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/021dbd238af5dfe74523ed229d2156a155a6bb9e.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6093,"url":"https://patchwork.plctlab.org/api/1.2/patches/6093/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/51a03f7097921cc48954210cf99e370ae8982ec8.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<51a03f7097921cc48954210cf99e370ae8982ec8.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:25:59","name":"[13/40] sim/frv: Initialize some variables","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/51a03f7097921cc48954210cf99e370ae8982ec8.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6092,"url":"https://patchwork.plctlab.org/api/1.2/patches/6092/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e1baa1be3601612266dc6ae0bdde8426ff2a42c8.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-20T09:26:00","name":"[14/40] sim/frv: Add explicit casts","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e1baa1be3601612266dc6ae0bdde8426ff2a42c8.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6095,"url":"https://patchwork.plctlab.org/api/1.2/patches/6095/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5ab303a5bdfc1da7832f8fa22f57678c9ef1a5fa.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"<5ab303a5bdfc1da7832f8fa22f57678c9ef1a5fa.1666257885.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-20T09:26:01","name":"[15/40] sim/h8300: Add \"+ 0x0\" to avoid self-assignments","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5ab303a5bdfc1da7832f8fa22f57678c9ef1a5fa.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6101,"url":"https://patchwork.plctlab.org/api/1.2/patches/6101/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ddff80db3328a2286fe6fbc1240d2abc1e3813eb.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-20T09:26:02","name":"[16/40] sim/lm32: fix some missing function declaration warnings","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ddff80db3328a2286fe6fbc1240d2abc1e3813eb.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6094,"url":"https://patchwork.plctlab.org/api/1.2/patches/6094/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e094b1379231d9ffb59a78cfebbcc84634c779c6.1666257885.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-20T09:26:03","name":"[17/40] sim/lm32: Add explicit casts","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e094b1379231d9ffb59a78cfebbcc84634c779c6.1666257885.git.research_trasio@irq.a4lg.com/mbox/"},{"id":6141,"url":"https://patchwork.plctlab.org/api/1.2/patches/6141/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/cabebead-489b-528c-580e-933832417474@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-20T10:25:51","name":"[1/3] x86: emit {evex} prefix when disassembling ambiguous AVX512VL insns","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/cabebead-489b-528c-580e-933832417474@suse.com/mbox/"},{"id":6143,"url":"https://patchwork.plctlab.org/api/1.2/patches/6143/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a032d61c-63a0-23d1-331f-619a2b8bbde3@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-20T10:26:15","name":"[2/3] x86: consolidate VAES tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a032d61c-63a0-23d1-331f-619a2b8bbde3@suse.com/mbox/"},{"id":6142,"url":"https://patchwork.plctlab.org/api/1.2/patches/6142/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7ff09c86-2de7-dc34-3183-5187de3df5ac@suse.com/","msgid":"<7ff09c86-2de7-dc34-3183-5187de3df5ac@suse.com>","list_archive_url":null,"date":"2022-10-20T10:26:40","name":"[3/3] x86: consolidate VPCLMUL tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7ff09c86-2de7-dc34-3183-5187de3df5ac@suse.com/mbox/"},{"id":6228,"url":"https://patchwork.plctlab.org/api/1.2/patches/6228/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.LSU.2.20.2210201432170.29399@wotan.suse.de/","msgid":"","list_archive_url":null,"date":"2022-10-20T14:42:25","name":"x86-64: Use only one default max-page-size","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.LSU.2.20.2210201432170.29399@wotan.suse.de/mbox/"},{"id":6229,"url":"https://patchwork.plctlab.org/api/1.2/patches/6229/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221020144351.1398099-1-chigot@adacore.com/","msgid":"<20221020144351.1398099-1-chigot@adacore.com>","list_archive_url":null,"date":"2022-10-20T14:43:50","name":"[1/2] ld/testsuite: skip ld-elf/exclude when -shared is not supported","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221020144351.1398099-1-chigot@adacore.com/mbox/"},{"id":6230,"url":"https://patchwork.plctlab.org/api/1.2/patches/6230/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221020144351.1398099-2-chigot@adacore.com/","msgid":"<20221020144351.1398099-2-chigot@adacore.com>","list_archive_url":null,"date":"2022-10-20T14:43:51","name":"[2/2] ld/testsuite: adjust ld-arm to run shared tests only when supported","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221020144351.1398099-2-chigot@adacore.com/mbox/"},{"id":6236,"url":"https://patchwork.plctlab.org/api/1.2/patches/6236/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221020151027.GA1300@delia.home/","msgid":"<20221020151027.GA1300@delia.home>","list_archive_url":null,"date":"2022-10-20T15:10:28","name":"[RFC,top-level] Add configure test-case","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221020151027.GA1300@delia.home/mbox/"},{"id":6286,"url":"https://patchwork.plctlab.org/api/1.2/patches/6286/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221020162911.1113338-1-hjl.tools@gmail.com/","msgid":"<20221020162911.1113338-1-hjl.tools@gmail.com>","list_archive_url":null,"date":"2022-10-20T16:29:11","name":"x86: Check VEX/EVEX encoding before checking vector operands","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221020162911.1113338-1-hjl.tools@gmail.com/mbox/"},{"id":7884,"url":"https://patchwork.plctlab.org/api/1.2/patches/7884/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7e53b7980f2b3b74d2250bc87f5db94b1d888a2d.camel@espressif.com/","msgid":"<7e53b7980f2b3b74d2250bc87f5db94b1d888a2d.camel@espressif.com>","list_archive_url":null,"date":"2022-10-22T12:53:54","name":"[1/5] bfd: xtensa: move common code from ld and gas","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7e53b7980f2b3b74d2250bc87f5db94b1d888a2d.camel@espressif.com/mbox/"},{"id":7885,"url":"https://patchwork.plctlab.org/api/1.2/patches/7885/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/63f2699e6ef3e6d1ca415a6ed1187d4f64297521.camel@espressif.com/","msgid":"<63f2699e6ef3e6d1ca415a6ed1187d4f64297521.camel@espressif.com>","list_archive_url":null,"date":"2022-10-22T12:55:16","name":"[2/5] gas: xtensa: add endianness, loops, booleans options","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/63f2699e6ef3e6d1ca415a6ed1187d4f64297521.camel@espressif.com/mbox/"},{"id":7886,"url":"https://patchwork.plctlab.org/api/1.2/patches/7886/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/34d2f747237aeeda595560cfded8096d9bd1c28c.camel@espressif.com/","msgid":"<34d2f747237aeeda595560cfded8096d9bd1c28c.camel@espressif.com>","list_archive_url":null,"date":"2022-10-22T12:56:02","name":"[3/5] ld: xtensa: use default LD command line options for endianness","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/34d2f747237aeeda595560cfded8096d9bd1c28c.camel@espressif.com/mbox/"},{"id":7891,"url":"https://patchwork.plctlab.org/api/1.2/patches/7891/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/535b6208c1718b9acf3258575e1ebc0a65af9f07.camel@espressif.com/","msgid":"<535b6208c1718b9acf3258575e1ebc0a65af9f07.camel@espressif.com>","list_archive_url":null,"date":"2022-10-22T13:56:44","name":"[5/5] gdb: xtensa: add support for esp32, esp32s2, esp32s3 isa-modules","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/535b6208c1718b9acf3258575e1ebc0a65af9f07.camel@espressif.com/mbox/"},{"id":10456,"url":"https://patchwork.plctlab.org/api/1.2/patches/10456/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221025013347.68282-1-nelson@rivosinc.com/","msgid":"<20221025013347.68282-1-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-10-25T01:33:46","name":"[committed,1/2] RISC-V: Improve link time complexity.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221025013347.68282-1-nelson@rivosinc.com/mbox/"},{"id":10454,"url":"https://patchwork.plctlab.org/api/1.2/patches/10454/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221025013347.68282-2-nelson@rivosinc.com/","msgid":"<20221025013347.68282-2-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-10-25T01:33:47","name":"[committed,2/2] RISC-V: Should reset `again'\'' flag for _bfd_riscv_relax_pc.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221025013347.68282-2-nelson@rivosinc.com/mbox/"},{"id":10536,"url":"https://patchwork.plctlab.org/api/1.2/patches/10536/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/bb7b87e4-1893-5c86-4a14-92bafc818b03@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-25T07:24:56","name":"[v5,1/8] x86: constify parse_insn()'\''s input","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/bb7b87e4-1893-5c86-4a14-92bafc818b03@suse.com/mbox/"},{"id":10537,"url":"https://patchwork.plctlab.org/api/1.2/patches/10537/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b9273ae6-0218-54f8-5374-b265ed13b71a@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-25T07:25:26","name":"[v5,1/8] x86: introduce Pass2 insn attribute","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b9273ae6-0218-54f8-5374-b265ed13b71a@suse.com/mbox/"},{"id":10541,"url":"https://patchwork.plctlab.org/api/1.2/patches/10541/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7250dab9-e218-e6dd-4c74-23da9f611ab4@suse.com/","msgid":"<7250dab9-e218-e6dd-4c74-23da9f611ab4@suse.com>","list_archive_url":null,"date":"2022-10-25T07:26:11","name":"[v5,3/8] x86: re-work insn/suffix recognition","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7250dab9-e218-e6dd-4c74-23da9f611ab4@suse.com/mbox/"},{"id":10540,"url":"https://patchwork.plctlab.org/api/1.2/patches/10540/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/13fc630f-e116-0099-5c9e-2697df6519d7@suse.com/","msgid":"<13fc630f-e116-0099-5c9e-2697df6519d7@suse.com>","list_archive_url":null,"date":"2022-10-25T07:26:40","name":"[v5,4/8] ix86: don'\''t recognize/derive Q suffix in the common case","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/13fc630f-e116-0099-5c9e-2697df6519d7@suse.com/mbox/"},{"id":10543,"url":"https://patchwork.plctlab.org/api/1.2/patches/10543/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/74db429d-d203-eab8-4ae1-18b9ad416b02@suse.com/","msgid":"<74db429d-d203-eab8-4ae1-18b9ad416b02@suse.com>","list_archive_url":null,"date":"2022-10-25T07:27:11","name":"[v5,5/8] x86-64: allow HLE store of accumulator to absolute 32-bit address","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/74db429d-d203-eab8-4ae1-18b9ad416b02@suse.com/mbox/"},{"id":10542,"url":"https://patchwork.plctlab.org/api/1.2/patches/10542/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2e2f7841-de4e-b5de-e8d9-a47a6a4113c8@suse.com/","msgid":"<2e2f7841-de4e-b5de-e8d9-a47a6a4113c8@suse.com>","list_archive_url":null,"date":"2022-10-25T07:27:35","name":"[v5,6/8] x86: move bad-use-of-TLS-reloc check","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2e2f7841-de4e-b5de-e8d9-a47a6a4113c8@suse.com/mbox/"},{"id":10545,"url":"https://patchwork.plctlab.org/api/1.2/patches/10545/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/421bc96e-7591-6980-48e9-5af8c8b0775a@suse.com/","msgid":"<421bc96e-7591-6980-48e9-5af8c8b0775a@suse.com>","list_archive_url":null,"date":"2022-10-25T07:28:27","name":"[v5,7/8] x86: drop (now) stray IsString","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/421bc96e-7591-6980-48e9-5af8c8b0775a@suse.com/mbox/"},{"id":10546,"url":"https://patchwork.plctlab.org/api/1.2/patches/10546/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/06ff83d4-4633-a07b-70e5-a8e049981dd4@suse.com/","msgid":"<06ff83d4-4633-a07b-70e5-a8e049981dd4@suse.com>","list_archive_url":null,"date":"2022-10-25T07:29:18","name":"[v5,8/8] x86: further re-work insn/suffix recognition to also cover MOVSX","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/06ff83d4-4633-a07b-70e5-a8e049981dd4@suse.com/mbox/"},{"id":10777,"url":"https://patchwork.plctlab.org/api/1.2/patches/10777/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6a8e7a71acccd0efb9789dfb3edfa307e83bdaa1.1666702934.git.research_trasio@irq.a4lg.com/","msgid":"<6a8e7a71acccd0efb9789dfb3edfa307e83bdaa1.1666702934.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-25T13:04:02","name":"[RFC] RISC-V: Allocate \"various\" operand type","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6a8e7a71acccd0efb9789dfb3edfa307e83bdaa1.1666702934.git.research_trasio@irq.a4lg.com/mbox/"},{"id":11062,"url":"https://patchwork.plctlab.org/api/1.2/patches/11062/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jAhwbXhxJHL66v@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-26T05:07:19","name":"PR29720, objdump -S crashes if build-id is missing","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jAhwbXhxJHL66v@squeak.grove.modra.org/mbox/"},{"id":11063,"url":"https://patchwork.plctlab.org/api/1.2/patches/11063/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jAxD+NxpMIah6s@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-26T05:08:20","name":"som.c buffer overflow","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jAxD+NxpMIah6s@squeak.grove.modra.org/mbox/"},{"id":11064,"url":"https://patchwork.plctlab.org/api/1.2/patches/11064/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jBYw4lfRQfOZhi@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-26T05:10:59","name":"som.c reloc sanity checking","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jBYw4lfRQfOZhi@squeak.grove.modra.org/mbox/"},{"id":11080,"url":"https://patchwork.plctlab.org/api/1.2/patches/11080/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jY7hygm01PelCY@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-26T06:51:26","name":"segfault in objdump.c reloc_at","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jY7hygm01PelCY@squeak.grove.modra.org/mbox/"},{"id":11081,"url":"https://patchwork.plctlab.org/api/1.2/patches/11081/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jZWIeIvCCYm9/g@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-26T06:53:12","name":"Correct ELF reloc size sanity check","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jZWIeIvCCYm9/g@squeak.grove.modra.org/mbox/"},{"id":11082,"url":"https://patchwork.plctlab.org/api/1.2/patches/11082/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221026070009.3663574-1-ysato@users.sourceforge.jp/","msgid":"<20221026070009.3663574-1-ysato@users.sourceforge.jp>","list_archive_url":null,"date":"2022-10-26T07:00:09","name":"opcodes: RX fix invalid output.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221026070009.3663574-1-ysato@users.sourceforge.jp/mbox/"},{"id":11089,"url":"https://patchwork.plctlab.org/api/1.2/patches/11089/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jhW48kuVC8Ig2d@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-26T07:27:23","name":"buffer overflow in _bfd_XX_print_ce_compressed_pdata","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1jhW48kuVC8Ig2d@squeak.grove.modra.org/mbox/"},{"id":11157,"url":"https://patchwork.plctlab.org/api/1.2/patches/11157/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c52dbd16-7e1b-c356-7a92-1ff089564ef7@suse.cz/","msgid":"","list_archive_url":null,"date":"2022-10-26T08:47:09","name":"tests: use canonical option name","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c52dbd16-7e1b-c356-7a92-1ff089564ef7@suse.cz/mbox/"},{"id":11526,"url":"https://patchwork.plctlab.org/api/1.2/patches/11526/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027031915.4013-1-lifang_xia@linux.alibaba.com/","msgid":"<20221027031915.4013-1-lifang_xia@linux.alibaba.com>","list_archive_url":null,"date":"2022-10-27T03:19:15","name":"[v2] RISC-V: Optimize relax of GP/call with max_alignment.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027031915.4013-1-lifang_xia@linux.alibaba.com/mbox/"},{"id":11619,"url":"https://patchwork.plctlab.org/api/1.2/patches/11619/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9df9d9e5bb4c7594b76c40613a349b4d2364e9c5.1666854355.git.research_trasio@irq.a4lg.com/","msgid":"<9df9d9e5bb4c7594b76c40613a349b4d2364e9c5.1666854355.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-27T07:06:01","name":"include: Define macro to ignore -Wdeprecated-declarations on GCC","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9df9d9e5bb4c7594b76c40613a349b4d2364e9c5.1666854355.git.research_trasio@irq.a4lg.com/mbox/"},{"id":11627,"url":"https://patchwork.plctlab.org/api/1.2/patches/11627/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1o06O9Pp8ncCsOw@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-27T07:36:08","name":"Fuzzed files in archives","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1o06O9Pp8ncCsOw@squeak.grove.modra.org/mbox/"},{"id":11658,"url":"https://patchwork.plctlab.org/api/1.2/patches/11658/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027084808.37252-1-nelson@rivosinc.com/","msgid":"<20221027084808.37252-1-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-10-27T08:48:08","name":"[committed] RISC-V: Fix build failures for -Werror=sign-compare.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027084808.37252-1-nelson@rivosinc.com/mbox/"},{"id":11921,"url":"https://patchwork.plctlab.org/api/1.2/patches/11921/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027190052.10536-1-mark@harmstone.com/","msgid":"<20221027190052.10536-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-27T19:00:51","name":"[1/2] ld: Add section header stream to PDB files","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027190052.10536-1-mark@harmstone.com/mbox/"},{"id":11922,"url":"https://patchwork.plctlab.org/api/1.2/patches/11922/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027190052.10536-2-mark@harmstone.com/","msgid":"<20221027190052.10536-2-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-27T19:00:52","name":"[2/2] ld: Add publics stream to PDB files","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027190052.10536-2-mark@harmstone.com/mbox/"},{"id":11965,"url":"https://patchwork.plctlab.org/api/1.2/patches/11965/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027202719.32497-1-palmer@rivosinc.com/","msgid":"<20221027202719.32497-1-palmer@rivosinc.com>","list_archive_url":null,"date":"2022-10-27T20:27:18","name":"[1/2] gas: NEWS: Add a missing newline","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027202719.32497-1-palmer@rivosinc.com/mbox/"},{"id":11966,"url":"https://patchwork.plctlab.org/api/1.2/patches/11966/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027202719.32497-2-palmer@rivosinc.com/","msgid":"<20221027202719.32497-2-palmer@rivosinc.com>","list_archive_url":null,"date":"2022-10-27T20:27:19","name":"[2/2] gas: NEWS: Note support for RISC-V Zawrs","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221027202719.32497-2-palmer@rivosinc.com/mbox/"},{"id":12016,"url":"https://patchwork.plctlab.org/api/1.2/patches/12016/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/21ec9a18-fa89-0828-f625-499680022ec7@linux.ibm.com/","msgid":"<21ec9a18-fa89-0828-f625-499680022ec7@linux.ibm.com>","list_archive_url":null,"date":"2022-10-28T00:35:19","name":"[COMMITTED] PowerPC: Add support for RFC02653 - Dense Math Facility","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/21ec9a18-fa89-0828-f625-499680022ec7@linux.ibm.com/mbox/"},{"id":12017,"url":"https://patchwork.plctlab.org/api/1.2/patches/12017/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fd94047d-a070-45a6-3840-c105391718e0@linux.ibm.com/","msgid":"","list_archive_url":null,"date":"2022-10-28T00:37:18","name":"[COMMITTED] PowerPC: Add support for RFC02658 - MMA+ Outer-Product, Instructions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fd94047d-a070-45a6-3840-c105391718e0@linux.ibm.com/mbox/"},{"id":12122,"url":"https://patchwork.plctlab.org/api/1.2/patches/12122/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ac4f3f3c7115a824f73aca6935789b14d33c9a58.1666939920.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-28T06:53:02","name":"RISC-V: Fix build failure for -Werror=maybe-uninitialized","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ac4f3f3c7115a824f73aca6935789b14d33c9a58.1666939920.git.research_trasio@irq.a4lg.com/mbox/"},{"id":12181,"url":"https://patchwork.plctlab.org/api/1.2/patches/12181/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221028093840.19164-1-nelson@rivosinc.com/","msgid":"<20221028093840.19164-1-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-10-28T09:38:40","name":"RISC-V: Added SiFive custom cache control extensions.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221028093840.19164-1-nelson@rivosinc.com/mbox/"},{"id":12211,"url":"https://patchwork.plctlab.org/api/1.2/patches/12211/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4a280588-a85b-6ed3-634b-2b9cbc128f86@suse.com/","msgid":"<4a280588-a85b-6ed3-634b-2b9cbc128f86@suse.com>","list_archive_url":null,"date":"2022-10-28T10:06:35","name":"RISC-V/gas: fix build with certain gcc versions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4a280588-a85b-6ed3-634b-2b9cbc128f86@suse.com/mbox/"},{"id":12249,"url":"https://patchwork.plctlab.org/api/1.2/patches/12249/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/eb0e1bff-675e-72db-b8b1-b0f0e50b7121@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-28T12:35:35","name":"x86: minor improvements to optimize_imm() (part III)","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/eb0e1bff-675e-72db-b8b1-b0f0e50b7121@suse.com/mbox/"},{"id":12382,"url":"https://patchwork.plctlab.org/api/1.2/patches/12382/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/17f57574936af82be381a1451eac56b3709b60bb.1666968673.git.research_trasio@irq.a4lg.com/","msgid":"<17f57574936af82be381a1451eac56b3709b60bb.1666968673.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-28T14:52:12","name":"RISC-V: Emit mapping symbol with ISA string if non-default arch is used","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/17f57574936af82be381a1451eac56b3709b60bb.1666968673.git.research_trasio@irq.a4lg.com/mbox/"},{"id":12627,"url":"https://patchwork.plctlab.org/api/1.2/patches/12627/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221029034432.49859-1-nelson@rivosinc.com/","msgid":"<20221029034432.49859-1-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-10-29T03:44:32","name":"[committed] RISC-V: Always generate mapping symbols at the start of the sections.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221029034432.49859-1-nelson@rivosinc.com/mbox/"},{"id":12629,"url":"https://patchwork.plctlab.org/api/1.2/patches/12629/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1yxgzNJg5M48uPI@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-29T04:52:19","name":"NULL dereference read in som_write_object_contents","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1yxgzNJg5M48uPI@squeak.grove.modra.org/mbox/"},{"id":12630,"url":"https://patchwork.plctlab.org/api/1.2/patches/12630/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1yxnSHLY+FeB5DQ@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-29T04:52:45","name":"Fix small objcopy memory leak","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1yxnSHLY+FeB5DQ@squeak.grove.modra.org/mbox/"},{"id":12631,"url":"https://patchwork.plctlab.org/api/1.2/patches/12631/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1yxxfpJz+Jx4KTh@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-29T04:53:25","name":"pef: sanity check before malloc","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y1yxxfpJz+Jx4KTh@squeak.grove.modra.org/mbox/"},{"id":12950,"url":"https://patchwork.plctlab.org/api/1.2/patches/12950/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-2-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-2-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:36","name":"[V3,01/15] sframe.h: Add SFrame format definition","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-2-indu.bhagat@oracle.com/mbox/"},{"id":12952,"url":"https://patchwork.plctlab.org/api/1.2/patches/12952/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-3-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-3-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:37","name":"[V3,02/15] gas: add new command line option --gsframe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-3-indu.bhagat@oracle.com/mbox/"},{"id":12951,"url":"https://patchwork.plctlab.org/api/1.2/patches/12951/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-4-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-4-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:38","name":"[V3,03/15] gas: generate .sframe from CFI directives","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-4-indu.bhagat@oracle.com/mbox/"},{"id":12956,"url":"https://patchwork.plctlab.org/api/1.2/patches/12956/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-5-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-5-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:39","name":"[V3,04/15] gas: testsuite: add new tests for SFrame unwind info","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-5-indu.bhagat@oracle.com/mbox/"},{"id":12955,"url":"https://patchwork.plctlab.org/api/1.2/patches/12955/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-6-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-6-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:40","name":"[V3,05/15] libsframe: add the SFrame library","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-6-indu.bhagat@oracle.com/mbox/"},{"id":12959,"url":"https://patchwork.plctlab.org/api/1.2/patches/12959/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-7-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-7-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:41","name":"[V3,06/15] bfd: linker: merge .sframe sections","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-7-indu.bhagat@oracle.com/mbox/"},{"id":12961,"url":"https://patchwork.plctlab.org/api/1.2/patches/12961/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-8-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-8-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:42","name":"[V3,07/15] readelf/objdump: support for SFrame section","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-8-indu.bhagat@oracle.com/mbox/"},{"id":12962,"url":"https://patchwork.plctlab.org/api/1.2/patches/12962/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-9-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-9-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:43","name":"[V3,08/15] unwinder: generate backtrace using SFrame format","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-9-indu.bhagat@oracle.com/mbox/"},{"id":12963,"url":"https://patchwork.plctlab.org/api/1.2/patches/12963/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-10-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-10-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:44","name":"[V3,09/15] unwinder: Add SFrame unwinder tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-10-indu.bhagat@oracle.com/mbox/"},{"id":12964,"url":"https://patchwork.plctlab.org/api/1.2/patches/12964/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-11-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-11-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:45","name":"[V3,10/15] gdb: sim: buildsystem changes to accommodate libsframe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-11-indu.bhagat@oracle.com/mbox/"},{"id":12957,"url":"https://patchwork.plctlab.org/api/1.2/patches/12957/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-12-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-12-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:46","name":"[V3,11/15] libctf: add libsframe to LDFLAGS and LIBS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-12-indu.bhagat@oracle.com/mbox/"},{"id":12960,"url":"https://patchwork.plctlab.org/api/1.2/patches/12960/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-13-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-13-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:47","name":"[V3,12/15] src-release.sh: Add libsframe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-13-indu.bhagat@oracle.com/mbox/"},{"id":12953,"url":"https://patchwork.plctlab.org/api/1.2/patches/12953/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-14-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-14-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:48","name":"[V3,13/15] binutils/NEWS: add text for SFrame support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-14-indu.bhagat@oracle.com/mbox/"},{"id":12954,"url":"https://patchwork.plctlab.org/api/1.2/patches/12954/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-15-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-15-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:49","name":"[V3,14/15] gas/NEWS: add text about new command line option and SFrame support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-15-indu.bhagat@oracle.com/mbox/"},{"id":12958,"url":"https://patchwork.plctlab.org/api/1.2/patches/12958/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-16-indu.bhagat@oracle.com/","msgid":"<20221030074450.1956074-16-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-30T07:44:50","name":"[V3,15/15] doc: add SFrame spec file","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221030074450.1956074-16-indu.bhagat@oracle.com/mbox/"},{"id":12988,"url":"https://patchwork.plctlab.org/api/1.2/patches/12988/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y15KFY32CyFhh/+u@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-30T09:55:33","name":"Pool section entries for DWP version 1","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y15KFY32CyFhh/+u@squeak.grove.modra.org/mbox/"},{"id":13076,"url":"https://patchwork.plctlab.org/api/1.2/patches/13076/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031001554.14615-1-mark@harmstone.com/","msgid":"<20221031001554.14615-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-31T00:15:52","name":"[v2,1/3] ld: Use %E in einfo in pdb.c","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031001554.14615-1-mark@harmstone.com/mbox/"},{"id":13078,"url":"https://patchwork.plctlab.org/api/1.2/patches/13078/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031001554.14615-2-mark@harmstone.com/","msgid":"<20221031001554.14615-2-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-31T00:15:53","name":"[v2,2/3] ld: Add section header stream to PDB files","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031001554.14615-2-mark@harmstone.com/mbox/"},{"id":13077,"url":"https://patchwork.plctlab.org/api/1.2/patches/13077/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031001554.14615-3-mark@harmstone.com/","msgid":"<20221031001554.14615-3-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-31T00:15:54","name":"[v2,3/3] ld: Add publics stream to PDB files","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031001554.14615-3-mark@harmstone.com/mbox/"},{"id":13106,"url":"https://patchwork.plctlab.org/api/1.2/patches/13106/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031030507.35588-2-haochen.jiang@intel.com/","msgid":"<20221031030507.35588-2-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-31T03:05:02","name":"[1/6] Support Intel AVX-IFMA","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031030507.35588-2-haochen.jiang@intel.com/mbox/"},{"id":13105,"url":"https://patchwork.plctlab.org/api/1.2/patches/13105/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031030507.35588-3-haochen.jiang@intel.com/","msgid":"<20221031030507.35588-3-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-31T03:05:03","name":"[2/6] Support Intel AVX-VNNI-INT8","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031030507.35588-3-haochen.jiang@intel.com/mbox/"},{"id":13103,"url":"https://patchwork.plctlab.org/api/1.2/patches/13103/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031030507.35588-4-haochen.jiang@intel.com/","msgid":"<20221031030507.35588-4-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-31T03:05:04","name":"[3/6] Support Intel CMPccXADD","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031030507.35588-4-haochen.jiang@intel.com/mbox/"},{"id":13101,"url":"https://patchwork.plctlab.org/api/1.2/patches/13101/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031030507.35588-5-haochen.jiang@intel.com/","msgid":"<20221031030507.35588-5-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-31T03:05:05","name":"[4/6] Add handler for more i386_cpu_flags","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031030507.35588-5-haochen.jiang@intel.com/mbox/"},{"id":13104,"url":"https://patchwork.plctlab.org/api/1.2/patches/13104/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031030507.35588-6-haochen.jiang@intel.com/","msgid":"<20221031030507.35588-6-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-31T03:05:06","name":"[5/6] Support Intel WRMSRNS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031030507.35588-6-haochen.jiang@intel.com/mbox/"},{"id":13102,"url":"https://patchwork.plctlab.org/api/1.2/patches/13102/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031030507.35588-7-haochen.jiang@intel.com/","msgid":"<20221031030507.35588-7-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-31T03:05:07","name":"[6/6] Support Intel MSRLIST","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031030507.35588-7-haochen.jiang@intel.com/mbox/"},{"id":13120,"url":"https://patchwork.plctlab.org/api/1.2/patches/13120/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031060601.38460-2-haochen.jiang@intel.com/","msgid":"<20221031060601.38460-2-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-31T06:06:00","name":"[1/2] i386: Add and ","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031060601.38460-2-haochen.jiang@intel.com/mbox/"},{"id":13121,"url":"https://patchwork.plctlab.org/api/1.2/patches/13121/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031060601.38460-3-haochen.jiang@intel.com/","msgid":"<20221031060601.38460-3-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-31T06:06:01","name":"[2/2] Support Intel AVX-NE-CONVERT","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031060601.38460-3-haochen.jiang@intel.com/mbox/"},{"id":13188,"url":"https://patchwork.plctlab.org/api/1.2/patches/13188/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9f6f8888-4dc1-a6b0-0590-35fc8a276369@suse.com/","msgid":"<9f6f8888-4dc1-a6b0-0590-35fc8a276369@suse.com>","list_archive_url":null,"date":"2022-10-31T10:18:20","name":"x86: drop bogus Tbyte","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9f6f8888-4dc1-a6b0-0590-35fc8a276369@suse.com/mbox/"},{"id":13213,"url":"https://patchwork.plctlab.org/api/1.2/patches/13213/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4f1aac95-fea5-2279-cb18-dfcdb51a2589@arm.com/","msgid":"<4f1aac95-fea5-2279-cb18-dfcdb51a2589@arm.com>","list_archive_url":null,"date":"2022-10-31T11:14:44","name":"aarch64: Add support for Common Short Sequence Compression extension","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4f1aac95-fea5-2279-cb18-dfcdb51a2589@arm.com/mbox/"}],"public":true,"mbox":"https://patchwork.plctlab.org/bundle/patchwork-bot/binutils-gdb_2022-10/mbox/"},{"id":7,"url":"https://patchwork.plctlab.org/api/1.2/bundles/7/","web_url":"https://patchwork.plctlab.org/bundle/patchwork-bot/binutils-gdb_2022-09/","project":{"id":2,"url":"https://patchwork.plctlab.org/api/1.2/projects/2/","name":"binutils-gdb","link_name":"binutils-gdb","list_id":"binutils.sourceware.org","list_email":"binutils@sourceware.org","web_url":"https://github.com/wangliu-iscas/Patchwork-Bundles/blob/main/binutils-gdb.md","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"name":"binutils-gdb_2022-09","owner":{"id":3,"url":"https://patchwork.plctlab.org/api/1.2/users/3/","username":"patchwork-bot","first_name":"","last_name":"","email":"ouuuleilei@gmail.com"},"patches":[{"id":1573,"url":"https://patchwork.plctlab.org/api/1.2/patches/1573/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930073211.2634-1-jiawei@iscas.ac.cn/","msgid":"<20220930073211.2634-1-jiawei@iscas.ac.cn>","list_archive_url":null,"date":"2022-09-30T07:32:11","name":"[V2] RISC-V: Add Smepmp CSR '\''mseccfg'\'' define and testcases.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930073211.2634-1-jiawei@iscas.ac.cn/mbox/"},{"id":1577,"url":"https://patchwork.plctlab.org/api/1.2/patches/1577/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/76fa0c3c-2303-ebdf-a765-ac4731581517@suse.com/","msgid":"<76fa0c3c-2303-ebdf-a765-ac4731581517@suse.com>","list_archive_url":null,"date":"2022-09-30T08:54:18","name":"objcopy: avoid \"shadowing\" of remove() function name","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/76fa0c3c-2303-ebdf-a765-ac4731581517@suse.com/mbox/"},{"id":1579,"url":"https://patchwork.plctlab.org/api/1.2/patches/1579/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930085852.71213-1-nelson@rivosinc.com/","msgid":"<20220930085852.71213-1-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-09-30T08:58:51","name":"[1/2] RISC-V: Output mapping symbols with ISA string.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930085852.71213-1-nelson@rivosinc.com/mbox/"},{"id":1578,"url":"https://patchwork.plctlab.org/api/1.2/patches/1578/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930085852.71213-2-nelson@rivosinc.com/","msgid":"<20220930085852.71213-2-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-09-30T08:58:52","name":"[2/2] RISC-V: Refer mapping symbol to R_RISCV_RELAX for rvc relaxations.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930085852.71213-2-nelson@rivosinc.com/mbox/"},{"id":1581,"url":"https://patchwork.plctlab.org/api/1.2/patches/1581/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930092058.71286-1-nelson@rivosinc.com/","msgid":"<20220930092058.71286-1-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-09-30T09:20:57","name":"[1/2] RISC-V: Output mapping symbols with ISA string.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930092058.71286-1-nelson@rivosinc.com/mbox/"},{"id":1580,"url":"https://patchwork.plctlab.org/api/1.2/patches/1580/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930092058.71286-2-nelson@rivosinc.com/","msgid":"<20220930092058.71286-2-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-09-30T09:20:58","name":"[2/2] RISC-V: Refer mapping symbol to R_RISCV_RELAX for rvc relaxations.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930092058.71286-2-nelson@rivosinc.com/mbox/"},{"id":1582,"url":"https://patchwork.plctlab.org/api/1.2/patches/1582/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5874dd79-0cf5-d65c-7ea2-13adfc799c0f@suse.com/","msgid":"<5874dd79-0cf5-d65c-7ea2-13adfc799c0f@suse.com>","list_archive_url":null,"date":"2022-09-30T09:41:29","name":"RISC-V: fix build after \"Add support for arbitrary immediate encoding formats\"","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5874dd79-0cf5-d65c-7ea2-13adfc799c0f@suse.com/mbox/"},{"id":1583,"url":"https://patchwork.plctlab.org/api/1.2/patches/1583/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/57d8ac2a-5757-3776-9924-99c17ca69938@suse.com/","msgid":"<57d8ac2a-5757-3776-9924-99c17ca69938@suse.com>","list_archive_url":null,"date":"2022-09-30T09:42:08","name":"RISC-V: fallout from \"re-arrange opcode table for consistent alias handling\"","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/57d8ac2a-5757-3776-9924-99c17ca69938@suse.com/mbox/"},{"id":1584,"url":"https://patchwork.plctlab.org/api/1.2/patches/1584/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e76ef8f7-72b9-5103-cb43-9608af01d017@suse.com/","msgid":"","list_archive_url":null,"date":"2022-09-30T09:42:50","name":"RISC-V: don'\''t cast expressions'\'' X_add_number to long in diagnostics","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e76ef8f7-72b9-5103-cb43-9608af01d017@suse.com/mbox/"},{"id":1585,"url":"https://patchwork.plctlab.org/api/1.2/patches/1585/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/61355429-24b3-17d0-ab03-6fa57ee861d5@suse.cz/","msgid":"<61355429-24b3-17d0-ab03-6fa57ee861d5@suse.cz>","list_archive_url":null,"date":"2022-09-30T09:48:52","name":"[RFC] add --enable-zstd-compressed-debug-sections configure option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/61355429-24b3-17d0-ab03-6fa57ee861d5@suse.cz/mbox/"},{"id":1586,"url":"https://patchwork.plctlab.org/api/1.2/patches/1586/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930103919.323690-1-christoph.muellner@vrull.eu/","msgid":"<20220930103919.323690-1-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2022-09-30T10:39:19","name":"RISC-V: Eliminate long-casts of X_add_number in diagnostics","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930103919.323690-1-christoph.muellner@vrull.eu/mbox/"},{"id":1590,"url":"https://patchwork.plctlab.org/api/1.2/patches/1590/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/DM6PR12MB4219C943049C6D883DEA3E55E7569@DM6PR12MB4219.namprd12.prod.outlook.com/","msgid":"","list_archive_url":null,"date":"2022-09-30T11:41:37","name":"[V2] Ignore DWARF debug information for -gsplit-dwarf with dwarf-5.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/DM6PR12MB4219C943049C6D883DEA3E55E7569@DM6PR12MB4219.namprd12.prod.outlook.com/mbox/"},{"id":1591,"url":"https://patchwork.plctlab.org/api/1.2/patches/1591/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c10321f9-d289-ef84-d263-bc278fb3d31b@suse.com/","msgid":"","list_archive_url":null,"date":"2022-09-30T11:59:04","name":"[1/4] RISC-V/gas: drop riscv_subsets static variable","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c10321f9-d289-ef84-d263-bc278fb3d31b@suse.com/mbox/"},{"id":1593,"url":"https://patchwork.plctlab.org/api/1.2/patches/1593/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3244eea0-c18c-e49a-4588-d69423130226@suse.com/","msgid":"<3244eea0-c18c-e49a-4588-d69423130226@suse.com>","list_archive_url":null,"date":"2022-09-30T11:59:23","name":"[2/4] RISC-V/gas: drop stray call to install_insn()","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3244eea0-c18c-e49a-4588-d69423130226@suse.com/mbox/"},{"id":1592,"url":"https://patchwork.plctlab.org/api/1.2/patches/1592/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/385d01fd-7e57-1f3f-1bae-30aa0c313d63@suse.com/","msgid":"<385d01fd-7e57-1f3f-1bae-30aa0c313d63@suse.com>","list_archive_url":null,"date":"2022-09-30T11:59:45","name":"[3/4] RISC-V/gas: don'\''t open-code insn_length()","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/385d01fd-7e57-1f3f-1bae-30aa0c313d63@suse.com/mbox/"},{"id":1594,"url":"https://patchwork.plctlab.org/api/1.2/patches/1594/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f5757acf-7b90-a0e3-5eea-3b97cc226930@suse.com/","msgid":"","list_archive_url":null,"date":"2022-09-30T12:00:12","name":"[4/4] RISC-V/gas: allow generating up to 176-bit instructions with .insn","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f5757acf-7b90-a0e3-5eea-3b97cc226930@suse.com/mbox/"},{"id":1596,"url":"https://patchwork.plctlab.org/api/1.2/patches/1596/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930140503.38233-1-chigot@adacore.com/","msgid":"<20220930140503.38233-1-chigot@adacore.com>","list_archive_url":null,"date":"2022-09-30T14:05:03","name":"ld/testsuite: consistently add board_ldflags when linking with GCC","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930140503.38233-1-chigot@adacore.com/mbox/"}],"public":true,"mbox":"https://patchwork.plctlab.org/bundle/patchwork-bot/binutils-gdb_2022-09/mbox/"},{"id":9,"url":"https://patchwork.plctlab.org/api/1.2/bundles/9/","web_url":"https://patchwork.plctlab.org/bundle/patchwork-bot/binutils-gdb_2022-11/","project":{"id":2,"url":"https://patchwork.plctlab.org/api/1.2/projects/2/","name":"binutils-gdb","link_name":"binutils-gdb","list_id":"binutils.sourceware.org","list_email":"binutils@sourceware.org","web_url":"https://github.com/wangliu-iscas/Patchwork-Bundles/blob/main/binutils-gdb.md","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"name":"binutils-gdb_2022-11","owner":{"id":3,"url":"https://patchwork.plctlab.org/api/1.2/users/3/","username":"patchwork-bot","first_name":"","last_name":"","email":"ouuuleilei@gmail.com"},"patches":[{"id":13337,"url":"https://patchwork.plctlab.org/api/1.2/patches/13337/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031160625.684434-1-hjl.tools@gmail.com/","msgid":"<20221031160625.684434-1-hjl.tools@gmail.com>","list_archive_url":null,"date":"2022-10-31T16:06:25","name":"x86: Silence GCC 12 warning on tc-i386.c","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221031160625.684434-1-hjl.tools@gmail.com/mbox/"},{"id":13350,"url":"https://patchwork.plctlab.org/api/1.2/patches/13350/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c8d25b29-37fe-9623-a799-e67e1f991743@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-31T17:00:56","name":"x86: simplify expressions in update_imm()","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c8d25b29-37fe-9623-a799-e67e1f991743@suse.com/mbox/"},{"id":13487,"url":"https://patchwork.plctlab.org/api/1.2/patches/13487/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/CAMe9rOohVjin92PTeeiu_dvAtzYJn4dGtu5E=OxYfbyteraZWw@mail.gmail.com/","msgid":"","list_archive_url":null,"date":"2022-11-01T00:08:04","name":"binutils: Run PR binutils/26160 test","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/CAMe9rOohVjin92PTeeiu_dvAtzYJn4dGtu5E=OxYfbyteraZWw@mail.gmail.com/mbox/"},{"id":13621,"url":"https://patchwork.plctlab.org/api/1.2/patches/13621/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221101105724.1527333-1-aburgess@redhat.com/","msgid":"<20221101105724.1527333-1-aburgess@redhat.com>","list_archive_url":null,"date":"2022-11-01T10:57:24","name":"[PUSHED] opcodes/arm: silence compiler warning about uninitialized variable use","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221101105724.1527333-1-aburgess@redhat.com/mbox/"},{"id":13628,"url":"https://patchwork.plctlab.org/api/1.2/patches/13628/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221101111802.1532080-1-aburgess@redhat.com/","msgid":"<20221101111802.1532080-1-aburgess@redhat.com>","list_archive_url":null,"date":"2022-11-01T11:18:02","name":"[PUSHED] opcodes/arm: don'\''t pass non-string literal to printf like function","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221101111802.1532080-1-aburgess@redhat.com/mbox/"},{"id":13747,"url":"https://patchwork.plctlab.org/api/1.2/patches/13747/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/yw8jbkpqk6vw.fsf@arm.com/","msgid":"","list_archive_url":null,"date":"2022-11-01T15:54:11","name":"[Binutils-2.39,backport,GAS] arm: Use DWARF numbering convention for pseudo-register representation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/yw8jbkpqk6vw.fsf@arm.com/mbox/"},{"id":13993,"url":"https://patchwork.plctlab.org/api/1.2/patches/13993/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221102020752.24441-1-mark@harmstone.com/","msgid":"<20221102020752.24441-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-11-02T02:07:52","name":"ld: Add module information substream to PDB files","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221102020752.24441-1-mark@harmstone.com/mbox/"},{"id":14028,"url":"https://patchwork.plctlab.org/api/1.2/patches/14028/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221102050430.1053-1-nelson@rivosinc.com/","msgid":"<20221102050430.1053-1-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-11-02T05:04:30","name":"[committed] RISC-V: Fixed the missing $x+arch when adding odd paddings for alignment.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221102050430.1053-1-nelson@rivosinc.com/mbox/"},{"id":14043,"url":"https://patchwork.plctlab.org/api/1.2/patches/14043/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221102063046.31551-1-rjiejie@linux.alibaba.com/","msgid":"<20221102063046.31551-1-rjiejie@linux.alibaba.com>","list_archive_url":null,"date":"2022-11-02T06:30:46","name":"gas/doc/internals.texi: fix typo","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221102063046.31551-1-rjiejie@linux.alibaba.com/mbox/"},{"id":14069,"url":"https://patchwork.plctlab.org/api/1.2/patches/14069/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221102080112.33378-1-rjiejie@linux.alibaba.com/","msgid":"<20221102080112.33378-1-rjiejie@linux.alibaba.com>","list_archive_url":null,"date":"2022-11-02T08:01:12","name":"[v2] Support multiple .eh_frame sections","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221102080112.33378-1-rjiejie@linux.alibaba.com/mbox/"},{"id":14409,"url":"https://patchwork.plctlab.org/api/1.2/patches/14409/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221102172923.4009281-1-christophe.lyon@arm.com/","msgid":"<20221102172923.4009281-1-christophe.lyon@arm.com>","list_archive_url":null,"date":"2022-11-02T17:29:23","name":"arm: PR 29739 Fix typo where '\''; '\'' should not have been replaced with '\''@'\''","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221102172923.4009281-1-christophe.lyon@arm.com/mbox/"},{"id":14588,"url":"https://patchwork.plctlab.org/api/1.2/patches/14588/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221103020409.37322-1-rjiejie@linux.alibaba.com/","msgid":"<20221103020409.37322-1-rjiejie@linux.alibaba.com>","list_archive_url":null,"date":"2022-11-03T02:04:09","name":"[v3] Support multiple .eh_frame sections","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221103020409.37322-1-rjiejie@linux.alibaba.com/mbox/"},{"id":14602,"url":"https://patchwork.plctlab.org/api/1.2/patches/14602/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221103024604.614-1-mark@harmstone.com/","msgid":"<20221103024604.614-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-11-03T02:46:04","name":"[v2] ld: Add module information substream to PDB files","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221103024604.614-1-mark@harmstone.com/mbox/"},{"id":14706,"url":"https://patchwork.plctlab.org/api/1.2/patches/14706/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221103071519.3510462-1-luis.machado@arm.com/","msgid":"<20221103071519.3510462-1-luis.machado@arm.com>","list_archive_url":null,"date":"2022-11-03T07:15:19","name":"[opcodes/arm] Fix potential null pointer dereferences","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221103071519.3510462-1-luis.machado@arm.com/mbox/"},{"id":14840,"url":"https://patchwork.plctlab.org/api/1.2/patches/14840/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/283a86ebf0941f0f63dc1a590ec3d547bd5d69e8.1667478033.git.research_trasio@irq.a4lg.com/","msgid":"<283a86ebf0941f0f63dc1a590ec3d547bd5d69e8.1667478033.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-03T12:26:28","name":"[REVIEW,ONLY,1/2] NEAR-RATIFICATION RISC-V: Add '\''Ssstateen'\'' extension and its CSRs","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/283a86ebf0941f0f63dc1a590ec3d547bd5d69e8.1667478033.git.research_trasio@irq.a4lg.com/mbox/"},{"id":14841,"url":"https://patchwork.plctlab.org/api/1.2/patches/14841/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8083ad9d5339afdeb7f1ba88ee6af0665dcc76d5.1667478033.git.research_trasio@irq.a4lg.com/","msgid":"<8083ad9d5339afdeb7f1ba88ee6af0665dcc76d5.1667478033.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-03T12:26:29","name":"[REVIEW,ONLY,2/2] NEAR-RATIFICATION RISC-V: Add platform property/capability extensions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8083ad9d5339afdeb7f1ba88ee6af0665dcc76d5.1667478033.git.research_trasio@irq.a4lg.com/mbox/"},{"id":14894,"url":"https://patchwork.plctlab.org/api/1.2/patches/14894/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e53fbf5025e59fe6a3481b9c1fe37e4f6cf6e03d.1667483581.git.aburgess@redhat.com/","msgid":"","list_archive_url":null,"date":"2022-11-03T13:58:12","name":"[1/2] opcodes/mips: use .word/.short for undefined instructions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e53fbf5025e59fe6a3481b9c1fe37e4f6cf6e03d.1667483581.git.aburgess@redhat.com/mbox/"},{"id":14893,"url":"https://patchwork.plctlab.org/api/1.2/patches/14893/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ca81edb86580566b1641ad140eb2bed385160ab7.1667483581.git.aburgess@redhat.com/","msgid":"","list_archive_url":null,"date":"2022-11-03T13:58:13","name":"[2/2] libopcodes/mips: add support for disassembler styling","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ca81edb86580566b1641ad140eb2bed385160ab7.1667483581.git.aburgess@redhat.com/mbox/"},{"id":15465,"url":"https://patchwork.plctlab.org/api/1.2/patches/15465/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/926e5154-b40b-9df8-d770-a8bf7d40e40e@suse.com/","msgid":"<926e5154-b40b-9df8-d770-a8bf7d40e40e@suse.com>","list_archive_url":null,"date":"2022-11-04T10:50:38","name":"[v6,1/7] x86: constify parse_insn()'\''s input","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/926e5154-b40b-9df8-d770-a8bf7d40e40e@suse.com/mbox/"},{"id":15466,"url":"https://patchwork.plctlab.org/api/1.2/patches/15466/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/07ef67fd-752c-ad1f-b8cb-4eaec1f420fc@suse.com/","msgid":"<07ef67fd-752c-ad1f-b8cb-4eaec1f420fc@suse.com>","list_archive_url":null,"date":"2022-11-04T10:51:34","name":"[v6,2/7] x86: re-work insn/suffix recognition","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/07ef67fd-752c-ad1f-b8cb-4eaec1f420fc@suse.com/mbox/"},{"id":15467,"url":"https://patchwork.plctlab.org/api/1.2/patches/15467/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ee8fd655-19a5-d944-0f5e-4351b88a59f9@suse.com/","msgid":"","list_archive_url":null,"date":"2022-11-04T10:52:02","name":"[v6,3/7] ix86: don'\''t recognize/derive Q suffix in the common case","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ee8fd655-19a5-d944-0f5e-4351b88a59f9@suse.com/mbox/"},{"id":15468,"url":"https://patchwork.plctlab.org/api/1.2/patches/15468/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/15ab2cf5-f1ac-e882-c415-6318f1bcc7f0@suse.com/","msgid":"<15ab2cf5-f1ac-e882-c415-6318f1bcc7f0@suse.com>","list_archive_url":null,"date":"2022-11-04T10:52:31","name":"[v6,4/7] x86-64: allow HLE store of accumulator to absolute 32-bit address","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/15ab2cf5-f1ac-e882-c415-6318f1bcc7f0@suse.com/mbox/"},{"id":15470,"url":"https://patchwork.plctlab.org/api/1.2/patches/15470/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/352d1e49-ac9f-ee86-7e9d-74f79744268b@suse.com/","msgid":"<352d1e49-ac9f-ee86-7e9d-74f79744268b@suse.com>","list_archive_url":null,"date":"2022-11-04T10:53:14","name":"[v6,5/7] x86: move bad-use-of-TLS-reloc check","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/352d1e49-ac9f-ee86-7e9d-74f79744268b@suse.com/mbox/"},{"id":15469,"url":"https://patchwork.plctlab.org/api/1.2/patches/15469/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c1913bf6-7328-e45f-69f1-20da1954af43@suse.com/","msgid":"","list_archive_url":null,"date":"2022-11-04T10:53:52","name":"[v6,6/7] x86: drop (now) stray IsString","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c1913bf6-7328-e45f-69f1-20da1954af43@suse.com/mbox/"},{"id":15471,"url":"https://patchwork.plctlab.org/api/1.2/patches/15471/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2baf6a9d-c1bf-660d-bbca-99b1604f5478@suse.com/","msgid":"<2baf6a9d-c1bf-660d-bbca-99b1604f5478@suse.com>","list_archive_url":null,"date":"2022-11-04T10:54:30","name":"[v6,7/7] x86: further re-work insn/suffix recognition to also cover MOVSX","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2baf6a9d-c1bf-660d-bbca-99b1604f5478@suse.com/mbox/"},{"id":15472,"url":"https://patchwork.plctlab.org/api/1.2/patches/15472/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104110132.694984-1-aburgess@redhat.com/","msgid":"<20221104110132.694984-1-aburgess@redhat.com>","list_archive_url":null,"date":"2022-11-04T11:01:32","name":"[PUSHED] opcodes/arm: silence compiler warning about uninitialized variable use","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104110132.694984-1-aburgess@redhat.com/mbox/"},{"id":15473,"url":"https://patchwork.plctlab.org/api/1.2/patches/15473/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104110214.129095-1-christophe.lyon@arm.com/","msgid":"<20221104110214.129095-1-christophe.lyon@arm.com>","list_archive_url":null,"date":"2022-11-04T11:02:14","name":"configure: require libzstd >= 1.4.0","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104110214.129095-1-christophe.lyon@arm.com/mbox/"},{"id":15485,"url":"https://patchwork.plctlab.org/api/1.2/patches/15485/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104115038.8957-1-nelson@rivosinc.com/","msgid":"<20221104115038.8957-1-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-11-04T11:50:37","name":"[1/2] RISC-V: File-level architecture shouldn'\''t be affected by section-level ones.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104115038.8957-1-nelson@rivosinc.com/mbox/"},{"id":15486,"url":"https://patchwork.plctlab.org/api/1.2/patches/15486/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104115038.8957-2-nelson@rivosinc.com/","msgid":"<20221104115038.8957-2-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-11-04T11:50:38","name":"[2/2] RISC-V: Clarify the suppress rule of mapping symbol with architecture string.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104115038.8957-2-nelson@rivosinc.com/mbox/"},{"id":15509,"url":"https://patchwork.plctlab.org/api/1.2/patches/15509/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/cc133c88-9ce9-5e3a-a8f7-ad72766862b9@suse.com/","msgid":"","list_archive_url":null,"date":"2022-11-04T13:12:07","name":"x86: adjust recently introduced testcases","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/cc133c88-9ce9-5e3a-a8f7-ad72766862b9@suse.com/mbox/"},{"id":15679,"url":"https://patchwork.plctlab.org/api/1.2/patches/15679/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104163328.2274371-1-chigot@adacore.com/","msgid":"<20221104163328.2274371-1-chigot@adacore.com>","list_archive_url":null,"date":"2022-11-04T16:33:28","name":"ld/testsuite: skip tests related to -shared when disabled","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104163328.2274371-1-chigot@adacore.com/mbox/"},{"id":15751,"url":"https://patchwork.plctlab.org/api/1.2/patches/15751/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104190216.1352855-1-indu.bhagat@oracle.com/","msgid":"<20221104190216.1352855-1-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-04T19:02:16","name":"[V3.1,11/15] libctf: add libsframe to LDFLAGS and LIBS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104190216.1352855-1-indu.bhagat@oracle.com/mbox/"},{"id":15792,"url":"https://patchwork.plctlab.org/api/1.2/patches/15792/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104205547.3728827-1-hjl.tools@gmail.com/","msgid":"<20221104205547.3728827-1-hjl.tools@gmail.com>","list_archive_url":null,"date":"2022-11-04T20:55:47","name":"i386: Check invalid (%dx) usage","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104205547.3728827-1-hjl.tools@gmail.com/mbox/"},{"id":15794,"url":"https://patchwork.plctlab.org/api/1.2/patches/15794/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104210134.1721620-1-indu.bhagat@oracle.com/","msgid":"<20221104210134.1721620-1-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-04T21:01:34","name":"[V3.2,11/15] libctf: add libsframe to LDFLAGS and LIBS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221104210134.1721620-1-indu.bhagat@oracle.com/mbox/"},{"id":15959,"url":"https://patchwork.plctlab.org/api/1.2/patches/15959/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c620070e3e335df2b487d3836e20d251dac37525.1667651354.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-11-05T12:29:07","name":"[01/12] RISC-V: Remove unnecessary empty matching file","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c620070e3e335df2b487d3836e20d251dac37525.1667651354.git.research_trasio@irq.a4lg.com/mbox/"},{"id":15961,"url":"https://patchwork.plctlab.org/api/1.2/patches/15961/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4496235002a396043598ab9755bd8eda5c077b1f.1667651354.git.research_trasio@irq.a4lg.com/","msgid":"<4496235002a396043598ab9755bd8eda5c077b1f.1667651354.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-05T12:29:08","name":"[02/12] RISC-V: Tidy disassembler corner case tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4496235002a396043598ab9755bd8eda5c077b1f.1667651354.git.research_trasio@irq.a4lg.com/mbox/"},{"id":15960,"url":"https://patchwork.plctlab.org/api/1.2/patches/15960/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a9229a2798480f00bf12ac3c435b3ef57f867022.1667651354.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-11-05T12:29:09","name":"[03/12] RISC-V: Tidying related to '\''Zfinx'\'' disassembler test","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a9229a2798480f00bf12ac3c435b3ef57f867022.1667651354.git.research_trasio@irq.a4lg.com/mbox/"},{"id":15962,"url":"https://patchwork.plctlab.org/api/1.2/patches/15962/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6a020edd0e114a003edbaafe1088a040e9fa07e7.1667651354.git.research_trasio@irq.a4lg.com/","msgid":"<6a020edd0e114a003edbaafe1088a040e9fa07e7.1667651354.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-05T12:29:10","name":"[04/12] RISC-V: GAS: Add basic shared test utilities","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6a020edd0e114a003edbaafe1088a040e9fa07e7.1667651354.git.research_trasio@irq.a4lg.com/mbox/"},{"id":15966,"url":"https://patchwork.plctlab.org/api/1.2/patches/15966/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6fc2851a4161edc429089bd2bbd9c2bb4c0c118f.1667651354.git.research_trasio@irq.a4lg.com/","msgid":"<6fc2851a4161edc429089bd2bbd9c2bb4c0c118f.1667651354.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-05T12:29:11","name":"[05/12] RISC-V: Redefine \"nop\" test","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6fc2851a4161edc429089bd2bbd9c2bb4c0c118f.1667651354.git.research_trasio@irq.a4lg.com/mbox/"},{"id":15963,"url":"https://patchwork.plctlab.org/api/1.2/patches/15963/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7311ed3d2429000e18877d7af594890da170a7a3.1667651354.git.research_trasio@irq.a4lg.com/","msgid":"<7311ed3d2429000e18877d7af594890da170a7a3.1667651354.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-05T12:29:12","name":"[06/12] RISC-V: Reorganize/enhance {sign, zero}-extension instructions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7311ed3d2429000e18877d7af594890da170a7a3.1667651354.git.research_trasio@irq.a4lg.com/mbox/"},{"id":15968,"url":"https://patchwork.plctlab.org/api/1.2/patches/15968/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ac99c9696c156207f06c18f2d6bf423c96c5876b.1667651354.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-11-05T12:29:13","name":"[07/12] RISC-V: Combine complex extension error handling tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ac99c9696c156207f06c18f2d6bf423c96c5876b.1667651354.git.research_trasio@irq.a4lg.com/mbox/"},{"id":15970,"url":"https://patchwork.plctlab.org/api/1.2/patches/15970/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9378b9505e3e230e0a690c56e67d253e2a0f5864.1667651354.git.research_trasio@irq.a4lg.com/","msgid":"<9378b9505e3e230e0a690c56e67d253e2a0f5864.1667651354.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-05T12:29:14","name":"[08/12] RISC-V: Refine/enhance '\''M'\''/'\''Zmmul'\'' extension tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9378b9505e3e230e0a690c56e67d253e2a0f5864.1667651354.git.research_trasio@irq.a4lg.com/mbox/"},{"id":15964,"url":"https://patchwork.plctlab.org/api/1.2/patches/15964/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/82832a67f240d5857fd502d4b74fd7d841ee2d6e.1667651354.git.research_trasio@irq.a4lg.com/","msgid":"<82832a67f240d5857fd502d4b74fd7d841ee2d6e.1667651354.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-05T12:29:15","name":"[09/12] RISC-V: Combine/enhance '\''Zicbo[mz]'\'' extension tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/82832a67f240d5857fd502d4b74fd7d841ee2d6e.1667651354.git.research_trasio@irq.a4lg.com/mbox/"},{"id":15965,"url":"https://patchwork.plctlab.org/api/1.2/patches/15965/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9c47e59868a64b13e5a7bb487e3619d4f1497d78.1667651354.git.research_trasio@irq.a4lg.com/","msgid":"<9c47e59868a64b13e5a7bb487e3619d4f1497d78.1667651354.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-05T12:29:16","name":"[10/12] RISC-V: Enhance '\''Zicbop'\'' testcases","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9c47e59868a64b13e5a7bb487e3619d4f1497d78.1667651354.git.research_trasio@irq.a4lg.com/mbox/"},{"id":15967,"url":"https://patchwork.plctlab.org/api/1.2/patches/15967/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2d9befc5bc5eed80b6bd7da6d092a61b1162ecac.1667651354.git.research_trasio@irq.a4lg.com/","msgid":"<2d9befc5bc5eed80b6bd7da6d092a61b1162ecac.1667651354.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-05T12:29:17","name":"[11/12] RISC-V: Reorganize/enhance '\''Zb*'\'' extension tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2d9befc5bc5eed80b6bd7da6d092a61b1162ecac.1667651354.git.research_trasio@irq.a4lg.com/mbox/"},{"id":15969,"url":"https://patchwork.plctlab.org/api/1.2/patches/15969/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f1c5589ab606b74eeac98e3dafd4a7903450d3b2.1667651354.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-11-05T12:29:18","name":"[12/12] RISC-V: Combine/enhance '\''Zk*'\''/'\''Zbk*'\'' extension tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f1c5589ab606b74eeac98e3dafd4a7903450d3b2.1667651354.git.research_trasio@irq.a4lg.com/mbox/"},{"id":16066,"url":"https://patchwork.plctlab.org/api/1.2/patches/16066/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221106053640.1649752-1-indu.bhagat@oracle.com/","msgid":"<20221106053640.1649752-1-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-06T05:36:40","name":"[V3.1,03/15] gas: generate .sframe from CFI directives","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221106053640.1649752-1-indu.bhagat@oracle.com/mbox/"},{"id":16379,"url":"https://patchwork.plctlab.org/api/1.2/patches/16379/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221107112805.3332619-1-och95@yandex.ru/","msgid":"<20221107112805.3332619-1-och95@yandex.ru>","list_archive_url":null,"date":"2022-11-07T11:28:05","name":"gold/aarch64: Fix adrp distance check","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221107112805.3332619-1-och95@yandex.ru/mbox/"},{"id":16400,"url":"https://patchwork.plctlab.org/api/1.2/patches/16400/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221107124620.1271470-1-christoph.muellner@vrull.eu/","msgid":"<20221107124620.1271470-1-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2022-11-07T12:46:20","name":"RISC-V: xtheadfmemidx: Use fp register in mnemonics","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221107124620.1271470-1-christoph.muellner@vrull.eu/mbox/"},{"id":16594,"url":"https://patchwork.plctlab.org/api/1.2/patches/16594/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/CACVBkZ+kM2xcpwk5zHQ4bqDV7dbPjZ6cMU9tR-h62+tDTgi3Tw@mail.gmail.com/","msgid":"","list_archive_url":null,"date":"2022-11-07T17:53:35","name":"GAS fix section alignment for aarch64-pe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/CACVBkZ+kM2xcpwk5zHQ4bqDV7dbPjZ6cMU9tR-h62+tDTgi3Tw@mail.gmail.com/mbox/"},{"id":16744,"url":"https://patchwork.plctlab.org/api/1.2/patches/16744/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221107222809.924195-1-indu.bhagat@oracle.com/","msgid":"<20221107222809.924195-1-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-07T22:28:09","name":"[V3.3,11/15] libctf: add libsframe to LDFLAGS and LIBS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221107222809.924195-1-indu.bhagat@oracle.com/mbox/"},{"id":16797,"url":"https://patchwork.plctlab.org/api/1.2/patches/16797/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221108012556.66467-1-haochen.jiang@intel.com/","msgid":"<20221108012556.66467-1-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-11-08T01:25:56","name":"x86: Correct wrong comments in vex_w_table","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221108012556.66467-1-haochen.jiang@intel.com/mbox/"},{"id":16884,"url":"https://patchwork.plctlab.org/api/1.2/patches/16884/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221108054530.796968-1-markus.t.metzger@intel.com/","msgid":"<20221108054530.796968-1-markus.t.metzger@intel.com>","list_archive_url":null,"date":"2022-11-08T05:45:29","name":"[1/2] gprofng: make cpu identification available to others","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221108054530.796968-1-markus.t.metzger@intel.com/mbox/"},{"id":16885,"url":"https://patchwork.plctlab.org/api/1.2/patches/16885/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221108054530.796968-2-markus.t.metzger@intel.com/","msgid":"<20221108054530.796968-2-markus.t.metzger@intel.com>","list_archive_url":null,"date":"2022-11-08T05:45:30","name":"[2/2] gdb, btrace: use cpuident.h to implement btrace_this_cpu","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221108054530.796968-2-markus.t.metzger@intel.com/mbox/"},{"id":16995,"url":"https://patchwork.plctlab.org/api/1.2/patches/16995/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ea0daf08-4923-ebfa-dcfe-699c43d63822@suse.com/","msgid":"","list_archive_url":null,"date":"2022-11-08T11:29:40","name":"x86/Intel: don'\''t accept malformed EXTRQ / INSERTQ","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ea0daf08-4923-ebfa-dcfe-699c43d63822@suse.com/mbox/"},{"id":17057,"url":"https://patchwork.plctlab.org/api/1.2/patches/17057/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221108141352.6613-1-jwilk@jwilk.net/","msgid":"<20221108141352.6613-1-jwilk@jwilk.net>","list_archive_url":null,"date":"2022-11-08T14:13:52","name":"Fix typos in the list of objdump options","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221108141352.6613-1-jwilk@jwilk.net/mbox/"},{"id":17117,"url":"https://patchwork.plctlab.org/api/1.2/patches/17117/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1667924955-9218-1-git-send-email-apinski@marvell.com/","msgid":"<1667924955-9218-1-git-send-email-apinski@marvell.com>","list_archive_url":null,"date":"2022-11-08T16:29:15","name":"Use toplevel configure for GMP and MPFR for gdb","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1667924955-9218-1-git-send-email-apinski@marvell.com/mbox/"},{"id":17160,"url":"https://patchwork.plctlab.org/api/1.2/patches/17160/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/27382086-397f-060f-6cf6-c1d36ff6b812@linux.ibm.com/","msgid":"<27382086-397f-060f-6cf6-c1d36ff6b812@linux.ibm.com>","list_archive_url":null,"date":"2022-11-08T18:23:32","name":"[COMMITTED] PowerPC: Add XSP operand define","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/27382086-397f-060f-6cf6-c1d36ff6b812@linux.ibm.com/mbox/"},{"id":17202,"url":"https://patchwork.plctlab.org/api/1.2/patches/17202/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221108192248.1622627-1-indu.bhagat@oracle.com/","msgid":"<20221108192248.1622627-1-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-08T19:22:48","name":"libctf: use libtool for link test in configure","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221108192248.1622627-1-indu.bhagat@oracle.com/mbox/"},{"id":17262,"url":"https://patchwork.plctlab.org/api/1.2/patches/17262/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221108225030.371817-1-hjl.tools@gmail.com/","msgid":"<20221108225030.371817-1-hjl.tools@gmail.com>","list_archive_url":null,"date":"2022-11-08T22:50:30","name":"ld: Always output local symbol for relocatable link","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221108225030.371817-1-hjl.tools@gmail.com/mbox/"},{"id":17399,"url":"https://patchwork.plctlab.org/api/1.2/patches/17399/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-2-indu.bhagat@oracle.com/","msgid":"<20221109084244.261296-2-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-09T08:42:34","name":"[V4,01/11] sframe.h: Add SFrame format definition","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-2-indu.bhagat@oracle.com/mbox/"},{"id":17398,"url":"https://patchwork.plctlab.org/api/1.2/patches/17398/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-3-indu.bhagat@oracle.com/","msgid":"<20221109084244.261296-3-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-09T08:42:35","name":"[V4,02/11] gas: add new command line option --gsframe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-3-indu.bhagat@oracle.com/mbox/"},{"id":17400,"url":"https://patchwork.plctlab.org/api/1.2/patches/17400/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-4-indu.bhagat@oracle.com/","msgid":"<20221109084244.261296-4-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-09T08:42:36","name":"[V4,03/11] gas: generate .sframe from CFI directives","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-4-indu.bhagat@oracle.com/mbox/"},{"id":17403,"url":"https://patchwork.plctlab.org/api/1.2/patches/17403/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-5-indu.bhagat@oracle.com/","msgid":"<20221109084244.261296-5-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-09T08:42:37","name":"[V4,04/11] gas: testsuite: add new tests for SFrame unwind info","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-5-indu.bhagat@oracle.com/mbox/"},{"id":17407,"url":"https://patchwork.plctlab.org/api/1.2/patches/17407/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-6-indu.bhagat@oracle.com/","msgid":"<20221109084244.261296-6-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-09T08:42:38","name":"[V4,05/11] libsframe: add the SFrame library","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-6-indu.bhagat@oracle.com/mbox/"},{"id":17406,"url":"https://patchwork.plctlab.org/api/1.2/patches/17406/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-7-indu.bhagat@oracle.com/","msgid":"<20221109084244.261296-7-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-09T08:42:39","name":"[V4,06/11] bfd: linker: merge .sframe sections","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-7-indu.bhagat@oracle.com/mbox/"},{"id":17402,"url":"https://patchwork.plctlab.org/api/1.2/patches/17402/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-8-indu.bhagat@oracle.com/","msgid":"<20221109084244.261296-8-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-09T08:42:40","name":"[V4,07/11] readelf/objdump: support for SFrame section","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-8-indu.bhagat@oracle.com/mbox/"},{"id":17401,"url":"https://patchwork.plctlab.org/api/1.2/patches/17401/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-9-indu.bhagat@oracle.com/","msgid":"<20221109084244.261296-9-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-09T08:42:41","name":"[V4,08/11] src-release.sh: Add libsframe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-9-indu.bhagat@oracle.com/mbox/"},{"id":17404,"url":"https://patchwork.plctlab.org/api/1.2/patches/17404/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-10-indu.bhagat@oracle.com/","msgid":"<20221109084244.261296-10-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-09T08:42:42","name":"[V4,09/11] binutils/NEWS: add text for SFrame support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-10-indu.bhagat@oracle.com/mbox/"},{"id":17405,"url":"https://patchwork.plctlab.org/api/1.2/patches/17405/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-11-indu.bhagat@oracle.com/","msgid":"<20221109084244.261296-11-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-09T08:42:43","name":"[V4,10/11] gas/NEWS: add text about new command line option and SFrame support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-11-indu.bhagat@oracle.com/mbox/"},{"id":17418,"url":"https://patchwork.plctlab.org/api/1.2/patches/17418/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-12-indu.bhagat@oracle.com/","msgid":"<20221109084244.261296-12-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-09T08:42:44","name":"[V4,11/11] doc: add SFrame spec file","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109084244.261296-12-indu.bhagat@oracle.com/mbox/"},{"id":17662,"url":"https://patchwork.plctlab.org/api/1.2/patches/17662/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109162611.760465-1-chigot@adacore.com/","msgid":"<20221109162611.760465-1-chigot@adacore.com>","list_archive_url":null,"date":"2022-11-09T16:26:11","name":"ld/testsuite: skip ld-size when -shared is not supported","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109162611.760465-1-chigot@adacore.com/mbox/"},{"id":17804,"url":"https://patchwork.plctlab.org/api/1.2/patches/17804/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109202129.475283-1-hjl.tools@gmail.com/","msgid":"<20221109202129.475283-1-hjl.tools@gmail.com>","list_archive_url":null,"date":"2022-11-09T20:21:29","name":"[v2] i386: Check invalid (%dx) usage","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221109202129.475283-1-hjl.tools@gmail.com/mbox/"},{"id":18043,"url":"https://patchwork.plctlab.org/api/1.2/patches/18043/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y2zOaxv1jkhwTIAi@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-11-10T10:11:55","name":"Sanity check reloc count in get_reloc_upper_bound","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y2zOaxv1jkhwTIAi@squeak.grove.modra.org/mbox/"},{"id":18044,"url":"https://patchwork.plctlab.org/api/1.2/patches/18044/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y2zOkpGuKAn+V2Tk@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-11-10T10:12:34","name":"mach-o reloc size overflow","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y2zOkpGuKAn+V2Tk@squeak.grove.modra.org/mbox/"},{"id":18045,"url":"https://patchwork.plctlab.org/api/1.2/patches/18045/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fddbca08-756a-4d78-b117-3e82dc40df8d@AZ-NEU-EX04.Arm.com/","msgid":"","list_archive_url":null,"date":"2022-11-10T10:17:38","name":"[BINTUILS] arm: Add support for Cortex-X1C CPU.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fddbca08-756a-4d78-b117-3e82dc40df8d@AZ-NEU-EX04.Arm.com/mbox/"},{"id":18051,"url":"https://patchwork.plctlab.org/api/1.2/patches/18051/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1518b510-2124-cbcb-9dcb-059dcfdc6cd4@suse.com/","msgid":"<1518b510-2124-cbcb-9dcb-059dcfdc6cd4@suse.com>","list_archive_url":null,"date":"2022-11-10T10:24:31","name":"x86: drop stray IsString from PadLock insns","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1518b510-2124-cbcb-9dcb-059dcfdc6cd4@suse.com/mbox/"},{"id":18088,"url":"https://patchwork.plctlab.org/api/1.2/patches/18088/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/25e8786d-289e-0521-baa2-2f2b85124dfe@suse.com/","msgid":"<25e8786d-289e-0521-baa2-2f2b85124dfe@suse.com>","list_archive_url":null,"date":"2022-11-10T12:12:46","name":"[v2] x86: drop stray IsString from PadLock insns","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/25e8786d-289e-0521-baa2-2f2b85124dfe@suse.com/mbox/"},{"id":18130,"url":"https://patchwork.plctlab.org/api/1.2/patches/18130/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9bb8ebe7-9e49-d60b-d586-e4d98242acda@suse.com/","msgid":"<9bb8ebe7-9e49-d60b-d586-e4d98242acda@suse.com>","list_archive_url":null,"date":"2022-11-10T13:36:16","name":"x86: drop duplicate sse4a entry from cpu_arch[]","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9bb8ebe7-9e49-d60b-d586-e4d98242acda@suse.com/mbox/"},{"id":18135,"url":"https://patchwork.plctlab.org/api/1.2/patches/18135/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/21665493-a9f9-3429-c9ae-ea69bc7751e2@suse.com/","msgid":"<21665493-a9f9-3429-c9ae-ea69bc7751e2@suse.com>","list_archive_url":null,"date":"2022-11-10T13:45:30","name":"x86: fold special-operand insn attributes into a single enum","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/21665493-a9f9-3429-c9ae-ea69bc7751e2@suse.com/mbox/"},{"id":18284,"url":"https://patchwork.plctlab.org/api/1.2/patches/18284/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1668107159-16961-1-git-send-email-apinski@marvell.com/","msgid":"<1668107159-16961-1-git-send-email-apinski@marvell.com>","list_archive_url":null,"date":"2022-11-10T19:05:59","name":"[PATCHv2] Use toplevel configure for GMP and MPFR for gdb","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1668107159-16961-1-git-send-email-apinski@marvell.com/mbox/"},{"id":18337,"url":"https://patchwork.plctlab.org/api/1.2/patches/18337/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221110224002.3798725-1-vladimir.mezentsev@oracle.com/","msgid":"<20221110224002.3798725-1-vladimir.mezentsev@oracle.com>","list_archive_url":null,"date":"2022-11-10T22:40:02","name":"gprofng: fix typo in configure.ac","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221110224002.3798725-1-vladimir.mezentsev@oracle.com/mbox/"},{"id":18424,"url":"https://patchwork.plctlab.org/api/1.2/patches/18424/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221111033040.23115-1-mark@harmstone.com/","msgid":"<20221111033040.23115-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-11-11T03:30:40","name":"ld: Add section contributions substream to PDB files","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221111033040.23115-1-mark@harmstone.com/mbox/"},{"id":18513,"url":"https://patchwork.plctlab.org/api/1.2/patches/18513/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/40e89395-1438-6cbe-aa37-1a04a724c8c7@suse.com/","msgid":"<40e89395-1438-6cbe-aa37-1a04a724c8c7@suse.com>","list_archive_url":null,"date":"2022-11-11T07:32:17","name":"gas: accept custom \".linefile .\"","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/40e89395-1438-6cbe-aa37-1a04a724c8c7@suse.com/mbox/"},{"id":18517,"url":"https://patchwork.plctlab.org/api/1.2/patches/18517/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y23642YK4HTWnn3X@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-11-11T07:33:55","name":"Sanity check SHT_MIPS_OPTIONS size","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y23642YK4HTWnn3X@squeak.grove.modra.org/mbox/"},{"id":18519,"url":"https://patchwork.plctlab.org/api/1.2/patches/18519/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y237HYVYLWv1R4b/@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-11-11T07:34:53","name":"PR28834, PR26946 sanity checking section size","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y237HYVYLWv1R4b/@squeak.grove.modra.org/mbox/"},{"id":18670,"url":"https://patchwork.plctlab.org/api/1.2/patches/18670/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c5ab35f0-595a-439c-b120-f93bd109ab96@AZ-NEU-EX04.Arm.com/","msgid":"","list_archive_url":null,"date":"2022-11-11T10:51:43","name":"[Binutils,gas] arm: Add support for new unwinder directive \".pacspval\".","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c5ab35f0-595a-439c-b120-f93bd109ab96@AZ-NEU-EX04.Arm.com/mbox/"},{"id":18672,"url":"https://patchwork.plctlab.org/api/1.2/patches/18672/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/33eb9aff-d813-44c5-8315-aeb3e339b3f2@AZ-NEU-EX04.Arm.com/","msgid":"<33eb9aff-d813-44c5-8315-aeb3e339b3f2@AZ-NEU-EX04.Arm.com>","list_archive_url":null,"date":"2022-11-11T10:53:55","name":"[Binutils,readelf] arm: Support for new pacbti unwind opcode 0xb5.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/33eb9aff-d813-44c5-8315-aeb3e339b3f2@AZ-NEU-EX04.Arm.com/mbox/"},{"id":19116,"url":"https://patchwork.plctlab.org/api/1.2/patches/19116/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y29EZ/ykU1Qe6AAw@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-11-12T06:59:51","name":"PowerPC64 paddi -Mraw","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y29EZ/ykU1Qe6AAw@squeak.grove.modra.org/mbox/"},{"id":19138,"url":"https://patchwork.plctlab.org/api/1.2/patches/19138/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221112091217.558020-1-dimitar@dinux.eu/","msgid":"<20221112091217.558020-1-dimitar@dinux.eu>","list_archive_url":null,"date":"2022-11-12T09:12:17","name":"pru: bfd: Correct default to no execstack","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221112091217.558020-1-dimitar@dinux.eu/mbox/"},{"id":19173,"url":"https://patchwork.plctlab.org/api/1.2/patches/19173/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221112124441.5084-1-patrick@monnerat.net/","msgid":"<20221112124441.5084-1-patrick@monnerat.net>","list_archive_url":null,"date":"2022-11-12T12:44:41","name":"binutils/objcopy: keep relocation while renaming a section with explicit flags","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221112124441.5084-1-patrick@monnerat.net/mbox/"},{"id":19377,"url":"https://patchwork.plctlab.org/api/1.2/patches/19377/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221113155921.1445808-1-christoph.muellner@vrull.eu/","msgid":"<20221113155921.1445808-1-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2022-11-13T15:59:20","name":"[1/2] RISC-V: Add T-Head Fmv vendor extension","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221113155921.1445808-1-christoph.muellner@vrull.eu/mbox/"},{"id":19378,"url":"https://patchwork.plctlab.org/api/1.2/patches/19378/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221113155921.1445808-2-christoph.muellner@vrull.eu/","msgid":"<20221113155921.1445808-2-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2022-11-13T15:59:21","name":"[2/2] RISC-V: Add T-Head Int vendor extension","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221113155921.1445808-2-christoph.muellner@vrull.eu/mbox/"},{"id":19850,"url":"https://patchwork.plctlab.org/api/1.2/patches/19850/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221114150348.112815-1-bwerl.dev@gmail.com/","msgid":"<20221114150348.112815-1-bwerl.dev@gmail.com>","list_archive_url":null,"date":"2022-11-14T15:03:48","name":"readelf: use fseeko for elf files >= 2 GiB on x86_64-mingw32","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221114150348.112815-1-bwerl.dev@gmail.com/mbox/"},{"id":19866,"url":"https://patchwork.plctlab.org/api/1.2/patches/19866/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3dd1c6f9-a773-c05f-44d7-12b7947072d2@suse.com/","msgid":"<3dd1c6f9-a773-c05f-44d7-12b7947072d2@suse.com>","list_archive_url":null,"date":"2022-11-14T16:12:26","name":"x86: infer No_*Suf from other insn attributes","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3dd1c6f9-a773-c05f-44d7-12b7947072d2@suse.com/mbox/"},{"id":19934,"url":"https://patchwork.plctlab.org/api/1.2/patches/19934/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f659dfbb-b84b-af86-bd8c-d177900af779@linaro.org/","msgid":"","list_archive_url":null,"date":"2022-11-14T17:24:23","name":"[V2] GAS fix alignment for aarch64-pe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f659dfbb-b84b-af86-bd8c-d177900af779@linaro.org/mbox/"},{"id":20111,"url":"https://patchwork.plctlab.org/api/1.2/patches/20111/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221115010409.24214-1-mark@harmstone.com/","msgid":"<20221115010409.24214-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-11-15T01:04:09","name":"gas: Add --gcodeview option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221115010409.24214-1-mark@harmstone.com/mbox/"},{"id":20174,"url":"https://patchwork.plctlab.org/api/1.2/patches/20174/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d305cd6178975195b025828561d59e505524ea45.1668486687.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-11-15T04:31:22","name":"[v3,1/8] RISC-V: Add a space at the end of pinfo","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d305cd6178975195b025828561d59e505524ea45.1668486687.git.research_trasio@irq.a4lg.com/mbox/"},{"id":20177,"url":"https://patchwork.plctlab.org/api/1.2/patches/20177/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2627dd5e18e59b6d976a8e6f1be39336e8a12cc3.1668486687.git.research_trasio@irq.a4lg.com/","msgid":"<2627dd5e18e59b6d976a8e6f1be39336e8a12cc3.1668486687.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-15T04:31:23","name":"[v3,2/8] RISC-V: Fix obvious misalignments ('\''Zbb'\''/'\''Zba'\'')","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2627dd5e18e59b6d976a8e6f1be39336e8a12cc3.1668486687.git.research_trasio@irq.a4lg.com/mbox/"},{"id":20173,"url":"https://patchwork.plctlab.org/api/1.2/patches/20173/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9d110279505cf502900a000a07e6e82b50f12adc.1668486687.git.research_trasio@irq.a4lg.com/","msgid":"<9d110279505cf502900a000a07e6e82b50f12adc.1668486687.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-15T04:31:24","name":"[v3,3/8] RISC-V: Remove spaces in opcode entries","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9d110279505cf502900a000a07e6e82b50f12adc.1668486687.git.research_trasio@irq.a4lg.com/mbox/"},{"id":20179,"url":"https://patchwork.plctlab.org/api/1.2/patches/20179/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8f77aa968ed9457ce1bce0a1f6449a287d0e6a18.1668486687.git.research_trasio@irq.a4lg.com/","msgid":"<8f77aa968ed9457ce1bce0a1f6449a287d0e6a18.1668486687.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-15T04:31:25","name":"[v3,4/8] RISC-V: Remove unused instruction macros","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8f77aa968ed9457ce1bce0a1f6449a287d0e6a18.1668486687.git.research_trasio@irq.a4lg.com/mbox/"},{"id":20176,"url":"https://patchwork.plctlab.org/api/1.2/patches/20176/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b43454773d597c1bc51741ef09aac960fecdfbd5.1668486687.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-11-15T04:31:26","name":"[v3,5/8] RISC-V: Complete tidying up with SCALL and SBREAK","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b43454773d597c1bc51741ef09aac960fecdfbd5.1668486687.git.research_trasio@irq.a4lg.com/mbox/"},{"id":20178,"url":"https://patchwork.plctlab.org/api/1.2/patches/20178/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/58cfec431ff2535aeb0c3fd9213933cf28864cb9.1668486687.git.research_trasio@irq.a4lg.com/","msgid":"<58cfec431ff2535aeb0c3fd9213933cf28864cb9.1668486687.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-15T04:31:27","name":"[v3,6/8] RISC-V: Tidying up with fmv.w.x and fmv.x.w","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/58cfec431ff2535aeb0c3fd9213933cf28864cb9.1668486687.git.research_trasio@irq.a4lg.com/mbox/"},{"id":20180,"url":"https://patchwork.plctlab.org/api/1.2/patches/20180/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/192f62be797f7c46a03acadb7d1bcdb83a7e9d6e.1668486687.git.research_trasio@irq.a4lg.com/","msgid":"<192f62be797f7c46a03acadb7d1bcdb83a7e9d6e.1668486687.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-15T04:31:28","name":"[v3,7/8] RISC-V: Make alias instructions aliases","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/192f62be797f7c46a03acadb7d1bcdb83a7e9d6e.1668486687.git.research_trasio@irq.a4lg.com/mbox/"},{"id":20175,"url":"https://patchwork.plctlab.org/api/1.2/patches/20175/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c89919c84067e1c2105b1857937df6405aec70fa.1668486687.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-11-15T04:31:29","name":"[v3,8/8] RISC-V: Use defined mask and match values","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c89919c84067e1c2105b1857937df6405aec70fa.1668486687.git.research_trasio@irq.a4lg.com/mbox/"},{"id":20185,"url":"https://patchwork.plctlab.org/api/1.2/patches/20185/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ebc1e98ae09f2c209ebaed2b81d5b418ce2c5128.1668487922.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-11-15T04:52:44","name":"[01/11] opcodes/riscv-dis.c: More tidying","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ebc1e98ae09f2c209ebaed2b81d5b418ce2c5128.1668487922.git.research_trasio@irq.a4lg.com/mbox/"},{"id":20188,"url":"https://patchwork.plctlab.org/api/1.2/patches/20188/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9795298f970f0b8a02796edc2c4249417614103b.1668487922.git.research_trasio@irq.a4lg.com/","msgid":"<9795298f970f0b8a02796edc2c4249417614103b.1668487922.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-15T04:52:45","name":"[02/11] RISC-V: Add test for '\''Zfinx'\'' register switching","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9795298f970f0b8a02796edc2c4249417614103b.1668487922.git.research_trasio@irq.a4lg.com/mbox/"},{"id":20186,"url":"https://patchwork.plctlab.org/api/1.2/patches/20186/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6c6c644515c6bc2751062543097eb14ee98e97c8.1668487922.git.research_trasio@irq.a4lg.com/","msgid":"<6c6c644515c6bc2751062543097eb14ee98e97c8.1668487922.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-15T04:52:46","name":"[03/11] RISC-V: Make mapping symbol checking consistent","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6c6c644515c6bc2751062543097eb14ee98e97c8.1668487922.git.research_trasio@irq.a4lg.com/mbox/"},{"id":20187,"url":"https://patchwork.plctlab.org/api/1.2/patches/20187/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b5b5ce7e34544c7934b775062413e0fe07dcd6e6.1668487922.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-11-15T04:52:47","name":"[04/11] RISC-V: Split riscv_get_map_state into two steps","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b5b5ce7e34544c7934b775062413e0fe07dcd6e6.1668487922.git.research_trasio@irq.a4lg.com/mbox/"},{"id":20192,"url":"https://patchwork.plctlab.org/api/1.2/patches/20192/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c143088cbaf7a19a992e008689420d95a90f3fab.1668487922.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-11-15T04:52:48","name":"[05/11] RISC-V: One time CSR hash table initialization","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c143088cbaf7a19a992e008689420d95a90f3fab.1668487922.git.research_trasio@irq.a4lg.com/mbox/"},{"id":20193,"url":"https://patchwork.plctlab.org/api/1.2/patches/20193/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9734125736efc8b63be17df87d38cf24bb14a156.1668487922.git.research_trasio@irq.a4lg.com/","msgid":"<9734125736efc8b63be17df87d38cf24bb14a156.1668487922.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-15T04:52:49","name":"[06/11] RISC-V: Use static xlen on ADDIW sequence","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9734125736efc8b63be17df87d38cf24bb14a156.1668487922.git.research_trasio@irq.a4lg.com/mbox/"},{"id":20191,"url":"https://patchwork.plctlab.org/api/1.2/patches/20191/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/34dbd0c82de0af284887a3bff649c8c53d67e752.1668487922.git.research_trasio@irq.a4lg.com/","msgid":"<34dbd0c82de0af284887a3bff649c8c53d67e752.1668487922.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-15T04:52:50","name":"[07/11] opcodes/riscv-dis.c: Add form feed for separation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/34dbd0c82de0af284887a3bff649c8c53d67e752.1668487922.git.research_trasio@irq.a4lg.com/mbox/"},{"id":20190,"url":"https://patchwork.plctlab.org/api/1.2/patches/20190/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1352fb8c63539727204df94651f371ed09bbce4c.1668487922.git.research_trasio@irq.a4lg.com/","msgid":"<1352fb8c63539727204df94651f371ed09bbce4c.1668487922.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-15T04:52:51","name":"[08/11] RISC-V: Split match/print steps on disassembler","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1352fb8c63539727204df94651f371ed09bbce4c.1668487922.git.research_trasio@irq.a4lg.com/mbox/"},{"id":20189,"url":"https://patchwork.plctlab.org/api/1.2/patches/20189/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/12cd8820841f695708875206b6461b6322c74428.1668487922.git.research_trasio@irq.a4lg.com/","msgid":"<12cd8820841f695708875206b6461b6322c74428.1668487922.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-15T04:52:52","name":"[09/11] RISC-V: Reorganize disassembler state initialization","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/12cd8820841f695708875206b6461b6322c74428.1668487922.git.research_trasio@irq.a4lg.com/mbox/"},{"id":20194,"url":"https://patchwork.plctlab.org/api/1.2/patches/20194/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6aade17e12ce2a928d044d9f148c874cf9922da8.1668487922.git.research_trasio@irq.a4lg.com/","msgid":"<6aade17e12ce2a928d044d9f148c874cf9922da8.1668487922.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-15T04:52:53","name":"[10/11] RISC-V: Reorganize arch-related initialization and management","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6aade17e12ce2a928d044d9f148c874cf9922da8.1668487922.git.research_trasio@irq.a4lg.com/mbox/"},{"id":20195,"url":"https://patchwork.plctlab.org/api/1.2/patches/20195/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a239fb0682bd24d4f1eb3014685eed78f9ea779a.1668487922.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-11-15T04:52:54","name":"[11/11] RISC-V: Move disassembler private data initialization","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a239fb0682bd24d4f1eb3014685eed78f9ea779a.1668487922.git.research_trasio@irq.a4lg.com/mbox/"},{"id":20236,"url":"https://patchwork.plctlab.org/api/1.2/patches/20236/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221115081455.2354987-2-zengxiao@eswincomputing.com/","msgid":"<20221115081455.2354987-2-zengxiao@eswincomputing.com>","list_archive_url":null,"date":"2022-11-15T08:14:55","name":"[v1,1/1] RISC-V: Make R_RISCV_SUB6 conforms to riscv abi standard","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221115081455.2354987-2-zengxiao@eswincomputing.com/mbox/"},{"id":20422,"url":"https://patchwork.plctlab.org/api/1.2/patches/20422/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221115145717.64948-1-bwerl.dev@gmail.com/","msgid":"<20221115145717.64948-1-bwerl.dev@gmail.com>","list_archive_url":null,"date":"2022-11-15T14:57:17","name":"readelf: use fseeko64 or fseeko if possible","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221115145717.64948-1-bwerl.dev@gmail.com/mbox/"},{"id":20600,"url":"https://patchwork.plctlab.org/api/1.2/patches/20600/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y3QKUwDn748CbDIs@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-11-15T21:53:23","name":"aarch64-pe can'\''t fill 16 bytes in section .text","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y3QKUwDn748CbDIs@squeak.grove.modra.org/mbox/"},{"id":20720,"url":"https://patchwork.plctlab.org/api/1.2/patches/20720/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221116053326.1337432-1-vladimir.mezentsev@oracle.com/","msgid":"<20221116053326.1337432-1-vladimir.mezentsev@oracle.com>","list_archive_url":null,"date":"2022-11-16T05:33:26","name":"PR29788, gprofng cannot display Java'\''s generated assembly code","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221116053326.1337432-1-vladimir.mezentsev@oracle.com/mbox/"},{"id":21321,"url":"https://patchwork.plctlab.org/api/1.2/patches/21321/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221116232039.1793148-1-hjl.tools@gmail.com/","msgid":"<20221116232039.1793148-1-hjl.tools@gmail.com>","list_archive_url":null,"date":"2022-11-16T23:20:39","name":"ld: Always call elf_backend_output_arch_local_syms","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221116232039.1793148-1-hjl.tools@gmail.com/mbox/"},{"id":21322,"url":"https://patchwork.plctlab.org/api/1.2/patches/21322/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221116232132.1009459-1-indu.bhagat@oracle.com/","msgid":"<20221116232132.1009459-1-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-16T23:21:32","name":"[gas,aarch64] : fix build breakage for aarch64-pe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221116232132.1009459-1-indu.bhagat@oracle.com/mbox/"},{"id":21449,"url":"https://patchwork.plctlab.org/api/1.2/patches/21449/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221117060234.1771025-1-indu.bhagat@oracle.com/","msgid":"<20221117060234.1771025-1-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-17T06:02:34","name":"[V2,gas,aarch64] : fix build breakage for aarch64-pe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221117060234.1771025-1-indu.bhagat@oracle.com/mbox/"},{"id":21662,"url":"https://patchwork.plctlab.org/api/1.2/patches/21662/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a050b8da-b978-d443-eee0-32b5a7836bb4@suse.com/","msgid":"","list_archive_url":null,"date":"2022-11-17T13:29:02","name":"[1/2] x86: instantiate i386_{op, reg}tab[] in gas instead of in libopcodes","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a050b8da-b978-d443-eee0-32b5a7836bb4@suse.com/mbox/"},{"id":21663,"url":"https://patchwork.plctlab.org/api/1.2/patches/21663/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d9b5137b-3bc0-8496-4533-03402ac00628@suse.com/","msgid":"","list_archive_url":null,"date":"2022-11-17T13:29:36","name":"[2/2] x86: break gas dependency on libopcodes","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d9b5137b-3bc0-8496-4533-03402ac00628@suse.com/mbox/"},{"id":21682,"url":"https://patchwork.plctlab.org/api/1.2/patches/21682/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221117143419.19571-1-bwerl.dev@gmail.com/","msgid":"<20221117143419.19571-1-bwerl.dev@gmail.com>","list_archive_url":null,"date":"2022-11-17T14:34:19","name":"readelf: use fseeko64 or fseeko if possible","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221117143419.19571-1-bwerl.dev@gmail.com/mbox/"},{"id":21850,"url":"https://patchwork.plctlab.org/api/1.2/patches/21850/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221117170546.1941945-1-hjl.tools@gmail.com/","msgid":"<20221117170546.1941945-1-hjl.tools@gmail.com>","list_archive_url":null,"date":"2022-11-17T17:05:46","name":"i386: Move i386_seg_prefixes to gas","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221117170546.1941945-1-hjl.tools@gmail.com/mbox/"},{"id":21858,"url":"https://patchwork.plctlab.org/api/1.2/patches/21858/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/CAPOVtOvi0D-u7MKAuO97-q241JZFojD8xppn3GdF2kH57iT+TA@mail.gmail.com/","msgid":"","list_archive_url":null,"date":"2022-11-17T17:44:00","name":"binutils: partially revert 17c6c3b99156fe82c1e637e1a5fd9f163ac788c8","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/CAPOVtOvi0D-u7MKAuO97-q241JZFojD8xppn3GdF2kH57iT+TA@mail.gmail.com/mbox/"},{"id":21992,"url":"https://patchwork.plctlab.org/api/1.2/patches/21992/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221118003212.3628771-1-christoph.muellner@vrull.eu/","msgid":"<20221118003212.3628771-1-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2022-11-18T00:32:12","name":"riscv: Add AIA extension support (Smaia, Ssaia)","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221118003212.3628771-1-christoph.muellner@vrull.eu/mbox/"},{"id":22004,"url":"https://patchwork.plctlab.org/api/1.2/patches/22004/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y3bZt50nhFXkf2WU@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-11-18T01:02:47","name":"go32 sanity check","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y3bZt50nhFXkf2WU@squeak.grove.modra.org/mbox/"},{"id":22005,"url":"https://patchwork.plctlab.org/api/1.2/patches/22005/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y3bZ0x42eeZFSqXt@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-11-18T01:03:15","name":"PR29799 heap buffer overflow in display_gdb_index dwarf.c:10548","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y3bZ0x42eeZFSqXt@squeak.grove.modra.org/mbox/"},{"id":22050,"url":"https://patchwork.plctlab.org/api/1.2/patches/22050/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4c45925619ab51261ca87d309883c9aa7cd05240.1668736896.git.research_trasio@irq.a4lg.com/","msgid":"<4c45925619ab51261ca87d309883c9aa7cd05240.1668736896.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-18T02:02:21","name":"RISC-V: Add INSN_DREF to memory read/write instructions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4c45925619ab51261ca87d309883c9aa7cd05240.1668736896.git.research_trasio@irq.a4lg.com/mbox/"},{"id":22053,"url":"https://patchwork.plctlab.org/api/1.2/patches/22053/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/13809b68ae60e912f3cb8e9bedd8eedf3899b547.1668737241.git.research_trasio@irq.a4lg.com/","msgid":"<13809b68ae60e912f3cb8e9bedd8eedf3899b547.1668737241.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-18T02:07:48","name":"[v4,1/8] RISC-V: Add a space at the end of pinfo","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/13809b68ae60e912f3cb8e9bedd8eedf3899b547.1668737241.git.research_trasio@irq.a4lg.com/mbox/"},{"id":22051,"url":"https://patchwork.plctlab.org/api/1.2/patches/22051/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9abf4696a17c5407a75d87b3c200fb9958ff227e.1668737241.git.research_trasio@irq.a4lg.com/","msgid":"<9abf4696a17c5407a75d87b3c200fb9958ff227e.1668737241.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-18T02:07:49","name":"[v4,2/8] RISC-V: Fix obvious misalignments ('\''Zbb'\''/'\''Zba'\'')","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9abf4696a17c5407a75d87b3c200fb9958ff227e.1668737241.git.research_trasio@irq.a4lg.com/mbox/"},{"id":22052,"url":"https://patchwork.plctlab.org/api/1.2/patches/22052/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/80185b54704af681ba81c6f84b6ce099cc3b5970.1668737241.git.research_trasio@irq.a4lg.com/","msgid":"<80185b54704af681ba81c6f84b6ce099cc3b5970.1668737241.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-18T02:07:50","name":"[v4,3/8] RISC-V: Remove spaces in opcode entries","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/80185b54704af681ba81c6f84b6ce099cc3b5970.1668737241.git.research_trasio@irq.a4lg.com/mbox/"},{"id":22055,"url":"https://patchwork.plctlab.org/api/1.2/patches/22055/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5d675a4132e2f6160d3294563e16f5093b5b1e20.1668737241.git.research_trasio@irq.a4lg.com/","msgid":"<5d675a4132e2f6160d3294563e16f5093b5b1e20.1668737241.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-18T02:07:51","name":"[v4,4/8] RISC-V: Remove unused instruction macros","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5d675a4132e2f6160d3294563e16f5093b5b1e20.1668737241.git.research_trasio@irq.a4lg.com/mbox/"},{"id":22056,"url":"https://patchwork.plctlab.org/api/1.2/patches/22056/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/27a4301cbae3d6788c878924f55aa9a6ae910669.1668737241.git.research_trasio@irq.a4lg.com/","msgid":"<27a4301cbae3d6788c878924f55aa9a6ae910669.1668737241.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-18T02:07:52","name":"[v4,5/8] RISC-V: Complete tidying up with SCALL and SBREAK","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/27a4301cbae3d6788c878924f55aa9a6ae910669.1668737241.git.research_trasio@irq.a4lg.com/mbox/"},{"id":22058,"url":"https://patchwork.plctlab.org/api/1.2/patches/22058/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7f0ea4bf1af541504b72791b5217253b2450071c.1668737241.git.research_trasio@irq.a4lg.com/","msgid":"<7f0ea4bf1af541504b72791b5217253b2450071c.1668737241.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-18T02:07:53","name":"[v4,6/8] RISC-V: Tidying up with fmv.w.x and fmv.x.w","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7f0ea4bf1af541504b72791b5217253b2450071c.1668737241.git.research_trasio@irq.a4lg.com/mbox/"},{"id":22057,"url":"https://patchwork.plctlab.org/api/1.2/patches/22057/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e5d45f2c8d1bb5b2d9adbfa117a3fc7d32afd6c9.1668737241.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-11-18T02:07:54","name":"[v4,7/8] RISC-V: Make alias instructions aliases","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e5d45f2c8d1bb5b2d9adbfa117a3fc7d32afd6c9.1668737241.git.research_trasio@irq.a4lg.com/mbox/"},{"id":22054,"url":"https://patchwork.plctlab.org/api/1.2/patches/22054/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3c1e28e61eb0275d0fd02a7d9ff956cc4f589104.1668737241.git.research_trasio@irq.a4lg.com/","msgid":"<3c1e28e61eb0275d0fd02a7d9ff956cc4f589104.1668737241.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-18T02:07:55","name":"[v4,8/8] RISC-V: Use defined mask and match values","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3c1e28e61eb0275d0fd02a7d9ff956cc4f589104.1668737241.git.research_trasio@irq.a4lg.com/mbox/"},{"id":22215,"url":"https://patchwork.plctlab.org/api/1.2/patches/22215/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/028280ab-56ad-2380-6bdd-3c944695ec5f@suse.com/","msgid":"<028280ab-56ad-2380-6bdd-3c944695ec5f@suse.com>","list_archive_url":null,"date":"2022-11-18T09:12:10","name":"[v2,1/4] x86: instantiate i386_{op, reg}tab[] in gas instead of in libopcodes","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/028280ab-56ad-2380-6bdd-3c944695ec5f@suse.com/mbox/"},{"id":22216,"url":"https://patchwork.plctlab.org/api/1.2/patches/22216/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b9a2ae11-6e9c-e9a8-88f6-17c686f0b844@suse.com/","msgid":"","list_archive_url":null,"date":"2022-11-18T09:13:01","name":"[v2,2/4] x86: remove i386-opc.c","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b9a2ae11-6e9c-e9a8-88f6-17c686f0b844@suse.com/mbox/"},{"id":22217,"url":"https://patchwork.plctlab.org/api/1.2/patches/22217/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fad783e7-e00a-c3c1-cb6d-89b70816a737@suse.com/","msgid":"","list_archive_url":null,"date":"2022-11-18T09:13:24","name":"[v2,3/4] x86: break gas dependency on libopcodes","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fad783e7-e00a-c3c1-cb6d-89b70816a737@suse.com/mbox/"},{"id":22218,"url":"https://patchwork.plctlab.org/api/1.2/patches/22218/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e3d67085-1385-d576-8656-30454f9e4474@suse.com/","msgid":"","list_archive_url":null,"date":"2022-11-18T09:14:05","name":"[v2,4/4] x86: drop sentinel from i386_optab[]","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e3d67085-1385-d576-8656-30454f9e4474@suse.com/mbox/"},{"id":23223,"url":"https://patchwork.plctlab.org/api/1.2/patches/23223/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2e469b6dd7d8b93ffd3cac333dd58d172a8f28d6.1668841829.git.research_trasio@irq.a4lg.com/","msgid":"<2e469b6dd7d8b93ffd3cac333dd58d172a8f28d6.1668841829.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-19T07:10:33","name":"[1/2] RISC-V: Make .insn tests stricter","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2e469b6dd7d8b93ffd3cac333dd58d172a8f28d6.1668841829.git.research_trasio@irq.a4lg.com/mbox/"},{"id":23224,"url":"https://patchwork.plctlab.org/api/1.2/patches/23224/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ed49fad6bc6aa4f59d619fd6b445582331594e08.1668841829.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-11-19T07:10:34","name":"[2/2] RISC-V: Better support for long instructions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ed49fad6bc6aa4f59d619fd6b445582331594e08.1668841829.git.research_trasio@irq.a4lg.com/mbox/"},{"id":23362,"url":"https://patchwork.plctlab.org/api/1.2/patches/23362/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7487608537fcd71f322e56d40bfb2cc605cee89a.1668906514.git.research_trasio@irq.a4lg.com/","msgid":"<7487608537fcd71f322e56d40bfb2cc605cee89a.1668906514.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-20T01:08:40","name":"[1/3] RISC-V: Use faster hash table on disassembling","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7487608537fcd71f322e56d40bfb2cc605cee89a.1668906514.git.research_trasio@irq.a4lg.com/mbox/"},{"id":23361,"url":"https://patchwork.plctlab.org/api/1.2/patches/23361/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e984efaf6c2d42891fa466338d999bf8b292dd7d.1668906514.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-11-20T01:08:41","name":"[2/3] RISC-V: Fallback on faster hash table","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e984efaf6c2d42891fa466338d999bf8b292dd7d.1668906514.git.research_trasio@irq.a4lg.com/mbox/"},{"id":23366,"url":"https://patchwork.plctlab.org/api/1.2/patches/23366/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/844db363911065a3b5f0c5e4601f89ee1d7360c5.1668906514.git.research_trasio@irq.a4lg.com/","msgid":"<844db363911065a3b5f0c5e4601f89ee1d7360c5.1668906514.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-20T01:08:42","name":"[3/3] RISC-V: Cache instruction support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/844db363911065a3b5f0c5e4601f89ee1d7360c5.1668906514.git.research_trasio@irq.a4lg.com/mbox/"},{"id":23363,"url":"https://patchwork.plctlab.org/api/1.2/patches/23363/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/88793c204c9270376959c6276fb1b63275bef3c8.1668906599.git.research_trasio@irq.a4lg.com/","msgid":"<88793c204c9270376959c6276fb1b63275bef3c8.1668906599.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-20T01:10:07","name":"[1/3] RISC-V: Easy optimization on riscv_search_mapping_symbol","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/88793c204c9270376959c6276fb1b63275bef3c8.1668906599.git.research_trasio@irq.a4lg.com/mbox/"},{"id":23365,"url":"https://patchwork.plctlab.org/api/1.2/patches/23365/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/55a36e28e1cb3983c637b3019d48717278574591.1668906599.git.research_trasio@irq.a4lg.com/","msgid":"<55a36e28e1cb3983c637b3019d48717278574591.1668906599.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-20T01:10:08","name":"[2/3] RISC-V: Per-section private data initialization","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/55a36e28e1cb3983c637b3019d48717278574591.1668906599.git.research_trasio@irq.a4lg.com/mbox/"},{"id":23364,"url":"https://patchwork.plctlab.org/api/1.2/patches/23364/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d41edfbaf150abb20fd78e8518ca5a9e7e5eb74f.1668906599.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-11-20T01:10:09","name":"[3/3] RISC-V: Optimized search on mapping symbols","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d41edfbaf150abb20fd78e8518ca5a9e7e5eb74f.1668906599.git.research_trasio@irq.a4lg.com/mbox/"},{"id":23372,"url":"https://patchwork.plctlab.org/api/1.2/patches/23372/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/94304c8d9174ae7e9cf52abc3af6ccf5e3e0ecd9.1668910970.git.research_trasio@irq.a4lg.com/","msgid":"<94304c8d9174ae7e9cf52abc3af6ccf5e3e0ecd9.1668910970.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-20T02:23:27","name":"[v3,1/3] RISC-V: Make \"priv-spec\" overridable","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/94304c8d9174ae7e9cf52abc3af6ccf5e3e0ecd9.1668910970.git.research_trasio@irq.a4lg.com/mbox/"},{"id":23371,"url":"https://patchwork.plctlab.org/api/1.2/patches/23371/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9d6008e38402c4e60ada6f3d3db14b92815177d8.1668910970.git.research_trasio@irq.a4lg.com/","msgid":"<9d6008e38402c4e60ada6f3d3db14b92815177d8.1668910970.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-20T02:23:28","name":"[v3,2/3] RISC-V: Add \"arch\" disassembler option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9d6008e38402c4e60ada6f3d3db14b92815177d8.1668910970.git.research_trasio@irq.a4lg.com/mbox/"},{"id":23370,"url":"https://patchwork.plctlab.org/api/1.2/patches/23370/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/70a4ac1ba8c12101de56c24d3a47939a2f5ee542.1668910970.git.research_trasio@irq.a4lg.com/","msgid":"<70a4ac1ba8c12101de56c24d3a47939a2f5ee542.1668910970.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-20T02:23:29","name":"[v3,3/3] gdb/testsuite: RISC-V disassembler option tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/70a4ac1ba8c12101de56c24d3a47939a2f5ee542.1668910970.git.research_trasio@irq.a4lg.com/mbox/"},{"id":23667,"url":"https://patchwork.plctlab.org/api/1.2/patches/23667/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221121110926.124434-1-aleksandar.rikalo@syrmia.com/","msgid":"<20221121110926.124434-1-aleksandar.rikalo@syrmia.com>","list_archive_url":null,"date":"2022-11-21T11:09:26","name":"[v3] Add support for nanoMIPS architecture","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221121110926.124434-1-aleksandar.rikalo@syrmia.com/mbox/"},{"id":23697,"url":"https://patchwork.plctlab.org/api/1.2/patches/23697/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221121120037.19325-1-zengxiao@eswincomputing.com/","msgid":"<20221121120037.19325-1-zengxiao@eswincomputing.com>","list_archive_url":null,"date":"2022-11-21T12:00:37","name":"[v2] RISC-V: Make R_RISCV_SUB6 conforms to riscv ABI standard","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221121120037.19325-1-zengxiao@eswincomputing.com/mbox/"},{"id":23957,"url":"https://patchwork.plctlab.org/api/1.2/patches/23957/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221121171544.3291-1-shahab@synopsys.com/","msgid":"<20221121171544.3291-1-shahab@synopsys.com>","list_archive_url":null,"date":"2022-11-21T17:15:44","name":"opcodes: Correct address for ARC'\''s \"isa_config\" aux reg","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221121171544.3291-1-shahab@synopsys.com/mbox/"},{"id":24026,"url":"https://patchwork.plctlab.org/api/1.2/patches/24026/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y3vyL3UATztRRM8v@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-11-21T21:48:31","name":"PR29807, SIGSEGV when linking fuzzed PE object","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y3vyL3UATztRRM8v@squeak.grove.modra.org/mbox/"},{"id":24269,"url":"https://patchwork.plctlab.org/api/1.2/patches/24269/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221122110927.2328582-1-christoph.muellner@vrull.eu/","msgid":"<20221122110927.2328582-1-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2022-11-22T11:09:27","name":"[v3] riscv: Add AIA extension support (Smaia, Ssaia)","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221122110927.2328582-1-christoph.muellner@vrull.eu/mbox/"},{"id":24318,"url":"https://patchwork.plctlab.org/api/1.2/patches/24318/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221122120339.23186-1-shahab@synopsys.com/","msgid":"<20221122120339.23186-1-shahab@synopsys.com>","list_archive_url":null,"date":"2022-11-22T12:03:39","name":"[PUSHED] opcodes: Correct address for ARC'\''s \"isa_config\" aux reg","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221122120339.23186-1-shahab@synopsys.com/mbox/"},{"id":24501,"url":"https://patchwork.plctlab.org/api/1.2/patches/24501/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221122181927.251937-1-hjl.tools@gmail.com/","msgid":"<20221122181927.251937-1-hjl.tools@gmail.com>","list_archive_url":null,"date":"2022-11-22T18:19:27","name":"x86: Remove libopcodes dependency","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221122181927.251937-1-hjl.tools@gmail.com/mbox/"},{"id":24599,"url":"https://patchwork.plctlab.org/api/1.2/patches/24599/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y31GJLbFpb5DCn2F@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-11-22T21:59:00","name":"Don'\''t use \"long\" in readelf for file offsets","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y31GJLbFpb5DCn2F@squeak.grove.modra.org/mbox/"},{"id":24600,"url":"https://patchwork.plctlab.org/api/1.2/patches/24600/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221122220236.429230-1-hjl.tools@gmail.com/","msgid":"<20221122220236.429230-1-hjl.tools@gmail.com>","list_archive_url":null,"date":"2022-11-22T22:02:36","name":"x86: Don'\''t define _TLS_MODULE_BASE_ for ld -r","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221122220236.429230-1-hjl.tools@gmail.com/mbox/"},{"id":24605,"url":"https://patchwork.plctlab.org/api/1.2/patches/24605/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221122221028.2924195-1-indu.bhagat@oracle.com/","msgid":"<20221122221028.2924195-1-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-22T22:10:28","name":"sframe/doc: remove usage of xrefautomaticsectiontitle","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221122221028.2924195-1-indu.bhagat@oracle.com/mbox/"},{"id":24787,"url":"https://patchwork.plctlab.org/api/1.2/patches/24787/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fdcd78c77ec384da0cb74a6d91c1e7f00bdde6cf.1669192210.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-11-23T08:30:48","name":"[v2,1/2] RISC-V: Make .insn tests stricter","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fdcd78c77ec384da0cb74a6d91c1e7f00bdde6cf.1669192210.git.research_trasio@irq.a4lg.com/mbox/"},{"id":24789,"url":"https://patchwork.plctlab.org/api/1.2/patches/24789/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/cdd1f831660ce24353b47dc4098992f136e45bcc.1669192210.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-11-23T08:30:49","name":"[v2,2/2] RISC-V: Better support for long instructions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/cdd1f831660ce24353b47dc4098992f136e45bcc.1669192210.git.research_trasio@irq.a4lg.com/mbox/"},{"id":24873,"url":"https://patchwork.plctlab.org/api/1.2/patches/24873/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/40d1240c-154b-ecea-c391-9fab12129b2b@suse.com/","msgid":"<40d1240c-154b-ecea-c391-9fab12129b2b@suse.com>","list_archive_url":null,"date":"2022-11-23T10:33:38","name":"[1/3] x86: correct handling of LAR and LSL","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/40d1240c-154b-ecea-c391-9fab12129b2b@suse.com/mbox/"},{"id":24876,"url":"https://patchwork.plctlab.org/api/1.2/patches/24876/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3dbee940-c57e-f89f-fdb1-730b275c0c17@suse.com/","msgid":"<3dbee940-c57e-f89f-fdb1-730b275c0c17@suse.com>","list_archive_url":null,"date":"2022-11-23T10:34:34","name":"[2/3] x86: add missing CheckRegSize","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3dbee940-c57e-f89f-fdb1-730b275c0c17@suse.com/mbox/"},{"id":24882,"url":"https://patchwork.plctlab.org/api/1.2/patches/24882/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0168ba4a-766c-7cfe-7917-53259f846da0@suse.com/","msgid":"<0168ba4a-766c-7cfe-7917-53259f846da0@suse.com>","list_archive_url":null,"date":"2022-11-23T10:35:16","name":"[3/3] x86: widen applicability and use of CheckRegSize","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0168ba4a-766c-7cfe-7917-53259f846da0@suse.com/mbox/"},{"id":24939,"url":"https://patchwork.plctlab.org/api/1.2/patches/24939/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y34R4z7auiQd9V9m@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-11-23T12:28:19","name":"asan: NULL deref in filter_symbols","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y34R4z7auiQd9V9m@squeak.grove.modra.org/mbox/"},{"id":24943,"url":"https://patchwork.plctlab.org/api/1.2/patches/24943/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y34SFSgfRguI0pMs@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-11-23T12:29:09","name":"PR22509 - Null pointer dereference on coff_slurp_reloc_table","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y34SFSgfRguI0pMs@squeak.grove.modra.org/mbox/"},{"id":25150,"url":"https://patchwork.plctlab.org/api/1.2/patches/25150/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221123194330.21185-1-mark@harmstone.com/","msgid":"<20221123194330.21185-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-11-23T19:43:30","name":"gas: Disable --gcodeview on PE targets with no O_secrel","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221123194330.21185-1-mark@harmstone.com/mbox/"},{"id":25255,"url":"https://patchwork.plctlab.org/api/1.2/patches/25255/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221124002827.1915219-1-indu.bhagat@oracle.com/","msgid":"<20221124002827.1915219-1-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-11-24T00:28:27","name":"[V2] sframe/doc: remove usage of xrefautomaticsectiontitle","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221124002827.1915219-1-indu.bhagat@oracle.com/mbox/"},{"id":25302,"url":"https://patchwork.plctlab.org/api/1.2/patches/25302/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221124034051.11711-1-mark@harmstone.com/","msgid":"<20221124034051.11711-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-11-24T03:40:51","name":"ld: Generate PDB string table","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221124034051.11711-1-mark@harmstone.com/mbox/"},{"id":25339,"url":"https://patchwork.plctlab.org/api/1.2/patches/25339/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y38dhqK5vRWbfFEO@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-11-24T07:30:14","name":"PR16995, m68k coldfire emac immediate to macsr incorrect disassembly","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y38dhqK5vRWbfFEO@squeak.grove.modra.org/mbox/"},{"id":25340,"url":"https://patchwork.plctlab.org/api/1.2/patches/25340/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y38duAgksZJEg8Ca@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-11-24T07:31:04","name":"Constify nm format array","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y38duAgksZJEg8Ca@squeak.grove.modra.org/mbox/"},{"id":25341,"url":"https://patchwork.plctlab.org/api/1.2/patches/25341/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y38eF5ySbTaGA/Gm@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-11-24T07:32:39","name":"Tidy objdump printing of section size","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y38eF5ySbTaGA/Gm@squeak.grove.modra.org/mbox/"},{"id":25382,"url":"https://patchwork.plctlab.org/api/1.2/patches/25382/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ebd260da-8bc5-7672-f529-a6bb1d9e9c7f@suse.com/","msgid":"","list_archive_url":null,"date":"2022-11-24T08:57:24","name":"[1/3] x86: extend FPU test coverage for AT&T / Intel mnemonic differences","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ebd260da-8bc5-7672-f529-a6bb1d9e9c7f@suse.com/mbox/"},{"id":25384,"url":"https://patchwork.plctlab.org/api/1.2/patches/25384/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0ef86245-7f0d-ef4e-957a-4086eb54ef43@suse.com/","msgid":"<0ef86245-7f0d-ef4e-957a-4086eb54ef43@suse.com>","list_archive_url":null,"date":"2022-11-24T08:57:56","name":"[2/3] x86: drop FloatR","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0ef86245-7f0d-ef4e-957a-4086eb54ef43@suse.com/mbox/"},{"id":25385,"url":"https://patchwork.plctlab.org/api/1.2/patches/25385/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5dd8b2df-62f2-a551-4b35-f3df66d57e04@suse.com/","msgid":"<5dd8b2df-62f2-a551-4b35-f3df66d57e04@suse.com>","list_archive_url":null,"date":"2022-11-24T08:58:36","name":"[3/3] x86: clean up after removal of support for gcc <= 2.8.1","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5dd8b2df-62f2-a551-4b35-f3df66d57e04@suse.com/mbox/"},{"id":25492,"url":"https://patchwork.plctlab.org/api/1.2/patches/25492/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9790982d-5a3d-f711-b588-184edd41a0dd@suse.cz/","msgid":"<9790982d-5a3d-f711-b588-184edd41a0dd@suse.cz>","list_archive_url":null,"date":"2022-11-24T12:18:33","name":"[PUSHED] readelf: Do not require EI_OSABI for IFUNC.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9790982d-5a3d-f711-b588-184edd41a0dd@suse.cz/mbox/"},{"id":25494,"url":"https://patchwork.plctlab.org/api/1.2/patches/25494/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/874juopmb0.fsf@redhat.com/","msgid":"<874juopmb0.fsf@redhat.com>","list_archive_url":null,"date":"2022-11-24T12:30:11","name":"Commit: Fix compile time warnings in conftest.c files","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/874juopmb0.fsf@redhat.com/mbox/"},{"id":25627,"url":"https://patchwork.plctlab.org/api/1.2/patches/25627/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221124154531.903548-1-aleksandar.rikalo@syrmia.com/","msgid":"<20221124154531.903548-1-aleksandar.rikalo@syrmia.com>","list_archive_url":null,"date":"2022-11-24T15:45:31","name":"[v4] Add support for nanoMIPS architecture","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221124154531.903548-1-aleksandar.rikalo@syrmia.com/mbox/"},{"id":25784,"url":"https://patchwork.plctlab.org/api/1.2/patches/25784/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/66ca80358f78d66d66bbf390fc0be8bec8183e93.1669342633.git.research_trasio@irq.a4lg.com/","msgid":"<66ca80358f78d66d66bbf390fc0be8bec8183e93.1669342633.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-25T02:17:23","name":"[v3,1/2] RISC-V: Better support for long instructions (disassembler)","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/66ca80358f78d66d66bbf390fc0be8bec8183e93.1669342633.git.research_trasio@irq.a4lg.com/mbox/"},{"id":25785,"url":"https://patchwork.plctlab.org/api/1.2/patches/25785/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/47d1751320314f02bede4f6096c09b7f6585c94d.1669342633.git.research_trasio@irq.a4lg.com/","msgid":"<47d1751320314f02bede4f6096c09b7f6585c94d.1669342633.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-25T02:17:24","name":"[v3,2/2] RISC-V: Better support for long instructions (assembler)","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/47d1751320314f02bede4f6096c09b7f6585c94d.1669342633.git.research_trasio@irq.a4lg.com/mbox/"},{"id":25790,"url":"https://patchwork.plctlab.org/api/1.2/patches/25790/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221125025334.26665-1-mark@harmstone.com/","msgid":"<20221125025334.26665-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-11-25T02:53:34","name":"[v2] ld: Generate PDB string table","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221125025334.26665-1-mark@harmstone.com/mbox/"},{"id":25791,"url":"https://patchwork.plctlab.org/api/1.2/patches/25791/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221125025433.26818-1-mark@harmstone.com/","msgid":"<20221125025433.26818-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-11-25T02:54:33","name":"ld: Write DEBUG_S_FILECHKSMS entries in PDBs","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221125025433.26818-1-mark@harmstone.com/mbox/"},{"id":25914,"url":"https://patchwork.plctlab.org/api/1.2/patches/25914/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/457fc649-adf7-a35d-2ae1-8a9f1a00ce0a@suse.com/","msgid":"<457fc649-adf7-a35d-2ae1-8a9f1a00ce0a@suse.com>","list_archive_url":null,"date":"2022-11-25T10:09:58","name":"Arm: .noinit and .persistent are not supported for Linux targets","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/457fc649-adf7-a35d-2ae1-8a9f1a00ce0a@suse.com/mbox/"},{"id":25948,"url":"https://patchwork.plctlab.org/api/1.2/patches/25948/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2c04525e48f5fc135b6dcb35ca6f1fec4e9b122b.1669376496.git.research_trasio@irq.a4lg.com/","msgid":"<2c04525e48f5fc135b6dcb35ca6f1fec4e9b122b.1669376496.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-25T11:41:40","name":"[v3,1/3] RISC-V: Better support for long instructions (disassembler)","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2c04525e48f5fc135b6dcb35ca6f1fec4e9b122b.1669376496.git.research_trasio@irq.a4lg.com/mbox/"},{"id":25950,"url":"https://patchwork.plctlab.org/api/1.2/patches/25950/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2c04525e48f5fc135b6dcb35ca6f1fec4e9b122b.1669376539.git.research_trasio@irq.a4lg.com/","msgid":"<2c04525e48f5fc135b6dcb35ca6f1fec4e9b122b.1669376539.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-25T11:42:20","name":"[v4,1/3] RISC-V: Better support for long instructions (disassembler)","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2c04525e48f5fc135b6dcb35ca6f1fec4e9b122b.1669376539.git.research_trasio@irq.a4lg.com/mbox/"},{"id":25951,"url":"https://patchwork.plctlab.org/api/1.2/patches/25951/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d8d2cda8e4b1a82f93fd9e9daa57f705c582d06f.1669376539.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-11-25T11:42:21","name":"[v4,2/3] RISC-V: Better support for long instructions (assembler)","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d8d2cda8e4b1a82f93fd9e9daa57f705c582d06f.1669376539.git.research_trasio@irq.a4lg.com/mbox/"},{"id":25949,"url":"https://patchwork.plctlab.org/api/1.2/patches/25949/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/523d1243d28a817c7ab371daed61335ab1dd31bc.1669376539.git.research_trasio@irq.a4lg.com/","msgid":"<523d1243d28a817c7ab371daed61335ab1dd31bc.1669376539.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-25T11:42:22","name":"[v4,3/3] RISC-V: Better support for long instructions (tests)","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/523d1243d28a817c7ab371daed61335ab1dd31bc.1669376539.git.research_trasio@irq.a4lg.com/mbox/"},{"id":26085,"url":"https://patchwork.plctlab.org/api/1.2/patches/26085/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.LSU.2.20.2211251556330.24878@wotan.suse.de/","msgid":"","list_archive_url":null,"date":"2022-11-25T16:00:05","name":"Fix msp430 section name scribbling and tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.LSU.2.20.2211251556330.24878@wotan.suse.de/mbox/"},{"id":26086,"url":"https://patchwork.plctlab.org/api/1.2/patches/26086/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.LSU.2.20.2211251600280.24878@wotan.suse.de/","msgid":"","list_archive_url":null,"date":"2022-11-25T16:01:58","name":"Special case more simple patterns","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.LSU.2.20.2211251600280.24878@wotan.suse.de/mbox/"},{"id":26087,"url":"https://patchwork.plctlab.org/api/1.2/patches/26087/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.LSU.2.20.2211251602070.24878@wotan.suse.de/","msgid":"","list_archive_url":null,"date":"2022-11-25T16:04:51","name":"Only use wild_sort_fast","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.LSU.2.20.2211251602070.24878@wotan.suse.de/mbox/"},{"id":26094,"url":"https://patchwork.plctlab.org/api/1.2/patches/26094/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.LSU.2.20.2211251644290.24878@wotan.suse.de/","msgid":"","list_archive_url":null,"date":"2022-11-25T16:44:54","name":"[1/8] section-select: Lazily resolve section matches","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.LSU.2.20.2211251644290.24878@wotan.suse.de/mbox/"},{"id":26095,"url":"https://patchwork.plctlab.org/api/1.2/patches/26095/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.LSU.2.20.2211251645000.24878@wotan.suse.de/","msgid":"","list_archive_url":null,"date":"2022-11-25T16:46:41","name":"[2/8] section-select: Deal with sections added late","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.LSU.2.20.2211251645000.24878@wotan.suse.de/mbox/"},{"id":26096,"url":"https://patchwork.plctlab.org/api/1.2/patches/26096/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.LSU.2.20.2211251646510.24878@wotan.suse.de/","msgid":"","list_archive_url":null,"date":"2022-11-25T16:47:17","name":"[3/8] section-select: Implement a prefix-tree","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.LSU.2.20.2211251646510.24878@wotan.suse.de/mbox/"},{"id":26097,"url":"https://patchwork.plctlab.org/api/1.2/patches/26097/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.LSU.2.20.2211251647220.24878@wotan.suse.de/","msgid":"","list_archive_url":null,"date":"2022-11-25T16:55:12","name":"[4/8] section-select: Completely rebuild matches","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.LSU.2.20.2211251647220.24878@wotan.suse.de/mbox/"},{"id":26098,"url":"https://patchwork.plctlab.org/api/1.2/patches/26098/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.LSU.2.20.2211251655221.24878@wotan.suse.de/","msgid":"","list_archive_url":null,"date":"2022-11-25T16:55:36","name":"[5/8] section-select: Remove unused code","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.LSU.2.20.2211251655221.24878@wotan.suse.de/mbox/"},{"id":26099,"url":"https://patchwork.plctlab.org/api/1.2/patches/26099/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.LSU.2.20.2211251655420.24878@wotan.suse.de/","msgid":"","list_archive_url":null,"date":"2022-11-25T16:55:57","name":"[6/8] section-select: Cleanup","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.LSU.2.20.2211251655420.24878@wotan.suse.de/mbox/"},{"id":26100,"url":"https://patchwork.plctlab.org/api/1.2/patches/26100/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.LSU.2.20.2211251656020.24878@wotan.suse.de/","msgid":"","list_archive_url":null,"date":"2022-11-25T16:57:38","name":"[7/8] section-select: Remove bfd_max_section_id again","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.LSU.2.20.2211251656020.24878@wotan.suse.de/mbox/"},{"id":26101,"url":"https://patchwork.plctlab.org/api/1.2/patches/26101/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.LSU.2.20.2211251657410.24878@wotan.suse.de/","msgid":"","list_archive_url":null,"date":"2022-11-25T16:58:03","name":"[8/8] section-select: Fix exclude-file-3","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.LSU.2.20.2211251657410.24878@wotan.suse.de/mbox/"},{"id":26180,"url":"https://patchwork.plctlab.org/api/1.2/patches/26180/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c55d94343b1e04c73baf4db9d8b22111528f1b40.1669432329.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-11-26T03:13:51","name":"RISC-V: Allow merging '\''H'\'' extension","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c55d94343b1e04c73baf4db9d8b22111528f1b40.1669432329.git.research_trasio@irq.a4lg.com/mbox/"},{"id":26307,"url":"https://patchwork.plctlab.org/api/1.2/patches/26307/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221127023840.32080-1-mark@harmstone.com/","msgid":"<20221127023840.32080-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-11-27T02:38:39","name":"ld: Fix segfault in populate_publics_stream","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221127023840.32080-1-mark@harmstone.com/mbox/"},{"id":26308,"url":"https://patchwork.plctlab.org/api/1.2/patches/26308/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221127023840.32080-2-mark@harmstone.com/","msgid":"<20221127023840.32080-2-mark@harmstone.com>","list_archive_url":null,"date":"2022-11-27T02:38:40","name":"ld: Write DEBUG_S_LINES entries in PDB file","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221127023840.32080-2-mark@harmstone.com/mbox/"},{"id":26350,"url":"https://patchwork.plctlab.org/api/1.2/patches/26350/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221127125325.263577-1-brobecker@adacore.com/","msgid":"<20221127125325.263577-1-brobecker@adacore.com>","list_archive_url":null,"date":"2022-11-27T12:53:25","name":"[RFA] src-release.sh: Fix gdb source tarball build failure due to libsframe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221127125325.263577-1-brobecker@adacore.com/mbox/"},{"id":26493,"url":"https://patchwork.plctlab.org/api/1.2/patches/26493/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5965a4d1d20a33accd4a9872f87da9e0fd6c1747.1669610611.git.research_trasio@irq.a4lg.com/","msgid":"<5965a4d1d20a33accd4a9872f87da9e0fd6c1747.1669610611.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-28T04:43:36","name":"[v2,01/11] opcodes/riscv-dis.c: More tidying","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5965a4d1d20a33accd4a9872f87da9e0fd6c1747.1669610611.git.research_trasio@irq.a4lg.com/mbox/"},{"id":26494,"url":"https://patchwork.plctlab.org/api/1.2/patches/26494/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/761a39a87ef882c6d99d135988d251d18c2bf096.1669610611.git.research_trasio@irq.a4lg.com/","msgid":"<761a39a87ef882c6d99d135988d251d18c2bf096.1669610611.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-28T04:43:37","name":"[v2,02/11] RISC-V: Add test for '\''Zfinx'\'' register switching","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/761a39a87ef882c6d99d135988d251d18c2bf096.1669610611.git.research_trasio@irq.a4lg.com/mbox/"},{"id":26495,"url":"https://patchwork.plctlab.org/api/1.2/patches/26495/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c52af18da452a844c5fddf64b9b8e7b53f208111.1669610611.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-11-28T04:43:38","name":"[v2,03/11] RISC-V: Make mapping symbol checking consistent","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c52af18da452a844c5fddf64b9b8e7b53f208111.1669610611.git.research_trasio@irq.a4lg.com/mbox/"},{"id":26497,"url":"https://patchwork.plctlab.org/api/1.2/patches/26497/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/395973f56b805a000b0e2929c6b2ba6cd8fd140b.1669610611.git.research_trasio@irq.a4lg.com/","msgid":"<395973f56b805a000b0e2929c6b2ba6cd8fd140b.1669610611.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-28T04:43:39","name":"[v2,04/11] RISC-V: Split riscv_get_map_state into two steps","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/395973f56b805a000b0e2929c6b2ba6cd8fd140b.1669610611.git.research_trasio@irq.a4lg.com/mbox/"},{"id":26496,"url":"https://patchwork.plctlab.org/api/1.2/patches/26496/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/72c8e56861fccff6720a9b6ccefcecfd80e1adba.1669610611.git.research_trasio@irq.a4lg.com/","msgid":"<72c8e56861fccff6720a9b6ccefcecfd80e1adba.1669610611.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-28T04:43:40","name":"[v2,05/11] RISC-V: One time CSR hash table initialization","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/72c8e56861fccff6720a9b6ccefcecfd80e1adba.1669610611.git.research_trasio@irq.a4lg.com/mbox/"},{"id":26499,"url":"https://patchwork.plctlab.org/api/1.2/patches/26499/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/072cb269b90f85fdfd880a6513080a18ddde015d.1669610611.git.research_trasio@irq.a4lg.com/","msgid":"<072cb269b90f85fdfd880a6513080a18ddde015d.1669610611.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-28T04:43:41","name":"[v2,06/11] RISC-V: Use static xlen on ADDIW sequence","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/072cb269b90f85fdfd880a6513080a18ddde015d.1669610611.git.research_trasio@irq.a4lg.com/mbox/"},{"id":26503,"url":"https://patchwork.plctlab.org/api/1.2/patches/26503/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8f4167371bc52f2c4c7fc6f1a0fc3775e8e8de95.1669610611.git.research_trasio@irq.a4lg.com/","msgid":"<8f4167371bc52f2c4c7fc6f1a0fc3775e8e8de95.1669610611.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-28T04:43:42","name":"[v2,07/11] opcodes/riscv-dis.c: Add form feed for separation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8f4167371bc52f2c4c7fc6f1a0fc3775e8e8de95.1669610611.git.research_trasio@irq.a4lg.com/mbox/"},{"id":26498,"url":"https://patchwork.plctlab.org/api/1.2/patches/26498/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c30cdce491780153a7fe89b79ac4b5f1a03f6e5c.1669610611.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-11-28T04:43:43","name":"[v2,08/11] RISC-V: Split match/print steps on disassembler","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c30cdce491780153a7fe89b79ac4b5f1a03f6e5c.1669610611.git.research_trasio@irq.a4lg.com/mbox/"},{"id":26506,"url":"https://patchwork.plctlab.org/api/1.2/patches/26506/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a30d861f289af8dfaf7c80ff275980699aa78482.1669610611.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-11-28T04:43:44","name":"[v2,09/11] RISC-V: Reorganize disassembler state initialization","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a30d861f289af8dfaf7c80ff275980699aa78482.1669610611.git.research_trasio@irq.a4lg.com/mbox/"},{"id":26508,"url":"https://patchwork.plctlab.org/api/1.2/patches/26508/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0e328130d90af42f30e3632fadd6c48e422b7b82.1669610611.git.research_trasio@irq.a4lg.com/","msgid":"<0e328130d90af42f30e3632fadd6c48e422b7b82.1669610611.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-28T04:43:45","name":"[v2,10/11] RISC-V: Reorganize arch-related initialization and management","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0e328130d90af42f30e3632fadd6c48e422b7b82.1669610611.git.research_trasio@irq.a4lg.com/mbox/"},{"id":26500,"url":"https://patchwork.plctlab.org/api/1.2/patches/26500/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/75d9e5b0cfebcce34c855e4c98a956de4d7d7753.1669610611.git.research_trasio@irq.a4lg.com/","msgid":"<75d9e5b0cfebcce34c855e4c98a956de4d7d7753.1669610611.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-28T04:43:46","name":"[v2,11/11] RISC-V: Move disassembler private data initialization","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/75d9e5b0cfebcce34c855e4c98a956de4d7d7753.1669610611.git.research_trasio@irq.a4lg.com/mbox/"},{"id":26504,"url":"https://patchwork.plctlab.org/api/1.2/patches/26504/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a3f9238a36255d5bd251cc73cee6a47eea6b9b49.1669610780.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-11-28T04:46:20","name":"[v2,1/3] RISC-V: Use faster hash table on disassembling","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a3f9238a36255d5bd251cc73cee6a47eea6b9b49.1669610780.git.research_trasio@irq.a4lg.com/mbox/"},{"id":26507,"url":"https://patchwork.plctlab.org/api/1.2/patches/26507/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0cd0bbfa70f83db276facb842b9a7bca1aaa77a6.1669610780.git.research_trasio@irq.a4lg.com/","msgid":"<0cd0bbfa70f83db276facb842b9a7bca1aaa77a6.1669610780.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-28T04:46:21","name":"[v2,2/3] RISC-V: Fallback on faster hash table","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0cd0bbfa70f83db276facb842b9a7bca1aaa77a6.1669610780.git.research_trasio@irq.a4lg.com/mbox/"},{"id":26501,"url":"https://patchwork.plctlab.org/api/1.2/patches/26501/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5b561967091a59d0052bd717d1b9f3e31ef841cc.1669610780.git.research_trasio@irq.a4lg.com/","msgid":"<5b561967091a59d0052bd717d1b9f3e31ef841cc.1669610780.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-28T04:46:22","name":"[v2,3/3] RISC-V: Cache instruction support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5b561967091a59d0052bd717d1b9f3e31ef841cc.1669610780.git.research_trasio@irq.a4lg.com/mbox/"},{"id":26505,"url":"https://patchwork.plctlab.org/api/1.2/patches/26505/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c49e114f7ae383c0e1da452391f19ecf45a3896e.1669610841.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-11-28T04:47:21","name":"[v2,1/3] RISC-V: Easy optimization on riscv_search_mapping_symbol","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c49e114f7ae383c0e1da452391f19ecf45a3896e.1669610841.git.research_trasio@irq.a4lg.com/mbox/"},{"id":26509,"url":"https://patchwork.plctlab.org/api/1.2/patches/26509/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4b8fcca24b8897f382b6e32fd29337f0b6972e2f.1669610841.git.research_trasio@irq.a4lg.com/","msgid":"<4b8fcca24b8897f382b6e32fd29337f0b6972e2f.1669610841.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-28T04:47:22","name":"[v2,2/3] RISC-V: Per-section private data initialization","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4b8fcca24b8897f382b6e32fd29337f0b6972e2f.1669610841.git.research_trasio@irq.a4lg.com/mbox/"},{"id":26510,"url":"https://patchwork.plctlab.org/api/1.2/patches/26510/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f1cbc305ba19880fa0631ebe691b5c0984cbf111.1669610841.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-11-28T04:47:23","name":"[v2,3/3] RISC-V: Optimized search on mapping symbols","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f1cbc305ba19880fa0631ebe691b5c0984cbf111.1669610841.git.research_trasio@irq.a4lg.com/mbox/"},{"id":26531,"url":"https://patchwork.plctlab.org/api/1.2/patches/26531/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221128063532.1153605-1-jiawei@iscas.ac.cn/","msgid":"<20221128063532.1153605-1-jiawei@iscas.ac.cn>","list_archive_url":null,"date":"2022-11-28T06:35:32","name":"RISC-V: Add support for RISCV64 EFI(efi-*-riscv64)","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221128063532.1153605-1-jiawei@iscas.ac.cn/mbox/"},{"id":26532,"url":"https://patchwork.plctlab.org/api/1.2/patches/26532/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d1c4d243e6e33c6d0c681a7de3a8fb8be548c99d.1669617534.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-11-28T06:39:32","name":"[1/3] RISC-V: Allocate \"various\" operand type","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d1c4d243e6e33c6d0c681a7de3a8fb8be548c99d.1669617534.git.research_trasio@irq.a4lg.com/mbox/"},{"id":26533,"url":"https://patchwork.plctlab.org/api/1.2/patches/26533/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1a60e4b17f89e7aa94a6a41674f885398e5afd85.1669617534.git.research_trasio@irq.a4lg.com/","msgid":"<1a60e4b17f89e7aa94a6a41674f885398e5afd85.1669617534.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-28T06:39:33","name":"[2/3] RISC-V: Reorganize invalid rounding mode test","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1a60e4b17f89e7aa94a6a41674f885398e5afd85.1669617534.git.research_trasio@irq.a4lg.com/mbox/"},{"id":26534,"url":"https://patchwork.plctlab.org/api/1.2/patches/26534/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/354029278ac02efee0bf1f1dbc3514647f057424.1669617534.git.research_trasio@irq.a4lg.com/","msgid":"<354029278ac02efee0bf1f1dbc3514647f057424.1669617534.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-28T06:39:34","name":"[3/3] RISC-V: Rounding mode on widening instructions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/354029278ac02efee0bf1f1dbc3514647f057424.1669617534.git.research_trasio@irq.a4lg.com/mbox/"},{"id":26600,"url":"https://patchwork.plctlab.org/api/1.2/patches/26600/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y4SDJrb7d7HMtR7H@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-11-28T09:45:10","name":"asan: pef: buffer overflow","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y4SDJrb7d7HMtR7H@squeak.grove.modra.org/mbox/"},{"id":26601,"url":"https://patchwork.plctlab.org/api/1.2/patches/26601/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y4SDxVt7uN6m6oKA@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-11-28T09:47:49","name":"PR10368, ISO 8859 mentioned as 7bit encoding in strings documentation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y4SDxVt7uN6m6oKA@squeak.grove.modra.org/mbox/"},{"id":26634,"url":"https://patchwork.plctlab.org/api/1.2/patches/26634/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/da678d9e-b1eb-e599-ec0b-2a991d65e61c@suse.com/","msgid":"","list_archive_url":null,"date":"2022-11-28T11:30:46","name":"[v3,1/6] x86: instantiate i386_{op, reg}tab[] in gas instead of in libopcodes","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/da678d9e-b1eb-e599-ec0b-2a991d65e61c@suse.com/mbox/"},{"id":26636,"url":"https://patchwork.plctlab.org/api/1.2/patches/26636/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/851ace49-624f-c3bc-805f-59feeaf8a711@suse.com/","msgid":"<851ace49-624f-c3bc-805f-59feeaf8a711@suse.com>","list_archive_url":null,"date":"2022-11-28T11:31:20","name":"[v3,2/6] x86: remove i386-opc.c","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/851ace49-624f-c3bc-805f-59feeaf8a711@suse.com/mbox/"},{"id":26638,"url":"https://patchwork.plctlab.org/api/1.2/patches/26638/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2bf96982-d3d6-026a-ca1c-16b932d9630a@suse.com/","msgid":"<2bf96982-d3d6-026a-ca1c-16b932d9630a@suse.com>","list_archive_url":null,"date":"2022-11-28T11:31:44","name":"[v3,3/6] x86: break gas dependency on libopcodes","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2bf96982-d3d6-026a-ca1c-16b932d9630a@suse.com/mbox/"},{"id":26640,"url":"https://patchwork.plctlab.org/api/1.2/patches/26640/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c8f5780b-072e-b184-f153-3c2af7ea577e@suse.com/","msgid":"","list_archive_url":null,"date":"2022-11-28T11:32:07","name":"[v3,4/6] x86: add generated tables dependency check to gas","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c8f5780b-072e-b184-f153-3c2af7ea577e@suse.com/mbox/"},{"id":26643,"url":"https://patchwork.plctlab.org/api/1.2/patches/26643/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/414cbe39-9398-ddab-97f2-93d6c0bf9852@suse.com/","msgid":"<414cbe39-9398-ddab-97f2-93d6c0bf9852@suse.com>","list_archive_url":null,"date":"2022-11-28T11:32:40","name":"[v3,5/6] x86: drop sentinel from i386_optab[]","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/414cbe39-9398-ddab-97f2-93d6c0bf9852@suse.com/mbox/"},{"id":26644,"url":"https://patchwork.plctlab.org/api/1.2/patches/26644/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0387160b-8925-7515-e287-e1f240f93523@suse.com/","msgid":"<0387160b-8925-7515-e287-e1f240f93523@suse.com>","list_archive_url":null,"date":"2022-11-28T11:33:37","name":"[v3,6/6] x86: generate template sets data at build time","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0387160b-8925-7515-e287-e1f240f93523@suse.com/mbox/"},{"id":26794,"url":"https://patchwork.plctlab.org/api/1.2/patches/26794/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/67cc7870-f49c-08ed-afb3-e83f4378095a@arm.com/","msgid":"<67cc7870-f49c-08ed-afb3-e83f4378095a@arm.com>","list_archive_url":null,"date":"2022-11-28T14:13:12","name":"[1/2] gas: arm: Fix a further IT-predicated vcvt issue in the presense of MVE vcvtn","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/67cc7870-f49c-08ed-afb3-e83f4378095a@arm.com/mbox/"},{"id":26795,"url":"https://patchwork.plctlab.org/api/1.2/patches/26795/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b40e6dc8-9ff8-000c-f639-ee516c4ccab7@arm.com/","msgid":"","list_archive_url":null,"date":"2022-11-28T14:13:27","name":"[2/2] gas: arm: Change warning message to not reference specific A-class architecture revision","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b40e6dc8-9ff8-000c-f639-ee516c4ccab7@arm.com/mbox/"},{"id":26799,"url":"https://patchwork.plctlab.org/api/1.2/patches/26799/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/661d0e07-cc75-0fba-941b-88160dbcbb13@suse.com/","msgid":"<661d0e07-cc75-0fba-941b-88160dbcbb13@suse.com>","list_archive_url":null,"date":"2022-11-28T14:24:31","name":"x86/Intel: adjustment to restricted suffix derivation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/661d0e07-cc75-0fba-941b-88160dbcbb13@suse.com/mbox/"},{"id":26977,"url":"https://patchwork.plctlab.org/api/1.2/patches/26977/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/CAMe9rOpbKEZ=wSgTbDLEXgzj2sbAHp1uU0WSGy0qTPL1fakM0g@mail.gmail.com/","msgid":"","list_archive_url":null,"date":"2022-11-28T23:49:42","name":"[v2] x86: Remove libopcodes dependency","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/CAMe9rOpbKEZ=wSgTbDLEXgzj2sbAHp1uU0WSGy0qTPL1fakM0g@mail.gmail.com/mbox/"},{"id":26982,"url":"https://patchwork.plctlab.org/api/1.2/patches/26982/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221129001015.21775-1-mark@harmstone.com/","msgid":"<20221129001015.21775-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-11-29T00:10:13","name":"ld: Write types into TPI stream of PDB","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221129001015.21775-1-mark@harmstone.com/mbox/"},{"id":26981,"url":"https://patchwork.plctlab.org/api/1.2/patches/26981/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221129001015.21775-2-mark@harmstone.com/","msgid":"<20221129001015.21775-2-mark@harmstone.com>","list_archive_url":null,"date":"2022-11-29T00:10:14","name":"ld: Write types into IPI stream of PDB","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221129001015.21775-2-mark@harmstone.com/mbox/"},{"id":26983,"url":"https://patchwork.plctlab.org/api/1.2/patches/26983/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221129001015.21775-3-mark@harmstone.com/","msgid":"<20221129001015.21775-3-mark@harmstone.com>","list_archive_url":null,"date":"2022-11-29T00:10:15","name":"ld: Parse LF_UDT_SRC_LINE records when creating PDB file","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221129001015.21775-3-mark@harmstone.com/mbox/"},{"id":26994,"url":"https://patchwork.plctlab.org/api/1.2/patches/26994/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/daddde128db2f014de16a7cf8a229aed53074b02.1669684562.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-11-29T01:16:56","name":"[REVIEW,ONLY,1/1] UNRATIFIED RISC-V: Add '\''ZiCondOps'\'' extension","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/daddde128db2f014de16a7cf8a229aed53074b02.1669684562.git.research_trasio@irq.a4lg.com/mbox/"},{"id":26995,"url":"https://patchwork.plctlab.org/api/1.2/patches/26995/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/29f89ef04335561879d14d9cdb8e1e9a550bc811.1669684692.git.research_trasio@irq.a4lg.com/","msgid":"<29f89ef04335561879d14d9cdb8e1e9a550bc811.1669684692.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-29T01:18:15","name":"[REVIEW,ONLY,1/1] UNRATIFIED RISC-V: Add '\''Svadu'\'' extension","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/29f89ef04335561879d14d9cdb8e1e9a550bc811.1669684692.git.research_trasio@irq.a4lg.com/mbox/"},{"id":26996,"url":"https://patchwork.plctlab.org/api/1.2/patches/26996/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d32f305c187892c2a97fef6eebca220c90eac3b7.1669684774.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-11-29T01:19:53","name":"[REVIEW,ONLY,1/1] UNRATIFIED RISC-V: Add '\''Smclic'\'' extension and its CSRs","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d32f305c187892c2a97fef6eebca220c90eac3b7.1669684774.git.research_trasio@irq.a4lg.com/mbox/"},{"id":26997,"url":"https://patchwork.plctlab.org/api/1.2/patches/26997/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/54d777ce6e71c02b8b0f9426367e98d0f927ce40.1669684854.git.research_trasio@irq.a4lg.com/","msgid":"<54d777ce6e71c02b8b0f9426367e98d0f927ce40.1669684854.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-29T01:20:57","name":"[REVIEW,ONLY,1/2] UNRATIFIED RISC-V: Add '\''Sspmp'\'' extension and its TENTATIVE CSRs","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/54d777ce6e71c02b8b0f9426367e98d0f927ce40.1669684854.git.research_trasio@irq.a4lg.com/mbox/"},{"id":26998,"url":"https://patchwork.plctlab.org/api/1.2/patches/26998/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ee7c7490f10af1e9cc9c9475814e4d8a9b1a9304.1669684854.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-11-29T01:20:58","name":"[REVIEW,ONLY,2/2] TEST: Add instantiation script on CSR allocation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ee7c7490f10af1e9cc9c9475814e4d8a9b1a9304.1669684854.git.research_trasio@irq.a4lg.com/mbox/"},{"id":27004,"url":"https://patchwork.plctlab.org/api/1.2/patches/27004/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/03cbfeb6934c7bf653cbdfbafcc6ee5ce3cb519c.1669684907.git.research_trasio@irq.a4lg.com/","msgid":"<03cbfeb6934c7bf653cbdfbafcc6ee5ce3cb519c.1669684907.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-29T01:21:51","name":"[REVIEW,ONLY,1/1] UNRATIFIED RISC-V: Add '\''Smrnmi'\'' extension and its CSRs","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/03cbfeb6934c7bf653cbdfbafcc6ee5ce3cb519c.1669684907.git.research_trasio@irq.a4lg.com/mbox/"},{"id":27013,"url":"https://patchwork.plctlab.org/api/1.2/patches/27013/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0187562c00ee6c8ba82439bd61e46a1899b9f916.1669684988.git.research_trasio@irq.a4lg.com/","msgid":"<0187562c00ee6c8ba82439bd61e46a1899b9f916.1669684988.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-29T01:23:57","name":"[REVIEW,ONLY,1/3] RISC-V: Add \"XUN@S\" operand type","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0187562c00ee6c8ba82439bd61e46a1899b9f916.1669684988.git.research_trasio@irq.a4lg.com/mbox/"},{"id":27017,"url":"https://patchwork.plctlab.org/api/1.2/patches/27017/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/cae340b249629f0b05b527ae8aec3023b159b487.1669684988.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-11-29T01:23:58","name":"[REVIEW,ONLY,2/3] UNRATIFIED RISC-V: Add '\''Zisslpcfi'\'' extension and its TENTATIVE CSRs","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/cae340b249629f0b05b527ae8aec3023b159b487.1669684988.git.research_trasio@irq.a4lg.com/mbox/"},{"id":27018,"url":"https://patchwork.plctlab.org/api/1.2/patches/27018/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/73828cb4ccf8c03275b6af7e42872d661dea267f.1669684988.git.research_trasio@irq.a4lg.com/","msgid":"<73828cb4ccf8c03275b6af7e42872d661dea267f.1669684988.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-11-29T01:23:59","name":"[REVIEW,ONLY,3/3] TEST: Add instantiation script on CSR allocation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/73828cb4ccf8c03275b6af7e42872d661dea267f.1669684988.git.research_trasio@irq.a4lg.com/mbox/"},{"id":27030,"url":"https://patchwork.plctlab.org/api/1.2/patches/27030/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d6ee991833120682dc021b0269f5535c9ac3a806.1669687611.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-11-29T02:06:57","name":"[REVIEW,ONLY,v2,1/1] UNRATIFIED RISC-V: Add '\''ZiCondOps'\'' extension","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d6ee991833120682dc021b0269f5535c9ac3a806.1669687611.git.research_trasio@irq.a4lg.com/mbox/"},{"id":27035,"url":"https://patchwork.plctlab.org/api/1.2/patches/27035/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221129022520.2218851-1-jcmvbkbc@gmail.com/","msgid":"<20221129022520.2218851-1-jcmvbkbc@gmail.com>","list_archive_url":null,"date":"2022-11-29T02:25:20","name":"[COMMITTED] xtensa: allow dynamic configuration","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221129022520.2218851-1-jcmvbkbc@gmail.com/mbox/"},{"id":27161,"url":"https://patchwork.plctlab.org/api/1.2/patches/27161/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/01b77f18-8af3-4128-3645-2f1e05690197@suse.com/","msgid":"<01b77f18-8af3-4128-3645-2f1e05690197@suse.com>","list_archive_url":null,"date":"2022-11-29T10:36:21","name":"[1/5] gas: avoid inserting extra newline in buffer_and_nest()","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/01b77f18-8af3-4128-3645-2f1e05690197@suse.com/mbox/"},{"id":27163,"url":"https://patchwork.plctlab.org/api/1.2/patches/27163/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2ae84a68-29f3-d94d-1a12-c3d0c81f81a3@suse.com/","msgid":"<2ae84a68-29f3-d94d-1a12-c3d0c81f81a3@suse.com>","list_archive_url":null,"date":"2022-11-29T10:36:59","name":"[2/5] gas: squash (some) .linefile from listings","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2ae84a68-29f3-d94d-1a12-c3d0c81f81a3@suse.com/mbox/"},{"id":27164,"url":"https://patchwork.plctlab.org/api/1.2/patches/27164/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8b41d62d-8345-a2bd-ce90-27d79aefe2eb@suse.com/","msgid":"<8b41d62d-8345-a2bd-ce90-27d79aefe2eb@suse.com>","list_archive_url":null,"date":"2022-11-29T10:37:42","name":"[3/5] gas: add Dwarf line number test for .macro expansions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8b41d62d-8345-a2bd-ce90-27d79aefe2eb@suse.com/mbox/"},{"id":27165,"url":"https://patchwork.plctlab.org/api/1.2/patches/27165/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ca933e73-103d-0e9c-84b7-f0a1650dfa2f@suse.com/","msgid":"","list_archive_url":null,"date":"2022-11-29T10:38:52","name":"[4/5] Arm: avoid unhelpful use of .macro in testsuite","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ca933e73-103d-0e9c-84b7-f0a1650dfa2f@suse.com/mbox/"},{"id":27167,"url":"https://patchwork.plctlab.org/api/1.2/patches/27167/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1c75f3b4-14ac-fa39-fac8-2c98b4c4dbab@suse.com/","msgid":"<1c75f3b4-14ac-fa39-fac8-2c98b4c4dbab@suse.com>","list_archive_url":null,"date":"2022-11-29T10:44:51","name":"[5/5] gas: re-work line number tracking for macros and their expansions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1c75f3b4-14ac-fa39-fac8-2c98b4c4dbab@suse.com/mbox/"},{"id":27626,"url":"https://patchwork.plctlab.org/api/1.2/patches/27626/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y4cPz0nw9PS+slTj@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-11-30T08:09:51","name":"regen SRC-POTFILES.in","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y4cPz0nw9PS+slTj@squeak.grove.modra.org/mbox/"},{"id":27629,"url":"https://patchwork.plctlab.org/api/1.2/patches/27629/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y4cQAk+8VjJUNcAS@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-11-30T08:10:42","name":"Correct ordering problem in comm-data.exp","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y4cQAk+8VjJUNcAS@squeak.grove.modra.org/mbox/"},{"id":27689,"url":"https://patchwork.plctlab.org/api/1.2/patches/27689/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3d8c5353-723d-31ec-8efa-ee4fc994eaec@suse.com/","msgid":"<3d8c5353-723d-31ec-8efa-ee4fc994eaec@suse.com>","list_archive_url":null,"date":"2022-11-30T08:54:43","name":"[1/4] x86/Intel: restrict use of LONG_DOUBLE_MNEM_SUFFIX","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3d8c5353-723d-31ec-8efa-ee4fc994eaec@suse.com/mbox/"},{"id":27690,"url":"https://patchwork.plctlab.org/api/1.2/patches/27690/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/934cece1-77ed-b4ee-a61d-451d71680a9e@suse.com/","msgid":"<934cece1-77ed-b4ee-a61d-451d71680a9e@suse.com>","list_archive_url":null,"date":"2022-11-30T08:55:11","name":"[2/4] x86/Intel: drop LONG_DOUBLE_MNEM_SUFFIX","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/934cece1-77ed-b4ee-a61d-451d71680a9e@suse.com/mbox/"},{"id":27691,"url":"https://patchwork.plctlab.org/api/1.2/patches/27691/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f0d0c80a-1b30-6e13-ceff-d3a1061db2ea@suse.com/","msgid":"","list_archive_url":null,"date":"2022-11-30T08:55:43","name":"[3/4] x86: drop No_ldSuf","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f0d0c80a-1b30-6e13-ceff-d3a1061db2ea@suse.com/mbox/"},{"id":27692,"url":"https://patchwork.plctlab.org/api/1.2/patches/27692/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/787c0eff-5b73-ed04-6e06-e3f49d5a3ce1@suse.com/","msgid":"<787c0eff-5b73-ed04-6e06-e3f49d5a3ce1@suse.com>","list_archive_url":null,"date":"2022-11-30T08:56:52","name":"[4/4] x86: rework of match_template()'\''s suffix checking","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/787c0eff-5b73-ed04-6e06-e3f49d5a3ce1@suse.com/mbox/"}],"public":true,"mbox":"https://patchwork.plctlab.org/bundle/patchwork-bot/binutils-gdb_2022-11/mbox/"},{"id":12,"url":"https://patchwork.plctlab.org/api/1.2/bundles/12/","web_url":"https://patchwork.plctlab.org/bundle/patchwork-bot/binutils-gdb_2022-12/","project":{"id":2,"url":"https://patchwork.plctlab.org/api/1.2/projects/2/","name":"binutils-gdb","link_name":"binutils-gdb","list_id":"binutils.sourceware.org","list_email":"binutils@sourceware.org","web_url":"https://github.com/wangliu-iscas/Patchwork-Bundles/blob/main/binutils-gdb.md","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"name":"binutils-gdb_2022-12","owner":{"id":3,"url":"https://patchwork.plctlab.org/api/1.2/users/3/","username":"patchwork-bot","first_name":"","last_name":"","email":"ouuuleilei@gmail.com"},"patches":[{"id":28023,"url":"https://patchwork.plctlab.org/api/1.2/patches/28023/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221130214802.32340-1-hjl.tools@gmail.com/","msgid":"<20221130214802.32340-1-hjl.tools@gmail.com>","list_archive_url":null,"date":"2022-11-30T21:48:02","name":"opcodes: Remove i386-init.h and i386-tbl.h from HFILES","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221130214802.32340-1-hjl.tools@gmail.com/mbox/"},{"id":28172,"url":"https://patchwork.plctlab.org/api/1.2/patches/28172/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f6ef4412c1f0d5a7b0292f443ea5aee31c25056d.1669864784.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-12-01T03:20:31","name":"[REVIEW,ONLY,v3,1/1] UNRATIFIED RISC-V: Add '\''ZiCond'\'' extension","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f6ef4412c1f0d5a7b0292f443ea5aee31c25056d.1669864784.git.research_trasio@irq.a4lg.com/mbox/"},{"id":28257,"url":"https://patchwork.plctlab.org/api/1.2/patches/28257/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/673753a0-ab7b-6c44-844e-3addfcf01693@suse.com/","msgid":"<673753a0-ab7b-6c44-844e-3addfcf01693@suse.com>","list_archive_url":null,"date":"2022-12-01T09:09:26","name":"x86: also use D for XCHG and TEST","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/673753a0-ab7b-6c44-844e-3addfcf01693@suse.com/mbox/"},{"id":28258,"url":"https://patchwork.plctlab.org/api/1.2/patches/28258/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/35539292-53a8-292d-2f5d-f65ad02a36bb@suse.com/","msgid":"<35539292-53a8-292d-2f5d-f65ad02a36bb@suse.com>","list_archive_url":null,"date":"2022-12-01T09:11:50","name":"x86: simplify and slightly correct XCHG vs NOP checking","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/35539292-53a8-292d-2f5d-f65ad02a36bb@suse.com/mbox/"},{"id":28260,"url":"https://patchwork.plctlab.org/api/1.2/patches/28260/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b56e7b03-c15b-a932-bd6b-e026d9ae8675@suse.com/","msgid":"","list_archive_url":null,"date":"2022-12-01T09:20:24","name":"x86: drop most OPERAND_TYPE_* (and rework the rest)","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b56e7b03-c15b-a932-bd6b-e026d9ae8675@suse.com/mbox/"},{"id":28274,"url":"https://patchwork.plctlab.org/api/1.2/patches/28274/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221201094409.1982624-1-chigot@adacore.com/","msgid":"<20221201094409.1982624-1-chigot@adacore.com>","list_archive_url":null,"date":"2022-12-01T09:44:09","name":"binutils: improve holes detection in .debug_loclists.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221201094409.1982624-1-chigot@adacore.com/mbox/"},{"id":28448,"url":"https://patchwork.plctlab.org/api/1.2/patches/28448/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221201162038.421271-1-hjl.tools@gmail.com/","msgid":"<20221201162038.421271-1-hjl.tools@gmail.com>","list_archive_url":null,"date":"2022-12-01T16:20:38","name":"opcodes: Make i386-init.h depend on i386-tbl.h","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221201162038.421271-1-hjl.tools@gmail.com/mbox/"},{"id":28503,"url":"https://patchwork.plctlab.org/api/1.2/patches/28503/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y4jx62oUPn2PB3tC@gmail.com/","msgid":"","list_archive_url":null,"date":"2022-12-01T18:26:51","name":"[v3] x86: Remove libopcodes dependency","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y4jx62oUPn2PB3tC@gmail.com/mbox/"},{"id":28837,"url":"https://patchwork.plctlab.org/api/1.2/patches/28837/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/87mt8615k1.fsf@redhat.com/","msgid":"<87mt8615k1.fsf@redhat.com>","list_archive_url":null,"date":"2022-12-02T10:08:30","name":"Adding Jan Beulich as an x86_64 maintainer","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/87mt8615k1.fsf@redhat.com/mbox/"},{"id":28852,"url":"https://patchwork.plctlab.org/api/1.2/patches/28852/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8bfb1c56-8207-fe92-87ae-1b7ef26b3544@suse.com/","msgid":"<8bfb1c56-8207-fe92-87ae-1b7ef26b3544@suse.com>","list_archive_url":null,"date":"2022-12-02T10:18:00","name":"[v7,1/7] x86: constify parse_insn()'\''s input","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8bfb1c56-8207-fe92-87ae-1b7ef26b3544@suse.com/mbox/"},{"id":28855,"url":"https://patchwork.plctlab.org/api/1.2/patches/28855/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6043f9b3-1ea1-ea4a-59ae-dcccf129c241@suse.com/","msgid":"<6043f9b3-1ea1-ea4a-59ae-dcccf129c241@suse.com>","list_archive_url":null,"date":"2022-12-02T10:18:54","name":"[v7,2/7] x86: re-work insn/suffix recognition","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6043f9b3-1ea1-ea4a-59ae-dcccf129c241@suse.com/mbox/"},{"id":28856,"url":"https://patchwork.plctlab.org/api/1.2/patches/28856/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f7f77244-9782-0bc1-365c-e73d72045f36@suse.com/","msgid":"","list_archive_url":null,"date":"2022-12-02T10:19:32","name":"[v7,3/7] ix86: don'\''t recognize/derive Q suffix in the common case","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f7f77244-9782-0bc1-365c-e73d72045f36@suse.com/mbox/"},{"id":28857,"url":"https://patchwork.plctlab.org/api/1.2/patches/28857/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/77fa4300-e192-5b9d-d699-37255054d391@suse.com/","msgid":"<77fa4300-e192-5b9d-d699-37255054d391@suse.com>","list_archive_url":null,"date":"2022-12-02T10:20:06","name":"[v7,4/7] x86-64: allow HLE store of accumulator to absolute 32-bit address","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/77fa4300-e192-5b9d-d699-37255054d391@suse.com/mbox/"},{"id":28860,"url":"https://patchwork.plctlab.org/api/1.2/patches/28860/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b4c2d623-517c-f5e8-90d9-01e933a68a00@suse.com/","msgid":"","list_archive_url":null,"date":"2022-12-02T10:20:34","name":"[v7,5/7] x86: move bad-use-of-TLS-reloc check","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b4c2d623-517c-f5e8-90d9-01e933a68a00@suse.com/mbox/"},{"id":28859,"url":"https://patchwork.plctlab.org/api/1.2/patches/28859/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ac7e5911-4c5e-27c3-b0e5-cd3dcfa67155@suse.com/","msgid":"","list_archive_url":null,"date":"2022-12-02T10:21:02","name":"[v7,6/7] x86: drop (now) stray IsString","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ac7e5911-4c5e-27c3-b0e5-cd3dcfa67155@suse.com/mbox/"},{"id":28861,"url":"https://patchwork.plctlab.org/api/1.2/patches/28861/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/46702842-5bc7-113e-bab8-d67304f0f337@suse.com/","msgid":"<46702842-5bc7-113e-bab8-d67304f0f337@suse.com>","list_archive_url":null,"date":"2022-12-02T10:21:46","name":"[v7,7/7] x86: further re-work insn/suffix recognition to also cover MOVSX","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/46702842-5bc7-113e-bab8-d67304f0f337@suse.com/mbox/"},{"id":29215,"url":"https://patchwork.plctlab.org/api/1.2/patches/29215/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221203041307.34407-1-hjl.tools@gmail.com/","msgid":"<20221203041307.34407-1-hjl.tools@gmail.com>","list_archive_url":null,"date":"2022-12-03T04:13:07","name":"x86: Allow 16-bit register source for LAR and LSL","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221203041307.34407-1-hjl.tools@gmail.com/mbox/"},{"id":29241,"url":"https://patchwork.plctlab.org/api/1.2/patches/29241/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221203073435.1451856-1-mengqinggang@loongson.cn/","msgid":"<20221203073435.1451856-1-mengqinggang@loongson.cn>","list_archive_url":null,"date":"2022-12-03T07:34:35","name":"LoongArch: Fix dynamic reloc not generated bug in some cases.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221203073435.1451856-1-mengqinggang@loongson.cn/mbox/"},{"id":29297,"url":"https://patchwork.plctlab.org/api/1.2/patches/29297/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221203174330.682680-1-hjl.tools@gmail.com/","msgid":"<20221203174330.682680-1-hjl.tools@gmail.com>","list_archive_url":null,"date":"2022-12-03T17:43:30","name":"ld: Add .note.GNU-stack to ld-plugin/dummy.s","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221203174330.682680-1-hjl.tools@gmail.com/mbox/"},{"id":29299,"url":"https://patchwork.plctlab.org/api/1.2/patches/29299/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221203184408.866763-1-hjl.tools@gmail.com/","msgid":"<20221203184408.866763-1-hjl.tools@gmail.com>","list_archive_url":null,"date":"2022-12-03T18:44:08","name":"Revert \"ld: Add .note.GNU-stack to ld-plugin/dummy.s\"","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221203184408.866763-1-hjl.tools@gmail.com/mbox/"},{"id":29461,"url":"https://patchwork.plctlab.org/api/1.2/patches/29461/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y40WXnjN0f0LjrIt@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-12-04T21:51:26","name":"Renaming .debug to .zdebug and vice versa","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y40WXnjN0f0LjrIt@squeak.grove.modra.org/mbox/"},{"id":29462,"url":"https://patchwork.plctlab.org/api/1.2/patches/29462/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y40WfJl0V9ifv+fN@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-12-04T21:51:56","name":"COFF compressed debug support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y40WfJl0V9ifv+fN@squeak.grove.modra.org/mbox/"},{"id":29463,"url":"https://patchwork.plctlab.org/api/1.2/patches/29463/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y40WrrfotDOwKqZb@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-12-04T21:52:46","name":"PR29846, segmentation fault in objdump.c compare_symbols","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y40WrrfotDOwKqZb@squeak.grove.modra.org/mbox/"},{"id":29492,"url":"https://patchwork.plctlab.org/api/1.2/patches/29492/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221205015347.25781-1-mark@harmstone.com/","msgid":"<20221205015347.25781-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-12-05T01:53:45","name":"ld: Write globals stream in PDB","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221205015347.25781-1-mark@harmstone.com/mbox/"},{"id":29491,"url":"https://patchwork.plctlab.org/api/1.2/patches/29491/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221205015347.25781-2-mark@harmstone.com/","msgid":"<20221205015347.25781-2-mark@harmstone.com>","list_archive_url":null,"date":"2022-12-05T01:53:46","name":"ld: Copy other symbols into PDB file","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221205015347.25781-2-mark@harmstone.com/mbox/"},{"id":29490,"url":"https://patchwork.plctlab.org/api/1.2/patches/29490/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221205015347.25781-3-mark@harmstone.com/","msgid":"<20221205015347.25781-3-mark@harmstone.com>","list_archive_url":null,"date":"2022-12-05T01:53:47","name":"ld: Write linker symbols in PDB","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221205015347.25781-3-mark@harmstone.com/mbox/"},{"id":29502,"url":"https://patchwork.plctlab.org/api/1.2/patches/29502/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221205025311.73743-1-haochen.jiang@intel.com/","msgid":"<20221205025311.73743-1-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-12-05T02:53:11","name":"x86: Remove unnecessary vex.w check for xh_mode in disassembler","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221205025311.73743-1-haochen.jiang@intel.com/mbox/"},{"id":29578,"url":"https://patchwork.plctlab.org/api/1.2/patches/29578/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221205080453.1352069-2-mengqinggang@loongson.cn/","msgid":"<20221205080453.1352069-2-mengqinggang@loongson.cn>","list_archive_url":null,"date":"2022-12-05T08:04:48","name":"[v1,1/6] LoongArch: include: Add support for linker relaxation.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221205080453.1352069-2-mengqinggang@loongson.cn/mbox/"},{"id":29585,"url":"https://patchwork.plctlab.org/api/1.2/patches/29585/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221205080453.1352069-3-mengqinggang@loongson.cn/","msgid":"<20221205080453.1352069-3-mengqinggang@loongson.cn>","list_archive_url":null,"date":"2022-12-05T08:04:49","name":"[v1,2/6] LoongArch: bfd: Add support for linker relaxation.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221205080453.1352069-3-mengqinggang@loongson.cn/mbox/"},{"id":29577,"url":"https://patchwork.plctlab.org/api/1.2/patches/29577/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221205080453.1352069-4-mengqinggang@loongson.cn/","msgid":"<20221205080453.1352069-4-mengqinggang@loongson.cn>","list_archive_url":null,"date":"2022-12-05T08:04:50","name":"[v1,3/6] LoongArch: opcodes: Add support for linker relaxation.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221205080453.1352069-4-mengqinggang@loongson.cn/mbox/"},{"id":29580,"url":"https://patchwork.plctlab.org/api/1.2/patches/29580/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221205080453.1352069-5-mengqinggang@loongson.cn/","msgid":"<20221205080453.1352069-5-mengqinggang@loongson.cn>","list_archive_url":null,"date":"2022-12-05T08:04:51","name":"[v1,4/6] LoongArch: binutils: Add support for linker relaxation.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221205080453.1352069-5-mengqinggang@loongson.cn/mbox/"},{"id":29581,"url":"https://patchwork.plctlab.org/api/1.2/patches/29581/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221205080453.1352069-6-mengqinggang@loongson.cn/","msgid":"<20221205080453.1352069-6-mengqinggang@loongson.cn>","list_archive_url":null,"date":"2022-12-05T08:04:52","name":"[v1,5/6] LoongArch: gas: Add support for linker relaxation.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221205080453.1352069-6-mengqinggang@loongson.cn/mbox/"},{"id":29587,"url":"https://patchwork.plctlab.org/api/1.2/patches/29587/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221205080453.1352069-7-mengqinggang@loongson.cn/","msgid":"<20221205080453.1352069-7-mengqinggang@loongson.cn>","list_archive_url":null,"date":"2022-12-05T08:04:53","name":"[v1,6/6] LoongArch: ld: Add support for linker relaxation.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221205080453.1352069-7-mengqinggang@loongson.cn/mbox/"},{"id":29662,"url":"https://patchwork.plctlab.org/api/1.2/patches/29662/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/76253e84-a7c3-5d09-c6a7-422573ca2d37@suse.cz/","msgid":"<76253e84-a7c3-5d09-c6a7-422573ca2d37@suse.cz>","list_archive_url":null,"date":"2022-12-05T12:10:10","name":"testsuite: support mold linker","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/76253e84-a7c3-5d09-c6a7-422573ca2d37@suse.cz/mbox/"},{"id":29689,"url":"https://patchwork.plctlab.org/api/1.2/patches/29689/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e41a37eb-20ae-b5ef-9ab3-6e38682bfbd3@suse.cz/","msgid":"","list_archive_url":null,"date":"2022-12-05T13:48:16","name":"[V2] testsuite: support mold linker","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e41a37eb-20ae-b5ef-9ab3-6e38682bfbd3@suse.cz/mbox/"},{"id":29700,"url":"https://patchwork.plctlab.org/api/1.2/patches/29700/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2eb01f7a-2430-b0bc-9c58-d15d06ca6bf9@suse.cz/","msgid":"<2eb01f7a-2430-b0bc-9c58-d15d06ca6bf9@suse.cz>","list_archive_url":null,"date":"2022-12-05T14:41:04","name":"[V3] testsuite: support mold linker","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2eb01f7a-2430-b0bc-9c58-d15d06ca6bf9@suse.cz/mbox/"},{"id":30027,"url":"https://patchwork.plctlab.org/api/1.2/patches/30027/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y46GBCcdb5NKqOgS@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-12-06T00:00:04","name":"PR29855, ch_type in bfd_init_section_decompress_status can be uninitialized","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y46GBCcdb5NKqOgS@squeak.grove.modra.org/mbox/"},{"id":30082,"url":"https://patchwork.plctlab.org/api/1.2/patches/30082/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y47NCokv10HcVEpf@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-12-06T05:03:06","name":"Compression header enum","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y47NCokv10HcVEpf@squeak.grove.modra.org/mbox/"},{"id":30083,"url":"https://patchwork.plctlab.org/api/1.2/patches/30083/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y47NPN4wWWRZyL00@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-12-06T05:03:56","name":"Get rid of SEC_ELF_RENAME","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y47NPN4wWWRZyL00@squeak.grove.modra.org/mbox/"},{"id":30084,"url":"https://patchwork.plctlab.org/api/1.2/patches/30084/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y47NWJ/QfmCo4NNo@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-12-06T05:04:24","name":"Get rid of SEC_ELF_COMPRESS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y47NWJ/QfmCo4NNo@squeak.grove.modra.org/mbox/"},{"id":30085,"url":"https://patchwork.plctlab.org/api/1.2/patches/30085/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221206053947.821648-1-zengxiao@eswincomputing.com/","msgid":"<20221206053947.821648-1-zengxiao@eswincomputing.com>","list_archive_url":null,"date":"2022-12-06T05:39:47","name":"RISC-V: Correction of machine registers mapping to dwarf registers","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221206053947.821648-1-zengxiao@eswincomputing.com/mbox/"},{"id":30511,"url":"https://patchwork.plctlab.org/api/1.2/patches/30511/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221206211044.766653-1-hjl.tools@gmail.com/","msgid":"<20221206211044.766653-1-hjl.tools@gmail.com>","list_archive_url":null,"date":"2022-12-06T21:10:44","name":"x86-64: Remove BND from 64-bit IBT PLT","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221206211044.766653-1-hjl.tools@gmail.com/mbox/"},{"id":30519,"url":"https://patchwork.plctlab.org/api/1.2/patches/30519/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221206214444.799449-1-hjl.tools@gmail.com/","msgid":"<20221206214444.799449-1-hjl.tools@gmail.com>","list_archive_url":null,"date":"2022-12-06T21:44:44","name":"gold: Remove BND from 64-bit x86-64 IBT PLT","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221206214444.799449-1-hjl.tools@gmail.com/mbox/"},{"id":30606,"url":"https://patchwork.plctlab.org/api/1.2/patches/30606/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y4/+I/FAq0yyNLGs@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-12-07T02:44:51","name":"Compression tidy and fixes","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y4/+I/FAq0yyNLGs@squeak.grove.modra.org/mbox/"},{"id":30613,"url":"https://patchwork.plctlab.org/api/1.2/patches/30613/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y5ANBOjjh0d9TEW4@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-12-07T03:48:20","name":"bfd_compress_section_contents access to elf_section_data","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y5ANBOjjh0d9TEW4@squeak.grove.modra.org/mbox/"},{"id":30615,"url":"https://patchwork.plctlab.org/api/1.2/patches/30615/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y5AOFp9g+oujWvPw@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-12-07T03:52:54","name":"_bfd_elf_slurp_secondary_reloc_section sanity check","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y5AOFp9g+oujWvPw@squeak.grove.modra.org/mbox/"},{"id":30641,"url":"https://patchwork.plctlab.org/api/1.2/patches/30641/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y5ArCeLOXPteRDFk@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-12-07T05:56:25","name":"gas compress_debug tidy","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y5ArCeLOXPteRDFk@squeak.grove.modra.org/mbox/"},{"id":30643,"url":"https://patchwork.plctlab.org/api/1.2/patches/30643/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y5ArREIxkCA2Eoqb@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-12-07T05:57:24","name":"coff make_a_section_from_file tidy","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y5ArREIxkCA2Eoqb@squeak.grove.modra.org/mbox/"},{"id":30845,"url":"https://patchwork.plctlab.org/api/1.2/patches/30845/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221207133155.3052074-2-i.swmail@xen0n.name/","msgid":"<20221207133155.3052074-2-i.swmail@xen0n.name>","list_archive_url":null,"date":"2022-12-07T13:31:51","name":"[v2,1/5] opcodes/loongarch: remove unused code","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221207133155.3052074-2-i.swmail@xen0n.name/mbox/"},{"id":30847,"url":"https://patchwork.plctlab.org/api/1.2/patches/30847/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221207133155.3052074-3-i.swmail@xen0n.name/","msgid":"<20221207133155.3052074-3-i.swmail@xen0n.name>","list_archive_url":null,"date":"2022-12-07T13:31:52","name":"[v2,2/5] opcodes/loongarch: implement style support in the disassembler","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221207133155.3052074-3-i.swmail@xen0n.name/mbox/"},{"id":30848,"url":"https://patchwork.plctlab.org/api/1.2/patches/30848/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221207133155.3052074-4-i.swmail@xen0n.name/","msgid":"<20221207133155.3052074-4-i.swmail@xen0n.name>","list_archive_url":null,"date":"2022-12-07T13:31:53","name":"[v2,3/5] opcodes/loongarch: style disassembled address offsets as such","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221207133155.3052074-4-i.swmail@xen0n.name/mbox/"},{"id":30849,"url":"https://patchwork.plctlab.org/api/1.2/patches/30849/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221207133155.3052074-5-i.swmail@xen0n.name/","msgid":"<20221207133155.3052074-5-i.swmail@xen0n.name>","list_archive_url":null,"date":"2022-12-07T13:31:54","name":"[v2,4/5] opcodes/loongarch: do not print hex notation for signed immediates","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221207133155.3052074-5-i.swmail@xen0n.name/mbox/"},{"id":30846,"url":"https://patchwork.plctlab.org/api/1.2/patches/30846/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221207133155.3052074-6-i.swmail@xen0n.name/","msgid":"<20221207133155.3052074-6-i.swmail@xen0n.name>","list_archive_url":null,"date":"2022-12-07T13:31:55","name":"[v2,5/5] opcodes/loongarch: print unrecognized instruction words with .insn prefix","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221207133155.3052074-6-i.swmail@xen0n.name/mbox/"},{"id":30875,"url":"https://patchwork.plctlab.org/api/1.2/patches/30875/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221207141137.1527113-1-felix.willgerodt@intel.com/","msgid":"<20221207141137.1527113-1-felix.willgerodt@intel.com>","list_archive_url":null,"date":"2022-12-07T14:11:37","name":"[1/1] libctf: Fix double free in ctf_link_add_cu_mapping.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221207141137.1527113-1-felix.willgerodt@intel.com/mbox/"},{"id":30967,"url":"https://patchwork.plctlab.org/api/1.2/patches/30967/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9e57c8dc-481b-82d3-7bba-8e7bd9426a1f@linux.ibm.com/","msgid":"<9e57c8dc-481b-82d3-7bba-8e7bd9426a1f@linux.ibm.com>","list_archive_url":null,"date":"2022-12-07T17:59:19","name":"[COMMITTED] PowerPC: Add support for RFC02656 - Enhanced Load Store, with Length Instructions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9e57c8dc-481b-82d3-7bba-8e7bd9426a1f@linux.ibm.com/mbox/"},{"id":30973,"url":"https://patchwork.plctlab.org/api/1.2/patches/30973/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a1b16cc6-6e73-7d5f-ff38-564b0978243b@linux.ibm.com/","msgid":"","list_archive_url":null,"date":"2022-12-07T18:08:00","name":"[COMMITTED] PowerPC: Add support for RFC02655 - Saturating Subtract Instruction","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a1b16cc6-6e73-7d5f-ff38-564b0978243b@linux.ibm.com/mbox/"},{"id":31010,"url":"https://patchwork.plctlab.org/api/1.2/patches/31010/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221207195222.1182788-2-indu.bhagat@oracle.com/","msgid":"<20221207195222.1182788-2-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-12-07T19:52:17","name":"[1/6] libsframe: minor formatting nits","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221207195222.1182788-2-indu.bhagat@oracle.com/mbox/"},{"id":31011,"url":"https://patchwork.plctlab.org/api/1.2/patches/31011/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221207195222.1182788-3-indu.bhagat@oracle.com/","msgid":"<20221207195222.1182788-3-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-12-07T19:52:18","name":"[2/6] sframe.h: make some macros more precise","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221207195222.1182788-3-indu.bhagat@oracle.com/mbox/"},{"id":31013,"url":"https://patchwork.plctlab.org/api/1.2/patches/31013/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221207195222.1182788-4-indu.bhagat@oracle.com/","msgid":"<20221207195222.1182788-4-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-12-07T19:52:19","name":"[3/6] sframe: gas: libsframe: define constants and remove magic numbers","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221207195222.1182788-4-indu.bhagat@oracle.com/mbox/"},{"id":31012,"url":"https://patchwork.plctlab.org/api/1.2/patches/31012/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221207195222.1182788-5-indu.bhagat@oracle.com/","msgid":"<20221207195222.1182788-5-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-12-07T19:52:20","name":"[4/6] gas: sframe: fine tune the fragment fixup for SFrame func info","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221207195222.1182788-5-indu.bhagat@oracle.com/mbox/"},{"id":31014,"url":"https://patchwork.plctlab.org/api/1.2/patches/31014/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221207195222.1182788-6-indu.bhagat@oracle.com/","msgid":"<20221207195222.1182788-6-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-12-07T19:52:21","name":"[5/6] libsframe: rename API sframe_fde_func_info to sframe_fde_create_func_info","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221207195222.1182788-6-indu.bhagat@oracle.com/mbox/"},{"id":31015,"url":"https://patchwork.plctlab.org/api/1.2/patches/31015/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221207195222.1182788-7-indu.bhagat@oracle.com/","msgid":"<20221207195222.1182788-7-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-12-07T19:52:22","name":"[6/6] objdump: sframe: fix memory leaks","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221207195222.1182788-7-indu.bhagat@oracle.com/mbox/"},{"id":31198,"url":"https://patchwork.plctlab.org/api/1.2/patches/31198/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/aa0c1392-c3e1-53c4-45ce-4cee9af3b243@suse.cz/","msgid":"","list_archive_url":null,"date":"2022-12-08T08:21:54","name":"ld, gold: remove support for -z bndplt (MPX prefix)","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/aa0c1392-c3e1-53c4-45ce-4cee9af3b243@suse.cz/mbox/"},{"id":31490,"url":"https://patchwork.plctlab.org/api/1.2/patches/31490/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221208202649.2852852-1-indu.bhagat@oracle.com/","msgid":"<20221208202649.2852852-1-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-12-08T20:26:49","name":"[V2,2/6] sframe.h: make some macros more precise","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221208202649.2852852-1-indu.bhagat@oracle.com/mbox/"},{"id":31571,"url":"https://patchwork.plctlab.org/api/1.2/patches/31571/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221209015240.6348-1-mark@harmstone.com/","msgid":"<20221209015240.6348-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-12-09T01:52:31","name":"[01/10] ld: Generate PDB string table","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221209015240.6348-1-mark@harmstone.com/mbox/"},{"id":31572,"url":"https://patchwork.plctlab.org/api/1.2/patches/31572/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221209015240.6348-2-mark@harmstone.com/","msgid":"<20221209015240.6348-2-mark@harmstone.com>","list_archive_url":null,"date":"2022-12-09T01:52:32","name":"[02/10] ld: Write DEBUG_S_FILECHKSMS entries in PDBs","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221209015240.6348-2-mark@harmstone.com/mbox/"},{"id":31570,"url":"https://patchwork.plctlab.org/api/1.2/patches/31570/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221209015240.6348-3-mark@harmstone.com/","msgid":"<20221209015240.6348-3-mark@harmstone.com>","list_archive_url":null,"date":"2022-12-09T01:52:33","name":"[03/10] ld: Fix segfault in populate_publics_stream","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221209015240.6348-3-mark@harmstone.com/mbox/"},{"id":31573,"url":"https://patchwork.plctlab.org/api/1.2/patches/31573/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221209015240.6348-4-mark@harmstone.com/","msgid":"<20221209015240.6348-4-mark@harmstone.com>","list_archive_url":null,"date":"2022-12-09T01:52:34","name":"[04/10] ld: Write DEBUG_S_LINES entries in PDB file","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221209015240.6348-4-mark@harmstone.com/mbox/"},{"id":31584,"url":"https://patchwork.plctlab.org/api/1.2/patches/31584/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221209015240.6348-5-mark@harmstone.com/","msgid":"<20221209015240.6348-5-mark@harmstone.com>","list_archive_url":null,"date":"2022-12-09T01:52:35","name":"[05/10] ld: Write types into TPI stream of PDB","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221209015240.6348-5-mark@harmstone.com/mbox/"},{"id":31580,"url":"https://patchwork.plctlab.org/api/1.2/patches/31580/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221209015240.6348-6-mark@harmstone.com/","msgid":"<20221209015240.6348-6-mark@harmstone.com>","list_archive_url":null,"date":"2022-12-09T01:52:36","name":"[06/10] ld: Write types into IPI stream of PDB","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221209015240.6348-6-mark@harmstone.com/mbox/"},{"id":31579,"url":"https://patchwork.plctlab.org/api/1.2/patches/31579/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221209015240.6348-7-mark@harmstone.com/","msgid":"<20221209015240.6348-7-mark@harmstone.com>","list_archive_url":null,"date":"2022-12-09T01:52:37","name":"[07/10] ld: Parse LF_UDT_SRC_LINE records when creating PDB file","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221209015240.6348-7-mark@harmstone.com/mbox/"},{"id":31591,"url":"https://patchwork.plctlab.org/api/1.2/patches/31591/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221209015240.6348-8-mark@harmstone.com/","msgid":"<20221209015240.6348-8-mark@harmstone.com>","list_archive_url":null,"date":"2022-12-09T01:52:38","name":"[08/10] ld: Write globals stream in PDB","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221209015240.6348-8-mark@harmstone.com/mbox/"},{"id":31582,"url":"https://patchwork.plctlab.org/api/1.2/patches/31582/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221209015240.6348-9-mark@harmstone.com/","msgid":"<20221209015240.6348-9-mark@harmstone.com>","list_archive_url":null,"date":"2022-12-09T01:52:39","name":"[09/10] ld: Copy other symbols into PDB file","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221209015240.6348-9-mark@harmstone.com/mbox/"},{"id":31592,"url":"https://patchwork.plctlab.org/api/1.2/patches/31592/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221209015240.6348-10-mark@harmstone.com/","msgid":"<20221209015240.6348-10-mark@harmstone.com>","list_archive_url":null,"date":"2022-12-09T01:52:40","name":"[10/10] ld: Write linker symbols in PDB","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221209015240.6348-10-mark@harmstone.com/mbox/"},{"id":31705,"url":"https://patchwork.plctlab.org/api/1.2/patches/31705/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221209095719.193008-1-i.swmail@xen0n.name/","msgid":"<20221209095719.193008-1-i.swmail@xen0n.name>","list_archive_url":null,"date":"2022-12-09T09:57:19","name":"LoongArch: support disassembling certain pseudo-instructions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221209095719.193008-1-i.swmail@xen0n.name/mbox/"},{"id":31717,"url":"https://patchwork.plctlab.org/api/1.2/patches/31717/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b291b099-c0f2-e206-4296-1fcf040c32b1@suse.com/","msgid":"","list_archive_url":null,"date":"2022-12-09T10:49:20","name":"[v2,1/2] Arm: avoid unhelpful uses of .macro in testsuite","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b291b099-c0f2-e206-4296-1fcf040c32b1@suse.com/mbox/"},{"id":31720,"url":"https://patchwork.plctlab.org/api/1.2/patches/31720/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8eff1de6-871d-24cc-8804-9af7da0a86cf@suse.com/","msgid":"<8eff1de6-871d-24cc-8804-9af7da0a86cf@suse.com>","list_archive_url":null,"date":"2022-12-09T10:52:06","name":"[v2,2/2] gas: re-work line number tracking for macros and their expansions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8eff1de6-871d-24cc-8804-9af7da0a86cf@suse.com/mbox/"},{"id":31724,"url":"https://patchwork.plctlab.org/api/1.2/patches/31724/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y5MXFFPorfWbzTDZ@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-12-09T11:08:04","name":"PR28306, segfault in _bfd_mips_elf_reloc_unshuffle","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y5MXFFPorfWbzTDZ@squeak.grove.modra.org/mbox/"},{"id":31924,"url":"https://patchwork.plctlab.org/api/1.2/patches/31924/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221209202118.4106688-2-indu.bhagat@oracle.com/","msgid":"<20221209202118.4106688-2-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-12-09T20:21:17","name":"[1/2] libctf: remove unnecessary zlib constructs","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221209202118.4106688-2-indu.bhagat@oracle.com/mbox/"},{"id":31925,"url":"https://patchwork.plctlab.org/api/1.2/patches/31925/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221209202118.4106688-3-indu.bhagat@oracle.com/","msgid":"<20221209202118.4106688-3-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-12-09T20:21:18","name":"[2/2] libctf: remove AC_CONFIG_MACRO_DIR","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221209202118.4106688-3-indu.bhagat@oracle.com/mbox/"},{"id":32115,"url":"https://patchwork.plctlab.org/api/1.2/patches/32115/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221211001022.564137-2-indu.bhagat@oracle.com/","msgid":"<20221211001022.564137-2-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-12-11T00:10:21","name":"[V2,1/2] libctf: remove unnecessary zlib constructs","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221211001022.564137-2-indu.bhagat@oracle.com/mbox/"},{"id":32114,"url":"https://patchwork.plctlab.org/api/1.2/patches/32114/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221211001022.564137-3-indu.bhagat@oracle.com/","msgid":"<20221211001022.564137-3-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-12-11T00:10:22","name":"[V2,2/2] libctf: remove AC_CONFIG_MACRO_DIR","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221211001022.564137-3-indu.bhagat@oracle.com/mbox/"},{"id":32116,"url":"https://patchwork.plctlab.org/api/1.2/patches/32116/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221211002622.564875-1-indu.bhagat@oracle.com/","msgid":"<20221211002622.564875-1-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-12-11T00:26:22","name":"libctf: remove unnecessary zstd constructs","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221211002622.564875-1-indu.bhagat@oracle.com/mbox/"},{"id":32188,"url":"https://patchwork.plctlab.org/api/1.2/patches/32188/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y5XZZileMxvCEgnH@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-12-11T13:21:42","name":"PR29870, objdump SEGV in display_debug_lines_decoded dwarf.c:5524","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y5XZZileMxvCEgnH@squeak.grove.modra.org/mbox/"},{"id":32268,"url":"https://patchwork.plctlab.org/api/1.2/patches/32268/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y5btF1SICJIaR6s4@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-12-12T08:57:59","name":"PR29872, uninitialised value in display_debug_lines_decoded dwarf.c:5413","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y5btF1SICJIaR6s4@squeak.grove.modra.org/mbox/"},{"id":32269,"url":"https://patchwork.plctlab.org/api/1.2/patches/32269/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y5btNpE+vZlCyuFQ@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-12-12T08:58:30","name":"Lack of bounds checking in vms-alpha.c parse_module","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y5btNpE+vZlCyuFQ@squeak.grove.modra.org/mbox/"},{"id":32270,"url":"https://patchwork.plctlab.org/api/1.2/patches/32270/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y5btWGqMk2HBW0DG@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-12-12T08:59:04","name":"PR29892, Field file_table of struct module is uninitialized","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y5btWGqMk2HBW0DG@squeak.grove.modra.org/mbox/"},{"id":32366,"url":"https://patchwork.plctlab.org/api/1.2/patches/32366/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4a972040-5bdf-4c00-47db-7e26e603ff47@suse.com/","msgid":"<4a972040-5bdf-4c00-47db-7e26e603ff47@suse.com>","list_archive_url":null,"date":"2022-12-12T12:42:31","name":"x86: revert disassembler parts of \"x86: Allow 16-bit register source for LAR and LSL\"","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4a972040-5bdf-4c00-47db-7e26e603ff47@suse.com/mbox/"},{"id":32384,"url":"https://patchwork.plctlab.org/api/1.2/patches/32384/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2e6ab22e-9141-7209-5dcd-f10f2e20b0f0@suse.com/","msgid":"<2e6ab22e-9141-7209-5dcd-f10f2e20b0f0@suse.com>","list_archive_url":null,"date":"2022-12-12T13:12:43","name":"[1/2] x86: change representation of extension opcode","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2e6ab22e-9141-7209-5dcd-f10f2e20b0f0@suse.com/mbox/"},{"id":32387,"url":"https://patchwork.plctlab.org/api/1.2/patches/32387/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/90f8b494-64b2-fd9a-6b19-ded5f185ddd1@suse.com/","msgid":"<90f8b494-64b2-fd9a-6b19-ded5f185ddd1@suse.com>","list_archive_url":null,"date":"2022-12-12T13:14:13","name":"[2/2] x86: omit Cpu prefixes from opcode table","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/90f8b494-64b2-fd9a-6b19-ded5f185ddd1@suse.com/mbox/"},{"id":32407,"url":"https://patchwork.plctlab.org/api/1.2/patches/32407/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y5c2J0s2fgqvL61d@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-12-12T14:09:43","name":"PR29893, buffer overflow in display_debug_addr","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y5c2J0s2fgqvL61d@squeak.grove.modra.org/mbox/"},{"id":32596,"url":"https://patchwork.plctlab.org/api/1.2/patches/32596/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y5fj/uw/pAKASueh@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-12-13T02:31:26","name":"asan: mips_hi16_list segfault in bfd_get_section_limit_octets","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y5fj/uw/pAKASueh@squeak.grove.modra.org/mbox/"},{"id":32623,"url":"https://patchwork.plctlab.org/api/1.2/patches/32623/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221213043428.33155-1-xuli1@eswincomputing.com/","msgid":"<20221213043428.33155-1-xuli1@eswincomputing.com>","list_archive_url":null,"date":"2022-12-13T04:34:28","name":"RISC-V: Add string length check for operands in AS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221213043428.33155-1-xuli1@eswincomputing.com/mbox/"},{"id":32656,"url":"https://patchwork.plctlab.org/api/1.2/patches/32656/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221213065851.2777297-2-mengqinggang@loongson.cn/","msgid":"<20221213065851.2777297-2-mengqinggang@loongson.cn>","list_archive_url":null,"date":"2022-12-13T06:58:46","name":"[v2,1/6] LoongArch: include: Add support for linker relaxation.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221213065851.2777297-2-mengqinggang@loongson.cn/mbox/"},{"id":32660,"url":"https://patchwork.plctlab.org/api/1.2/patches/32660/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221213065851.2777297-3-mengqinggang@loongson.cn/","msgid":"<20221213065851.2777297-3-mengqinggang@loongson.cn>","list_archive_url":null,"date":"2022-12-13T06:58:47","name":"[v2,2/6] LoongArch: bfd: Add support for linker relaxation.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221213065851.2777297-3-mengqinggang@loongson.cn/mbox/"},{"id":32657,"url":"https://patchwork.plctlab.org/api/1.2/patches/32657/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221213065851.2777297-4-mengqinggang@loongson.cn/","msgid":"<20221213065851.2777297-4-mengqinggang@loongson.cn>","list_archive_url":null,"date":"2022-12-13T06:58:48","name":"[v2,3/6] LoongArch: opcodes: Add support for linker relaxation.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221213065851.2777297-4-mengqinggang@loongson.cn/mbox/"},{"id":32661,"url":"https://patchwork.plctlab.org/api/1.2/patches/32661/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221213065851.2777297-5-mengqinggang@loongson.cn/","msgid":"<20221213065851.2777297-5-mengqinggang@loongson.cn>","list_archive_url":null,"date":"2022-12-13T06:58:49","name":"[v2,4/6] LoongArch: binutils: Add support for linker relaxation.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221213065851.2777297-5-mengqinggang@loongson.cn/mbox/"},{"id":32659,"url":"https://patchwork.plctlab.org/api/1.2/patches/32659/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221213065851.2777297-6-mengqinggang@loongson.cn/","msgid":"<20221213065851.2777297-6-mengqinggang@loongson.cn>","list_archive_url":null,"date":"2022-12-13T06:58:50","name":"[v2,5/6] LoongArch: gas: Add support for linker relaxation.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221213065851.2777297-6-mengqinggang@loongson.cn/mbox/"},{"id":32658,"url":"https://patchwork.plctlab.org/api/1.2/patches/32658/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221213065851.2777297-7-mengqinggang@loongson.cn/","msgid":"<20221213065851.2777297-7-mengqinggang@loongson.cn>","list_archive_url":null,"date":"2022-12-13T06:58:51","name":"[v2,6/6] LoongArch: ld: Add support for linker relaxation.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221213065851.2777297-7-mengqinggang@loongson.cn/mbox/"},{"id":32855,"url":"https://patchwork.plctlab.org/api/1.2/patches/32855/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0adeda5c-0696-d3bf-499a-fd63e3a4f709@suse.com/","msgid":"<0adeda5c-0696-d3bf-499a-fd63e3a4f709@suse.com>","list_archive_url":null,"date":"2022-12-13T15:31:27","name":"Arm: break gas dependency on libopcodes","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0adeda5c-0696-d3bf-499a-fd63e3a4f709@suse.com/mbox/"},{"id":33035,"url":"https://patchwork.plctlab.org/api/1.2/patches/33035/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y5lEcMxUdytmdyC6@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-12-14T03:35:12","name":"Don'\''t access freed memory printing objcopy warning","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y5lEcMxUdytmdyC6@squeak.grove.modra.org/mbox/"},{"id":33036,"url":"https://patchwork.plctlab.org/api/1.2/patches/33036/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y5lEjrLPqV3l35Qf@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-12-14T03:35:42","name":"asan: signed integer overflow in display_debug_frames","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y5lEjrLPqV3l35Qf@squeak.grove.modra.org/mbox/"},{"id":33054,"url":"https://patchwork.plctlab.org/api/1.2/patches/33054/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221214054700.2889049-2-i.swmail@xen0n.name/","msgid":"<20221214054700.2889049-2-i.swmail@xen0n.name>","list_archive_url":null,"date":"2022-12-14T05:46:55","name":"[v3,1/6] LoongArch: support disassembling certain pseudo-instructions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221214054700.2889049-2-i.swmail@xen0n.name/mbox/"},{"id":33055,"url":"https://patchwork.plctlab.org/api/1.2/patches/33055/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221214054700.2889049-3-i.swmail@xen0n.name/","msgid":"<20221214054700.2889049-3-i.swmail@xen0n.name>","list_archive_url":null,"date":"2022-12-14T05:46:56","name":"[v3,2/6] opcodes/loongarch: remove unused code","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221214054700.2889049-3-i.swmail@xen0n.name/mbox/"},{"id":33057,"url":"https://patchwork.plctlab.org/api/1.2/patches/33057/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221214054700.2889049-4-i.swmail@xen0n.name/","msgid":"<20221214054700.2889049-4-i.swmail@xen0n.name>","list_archive_url":null,"date":"2022-12-14T05:46:57","name":"[v3,3/6] opcodes/loongarch: implement style support in the disassembler","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221214054700.2889049-4-i.swmail@xen0n.name/mbox/"},{"id":33058,"url":"https://patchwork.plctlab.org/api/1.2/patches/33058/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221214054700.2889049-5-i.swmail@xen0n.name/","msgid":"<20221214054700.2889049-5-i.swmail@xen0n.name>","list_archive_url":null,"date":"2022-12-14T05:46:58","name":"[v3,4/6] opcodes/loongarch: style disassembled address offsets as such","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221214054700.2889049-5-i.swmail@xen0n.name/mbox/"},{"id":33059,"url":"https://patchwork.plctlab.org/api/1.2/patches/33059/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221214054700.2889049-6-i.swmail@xen0n.name/","msgid":"<20221214054700.2889049-6-i.swmail@xen0n.name>","list_archive_url":null,"date":"2022-12-14T05:46:59","name":"[v3,5/6] opcodes/loongarch: do not print hex notation for signed immediates","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221214054700.2889049-6-i.swmail@xen0n.name/mbox/"},{"id":33056,"url":"https://patchwork.plctlab.org/api/1.2/patches/33056/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221214054700.2889049-7-i.swmail@xen0n.name/","msgid":"<20221214054700.2889049-7-i.swmail@xen0n.name>","list_archive_url":null,"date":"2022-12-14T05:47:00","name":"[v3,6/6] opcodes/loongarch: print unrecognized insn words with the .word directive","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221214054700.2889049-7-i.swmail@xen0n.name/mbox/"},{"id":33061,"url":"https://patchwork.plctlab.org/api/1.2/patches/33061/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221214055204.2890795-2-i.swmail@xen0n.name/","msgid":"<20221214055204.2890795-2-i.swmail@xen0n.name>","list_archive_url":null,"date":"2022-12-14T05:51:59","name":"[v3,1/6] LoongArch: support disassembling certain pseudo-instructions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221214055204.2890795-2-i.swmail@xen0n.name/mbox/"},{"id":33062,"url":"https://patchwork.plctlab.org/api/1.2/patches/33062/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221214055204.2890795-3-i.swmail@xen0n.name/","msgid":"<20221214055204.2890795-3-i.swmail@xen0n.name>","list_archive_url":null,"date":"2022-12-14T05:52:00","name":"[v3,2/6] opcodes/loongarch: remove unused code","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221214055204.2890795-3-i.swmail@xen0n.name/mbox/"},{"id":33060,"url":"https://patchwork.plctlab.org/api/1.2/patches/33060/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221214055204.2890795-4-i.swmail@xen0n.name/","msgid":"<20221214055204.2890795-4-i.swmail@xen0n.name>","list_archive_url":null,"date":"2022-12-14T05:52:01","name":"[v3,3/6] opcodes/loongarch: implement style support in the disassembler","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221214055204.2890795-4-i.swmail@xen0n.name/mbox/"},{"id":33063,"url":"https://patchwork.plctlab.org/api/1.2/patches/33063/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221214055204.2890795-5-i.swmail@xen0n.name/","msgid":"<20221214055204.2890795-5-i.swmail@xen0n.name>","list_archive_url":null,"date":"2022-12-14T05:52:02","name":"[v3,4/6] opcodes/loongarch: style disassembled address offsets as such","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221214055204.2890795-5-i.swmail@xen0n.name/mbox/"},{"id":33065,"url":"https://patchwork.plctlab.org/api/1.2/patches/33065/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221214055204.2890795-6-i.swmail@xen0n.name/","msgid":"<20221214055204.2890795-6-i.swmail@xen0n.name>","list_archive_url":null,"date":"2022-12-14T05:52:03","name":"[v3,5/6] opcodes/loongarch: do not print hex notation for signed immediates","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221214055204.2890795-6-i.swmail@xen0n.name/mbox/"},{"id":33064,"url":"https://patchwork.plctlab.org/api/1.2/patches/33064/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221214055204.2890795-7-i.swmail@xen0n.name/","msgid":"<20221214055204.2890795-7-i.swmail@xen0n.name>","list_archive_url":null,"date":"2022-12-14T05:52:04","name":"[v3,6/6] opcodes/loongarch: print unrecognized insn words with the .word directive","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221214055204.2890795-7-i.swmail@xen0n.name/mbox/"},{"id":33086,"url":"https://patchwork.plctlab.org/api/1.2/patches/33086/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221214073240.24973-1-xuli1@eswincomputing.com/","msgid":"<20221214073240.24973-1-xuli1@eswincomputing.com>","list_archive_url":null,"date":"2022-12-14T07:32:40","name":"[v2] RISC-V: Add string length check for operands in AS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221214073240.24973-1-xuli1@eswincomputing.com/mbox/"},{"id":33111,"url":"https://patchwork.plctlab.org/api/1.2/patches/33111/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/af826d86-8600-6a8b-f696-0b26c7774d45@suse.com/","msgid":"","list_archive_url":null,"date":"2022-12-14T09:07:07","name":"x86: adjust type checking constructs","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/af826d86-8600-6a8b-f696-0b26c7774d45@suse.com/mbox/"},{"id":33164,"url":"https://patchwork.plctlab.org/api/1.2/patches/33164/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y5m2zCJFXs1Ywa+M@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-12-14T11:43:08","name":"Fix haiku ld dependencies","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y5m2zCJFXs1Ywa+M@squeak.grove.modra.org/mbox/"},{"id":33165,"url":"https://patchwork.plctlab.org/api/1.2/patches/33165/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y5m285CXyYl9DPU6@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-12-14T11:43:47","name":"asan: buffer overflow in sh_reloc","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y5m285CXyYl9DPU6@squeak.grove.modra.org/mbox/"},{"id":33304,"url":"https://patchwork.plctlab.org/api/1.2/patches/33304/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221214195859.1233809-2-indu.bhagat@oracle.com/","msgid":"<20221214195859.1233809-2-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-12-14T19:58:54","name":"[1/6,1/6] sframe.h: add support for .cfi_negate_ra_state","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221214195859.1233809-2-indu.bhagat@oracle.com/mbox/"},{"id":33298,"url":"https://patchwork.plctlab.org/api/1.2/patches/33298/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221214195859.1233809-3-indu.bhagat@oracle.com/","msgid":"<20221214195859.1233809-3-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-12-14T19:58:55","name":"[2/6,2/6] gas: sframe: add support for .cfi_negate_ra_state","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221214195859.1233809-3-indu.bhagat@oracle.com/mbox/"},{"id":33299,"url":"https://patchwork.plctlab.org/api/1.2/patches/33299/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221214195859.1233809-4-indu.bhagat@oracle.com/","msgid":"<20221214195859.1233809-4-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-12-14T19:58:56","name":"[3/6,3/6] gas: sframe: testsuite: add testcase for .cfi_negate_ra_state","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221214195859.1233809-4-indu.bhagat@oracle.com/mbox/"},{"id":33313,"url":"https://patchwork.plctlab.org/api/1.2/patches/33313/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221214195859.1233809-5-indu.bhagat@oracle.com/","msgid":"<20221214195859.1233809-5-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-12-14T19:58:57","name":"[4/6,4/6] libsframe: provide new access API for mangled RA bit","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221214195859.1233809-5-indu.bhagat@oracle.com/mbox/"},{"id":33300,"url":"https://patchwork.plctlab.org/api/1.2/patches/33300/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221214195859.1233809-6-indu.bhagat@oracle.com/","msgid":"<20221214195859.1233809-6-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-12-14T19:58:58","name":"[5/6,5/6] objdump/readelf: sframe: emit marker for FREs with mangled RA","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221214195859.1233809-6-indu.bhagat@oracle.com/mbox/"},{"id":33307,"url":"https://patchwork.plctlab.org/api/1.2/patches/33307/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221214195859.1233809-7-indu.bhagat@oracle.com/","msgid":"<20221214195859.1233809-7-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-12-14T19:58:59","name":"[6/6,6/6] sframe: doc: update spec for the mangled-RA bit in FRE","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221214195859.1233809-7-indu.bhagat@oracle.com/mbox/"},{"id":33329,"url":"https://patchwork.plctlab.org/api/1.2/patches/33329/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221214200756.1234528-2-indu.bhagat@oracle.com/","msgid":"<20221214200756.1234528-2-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-12-14T20:07:52","name":"[1/5,1/5] sframe.h: add support for .cfi_b_key_frame","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221214200756.1234528-2-indu.bhagat@oracle.com/mbox/"},{"id":33336,"url":"https://patchwork.plctlab.org/api/1.2/patches/33336/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221214200756.1234528-3-indu.bhagat@oracle.com/","msgid":"<20221214200756.1234528-3-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-12-14T20:07:53","name":"[2/5,2/5] gas: sframe: add support for .cfi_b_key_frame","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221214200756.1234528-3-indu.bhagat@oracle.com/mbox/"},{"id":33334,"url":"https://patchwork.plctlab.org/api/1.2/patches/33334/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221214200756.1234528-4-indu.bhagat@oracle.com/","msgid":"<20221214200756.1234528-4-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-12-14T20:07:54","name":"[3/5,3/5] objdump/readelf: sframe: emit marker for SFrame FDE with B key","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221214200756.1234528-4-indu.bhagat@oracle.com/mbox/"},{"id":33331,"url":"https://patchwork.plctlab.org/api/1.2/patches/33331/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221214200756.1234528-5-indu.bhagat@oracle.com/","msgid":"<20221214200756.1234528-5-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-12-14T20:07:55","name":"[4/5,4/5] gas: sframe: testsuite: add testcase for .cfi_b_key_frame","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221214200756.1234528-5-indu.bhagat@oracle.com/mbox/"},{"id":33337,"url":"https://patchwork.plctlab.org/api/1.2/patches/33337/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221214200756.1234528-6-indu.bhagat@oracle.com/","msgid":"<20221214200756.1234528-6-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-12-14T20:07:56","name":"[5/5,5/5] sframe: doc: update documentation for pauth key in SFrame FDE","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221214200756.1234528-6-indu.bhagat@oracle.com/mbox/"},{"id":33412,"url":"https://patchwork.plctlab.org/api/1.2/patches/33412/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221214234310.1247719-1-indu.bhagat@oracle.com/","msgid":"<20221214234310.1247719-1-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-12-14T23:43:10","name":"[PR,29856] libsframe: avoid generating misaligned loads","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221214234310.1247719-1-indu.bhagat@oracle.com/mbox/"},{"id":33669,"url":"https://patchwork.plctlab.org/api/1.2/patches/33669/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/15b35aca-4b74-63ff-b6e9-831879fa7cfa@suse.com/","msgid":"<15b35aca-4b74-63ff-b6e9-831879fa7cfa@suse.com>","list_archive_url":null,"date":"2022-12-15T15:14:57","name":"gas: restore Dwarf info generation after macro diagnostic adjustments","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/15b35aca-4b74-63ff-b6e9-831879fa7cfa@suse.com/mbox/"},{"id":33836,"url":"https://patchwork.plctlab.org/api/1.2/patches/33836/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221216021400.22309-1-mark@harmstone.com/","msgid":"<20221216021400.22309-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-12-16T02:13:56","name":"[1/5] Fix size of external_reloc for pe-aarch64","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221216021400.22309-1-mark@harmstone.com/mbox/"},{"id":33839,"url":"https://patchwork.plctlab.org/api/1.2/patches/33839/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221216021400.22309-2-mark@harmstone.com/","msgid":"<20221216021400.22309-2-mark@harmstone.com>","list_archive_url":null,"date":"2022-12-16T02:13:57","name":"[2/5] Skip ELF-specific tests when targeting pe-aarch64","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221216021400.22309-2-mark@harmstone.com/mbox/"},{"id":33840,"url":"https://patchwork.plctlab.org/api/1.2/patches/33840/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221216021400.22309-3-mark@harmstone.com/","msgid":"<20221216021400.22309-3-mark@harmstone.com>","list_archive_url":null,"date":"2022-12-16T02:13:58","name":"[3/5] Add pe-aarch64 relocations","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221216021400.22309-3-mark@harmstone.com/mbox/"},{"id":33837,"url":"https://patchwork.plctlab.org/api/1.2/patches/33837/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221216021400.22309-4-mark@harmstone.com/","msgid":"<20221216021400.22309-4-mark@harmstone.com>","list_archive_url":null,"date":"2022-12-16T02:13:59","name":"[4/5] Add .secrel32 for pe-aarch64","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221216021400.22309-4-mark@harmstone.com/mbox/"},{"id":33838,"url":"https://patchwork.plctlab.org/api/1.2/patches/33838/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221216021400.22309-5-mark@harmstone.com/","msgid":"<20221216021400.22309-5-mark@harmstone.com>","list_archive_url":null,"date":"2022-12-16T02:14:00","name":"[5/5] Add aarch64-w64-mingw32 target","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221216021400.22309-5-mark@harmstone.com/mbox/"},{"id":33885,"url":"https://patchwork.plctlab.org/api/1.2/patches/33885/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221216072336.1087469-2-mengqinggang@loongson.cn/","msgid":"<20221216072336.1087469-2-mengqinggang@loongson.cn>","list_archive_url":null,"date":"2022-12-16T07:23:31","name":"[v3,1/6] LoongArch: include: Add support for linker relaxation.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221216072336.1087469-2-mengqinggang@loongson.cn/mbox/"},{"id":33886,"url":"https://patchwork.plctlab.org/api/1.2/patches/33886/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221216072336.1087469-3-mengqinggang@loongson.cn/","msgid":"<20221216072336.1087469-3-mengqinggang@loongson.cn>","list_archive_url":null,"date":"2022-12-16T07:23:32","name":"[v3,2/6] LoongArch: bfd: Add support for linker relaxation.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221216072336.1087469-3-mengqinggang@loongson.cn/mbox/"},{"id":33888,"url":"https://patchwork.plctlab.org/api/1.2/patches/33888/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221216072336.1087469-4-mengqinggang@loongson.cn/","msgid":"<20221216072336.1087469-4-mengqinggang@loongson.cn>","list_archive_url":null,"date":"2022-12-16T07:23:33","name":"[v3,3/6] LoongArch: opcodes: Add support for linker relaxation.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221216072336.1087469-4-mengqinggang@loongson.cn/mbox/"},{"id":33889,"url":"https://patchwork.plctlab.org/api/1.2/patches/33889/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221216072336.1087469-5-mengqinggang@loongson.cn/","msgid":"<20221216072336.1087469-5-mengqinggang@loongson.cn>","list_archive_url":null,"date":"2022-12-16T07:23:34","name":"[v3,4/6] LoongArch: binutils: Add support for linker relaxation.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221216072336.1087469-5-mengqinggang@loongson.cn/mbox/"},{"id":33887,"url":"https://patchwork.plctlab.org/api/1.2/patches/33887/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221216072336.1087469-6-mengqinggang@loongson.cn/","msgid":"<20221216072336.1087469-6-mengqinggang@loongson.cn>","list_archive_url":null,"date":"2022-12-16T07:23:35","name":"[v3,5/6] LoongArch: gas: Add support for linker relaxation.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221216072336.1087469-6-mengqinggang@loongson.cn/mbox/"},{"id":33890,"url":"https://patchwork.plctlab.org/api/1.2/patches/33890/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221216072336.1087469-7-mengqinggang@loongson.cn/","msgid":"<20221216072336.1087469-7-mengqinggang@loongson.cn>","list_archive_url":null,"date":"2022-12-16T07:23:36","name":"[v3,6/6] LoongArch: ld: Add support for linker relaxation.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221216072336.1087469-7-mengqinggang@loongson.cn/mbox/"},{"id":33895,"url":"https://patchwork.plctlab.org/api/1.2/patches/33895/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/98057a7f-d166-1940-f00f-d9c5d912328d@suse.com/","msgid":"<98057a7f-d166-1940-f00f-d9c5d912328d@suse.com>","list_archive_url":null,"date":"2022-12-16T08:07:29","name":"[v2] x86: omit Cpu prefixes from opcode table","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/98057a7f-d166-1940-f00f-d9c5d912328d@suse.com/mbox/"},{"id":33899,"url":"https://patchwork.plctlab.org/api/1.2/patches/33899/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/507f0d3f-c34e-9895-21bf-37525bf0a6fb@suse.com/","msgid":"<507f0d3f-c34e-9895-21bf-37525bf0a6fb@suse.com>","list_archive_url":null,"date":"2022-12-16T08:28:38","name":"[1/4] gprofng/testsuite: adjust linking of synprog","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/507f0d3f-c34e-9895-21bf-37525bf0a6fb@suse.com/mbox/"},{"id":33900,"url":"https://patchwork.plctlab.org/api/1.2/patches/33900/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/67f3d4e3-46dd-e39d-d154-49bf25dbafc8@suse.com/","msgid":"<67f3d4e3-46dd-e39d-d154-49bf25dbafc8@suse.com>","list_archive_url":null,"date":"2022-12-16T08:29:50","name":"[2/4] gprofng/testsuite: correct names for signal handling tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/67f3d4e3-46dd-e39d-d154-49bf25dbafc8@suse.com/mbox/"},{"id":33902,"url":"https://patchwork.plctlab.org/api/1.2/patches/33902/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/240a568e-ab05-b3b5-d004-c1fc6799c66f@suse.com/","msgid":"<240a568e-ab05-b3b5-d004-c1fc6799c66f@suse.com>","list_archive_url":null,"date":"2022-12-16T08:30:10","name":"[3/4] gprofng/testsuite: correct line continuation in endcases.c","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/240a568e-ab05-b3b5-d004-c1fc6799c66f@suse.com/mbox/"},{"id":33903,"url":"https://patchwork.plctlab.org/api/1.2/patches/33903/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f0679195-cfa8-6f87-2519-520f758e615e@suse.com/","msgid":"","list_archive_url":null,"date":"2022-12-16T08:30:30","name":"[4/4] gprofng/testsuite: eliminate bogus casts","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f0679195-cfa8-6f87-2519-520f758e615e@suse.com/mbox/"},{"id":33915,"url":"https://patchwork.plctlab.org/api/1.2/patches/33915/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0acc18cc-d246-9c2a-ba14-586c693b9e58@suse.com/","msgid":"<0acc18cc-d246-9c2a-ba14-586c693b9e58@suse.com>","list_archive_url":null,"date":"2022-12-16T09:13:36","name":"[5/4] gprofng/testsuite: skip Java test without JDK","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0acc18cc-d246-9c2a-ba14-586c693b9e58@suse.com/mbox/"},{"id":33950,"url":"https://patchwork.plctlab.org/api/1.2/patches/33950/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221216132541.45791-2-nick.alcock@oracle.com/","msgid":"<20221216132541.45791-2-nick.alcock@oracle.com>","list_archive_url":null,"date":"2022-12-16T13:25:38","name":"[1/4] ctf: fix various dreadful typos in the ctf_archive format comments","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221216132541.45791-2-nick.alcock@oracle.com/mbox/"},{"id":33951,"url":"https://patchwork.plctlab.org/api/1.2/patches/33951/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221216132541.45791-3-nick.alcock@oracle.com/","msgid":"<20221216132541.45791-3-nick.alcock@oracle.com>","list_archive_url":null,"date":"2022-12-16T13:25:39","name":"[2/4] libtool.m4: adjust kludge for ignoring syntax errors","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221216132541.45791-3-nick.alcock@oracle.com/mbox/"},{"id":33952,"url":"https://patchwork.plctlab.org/api/1.2/patches/33952/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221216132541.45791-4-nick.alcock@oracle.com/","msgid":"<20221216132541.45791-4-nick.alcock@oracle.com>","list_archive_url":null,"date":"2022-12-16T13:25:40","name":"[3/4] Regenerate affected configures.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221216132541.45791-4-nick.alcock@oracle.com/mbox/"},{"id":33953,"url":"https://patchwork.plctlab.org/api/1.2/patches/33953/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221216132541.45791-5-nick.alcock@oracle.com/","msgid":"<20221216132541.45791-5-nick.alcock@oracle.com>","list_archive_url":null,"date":"2022-12-16T13:25:41","name":"[4/4] libctf: skip the testsuite from inside dejagnu","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221216132541.45791-5-nick.alcock@oracle.com/mbox/"},{"id":34050,"url":"https://patchwork.plctlab.org/api/1.2/patches/34050/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221216185133.1342022-1-christoph.muellner@vrull.eu/","msgid":"<20221216185133.1342022-1-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2022-12-16T18:51:33","name":"RISC-V: Fix T-Head Fmv vendor extension encoding","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221216185133.1342022-1-christoph.muellner@vrull.eu/mbox/"},{"id":34093,"url":"https://patchwork.plctlab.org/api/1.2/patches/34093/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221216214310.13155-1-prabhakar.mahadev-lad.rj@bp.renesas.com/","msgid":"<20221216214310.13155-1-prabhakar.mahadev-lad.rj@bp.renesas.com>","list_archive_url":null,"date":"2022-12-16T21:43:10","name":"[RFC] ld/emulparams: elf32lriscv-defs: Add support tune the text segment start address","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221216214310.13155-1-prabhakar.mahadev-lad.rj@bp.renesas.com/mbox/"},{"id":34193,"url":"https://patchwork.plctlab.org/api/1.2/patches/34193/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221217064128.11326-2-indu.bhagat@oracle.com/","msgid":"<20221217064128.11326-2-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-12-17T06:41:23","name":"[COMMITTED,V2,1/6] sframe.h: add support for .cfi_negate_ra_state","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221217064128.11326-2-indu.bhagat@oracle.com/mbox/"},{"id":34188,"url":"https://patchwork.plctlab.org/api/1.2/patches/34188/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221217064128.11326-3-indu.bhagat@oracle.com/","msgid":"<20221217064128.11326-3-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-12-17T06:41:24","name":"[COMMITTED,V2,2/6] gas: sframe: add support for .cfi_negate_ra_state","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221217064128.11326-3-indu.bhagat@oracle.com/mbox/"},{"id":34187,"url":"https://patchwork.plctlab.org/api/1.2/patches/34187/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221217064128.11326-4-indu.bhagat@oracle.com/","msgid":"<20221217064128.11326-4-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-12-17T06:41:25","name":"[COMMITTED,V2,3/6] libsframe: provide new access API for mangled RA bit","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221217064128.11326-4-indu.bhagat@oracle.com/mbox/"},{"id":34189,"url":"https://patchwork.plctlab.org/api/1.2/patches/34189/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221217064128.11326-5-indu.bhagat@oracle.com/","msgid":"<20221217064128.11326-5-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-12-17T06:41:26","name":"[COMMITTED,V2,4/6] objdump/readelf: sframe: emit marker for FREs with mangled RA","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221217064128.11326-5-indu.bhagat@oracle.com/mbox/"},{"id":34195,"url":"https://patchwork.plctlab.org/api/1.2/patches/34195/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221217064128.11326-6-indu.bhagat@oracle.com/","msgid":"<20221217064128.11326-6-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-12-17T06:41:27","name":"[COMMITTED,V2,5/6] gas: sframe: testsuite: add testcase for .cfi_negate_ra_state","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221217064128.11326-6-indu.bhagat@oracle.com/mbox/"},{"id":34196,"url":"https://patchwork.plctlab.org/api/1.2/patches/34196/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221217064128.11326-7-indu.bhagat@oracle.com/","msgid":"<20221217064128.11326-7-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-12-17T06:41:28","name":"[COMMITTED,V2,6/6] sframe: doc: update spec for the mangled-RA bit in FRE","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221217064128.11326-7-indu.bhagat@oracle.com/mbox/"},{"id":34198,"url":"https://patchwork.plctlab.org/api/1.2/patches/34198/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y516F5Mqq4AgLz0T@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-12-17T08:13:11","name":"asan: elf.c:12621:18: applying zero offset to null pointer","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y516F5Mqq4AgLz0T@squeak.grove.modra.org/mbox/"},{"id":34199,"url":"https://patchwork.plctlab.org/api/1.2/patches/34199/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y516VfGAggasKzZE@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-12-17T08:14:13","name":"bfd_get_relocated_section_contents allow NULL data buffer","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y516VfGAggasKzZE@squeak.grove.modra.org/mbox/"},{"id":34204,"url":"https://patchwork.plctlab.org/api/1.2/patches/34204/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221217102842.3645997-1-torbjorn.svensson@foss.st.com/","msgid":"<20221217102842.3645997-1-torbjorn.svensson@foss.st.com>","list_archive_url":null,"date":"2022-12-17T10:28:42","name":"bfd: Discard region regardless of warning flag","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221217102842.3645997-1-torbjorn.svensson@foss.st.com/mbox/"},{"id":34302,"url":"https://patchwork.plctlab.org/api/1.2/patches/34302/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y57nSbf16Gc0Cm7u@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-12-18T10:11:21","name":"ld bootstrap test in build dir with path containing symlinks","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y57nSbf16Gc0Cm7u@squeak.grove.modra.org/mbox/"},{"id":34303,"url":"https://patchwork.plctlab.org/api/1.2/patches/34303/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y57nfEDqt/784poP@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-12-18T10:12:12","name":"Comment bfd_get_section_limit_octets and bfd_get_section_alloc_size","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y57nfEDqt/784poP@squeak.grove.modra.org/mbox/"},{"id":34459,"url":"https://patchwork.plctlab.org/api/1.2/patches/34459/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221219090346.213013-1-vladimir.mezentsev@oracle.com/","msgid":"<20221219090346.213013-1-vladimir.mezentsev@oracle.com>","list_archive_url":null,"date":"2022-12-19T09:03:46","name":"gprofng: PR29646 Various warnings","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221219090346.213013-1-vladimir.mezentsev@oracle.com/mbox/"},{"id":34460,"url":"https://patchwork.plctlab.org/api/1.2/patches/34460/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/63033af0-eb22-a8eb-c8cb-f268344c5a14@suse.com/","msgid":"<63033af0-eb22-a8eb-c8cb-f268344c5a14@suse.com>","list_archive_url":null,"date":"2022-12-19T10:44:40","name":"[01/10] x86: re-work ISA extension dependency handling","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/63033af0-eb22-a8eb-c8cb-f268344c5a14@suse.com/mbox/"},{"id":34461,"url":"https://patchwork.plctlab.org/api/1.2/patches/34461/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2cf259b7-9594-ed3f-f3f0-e7a232c03551@suse.com/","msgid":"<2cf259b7-9594-ed3f-f3f0-e7a232c03551@suse.com>","list_archive_url":null,"date":"2022-12-19T10:45:06","name":"[02/10] x86: correct what gets disabled by certain \".arch .no*\"","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2cf259b7-9594-ed3f-f3f0-e7a232c03551@suse.com/mbox/"},{"id":34462,"url":"https://patchwork.plctlab.org/api/1.2/patches/34462/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/141a0a8e-eb9f-f68f-0eb1-92d62e828f9e@suse.com/","msgid":"<141a0a8e-eb9f-f68f-0eb1-92d62e828f9e@suse.com>","list_archive_url":null,"date":"2022-12-19T10:45:36","name":"[03/10] x86: correct SSE dependencies","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/141a0a8e-eb9f-f68f-0eb1-92d62e828f9e@suse.com/mbox/"},{"id":34467,"url":"https://patchwork.plctlab.org/api/1.2/patches/34467/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ae514f08-6ed8-e30a-9077-c9e37d12bd46@suse.com/","msgid":"","list_archive_url":null,"date":"2022-12-19T10:45:55","name":"[04/10] x86: add dependencies on AVX2","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ae514f08-6ed8-e30a-9077-c9e37d12bd46@suse.com/mbox/"},{"id":34468,"url":"https://patchwork.plctlab.org/api/1.2/patches/34468/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0f352a12-4d8a-7658-0104-8537241b6b49@suse.com/","msgid":"<0f352a12-4d8a-7658-0104-8537241b6b49@suse.com>","list_archive_url":null,"date":"2022-12-19T10:46:24","name":"[05/10] x86: rework noavx512-1 testcase","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0f352a12-4d8a-7658-0104-8537241b6b49@suse.com/mbox/"},{"id":34464,"url":"https://patchwork.plctlab.org/api/1.2/patches/34464/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2176ff46-f9e9-19c5-576a-0e69d9d02c15@suse.com/","msgid":"<2176ff46-f9e9-19c5-576a-0e69d9d02c15@suse.com>","list_archive_url":null,"date":"2022-12-19T10:46:50","name":"[06/10] x86: correct dependencies of a few AVX512 sub-features","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2176ff46-f9e9-19c5-576a-0e69d9d02c15@suse.com/mbox/"},{"id":34466,"url":"https://patchwork.plctlab.org/api/1.2/patches/34466/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/70971dfa-e30a-ec90-d797-808ecf674cc5@suse.com/","msgid":"<70971dfa-e30a-ec90-d797-808ecf674cc5@suse.com>","list_archive_url":null,"date":"2022-12-19T10:47:18","name":"[07/10] x86: correct XSAVE* dependencies","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/70971dfa-e30a-ec90-d797-808ecf674cc5@suse.com/mbox/"},{"id":34471,"url":"https://patchwork.plctlab.org/api/1.2/patches/34471/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f29c5510-bc33-b0c3-aa25-27a02ba613ad@suse.com/","msgid":"","list_archive_url":null,"date":"2022-12-19T10:47:44","name":"[08/10] x86: add dependencies on VMX","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f29c5510-bc33-b0c3-aa25-27a02ba613ad@suse.com/mbox/"},{"id":34465,"url":"https://patchwork.plctlab.org/api/1.2/patches/34465/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0a930835-e8b4-40fa-34e5-bc29cde85200@suse.com/","msgid":"<0a930835-e8b4-40fa-34e5-bc29cde85200@suse.com>","list_archive_url":null,"date":"2022-12-19T10:48:11","name":"[09/10] x86: add dependencies on SVME","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0a930835-e8b4-40fa-34e5-bc29cde85200@suse.com/mbox/"},{"id":34472,"url":"https://patchwork.plctlab.org/api/1.2/patches/34472/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1b04fb35-1f99-7353-4e8c-d643e8ffa975@suse.com/","msgid":"<1b04fb35-1f99-7353-4e8c-d643e8ffa975@suse.com>","list_archive_url":null,"date":"2022-12-19T10:48:31","name":"[10/10] x86: correct/improve TSX controls","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1b04fb35-1f99-7353-4e8c-d643e8ffa975@suse.com/mbox/"},{"id":34470,"url":"https://patchwork.plctlab.org/api/1.2/patches/34470/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4a5ff47c-77cf-5ffa-ad7b-c8e0ae54b31c@suse.com/","msgid":"<4a5ff47c-77cf-5ffa-ad7b-c8e0ae54b31c@suse.com>","list_archive_url":null,"date":"2022-12-19T10:50:39","name":"x86: rename CheckRegSize to CheckOperandSize","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4a5ff47c-77cf-5ffa-ad7b-c8e0ae54b31c@suse.com/mbox/"},{"id":34473,"url":"https://patchwork.plctlab.org/api/1.2/patches/34473/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fdbff837-ebd9-7726-351c-1c43c619b4cb@suse.com/","msgid":"","list_archive_url":null,"date":"2022-12-19T10:53:19","name":"gas: re-arrange listing output for .irp and alike","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fdbff837-ebd9-7726-351c-1c43c619b4cb@suse.com/mbox/"},{"id":34476,"url":"https://patchwork.plctlab.org/api/1.2/patches/34476/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/87r0wvsl2q.fsf@redhat.com/","msgid":"<87r0wvsl2q.fsf@redhat.com>","list_archive_url":null,"date":"2022-12-19T11:13:17","name":"Commit: Add more tests for corrupt DWARF data","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/87r0wvsl2q.fsf@redhat.com/mbox/"},{"id":34538,"url":"https://patchwork.plctlab.org/api/1.2/patches/34538/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221219131149.2268979-1-luis.machado@arm.com/","msgid":"<20221219131149.2268979-1-luis.machado@arm.com>","list_archive_url":null,"date":"2022-12-19T13:11:49","name":"[aarch64/sme] binutils: Add new NT_ARM_ZA and NT_ARM_SSVE register set constants","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221219131149.2268979-1-luis.machado@arm.com/mbox/"},{"id":34542,"url":"https://patchwork.plctlab.org/api/1.2/patches/34542/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y6Bmt87TKcG5vugy@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-12-19T13:27:19","name":"Tidy PR29893 and PR29908 fix","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y6Bmt87TKcG5vugy@squeak.grove.modra.org/mbox/"},{"id":34553,"url":"https://patchwork.plctlab.org/api/1.2/patches/34553/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221219135303.116222-2-mpapini@redhat.com/","msgid":"<20221219135303.116222-2-mpapini@redhat.com>","list_archive_url":null,"date":"2022-12-19T13:53:02","name":"[1/2] addr2line: new option -n to add a newline at the end","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221219135303.116222-2-mpapini@redhat.com/mbox/"},{"id":34554,"url":"https://patchwork.plctlab.org/api/1.2/patches/34554/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221219135303.116222-3-mpapini@redhat.com/","msgid":"<20221219135303.116222-3-mpapini@redhat.com>","list_archive_url":null,"date":"2022-12-19T13:53:03","name":"[2/2] addr2line: test to check -n option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221219135303.116222-3-mpapini@redhat.com/mbox/"},{"id":34605,"url":"https://patchwork.plctlab.org/api/1.2/patches/34605/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f8cae085-3ed5-a6ec-cedf-f78d0c4b0ae1@suse.com/","msgid":"","list_archive_url":null,"date":"2022-12-19T15:06:26","name":"gprofng/testsuite: restrict testing to native configurations","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f8cae085-3ed5-a6ec-cedf-f78d0c4b0ae1@suse.com/mbox/"},{"id":34649,"url":"https://patchwork.plctlab.org/api/1.2/patches/34649/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221219164830.394274-1-tromey@adacore.com/","msgid":"<20221219164830.394274-1-tromey@adacore.com>","list_archive_url":null,"date":"2022-12-19T16:48:30","name":"[pushed] Avoid compiler warning in dwarf-do-refresh","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221219164830.394274-1-tromey@adacore.com/mbox/"},{"id":34689,"url":"https://patchwork.plctlab.org/api/1.2/patches/34689/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221219183450.3754890-1-torbjorn.svensson@foss.st.com/","msgid":"<20221219183450.3754890-1-torbjorn.svensson@foss.st.com>","list_archive_url":null,"date":"2022-12-19T18:34:51","name":"[v2] bfd: Discard region regardless of warning flag","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221219183450.3754890-1-torbjorn.svensson@foss.st.com/mbox/"},{"id":34751,"url":"https://patchwork.plctlab.org/api/1.2/patches/34751/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221219202328.1442022-2-indu.bhagat@oracle.com/","msgid":"<20221219202328.1442022-2-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-12-19T20:23:24","name":"[COMMITTED,V2,1/5,1/5] sframe.h: add support for .cfi_b_key_frame","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221219202328.1442022-2-indu.bhagat@oracle.com/mbox/"},{"id":34749,"url":"https://patchwork.plctlab.org/api/1.2/patches/34749/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221219202328.1442022-3-indu.bhagat@oracle.com/","msgid":"<20221219202328.1442022-3-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-12-19T20:23:25","name":"[COMMITTED,V2,2/5,2/5] gas: sframe: add support for .cfi_b_key_frame","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221219202328.1442022-3-indu.bhagat@oracle.com/mbox/"},{"id":34748,"url":"https://patchwork.plctlab.org/api/1.2/patches/34748/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221219202328.1442022-4-indu.bhagat@oracle.com/","msgid":"<20221219202328.1442022-4-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-12-19T20:23:26","name":"[COMMITTED,V2,3/5,3/5] objdump/readelf: sframe: emit marker for SFrame FDE with B key","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221219202328.1442022-4-indu.bhagat@oracle.com/mbox/"},{"id":34752,"url":"https://patchwork.plctlab.org/api/1.2/patches/34752/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221219202328.1442022-5-indu.bhagat@oracle.com/","msgid":"<20221219202328.1442022-5-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-12-19T20:23:27","name":"[COMMITTED,V2,4/5,4/5] gas: sframe: testsuite: add testcase for .cfi_b_key_frame","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221219202328.1442022-5-indu.bhagat@oracle.com/mbox/"},{"id":34750,"url":"https://patchwork.plctlab.org/api/1.2/patches/34750/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221219202328.1442022-6-indu.bhagat@oracle.com/","msgid":"<20221219202328.1442022-6-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-12-19T20:23:28","name":"[COMMITTED,V2,5/5,5/5] sframe: doc: update documentation for pauth key in SFrame FDE","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221219202328.1442022-6-indu.bhagat@oracle.com/mbox/"},{"id":34774,"url":"https://patchwork.plctlab.org/api/1.2/patches/34774/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221219211406.1443750-2-indu.bhagat@oracle.com/","msgid":"<20221219211406.1443750-2-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-12-19T21:14:02","name":"[V2,1/5,1/5] sframe.h: add support for .cfi_b_key_frame","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221219211406.1443750-2-indu.bhagat@oracle.com/mbox/"},{"id":34775,"url":"https://patchwork.plctlab.org/api/1.2/patches/34775/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221219211406.1443750-3-indu.bhagat@oracle.com/","msgid":"<20221219211406.1443750-3-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-12-19T21:14:03","name":"[V2,2/5,2/5] gas: sframe: add support for .cfi_b_key_frame","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221219211406.1443750-3-indu.bhagat@oracle.com/mbox/"},{"id":34776,"url":"https://patchwork.plctlab.org/api/1.2/patches/34776/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221219211406.1443750-4-indu.bhagat@oracle.com/","msgid":"<20221219211406.1443750-4-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-12-19T21:14:04","name":"[V2,3/5,3/5] objdump/readelf: sframe: emit marker for SFrame FDE with B key","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221219211406.1443750-4-indu.bhagat@oracle.com/mbox/"},{"id":34777,"url":"https://patchwork.plctlab.org/api/1.2/patches/34777/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221219211406.1443750-5-indu.bhagat@oracle.com/","msgid":"<20221219211406.1443750-5-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-12-19T21:14:05","name":"[V2,4/5,4/5] gas: sframe: testsuite: add testcase for .cfi_b_key_frame","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221219211406.1443750-5-indu.bhagat@oracle.com/mbox/"},{"id":34778,"url":"https://patchwork.plctlab.org/api/1.2/patches/34778/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221219211406.1443750-6-indu.bhagat@oracle.com/","msgid":"<20221219211406.1443750-6-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-12-19T21:14:06","name":"[V2,5/5,5/5] sframe: doc: update documentation for pauth key in SFrame FDE","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221219211406.1443750-6-indu.bhagat@oracle.com/mbox/"},{"id":34990,"url":"https://patchwork.plctlab.org/api/1.2/patches/34990/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y6FzlOKIrFOjqKVE@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-12-20T08:34:28","name":"PR29915, bfdio.c does not compile with mingw.org'\''s MinGW","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y6FzlOKIrFOjqKVE@squeak.grove.modra.org/mbox/"},{"id":35279,"url":"https://patchwork.plctlab.org/api/1.2/patches/35279/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y6K1tWIKWE+UA7+E@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-12-21T07:28:53","name":"PR29922, SHT_NOBITS section avoids section size sanity check","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y6K1tWIKWE+UA7+E@squeak.grove.modra.org/mbox/"},{"id":35280,"url":"https://patchwork.plctlab.org/api/1.2/patches/35280/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y6K17LKfvNSlmnbB@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-12-21T07:29:48","name":"enable-non-contiguous-regions warnings","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y6K17LKfvNSlmnbB@squeak.grove.modra.org/mbox/"},{"id":35347,"url":"https://patchwork.plctlab.org/api/1.2/patches/35347/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221221120934.45775-1-nelson@rivosinc.com/","msgid":"<20221221120934.45775-1-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-12-21T12:09:34","name":"RISC-V: Relax the order checking for the architecture string.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221221120934.45775-1-nelson@rivosinc.com/mbox/"},{"id":35432,"url":"https://patchwork.plctlab.org/api/1.2/patches/35432/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221221170706.2877188-2-christoph.muellner@vrull.eu/","msgid":"<20221221170706.2877188-2-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2022-12-21T17:07:01","name":"[RFC,1/6] RISC-V: Add Zvkb ISA extension support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221221170706.2877188-2-christoph.muellner@vrull.eu/mbox/"},{"id":35431,"url":"https://patchwork.plctlab.org/api/1.2/patches/35431/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221221170706.2877188-3-christoph.muellner@vrull.eu/","msgid":"<20221221170706.2877188-3-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2022-12-21T17:07:02","name":"[RFC,2/6] RISC-V: Add Zvkg ISA extension support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221221170706.2877188-3-christoph.muellner@vrull.eu/mbox/"},{"id":35434,"url":"https://patchwork.plctlab.org/api/1.2/patches/35434/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221221170706.2877188-4-christoph.muellner@vrull.eu/","msgid":"<20221221170706.2877188-4-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2022-12-21T17:07:03","name":"[RFC,3/6] RISC-V: Add Zvkh[a,b] ISA extension support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221221170706.2877188-4-christoph.muellner@vrull.eu/mbox/"},{"id":35435,"url":"https://patchwork.plctlab.org/api/1.2/patches/35435/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221221170706.2877188-5-christoph.muellner@vrull.eu/","msgid":"<20221221170706.2877188-5-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2022-12-21T17:07:04","name":"[RFC,4/6] RISC-V: Add Zvkn ISA extension support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221221170706.2877188-5-christoph.muellner@vrull.eu/mbox/"},{"id":35433,"url":"https://patchwork.plctlab.org/api/1.2/patches/35433/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221221170706.2877188-6-christoph.muellner@vrull.eu/","msgid":"<20221221170706.2877188-6-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2022-12-21T17:07:05","name":"[RFC,5/6] RISC-V: Add Zvksed ISA extension support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221221170706.2877188-6-christoph.muellner@vrull.eu/mbox/"},{"id":35437,"url":"https://patchwork.plctlab.org/api/1.2/patches/35437/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221221170706.2877188-7-christoph.muellner@vrull.eu/","msgid":"<20221221170706.2877188-7-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2022-12-21T17:07:06","name":"[RFC,6/6] RISC-V: Add Zvksh ISA extension support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221221170706.2877188-7-christoph.muellner@vrull.eu/mbox/"},{"id":35528,"url":"https://patchwork.plctlab.org/api/1.2/patches/35528/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y6N6cNwCN8q5hhHc@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-12-21T21:28:16","name":"PR29925, Memory leak in find_abstract_instance","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y6N6cNwCN8q5hhHc@squeak.grove.modra.org/mbox/"},{"id":35982,"url":"https://patchwork.plctlab.org/api/1.2/patches/35982/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221222225457.1095930-2-indu.bhagat@oracle.com/","msgid":"<20221222225457.1095930-2-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-12-22T22:54:56","name":"[1/2] libsframe: fix a memory leak in sframe_decode","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221222225457.1095930-2-indu.bhagat@oracle.com/mbox/"},{"id":35983,"url":"https://patchwork.plctlab.org/api/1.2/patches/35983/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221222225457.1095930-3-indu.bhagat@oracle.com/","msgid":"<20221222225457.1095930-3-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-12-22T22:54:57","name":"[2/2] libsframe: testsuite: fix memory leaks in testcases","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221222225457.1095930-3-indu.bhagat@oracle.com/mbox/"},{"id":36015,"url":"https://patchwork.plctlab.org/api/1.2/patches/36015/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y6TwpegMSaNdNc48@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-12-23T00:04:53","name":"COFF build-id writes uninitialised data to file","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y6TwpegMSaNdNc48@squeak.grove.modra.org/mbox/"},{"id":36206,"url":"https://patchwork.plctlab.org/api/1.2/patches/36206/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y6WIDO8tOPdLz0+5@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-12-23T10:50:52","name":"pdb build fixes","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y6WIDO8tOPdLz0+5@squeak.grove.modra.org/mbox/"},{"id":36281,"url":"https://patchwork.plctlab.org/api/1.2/patches/36281/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/98617b373993a3c6054b9389cddfde56b9aec7d1.camel@klomp.org/","msgid":"<98617b373993a3c6054b9389cddfde56b9aec7d1.camel@klomp.org>","list_archive_url":null,"date":"2022-12-23T14:22:38","name":"libsframe builder (Was: [PATCH 0/2] libsframe: fix some memory leaks)","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/98617b373993a3c6054b9389cddfde56b9aec7d1.camel@klomp.org/mbox/"},{"id":36442,"url":"https://patchwork.plctlab.org/api/1.2/patches/36442/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221224194012.1889405-1-indu.bhagat@oracle.com/","msgid":"<20221224194012.1889405-1-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-12-24T19:40:12","name":"libsframe: write out SFrame FRE start address correctly","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221224194012.1889405-1-indu.bhagat@oracle.com/mbox/"},{"id":36515,"url":"https://patchwork.plctlab.org/api/1.2/patches/36515/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y6j2+q32Gg+3rSGs@mars/","msgid":"","list_archive_url":null,"date":"2022-12-26T01:20:58","name":"Add support for x86_64-*-gnu-* targets to build x86_64 gnumach/hurd","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y6j2+q32Gg+3rSGs@mars/mbox/"},{"id":36605,"url":"https://patchwork.plctlab.org/api/1.2/patches/36605/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y6mS/HVlwxWvjyo9@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-12-26T12:26:36","name":"bfd/dwarf2.c: allow use of DWARF5 directory entry 0","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y6mS/HVlwxWvjyo9@squeak.grove.modra.org/mbox/"},{"id":36702,"url":"https://patchwork.plctlab.org/api/1.2/patches/36702/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221226204751.23761-1-mark@harmstone.com/","msgid":"<20221226204751.23761-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-12-26T20:47:49","name":"[1/3] ld: Handle extended-length data structures in PDB types","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221226204751.23761-1-mark@harmstone.com/mbox/"},{"id":36701,"url":"https://patchwork.plctlab.org/api/1.2/patches/36701/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221226204751.23761-2-mark@harmstone.com/","msgid":"<20221226204751.23761-2-mark@harmstone.com>","list_archive_url":null,"date":"2022-12-26T20:47:50","name":"[2/3] ld: Handle LF_VFTABLE types in PDBs","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221226204751.23761-2-mark@harmstone.com/mbox/"},{"id":36700,"url":"https://patchwork.plctlab.org/api/1.2/patches/36700/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221226204751.23761-3-mark@harmstone.com/","msgid":"<20221226204751.23761-3-mark@harmstone.com>","list_archive_url":null,"date":"2022-12-26T20:47:51","name":"[3/3] ld/testsuite: Don'\''t add index to sizes in pdb.exp","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221226204751.23761-3-mark@harmstone.com/mbox/"},{"id":36989,"url":"https://patchwork.plctlab.org/api/1.2/patches/36989/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221227194756.448332-1-hjl.tools@gmail.com/","msgid":"<20221227194756.448332-1-hjl.tools@gmail.com>","list_archive_url":null,"date":"2022-12-27T19:47:56","name":"x86-64: Allocate input section memory if needed","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221227194756.448332-1-hjl.tools@gmail.com/mbox/"},{"id":37100,"url":"https://patchwork.plctlab.org/api/1.2/patches/37100/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221228040649.810-1-shihua@iscas.ac.cn/","msgid":"<20221228040649.810-1-shihua@iscas.ac.cn>","list_archive_url":null,"date":"2022-12-28T04:06:49","name":"[RFC] Support RV64-ILP32","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221228040649.810-1-shihua@iscas.ac.cn/mbox/"},{"id":37293,"url":"https://patchwork.plctlab.org/api/1.2/patches/37293/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e6156a39f6be66c559443e890d8a3a9a592e63d6.1672285661.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-12-29T03:51:44","name":"RISC-V: Make T-Head testing pattern more generic","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e6156a39f6be66c559443e890d8a3a9a592e63d6.1672285661.git.research_trasio@irq.a4lg.com/mbox/"},{"id":37294,"url":"https://patchwork.plctlab.org/api/1.2/patches/37294/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c509db05e4f1500736f4de994ed2aede544234d5.1672286099.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-12-29T03:55:05","name":"[1/2] RISC-V: Simplify riscv_csr_address logic on state enable extensions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c509db05e4f1500736f4de994ed2aede544234d5.1672286099.git.research_trasio@irq.a4lg.com/mbox/"},{"id":37295,"url":"https://patchwork.plctlab.org/api/1.2/patches/37295/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e5ff96022a4144e49d9151946a2e6cb2bd7b8419.1672286099.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-12-29T03:55:06","name":"[2/2] RISC-V: Reorder CSR classes related to '\''Ssstateen'\''","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e5ff96022a4144e49d9151946a2e6cb2bd7b8419.1672286099.git.research_trasio@irq.a4lg.com/mbox/"},{"id":37548,"url":"https://patchwork.plctlab.org/api/1.2/patches/37548/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221230024055.31841-1-mark@harmstone.com/","msgid":"<20221230024055.31841-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-12-30T02:40:48","name":"[1/8] ld: Rename aarch64pe emulation target to arm64pe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221230024055.31841-1-mark@harmstone.com/mbox/"},{"id":37549,"url":"https://patchwork.plctlab.org/api/1.2/patches/37549/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221230024055.31841-2-mark@harmstone.com/","msgid":"<20221230024055.31841-2-mark@harmstone.com>","list_archive_url":null,"date":"2022-12-30T02:40:49","name":"[2/8] Fix size of external_reloc for pe-aarch64","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221230024055.31841-2-mark@harmstone.com/mbox/"},{"id":37551,"url":"https://patchwork.plctlab.org/api/1.2/patches/37551/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221230024055.31841-3-mark@harmstone.com/","msgid":"<20221230024055.31841-3-mark@harmstone.com>","list_archive_url":null,"date":"2022-12-30T02:40:50","name":"[3/8] Skip ELF-specific tests when targeting pe-aarch64","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221230024055.31841-3-mark@harmstone.com/mbox/"},{"id":37550,"url":"https://patchwork.plctlab.org/api/1.2/patches/37550/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221230024055.31841-4-mark@harmstone.com/","msgid":"<20221230024055.31841-4-mark@harmstone.com>","list_archive_url":null,"date":"2022-12-30T02:40:51","name":"[4/8] Skip big-obj test for pe-aarch64","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221230024055.31841-4-mark@harmstone.com/mbox/"},{"id":37554,"url":"https://patchwork.plctlab.org/api/1.2/patches/37554/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221230024055.31841-5-mark@harmstone.com/","msgid":"<20221230024055.31841-5-mark@harmstone.com>","list_archive_url":null,"date":"2022-12-30T02:40:52","name":"[5/8] Add pe-aarch64 relocations","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221230024055.31841-5-mark@harmstone.com/mbox/"},{"id":37553,"url":"https://patchwork.plctlab.org/api/1.2/patches/37553/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221230024055.31841-6-mark@harmstone.com/","msgid":"<20221230024055.31841-6-mark@harmstone.com>","list_archive_url":null,"date":"2022-12-30T02:40:53","name":"[6/8] Add .secrel32 for pe-aarch64","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221230024055.31841-6-mark@harmstone.com/mbox/"},{"id":37555,"url":"https://patchwork.plctlab.org/api/1.2/patches/37555/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221230024055.31841-7-mark@harmstone.com/","msgid":"<20221230024055.31841-7-mark@harmstone.com>","list_archive_url":null,"date":"2022-12-30T02:40:54","name":"[7/8] Add aarch64-w64-mingw32 target","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221230024055.31841-7-mark@harmstone.com/mbox/"},{"id":37552,"url":"https://patchwork.plctlab.org/api/1.2/patches/37552/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221230024055.31841-8-mark@harmstone.com/","msgid":"<20221230024055.31841-8-mark@harmstone.com>","list_archive_url":null,"date":"2022-12-30T02:40:55","name":"[8/8] gas: Restore tc_pe_dwarf2_emit_offset for pe-aarch64","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221230024055.31841-8-mark@harmstone.com/mbox/"},{"id":37656,"url":"https://patchwork.plctlab.org/api/1.2/patches/37656/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y67RWv4jQ93m2JzK@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-12-30T11:54:02","name":"PR29948, heap-buffer-overflow in display_debug_lines_decoded","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y67RWv4jQ93m2JzK@squeak.grove.modra.org/mbox/"},{"id":37836,"url":"https://patchwork.plctlab.org/api/1.2/patches/37836/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/87v8lr93ws.fsf@redhat.com/","msgid":"<87v8lr93ws.fsf@redhat.com>","list_archive_url":null,"date":"2022-12-31T12:02:59","name":"Commit: Sync libiberty sources with gcc mainline","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/87v8lr93ws.fsf@redhat.com/mbox/"}],"public":true,"mbox":"https://patchwork.plctlab.org/bundle/patchwork-bot/binutils-gdb_2022-12/mbox/"},{"id":13,"url":"https://patchwork.plctlab.org/api/1.2/bundles/13/","web_url":"https://patchwork.plctlab.org/bundle/patchwork-bot/binutils-gdb_2023-01/","project":{"id":2,"url":"https://patchwork.plctlab.org/api/1.2/projects/2/","name":"binutils-gdb","link_name":"binutils-gdb","list_id":"binutils.sourceware.org","list_email":"binutils@sourceware.org","web_url":"https://github.com/wangliu-iscas/Patchwork-Bundles/blob/main/binutils-gdb.md","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"name":"binutils-gdb_2023-01","owner":{"id":3,"url":"https://patchwork.plctlab.org/api/1.2/users/3/","username":"patchwork-bot","first_name":"","last_name":"","email":"ouuuleilei@gmail.com"},"patches":[{"id":37894,"url":"https://patchwork.plctlab.org/api/1.2/patches/37894/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221231205546.14330-1-mark@harmstone.com/","msgid":"<20221231205546.14330-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-12-31T20:55:46","name":"Avoid unaligned pointer reads in PEP .idata section","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221231205546.14330-1-mark@harmstone.com/mbox/"},{"id":37945,"url":"https://patchwork.plctlab.org/api/1.2/patches/37945/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y7FukAKCvmmsn7pb@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-01-01T11:29:20","name":"Update etc/update-copyright.py","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y7FukAKCvmmsn7pb@squeak.grove.modra.org/mbox/"},{"id":37992,"url":"https://patchwork.plctlab.org/api/1.2/patches/37992/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y7JSKtcK8QTgIQY5@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-01-02T03:40:26","name":"obsolete target tidy","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y7JSKtcK8QTgIQY5@squeak.grove.modra.org/mbox/"},{"id":38142,"url":"https://patchwork.plctlab.org/api/1.2/patches/38142/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230102160857.ABA7F2042C@pchp3.se.axis.com/","msgid":"<20230102160857.ABA7F2042C@pchp3.se.axis.com>","list_archive_url":null,"date":"2023-01-02T16:08:57","name":"Fix ld bloat introduced between binutils-2.38 and 2.39","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230102160857.ABA7F2042C@pchp3.se.axis.com/mbox/"},{"id":38247,"url":"https://patchwork.plctlab.org/api/1.2/patches/38247/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230103024119.12F182042C@pchp3.se.axis.com/","msgid":"<20230103024119.12F182042C@pchp3.se.axis.com>","list_archive_url":null,"date":"2023-01-03T02:41:19","name":"ARM: Fix ld bloat introduced between binutils-2.38 and 2.39","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230103024119.12F182042C@pchp3.se.axis.com/mbox/"},{"id":38355,"url":"https://patchwork.plctlab.org/api/1.2/patches/38355/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230103102251.89478-1-christophe.lyon@arm.com/","msgid":"<20230103102251.89478-1-christophe.lyon@arm.com>","list_archive_url":null,"date":"2023-01-03T10:22:50","name":"[arm] Fix PR18841 ifunc relocation ordering","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230103102251.89478-1-christophe.lyon@arm.com/mbox/"},{"id":38356,"url":"https://patchwork.plctlab.org/api/1.2/patches/38356/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230103102251.89478-2-christophe.lyon@arm.com/","msgid":"<20230103102251.89478-2-christophe.lyon@arm.com>","list_archive_url":null,"date":"2023-01-03T10:22:51","name":"[arm] Skip ld/pr23169 test on arm.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230103102251.89478-2-christophe.lyon@arm.com/mbox/"},{"id":38431,"url":"https://patchwork.plctlab.org/api/1.2/patches/38431/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230103135330.1225218-1-chigot@adacore.com/","msgid":"<20230103135330.1225218-1-chigot@adacore.com>","list_archive_url":null,"date":"2023-01-03T13:53:30","name":"configure: remove dependencies on gmp and mpfr when gdb is disabled","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230103135330.1225218-1-chigot@adacore.com/mbox/"},{"id":38506,"url":"https://patchwork.plctlab.org/api/1.2/patches/38506/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230103162543.2412854-1-chigot@adacore.com/","msgid":"<20230103162543.2412854-1-chigot@adacore.com>","list_archive_url":null,"date":"2023-01-03T16:25:43","name":"[v2] configure: remove dependencies on gmp and mpfr when gdb is disabled","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230103162543.2412854-1-chigot@adacore.com/mbox/"},{"id":38694,"url":"https://patchwork.plctlab.org/api/1.2/patches/38694/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230103214931.3320223-1-dilfridge@gentoo.org/","msgid":"<20230103214931.3320223-1-dilfridge@gentoo.org>","list_archive_url":null,"date":"2023-01-03T21:49:31","name":"ld testsuite: un-xfail pr19719 tests on aarch64, seems to succeed now","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230103214931.3320223-1-dilfridge@gentoo.org/mbox/"},{"id":38658,"url":"https://patchwork.plctlab.org/api/1.2/patches/38658/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230103215722.616744-1-jcmvbkbc@gmail.com/","msgid":"<20230103215722.616744-1-jcmvbkbc@gmail.com>","list_archive_url":null,"date":"2023-01-03T21:57:22","name":"[COMMITTED] opcodes: xtensa: implement styled disassembly","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230103215722.616744-1-jcmvbkbc@gmail.com/mbox/"},{"id":38659,"url":"https://patchwork.plctlab.org/api/1.2/patches/38659/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230103215746.616794-1-jcmvbkbc@gmail.com/","msgid":"<20230103215746.616794-1-jcmvbkbc@gmail.com>","list_archive_url":null,"date":"2023-01-03T21:57:46","name":"[COMMITTED] opcodes: xtensa: fix jump visualization for FLIX","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230103215746.616794-1-jcmvbkbc@gmail.com/mbox/"},{"id":38714,"url":"https://patchwork.plctlab.org/api/1.2/patches/38714/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230104011831.965647-1-indu.bhagat@oracle.com/","msgid":"<20230104011831.965647-1-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-01-04T01:18:31","name":"MAINTAINERS: add myself as maintainer of libsframe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230104011831.965647-1-indu.bhagat@oracle.com/mbox/"},{"id":38733,"url":"https://patchwork.plctlab.org/api/1.2/patches/38733/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230104041219.794237-1-guillermo.e.martinez@oracle.com/","msgid":"<20230104041219.794237-1-guillermo.e.martinez@oracle.com>","list_archive_url":null,"date":"2023-01-04T04:12:19","name":"Fix sim/testsuite/bpf due to linker warnings","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230104041219.794237-1-guillermo.e.martinez@oracle.com/mbox/"},{"id":38743,"url":"https://patchwork.plctlab.org/api/1.2/patches/38743/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230104055936.1130680-1-aurelien@aurel32.net/","msgid":"<20230104055936.1130680-1-aurelien@aurel32.net>","list_archive_url":null,"date":"2023-01-04T05:59:36","name":"RISC-V: fix JAL aliases ordering in opcode table","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230104055936.1130680-1-aurelien@aurel32.net/mbox/"},{"id":38774,"url":"https://patchwork.plctlab.org/api/1.2/patches/38774/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230104065611.377771-1-indu.bhagat@oracle.com/","msgid":"<20230104065611.377771-1-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-01-04T06:56:11","name":"libsframe: adjust an incorrect check in flip_sframe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230104065611.377771-1-indu.bhagat@oracle.com/mbox/"},{"id":38920,"url":"https://patchwork.plctlab.org/api/1.2/patches/38920/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y7V+MNgHYTpMBNw5@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-01-04T13:25:04","name":"addr2line out of memory on fuzzed file","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y7V+MNgHYTpMBNw5@squeak.grove.modra.org/mbox/"},{"id":38921,"url":"https://patchwork.plctlab.org/api/1.2/patches/38921/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y7V+U0bOlfYE++6E@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-01-04T13:25:39","name":"asan: segv in parse_module","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y7V+U0bOlfYE++6E@squeak.grove.modra.org/mbox/"},{"id":38922,"url":"https://patchwork.plctlab.org/api/1.2/patches/38922/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y7V+g16MZQvQAYgv@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-01-04T13:26:27","name":"fuzzed file timeout","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y7V+g16MZQvQAYgv@squeak.grove.modra.org/mbox/"},{"id":39067,"url":"https://patchwork.plctlab.org/api/1.2/patches/39067/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230104191414.149668-1-hjl.tools@gmail.com/","msgid":"<20230104191414.149668-1-hjl.tools@gmail.com>","list_archive_url":null,"date":"2023-01-04T19:14:14","name":"x86: Remove duplicated I386_PCREL_TYPE_P/X86_64_PCREL_TYPE_P","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230104191414.149668-1-hjl.tools@gmail.com/mbox/"},{"id":39123,"url":"https://patchwork.plctlab.org/api/1.2/patches/39123/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230104214109.51006-1-guillermo.e.martinez@oracle.com/","msgid":"<20230104214109.51006-1-guillermo.e.martinez@oracle.com>","list_archive_url":null,"date":"2023-01-04T21:41:09","name":"[PATCHv2] Fix sim/testsuite/bpf due to linker warnings","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230104214109.51006-1-guillermo.e.martinez@oracle.com/mbox/"},{"id":39188,"url":"https://patchwork.plctlab.org/api/1.2/patches/39188/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230105002743.25019-1-mark@harmstone.com/","msgid":"<20230105002743.25019-1-mark@harmstone.com>","list_archive_url":null,"date":"2023-01-05T00:27:43","name":"ld/testsuite: Fix test failures in pe.exp caused by 8819b236","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230105002743.25019-1-mark@harmstone.com/mbox/"},{"id":39795,"url":"https://patchwork.plctlab.org/api/1.2/patches/39795/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230105210542.3573076-1-maskray@google.com/","msgid":"<20230105210542.3573076-1-maskray@google.com>","list_archive_url":null,"date":"2023-01-05T21:05:42","name":"ld: Allow R_X86_64_GOTPCREL for call *__tls_get_addr@GOTPCREL(%rip)","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230105210542.3573076-1-maskray@google.com/mbox/"},{"id":39834,"url":"https://patchwork.plctlab.org/api/1.2/patches/39834/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230105230742.1097314-1-maskray@google.com/","msgid":"<20230105230742.1097314-1-maskray@google.com>","list_archive_url":null,"date":"2023-01-05T23:07:42","name":"ld: Allow R_386_GOT32 for call *__tls_get_addr@GOT(%reg)","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230105230742.1097314-1-maskray@google.com/mbox/"},{"id":39890,"url":"https://patchwork.plctlab.org/api/1.2/patches/39890/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230106012509.7918-1-mark@harmstone.com/","msgid":"<20230106012509.7918-1-mark@harmstone.com>","list_archive_url":null,"date":"2023-01-06T01:25:03","name":"[1/7] Fix size of external_reloc for pe-aarch64","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230106012509.7918-1-mark@harmstone.com/mbox/"},{"id":39891,"url":"https://patchwork.plctlab.org/api/1.2/patches/39891/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230106012509.7918-2-mark@harmstone.com/","msgid":"<20230106012509.7918-2-mark@harmstone.com>","list_archive_url":null,"date":"2023-01-06T01:25:04","name":"[2/7] Skip ELF-specific tests when targeting pe-aarch64","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230106012509.7918-2-mark@harmstone.com/mbox/"},{"id":39892,"url":"https://patchwork.plctlab.org/api/1.2/patches/39892/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230106012509.7918-3-mark@harmstone.com/","msgid":"<20230106012509.7918-3-mark@harmstone.com>","list_archive_url":null,"date":"2023-01-06T01:25:05","name":"[3/7] Skip big-obj test for pe-aarch64","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230106012509.7918-3-mark@harmstone.com/mbox/"},{"id":39896,"url":"https://patchwork.plctlab.org/api/1.2/patches/39896/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230106012509.7918-4-mark@harmstone.com/","msgid":"<20230106012509.7918-4-mark@harmstone.com>","list_archive_url":null,"date":"2023-01-06T01:25:06","name":"[4/7] Add pe-aarch64 relocations","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230106012509.7918-4-mark@harmstone.com/mbox/"},{"id":39894,"url":"https://patchwork.plctlab.org/api/1.2/patches/39894/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230106012509.7918-5-mark@harmstone.com/","msgid":"<20230106012509.7918-5-mark@harmstone.com>","list_archive_url":null,"date":"2023-01-06T01:25:07","name":"[5/7] Add .secrel32 for pe-aarch64","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230106012509.7918-5-mark@harmstone.com/mbox/"},{"id":39893,"url":"https://patchwork.plctlab.org/api/1.2/patches/39893/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230106012509.7918-6-mark@harmstone.com/","msgid":"<20230106012509.7918-6-mark@harmstone.com>","list_archive_url":null,"date":"2023-01-06T01:25:08","name":"[6/7] Add aarch64-w64-mingw32 target","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230106012509.7918-6-mark@harmstone.com/mbox/"},{"id":39895,"url":"https://patchwork.plctlab.org/api/1.2/patches/39895/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230106012509.7918-7-mark@harmstone.com/","msgid":"<20230106012509.7918-7-mark@harmstone.com>","list_archive_url":null,"date":"2023-01-06T01:25:09","name":"[7/7] gas: Restore tc_pe_dwarf2_emit_offset for pe-aarch64","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230106012509.7918-7-mark@harmstone.com/mbox/"},{"id":39967,"url":"https://patchwork.plctlab.org/api/1.2/patches/39967/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230106064053.984817-1-indu.bhagat@oracle.com/","msgid":"<20230106064053.984817-1-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-01-06T06:40:53","name":"sframe: fix the defined SFRAME_FRE_TYPE_*_LIMIT constants","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230106064053.984817-1-indu.bhagat@oracle.com/mbox/"},{"id":39979,"url":"https://patchwork.plctlab.org/api/1.2/patches/39979/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230106075816.387489-1-guillermo.e.martinez@oracle.com/","msgid":"<20230106075816.387489-1-guillermo.e.martinez@oracle.com>","list_archive_url":null,"date":"2023-01-06T07:58:16","name":"bpf: fix error conversion from long unsigned int to unsigned int [-Werror=overflow]","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230106075816.387489-1-guillermo.e.martinez@oracle.com/mbox/"},{"id":40061,"url":"https://patchwork.plctlab.org/api/1.2/patches/40061/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b7e9975b-086f-a9f6-ab6b-0181d50187e1@suse.com/","msgid":"","list_archive_url":null,"date":"2023-01-06T09:33:00","name":"ld: yet another PDB build fix (or workaround)","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b7e9975b-086f-a9f6-ab6b-0181d50187e1@suse.com/mbox/"},{"id":40085,"url":"https://patchwork.plctlab.org/api/1.2/patches/40085/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y7f7RLzDodzChR88@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-01-06T10:43:16","name":"Make coff backend data read-only","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y7f7RLzDodzChR88@squeak.grove.modra.org/mbox/"},{"id":40086,"url":"https://patchwork.plctlab.org/api/1.2/patches/40086/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y7f7chtgwRfAVNME@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-01-06T10:44:02","name":"Tidy pe flag in coff_data","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y7f7chtgwRfAVNME@squeak.grove.modra.org/mbox/"},{"id":40087,"url":"https://patchwork.plctlab.org/api/1.2/patches/40087/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y7f7lGQlMvLz157a@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-01-06T10:44:36","name":"Fix an aout memory leak","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y7f7lGQlMvLz157a@squeak.grove.modra.org/mbox/"},{"id":40114,"url":"https://patchwork.plctlab.org/api/1.2/patches/40114/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6c9f38b9-c582-3a1a-55ce-bb9966940a80@suse.com/","msgid":"<6c9f38b9-c582-3a1a-55ce-bb9966940a80@suse.com>","list_archive_url":null,"date":"2023-01-06T12:34:46","name":"gas/RISC-V: adjust assembler for opcode table re-ordering","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6c9f38b9-c582-3a1a-55ce-bb9966940a80@suse.com/mbox/"},{"id":40415,"url":"https://patchwork.plctlab.org/api/1.2/patches/40415/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230107154743.624854-1-guillermo.e.martinez@oracle.com/","msgid":"<20230107154743.624854-1-guillermo.e.martinez@oracle.com>","list_archive_url":null,"date":"2023-01-07T15:47:43","name":"bpf: fix error conversion from long unsigned int to unsigned int [-Werror=overflow]","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230107154743.624854-1-guillermo.e.martinez@oracle.com/mbox/"},{"id":40698,"url":"https://patchwork.plctlab.org/api/1.2/patches/40698/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230109083526.74448-1-mengqinggang@loongson.cn/","msgid":"<20230109083526.74448-1-mengqinggang@loongson.cn>","list_archive_url":null,"date":"2023-01-09T08:35:26","name":"LoongArch: ld: Fix hidden ifunc symbol linker error bug.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230109083526.74448-1-mengqinggang@loongson.cn/mbox/"},{"id":41215,"url":"https://patchwork.plctlab.org/api/1.2/patches/41215/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y7ygyYa8VydFJqaD@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-01-09T23:18:33","name":"Move bfd_init to bfd.c","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y7ygyYa8VydFJqaD@squeak.grove.modra.org/mbox/"},{"id":41216,"url":"https://patchwork.plctlab.org/api/1.2/patches/41216/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y7yg79B/YO6FUkMB@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-01-09T23:19:11","name":"Move mips_refhi_list to bfd tdata","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y7yg79B/YO6FUkMB@squeak.grove.modra.org/mbox/"},{"id":41226,"url":"https://patchwork.plctlab.org/api/1.2/patches/41226/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y7ylp96AC5XxPRgq@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-01-09T23:39:19","name":"peXXigen.c sanity checks","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y7ylp96AC5XxPRgq@squeak.grove.modra.org/mbox/"},{"id":41227,"url":"https://patchwork.plctlab.org/api/1.2/patches/41227/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y7yl1F46NAHWkWo5@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-01-09T23:40:04","name":"Set dwarf2 stash pointer earlier","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y7yl1F46NAHWkWo5@squeak.grove.modra.org/mbox/"},{"id":41452,"url":"https://patchwork.plctlab.org/api/1.2/patches/41452/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230110130050.366404-2-nick.alcock@oracle.com/","msgid":"<20230110130050.366404-2-nick.alcock@oracle.com>","list_archive_url":null,"date":"2023-01-10T13:00:48","name":"[v2,1/3] ctf: fix various dreadful typos in the ctf_archive format comments","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230110130050.366404-2-nick.alcock@oracle.com/mbox/"},{"id":41453,"url":"https://patchwork.plctlab.org/api/1.2/patches/41453/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230110130050.366404-3-nick.alcock@oracle.com/","msgid":"<20230110130050.366404-3-nick.alcock@oracle.com>","list_archive_url":null,"date":"2023-01-10T13:00:49","name":"[v2,2/3] libctf: skip the testsuite from inside dejagnu","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230110130050.366404-3-nick.alcock@oracle.com/mbox/"},{"id":41454,"url":"https://patchwork.plctlab.org/api/1.2/patches/41454/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230110130050.366404-4-nick.alcock@oracle.com/","msgid":"<20230110130050.366404-4-nick.alcock@oracle.com>","list_archive_url":null,"date":"2023-01-10T13:00:50","name":"[v2,3/3] libctf: ctf-link outdated input check faulty","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230110130050.366404-4-nick.alcock@oracle.com/mbox/"},{"id":41470,"url":"https://patchwork.plctlab.org/api/1.2/patches/41470/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230110133534.5295-1-stefansf@linux.ibm.com/","msgid":"<20230110133534.5295-1-stefansf@linux.ibm.com>","list_archive_url":null,"date":"2023-01-10T13:35:35","name":"IBM zSystems: Fix offset relative to static TLS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230110133534.5295-1-stefansf@linux.ibm.com/mbox/"},{"id":41571,"url":"https://patchwork.plctlab.org/api/1.2/patches/41571/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230110182745.3641128-1-indu.bhagat@oracle.com/","msgid":"<20230110182745.3641128-1-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-01-10T18:27:45","name":"libsframe: replace an strncat with strcat","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230110182745.3641128-1-indu.bhagat@oracle.com/mbox/"},{"id":41761,"url":"https://patchwork.plctlab.org/api/1.2/patches/41761/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y75R4sYOPg/8UuHm@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-01-11T06:06:26","name":"now_seg after closing output file","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y75R4sYOPg/8UuHm@squeak.grove.modra.org/mbox/"},{"id":41817,"url":"https://patchwork.plctlab.org/api/1.2/patches/41817/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y751L9gX14jBBlO0@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-01-11T08:37:03","name":"Tidy some global bfd state used by gas","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y751L9gX14jBBlO0@squeak.grove.modra.org/mbox/"},{"id":41974,"url":"https://patchwork.plctlab.org/api/1.2/patches/41974/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y762S0diPNqwWu1a@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-01-11T13:14:51","name":"Fix XPASS weak symbols on x86_64-mingw32","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y762S0diPNqwWu1a@squeak.grove.modra.org/mbox/"},{"id":42134,"url":"https://patchwork.plctlab.org/api/1.2/patches/42134/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230111183204.11600-1-mark@harmstone.com/","msgid":"<20230111183204.11600-1-mark@harmstone.com>","list_archive_url":null,"date":"2023-01-11T18:32:04","name":"Use subsystem to distinguish between pei-arm-little and pei-arm-wince-little","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230111183204.11600-1-mark@harmstone.com/mbox/"},{"id":42262,"url":"https://patchwork.plctlab.org/api/1.2/patches/42262/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y7+tQPYaY/skpLIf@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-01-12T06:48:32","name":"Remove myself as hppa32 maintainer","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y7+tQPYaY/skpLIf@squeak.grove.modra.org/mbox/"},{"id":42263,"url":"https://patchwork.plctlab.org/api/1.2/patches/42263/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y7+tkeiBByVJdca3@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-01-12T06:49:53","name":"Use __func__ rather than __FUNCTION__","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y7+tkeiBByVJdca3@squeak.grove.modra.org/mbox/"},{"id":42799,"url":"https://patchwork.plctlab.org/api/1.2/patches/42799/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230112205654.3456561-1-vladimir.mezentsev@oracle.com/","msgid":"<20230112205654.3456561-1-vladimir.mezentsev@oracle.com>","list_archive_url":null,"date":"2023-01-12T20:56:54","name":"gprofng: PR29987 bfd/archive.c:1447: undefined reference to `filename_ncmp'\''","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230112205654.3456561-1-vladimir.mezentsev@oracle.com/mbox/"},{"id":43131,"url":"https://patchwork.plctlab.org/api/1.2/patches/43131/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/95936261-d824-9128-1be9-ba7dfe12b042@suse.com/","msgid":"<95936261-d824-9128-1be9-ba7dfe12b042@suse.com>","list_archive_url":null,"date":"2023-01-13T10:19:19","name":"[1/3] RISC-V: prefer SLT{,U} aliases for SLTI{,U}","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/95936261-d824-9128-1be9-ba7dfe12b042@suse.com/mbox/"},{"id":43133,"url":"https://patchwork.plctlab.org/api/1.2/patches/43133/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/63fa0796-59e6-6429-6c86-b8707cc9f8d9@suse.com/","msgid":"<63fa0796-59e6-6429-6c86-b8707cc9f8d9@suse.com>","list_archive_url":null,"date":"2023-01-13T10:19:51","name":"[2/3] RISC-V: move OR and XOR aliases down","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/63fa0796-59e6-6429-6c86-b8707cc9f8d9@suse.com/mbox/"},{"id":43134,"url":"https://patchwork.plctlab.org/api/1.2/patches/43134/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/448243b9-8134-f981-8e66-635790d4e680@suse.com/","msgid":"<448243b9-8134-f981-8e66-635790d4e680@suse.com>","list_archive_url":null,"date":"2023-01-13T10:20:23","name":"[3/3] RISC-V: prefer FSRM/FSFLAGS aliases for FSRMI/FSFLAGSI","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/448243b9-8134-f981-8e66-635790d4e680@suse.com/mbox/"},{"id":43166,"url":"https://patchwork.plctlab.org/api/1.2/patches/43166/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/55dd0365-1b8c-45d0-cb85-fc8ebdc2ac21@suse.com/","msgid":"<55dd0365-1b8c-45d0-cb85-fc8ebdc2ac21@suse.com>","list_archive_url":null,"date":"2023-01-13T11:05:43","name":"[1/8] x86: abstract out obtaining of a template'\''s mnemonic","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/55dd0365-1b8c-45d0-cb85-fc8ebdc2ac21@suse.com/mbox/"},{"id":43167,"url":"https://patchwork.plctlab.org/api/1.2/patches/43167/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fa681978-5ee6-16ba-3f08-958f6d1cf805@suse.com/","msgid":"","list_archive_url":null,"date":"2023-01-13T11:06:32","name":"[1/8] x86: move insn mnemonics to a separate table","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fa681978-5ee6-16ba-3f08-958f6d1cf805@suse.com/mbox/"},{"id":43168,"url":"https://patchwork.plctlab.org/api/1.2/patches/43168/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d87c0ed5-4678-d8ea-9744-7447ff82a843@suse.com/","msgid":"","list_archive_url":null,"date":"2023-01-13T11:07:24","name":"[3/8] x86: re-use insn mnemonic strings as much as possible","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d87c0ed5-4678-d8ea-9744-7447ff82a843@suse.com/mbox/"},{"id":43169,"url":"https://patchwork.plctlab.org/api/1.2/patches/43169/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8f43bf06-9323-8838-bcdc-bfbf9a850ae2@suse.com/","msgid":"<8f43bf06-9323-8838-bcdc-bfbf9a850ae2@suse.com>","list_archive_url":null,"date":"2023-01-13T11:07:46","name":"[4/8] x86: absorb allocation in i386-gen","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8f43bf06-9323-8838-bcdc-bfbf9a850ae2@suse.com/mbox/"},{"id":43170,"url":"https://patchwork.plctlab.org/api/1.2/patches/43170/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c60483a9-14fc-f2f4-0185-80c2510e45a5@suse.com/","msgid":"","list_archive_url":null,"date":"2023-01-13T11:08:33","name":"[5/8] x86: avoid strcmp() in a few places","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c60483a9-14fc-f2f4-0185-80c2510e45a5@suse.com/mbox/"},{"id":43171,"url":"https://patchwork.plctlab.org/api/1.2/patches/43171/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1c763a63-05e0-33e8-c9c4-48a26cbc5db7@suse.com/","msgid":"<1c763a63-05e0-33e8-c9c4-48a26cbc5db7@suse.com>","list_archive_url":null,"date":"2023-01-13T11:10:03","name":"[6/8] x86: embed register names in reg_entry","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1c763a63-05e0-33e8-c9c4-48a26cbc5db7@suse.com/mbox/"},{"id":43172,"url":"https://patchwork.plctlab.org/api/1.2/patches/43172/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8a6f1fce-435a-b8fa-44a3-c7ae2c621968@suse.com/","msgid":"<8a6f1fce-435a-b8fa-44a3-c7ae2c621968@suse.com>","list_archive_url":null,"date":"2023-01-13T11:11:01","name":"[7/8] x86: embed register and alike names in disassembler","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8a6f1fce-435a-b8fa-44a3-c7ae2c621968@suse.com/mbox/"},{"id":43174,"url":"https://patchwork.plctlab.org/api/1.2/patches/43174/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1d538fdf-536a-37b0-556b-b4ca86b0a090@suse.com/","msgid":"<1d538fdf-536a-37b0-556b-b4ca86b0a090@suse.com>","list_archive_url":null,"date":"2023-01-13T11:11:37","name":"[8/8] x86: split i386-gen'\''s opcode hash entry struct","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1d538fdf-536a-37b0-556b-b4ca86b0a090@suse.com/mbox/"},{"id":43288,"url":"https://patchwork.plctlab.org/api/1.2/patches/43288/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230113125454.75744-1-cooper.qu@linux.alibaba.com/","msgid":"<20230113125454.75744-1-cooper.qu@linux.alibaba.com>","list_archive_url":null,"date":"2023-01-13T12:54:54","name":"C-SKY: Fix machine flag.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230113125454.75744-1-cooper.qu@linux.alibaba.com/mbox/"},{"id":43355,"url":"https://patchwork.plctlab.org/api/1.2/patches/43355/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/OS3P286MB2152AC3F96A88680022D57ADF0C29@OS3P286MB2152.JPNP286.PROD.OUTLOOK.COM/","msgid":"","list_archive_url":null,"date":"2023-01-13T14:42:32","name":"libctf: update regexp to allow makeinfo to build document","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/OS3P286MB2152AC3F96A88680022D57ADF0C29@OS3P286MB2152.JPNP286.PROD.OUTLOOK.COM/mbox/"},{"id":43695,"url":"https://patchwork.plctlab.org/api/1.2/patches/43695/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/OS3P286MB2152CCD151694D02E2A84D23F0C39@OS3P286MB2152.JPNP286.PROD.OUTLOOK.COM/","msgid":"","list_archive_url":null,"date":"2023-01-14T04:23:26","name":"[v2] libctf: update regexp to allow makeinfo to build document","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/OS3P286MB2152CCD151694D02E2A84D23F0C39@OS3P286MB2152.JPNP286.PROD.OUTLOOK.COM/mbox/"},{"id":44089,"url":"https://patchwork.plctlab.org/api/1.2/patches/44089/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y8U25YxsSHWBz8of@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-01-16T11:37:09","name":"PR29991, MicroMIPS flag erased after align directives","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y8U25YxsSHWBz8of@squeak.grove.modra.org/mbox/"},{"id":44107,"url":"https://patchwork.plctlab.org/api/1.2/patches/44107/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y8VJCZte0qnkPRWk@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-01-16T12:54:33","name":"COFF CALC_ADDEND comment","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y8VJCZte0qnkPRWk@squeak.grove.modra.org/mbox/"},{"id":44109,"url":"https://patchwork.plctlab.org/api/1.2/patches/44109/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y8VJdIvu7DGz4i7I@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-01-16T12:56:20","name":"Leftover hack from i960-coff","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y8VJdIvu7DGz4i7I@squeak.grove.modra.org/mbox/"},{"id":44111,"url":"https://patchwork.plctlab.org/api/1.2/patches/44111/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y8VJxpkPeEvO360+@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-01-16T12:57:42","name":"Tidy gas/expr.c static state","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y8VJxpkPeEvO360+@squeak.grove.modra.org/mbox/"},{"id":44146,"url":"https://patchwork.plctlab.org/api/1.2/patches/44146/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y8VRUsfXY5Vjk5A1@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-01-16T13:29:54","name":"Correct ld-pe/aarch64.d test output","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y8VRUsfXY5Vjk5A1@squeak.grove.modra.org/mbox/"},{"id":44218,"url":"https://patchwork.plctlab.org/api/1.2/patches/44218/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1ff07fee-24f1-7aeb-8fb6-44457af557c4@arm.com/","msgid":"<1ff07fee-24f1-7aeb-8fb6-44457af557c4@arm.com>","list_archive_url":null,"date":"2023-01-16T15:14:42","name":"[PING,1/2] gas: arm: Fix a further IT-predicated vcvt issue in the presense of MVE vcvtn","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1ff07fee-24f1-7aeb-8fb6-44457af557c4@arm.com/mbox/"},{"id":44219,"url":"https://patchwork.plctlab.org/api/1.2/patches/44219/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0b4d01ad-38b9-428e-39af-3ff452f94ef2@arm.com/","msgid":"<0b4d01ad-38b9-428e-39af-3ff452f94ef2@arm.com>","list_archive_url":null,"date":"2023-01-16T15:14:55","name":"[PING,2/2] gas: arm: Change warning message to not reference specific A-class architecture revision","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0b4d01ad-38b9-428e-39af-3ff452f94ef2@arm.com/mbox/"},{"id":44644,"url":"https://patchwork.plctlab.org/api/1.2/patches/44644/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/yddbkmx8kt8.fsf@CeBiTec.Uni-Bielefeld.DE/","msgid":"","list_archive_url":null,"date":"2023-01-17T11:25:23","name":"i386: Don'\''t emit unsupported TLS relocs on Solaris [PR13671]","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/yddbkmx8kt8.fsf@CeBiTec.Uni-Bielefeld.DE/mbox/"},{"id":44718,"url":"https://patchwork.plctlab.org/api/1.2/patches/44718/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230117154125.601189-1-hjl.tools@gmail.com/","msgid":"<20230117154125.601189-1-hjl.tools@gmail.com>","list_archive_url":null,"date":"2023-01-17T15:41:25","name":"ld: Use run_cc_link_tests for PR ld/26391 tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230117154125.601189-1-hjl.tools@gmail.com/mbox/"},{"id":44872,"url":"https://patchwork.plctlab.org/api/1.2/patches/44872/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230118001851.3467920-1-indu.bhagat@oracle.com/","msgid":"<20230118001851.3467920-1-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-01-18T00:18:51","name":"toplevel: Makefile.def: add install-strip dependency on libsframe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230118001851.3467920-1-indu.bhagat@oracle.com/mbox/"},{"id":44975,"url":"https://patchwork.plctlab.org/api/1.2/patches/44975/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230118051136.10243-1-mark@harmstone.com/","msgid":"<20230118051136.10243-1-mark@harmstone.com>","list_archive_url":null,"date":"2023-01-18T05:11:36","name":"ld: Fix ADDR32/64 incorrect outputs in pe-aarch64","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230118051136.10243-1-mark@harmstone.com/mbox/"},{"id":44995,"url":"https://patchwork.plctlab.org/api/1.2/patches/44995/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230118062657.1125934-2-amodra@gmail.com/","msgid":"<20230118062657.1125934-2-amodra@gmail.com>","list_archive_url":null,"date":"2023-01-18T06:26:54","name":"[1/4] howto install_addend","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230118062657.1125934-2-amodra@gmail.com/mbox/"},{"id":44994,"url":"https://patchwork.plctlab.org/api/1.2/patches/44994/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230118062657.1125934-3-amodra@gmail.com/","msgid":"<20230118062657.1125934-3-amodra@gmail.com>","list_archive_url":null,"date":"2023-01-18T06:26:55","name":"[2/4] coff-aarch64.c howtos","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230118062657.1125934-3-amodra@gmail.com/mbox/"},{"id":44999,"url":"https://patchwork.plctlab.org/api/1.2/patches/44999/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230118062657.1125934-4-amodra@gmail.com/","msgid":"<20230118062657.1125934-4-amodra@gmail.com>","list_archive_url":null,"date":"2023-01-18T06:26:56","name":"[3/4] Correct coff-aarch64 howtos and delete unnecessary special functions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230118062657.1125934-4-amodra@gmail.com/mbox/"},{"id":44998,"url":"https://patchwork.plctlab.org/api/1.2/patches/44998/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230118062657.1125934-5-amodra@gmail.com/","msgid":"<20230118062657.1125934-5-amodra@gmail.com>","list_archive_url":null,"date":"2023-01-18T06:26:57","name":"[4/4] The fuzzers have found the reloc special functions in coff-aarch64.c","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230118062657.1125934-5-amodra@gmail.com/mbox/"},{"id":45183,"url":"https://patchwork.plctlab.org/api/1.2/patches/45183/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/87y1q013k1.fsf@redhat.com/","msgid":"<87y1q013k1.fsf@redhat.com>","list_archive_url":null,"date":"2023-01-18T11:32:14","name":"Commit: Improve the performance of objcopy'\''s note merging algorithm","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/87y1q013k1.fsf@redhat.com/mbox/"},{"id":45396,"url":"https://patchwork.plctlab.org/api/1.2/patches/45396/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.LSU.2.20.2301181731360.30340@wotan.suse.de/","msgid":"","list_archive_url":null,"date":"2023-01-18T17:31:54","name":"[1/3] Faster string merging","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.LSU.2.20.2301181731360.30340@wotan.suse.de/mbox/"},{"id":45399,"url":"https://patchwork.plctlab.org/api/1.2/patches/45399/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.LSU.2.20.2301181731590.30340@wotan.suse.de/","msgid":"","list_archive_url":null,"date":"2023-01-18T17:32:09","name":"[2/3] arm32: Fix rodata-merge-map","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.LSU.2.20.2301181731590.30340@wotan.suse.de/mbox/"},{"id":45395,"url":"https://patchwork.plctlab.org/api/1.2/patches/45395/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.LSU.2.20.2301181732140.30340@wotan.suse.de/","msgid":"","list_archive_url":null,"date":"2023-01-18T17:32:24","name":"[3/3] Add testcase ld-elf/merge4","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.LSU.2.20.2301181732140.30340@wotan.suse.de/mbox/"},{"id":45571,"url":"https://patchwork.plctlab.org/api/1.2/patches/45571/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230119035126.1172654-1-raj.khem@gmail.com/","msgid":"<20230119035126.1172654-1-raj.khem@gmail.com>","list_archive_url":null,"date":"2023-01-19T03:51:26","name":"Remove duplicate pe-dll.o entry deom targ_extra_ofiles","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230119035126.1172654-1-raj.khem@gmail.com/mbox/"},{"id":45616,"url":"https://patchwork.plctlab.org/api/1.2/patches/45616/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y8juE1B+0XLFwkuv@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-01-19T07:15:31","name":"PR 30022, concurrent builds can fail","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y8juE1B+0XLFwkuv@squeak.grove.modra.org/mbox/"},{"id":45640,"url":"https://patchwork.plctlab.org/api/1.2/patches/45640/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y8j634999Uh3otCN@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-01-19T08:10:07","name":"Reinitialise macro_nest","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y8j634999Uh3otCN@squeak.grove.modra.org/mbox/"},{"id":45960,"url":"https://patchwork.plctlab.org/api/1.2/patches/45960/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230119205932.3025258-1-indu.bhagat@oracle.com/","msgid":"<20230119205932.3025258-1-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-01-19T20:59:32","name":"[COMMITTED] libsframe: Use AM_SILENT_RULES macro in configure.ac","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230119205932.3025258-1-indu.bhagat@oracle.com/mbox/"},{"id":45961,"url":"https://patchwork.plctlab.org/api/1.2/patches/45961/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y8mwO5KmTqXAtFhC@fedora/","msgid":"","list_archive_url":null,"date":"2023-01-19T21:03:55","name":"Add OpenBSD ARM GAS support.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y8mwO5KmTqXAtFhC@fedora/mbox/"},{"id":46019,"url":"https://patchwork.plctlab.org/api/1.2/patches/46019/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230119214728.3208371-1-indu.bhagat@oracle.com/","msgid":"<20230119214728.3208371-1-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-01-19T21:47:28","name":"doc: sframe: fix some warnings","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230119214728.3208371-1-indu.bhagat@oracle.com/mbox/"},{"id":46256,"url":"https://patchwork.plctlab.org/api/1.2/patches/46256/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/98a5c1d5-00c9-75b3-db8c-019e056d720c@suse.com/","msgid":"<98a5c1d5-00c9-75b3-db8c-019e056d720c@suse.com>","list_archive_url":null,"date":"2023-01-20T09:30:48","name":"[1/2] x86: remove internationalization from i386-gen.c","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/98a5c1d5-00c9-75b3-db8c-019e056d720c@suse.com/mbox/"},{"id":46257,"url":"https://patchwork.plctlab.org/api/1.2/patches/46257/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c2aea3ae-6280-ad3d-2657-ad54f5d5b6bc@suse.com/","msgid":"","list_archive_url":null,"date":"2023-01-20T09:31:27","name":"[2/2] opcodes: suppress internationalization on build helper tools","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c2aea3ae-6280-ad3d-2657-ad54f5d5b6bc@suse.com/mbox/"},{"id":46268,"url":"https://patchwork.plctlab.org/api/1.2/patches/46268/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b8481a70-fa06-a794-ba34-555e712d679f@suse.com/","msgid":"","list_archive_url":null,"date":"2023-01-20T09:55:26","name":"x86/Intel: improve special casing of certain insns","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b8481a70-fa06-a794-ba34-555e712d679f@suse.com/mbox/"},{"id":46274,"url":"https://patchwork.plctlab.org/api/1.2/patches/46274/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1299219c-8f54-8672-a898-3aa1acc2b9ec@suse.com/","msgid":"<1299219c-8f54-8672-a898-3aa1acc2b9ec@suse.com>","list_archive_url":null,"date":"2023-01-20T10:00:13","name":"[1/3] x86: use ModR/M for FPU insns with operands","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1299219c-8f54-8672-a898-3aa1acc2b9ec@suse.com/mbox/"},{"id":46276,"url":"https://patchwork.plctlab.org/api/1.2/patches/46276/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7882acac-b12c-ac86-77f7-063ecd07e799@suse.com/","msgid":"<7882acac-b12c-ac86-77f7-063ecd07e799@suse.com>","list_archive_url":null,"date":"2023-01-20T10:00:35","name":"[2/3] x86: drop dead SSE2AVX-related code","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7882acac-b12c-ac86-77f7-063ecd07e799@suse.com/mbox/"},{"id":46275,"url":"https://patchwork.plctlab.org/api/1.2/patches/46275/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/44a44856-b7b2-5236-9d5e-6c681fc0fb82@suse.com/","msgid":"<44a44856-b7b2-5236-9d5e-6c681fc0fb82@suse.com>","list_archive_url":null,"date":"2023-01-20T10:00:54","name":"[3/3] x86: move reg_operands adjustment","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/44a44856-b7b2-5236-9d5e-6c681fc0fb82@suse.com/mbox/"},{"id":46588,"url":"https://patchwork.plctlab.org/api/1.2/patches/46588/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230120191842.3799467-1-indu.bhagat@oracle.com/","msgid":"<20230120191842.3799467-1-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-01-20T19:18:42","name":"[COMMITTED] Upload SFrame spec files as well","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230120191842.3799467-1-indu.bhagat@oracle.com/mbox/"},{"id":46609,"url":"https://patchwork.plctlab.org/api/1.2/patches/46609/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230120195532.917113-2-christoph.muellner@vrull.eu/","msgid":"<20230120195532.917113-2-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2023-01-20T19:55:27","name":"[RFC,v2,1/6] RISC-V: Add Zvkb ISA extension support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230120195532.917113-2-christoph.muellner@vrull.eu/mbox/"},{"id":46608,"url":"https://patchwork.plctlab.org/api/1.2/patches/46608/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230120195532.917113-3-christoph.muellner@vrull.eu/","msgid":"<20230120195532.917113-3-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2023-01-20T19:55:28","name":"[RFC,v2,2/6] RISC-V: Add Zvkg ISA extension support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230120195532.917113-3-christoph.muellner@vrull.eu/mbox/"},{"id":46612,"url":"https://patchwork.plctlab.org/api/1.2/patches/46612/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230120195532.917113-4-christoph.muellner@vrull.eu/","msgid":"<20230120195532.917113-4-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2023-01-20T19:55:29","name":"[RFC,v2,3/6] RISC-V: Add Zvknh[a,b] ISA extension support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230120195532.917113-4-christoph.muellner@vrull.eu/mbox/"},{"id":46611,"url":"https://patchwork.plctlab.org/api/1.2/patches/46611/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230120195532.917113-5-christoph.muellner@vrull.eu/","msgid":"<20230120195532.917113-5-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2023-01-20T19:55:30","name":"[RFC,v2,4/6] RISC-V: Add Zvkns ISA extension support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230120195532.917113-5-christoph.muellner@vrull.eu/mbox/"},{"id":46610,"url":"https://patchwork.plctlab.org/api/1.2/patches/46610/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230120195532.917113-6-christoph.muellner@vrull.eu/","msgid":"<20230120195532.917113-6-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2023-01-20T19:55:31","name":"[RFC,v2,5/6] RISC-V: Add Zvksed ISA extension support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230120195532.917113-6-christoph.muellner@vrull.eu/mbox/"},{"id":46613,"url":"https://patchwork.plctlab.org/api/1.2/patches/46613/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230120195532.917113-7-christoph.muellner@vrull.eu/","msgid":"<20230120195532.917113-7-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2023-01-20T19:55:32","name":"[RFC,v2,6/6] RISC-V: Add Zvksh ISA extension support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230120195532.917113-7-christoph.muellner@vrull.eu/mbox/"},{"id":46737,"url":"https://patchwork.plctlab.org/api/1.2/patches/46737/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230121002935.1139281-1-philipp.tomsich@vrull.eu/","msgid":"<20230121002935.1139281-1-philipp.tomsich@vrull.eu>","list_archive_url":null,"date":"2023-01-21T00:29:34","name":"[RFC,v1] RISC-V: Support Zicond extension","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230121002935.1139281-1-philipp.tomsich@vrull.eu/mbox/"},{"id":46985,"url":"https://patchwork.plctlab.org/api/1.2/patches/46985/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230122180736.55917-1-och95@yandex.ru/","msgid":"<20230122180736.55917-1-och95@yandex.ru>","list_archive_url":null,"date":"2023-01-22T18:07:36","name":"objdump: Fix relocations objdumping for specific symbol","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230122180736.55917-1-och95@yandex.ru/mbox/"},{"id":47021,"url":"https://patchwork.plctlab.org/api/1.2/patches/47021/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230122235733.4160-1-mark@harmstone.com/","msgid":"<20230122235733.4160-1-mark@harmstone.com>","list_archive_url":null,"date":"2023-01-22T23:57:33","name":"ld: Set default subsystem for arm-pe to IMAGE_SUBSYSTEM_WINDOWS_GUI","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230122235733.4160-1-mark@harmstone.com/mbox/"},{"id":47022,"url":"https://patchwork.plctlab.org/api/1.2/patches/47022/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230123003231.3100-1-mark@harmstone.com/","msgid":"<20230123003231.3100-1-mark@harmstone.com>","list_archive_url":null,"date":"2023-01-23T00:32:31","name":"Add support for secidx relocations to aarch64-w64-mingw32","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230123003231.3100-1-mark@harmstone.com/mbox/"},{"id":47041,"url":"https://patchwork.plctlab.org/api/1.2/patches/47041/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230123045058.449255-1-vladimir.mezentsev@oracle.com/","msgid":"<20230123045058.449255-1-vladimir.mezentsev@oracle.com>","list_archive_url":null,"date":"2023-01-23T04:50:58","name":"gprofng: PR29521 [docs] man pages are not in the release tarball","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230123045058.449255-1-vladimir.mezentsev@oracle.com/mbox/"},{"id":47453,"url":"https://patchwork.plctlab.org/api/1.2/patches/47453/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230123230154.17957-1-mark@harmstone.com/","msgid":"<20230123230154.17957-1-mark@harmstone.com>","list_archive_url":null,"date":"2023-01-23T23:01:54","name":"ld: Add pdb support to aarch64-w64-mingw32","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230123230154.17957-1-mark@harmstone.com/mbox/"},{"id":47706,"url":"https://patchwork.plctlab.org/api/1.2/patches/47706/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230124133641.258195-1-och95@yandex.ru/","msgid":"<20230124133641.258195-1-och95@yandex.ru>","list_archive_url":null,"date":"2023-01-24T13:36:41","name":"Fix emit-relocs for aarch64 gold","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230124133641.258195-1-och95@yandex.ru/mbox/"},{"id":47709,"url":"https://patchwork.plctlab.org/api/1.2/patches/47709/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230124134202.2452845-1-felix.willgerodt@intel.com/","msgid":"<20230124134202.2452845-1-felix.willgerodt@intel.com>","list_archive_url":null,"date":"2023-01-24T13:42:02","name":"[1/1] bfd, gdb: fix missing \"Core was generated by\" when loading a x32 corefile.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230124134202.2452845-1-felix.willgerodt@intel.com/mbox/"},{"id":47742,"url":"https://patchwork.plctlab.org/api/1.2/patches/47742/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4e1ac6f6-8aa5-9605-0969-40f66549c181@suse.com/","msgid":"<4e1ac6f6-8aa5-9605-0969-40f66549c181@suse.com>","list_archive_url":null,"date":"2023-01-24T15:24:32","name":"RISC-V: make C-extension JAL available again for (32-bit) assembly","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4e1ac6f6-8aa5-9605-0969-40f66549c181@suse.com/mbox/"},{"id":47994,"url":"https://patchwork.plctlab.org/api/1.2/patches/47994/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230125012024.6317-1-mark@harmstone.com/","msgid":"<20230125012024.6317-1-mark@harmstone.com>","list_archive_url":null,"date":"2023-01-25T01:20:24","name":"ld/testsuite: Add missing targets to PDB tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230125012024.6317-1-mark@harmstone.com/mbox/"},{"id":48216,"url":"https://patchwork.plctlab.org/api/1.2/patches/48216/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230125170725.386430-1-hjl.tools@gmail.com/","msgid":"<20230125170725.386430-1-hjl.tools@gmail.com>","list_archive_url":null,"date":"2023-01-25T17:07:25","name":"i386: Pass -Wl,--no-as-needed to compiler as needed","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230125170725.386430-1-hjl.tools@gmail.com/mbox/"},{"id":48437,"url":"https://patchwork.plctlab.org/api/1.2/patches/48437/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230126003820.28482-1-mark@harmstone.com/","msgid":"<20230126003820.28482-1-mark@harmstone.com>","list_archive_url":null,"date":"2023-01-26T00:38:19","name":"[1/2] gas: Add CodeView constant for aarch64","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230126003820.28482-1-mark@harmstone.com/mbox/"},{"id":48438,"url":"https://patchwork.plctlab.org/api/1.2/patches/48438/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230126003820.28482-2-mark@harmstone.com/","msgid":"<20230126003820.28482-2-mark@harmstone.com>","list_archive_url":null,"date":"2023-01-26T00:38:20","name":"[2/2] gas/testsuite: Add -gcodeview test for aarch64-w64-mingw32","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230126003820.28482-2-mark@harmstone.com/mbox/"},{"id":48479,"url":"https://patchwork.plctlab.org/api/1.2/patches/48479/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230126032613.2446180-1-vladimir.mezentsev@oracle.com/","msgid":"<20230126032613.2446180-1-vladimir.mezentsev@oracle.com>","list_archive_url":null,"date":"2023-01-26T03:26:13","name":"gprofng: PR30043 libgprofng.so.* are installed to a wrong location","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230126032613.2446180-1-vladimir.mezentsev@oracle.com/mbox/"},{"id":48906,"url":"https://patchwork.plctlab.org/api/1.2/patches/48906/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y9L12EZ4fvTcwQj1@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-01-26T21:51:20","name":"segv in coff_aarch64_addr32nb_reloc","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y9L12EZ4fvTcwQj1@squeak.grove.modra.org/mbox/"},{"id":48909,"url":"https://patchwork.plctlab.org/api/1.2/patches/48909/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y9L2F1zkVoK5AqSW@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-01-26T21:52:23","name":"resolve gas shift expressions with large exponents to zero","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y9L2F1zkVoK5AqSW@squeak.grove.modra.org/mbox/"},{"id":48911,"url":"https://patchwork.plctlab.org/api/1.2/patches/48911/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y9L2O3TbmvhYyhsC@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-01-26T21:52:59","name":"Sanity check dwarf5 form of .file","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y9L2O3TbmvhYyhsC@squeak.grove.modra.org/mbox/"},{"id":48914,"url":"https://patchwork.plctlab.org/api/1.2/patches/48914/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y9L2WRS5mIZy8y43@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-01-26T21:53:29","name":"Free gas/dwarf2dbg.c dirs","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y9L2WRS5mIZy8y43@squeak.grove.modra.org/mbox/"},{"id":49109,"url":"https://patchwork.plctlab.org/api/1.2/patches/49109/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y9N2nkjI4TDjK9+4@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-01-27T07:00:46","name":"gas macro memory leaks","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y9N2nkjI4TDjK9+4@squeak.grove.modra.org/mbox/"},{"id":49110,"url":"https://patchwork.plctlab.org/api/1.2/patches/49110/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y9N2vclgJwnt0fbW@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-01-27T07:01:17","name":"Call bfd_close_all_done in output_file_close","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y9N2vclgJwnt0fbW@squeak.grove.modra.org/mbox/"},{"id":49112,"url":"https://patchwork.plctlab.org/api/1.2/patches/49112/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y9N25JqhQsKIRAtn@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-01-27T07:01:56","name":"Perform cleanup in bfd_close after errors","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y9N25JqhQsKIRAtn@squeak.grove.modra.org/mbox/"},{"id":49111,"url":"https://patchwork.plctlab.org/api/1.2/patches/49111/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y9N3ClMTDGAq08yV@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-01-27T07:02:34","name":"Call bfd_close_all_done in ld_cleanup","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y9N3ClMTDGAq08yV@squeak.grove.modra.org/mbox/"},{"id":49193,"url":"https://patchwork.plctlab.org/api/1.2/patches/49193/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/46af6fa7-e2c2-f771-47e2-05124675b096@suse.com/","msgid":"<46af6fa7-e2c2-f771-47e2-05124675b096@suse.com>","list_archive_url":null,"date":"2023-01-27T11:10:24","name":"x86-64: respect MOVABS when choosing alternative encodings","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/46af6fa7-e2c2-f771-47e2-05124675b096@suse.com/mbox/"},{"id":49266,"url":"https://patchwork.plctlab.org/api/1.2/patches/49266/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3162e04b-3063-ab0c-3596-963132fd6233@suse.com/","msgid":"<3162e04b-3063-ab0c-3596-963132fd6233@suse.com>","list_archive_url":null,"date":"2023-01-27T11:35:04","name":"[1/3] x86: respect {nooptimize} for LEA","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3162e04b-3063-ab0c-3596-963132fd6233@suse.com/mbox/"},{"id":49267,"url":"https://patchwork.plctlab.org/api/1.2/patches/49267/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fd4ad7a1-565d-12ea-c7e0-744d35d77aa6@suse.com/","msgid":"","list_archive_url":null,"date":"2023-01-27T11:35:33","name":"[2/3] x86-64: respect {nooptimize} when building VEX prefix","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fd4ad7a1-565d-12ea-c7e0-744d35d77aa6@suse.com/mbox/"},{"id":49268,"url":"https://patchwork.plctlab.org/api/1.2/patches/49268/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/44b896ee-5b03-1ed6-bda2-8cffec382810@suse.com/","msgid":"<44b896ee-5b03-1ed6-bda2-8cffec382810@suse.com>","list_archive_url":null,"date":"2023-01-27T11:36:02","name":"[3/3] x86: drop LOCK from XCHG when optimizing","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/44b896ee-5b03-1ed6-bda2-8cffec382810@suse.com/mbox/"},{"id":49386,"url":"https://patchwork.plctlab.org/api/1.2/patches/49386/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/dc521fdd-1462-0a4e-6d8e-5fa3f35c82b5@suse.com/","msgid":"","list_archive_url":null,"date":"2023-01-27T13:14:44","name":"RISC-V: don'\''t disassemble unrecognized insns as .byte","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/dc521fdd-1462-0a4e-6d8e-5fa3f35c82b5@suse.com/mbox/"},{"id":50004,"url":"https://patchwork.plctlab.org/api/1.2/patches/50004/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230129153207.944175-1-dimitar@dinux.eu/","msgid":"<20230129153207.944175-1-dimitar@dinux.eu>","list_archive_url":null,"date":"2023-01-29T15:32:06","name":"[1/2] ld: pru: Merge the bss input sections into data","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230129153207.944175-1-dimitar@dinux.eu/mbox/"},{"id":50008,"url":"https://patchwork.plctlab.org/api/1.2/patches/50008/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230129153820.944711-1-dimitar@dinux.eu/","msgid":"<20230129153820.944711-1-dimitar@dinux.eu>","list_archive_url":null,"date":"2023-01-29T15:38:20","name":"[2/2] ld: pru: Add optional section alignments","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230129153820.944711-1-dimitar@dinux.eu/mbox/"},{"id":50144,"url":"https://patchwork.plctlab.org/api/1.2/patches/50144/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c72a27dfcb254b72e542f3a292b387b16add7ef7.1675060487.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2023-01-30T06:35:29","name":"[v2,1/1] RISC-V: Add platform property/capability extensions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c72a27dfcb254b72e542f3a292b387b16add7ef7.1675060487.git.research_trasio@irq.a4lg.com/mbox/"},{"id":50162,"url":"https://patchwork.plctlab.org/api/1.2/patches/50162/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3d42328e6f41cce145063883e5a9f513f4570840.1675062682.git.research_trasio@irq.a4lg.com/","msgid":"<3d42328e6f41cce145063883e5a9f513f4570840.1675062682.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2023-01-30T07:11:31","name":"[v3,1/1] RISC-V: Add platform property/capability extensions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3d42328e6f41cce145063883e5a9f513f4570840.1675062682.git.research_trasio@irq.a4lg.com/mbox/"},{"id":50300,"url":"https://patchwork.plctlab.org/api/1.2/patches/50300/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b61869e7-8fd3-2bec-da2b-046066edc3f3@suse.com/","msgid":"","list_archive_url":null,"date":"2023-01-30T14:07:20","name":"[v2] RISC-V: make C-extension JAL available again for (32-bit) assembly","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b61869e7-8fd3-2bec-da2b-046066edc3f3@suse.com/mbox/"},{"id":50324,"url":"https://patchwork.plctlab.org/api/1.2/patches/50324/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ef8afeef-b35f-348c-7d4c-bac8081e9952@suse.com/","msgid":"","list_archive_url":null,"date":"2023-01-30T14:40:38","name":"[v2] RISC-V: don'\''t disassemble unrecognized insns as .byte","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ef8afeef-b35f-348c-7d4c-bac8081e9952@suse.com/mbox/"},{"id":50325,"url":"https://patchwork.plctlab.org/api/1.2/patches/50325/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/95d700d49f5cdd2239c44ec17dadd11652f7be93.1675091147.git.aburgess@redhat.com/","msgid":"<95d700d49f5cdd2239c44ec17dadd11652f7be93.1675091147.git.aburgess@redhat.com>","list_archive_url":null,"date":"2023-01-30T15:11:41","name":"gas/ppc: Additional tests for DFP instructions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/95d700d49f5cdd2239c44ec17dadd11652f7be93.1675091147.git.aburgess@redhat.com/mbox/"},{"id":50492,"url":"https://patchwork.plctlab.org/api/1.2/patches/50492/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230130210642.7579-1-palmer@rivosinc.com/","msgid":"<20230130210642.7579-1-palmer@rivosinc.com>","list_archive_url":null,"date":"2023-01-30T21:06:41","name":"[1/2] gas: RISC-V: Add a test for near->far branch conversion","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230130210642.7579-1-palmer@rivosinc.com/mbox/"},{"id":50493,"url":"https://patchwork.plctlab.org/api/1.2/patches/50493/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230130210642.7579-2-palmer@rivosinc.com/","msgid":"<20230130210642.7579-2-palmer@rivosinc.com>","list_archive_url":null,"date":"2023-01-30T21:06:42","name":"[2/2] ld: RISC-V: Test R_RISCV_BRANCH truncation errors","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230130210642.7579-2-palmer@rivosinc.com/mbox/"},{"id":50594,"url":"https://patchwork.plctlab.org/api/1.2/patches/50594/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y9id+58ffnaAfImy@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-01-31T04:50:03","name":"testsuite XPASSes","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y9id+58ffnaAfImy@squeak.grove.modra.org/mbox/"},{"id":50595,"url":"https://patchwork.plctlab.org/api/1.2/patches/50595/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y9ieVWMZ5oxFqZJJ@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-01-31T04:51:33","name":"PR30060, ASAN error in bfd_cache_close","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y9ieVWMZ5oxFqZJJ@squeak.grove.modra.org/mbox/"},{"id":50596,"url":"https://patchwork.plctlab.org/api/1.2/patches/50596/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y9iegPmzz6ZQLXCO@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-01-31T04:52:16","name":"Silence ubsan warning about 1<<31","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y9iegPmzz6ZQLXCO@squeak.grove.modra.org/mbox/"},{"id":50784,"url":"https://patchwork.plctlab.org/api/1.2/patches/50784/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230131114257.4585-1-tdevries@suse.de/","msgid":"<20230131114257.4585-1-tdevries@suse.de>","list_archive_url":null,"date":"2023-01-31T11:42:57","name":"[gas] Emit v2 .debug_line for -gdwarf-2","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230131114257.4585-1-tdevries@suse.de/mbox/"}],"public":true,"mbox":"https://patchwork.plctlab.org/bundle/patchwork-bot/binutils-gdb_2023-01/mbox/"},{"id":16,"url":"https://patchwork.plctlab.org/api/1.2/bundles/16/","web_url":"https://patchwork.plctlab.org/bundle/patchwork-bot/binutils-gdb_2023-02/","project":{"id":2,"url":"https://patchwork.plctlab.org/api/1.2/projects/2/","name":"binutils-gdb","link_name":"binutils-gdb","list_id":"binutils.sourceware.org","list_email":"binutils@sourceware.org","web_url":"https://github.com/wangliu-iscas/Patchwork-Bundles/blob/main/binutils-gdb.md","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"name":"binutils-gdb_2023-02","owner":{"id":3,"url":"https://patchwork.plctlab.org/api/1.2/users/3/","username":"patchwork-bot","first_name":"","last_name":"","email":"ouuuleilei@gmail.com"},"patches":[{"id":51097,"url":"https://patchwork.plctlab.org/api/1.2/patches/51097/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230131233429.3708328-2-indu.bhagat@oracle.com/","msgid":"<20230131233429.3708328-2-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-01-31T23:34:25","name":"[1/5] libsframe/doc: use \"stack trace\" instead of \"unwind\" for SFrame","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230131233429.3708328-2-indu.bhagat@oracle.com/mbox/"},{"id":51096,"url":"https://patchwork.plctlab.org/api/1.2/patches/51096/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230131233429.3708328-3-indu.bhagat@oracle.com/","msgid":"<20230131233429.3708328-3-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-01-31T23:34:26","name":"[2/5] sframe: use \"stack trace\" instead of \"unwind\" for SFrame","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230131233429.3708328-3-indu.bhagat@oracle.com/mbox/"},{"id":51099,"url":"https://patchwork.plctlab.org/api/1.2/patches/51099/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230131233429.3708328-4-indu.bhagat@oracle.com/","msgid":"<20230131233429.3708328-4-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-01-31T23:34:27","name":"[3/5] gas: use \"stack trace\" instead of \"unwind\" for SFrame","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230131233429.3708328-4-indu.bhagat@oracle.com/mbox/"},{"id":51098,"url":"https://patchwork.plctlab.org/api/1.2/patches/51098/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230131233429.3708328-5-indu.bhagat@oracle.com/","msgid":"<20230131233429.3708328-5-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-01-31T23:34:28","name":"[4/5] bfd: use \"stack trace\" instead of \"unwind\" for SFrame","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230131233429.3708328-5-indu.bhagat@oracle.com/mbox/"},{"id":51100,"url":"https://patchwork.plctlab.org/api/1.2/patches/51100/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230131233429.3708328-6-indu.bhagat@oracle.com/","msgid":"<20230131233429.3708328-6-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-01-31T23:34:29","name":"[5/5] ld/doc: use \"stack trace\" instead of \"unwind\" for SFrame","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230131233429.3708328-6-indu.bhagat@oracle.com/mbox/"},{"id":51183,"url":"https://patchwork.plctlab.org/api/1.2/patches/51183/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y9oIhhJR9qaUEmFI@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-02-01T06:36:54","name":"Recursion in as_info_where","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y9oIhhJR9qaUEmFI@squeak.grove.modra.org/mbox/"},{"id":51254,"url":"https://patchwork.plctlab.org/api/1.2/patches/51254/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/87lelhzpg3.fsf@redhat.com/","msgid":"<87lelhzpg3.fsf@redhat.com>","list_archive_url":null,"date":"2023-02-01T09:48:28","name":"Fix sanitization warning message building gas.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/87lelhzpg3.fsf@redhat.com/mbox/"},{"id":51529,"url":"https://patchwork.plctlab.org/api/1.2/patches/51529/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/patch-16852-tamar@arm.com/","msgid":"","list_archive_url":null,"date":"2023-02-01T19:25:23","name":"[Binutils] AArch64 gas: relax ordering constriants on enabling and disabling feature extensions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/patch-16852-tamar@arm.com/mbox/"},{"id":51590,"url":"https://patchwork.plctlab.org/api/1.2/patches/51590/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y9rrfysbgq2B456K@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-02-01T22:45:19","name":"gas obj_end","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y9rrfysbgq2B456K@squeak.grove.modra.org/mbox/"},{"id":51591,"url":"https://patchwork.plctlab.org/api/1.2/patches/51591/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y9rrosJRMXXJwzAo@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-02-01T22:45:54","name":"obj-elf.h BYTES_IN_WORD","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y9rrosJRMXXJwzAo@squeak.grove.modra.org/mbox/"},{"id":51640,"url":"https://patchwork.plctlab.org/api/1.2/patches/51640/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y9spf1UfzfEL5hKO@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-02-02T03:09:51","name":"ld-elf/merge test update","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y9spf1UfzfEL5hKO@squeak.grove.modra.org/mbox/"},{"id":51936,"url":"https://patchwork.plctlab.org/api/1.2/patches/51936/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230202140811.20373-1-tdevries@suse.de/","msgid":"<20230202140811.20373-1-tdevries@suse.de>","list_archive_url":null,"date":"2023-02-02T14:08:11","name":"[pushed,gas] Update .loc syntax comment in dwarf2dbg.c","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230202140811.20373-1-tdevries@suse.de/mbox/"},{"id":52314,"url":"https://patchwork.plctlab.org/api/1.2/patches/52314/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y9yeZbU4atFWrl5i@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-02-03T05:40:53","name":"Add ECOFF Symbolic Header sanity checks","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y9yeZbU4atFWrl5i@squeak.grove.modra.org/mbox/"},{"id":52352,"url":"https://patchwork.plctlab.org/api/1.2/patches/52352/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/06804163-be78-6130-b082-71661e50e876@suse.com/","msgid":"<06804163-be78-6130-b082-71661e50e876@suse.com>","list_archive_url":null,"date":"2023-02-03T07:32:13","name":"[1/3] x86: improve special casing of certain insns","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/06804163-be78-6130-b082-71661e50e876@suse.com/mbox/"},{"id":52353,"url":"https://patchwork.plctlab.org/api/1.2/patches/52353/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/645a01e0-8acf-f55d-1f5a-c9e8bbb1d10f@suse.com/","msgid":"<645a01e0-8acf-f55d-1f5a-c9e8bbb1d10f@suse.com>","list_archive_url":null,"date":"2023-02-03T07:32:33","name":"[2/3] x86: simplify a few expressions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/645a01e0-8acf-f55d-1f5a-c9e8bbb1d10f@suse.com/mbox/"},{"id":52354,"url":"https://patchwork.plctlab.org/api/1.2/patches/52354/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8aa94a23-664f-f3ed-fa90-2e0cfa963bd0@suse.com/","msgid":"<8aa94a23-664f-f3ed-fa90-2e0cfa963bd0@suse.com>","list_archive_url":null,"date":"2023-02-03T07:33:44","name":"[3/3] x86: move (and rename) opcodespace attribute","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8aa94a23-664f-f3ed-fa90-2e0cfa963bd0@suse.com/mbox/"},{"id":52367,"url":"https://patchwork.plctlab.org/api/1.2/patches/52367/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/573dd630-a3ca-52c6-846a-d7d18a7e3d52@suse.com/","msgid":"<573dd630-a3ca-52c6-846a-d7d18a7e3d52@suse.com>","list_archive_url":null,"date":"2023-02-03T07:44:56","name":"[1/3] x86: limit use of XOP2SOURCES","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/573dd630-a3ca-52c6-846a-d7d18a7e3d52@suse.com/mbox/"},{"id":52368,"url":"https://patchwork.plctlab.org/api/1.2/patches/52368/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/03deb7fa-cc01-a049-965e-4ee534aadc35@suse.com/","msgid":"<03deb7fa-cc01-a049-965e-4ee534aadc35@suse.com>","list_archive_url":null,"date":"2023-02-03T07:45:51","name":"[2/3] x86: drop use of XOP2SOURCES","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/03deb7fa-cc01-a049-965e-4ee534aadc35@suse.com/mbox/"},{"id":52370,"url":"https://patchwork.plctlab.org/api/1.2/patches/52370/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1364c0e8-5e91-4a92-c14c-072b2a1edf6d@suse.com/","msgid":"<1364c0e8-5e91-4a92-c14c-072b2a1edf6d@suse.com>","list_archive_url":null,"date":"2023-02-03T07:46:45","name":"[3/3] x86: drop use of VEX3SOURCES","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1364c0e8-5e91-4a92-c14c-072b2a1edf6d@suse.com/mbox/"},{"id":53113,"url":"https://patchwork.plctlab.org/api/1.2/patches/53113/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y+DKOkv+GiK5JKLG@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-02-06T09:36:58","name":"Resetting section vma after _bfd_dwarf2_find_nearest_line","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y+DKOkv+GiK5JKLG@squeak.grove.modra.org/mbox/"},{"id":53214,"url":"https://patchwork.plctlab.org/api/1.2/patches/53214/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y+DzhUGfFBaLPJiD@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-02-06T12:33:09","name":"Protect mips_hi16_list from fuzzed debug info","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y+DzhUGfFBaLPJiD@squeak.grove.modra.org/mbox/"},{"id":53216,"url":"https://patchwork.plctlab.org/api/1.2/patches/53216/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y+D0PyRzBoWRnzLq@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-02-06T12:36:15","name":"ppc32 and \"LOAD segment with RWX permissions\"","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y+D0PyRzBoWRnzLq@squeak.grove.modra.org/mbox/"},{"id":53418,"url":"https://patchwork.plctlab.org/api/1.2/patches/53418/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/BLAPR10MB52986899D13C84F0505C23CEABDA9@BLAPR10MB5298.namprd10.prod.outlook.com/","msgid":"","list_archive_url":null,"date":"2023-02-06T16:37:29","name":"gprofng SIGSEGV when processing unusual dwarf","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/BLAPR10MB52986899D13C84F0505C23CEABDA9@BLAPR10MB5298.namprd10.prod.outlook.com/mbox/"},{"id":53591,"url":"https://patchwork.plctlab.org/api/1.2/patches/53591/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230207015340.2021329-1-vladimir.mezentsev@oracle.com/","msgid":"<20230207015340.2021329-1-vladimir.mezentsev@oracle.com>","list_archive_url":null,"date":"2023-02-07T01:53:40","name":"gprofng: fix SIGSEGV when processing unusual dwarf","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230207015340.2021329-1-vladimir.mezentsev@oracle.com/mbox/"},{"id":53606,"url":"https://patchwork.plctlab.org/api/1.2/patches/53606/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230207024424.4000862-1-yunqiang.su@cipunited.com/","msgid":"<20230207024424.4000862-1-yunqiang.su@cipunited.com>","list_archive_url":null,"date":"2023-02-07T02:44:24","name":"MIPS: allow link o32 objects with mach mips64r6 and mips32r6","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230207024424.4000862-1-yunqiang.su@cipunited.com/mbox/"},{"id":54238,"url":"https://patchwork.plctlab.org/api/1.2/patches/54238/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230208071725.3668898-2-tom@tromey.com/","msgid":"<20230208071725.3668898-2-tom@tromey.com>","list_archive_url":null,"date":"2023-02-08T07:17:18","name":"[1/8] Remove H_CFLAGS from doc/local.mk","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230208071725.3668898-2-tom@tromey.com/mbox/"},{"id":54231,"url":"https://patchwork.plctlab.org/api/1.2/patches/54231/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230208071725.3668898-3-tom@tromey.com/","msgid":"<20230208071725.3668898-3-tom@tromey.com>","list_archive_url":null,"date":"2023-02-08T07:17:19","name":"[2/8] Simplify @node use in BFD documentation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230208071725.3668898-3-tom@tromey.com/mbox/"},{"id":54222,"url":"https://patchwork.plctlab.org/api/1.2/patches/54222/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230208071725.3668898-4-tom@tromey.com/","msgid":"<20230208071725.3668898-4-tom@tromey.com>","list_archive_url":null,"date":"2023-02-08T07:17:20","name":"[3/8] Add copyright headers to the .str files","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230208071725.3668898-4-tom@tromey.com/mbox/"},{"id":54226,"url":"https://patchwork.plctlab.org/api/1.2/patches/54226/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230208071725.3668898-5-tom@tromey.com/","msgid":"<20230208071725.3668898-5-tom@tromey.com>","list_archive_url":null,"date":"2023-02-08T07:17:21","name":"[4/8] Remove the paramstuff word","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230208071725.3668898-5-tom@tromey.com/mbox/"},{"id":54223,"url":"https://patchwork.plctlab.org/api/1.2/patches/54223/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230208071725.3668898-6-tom@tromey.com/","msgid":"<20230208071725.3668898-6-tom@tromey.com>","list_archive_url":null,"date":"2023-02-08T07:17:22","name":"[5/8] Use intptr_t rather than long in chew","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230208071725.3668898-6-tom@tromey.com/mbox/"},{"id":54232,"url":"https://patchwork.plctlab.org/api/1.2/patches/54232/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230208071725.3668898-7-tom@tromey.com/","msgid":"<20230208071725.3668898-7-tom@tromey.com>","list_archive_url":null,"date":"2023-02-08T07:17:23","name":"[6/8] Change internalmode to be an intrinsic variable","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230208071725.3668898-7-tom@tromey.com/mbox/"},{"id":54235,"url":"https://patchwork.plctlab.org/api/1.2/patches/54235/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230208071725.3668898-8-tom@tromey.com/","msgid":"<20230208071725.3668898-8-tom@tromey.com>","list_archive_url":null,"date":"2023-02-08T07:17:24","name":"[7/8] Use @deftypefn in chew output","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230208071725.3668898-8-tom@tromey.com/mbox/"},{"id":54227,"url":"https://patchwork.plctlab.org/api/1.2/patches/54227/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230208071725.3668898-9-tom@tromey.com/","msgid":"<20230208071725.3668898-9-tom@tromey.com>","list_archive_url":null,"date":"2023-02-08T07:17:25","name":"[8/8] Remove RETURNS from BFD chew comments","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230208071725.3668898-9-tom@tromey.com/mbox/"},{"id":54632,"url":"https://patchwork.plctlab.org/api/1.2/patches/54632/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y+QsUGAY7LQw0zQu@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-02-08T23:12:16","name":"Internal error at gas/expr.c:1814","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y+QsUGAY7LQw0zQu@squeak.grove.modra.org/mbox/"},{"id":54633,"url":"https://patchwork.plctlab.org/api/1.2/patches/54633/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y+QsheSWZko4+7vV@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-02-08T23:13:09","name":"Clear cached file size when bfd changed to BFD_IN_MEMORY","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y+QsheSWZko4+7vV@squeak.grove.modra.org/mbox/"},{"id":54634,"url":"https://patchwork.plctlab.org/api/1.2/patches/54634/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y+QsoGbCT4Ei4rlW@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-02-08T23:13:36","name":"Memory leak in bfd_init_section_compress_status","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y+QsoGbCT4Ei4rlW@squeak.grove.modra.org/mbox/"},{"id":54635,"url":"https://patchwork.plctlab.org/api/1.2/patches/54635/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y+QszzU2zl+ApZy4@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-02-08T23:14:23","name":"coff-sh.c keep_relocs, keep_contents and keep_syms","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y+QszzU2zl+ApZy4@squeak.grove.modra.org/mbox/"},{"id":54823,"url":"https://patchwork.plctlab.org/api/1.2/patches/54823/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y+S/4ej6hbSlHWUj@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-02-09T09:41:53","name":"coff keep_relocs and keep_contents","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y+S/4ej6hbSlHWUj@squeak.grove.modra.org/mbox/"},{"id":55093,"url":"https://patchwork.plctlab.org/api/1.2/patches/55093/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230209205040.1286063-1-tromey@adacore.com/","msgid":"<20230209205040.1286063-1-tromey@adacore.com>","list_archive_url":null,"date":"2023-02-09T20:50:40","name":"[pushed] Add full display feature to dwarf-mode.el","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230209205040.1286063-1-tromey@adacore.com/mbox/"},{"id":55172,"url":"https://patchwork.plctlab.org/api/1.2/patches/55172/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y+WWbsUP6DBus1sD@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-02-10T00:57:18","name":"objcopy of mach-o indirect symbols","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y+WWbsUP6DBus1sD@squeak.grove.modra.org/mbox/"},{"id":55284,"url":"https://patchwork.plctlab.org/api/1.2/patches/55284/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y+X07Mh4TUJM0qoV@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-02-10T07:40:28","name":"Local label checks in integer_constant","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y+X07Mh4TUJM0qoV@squeak.grove.modra.org/mbox/"},{"id":55314,"url":"https://patchwork.plctlab.org/api/1.2/patches/55314/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1d6f89f5-0e6e-6a8b-3a93-41dd26d09c0a@suse.com/","msgid":"<1d6f89f5-0e6e-6a8b-3a93-41dd26d09c0a@suse.com>","list_archive_url":null,"date":"2023-02-10T08:36:05","name":"[1/2] x86: optimize BT{,C,R,S} $imm,%reg","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1d6f89f5-0e6e-6a8b-3a93-41dd26d09c0a@suse.com/mbox/"},{"id":55315,"url":"https://patchwork.plctlab.org/api/1.2/patches/55315/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/58de4278-3b30-1e3b-f2da-551c47bca681@suse.com/","msgid":"<58de4278-3b30-1e3b-f2da-551c47bca681@suse.com>","list_archive_url":null,"date":"2023-02-10T08:36:40","name":"[2/2] x86: restrict insn templates accepting negative 8-bit immediates","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/58de4278-3b30-1e3b-f2da-551c47bca681@suse.com/mbox/"},{"id":55317,"url":"https://patchwork.plctlab.org/api/1.2/patches/55317/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b0c44651-1f3f-46c6-09ff-c12bf6026bdc@suse.com/","msgid":"","list_archive_url":null,"date":"2023-02-10T08:48:39","name":"[1/4] x86-64: LAR and LSL don'\''t need REX.W","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b0c44651-1f3f-46c6-09ff-c12bf6026bdc@suse.com/mbox/"},{"id":55318,"url":"https://patchwork.plctlab.org/api/1.2/patches/55318/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/623497d9-1367-d446-1cce-f9b0fe177699@suse.com/","msgid":"<623497d9-1367-d446-1cce-f9b0fe177699@suse.com>","list_archive_url":null,"date":"2023-02-10T08:49:18","name":"[2/4] x86: have insns acting on segment selector values allow for consistent operands","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/623497d9-1367-d446-1cce-f9b0fe177699@suse.com/mbox/"},{"id":55319,"url":"https://patchwork.plctlab.org/api/1.2/patches/55319/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3ab09feb-290d-693d-b43f-237022f3f6aa@suse.com/","msgid":"<3ab09feb-290d-693d-b43f-237022f3f6aa@suse.com>","list_archive_url":null,"date":"2023-02-10T08:50:25","name":"[3/4] x86-64: don'\''t permit LAHF/SAHF with \"generic64\"","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3ab09feb-290d-693d-b43f-237022f3f6aa@suse.com/mbox/"},{"id":55320,"url":"https://patchwork.plctlab.org/api/1.2/patches/55320/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/67715baf-b718-0d00-959a-fc4e70c0dff9@suse.com/","msgid":"<67715baf-b718-0d00-959a-fc4e70c0dff9@suse.com>","list_archive_url":null,"date":"2023-02-10T08:51:42","name":"[4/4] x86: MONITOR/MWAIT are not SSE3 insns","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/67715baf-b718-0d00-959a-fc4e70c0dff9@suse.com/mbox/"},{"id":55325,"url":"https://patchwork.plctlab.org/api/1.2/patches/55325/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d6e6f04a-d7d2-fffc-1672-89356d00888c@suse.com/","msgid":"","list_archive_url":null,"date":"2023-02-10T08:53:47","name":"x86: allow to request ModR/M encoding","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d6e6f04a-d7d2-fffc-1672-89356d00888c@suse.com/mbox/"},{"id":55358,"url":"https://patchwork.plctlab.org/api/1.2/patches/55358/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y+YW49ew8TrVHIVE@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-02-10T10:05:23","name":"Fix mmo memory leaks","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y+YW49ew8TrVHIVE@squeak.grove.modra.org/mbox/"},{"id":55383,"url":"https://patchwork.plctlab.org/api/1.2/patches/55383/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/26a512cf3d23fca9a71d4328d554f640d080e8a8.1676025351.git.research_trasio@irq.a4lg.com/","msgid":"<26a512cf3d23fca9a71d4328d554f640d080e8a8.1676025351.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2023-02-10T10:37:22","name":"RISC-V: Reduce effective linker relaxation passses","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/26a512cf3d23fca9a71d4328d554f640d080e8a8.1676025351.git.research_trasio@irq.a4lg.com/mbox/"},{"id":55502,"url":"https://patchwork.plctlab.org/api/1.2/patches/55502/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230210174404.3763-2-binutils@emagii.com/","msgid":"<20230210174404.3763-2-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-10T17:44:01","name":"[1/4] ldlex.l: Add ASCIZ token","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230210174404.3763-2-binutils@emagii.com/mbox/"},{"id":55503,"url":"https://patchwork.plctlab.org/api/1.2/patches/55503/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230210174404.3763-3-binutils@emagii.com/","msgid":"<20230210174404.3763-3-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-10T17:44:02","name":"[2/4] ldgram.y: Add '\''ASCIZ '\'' command","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230210174404.3763-3-binutils@emagii.com/mbox/"},{"id":55504,"url":"https://patchwork.plctlab.org/api/1.2/patches/55504/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230210174404.3763-4-binutils@emagii.com/","msgid":"<20230210174404.3763-4-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-10T17:44:03","name":"[3/4] Parse ASCIZ command","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230210174404.3763-4-binutils@emagii.com/mbox/"},{"id":55505,"url":"https://patchwork.plctlab.org/api/1.2/patches/55505/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230210174404.3763-5-binutils@emagii.com/","msgid":"<20230210174404.3763-5-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-10T17:44:04","name":"[4/4] Document the ASCIZ command","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230210174404.3763-5-binutils@emagii.com/mbox/"},{"id":55698,"url":"https://patchwork.plctlab.org/api/1.2/patches/55698/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y+cxtbhMXNT350aU@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-02-11T06:12:05","name":".debug sections without contents","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y+cxtbhMXNT350aU@squeak.grove.modra.org/mbox/"},{"id":55699,"url":"https://patchwork.plctlab.org/api/1.2/patches/55699/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y+cyCbQkCFHOPzaA@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-02-11T06:13:29","name":"objdump -D of bss sections and -s with -j","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y+cyCbQkCFHOPzaA@squeak.grove.modra.org/mbox/"},{"id":55977,"url":"https://patchwork.plctlab.org/api/1.2/patches/55977/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y+lm2hoJrZN/I1OO@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-02-12T22:23:22","name":"objcopy memory leaks","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y+lm2hoJrZN/I1OO@squeak.grove.modra.org/mbox/"},{"id":56071,"url":"https://patchwork.plctlab.org/api/1.2/patches/56071/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5003cbd5-448c-7f39-5219-ae3bfe50504f@suse.com/","msgid":"<5003cbd5-448c-7f39-5219-ae3bfe50504f@suse.com>","list_archive_url":null,"date":"2023-02-13T08:02:36","name":"[1/2] RISC-V: test for expected / no unexpected symbols","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5003cbd5-448c-7f39-5219-ae3bfe50504f@suse.com/mbox/"},{"id":56072,"url":"https://patchwork.plctlab.org/api/1.2/patches/56072/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3bb126f6-5bf1-dab0-f540-25c386b9507e@suse.com/","msgid":"<3bb126f6-5bf1-dab0-f540-25c386b9507e@suse.com>","list_archive_url":null,"date":"2023-02-13T08:02:58","name":"[2/2] RISC-V: adjust logic to avoid register name symbols","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3bb126f6-5bf1-dab0-f540-25c386b9507e@suse.com/mbox/"},{"id":56078,"url":"https://patchwork.plctlab.org/api/1.2/patches/56078/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/09ff32c5-3ebc-dda1-2eb5-be7851cb7c66@suse.com/","msgid":"<09ff32c5-3ebc-dda1-2eb5-be7851cb7c66@suse.com>","list_archive_url":null,"date":"2023-02-13T08:12:12","name":"[1/2] Arm64/gas: add missing prereq features","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/09ff32c5-3ebc-dda1-2eb5-be7851cb7c66@suse.com/mbox/"},{"id":56080,"url":"https://patchwork.plctlab.org/api/1.2/patches/56080/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c1e56cb2-a33f-59fd-a431-6a27460525cf@suse.com/","msgid":"","list_archive_url":null,"date":"2023-02-13T08:12:45","name":"[2/2] Arm64/gas: drop redundant feature prereqs","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c1e56cb2-a33f-59fd-a431-6a27460525cf@suse.com/mbox/"},{"id":56081,"url":"https://patchwork.plctlab.org/api/1.2/patches/56081/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/08d262e3-c736-85ff-c45e-db96e55cff4c@suse.com/","msgid":"<08d262e3-c736-85ff-c45e-db96e55cff4c@suse.com>","list_archive_url":null,"date":"2023-02-13T08:15:36","name":"gas: improve interaction between read_a_source_file() and s_linefile()","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/08d262e3-c736-85ff-c45e-db96e55cff4c@suse.com/mbox/"},{"id":56098,"url":"https://patchwork.plctlab.org/api/1.2/patches/56098/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8c7753dd-a5f5-f994-88ee-d4e053a20bc0@suse.com/","msgid":"<8c7753dd-a5f5-f994-88ee-d4e053a20bc0@suse.com>","list_archive_url":null,"date":"2023-02-13T08:42:20","name":"x86: {LD,ST}TILECFG use an extension opcode","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8c7753dd-a5f5-f994-88ee-d4e053a20bc0@suse.com/mbox/"},{"id":56162,"url":"https://patchwork.plctlab.org/api/1.2/patches/56162/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y+oSap1kQICg3JMp@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-02-13T10:35:22","name":"Split off gas init to functions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y+oSap1kQICg3JMp@squeak.grove.modra.org/mbox/"},{"id":56164,"url":"https://patchwork.plctlab.org/api/1.2/patches/56164/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y+oSkktwhytmt7rZ@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-02-13T10:36:02","name":"stabs.c static state","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y+oSkktwhytmt7rZ@squeak.grove.modra.org/mbox/"},{"id":56261,"url":"https://patchwork.plctlab.org/api/1.2/patches/56261/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230213122241.6144-2-binutils@emagii.com/","msgid":"<20230213122241.6144-2-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-13T12:22:37","name":"[v2,1/5] ldlex.l: Add ASCIZ token","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230213122241.6144-2-binutils@emagii.com/mbox/"},{"id":56262,"url":"https://patchwork.plctlab.org/api/1.2/patches/56262/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230213122241.6144-3-binutils@emagii.com/","msgid":"<20230213122241.6144-3-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-13T12:22:38","name":"[v2,2/5] ldgram.y: Add '\''ASCIZ '\'' command","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230213122241.6144-3-binutils@emagii.com/mbox/"},{"id":56263,"url":"https://patchwork.plctlab.org/api/1.2/patches/56263/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230213122241.6144-4-binutils@emagii.com/","msgid":"<20230213122241.6144-4-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-13T12:22:39","name":"[v2,3/5] Parse ASCIZ command","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230213122241.6144-4-binutils@emagii.com/mbox/"},{"id":56264,"url":"https://patchwork.plctlab.org/api/1.2/patches/56264/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230213122241.6144-5-binutils@emagii.com/","msgid":"<20230213122241.6144-5-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-13T12:22:40","name":"[v2,4/5] Document the ASCIZ command","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230213122241.6144-5-binutils@emagii.com/mbox/"},{"id":56265,"url":"https://patchwork.plctlab.org/api/1.2/patches/56265/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230213122241.6144-6-binutils@emagii.com/","msgid":"<20230213122241.6144-6-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-13T12:22:41","name":"[v2,5/5] Use lang_add_data","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230213122241.6144-6-binutils@emagii.com/mbox/"},{"id":56267,"url":"https://patchwork.plctlab.org/api/1.2/patches/56267/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y+ovRotGLLHQE09t@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-02-13T12:38:30","name":"_bfd_ecoff_slurp_symbol_table buffer overflow","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y+ovRotGLLHQE09t@squeak.grove.modra.org/mbox/"},{"id":56279,"url":"https://patchwork.plctlab.org/api/1.2/patches/56279/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.LSU.2.20.2302131301550.29328@wotan.suse.de/","msgid":"","list_archive_url":null,"date":"2023-02-13T13:04:14","name":"[obvious] Fix PR30079: abort on mingw","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.LSU.2.20.2302131301550.29328@wotan.suse.de/mbox/"},{"id":56293,"url":"https://patchwork.plctlab.org/api/1.2/patches/56293/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230213133949.3773320-2-christoph.muellner@vrull.eu/","msgid":"<20230213133949.3773320-2-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2023-02-13T13:39:42","name":"[RFC,v3,1/8] RISC-V: Add Zvkb ISA extension support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230213133949.3773320-2-christoph.muellner@vrull.eu/mbox/"},{"id":56296,"url":"https://patchwork.plctlab.org/api/1.2/patches/56296/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230213133949.3773320-3-christoph.muellner@vrull.eu/","msgid":"<20230213133949.3773320-3-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2023-02-13T13:39:43","name":"[RFC,v3,2/8] RISC-V: Add Zvkg ISA extension support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230213133949.3773320-3-christoph.muellner@vrull.eu/mbox/"},{"id":56297,"url":"https://patchwork.plctlab.org/api/1.2/patches/56297/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230213133949.3773320-4-christoph.muellner@vrull.eu/","msgid":"<20230213133949.3773320-4-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2023-02-13T13:39:44","name":"[RFC,v3,3/8] RISC-V: Add Zvkned ISA extension support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230213133949.3773320-4-christoph.muellner@vrull.eu/mbox/"},{"id":56294,"url":"https://patchwork.plctlab.org/api/1.2/patches/56294/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230213133949.3773320-5-christoph.muellner@vrull.eu/","msgid":"<20230213133949.3773320-5-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2023-02-13T13:39:45","name":"[RFC,v3,4/8] RISC-V: Add Zvknh[a,b] ISA extension support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230213133949.3773320-5-christoph.muellner@vrull.eu/mbox/"},{"id":56298,"url":"https://patchwork.plctlab.org/api/1.2/patches/56298/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230213133949.3773320-6-christoph.muellner@vrull.eu/","msgid":"<20230213133949.3773320-6-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2023-02-13T13:39:46","name":"[RFC,v3,5/8] RISC-V: Add Zvkn ISA extension support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230213133949.3773320-6-christoph.muellner@vrull.eu/mbox/"},{"id":56300,"url":"https://patchwork.plctlab.org/api/1.2/patches/56300/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230213133949.3773320-7-christoph.muellner@vrull.eu/","msgid":"<20230213133949.3773320-7-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2023-02-13T13:39:47","name":"[RFC,v3,6/8] RISC-V: Add Zvksed ISA extension support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230213133949.3773320-7-christoph.muellner@vrull.eu/mbox/"},{"id":56295,"url":"https://patchwork.plctlab.org/api/1.2/patches/56295/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230213133949.3773320-8-christoph.muellner@vrull.eu/","msgid":"<20230213133949.3773320-8-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2023-02-13T13:39:48","name":"[RFC,v3,7/8] RISC-V: Add Zvksh ISA extension support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230213133949.3773320-8-christoph.muellner@vrull.eu/mbox/"},{"id":56299,"url":"https://patchwork.plctlab.org/api/1.2/patches/56299/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230213133949.3773320-9-christoph.muellner@vrull.eu/","msgid":"<20230213133949.3773320-9-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2023-02-13T13:39:49","name":"[RFC,v3,8/8] RISC-V: Add Zvks ISA extension support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230213133949.3773320-9-christoph.muellner@vrull.eu/mbox/"},{"id":56326,"url":"https://patchwork.plctlab.org/api/1.2/patches/56326/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2096ddec-287a-de42-a2f6-58293af2fd48@suse.com/","msgid":"<2096ddec-287a-de42-a2f6-58293af2fd48@suse.com>","list_archive_url":null,"date":"2023-02-13T14:54:00","name":"gas: correct symbol name comparison in .startof./.sizeof. handling","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2096ddec-287a-de42-a2f6-58293af2fd48@suse.com/mbox/"},{"id":56363,"url":"https://patchwork.plctlab.org/api/1.2/patches/56363/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230213161124.15340-2-binutils@emagii.com/","msgid":"<20230213161124.15340-2-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-13T16:11:19","name":"[v3,1/6] Document the ASCIZ command","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230213161124.15340-2-binutils@emagii.com/mbox/"},{"id":56366,"url":"https://patchwork.plctlab.org/api/1.2/patches/56366/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230213161124.15340-3-binutils@emagii.com/","msgid":"<20230213161124.15340-3-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-13T16:11:20","name":"[v3,2/6] Add ASCIZ to NEWS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230213161124.15340-3-binutils@emagii.com/mbox/"},{"id":56365,"url":"https://patchwork.plctlab.org/api/1.2/patches/56365/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230213161124.15340-4-binutils@emagii.com/","msgid":"<20230213161124.15340-4-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-13T16:11:21","name":"[v3,3/6] Add ASCIZ to testsuite","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230213161124.15340-4-binutils@emagii.com/mbox/"},{"id":56364,"url":"https://patchwork.plctlab.org/api/1.2/patches/56364/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230213161124.15340-5-binutils@emagii.com/","msgid":"<20230213161124.15340-5-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-13T16:11:22","name":"[v3,4/6] ldlex.l: Add ASCIZ token","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230213161124.15340-5-binutils@emagii.com/mbox/"},{"id":56367,"url":"https://patchwork.plctlab.org/api/1.2/patches/56367/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230213161124.15340-6-binutils@emagii.com/","msgid":"<20230213161124.15340-6-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-13T16:11:23","name":"[v3,5/6] ldgram.y: Add '\''ASCIZ '\'' command","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230213161124.15340-6-binutils@emagii.com/mbox/"},{"id":56368,"url":"https://patchwork.plctlab.org/api/1.2/patches/56368/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230213161124.15340-7-binutils@emagii.com/","msgid":"<20230213161124.15340-7-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-13T16:11:24","name":"[v3,6/6] Parse ASCIZ command","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230213161124.15340-7-binutils@emagii.com/mbox/"},{"id":56372,"url":"https://patchwork.plctlab.org/api/1.2/patches/56372/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230213162009.15515-2-binutils@emagii.com/","msgid":"<20230213162009.15515-2-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-13T16:20:04","name":"[v4,1/6] Document the ASCIZ command","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230213162009.15515-2-binutils@emagii.com/mbox/"},{"id":56369,"url":"https://patchwork.plctlab.org/api/1.2/patches/56369/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230213162009.15515-3-binutils@emagii.com/","msgid":"<20230213162009.15515-3-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-13T16:20:05","name":"[v4,2/6] Add ASCIZ to NEWS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230213162009.15515-3-binutils@emagii.com/mbox/"},{"id":56370,"url":"https://patchwork.plctlab.org/api/1.2/patches/56370/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230213162009.15515-4-binutils@emagii.com/","msgid":"<20230213162009.15515-4-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-13T16:20:06","name":"[v4,3/6] Add ASCIZ to testsuite","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230213162009.15515-4-binutils@emagii.com/mbox/"},{"id":56371,"url":"https://patchwork.plctlab.org/api/1.2/patches/56371/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230213162009.15515-5-binutils@emagii.com/","msgid":"<20230213162009.15515-5-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-13T16:20:07","name":"[v4,4/6] ldlex.l: Add ASCIZ token","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230213162009.15515-5-binutils@emagii.com/mbox/"},{"id":56373,"url":"https://patchwork.plctlab.org/api/1.2/patches/56373/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230213162009.15515-6-binutils@emagii.com/","msgid":"<20230213162009.15515-6-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-13T16:20:08","name":"[v4,5/6] ldgram.y: Add '\''ASCIZ '\'' command","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230213162009.15515-6-binutils@emagii.com/mbox/"},{"id":56404,"url":"https://patchwork.plctlab.org/api/1.2/patches/56404/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.LSU.2.20.2302131741480.29328@wotan.suse.de/","msgid":"","list_archive_url":null,"date":"2023-02-13T17:42:58","name":"PR30120: fix x87 fucomp misassembled","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.LSU.2.20.2302131741480.29328@wotan.suse.de/mbox/"},{"id":56662,"url":"https://patchwork.plctlab.org/api/1.2/patches/56662/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230214050633.28910-6-binutils@emagii.com/","msgid":"<20230214050633.28910-6-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-14T05:06:33","name":"[v4,6/6] Parse ASCIZ command","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230214050633.28910-6-binutils@emagii.com/mbox/"},{"id":57082,"url":"https://patchwork.plctlab.org/api/1.2/patches/57082/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b876de99-e433-61b6-1645-e026f6c9dd80@suse.com/","msgid":"","list_archive_url":null,"date":"2023-02-14T15:53:10","name":"gas: buffer_and_nest() needs to pass nul-terminated string to temp_ilp()","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b876de99-e433-61b6-1645-e026f6c9dd80@suse.com/mbox/"},{"id":57344,"url":"https://patchwork.plctlab.org/api/1.2/patches/57344/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y+xE0Fa4HqQq/1p0@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-02-15T02:34:56","name":"binutils stabs type list","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y+xE0Fa4HqQq/1p0@squeak.grove.modra.org/mbox/"},{"id":57373,"url":"https://patchwork.plctlab.org/api/1.2/patches/57373/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y+x2gNcp9REGOj8e@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-02-15T06:06:56","name":"More ecoff sanity checks","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y+x2gNcp9REGOj8e@squeak.grove.modra.org/mbox/"},{"id":57417,"url":"https://patchwork.plctlab.org/api/1.2/patches/57417/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/56cd41d5-c0ba-d076-bf09-06612a2b54c3@suse.com/","msgid":"<56cd41d5-c0ba-d076-bf09-06612a2b54c3@suse.com>","list_archive_url":null,"date":"2023-02-15T07:44:24","name":"x86/gas: replace inappropriate assertion when parsing registers","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/56cd41d5-c0ba-d076-bf09-06612a2b54c3@suse.com/mbox/"},{"id":57485,"url":"https://patchwork.plctlab.org/api/1.2/patches/57485/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y+zDOBCppQShhWzW@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-02-15T11:34:16","name":"objdump -G memory leak","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y+zDOBCppQShhWzW@squeak.grove.modra.org/mbox/"},{"id":57486,"url":"https://patchwork.plctlab.org/api/1.2/patches/57486/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y+zDasJ/lS/QXsxw@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-02-15T11:35:06","name":"objdump read_section_stabs","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y+zDasJ/lS/QXsxw@squeak.grove.modra.org/mbox/"},{"id":57497,"url":"https://patchwork.plctlab.org/api/1.2/patches/57497/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230215114052.28292-2-binutils@emagii.com/","msgid":"<20230215114052.28292-2-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-15T11:40:47","name":"[v0,1/6] Add testsuite for ASCII command","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230215114052.28292-2-binutils@emagii.com/mbox/"},{"id":57488,"url":"https://patchwork.plctlab.org/api/1.2/patches/57488/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230215114052.28292-3-binutils@emagii.com/","msgid":"<20230215114052.28292-3-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-15T11:40:48","name":"[v0,2/6] Add ASCII command info to NEWS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230215114052.28292-3-binutils@emagii.com/mbox/"},{"id":57498,"url":"https://patchwork.plctlab.org/api/1.2/patches/57498/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230215114052.28292-4-binutils@emagii.com/","msgid":"<20230215114052.28292-4-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-15T11:40:49","name":"[v0,3/6] Add ASCII to info file","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230215114052.28292-4-binutils@emagii.com/mbox/"},{"id":57499,"url":"https://patchwork.plctlab.org/api/1.2/patches/57499/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230215114052.28292-5-binutils@emagii.com/","msgid":"<20230215114052.28292-5-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-15T11:40:50","name":"[v0,4/6] ldlex.l: add ASCII","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230215114052.28292-5-binutils@emagii.com/mbox/"},{"id":57490,"url":"https://patchwork.plctlab.org/api/1.2/patches/57490/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230215114052.28292-6-binutils@emagii.com/","msgid":"<20230215114052.28292-6-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-15T11:40:51","name":"[v0,5/6] ldgram.y: add ASCII","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230215114052.28292-6-binutils@emagii.com/mbox/"},{"id":57491,"url":"https://patchwork.plctlab.org/api/1.2/patches/57491/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230215114052.28292-7-binutils@emagii.com/","msgid":"<20230215114052.28292-7-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-15T11:40:52","name":"[v0,6/6] ldlang.*: parse ASCII command","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230215114052.28292-7-binutils@emagii.com/mbox/"},{"id":57650,"url":"https://patchwork.plctlab.org/api/1.2/patches/57650/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230215180303.620184-2-i.swmail@xen0n.name/","msgid":"<20230215180303.620184-2-i.swmail@xen0n.name>","list_archive_url":null,"date":"2023-02-15T18:02:58","name":"[v4,1/6] LoongArch: support disassembling certain pseudo-instructions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230215180303.620184-2-i.swmail@xen0n.name/mbox/"},{"id":57649,"url":"https://patchwork.plctlab.org/api/1.2/patches/57649/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230215180303.620184-3-i.swmail@xen0n.name/","msgid":"<20230215180303.620184-3-i.swmail@xen0n.name>","list_archive_url":null,"date":"2023-02-15T18:02:59","name":"[v4,2/6] opcodes/loongarch: remove unused code","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230215180303.620184-3-i.swmail@xen0n.name/mbox/"},{"id":57652,"url":"https://patchwork.plctlab.org/api/1.2/patches/57652/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230215180303.620184-4-i.swmail@xen0n.name/","msgid":"<20230215180303.620184-4-i.swmail@xen0n.name>","list_archive_url":null,"date":"2023-02-15T18:03:00","name":"[v4,3/6] opcodes/loongarch: implement style support in the disassembler","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230215180303.620184-4-i.swmail@xen0n.name/mbox/"},{"id":57651,"url":"https://patchwork.plctlab.org/api/1.2/patches/57651/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230215180303.620184-5-i.swmail@xen0n.name/","msgid":"<20230215180303.620184-5-i.swmail@xen0n.name>","list_archive_url":null,"date":"2023-02-15T18:03:01","name":"[v4,4/6] opcodes/loongarch: style disassembled address offsets as such","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230215180303.620184-5-i.swmail@xen0n.name/mbox/"},{"id":57654,"url":"https://patchwork.plctlab.org/api/1.2/patches/57654/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230215180303.620184-6-i.swmail@xen0n.name/","msgid":"<20230215180303.620184-6-i.swmail@xen0n.name>","list_archive_url":null,"date":"2023-02-15T18:03:02","name":"[v4,5/6] opcodes/loongarch: do not print hex notation for signed immediates","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230215180303.620184-6-i.swmail@xen0n.name/mbox/"},{"id":57653,"url":"https://patchwork.plctlab.org/api/1.2/patches/57653/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230215180303.620184-7-i.swmail@xen0n.name/","msgid":"<20230215180303.620184-7-i.swmail@xen0n.name>","list_archive_url":null,"date":"2023-02-15T18:03:03","name":"[v4,6/6] opcodes/loongarch: print unrecognized insn words with the .word directive","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230215180303.620184-7-i.swmail@xen0n.name/mbox/"},{"id":57811,"url":"https://patchwork.plctlab.org/api/1.2/patches/57811/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y+2O/JECc+OX2WWd@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-02-16T02:03:40","name":"gas_init","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y+2O/JECc+OX2WWd@squeak.grove.modra.org/mbox/"},{"id":57812,"url":"https://patchwork.plctlab.org/api/1.2/patches/57812/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y+2PQpJcZUJBOxco@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-02-16T02:04:50","name":"Delete PROGRESS macros","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y+2PQpJcZUJBOxco@squeak.grove.modra.org/mbox/"},{"id":57925,"url":"https://patchwork.plctlab.org/api/1.2/patches/57925/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f055cbdb-e706-3a74-ab63-725ed8a047fd@suse.com/","msgid":"","list_archive_url":null,"date":"2023-02-16T08:56:11","name":"RISC-V: as_warn() already emits a newline","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f055cbdb-e706-3a74-ab63-725ed8a047fd@suse.com/mbox/"},{"id":58064,"url":"https://patchwork.plctlab.org/api/1.2/patches/58064/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230216131905.1012-2-binutils@emagii.com/","msgid":"<20230216131905.1012-2-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-16T13:19:05","name":"[v0,1/1,RFC] Add support for CRC64 generation in linker","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230216131905.1012-2-binutils@emagii.com/mbox/"},{"id":58227,"url":"https://patchwork.plctlab.org/api/1.2/patches/58227/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230216204006.1977-2-binutils@emagii.com/","msgid":"<20230216204006.1977-2-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-16T20:40:01","name":"[v0,1/6] CRC64 header","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230216204006.1977-2-binutils@emagii.com/mbox/"},{"id":58228,"url":"https://patchwork.plctlab.org/api/1.2/patches/58228/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230216204006.1977-3-binutils@emagii.com/","msgid":"<20230216204006.1977-3-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-16T20:40:02","name":"[v0,2/6] ldlang.h: CRC64","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230216204006.1977-3-binutils@emagii.com/mbox/"},{"id":58229,"url":"https://patchwork.plctlab.org/api/1.2/patches/58229/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230216204006.1977-4-binutils@emagii.com/","msgid":"<20230216204006.1977-4-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-16T20:40:03","name":"[v0,3/6] ldlex.l: CRC64","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230216204006.1977-4-binutils@emagii.com/mbox/"},{"id":58230,"url":"https://patchwork.plctlab.org/api/1.2/patches/58230/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230216204006.1977-5-binutils@emagii.com/","msgid":"<20230216204006.1977-5-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-16T20:40:04","name":"[v0,4/6] ldgram.y: CRC64","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230216204006.1977-5-binutils@emagii.com/mbox/"},{"id":58232,"url":"https://patchwork.plctlab.org/api/1.2/patches/58232/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230216204006.1977-6-binutils@emagii.com/","msgid":"<20230216204006.1977-6-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-16T20:40:05","name":"[v0,5/6] ldlang.c: CRC64","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230216204006.1977-6-binutils@emagii.com/mbox/"},{"id":58231,"url":"https://patchwork.plctlab.org/api/1.2/patches/58231/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230216204006.1977-7-binutils@emagii.com/","msgid":"<20230216204006.1977-7-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-16T20:40:06","name":"[v0,6/6] ldlang.c: Try to get the .text section for checking CRC","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230216204006.1977-7-binutils@emagii.com/mbox/"},{"id":58259,"url":"https://patchwork.plctlab.org/api/1.2/patches/58259/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y+6nfaKgOuYb/KBD@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-02-16T22:00:29","name":"PR30046, power cmpi leads to unknown architecture","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y+6nfaKgOuYb/KBD@squeak.grove.modra.org/mbox/"},{"id":58321,"url":"https://patchwork.plctlab.org/api/1.2/patches/58321/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y+7ouisD+WH2nZn5@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-02-17T02:38:50","name":"Wild pointer reads in _bfd_ecoff_locate_line","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y+7ouisD+WH2nZn5@squeak.grove.modra.org/mbox/"},{"id":58346,"url":"https://patchwork.plctlab.org/api/1.2/patches/58346/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230217044033.2131866-1-vladimir.mezentsev@oracle.com/","msgid":"<20230217044033.2131866-1-vladimir.mezentsev@oracle.com>","list_archive_url":null,"date":"2023-02-17T04:40:33","name":"[1/2] gprofng: PR30036 Build failure on aarch64 w/ glibc: symbol `pwrite64'\'' is already defined","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230217044033.2131866-1-vladimir.mezentsev@oracle.com/mbox/"},{"id":58347,"url":"https://patchwork.plctlab.org/api/1.2/patches/58347/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230217044105.2133872-1-vladimir.mezentsev@oracle.com/","msgid":"<20230217044105.2133872-1-vladimir.mezentsev@oracle.com>","list_archive_url":null,"date":"2023-02-17T04:41:05","name":"[2/2] gprofng: fix Dwarf reader for DW_TAG_subprogram","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230217044105.2133872-1-vladimir.mezentsev@oracle.com/mbox/"},{"id":58348,"url":"https://patchwork.plctlab.org/api/1.2/patches/58348/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y+8HWSTBuPWN+K3i@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-02-17T04:49:29","name":"ld test asciz and ascii fails","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y+8HWSTBuPWN+K3i@squeak.grove.modra.org/mbox/"},{"id":58514,"url":"https://patchwork.plctlab.org/api/1.2/patches/58514/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230217112016.19718-2-binutils@emagii.com/","msgid":"<20230217112016.19718-2-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-17T11:20:12","name":"[v1,1/5] ldlex.l: CRC64","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230217112016.19718-2-binutils@emagii.com/mbox/"},{"id":58513,"url":"https://patchwork.plctlab.org/api/1.2/patches/58513/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230217112016.19718-3-binutils@emagii.com/","msgid":"<20230217112016.19718-3-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-17T11:20:13","name":"[v1,2/5] ldgram.y: CRC64","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230217112016.19718-3-binutils@emagii.com/mbox/"},{"id":58591,"url":"https://patchwork.plctlab.org/api/1.2/patches/58591/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230217135446.26053-2-binutils@emagii.com/","msgid":"<20230217135446.26053-2-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-17T13:54:42","name":"[v1,1/5] ldlex.l: CRC64","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230217135446.26053-2-binutils@emagii.com/mbox/"},{"id":58593,"url":"https://patchwork.plctlab.org/api/1.2/patches/58593/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230217135446.26053-3-binutils@emagii.com/","msgid":"<20230217135446.26053-3-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-17T13:54:43","name":"[v1,2/5] ldgram.y: CRC64","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230217135446.26053-3-binutils@emagii.com/mbox/"},{"id":58589,"url":"https://patchwork.plctlab.org/api/1.2/patches/58589/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230217135446.26053-4-binutils@emagii.com/","msgid":"<20230217135446.26053-4-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-17T13:54:44","name":"[v1,3/5] Calculate CRC64 over the .text area","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230217135446.26053-4-binutils@emagii.com/mbox/"},{"id":58590,"url":"https://patchwork.plctlab.org/api/1.2/patches/58590/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230217135446.26053-5-binutils@emagii.com/","msgid":"<20230217135446.26053-5-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-17T13:54:45","name":"[v1,4/5] CRC64 commands documentation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230217135446.26053-5-binutils@emagii.com/mbox/"},{"id":58592,"url":"https://patchwork.plctlab.org/api/1.2/patches/58592/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230217135446.26053-6-binutils@emagii.com/","msgid":"<20230217135446.26053-6-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-17T13:54:46","name":"[v1,5/5] CRC64 testsuite","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230217135446.26053-6-binutils@emagii.com/mbox/"},{"id":58650,"url":"https://patchwork.plctlab.org/api/1.2/patches/58650/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.LSU.2.20.2302171451390.16810@wotan.suse.de/","msgid":"","list_archive_url":null,"date":"2023-02-17T15:03:57","name":"[RFC] Move static archive dependencies into ld","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.LSU.2.20.2302171451390.16810@wotan.suse.de/mbox/"},{"id":58738,"url":"https://patchwork.plctlab.org/api/1.2/patches/58738/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230217174037.11911-2-binutils@emagii.com/","msgid":"<20230217174037.11911-2-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-17T17:40:33","name":"[v2,1/5] ldlex.l: CRC64","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230217174037.11911-2-binutils@emagii.com/mbox/"},{"id":58735,"url":"https://patchwork.plctlab.org/api/1.2/patches/58735/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230217174037.11911-3-binutils@emagii.com/","msgid":"<20230217174037.11911-3-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-17T17:40:34","name":"[v2,2/5] ldgram.y: CRC64","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230217174037.11911-3-binutils@emagii.com/mbox/"},{"id":58736,"url":"https://patchwork.plctlab.org/api/1.2/patches/58736/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230217174037.11911-4-binutils@emagii.com/","msgid":"<20230217174037.11911-4-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-17T17:40:35","name":"[v2,3/5] Calculate CRC64 over the .text area","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230217174037.11911-4-binutils@emagii.com/mbox/"},{"id":58734,"url":"https://patchwork.plctlab.org/api/1.2/patches/58734/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230217174037.11911-5-binutils@emagii.com/","msgid":"<20230217174037.11911-5-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-17T17:40:36","name":"[v2,4/5] CRC64 commands documentation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230217174037.11911-5-binutils@emagii.com/mbox/"},{"id":58737,"url":"https://patchwork.plctlab.org/api/1.2/patches/58737/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230217174037.11911-6-binutils@emagii.com/","msgid":"<20230217174037.11911-6-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-17T17:40:37","name":"[v2,5/5] CRC64 testsuite","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230217174037.11911-6-binutils@emagii.com/mbox/"},{"id":58757,"url":"https://patchwork.plctlab.org/api/1.2/patches/58757/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230217192905.3160819-2-tom@tromey.com/","msgid":"<20230217192905.3160819-2-tom@tromey.com>","list_archive_url":null,"date":"2023-02-17T19:29:02","name":"[1/4] Fix formatting of long function description in chew output","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230217192905.3160819-2-tom@tromey.com/mbox/"},{"id":58758,"url":"https://patchwork.plctlab.org/api/1.2/patches/58758/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230217192905.3160819-3-tom@tromey.com/","msgid":"<20230217192905.3160819-3-tom@tromey.com>","list_archive_url":null,"date":"2023-02-17T19:29:03","name":"[2/4] Don'\''t use chew comments for static functions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230217192905.3160819-3-tom@tromey.com/mbox/"},{"id":58756,"url":"https://patchwork.plctlab.org/api/1.2/patches/58756/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230217192905.3160819-4-tom@tromey.com/","msgid":"<20230217192905.3160819-4-tom@tromey.com>","list_archive_url":null,"date":"2023-02-17T19:29:04","name":"[3/4] Hoist the SECTION comment in opncls.c","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230217192905.3160819-4-tom@tromey.com/mbox/"},{"id":58755,"url":"https://patchwork.plctlab.org/api/1.2/patches/58755/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230217192905.3160819-5-tom@tromey.com/","msgid":"<20230217192905.3160819-5-tom@tromey.com>","list_archive_url":null,"date":"2023-02-17T19:29:05","name":"[4/4] Redefine FUNCTION in doc.str","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230217192905.3160819-5-tom@tromey.com/mbox/"},{"id":58951,"url":"https://patchwork.plctlab.org/api/1.2/patches/58951/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/877cwere3q.fsf@igel.home/","msgid":"<877cwere3q.fsf@igel.home>","list_archive_url":null,"date":"2023-02-18T19:02:49","name":"opcodes: style m68k disassembler output","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/877cwere3q.fsf@igel.home/mbox/"},{"id":59075,"url":"https://patchwork.plctlab.org/api/1.2/patches/59075/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y/GbxH+cM+iKG3WP@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-02-19T03:47:16","name":"Buffer overflow in evax_bfd_print_eobj","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y/GbxH+cM+iKG3WP@squeak.grove.modra.org/mbox/"},{"id":59334,"url":"https://patchwork.plctlab.org/api/1.2/patches/59334/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230219173450.25555-2-binutils@emagii.com/","msgid":"<20230219173450.25555-2-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-19T17:34:46","name":"[v3,1/5] CRC64 commands documentation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230219173450.25555-2-binutils@emagii.com/mbox/"},{"id":59332,"url":"https://patchwork.plctlab.org/api/1.2/patches/59332/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230219173450.25555-3-binutils@emagii.com/","msgid":"<20230219173450.25555-3-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-19T17:34:47","name":"[v3,2/5] CRC64 testsuite","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230219173450.25555-3-binutils@emagii.com/mbox/"},{"id":59333,"url":"https://patchwork.plctlab.org/api/1.2/patches/59333/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230219173450.25555-4-binutils@emagii.com/","msgid":"<20230219173450.25555-4-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-19T17:34:48","name":"[v3,3/5] ldlex.l: CRC64","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230219173450.25555-4-binutils@emagii.com/mbox/"},{"id":59331,"url":"https://patchwork.plctlab.org/api/1.2/patches/59331/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230219173450.25555-5-binutils@emagii.com/","msgid":"<20230219173450.25555-5-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-19T17:34:49","name":"[v3,4/5] ldgram.y: CRC64","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230219173450.25555-5-binutils@emagii.com/mbox/"},{"id":59340,"url":"https://patchwork.plctlab.org/api/1.2/patches/59340/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230219173450.25555-6-binutils@emagii.com/","msgid":"<20230219173450.25555-6-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-19T17:34:50","name":"[v3,5/5] Calculate CRC64 over the .text area","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230219173450.25555-6-binutils@emagii.com/mbox/"},{"id":59338,"url":"https://patchwork.plctlab.org/api/1.2/patches/59338/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230219194549.22554-2-binutils@emagii.com/","msgid":"<20230219194549.22554-2-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-19T19:45:45","name":"[v4,1/5] CRC64 commands documentation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230219194549.22554-2-binutils@emagii.com/mbox/"},{"id":59361,"url":"https://patchwork.plctlab.org/api/1.2/patches/59361/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230219194549.22554-3-binutils@emagii.com/","msgid":"<20230219194549.22554-3-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-19T19:45:46","name":"[v4,2/5] CRC64 testsuite","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230219194549.22554-3-binutils@emagii.com/mbox/"},{"id":59324,"url":"https://patchwork.plctlab.org/api/1.2/patches/59324/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230219194549.22554-4-binutils@emagii.com/","msgid":"<20230219194549.22554-4-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-19T19:45:47","name":"[v4,3/5] ldlex.l: CRC64","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230219194549.22554-4-binutils@emagii.com/mbox/"},{"id":59325,"url":"https://patchwork.plctlab.org/api/1.2/patches/59325/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230219194549.22554-5-binutils@emagii.com/","msgid":"<20230219194549.22554-5-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-19T19:45:48","name":"[v4,4/5] ldgram.y: CRC64","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230219194549.22554-5-binutils@emagii.com/mbox/"},{"id":59360,"url":"https://patchwork.plctlab.org/api/1.2/patches/59360/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230219194549.22554-6-binutils@emagii.com/","msgid":"<20230219194549.22554-6-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-19T19:45:49","name":"[v4,5/5] Calculate CRC64 over the .text area","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230219194549.22554-6-binutils@emagii.com/mbox/"},{"id":59371,"url":"https://patchwork.plctlab.org/api/1.2/patches/59371/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y/LTY//irZ06TbCl@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-02-20T01:56:51","name":"In-memory nested archives","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y/LTY//irZ06TbCl@squeak.grove.modra.org/mbox/"},{"id":59328,"url":"https://patchwork.plctlab.org/api/1.2/patches/59328/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230220082224.415968-1-chigot@adacore.com/","msgid":"<20230220082224.415968-1-chigot@adacore.com>","list_archive_url":null,"date":"2023-02-20T08:22:21","name":"[1/4] gas/testsuite: adjust a test for case insensitive file systems","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230220082224.415968-1-chigot@adacore.com/mbox/"},{"id":59350,"url":"https://patchwork.plctlab.org/api/1.2/patches/59350/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230220082224.415968-2-chigot@adacore.com/","msgid":"<20230220082224.415968-2-chigot@adacore.com>","list_archive_url":null,"date":"2023-02-20T08:22:22","name":"[2/4] ld/testsuite: don'\''t output to /dev/null on mingw hosts","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230220082224.415968-2-chigot@adacore.com/mbox/"},{"id":59358,"url":"https://patchwork.plctlab.org/api/1.2/patches/59358/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230220082224.415968-3-chigot@adacore.com/","msgid":"<20230220082224.415968-3-chigot@adacore.com>","list_archive_url":null,"date":"2023-02-20T08:22:23","name":"[3/4] ld/testsuite: adjust to Windows path separator.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230220082224.415968-3-chigot@adacore.com/mbox/"},{"id":59335,"url":"https://patchwork.plctlab.org/api/1.2/patches/59335/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230220082224.415968-4-chigot@adacore.com/","msgid":"<20230220082224.415968-4-chigot@adacore.com>","list_archive_url":null,"date":"2023-02-20T08:22:24","name":"[4/4] ld/testsuite: handle Windows drive letter in a noinit test","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230220082224.415968-4-chigot@adacore.com/mbox/"},{"id":59456,"url":"https://patchwork.plctlab.org/api/1.2/patches/59456/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230220141328.20441-1-mark@harmstone.com/","msgid":"<20230220141328.20441-1-mark@harmstone.com>","list_archive_url":null,"date":"2023-02-20T14:13:28","name":"ld: Sort section contributions in PDB files","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230220141328.20441-1-mark@harmstone.com/mbox/"},{"id":59466,"url":"https://patchwork.plctlab.org/api/1.2/patches/59466/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230220144302.1234792-1-chigot@adacore.com/","msgid":"<20230220144302.1234792-1-chigot@adacore.com>","list_archive_url":null,"date":"2023-02-20T14:43:02","name":"[v2] ld/testsuite: don'\''t output to /dev/null","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230220144302.1234792-1-chigot@adacore.com/mbox/"},{"id":59759,"url":"https://patchwork.plctlab.org/api/1.2/patches/59759/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230221040650.2337395-1-yunqiang.su@cipunited.com/","msgid":"<20230221040650.2337395-1-yunqiang.su@cipunited.com>","list_archive_url":null,"date":"2023-02-21T04:06:50","name":"MIPS: make mipsisa32 and mipsisa64 link more systematic","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230221040650.2337395-1-yunqiang.su@cipunited.com/mbox/"},{"id":59767,"url":"https://patchwork.plctlab.org/api/1.2/patches/59767/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y/RcPwp09t1wQTFF@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-02-21T05:53:03","name":"alpha-*-vms missing libraries","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y/RcPwp09t1wQTFF@squeak.grove.modra.org/mbox/"},{"id":59769,"url":"https://patchwork.plctlab.org/api/1.2/patches/59769/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y/RcV7KZ8EOf9LeQ@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-02-21T05:53:27","name":"ld-libs test on alpha-vms","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y/RcV7KZ8EOf9LeQ@squeak.grove.modra.org/mbox/"},{"id":59768,"url":"https://patchwork.plctlab.org/api/1.2/patches/59768/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y/RcdkYHUwcnAETA@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-02-21T05:53:58","name":"Both FAIL and PASS \"check sections 2\"?","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y/RcdkYHUwcnAETA@squeak.grove.modra.org/mbox/"},{"id":59807,"url":"https://patchwork.plctlab.org/api/1.2/patches/59807/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230221090331.559683-1-chigot@adacore.com/","msgid":"<20230221090331.559683-1-chigot@adacore.com>","list_archive_url":null,"date":"2023-02-21T09:03:31","name":"ld/testsuite: handle Windows drive letter in persistent section","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230221090331.559683-1-chigot@adacore.com/mbox/"},{"id":59864,"url":"https://patchwork.plctlab.org/api/1.2/patches/59864/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/87v8jv9snh.fsf@redhat.com/","msgid":"<87v8jv9snh.fsf@redhat.com>","list_archive_url":null,"date":"2023-02-21T11:14:58","name":"Commit: Update description of bfd_fill_in_gnu_debuglink_section","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/87v8jv9snh.fsf@redhat.com/mbox/"},{"id":60156,"url":"https://patchwork.plctlab.org/api/1.2/patches/60156/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230221161442.1554824-1-chigot@adacore.com/","msgid":"<20230221161442.1554824-1-chigot@adacore.com>","list_archive_url":null,"date":"2023-02-21T16:14:42","name":"testsuite: prune DOS drive letter in test outputs","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230221161442.1554824-1-chigot@adacore.com/mbox/"},{"id":60284,"url":"https://patchwork.plctlab.org/api/1.2/patches/60284/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y/VMwx4rDcB3csbz@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-02-21T22:59:15","name":"debug_link duplicate file size checks","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y/VMwx4rDcB3csbz@squeak.grove.modra.org/mbox/"},{"id":60522,"url":"https://patchwork.plctlab.org/api/1.2/patches/60522/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2767901e-2ebc-f42f-982b-1b9b6df3b18f@suse.com/","msgid":"<2767901e-2ebc-f42f-982b-1b9b6df3b18f@suse.com>","list_archive_url":null,"date":"2023-02-22T13:14:48","name":"x86: avoid .byte in testcases where possible","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2767901e-2ebc-f42f-982b-1b9b6df3b18f@suse.com/mbox/"},{"id":60572,"url":"https://patchwork.plctlab.org/api/1.2/patches/60572/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230222151639.588269-1-chigot@adacore.com/","msgid":"<20230222151639.588269-1-chigot@adacore.com>","list_archive_url":null,"date":"2023-02-22T15:16:39","name":"[v2] testsuite: prune DOS drive letter in test outputs","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230222151639.588269-1-chigot@adacore.com/mbox/"},{"id":60602,"url":"https://patchwork.plctlab.org/api/1.2/patches/60602/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230222161609.239928-2-binutils@emagii.com/","msgid":"<20230222161609.239928-2-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-22T16:16:00","name":"[v5,01/10] TIMESTAMP: ldlang: process","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230222161609.239928-2-binutils@emagii.com/mbox/"},{"id":60606,"url":"https://patchwork.plctlab.org/api/1.2/patches/60606/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230222161609.239928-3-binutils@emagii.com/","msgid":"<20230222161609.239928-3-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-22T16:16:01","name":"[v5,02/10] DIGEST: NEWS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230222161609.239928-3-binutils@emagii.com/mbox/"},{"id":60597,"url":"https://patchwork.plctlab.org/api/1.2/patches/60597/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230222161609.239928-4-binutils@emagii.com/","msgid":"<20230222161609.239928-4-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-22T16:16:02","name":"[v5,03/10] DIGEST: ld.texi","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230222161609.239928-4-binutils@emagii.com/mbox/"},{"id":60599,"url":"https://patchwork.plctlab.org/api/1.2/patches/60599/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230222161609.239928-5-binutils@emagii.com/","msgid":"<20230222161609.239928-5-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-22T16:16:03","name":"[v5,04/10] LIBCRC: license","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230222161609.239928-5-binutils@emagii.com/mbox/"},{"id":60604,"url":"https://patchwork.plctlab.org/api/1.2/patches/60604/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230222161609.239928-6-binutils@emagii.com/","msgid":"<20230222161609.239928-6-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-22T16:16:04","name":"[v5,05/10] DIGEST: ldlex.l","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230222161609.239928-6-binutils@emagii.com/mbox/"},{"id":60608,"url":"https://patchwork.plctlab.org/api/1.2/patches/60608/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230222161609.239928-7-binutils@emagii.com/","msgid":"<20230222161609.239928-7-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-22T16:16:05","name":"[v5,06/10] DIGEST: ldgram.y","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230222161609.239928-7-binutils@emagii.com/mbox/"},{"id":60609,"url":"https://patchwork.plctlab.org/api/1.2/patches/60609/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230222161609.239928-8-binutils@emagii.com/","msgid":"<20230222161609.239928-8-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-22T16:16:06","name":"[v5,07/10] DIGEST: Makefile.am: add new files","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230222161609.239928-8-binutils@emagii.com/mbox/"},{"id":60603,"url":"https://patchwork.plctlab.org/api/1.2/patches/60603/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230222161609.239928-9-binutils@emagii.com/","msgid":"<20230222161609.239928-9-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-22T16:16:07","name":"[v5,08/10] DIGEST: CRC-32/64 algorithms","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230222161609.239928-9-binutils@emagii.com/mbox/"},{"id":60605,"url":"https://patchwork.plctlab.org/api/1.2/patches/60605/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230222161609.239928-10-binutils@emagii.com/","msgid":"<20230222161609.239928-10-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-22T16:16:08","name":"[v5,09/10] DIGEST: ldmain.c: add CRC calculation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230222161609.239928-10-binutils@emagii.com/mbox/"},{"id":60607,"url":"https://patchwork.plctlab.org/api/1.2/patches/60607/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230222161609.239928-11-binutils@emagii.com/","msgid":"<20230222161609.239928-11-binutils@emagii.com>","list_archive_url":null,"date":"2023-02-22T16:16:09","name":"[v5,10/10] DIGEST: testsuite","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230222161609.239928-11-binutils@emagii.com/mbox/"},{"id":60774,"url":"https://patchwork.plctlab.org/api/1.2/patches/60774/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y/biKm/PHgcgid9l@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-02-23T03:48:58","name":"Test SEC_HAS_CONTENTS before reading section contents","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y/biKm/PHgcgid9l@squeak.grove.modra.org/mbox/"},{"id":60775,"url":"https://patchwork.plctlab.org/api/1.2/patches/60775/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y/biSBwPDeTjESNU@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-02-23T03:49:28","name":"Test SEC_HAS_CONTENTS in relax routines","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y/biSBwPDeTjESNU@squeak.grove.modra.org/mbox/"},{"id":60776,"url":"https://patchwork.plctlab.org/api/1.2/patches/60776/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y/biZsHVn/HEmkal@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-02-23T03:49:58","name":"ip2k: don'\''t look at stab sections without relocs","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y/biZsHVn/HEmkal@squeak.grove.modra.org/mbox/"},{"id":60777,"url":"https://patchwork.plctlab.org/api/1.2/patches/60777/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y/bii4z1P2p0EwAC@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-02-23T03:50:35","name":"dwarf1 .line SEC_HAS_CONTENTS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y/bii4z1P2p0EwAC@squeak.grove.modra.org/mbox/"},{"id":60907,"url":"https://patchwork.plctlab.org/api/1.2/patches/60907/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230223110417.63915-1-chigot@adacore.com/","msgid":"<20230223110417.63915-1-chigot@adacore.com>","list_archive_url":null,"date":"2023-02-23T11:04:17","name":"[v3] testsuite: prune DOS drive letter in test outputs","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230223110417.63915-1-chigot@adacore.com/mbox/"},{"id":60908,"url":"https://patchwork.plctlab.org/api/1.2/patches/60908/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230223111115.3752443-1-yunqiang.su@cipunited.com/","msgid":"<20230223111115.3752443-1-yunqiang.su@cipunited.com>","list_archive_url":null,"date":"2023-02-23T11:11:15","name":"MIPS: support specify isa level when configure","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230223111115.3752443-1-yunqiang.su@cipunited.com/mbox/"},{"id":60954,"url":"https://patchwork.plctlab.org/api/1.2/patches/60954/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230223124519.4228-1-tdevries@suse.de/","msgid":"<20230223124519.4228-1-tdevries@suse.de>","list_archive_url":null,"date":"2023-02-23T12:45:19","name":"gas: Add --force-compress-debug-sections","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230223124519.4228-1-tdevries@suse.de/mbox/"},{"id":61014,"url":"https://patchwork.plctlab.org/api/1.2/patches/61014/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/877651c1-3d70-6985-54b3-e4416bed3048@arm.com/","msgid":"<877651c1-3d70-6985-54b3-e4416bed3048@arm.com>","list_archive_url":null,"date":"2023-02-23T15:18:03","name":"[GAS,Aarch64] Add Binutils support for MEC","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/877651c1-3d70-6985-54b3-e4416bed3048@arm.com/mbox/"},{"id":61037,"url":"https://patchwork.plctlab.org/api/1.2/patches/61037/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/87bklkths4.fsf@redhat.com/","msgid":"<87bklkths4.fsf@redhat.com>","list_archive_url":null,"date":"2023-02-23T17:26:19","name":"Commit: Better caching in elf_find_function","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/87bklkths4.fsf@redhat.com/mbox/"},{"id":61175,"url":"https://patchwork.plctlab.org/api/1.2/patches/61175/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y/htA80wwgArcHQ0@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-02-24T07:53:39","name":"PR30155, ld segfault in _bfd_nearby_section","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y/htA80wwgArcHQ0@squeak.grove.modra.org/mbox/"},{"id":61302,"url":"https://patchwork.plctlab.org/api/1.2/patches/61302/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fe210be6-76c8-155f-f151-15ce767b133f@suse.com/","msgid":"","list_archive_url":null,"date":"2023-02-24T13:02:22","name":"gas: default .debug section compression method adjustments","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fe210be6-76c8-155f-f151-15ce767b133f@suse.com/mbox/"},{"id":61306,"url":"https://patchwork.plctlab.org/api/1.2/patches/61306/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3dba3751-3fa1-0684-b98c-2c383f26c5a6@suse.com/","msgid":"<3dba3751-3fa1-0684-b98c-2c383f26c5a6@suse.com>","list_archive_url":null,"date":"2023-02-24T13:08:25","name":"[1/2] x86: drop redundant calculation of EVEX broadcast size","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3dba3751-3fa1-0684-b98c-2c383f26c5a6@suse.com/mbox/"},{"id":61307,"url":"https://patchwork.plctlab.org/api/1.2/patches/61307/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a68e2ee4-9198-664e-4e62-245ff29494fc@suse.com/","msgid":"","list_archive_url":null,"date":"2023-02-24T13:09:14","name":"[2/2] x86: use swap_2_operands() in build_vex_prefix()","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a68e2ee4-9198-664e-4e62-245ff29494fc@suse.com/mbox/"},{"id":61506,"url":"https://patchwork.plctlab.org/api/1.2/patches/61506/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/87ilfqjb5y.fsf@redhat.com/","msgid":"<87ilfqjb5y.fsf@redhat.com>","list_archive_url":null,"date":"2023-02-25T10:23:53","name":"[PUSHED] Enable styling for GDB (Was: [PATCH] opcodes: style m68k disassembler output)","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/87ilfqjb5y.fsf@redhat.com/mbox/"},{"id":61690,"url":"https://patchwork.plctlab.org/api/1.2/patches/61690/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230227005935.12270-1-mark@harmstone.com/","msgid":"<20230227005935.12270-1-mark@harmstone.com>","list_archive_url":null,"date":"2023-02-27T00:59:35","name":"[v2] ld: Sort section contributions in PDB files","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230227005935.12270-1-mark@harmstone.com/mbox/"},{"id":61924,"url":"https://patchwork.plctlab.org/api/1.2/patches/61924/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9eb9eaf6-2cff-360b-3de6-072d3f8185dc@suse.de/","msgid":"<9eb9eaf6-2cff-360b-3de6-072d3f8185dc@suse.de>","list_archive_url":null,"date":"2023-02-27T11:43:09","name":"gas: Add --compress-debug-sections=force","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9eb9eaf6-2cff-360b-3de6-072d3f8185dc@suse.de/mbox/"},{"id":61954,"url":"https://patchwork.plctlab.org/api/1.2/patches/61954/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230227134135.462271-1-chigot@adacore.com/","msgid":"<20230227134135.462271-1-chigot@adacore.com>","list_archive_url":null,"date":"2023-02-27T13:41:35","name":"gas/testsuite: adjust another test for case insensitive file systems","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230227134135.462271-1-chigot@adacore.com/mbox/"},{"id":62196,"url":"https://patchwork.plctlab.org/api/1.2/patches/62196/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y/1FKI3FT2qt6LnH@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-02-28T00:04:56","name":"Another PE SEC_HAS_CONTENTS test","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y/1FKI3FT2qt6LnH@squeak.grove.modra.org/mbox/"},{"id":62197,"url":"https://patchwork.plctlab.org/api/1.2/patches/62197/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y/1FWTrLectdFgCl@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-02-28T00:05:45","name":"Add some sanity checking in ECOFF lookup_line","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y/1FWTrLectdFgCl@squeak.grove.modra.org/mbox/"},{"id":62198,"url":"https://patchwork.plctlab.org/api/1.2/patches/62198/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y/1FjDQ7XxwI4Zxz@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-02-28T00:06:36","name":"Free ecoff debug info","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y/1FjDQ7XxwI4Zxz@squeak.grove.modra.org/mbox/"},{"id":62205,"url":"https://patchwork.plctlab.org/api/1.2/patches/62205/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230228001633.3602-1-tdevries@suse.de/","msgid":"<20230228001633.3602-1-tdevries@suse.de>","list_archive_url":null,"date":"2023-02-28T00:16:31","name":"[v2,1/3] gas: Unify parsing of --compress-debug-sections","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230228001633.3602-1-tdevries@suse.de/mbox/"},{"id":62206,"url":"https://patchwork.plctlab.org/api/1.2/patches/62206/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230228001633.3602-2-tdevries@suse.de/","msgid":"<20230228001633.3602-2-tdevries@suse.de>","list_archive_url":null,"date":"2023-02-28T00:16:32","name":"[v2,2/3] gas: Handle --compress-debug-sections=subopt1,subopt2","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230228001633.3602-2-tdevries@suse.de/mbox/"},{"id":62204,"url":"https://patchwork.plctlab.org/api/1.2/patches/62204/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230228001633.3602-3-tdevries@suse.de/","msgid":"<20230228001633.3602-3-tdevries@suse.de>","list_archive_url":null,"date":"2023-02-28T00:16:33","name":"[v2,3/3] gas: Add --compress-debug-sections={heuristic-always, heuristic-sizewin}","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230228001633.3602-3-tdevries@suse.de/mbox/"},{"id":62220,"url":"https://patchwork.plctlab.org/api/1.2/patches/62220/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y/1M54x/w6QMpPfQ@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-02-28T00:37:59","name":"chew.c printf of intptr_t","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y/1M54x/w6QMpPfQ@squeak.grove.modra.org/mbox/"},{"id":62640,"url":"https://patchwork.plctlab.org/api/1.2/patches/62640/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2efba8824df3f1bc782b9bd9aa598e2dae02f9ca.1677620627.git.aburgess@redhat.com/","msgid":"<2efba8824df3f1bc782b9bd9aa598e2dae02f9ca.1677620627.git.aburgess@redhat.com>","list_archive_url":null,"date":"2023-02-28T21:44:06","name":"opcodes/arm: adjust whitespace in cpsie instruction","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2efba8824df3f1bc782b9bd9aa598e2dae02f9ca.1677620627.git.aburgess@redhat.com/mbox/"},{"id":62664,"url":"https://patchwork.plctlab.org/api/1.2/patches/62664/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230228224937.3832887-1-dilfridge@gentoo.org/","msgid":"<20230228224937.3832887-1-dilfridge@gentoo.org>","list_archive_url":null,"date":"2023-02-28T22:49:37","name":"[needs,more,eyes] Relink also libopcodes and libgprofng to newly built libiberty.a","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230228224937.3832887-1-dilfridge@gentoo.org/mbox/"}],"public":true,"mbox":"https://patchwork.plctlab.org/bundle/patchwork-bot/binutils-gdb_2023-02/mbox/"},{"id":17,"url":"https://patchwork.plctlab.org/api/1.2/bundles/17/","web_url":"https://patchwork.plctlab.org/bundle/patchwork-bot/binutils-gdb_2023-03/","project":{"id":2,"url":"https://patchwork.plctlab.org/api/1.2/projects/2/","name":"binutils-gdb","link_name":"binutils-gdb","list_id":"binutils.sourceware.org","list_email":"binutils@sourceware.org","web_url":"https://github.com/wangliu-iscas/Patchwork-Bundles/blob/main/binutils-gdb.md","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"name":"binutils-gdb_2023-03","owner":{"id":3,"url":"https://patchwork.plctlab.org/api/1.2/users/3/","username":"patchwork-bot","first_name":"","last_name":"","email":"ouuuleilei@gmail.com"},"patches":[{"id":62751,"url":"https://patchwork.plctlab.org/api/1.2/patches/62751/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y/7Nlh7yA1PLiIvj@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-01T03:59:18","name":"Memory leak in gas do_repeat","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y/7Nlh7yA1PLiIvj@squeak.grove.modra.org/mbox/"},{"id":62752,"url":"https://patchwork.plctlab.org/api/1.2/patches/62752/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y/7Nw2XouT8JokFm@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-01T04:00:03","name":"gas s_fill caused internal error in frag_new","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y/7Nw2XouT8JokFm@squeak.grove.modra.org/mbox/"},{"id":62753,"url":"https://patchwork.plctlab.org/api/1.2/patches/62753/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y/7N5GnBecgnIXQx@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-01T04:00:36","name":"Catch overflow in gas s_space","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y/7N5GnBecgnIXQx@squeak.grove.modra.org/mbox/"},{"id":62932,"url":"https://patchwork.plctlab.org/api/1.2/patches/62932/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301144756.1847278-2-binutils@emagii.com/","msgid":"<20230301144756.1847278-2-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-01T14:47:46","name":"[v6,01/11] DIGEST: LICENSING","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301144756.1847278-2-binutils@emagii.com/mbox/"},{"id":62934,"url":"https://patchwork.plctlab.org/api/1.2/patches/62934/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301144756.1847278-3-binutils@emagii.com/","msgid":"<20230301144756.1847278-3-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-01T14:47:47","name":"[v6,02/11] DIGEST: NEWS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301144756.1847278-3-binutils@emagii.com/mbox/"},{"id":62935,"url":"https://patchwork.plctlab.org/api/1.2/patches/62935/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301144756.1847278-4-binutils@emagii.com/","msgid":"<20230301144756.1847278-4-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-01T14:47:48","name":"[v6,03/11] DIGEST: Documentation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301144756.1847278-4-binutils@emagii.com/mbox/"},{"id":62933,"url":"https://patchwork.plctlab.org/api/1.2/patches/62933/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301144756.1847278-5-binutils@emagii.com/","msgid":"<20230301144756.1847278-5-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-01T14:47:49","name":"[v6,04/11] DIGEST: testsuite","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301144756.1847278-5-binutils@emagii.com/mbox/"},{"id":62937,"url":"https://patchwork.plctlab.org/api/1.2/patches/62937/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301144756.1847278-6-binutils@emagii.com/","msgid":"<20230301144756.1847278-6-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-01T14:47:50","name":"[v6,05/11] DIGEST: ldlex.l","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301144756.1847278-6-binutils@emagii.com/mbox/"},{"id":62941,"url":"https://patchwork.plctlab.org/api/1.2/patches/62941/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301144756.1847278-7-binutils@emagii.com/","msgid":"<20230301144756.1847278-7-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-01T14:47:51","name":"[v6,06/11] DIGEST: ldgram.y","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301144756.1847278-7-binutils@emagii.com/mbox/"},{"id":62939,"url":"https://patchwork.plctlab.org/api/1.2/patches/62939/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301144756.1847278-8-binutils@emagii.com/","msgid":"<20230301144756.1847278-8-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-01T14:47:52","name":"[v6,07/11] DIGEST: ldmain.c","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301144756.1847278-8-binutils@emagii.com/mbox/"},{"id":62940,"url":"https://patchwork.plctlab.org/api/1.2/patches/62940/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301144756.1847278-9-binutils@emagii.com/","msgid":"<20230301144756.1847278-9-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-01T14:47:53","name":"[v6,08/11] DIGEST: ldlang.*: add timestamp","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301144756.1847278-9-binutils@emagii.com/mbox/"},{"id":62944,"url":"https://patchwork.plctlab.org/api/1.2/patches/62944/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301144756.1847278-10-binutils@emagii.com/","msgid":"<20230301144756.1847278-10-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-01T14:47:54","name":"[v6,09/11] DIGEST: calculation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301144756.1847278-10-binutils@emagii.com/mbox/"},{"id":62936,"url":"https://patchwork.plctlab.org/api/1.2/patches/62936/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301144756.1847278-11-binutils@emagii.com/","msgid":"<20230301144756.1847278-11-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-01T14:47:55","name":"[v6,10/11] DIGEST: Makefile.*","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301144756.1847278-11-binutils@emagii.com/mbox/"},{"id":62947,"url":"https://patchwork.plctlab.org/api/1.2/patches/62947/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301144756.1847278-12-binutils@emagii.com/","msgid":"<20230301144756.1847278-12-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-01T14:47:56","name":"[v6,11/11] Build ldint","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301144756.1847278-12-binutils@emagii.com/mbox/"},{"id":62967,"url":"https://patchwork.plctlab.org/api/1.2/patches/62967/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301154513.1850449-2-binutils@emagii.com/","msgid":"<20230301154513.1850449-2-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-01T15:45:03","name":"[v7,01/11] DIGEST: LICENSING","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301154513.1850449-2-binutils@emagii.com/mbox/"},{"id":62966,"url":"https://patchwork.plctlab.org/api/1.2/patches/62966/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301154513.1850449-3-binutils@emagii.com/","msgid":"<20230301154513.1850449-3-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-01T15:45:04","name":"[v7,02/11] DIGEST: NEWS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301154513.1850449-3-binutils@emagii.com/mbox/"},{"id":62971,"url":"https://patchwork.plctlab.org/api/1.2/patches/62971/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301154513.1850449-4-binutils@emagii.com/","msgid":"<20230301154513.1850449-4-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-01T15:45:05","name":"[v7,03/11] DIGEST: Documentation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301154513.1850449-4-binutils@emagii.com/mbox/"},{"id":62973,"url":"https://patchwork.plctlab.org/api/1.2/patches/62973/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301154513.1850449-5-binutils@emagii.com/","msgid":"<20230301154513.1850449-5-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-01T15:45:06","name":"[v7,04/11] DIGEST: testsuite","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301154513.1850449-5-binutils@emagii.com/mbox/"},{"id":62972,"url":"https://patchwork.plctlab.org/api/1.2/patches/62972/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301154513.1850449-6-binutils@emagii.com/","msgid":"<20230301154513.1850449-6-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-01T15:45:07","name":"[v7,05/11] DIGEST: ldlex.l","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301154513.1850449-6-binutils@emagii.com/mbox/"},{"id":62974,"url":"https://patchwork.plctlab.org/api/1.2/patches/62974/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301154513.1850449-7-binutils@emagii.com/","msgid":"<20230301154513.1850449-7-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-01T15:45:08","name":"[v7,06/11] DIGEST: ldgram.y","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301154513.1850449-7-binutils@emagii.com/mbox/"},{"id":62968,"url":"https://patchwork.plctlab.org/api/1.2/patches/62968/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301154513.1850449-8-binutils@emagii.com/","msgid":"<20230301154513.1850449-8-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-01T15:45:09","name":"[v7,07/11] DIGEST: ldmain.c","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301154513.1850449-8-binutils@emagii.com/mbox/"},{"id":62994,"url":"https://patchwork.plctlab.org/api/1.2/patches/62994/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301173022.1851188-8-binutils@emagii.com/","msgid":"<20230301173022.1851188-8-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-01T17:30:19","name":"[v7,08/11] DIGEST: ldlang.*: add timestamp","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301173022.1851188-8-binutils@emagii.com/mbox/"},{"id":62997,"url":"https://patchwork.plctlab.org/api/1.2/patches/62997/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301173022.1851188-9-binutils@emagii.com/","msgid":"<20230301173022.1851188-9-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-01T17:30:20","name":"[v7,09/11] DIGEST: calculation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301173022.1851188-9-binutils@emagii.com/mbox/"},{"id":62995,"url":"https://patchwork.plctlab.org/api/1.2/patches/62995/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301173022.1851188-10-binutils@emagii.com/","msgid":"<20230301173022.1851188-10-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-01T17:30:21","name":"[v7,10/11] DIGEST: Makefile.*","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301173022.1851188-10-binutils@emagii.com/mbox/"},{"id":62996,"url":"https://patchwork.plctlab.org/api/1.2/patches/62996/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301173022.1851188-11-binutils@emagii.com/","msgid":"<20230301173022.1851188-11-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-01T17:30:22","name":"[v7,11/11] Build ldint","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301173022.1851188-11-binutils@emagii.com/mbox/"},{"id":62999,"url":"https://patchwork.plctlab.org/api/1.2/patches/62999/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301174325.1858522-2-binutils@emagii.com/","msgid":"<20230301174325.1858522-2-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-01T17:43:15","name":"[v8,01/11] DIGEST: LICENSING","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301174325.1858522-2-binutils@emagii.com/mbox/"},{"id":63002,"url":"https://patchwork.plctlab.org/api/1.2/patches/63002/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301174325.1858522-3-binutils@emagii.com/","msgid":"<20230301174325.1858522-3-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-01T17:43:16","name":"[v8,02/11] DIGEST: NEWS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301174325.1858522-3-binutils@emagii.com/mbox/"},{"id":63000,"url":"https://patchwork.plctlab.org/api/1.2/patches/63000/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301174325.1858522-4-binutils@emagii.com/","msgid":"<20230301174325.1858522-4-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-01T17:43:17","name":"[v8,03/11] DIGEST: Documentation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301174325.1858522-4-binutils@emagii.com/mbox/"},{"id":63001,"url":"https://patchwork.plctlab.org/api/1.2/patches/63001/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301174325.1858522-5-binutils@emagii.com/","msgid":"<20230301174325.1858522-5-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-01T17:43:18","name":"[v8,04/11] DIGEST: testsuite","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301174325.1858522-5-binutils@emagii.com/mbox/"},{"id":63005,"url":"https://patchwork.plctlab.org/api/1.2/patches/63005/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301174325.1858522-6-binutils@emagii.com/","msgid":"<20230301174325.1858522-6-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-01T17:43:19","name":"[v8,05/11] DIGEST: ldlex.l","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301174325.1858522-6-binutils@emagii.com/mbox/"},{"id":63006,"url":"https://patchwork.plctlab.org/api/1.2/patches/63006/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301174325.1858522-7-binutils@emagii.com/","msgid":"<20230301174325.1858522-7-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-01T17:43:20","name":"[v8,06/11] DIGEST: ldgram.y","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301174325.1858522-7-binutils@emagii.com/mbox/"},{"id":63007,"url":"https://patchwork.plctlab.org/api/1.2/patches/63007/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301174325.1858522-8-binutils@emagii.com/","msgid":"<20230301174325.1858522-8-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-01T17:43:21","name":"[v8,07/11] DIGEST: ldmain.c","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301174325.1858522-8-binutils@emagii.com/mbox/"},{"id":63008,"url":"https://patchwork.plctlab.org/api/1.2/patches/63008/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301174325.1858522-9-binutils@emagii.com/","msgid":"<20230301174325.1858522-9-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-01T17:43:22","name":"[v8,08/11] DIGEST: ldlang.*: add timestamp","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301174325.1858522-9-binutils@emagii.com/mbox/"},{"id":63010,"url":"https://patchwork.plctlab.org/api/1.2/patches/63010/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301174325.1858522-10-binutils@emagii.com/","msgid":"<20230301174325.1858522-10-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-01T17:43:23","name":"[v8,09/11] DIGEST: calculation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301174325.1858522-10-binutils@emagii.com/mbox/"},{"id":63011,"url":"https://patchwork.plctlab.org/api/1.2/patches/63011/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301174325.1858522-11-binutils@emagii.com/","msgid":"<20230301174325.1858522-11-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-01T17:43:24","name":"[v8,10/11] DIGEST: Makefile.*","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301174325.1858522-11-binutils@emagii.com/mbox/"},{"id":63004,"url":"https://patchwork.plctlab.org/api/1.2/patches/63004/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301174325.1858522-12-binutils@emagii.com/","msgid":"<20230301174325.1858522-12-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-01T17:43:25","name":"[v8,11/11] Build ldint","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230301174325.1858522-12-binutils@emagii.com/mbox/"},{"id":63103,"url":"https://patchwork.plctlab.org/api/1.2/patches/63103/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y//K/QCIk6YuuRF3@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-01T22:00:29","name":"Using .mri in assembly","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y//K/QCIk6YuuRF3@squeak.grove.modra.org/mbox/"},{"id":63104,"url":"https://patchwork.plctlab.org/api/1.2/patches/63104/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y//LGl4CuJ+YN+i5@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-01T22:00:58","name":"More bounds checking in macro_expand","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y//LGl4CuJ+YN+i5@squeak.grove.modra.org/mbox/"},{"id":63167,"url":"https://patchwork.plctlab.org/api/1.2/patches/63167/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230302015222.291088-1-yunqiang.su@cipunited.com/","msgid":"<20230302015222.291088-1-yunqiang.su@cipunited.com>","list_archive_url":null,"date":"2023-03-02T01:52:22","name":"[v2] MIPS: make mipsisa32 and mipsisa64 link more systematic","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230302015222.291088-1-yunqiang.su@cipunited.com/mbox/"},{"id":63263,"url":"https://patchwork.plctlab.org/api/1.2/patches/63263/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230302080137.3346439-1-i.swmail@xen0n.name/","msgid":"<20230302080137.3346439-1-i.swmail@xen0n.name>","list_archive_url":null,"date":"2023-03-02T08:01:37","name":"elfedit: add support for editing e_flags","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230302080137.3346439-1-i.swmail@xen0n.name/mbox/"},{"id":63267,"url":"https://patchwork.plctlab.org/api/1.2/patches/63267/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230302081452.3429908-1-i.swmail@xen0n.name/","msgid":"<20230302081452.3429908-1-i.swmail@xen0n.name>","list_archive_url":null,"date":"2023-03-02T08:14:52","name":"[RESEND] elfedit: add support for editing e_flags","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230302081452.3429908-1-i.swmail@xen0n.name/mbox/"},{"id":63360,"url":"https://patchwork.plctlab.org/api/1.2/patches/63360/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230302112531.200647-2-cupertino.miranda@oracle.com/","msgid":"<20230302112531.200647-2-cupertino.miranda@oracle.com>","list_archive_url":null,"date":"2023-03-02T11:25:31","name":"BPF relocations review / refactoring","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230302112531.200647-2-cupertino.miranda@oracle.com/mbox/"},{"id":63387,"url":"https://patchwork.plctlab.org/api/1.2/patches/63387/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZACQFdX4P07PysEc@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-02T12:01:25","name":"Don'\''t write zeros to a gap in the output file","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZACQFdX4P07PysEc@squeak.grove.modra.org/mbox/"},{"id":63554,"url":"https://patchwork.plctlab.org/api/1.2/patches/63554/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230302201029.vflqmyjxh7qnyxa3@google.com/","msgid":"<20230302201029.vflqmyjxh7qnyxa3@google.com>","list_archive_url":null,"date":"2023-03-02T20:10:29","name":"[v2] ld: Allow R_X86_64_GOTPCREL for call *__tls_get_addr@GOTPCREL(%rip)","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230302201029.vflqmyjxh7qnyxa3@google.com/mbox/"},{"id":63555,"url":"https://patchwork.plctlab.org/api/1.2/patches/63555/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230302201722.1304941-1-maskray@google.com/","msgid":"<20230302201722.1304941-1-maskray@google.com>","list_archive_url":null,"date":"2023-03-02T20:17:22","name":"[v2] ld: Allow R_386_GOT32 for call *__tls_get_addr@GOT(%reg)","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230302201722.1304941-1-maskray@google.com/mbox/"},{"id":63603,"url":"https://patchwork.plctlab.org/api/1.2/patches/63603/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230302220408.1925678-2-binutils@emagii.com/","msgid":"<20230302220408.1925678-2-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-02T22:03:58","name":"[v9,01/11,gdb/testsuite] Fix gdb.rust/watch.exp on ppc64le","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230302220408.1925678-2-binutils@emagii.com/mbox/"},{"id":63598,"url":"https://patchwork.plctlab.org/api/1.2/patches/63598/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230302220408.1925678-3-binutils@emagii.com/","msgid":"<20230302220408.1925678-3-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-02T22:03:59","name":"[v9,02/11] Remove value_in","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230302220408.1925678-3-binutils@emagii.com/mbox/"},{"id":63607,"url":"https://patchwork.plctlab.org/api/1.2/patches/63607/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230302220408.1925678-4-binutils@emagii.com/","msgid":"<20230302220408.1925678-4-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-02T22:04:00","name":"[v9,03/11,gdb/testsuite] Fix gdb.python/py-breakpoint.exp timeouts","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230302220408.1925678-4-binutils@emagii.com/mbox/"},{"id":63602,"url":"https://patchwork.plctlab.org/api/1.2/patches/63602/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230302220408.1925678-5-binutils@emagii.com/","msgid":"<20230302220408.1925678-5-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-02T22:04:01","name":"[v9,04/11] gdb: add HtabPrinter to gdb-gdb.py.in","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230302220408.1925678-5-binutils@emagii.com/mbox/"},{"id":63608,"url":"https://patchwork.plctlab.org/api/1.2/patches/63608/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230302220408.1925678-6-binutils@emagii.com/","msgid":"<20230302220408.1925678-6-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-02T22:04:02","name":"[v9,05/11] Automatic date update in version.in","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230302220408.1925678-6-binutils@emagii.com/mbox/"},{"id":63609,"url":"https://patchwork.plctlab.org/api/1.2/patches/63609/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230302220408.1925678-7-binutils@emagii.com/","msgid":"<20230302220408.1925678-7-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-02T22:04:03","name":"[v9,06/11] Memory leak in gas do_repeat","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230302220408.1925678-7-binutils@emagii.com/mbox/"},{"id":63599,"url":"https://patchwork.plctlab.org/api/1.2/patches/63599/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230302220408.1925678-8-binutils@emagii.com/","msgid":"<20230302220408.1925678-8-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-02T22:04:04","name":"[v9,07/11] gas s_fill caused internal error in frag_new","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230302220408.1925678-8-binutils@emagii.com/mbox/"},{"id":63610,"url":"https://patchwork.plctlab.org/api/1.2/patches/63610/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230302220408.1925678-9-binutils@emagii.com/","msgid":"<20230302220408.1925678-9-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-02T22:04:05","name":"[v9,08/11] Catch overflow in gas s_space","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230302220408.1925678-9-binutils@emagii.com/mbox/"},{"id":63606,"url":"https://patchwork.plctlab.org/api/1.2/patches/63606/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230302220408.1925678-10-binutils@emagii.com/","msgid":"<20230302220408.1925678-10-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-02T22:04:06","name":"[v9,09/11,gdb/testsuite] Add another xfail case in gdb.python/py-record-btrace.exp","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230302220408.1925678-10-binutils@emagii.com/mbox/"},{"id":63605,"url":"https://patchwork.plctlab.org/api/1.2/patches/63605/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230302220408.1925678-11-binutils@emagii.com/","msgid":"<20230302220408.1925678-11-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-02T22:04:07","name":"[v9,10/11] Fix btrace regression","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230302220408.1925678-11-binutils@emagii.com/mbox/"},{"id":63601,"url":"https://patchwork.plctlab.org/api/1.2/patches/63601/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230302220408.1925678-12-binutils@emagii.com/","msgid":"<20230302220408.1925678-12-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-02T22:04:08","name":"[v9,11/11] Fix typo with my email address","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230302220408.1925678-12-binutils@emagii.com/mbox/"},{"id":63630,"url":"https://patchwork.plctlab.org/api/1.2/patches/63630/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230302231051.1928782-2-binutils@emagii.com/","msgid":"<20230302231051.1928782-2-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-02T23:10:41","name":"[v10,01/11] DIGEST: LICENSING","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230302231051.1928782-2-binutils@emagii.com/mbox/"},{"id":63632,"url":"https://patchwork.plctlab.org/api/1.2/patches/63632/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230302231051.1928782-3-binutils@emagii.com/","msgid":"<20230302231051.1928782-3-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-02T23:10:42","name":"[v10,02/11] DIGEST: NEWS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230302231051.1928782-3-binutils@emagii.com/mbox/"},{"id":63635,"url":"https://patchwork.plctlab.org/api/1.2/patches/63635/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230302231051.1928782-4-binutils@emagii.com/","msgid":"<20230302231051.1928782-4-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-02T23:10:43","name":"[v10,03/11] DIGEST: Documentation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230302231051.1928782-4-binutils@emagii.com/mbox/"},{"id":63633,"url":"https://patchwork.plctlab.org/api/1.2/patches/63633/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230302231051.1928782-5-binutils@emagii.com/","msgid":"<20230302231051.1928782-5-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-02T23:10:44","name":"[v10,04/11] DIGEST: testsuite","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230302231051.1928782-5-binutils@emagii.com/mbox/"},{"id":63631,"url":"https://patchwork.plctlab.org/api/1.2/patches/63631/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230302231051.1928782-6-binutils@emagii.com/","msgid":"<20230302231051.1928782-6-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-02T23:10:45","name":"[v10,05/11] DIGEST: ldlex.l","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230302231051.1928782-6-binutils@emagii.com/mbox/"},{"id":63636,"url":"https://patchwork.plctlab.org/api/1.2/patches/63636/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230302231051.1928782-7-binutils@emagii.com/","msgid":"<20230302231051.1928782-7-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-02T23:10:46","name":"[v10,06/11] DIGEST: ldgram.y","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230302231051.1928782-7-binutils@emagii.com/mbox/"},{"id":63634,"url":"https://patchwork.plctlab.org/api/1.2/patches/63634/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230302231051.1928782-8-binutils@emagii.com/","msgid":"<20230302231051.1928782-8-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-02T23:10:47","name":"[v10,07/11] DIGEST: ldmain.c","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230302231051.1928782-8-binutils@emagii.com/mbox/"},{"id":63640,"url":"https://patchwork.plctlab.org/api/1.2/patches/63640/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230302231051.1928782-9-binutils@emagii.com/","msgid":"<20230302231051.1928782-9-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-02T23:10:48","name":"[v10,08/11] DIGEST: ldlang.*: add timestamp","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230302231051.1928782-9-binutils@emagii.com/mbox/"},{"id":63642,"url":"https://patchwork.plctlab.org/api/1.2/patches/63642/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230302231051.1928782-10-binutils@emagii.com/","msgid":"<20230302231051.1928782-10-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-02T23:10:49","name":"[v10,09/11] DIGEST: calculation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230302231051.1928782-10-binutils@emagii.com/mbox/"},{"id":63641,"url":"https://patchwork.plctlab.org/api/1.2/patches/63641/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230302231051.1928782-11-binutils@emagii.com/","msgid":"<20230302231051.1928782-11-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-02T23:10:50","name":"[v10,10/11] DIGEST: Makefile.*","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230302231051.1928782-11-binutils@emagii.com/mbox/"},{"id":63644,"url":"https://patchwork.plctlab.org/api/1.2/patches/63644/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230302231051.1928782-12-binutils@emagii.com/","msgid":"<20230302231051.1928782-12-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-02T23:10:51","name":"[v10,11/11] Build ldint","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230302231051.1928782-12-binutils@emagii.com/mbox/"},{"id":63749,"url":"https://patchwork.plctlab.org/api/1.2/patches/63749/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZAFthsObl5Xz7luZ@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-03T03:46:14","name":"binutils coff type list","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZAFthsObl5Xz7luZ@squeak.grove.modra.org/mbox/"},{"id":63750,"url":"https://patchwork.plctlab.org/api/1.2/patches/63750/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZAFtv3Y3nogpi2mk@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-03T03:47:11","name":"Tidy type handling in binutils/rdcoff.c","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZAFtv3Y3nogpi2mk@squeak.grove.modra.org/mbox/"},{"id":63885,"url":"https://patchwork.plctlab.org/api/1.2/patches/63885/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d42f8a58-0fb2-797e-2313-ba4c8a415b4b@suse.com/","msgid":"","list_archive_url":null,"date":"2023-03-03T12:56:20","name":"[01/18] x86: introduce .insn directive","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d42f8a58-0fb2-797e-2313-ba4c8a415b4b@suse.com/mbox/"},{"id":63887,"url":"https://patchwork.plctlab.org/api/1.2/patches/63887/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3bab7c05-755b-f494-8d7a-0183ab14563a@suse.com/","msgid":"<3bab7c05-755b-f494-8d7a-0183ab14563a@suse.com>","list_archive_url":null,"date":"2023-03-03T12:57:00","name":"[02/18] x86: parse VEX and alike specifiers for .insn","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3bab7c05-755b-f494-8d7a-0183ab14563a@suse.com/mbox/"},{"id":63889,"url":"https://patchwork.plctlab.org/api/1.2/patches/63889/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/242fa8c9-44f3-43e8-fbbd-4248a6abec18@suse.com/","msgid":"<242fa8c9-44f3-43e8-fbbd-4248a6abec18@suse.com>","list_archive_url":null,"date":"2023-03-03T12:57:39","name":"[03/18] x86: parse special opcode modifiers for .insn","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/242fa8c9-44f3-43e8-fbbd-4248a6abec18@suse.com/mbox/"},{"id":63892,"url":"https://patchwork.plctlab.org/api/1.2/patches/63892/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2ab58b70-a02f-cba3-8131-c54eb81b109a@suse.com/","msgid":"<2ab58b70-a02f-cba3-8131-c54eb81b109a@suse.com>","list_archive_url":null,"date":"2023-03-03T12:58:12","name":"[04/18] x86: use set_rex_vrex() also for short-form handling","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2ab58b70-a02f-cba3-8131-c54eb81b109a@suse.com/mbox/"},{"id":63893,"url":"https://patchwork.plctlab.org/api/1.2/patches/63893/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/34990244-84ae-bd27-04c3-1632ad5d7841@suse.com/","msgid":"<34990244-84ae-bd27-04c3-1632ad5d7841@suse.com>","list_archive_url":null,"date":"2023-03-03T12:58:33","name":"[05/18] x86: move more disp processing out of md_assemble()","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/34990244-84ae-bd27-04c3-1632ad5d7841@suse.com/mbox/"},{"id":63895,"url":"https://patchwork.plctlab.org/api/1.2/patches/63895/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/83d24f6c-14a1-2086-855e-453d5a9f3117@suse.com/","msgid":"<83d24f6c-14a1-2086-855e-453d5a9f3117@suse.com>","list_archive_url":null,"date":"2023-03-03T12:59:23","name":"[06/18] x86-64: adjust REX-prefix part of SSE2AVX test","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/83d24f6c-14a1-2086-855e-453d5a9f3117@suse.com/mbox/"},{"id":63896,"url":"https://patchwork.plctlab.org/api/1.2/patches/63896/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/462c093e-13a0-0aff-2dad-e4656180ea9c@suse.com/","msgid":"<462c093e-13a0-0aff-2dad-e4656180ea9c@suse.com>","list_archive_url":null,"date":"2023-03-03T13:00:05","name":"[07/18] x86: re-work build_modrm_byte()'\''s register assignment","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/462c093e-13a0-0aff-2dad-e4656180ea9c@suse.com/mbox/"},{"id":63897,"url":"https://patchwork.plctlab.org/api/1.2/patches/63897/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7a373ee5-4f74-0d63-3995-81b3dc05809c@suse.com/","msgid":"<7a373ee5-4f74-0d63-3995-81b3dc05809c@suse.com>","list_archive_url":null,"date":"2023-03-03T13:00:50","name":"[08/18] x86: VexVVVV is now merely a boolean","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7a373ee5-4f74-0d63-3995-81b3dc05809c@suse.com/mbox/"},{"id":63898,"url":"https://patchwork.plctlab.org/api/1.2/patches/63898/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5f7617d7-f545-cb43-e133-080abb5ede88@suse.com/","msgid":"<5f7617d7-f545-cb43-e133-080abb5ede88@suse.com>","list_archive_url":null,"date":"2023-03-03T13:01:14","name":"[09/18] x86: drop \"shimm\" special case template expansions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5f7617d7-f545-cb43-e133-080abb5ede88@suse.com/mbox/"},{"id":63899,"url":"https://patchwork.plctlab.org/api/1.2/patches/63899/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/42f27545-f571-c78f-415c-50817730faea@suse.com/","msgid":"<42f27545-f571-c78f-415c-50817730faea@suse.com>","list_archive_url":null,"date":"2023-03-03T13:01:41","name":"[10/18] x86/AT&T: restrict recognition of the \"absolute branch\" prefix character","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/42f27545-f571-c78f-415c-50817730faea@suse.com/mbox/"},{"id":63900,"url":"https://patchwork.plctlab.org/api/1.2/patches/63900/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c9bfa265-6d45-fc33-5b1b-db0b95824d92@suse.com/","msgid":"","list_archive_url":null,"date":"2023-03-03T13:02:44","name":"[11/18] x86: process instruction operands for .insn","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c9bfa265-6d45-fc33-5b1b-db0b95824d92@suse.com/mbox/"},{"id":63902,"url":"https://patchwork.plctlab.org/api/1.2/patches/63902/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/689eb629-ad65-4611-2a22-ac0dea62590d@suse.com/","msgid":"<689eb629-ad65-4611-2a22-ac0dea62590d@suse.com>","list_archive_url":null,"date":"2023-03-03T13:03:17","name":"[12/18] x86: decouple broadcast type and bytes fields","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/689eb629-ad65-4611-2a22-ac0dea62590d@suse.com/mbox/"},{"id":63903,"url":"https://patchwork.plctlab.org/api/1.2/patches/63903/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3bbf02eb-364b-88de-d6c5-3e63a79ee602@suse.com/","msgid":"<3bbf02eb-364b-88de-d6c5-3e63a79ee602@suse.com>","list_archive_url":null,"date":"2023-03-03T13:03:51","name":"[13/18] x86: handle EVEX Disp8 for .insn","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3bbf02eb-364b-88de-d6c5-3e63a79ee602@suse.com/mbox/"},{"id":63904,"url":"https://patchwork.plctlab.org/api/1.2/patches/63904/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/433b1d03-2e38-8b3f-be46-c859e678959f@suse.com/","msgid":"<433b1d03-2e38-8b3f-be46-c859e678959f@suse.com>","list_archive_url":null,"date":"2023-03-03T13:04:32","name":"[14/18] x86: allow for multiple immediates in output_disp()","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/433b1d03-2e38-8b3f-be46-c859e678959f@suse.com/mbox/"},{"id":63905,"url":"https://patchwork.plctlab.org/api/1.2/patches/63905/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d85d3d06-46e5-2f23-660a-0daaa9e5088f@suse.com/","msgid":"","list_archive_url":null,"date":"2023-03-03T13:05:00","name":"[15/18] x86: handle immediate operands for .insn","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d85d3d06-46e5-2f23-660a-0daaa9e5088f@suse.com/mbox/"},{"id":63906,"url":"https://patchwork.plctlab.org/api/1.2/patches/63906/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/14ee4656-f39a-59c4-48d0-c397b77ad969@suse.com/","msgid":"<14ee4656-f39a-59c4-48d0-c397b77ad969@suse.com>","list_archive_url":null,"date":"2023-03-03T13:05:36","name":"[16/18] x86: document .insn","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/14ee4656-f39a-59c4-48d0-c397b77ad969@suse.com/mbox/"},{"id":63907,"url":"https://patchwork.plctlab.org/api/1.2/patches/63907/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/10b9c1df-587e-e788-641b-43ccde48be21@suse.com/","msgid":"<10b9c1df-587e-e788-641b-43ccde48be21@suse.com>","list_archive_url":null,"date":"2023-03-03T13:06:25","name":"[17/18] x86: convert testcases to use .insn","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/10b9c1df-587e-e788-641b-43ccde48be21@suse.com/mbox/"},{"id":63908,"url":"https://patchwork.plctlab.org/api/1.2/patches/63908/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/390b97ee-c38a-4239-01a4-32d17ecdf44c@suse.com/","msgid":"<390b97ee-c38a-4239-01a4-32d17ecdf44c@suse.com>","list_archive_url":null,"date":"2023-03-03T13:06:56","name":"[RFC,18/18] x86: .insn example - VEX-encoded instructions of original Xeon Phi","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/390b97ee-c38a-4239-01a4-32d17ecdf44c@suse.com/mbox/"},{"id":63958,"url":"https://patchwork.plctlab.org/api/1.2/patches/63958/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230303144706.1977061-2-binutils@emagii.com/","msgid":"<20230303144706.1977061-2-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-03T14:46:56","name":"[v11,01/11] DIGEST: LICENSING","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230303144706.1977061-2-binutils@emagii.com/mbox/"},{"id":63953,"url":"https://patchwork.plctlab.org/api/1.2/patches/63953/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230303144706.1977061-3-binutils@emagii.com/","msgid":"<20230303144706.1977061-3-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-03T14:46:57","name":"[v11,02/11] DIGEST: NEWS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230303144706.1977061-3-binutils@emagii.com/mbox/"},{"id":63954,"url":"https://patchwork.plctlab.org/api/1.2/patches/63954/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230303144706.1977061-4-binutils@emagii.com/","msgid":"<20230303144706.1977061-4-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-03T14:46:58","name":"[v11,03/11] DIGEST: Documentation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230303144706.1977061-4-binutils@emagii.com/mbox/"},{"id":63966,"url":"https://patchwork.plctlab.org/api/1.2/patches/63966/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230303144706.1977061-5-binutils@emagii.com/","msgid":"<20230303144706.1977061-5-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-03T14:46:59","name":"[v11,04/11] DIGEST: testsuite","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230303144706.1977061-5-binutils@emagii.com/mbox/"},{"id":63962,"url":"https://patchwork.plctlab.org/api/1.2/patches/63962/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230303144706.1977061-6-binutils@emagii.com/","msgid":"<20230303144706.1977061-6-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-03T14:47:00","name":"[v11,05/11] DIGEST: ldlex.l","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230303144706.1977061-6-binutils@emagii.com/mbox/"},{"id":63960,"url":"https://patchwork.plctlab.org/api/1.2/patches/63960/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230303144706.1977061-7-binutils@emagii.com/","msgid":"<20230303144706.1977061-7-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-03T14:47:01","name":"[v11,06/11] DIGEST: ldgram.y","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230303144706.1977061-7-binutils@emagii.com/mbox/"},{"id":63964,"url":"https://patchwork.plctlab.org/api/1.2/patches/63964/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230303144706.1977061-8-binutils@emagii.com/","msgid":"<20230303144706.1977061-8-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-03T14:47:02","name":"[v11,07/11] DIGEST: ldmain.c","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230303144706.1977061-8-binutils@emagii.com/mbox/"},{"id":63961,"url":"https://patchwork.plctlab.org/api/1.2/patches/63961/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230303144706.1977061-9-binutils@emagii.com/","msgid":"<20230303144706.1977061-9-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-03T14:47:03","name":"[v11,08/11] DIGEST: ldlang.*: add timestamp","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230303144706.1977061-9-binutils@emagii.com/mbox/"},{"id":63955,"url":"https://patchwork.plctlab.org/api/1.2/patches/63955/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230303144706.1977061-10-binutils@emagii.com/","msgid":"<20230303144706.1977061-10-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-03T14:47:04","name":"[v11,09/11] DIGEST: calculation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230303144706.1977061-10-binutils@emagii.com/mbox/"},{"id":63967,"url":"https://patchwork.plctlab.org/api/1.2/patches/63967/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230303144706.1977061-11-binutils@emagii.com/","msgid":"<20230303144706.1977061-11-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-03T14:47:05","name":"[v11,10/11] DIGEST: Makefile.*","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230303144706.1977061-11-binutils@emagii.com/mbox/"},{"id":63965,"url":"https://patchwork.plctlab.org/api/1.2/patches/63965/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230303144706.1977061-12-binutils@emagii.com/","msgid":"<20230303144706.1977061-12-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-03T14:47:06","name":"[v11,11/11] Build ldint","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230303144706.1977061-12-binutils@emagii.com/mbox/"},{"id":64411,"url":"https://patchwork.plctlab.org/api/1.2/patches/64411/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZAVdsMx3t7PJx6/N@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-06T03:27:44","name":"Correct objdump command line error handling","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZAVdsMx3t7PJx6/N@squeak.grove.modra.org/mbox/"},{"id":64412,"url":"https://patchwork.plctlab.org/api/1.2/patches/64412/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZAVdzGu9AOUk0jwF@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-06T03:28:12","name":"Move nm.c cached line number info to bfd usrdata","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZAVdzGu9AOUk0jwF@squeak.grove.modra.org/mbox/"},{"id":64413,"url":"https://patchwork.plctlab.org/api/1.2/patches/64413/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZAVd75QsC9WDKjib@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-06T03:28:47","name":"Downgrade nm fatal errors to non-fatal","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZAVd75QsC9WDKjib@squeak.grove.modra.org/mbox/"},{"id":64414,"url":"https://patchwork.plctlab.org/api/1.2/patches/64414/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZAVeXfeOtW187hlw@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-06T03:30:37","name":"Downgrade addr2line fatal errors to non-fatal","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZAVeXfeOtW187hlw@squeak.grove.modra.org/mbox/"},{"id":64415,"url":"https://patchwork.plctlab.org/api/1.2/patches/64415/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZAVefjechteynu1f@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-06T03:31:10","name":"Downgrade objdump fatal errors to non-fatal","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZAVefjechteynu1f@squeak.grove.modra.org/mbox/"},{"id":64416,"url":"https://patchwork.plctlab.org/api/1.2/patches/64416/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZAVeo2/RNgqKm+AA@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-06T03:31:47","name":"Correct odd loop in ecoff lookup_line","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZAVeo2/RNgqKm+AA@squeak.grove.modra.org/mbox/"},{"id":64418,"url":"https://patchwork.plctlab.org/api/1.2/patches/64418/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZAVewBOf2ip1On9w@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-06T03:32:16","name":"More _bfd_ecoff_locate_line sanity checks","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZAVewBOf2ip1On9w@squeak.grove.modra.org/mbox/"},{"id":64417,"url":"https://patchwork.plctlab.org/api/1.2/patches/64417/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZAVe3UuTbz+f5v74@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-06T03:32:45","name":"PR30198, Assertion and segfault when linking x86_64 elf and coff","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZAVe3UuTbz+f5v74@squeak.grove.modra.org/mbox/"},{"id":64619,"url":"https://patchwork.plctlab.org/api/1.2/patches/64619/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZAXSk4uW7BEA153b@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-06T11:46:27","name":"macho null dereference read","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZAXSk4uW7BEA153b@squeak.grove.modra.org/mbox/"},{"id":64651,"url":"https://patchwork.plctlab.org/api/1.2/patches/64651/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230306133158.91917-2-binutils@emagii.com/","msgid":"<20230306133158.91917-2-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-06T13:31:48","name":"[v12,01/11] DIGEST: LICENSING","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230306133158.91917-2-binutils@emagii.com/mbox/"},{"id":64652,"url":"https://patchwork.plctlab.org/api/1.2/patches/64652/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230306133158.91917-3-binutils@emagii.com/","msgid":"<20230306133158.91917-3-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-06T13:31:49","name":"[v12,02/11] DIGEST: NEWS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230306133158.91917-3-binutils@emagii.com/mbox/"},{"id":64653,"url":"https://patchwork.plctlab.org/api/1.2/patches/64653/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230306133158.91917-4-binutils@emagii.com/","msgid":"<20230306133158.91917-4-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-06T13:31:50","name":"[v12,03/11] DIGEST: Documentation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230306133158.91917-4-binutils@emagii.com/mbox/"},{"id":64657,"url":"https://patchwork.plctlab.org/api/1.2/patches/64657/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230306133158.91917-5-binutils@emagii.com/","msgid":"<20230306133158.91917-5-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-06T13:31:51","name":"[v12,04/11] DIGEST: testsuite","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230306133158.91917-5-binutils@emagii.com/mbox/"},{"id":64654,"url":"https://patchwork.plctlab.org/api/1.2/patches/64654/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230306133158.91917-6-binutils@emagii.com/","msgid":"<20230306133158.91917-6-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-06T13:31:52","name":"[v12,05/11] DIGEST: ldlex.l","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230306133158.91917-6-binutils@emagii.com/mbox/"},{"id":64655,"url":"https://patchwork.plctlab.org/api/1.2/patches/64655/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230306133158.91917-7-binutils@emagii.com/","msgid":"<20230306133158.91917-7-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-06T13:31:53","name":"[v12,06/11] DIGEST: ldgram.y","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230306133158.91917-7-binutils@emagii.com/mbox/"},{"id":64656,"url":"https://patchwork.plctlab.org/api/1.2/patches/64656/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230306133158.91917-8-binutils@emagii.com/","msgid":"<20230306133158.91917-8-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-06T13:31:54","name":"[v12,07/11] DIGEST: ldmain.c","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230306133158.91917-8-binutils@emagii.com/mbox/"},{"id":64658,"url":"https://patchwork.plctlab.org/api/1.2/patches/64658/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230306133158.91917-9-binutils@emagii.com/","msgid":"<20230306133158.91917-9-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-06T13:31:55","name":"[v12,08/11] DIGEST: ldlang.*: add timestamp","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230306133158.91917-9-binutils@emagii.com/mbox/"},{"id":64661,"url":"https://patchwork.plctlab.org/api/1.2/patches/64661/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230306133158.91917-10-binutils@emagii.com/","msgid":"<20230306133158.91917-10-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-06T13:31:56","name":"[v12,09/11] DIGEST: calculation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230306133158.91917-10-binutils@emagii.com/mbox/"},{"id":64660,"url":"https://patchwork.plctlab.org/api/1.2/patches/64660/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230306133158.91917-11-binutils@emagii.com/","msgid":"<20230306133158.91917-11-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-06T13:31:57","name":"[v12,10/11] DIGEST: Makefile.*","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230306133158.91917-11-binutils@emagii.com/mbox/"},{"id":64659,"url":"https://patchwork.plctlab.org/api/1.2/patches/64659/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230306133158.91917-12-binutils@emagii.com/","msgid":"<20230306133158.91917-12-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-06T13:31:58","name":"[v12,11/11] Build ldint","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230306133158.91917-12-binutils@emagii.com/mbox/"},{"id":65273,"url":"https://patchwork.plctlab.org/api/1.2/patches/65273/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230307050431.288433-1-vladimir.mezentsev@oracle.com/","msgid":"<20230307050431.288433-1-vladimir.mezentsev@oracle.com>","list_archive_url":null,"date":"2023-03-07T05:04:31","name":"[Review,is,needed] gprofng: read Dwarf 5","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230307050431.288433-1-vladimir.mezentsev@oracle.com/mbox/"},{"id":65986,"url":"https://patchwork.plctlab.org/api/1.2/patches/65986/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZAf9qw1lk5r9MWOY@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-08T03:14:51","name":"z8 and z80 coff_reloc16_extra_cases sanity checks","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZAf9qw1lk5r9MWOY@squeak.grove.modra.org/mbox/"},{"id":65987,"url":"https://patchwork.plctlab.org/api/1.2/patches/65987/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZAf96/aiNOmLZEuS@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-08T03:15:55","name":"Regen potfiles","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZAf96/aiNOmLZEuS@squeak.grove.modra.org/mbox/"},{"id":66046,"url":"https://patchwork.plctlab.org/api/1.2/patches/66046/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZAg5M/tmFWFGCq2N@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-08T07:28:51","name":"Tidy pe_ILF_build_a_bfd a little","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZAg5M/tmFWFGCq2N@squeak.grove.modra.org/mbox/"},{"id":66183,"url":"https://patchwork.plctlab.org/api/1.2/patches/66183/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230308125441.356419-2-binutils@emagii.com/","msgid":"<20230308125441.356419-2-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-08T12:54:41","name":"[v1] DIGEST: Disable 64-bit CRC for 32-bit BFD","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230308125441.356419-2-binutils@emagii.com/mbox/"},{"id":66328,"url":"https://patchwork.plctlab.org/api/1.2/patches/66328/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a513b979-d455-eea6-ba19-1af0dff5d4e2@suse.com/","msgid":"","list_archive_url":null,"date":"2023-03-08T16:07:35","name":"[1/4] gas: drop function pointer parameter from macro_init()","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a513b979-d455-eea6-ba19-1af0dff5d4e2@suse.com/mbox/"},{"id":66329,"url":"https://patchwork.plctlab.org/api/1.2/patches/66329/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e7780d8a-ad1c-a738-a7f5-f5b70c46c6fe@suse.com/","msgid":"","list_archive_url":null,"date":"2023-03-08T16:08:17","name":"[2/4] gas: isolate macro_strip_at to macro.c","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e7780d8a-ad1c-a738-a7f5-f5b70c46c6fe@suse.com/mbox/"},{"id":66332,"url":"https://patchwork.plctlab.org/api/1.2/patches/66332/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0cdb6ff1-8f31-8222-629f-cb991a1efb63@suse.com/","msgid":"<0cdb6ff1-8f31-8222-629f-cb991a1efb63@suse.com>","list_archive_url":null,"date":"2023-03-08T16:08:39","name":"[3/4] gas: use flag_mri directly in macro processing","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0cdb6ff1-8f31-8222-629f-cb991a1efb63@suse.com/mbox/"},{"id":66336,"url":"https://patchwork.plctlab.org/api/1.2/patches/66336/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/06908d40-8d11-9540-6932-efb4f54dba0f@suse.com/","msgid":"<06908d40-8d11-9540-6932-efb4f54dba0f@suse.com>","list_archive_url":null,"date":"2023-03-08T16:09:22","name":"[4/4] gas: expose flag_macro_alternate globally","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/06908d40-8d11-9540-6932-efb4f54dba0f@suse.com/mbox/"},{"id":66649,"url":"https://patchwork.plctlab.org/api/1.2/patches/66649/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230309080446.24714-1-nelson@rivosinc.com/","msgid":"<20230309080446.24714-1-nelson@rivosinc.com>","list_archive_url":null,"date":"2023-03-09T08:04:46","name":"RISC-V: Segment fault in riscv_elf_append_rela.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230309080446.24714-1-nelson@rivosinc.com/mbox/"},{"id":66827,"url":"https://patchwork.plctlab.org/api/1.2/patches/66827/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZAnOJ6t4+ezsABPt@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-09T12:16:39","name":"Allow frag address wrapping in absolute section","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZAnOJ6t4+ezsABPt@squeak.grove.modra.org/mbox/"},{"id":66828,"url":"https://patchwork.plctlab.org/api/1.2/patches/66828/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZAnOVl9L363M77Cx@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-09T12:17:26","name":"objdump: report no section contents","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZAnOVl9L363M77Cx@squeak.grove.modra.org/mbox/"},{"id":67175,"url":"https://patchwork.plctlab.org/api/1.2/patches/67175/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230310000817.751962-2-binutils@emagii.com/","msgid":"<20230310000817.751962-2-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-10T00:08:11","name":"[v1,1/7] SECTOR: NEWS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230310000817.751962-2-binutils@emagii.com/mbox/"},{"id":67174,"url":"https://patchwork.plctlab.org/api/1.2/patches/67174/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230310000817.751962-3-binutils@emagii.com/","msgid":"<20230310000817.751962-3-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-10T00:08:12","name":"[v1,2/7] SECTOR: ld.texi","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230310000817.751962-3-binutils@emagii.com/mbox/"},{"id":67177,"url":"https://patchwork.plctlab.org/api/1.2/patches/67177/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230310000817.751962-4-binutils@emagii.com/","msgid":"<20230310000817.751962-4-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-10T00:08:13","name":"[v1,3/7] SECTOR: ldlex.l","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230310000817.751962-4-binutils@emagii.com/mbox/"},{"id":67179,"url":"https://patchwork.plctlab.org/api/1.2/patches/67179/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230310000817.751962-5-binutils@emagii.com/","msgid":"<20230310000817.751962-5-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-10T00:08:14","name":"[v1,4/7] SECTOR: ldgram.y","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230310000817.751962-5-binutils@emagii.com/mbox/"},{"id":67180,"url":"https://patchwork.plctlab.org/api/1.2/patches/67180/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230310000817.751962-6-binutils@emagii.com/","msgid":"<20230310000817.751962-6-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-10T00:08:15","name":"[v1,5/7] SECTOR: language additions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230310000817.751962-6-binutils@emagii.com/mbox/"},{"id":67176,"url":"https://patchwork.plctlab.org/api/1.2/patches/67176/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230310000817.751962-7-binutils@emagii.com/","msgid":"<20230310000817.751962-7-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-10T00:08:16","name":"[v1,6/7] SECTOR: add testsuite","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230310000817.751962-7-binutils@emagii.com/mbox/"},{"id":67178,"url":"https://patchwork.plctlab.org/api/1.2/patches/67178/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230310000817.751962-8-binutils@emagii.com/","msgid":"<20230310000817.751962-8-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-10T00:08:17","name":"[v1,7/7] SECTOR: Makefile.*","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230310000817.751962-8-binutils@emagii.com/mbox/"},{"id":67202,"url":"https://patchwork.plctlab.org/api/1.2/patches/67202/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZAqu271thSCsaKU3@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-10T04:15:23","name":"eh static data","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZAqu271thSCsaKU3@squeak.grove.modra.org/mbox/"},{"id":67293,"url":"https://patchwork.plctlab.org/api/1.2/patches/67293/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f1892080-b6fe-a164-73bb-91cd88302e0f@suse.com/","msgid":"","list_archive_url":null,"date":"2023-03-10T09:25:27","name":"[v2,1/7] RISC-V: minor effort reduction in relocation specifier parsing","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f1892080-b6fe-a164-73bb-91cd88302e0f@suse.com/mbox/"},{"id":67294,"url":"https://patchwork.plctlab.org/api/1.2/patches/67294/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/366e4dcf-e273-a321-dd38-7adf4212c901@suse.com/","msgid":"<366e4dcf-e273-a321-dd38-7adf4212c901@suse.com>","list_archive_url":null,"date":"2023-03-10T09:26:00","name":"[v2,2/7] RISC-V: drop \"percent_op\" parameter from my_getOpcodeExpression()","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/366e4dcf-e273-a321-dd38-7adf4212c901@suse.com/mbox/"},{"id":67296,"url":"https://patchwork.plctlab.org/api/1.2/patches/67296/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5352e5fd-d1c5-4267-c802-73d6074e80ca@suse.com/","msgid":"<5352e5fd-d1c5-4267-c802-73d6074e80ca@suse.com>","list_archive_url":null,"date":"2023-03-10T09:26:25","name":"[v2,3/7] RISC-V: avoid redundant and misleading/wrong error messages","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5352e5fd-d1c5-4267-c802-73d6074e80ca@suse.com/mbox/"},{"id":67297,"url":"https://patchwork.plctlab.org/api/1.2/patches/67297/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ebffbf50-fa83-8e7e-eedd-d9e9d1b4aa04@suse.com/","msgid":"","list_archive_url":null,"date":"2023-03-10T09:27:05","name":"[v2,4/7] RISC-V: don'\''t recognize bogus relocations","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ebffbf50-fa83-8e7e-eedd-d9e9d1b4aa04@suse.com/mbox/"},{"id":67302,"url":"https://patchwork.plctlab.org/api/1.2/patches/67302/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/89f892c8-e378-b81c-7b13-322a7876a252@suse.com/","msgid":"<89f892c8-e378-b81c-7b13-322a7876a252@suse.com>","list_archive_url":null,"date":"2023-03-10T09:27:26","name":"[v2,5/7] RISC-V: relax post-relocation-operator separator expectation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/89f892c8-e378-b81c-7b13-322a7876a252@suse.com/mbox/"},{"id":67301,"url":"https://patchwork.plctlab.org/api/1.2/patches/67301/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/756c5464-9bcb-d78f-c763-4bb5504eec92@suse.com/","msgid":"<756c5464-9bcb-d78f-c763-4bb5504eec92@suse.com>","list_archive_url":null,"date":"2023-03-10T09:27:58","name":"[v2,6/7] RISC-V: test for expected / no unexpected symbols","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/756c5464-9bcb-d78f-c763-4bb5504eec92@suse.com/mbox/"},{"id":67305,"url":"https://patchwork.plctlab.org/api/1.2/patches/67305/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/54b0d4cc-855a-78c7-5233-22f7d454c0c4@suse.com/","msgid":"<54b0d4cc-855a-78c7-5233-22f7d454c0c4@suse.com>","list_archive_url":null,"date":"2023-03-10T09:28:23","name":"[v2,7/7] RISC-V: adjust logic to avoid register name symbols","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/54b0d4cc-855a-78c7-5233-22f7d454c0c4@suse.com/mbox/"},{"id":67308,"url":"https://patchwork.plctlab.org/api/1.2/patches/67308/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/150b4184-62af-3f5c-c07b-24b0c2ae788f@suse.com/","msgid":"<150b4184-62af-3f5c-c07b-24b0c2ae788f@suse.com>","list_archive_url":null,"date":"2023-03-10T09:36:31","name":"[RFC] RISC-V: alter the special character used in FAKE_LABEL_NAME","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/150b4184-62af-3f5c-c07b-24b0c2ae788f@suse.com/mbox/"},{"id":67313,"url":"https://patchwork.plctlab.org/api/1.2/patches/67313/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c7f7f3a2-033c-da49-6e04-9a1df21eef6f@suse.com/","msgid":"","list_archive_url":null,"date":"2023-03-10T09:43:48","name":"gas: apply md_register_arithmetic also to unary '\''+'\''","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c7f7f3a2-033c-da49-6e04-9a1df21eef6f@suse.com/mbox/"},{"id":67317,"url":"https://patchwork.plctlab.org/api/1.2/patches/67317/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/312cb612-378a-be36-6f6c-62df7313975d@suse.com/","msgid":"<312cb612-378a-be36-6f6c-62df7313975d@suse.com>","list_archive_url":null,"date":"2023-03-10T10:11:28","name":"x86: drop identifier_chars[]","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/312cb612-378a-be36-6f6c-62df7313975d@suse.com/mbox/"},{"id":67319,"url":"https://patchwork.plctlab.org/api/1.2/patches/67319/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/97d9240d-2d1a-d7a4-35e4-7cec1f418f38@suse.com/","msgid":"<97d9240d-2d1a-d7a4-35e4-7cec1f418f38@suse.com>","list_archive_url":null,"date":"2023-03-10T10:19:22","name":"[v2,01/14] x86: introduce .insn directive","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/97d9240d-2d1a-d7a4-35e4-7cec1f418f38@suse.com/mbox/"},{"id":67320,"url":"https://patchwork.plctlab.org/api/1.2/patches/67320/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8df023f9-58a5-dca7-badd-f3354ed18442@suse.com/","msgid":"<8df023f9-58a5-dca7-badd-f3354ed18442@suse.com>","list_archive_url":null,"date":"2023-03-10T10:19:50","name":"[v2,02/14] x86: parse VEX and alike specifiers for .insn","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8df023f9-58a5-dca7-badd-f3354ed18442@suse.com/mbox/"},{"id":67321,"url":"https://patchwork.plctlab.org/api/1.2/patches/67321/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5771df73-12d8-e880-a051-86c09d6bdb06@suse.com/","msgid":"<5771df73-12d8-e880-a051-86c09d6bdb06@suse.com>","list_archive_url":null,"date":"2023-03-10T10:20:26","name":"[v2,03/14] x86: parse special opcode modifiers for .insn","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5771df73-12d8-e880-a051-86c09d6bdb06@suse.com/mbox/"},{"id":67322,"url":"https://patchwork.plctlab.org/api/1.2/patches/67322/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fba4e20a-8b63-652c-7766-8b0ba47f1672@suse.com/","msgid":"","list_archive_url":null,"date":"2023-03-10T10:21:11","name":"[v2,04/14] x86: re-work build_modrm_byte()'\''s register assignment","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fba4e20a-8b63-652c-7766-8b0ba47f1672@suse.com/mbox/"},{"id":67325,"url":"https://patchwork.plctlab.org/api/1.2/patches/67325/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/08829d31-820b-7dea-5609-de609bf69aa9@suse.com/","msgid":"<08829d31-820b-7dea-5609-de609bf69aa9@suse.com>","list_archive_url":null,"date":"2023-03-10T10:21:48","name":"[v2,05/14] x86: VexVVVV is now merely a boolean","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/08829d31-820b-7dea-5609-de609bf69aa9@suse.com/mbox/"},{"id":67323,"url":"https://patchwork.plctlab.org/api/1.2/patches/67323/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a4fdab7e-bc8f-ff75-6be2-559f053bef28@suse.com/","msgid":"","list_archive_url":null,"date":"2023-03-10T10:22:16","name":"[v2,06/14] x86: drop \"shimm\" special case template expansions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a4fdab7e-bc8f-ff75-6be2-559f053bef28@suse.com/mbox/"},{"id":67326,"url":"https://patchwork.plctlab.org/api/1.2/patches/67326/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/667d9ad0-3165-08cf-dead-efd27a5d267e@suse.com/","msgid":"<667d9ad0-3165-08cf-dead-efd27a5d267e@suse.com>","list_archive_url":null,"date":"2023-03-10T10:22:38","name":"[v2,07/14] x86/AT&T: restrict recognition of the \"absolute branch\" prefix character","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/667d9ad0-3165-08cf-dead-efd27a5d267e@suse.com/mbox/"},{"id":67327,"url":"https://patchwork.plctlab.org/api/1.2/patches/67327/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8d917f97-af55-11f3-a9f8-d5a209725336@suse.com/","msgid":"<8d917f97-af55-11f3-a9f8-d5a209725336@suse.com>","list_archive_url":null,"date":"2023-03-10T10:23:40","name":"[v2,08/14] x86: process instruction operands for .insn","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8d917f97-af55-11f3-a9f8-d5a209725336@suse.com/mbox/"},{"id":67328,"url":"https://patchwork.plctlab.org/api/1.2/patches/67328/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/010a5ae0-91a5-813b-8896-8fd11d5383d7@suse.com/","msgid":"<010a5ae0-91a5-813b-8896-8fd11d5383d7@suse.com>","list_archive_url":null,"date":"2023-03-10T10:24:03","name":"[v2,09/14] x86: handle EVEX Disp8 for .insn","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/010a5ae0-91a5-813b-8896-8fd11d5383d7@suse.com/mbox/"},{"id":67329,"url":"https://patchwork.plctlab.org/api/1.2/patches/67329/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/68848170-59cb-6546-6e7f-527f65a8c1fe@suse.com/","msgid":"<68848170-59cb-6546-6e7f-527f65a8c1fe@suse.com>","list_archive_url":null,"date":"2023-03-10T10:24:53","name":"[v2,10/14] x86: allow for multiple immediates in output_disp()","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/68848170-59cb-6546-6e7f-527f65a8c1fe@suse.com/mbox/"},{"id":67330,"url":"https://patchwork.plctlab.org/api/1.2/patches/67330/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a154c5f8-b5af-320d-f542-5dfccbefba3b@suse.com/","msgid":"","list_archive_url":null,"date":"2023-03-10T10:25:43","name":"[v2,11/14] x86: handle immediate operands for .insn","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a154c5f8-b5af-320d-f542-5dfccbefba3b@suse.com/mbox/"},{"id":67331,"url":"https://patchwork.plctlab.org/api/1.2/patches/67331/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e11eeb2e-0e16-886e-ee81-bf9a57f57965@suse.com/","msgid":"","list_archive_url":null,"date":"2023-03-10T10:26:03","name":"[v2,12/14] x86: document .insn","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e11eeb2e-0e16-886e-ee81-bf9a57f57965@suse.com/mbox/"},{"id":67332,"url":"https://patchwork.plctlab.org/api/1.2/patches/67332/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2b0ca132-9d85-86a8-8b91-828fa66881b8@suse.com/","msgid":"<2b0ca132-9d85-86a8-8b91-828fa66881b8@suse.com>","list_archive_url":null,"date":"2023-03-10T10:26:44","name":"[v2,13/14] x86: convert testcases to use .insn","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2b0ca132-9d85-86a8-8b91-828fa66881b8@suse.com/mbox/"},{"id":67333,"url":"https://patchwork.plctlab.org/api/1.2/patches/67333/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/df8e84be-1e77-07ee-aff6-d457e9b0f818@suse.com/","msgid":"","list_archive_url":null,"date":"2023-03-10T10:27:47","name":"[RFC,v2,14/14] x86: .insn example - VEX-encoded instructions of original Xeon Phi","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/df8e84be-1e77-07ee-aff6-d457e9b0f818@suse.com/mbox/"},{"id":68729,"url":"https://patchwork.plctlab.org/api/1.2/patches/68729/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230313102216.355828-1-och95@yandex.ru/","msgid":"<20230313102216.355828-1-och95@yandex.ru>","list_archive_url":null,"date":"2023-03-13T10:22:16","name":"Fix emit-relocs for aarch64 gold","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230313102216.355828-1-och95@yandex.ru/mbox/"},{"id":69242,"url":"https://patchwork.plctlab.org/api/1.2/patches/69242/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZA/V6rdHyBWRJeg/@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-14T02:03:22","name":"gas/compress-debug.c init all of strm","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZA/V6rdHyBWRJeg/@squeak.grove.modra.org/mbox/"},{"id":69243,"url":"https://patchwork.plctlab.org/api/1.2/patches/69243/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZA/WAkr1NO7joSsy@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-14T02:03:46","name":"gas/ecoff.c: don'\''t use zero struct copies to init","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZA/WAkr1NO7joSsy@squeak.grove.modra.org/mbox/"},{"id":69245,"url":"https://patchwork.plctlab.org/api/1.2/patches/69245/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZA/WGWSYR8IA1rJl@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-14T02:04:09","name":"gas/dwarf2dbg.c init more statics","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZA/WGWSYR8IA1rJl@squeak.grove.modra.org/mbox/"},{"id":69244,"url":"https://patchwork.plctlab.org/api/1.2/patches/69244/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZA/WNm1YCQpP7t+a@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-14T02:04:38","name":"gas .include and .incbin","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZA/WNm1YCQpP7t+a@squeak.grove.modra.org/mbox/"},{"id":69246,"url":"https://patchwork.plctlab.org/api/1.2/patches/69246/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZA/WTCOXOOCfB3kP@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-14T02:05:00","name":"gas/read.c: init more statics","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZA/WTCOXOOCfB3kP@squeak.grove.modra.org/mbox/"},{"id":69247,"url":"https://patchwork.plctlab.org/api/1.2/patches/69247/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZA/Wa/V9ZyhkIDlz@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-14T02:05:31","name":"Sanity check read_section_stabs_debugging_info","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZA/Wa/V9ZyhkIDlz@squeak.grove.modra.org/mbox/"},{"id":69248,"url":"https://patchwork.plctlab.org/api/1.2/patches/69248/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZA/WoJ/0CrDmzojB@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-14T02:06:24","name":"objdump segfault after symbol table error","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZA/WoJ/0CrDmzojB@squeak.grove.modra.org/mbox/"},{"id":69845,"url":"https://patchwork.plctlab.org/api/1.2/patches/69845/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230314220114.1117782-2-binutils@emagii.com/","msgid":"<20230314220114.1117782-2-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-14T22:01:12","name":"[v1,1/3] CHIP: ldlex.l","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230314220114.1117782-2-binutils@emagii.com/mbox/"},{"id":69843,"url":"https://patchwork.plctlab.org/api/1.2/patches/69843/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230314220114.1117782-3-binutils@emagii.com/","msgid":"<20230314220114.1117782-3-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-14T22:01:13","name":"[v1,2/3] CHIP: ldgram.y","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230314220114.1117782-3-binutils@emagii.com/mbox/"},{"id":69844,"url":"https://patchwork.plctlab.org/api/1.2/patches/69844/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230314220114.1117782-4-binutils@emagii.com/","msgid":"<20230314220114.1117782-4-binutils@emagii.com>","list_archive_url":null,"date":"2023-03-14T22:01:14","name":"[v1,3/3] CHIP: language additions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230314220114.1117782-4-binutils@emagii.com/mbox/"},{"id":70532,"url":"https://patchwork.plctlab.org/api/1.2/patches/70532/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZBJprOGHAKOvXNTu@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-16T00:58:20","name":"PR30217, dynamic relocations using local dynamic symbols","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZBJprOGHAKOvXNTu@squeak.grove.modra.org/mbox/"},{"id":70595,"url":"https://patchwork.plctlab.org/api/1.2/patches/70595/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZBK+tK3Heqd68P3Y@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-16T07:01:08","name":"cpu/mem.opc whitespace tidy","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZBK+tK3Heqd68P3Y@squeak.grove.modra.org/mbox/"},{"id":70703,"url":"https://patchwork.plctlab.org/api/1.2/patches/70703/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230316101736.482737-2-chigot@adacore.com/","msgid":"<20230316101736.482737-2-chigot@adacore.com>","list_archive_url":null,"date":"2023-03-16T10:17:32","name":"[1/5] configure: add new target aarch64-*-nto*","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230316101736.482737-2-chigot@adacore.com/mbox/"},{"id":70705,"url":"https://patchwork.plctlab.org/api/1.2/patches/70705/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230316101736.482737-3-chigot@adacore.com/","msgid":"<20230316101736.482737-3-chigot@adacore.com>","list_archive_url":null,"date":"2023-03-16T10:17:33","name":"[2/5] readelf: add support for QNT_STACK note subsections","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230316101736.482737-3-chigot@adacore.com/mbox/"},{"id":70706,"url":"https://patchwork.plctlab.org/api/1.2/patches/70706/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230316101736.482737-4-chigot@adacore.com/","msgid":"<20230316101736.482737-4-chigot@adacore.com>","list_archive_url":null,"date":"2023-03-16T10:17:34","name":"[3/5] ld: add support of QNX stack arguments for aarch64nto","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230316101736.482737-4-chigot@adacore.com/mbox/"},{"id":70704,"url":"https://patchwork.plctlab.org/api/1.2/patches/70704/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230316101736.482737-5-chigot@adacore.com/","msgid":"<20230316101736.482737-5-chigot@adacore.com>","list_archive_url":null,"date":"2023-03-16T10:17:35","name":"[4/5] ld/testsuite: add aarch64nto to ld-aarch64","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230316101736.482737-5-chigot@adacore.com/mbox/"},{"id":70707,"url":"https://patchwork.plctlab.org/api/1.2/patches/70707/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230316101736.482737-6-chigot@adacore.com/","msgid":"<20230316101736.482737-6-chigot@adacore.com>","list_archive_url":null,"date":"2023-03-16T10:17:36","name":"[5/5] ld/testsuite: disable ilp32 tests for aarch64-qnx","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230316101736.482737-6-chigot@adacore.com/mbox/"},{"id":70782,"url":"https://patchwork.plctlab.org/api/1.2/patches/70782/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230316132101.205752-1-christophe.lyon@linaro.org/","msgid":"<20230316132101.205752-1-christophe.lyon@linaro.org>","list_archive_url":null,"date":"2023-03-16T13:21:01","name":"Re: Add --enable-linker-version option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230316132101.205752-1-christophe.lyon@linaro.org/mbox/"},{"id":71031,"url":"https://patchwork.plctlab.org/api/1.2/patches/71031/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230317015323.567132-1-jiawei@iscas.ac.cn/","msgid":"<20230317015323.567132-1-jiawei@iscas.ac.cn>","list_archive_url":null,"date":"2023-03-17T01:53:23","name":"RISC-V: Adjust the '\''print_insn'\'' return value of disassembling.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230317015323.567132-1-jiawei@iscas.ac.cn/mbox/"},{"id":71117,"url":"https://patchwork.plctlab.org/api/1.2/patches/71117/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZBQb0o0YlU860KEo@fedora/","msgid":"","list_archive_url":null,"date":"2023-03-17T07:50:42","name":"Add support to readelf for the PT_OPENBSD_MUTABLE segment type.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZBQb0o0YlU860KEo@fedora/mbox/"},{"id":71230,"url":"https://patchwork.plctlab.org/api/1.2/patches/71230/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZBRD1+lZYMBOT2i6@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-17T10:41:27","name":"strange segfault i386-dis.c:9815:28","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZBRD1+lZYMBOT2i6@squeak.grove.modra.org/mbox/"},{"id":71234,"url":"https://patchwork.plctlab.org/api/1.2/patches/71234/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZBRE2M3WrYfRkhVz@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-17T10:45:44","name":"Another source_sh","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZBRE2M3WrYfRkhVz@squeak.grove.modra.org/mbox/"},{"id":71237,"url":"https://patchwork.plctlab.org/api/1.2/patches/71237/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZBRE8g4zs0fVGz5o@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-17T10:46:10","name":"mach-o: out of memory in get_dynamic_reloc_upper_bound","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZBRE8g4zs0fVGz5o@squeak.grove.modra.org/mbox/"},{"id":71244,"url":"https://patchwork.plctlab.org/api/1.2/patches/71244/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230317105552.82190-1-nelson@rivosinc.com/","msgid":"<20230317105552.82190-1-nelson@rivosinc.com>","list_archive_url":null,"date":"2023-03-17T10:55:52","name":"RISC-V: Clarify link behaviors of R_RISCV_32/64 relocations with ABS symbol.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230317105552.82190-1-nelson@rivosinc.com/mbox/"},{"id":71345,"url":"https://patchwork.plctlab.org/api/1.2/patches/71345/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230317160045.502282-2-cupertino.miranda@oracle.com/","msgid":"<20230317160045.502282-2-cupertino.miranda@oracle.com>","list_archive_url":null,"date":"2023-03-17T16:00:44","name":"[1/2] Reloc howto access broken for BPF","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230317160045.502282-2-cupertino.miranda@oracle.com/mbox/"},{"id":71346,"url":"https://patchwork.plctlab.org/api/1.2/patches/71346/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230317160045.502282-3-cupertino.miranda@oracle.com/","msgid":"<20230317160045.502282-3-cupertino.miranda@oracle.com>","list_archive_url":null,"date":"2023-03-17T16:00:45","name":"[2/2] Changed ld and gas BPF tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230317160045.502282-3-cupertino.miranda@oracle.com/mbox/"},{"id":71521,"url":"https://patchwork.plctlab.org/api/1.2/patches/71521/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230317233448.1832535-1-vladimir.mezentsev@oracle.com/","msgid":"<20230317233448.1832535-1-vladimir.mezentsev@oracle.com>","list_archive_url":null,"date":"2023-03-17T23:34:48","name":"[Review,is,neded] gprofng: Use prototype to call libc functions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230317233448.1832535-1-vladimir.mezentsev@oracle.com/mbox/"},{"id":71749,"url":"https://patchwork.plctlab.org/api/1.2/patches/71749/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZBb3JpbiFebpIfHc@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-19T11:51:02","name":"ctf segfaults","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZBb3JpbiFebpIfHc@squeak.grove.modra.org/mbox/"},{"id":71751,"url":"https://patchwork.plctlab.org/api/1.2/patches/71751/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZBb3UOUJo8DAMRJy@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-19T11:51:44","name":"Another sanity check for read_section_stabs_debugging_info","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZBb3UOUJo8DAMRJy@squeak.grove.modra.org/mbox/"},{"id":71752,"url":"https://patchwork.plctlab.org/api/1.2/patches/71752/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZBb3eQ0ulZBDWzmK@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-19T11:52:25","name":"rewrite_elf_program_header and want_p_paddr_set_to_zero","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZBb3eQ0ulZBDWzmK@squeak.grove.modra.org/mbox/"},{"id":71753,"url":"https://patchwork.plctlab.org/api/1.2/patches/71753/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZBb3oOZ4J35lf6nK@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-19T11:53:04","name":"XCOFF archive sanity check","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZBb3oOZ4J35lf6nK@squeak.grove.modra.org/mbox/"},{"id":71754,"url":"https://patchwork.plctlab.org/api/1.2/patches/71754/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZBb3vmeOkA/l+tlY@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-19T11:53:34","name":"Regen ld/po/BLD-POTFILES.in","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZBb3vmeOkA/l+tlY@squeak.grove.modra.org/mbox/"},{"id":71942,"url":"https://patchwork.plctlab.org/api/1.2/patches/71942/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230320033444.2819-1-jiawei@iscas.ac.cn/","msgid":"<20230320033444.2819-1-jiawei@iscas.ac.cn>","list_archive_url":null,"date":"2023-03-20T03:34:44","name":"[v2] RISC-V: Fix disassemble fetch fail return value.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230320033444.2819-1-jiawei@iscas.ac.cn/mbox/"},{"id":72083,"url":"https://patchwork.plctlab.org/api/1.2/patches/72083/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZBg2d0PwGiSJ3tft@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-20T10:33:27","name":"libctf: unused variable","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZBg2d0PwGiSJ3tft@squeak.grove.modra.org/mbox/"},{"id":72295,"url":"https://patchwork.plctlab.org/api/1.2/patches/72295/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230320170313.354203-1-hjl.tools@gmail.com/","msgid":"<20230320170313.354203-1-hjl.tools@gmail.com>","list_archive_url":null,"date":"2023-03-20T17:03:13","name":"x86: Check unbalanced braces in memory reference","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230320170313.354203-1-hjl.tools@gmail.com/mbox/"},{"id":72904,"url":"https://patchwork.plctlab.org/api/1.2/patches/72904/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230321142839.672428-1-szabolcs.nagy@arm.com/","msgid":"<20230321142839.672428-1-szabolcs.nagy@arm.com>","list_archive_url":null,"date":"2023-03-21T14:28:39","name":"[1/3] bfd: aarch64: Refactor stub sizing code","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230321142839.672428-1-szabolcs.nagy@arm.com/mbox/"},{"id":72903,"url":"https://patchwork.plctlab.org/api/1.2/patches/72903/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230321142848.672474-1-szabolcs.nagy@arm.com/","msgid":"<20230321142848.672474-1-szabolcs.nagy@arm.com>","list_archive_url":null,"date":"2023-03-21T14:28:48","name":"[2/3] bfd: aarch64: Fix stubs that may break BTI PR30076","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230321142848.672474-1-szabolcs.nagy@arm.com/mbox/"},{"id":72905,"url":"https://patchwork.plctlab.org/api/1.2/patches/72905/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230321142857.672520-1-szabolcs.nagy@arm.com/","msgid":"<20230321142857.672520-1-szabolcs.nagy@arm.com>","list_archive_url":null,"date":"2023-03-21T14:28:57","name":"[3/3] bfd: aarch64: Optimize BTI stubs PR30076","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230321142857.672520-1-szabolcs.nagy@arm.com/mbox/"},{"id":73096,"url":"https://patchwork.plctlab.org/api/1.2/patches/73096/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZBoyS2GDkUCU6oU6@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-21T22:40:11","name":"gas: expand_irp memory leaks","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZBoyS2GDkUCU6oU6@squeak.grove.modra.org/mbox/"},{"id":73098,"url":"https://patchwork.plctlab.org/api/1.2/patches/73098/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZBoyeGHPA+1YemsH@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-21T22:40:56","name":"XCOFF: use bfd_coff_close_and_cleanup","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZBoyeGHPA+1YemsH@squeak.grove.modra.org/mbox/"},{"id":73100,"url":"https://patchwork.plctlab.org/api/1.2/patches/73100/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZBoyosqQBtXm4rI0@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-21T22:41:38","name":"PE fake section for C_SECTION syms","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZBoyosqQBtXm4rI0@squeak.grove.modra.org/mbox/"},{"id":73101,"url":"https://patchwork.plctlab.org/api/1.2/patches/73101/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZBoz7Wa4EHV+q9Gd@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-21T22:47:09","name":"PR17910 sym string offset check","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZBoz7Wa4EHV+q9Gd@squeak.grove.modra.org/mbox/"},{"id":73102,"url":"https://patchwork.plctlab.org/api/1.2/patches/73102/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZBo0ISexQkdavEpk@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-21T22:48:01","name":"Sanity check coff-sh and coff-mcore sym string offset","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZBo0ISexQkdavEpk@squeak.grove.modra.org/mbox/"},{"id":73105,"url":"https://patchwork.plctlab.org/api/1.2/patches/73105/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZBo5fIjQft2+fwJW@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-21T23:10:52","name":"Remove unnecessary memsets in sframe-dump.c","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZBo5fIjQft2+fwJW@squeak.grove.modra.org/mbox/"},{"id":73115,"url":"https://patchwork.plctlab.org/api/1.2/patches/73115/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZBpIM3lRdkoNAN+5@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-22T00:13:39","name":"coff_get_normalized_symtab bfd_release","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZBpIM3lRdkoNAN+5@squeak.grove.modra.org/mbox/"},{"id":73996,"url":"https://patchwork.plctlab.org/api/1.2/patches/73996/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230323105959.1449936-1-yunqiang.su@cipunited.com/","msgid":"<20230323105959.1449936-1-yunqiang.su@cipunited.com>","list_archive_url":null,"date":"2023-03-23T10:59:59","name":"MIPS: fix loongson3 llsc workaround","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230323105959.1449936-1-yunqiang.su@cipunited.com/mbox/"},{"id":74094,"url":"https://patchwork.plctlab.org/api/1.2/patches/74094/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/dc0f734f-9fba-7a7b-a746-49b4fc033dac@suse.com/","msgid":"","list_archive_url":null,"date":"2023-03-23T14:30:15","name":"Arm64/ELF: accept relocations against STN_UNDEF","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/dc0f734f-9fba-7a7b-a746-49b4fc033dac@suse.com/mbox/"},{"id":74480,"url":"https://patchwork.plctlab.org/api/1.2/patches/74480/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZB18Z0o3MG+6xpxp@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-24T10:33:11","name":"Tidy dwarf1 cached section contents","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZB18Z0o3MG+6xpxp@squeak.grove.modra.org/mbox/"},{"id":74481,"url":"https://patchwork.plctlab.org/api/1.2/patches/74481/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZB187ZhUAam/KJLp@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-24T10:35:25","name":"Tidy string_ptr increment","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZB187ZhUAam/KJLp@squeak.grove.modra.org/mbox/"},{"id":74544,"url":"https://patchwork.plctlab.org/api/1.2/patches/74544/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230324133625.450723-1-nick.alcock@oracle.com/","msgid":"<20230324133625.450723-1-nick.alcock@oracle.com>","list_archive_url":null,"date":"2023-03-24T13:36:22","name":"[1/4] libctf: fix assertion failure with no system qsort_r","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230324133625.450723-1-nick.alcock@oracle.com/mbox/"},{"id":74545,"url":"https://patchwork.plctlab.org/api/1.2/patches/74545/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230324133625.450723-2-nick.alcock@oracle.com/","msgid":"<20230324133625.450723-2-nick.alcock@oracle.com>","list_archive_url":null,"date":"2023-03-24T13:36:23","name":"[2/4] libctf: work around an uninitialized variable warning","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230324133625.450723-2-nick.alcock@oracle.com/mbox/"},{"id":74547,"url":"https://patchwork.plctlab.org/api/1.2/patches/74547/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230324133625.450723-3-nick.alcock@oracle.com/","msgid":"<20230324133625.450723-3-nick.alcock@oracle.com>","list_archive_url":null,"date":"2023-03-24T13:36:24","name":"[3/4] libctf: fix a comment typo","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230324133625.450723-3-nick.alcock@oracle.com/mbox/"},{"id":74546,"url":"https://patchwork.plctlab.org/api/1.2/patches/74546/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230324133625.450723-4-nick.alcock@oracle.com/","msgid":"<20230324133625.450723-4-nick.alcock@oracle.com>","list_archive_url":null,"date":"2023-03-24T13:36:25","name":"[4/4] libctf: get the offsets of fields of unnamed structs/unions right","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230324133625.450723-4-nick.alcock@oracle.com/mbox/"},{"id":74560,"url":"https://patchwork.plctlab.org/api/1.2/patches/74560/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ba77df02-5583-fb1d-5e1c-812106c2749f@redhat.com/","msgid":"","list_archive_url":null,"date":"2023-03-24T14:02:55","name":"[Bug,gold/30187] ld.bfd and ld.gold versions in .comment section of ELF files","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ba77df02-5583-fb1d-5e1c-812106c2749f@redhat.com/mbox/"},{"id":74795,"url":"https://patchwork.plctlab.org/api/1.2/patches/74795/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230325004113.22673-1-nelson@rivosinc.com/","msgid":"<20230325004113.22673-1-nelson@rivosinc.com>","list_archive_url":null,"date":"2023-03-25T00:41:11","name":"[1/3] RISC-V: Extract the ld code which are too complicated, and may be reused.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230325004113.22673-1-nelson@rivosinc.com/mbox/"},{"id":74798,"url":"https://patchwork.plctlab.org/api/1.2/patches/74798/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230325004113.22673-2-nelson@rivosinc.com/","msgid":"<20230325004113.22673-2-nelson@rivosinc.com>","list_archive_url":null,"date":"2023-03-25T00:41:12","name":"[2/3] RISC-V: Clarify link behaviors of R_RISCV_32/64 relocations with ABS symbol.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230325004113.22673-2-nelson@rivosinc.com/mbox/"},{"id":74796,"url":"https://patchwork.plctlab.org/api/1.2/patches/74796/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230325004113.22673-3-nelson@rivosinc.com/","msgid":"<20230325004113.22673-3-nelson@rivosinc.com>","list_archive_url":null,"date":"2023-03-25T00:41:13","name":"[3/3] RISC-V: PR28789, Reject R_RISCV_PCREL relocations with ABS symbol in PIC/PIE.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230325004113.22673-3-nelson@rivosinc.com/mbox/"},{"id":75166,"url":"https://patchwork.plctlab.org/api/1.2/patches/75166/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230326231111.3207581-1-vladimir.mezentsev@oracle.com/","msgid":"<20230326231111.3207581-1-vladimir.mezentsev@oracle.com>","list_archive_url":null,"date":"2023-03-26T23:11:11","name":"[Review,is,neded] gprofng: 30089 [display text] Invalid number of threads","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230326231111.3207581-1-vladimir.mezentsev@oracle.com/mbox/"},{"id":75242,"url":"https://patchwork.plctlab.org/api/1.2/patches/75242/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230327080107.3266866-2-christoph.muellner@vrull.eu/","msgid":"<20230327080107.3266866-2-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2023-03-27T08:01:06","name":"[RFC,v2,1/2] RISC-V: Allocate \"various\" operand type","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230327080107.3266866-2-christoph.muellner@vrull.eu/mbox/"},{"id":75245,"url":"https://patchwork.plctlab.org/api/1.2/patches/75245/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230327080107.3266866-3-christoph.muellner@vrull.eu/","msgid":"<20230327080107.3266866-3-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2023-03-27T08:01:07","name":"[RFC,v2,2/2] RISC-V: Add support for the Zfa extension","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230327080107.3266866-3-christoph.muellner@vrull.eu/mbox/"},{"id":75347,"url":"https://patchwork.plctlab.org/api/1.2/patches/75347/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZCF80Rw5CxmJnTxO@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-27T11:24:01","name":"XCOFF sanity check","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZCF80Rw5CxmJnTxO@squeak.grove.modra.org/mbox/"},{"id":75348,"url":"https://patchwork.plctlab.org/api/1.2/patches/75348/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZCF9NGTTWGGN5wkG@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-27T11:25:40","name":"Duplicate DW_AT_call_file leak","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZCF9NGTTWGGN5wkG@squeak.grove.modra.org/mbox/"},{"id":75350,"url":"https://patchwork.plctlab.org/api/1.2/patches/75350/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZCF9rPmAN9m9hcUD@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-27T11:27:40","name":"coffgrok access of u.auxent.x_sym.x_tagndx.p","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZCF9rPmAN9m9hcUD@squeak.grove.modra.org/mbox/"},{"id":75351,"url":"https://patchwork.plctlab.org/api/1.2/patches/75351/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZCF90abJaTld4Nn0@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-27T11:28:17","name":"Set proper union selector tag","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZCF90abJaTld4Nn0@squeak.grove.modra.org/mbox/"},{"id":75353,"url":"https://patchwork.plctlab.org/api/1.2/patches/75353/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZCF+rw8MIhhkeETH@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-27T11:31:59","name":"Use stdint types in coff internal_auxent","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZCF+rw8MIhhkeETH@squeak.grove.modra.org/mbox/"},{"id":75354,"url":"https://patchwork.plctlab.org/api/1.2/patches/75354/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZCF+2jvDqqXV1fVf@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-27T11:32:42","name":"Remove coff_pointerize_aux table_end param","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZCF+2jvDqqXV1fVf@squeak.grove.modra.org/mbox/"},{"id":75355,"url":"https://patchwork.plctlab.org/api/1.2/patches/75355/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZCF/CDC7SaaO4WhF@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-27T11:33:28","name":"Tidy tc-ppc.c XCOFF auxent access","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZCF/CDC7SaaO4WhF@squeak.grove.modra.org/mbox/"},{"id":75768,"url":"https://patchwork.plctlab.org/api/1.2/patches/75768/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZCJMUDd146mhNogB@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-28T02:09:20","name":"ubsan: elfnn-aarch64.c:4595:19: runtime error: load of value 190","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZCJMUDd146mhNogB@squeak.grove.modra.org/mbox/"},{"id":75974,"url":"https://patchwork.plctlab.org/api/1.2/patches/75974/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZCLDZsdo518WMpRM@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-28T10:37:26","name":"Avoid undefined behaviour in m68hc11 md_begin","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZCLDZsdo518WMpRM@squeak.grove.modra.org/mbox/"},{"id":76299,"url":"https://patchwork.plctlab.org/api/1.2/patches/76299/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230328230249.274759-2-david@davidgf.es/","msgid":"<20230328230249.274759-2-david@davidgf.es>","list_archive_url":null,"date":"2023-03-28T23:02:47","name":"[1/3] Add Allegrex CPU as a MIPS2-based CPU","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230328230249.274759-2-david@davidgf.es/mbox/"},{"id":76298,"url":"https://patchwork.plctlab.org/api/1.2/patches/76298/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230328230249.274759-3-david@davidgf.es/","msgid":"<20230328230249.274759-3-david@davidgf.es>","list_archive_url":null,"date":"2023-03-28T23:02:48","name":"[2/3] Add rotation instructions to allegrex CPU","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230328230249.274759-3-david@davidgf.es/mbox/"},{"id":76300,"url":"https://patchwork.plctlab.org/api/1.2/patches/76300/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230328230249.274759-4-david@davidgf.es/","msgid":"<20230328230249.274759-4-david@davidgf.es>","list_archive_url":null,"date":"2023-03-28T23:02:49","name":"[3/3] Adding more instructions to Allegrex CPU","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230328230249.274759-4-david@davidgf.es/mbox/"},{"id":76303,"url":"https://patchwork.plctlab.org/api/1.2/patches/76303/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZCN2J6V/OvvDMa3L@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-28T23:20:07","name":"ld testsuite CFLAGS_FOR_TARGET","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZCN2J6V/OvvDMa3L@squeak.grove.modra.org/mbox/"},{"id":76347,"url":"https://patchwork.plctlab.org/api/1.2/patches/76347/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZCOnk+1MgYLzyM65@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-29T02:50:59","name":"Sanity check section size in bfd_init_section_compress_status","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZCOnk+1MgYLzyM65@squeak.grove.modra.org/mbox/"},{"id":76561,"url":"https://patchwork.plctlab.org/api/1.2/patches/76561/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2a19f48f-2230-70c2-a6eb-de224028e8ae@embedded-brains.de/","msgid":"<2a19f48f-2230-70c2-a6eb-de224028e8ae@embedded-brains.de>","list_archive_url":null,"date":"2023-03-29T12:44:50","name":"RFC: Add ELF note for description with JSON data","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2a19f48f-2230-70c2-a6eb-de224028e8ae@embedded-brains.de/mbox/"},{"id":76636,"url":"https://patchwork.plctlab.org/api/1.2/patches/76636/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/87v8ijmxjh.fsf@redhat.com/","msgid":"<87v8ijmxjh.fsf@redhat.com>","list_archive_url":null,"date":"2023-03-29T14:39:46","name":"RFC: Can static executables contain relocations against symbols ?","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/87v8ijmxjh.fsf@redhat.com/mbox/"},{"id":76860,"url":"https://patchwork.plctlab.org/api/1.2/patches/76860/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/CAB=4xhrACo0JzK-VrnJfYoPxZOiwOYA48-OkShYOz26JPQ9YCA@mail.gmail.com/","msgid":"","list_archive_url":null,"date":"2023-03-30T00:08:03","name":"[COMMITTED] Fix typo in ld manual --enable-non-contiguous-regions example","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/CAB=4xhrACo0JzK-VrnJfYoPxZOiwOYA48-OkShYOz26JPQ9YCA@mail.gmail.com/mbox/"},{"id":76881,"url":"https://patchwork.plctlab.org/api/1.2/patches/76881/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZCUUuatLLu5VmpJx@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-30T04:48:57","name":"Tidy memory on addr2line failures","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZCUUuatLLu5VmpJx@squeak.grove.modra.org/mbox/"},{"id":76882,"url":"https://patchwork.plctlab.org/api/1.2/patches/76882/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZCUU2U5h4L4pOyCY@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-30T04:49:29","name":"Tidy leaked objcopy memory","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZCUU2U5h4L4pOyCY@squeak.grove.modra.org/mbox/"},{"id":76887,"url":"https://patchwork.plctlab.org/api/1.2/patches/76887/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZCUVAjKL5j0X5DTH@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-03-30T04:50:10","name":"Fix memory leak in bfd_get_debug_link_info_1","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZCUVAjKL5j0X5DTH@squeak.grove.modra.org/mbox/"},{"id":77007,"url":"https://patchwork.plctlab.org/api/1.2/patches/77007/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330101245.3327499-1-richard.sandiford@arm.com/","msgid":"<20230330101245.3327499-1-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:12:45","name":"aarch64: Add sme-i16i64 and sme-f64f64 aliases","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330101245.3327499-1-richard.sandiford@arm.com/mbox/"},{"id":77019,"url":"https://patchwork.plctlab.org/api/1.2/patches/77019/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-2-richard.sandiford@arm.com/","msgid":"<20230330102359.3327695-2-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:23:17","name":"[01/43] aarch64: Fix PSEL opcode mask","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-2-richard.sandiford@arm.com/mbox/"},{"id":77024,"url":"https://patchwork.plctlab.org/api/1.2/patches/77024/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-3-richard.sandiford@arm.com/","msgid":"<20230330102359.3327695-3-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:23:18","name":"[02/43] aarch64: Restrict range of PRFM opcodes","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-3-richard.sandiford@arm.com/mbox/"},{"id":77016,"url":"https://patchwork.plctlab.org/api/1.2/patches/77016/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-4-richard.sandiford@arm.com/","msgid":"<20230330102359.3327695-4-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:23:19","name":"[03/43] aarch64: Fix SVE2 register/immediate distinction","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-4-richard.sandiford@arm.com/mbox/"},{"id":77017,"url":"https://patchwork.plctlab.org/api/1.2/patches/77017/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-5-richard.sandiford@arm.com/","msgid":"<20230330102359.3327695-5-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:23:20","name":"[04/43] aarch64: Make SME instructions use F_STRICT","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-5-richard.sandiford@arm.com/mbox/"},{"id":77031,"url":"https://patchwork.plctlab.org/api/1.2/patches/77031/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-6-richard.sandiford@arm.com/","msgid":"<20230330102359.3327695-6-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:23:21","name":"[05/43] aarch64: Use aarch64_operand_error more widely","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-6-richard.sandiford@arm.com/mbox/"},{"id":77021,"url":"https://patchwork.plctlab.org/api/1.2/patches/77021/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-7-richard.sandiford@arm.com/","msgid":"<20230330102359.3327695-7-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:23:22","name":"[06/43] aarch64: Rename REG_TYPE_ZA* to REG_TYPE_ZAT*","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-7-richard.sandiford@arm.com/mbox/"},{"id":77018,"url":"https://patchwork.plctlab.org/api/1.2/patches/77018/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-8-richard.sandiford@arm.com/","msgid":"<20230330102359.3327695-8-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:23:23","name":"[07/43] aarch64: Add REG_TYPE_ZATHV","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-8-richard.sandiford@arm.com/mbox/"},{"id":77020,"url":"https://patchwork.plctlab.org/api/1.2/patches/77020/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-9-richard.sandiford@arm.com/","msgid":"<20230330102359.3327695-9-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:23:24","name":"[08/43] aarch64: Move vectype_to_qualifier further up","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-9-richard.sandiford@arm.com/mbox/"},{"id":77022,"url":"https://patchwork.plctlab.org/api/1.2/patches/77022/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-10-richard.sandiford@arm.com/","msgid":"<20230330102359.3327695-10-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:23:25","name":"[09/43] aarch64: Rework parse_typed_reg interface","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-10-richard.sandiford@arm.com/mbox/"},{"id":77027,"url":"https://patchwork.plctlab.org/api/1.2/patches/77027/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-11-richard.sandiford@arm.com/","msgid":"<20230330102359.3327695-11-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:23:26","name":"[10/43] aarch64: Reuse parse_typed_reg for ZA tiles","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-11-richard.sandiford@arm.com/mbox/"},{"id":77037,"url":"https://patchwork.plctlab.org/api/1.2/patches/77037/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-12-richard.sandiford@arm.com/","msgid":"<20230330102359.3327695-12-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:23:27","name":"[11/43] aarch64: Consolidate ZA tile range checks","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-12-richard.sandiford@arm.com/mbox/"},{"id":77034,"url":"https://patchwork.plctlab.org/api/1.2/patches/77034/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-13-richard.sandiford@arm.com/","msgid":"<20230330102359.3327695-13-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:23:28","name":"[12/43] aarch64: Treat ZA as a register","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-13-richard.sandiford@arm.com/mbox/"},{"id":77029,"url":"https://patchwork.plctlab.org/api/1.2/patches/77029/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-14-richard.sandiford@arm.com/","msgid":"<20230330102359.3327695-14-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:23:29","name":"[13/43] aarch64: Rename za_tile_vector to za_index","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-14-richard.sandiford@arm.com/mbox/"},{"id":77043,"url":"https://patchwork.plctlab.org/api/1.2/patches/77043/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-15-richard.sandiford@arm.com/","msgid":"<20230330102359.3327695-15-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:23:30","name":"[14/43] aarch64: Make indexed_za use 64-bit immediates","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-15-richard.sandiford@arm.com/mbox/"},{"id":77041,"url":"https://patchwork.plctlab.org/api/1.2/patches/77041/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-16-richard.sandiford@arm.com/","msgid":"<20230330102359.3327695-16-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:23:31","name":"[15/43] aarch64: Pass aarch64_indexed_za to parsers","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-16-richard.sandiford@arm.com/mbox/"},{"id":77045,"url":"https://patchwork.plctlab.org/api/1.2/patches/77045/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-17-richard.sandiford@arm.com/","msgid":"<20230330102359.3327695-17-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:23:32","name":"[16/43] aarch64: Move ZA range checks to aarch64-opc.c","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-17-richard.sandiford@arm.com/mbox/"},{"id":77048,"url":"https://patchwork.plctlab.org/api/1.2/patches/77048/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-18-richard.sandiford@arm.com/","msgid":"<20230330102359.3327695-18-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:23:33","name":"[17/43] aarch64: Consolidate ZA slice parsing","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-18-richard.sandiford@arm.com/mbox/"},{"id":77046,"url":"https://patchwork.plctlab.org/api/1.2/patches/77046/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-19-richard.sandiford@arm.com/","msgid":"<20230330102359.3327695-19-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:23:34","name":"[18/43] aarch64: Commonise index parsing","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-19-richard.sandiford@arm.com/mbox/"},{"id":77053,"url":"https://patchwork.plctlab.org/api/1.2/patches/77053/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-20-richard.sandiford@arm.com/","msgid":"<20230330102359.3327695-20-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:23:35","name":"[19/43] aarch64: Move w12-w15 range check to libopcodes","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-20-richard.sandiford@arm.com/mbox/"},{"id":77032,"url":"https://patchwork.plctlab.org/api/1.2/patches/77032/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-21-richard.sandiford@arm.com/","msgid":"<20230330102359.3327695-21-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:23:36","name":"[20/43] aarch64: Tweak error for missing immediate offset","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-21-richard.sandiford@arm.com/mbox/"},{"id":77058,"url":"https://patchwork.plctlab.org/api/1.2/patches/77058/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-22-richard.sandiford@arm.com/","msgid":"<20230330102359.3327695-22-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:23:37","name":"[21/43] aarch64: Tweak errors for base & offset registers","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-22-richard.sandiford@arm.com/mbox/"},{"id":77056,"url":"https://patchwork.plctlab.org/api/1.2/patches/77056/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-23-richard.sandiford@arm.com/","msgid":"<20230330102359.3327695-23-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:23:38","name":"[22/43] aarch64: Tweak parsing of integer & FP registers","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-23-richard.sandiford@arm.com/mbox/"},{"id":77052,"url":"https://patchwork.plctlab.org/api/1.2/patches/77052/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-24-richard.sandiford@arm.com/","msgid":"<20230330102359.3327695-24-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:23:39","name":"[23/43] aarch64: Improve errors for malformed register lists","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-24-richard.sandiford@arm.com/mbox/"},{"id":77064,"url":"https://patchwork.plctlab.org/api/1.2/patches/77064/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-25-richard.sandiford@arm.com/","msgid":"<20230330102359.3327695-25-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:23:40","name":"[24/43] aarch64: Try to avoid inappropriate default errors","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-25-richard.sandiford@arm.com/mbox/"},{"id":77070,"url":"https://patchwork.plctlab.org/api/1.2/patches/77070/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-26-richard.sandiford@arm.com/","msgid":"<20230330102359.3327695-26-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:23:41","name":"[25/43] aarch64: Rework reporting of failed register checks","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-26-richard.sandiford@arm.com/mbox/"},{"id":77050,"url":"https://patchwork.plctlab.org/api/1.2/patches/77050/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-27-richard.sandiford@arm.com/","msgid":"<20230330102359.3327695-27-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:23:42","name":"[26/43] aarch64: Update operand_mismatch_kind_names","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-27-richard.sandiford@arm.com/mbox/"},{"id":77054,"url":"https://patchwork.plctlab.org/api/1.2/patches/77054/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-28-richard.sandiford@arm.com/","msgid":"<20230330102359.3327695-28-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:23:43","name":"[27/43] aarch64: Deprioritise AARCH64_OPDE_REG_LIST","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-28-richard.sandiford@arm.com/mbox/"},{"id":77042,"url":"https://patchwork.plctlab.org/api/1.2/patches/77042/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-29-richard.sandiford@arm.com/","msgid":"<20230330102359.3327695-29-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:23:44","name":"[28/43] aarch64: Add an error code for out-of-range registers","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-29-richard.sandiford@arm.com/mbox/"},{"id":77060,"url":"https://patchwork.plctlab.org/api/1.2/patches/77060/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-30-richard.sandiford@arm.com/","msgid":"<20230330102359.3327695-30-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:23:45","name":"[29/43] aarch64: Commonise checks for index operands","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-30-richard.sandiford@arm.com/mbox/"},{"id":77066,"url":"https://patchwork.plctlab.org/api/1.2/patches/77066/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-31-richard.sandiford@arm.com/","msgid":"<20230330102359.3327695-31-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:23:46","name":"[30/43] aarch64: Add an operand class for SVE register lists","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-31-richard.sandiford@arm.com/mbox/"},{"id":77067,"url":"https://patchwork.plctlab.org/api/1.2/patches/77067/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-32-richard.sandiford@arm.com/","msgid":"<20230330102359.3327695-32-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:23:47","name":"[31/43] aarch64: Make AARCH64_OPDE_REG_LIST take a bitfield","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-32-richard.sandiford@arm.com/mbox/"},{"id":77047,"url":"https://patchwork.plctlab.org/api/1.2/patches/77047/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-33-richard.sandiford@arm.com/","msgid":"<20230330102359.3327695-33-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:23:48","name":"[32/43] aarch64: Tweak register list errors","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-33-richard.sandiford@arm.com/mbox/"},{"id":77072,"url":"https://patchwork.plctlab.org/api/1.2/patches/77072/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-34-richard.sandiford@arm.com/","msgid":"<20230330102359.3327695-34-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:23:49","name":"[33/43] aarch64: Try to report invalid variants against the closest match","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-34-richard.sandiford@arm.com/mbox/"},{"id":77051,"url":"https://patchwork.plctlab.org/api/1.2/patches/77051/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-35-richard.sandiford@arm.com/","msgid":"<20230330102359.3327695-35-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:23:50","name":"[34/43] aarch64: Tweak priorities of parsing-related errors","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-35-richard.sandiford@arm.com/mbox/"},{"id":77079,"url":"https://patchwork.plctlab.org/api/1.2/patches/77079/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-36-richard.sandiford@arm.com/","msgid":"<20230330102359.3327695-36-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:23:51","name":"[35/43] aarch64: Rename aarch64-tbl.h OP_SME_* macros","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-36-richard.sandiford@arm.com/mbox/"},{"id":77055,"url":"https://patchwork.plctlab.org/api/1.2/patches/77055/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-37-richard.sandiford@arm.com/","msgid":"<20230330102359.3327695-37-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:23:52","name":"[36/43] aarch64: Reorder some OP_SVE_* macros","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-37-richard.sandiford@arm.com/mbox/"},{"id":77082,"url":"https://patchwork.plctlab.org/api/1.2/patches/77082/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-38-richard.sandiford@arm.com/","msgid":"<20230330102359.3327695-38-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:23:53","name":"[37/43] aarch64: Add a aarch64_cpu_supports_inst_p helper","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-38-richard.sandiford@arm.com/mbox/"},{"id":77068,"url":"https://patchwork.plctlab.org/api/1.2/patches/77068/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-39-richard.sandiford@arm.com/","msgid":"<20230330102359.3327695-39-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:23:54","name":"[38/43] aarch64: Rename some of GAS'\''s REG_TYPE_* macros","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-39-richard.sandiford@arm.com/mbox/"},{"id":77073,"url":"https://patchwork.plctlab.org/api/1.2/patches/77073/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-40-richard.sandiford@arm.com/","msgid":"<20230330102359.3327695-40-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:23:55","name":"[39/43] aarch64: Regularise FLD_* suffixes","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-40-richard.sandiford@arm.com/mbox/"},{"id":77084,"url":"https://patchwork.plctlab.org/api/1.2/patches/77084/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-41-richard.sandiford@arm.com/","msgid":"<20230330102359.3327695-41-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:23:56","name":"[40/43] aarch64: Resync field names","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-41-richard.sandiford@arm.com/mbox/"},{"id":77077,"url":"https://patchwork.plctlab.org/api/1.2/patches/77077/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-42-richard.sandiford@arm.com/","msgid":"<20230330102359.3327695-42-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:23:57","name":"[41/43] aarch64: Sort fields alphanumerically","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-42-richard.sandiford@arm.com/mbox/"},{"id":77063,"url":"https://patchwork.plctlab.org/api/1.2/patches/77063/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-43-richard.sandiford@arm.com/","msgid":"<20230330102359.3327695-43-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:23:58","name":"[42/43] aarch64: Add support for strided register lists","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-43-richard.sandiford@arm.com/mbox/"},{"id":77078,"url":"https://patchwork.plctlab.org/api/1.2/patches/77078/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-44-richard.sandiford@arm.com/","msgid":"<20230330102359.3327695-44-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:23:59","name":"[43/43] aarch64: Prefer register ranges & support wrapping","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102359.3327695-44-richard.sandiford@arm.com/mbox/"},{"id":77086,"url":"https://patchwork.plctlab.org/api/1.2/patches/77086/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102646.3327818-2-richard.sandiford@arm.com/","msgid":"<20230330102646.3327818-2-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:26:16","name":"[01/31] aarch64: Add +sme2","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102646.3327818-2-richard.sandiford@arm.com/mbox/"},{"id":77090,"url":"https://patchwork.plctlab.org/api/1.2/patches/77090/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102646.3327818-3-richard.sandiford@arm.com/","msgid":"<20230330102646.3327818-3-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:26:17","name":"[02/31] aarch64: Add a _10 suffix to FLD_imm3","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102646.3327818-3-richard.sandiford@arm.com/mbox/"},{"id":77076,"url":"https://patchwork.plctlab.org/api/1.2/patches/77076/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102646.3327818-4-richard.sandiford@arm.com/","msgid":"<20230330102646.3327818-4-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:26:18","name":"[03/31] aarch64: Add _off4 suffix to AARCH64_OPND_SME_ZA_array","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102646.3327818-4-richard.sandiford@arm.com/mbox/"},{"id":77083,"url":"https://patchwork.plctlab.org/api/1.2/patches/77083/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102646.3327818-5-richard.sandiford@arm.com/","msgid":"<20230330102646.3327818-5-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:26:19","name":"[04/31] aarch64: Add support for vgx2 and vgx4","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102646.3327818-5-richard.sandiford@arm.com/mbox/"},{"id":77081,"url":"https://patchwork.plctlab.org/api/1.2/patches/77081/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102646.3327818-6-richard.sandiford@arm.com/","msgid":"<20230330102646.3327818-6-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:26:20","name":"[05/31] aarch64; Add support for vector offset ranges","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102646.3327818-6-richard.sandiford@arm.com/mbox/"},{"id":77085,"url":"https://patchwork.plctlab.org/api/1.2/patches/77085/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102646.3327818-8-richard.sandiford@arm.com/","msgid":"<20230330102646.3327818-8-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:26:22","name":"[07/31] aarch64: Add the SME2 MOVA instructions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102646.3327818-8-richard.sandiford@arm.com/mbox/"},{"id":77071,"url":"https://patchwork.plctlab.org/api/1.2/patches/77071/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102646.3327818-11-richard.sandiford@arm.com/","msgid":"<20230330102646.3327818-11-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:26:25","name":"[10/31] aarch64: Add the SME2 ZT0 instructions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102646.3327818-11-richard.sandiford@arm.com/mbox/"},{"id":77080,"url":"https://patchwork.plctlab.org/api/1.2/patches/77080/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102646.3327818-12-richard.sandiford@arm.com/","msgid":"<20230330102646.3327818-12-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:26:26","name":"[11/31] aarch64: Add the SME2 ADD and SUB instructions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102646.3327818-12-richard.sandiford@arm.com/mbox/"},{"id":77087,"url":"https://patchwork.plctlab.org/api/1.2/patches/77087/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102646.3327818-14-richard.sandiford@arm.com/","msgid":"<20230330102646.3327818-14-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:26:28","name":"[13/31] aarch64: Add the SME2 FMLA and FMLS instructions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102646.3327818-14-richard.sandiford@arm.com/mbox/"},{"id":77093,"url":"https://patchwork.plctlab.org/api/1.2/patches/77093/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102646.3327818-23-richard.sandiford@arm.com/","msgid":"<20230330102646.3327818-23-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:26:37","name":"[22/31] aarch64: Add the SME2 saturating conversion instructions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102646.3327818-23-richard.sandiford@arm.com/mbox/"},{"id":77091,"url":"https://patchwork.plctlab.org/api/1.2/patches/77091/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102646.3327818-24-richard.sandiford@arm.com/","msgid":"<20230330102646.3327818-24-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:26:38","name":"[23/31] aarch64: Add the SME2 shift instructions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102646.3327818-24-richard.sandiford@arm.com/mbox/"},{"id":77095,"url":"https://patchwork.plctlab.org/api/1.2/patches/77095/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102646.3327818-25-richard.sandiford@arm.com/","msgid":"<20230330102646.3327818-25-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:26:39","name":"[24/31] aarch64: Add the SME2 UNPK instructions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102646.3327818-25-richard.sandiford@arm.com/mbox/"},{"id":77092,"url":"https://patchwork.plctlab.org/api/1.2/patches/77092/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102646.3327818-26-richard.sandiford@arm.com/","msgid":"<20230330102646.3327818-26-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:26:40","name":"[25/31] aarch64: Add the SME2 UZP and ZIP instructions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102646.3327818-26-richard.sandiford@arm.com/mbox/"},{"id":77097,"url":"https://patchwork.plctlab.org/api/1.2/patches/77097/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330103528.3497996-2-christoph.muellner@vrull.eu/","msgid":"<20230330103528.3497996-2-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2023-03-30T10:35:27","name":"[RFC,v3,1/2] RISC-V: Allocate \"various\" operand type","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330103528.3497996-2-christoph.muellner@vrull.eu/mbox/"},{"id":77098,"url":"https://patchwork.plctlab.org/api/1.2/patches/77098/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330103528.3497996-3-christoph.muellner@vrull.eu/","msgid":"<20230330103528.3497996-3-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2023-03-30T10:35:28","name":"[RFC,v3,2/2] RISC-V: Add support for the Zfa extension","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330103528.3497996-3-christoph.muellner@vrull.eu/mbox/"},{"id":77244,"url":"https://patchwork.plctlab.org/api/1.2/patches/77244/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/mptsfdmut0x.fsf@arm.com/","msgid":"","list_archive_url":null,"date":"2023-03-30T16:02:22","name":"aarch64: Remove stray reglist variable","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/mptsfdmut0x.fsf@arm.com/mbox/"},{"id":77311,"url":"https://patchwork.plctlab.org/api/1.2/patches/77311/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330164214.735462-1-hjl.tools@gmail.com/","msgid":"<20230330164214.735462-1-hjl.tools@gmail.com>","list_archive_url":null,"date":"2023-03-30T16:42:14","name":"lto: Don'\''t add indirect symbols for versioned aliases in IR","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330164214.735462-1-hjl.tools@gmail.com/mbox/"},{"id":77350,"url":"https://patchwork.plctlab.org/api/1.2/patches/77350/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330175438.107102-2-christoph.muellner@vrull.eu/","msgid":"<20230330175438.107102-2-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2023-03-30T17:54:37","name":"[RFC,v4,1/2] RISC-V: Allocate \"various\" operand type","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330175438.107102-2-christoph.muellner@vrull.eu/mbox/"},{"id":77351,"url":"https://patchwork.plctlab.org/api/1.2/patches/77351/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330175438.107102-3-christoph.muellner@vrull.eu/","msgid":"<20230330175438.107102-3-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2023-03-30T17:54:38","name":"[RFC,v4,2/2] RISC-V: Add support for the Zfa extension","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330175438.107102-3-christoph.muellner@vrull.eu/mbox/"},{"id":77708,"url":"https://patchwork.plctlab.org/api/1.2/patches/77708/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/bcc26bf7-bb9f-6ffc-51e8-05b8ff9e05e1@suse.com/","msgid":"","list_archive_url":null,"date":"2023-03-31T10:04:54","name":"[1/3] x86: parse_real_register() does not alter the parsed string","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/bcc26bf7-bb9f-6ffc-51e8-05b8ff9e05e1@suse.com/mbox/"},{"id":77709,"url":"https://patchwork.plctlab.org/api/1.2/patches/77709/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e0e3ab15-50da-a92a-bcec-e392f09a9c37@suse.com/","msgid":"","list_archive_url":null,"date":"2023-03-31T10:05:53","name":"[2/3] x86: parse_register() must not alter the parsed string","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e0e3ab15-50da-a92a-bcec-e392f09a9c37@suse.com/mbox/"},{"id":77710,"url":"https://patchwork.plctlab.org/api/1.2/patches/77710/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b9ae928e-7e33-e158-bc2e-5e832c2f6032@suse.com/","msgid":"","list_archive_url":null,"date":"2023-03-31T10:07:04","name":"[3/3] gas: document that get_symbol_name() can clobber the input buffer","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b9ae928e-7e33-e158-bc2e-5e832c2f6032@suse.com/mbox/"},{"id":77794,"url":"https://patchwork.plctlab.org/api/1.2/patches/77794/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/efb685d2-b2cb-9baf-0352-d0aa7961c300@suse.com/","msgid":"","list_archive_url":null,"date":"2023-03-31T14:19:21","name":"bfd+ld: when / whether to generate .c files","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/efb685d2-b2cb-9baf-0352-d0aa7961c300@suse.com/mbox/"}],"public":true,"mbox":"https://patchwork.plctlab.org/bundle/patchwork-bot/binutils-gdb_2023-03/mbox/"},{"id":20,"url":"https://patchwork.plctlab.org/api/1.2/bundles/20/","web_url":"https://patchwork.plctlab.org/bundle/patchwork-bot/binutils-gdb_2023-04/","project":{"id":2,"url":"https://patchwork.plctlab.org/api/1.2/projects/2/","name":"binutils-gdb","link_name":"binutils-gdb","list_id":"binutils.sourceware.org","list_email":"binutils@sourceware.org","web_url":"https://github.com/wangliu-iscas/Patchwork-Bundles/blob/main/binutils-gdb.md","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"name":"binutils-gdb_2023-04","owner":{"id":3,"url":"https://patchwork.plctlab.org/api/1.2/users/3/","username":"patchwork-bot","first_name":"","last_name":"","email":"ouuuleilei@gmail.com"},"patches":[{"id":78307,"url":"https://patchwork.plctlab.org/api/1.2/patches/78307/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZCoAJjprIo2dA8lE@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-04-02T22:22:30","name":"Memory leak in process_abbrev_set","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZCoAJjprIo2dA8lE@squeak.grove.modra.org/mbox/"},{"id":78308,"url":"https://patchwork.plctlab.org/api/1.2/patches/78308/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZCoAR84jVZy97VzK@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-04-02T22:23:03","name":"rddbg.c stabs FIXMEs","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZCoAR84jVZy97VzK@squeak.grove.modra.org/mbox/"},{"id":78309,"url":"https://patchwork.plctlab.org/api/1.2/patches/78309/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZCoAZZg7Py/LwyZl@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-04-02T22:23:33","name":"ubsan: aarch64 parse_vector_reg_list","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZCoAZZg7Py/LwyZl@squeak.grove.modra.org/mbox/"},{"id":78310,"url":"https://patchwork.plctlab.org/api/1.2/patches/78310/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZCoAizHXDaTVgiFm@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-04-02T22:24:11","name":"asan: heap buffer overflow printing ecoff debug info file name","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZCoAizHXDaTVgiFm@squeak.grove.modra.org/mbox/"},{"id":78375,"url":"https://patchwork.plctlab.org/api/1.2/patches/78375/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230403071118.2097883-1-haochen.jiang@intel.com/","msgid":"<20230403071118.2097883-1-haochen.jiang@intel.com>","list_archive_url":null,"date":"2023-04-03T07:11:18","name":"Support Intel AMX-COMPLEX","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230403071118.2097883-1-haochen.jiang@intel.com/mbox/"},{"id":78496,"url":"https://patchwork.plctlab.org/api/1.2/patches/78496/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230403110635.23391-1-yunqiang.su@cipunited.com/","msgid":"<20230403110635.23391-1-yunqiang.su@cipunited.com>","list_archive_url":null,"date":"2023-04-03T11:06:35","name":"[v2] MIPS: the default output fellows triple and with-arch","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230403110635.23391-1-yunqiang.su@cipunited.com/mbox/"},{"id":78553,"url":"https://patchwork.plctlab.org/api/1.2/patches/78553/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZCrYJNj8VL4ZsHBV@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-04-03T13:44:04","name":"asan: csky floatformat_to_double uninitialised value","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZCrYJNj8VL4ZsHBV@squeak.grove.modra.org/mbox/"},{"id":78838,"url":"https://patchwork.plctlab.org/api/1.2/patches/78838/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZCueM3aNMfvEirla@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-04-04T03:49:07","name":"Use bfd_alloc memory for read_debugging_info storage","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZCueM3aNMfvEirla@squeak.grove.modra.org/mbox/"},{"id":78868,"url":"https://patchwork.plctlab.org/api/1.2/patches/78868/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9b770800-dc80-2c00-40a2-903cbe4ffb8c@suse.com/","msgid":"<9b770800-dc80-2c00-40a2-903cbe4ffb8c@suse.com>","list_archive_url":null,"date":"2023-04-04T06:58:15","name":"[1/8] x86: move fetch error handling into a helper function","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9b770800-dc80-2c00-40a2-903cbe4ffb8c@suse.com/mbox/"},{"id":78869,"url":"https://patchwork.plctlab.org/api/1.2/patches/78869/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/39b50a10-ad10-aca0-2ef1-4d32be787762@suse.com/","msgid":"<39b50a10-ad10-aca0-2ef1-4d32be787762@suse.com>","list_archive_url":null,"date":"2023-04-04T06:58:37","name":"[2/8] x86: change fetch error handling in top-level function","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/39b50a10-ad10-aca0-2ef1-4d32be787762@suse.com/mbox/"},{"id":78870,"url":"https://patchwork.plctlab.org/api/1.2/patches/78870/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/838292bd-8855-00af-59c8-fcf0acb34d5c@suse.com/","msgid":"<838292bd-8855-00af-59c8-fcf0acb34d5c@suse.com>","list_archive_url":null,"date":"2023-04-04T06:59:17","name":"[3/8] x86: change fetch error handling in ckprefix()","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/838292bd-8855-00af-59c8-fcf0acb34d5c@suse.com/mbox/"},{"id":78871,"url":"https://patchwork.plctlab.org/api/1.2/patches/78871/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b4c84a3d-5266-2395-ba72-97e5ec540b3c@suse.com/","msgid":"","list_archive_url":null,"date":"2023-04-04T06:59:49","name":"[4/8] x86: change fetch error handling in get_valid_dis386()","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b4c84a3d-5266-2395-ba72-97e5ec540b3c@suse.com/mbox/"},{"id":78872,"url":"https://patchwork.plctlab.org/api/1.2/patches/78872/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3231104b-ffc0-e471-79be-f18e14c3264e@suse.com/","msgid":"<3231104b-ffc0-e471-79be-f18e14c3264e@suse.com>","list_archive_url":null,"date":"2023-04-04T07:00:24","name":"[5/8] x86: change fetch error handling when processing operands","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3231104b-ffc0-e471-79be-f18e14c3264e@suse.com/mbox/"},{"id":78873,"url":"https://patchwork.plctlab.org/api/1.2/patches/78873/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a9e13e17-ecf2-8e96-5b48-870801faa750@suse.com/","msgid":"","list_archive_url":null,"date":"2023-04-04T07:00:46","name":"[6/8] x86: change fetch error handling for get()","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a9e13e17-ecf2-8e96-5b48-870801faa750@suse.com/mbox/"},{"id":78874,"url":"https://patchwork.plctlab.org/api/1.2/patches/78874/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9375ae85-ac76-2081-547d-55803c97aadf@suse.com/","msgid":"<9375ae85-ac76-2081-547d-55803c97aadf@suse.com>","list_archive_url":null,"date":"2023-04-04T07:01:04","name":"[7/8] x86: drop use of setjmp() from disassembler","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9375ae85-ac76-2081-547d-55803c97aadf@suse.com/mbox/"},{"id":78875,"url":"https://patchwork.plctlab.org/api/1.2/patches/78875/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4eed4c72-002f-268e-b5cd-0929bc57d6d2@suse.com/","msgid":"<4eed4c72-002f-268e-b5cd-0929bc57d6d2@suse.com>","list_archive_url":null,"date":"2023-04-04T07:01:31","name":"[8/8] x86: drop (explicit) BFD64 dependency from disassembler","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4eed4c72-002f-268e-b5cd-0929bc57d6d2@suse.com/mbox/"},{"id":79194,"url":"https://patchwork.plctlab.org/api/1.2/patches/79194/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/OS3P286MB2152D2B8F88B6EB24B91BD8BF0939@OS3P286MB2152.JPNP286.PROD.OUTLOOK.COM/","msgid":"","list_archive_url":null,"date":"2023-04-04T15:07:13","name":"bfd: add version check to makeinfo","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/OS3P286MB2152D2B8F88B6EB24B91BD8BF0939@OS3P286MB2152.JPNP286.PROD.OUTLOOK.COM/mbox/"},{"id":79999,"url":"https://patchwork.plctlab.org/api/1.2/patches/79999/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZC4RKePLqGKgQ3pO@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-04-06T00:24:09","name":"objcopy write_debugging_info memory leaks","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZC4RKePLqGKgQ3pO@squeak.grove.modra.org/mbox/"},{"id":80000,"url":"https://patchwork.plctlab.org/api/1.2/patches/80000/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZC4RRVFBYw/0n5Le@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-04-06T00:24:37","name":"gas/write.c use better types","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZC4RRVFBYw/0n5Le@squeak.grove.modra.org/mbox/"},{"id":80002,"url":"https://patchwork.plctlab.org/api/1.2/patches/80002/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZC4RdBr7BVn64YcM@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-04-06T00:25:24","name":"objdump -g on gcc COFF/PE files","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZC4RdBr7BVn64YcM@squeak.grove.modra.org/mbox/"},{"id":80003,"url":"https://patchwork.plctlab.org/api/1.2/patches/80003/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZC4RjLt+tU2D/RxY@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-04-06T00:25:48","name":"objdump print_debugging_info memory leaks","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZC4RjLt+tU2D/RxY@squeak.grove.modra.org/mbox/"},{"id":80108,"url":"https://patchwork.plctlab.org/api/1.2/patches/80108/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230406071732.2092853-1-haochen.jiang@intel.com/","msgid":"<20230406071732.2092853-1-haochen.jiang@intel.com>","list_archive_url":null,"date":"2023-04-06T07:17:32","name":"[v2] Support Intel AMX-COMPLEX","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230406071732.2092853-1-haochen.jiang@intel.com/mbox/"},{"id":80642,"url":"https://patchwork.plctlab.org/api/1.2/patches/80642/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230407032809.3763561-1-haochen.jiang@intel.com/","msgid":"<20230407032809.3763561-1-haochen.jiang@intel.com>","list_archive_url":null,"date":"2023-04-07T03:28:09","name":"x86: Add inval tests for AMX instructions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230407032809.3763561-1-haochen.jiang@intel.com/mbox/"},{"id":80675,"url":"https://patchwork.plctlab.org/api/1.2/patches/80675/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230407073501.66953-1-lidie@eswincomputing.com/","msgid":"<20230407073501.66953-1-lidie@eswincomputing.com>","list_archive_url":null,"date":"2023-04-07T07:35:01","name":"Add unclosed macros.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230407073501.66953-1-lidie@eswincomputing.com/mbox/"},{"id":81057,"url":"https://patchwork.plctlab.org/api/1.2/patches/81057/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230407220426.63786-1-nick.alcock@oracle.com/","msgid":"<20230407220426.63786-1-nick.alcock@oracle.com>","list_archive_url":null,"date":"2023-04-07T22:04:24","name":"[1/3] libctf, tests: do not assume host and target have identical field offsets","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230407220426.63786-1-nick.alcock@oracle.com/mbox/"},{"id":81059,"url":"https://patchwork.plctlab.org/api/1.2/patches/81059/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230407220426.63786-2-nick.alcock@oracle.com/","msgid":"<20230407220426.63786-2-nick.alcock@oracle.com>","list_archive_url":null,"date":"2023-04-07T22:04:25","name":"[2/3] libctf: propagate errors from parents correctly","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230407220426.63786-2-nick.alcock@oracle.com/mbox/"},{"id":81058,"url":"https://patchwork.plctlab.org/api/1.2/patches/81058/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230407220426.63786-3-nick.alcock@oracle.com/","msgid":"<20230407220426.63786-3-nick.alcock@oracle.com>","list_archive_url":null,"date":"2023-04-07T22:04:26","name":"[3/3] libctf, link: fix CU-mapped links with CTF_LINK_EMPTY_CU_MAPPINGS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230407220426.63786-3-nick.alcock@oracle.com/mbox/"},{"id":81328,"url":"https://patchwork.plctlab.org/api/1.2/patches/81328/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/745eb337-facd-244a-bd02-d9b8b1f653a5@acm.org/","msgid":"<745eb337-facd-244a-bd02-d9b8b1f653a5@acm.org>","list_archive_url":null,"date":"2023-04-09T22:55:13","name":"bfd: optimize bfd_elf_hash","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/745eb337-facd-244a-bd02-d9b8b1f653a5@acm.org/mbox/"},{"id":81368,"url":"https://patchwork.plctlab.org/api/1.2/patches/81368/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230410065101.822124-1-yunqiang.su@cipunited.com/","msgid":"<20230410065101.822124-1-yunqiang.su@cipunited.com>","list_archive_url":null,"date":"2023-04-10T06:51:01","name":"[v3] MIPS: make mipsisa32 and mipsisa64 link more systematic","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230410065101.822124-1-yunqiang.su@cipunited.com/mbox/"},{"id":82223,"url":"https://patchwork.plctlab.org/api/1.2/patches/82223/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZDYKGcHwDnuaixXL@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-04-12T01:32:09","name":"Comment typo fix","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZDYKGcHwDnuaixXL@squeak.grove.modra.org/mbox/"},{"id":82224,"url":"https://patchwork.plctlab.org/api/1.2/patches/82224/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZDYKPKZ4fcn/AF6v@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-04-12T01:32:44","name":"pe_ILF_object_p and bfd_check_format_matches","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZDYKPKZ4fcn/AF6v@squeak.grove.modra.org/mbox/"},{"id":82225,"url":"https://patchwork.plctlab.org/api/1.2/patches/82225/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZDYKWh5RnEtHftFe@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-04-12T01:33:14","name":"Fail of x86_64 AMX-COMPLEX insns (Intel disassembly)","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZDYKWh5RnEtHftFe@squeak.grove.modra.org/mbox/"},{"id":82226,"url":"https://patchwork.plctlab.org/api/1.2/patches/82226/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZDYKkMb0QCBGC1/F@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-04-12T01:34:08","name":"ubsan: dwarf2.c:2232:7: runtime error: index 16 out of bounds","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZDYKkMb0QCBGC1/F@squeak.grove.modra.org/mbox/"},{"id":82246,"url":"https://patchwork.plctlab.org/api/1.2/patches/82246/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZDY9jn6M1PdoXqNi@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-04-12T05:11:42","name":"PR30326, uninitialised value in objdump compare_relocs","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZDY9jn6M1PdoXqNi@squeak.grove.modra.org/mbox/"},{"id":82545,"url":"https://patchwork.plctlab.org/api/1.2/patches/82545/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230412154444.1741657-1-claziss@gmail.com/","msgid":"<20230412154444.1741657-1-claziss@gmail.com>","list_archive_url":null,"date":"2023-04-12T15:44:44","name":"[committed] arc: remove faulty instructions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230412154444.1741657-1-claziss@gmail.com/mbox/"},{"id":82801,"url":"https://patchwork.plctlab.org/api/1.2/patches/82801/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZDeVznw01giUi/SE@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-04-13T05:40:30","name":"Preserve a few more bfd fields in check_format_matches","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZDeVznw01giUi/SE@squeak.grove.modra.org/mbox/"},{"id":82831,"url":"https://patchwork.plctlab.org/api/1.2/patches/82831/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230413070544.1961068-1-claziss@gmail.com/","msgid":"<20230413070544.1961068-1-claziss@gmail.com>","list_archive_url":null,"date":"2023-04-13T07:05:44","name":"[committed] arc: Update GAS test","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230413070544.1961068-1-claziss@gmail.com/mbox/"},{"id":82839,"url":"https://patchwork.plctlab.org/api/1.2/patches/82839/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230413073144.1973667-1-claziss@gmail.com/","msgid":"<20230413073144.1973667-1-claziss@gmail.com>","list_archive_url":null,"date":"2023-04-13T07:31:44","name":"[committed] arc: Update ARC'\''s CFI tests.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230413073144.1973667-1-claziss@gmail.com/mbox/"},{"id":82843,"url":"https://patchwork.plctlab.org/api/1.2/patches/82843/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230413074914.354662-1-chigot@adacore.com/","msgid":"<20230413074914.354662-1-chigot@adacore.com>","list_archive_url":null,"date":"2023-04-13T07:49:14","name":"ld: build libdep plugin only when shared library support is enabled","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230413074914.354662-1-chigot@adacore.com/mbox/"},{"id":82854,"url":"https://patchwork.plctlab.org/api/1.2/patches/82854/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230413082502.2009382-1-claziss@gmail.com/","msgid":"<20230413082502.2009382-1-claziss@gmail.com>","list_archive_url":null,"date":"2023-04-13T08:25:02","name":"[committed] arc: Update ARC specific linker tests.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230413082502.2009382-1-claziss@gmail.com/mbox/"},{"id":82982,"url":"https://patchwork.plctlab.org/api/1.2/patches/82982/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230413133654.71247-1-christoph.muellner@vrull.eu/","msgid":"<20230413133654.71247-1-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2023-04-13T13:36:54","name":"[RFC,v5] RISC-V: Add support for the Zfa extension","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230413133654.71247-1-christoph.muellner@vrull.eu/mbox/"},{"id":83244,"url":"https://patchwork.plctlab.org/api/1.2/patches/83244/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230414061935.1252692-1-mengqinggang@loongson.cn/","msgid":"<20230414061935.1252692-1-mengqinggang@loongson.cn>","list_archive_url":null,"date":"2023-04-14T06:19:35","name":"Symbols with GOT relocatios do not fix adjustbale","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230414061935.1252692-1-mengqinggang@loongson.cn/mbox/"},{"id":83259,"url":"https://patchwork.plctlab.org/api/1.2/patches/83259/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230414072046.1639896-1-yunqiang.su@cipunited.com/","msgid":"<20230414072046.1639896-1-yunqiang.su@cipunited.com>","list_archive_url":null,"date":"2023-04-14T07:20:46","name":"[v3] MIPS: the default output fellows triple","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230414072046.1639896-1-yunqiang.su@cipunited.com/mbox/"},{"id":83780,"url":"https://patchwork.plctlab.org/api/1.2/patches/83780/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230416005921.3061576-1-vladimir.mezentsev@oracle.com/","msgid":"<20230416005921.3061576-1-vladimir.mezentsev@oracle.com>","list_archive_url":null,"date":"2023-04-16T00:59:21","name":"[Review,is,neded] gprofng: Update documentation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230416005921.3061576-1-vladimir.mezentsev@oracle.com/mbox/"},{"id":83922,"url":"https://patchwork.plctlab.org/api/1.2/patches/83922/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/baf3b8d6-a257-7bc7-5dfa-2a8f578c2c93@netcologne.de/","msgid":"","list_archive_url":null,"date":"2023-04-16T19:47:11","name":"[gas,documentation] Describe handling of opcodes for relaxation a bit better","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/baf3b8d6-a257-7bc7-5dfa-2a8f578c2c93@netcologne.de/mbox/"},{"id":83932,"url":"https://patchwork.plctlab.org/api/1.2/patches/83932/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230416210122.3363899-1-vladimir.mezentsev@oracle.com/","msgid":"<20230416210122.3363899-1-vladimir.mezentsev@oracle.com>","list_archive_url":null,"date":"2023-04-16T21:01:22","name":"[Review,is,neded] gprofng: 30360 Seg. Fault when application uses std::thread","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230416210122.3363899-1-vladimir.mezentsev@oracle.com/mbox/"},{"id":84106,"url":"https://patchwork.plctlab.org/api/1.2/patches/84106/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230417095443.73581-1-nelson@rivosinc.com/","msgid":"<20230417095443.73581-1-nelson@rivosinc.com>","list_archive_url":null,"date":"2023-04-17T09:54:43","name":"RISC-V: Optimize relaxation of gp with max_alignment.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230417095443.73581-1-nelson@rivosinc.com/mbox/"},{"id":84192,"url":"https://patchwork.plctlab.org/api/1.2/patches/84192/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230417121633.68761-1-kito.cheng@sifive.com/","msgid":"<20230417121633.68761-1-kito.cheng@sifive.com>","list_archive_url":null,"date":"2023-04-17T12:16:33","name":"RISC-V: Cache the latest mapping symbol and its boundary.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230417121633.68761-1-kito.cheng@sifive.com/mbox/"},{"id":84514,"url":"https://patchwork.plctlab.org/api/1.2/patches/84514/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZD3xccVokEyi/Cbv@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-04-18T01:25:05","name":"objdump buffer overflow in fetch_indexed_string","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZD3xccVokEyi/Cbv@squeak.grove.modra.org/mbox/"},{"id":84515,"url":"https://patchwork.plctlab.org/api/1.2/patches/84515/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZD3xnwW1LKQe7Oqe@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-04-18T01:25:51","name":"objdump use of uninitialised value in pr_string_field","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZD3xnwW1LKQe7Oqe@squeak.grove.modra.org/mbox/"},{"id":84879,"url":"https://patchwork.plctlab.org/api/1.2/patches/84879/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230418140019.2195551-1-yunqiang.su@cipunited.com/","msgid":"<20230418140019.2195551-1-yunqiang.su@cipunited.com>","list_archive_url":null,"date":"2023-04-18T14:00:18","name":"[v4,1/2] MIPS: support mips*64 as CPU and gnuabi64 as ABI","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230418140019.2195551-1-yunqiang.su@cipunited.com/mbox/"},{"id":84880,"url":"https://patchwork.plctlab.org/api/1.2/patches/84880/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230418140019.2195551-2-yunqiang.su@cipunited.com/","msgid":"<20230418140019.2195551-2-yunqiang.su@cipunited.com>","list_archive_url":null,"date":"2023-04-18T14:00:19","name":"[v4,2/2] MIPS: default output r6 obj if the triple is r6","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230418140019.2195551-2-yunqiang.su@cipunited.com/mbox/"},{"id":84915,"url":"https://patchwork.plctlab.org/api/1.2/patches/84915/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.LSU.2.20.2304181502360.3155@wotan.suse.de/","msgid":"","list_archive_url":null,"date":"2023-04-18T15:12:12","name":"section-select: Fix performance problem (PR30367)","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.LSU.2.20.2304181502360.3155@wotan.suse.de/mbox/"},{"id":85574,"url":"https://patchwork.plctlab.org/api/1.2/patches/85574/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230419221125.502883-2-indu.bhagat@oracle.com/","msgid":"<20230419221125.502883-2-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-04-19T22:11:20","name":"[COMMITTED,1/6] gas: sframe: use ATTRIBUTE_UNUSED consistently","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230419221125.502883-2-indu.bhagat@oracle.com/mbox/"},{"id":85578,"url":"https://patchwork.plctlab.org/api/1.2/patches/85578/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230419221125.502883-3-indu.bhagat@oracle.com/","msgid":"<20230419221125.502883-3-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-04-19T22:11:21","name":"[COMMITTED,2/6] gas: sframe: fix comment","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230419221125.502883-3-indu.bhagat@oracle.com/mbox/"},{"id":85575,"url":"https://patchwork.plctlab.org/api/1.2/patches/85575/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230419221125.502883-4-indu.bhagat@oracle.com/","msgid":"<20230419221125.502883-4-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-04-19T22:11:22","name":"[COMMITTED,3/6] libsframe: use return type of bool for predicate functions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230419221125.502883-4-indu.bhagat@oracle.com/mbox/"},{"id":85577,"url":"https://patchwork.plctlab.org/api/1.2/patches/85577/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230419221125.502883-5-indu.bhagat@oracle.com/","msgid":"<20230419221125.502883-5-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-04-19T22:11:23","name":"[COMMITTED,4/6] sframe: correct some typos","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230419221125.502883-5-indu.bhagat@oracle.com/mbox/"},{"id":85576,"url":"https://patchwork.plctlab.org/api/1.2/patches/85576/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230419221125.502883-6-indu.bhagat@oracle.com/","msgid":"<20230419221125.502883-6-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-04-19T22:11:24","name":"[COMMITTED,5/6] libsframe: use consistent function argument names","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230419221125.502883-6-indu.bhagat@oracle.com/mbox/"},{"id":85579,"url":"https://patchwork.plctlab.org/api/1.2/patches/85579/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230419221125.502883-7-indu.bhagat@oracle.com/","msgid":"<20230419221125.502883-7-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-04-19T22:11:25","name":"[COMMITTED,6/6] libsframe: minor formatting fixes in sframe_encoder_write_fre","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230419221125.502883-7-indu.bhagat@oracle.com/mbox/"},{"id":85638,"url":"https://patchwork.plctlab.org/api/1.2/patches/85638/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZEBzqwgJEiqZ3AaD@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-04-19T23:05:15","name":"buffer overflow in print_symname","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZEBzqwgJEiqZ3AaD@squeak.grove.modra.org/mbox/"},{"id":85639,"url":"https://patchwork.plctlab.org/api/1.2/patches/85639/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZEB0Nkp//9ZWvzA4@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-04-19T23:07:34","name":"Yet another out-of-memory fuzzed object","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZEB0Nkp//9ZWvzA4@squeak.grove.modra.org/mbox/"},{"id":85640,"url":"https://patchwork.plctlab.org/api/1.2/patches/85640/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZEB0XGn82KUoFAth@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-04-19T23:08:12","name":"ubsan: signed integer overflow in display_debug_lines_raw","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZEB0XGn82KUoFAth@squeak.grove.modra.org/mbox/"},{"id":85641,"url":"https://patchwork.plctlab.org/api/1.2/patches/85641/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZEB0yrc7sb7PgfVj@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-04-19T23:10:02","name":"PR30343 infrastructure","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZEB0yrc7sb7PgfVj@squeak.grove.modra.org/mbox/"},{"id":85642,"url":"https://patchwork.plctlab.org/api/1.2/patches/85642/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZEB1FHCdkVcnkby8@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-04-19T23:11:16","name":"sh4-linux segfaults running ld testsuite","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZEB1FHCdkVcnkby8@squeak.grove.modra.org/mbox/"},{"id":85912,"url":"https://patchwork.plctlab.org/api/1.2/patches/85912/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230420133102.2422583-1-yunqiang.su@cipunited.com/","msgid":"<20230420133102.2422583-1-yunqiang.su@cipunited.com>","list_archive_url":null,"date":"2023-04-20T13:31:01","name":"[v5,1/2] MIPS: support mips*64 as CPU and gnuabi64 as ABI","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230420133102.2422583-1-yunqiang.su@cipunited.com/mbox/"},{"id":85913,"url":"https://patchwork.plctlab.org/api/1.2/patches/85913/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230420133102.2422583-2-yunqiang.su@cipunited.com/","msgid":"<20230420133102.2422583-2-yunqiang.su@cipunited.com>","list_archive_url":null,"date":"2023-04-20T13:31:02","name":"[v5,2/2] MIPS: default output r6 obj if the triple is r6","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230420133102.2422583-2-yunqiang.su@cipunited.com/mbox/"},{"id":86103,"url":"https://patchwork.plctlab.org/api/1.2/patches/86103/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZEH3P5K8BQ4euUsQ@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-04-21T02:38:55","name":"Delete struct artdata archive_head","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZEH3P5K8BQ4euUsQ@squeak.grove.modra.org/mbox/"},{"id":86104,"url":"https://patchwork.plctlab.org/api/1.2/patches/86104/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZEH5tX5D6VSOFPit@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-04-21T02:49:25","name":"Keeping track of rs6000-coff archive element pointers","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZEH5tX5D6VSOFPit@squeak.grove.modra.org/mbox/"},{"id":86139,"url":"https://patchwork.plctlab.org/api/1.2/patches/86139/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/72cd2df6-f7dd-9217-aa03-e218631c879e@suse.com/","msgid":"<72cd2df6-f7dd-9217-aa03-e218631c879e@suse.com>","list_archive_url":null,"date":"2023-04-21T05:53:28","name":"ld: add missing period after @xref","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/72cd2df6-f7dd-9217-aa03-e218631c879e@suse.com/mbox/"},{"id":86171,"url":"https://patchwork.plctlab.org/api/1.2/patches/86171/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230421082839.41542-1-nelson@rivosinc.com/","msgid":"<20230421082839.41542-1-nelson@rivosinc.com>","list_archive_url":null,"date":"2023-04-21T08:28:38","name":"[1/2] RISC-V: Relax R_RISCV_[PCREL_]LO12_I/S to R_RISCV_GPREL_I/S for undefined weak.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230421082839.41542-1-nelson@rivosinc.com/mbox/"},{"id":86170,"url":"https://patchwork.plctlab.org/api/1.2/patches/86170/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230421082839.41542-2-nelson@rivosinc.com/","msgid":"<20230421082839.41542-2-nelson@rivosinc.com>","list_archive_url":null,"date":"2023-04-21T08:28:39","name":"[2/2] RISC-V: Enable x0 base relaxation for relax_pc even if --no-relax-gp.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230421082839.41542-2-nelson@rivosinc.com/mbox/"},{"id":86203,"url":"https://patchwork.plctlab.org/api/1.2/patches/86203/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230421094346.3017667-1-mengqinggang@loongson.cn/","msgid":"<20230421094346.3017667-1-mengqinggang@loongson.cn>","list_archive_url":null,"date":"2023-04-21T09:43:46","name":"LoongArch: Fix loongarch32 test fails","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230421094346.3017667-1-mengqinggang@loongson.cn/mbox/"},{"id":86214,"url":"https://patchwork.plctlab.org/api/1.2/patches/86214/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f339bf78-9ba2-594b-3dec-232edb0e7f70@suse.com/","msgid":"","list_archive_url":null,"date":"2023-04-21T10:05:16","name":"bfd: fix STRICT_PE_FORMAT build","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f339bf78-9ba2-594b-3dec-232edb0e7f70@suse.com/mbox/"},{"id":86221,"url":"https://patchwork.plctlab.org/api/1.2/patches/86221/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0ece83ad-f7a0-7951-374b-2c86cbafad36@suse.com/","msgid":"<0ece83ad-f7a0-7951-374b-2c86cbafad36@suse.com>","list_archive_url":null,"date":"2023-04-21T10:16:23","name":"[1/2] x86: rework AMX multiplication insn disassembly","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0ece83ad-f7a0-7951-374b-2c86cbafad36@suse.com/mbox/"},{"id":86222,"url":"https://patchwork.plctlab.org/api/1.2/patches/86222/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/657c81bd-2182-c663-04a4-c5e6962531ea@suse.com/","msgid":"<657c81bd-2182-c663-04a4-c5e6962531ea@suse.com>","list_archive_url":null,"date":"2023-04-21T10:16:59","name":"[2/2] x86: rework AMX control insn disassembly","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/657c81bd-2182-c663-04a4-c5e6962531ea@suse.com/mbox/"},{"id":86240,"url":"https://patchwork.plctlab.org/api/1.2/patches/86240/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/335d1933-a5dc-9183-cbe7-d8b139e232fc@suse.com/","msgid":"<335d1933-a5dc-9183-cbe7-d8b139e232fc@suse.com>","list_archive_url":null,"date":"2023-04-21T10:26:15","name":"gas: move shift count check","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/335d1933-a5dc-9183-cbe7-d8b139e232fc@suse.com/mbox/"},{"id":86274,"url":"https://patchwork.plctlab.org/api/1.2/patches/86274/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4c40b0d1-8375-9284-cfaf-ce63b8df1b9b@suse.com/","msgid":"<4c40b0d1-8375-9284-cfaf-ce63b8df1b9b@suse.com>","list_archive_url":null,"date":"2023-04-21T12:17:54","name":"gas: equates of registers","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4c40b0d1-8375-9284-cfaf-ce63b8df1b9b@suse.com/mbox/"},{"id":86301,"url":"https://patchwork.plctlab.org/api/1.2/patches/86301/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230421130802.2964785-1-tromey@adacore.com/","msgid":"<20230421130802.2964785-1-tromey@adacore.com>","list_archive_url":null,"date":"2023-04-21T13:08:02","name":"Fix -Wmaybe-uninitialized warning in opcodes/i386-dis.c","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230421130802.2964785-1-tromey@adacore.com/mbox/"},{"id":86651,"url":"https://patchwork.plctlab.org/api/1.2/patches/86651/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230423015546.2664272-1-mengqinggang@loongson.cn/","msgid":"<20230423015546.2664272-1-mengqinggang@loongson.cn>","list_archive_url":null,"date":"2023-04-23T01:55:46","name":"[v1] LoongArch: Fix loongarch32 test fails","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230423015546.2664272-1-mengqinggang@loongson.cn/mbox/"},{"id":86786,"url":"https://patchwork.plctlab.org/api/1.2/patches/86786/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230423173021.582102-1-och95@yandex.ru/","msgid":"<20230423173021.582102-1-och95@yandex.ru>","list_archive_url":null,"date":"2023-04-23T17:30:21","name":"Fix emit-relocs for aarch64 gold","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230423173021.582102-1-och95@yandex.ru/mbox/"},{"id":86885,"url":"https://patchwork.plctlab.org/api/1.2/patches/86885/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a475270f-97f0-4fc7-bd0c-eb99bd8b2b3c@suse.com/","msgid":"","list_archive_url":null,"date":"2023-04-24T07:34:27","name":"[1/3] x86: work around compiler diagnosing dangling pointer","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a475270f-97f0-4fc7-bd0c-eb99bd8b2b3c@suse.com/mbox/"},{"id":86886,"url":"https://patchwork.plctlab.org/api/1.2/patches/86886/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c26e2fcd-62aa-98f3-1b62-0c53ce7d16a5@suse.com/","msgid":"","list_archive_url":null,"date":"2023-04-24T07:35:05","name":"[2/3] x86: limit data passed to prefix_name()","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c26e2fcd-62aa-98f3-1b62-0c53ce7d16a5@suse.com/mbox/"},{"id":86887,"url":"https://patchwork.plctlab.org/api/1.2/patches/86887/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b3511736-584c-6c99-9046-331a18c60417@suse.com/","msgid":"","list_archive_url":null,"date":"2023-04-24T07:35:28","name":"[3/3] x86: limit data passed to i386_dis_printf()","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b3511736-584c-6c99-9046-331a18c60417@suse.com/mbox/"},{"id":86999,"url":"https://patchwork.plctlab.org/api/1.2/patches/86999/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZEZoqCKm+ebNL+I7@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-04-24T11:31:52","name":"objcopy of archives tidy","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZEZoqCKm+ebNL+I7@squeak.grove.modra.org/mbox/"},{"id":87000,"url":"https://patchwork.plctlab.org/api/1.2/patches/87000/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZEZo4oH/oT6Gu/5S@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-04-24T11:32:50","name":"asan: segfault in coff_mangle_symbols","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZEZo4oH/oT6Gu/5S@squeak.grove.modra.org/mbox/"},{"id":87259,"url":"https://patchwork.plctlab.org/api/1.2/patches/87259/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230425065626.3587754-1-yunqiang.su@cipunited.com/","msgid":"<20230425065626.3587754-1-yunqiang.su@cipunited.com>","list_archive_url":null,"date":"2023-04-25T06:56:26","name":"MIPS: add MT ASE support for micromips32","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230425065626.3587754-1-yunqiang.su@cipunited.com/mbox/"},{"id":87491,"url":"https://patchwork.plctlab.org/api/1.2/patches/87491/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/CACcXsZjbOetUzc5MOhWFJbqkkhuurqcDD7faHs9PJjM02Be9TA@mail.gmail.com/","msgid":"","list_archive_url":null,"date":"2023-04-25T16:48:11","name":"optimize handle_COMDAT","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/CACcXsZjbOetUzc5MOhWFJbqkkhuurqcDD7faHs9PJjM02Be9TA@mail.gmail.com/mbox/"},{"id":87591,"url":"https://patchwork.plctlab.org/api/1.2/patches/87591/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZEiNgqU+7bX6pfwL@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-04-26T02:33:38","name":"Avoid another -Werror=dangling-pointer","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZEiNgqU+7bX6pfwL@squeak.grove.modra.org/mbox/"},{"id":87592,"url":"https://patchwork.plctlab.org/api/1.2/patches/87592/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZEiN3mQ74ldcG/+R@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-04-26T02:35:10","name":"binutils runtest $CC","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZEiN3mQ74ldcG/+R@squeak.grove.modra.org/mbox/"},{"id":87598,"url":"https://patchwork.plctlab.org/api/1.2/patches/87598/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZEirEhA/zSf9YWhh@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-04-26T04:39:46","name":"i386-dis.c UB shift and other tidies","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZEirEhA/zSf9YWhh@squeak.grove.modra.org/mbox/"},{"id":87791,"url":"https://patchwork.plctlab.org/api/1.2/patches/87791/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230426101640.264902-1-yunqiang.su@cipunited.com/","msgid":"<20230426101640.264902-1-yunqiang.su@cipunited.com>","list_archive_url":null,"date":"2023-04-26T10:16:39","name":"[v2,1/2] MIPS: add MT ASE support for micromips32","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230426101640.264902-1-yunqiang.su@cipunited.com/mbox/"},{"id":87792,"url":"https://patchwork.plctlab.org/api/1.2/patches/87792/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230426101640.264902-2-yunqiang.su@cipunited.com/","msgid":"<20230426101640.264902-2-yunqiang.su@cipunited.com>","list_archive_url":null,"date":"2023-04-26T10:16:40","name":"[v2,2/2] MIPS: sync oprand char usage between mips and micromips","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230426101640.264902-2-yunqiang.su@cipunited.com/mbox/"},{"id":87865,"url":"https://patchwork.plctlab.org/api/1.2/patches/87865/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5aebce50-8b8a-26ee-b452-d9164668c145@suse.com/","msgid":"<5aebce50-8b8a-26ee-b452-d9164668c145@suse.com>","list_archive_url":null,"date":"2023-04-26T13:15:38","name":"x86/Intel: reduce ELF/PE conditional scope in x86_cons()","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5aebce50-8b8a-26ee-b452-d9164668c145@suse.com/mbox/"},{"id":87876,"url":"https://patchwork.plctlab.org/api/1.2/patches/87876/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.LSU.2.20.2304261416140.3155@wotan.suse.de/","msgid":"","list_archive_url":null,"date":"2023-04-26T14:16:55","name":"Fix PR30358, performance with --sort-section","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.LSU.2.20.2304261416140.3155@wotan.suse.de/mbox/"},{"id":87921,"url":"https://patchwork.plctlab.org/api/1.2/patches/87921/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230426173123.24564-1-jose.marchesi@oracle.com/","msgid":"<20230426173123.24564-1-jose.marchesi@oracle.com>","list_archive_url":null,"date":"2023-04-26T17:31:21","name":"[COMMITTED,1/3] gas: support for the BPF pseudo-c assembly syntax","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230426173123.24564-1-jose.marchesi@oracle.com/mbox/"},{"id":87924,"url":"https://patchwork.plctlab.org/api/1.2/patches/87924/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230426173123.24564-2-jose.marchesi@oracle.com/","msgid":"<20230426173123.24564-2-jose.marchesi@oracle.com>","list_archive_url":null,"date":"2023-04-26T17:31:22","name":"[COMMITTED,2/3] gas: BPF pseudo-c syntax tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230426173123.24564-2-jose.marchesi@oracle.com/mbox/"},{"id":87922,"url":"https://patchwork.plctlab.org/api/1.2/patches/87922/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230426173123.24564-3-jose.marchesi@oracle.com/","msgid":"<20230426173123.24564-3-jose.marchesi@oracle.com>","list_archive_url":null,"date":"2023-04-26T17:31:23","name":"[COMMITTED,3/3] gas: documentation for the BPF pseudo-c asm syntax","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230426173123.24564-3-jose.marchesi@oracle.com/mbox/"},{"id":87976,"url":"https://patchwork.plctlab.org/api/1.2/patches/87976/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9b903d19-c4b7-40a3-dce0-84d36e4ff32c@ventanamicro.com/","msgid":"<9b903d19-c4b7-40a3-dce0-84d36e4ff32c@ventanamicro.com>","list_archive_url":null,"date":"2023-04-26T20:28:40","name":"[committed] RISC-V: XVentanaCondops support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9b903d19-c4b7-40a3-dce0-84d36e4ff32c@ventanamicro.com/mbox/"},{"id":88220,"url":"https://patchwork.plctlab.org/api/1.2/patches/88220/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/87354lr0sz.fsf@redhat.com/","msgid":"<87354lr0sz.fsf@redhat.com>","list_archive_url":null,"date":"2023-04-27T12:01:48","name":"Commit: ld: Add ability to print hex values in the linker map","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/87354lr0sz.fsf@redhat.com/mbox/"},{"id":88258,"url":"https://patchwork.plctlab.org/api/1.2/patches/88258/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230427125607.362035-1-iii@linux.ibm.com/","msgid":"<20230427125607.362035-1-iii@linux.ibm.com>","list_archive_url":null,"date":"2023-04-27T12:56:07","name":"gas: fix building tc-bpf.c on s390x","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230427125607.362035-1-iii@linux.ibm.com/mbox/"},{"id":88359,"url":"https://patchwork.plctlab.org/api/1.2/patches/88359/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/CACcXsZjzrLPP5Ngo2bt20hkCQF+uvZ2syNvz5rW-bha_mDTfQw@mail.gmail.com/","msgid":"","list_archive_url":null,"date":"2023-04-27T18:24:48","name":"make coff_compute_checksum faster","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/CACcXsZjzrLPP5Ngo2bt20hkCQF+uvZ2syNvz5rW-bha_mDTfQw@mail.gmail.com/mbox/"},{"id":88408,"url":"https://patchwork.plctlab.org/api/1.2/patches/88408/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/CACcXsZi9c641-gEbCZbP0=Ni+sJKbEwW3gV6CMpT4wOjks85dg@mail.gmail.com/","msgid":"","list_archive_url":null,"date":"2023-04-27T23:35:20","name":"make ar faster","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/CACcXsZi9c641-gEbCZbP0=Ni+sJKbEwW3gV6CMpT4wOjks85dg@mail.gmail.com/mbox/"},{"id":88459,"url":"https://patchwork.plctlab.org/api/1.2/patches/88459/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZEtkW7ozVq5sX1e8@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-04-28T06:14:51","name":"Make bfd_byte an int8_t, flagword a uint32_t","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZEtkW7ozVq5sX1e8@squeak.grove.modra.org/mbox/"},{"id":88460,"url":"https://patchwork.plctlab.org/api/1.2/patches/88460/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZEtkeBiugmBcY34m@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-04-28T06:15:20","name":"Remove deprecated bfd_read","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZEtkeBiugmBcY34m@squeak.grove.modra.org/mbox/"},{"id":88639,"url":"https://patchwork.plctlab.org/api/1.2/patches/88639/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e1da592f-5c5b-418b-a25b-afeeb0691ea7@suse.com/","msgid":"","list_archive_url":null,"date":"2023-04-28T12:57:30","name":"RISC-V: tighten post-relocation-operator separator expectation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e1da592f-5c5b-418b-a25b-afeeb0691ea7@suse.com/mbox/"},{"id":88872,"url":"https://patchwork.plctlab.org/api/1.2/patches/88872/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/CACcXsZjWfeQR3_pC3nVtq+sAkq-QGfEnA3DE2K8rsDnK9edWrQ@mail.gmail.com/","msgid":"","list_archive_url":null,"date":"2023-04-29T11:19:26","name":"add section caches to coff_data_type","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/CACcXsZjWfeQR3_pC3nVtq+sAkq-QGfEnA3DE2K8rsDnK9edWrQ@mail.gmail.com/mbox/"},{"id":88907,"url":"https://patchwork.plctlab.org/api/1.2/patches/88907/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/541a3fba-3b07-d4e3-f913-f10d7163a59e@netcologne.de/","msgid":"<541a3fba-3b07-d4e3-f913-f10d7163a59e@netcologne.de>","list_archive_url":null,"date":"2023-04-30T10:16:23","name":"[gas,documentation] Some additional testsuite info","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/541a3fba-3b07-d4e3-f913-f10d7163a59e@netcologne.de/mbox/"}],"public":true,"mbox":"https://patchwork.plctlab.org/bundle/patchwork-bot/binutils-gdb_2023-04/mbox/"},{"id":22,"url":"https://patchwork.plctlab.org/api/1.2/bundles/22/","web_url":"https://patchwork.plctlab.org/bundle/patchwork-bot/binutils-gdb_2023-05/","project":{"id":2,"url":"https://patchwork.plctlab.org/api/1.2/projects/2/","name":"binutils-gdb","link_name":"binutils-gdb","list_id":"binutils.sourceware.org","list_email":"binutils@sourceware.org","web_url":"https://github.com/wangliu-iscas/Patchwork-Bundles/blob/main/binutils-gdb.md","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"name":"binutils-gdb_2023-05","owner":{"id":3,"url":"https://patchwork.plctlab.org/api/1.2/users/3/","username":"patchwork-bot","first_name":"","last_name":"","email":"ouuuleilei@gmail.com"},"patches":[{"id":89293,"url":"https://patchwork.plctlab.org/api/1.2/patches/89293/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3a7b6bb3-4ab0-15af-0c74-5d7798ac3793@suse.com/","msgid":"<3a7b6bb3-4ab0-15af-0c74-5d7798ac3793@suse.com>","list_archive_url":null,"date":"2023-05-02T09:04:28","name":"[v2] gas: equates of registers","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3a7b6bb3-4ab0-15af-0c74-5d7798ac3793@suse.com/mbox/"},{"id":89429,"url":"https://patchwork.plctlab.org/api/1.2/patches/89429/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3cdc56a8-62eb-d33c-3038-0af00d8a52ba@codesourcery.com/","msgid":"<3cdc56a8-62eb-d33c-3038-0af00d8a52ba@codesourcery.com>","list_archive_url":null,"date":"2023-05-02T17:19:14","name":"[RFC] Linker plugin - extend API for offloading corner case (aka: LDPT_REGISTER_CLAIM_FILE_HOOK_V2 linker plugin hook [GCC PR109128])","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3cdc56a8-62eb-d33c-3038-0af00d8a52ba@codesourcery.com/mbox/"},{"id":89523,"url":"https://patchwork.plctlab.org/api/1.2/patches/89523/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZFGkCFaFJysW0kh1@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-05-03T00:00:08","name":"_bfd_mips_elf_lo16_reloc vallo comment","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZFGkCFaFJysW0kh1@squeak.grove.modra.org/mbox/"},{"id":89569,"url":"https://patchwork.plctlab.org/api/1.2/patches/89569/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZFH4p/bxWZOU/b70@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-05-03T06:01:11","name":"Change signature of bfd crc functions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZFH4p/bxWZOU/b70@squeak.grove.modra.org/mbox/"},{"id":89570,"url":"https://patchwork.plctlab.org/api/1.2/patches/89570/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZFH4xh+ePb7tKT7Q@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-05-03T06:01:42","name":"libbfc.c: Use stdint types for unsigned char and unsigned long","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZFH4xh+ePb7tKT7Q@squeak.grove.modra.org/mbox/"},{"id":89571,"url":"https://patchwork.plctlab.org/api/1.2/patches/89571/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZFH44S/nfshKLrn9@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-05-03T06:02:09","name":"hash.c: replace some unsigned long with unsigned int","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZFH44S/nfshKLrn9@squeak.grove.modra.org/mbox/"},{"id":89572,"url":"https://patchwork.plctlab.org/api/1.2/patches/89572/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZFH5CJb/dZFBG9hD@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-05-03T06:02:48","name":"Move bfd_elf_bfd_from_remote_memory to opncls.c","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZFH5CJb/dZFBG9hD@squeak.grove.modra.org/mbox/"},{"id":89573,"url":"https://patchwork.plctlab.org/api/1.2/patches/89573/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZFH5Jt7SVTKp0rvP@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-05-03T06:03:18","name":"Move bfd_alloc, bfd_zalloc and bfd_release to libbfd.c","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZFH5Jt7SVTKp0rvP@squeak.grove.modra.org/mbox/"},{"id":89574,"url":"https://patchwork.plctlab.org/api/1.2/patches/89574/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZFH5gcFv4YXk03OL@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-05-03T06:04:49","name":"Generated docs and include files","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZFH5gcFv4YXk03OL@squeak.grove.modra.org/mbox/"},{"id":89577,"url":"https://patchwork.plctlab.org/api/1.2/patches/89577/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZFIAiF82oU/87le9@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-05-03T06:34:48","name":"Remove unused args from bfd_make_debug_symbol","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZFIAiF82oU/87le9@squeak.grove.modra.org/mbox/"},{"id":89732,"url":"https://patchwork.plctlab.org/api/1.2/patches/89732/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230503120210.564966-1-iii@linux.ibm.com/","msgid":"<20230503120210.564966-1-iii@linux.ibm.com>","list_archive_url":null,"date":"2023-05-03T12:02:10","name":"[v2] gas: fix building tc-bpf.c on s390x","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230503120210.564966-1-iii@linux.ibm.com/mbox/"},{"id":89794,"url":"https://patchwork.plctlab.org/api/1.2/patches/89794/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230503171124.6710-1-dimitar@dinux.eu/","msgid":"<20230503171124.6710-1-dimitar@dinux.eu>","list_archive_url":null,"date":"2023-05-03T17:11:24","name":"ld: pru: Place exception-handling sections correctly","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230503171124.6710-1-dimitar@dinux.eu/mbox/"},{"id":89976,"url":"https://patchwork.plctlab.org/api/1.2/patches/89976/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230504081452.50748-1-nelson@rivosinc.com/","msgid":"<20230504081452.50748-1-nelson@rivosinc.com>","list_archive_url":null,"date":"2023-05-04T08:14:52","name":"RISC-V: Minor improvements for dis-assembler.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230504081452.50748-1-nelson@rivosinc.com/mbox/"},{"id":90003,"url":"https://patchwork.plctlab.org/api/1.2/patches/90003/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230504090850.91004-1-nelson@rivosinc.com/","msgid":"<20230504090850.91004-1-nelson@rivosinc.com>","list_archive_url":null,"date":"2023-05-04T09:08:50","name":"[PR,ld/22263,PR,ld/25694] RISC-V: Avoid dynamic TLS relocs in PIE.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230504090850.91004-1-nelson@rivosinc.com/mbox/"},{"id":90380,"url":"https://patchwork.plctlab.org/api/1.2/patches/90380/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230505092316.1046472-1-aleksandar.rikalo@syrmia.com/","msgid":"<20230505092316.1046472-1-aleksandar.rikalo@syrmia.com>","list_archive_url":null,"date":"2023-05-05T09:23:16","name":"[v5] Add support for nanoMIPS architecture","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230505092316.1046472-1-aleksandar.rikalo@syrmia.com/mbox/"},{"id":90383,"url":"https://patchwork.plctlab.org/api/1.2/patches/90383/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230505092716.885338-1-yunqiang.su@cipunited.com/","msgid":"<20230505092716.885338-1-yunqiang.su@cipunited.com>","list_archive_url":null,"date":"2023-05-05T09:27:16","name":"gas: documents .gnu_attribute Tag_GNU_MIPS_ABI_MSA","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230505092716.885338-1-yunqiang.su@cipunited.com/mbox/"},{"id":90408,"url":"https://patchwork.plctlab.org/api/1.2/patches/90408/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a63ab9f1-6150-1948-c6e2-6a77855155e6@suse.com/","msgid":"","list_archive_url":null,"date":"2023-05-05T11:10:21","name":"x86: slightly simplify i386_parse_name()","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a63ab9f1-6150-1948-c6e2-6a77855155e6@suse.com/mbox/"},{"id":90410,"url":"https://patchwork.plctlab.org/api/1.2/patches/90410/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/52d14c6e-e232-efe3-d486-06cda1c19fdf@suse.com/","msgid":"<52d14c6e-e232-efe3-d486-06cda1c19fdf@suse.com>","list_archive_url":null,"date":"2023-05-05T11:12:44","name":"[1/2] x86: move get() disassembler helper functions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/52d14c6e-e232-efe3-d486-06cda1c19fdf@suse.com/mbox/"},{"id":90411,"url":"https://patchwork.plctlab.org/api/1.2/patches/90411/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/666d8c60-5ffe-a307-f260-0c4bbd674887@suse.com/","msgid":"<666d8c60-5ffe-a307-f260-0c4bbd674887@suse.com>","list_archive_url":null,"date":"2023-05-05T11:13:10","name":"[2/2] x86: move a few more disassembler helper functions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/666d8c60-5ffe-a307-f260-0c4bbd674887@suse.com/mbox/"},{"id":90430,"url":"https://patchwork.plctlab.org/api/1.2/patches/90430/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4735d366-fe31-0092-2edc-d166184b8567@suse.com/","msgid":"<4735d366-fe31-0092-2edc-d166184b8567@suse.com>","list_archive_url":null,"date":"2023-05-05T12:51:05","name":"[1/2] x86: don'\''t recognize quoted symbol names as registers or operators","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4735d366-fe31-0092-2edc-d166184b8567@suse.com/mbox/"},{"id":90431,"url":"https://patchwork.plctlab.org/api/1.2/patches/90431/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9d0f914a-5668-a09b-5993-16a2270cf059@suse.com/","msgid":"<9d0f914a-5668-a09b-5993-16a2270cf059@suse.com>","list_archive_url":null,"date":"2023-05-05T12:52:02","name":"[2/2] x86/Intel: address quoted-symbol related FIXMEs","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9d0f914a-5668-a09b-5993-16a2270cf059@suse.com/mbox/"},{"id":90432,"url":"https://patchwork.plctlab.org/api/1.2/patches/90432/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/168dfa6e-63d2-06d5-49d5-4d7a1797efb4@suse.com/","msgid":"<168dfa6e-63d2-06d5-49d5-4d7a1797efb4@suse.com>","list_archive_url":null,"date":"2023-05-05T13:01:10","name":"[1/4] x86: tighten extend-to-32bit-address conditions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/168dfa6e-63d2-06d5-49d5-4d7a1797efb4@suse.com/mbox/"},{"id":90434,"url":"https://patchwork.plctlab.org/api/1.2/patches/90434/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/905e0a5d-d49d-03a6-d441-302bc5c2da6a@suse.com/","msgid":"<905e0a5d-d49d-03a6-d441-302bc5c2da6a@suse.com>","list_archive_url":null,"date":"2023-05-05T13:01:57","name":"[2/4] gas: maintain O_constant signedness in more cases","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/905e0a5d-d49d-03a6-d441-302bc5c2da6a@suse.com/mbox/"},{"id":90435,"url":"https://patchwork.plctlab.org/api/1.2/patches/90435/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a766b568-5192-9660-34cd-2df6415a85c4@suse.com/","msgid":"","list_archive_url":null,"date":"2023-05-05T13:03:57","name":"[3/4] gas: invoke md_optimize_expr() also for unary expressions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a766b568-5192-9660-34cd-2df6415a85c4@suse.com/mbox/"},{"id":90436,"url":"https://patchwork.plctlab.org/api/1.2/patches/90436/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4f7d2d8d-d4fd-a799-9c8f-7a955a786d60@suse.com/","msgid":"<4f7d2d8d-d4fd-a799-9c8f-7a955a786d60@suse.com>","list_archive_url":null,"date":"2023-05-05T13:04:37","name":"[4/4] x86: further adjust extend-to-32bit-address conditions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4f7d2d8d-d4fd-a799-9c8f-7a955a786d60@suse.com/mbox/"},{"id":90707,"url":"https://patchwork.plctlab.org/api/1.2/patches/90707/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230506083718.3669965-1-yunqiang.su@cipunited.com/","msgid":"<20230506083718.3669965-1-yunqiang.su@cipunited.com>","list_archive_url":null,"date":"2023-05-06T08:37:18","name":"MIPS: gas: alter 64 or 32 for r6 triples if march is implicit","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230506083718.3669965-1-yunqiang.su@cipunited.com/mbox/"},{"id":90756,"url":"https://patchwork.plctlab.org/api/1.2/patches/90756/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/OS3P286MB2152C5D5037E18A71DEBF80BF0739@OS3P286MB2152.JPNP286.PROD.OUTLOOK.COM/","msgid":"","list_archive_url":null,"date":"2023-05-06T13:11:56","name":"Fix a typo in the README of binutils","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/OS3P286MB2152C5D5037E18A71DEBF80BF0739@OS3P286MB2152.JPNP286.PROD.OUTLOOK.COM/mbox/"},{"id":90933,"url":"https://patchwork.plctlab.org/api/1.2/patches/90933/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZFh73WJCS1aujdsO@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-05-08T04:34:37","name":"PR30343, LTO ignores linker reference to _pei386_runtime_relocator","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZFh73WJCS1aujdsO@squeak.grove.modra.org/mbox/"},{"id":90934,"url":"https://patchwork.plctlab.org/api/1.2/patches/90934/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZFh8AXXazWkP9+0w@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-05-08T04:35:13","name":"pe.em and pep.em make_import_fixup","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZFh8AXXazWkP9+0w@squeak.grove.modra.org/mbox/"},{"id":91322,"url":"https://patchwork.plctlab.org/api/1.2/patches/91322/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230509003247.24156-1-mark@harmstone.com/","msgid":"<20230509003247.24156-1-mark@harmstone.com>","list_archive_url":null,"date":"2023-05-09T00:32:46","name":"[1/2] pdb: Allow loading by gdb","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230509003247.24156-1-mark@harmstone.com/mbox/"},{"id":91323,"url":"https://patchwork.plctlab.org/api/1.2/patches/91323/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230509003247.24156-2-mark@harmstone.com/","msgid":"<20230509003247.24156-2-mark@harmstone.com>","list_archive_url":null,"date":"2023-05-09T00:32:47","name":"[2/2] gdb: Allow reading of enum definitions in PDB files","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230509003247.24156-2-mark@harmstone.com/mbox/"},{"id":91360,"url":"https://patchwork.plctlab.org/api/1.2/patches/91360/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZFnEez0cjGviUx4M@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-05-09T03:56:43","name":"alpha-vms reloc sanity check","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZFnEez0cjGviUx4M@squeak.grove.modra.org/mbox/"},{"id":91405,"url":"https://patchwork.plctlab.org/api/1.2/patches/91405/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZFn66p7K1lW/yNEL@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-05-09T07:48:58","name":"stack overflow in debug_write_type","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZFn66p7K1lW/yNEL@squeak.grove.modra.org/mbox/"},{"id":92148,"url":"https://patchwork.plctlab.org/api/1.2/patches/92148/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.LSU.2.20.2305101400000.13548@wotan.suse.de/","msgid":"","list_archive_url":null,"date":"2023-05-10T14:04:27","name":"PR30437 aarch64: make RELA relocs idempotent","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.LSU.2.20.2305101400000.13548@wotan.suse.de/mbox/"},{"id":92153,"url":"https://patchwork.plctlab.org/api/1.2/patches/92153/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230510141829.2748105-2-aleksandar.rikalo@syrmia.com/","msgid":"<20230510141829.2748105-2-aleksandar.rikalo@syrmia.com>","list_archive_url":null,"date":"2023-05-10T14:18:27","name":"[v6,1/3] BFD changes for nanoMIPS support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230510141829.2748105-2-aleksandar.rikalo@syrmia.com/mbox/"},{"id":92154,"url":"https://patchwork.plctlab.org/api/1.2/patches/92154/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230510141829.2748105-3-aleksandar.rikalo@syrmia.com/","msgid":"<20230510141829.2748105-3-aleksandar.rikalo@syrmia.com>","list_archive_url":null,"date":"2023-05-10T14:18:28","name":"[v6,2/3] Opcodes changes for nanoMIPS support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230510141829.2748105-3-aleksandar.rikalo@syrmia.com/mbox/"},{"id":92152,"url":"https://patchwork.plctlab.org/api/1.2/patches/92152/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230510141829.2748105-4-aleksandar.rikalo@syrmia.com/","msgid":"<20230510141829.2748105-4-aleksandar.rikalo@syrmia.com>","list_archive_url":null,"date":"2023-05-10T14:18:29","name":"[v6,3/3] Readelf for nanoMIPS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230510141829.2748105-4-aleksandar.rikalo@syrmia.com/mbox/"},{"id":92359,"url":"https://patchwork.plctlab.org/api/1.2/patches/92359/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/243D0799-E3D0-4938-A438-DD8725593F67@free.fr/","msgid":"<243D0799-E3D0-4938-A438-DD8725593F67@free.fr>","list_archive_url":null,"date":"2023-05-11T05:28:58","name":"pe/coff - add support for base64 encoded long section names","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/243D0799-E3D0-4938-A438-DD8725593F67@free.fr/mbox/"},{"id":92467,"url":"https://patchwork.plctlab.org/api/1.2/patches/92467/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230511100354.3995358-1-mengqinggang@loongson.cn/","msgid":"<20230511100354.3995358-1-mengqinggang@loongson.cn>","list_archive_url":null,"date":"2023-05-11T10:03:54","name":"LoongArch: Fix PLT entry generate bug","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230511100354.3995358-1-mengqinggang@loongson.cn/mbox/"},{"id":92629,"url":"https://patchwork.plctlab.org/api/1.2/patches/92629/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230511141351.18886-2-jose.marchesi@oracle.com/","msgid":"<20230511141351.18886-2-jose.marchesi@oracle.com>","list_archive_url":null,"date":"2023-05-11T14:13:48","name":"[1/4] opcodes: use CGEN_INSN_LGUINT for base instructions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230511141351.18886-2-jose.marchesi@oracle.com/mbox/"},{"id":92630,"url":"https://patchwork.plctlab.org/api/1.2/patches/92630/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230511141351.18886-3-jose.marchesi@oracle.com/","msgid":"<20230511141351.18886-3-jose.marchesi@oracle.com>","list_archive_url":null,"date":"2023-05-11T14:13:49","name":"[2/4] cpu: add V3 BPF atomic instructions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230511141351.18886-3-jose.marchesi@oracle.com/mbox/"},{"id":92634,"url":"https://patchwork.plctlab.org/api/1.2/patches/92634/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230511141351.18886-4-jose.marchesi@oracle.com/","msgid":"<20230511141351.18886-4-jose.marchesi@oracle.com>","list_archive_url":null,"date":"2023-05-11T14:13:50","name":"[3/4] gas: add tests for BPF V3 atomic instructions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230511141351.18886-4-jose.marchesi@oracle.com/mbox/"},{"id":92637,"url":"https://patchwork.plctlab.org/api/1.2/patches/92637/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230511141351.18886-5-jose.marchesi@oracle.com/","msgid":"<20230511141351.18886-5-jose.marchesi@oracle.com>","list_archive_url":null,"date":"2023-05-11T14:13:51","name":"[4/4] gas: document V3 BPF atomic instructions in the GAS manual","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230511141351.18886-5-jose.marchesi@oracle.com/mbox/"},{"id":92848,"url":"https://patchwork.plctlab.org/api/1.2/patches/92848/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230511210232.1491265-1-goldstein.w.n@gmail.com/","msgid":"<20230511210232.1491265-1-goldstein.w.n@gmail.com>","list_archive_url":null,"date":"2023-05-11T21:02:32","name":"[v1] gold: Make '\''--section-ordering-file'\'' also specifiable in env variable","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230511210232.1491265-1-goldstein.w.n@gmail.com/mbox/"},{"id":92935,"url":"https://patchwork.plctlab.org/api/1.2/patches/92935/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/de17e059-80f6-5aa9-b693-14bdac45f0a4@rivosinc.com/","msgid":"","list_archive_url":null,"date":"2023-05-12T03:44:43","name":"[RFC] RISC-V: Support Zacas extension.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/de17e059-80f6-5aa9-b693-14bdac45f0a4@rivosinc.com/mbox/"},{"id":92974,"url":"https://patchwork.plctlab.org/api/1.2/patches/92974/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230512071720.1880195-2-yunqiang.su@cipunited.com/","msgid":"<20230512071720.1880195-2-yunqiang.su@cipunited.com>","list_archive_url":null,"date":"2023-05-12T07:17:17","name":"[1/4] MIPS: gas: alter 64 or 32 for mipsisa triples if march is implicit","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230512071720.1880195-2-yunqiang.su@cipunited.com/mbox/"},{"id":92976,"url":"https://patchwork.plctlab.org/api/1.2/patches/92976/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230512071720.1880195-3-yunqiang.su@cipunited.com/","msgid":"<20230512071720.1880195-3-yunqiang.su@cipunited.com>","list_archive_url":null,"date":"2023-05-12T07:17:18","name":"[2/4] MIPS: default r6 if vendor is img","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230512071720.1880195-3-yunqiang.su@cipunited.com/mbox/"},{"id":92978,"url":"https://patchwork.plctlab.org/api/1.2/patches/92978/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230512071720.1880195-4-yunqiang.su@cipunited.com/","msgid":"<20230512071720.1880195-4-yunqiang.su@cipunited.com>","list_archive_url":null,"date":"2023-05-12T07:17:19","name":"[3/4] MIPS: fix r6 testsuites","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230512071720.1880195-4-yunqiang.su@cipunited.com/mbox/"},{"id":92975,"url":"https://patchwork.plctlab.org/api/1.2/patches/92975/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230512071720.1880195-5-yunqiang.su@cipunited.com/","msgid":"<20230512071720.1880195-5-yunqiang.su@cipunited.com>","list_archive_url":null,"date":"2023-05-12T07:17:20","name":"[4/4] MIPS: fix -gnuabi64 testsuite","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230512071720.1880195-5-yunqiang.su@cipunited.com/mbox/"},{"id":93018,"url":"https://patchwork.plctlab.org/api/1.2/patches/93018/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230512091558.83523-1-nelson@rivosinc.com/","msgid":"<20230512091558.83523-1-nelson@rivosinc.com>","list_archive_url":null,"date":"2023-05-12T09:15:58","name":"RISC-V: PR27566, consider ELF_MAXPAGESIZE/COMMONPAGESIZE for gp relaxations.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230512091558.83523-1-nelson@rivosinc.com/mbox/"},{"id":93504,"url":"https://patchwork.plctlab.org/api/1.2/patches/93504/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZF9w7hthSZx+ryOw@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-05-13T11:13:50","name":"PR28902, -T script with INSERT ordering","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZF9w7hthSZx+ryOw@squeak.grove.modra.org/mbox/"},{"id":93505,"url":"https://patchwork.plctlab.org/api/1.2/patches/93505/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZF9x6S6gsYrA1lYO@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-05-13T11:18:01","name":"PR28955 mips gas segfault","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZF9x6S6gsYrA1lYO@squeak.grove.modra.org/mbox/"},{"id":93544,"url":"https://patchwork.plctlab.org/api/1.2/patches/93544/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230513172938.2831329-1-vladimir.mezentsev@oracle.com/","msgid":"<20230513172938.2831329-1-vladimir.mezentsev@oracle.com>","list_archive_url":null,"date":"2023-05-13T17:29:38","name":"[Review,is,neded] gprofng: include a new function in the right place","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230513172938.2831329-1-vladimir.mezentsev@oracle.com/mbox/"},{"id":93971,"url":"https://patchwork.plctlab.org/api/1.2/patches/93971/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/DU0P190MB200294640D702757F760A53383789@DU0P190MB2002.EURP190.PROD.OUTLOOK.COM/","msgid":"","list_archive_url":null,"date":"2023-05-15T08:50:27","name":"Decorated symbols in import libs (BUG 30421)","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/DU0P190MB200294640D702757F760A53383789@DU0P190MB2002.EURP190.PROD.OUTLOOK.COM/mbox/"},{"id":94420,"url":"https://patchwork.plctlab.org/api/1.2/patches/94420/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230516025426.2334478-2-yunqiang.su@cipunited.com/","msgid":"<20230516025426.2334478-2-yunqiang.su@cipunited.com>","list_archive_url":null,"date":"2023-05-16T02:54:22","name":"[v2,1/5] MIPS: gas: alter 64 or 32 for mipsisa triples if march is implicit","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230516025426.2334478-2-yunqiang.su@cipunited.com/mbox/"},{"id":94421,"url":"https://patchwork.plctlab.org/api/1.2/patches/94421/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230516025426.2334478-3-yunqiang.su@cipunited.com/","msgid":"<20230516025426.2334478-3-yunqiang.su@cipunited.com>","list_archive_url":null,"date":"2023-05-16T02:54:23","name":"[v2,2/5] MIPS: default r6 if vendor is img","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230516025426.2334478-3-yunqiang.su@cipunited.com/mbox/"},{"id":94425,"url":"https://patchwork.plctlab.org/api/1.2/patches/94425/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230516025426.2334478-4-yunqiang.su@cipunited.com/","msgid":"<20230516025426.2334478-4-yunqiang.su@cipunited.com>","list_archive_url":null,"date":"2023-05-16T02:54:24","name":"[v2,3/5] MIPS: fix r6 testsuites","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230516025426.2334478-4-yunqiang.su@cipunited.com/mbox/"},{"id":94423,"url":"https://patchwork.plctlab.org/api/1.2/patches/94423/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230516025426.2334478-5-yunqiang.su@cipunited.com/","msgid":"<20230516025426.2334478-5-yunqiang.su@cipunited.com>","list_archive_url":null,"date":"2023-05-16T02:54:25","name":"[v2,4/5] MIPS: fix -gnuabi64 testsuite","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230516025426.2334478-5-yunqiang.su@cipunited.com/mbox/"},{"id":94424,"url":"https://patchwork.plctlab.org/api/1.2/patches/94424/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230516025426.2334478-6-yunqiang.su@cipunited.com/","msgid":"<20230516025426.2334478-6-yunqiang.su@cipunited.com>","list_archive_url":null,"date":"2023-05-16T02:54:26","name":"[v2,5/5] MIPS: fix some ld testcases with compiler","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230516025426.2334478-6-yunqiang.su@cipunited.com/mbox/"},{"id":94985,"url":"https://patchwork.plctlab.org/api/1.2/patches/94985/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZGQXmQ+tAKqUC/IX@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-05-16T23:54:01","name":"gcc-4.5 build fixes","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZGQXmQ+tAKqUC/IX@squeak.grove.modra.org/mbox/"},{"id":94992,"url":"https://patchwork.plctlab.org/api/1.2/patches/94992/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZGQlZ4KofqcYiJX1@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-05-17T00:52:55","name":"PR29189, dlltool delaylibs corrupt float/double arguments","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZGQlZ4KofqcYiJX1@squeak.grove.modra.org/mbox/"},{"id":94997,"url":"https://patchwork.plctlab.org/api/1.2/patches/94997/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZGQzE2Ak4W5y2Xn9@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-05-17T01:51:15","name":"PR29961, plugin-api.h: \"Could not detect architecture endianess\"","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZGQzE2Ak4W5y2Xn9@squeak.grove.modra.org/mbox/"},{"id":95160,"url":"https://patchwork.plctlab.org/api/1.2/patches/95160/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/61663a6c-a5a4-812a-1110-06e0122aabba@suse.com/","msgid":"<61663a6c-a5a4-812a-1110-06e0122aabba@suse.com>","list_archive_url":null,"date":"2023-05-17T11:00:04","name":"x86: permit all relational operators in insn operands","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/61663a6c-a5a4-812a-1110-06e0122aabba@suse.com/mbox/"},{"id":95625,"url":"https://patchwork.plctlab.org/api/1.2/patches/95625/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZGWS/0oFOMVSyf+m@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-05-18T02:52:47","name":"PR11601, Solaris assembler compatibility doesn'\''t work","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZGWS/0oFOMVSyf+m@squeak.grove.modra.org/mbox/"},{"id":95637,"url":"https://patchwork.plctlab.org/api/1.2/patches/95637/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230518034102.1747564-1-jun.zhang@intel.com/","msgid":"<20230518034102.1747564-1-jun.zhang@intel.com>","list_archive_url":null,"date":"2023-05-18T03:41:02","name":"Support Intel FRED LKGS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230518034102.1747564-1-jun.zhang@intel.com/mbox/"},{"id":95667,"url":"https://patchwork.plctlab.org/api/1.2/patches/95667/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230518062025.1535847-1-indu.bhagat@oracle.com/","msgid":"<20230518062025.1535847-1-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-05-18T06:20:24","name":"[COMMITTED] libsframe: testsuite: add new tests for sframe_find_fre API","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230518062025.1535847-1-indu.bhagat@oracle.com/mbox/"},{"id":95668,"url":"https://patchwork.plctlab.org/api/1.2/patches/95668/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230518062025.1535847-2-indu.bhagat@oracle.com/","msgid":"<20230518062025.1535847-2-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-05-18T06:20:25","name":"[COMMITTED] libsframe: testsuite: add tests for sframe_get_funcdesc_with_addr API","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230518062025.1535847-2-indu.bhagat@oracle.com/mbox/"},{"id":95674,"url":"https://patchwork.plctlab.org/api/1.2/patches/95674/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230518065950.6166-1-xuli1@eswincomputing.com/","msgid":"<20230518065950.6166-1-xuli1@eswincomputing.com>","list_archive_url":null,"date":"2023-05-18T06:59:50","name":"RISC-V: Warn in AS if vsew/vlmul/vtype is reserved.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230518065950.6166-1-xuli1@eswincomputing.com/mbox/"},{"id":95717,"url":"https://patchwork.plctlab.org/api/1.2/patches/95717/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230518085739.2195035-1-lei.wang@oss.cipunited.com/","msgid":"<20230518085739.2195035-1-lei.wang@oss.cipunited.com>","list_archive_url":null,"date":"2023-05-18T08:57:50","name":"Add GINV(+VIRT) ASE for MIPSr6","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230518085739.2195035-1-lei.wang@oss.cipunited.com/mbox/"},{"id":95721,"url":"https://patchwork.plctlab.org/api/1.2/patches/95721/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230518092246.2450-1-nelson@rivosinc.com/","msgid":"<20230518092246.2450-1-nelson@rivosinc.com>","list_archive_url":null,"date":"2023-05-18T09:22:46","name":"RISC-V: Support subtraction of .uleb128.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230518092246.2450-1-nelson@rivosinc.com/mbox/"},{"id":96167,"url":"https://patchwork.plctlab.org/api/1.2/patches/96167/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230519021448.30120-1-xuli1@eswincomputing.com/","msgid":"<20230519021448.30120-1-xuli1@eswincomputing.com>","list_archive_url":null,"date":"2023-05-19T02:14:48","name":"RISC-V: Warn in AS if vsew/vlmul/vtype is reserved.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230519021448.30120-1-xuli1@eswincomputing.com/mbox/"},{"id":96176,"url":"https://patchwork.plctlab.org/api/1.2/patches/96176/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230519034835.664-2-shihua@iscas.ac.cn/","msgid":"<20230519034835.664-2-shihua@iscas.ac.cn>","list_archive_url":null,"date":"2023-05-19T03:48:32","name":"[RFC,1/4] RISC-V : Remove checking when -march=rv64XX and -mabi=ilp32X","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230519034835.664-2-shihua@iscas.ac.cn/mbox/"},{"id":96178,"url":"https://patchwork.plctlab.org/api/1.2/patches/96178/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230519034835.664-3-shihua@iscas.ac.cn/","msgid":"<20230519034835.664-3-shihua@iscas.ac.cn>","list_archive_url":null,"date":"2023-05-19T03:48:33","name":"[RFC,2/4] RISC-V : Add support for rv64 arch using ilp32 abi","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230519034835.664-3-shihua@iscas.ac.cn/mbox/"},{"id":96177,"url":"https://patchwork.plctlab.org/api/1.2/patches/96177/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230519034835.664-4-shihua@iscas.ac.cn/","msgid":"<20230519034835.664-4-shihua@iscas.ac.cn>","list_archive_url":null,"date":"2023-05-19T03:48:34","name":"[RFC,3/4] RISC-V : Add rv64 ilp32 support in disassemble","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230519034835.664-4-shihua@iscas.ac.cn/mbox/"},{"id":96180,"url":"https://patchwork.plctlab.org/api/1.2/patches/96180/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230519034835.664-5-shihua@iscas.ac.cn/","msgid":"<20230519034835.664-5-shihua@iscas.ac.cn>","list_archive_url":null,"date":"2023-05-19T03:48:35","name":"[RFC,4/4] gdb/riscv : Add rv64 ilp32 support in gdb","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230519034835.664-5-shihua@iscas.ac.cn/mbox/"},{"id":96420,"url":"https://patchwork.plctlab.org/api/1.2/patches/96420/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/54c5d383-28bc-c61d-48b2-93b2b40a444c@suse.com/","msgid":"<54c5d383-28bc-c61d-48b2-93b2b40a444c@suse.com>","list_archive_url":null,"date":"2023-05-19T13:24:05","name":"ld: drop stray blank from ld.texi","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/54c5d383-28bc-c61d-48b2-93b2b40a444c@suse.com/mbox/"},{"id":96421,"url":"https://patchwork.plctlab.org/api/1.2/patches/96421/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b660dcfd-4a87-d6a4-a737-572b1b555f7c@suse.com/","msgid":"","list_archive_url":null,"date":"2023-05-19T13:30:57","name":"[1/2] x86: de-duplicate operand_special_chars[] wrt extra_symbol_chars[]","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b660dcfd-4a87-d6a4-a737-572b1b555f7c@suse.com/mbox/"},{"id":96422,"url":"https://patchwork.plctlab.org/api/1.2/patches/96422/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/83c328ec-3eab-767c-e65c-0d83183fd18a@suse.com/","msgid":"<83c328ec-3eab-767c-e65c-0d83183fd18a@suse.com>","list_archive_url":null,"date":"2023-05-19T13:31:28","name":"[2/2] x86: figure braces aren'\''t really part of mnemonics","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/83c328ec-3eab-767c-e65c-0d83183fd18a@suse.com/mbox/"},{"id":96432,"url":"https://patchwork.plctlab.org/api/1.2/patches/96432/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4989461e-c6fe-b102-2be1-6806e28abbb2@suse.com/","msgid":"<4989461e-c6fe-b102-2be1-6806e28abbb2@suse.com>","list_archive_url":null,"date":"2023-05-19T13:51:24","name":"[1/4] x86: split gas testsuite .exp file","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4989461e-c6fe-b102-2be1-6806e28abbb2@suse.com/mbox/"},{"id":96433,"url":"https://patchwork.plctlab.org/api/1.2/patches/96433/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/da25f556-06a6-9b64-f333-04953812fcaa@suse.com/","msgid":"","list_archive_url":null,"date":"2023-05-19T13:51:57","name":"[2/4] x86-64: conditionalize tests using --32","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/da25f556-06a6-9b64-f333-04953812fcaa@suse.com/mbox/"},{"id":96434,"url":"https://patchwork.plctlab.org/api/1.2/patches/96434/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/778a4bcd-ac39-6512-38d2-782e4eb1eea9@suse.com/","msgid":"<778a4bcd-ac39-6512-38d2-782e4eb1eea9@suse.com>","list_archive_url":null,"date":"2023-05-19T13:52:18","name":"[3/4] x86-64: improve gas diagnostic when no 32-bit target is configured","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/778a4bcd-ac39-6512-38d2-782e4eb1eea9@suse.com/mbox/"},{"id":96435,"url":"https://patchwork.plctlab.org/api/1.2/patches/96435/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d5ebeef6-ea62-b26b-bd67-ea24a21582d8@suse.com/","msgid":"","list_archive_url":null,"date":"2023-05-19T13:52:57","name":"[4/4] iamcu: suppress tests which can'\''t possibly work","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d5ebeef6-ea62-b26b-bd67-ea24a21582d8@suse.com/mbox/"},{"id":96442,"url":"https://patchwork.plctlab.org/api/1.2/patches/96442/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2274d914-c77f-37e7-5589-870a647e24a0@suse.com/","msgid":"<2274d914-c77f-37e7-5589-870a647e24a0@suse.com>","list_archive_url":null,"date":"2023-05-19T14:06:31","name":"[1/3] x86: use fixed-width type for codep and friends","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2274d914-c77f-37e7-5589-870a647e24a0@suse.com/mbox/"},{"id":96443,"url":"https://patchwork.plctlab.org/api/1.2/patches/96443/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/65393035-8006-1a66-deae-70a88ed29077@suse.com/","msgid":"<65393035-8006-1a66-deae-70a88ed29077@suse.com>","list_archive_url":null,"date":"2023-05-19T14:06:57","name":"[2/3] x86: disassembling over-long insns","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/65393035-8006-1a66-deae-70a88ed29077@suse.com/mbox/"},{"id":96444,"url":"https://patchwork.plctlab.org/api/1.2/patches/96444/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/51d38635-479f-831f-e678-3da1a1c9acae@suse.com/","msgid":"<51d38635-479f-831f-e678-3da1a1c9acae@suse.com>","list_archive_url":null,"date":"2023-05-19T14:07:25","name":"[3/3] x86: convert two pointers to (indexing) integers","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/51d38635-479f-831f-e678-3da1a1c9acae@suse.com/mbox/"},{"id":96697,"url":"https://patchwork.plctlab.org/api/1.2/patches/96697/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZGgfi5EKNdCyxFOt@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-05-20T01:16:59","name":"tic54x set_arch_mach","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZGgfi5EKNdCyxFOt@squeak.grove.modra.org/mbox/"},{"id":96698,"url":"https://patchwork.plctlab.org/api/1.2/patches/96698/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZGgf5d2KsCwesZbD@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-05-20T01:18:29","name":"coffcode.h handle_COMDAT tidy","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZGgf5d2KsCwesZbD@squeak.grove.modra.org/mbox/"},{"id":96762,"url":"https://patchwork.plctlab.org/api/1.2/patches/96762/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZGiyriwnKNKJqiJV@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-05-20T11:44:46","name":"coff-mips refhi list","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZGiyriwnKNKJqiJV@squeak.grove.modra.org/mbox/"},{"id":96951,"url":"https://patchwork.plctlab.org/api/1.2/patches/96951/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230522013441.3074776-2-mengqinggang@loongson.cn/","msgid":"<20230522013441.3074776-2-mengqinggang@loongson.cn>","list_archive_url":null,"date":"2023-05-22T01:34:36","name":"[v4,1/6] LoongArch: include: Add support for linker relaxation.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230522013441.3074776-2-mengqinggang@loongson.cn/mbox/"},{"id":96954,"url":"https://patchwork.plctlab.org/api/1.2/patches/96954/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230522013441.3074776-3-mengqinggang@loongson.cn/","msgid":"<20230522013441.3074776-3-mengqinggang@loongson.cn>","list_archive_url":null,"date":"2023-05-22T01:34:37","name":"[v4,2/6] LoongArch: bfd: Add support for linker relaxation.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230522013441.3074776-3-mengqinggang@loongson.cn/mbox/"},{"id":96952,"url":"https://patchwork.plctlab.org/api/1.2/patches/96952/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230522013441.3074776-4-mengqinggang@loongson.cn/","msgid":"<20230522013441.3074776-4-mengqinggang@loongson.cn>","list_archive_url":null,"date":"2023-05-22T01:34:38","name":"[v4,3/6] LoongArch: opcodes: Add support for linker relaxation.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230522013441.3074776-4-mengqinggang@loongson.cn/mbox/"},{"id":96955,"url":"https://patchwork.plctlab.org/api/1.2/patches/96955/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230522013441.3074776-5-mengqinggang@loongson.cn/","msgid":"<20230522013441.3074776-5-mengqinggang@loongson.cn>","list_archive_url":null,"date":"2023-05-22T01:34:39","name":"[v4,4/6] LoongArch: binutils: Add support for linker relaxation.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230522013441.3074776-5-mengqinggang@loongson.cn/mbox/"},{"id":96956,"url":"https://patchwork.plctlab.org/api/1.2/patches/96956/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230522013441.3074776-6-mengqinggang@loongson.cn/","msgid":"<20230522013441.3074776-6-mengqinggang@loongson.cn>","list_archive_url":null,"date":"2023-05-22T01:34:40","name":"[v4,5/6] LoongArch: gas: Add support for linker relaxation.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230522013441.3074776-6-mengqinggang@loongson.cn/mbox/"},{"id":96957,"url":"https://patchwork.plctlab.org/api/1.2/patches/96957/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230522013441.3074776-7-mengqinggang@loongson.cn/","msgid":"<20230522013441.3074776-7-mengqinggang@loongson.cn>","list_archive_url":null,"date":"2023-05-22T01:34:41","name":"[v4,6/6] LoongArch: ld: Add support for linker relaxation.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230522013441.3074776-7-mengqinggang@loongson.cn/mbox/"},{"id":97053,"url":"https://patchwork.plctlab.org/api/1.2/patches/97053/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230522060030.100976-1-jun.zhang@intel.com/","msgid":"<20230522060030.100976-1-jun.zhang@intel.com>","list_archive_url":null,"date":"2023-05-22T06:00:30","name":"[v2] Support Intel FRED LKGS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230522060030.100976-1-jun.zhang@intel.com/mbox/"},{"id":97056,"url":"https://patchwork.plctlab.org/api/1.2/patches/97056/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230522060726.101037-1-jun.zhang@intel.com/","msgid":"<20230522060726.101037-1-jun.zhang@intel.com>","list_archive_url":null,"date":"2023-05-22T06:07:26","name":"[v2] Support Intel FRED LKGS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230522060726.101037-1-jun.zhang@intel.com/mbox/"},{"id":97175,"url":"https://patchwork.plctlab.org/api/1.2/patches/97175/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZGsqFcGAvyznqFbB@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-05-22T08:38:45","name":"PowerPC64 report number of stub iterations","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZGsqFcGAvyznqFbB@squeak.grove.modra.org/mbox/"},{"id":97480,"url":"https://patchwork.plctlab.org/api/1.2/patches/97480/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230522142036.199490-1-jun.zhang@intel.com/","msgid":"<20230522142036.199490-1-jun.zhang@intel.com>","list_archive_url":null,"date":"2023-05-22T14:20:36","name":"[v3] Support Intel FRED LKGS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230522142036.199490-1-jun.zhang@intel.com/mbox/"},{"id":97571,"url":"https://patchwork.plctlab.org/api/1.2/patches/97571/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b0750b7e-fc76-d5ed-cd26-1a1bb6a1f2db@free.fr/","msgid":"","list_archive_url":null,"date":"2023-05-22T19:48:22","name":"[v2] pe/coff - add support for base64 encoded long section names","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b0750b7e-fc76-d5ed-cd26-1a1bb6a1f2db@free.fr/mbox/"},{"id":99104,"url":"https://patchwork.plctlab.org/api/1.2/patches/99104/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/871qj41iw5.fsf@redhat.com/","msgid":"<871qj41iw5.fsf@redhat.com>","list_archive_url":null,"date":"2023-05-25T16:21:46","name":"RFC: Objdump: Dumping PE specific headers","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/871qj41iw5.fsf@redhat.com/mbox/"},{"id":99146,"url":"https://patchwork.plctlab.org/api/1.2/patches/99146/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/87y1lcxpj0.fsf@igel.home/","msgid":"<87y1lcxpj0.fsf@igel.home>","list_archive_url":null,"date":"2023-05-25T17:57:23","name":"Remove duplicate definition","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/87y1lcxpj0.fsf@igel.home/mbox/"},{"id":99271,"url":"https://patchwork.plctlab.org/api/1.2/patches/99271/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZHAjjvo+Ldk5OyAQ@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-05-26T03:12:14","name":"PR22263 ld test, riscv fail","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZHAjjvo+Ldk5OyAQ@squeak.grove.modra.org/mbox/"},{"id":99314,"url":"https://patchwork.plctlab.org/api/1.2/patches/99314/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230526070132.4185600-1-indu.bhagat@oracle.com/","msgid":"<20230526070132.4185600-1-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-05-26T07:01:29","name":"[COMMITTED] libsframe: use uint8_t data type for FRE info related stubs","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230526070132.4185600-1-indu.bhagat@oracle.com/mbox/"},{"id":99315,"url":"https://patchwork.plctlab.org/api/1.2/patches/99315/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230526070132.4185600-2-indu.bhagat@oracle.com/","msgid":"<20230526070132.4185600-2-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-05-26T07:01:30","name":"[COMMITTED] libsframe: use const char * consistently for immutable FRE buffers","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230526070132.4185600-2-indu.bhagat@oracle.com/mbox/"},{"id":99316,"url":"https://patchwork.plctlab.org/api/1.2/patches/99316/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230526070132.4185600-3-indu.bhagat@oracle.com/","msgid":"<20230526070132.4185600-3-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-05-26T07:01:31","name":"[COMMITTED] libsframe: revisit sframe_find_fre API","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230526070132.4185600-3-indu.bhagat@oracle.com/mbox/"},{"id":99317,"url":"https://patchwork.plctlab.org/api/1.2/patches/99317/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230526070132.4185600-4-indu.bhagat@oracle.com/","msgid":"<20230526070132.4185600-4-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-05-26T07:01:32","name":"[COMMITTED] sframe/doc: minor improvements for readability","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230526070132.4185600-4-indu.bhagat@oracle.com/mbox/"},{"id":99387,"url":"https://patchwork.plctlab.org/api/1.2/patches/99387/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230526073833.3933735-2-mengqinggang@loongson.cn/","msgid":"<20230526073833.3933735-2-mengqinggang@loongson.cn>","list_archive_url":null,"date":"2023-05-26T07:38:28","name":"[v5,1/6] LoongArch: include: Add support for linker relaxation.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230526073833.3933735-2-mengqinggang@loongson.cn/mbox/"},{"id":99397,"url":"https://patchwork.plctlab.org/api/1.2/patches/99397/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230526073833.3933735-3-mengqinggang@loongson.cn/","msgid":"<20230526073833.3933735-3-mengqinggang@loongson.cn>","list_archive_url":null,"date":"2023-05-26T07:38:29","name":"[v5,2/6] LoongArch: bfd: Add support for linker relaxation.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230526073833.3933735-3-mengqinggang@loongson.cn/mbox/"},{"id":99391,"url":"https://patchwork.plctlab.org/api/1.2/patches/99391/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230526073833.3933735-4-mengqinggang@loongson.cn/","msgid":"<20230526073833.3933735-4-mengqinggang@loongson.cn>","list_archive_url":null,"date":"2023-05-26T07:38:30","name":"[v5,3/6] LoongArch: opcodes: Add support for linker relaxation.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230526073833.3933735-4-mengqinggang@loongson.cn/mbox/"},{"id":99393,"url":"https://patchwork.plctlab.org/api/1.2/patches/99393/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230526073833.3933735-5-mengqinggang@loongson.cn/","msgid":"<20230526073833.3933735-5-mengqinggang@loongson.cn>","list_archive_url":null,"date":"2023-05-26T07:38:31","name":"[v5,4/6] LoongArch: binutils: Add support for linker relaxation.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230526073833.3933735-5-mengqinggang@loongson.cn/mbox/"},{"id":99385,"url":"https://patchwork.plctlab.org/api/1.2/patches/99385/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230526073833.3933735-6-mengqinggang@loongson.cn/","msgid":"<20230526073833.3933735-6-mengqinggang@loongson.cn>","list_archive_url":null,"date":"2023-05-26T07:38:32","name":"[v5,5/6] LoongArch: gas: Add support for linker relaxation.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230526073833.3933735-6-mengqinggang@loongson.cn/mbox/"},{"id":99370,"url":"https://patchwork.plctlab.org/api/1.2/patches/99370/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230526073833.3933735-7-mengqinggang@loongson.cn/","msgid":"<20230526073833.3933735-7-mengqinggang@loongson.cn>","list_archive_url":null,"date":"2023-05-26T07:38:33","name":"[v5,6/6] LoongArch: ld: Add support for linker relaxation.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230526073833.3933735-7-mengqinggang@loongson.cn/mbox/"},{"id":99406,"url":"https://patchwork.plctlab.org/api/1.2/patches/99406/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230526082648.1503574-1-haochen.jiang@intel.com/","msgid":"<20230526082648.1503574-1-haochen.jiang@intel.com>","list_archive_url":null,"date":"2023-05-26T08:26:48","name":"x86: Add Evw to emit w suffix for several instrctions for word ptr","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230526082648.1503574-1-haochen.jiang@intel.com/mbox/"},{"id":99429,"url":"https://patchwork.plctlab.org/api/1.2/patches/99429/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230526101358.787593-1-jun.zhang@intel.com/","msgid":"<20230526101358.787593-1-jun.zhang@intel.com>","list_archive_url":null,"date":"2023-05-26T10:13:58","name":"Enable x86-64-fred-intel and x86-64-lkgs-intel test.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230526101358.787593-1-jun.zhang@intel.com/mbox/"},{"id":99644,"url":"https://patchwork.plctlab.org/api/1.2/patches/99644/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230526195407.2663991-1-vladimir.mezentsev@oracle.com/","msgid":"<20230526195407.2663991-1-vladimir.mezentsev@oracle.com>","list_archive_url":null,"date":"2023-05-26T19:54:07","name":"gprofng: 29470 The test suite should be made more flexible","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230526195407.2663991-1-vladimir.mezentsev@oracle.com/mbox/"},{"id":99645,"url":"https://patchwork.plctlab.org/api/1.2/patches/99645/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230526195518.2664720-1-vladimir.mezentsev@oracle.com/","msgid":"<20230526195518.2664720-1-vladimir.mezentsev@oracle.com>","list_archive_url":null,"date":"2023-05-26T19:55:18","name":"gprofng: Fix -Wsign-compare warning","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230526195518.2664720-1-vladimir.mezentsev@oracle.com/mbox/"},{"id":99734,"url":"https://patchwork.plctlab.org/api/1.2/patches/99734/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230527013620.65127-1-nelson@rivosinc.com/","msgid":"<20230527013620.65127-1-nelson@rivosinc.com>","list_archive_url":null,"date":"2023-05-27T01:36:20","name":"[PR,ld/22263] RISC-V: Avoid spurious R_RISCV_NONE for pr22263-1 test.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230527013620.65127-1-nelson@rivosinc.com/mbox/"},{"id":100526,"url":"https://patchwork.plctlab.org/api/1.2/patches/100526/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZHV5vB0C7IPf7sCX@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-05-30T04:21:16","name":"Regen binutils POTFILES.in","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZHV5vB0C7IPf7sCX@squeak.grove.modra.org/mbox/"},{"id":100527,"url":"https://patchwork.plctlab.org/api/1.2/patches/100527/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZHV544m6nKA2ck7Q@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-05-30T04:21:55","name":"Delete include/aout/encap.h","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZHV544m6nKA2ck7Q@squeak.grove.modra.org/mbox/"},{"id":100529,"url":"https://patchwork.plctlab.org/api/1.2/patches/100529/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZHV5/28XpXf2d9Wd@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-05-30T04:22:23","name":"Don'\''t define COFF_MAGIC","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZHV5/28XpXf2d9Wd@squeak.grove.modra.org/mbox/"},{"id":100528,"url":"https://patchwork.plctlab.org/api/1.2/patches/100528/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZHV6I0KUQQFhewlR@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-05-30T04:22:59","name":"Define IMAGE_FILE_MACHINE_ARMNT","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZHV6I0KUQQFhewlR@squeak.grove.modra.org/mbox/"},{"id":100530,"url":"https://patchwork.plctlab.org/api/1.2/patches/100530/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZHV6WtRazoQ6jCEo@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-05-30T04:23:54","name":"arm-pe objdump -P","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZHV6WtRazoQ6jCEo@squeak.grove.modra.org/mbox/"},{"id":101020,"url":"https://patchwork.plctlab.org/api/1.2/patches/101020/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230530171252.269552-2-hjl.tools@gmail.com/","msgid":"<20230530171252.269552-2-hjl.tools@gmail.com>","list_archive_url":null,"date":"2023-05-30T17:12:47","name":"[1/6] ELF: Strip section header in ELF objects","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230530171252.269552-2-hjl.tools@gmail.com/mbox/"},{"id":101025,"url":"https://patchwork.plctlab.org/api/1.2/patches/101025/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230530171252.269552-3-hjl.tools@gmail.com/","msgid":"<20230530171252.269552-3-hjl.tools@gmail.com>","list_archive_url":null,"date":"2023-05-30T17:12:48","name":"[2/6] bfd: Improve nm and objdump without section header","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230530171252.269552-3-hjl.tools@gmail.com/mbox/"},{"id":101028,"url":"https://patchwork.plctlab.org/api/1.2/patches/101028/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230530171252.269552-4-hjl.tools@gmail.com/","msgid":"<20230530171252.269552-4-hjl.tools@gmail.com>","list_archive_url":null,"date":"2023-05-30T17:12:49","name":"[3/6] ld: Add a simple test for -z nosectionheader","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230530171252.269552-4-hjl.tools@gmail.com/mbox/"},{"id":101022,"url":"https://patchwork.plctlab.org/api/1.2/patches/101022/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230530171252.269552-5-hjl.tools@gmail.com/","msgid":"<20230530171252.269552-5-hjl.tools@gmail.com>","list_archive_url":null,"date":"2023-05-30T17:12:50","name":"[4/6] binutils: Add a --strip-sections test","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230530171252.269552-5-hjl.tools@gmail.com/mbox/"},{"id":101027,"url":"https://patchwork.plctlab.org/api/1.2/patches/101027/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230530171252.269552-6-hjl.tools@gmail.com/","msgid":"<20230530171252.269552-6-hjl.tools@gmail.com>","list_archive_url":null,"date":"2023-05-30T17:12:51","name":"[5/6] ld: Add tests for -z nosectionheader and --strip-sections","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230530171252.269552-6-hjl.tools@gmail.com/mbox/"},{"id":101021,"url":"https://patchwork.plctlab.org/api/1.2/patches/101021/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230530171252.269552-7-hjl.tools@gmail.com/","msgid":"<20230530171252.269552-7-hjl.tools@gmail.com>","list_archive_url":null,"date":"2023-05-30T17:12:52","name":"[6/6] ld: Add -z nosectionheader test to bootstrap.exp","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230530171252.269552-7-hjl.tools@gmail.com/mbox/"},{"id":101296,"url":"https://patchwork.plctlab.org/api/1.2/patches/101296/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/87a5xkua9s.fsf@redhat.com/","msgid":"<87a5xkua9s.fsf@redhat.com>","list_archive_url":null,"date":"2023-05-31T09:21:03","name":"Commit: elfxx-loongarch64.c: Fix printf formatting issues.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/87a5xkua9s.fsf@redhat.com/mbox/"}],"public":true,"mbox":"https://patchwork.plctlab.org/bundle/patchwork-bot/binutils-gdb_2023-05/mbox/"},{"id":23,"url":"https://patchwork.plctlab.org/api/1.2/bundles/23/","web_url":"https://patchwork.plctlab.org/bundle/patchwork-bot/binutils-gdb_2023-06/","project":{"id":2,"url":"https://patchwork.plctlab.org/api/1.2/projects/2/","name":"binutils-gdb","link_name":"binutils-gdb","list_id":"binutils.sourceware.org","list_email":"binutils@sourceware.org","web_url":"https://github.com/wangliu-iscas/Patchwork-Bundles/blob/main/binutils-gdb.md","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"name":"binutils-gdb_2023-06","owner":{"id":3,"url":"https://patchwork.plctlab.org/api/1.2/users/3/","username":"patchwork-bot","first_name":"","last_name":"","email":"ouuuleilei@gmail.com"},"patches":[{"id":101537,"url":"https://patchwork.plctlab.org/api/1.2/patches/101537/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230531162856.48916-1-gianluca@rivosinc.com/","msgid":"<20230531162856.48916-1-gianluca@rivosinc.com>","list_archive_url":null,"date":"2023-05-31T16:28:56","name":"[RFC,v2] RISC-V: Support Zacas extension.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230531162856.48916-1-gianluca@rivosinc.com/mbox/"},{"id":101579,"url":"https://patchwork.plctlab.org/api/1.2/patches/101579/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230531200617.951996-2-hjl.tools@gmail.com/","msgid":"<20230531200617.951996-2-hjl.tools@gmail.com>","list_archive_url":null,"date":"2023-05-31T20:06:11","name":"[v2,1/7] ELF: Strip section header in ELF objects","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230531200617.951996-2-hjl.tools@gmail.com/mbox/"},{"id":101576,"url":"https://patchwork.plctlab.org/api/1.2/patches/101576/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230531200617.951996-3-hjl.tools@gmail.com/","msgid":"<20230531200617.951996-3-hjl.tools@gmail.com>","list_archive_url":null,"date":"2023-05-31T20:06:12","name":"[v2,2/7] ELF: Discard non-alloc sections without section header","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230531200617.951996-3-hjl.tools@gmail.com/mbox/"},{"id":101578,"url":"https://patchwork.plctlab.org/api/1.2/patches/101578/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230531200617.951996-4-hjl.tools@gmail.com/","msgid":"<20230531200617.951996-4-hjl.tools@gmail.com>","list_archive_url":null,"date":"2023-05-31T20:06:13","name":"[v2,3/7] bfd: Improve nm and objdump without section header","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230531200617.951996-4-hjl.tools@gmail.com/mbox/"},{"id":101572,"url":"https://patchwork.plctlab.org/api/1.2/patches/101572/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230531200617.951996-5-hjl.tools@gmail.com/","msgid":"<20230531200617.951996-5-hjl.tools@gmail.com>","list_archive_url":null,"date":"2023-05-31T20:06:14","name":"[v2,4/7] ld: Add a simple test for -z nosectionheader","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230531200617.951996-5-hjl.tools@gmail.com/mbox/"},{"id":101573,"url":"https://patchwork.plctlab.org/api/1.2/patches/101573/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230531200617.951996-6-hjl.tools@gmail.com/","msgid":"<20230531200617.951996-6-hjl.tools@gmail.com>","list_archive_url":null,"date":"2023-05-31T20:06:15","name":"[v2,5/7] binutils: Add a --strip-section-headers test","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230531200617.951996-6-hjl.tools@gmail.com/mbox/"},{"id":101580,"url":"https://patchwork.plctlab.org/api/1.2/patches/101580/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230531200617.951996-7-hjl.tools@gmail.com/","msgid":"<20230531200617.951996-7-hjl.tools@gmail.com>","list_archive_url":null,"date":"2023-05-31T20:06:16","name":"[v2,6/7] ld: Add tests for -z nosectionheader and --strip-section-headers","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230531200617.951996-7-hjl.tools@gmail.com/mbox/"},{"id":101574,"url":"https://patchwork.plctlab.org/api/1.2/patches/101574/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230531200617.951996-8-hjl.tools@gmail.com/","msgid":"<20230531200617.951996-8-hjl.tools@gmail.com>","list_archive_url":null,"date":"2023-05-31T20:06:17","name":"[v2,7/7] ld: Add -z nosectionheader test to bootstrap.exp","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230531200617.951996-8-hjl.tools@gmail.com/mbox/"},{"id":101625,"url":"https://patchwork.plctlab.org/api/1.2/patches/101625/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZHfmQsTZbxX1yUIq@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-06-01T00:28:50","name":"Remove BFD_FAIL in cpu-sh.c","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZHfmQsTZbxX1yUIq@squeak.grove.modra.org/mbox/"},{"id":101626,"url":"https://patchwork.plctlab.org/api/1.2/patches/101626/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZHfmjU0Ft5Jrcj3c@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-06-01T00:30:05","name":"section_by_target_index memory leak","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZHfmjU0Ft5Jrcj3c@squeak.grove.modra.org/mbox/"},{"id":101627,"url":"https://patchwork.plctlab.org/api/1.2/patches/101627/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZHfm5/WNQaE4NSYR@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-06-01T00:31:35","name":"bfd_close and target free_cached_memory","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZHfm5/WNQaE4NSYR@squeak.grove.modra.org/mbox/"},{"id":101628,"url":"https://patchwork.plctlab.org/api/1.2/patches/101628/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZHfnQckZnox2uLOu@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-06-01T00:33:05","name":"Harden PowerPC64 OPD handling against fuzzers","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZHfnQckZnox2uLOu@squeak.grove.modra.org/mbox/"},{"id":101754,"url":"https://patchwork.plctlab.org/api/1.2/patches/101754/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230601061610.2614564-1-indu.bhagat@oracle.com/","msgid":"<20230601061610.2614564-1-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-06-01T06:16:10","name":"[COMMITTED] libsframe: minor fixups in flip_fre related functions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230601061610.2614564-1-indu.bhagat@oracle.com/mbox/"},{"id":102114,"url":"https://patchwork.plctlab.org/api/1.2/patches/102114/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230601173312.3176329-1-indu.bhagat@oracle.com/","msgid":"<20230601173312.3176329-1-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-06-01T17:33:12","name":"[COMMITTED] libsframe: avoid using magic number","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230601173312.3176329-1-indu.bhagat@oracle.com/mbox/"},{"id":102244,"url":"https://patchwork.plctlab.org/api/1.2/patches/102244/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZHkxDSYR0EtVi6dY@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-06-02T00:00:13","name":"Minor objcopy optimisation for copy_relocations_in_section","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZHkxDSYR0EtVi6dY@squeak.grove.modra.org/mbox/"},{"id":102245,"url":"https://patchwork.plctlab.org/api/1.2/patches/102245/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZHkxOZ+7zNpFcAUv@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-06-02T00:00:57","name":"loongarch readelf support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZHkxOZ+7zNpFcAUv@squeak.grove.modra.org/mbox/"},{"id":102407,"url":"https://patchwork.plctlab.org/api/1.2/patches/102407/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230602092410.2841184-1-mengqinggang@loongson.cn/","msgid":"<20230602092410.2841184-1-mengqinggang@loongson.cn>","list_archive_url":null,"date":"2023-06-02T09:24:10","name":"LoongArch: gas: Relocations simplification when -mno-relax","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230602092410.2841184-1-mengqinggang@loongson.cn/mbox/"},{"id":102680,"url":"https://patchwork.plctlab.org/api/1.2/patches/102680/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230602192527.1532280-1-hjl.tools@gmail.com/","msgid":"<20230602192527.1532280-1-hjl.tools@gmail.com>","list_archive_url":null,"date":"2023-06-02T19:25:27","name":"ELF: Don'\''t warn an empty PT_LOAD with the program headers","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230602192527.1532280-1-hjl.tools@gmail.com/mbox/"},{"id":102961,"url":"https://patchwork.plctlab.org/api/1.2/patches/102961/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/221f70cf-5cff-6053-7499-499d4202e90b@debian.org/","msgid":"<221f70cf-5cff-6053-7499-499d4202e90b@debian.org>","list_archive_url":null,"date":"2023-06-04T06:44:45","name":"ignore lto-wrapper warnings for lto builds","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/221f70cf-5cff-6053-7499-499d4202e90b@debian.org/mbox/"},{"id":103136,"url":"https://patchwork.plctlab.org/api/1.2/patches/103136/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZH2Mwib11IEH7JDu@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-06-05T07:20:34","name":"Yet another ecoff fuzzed object fix","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZH2Mwib11IEH7JDu@squeak.grove.modra.org/mbox/"},{"id":103138,"url":"https://patchwork.plctlab.org/api/1.2/patches/103138/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZH2NDLgf5atBfB7S@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-06-05T07:21:48","name":"bfd_error_on_input messages","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZH2NDLgf5atBfB7S@squeak.grove.modra.org/mbox/"},{"id":103197,"url":"https://patchwork.plctlab.org/api/1.2/patches/103197/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230605102225.3566958-1-yunqiang.su@cipunited.com/","msgid":"<20230605102225.3566958-1-yunqiang.su@cipunited.com>","list_archive_url":null,"date":"2023-06-05T10:22:24","name":"[1/2] MIPS: Add n32 VECs to non-vendor elf targets","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230605102225.3566958-1-yunqiang.su@cipunited.com/mbox/"},{"id":103198,"url":"https://patchwork.plctlab.org/api/1.2/patches/103198/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230605102225.3566958-2-yunqiang.su@cipunited.com/","msgid":"<20230605102225.3566958-2-yunqiang.su@cipunited.com>","list_archive_url":null,"date":"2023-06-05T10:22:25","name":"[2/2] MIPS: fix Irix gas testcases","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230605102225.3566958-2-yunqiang.su@cipunited.com/mbox/"},{"id":103356,"url":"https://patchwork.plctlab.org/api/1.2/patches/103356/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230605153222.1728119-2-hjl.tools@gmail.com/","msgid":"<20230605153222.1728119-2-hjl.tools@gmail.com>","list_archive_url":null,"date":"2023-06-05T15:32:16","name":"[v3,1/7] ELF: Strip section header in ELF objects","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230605153222.1728119-2-hjl.tools@gmail.com/mbox/"},{"id":103349,"url":"https://patchwork.plctlab.org/api/1.2/patches/103349/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230605153222.1728119-3-hjl.tools@gmail.com/","msgid":"<20230605153222.1728119-3-hjl.tools@gmail.com>","list_archive_url":null,"date":"2023-06-05T15:32:17","name":"[v3,2/7] ELF: Discard non-alloc sections without section header","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230605153222.1728119-3-hjl.tools@gmail.com/mbox/"},{"id":103354,"url":"https://patchwork.plctlab.org/api/1.2/patches/103354/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230605153222.1728119-4-hjl.tools@gmail.com/","msgid":"<20230605153222.1728119-4-hjl.tools@gmail.com>","list_archive_url":null,"date":"2023-06-05T15:32:18","name":"[v3,3/7] bfd: Improve nm and objdump without section header","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230605153222.1728119-4-hjl.tools@gmail.com/mbox/"},{"id":103351,"url":"https://patchwork.plctlab.org/api/1.2/patches/103351/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230605153222.1728119-5-hjl.tools@gmail.com/","msgid":"<20230605153222.1728119-5-hjl.tools@gmail.com>","list_archive_url":null,"date":"2023-06-05T15:32:19","name":"[v3,4/7] ld: Add a simple test for -z nosectionheader","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230605153222.1728119-5-hjl.tools@gmail.com/mbox/"},{"id":103353,"url":"https://patchwork.plctlab.org/api/1.2/patches/103353/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230605153222.1728119-6-hjl.tools@gmail.com/","msgid":"<20230605153222.1728119-6-hjl.tools@gmail.com>","list_archive_url":null,"date":"2023-06-05T15:32:20","name":"[v3,5/7] binutils: Add a --strip-section-headers test","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230605153222.1728119-6-hjl.tools@gmail.com/mbox/"},{"id":103355,"url":"https://patchwork.plctlab.org/api/1.2/patches/103355/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230605153222.1728119-7-hjl.tools@gmail.com/","msgid":"<20230605153222.1728119-7-hjl.tools@gmail.com>","list_archive_url":null,"date":"2023-06-05T15:32:21","name":"[v3,6/7] ld: Add tests for -z nosectionheader and --strip-section-headers","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230605153222.1728119-7-hjl.tools@gmail.com/mbox/"},{"id":103350,"url":"https://patchwork.plctlab.org/api/1.2/patches/103350/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230605153222.1728119-8-hjl.tools@gmail.com/","msgid":"<20230605153222.1728119-8-hjl.tools@gmail.com>","list_archive_url":null,"date":"2023-06-05T15:32:22","name":"[v3,7/7] ld: Add -z nosectionheader test to bootstrap.exp","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230605153222.1728119-8-hjl.tools@gmail.com/mbox/"},{"id":103383,"url":"https://patchwork.plctlab.org/api/1.2/patches/103383/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230605163327.1864428-1-hjl.tools@gmail.com/","msgid":"<20230605163327.1864428-1-hjl.tools@gmail.com>","list_archive_url":null,"date":"2023-06-05T16:33:27","name":"ELF: Add \"#pass\" to ld-elf/pr30508.d","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230605163327.1864428-1-hjl.tools@gmail.com/mbox/"},{"id":103509,"url":"https://patchwork.plctlab.org/api/1.2/patches/103509/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230605214658.693003-1-indu.bhagat@oracle.com/","msgid":"<20230605214658.693003-1-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-06-05T21:46:58","name":"[COMMITTED] libsframe: avoid unnecessary type casts","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230605214658.693003-1-indu.bhagat@oracle.com/mbox/"},{"id":103542,"url":"https://patchwork.plctlab.org/api/1.2/patches/103542/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230606040315.4000351-1-yunqiang.su@cipunited.com/","msgid":"<20230606040315.4000351-1-yunqiang.su@cipunited.com>","list_archive_url":null,"date":"2023-06-06T04:03:13","name":"[v2,1/3] MIPS: disable fix-rm7000-2 and llpscp-64 if not has_newabi","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230606040315.4000351-1-yunqiang.su@cipunited.com/mbox/"},{"id":103543,"url":"https://patchwork.plctlab.org/api/1.2/patches/103543/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230606040315.4000351-2-yunqiang.su@cipunited.com/","msgid":"<20230606040315.4000351-2-yunqiang.su@cipunited.com>","list_archive_url":null,"date":"2023-06-06T04:03:14","name":"[v2,2/3] MIPS: Ignore the symbol index for comdat-reloc-r6.d","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230606040315.4000351-2-yunqiang.su@cipunited.com/mbox/"},{"id":103544,"url":"https://patchwork.plctlab.org/api/1.2/patches/103544/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230606040315.4000351-3-yunqiang.su@cipunited.com/","msgid":"<20230606040315.4000351-3-yunqiang.su@cipunited.com>","list_archive_url":null,"date":"2023-06-06T04:03:15","name":"[v2,3/3] MIPS: Fix Irix gas testcases","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230606040315.4000351-3-yunqiang.su@cipunited.com/mbox/"},{"id":103614,"url":"https://patchwork.plctlab.org/api/1.2/patches/103614/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230606074856.3463253-1-lei.wang@oss.cipunited.com/","msgid":"<20230606074856.3463253-1-lei.wang@oss.cipunited.com>","list_archive_url":null,"date":"2023-06-06T07:49:13","name":"[v2] Add GINV(+VIRT) ASE for MIPSr6","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230606074856.3463253-1-lei.wang@oss.cipunited.com/mbox/"},{"id":104005,"url":"https://patchwork.plctlab.org/api/1.2/patches/104005/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230606175846.399377-2-hjl.tools@gmail.com/","msgid":"<20230606175846.399377-2-hjl.tools@gmail.com>","list_archive_url":null,"date":"2023-06-06T17:58:40","name":"[v4,1/7] ELF: Strip section header in ELF objects","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230606175846.399377-2-hjl.tools@gmail.com/mbox/"},{"id":104004,"url":"https://patchwork.plctlab.org/api/1.2/patches/104004/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230606175846.399377-3-hjl.tools@gmail.com/","msgid":"<20230606175846.399377-3-hjl.tools@gmail.com>","list_archive_url":null,"date":"2023-06-06T17:58:41","name":"[v4,2/7] ELF: Discard non-alloc sections without section header","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230606175846.399377-3-hjl.tools@gmail.com/mbox/"},{"id":104009,"url":"https://patchwork.plctlab.org/api/1.2/patches/104009/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230606175846.399377-4-hjl.tools@gmail.com/","msgid":"<20230606175846.399377-4-hjl.tools@gmail.com>","list_archive_url":null,"date":"2023-06-06T17:58:42","name":"[v4,3/7] bfd: Improve nm and objdump without section header","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230606175846.399377-4-hjl.tools@gmail.com/mbox/"},{"id":104008,"url":"https://patchwork.plctlab.org/api/1.2/patches/104008/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230606175846.399377-5-hjl.tools@gmail.com/","msgid":"<20230606175846.399377-5-hjl.tools@gmail.com>","list_archive_url":null,"date":"2023-06-06T17:58:43","name":"[v4,4/7] ld: Add simple tests for -z nosectionheader","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230606175846.399377-5-hjl.tools@gmail.com/mbox/"},{"id":104006,"url":"https://patchwork.plctlab.org/api/1.2/patches/104006/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230606175846.399377-6-hjl.tools@gmail.com/","msgid":"<20230606175846.399377-6-hjl.tools@gmail.com>","list_archive_url":null,"date":"2023-06-06T17:58:44","name":"[v4,5/7] binutils: Add a --strip-section-headers test","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230606175846.399377-6-hjl.tools@gmail.com/mbox/"},{"id":104010,"url":"https://patchwork.plctlab.org/api/1.2/patches/104010/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230606175846.399377-7-hjl.tools@gmail.com/","msgid":"<20230606175846.399377-7-hjl.tools@gmail.com>","list_archive_url":null,"date":"2023-06-06T17:58:45","name":"[v4,6/7] ld: Add tests for -z nosectionheader and --strip-section-headers","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230606175846.399377-7-hjl.tools@gmail.com/mbox/"},{"id":104007,"url":"https://patchwork.plctlab.org/api/1.2/patches/104007/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230606175846.399377-8-hjl.tools@gmail.com/","msgid":"<20230606175846.399377-8-hjl.tools@gmail.com>","list_archive_url":null,"date":"2023-06-06T17:58:46","name":"[v4,7/7] ld: Add -z nosectionheader test to bootstrap.exp","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230606175846.399377-8-hjl.tools@gmail.com/mbox/"},{"id":104157,"url":"https://patchwork.plctlab.org/api/1.2/patches/104157/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230607001219.1262641-1-indu.bhagat@oracle.com/","msgid":"<20230607001219.1262641-1-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-06-07T00:12:19","name":"[COMMITTED] libsframe: fix cosmetic issues and typos","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230607001219.1262641-1-indu.bhagat@oracle.com/mbox/"},{"id":104187,"url":"https://patchwork.plctlab.org/api/1.2/patches/104187/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZH/kqvEBzDihSIXm@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-06-07T02:00:10","name":"objcopy memory leaks after errors","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZH/kqvEBzDihSIXm@squeak.grove.modra.org/mbox/"},{"id":104188,"url":"https://patchwork.plctlab.org/api/1.2/patches/104188/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZH/kzy91Kw/7oe/D@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-06-07T02:00:47","name":"bfd/elf.c strtab memory leak","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZH/kzy91Kw/7oe/D@squeak.grove.modra.org/mbox/"},{"id":104189,"url":"https://patchwork.plctlab.org/api/1.2/patches/104189/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZH/lDst5YNSnH53k@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-06-07T02:01:50","name":"Memory leaks in bfd/vms-lib.c","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZH/lDst5YNSnH53k@squeak.grove.modra.org/mbox/"},{"id":104228,"url":"https://patchwork.plctlab.org/api/1.2/patches/104228/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZIANNwcg5+tkbCiv@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-06-07T04:53:11","name":"_bfd_free_cached_info","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZIANNwcg5+tkbCiv@squeak.grove.modra.org/mbox/"},{"id":104370,"url":"https://patchwork.plctlab.org/api/1.2/patches/104370/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZIBPFJst5wp+jM/O@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-06-07T09:34:12","name":"ld-elf/eh5 remove xfail hppa64","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZIBPFJst5wp+jM/O@squeak.grove.modra.org/mbox/"},{"id":104777,"url":"https://patchwork.plctlab.org/api/1.2/patches/104777/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230607235757.4174552-1-indu.bhagat@oracle.com/","msgid":"<20230607235757.4174552-1-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-06-07T23:57:57","name":"[COMMITTED] libsframe: reuse static function sframe_decoder_get_funcdesc_at_index","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230607235757.4174552-1-indu.bhagat@oracle.com/mbox/"},{"id":104818,"url":"https://patchwork.plctlab.org/api/1.2/patches/104818/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230608044935.4183325-2-indu.bhagat@oracle.com/","msgid":"<20230608044935.4183325-2-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-06-08T04:49:34","name":"[1/2] libsframe: update the semantics of sframe_fre_get_ra_offset","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230608044935.4183325-2-indu.bhagat@oracle.com/mbox/"},{"id":104819,"url":"https://patchwork.plctlab.org/api/1.2/patches/104819/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230608044935.4183325-3-indu.bhagat@oracle.com/","msgid":"<20230608044935.4183325-3-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-06-08T04:49:35","name":"[2/2] libsframe: update the semantics of sframe_fre_get_fp_offset","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230608044935.4183325-3-indu.bhagat@oracle.com/mbox/"},{"id":105015,"url":"https://patchwork.plctlab.org/api/1.2/patches/105015/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230608155214.32435-1-palmer@rivosinc.com/","msgid":"<20230608155214.32435-1-palmer@rivosinc.com>","list_archive_url":null,"date":"2023-06-08T15:52:14","name":"RISC-V: Move __global_pointer$ to .sdata","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230608155214.32435-1-palmer@rivosinc.com/mbox/"},{"id":105186,"url":"https://patchwork.plctlab.org/api/1.2/patches/105186/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230609004717.30486-1-nelson@rivosinc.com/","msgid":"<20230609004717.30486-1-nelson@rivosinc.com>","list_archive_url":null,"date":"2023-06-09T00:47:17","name":"RISC-V: PR29823, defined the missing elf_backend_obj_attrs_handle_unknown.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230609004717.30486-1-nelson@rivosinc.com/mbox/"},{"id":105286,"url":"https://patchwork.plctlab.org/api/1.2/patches/105286/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZILCF8nLyVb4FoJ4@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-06-09T06:09:27","name":"ecoff find_nearest_line and final link leaks","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZILCF8nLyVb4FoJ4@squeak.grove.modra.org/mbox/"},{"id":105287,"url":"https://patchwork.plctlab.org/api/1.2/patches/105287/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZILCNa0O8HoJZZAo@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-06-09T06:09:57","name":"readelf/objdump remember_state memory leaks","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZILCNa0O8HoJZZAo@squeak.grove.modra.org/mbox/"},{"id":105603,"url":"https://patchwork.plctlab.org/api/1.2/patches/105603/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ad4cdc08-a78e-49ee-d650-bd5a8ebc164b@suse.com/","msgid":"","list_archive_url":null,"date":"2023-06-09T12:30:26","name":"x86: shrink Masking insn attribute to a single bit (boolean)","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ad4cdc08-a78e-49ee-d650-bd5a8ebc164b@suse.com/mbox/"},{"id":105785,"url":"https://patchwork.plctlab.org/api/1.2/patches/105785/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230609192822.2471957-1-indu.bhagat@oracle.com/","msgid":"<20230609192822.2471957-1-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-06-09T19:28:21","name":"[COMMITTED] libsframe: fix sframe_find_fre for pltN entries","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230609192822.2471957-1-indu.bhagat@oracle.com/mbox/"},{"id":105786,"url":"https://patchwork.plctlab.org/api/1.2/patches/105786/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230609192822.2471957-2-indu.bhagat@oracle.com/","msgid":"<20230609192822.2471957-2-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-06-09T19:28:22","name":"[COMMITTED] libsframe: testsuite: add sframe_find_fre tests for pltN entries","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230609192822.2471957-2-indu.bhagat@oracle.com/mbox/"},{"id":106323,"url":"https://patchwork.plctlab.org/api/1.2/patches/106323/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230612083649.907511-1-chenfeiyang@loongson.cn/","msgid":"<20230612083649.907511-1-chenfeiyang@loongson.cn>","list_archive_url":null,"date":"2023-06-12T08:36:49","name":"LoongArch: Add fcsr register names support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230612083649.907511-1-chenfeiyang@loongson.cn/mbox/"},{"id":107171,"url":"https://patchwork.plctlab.org/api/1.2/patches/107171/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230613080712.1651120-1-mengqinggang@loongson.cn/","msgid":"<20230613080712.1651120-1-mengqinggang@loongson.cn>","list_archive_url":null,"date":"2023-06-13T08:07:12","name":"LoongArch: Fix ld \"undefined reference\" error with --enable-shared","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230613080712.1651120-1-mengqinggang@loongson.cn/mbox/"},{"id":107373,"url":"https://patchwork.plctlab.org/api/1.2/patches/107373/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230613132342.783814-2-jiawei@iscas.ac.cn/","msgid":"<20230613132342.783814-2-jiawei@iscas.ac.cn>","list_archive_url":null,"date":"2023-06-13T13:23:39","name":"[1/4] RISC-V: Minimal support of ZC extensions.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230613132342.783814-2-jiawei@iscas.ac.cn/mbox/"},{"id":107375,"url":"https://patchwork.plctlab.org/api/1.2/patches/107375/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230613132342.783814-3-jiawei@iscas.ac.cn/","msgid":"<20230613132342.783814-3-jiawei@iscas.ac.cn>","list_archive_url":null,"date":"2023-06-13T13:23:40","name":"[2/4] RISC-V: Add Zca extension testcases.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230613132342.783814-3-jiawei@iscas.ac.cn/mbox/"},{"id":107377,"url":"https://patchwork.plctlab.org/api/1.2/patches/107377/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230613132342.783814-4-jiawei@iscas.ac.cn/","msgid":"<20230613132342.783814-4-jiawei@iscas.ac.cn>","list_archive_url":null,"date":"2023-06-13T13:23:41","name":"[3/4] RISC-V: Add Zcf extension testcases.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230613132342.783814-4-jiawei@iscas.ac.cn/mbox/"},{"id":107378,"url":"https://patchwork.plctlab.org/api/1.2/patches/107378/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230613132342.783814-5-jiawei@iscas.ac.cn/","msgid":"<20230613132342.783814-5-jiawei@iscas.ac.cn>","list_archive_url":null,"date":"2023-06-13T13:23:42","name":"[4/4] RISC-V: Add Zcd extension testcases.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230613132342.783814-5-jiawei@iscas.ac.cn/mbox/"},{"id":107381,"url":"https://patchwork.plctlab.org/api/1.2/patches/107381/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230613133851.786238-1-jiawei@iscas.ac.cn/","msgid":"<20230613133851.786238-1-jiawei@iscas.ac.cn>","list_archive_url":null,"date":"2023-06-13T13:38:50","name":"[1/2] RISC-V: Add Zcb extension supports.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230613133851.786238-1-jiawei@iscas.ac.cn/mbox/"},{"id":107380,"url":"https://patchwork.plctlab.org/api/1.2/patches/107380/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230613133851.786238-2-jiawei@iscas.ac.cn/","msgid":"<20230613133851.786238-2-jiawei@iscas.ac.cn>","list_archive_url":null,"date":"2023-06-13T13:38:51","name":"[2/2] RISC-V: Add Zcb extension testcases.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230613133851.786238-2-jiawei@iscas.ac.cn/mbox/"},{"id":107632,"url":"https://patchwork.plctlab.org/api/1.2/patches/107632/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230614000148.10989-2-david@davidgf.es/","msgid":"<20230614000148.10989-2-david@davidgf.es>","list_archive_url":null,"date":"2023-06-14T00:01:46","name":"[v2,1/3] Add MIPS Allegrex CPU as a MIPS2-based CPU","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230614000148.10989-2-david@davidgf.es/mbox/"},{"id":107631,"url":"https://patchwork.plctlab.org/api/1.2/patches/107631/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230614000148.10989-3-david@davidgf.es/","msgid":"<20230614000148.10989-3-david@davidgf.es>","list_archive_url":null,"date":"2023-06-14T00:01:47","name":"[v2,2/3] Add rotation instructions to MIPS Allegrex CPU","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230614000148.10989-3-david@davidgf.es/mbox/"},{"id":107630,"url":"https://patchwork.plctlab.org/api/1.2/patches/107630/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230614000148.10989-4-david@davidgf.es/","msgid":"<20230614000148.10989-4-david@davidgf.es>","list_archive_url":null,"date":"2023-06-14T00:01:48","name":"[v2,3/3] Add additional missing Allegrex CPU instructions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230614000148.10989-4-david@davidgf.es/mbox/"},{"id":107698,"url":"https://patchwork.plctlab.org/api/1.2/patches/107698/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZIlIv23B00XAlvGU@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-06-14T04:57:35","name":"asprintf memory leaks","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZIlIv23B00XAlvGU@squeak.grove.modra.org/mbox/"},{"id":107914,"url":"https://patchwork.plctlab.org/api/1.2/patches/107914/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/mvma5x245vb.fsf@suse.de/","msgid":"","list_archive_url":null,"date":"2023-06-14T11:53:44","name":"riscv: Use run-time endianess for floating point literals","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/mvma5x245vb.fsf@suse.de/mbox/"},{"id":107999,"url":"https://patchwork.plctlab.org/api/1.2/patches/107999/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/87ttva3xik.fsf@redhat.com/","msgid":"<87ttva3xik.fsf@redhat.com>","list_archive_url":null,"date":"2023-06-14T14:54:11","name":"commit: Add expected failures for some bfin linker tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/87ttva3xik.fsf@redhat.com/mbox/"},{"id":108238,"url":"https://patchwork.plctlab.org/api/1.2/patches/108238/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZIp6D6Of0QqK1XT0@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-06-15T02:40:15","name":"vms write_archive memory leaks","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZIp6D6Of0QqK1XT0@squeak.grove.modra.org/mbox/"},{"id":108244,"url":"https://patchwork.plctlab.org/api/1.2/patches/108244/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.DEB.2.21.2306150402280.64925@angie.orcam.me.uk/","msgid":"","list_archive_url":null,"date":"2023-06-15T03:50:33","name":"[committed] GAS/doc: Correct Tag_GNU_MIPS_ABI_MSA attribute description","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.DEB.2.21.2306150402280.64925@angie.orcam.me.uk/mbox/"},{"id":108247,"url":"https://patchwork.plctlab.org/api/1.2/patches/108247/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.DEB.2.21.2306150403370.64925@angie.orcam.me.uk/","msgid":"","list_archive_url":null,"date":"2023-06-15T03:51:53","name":"[committed] MIPS/GAS/testsuite: Fix `-modd-spreg'\''/`-mno-odd-spreg'\'' test invocations","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.DEB.2.21.2306150403370.64925@angie.orcam.me.uk/mbox/"},{"id":108432,"url":"https://patchwork.plctlab.org/api/1.2/patches/108432/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/AM6PR03MB49843D0F7C0438ADEB19172E985BA@AM6PR03MB4984.eurprd03.prod.outlook.com/","msgid":"","list_archive_url":null,"date":"2023-06-15T11:09:26","name":"[0/2] riscv: Fix gas when encoding BE floats/doubles","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/AM6PR03MB49843D0F7C0438ADEB19172E985BA@AM6PR03MB4984.eurprd03.prod.outlook.com/mbox/"},{"id":108551,"url":"https://patchwork.plctlab.org/api/1.2/patches/108551/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.DEB.2.21.2306151520460.64925@angie.orcam.me.uk/","msgid":"","list_archive_url":null,"date":"2023-06-15T14:24:56","name":"[committed] binutils/NEWS: Mention Sony Allegrex MIPS CPU support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.DEB.2.21.2306151520460.64925@angie.orcam.me.uk/mbox/"},{"id":108800,"url":"https://patchwork.plctlab.org/api/1.2/patches/108800/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230616031610.3982906-1-chenfeiyang@loongson.cn/","msgid":"<20230616031610.3982906-1-chenfeiyang@loongson.cn>","list_archive_url":null,"date":"2023-06-16T03:16:10","name":"[v2] LoongArch: Support referring to FCSRs as $fcsrX","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230616031610.3982906-1-chenfeiyang@loongson.cn/mbox/"},{"id":108836,"url":"https://patchwork.plctlab.org/api/1.2/patches/108836/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230616062504.1713904-2-yunqiang.su@cipunited.com/","msgid":"<20230616062504.1713904-2-yunqiang.su@cipunited.com>","list_archive_url":null,"date":"2023-06-16T06:24:54","name":"[v3,1/7] MIPS: Gas: alter 64 or 32 for mipsisa triples if march is implicit","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230616062504.1713904-2-yunqiang.su@cipunited.com/mbox/"},{"id":108840,"url":"https://patchwork.plctlab.org/api/1.2/patches/108840/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230616062504.1713904-3-yunqiang.su@cipunited.com/","msgid":"<20230616062504.1713904-3-yunqiang.su@cipunited.com>","list_archive_url":null,"date":"2023-06-16T06:24:55","name":"[v3,2/7] MIPS: default r6 if vendor is img","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230616062504.1713904-3-yunqiang.su@cipunited.com/mbox/"},{"id":108842,"url":"https://patchwork.plctlab.org/api/1.2/patches/108842/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230616062504.1713904-4-yunqiang.su@cipunited.com/","msgid":"<20230616062504.1713904-4-yunqiang.su@cipunited.com>","list_archive_url":null,"date":"2023-06-16T06:24:56","name":"[v3,2/7] MIPS: Set r6 as default arch if vendor is img","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230616062504.1713904-4-yunqiang.su@cipunited.com/mbox/"},{"id":108847,"url":"https://patchwork.plctlab.org/api/1.2/patches/108847/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230616062504.1713904-5-yunqiang.su@cipunited.com/","msgid":"<20230616062504.1713904-5-yunqiang.su@cipunited.com>","list_archive_url":null,"date":"2023-06-16T06:24:57","name":"[v3,3/7] MIPS: fix r6 testsuites","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230616062504.1713904-5-yunqiang.su@cipunited.com/mbox/"},{"id":108843,"url":"https://patchwork.plctlab.org/api/1.2/patches/108843/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230616062504.1713904-6-yunqiang.su@cipunited.com/","msgid":"<20230616062504.1713904-6-yunqiang.su@cipunited.com>","list_archive_url":null,"date":"2023-06-16T06:24:58","name":"[v3,3/7] MIPS: Fix r6 testsuites","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230616062504.1713904-6-yunqiang.su@cipunited.com/mbox/"},{"id":108851,"url":"https://patchwork.plctlab.org/api/1.2/patches/108851/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230616062504.1713904-7-yunqiang.su@cipunited.com/","msgid":"<20230616062504.1713904-7-yunqiang.su@cipunited.com>","list_archive_url":null,"date":"2023-06-16T06:24:59","name":"[v3,4/7] MIPS: fix -gnuabi64 testsuite","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230616062504.1713904-7-yunqiang.su@cipunited.com/mbox/"},{"id":108844,"url":"https://patchwork.plctlab.org/api/1.2/patches/108844/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230616062504.1713904-8-yunqiang.su@cipunited.com/","msgid":"<20230616062504.1713904-8-yunqiang.su@cipunited.com>","list_archive_url":null,"date":"2023-06-16T06:25:00","name":"[v3,4/7] MIPS: Fix -gnuabi64 testsuite","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230616062504.1713904-8-yunqiang.su@cipunited.com/mbox/"},{"id":108848,"url":"https://patchwork.plctlab.org/api/1.2/patches/108848/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230616062504.1713904-9-yunqiang.su@cipunited.com/","msgid":"<20230616062504.1713904-9-yunqiang.su@cipunited.com>","list_archive_url":null,"date":"2023-06-16T06:25:01","name":"[v3,5/7] MIPS: fix some ld testcases with compiler","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230616062504.1713904-9-yunqiang.su@cipunited.com/mbox/"},{"id":108846,"url":"https://patchwork.plctlab.org/api/1.2/patches/108846/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230616062504.1713904-10-yunqiang.su@cipunited.com/","msgid":"<20230616062504.1713904-10-yunqiang.su@cipunited.com>","list_archive_url":null,"date":"2023-06-16T06:25:02","name":"[v3,5/7] MIPS: Fix some ld testcases with compiler","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230616062504.1713904-10-yunqiang.su@cipunited.com/mbox/"},{"id":108857,"url":"https://patchwork.plctlab.org/api/1.2/patches/108857/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230616062504.1713904-11-yunqiang.su@cipunited.com/","msgid":"<20230616062504.1713904-11-yunqiang.su@cipunited.com>","list_archive_url":null,"date":"2023-06-16T06:25:03","name":"[v3,6/7] MIPS: disable fix-rm7000-2 and llpscp-64 if not has_newabi","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230616062504.1713904-11-yunqiang.su@cipunited.com/mbox/"},{"id":108863,"url":"https://patchwork.plctlab.org/api/1.2/patches/108863/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230616062504.1713904-12-yunqiang.su@cipunited.com/","msgid":"<20230616062504.1713904-12-yunqiang.su@cipunited.com>","list_archive_url":null,"date":"2023-06-16T06:25:04","name":"[v3,7/7] MIPS: Fix Irix gas testcases","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230616062504.1713904-12-yunqiang.su@cipunited.com/mbox/"},{"id":108869,"url":"https://patchwork.plctlab.org/api/1.2/patches/108869/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230616063412.1715024-2-yunqiang.su@cipunited.com/","msgid":"<20230616063412.1715024-2-yunqiang.su@cipunited.com>","list_archive_url":null,"date":"2023-06-16T06:34:06","name":"[v4,1/7] MIPS: Gas: alter 64 or 32 for mipsisa triples if march is implicit","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230616063412.1715024-2-yunqiang.su@cipunited.com/mbox/"},{"id":108870,"url":"https://patchwork.plctlab.org/api/1.2/patches/108870/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230616063412.1715024-3-yunqiang.su@cipunited.com/","msgid":"<20230616063412.1715024-3-yunqiang.su@cipunited.com>","list_archive_url":null,"date":"2023-06-16T06:34:07","name":"[v4,2/7] MIPS: Set r6 as default arch if vendor is img","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230616063412.1715024-3-yunqiang.su@cipunited.com/mbox/"},{"id":108878,"url":"https://patchwork.plctlab.org/api/1.2/patches/108878/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230616063412.1715024-4-yunqiang.su@cipunited.com/","msgid":"<20230616063412.1715024-4-yunqiang.su@cipunited.com>","list_archive_url":null,"date":"2023-06-16T06:34:08","name":"[v4,3/7] MIPS: Fix r6 testsuites","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230616063412.1715024-4-yunqiang.su@cipunited.com/mbox/"},{"id":108875,"url":"https://patchwork.plctlab.org/api/1.2/patches/108875/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230616063412.1715024-5-yunqiang.su@cipunited.com/","msgid":"<20230616063412.1715024-5-yunqiang.su@cipunited.com>","list_archive_url":null,"date":"2023-06-16T06:34:09","name":"[v4,4/7] MIPS: Fix -gnuabi64 testsuite","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230616063412.1715024-5-yunqiang.su@cipunited.com/mbox/"},{"id":108876,"url":"https://patchwork.plctlab.org/api/1.2/patches/108876/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230616063412.1715024-6-yunqiang.su@cipunited.com/","msgid":"<20230616063412.1715024-6-yunqiang.su@cipunited.com>","list_archive_url":null,"date":"2023-06-16T06:34:10","name":"[v4,5/7] MIPS: Fix some ld testcases with compiler","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230616063412.1715024-6-yunqiang.su@cipunited.com/mbox/"},{"id":108874,"url":"https://patchwork.plctlab.org/api/1.2/patches/108874/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230616063412.1715024-7-yunqiang.su@cipunited.com/","msgid":"<20230616063412.1715024-7-yunqiang.su@cipunited.com>","list_archive_url":null,"date":"2023-06-16T06:34:11","name":"[v4,6/7] MIPS: Disable fix-rm7000-2 and llpscp-64 if not has_newabi","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230616063412.1715024-7-yunqiang.su@cipunited.com/mbox/"},{"id":108877,"url":"https://patchwork.plctlab.org/api/1.2/patches/108877/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230616063412.1715024-8-yunqiang.su@cipunited.com/","msgid":"<20230616063412.1715024-8-yunqiang.su@cipunited.com>","list_archive_url":null,"date":"2023-06-16T06:34:12","name":"[v4,7/7] MIPS: Fix Irix gas testcases","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230616063412.1715024-8-yunqiang.su@cipunited.com/mbox/"},{"id":108891,"url":"https://patchwork.plctlab.org/api/1.2/patches/108891/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230616072536.1805704-1-yunqiang.su@cipunited.com/","msgid":"<20230616072536.1805704-1-yunqiang.su@cipunited.com>","list_archive_url":null,"date":"2023-06-16T07:25:35","name":"[v3,1/2] MIPS: Add MT ASE support for micromips32","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230616072536.1805704-1-yunqiang.su@cipunited.com/mbox/"},{"id":108892,"url":"https://patchwork.plctlab.org/api/1.2/patches/108892/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230616072536.1805704-2-yunqiang.su@cipunited.com/","msgid":"<20230616072536.1805704-2-yunqiang.su@cipunited.com>","list_archive_url":null,"date":"2023-06-16T07:25:36","name":"[v3,2/2] MIPS: Sync oprand char usage between mips and micromips","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230616072536.1805704-2-yunqiang.su@cipunited.com/mbox/"},{"id":108895,"url":"https://patchwork.plctlab.org/api/1.2/patches/108895/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/503caac8-8824-823a-81c2-762cba207cb6@suse.com/","msgid":"<503caac8-8824-823a-81c2-762cba207cb6@suse.com>","list_archive_url":null,"date":"2023-06-16T07:30:41","name":"[1/4] x86: optimize pre-AVX512 {,V}PCMPEQQ with identical sources","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/503caac8-8824-823a-81c2-762cba207cb6@suse.com/mbox/"},{"id":108896,"url":"https://patchwork.plctlab.org/api/1.2/patches/108896/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7141b586-9711-aef0-7f28-5d4489478f1b@suse.com/","msgid":"<7141b586-9711-aef0-7f28-5d4489478f1b@suse.com>","list_archive_url":null,"date":"2023-06-16T07:31:12","name":"[2/4] x86: optimize pre-AVX512 {,V}PCMPGT* with identical sources","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7141b586-9711-aef0-7f28-5d4489478f1b@suse.com/mbox/"},{"id":108899,"url":"https://patchwork.plctlab.org/api/1.2/patches/108899/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3e1b884e-7312-8546-ebdc-ac513a199858@suse.com/","msgid":"<3e1b884e-7312-8546-ebdc-ac513a199858@suse.com>","list_archive_url":null,"date":"2023-06-16T07:31:41","name":"[3/4] x86: optimize 128-bit VPBROADCASTQ to VPUNPCKLQDQ","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3e1b884e-7312-8546-ebdc-ac513a199858@suse.com/mbox/"},{"id":108900,"url":"https://patchwork.plctlab.org/api/1.2/patches/108900/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/08bf9dc9-5616-7dce-a094-d2ea799c92bf@suse.com/","msgid":"<08bf9dc9-5616-7dce-a094-d2ea799c92bf@suse.com>","list_archive_url":null,"date":"2023-06-16T07:32:40","name":"[4/4] x86: provide a 128-bit VBROADCASTSD pseudo","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/08bf9dc9-5616-7dce-a094-d2ea799c92bf@suse.com/mbox/"},{"id":109009,"url":"https://patchwork.plctlab.org/api/1.2/patches/109009/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f8f64771-eb63-2df3-b03b-8ed1cf3b4310@suse.com/","msgid":"","list_archive_url":null,"date":"2023-06-16T10:15:29","name":"[1/5] x86: re-work EVEX-z-without-masking check","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f8f64771-eb63-2df3-b03b-8ed1cf3b4310@suse.com/mbox/"},{"id":109010,"url":"https://patchwork.plctlab.org/api/1.2/patches/109010/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c7e5b576-f830-7493-74c1-66c05155fbec@suse.com/","msgid":"","list_archive_url":null,"date":"2023-06-16T10:15:55","name":"[2/5] x86: flag EVEX.z set when destination is a mask register","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c7e5b576-f830-7493-74c1-66c05155fbec@suse.com/mbox/"},{"id":109011,"url":"https://patchwork.plctlab.org/api/1.2/patches/109011/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/65872bf7-36c2-0a0a-8992-38a0843a897d@suse.com/","msgid":"<65872bf7-36c2-0a0a-8992-38a0843a897d@suse.com>","list_archive_url":null,"date":"2023-06-16T10:16:20","name":"[3/5] x86: flag EVEX.z set when destination is memory","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/65872bf7-36c2-0a0a-8992-38a0843a897d@suse.com/mbox/"},{"id":109013,"url":"https://patchwork.plctlab.org/api/1.2/patches/109013/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2574a7d2-68aa-70e3-c5da-fc726c952c22@suse.com/","msgid":"<2574a7d2-68aa-70e3-c5da-fc726c952c22@suse.com>","list_archive_url":null,"date":"2023-06-16T10:16:44","name":"[4/5] x86: flag EVEX masking when destination is GPR(-like)","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2574a7d2-68aa-70e3-c5da-fc726c952c22@suse.com/mbox/"},{"id":109017,"url":"https://patchwork.plctlab.org/api/1.2/patches/109017/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/33c2fa9f-1f8e-bed0-8653-39eb876fb0b3@suse.com/","msgid":"<33c2fa9f-1f8e-bed0-8653-39eb876fb0b3@suse.com>","list_archive_url":null,"date":"2023-06-16T10:17:26","name":"[5/5] x86: flag bad EVEX masking for miscellaneous insns","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/33c2fa9f-1f8e-bed0-8653-39eb876fb0b3@suse.com/mbox/"},{"id":109088,"url":"https://patchwork.plctlab.org/api/1.2/patches/109088/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/bd3adbb3-02d0-3fea-f154-ece44bed7b60@suse.com/","msgid":"","list_archive_url":null,"date":"2023-06-16T12:34:06","name":"x86: fix expansion of %XV","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/bd3adbb3-02d0-3fea-f154-ece44bed7b60@suse.com/mbox/"},{"id":109639,"url":"https://patchwork.plctlab.org/api/1.2/patches/109639/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/648f4180.a70a0220.a7021.407c@mx.google.com/","msgid":"<648f4180.a70a0220.a7021.407c@mx.google.com>","list_archive_url":null,"date":"2023-06-18T17:40:13","name":"[V3] optimize handle_COMDAT","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/648f4180.a70a0220.a7021.407c@mx.google.com/mbox/"},{"id":110435,"url":"https://patchwork.plctlab.org/api/1.2/patches/110435/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/AM6PR03MB49848E63E54AAB7B7C0D80E4985CA@AM6PR03MB4984.eurprd03.prod.outlook.com/","msgid":"","list_archive_url":null,"date":"2023-06-20T11:43:07","name":"[0/1] riscv: Ensure LE instruction fetching","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/AM6PR03MB49848E63E54AAB7B7C0D80E4985CA@AM6PR03MB4984.eurprd03.prod.outlook.com/mbox/"},{"id":110613,"url":"https://patchwork.plctlab.org/api/1.2/patches/110613/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230620164436.432481-1-hjl.tools@gmail.com/","msgid":"<20230620164436.432481-1-hjl.tools@gmail.com>","list_archive_url":null,"date":"2023-06-20T16:44:36","name":"x86: Don'\''t check if AVX512 template requires AVX512VL","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230620164436.432481-1-hjl.tools@gmail.com/mbox/"},{"id":110703,"url":"https://patchwork.plctlab.org/api/1.2/patches/110703/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230620223204.629663-1-hjl.tools@gmail.com/","msgid":"<20230620223204.629663-1-hjl.tools@gmail.com>","list_archive_url":null,"date":"2023-06-20T22:32:04","name":"x86: Free the symbol buffer and the relocation buffer after use","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230620223204.629663-1-hjl.tools@gmail.com/mbox/"},{"id":110789,"url":"https://patchwork.plctlab.org/api/1.2/patches/110789/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZJKWtMcKv3ZBw0Cq@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-06-21T06:20:36","name":"macho-o.c don'\''t leak strtab","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZJKWtMcKv3ZBw0Cq@squeak.grove.modra.org/mbox/"},{"id":110790,"url":"https://patchwork.plctlab.org/api/1.2/patches/110790/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZJKW2M//EO8S5UUV@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-06-21T06:21:12","name":"elf32_arm_get_synthetic_symtab memory leak","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZJKW2M//EO8S5UUV@squeak.grove.modra.org/mbox/"},{"id":110832,"url":"https://patchwork.plctlab.org/api/1.2/patches/110832/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230621072732.1652861-1-lili.cui@intel.com/","msgid":"<20230621072732.1652861-1-lili.cui@intel.com>","list_archive_url":null,"date":"2023-06-21T07:27:32","name":"gprofng: Update intel url","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230621072732.1652861-1-lili.cui@intel.com/mbox/"},{"id":110979,"url":"https://patchwork.plctlab.org/api/1.2/patches/110979/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/87352l6qjc.fsf@redhat.com/","msgid":"<87352l6qjc.fsf@redhat.com>","list_archive_url":null,"date":"2023-06-21T10:47:03","name":"Commit: Fix PR 29072 test with --enable-default-execstack=no","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/87352l6qjc.fsf@redhat.com/mbox/"},{"id":110983,"url":"https://patchwork.plctlab.org/api/1.2/patches/110983/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/87zg4t5awt.fsf@redhat.com/","msgid":"<87zg4t5awt.fsf@redhat.com>","list_archive_url":null,"date":"2023-06-21T11:09:54","name":"Commit: Prune warnings about -z execstack when --enable-warn-execstack=yes has been used","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/87zg4t5awt.fsf@redhat.com/mbox/"},{"id":111025,"url":"https://patchwork.plctlab.org/api/1.2/patches/111025/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZJL9LBr/Zuvjc+Yv@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-06-21T13:37:48","name":"[GOLD] PR30536, ppc64el gold linker produces unusable clang-16 binary","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZJL9LBr/Zuvjc+Yv@squeak.grove.modra.org/mbox/"},{"id":111790,"url":"https://patchwork.plctlab.org/api/1.2/patches/111790/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230622193759.737009-1-hjl.tools@gmail.com/","msgid":"<20230622193759.737009-1-hjl.tools@gmail.com>","list_archive_url":null,"date":"2023-06-22T19:37:59","name":"Revert \"x86: Don'\''t check if AVX512 template requires AVX512VL\"","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230622193759.737009-1-hjl.tools@gmail.com/mbox/"},{"id":111837,"url":"https://patchwork.plctlab.org/api/1.2/patches/111837/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230622232510.49099-1-david@davidgf.es/","msgid":"<20230622232510.49099-1-david@davidgf.es>","list_archive_url":null,"date":"2023-06-22T23:25:09","name":"[1/2] Exclude trap instructions for MIPS Allegrex","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230622232510.49099-1-david@davidgf.es/mbox/"},{"id":111838,"url":"https://patchwork.plctlab.org/api/1.2/patches/111838/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230622232510.49099-2-david@davidgf.es/","msgid":"<20230622232510.49099-2-david@davidgf.es>","list_archive_url":null,"date":"2023-06-22T23:25:10","name":"[2/2] Adding missing MIPS Allegrex instruction","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230622232510.49099-2-david@davidgf.es/mbox/"},{"id":111911,"url":"https://patchwork.plctlab.org/api/1.2/patches/111911/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230623044448.2617101-2-indu.bhagat@oracle.com/","msgid":"<20230623044448.2617101-2-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-06-23T04:44:39","name":"[01/10] libsframe: add library versioning","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230623044448.2617101-2-indu.bhagat@oracle.com/mbox/"},{"id":111910,"url":"https://patchwork.plctlab.org/api/1.2/patches/111910/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230623044448.2617101-3-indu.bhagat@oracle.com/","msgid":"<20230623044448.2617101-3-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-06-23T04:44:40","name":"[02/10] libsframe: remove sframe_get_funcdesc_with_addr API","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230623044448.2617101-3-indu.bhagat@oracle.com/mbox/"},{"id":111917,"url":"https://patchwork.plctlab.org/api/1.2/patches/111917/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230623044448.2617101-4-indu.bhagat@oracle.com/","msgid":"<20230623044448.2617101-4-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-06-23T04:44:41","name":"[03/10] libsframe: add symbol versioning","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230623044448.2617101-4-indu.bhagat@oracle.com/mbox/"},{"id":111913,"url":"https://patchwork.plctlab.org/api/1.2/patches/111913/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230623044448.2617101-5-indu.bhagat@oracle.com/","msgid":"<20230623044448.2617101-5-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-06-23T04:44:42","name":"[04/10] libsframe: update the semantics of sframe_fre_get_ra_offset","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230623044448.2617101-5-indu.bhagat@oracle.com/mbox/"},{"id":111912,"url":"https://patchwork.plctlab.org/api/1.2/patches/111912/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230623044448.2617101-6-indu.bhagat@oracle.com/","msgid":"<20230623044448.2617101-6-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-06-23T04:44:43","name":"[05/10] libsframe: update the semantics of sframe_fre_get_fp_offset","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230623044448.2617101-6-indu.bhagat@oracle.com/mbox/"},{"id":111916,"url":"https://patchwork.plctlab.org/api/1.2/patches/111916/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230623044448.2617101-7-indu.bhagat@oracle.com/","msgid":"<20230623044448.2617101-7-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-06-23T04:44:44","name":"[06/10] libsframe: use uint32_t for fre_type and fde_type function args","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230623044448.2617101-7-indu.bhagat@oracle.com/mbox/"},{"id":111919,"url":"https://patchwork.plctlab.org/api/1.2/patches/111919/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230623044448.2617101-8-indu.bhagat@oracle.com/","msgid":"<20230623044448.2617101-8-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-06-23T04:44:45","name":"[07/10] bfd: libsframe: use uint32_t for return type of sframe_calc_fre_type","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230623044448.2617101-8-indu.bhagat@oracle.com/mbox/"},{"id":111914,"url":"https://patchwork.plctlab.org/api/1.2/patches/111914/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230623044448.2617101-9-indu.bhagat@oracle.com/","msgid":"<20230623044448.2617101-9-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-06-23T04:44:46","name":"[08/10] libsframe: use uint8_t instead of unsigned char for abi_arch","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230623044448.2617101-9-indu.bhagat@oracle.com/mbox/"},{"id":111915,"url":"https://patchwork.plctlab.org/api/1.2/patches/111915/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230623044448.2617101-10-indu.bhagat@oracle.com/","msgid":"<20230623044448.2617101-10-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-06-23T04:44:47","name":"[09/10] libsframe: use uint8_t for return type of sframe_fre_get_base_reg_id","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230623044448.2617101-10-indu.bhagat@oracle.com/mbox/"},{"id":111918,"url":"https://patchwork.plctlab.org/api/1.2/patches/111918/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230623044448.2617101-11-indu.bhagat@oracle.com/","msgid":"<20230623044448.2617101-11-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-06-23T04:44:48","name":"[10/10] binutils/NEWS: add note about upcoming libsframe changes","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230623044448.2617101-11-indu.bhagat@oracle.com/mbox/"},{"id":112090,"url":"https://patchwork.plctlab.org/api/1.2/patches/112090/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZJWCzBxYkM7kIEJT@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-06-23T11:32:28","name":"lto test fails with -fno-inline in CFLAGS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZJWCzBxYkM7kIEJT@squeak.grove.modra.org/mbox/"},{"id":112092,"url":"https://patchwork.plctlab.org/api/1.2/patches/112092/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZJWDWhpXisjeWfPg@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-06-23T11:34:50","name":"[GOLD] powerpc DT_RELACOUNT","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZJWDWhpXisjeWfPg@squeak.grove.modra.org/mbox/"},{"id":112093,"url":"https://patchwork.plctlab.org/api/1.2/patches/112093/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZJWEWYg0ZOpwoMSq@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-06-23T11:39:05","name":"[GOLD] Support setting DT_RELACOUNT late","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZJWEWYg0ZOpwoMSq@squeak.grove.modra.org/mbox/"},{"id":112094,"url":"https://patchwork.plctlab.org/api/1.2/patches/112094/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZJWEtp7jDRVNckRK@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-06-23T11:40:38","name":"[GOLD] PowerPC64 huge branch dynamic relocs","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZJWEtp7jDRVNckRK@squeak.grove.modra.org/mbox/"},{"id":112524,"url":"https://patchwork.plctlab.org/api/1.2/patches/112524/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230625083850.1028642-2-mengqinggang@loongson.cn/","msgid":"<20230625083850.1028642-2-mengqinggang@loongson.cn>","list_archive_url":null,"date":"2023-06-25T08:38:49","name":"[v0,1/2] LoongArch: gas: Add LSX and LASX instructions support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230625083850.1028642-2-mengqinggang@loongson.cn/mbox/"},{"id":112523,"url":"https://patchwork.plctlab.org/api/1.2/patches/112523/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230625083850.1028642-3-mengqinggang@loongson.cn/","msgid":"<20230625083850.1028642-3-mengqinggang@loongson.cn>","list_archive_url":null,"date":"2023-06-25T08:38:50","name":"[v0,2/2] LoongArch: gas: Add LSX and LASX instructions test","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230625083850.1028642-3-mengqinggang@loongson.cn/mbox/"},{"id":112533,"url":"https://patchwork.plctlab.org/api/1.2/patches/112533/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230625095540.1202120-1-mengqinggang@loongson.cn/","msgid":"<20230625095540.1202120-1-mengqinggang@loongson.cn>","list_archive_url":null,"date":"2023-06-25T09:55:40","name":"LoongArch: Add R_LARCH_64_PCREL relocation support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230625095540.1202120-1-mengqinggang@loongson.cn/mbox/"},{"id":112807,"url":"https://patchwork.plctlab.org/api/1.2/patches/112807/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230626091656.31782-1-krebbel@linux.ibm.com/","msgid":"<20230626091656.31782-1-krebbel@linux.ibm.com>","list_archive_url":null,"date":"2023-06-26T09:16:56","name":"ld - Add SYMBOL_ABI_ALIGNMENT variable and apply to __bss_start","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230626091656.31782-1-krebbel@linux.ibm.com/mbox/"},{"id":112947,"url":"https://patchwork.plctlab.org/api/1.2/patches/112947/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/87sfaez7ut.fsf@redhat.com/","msgid":"<87sfaez7ut.fsf@redhat.com>","list_archive_url":null,"date":"2023-06-26T13:11:22","name":"Commit: Sync config.sub and config.guess","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/87sfaez7ut.fsf@redhat.com/mbox/"},{"id":112954,"url":"https://patchwork.plctlab.org/api/1.2/patches/112954/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/bf42815b-bc8c-dc64-9393-43cdbb6fbb76@e124511.cambridge.arm.com/","msgid":"","list_archive_url":null,"date":"2023-06-26T13:50:57","name":"aarch64: Remove version dependencies from features","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/bf42815b-bc8c-dc64-9393-43cdbb6fbb76@e124511.cambridge.arm.com/mbox/"},{"id":112991,"url":"https://patchwork.plctlab.org/api/1.2/patches/112991/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/87pm5iz3fu.fsf@redhat.com/","msgid":"<87pm5iz3fu.fsf@redhat.com>","list_archive_url":null,"date":"2023-06-26T14:46:45","name":"Commit: Update libiberty sources","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/87pm5iz3fu.fsf@redhat.com/mbox/"},{"id":113014,"url":"https://patchwork.plctlab.org/api/1.2/patches/113014/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.LSU.2.20.2306261532320.13548@wotan.suse.de/","msgid":"","list_archive_url":null,"date":"2023-06-26T15:35:09","name":"section-match: Check parent archive name as well","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.LSU.2.20.2306261532320.13548@wotan.suse.de/mbox/"},{"id":113046,"url":"https://patchwork.plctlab.org/api/1.2/patches/113046/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/87mt0myyc2.fsf@redhat.com/","msgid":"<87mt0myyc2.fsf@redhat.com>","list_archive_url":null,"date":"2023-06-26T16:37:01","name":"Commit: Fix gas testsuite failures for non-ELF AArch64 toolchains","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/87mt0myyc2.fsf@redhat.com/mbox/"},{"id":113129,"url":"https://patchwork.plctlab.org/api/1.2/patches/113129/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230626214619.1808676-1-vladimir.mezentsev@oracle.com/","msgid":"<20230626214619.1808676-1-vladimir.mezentsev@oracle.com>","list_archive_url":null,"date":"2023-06-26T21:46:19","name":"gprofng: Add new tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230626214619.1808676-1-vladimir.mezentsev@oracle.com/mbox/"},{"id":113414,"url":"https://patchwork.plctlab.org/api/1.2/patches/113414/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230627124728.3563-1-lidie@eswincomputing.com/","msgid":"<20230627124728.3563-1-lidie@eswincomputing.com>","list_archive_url":null,"date":"2023-06-27T12:47:28","name":"[RISC-V] Optimize GP-relative addressing for linker.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230627124728.3563-1-lidie@eswincomputing.com/mbox/"},{"id":113448,"url":"https://patchwork.plctlab.org/api/1.2/patches/113448/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230627144250.16818-1-palmer@rivosinc.com/","msgid":"<20230627144250.16818-1-palmer@rivosinc.com>","list_archive_url":null,"date":"2023-06-27T14:42:50","name":"gas: NEWS: Add the latest RISC-V extensions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230627144250.16818-1-palmer@rivosinc.com/mbox/"},{"id":113562,"url":"https://patchwork.plctlab.org/api/1.2/patches/113562/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230627195126.1955051-1-indu.bhagat@oracle.com/","msgid":"<20230627195126.1955051-1-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-06-27T19:51:15","name":"[COMMITTED] libsframe: add library versioning","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230627195126.1955051-1-indu.bhagat@oracle.com/mbox/"},{"id":113563,"url":"https://patchwork.plctlab.org/api/1.2/patches/113563/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230627195126.1955051-2-indu.bhagat@oracle.com/","msgid":"<20230627195126.1955051-2-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-06-27T19:51:16","name":"[COMMITTED] libsframe: remove sframe_get_funcdesc_with_addr API","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230627195126.1955051-2-indu.bhagat@oracle.com/mbox/"},{"id":113574,"url":"https://patchwork.plctlab.org/api/1.2/patches/113574/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230627195126.1955051-3-indu.bhagat@oracle.com/","msgid":"<20230627195126.1955051-3-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-06-27T19:51:17","name":"[COMMITTED] libsframe: add symbol versioning","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230627195126.1955051-3-indu.bhagat@oracle.com/mbox/"},{"id":113569,"url":"https://patchwork.plctlab.org/api/1.2/patches/113569/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230627195126.1955051-4-indu.bhagat@oracle.com/","msgid":"<20230627195126.1955051-4-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-06-27T19:51:18","name":"[COMMITTED] libsframe: update the semantics of sframe_fre_get_ra_offset","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230627195126.1955051-4-indu.bhagat@oracle.com/mbox/"},{"id":113572,"url":"https://patchwork.plctlab.org/api/1.2/patches/113572/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230627195126.1955051-5-indu.bhagat@oracle.com/","msgid":"<20230627195126.1955051-5-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-06-27T19:51:19","name":"[COMMITTED] libsframe: update the semantics of sframe_fre_get_fp_offset","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230627195126.1955051-5-indu.bhagat@oracle.com/mbox/"},{"id":113570,"url":"https://patchwork.plctlab.org/api/1.2/patches/113570/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230627195126.1955051-6-indu.bhagat@oracle.com/","msgid":"<20230627195126.1955051-6-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-06-27T19:51:20","name":"[COMMITTED] libsframe: use uint32_t for fre_type and fde_type function args","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230627195126.1955051-6-indu.bhagat@oracle.com/mbox/"},{"id":113577,"url":"https://patchwork.plctlab.org/api/1.2/patches/113577/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230627195126.1955051-7-indu.bhagat@oracle.com/","msgid":"<20230627195126.1955051-7-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-06-27T19:51:21","name":"[COMMITTED] libsframe: bfd: use uint32_t for return type of sframe_calc_fre_type","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230627195126.1955051-7-indu.bhagat@oracle.com/mbox/"},{"id":113573,"url":"https://patchwork.plctlab.org/api/1.2/patches/113573/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230627195126.1955051-8-indu.bhagat@oracle.com/","msgid":"<20230627195126.1955051-8-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-06-27T19:51:22","name":"[COMMITTED] libsframe: use uint8_t instead of unsigned char for abi_arch","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230627195126.1955051-8-indu.bhagat@oracle.com/mbox/"},{"id":113564,"url":"https://patchwork.plctlab.org/api/1.2/patches/113564/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230627195126.1955051-9-indu.bhagat@oracle.com/","msgid":"<20230627195126.1955051-9-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-06-27T19:51:23","name":"[COMMITTED] libsframe: use uint8_t for return type of sframe_fre_get_base_reg_id","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230627195126.1955051-9-indu.bhagat@oracle.com/mbox/"},{"id":113565,"url":"https://patchwork.plctlab.org/api/1.2/patches/113565/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230627195126.1955051-10-indu.bhagat@oracle.com/","msgid":"<20230627195126.1955051-10-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-06-27T19:51:24","name":"[COMMITTED] libsframe: use appropriate data types for args of sframe_encode","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230627195126.1955051-10-indu.bhagat@oracle.com/mbox/"},{"id":113576,"url":"https://patchwork.plctlab.org/api/1.2/patches/113576/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230627195126.1955051-11-indu.bhagat@oracle.com/","msgid":"<20230627195126.1955051-11-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-06-27T19:51:25","name":"[COMMITTED] libsframe: bfd: use uint32_t for return type of get_num_fidx APIs","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230627195126.1955051-11-indu.bhagat@oracle.com/mbox/"},{"id":113578,"url":"https://patchwork.plctlab.org/api/1.2/patches/113578/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230627195126.1955051-12-indu.bhagat@oracle.com/","msgid":"<20230627195126.1955051-12-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-06-27T19:51:26","name":"[COMMITTED] binutils/NEWS: add note about upcoming libsframe changes","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230627195126.1955051-12-indu.bhagat@oracle.com/mbox/"},{"id":113614,"url":"https://patchwork.plctlab.org/api/1.2/patches/113614/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230627212028.2138604-2-indu.bhagat@oracle.com/","msgid":"<20230627212028.2138604-2-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-06-27T21:20:17","name":"[01/12] sframe.h: format bump to SFrame version 2","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230627212028.2138604-2-indu.bhagat@oracle.com/mbox/"},{"id":113611,"url":"https://patchwork.plctlab.org/api/1.2/patches/113611/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230627212028.2138604-3-indu.bhagat@oracle.com/","msgid":"<20230627212028.2138604-3-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-06-27T21:20:18","name":"[02/12] gas: generate SFrame section with version SFRAME_VERSION_2","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230627212028.2138604-3-indu.bhagat@oracle.com/mbox/"},{"id":113615,"url":"https://patchwork.plctlab.org/api/1.2/patches/113615/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230627212028.2138604-4-indu.bhagat@oracle.com/","msgid":"<20230627212028.2138604-4-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-06-27T21:20:19","name":"[03/12] libsframe: add new APIs to get SFrame version","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230627212028.2138604-4-indu.bhagat@oracle.com/mbox/"},{"id":113612,"url":"https://patchwork.plctlab.org/api/1.2/patches/113612/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230627212028.2138604-5-indu.bhagat@oracle.com/","msgid":"<20230627212028.2138604-5-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-06-27T21:20:20","name":"[04/12] libsframe: add new APIs to add and get SFrame FDE in SFrame version 2","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230627212028.2138604-5-indu.bhagat@oracle.com/mbox/"},{"id":113618,"url":"https://patchwork.plctlab.org/api/1.2/patches/113618/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230627212028.2138604-6-indu.bhagat@oracle.com/","msgid":"<20230627212028.2138604-6-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-06-27T21:20:21","name":"[05/12] libsframe: adjust version check in sframe_header_sanity_check_p","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230627212028.2138604-6-indu.bhagat@oracle.com/mbox/"},{"id":113616,"url":"https://patchwork.plctlab.org/api/1.2/patches/113616/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230627212028.2138604-7-indu.bhagat@oracle.com/","msgid":"<20230627212028.2138604-7-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-06-27T21:20:22","name":"[06/12] libsframe: testsuite: fixes for SFRAME_VERSION_2","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230627212028.2138604-7-indu.bhagat@oracle.com/mbox/"},{"id":113619,"url":"https://patchwork.plctlab.org/api/1.2/patches/113619/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230627212028.2138604-8-indu.bhagat@oracle.com/","msgid":"<20230627212028.2138604-8-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-06-27T21:20:23","name":"[07/12] bfd: linker: add support for rep_block_size for pltN entries","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230627212028.2138604-8-indu.bhagat@oracle.com/mbox/"},{"id":113622,"url":"https://patchwork.plctlab.org/api/1.2/patches/113622/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230627212028.2138604-9-indu.bhagat@oracle.com/","msgid":"<20230627212028.2138604-9-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-06-27T21:20:24","name":"[08/12] bfd: linker: generate SFrame sections with version SFRAME_VERSION_2","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230627212028.2138604-9-indu.bhagat@oracle.com/mbox/"},{"id":113613,"url":"https://patchwork.plctlab.org/api/1.2/patches/113613/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230627212028.2138604-10-indu.bhagat@oracle.com/","msgid":"<20230627212028.2138604-10-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-06-27T21:20:25","name":"[09/12] objdump/readelf: adjust for SFRAME_VERSION_2","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230627212028.2138604-10-indu.bhagat@oracle.com/mbox/"},{"id":113617,"url":"https://patchwork.plctlab.org/api/1.2/patches/113617/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230627212028.2138604-11-indu.bhagat@oracle.com/","msgid":"<20230627212028.2138604-11-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-06-27T21:20:26","name":"[10/12] doc: sframe: update specification for SFRAME_VERSION_2","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230627212028.2138604-11-indu.bhagat@oracle.com/mbox/"},{"id":113620,"url":"https://patchwork.plctlab.org/api/1.2/patches/113620/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230627212028.2138604-12-indu.bhagat@oracle.com/","msgid":"<20230627212028.2138604-12-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-06-27T21:20:27","name":"[11/12] doc: sframe: add details about alignment in the SFrame format","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230627212028.2138604-12-indu.bhagat@oracle.com/mbox/"},{"id":113621,"url":"https://patchwork.plctlab.org/api/1.2/patches/113621/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230627212028.2138604-13-indu.bhagat@oracle.com/","msgid":"<20230627212028.2138604-13-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-06-27T21:20:28","name":"[12/12] binutils/NEWS: announce SFrame version 2 as the new default","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230627212028.2138604-13-indu.bhagat@oracle.com/mbox/"},{"id":113643,"url":"https://patchwork.plctlab.org/api/1.2/patches/113643/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230628010634.1147958-1-maskray@google.com/","msgid":"<20230628010634.1147958-1-maskray@google.com>","list_archive_url":null,"date":"2023-06-28T01:06:34","name":"PR30592 objcopy: allow --set-section-flags to add or remove SHF_X86_64_LARGE","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230628010634.1147958-1-maskray@google.com/mbox/"},{"id":113816,"url":"https://patchwork.plctlab.org/api/1.2/patches/113816/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230628115103.3440262-2-i.swmail@xen0n.name/","msgid":"<20230628115103.3440262-2-i.swmail@xen0n.name>","list_archive_url":null,"date":"2023-06-28T11:50:58","name":"[v5,1/6] LoongArch: support disassembling certain pseudo-instructions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230628115103.3440262-2-i.swmail@xen0n.name/mbox/"},{"id":113815,"url":"https://patchwork.plctlab.org/api/1.2/patches/113815/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230628115103.3440262-3-i.swmail@xen0n.name/","msgid":"<20230628115103.3440262-3-i.swmail@xen0n.name>","list_archive_url":null,"date":"2023-06-28T11:50:59","name":"[v5,2/6] opcodes/loongarch: remove unused code","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230628115103.3440262-3-i.swmail@xen0n.name/mbox/"},{"id":113817,"url":"https://patchwork.plctlab.org/api/1.2/patches/113817/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230628115103.3440262-4-i.swmail@xen0n.name/","msgid":"<20230628115103.3440262-4-i.swmail@xen0n.name>","list_archive_url":null,"date":"2023-06-28T11:51:00","name":"[v5,3/6] opcodes/loongarch: implement style support in the disassembler","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230628115103.3440262-4-i.swmail@xen0n.name/mbox/"},{"id":113818,"url":"https://patchwork.plctlab.org/api/1.2/patches/113818/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230628115103.3440262-5-i.swmail@xen0n.name/","msgid":"<20230628115103.3440262-5-i.swmail@xen0n.name>","list_archive_url":null,"date":"2023-06-28T11:51:01","name":"[v5,4/6] opcodes/loongarch: style disassembled address offsets as such","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230628115103.3440262-5-i.swmail@xen0n.name/mbox/"},{"id":113820,"url":"https://patchwork.plctlab.org/api/1.2/patches/113820/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230628115103.3440262-6-i.swmail@xen0n.name/","msgid":"<20230628115103.3440262-6-i.swmail@xen0n.name>","list_archive_url":null,"date":"2023-06-28T11:51:02","name":"[v5,5/6] opcodes/loongarch: do not print hex notation for signed immediates","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230628115103.3440262-6-i.swmail@xen0n.name/mbox/"},{"id":113821,"url":"https://patchwork.plctlab.org/api/1.2/patches/113821/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230628115103.3440262-7-i.swmail@xen0n.name/","msgid":"<20230628115103.3440262-7-i.swmail@xen0n.name>","list_archive_url":null,"date":"2023-06-28T11:51:03","name":"[v5,6/6] opcodes/loongarch: print unrecognized insn words with the .word directive","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230628115103.3440262-7-i.swmail@xen0n.name/mbox/"},{"id":113857,"url":"https://patchwork.plctlab.org/api/1.2/patches/113857/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230628131311.3895731-1-i.swmail@xen0n.name/","msgid":"<20230628131311.3895731-1-i.swmail@xen0n.name>","list_archive_url":null,"date":"2023-06-28T13:13:11","name":"[v2] LoongArch: Deprecate $v[01], $fv[01] and $x names per spec","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230628131311.3895731-1-i.swmail@xen0n.name/mbox/"},{"id":114109,"url":"https://patchwork.plctlab.org/api/1.2/patches/114109/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230628231610.220112-1-maskray@google.com/","msgid":"<20230628231610.220112-1-maskray@google.com>","list_archive_url":null,"date":"2023-06-28T23:16:10","name":"[v2] PR30592 objcopy: allow --set-section-flags to add or remove SHF_X86_64_LARGE","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230628231610.220112-1-maskray@google.com/mbox/"},{"id":114173,"url":"https://patchwork.plctlab.org/api/1.2/patches/114173/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629061029.29773-2-i.swmail@xen0n.name/","msgid":"<20230629061029.29773-2-i.swmail@xen0n.name>","list_archive_url":null,"date":"2023-06-29T06:10:23","name":"[v6,1/7] LoongArch: support disassembling certain pseudo-instructions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629061029.29773-2-i.swmail@xen0n.name/mbox/"},{"id":114170,"url":"https://patchwork.plctlab.org/api/1.2/patches/114170/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629061029.29773-3-i.swmail@xen0n.name/","msgid":"<20230629061029.29773-3-i.swmail@xen0n.name>","list_archive_url":null,"date":"2023-06-29T06:10:24","name":"[v6,2/7] opcodes/loongarch: remove unused code","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629061029.29773-3-i.swmail@xen0n.name/mbox/"},{"id":114175,"url":"https://patchwork.plctlab.org/api/1.2/patches/114175/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629061029.29773-4-i.swmail@xen0n.name/","msgid":"<20230629061029.29773-4-i.swmail@xen0n.name>","list_archive_url":null,"date":"2023-06-29T06:10:25","name":"[v6,3/7] opcodes/loongarch: implement style support in the disassembler","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629061029.29773-4-i.swmail@xen0n.name/mbox/"},{"id":114171,"url":"https://patchwork.plctlab.org/api/1.2/patches/114171/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629061029.29773-5-i.swmail@xen0n.name/","msgid":"<20230629061029.29773-5-i.swmail@xen0n.name>","list_archive_url":null,"date":"2023-06-29T06:10:26","name":"[v6,4/7] opcodes/loongarch: style disassembled address offsets as such","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629061029.29773-5-i.swmail@xen0n.name/mbox/"},{"id":114172,"url":"https://patchwork.plctlab.org/api/1.2/patches/114172/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629061029.29773-6-i.swmail@xen0n.name/","msgid":"<20230629061029.29773-6-i.swmail@xen0n.name>","list_archive_url":null,"date":"2023-06-29T06:10:27","name":"[v6,5/7] opcodes/loongarch: do not print hex notation for signed immediates","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629061029.29773-6-i.swmail@xen0n.name/mbox/"},{"id":114176,"url":"https://patchwork.plctlab.org/api/1.2/patches/114176/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629061029.29773-7-i.swmail@xen0n.name/","msgid":"<20230629061029.29773-7-i.swmail@xen0n.name>","list_archive_url":null,"date":"2023-06-29T06:10:28","name":"[v6,6/7] opcodes/loongarch: print unrecognized insn words with the .word directive","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629061029.29773-7-i.swmail@xen0n.name/mbox/"},{"id":114174,"url":"https://patchwork.plctlab.org/api/1.2/patches/114174/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629061029.29773-8-i.swmail@xen0n.name/","msgid":"<20230629061029.29773-8-i.swmail@xen0n.name>","list_archive_url":null,"date":"2023-06-29T06:10:29","name":"[v6,7/7] LoongArch: Deprecate $v[01], $fv[01] and $x names per spec","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629061029.29773-8-i.swmail@xen0n.name/mbox/"},{"id":114246,"url":"https://patchwork.plctlab.org/api/1.2/patches/114246/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629090831.2579210-1-mengqinggang@loongson.cn/","msgid":"<20230629090831.2579210-1-mengqinggang@loongson.cn>","list_archive_url":null,"date":"2023-06-29T09:08:31","name":"LoongArch: gas: Add LVZ and LBT instructions support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629090831.2579210-1-mengqinggang@loongson.cn/mbox/"},{"id":114357,"url":"https://patchwork.plctlab.org/api/1.2/patches/114357/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629163504.1331025-2-i.swmail@xen0n.name/","msgid":"<20230629163504.1331025-2-i.swmail@xen0n.name>","list_archive_url":null,"date":"2023-06-29T16:34:58","name":"[v7,1/7] LoongArch: support disassembling certain pseudo-instructions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629163504.1331025-2-i.swmail@xen0n.name/mbox/"},{"id":114359,"url":"https://patchwork.plctlab.org/api/1.2/patches/114359/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629163504.1331025-3-i.swmail@xen0n.name/","msgid":"<20230629163504.1331025-3-i.swmail@xen0n.name>","list_archive_url":null,"date":"2023-06-29T16:34:59","name":"[v7,2/7] opcodes/loongarch: remove unused code","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629163504.1331025-3-i.swmail@xen0n.name/mbox/"},{"id":114356,"url":"https://patchwork.plctlab.org/api/1.2/patches/114356/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629163504.1331025-4-i.swmail@xen0n.name/","msgid":"<20230629163504.1331025-4-i.swmail@xen0n.name>","list_archive_url":null,"date":"2023-06-29T16:35:00","name":"[v7,3/7] opcodes/loongarch: implement style support in the disassembler","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629163504.1331025-4-i.swmail@xen0n.name/mbox/"},{"id":114363,"url":"https://patchwork.plctlab.org/api/1.2/patches/114363/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629163504.1331025-5-i.swmail@xen0n.name/","msgid":"<20230629163504.1331025-5-i.swmail@xen0n.name>","list_archive_url":null,"date":"2023-06-29T16:35:01","name":"[v7,4/7] opcodes/loongarch: style disassembled address offsets as such","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629163504.1331025-5-i.swmail@xen0n.name/mbox/"},{"id":114362,"url":"https://patchwork.plctlab.org/api/1.2/patches/114362/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629163504.1331025-6-i.swmail@xen0n.name/","msgid":"<20230629163504.1331025-6-i.swmail@xen0n.name>","list_archive_url":null,"date":"2023-06-29T16:35:02","name":"[v7,5/7] opcodes/loongarch: do not print hex notation for signed immediates","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629163504.1331025-6-i.swmail@xen0n.name/mbox/"},{"id":114360,"url":"https://patchwork.plctlab.org/api/1.2/patches/114360/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629163504.1331025-7-i.swmail@xen0n.name/","msgid":"<20230629163504.1331025-7-i.swmail@xen0n.name>","list_archive_url":null,"date":"2023-06-29T16:35:03","name":"[v7,6/7] opcodes/loongarch: print unrecognized insn words with the .word directive","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629163504.1331025-7-i.swmail@xen0n.name/mbox/"},{"id":114364,"url":"https://patchwork.plctlab.org/api/1.2/patches/114364/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629163504.1331025-8-i.swmail@xen0n.name/","msgid":"<20230629163504.1331025-8-i.swmail@xen0n.name>","list_archive_url":null,"date":"2023-06-29T16:35:04","name":"[v7,7/7] LoongArch: Deprecate $v[01], $fv[01] and $x names per spec","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629163504.1331025-8-i.swmail@xen0n.name/mbox/"},{"id":114368,"url":"https://patchwork.plctlab.org/api/1.2/patches/114368/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629171839.573187-2-nhuck@google.com/","msgid":"<20230629171839.573187-2-nhuck@google.com>","list_archive_url":null,"date":"2023-06-29T17:18:26","name":"[01/14] Add support for the Zvbb ISA extension.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629171839.573187-2-nhuck@google.com/mbox/"},{"id":114371,"url":"https://patchwork.plctlab.org/api/1.2/patches/114371/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629171839.573187-3-nhuck@google.com/","msgid":"<20230629171839.573187-3-nhuck@google.com>","list_archive_url":null,"date":"2023-06-29T17:18:27","name":"[02/14] Add support for the Zvbc ISA extension.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629171839.573187-3-nhuck@google.com/mbox/"},{"id":114374,"url":"https://patchwork.plctlab.org/api/1.2/patches/114374/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629171839.573187-4-nhuck@google.com/","msgid":"<20230629171839.573187-4-nhuck@google.com>","list_archive_url":null,"date":"2023-06-29T17:18:28","name":"[03/14] Add support for the Zvkg ISA extension.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629171839.573187-4-nhuck@google.com/mbox/"},{"id":114369,"url":"https://patchwork.plctlab.org/api/1.2/patches/114369/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629171839.573187-5-nhuck@google.com/","msgid":"<20230629171839.573187-5-nhuck@google.com>","list_archive_url":null,"date":"2023-06-29T17:18:29","name":"[04/14] Add support for the Zvkned ISA extension.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629171839.573187-5-nhuck@google.com/mbox/"},{"id":114373,"url":"https://patchwork.plctlab.org/api/1.2/patches/114373/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629171839.573187-6-nhuck@google.com/","msgid":"<20230629171839.573187-6-nhuck@google.com>","list_archive_url":null,"date":"2023-06-29T17:18:30","name":"[05/14] Add support for the Zvknh[a,b] ISA extensions.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629171839.573187-6-nhuck@google.com/mbox/"},{"id":114376,"url":"https://patchwork.plctlab.org/api/1.2/patches/114376/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629171839.573187-7-nhuck@google.com/","msgid":"<20230629171839.573187-7-nhuck@google.com>","list_archive_url":null,"date":"2023-06-29T17:18:31","name":"[06/14] Add support for the Zvksed ISA extension.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629171839.573187-7-nhuck@google.com/mbox/"},{"id":114370,"url":"https://patchwork.plctlab.org/api/1.2/patches/114370/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629171839.573187-8-nhuck@google.com/","msgid":"<20230629171839.573187-8-nhuck@google.com>","list_archive_url":null,"date":"2023-06-29T17:18:32","name":"[07/14] Adds support for the Zvksh ISA extension.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629171839.573187-8-nhuck@google.com/mbox/"},{"id":114377,"url":"https://patchwork.plctlab.org/api/1.2/patches/114377/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629171839.573187-9-nhuck@google.com/","msgid":"<20230629171839.573187-9-nhuck@google.com>","list_archive_url":null,"date":"2023-06-29T17:18:33","name":"[08/14] Add support for the Zvkn ISA extension.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629171839.573187-9-nhuck@google.com/mbox/"},{"id":114381,"url":"https://patchwork.plctlab.org/api/1.2/patches/114381/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629171839.573187-10-nhuck@google.com/","msgid":"<20230629171839.573187-10-nhuck@google.com>","list_archive_url":null,"date":"2023-06-29T17:18:34","name":"[09/14] Allow nested implications for extensions.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629171839.573187-10-nhuck@google.com/mbox/"},{"id":114382,"url":"https://patchwork.plctlab.org/api/1.2/patches/114382/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629171839.573187-11-nhuck@google.com/","msgid":"<20230629171839.573187-11-nhuck@google.com>","list_archive_url":null,"date":"2023-06-29T17:18:35","name":"[10/14] Add support for the Zvkng ISA extension.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629171839.573187-11-nhuck@google.com/mbox/"},{"id":114372,"url":"https://patchwork.plctlab.org/api/1.2/patches/114372/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629171839.573187-12-nhuck@google.com/","msgid":"<20230629171839.573187-12-nhuck@google.com>","list_archive_url":null,"date":"2023-06-29T17:18:36","name":"[11/14] Add support for the Zvks ISA extension.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629171839.573187-12-nhuck@google.com/mbox/"},{"id":114375,"url":"https://patchwork.plctlab.org/api/1.2/patches/114375/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629171839.573187-13-nhuck@google.com/","msgid":"<20230629171839.573187-13-nhuck@google.com>","list_archive_url":null,"date":"2023-06-29T17:18:37","name":"[12/14] Add support for the Zvksg ISA extension.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629171839.573187-13-nhuck@google.com/mbox/"},{"id":114378,"url":"https://patchwork.plctlab.org/api/1.2/patches/114378/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629171839.573187-14-nhuck@google.com/","msgid":"<20230629171839.573187-14-nhuck@google.com>","list_archive_url":null,"date":"2023-06-29T17:18:38","name":"[13/14] Add support for the Zvknc ISA extension.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629171839.573187-14-nhuck@google.com/mbox/"},{"id":114383,"url":"https://patchwork.plctlab.org/api/1.2/patches/114383/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629171839.573187-15-nhuck@google.com/","msgid":"<20230629171839.573187-15-nhuck@google.com>","list_archive_url":null,"date":"2023-06-29T17:18:39","name":"[14/14] Add support for the Zvksc ISA extension.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629171839.573187-15-nhuck@google.com/mbox/"},{"id":114391,"url":"https://patchwork.plctlab.org/api/1.2/patches/114391/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629182618.2351051-1-indu.bhagat@oracle.com/","msgid":"<20230629182618.2351051-1-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-06-29T18:26:18","name":"[COMMITTED] libsframe: fix sframe_find_fre for pltN entries","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629182618.2351051-1-indu.bhagat@oracle.com/mbox/"},{"id":114494,"url":"https://patchwork.plctlab.org/api/1.2/patches/114494/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629235326.1167898-1-indu.bhagat@oracle.com/","msgid":"<20230629235326.1167898-1-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-06-29T23:53:23","name":"[COMMITTED] libsframe: add new APIs to get SFrame version","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629235326.1167898-1-indu.bhagat@oracle.com/mbox/"},{"id":114496,"url":"https://patchwork.plctlab.org/api/1.2/patches/114496/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629235326.1167898-2-indu.bhagat@oracle.com/","msgid":"<20230629235326.1167898-2-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-06-29T23:53:24","name":"[COMMITTED] sframe: bfd: gas: ld: format bump to SFrame version 2","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629235326.1167898-2-indu.bhagat@oracle.com/mbox/"},{"id":114492,"url":"https://patchwork.plctlab.org/api/1.2/patches/114492/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629235326.1167898-3-indu.bhagat@oracle.com/","msgid":"<20230629235326.1167898-3-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-06-29T23:53:25","name":"[COMMITTED] doc: sframe: update specification for SFRAME_VERSION_2","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629235326.1167898-3-indu.bhagat@oracle.com/mbox/"},{"id":114491,"url":"https://patchwork.plctlab.org/api/1.2/patches/114491/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629235326.1167898-4-indu.bhagat@oracle.com/","msgid":"<20230629235326.1167898-4-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2023-06-29T23:53:26","name":"[COMMITTED] binutils/NEWS: announce SFrame version 2 as the new default","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230629235326.1167898-4-indu.bhagat@oracle.com/mbox/"},{"id":114538,"url":"https://patchwork.plctlab.org/api/1.2/patches/114538/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230630025308.3258293-1-vladimir.mezentsev@oracle.com/","msgid":"<20230630025308.3258293-1-vladimir.mezentsev@oracle.com>","list_archive_url":null,"date":"2023-06-30T02:53:08","name":"gprofng: fix data race","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230630025308.3258293-1-vladimir.mezentsev@oracle.com/mbox/"},{"id":114543,"url":"https://patchwork.plctlab.org/api/1.2/patches/114543/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230630033443.2359278-2-mengqinggang@loongson.cn/","msgid":"<20230630033443.2359278-2-mengqinggang@loongson.cn>","list_archive_url":null,"date":"2023-06-30T03:34:42","name":"[v1,1/2] LoongArch: gas: Add LVZ and LBT instructions support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230630033443.2359278-2-mengqinggang@loongson.cn/mbox/"},{"id":114544,"url":"https://patchwork.plctlab.org/api/1.2/patches/114544/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230630033443.2359278-3-mengqinggang@loongson.cn/","msgid":"<20230630033443.2359278-3-mengqinggang@loongson.cn>","list_archive_url":null,"date":"2023-06-30T03:34:43","name":"[v1,2/2] LoongArch: gas: Fix code style issues","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230630033443.2359278-3-mengqinggang@loongson.cn/mbox/"},{"id":114557,"url":"https://patchwork.plctlab.org/api/1.2/patches/114557/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230630051451.1867944-1-yunqiang.su@cipunited.com/","msgid":"<20230630051451.1867944-1-yunqiang.su@cipunited.com>","list_archive_url":null,"date":"2023-06-30T05:14:51","name":"ld: Use [list ] syntax to define run_tests in indirect.exp","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230630051451.1867944-1-yunqiang.su@cipunited.com/mbox/"},{"id":114580,"url":"https://patchwork.plctlab.org/api/1.2/patches/114580/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230630060757.2006878-1-yunqiang.su@cipunited.com/","msgid":"<20230630060757.2006878-1-yunqiang.su@cipunited.com>","list_archive_url":null,"date":"2023-06-30T06:07:57","name":"ld: Use run_host_cmd_yesno in indirect.exp instead of catch exec","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230630060757.2006878-1-yunqiang.su@cipunited.com/mbox/"},{"id":114592,"url":"https://patchwork.plctlab.org/api/1.2/patches/114592/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230630064559.2282365-1-yunqiang.su@cipunited.com/","msgid":"<20230630064559.2282365-1-yunqiang.su@cipunited.com>","list_archive_url":null,"date":"2023-06-30T06:45:59","name":"MIPS: N64, mark .interp as INITIAL_READONLY_SECTIONS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230630064559.2282365-1-yunqiang.su@cipunited.com/mbox/"},{"id":114606,"url":"https://patchwork.plctlab.org/api/1.2/patches/114606/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/CAP2b4GMYH=czD31TwmNrqOjnRH1dOsPVo8Be9VN=_EiFQWitoQ@mail.gmail.com/","msgid":"","list_archive_url":null,"date":"2023-06-30T07:53:13","name":"Add the .seh_ifrepeat and .seh_ifnrepeat directives","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/CAP2b4GMYH=czD31TwmNrqOjnRH1dOsPVo8Be9VN=_EiFQWitoQ@mail.gmail.com/mbox/"},{"id":114625,"url":"https://patchwork.plctlab.org/api/1.2/patches/114625/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230630090416.3051425-2-mengqinggang@loongson.cn/","msgid":"<20230630090416.3051425-2-mengqinggang@loongson.cn>","list_archive_url":null,"date":"2023-06-30T09:04:15","name":"[v2,1/2] LoongArch: gas: Add LVZ and LBT instructions support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230630090416.3051425-2-mengqinggang@loongson.cn/mbox/"},{"id":114627,"url":"https://patchwork.plctlab.org/api/1.2/patches/114627/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230630090416.3051425-3-mengqinggang@loongson.cn/","msgid":"<20230630090416.3051425-3-mengqinggang@loongson.cn>","list_archive_url":null,"date":"2023-06-30T09:04:16","name":"[v2,2/2] LoongArch: gas: Fix code style issues","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230630090416.3051425-3-mengqinggang@loongson.cn/mbox/"},{"id":114639,"url":"https://patchwork.plctlab.org/api/1.2/patches/114639/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/878rc1707w.fsf@redhat.com/","msgid":"<878rc1707w.fsf@redhat.com>","list_archive_url":null,"date":"2023-06-30T09:45:07","name":"Commit: Fix used before initialised warnings from Clang 16","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/878rc1707w.fsf@redhat.com/mbox/"},{"id":114709,"url":"https://patchwork.plctlab.org/api/1.2/patches/114709/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230630123259.1900571-1-i.swmail@xen0n.name/","msgid":"<20230630123259.1900571-1-i.swmail@xen0n.name>","list_archive_url":null,"date":"2023-06-30T12:32:59","name":"opcodes/loongarch: Mark address offset operands of LVZ/LBT insns as such","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230630123259.1900571-1-i.swmail@xen0n.name/mbox/"},{"id":114726,"url":"https://patchwork.plctlab.org/api/1.2/patches/114726/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230630134436.1237733-1-luis.machado@arm.com/","msgid":"<20230630134436.1237733-1-luis.machado@arm.com>","list_archive_url":null,"date":"2023-06-30T13:44:36","name":"[aarch64] sme: Core file support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230630134436.1237733-1-luis.machado@arm.com/mbox/"},{"id":114727,"url":"https://patchwork.plctlab.org/api/1.2/patches/114727/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230630134519.1237879-1-luis.machado@arm.com/","msgid":"<20230630134519.1237879-1-luis.machado@arm.com>","list_archive_url":null,"date":"2023-06-30T13:45:19","name":"[aarch64] sme2: Teach binutils/BFD about the NT_ARM_ZT register set","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230630134519.1237879-1-luis.machado@arm.com/mbox/"}],"public":true,"mbox":"https://patchwork.plctlab.org/bundle/patchwork-bot/binutils-gdb_2023-06/mbox/"},{"id":26,"url":"https://patchwork.plctlab.org/api/1.2/bundles/26/","web_url":"https://patchwork.plctlab.org/bundle/patchwork-bot/binutils-gdb_2023-07/","project":{"id":2,"url":"https://patchwork.plctlab.org/api/1.2/projects/2/","name":"binutils-gdb","link_name":"binutils-gdb","list_id":"binutils.sourceware.org","list_email":"binutils@sourceware.org","web_url":"https://github.com/wangliu-iscas/Patchwork-Bundles/blob/main/binutils-gdb.md","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"name":"binutils-gdb_2023-07","owner":{"id":3,"url":"https://patchwork.plctlab.org/api/1.2/users/3/","username":"patchwork-bot","first_name":"","last_name":"","email":"ouuuleilei@gmail.com"},"patches":[{"id":114893,"url":"https://patchwork.plctlab.org/api/1.2/patches/114893/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230630215725.3725876-2-christoph.muellner@vrull.eu/","msgid":"<20230630215725.3725876-2-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2023-06-30T21:57:11","name":"[v5,01/15] RISC-V: Add support for the Zvbb ISA extension","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230630215725.3725876-2-christoph.muellner@vrull.eu/mbox/"},{"id":114888,"url":"https://patchwork.plctlab.org/api/1.2/patches/114888/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230630215725.3725876-3-christoph.muellner@vrull.eu/","msgid":"<20230630215725.3725876-3-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2023-06-30T21:57:12","name":"[v5,02/15] RISC-V: Add support for the Zvbc extension","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230630215725.3725876-3-christoph.muellner@vrull.eu/mbox/"},{"id":114896,"url":"https://patchwork.plctlab.org/api/1.2/patches/114896/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230630215725.3725876-4-christoph.muellner@vrull.eu/","msgid":"<20230630215725.3725876-4-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2023-06-30T21:57:13","name":"[v5,03/15] RISC-V: Add support for the Zvkg ISA extension","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230630215725.3725876-4-christoph.muellner@vrull.eu/mbox/"},{"id":114889,"url":"https://patchwork.plctlab.org/api/1.2/patches/114889/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230630215725.3725876-5-christoph.muellner@vrull.eu/","msgid":"<20230630215725.3725876-5-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2023-06-30T21:57:14","name":"[v5,04/15] RISC-V: Add support for the Zvkned ISA extension","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230630215725.3725876-5-christoph.muellner@vrull.eu/mbox/"},{"id":114890,"url":"https://patchwork.plctlab.org/api/1.2/patches/114890/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230630215725.3725876-6-christoph.muellner@vrull.eu/","msgid":"<20230630215725.3725876-6-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2023-06-30T21:57:15","name":"[v5,05/15] RISC-V: Add support for the Zvknh[a, b] ISA extensions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230630215725.3725876-6-christoph.muellner@vrull.eu/mbox/"},{"id":114899,"url":"https://patchwork.plctlab.org/api/1.2/patches/114899/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230630215725.3725876-7-christoph.muellner@vrull.eu/","msgid":"<20230630215725.3725876-7-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2023-06-30T21:57:16","name":"[v5,06/15] RISC-V: Add support for the Zvksed ISA extension","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230630215725.3725876-7-christoph.muellner@vrull.eu/mbox/"},{"id":114892,"url":"https://patchwork.plctlab.org/api/1.2/patches/114892/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230630215725.3725876-8-christoph.muellner@vrull.eu/","msgid":"<20230630215725.3725876-8-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2023-06-30T21:57:17","name":"[v5,07/15] RISC-V: Add support for the Zvksh ISA extension","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230630215725.3725876-8-christoph.muellner@vrull.eu/mbox/"},{"id":114895,"url":"https://patchwork.plctlab.org/api/1.2/patches/114895/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230630215725.3725876-9-christoph.muellner@vrull.eu/","msgid":"<20230630215725.3725876-9-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2023-06-30T21:57:18","name":"[v5,08/15] RISC-V: Add support for the Zvkn ISA extension","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230630215725.3725876-9-christoph.muellner@vrull.eu/mbox/"},{"id":114901,"url":"https://patchwork.plctlab.org/api/1.2/patches/114901/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230630215725.3725876-10-christoph.muellner@vrull.eu/","msgid":"<20230630215725.3725876-10-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2023-06-30T21:57:19","name":"[v5,09/15] RISC-V: Allow nested implications for extensions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230630215725.3725876-10-christoph.muellner@vrull.eu/mbox/"},{"id":114894,"url":"https://patchwork.plctlab.org/api/1.2/patches/114894/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230630215725.3725876-11-christoph.muellner@vrull.eu/","msgid":"<20230630215725.3725876-11-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2023-06-30T21:57:20","name":"[v5,10/15] RISC-V: Add support for the Zvkng ISA extension","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230630215725.3725876-11-christoph.muellner@vrull.eu/mbox/"},{"id":114897,"url":"https://patchwork.plctlab.org/api/1.2/patches/114897/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230630215725.3725876-12-christoph.muellner@vrull.eu/","msgid":"<20230630215725.3725876-12-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2023-06-30T21:57:21","name":"[v5,11/15] RISC-V: Add support for the Zvks ISA extension","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230630215725.3725876-12-christoph.muellner@vrull.eu/mbox/"},{"id":114903,"url":"https://patchwork.plctlab.org/api/1.2/patches/114903/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230630215725.3725876-13-christoph.muellner@vrull.eu/","msgid":"<20230630215725.3725876-13-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2023-06-30T21:57:22","name":"[v5,12/15] RISC-V: Add support for the Zvksg ISA extension","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230630215725.3725876-13-christoph.muellner@vrull.eu/mbox/"},{"id":114898,"url":"https://patchwork.plctlab.org/api/1.2/patches/114898/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230630215725.3725876-14-christoph.muellner@vrull.eu/","msgid":"<20230630215725.3725876-14-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2023-06-30T21:57:23","name":"[v5,13/15] RISC-V: Add support for the Zvknc ISA extension","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230630215725.3725876-14-christoph.muellner@vrull.eu/mbox/"},{"id":114900,"url":"https://patchwork.plctlab.org/api/1.2/patches/114900/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230630215725.3725876-15-christoph.muellner@vrull.eu/","msgid":"<20230630215725.3725876-15-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2023-06-30T21:57:24","name":"[v5,14/15] RISC-V: Add support for the Zvksc ISA extension","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230630215725.3725876-15-christoph.muellner@vrull.eu/mbox/"},{"id":114902,"url":"https://patchwork.plctlab.org/api/1.2/patches/114902/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230630215725.3725876-16-christoph.muellner@vrull.eu/","msgid":"<20230630215725.3725876-16-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2023-06-30T21:57:25","name":"[v5,15/15] binutils: NEWS: Announce new RISC-V vector crypto extensions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230630215725.3725876-16-christoph.muellner@vrull.eu/mbox/"},{"id":114949,"url":"https://patchwork.plctlab.org/api/1.2/patches/114949/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230701052104.4018352-2-christoph.muellner@vrull.eu/","msgid":"<20230701052104.4018352-2-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2023-07-01T05:20:50","name":"[v6,01/15] RISC-V: Add support for the Zvbb ISA extension","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230701052104.4018352-2-christoph.muellner@vrull.eu/mbox/"},{"id":114952,"url":"https://patchwork.plctlab.org/api/1.2/patches/114952/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230701052104.4018352-3-christoph.muellner@vrull.eu/","msgid":"<20230701052104.4018352-3-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2023-07-01T05:20:51","name":"[v6,02/15] RISC-V: Add support for the Zvbc extension","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230701052104.4018352-3-christoph.muellner@vrull.eu/mbox/"},{"id":114955,"url":"https://patchwork.plctlab.org/api/1.2/patches/114955/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230701052104.4018352-4-christoph.muellner@vrull.eu/","msgid":"<20230701052104.4018352-4-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2023-07-01T05:20:52","name":"[v6,03/15] RISC-V: Add support for the Zvkg ISA extension","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230701052104.4018352-4-christoph.muellner@vrull.eu/mbox/"},{"id":114958,"url":"https://patchwork.plctlab.org/api/1.2/patches/114958/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230701052104.4018352-5-christoph.muellner@vrull.eu/","msgid":"<20230701052104.4018352-5-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2023-07-01T05:20:53","name":"[v6,04/15] RISC-V: Add support for the Zvkned ISA extension","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230701052104.4018352-5-christoph.muellner@vrull.eu/mbox/"},{"id":114953,"url":"https://patchwork.plctlab.org/api/1.2/patches/114953/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230701052104.4018352-6-christoph.muellner@vrull.eu/","msgid":"<20230701052104.4018352-6-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2023-07-01T05:20:54","name":"[v6,05/15] RISC-V: Add support for the Zvknh[a, b] ISA extensions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230701052104.4018352-6-christoph.muellner@vrull.eu/mbox/"},{"id":114950,"url":"https://patchwork.plctlab.org/api/1.2/patches/114950/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230701052104.4018352-7-christoph.muellner@vrull.eu/","msgid":"<20230701052104.4018352-7-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2023-07-01T05:20:55","name":"[v6,06/15] RISC-V: Add support for the Zvksed ISA extension","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230701052104.4018352-7-christoph.muellner@vrull.eu/mbox/"},{"id":114956,"url":"https://patchwork.plctlab.org/api/1.2/patches/114956/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230701052104.4018352-8-christoph.muellner@vrull.eu/","msgid":"<20230701052104.4018352-8-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2023-07-01T05:20:56","name":"[v6,07/15] RISC-V: Add support for the Zvksh ISA extension","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230701052104.4018352-8-christoph.muellner@vrull.eu/mbox/"},{"id":114954,"url":"https://patchwork.plctlab.org/api/1.2/patches/114954/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230701052104.4018352-9-christoph.muellner@vrull.eu/","msgid":"<20230701052104.4018352-9-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2023-07-01T05:20:57","name":"[v6,08/15] RISC-V: Add support for the Zvkn ISA extension","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230701052104.4018352-9-christoph.muellner@vrull.eu/mbox/"},{"id":114960,"url":"https://patchwork.plctlab.org/api/1.2/patches/114960/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230701052104.4018352-10-christoph.muellner@vrull.eu/","msgid":"<20230701052104.4018352-10-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2023-07-01T05:20:58","name":"[v6,09/15] RISC-V: Allow nested implications for extensions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230701052104.4018352-10-christoph.muellner@vrull.eu/mbox/"},{"id":114951,"url":"https://patchwork.plctlab.org/api/1.2/patches/114951/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230701052104.4018352-11-christoph.muellner@vrull.eu/","msgid":"<20230701052104.4018352-11-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2023-07-01T05:20:59","name":"[v6,10/15] RISC-V: Add support for the Zvkng ISA extension","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230701052104.4018352-11-christoph.muellner@vrull.eu/mbox/"},{"id":114962,"url":"https://patchwork.plctlab.org/api/1.2/patches/114962/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230701052104.4018352-12-christoph.muellner@vrull.eu/","msgid":"<20230701052104.4018352-12-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2023-07-01T05:21:00","name":"[v6,11/15] RISC-V: Add support for the Zvks ISA extension","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230701052104.4018352-12-christoph.muellner@vrull.eu/mbox/"},{"id":114957,"url":"https://patchwork.plctlab.org/api/1.2/patches/114957/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230701052104.4018352-13-christoph.muellner@vrull.eu/","msgid":"<20230701052104.4018352-13-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2023-07-01T05:21:01","name":"[v6,12/15] RISC-V: Add support for the Zvksg ISA extension","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230701052104.4018352-13-christoph.muellner@vrull.eu/mbox/"},{"id":114963,"url":"https://patchwork.plctlab.org/api/1.2/patches/114963/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230701052104.4018352-14-christoph.muellner@vrull.eu/","msgid":"<20230701052104.4018352-14-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2023-07-01T05:21:02","name":"[v6,13/15] RISC-V: Add support for the Zvknc ISA extension","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230701052104.4018352-14-christoph.muellner@vrull.eu/mbox/"},{"id":114961,"url":"https://patchwork.plctlab.org/api/1.2/patches/114961/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230701052104.4018352-15-christoph.muellner@vrull.eu/","msgid":"<20230701052104.4018352-15-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2023-07-01T05:21:03","name":"[v6,14/15] RISC-V: Add support for the Zvksc ISA extension","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230701052104.4018352-15-christoph.muellner@vrull.eu/mbox/"},{"id":114964,"url":"https://patchwork.plctlab.org/api/1.2/patches/114964/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230701052104.4018352-16-christoph.muellner@vrull.eu/","msgid":"<20230701052104.4018352-16-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2023-07-01T05:21:04","name":"[v6,15/15] binutils: NEWS: Announce new RISC-V vector crypto extensions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230701052104.4018352-16-christoph.muellner@vrull.eu/mbox/"},{"id":115075,"url":"https://patchwork.plctlab.org/api/1.2/patches/115075/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230702101422.762791-1-i.swmail@xen0n.name/","msgid":"<20230702101422.762791-1-i.swmail@xen0n.name>","list_archive_url":null,"date":"2023-07-02T10:14:22","name":"LoongArch: gas: Fix shared builds","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230702101422.762791-1-i.swmail@xen0n.name/mbox/"},{"id":115076,"url":"https://patchwork.plctlab.org/api/1.2/patches/115076/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/CAP2b4GOzcaewq1dZjnN5=jR-pZ4cRwvnCm=giYxKZ90zSGD85w@mail.gmail.com/","msgid":"","list_archive_url":null,"date":"2023-07-02T10:16:07","name":"Reimplement the .seh_scope directive","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/CAP2b4GOzcaewq1dZjnN5=jR-pZ4cRwvnCm=giYxKZ90zSGD85w@mail.gmail.com/mbox/"},{"id":115077,"url":"https://patchwork.plctlab.org/api/1.2/patches/115077/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/CAP2b4GN6AvihQ9W0ebCMgH1ozEvYKjb41Te9HfQg4k=e9ejhSw@mail.gmail.com/","msgid":"","list_archive_url":null,"date":"2023-07-02T10:18:31","name":"Reimplement the .seh_scope directive","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/CAP2b4GN6AvihQ9W0ebCMgH1ozEvYKjb41Te9HfQg4k=e9ejhSw@mail.gmail.com/mbox/"},{"id":115083,"url":"https://patchwork.plctlab.org/api/1.2/patches/115083/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230702111053.815399-1-i.swmail@xen0n.name/","msgid":"<20230702111053.815399-1-i.swmail@xen0n.name>","list_archive_url":null,"date":"2023-07-02T11:10:52","name":"[1/2] binutils: NEWS: Announce LoongArch changes in the 2.41 cycle","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230702111053.815399-1-i.swmail@xen0n.name/mbox/"},{"id":115082,"url":"https://patchwork.plctlab.org/api/1.2/patches/115082/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230702111053.815399-2-i.swmail@xen0n.name/","msgid":"<20230702111053.815399-2-i.swmail@xen0n.name>","list_archive_url":null,"date":"2023-07-02T11:10:53","name":"[2/2] gas: NEWS: Announce LoongArch changes in the 2.41 cycle","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230702111053.815399-2-i.swmail@xen0n.name/mbox/"},{"id":115188,"url":"https://patchwork.plctlab.org/api/1.2/patches/115188/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230703044321.2951358-1-yunqiang.su@cipunited.com/","msgid":"<20230703044321.2951358-1-yunqiang.su@cipunited.com>","list_archive_url":null,"date":"2023-07-03T04:43:21","name":"ld: fix plugin tests for MIPS PIC","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230703044321.2951358-1-yunqiang.su@cipunited.com/mbox/"},{"id":115284,"url":"https://patchwork.plctlab.org/api/1.2/patches/115284/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230703101047.2589341-1-christoph.muellner@vrull.eu/","msgid":"<20230703101047.2589341-1-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2023-07-03T10:10:47","name":"RISC-V: Zvkh[a,b]: Remove individual instruction class","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230703101047.2589341-1-christoph.muellner@vrull.eu/mbox/"},{"id":115301,"url":"https://patchwork.plctlab.org/api/1.2/patches/115301/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230703103647.3162351-1-yunqiang.su@cipunited.com/","msgid":"<20230703103647.3162351-1-yunqiang.su@cipunited.com>","list_archive_url":null,"date":"2023-07-03T10:36:47","name":"MIPS: Don'\''t __gnu_lto_slim to .scommon","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230703103647.3162351-1-yunqiang.su@cipunited.com/mbox/"},{"id":115305,"url":"https://patchwork.plctlab.org/api/1.2/patches/115305/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230703105034.3163572-1-yunqiang.su@cipunited.com/","msgid":"<20230703105034.3163572-1-yunqiang.su@cipunited.com>","list_archive_url":null,"date":"2023-07-03T10:50:34","name":"[v2] MIPS: Don'\''t move __gnu_lto_slim to .scommon","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230703105034.3163572-1-yunqiang.su@cipunited.com/mbox/"},{"id":115445,"url":"https://patchwork.plctlab.org/api/1.2/patches/115445/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230703181052.41059-1-krebbel@linux.ibm.com/","msgid":"<20230703181052.41059-1-krebbel@linux.ibm.com>","list_archive_url":null,"date":"2023-07-03T18:10:52","name":"[Committed] IBM Z: Fix pcrel relocs for symA-symB expressions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230703181052.41059-1-krebbel@linux.ibm.com/mbox/"},{"id":115692,"url":"https://patchwork.plctlab.org/api/1.2/patches/115692/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230704102703.650038-1-claziss@gmail.com/","msgid":"<20230704102703.650038-1-claziss@gmail.com>","list_archive_url":null,"date":"2023-07-04T10:27:02","name":"[committed,1/2] arc: Update neg<.f> 0,b encoding","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230704102703.650038-1-claziss@gmail.com/mbox/"},{"id":115691,"url":"https://patchwork.plctlab.org/api/1.2/patches/115691/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230704102703.650038-2-claziss@gmail.com/","msgid":"<20230704102703.650038-2-claziss@gmail.com>","list_archive_url":null,"date":"2023-07-04T10:27:03","name":"[committed,2/2] arc: Update default target CPU to match GCC defaults","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230704102703.650038-2-claziss@gmail.com/mbox/"},{"id":115742,"url":"https://patchwork.plctlab.org/api/1.2/patches/115742/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230704121832.222400-1-krebbel@linux.ibm.com/","msgid":"<20230704121832.222400-1-krebbel@linux.ibm.com>","list_archive_url":null,"date":"2023-07-04T12:18:32","name":"Align linkerscript symbols according to ABI","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230704121832.222400-1-krebbel@linux.ibm.com/mbox/"},{"id":115827,"url":"https://patchwork.plctlab.org/api/1.2/patches/115827/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e098654c-98dd-1b2f-e876-6ba910260492@suse.com/","msgid":"","list_archive_url":null,"date":"2023-07-04T15:18:32","name":"[01/10] x86: fold certain legacy/VEX table entries","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e098654c-98dd-1b2f-e876-6ba910260492@suse.com/mbox/"},{"id":115828,"url":"https://patchwork.plctlab.org/api/1.2/patches/115828/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/18221c8c-4d6e-f0f1-3738-785023be1268@suse.com/","msgid":"<18221c8c-4d6e-f0f1-3738-785023be1268@suse.com>","list_archive_url":null,"date":"2023-07-04T15:19:53","name":"[02/10] x86: fold legacy/VEX {,V}MOV{H,L}* entries","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/18221c8c-4d6e-f0f1-3738-785023be1268@suse.com/mbox/"},{"id":115829,"url":"https://patchwork.plctlab.org/api/1.2/patches/115829/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/46594eee-305a-8913-c407-806158fbbe8f@suse.com/","msgid":"<46594eee-305a-8913-c407-806158fbbe8f@suse.com>","list_archive_url":null,"date":"2023-07-04T15:20:35","name":"[03/10] x86: {,V}MOVNT* don'\''t need to go through mod_table[]","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/46594eee-305a-8913-c407-806158fbbe8f@suse.com/mbox/"},{"id":115830,"url":"https://patchwork.plctlab.org/api/1.2/patches/115830/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/02a1aabf-4759-009b-5718-f567ed39b81c@suse.com/","msgid":"<02a1aabf-4759-009b-5718-f567ed39b81c@suse.com>","list_archive_url":null,"date":"2023-07-04T15:21:02","name":"[04/10] x86: misc further memory-only insns don'\''t need to go through mod_table[]","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/02a1aabf-4759-009b-5718-f567ed39b81c@suse.com/mbox/"},{"id":115832,"url":"https://patchwork.plctlab.org/api/1.2/patches/115832/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/96a500b4-1b68-520b-bccc-01d78f8e6f6c@suse.com/","msgid":"<96a500b4-1b68-520b-bccc-01d78f8e6f6c@suse.com>","list_archive_url":null,"date":"2023-07-04T15:21:38","name":"[05/10] x86: SIMD shift-by-immediate don'\''t need to go through mod_table[]","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/96a500b4-1b68-520b-bccc-01d78f8e6f6c@suse.com/mbox/"},{"id":115834,"url":"https://patchwork.plctlab.org/api/1.2/patches/115834/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d9842149-1c2b-2ff9-531d-87cae64e4b78@suse.com/","msgid":"","list_archive_url":null,"date":"2023-07-04T15:22:06","name":"[06/10] x86: slightly rework handling of some register-only insns","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d9842149-1c2b-2ff9-531d-87cae64e4b78@suse.com/mbox/"},{"id":115835,"url":"https://patchwork.plctlab.org/api/1.2/patches/115835/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/25535360-ad14-8ed2-bd86-b96f97306e43@suse.com/","msgid":"<25535360-ad14-8ed2-bd86-b96f97306e43@suse.com>","list_archive_url":null,"date":"2023-07-04T15:22:31","name":"[07/10] x86: various operations on mask registers can avoid going through mod_table[]","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/25535360-ad14-8ed2-bd86-b96f97306e43@suse.com/mbox/"},{"id":115833,"url":"https://patchwork.plctlab.org/api/1.2/patches/115833/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/54b1c54f-ddad-4d5a-f5d0-e585cd3aaa3e@suse.com/","msgid":"<54b1c54f-ddad-4d5a-f5d0-e585cd3aaa3e@suse.com>","list_archive_url":null,"date":"2023-07-04T15:22:59","name":"[08/10] x86: misc further register-only insns don'\''t need to go through mod_table[]","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/54b1c54f-ddad-4d5a-f5d0-e585cd3aaa3e@suse.com/mbox/"},{"id":115837,"url":"https://patchwork.plctlab.org/api/1.2/patches/115837/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ec881a0e-05b2-556b-8e21-a1c38429e465@suse.com/","msgid":"","list_archive_url":null,"date":"2023-07-04T15:23:25","name":"[09/10] x86: convert 0FXOP to just XOP in enumerator names","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ec881a0e-05b2-556b-8e21-a1c38429e465@suse.com/mbox/"},{"id":115836,"url":"https://patchwork.plctlab.org/api/1.2/patches/115836/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/126aeaee-40ae-34aa-5e30-9579264d6336@suse.com/","msgid":"<126aeaee-40ae-34aa-5e30-9579264d6336@suse.com>","list_archive_url":null,"date":"2023-07-04T15:24:08","name":"[10/10] x86: simplify table-referencing macros","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/126aeaee-40ae-34aa-5e30-9579264d6336@suse.com/mbox/"},{"id":116027,"url":"https://patchwork.plctlab.org/api/1.2/patches/116027/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230705084213.91043-1-lidie@eswincomputing.com/","msgid":"<20230705084213.91043-1-lidie@eswincomputing.com>","list_archive_url":null,"date":"2023-07-05T08:42:13","name":"[RISC-V] Fix the valid gp range for gp relax.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230705084213.91043-1-lidie@eswincomputing.com/mbox/"},{"id":116978,"url":"https://patchwork.plctlab.org/api/1.2/patches/116978/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230707054306.2810080-1-maskray@google.com/","msgid":"<20230707054306.2810080-1-maskray@google.com>","list_archive_url":null,"date":"2023-07-07T05:43:06","name":"[v3] PR30592 objcopy: allow --set-section-flags to add or remove SHF_X86_64_LARGE","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230707054306.2810080-1-maskray@google.com/mbox/"},{"id":117059,"url":"https://patchwork.plctlab.org/api/1.2/patches/117059/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230707101024.2863421-1-claziss@gmail.com/","msgid":"<20230707101024.2863421-1-claziss@gmail.com>","list_archive_url":null,"date":"2023-07-07T10:10:24","name":"[committed] arc: Update/Add ARCv3 support.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230707101024.2863421-1-claziss@gmail.com/mbox/"},{"id":117125,"url":"https://patchwork.plctlab.org/api/1.2/patches/117125/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d8cb6772-092f-b79e-421b-1da61ce020ac@suse.com/","msgid":"","list_archive_url":null,"date":"2023-07-07T12:01:07","name":"ld: fix build with old glibc / gcc","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d8cb6772-092f-b79e-421b-1da61ce020ac@suse.com/mbox/"},{"id":117135,"url":"https://patchwork.plctlab.org/api/1.2/patches/117135/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/88c2fb96-185d-ae27-c025-ed025ed54641@suse.com/","msgid":"<88c2fb96-185d-ae27-c025-ed025ed54641@suse.com>","list_archive_url":null,"date":"2023-07-07T13:47:35","name":"ld/PDB: fix off-by-1 in add_globals_ref()","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/88c2fb96-185d-ae27-c025-ed025ed54641@suse.com/mbox/"},{"id":117306,"url":"https://patchwork.plctlab.org/api/1.2/patches/117306/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/878rbrgzoz.fsf@gmail.com/","msgid":"<878rbrgzoz.fsf@gmail.com>","list_archive_url":null,"date":"2023-07-07T21:47:48","name":"objdump: Round ASCII art lines in jump visualization","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/878rbrgzoz.fsf@gmail.com/mbox/"},{"id":117387,"url":"https://patchwork.plctlab.org/api/1.2/patches/117387/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230708053035.528911-1-maskray@google.com/","msgid":"<20230708053035.528911-1-maskray@google.com>","list_archive_url":null,"date":"2023-07-08T05:30:35","name":"[v4] PR30592 objcopy: allow --set-section-flags to add or remove SHF_X86_64_LARGE","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230708053035.528911-1-maskray@google.com/mbox/"},{"id":118315,"url":"https://patchwork.plctlab.org/api/1.2/patches/118315/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230711083214.689474-1-jiawei@iscas.ac.cn/","msgid":"<20230711083214.689474-1-jiawei@iscas.ac.cn>","list_archive_url":null,"date":"2023-07-11T08:32:14","name":"[v2] RISC-V: Support Zca/f/d extensions.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230711083214.689474-1-jiawei@iscas.ac.cn/mbox/"},{"id":118324,"url":"https://patchwork.plctlab.org/api/1.2/patches/118324/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230711084931.18978-1-hejinyang@loongson.cn/","msgid":"<20230711084931.18978-1-hejinyang@loongson.cn>","list_archive_url":null,"date":"2023-07-11T08:49:30","name":"[1/2] LoongArch: bfd: Remove elf_seg_map condition in loongarch_elf_relax_section","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230711084931.18978-1-hejinyang@loongson.cn/mbox/"},{"id":118325,"url":"https://patchwork.plctlab.org/api/1.2/patches/118325/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230711084931.18978-2-hejinyang@loongson.cn/","msgid":"<20230711084931.18978-2-hejinyang@loongson.cn>","list_archive_url":null,"date":"2023-07-11T08:49:31","name":"[2/2] LoongArch: bfd: Add counter to get real relax region","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230711084931.18978-2-hejinyang@loongson.cn/mbox/"},{"id":118766,"url":"https://patchwork.plctlab.org/api/1.2/patches/118766/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZK4EFMJYmIzmJnh5@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-07-12T01:38:28","name":".noinit and .persistent alignment","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZK4EFMJYmIzmJnh5@squeak.grove.modra.org/mbox/"},{"id":118767,"url":"https://patchwork.plctlab.org/api/1.2/patches/118767/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZK4EZ3/IKANDAvI0@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-07-12T01:39:51","name":".noinit and .persistent for msp430","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZK4EZ3/IKANDAvI0@squeak.grove.modra.org/mbox/"},{"id":118801,"url":"https://patchwork.plctlab.org/api/1.2/patches/118801/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZK4j+R81iVz44wvm@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-07-12T03:54:33","name":"Support NEXT_SECTION in ALIGNOF and SIZEOF","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZK4j+R81iVz44wvm@squeak.grove.modra.org/mbox/"},{"id":119149,"url":"https://patchwork.plctlab.org/api/1.2/patches/119149/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230712124036.3385283-1-jiawei@iscas.ac.cn/","msgid":"<20230712124036.3385283-1-jiawei@iscas.ac.cn>","list_archive_url":null,"date":"2023-07-12T12:40:36","name":"[v2] RISC-V: Supports Zcb extension.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230712124036.3385283-1-jiawei@iscas.ac.cn/mbox/"},{"id":119190,"url":"https://patchwork.plctlab.org/api/1.2/patches/119190/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.LSU.2.20.2307121351250.13548@wotan.suse.de/","msgid":"","list_archive_url":null,"date":"2023-07-12T13:56:54","name":"Let '\''^'\'' through the lexer","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/alpine.LSU.2.20.2307121351250.13548@wotan.suse.de/mbox/"},{"id":119481,"url":"https://patchwork.plctlab.org/api/1.2/patches/119481/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/62b68369-0d02-3472-bbe6-cb627661252e@oracle.com/","msgid":"<62b68369-0d02-3472-bbe6-cb627661252e@oracle.com>","list_archive_url":null,"date":"2023-07-13T02:35:06","name":"Patch for version.texi?","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/62b68369-0d02-3472-bbe6-cb627661252e@oracle.com/mbox/"},{"id":119567,"url":"https://patchwork.plctlab.org/api/1.2/patches/119567/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230713063303.205862-2-haochen.jiang@intel.com/","msgid":"<20230713063303.205862-2-haochen.jiang@intel.com>","list_archive_url":null,"date":"2023-07-13T06:32:59","name":"[1/5] Support Intel AVX-VNNI-INT16","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230713063303.205862-2-haochen.jiang@intel.com/mbox/"},{"id":119565,"url":"https://patchwork.plctlab.org/api/1.2/patches/119565/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230713063303.205862-3-haochen.jiang@intel.com/","msgid":"<20230713063303.205862-3-haochen.jiang@intel.com>","list_archive_url":null,"date":"2023-07-13T06:33:00","name":"[2/5] Support Intel SHA512","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230713063303.205862-3-haochen.jiang@intel.com/mbox/"},{"id":119563,"url":"https://patchwork.plctlab.org/api/1.2/patches/119563/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230713063303.205862-4-haochen.jiang@intel.com/","msgid":"<20230713063303.205862-4-haochen.jiang@intel.com>","list_archive_url":null,"date":"2023-07-13T06:33:01","name":"[3/5] Support Intel SM3","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230713063303.205862-4-haochen.jiang@intel.com/mbox/"},{"id":119566,"url":"https://patchwork.plctlab.org/api/1.2/patches/119566/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230713063303.205862-5-haochen.jiang@intel.com/","msgid":"<20230713063303.205862-5-haochen.jiang@intel.com>","list_archive_url":null,"date":"2023-07-13T06:33:02","name":"[4/5] Support Intel SM4","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230713063303.205862-5-haochen.jiang@intel.com/mbox/"},{"id":119562,"url":"https://patchwork.plctlab.org/api/1.2/patches/119562/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230713063303.205862-6-haochen.jiang@intel.com/","msgid":"<20230713063303.205862-6-haochen.jiang@intel.com>","list_archive_url":null,"date":"2023-07-13T06:33:03","name":"[5/5] Support Intel PBNDKB","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230713063303.205862-6-haochen.jiang@intel.com/mbox/"},{"id":119993,"url":"https://patchwork.plctlab.org/api/1.2/patches/119993/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230713153738.2638727-1-vladimir.mezentsev@oracle.com/","msgid":"<20230713153738.2638727-1-vladimir.mezentsev@oracle.com>","list_archive_url":null,"date":"2023-07-13T15:37:38","name":"gprofng: 30602 [2.41] gprofng test hangs on i686-linux-gnu","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230713153738.2638727-1-vladimir.mezentsev@oracle.com/mbox/"},{"id":120205,"url":"https://patchwork.plctlab.org/api/1.2/patches/120205/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZLDCUfzWq0bZSyB4@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-07-14T03:34:41","name":"AIX_WEAK_SUPPORT","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZLDCUfzWq0bZSyB4@squeak.grove.modra.org/mbox/"},{"id":120206,"url":"https://patchwork.plctlab.org/api/1.2/patches/120206/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZLDCeFLsD6g+d1sB@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-07-14T03:35:20","name":"More tidies to objcopy archive handling","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZLDCeFLsD6g+d1sB@squeak.grove.modra.org/mbox/"},{"id":120207,"url":"https://patchwork.plctlab.org/api/1.2/patches/120207/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZLDClMEw/UQCGSPZ@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-07-14T03:35:48","name":"Fix loongarch build with gcc-4.5","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZLDClMEw/UQCGSPZ@squeak.grove.modra.org/mbox/"},{"id":120208,"url":"https://patchwork.plctlab.org/api/1.2/patches/120208/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZLDC03FCE+2lGiIo@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-07-14T03:36:51","name":"Make the default gas symbol hash table larger","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZLDC03FCE+2lGiIo@squeak.grove.modra.org/mbox/"},{"id":120326,"url":"https://patchwork.plctlab.org/api/1.2/patches/120326/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2350928d-ed93-91ed-8bcd-fce9902914b1@codesourcery.com/","msgid":"<2350928d-ed93-91ed-8bcd-fce9902914b1@codesourcery.com>","list_archive_url":null,"date":"2023-07-14T08:22:56","name":"'\''make pdf'\'' fails due to: [PATCH] Let '\''^'\'' through the lexer]","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2350928d-ed93-91ed-8bcd-fce9902914b1@codesourcery.com/mbox/"},{"id":120394,"url":"https://patchwork.plctlab.org/api/1.2/patches/120394/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/40ab94c5-d0c4-ee01-a53b-dbc6e5f3f9d2@suse.com/","msgid":"<40ab94c5-d0c4-ee01-a53b-dbc6e5f3f9d2@suse.com>","list_archive_url":null,"date":"2023-07-14T10:02:17","name":"[1/2] x86: simplify disassembly of LAR/LSL","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/40ab94c5-d0c4-ee01-a53b-dbc6e5f3f9d2@suse.com/mbox/"},{"id":120395,"url":"https://patchwork.plctlab.org/api/1.2/patches/120395/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7cc1eda0-713d-9172-c3ed-078e0899b0c4@suse.com/","msgid":"<7cc1eda0-713d-9172-c3ed-078e0899b0c4@suse.com>","list_archive_url":null,"date":"2023-07-14T10:02:39","name":"[2/2] x86: adjust disassembly of insns operating on selector values","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7cc1eda0-713d-9172-c3ed-078e0899b0c4@suse.com/mbox/"},{"id":120981,"url":"https://patchwork.plctlab.org/api/1.2/patches/120981/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZLR4TfHSewLy67fu@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-07-16T23:07:57","name":"PR10957, Missing option to really print section+offset","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZLR4TfHSewLy67fu@squeak.grove.modra.org/mbox/"},{"id":121117,"url":"https://patchwork.plctlab.org/api/1.2/patches/121117/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230717082229.2149099-1-mengqinggang@loongson.cn/","msgid":"<20230717082229.2149099-1-mengqinggang@loongson.cn>","list_archive_url":null,"date":"2023-07-17T08:22:28","name":"[1/2] LoongArch: Fix instruction immediate bug caused by sign-extend","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230717082229.2149099-1-mengqinggang@loongson.cn/mbox/"},{"id":121118,"url":"https://patchwork.plctlab.org/api/1.2/patches/121118/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230717082229.2149099-2-mengqinggang@loongson.cn/","msgid":"<20230717082229.2149099-2-mengqinggang@loongson.cn>","list_archive_url":null,"date":"2023-07-17T08:22:29","name":"[2/2] LoongArch: Fix immediate overflow check bug","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230717082229.2149099-2-mengqinggang@loongson.cn/mbox/"},{"id":121130,"url":"https://patchwork.plctlab.org/api/1.2/patches/121130/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230717084146.7978-1-tdevries@suse.de/","msgid":"<20230717084146.7978-1-tdevries@suse.de>","list_archive_url":null,"date":"2023-07-17T08:41:46","name":"[gdb/build] Fix Wlto-type-mismatch in opcodes/ft32-dis.c","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230717084146.7978-1-tdevries@suse.de/mbox/"},{"id":121835,"url":"https://patchwork.plctlab.org/api/1.2/patches/121835/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230718075412.1304548-1-haochen.jiang@intel.com/","msgid":"<20230718075412.1304548-1-haochen.jiang@intel.com>","list_archive_url":null,"date":"2023-07-18T07:54:12","name":"[v2] Support Intel SHA512","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230718075412.1304548-1-haochen.jiang@intel.com/mbox/"},{"id":121848,"url":"https://patchwork.plctlab.org/api/1.2/patches/121848/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230718080915.1391780-1-haochen.jiang@intel.com/","msgid":"<20230718080915.1391780-1-haochen.jiang@intel.com>","list_archive_url":null,"date":"2023-07-18T08:09:15","name":"[v2] Support Intel SM3","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230718080915.1391780-1-haochen.jiang@intel.com/mbox/"},{"id":121854,"url":"https://patchwork.plctlab.org/api/1.2/patches/121854/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230718081358.1394673-1-haochen.jiang@intel.com/","msgid":"<20230718081358.1394673-1-haochen.jiang@intel.com>","list_archive_url":null,"date":"2023-07-18T08:13:58","name":"[v2] Support Intel SM4","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230718081358.1394673-1-haochen.jiang@intel.com/mbox/"},{"id":122353,"url":"https://patchwork.plctlab.org/api/1.2/patches/122353/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZLc+98Th9pmqLTGc@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-07-19T01:40:07","name":"gas 32-bit host compile warnings","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZLc+98Th9pmqLTGc@squeak.grove.modra.org/mbox/"},{"id":122354,"url":"https://patchwork.plctlab.org/api/1.2/patches/122354/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZLc/HcP8ynwWNpO3@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-07-19T01:40:45","name":"Build all the objdump extensions with --enable-targets=all","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZLc/HcP8ynwWNpO3@squeak.grove.modra.org/mbox/"},{"id":122355,"url":"https://patchwork.plctlab.org/api/1.2/patches/122355/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZLc/RaA7zPjQQ2Sl@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-07-19T01:41:25","name":"Tidy binutils configure","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZLc/RaA7zPjQQ2Sl@squeak.grove.modra.org/mbox/"},{"id":122356,"url":"https://patchwork.plctlab.org/api/1.2/patches/122356/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZLc/ckC/wa90hisa@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2023-07-19T01:42:10","name":"[GOLD,PowerPC64] Debug info relocation overflow","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ZLc/ckC/wa90hisa@squeak.grove.modra.org/mbox/"},{"id":122359,"url":"https://patchwork.plctlab.org/api/1.2/patches/122359/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230719021721.776961-1-mengqinggang@loongson.cn/","msgid":"<20230719021721.776961-1-mengqinggang@loongson.cn>","list_archive_url":null,"date":"2023-07-19T02:17:21","name":"LoongArch: ld: Simplify inserting IRELATIVE relocations to .rela.dyn","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230719021721.776961-1-mengqinggang@loongson.cn/mbox/"},{"id":122541,"url":"https://patchwork.plctlab.org/api/1.2/patches/122541/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0c22e147-aa0c-12ae-24e0-4f770948054d@debian.org/","msgid":"<0c22e147-aa0c-12ae-24e0-4f770948054d@debian.org>","list_archive_url":null,"date":"2023-07-19T10:54:58","name":"objcopy embeds the current time and ignores SOURCE_DATE_EPOCH making the output unreproducible","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0c22e147-aa0c-12ae-24e0-4f770948054d@debian.org/mbox/"},{"id":123087,"url":"https://patchwork.plctlab.org/api/1.2/patches/123087/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230720083213.2280286-1-haochen.jiang@intel.com/","msgid":"<20230720083213.2280286-1-haochen.jiang@intel.com>","list_archive_url":null,"date":"2023-07-20T08:32:13","name":"Support Intel SHA512","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230720083213.2280286-1-haochen.jiang@intel.com/mbox/"},{"id":123319,"url":"https://patchwork.plctlab.org/api/1.2/patches/123319/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/efa3944b8dddd45e171baa8c3939e8636ab2d6b8.camel@espressif.com/","msgid":"","list_archive_url":null,"date":"2023-07-20T14:39:14","name":"xtensa: add dynconfig option for ld/gas","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/efa3944b8dddd45e171baa8c3939e8636ab2d6b8.camel@espressif.com/mbox/"},{"id":123564,"url":"https://patchwork.plctlab.org/api/1.2/patches/123564/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230721053218.16817-1-hau.hsu@sifive.com/","msgid":"<20230721053218.16817-1-hau.hsu@sifive.com>","list_archive_url":null,"date":"2023-07-21T05:32:18","name":"RISC-V: Fix wrongly inserted IRELATIVE relocs","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230721053218.16817-1-hau.hsu@sifive.com/mbox/"},{"id":123611,"url":"https://patchwork.plctlab.org/api/1.2/patches/123611/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/32719c54-c66a-384e-d570-ebefe607e3e9@suse.com/","msgid":"<32719c54-c66a-384e-d570-ebefe607e3e9@suse.com>","list_archive_url":null,"date":"2023-07-21T07:12:50","name":"[RFC] x86: pack CPU flags in opcode table","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/32719c54-c66a-384e-d570-ebefe607e3e9@suse.com/mbox/"},{"id":123632,"url":"https://patchwork.plctlab.org/api/1.2/patches/123632/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230721074956.7188-2-piannetta@kalrayinc.com/","msgid":"<20230721074956.7188-2-piannetta@kalrayinc.com>","list_archive_url":null,"date":"2023-07-21T07:49:50","name":"[1/7] kvx: Add bf files.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230721074956.7188-2-piannetta@kalrayinc.com/mbox/"},{"id":123627,"url":"https://patchwork.plctlab.org/api/1.2/patches/123627/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230721074956.7188-3-piannetta@kalrayinc.com/","msgid":"<20230721074956.7188-3-piannetta@kalrayinc.com>","list_archive_url":null,"date":"2023-07-21T07:49:51","name":"[2/7] kvx: Add binutils files.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230721074956.7188-3-piannetta@kalrayinc.com/mbox/"},{"id":123629,"url":"https://patchwork.plctlab.org/api/1.2/patches/123629/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230721074956.7188-5-piannetta@kalrayinc.com/","msgid":"<20230721074956.7188-5-piannetta@kalrayinc.com>","list_archive_url":null,"date":"2023-07-21T07:49:53","name":"[4/7] kvx: Add ld files.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230721074956.7188-5-piannetta@kalrayinc.com/mbox/"},{"id":123635,"url":"https://patchwork.plctlab.org/api/1.2/patches/123635/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230721074956.7188-6-piannetta@kalrayinc.com/","msgid":"<20230721074956.7188-6-piannetta@kalrayinc.com>","list_archive_url":null,"date":"2023-07-21T07:49:54","name":"[5/7] kvx: Add include files.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230721074956.7188-6-piannetta@kalrayinc.com/mbox/"},{"id":123631,"url":"https://patchwork.plctlab.org/api/1.2/patches/123631/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230721074956.7188-8-piannetta@kalrayinc.com/","msgid":"<20230721074956.7188-8-piannetta@kalrayinc.com>","list_archive_url":null,"date":"2023-07-21T07:49:56","name":"[7/7] kvx: Add toplevel files.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230721074956.7188-8-piannetta@kalrayinc.com/mbox/"}],"public":true,"mbox":"https://patchwork.plctlab.org/bundle/patchwork-bot/binutils-gdb_2023-07/mbox/"}]' + bundle_id=26 + git-pw bundle add 26 123757 +------------+-------------------------------------------------------------------------------------------------------+ | Property | Value | |------------+-------------------------------------------------------------------------------------------------------| | ID | 26 | | Name | binutils-gdb_2023-07 | | URL | https://patchwork.plctlab.org/bundle/patchwork-bot/binutils-gdb_2023-07/ | | Owner | patchwork-bot | | Project | binutils-gdb | | Public | True | | Patches | 114893 [v5,01/15] RISC-V: Add support for the Zvbb ISA extension | | | 114888 [v5,02/15] RISC-V: Add support for the Zvbc extension | | | 114896 [v5,03/15] RISC-V: Add support for the Zvkg ISA extension | | | 114889 [v5,04/15] RISC-V: Add support for the Zvkned ISA extension | | | 114890 [v5,05/15] RISC-V: Add support for the Zvknh[a, b] ISA extensions | | | 114899 [v5,06/15] RISC-V: Add support for the Zvksed ISA extension | | | 114892 [v5,07/15] RISC-V: Add support for the Zvksh ISA extension | | | 114895 [v5,08/15] RISC-V: Add support for the Zvkn ISA extension | | | 114901 [v5,09/15] RISC-V: Allow nested implications for extensions | | | 114894 [v5,10/15] RISC-V: Add support for the Zvkng ISA extension | | | 114897 [v5,11/15] RISC-V: Add support for the Zvks ISA extension | | | 114903 [v5,12/15] RISC-V: Add support for the Zvksg ISA extension | | | 114898 [v5,13/15] RISC-V: Add support for the Zvknc ISA extension | | | 114900 [v5,14/15] RISC-V: Add support for the Zvksc ISA extension | | | 114902 [v5,15/15] binutils: NEWS: Announce new RISC-V vector crypto extensions | | | 114949 [v6,01/15] RISC-V: Add support for the Zvbb ISA extension | | | 114952 [v6,02/15] RISC-V: Add support for the Zvbc extension | | | 114955 [v6,03/15] RISC-V: Add support for the Zvkg ISA extension | | | 114958 [v6,04/15] RISC-V: Add support for the Zvkned ISA extension | | | 114953 [v6,05/15] RISC-V: Add support for the Zvknh[a, b] ISA extensions | | | 114950 [v6,06/15] RISC-V: Add support for the Zvksed ISA extension | | | 114956 [v6,07/15] RISC-V: Add support for the Zvksh ISA extension | | | 114954 [v6,08/15] RISC-V: Add support for the Zvkn ISA extension | | | 114960 [v6,09/15] RISC-V: Allow nested implications for extensions | | | 114951 [v6,10/15] RISC-V: Add support for the Zvkng ISA extension | | | 114962 [v6,11/15] RISC-V: Add support for the Zvks ISA extension | | | 114957 [v6,12/15] RISC-V: Add support for the Zvksg ISA extension | | | 114963 [v6,13/15] RISC-V: Add support for the Zvknc ISA extension | | | 114961 [v6,14/15] RISC-V: Add support for the Zvksc ISA extension | | | 114964 [v6,15/15] binutils: NEWS: Announce new RISC-V vector crypto extensions | | | 115075 LoongArch: gas: Fix shared builds | | | 115076 Reimplement the .seh_scope directive | | | 115077 Reimplement the .seh_scope directive | | | 115083 [1/2] binutils: NEWS: Announce LoongArch changes in the 2.41 cycle | | | 115082 [2/2] gas: NEWS: Announce LoongArch changes in the 2.41 cycle | | | 115188 ld: fix plugin tests for MIPS PIC | | | 115284 RISC-V: Zvkh[a,b]: Remove individual instruction class | | | 115301 MIPS: Don't __gnu_lto_slim to .scommon | | | 115305 [v2] MIPS: Don't move __gnu_lto_slim to .scommon | | | 115445 [Committed] IBM Z: Fix pcrel relocs for symA-symB expressions | | | 115692 [committed,1/2] arc: Update neg<.f> 0,b encoding | | | 115691 [committed,2/2] arc: Update default target CPU to match GCC defaults | | | 115742 Align linkerscript symbols according to ABI | | | 115827 [01/10] x86: fold certain legacy/VEX table entries | | | 115828 [02/10] x86: fold legacy/VEX {,V}MOV{H,L}* entries | | | 115829 [03/10] x86: {,V}MOVNT* don't need to go through mod_table[] | | | 115830 [04/10] x86: misc further memory-only insns don't need to go through mod_table[] | | | 115832 [05/10] x86: SIMD shift-by-immediate don't need to go through mod_table[] | | | 115834 [06/10] x86: slightly rework handling of some register-only insns | | | 115835 [07/10] x86: various operations on mask registers can avoid going through mod_table[] | | | 115833 [08/10] x86: misc further register-only insns don't need to go through mod_table[] | | | 115837 [09/10] x86: convert 0FXOP to just XOP in enumerator names | | | 115836 [10/10] x86: simplify table-referencing macros | | | 116027 [RISC-V] Fix the valid gp range for gp relax. | | | 116978 [v3] PR30592 objcopy: allow --set-section-flags to add or remove SHF_X86_64_LARGE | | | 117059 [committed] arc: Update/Add ARCv3 support. | | | 117125 ld: fix build with old glibc / gcc | | | 117135 ld/PDB: fix off-by-1 in add_globals_ref() | | | 117306 objdump: Round ASCII art lines in jump visualization | | | 117387 [v4] PR30592 objcopy: allow --set-section-flags to add or remove SHF_X86_64_LARGE | | | 118315 [v2] RISC-V: Support Zca/f/d extensions. | | | 118324 [1/2] LoongArch: bfd: Remove elf_seg_map condition in loongarch_elf_relax_section | | | 118325 [2/2] LoongArch: bfd: Add counter to get real relax region | | | 118766 .noinit and .persistent alignment | | | 118767 .noinit and .persistent for msp430 | | | 118801 Support NEXT_SECTION in ALIGNOF and SIZEOF | | | 119149 [v2] RISC-V: Supports Zcb extension. | | | 119190 Let '^' through the lexer | | | 119481 Patch for version.texi? | | | 119567 [1/5] Support Intel AVX-VNNI-INT16 | | | 119565 [2/5] Support Intel SHA512 | | | 119563 [3/5] Support Intel SM3 | | | 119566 [4/5] Support Intel SM4 | | | 119562 [5/5] Support Intel PBNDKB | | | 119993 gprofng: 30602 [2.41] gprofng test hangs on i686-linux-gnu | | | 120205 AIX_WEAK_SUPPORT | | | 120206 More tidies to objcopy archive handling | | | 120207 Fix loongarch build with gcc-4.5 | | | 120208 Make the default gas symbol hash table larger | | | 120326 'make pdf' fails due to: [PATCH] Let '^' through the lexer] | | | 120394 [1/2] x86: simplify disassembly of LAR/LSL | | | 120395 [2/2] x86: adjust disassembly of insns operating on selector values | | | 120981 PR10957, Missing option to really print section+offset | | | 121117 [1/2] LoongArch: Fix instruction immediate bug caused by sign-extend | | | 121118 [2/2] LoongArch: Fix immediate overflow check bug | | | 121130 [gdb/build] Fix Wlto-type-mismatch in opcodes/ft32-dis.c | | | 121835 [v2] Support Intel SHA512 | | | 121848 [v2] Support Intel SM3 | | | 121854 [v2] Support Intel SM4 | | | 122353 gas 32-bit host compile warnings | | | 122354 Build all the objdump extensions with --enable-targets=all | | | 122355 Tidy binutils configure | | | 122356 [GOLD,PowerPC64] Debug info relocation overflow | | | 122359 LoongArch: ld: Simplify inserting IRELATIVE relocations to .rela.dyn | | | 122541 objcopy embeds the current time and ignores SOURCE_DATE_EPOCH making the output unreproducible | | | 123087 Support Intel SHA512 | | | 123319 xtensa: add dynconfig option for ld/gas | | | 123564 RISC-V: Fix wrongly inserted IRELATIVE relocs | | | 123611 [RFC] x86: pack CPU flags in opcode table | | | 123632 [1/7] kvx: Add bf files. | | | 123627 [2/7] kvx: Add binutils files. | | | 123629 [4/7] kvx: Add ld files. | | | 123635 [5/7] kvx: Add include files. | | | 123631 [7/7] kvx: Add toplevel files. | | | 123757 [COMMITTED] DesCGENization of the BPF binutils port | +------------+-------------------------------------------------------------------------------------------------------+ + git config pull.rebase false + git fetch origin master From github.com:plctlab/patchwork-binutils-gdb * branch master -> FETCH_HEAD + git checkout master Switched to a new branch 'master' branch 'master' set up to track 'origin/master'. + git pull origin master From github.com:plctlab/patchwork-binutils-gdb * branch master -> FETCH_HEAD Already up to date. + git fetch origin upstream-master From github.com:plctlab/patchwork-binutils-gdb * branch upstream-master -> FETCH_HEAD + git checkout upstream-master Switched to a new branch 'upstream-master' branch 'upstream-master' set up to track 'origin/upstream-master'. + git remote add upstream https://sourceware.org/git/binutils-gdb.git + git pull upstream master From https://sourceware.org/git/binutils-gdb * branch master -> FETCH_HEAD * [new branch] master -> upstream/master Updating 178e19707..7bb9f0c2b Fast-forward bfd/bfd-in2.h | 1 + bfd/bpf-reloc.def | 15 + bfd/elf64-bpf.c | 2 + bfd/libbfd.h | 1 + bfd/reloc.c | 2 + cpu/bpf.cpu | 855 ------- cpu/bpf.opc | 191 -- gas/config/tc-bpf.c | 2519 ++++++++------------ gas/config/tc-bpf.h | 4 +- gas/configure | 1 - gas/configure.ac | 1 - gas/doc/c-bpf.texi | 790 ++++--- gas/testsuite/gas/all/assign-bad-recursive.d | 1 - gas/testsuite/gas/all/eqv-dot.d | 2 +- gas/testsuite/gas/all/gas.exp | 5 +- gas/testsuite/gas/bpf/alu-be-pseudoc.d | 66 +- gas/testsuite/gas/bpf/alu-be.d | 68 +- gas/testsuite/gas/bpf/alu-be.dump | 54 - gas/testsuite/gas/bpf/alu-pseudoc.d | 68 +- gas/testsuite/gas/bpf/alu-pseudoc.s | 8 +- gas/testsuite/gas/bpf/alu-xbpf.d | 17 - gas/testsuite/gas/bpf/alu-xbpf.s | 11 - gas/testsuite/gas/bpf/alu.d | 68 +- gas/testsuite/gas/bpf/alu.dump | 54 - gas/testsuite/gas/bpf/alu.s | 8 +- gas/testsuite/gas/bpf/alu32-be-pseudoc.d | 62 +- gas/testsuite/gas/bpf/alu32-be.d | 64 +- gas/testsuite/gas/bpf/alu32-be.dump | 60 - gas/testsuite/gas/bpf/alu32-pseudoc.d | 62 +- gas/testsuite/gas/bpf/alu32-pseudoc.s | 30 +- gas/testsuite/gas/bpf/alu32-xbpf.d | 17 - gas/testsuite/gas/bpf/alu32-xbpf.s | 11 - gas/testsuite/gas/bpf/alu32.d | 62 +- gas/testsuite/gas/bpf/alu32.dump | 60 - gas/testsuite/gas/bpf/alu32.s | 8 +- gas/testsuite/gas/bpf/atomic-be-pseudoc.d | 12 + gas/testsuite/gas/bpf/atomic-be.d | 5 +- gas/testsuite/gas/bpf/atomic-pseudoc.d | 15 +- gas/testsuite/gas/bpf/atomic-pseudoc.s | 4 +- gas/testsuite/gas/bpf/atomic.d | 13 +- gas/testsuite/gas/bpf/atomic.dump | 7 - gas/testsuite/gas/bpf/atomic.s | 4 +- gas/testsuite/gas/bpf/bpf.exp | 30 +- gas/testsuite/gas/bpf/call-be.d | 4 +- gas/testsuite/gas/bpf/call.d | 4 +- gas/testsuite/gas/bpf/data-be.d | 2 +- gas/testsuite/gas/bpf/data.d | 2 +- gas/testsuite/gas/bpf/exit-be.d | 4 +- gas/testsuite/gas/bpf/exit.d | 4 +- gas/testsuite/gas/bpf/indcall-1-pseudoc.d | 24 +- gas/testsuite/gas/bpf/indcall-1.d | 24 +- gas/testsuite/gas/bpf/indcall-1.dump | 18 - gas/testsuite/gas/bpf/indcall-bad-1.l | 5 - gas/testsuite/gas/bpf/indcall-bad-1.s | 1 - gas/testsuite/gas/bpf/jump-be-pseudoc.d | 32 + gas/testsuite/gas/bpf/jump-be.d | 5 +- gas/testsuite/gas/bpf/jump-pseudoc.d | 33 +- gas/testsuite/gas/bpf/jump.d | 33 +- gas/testsuite/gas/bpf/jump.dump | 27 - gas/testsuite/gas/bpf/jump32-be-pseudoc.d | 32 + gas/testsuite/gas/bpf/jump32-be.d | 32 + gas/testsuite/gas/bpf/jump32-pseudoc.d | 33 +- gas/testsuite/gas/bpf/jump32.d | 33 +- gas/testsuite/gas/bpf/jump32.dump | 27 - gas/testsuite/gas/bpf/lddw-be-pseudoc.d | 19 +- gas/testsuite/gas/bpf/lddw-be.d | 19 +- gas/testsuite/gas/bpf/lddw-be.dump | 13 - gas/testsuite/gas/bpf/lddw-pseudoc.d | 19 +- gas/testsuite/gas/bpf/lddw.d | 19 +- gas/testsuite/gas/bpf/lddw.dump | 13 - gas/testsuite/gas/bpf/mem-be-pseudoc.d | 30 + gas/testsuite/gas/bpf/mem-be.d | 11 +- gas/testsuite/gas/bpf/mem-pseudoc.d | 31 +- gas/testsuite/gas/bpf/mem-pseudoc.s | 8 +- gas/testsuite/gas/bpf/mem.d | 31 +- gas/testsuite/gas/bpf/mem.dump | 25 - gas/testsuite/gas/bpf/mem.s | 2 +- gas/testsuite/gas/bpf/pseudoc-normal-be.d | 214 -- gas/testsuite/gas/bpf/pseudoc-normal.d | 214 -- gas/testsuite/gas/bpf/pseudoc-normal.s | 196 -- gas/testsuite/gas/bpf/spacing-pseudoc.d | 18 + gas/testsuite/gas/bpf/spacing-pseudoc.s | 9 + gdb/solib-rocm.c | 125 +- include/dis-asm.h | 1 + include/elf/bpf.h | 1 + include/opcode/bpf.h | 306 +++ ld/testsuite/ld-bpf/call-1.d | 4 +- ld/testsuite/ld-bpf/call-2.d | 2 +- ld/testsuite/ld-bpf/reloc-insn-external-be.d | 4 +- ld/testsuite/ld-bpf/reloc-insn-external-le.d | 4 +- opcodes/Makefile.am | 16 - opcodes/Makefile.in | 20 - opcodes/bpf-asm.c | 590 ----- opcodes/bpf-desc.c | 1939 ---------------- opcodes/bpf-desc.h | 268 --- opcodes/bpf-dis.c | 795 ++----- opcodes/bpf-ibld.c | 961 -------- opcodes/bpf-opc.c | 2271 ++++-------------- opcodes/bpf-opc.h | 166 -- opcodes/configure | 2 +- opcodes/configure.ac | 2 +- opcodes/disassemble.c | 30 +- sim/Makefile.in | 349 ++- sim/bpf/arch.c | 35 - sim/bpf/arch.h | 50 - sim/bpf/bpf-helpers.c | 181 -- sim/bpf/bpf-helpers.def | 194 -- sim/bpf/bpf-helpers.h | 33 - sim/bpf/bpf-sim.c | 1455 ++++++++++++ sim/bpf/bpf-sim.h | 20 +- sim/bpf/bpf.c | 329 --- sim/bpf/cpu.c | 61 - sim/bpf/cpu.h | 81 - sim/bpf/cpuall.h | 65 - sim/bpf/decode-be.c | 1131 --------- sim/bpf/decode-be.h | 94 - sim/bpf/decode-le.c | 1131 --------- sim/bpf/decode-le.h | 94 - sim/bpf/decode.h | 37 - sim/bpf/defs-be.h | 383 --- sim/bpf/defs-le.h | 383 --- sim/bpf/eng.h | 23 - sim/bpf/local.mk | 108 +- sim/bpf/mloop.in | 168 -- sim/bpf/sem-be.c | 3207 -------------------------- sim/bpf/sem-le.c | 3207 -------------------------- sim/bpf/sim-if.c | 228 -- sim/bpf/sim-main.h | 25 +- sim/testsuite/bpf/alu.s | 4 +- sim/testsuite/bpf/alu32.s | 6 +- 130 files changed, 5171 insertions(+), 22026 deletions(-) delete mode 100644 cpu/bpf.cpu delete mode 100644 cpu/bpf.opc delete mode 100644 gas/testsuite/gas/bpf/alu-be.dump delete mode 100644 gas/testsuite/gas/bpf/alu-xbpf.d delete mode 100644 gas/testsuite/gas/bpf/alu-xbpf.s delete mode 100644 gas/testsuite/gas/bpf/alu.dump delete mode 100644 gas/testsuite/gas/bpf/alu32-be.dump delete mode 100644 gas/testsuite/gas/bpf/alu32-xbpf.d delete mode 100644 gas/testsuite/gas/bpf/alu32-xbpf.s delete mode 100644 gas/testsuite/gas/bpf/alu32.dump create mode 100644 gas/testsuite/gas/bpf/atomic-be-pseudoc.d delete mode 100644 gas/testsuite/gas/bpf/atomic.dump delete mode 100644 gas/testsuite/gas/bpf/indcall-1.dump delete mode 100644 gas/testsuite/gas/bpf/indcall-bad-1.l delete mode 100644 gas/testsuite/gas/bpf/indcall-bad-1.s create mode 100644 gas/testsuite/gas/bpf/jump-be-pseudoc.d delete mode 100644 gas/testsuite/gas/bpf/jump.dump create mode 100644 gas/testsuite/gas/bpf/jump32-be-pseudoc.d create mode 100644 gas/testsuite/gas/bpf/jump32-be.d delete mode 100644 gas/testsuite/gas/bpf/jump32.dump delete mode 100644 gas/testsuite/gas/bpf/lddw-be.dump delete mode 100644 gas/testsuite/gas/bpf/lddw.dump create mode 100644 gas/testsuite/gas/bpf/mem-be-pseudoc.d delete mode 100644 gas/testsuite/gas/bpf/mem.dump delete mode 100644 gas/testsuite/gas/bpf/pseudoc-normal-be.d delete mode 100644 gas/testsuite/gas/bpf/pseudoc-normal.d delete mode 100644 gas/testsuite/gas/bpf/pseudoc-normal.s create mode 100644 gas/testsuite/gas/bpf/spacing-pseudoc.d create mode 100644 gas/testsuite/gas/bpf/spacing-pseudoc.s create mode 100644 include/opcode/bpf.h delete mode 100644 opcodes/bpf-asm.c delete mode 100644 opcodes/bpf-desc.c delete mode 100644 opcodes/bpf-desc.h delete mode 100644 opcodes/bpf-ibld.c delete mode 100644 opcodes/bpf-opc.h delete mode 100644 sim/bpf/arch.c delete mode 100644 sim/bpf/arch.h delete mode 100644 sim/bpf/bpf-helpers.c delete mode 100644 sim/bpf/bpf-helpers.def delete mode 100644 sim/bpf/bpf-helpers.h create mode 100644 sim/bpf/bpf-sim.c delete mode 100644 sim/bpf/bpf.c delete mode 100644 sim/bpf/cpu.c delete mode 100644 sim/bpf/cpu.h delete mode 100644 sim/bpf/cpuall.h delete mode 100644 sim/bpf/decode-be.c delete mode 100644 sim/bpf/decode-be.h delete mode 100644 sim/bpf/decode-le.c delete mode 100644 sim/bpf/decode-le.h delete mode 100644 sim/bpf/decode.h delete mode 100644 sim/bpf/defs-be.h delete mode 100644 sim/bpf/defs-le.h delete mode 100644 sim/bpf/eng.h delete mode 100644 sim/bpf/mloop.in delete mode 100644 sim/bpf/sem-be.c delete mode 100644 sim/bpf/sem-le.c delete mode 100644 sim/bpf/sim-if.c + git push -u origin upstream-master To github.com:plctlab/patchwork-binutils-gdb.git 178e19707..7bb9f0c2b upstream-master -> upstream-master branch 'upstream-master' set up to track 'origin/upstream-master'. + git checkout master Switched to branch 'master' Your branch is up to date with 'origin/master'. + git merge upstream-master fatal: refusing to merge unrelated histories + git push -u origin master Everything up-to-date branch 'master' set up to track 'origin/master'. + branchname=series51043-patch123757 ++ git branch -a ++ grep 'series51043-patch123757$' + checkbranch= + checkbranchresult=null + '[' null = series51043-patch123757 ']' + git checkout -b series51043-patch123757 Switched to a new branch 'series51043-patch123757' ++ curl https://patchwork.plctlab.org/api/1.2/series/51043/ % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 1416 100 1416 0 0 40457 0 --:--:-- --:--:-- --:--:-- 40457 + series_response='{"id":51043,"url":"https://patchwork.plctlab.org/api/1.2/series/51043/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/list/?series=51043","project":{"id":2,"url":"https://patchwork.plctlab.org/api/1.2/projects/2/","name":"binutils-gdb","link_name":"binutils-gdb","list_id":"binutils.sourceware.org","list_email":"binutils@sourceware.org","web_url":"https://github.com/wangliu-iscas/Patchwork-Bundles/blob/main/binutils-gdb.md","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"name":"[COMMITTED] DesCGENization of the BPF binutils port","date":"2023-07-21T10:33:36","submitter":{"id":82,"url":"https://patchwork.plctlab.org/api/1.2/people/82/","name":"Jose E. Marchesi","email":"jose.marchesi@oracle.com"},"version":1,"total":1,"received_total":1,"received_all":true,"mbox":"https://patchwork.plctlab.org/series/51043/mbox/","cover_letter":null,"patches":[{"id":123757,"url":"https://patchwork.plctlab.org/api/1.2/patches/123757/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230721103336.22880-1-jose.marchesi@oracle.com/","msgid":"<20230721103336.22880-1-jose.marchesi@oracle.com>","list_archive_url":null,"date":"2023-07-21T10:33:36","name":"[COMMITTED] DesCGENization of the BPF binutils port","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230721103336.22880-1-jose.marchesi@oracle.com/mbox/"}]}' ++ jq '.patches[] | (.id|tostring) + "," + .mbox' ++ echo '{"id":51043,"url":"https://patchwork.plctlab.org/api/1.2/series/51043/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/list/?series=51043","project":{"id":2,"url":"https://patchwork.plctlab.org/api/1.2/projects/2/","name":"binutils-gdb","link_name":"binutils-gdb","list_id":"binutils.sourceware.org","list_email":"binutils@sourceware.org","web_url":"https://github.com/wangliu-iscas/Patchwork-Bundles/blob/main/binutils-gdb.md","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"name":"[COMMITTED] DesCGENization of the BPF binutils port","date":"2023-07-21T10:33:36","submitter":{"id":82,"url":"https://patchwork.plctlab.org/api/1.2/people/82/","name":"Jose E. Marchesi","email":"jose.marchesi@oracle.com"},"version":1,"total":1,"received_total":1,"received_all":true,"mbox":"https://patchwork.plctlab.org/series/51043/mbox/","cover_letter":null,"patches":[{"id":123757,"url":"https://patchwork.plctlab.org/api/1.2/patches/123757/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230721103336.22880-1-jose.marchesi@oracle.com/","msgid":"<20230721103336.22880-1-jose.marchesi@oracle.com>","list_archive_url":null,"date":"2023-07-21T10:33:36","name":"[COMMITTED] DesCGENization of the BPF binutils port","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230721103336.22880-1-jose.marchesi@oracle.com/mbox/"}]}' + patchid_patchurl='"123757,https://patchwork.plctlab.org/project/binutils-gdb/patch/20230721103336.22880-1-jose.marchesi@oracle.com/mbox/"' + echo '"123757,https://patchwork.plctlab.org/project/binutils-gdb/patch/20230721103336.22880-1-jose.marchesi@oracle.com/mbox/"' + IFS=, + read -r series_patch_id series_patch_url ++ sed 's/"//g' ++ echo '"123757' + series_patch_id=123757 ++ echo 'https://patchwork.plctlab.org/project/binutils-gdb/patch/20230721103336.22880-1-jose.marchesi@oracle.com/mbox/"' ++ sed 's/"//g' + series_patch_url=https://patchwork.plctlab.org/project/binutils-gdb/patch/20230721103336.22880-1-jose.marchesi@oracle.com/mbox/ ++ git rev-parse HEAD + commitid_before=324998b47364528f407666512015370c12ab83a1 + eval '+++ declare -p bout bret declare -- bout="Applying: DesCGENization of the BPF binutils port .git/rebase-apply/patch:367: indent with spaces. asm_dialect = DIALECT_NORMAL; .git/rebase-apply/patch:369: indent with spaces. asm_dialect = DIALECT_PSEUDOC; .git/rebase-apply/patch:371: indent with spaces. as_fatal (_(\"-mdialect=%s is not valid. Expected normal or pseudoc\"), .git/rebase-apply/patch:372: indent with spaces. arg); .git/rebase-apply/patch:376: indent with spaces. isa_spec = BPF_V1; warning: squelched 646 whitespace errors warning: 651 lines add whitespace errors. Using index info to reconstruct a base tree... M bfd/bfd-in2.h M bfd/libbfd.h M bfd/reloc.c M gas/config/tc-bpf.c M gas/config/tc-bpf.h M gas/configure M gas/configure.ac M gas/doc/c-bpf.texi M gas/testsuite/gas/all/assign-bad-recursive.d M gas/testsuite/gas/all/eqv-dot.d M gas/testsuite/gas/all/gas.exp A gas/testsuite/gas/bpf/alu-be-pseudoc.d M gas/testsuite/gas/bpf/alu-be.d A gas/testsuite/gas/bpf/alu-pseudoc.d A gas/testsuite/gas/bpf/alu-pseudoc.s M gas/testsuite/gas/bpf/alu.d A gas/testsuite/gas/bpf/alu32-be-pseudoc.d M gas/testsuite/gas/bpf/alu32-be.d A gas/testsuite/gas/bpf/alu32-pseudoc.d A gas/testsuite/gas/bpf/alu32-pseudoc.s M gas/testsuite/gas/bpf/alu32.d M gas/testsuite/gas/bpf/atomic-be.d A gas/testsuite/gas/bpf/atomic-pseudoc.d A gas/testsuite/gas/bpf/atomic-pseudoc.s M gas/testsuite/gas/bpf/atomic.d M gas/testsuite/gas/bpf/bpf.exp A gas/testsuite/gas/bpf/indcall-1-pseudoc.d M gas/testsuite/gas/bpf/indcall-1.d M gas/testsuite/gas/bpf/jump-be.d A gas/testsuite/gas/bpf/jump-pseudoc.d M gas/testsuite/gas/bpf/jump.d A gas/testsuite/gas/bpf/jump32-pseudoc.d M gas/testsuite/gas/bpf/jump32.d A gas/testsuite/gas/bpf/lddw-be-pseudoc.d M gas/testsuite/gas/bpf/lddw-be.d A gas/testsuite/gas/bpf/lddw-pseudoc.d M gas/testsuite/gas/bpf/lddw.d M gas/testsuite/gas/bpf/mem-be.d A gas/testsuite/gas/bpf/mem-pseudoc.d A gas/testsuite/gas/bpf/mem-pseudoc.s M gas/testsuite/gas/bpf/mem.d M opcodes/configure M opcodes/disassemble.c Falling back to patching base and 3-way merge... Auto-merging opcodes/disassemble.c Auto-merging opcodes/configure Auto-merging gas/testsuite/gas/bpf/mem.d CONFLICT (content): Merge conflict in gas/testsuite/gas/bpf/mem.d CONFLICT (modify/delete): gas/testsuite/gas/bpf/mem-pseudoc.s deleted in HEAD and modified in DesCGENization of the BPF binutils port. Version DesCGENization of the BPF binutils port of gas/testsuite/gas/bpf/mem-pseudoc.s left in tree. CONFLICT (modify/delete): gas/testsuite/gas/bpf/mem-pseudoc.d deleted in HEAD and modified in DesCGENization of the BPF binutils port. Version DesCGENization of the BPF binutils port of gas/testsuite/gas/bpf/mem-pseudoc.d left in tree. Auto-merging gas/testsuite/gas/bpf/mem-be.d CONFLICT (content): Merge conflict in gas/testsuite/gas/bpf/mem-be.d Auto-merging gas/testsuite/gas/bpf/lddw.d CONFLICT (content): Merge conflict in gas/testsuite/gas/bpf/lddw.d CONFLICT (modify/delete): gas/testsuite/gas/bpf/lddw-pseudoc.d deleted in HEAD and modified in DesCGENization of the BPF binutils port. Version DesCGENization of the BPF binutils port of gas/testsuite/gas/bpf/lddw-pseudoc.d left in tree. Auto-merging gas/testsuite/gas/bpf/lddw-be.d CONFLICT (content): Merge conflict in gas/testsuite/gas/bpf/lddw-be.d CONFLICT (modify/delete): gas/testsuite/gas/bpf/lddw-be-pseudoc.d deleted in HEAD and modified in DesCGENization of the BPF binutils port. Version DesCGENization of the BPF binutils port of gas/testsuite/gas/bpf/lddw-be-pseudoc.d left in tree. Auto-merging gas/testsuite/gas/bpf/jump32.d CONFLICT (content): Merge conflict in gas/testsuite/gas/bpf/jump32.d CONFLICT (modify/delete): gas/testsuite/gas/bpf/jump32-pseudoc.d deleted in HEAD and modified in DesCGENization of the BPF binutils port. Version DesCGENization of the BPF binutils port of gas/testsuite/gas/bpf/jump32-pseudoc.d left in tree. Auto-merging gas/testsuite/gas/bpf/jump.d CONFLICT (content): Merge conflict in gas/testsuite/gas/bpf/jump.d CONFLICT (modify/delete): gas/testsuite/gas/bpf/jump-pseudoc.d deleted in HEAD and modified in DesCGENization of the BPF binutils port. Version DesCGENization of the BPF binutils port of gas/testsuite/gas/bpf/jump-pseudoc.d left in tree. Auto-merging gas/testsuite/gas/bpf/jump-be.d CONFLICT (content): Merge conflict in gas/testsuite/gas/bpf/jump-be.d Auto-merging gas/testsuite/gas/bpf/indcall-1.d CONFLICT (content): Merge conflict in gas/testsuite/gas/bpf/indcall-1.d CONFLICT (modify/delete): gas/testsuite/gas/bpf/indcall-1-pseudoc.d deleted in HEAD and modified in DesCGENization of the BPF binutils port. Version DesCGENization of the BPF binutils port of gas/testsuite/gas/bpf/indcall-1-pseudoc.d left in tree. Auto-merging gas/testsuite/gas/bpf/bpf.exp CONFLICT (content): Merge conflict in gas/testsuite/gas/bpf/bpf.exp Auto-merging gas/testsuite/gas/bpf/atomic.d CONFLICT (content): Merge conflict in gas/testsuite/gas/bpf/atomic.d CONFLICT (modify/delete): gas/testsuite/gas/bpf/atomic-pseudoc.s deleted in HEAD and modified in DesCGENization of the BPF binutils port. Version DesCGENization of the BPF binutils port of gas/testsuite/gas/bpf/atomic-pseudoc.s left in tree. CONFLICT (modify/delete): gas/testsuite/gas/bpf/atomic-pseudoc.d deleted in HEAD and modified in DesCGENization of the BPF binutils port. Version DesCGENization of the BPF binutils port of gas/testsuite/gas/bpf/atomic-pseudoc.d left in tree. Auto-merging gas/testsuite/gas/bpf/atomic-be.d CONFLICT (content): Merge conflict in gas/testsuite/gas/bpf/atomic-be.d Auto-merging gas/testsuite/gas/bpf/alu32.d CONFLICT (content): Merge conflict in gas/testsuite/gas/bpf/alu32.d CONFLICT (modify/delete): gas/testsuite/gas/bpf/alu32-pseudoc.s deleted in HEAD and modified in DesCGENization of the BPF binutils port. Version DesCGENization of the BPF binutils port of gas/testsuite/gas/bpf/alu32-pseudoc.s left in tree. CONFLICT (modify/delete): gas/testsuite/gas/bpf/alu32-pseudoc.d deleted in HEAD and modified in DesCGENization of the BPF binutils port. Version DesCGENization of the BPF binutils port of gas/testsuite/gas/bpf/alu32-pseudoc.d left in tree. Auto-merging gas/testsuite/gas/bpf/alu32-be.d CONFLICT (content): Merge conflict in gas/testsuite/gas/bpf/alu32-be.d CONFLICT (modify/delete): gas/testsuite/gas/bpf/alu32-be-pseudoc.d deleted in HEAD and modified in DesCGENization of the BPF binutils port. Version DesCGENization of the BPF binutils port of gas/testsuite/gas/bpf/alu32-be-pseudoc.d left in tree. Auto-merging gas/testsuite/gas/bpf/alu.d CONFLICT (content): Merge conflict in gas/testsuite/gas/bpf/alu.d CONFLICT (modify/delete): gas/testsuite/gas/bpf/alu-pseudoc.s deleted in HEAD and modified in DesCGENization of the BPF binutils port. Version DesCGENization of the BPF binutils port of gas/testsuite/gas/bpf/alu-pseudoc.s left in tree. CONFLICT (modify/delete): gas/testsuite/gas/bpf/alu-pseudoc.d deleted in HEAD and modified in DesCGENization of the BPF binutils port. Version DesCGENization of the BPF binutils port of gas/testsuite/gas/bpf/alu-pseudoc.d left in tree. Auto-merging gas/testsuite/gas/bpf/alu-be.d CONFLICT (content): Merge conflict in gas/testsuite/gas/bpf/alu-be.d CONFLICT (modify/delete): gas/testsuite/gas/bpf/alu-be-pseudoc.d deleted in HEAD and modified in DesCGENization of the BPF binutils port. Version DesCGENization of the BPF binutils port of gas/testsuite/gas/bpf/alu-be-pseudoc.d left in tree. Auto-merging gas/testsuite/gas/all/gas.exp Auto-merging gas/doc/c-bpf.texi CONFLICT (content): Merge conflict in gas/doc/c-bpf.texi Auto-merging gas/configure.ac Auto-merging gas/configure Auto-merging gas/config/tc-bpf.h CONFLICT (content): Merge conflict in gas/config/tc-bpf.h Auto-merging gas/config/tc-bpf.c CONFLICT (content): Merge conflict in gas/config/tc-bpf.c Auto-merging bfd/reloc.c Auto-merging bfd/libbfd.h Auto-merging bfd/bfd-in2.h CONFLICT (content): Merge conflict in bfd/bfd-in2.h error: Failed to merge in the changes. hint: Use '\''git am --show-current-patch=diff'\'' to see the failed patch Patch failed at 0001 DesCGENization of the BPF binutils port When you have resolved this problem, run \"git am --continue\". If you prefer to skip this patch, run \"git am --skip\" instead. To restore the original branch and stop patching, run \"git am --abort\"." declare -- bret="128" ++ berr='\''++++ git_am https://patchwork.plctlab.org/project/binutils-gdb/patch/20230721103336.22880-1-jose.marchesi@oracle.com/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/binutils-gdb/patch/20230721103336.22880-1-jose.marchesi@oracle.com/mbox/ ++++ curl https://patchwork.plctlab.org/project/binutils-gdb/patch/20230721103336.22880-1-jose.marchesi@oracle.com/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 308k 100 308k 0 0 5064k 0 --:--:-- --:--:-- --:--:-- 5064k +++ bout='\''\'\'''\''Applying: DesCGENization of the BPF binutils port .git/rebase-apply/patch:367: indent with spaces. asm_dialect = DIALECT_NORMAL; .git/rebase-apply/patch:369: indent with spaces. asm_dialect = DIALECT_PSEUDOC; .git/rebase-apply/patch:371: indent with spaces. as_fatal (_("-mdialect=%s is not valid. Expected normal or pseudoc"), .git/rebase-apply/patch:372: indent with spaces. arg); .git/rebase-apply/patch:376: indent with spaces. isa_spec = BPF_V1; warning: squelched 646 whitespace errors warning: 651 lines add whitespace errors. Using index info to reconstruct a base tree... M bfd/bfd-in2.h M bfd/libbfd.h M bfd/reloc.c M gas/config/tc-bpf.c M gas/config/tc-bpf.h M gas/configure M gas/configure.ac M gas/doc/c-bpf.texi M gas/testsuite/gas/all/assign-bad-recursive.d M gas/testsuite/gas/all/eqv-dot.d M gas/testsuite/gas/all/gas.exp A gas/testsuite/gas/bpf/alu-be-pseudoc.d M gas/testsuite/gas/bpf/alu-be.d A gas/testsuite/gas/bpf/alu-pseudoc.d A gas/testsuite/gas/bpf/alu-pseudoc.s M gas/testsuite/gas/bpf/alu.d A gas/testsuite/gas/bpf/alu32-be-pseudoc.d M gas/testsuite/gas/bpf/alu32-be.d A gas/testsuite/gas/bpf/alu32-pseudoc.d A gas/testsuite/gas/bpf/alu32-pseudoc.s M gas/testsuite/gas/bpf/alu32.d M gas/testsuite/gas/bpf/atomic-be.d A gas/testsuite/gas/bpf/atomic-pseudoc.d A gas/testsuite/gas/bpf/atomic-pseudoc.s M gas/testsuite/gas/bpf/atomic.d M gas/testsuite/gas/bpf/bpf.exp A gas/testsuite/gas/bpf/indcall-1-pseudoc.d M gas/testsuite/gas/bpf/indcall-1.d M gas/testsuite/gas/bpf/jump-be.d A gas/testsuite/gas/bpf/jump-pseudoc.d M gas/testsuite/gas/bpf/jump.d A gas/testsuite/gas/bpf/jump32-pseudoc.d M gas/testsuite/gas/bpf/jump32.d A gas/testsuite/gas/bpf/lddw-be-pseudoc.d M gas/testsuite/gas/bpf/lddw-be.d A gas/testsuite/gas/bpf/lddw-pseudoc.d M gas/testsuite/gas/bpf/lddw.d M gas/testsuite/gas/bpf/mem-be.d A gas/testsuite/gas/bpf/mem-pseudoc.d A gas/testsuite/gas/bpf/mem-pseudoc.s M gas/testsuite/gas/bpf/mem.d M opcodes/configure M opcodes/disassemble.c Falling back to patching base and 3-way merge... Auto-merging opcodes/disassemble.c Auto-merging opcodes/configure Auto-merging gas/testsuite/gas/bpf/mem.d CONFLICT (content): Merge conflict in gas/testsuite/gas/bpf/mem.d CONFLICT (modify/delete): gas/testsuite/gas/bpf/mem-pseudoc.s deleted in HEAD and modified in DesCGENization of the BPF binutils port. Version DesCGENization of the BPF binutils port of gas/testsuite/gas/bpf/mem-pseudoc.s left in tree. CONFLICT (modify/delete): gas/testsuite/gas/bpf/mem-pseudoc.d deleted in HEAD and modified in DesCGENization of the BPF binutils port. Version DesCGENization of the BPF binutils port of gas/testsuite/gas/bpf/mem-pseudoc.d left in tree. Auto-merging gas/testsuite/gas/bpf/mem-be.d CONFLICT (content): Merge conflict in gas/testsuite/gas/bpf/mem-be.d Auto-merging gas/testsuite/gas/bpf/lddw.d CONFLICT (content): Merge conflict in gas/testsuite/gas/bpf/lddw.d CONFLICT (modify/delete): gas/testsuite/gas/bpf/lddw-pseudoc.d deleted in HEAD and modified in DesCGENization of the BPF binutils port. Version DesCGENization of the BPF binutils port of gas/testsuite/gas/bpf/lddw-pseudoc.d left in tree. Auto-merging gas/testsuite/gas/bpf/lddw-be.d CONFLICT (content): Merge conflict in gas/testsuite/gas/bpf/lddw-be.d CONFLICT (modify/delete): gas/testsuite/gas/bpf/lddw-be-pseudoc.d deleted in HEAD and modified in DesCGENization of the BPF binutils port. Version DesCGENization of the BPF binutils port of gas/testsuite/gas/bpf/lddw-be-pseudoc.d left in tree. Auto-merging gas/testsuite/gas/bpf/jump32.d CONFLICT (content): Merge conflict in gas/testsuite/gas/bpf/jump32.d CONFLICT (modify/delete): gas/testsuite/gas/bpf/jump32-pseudoc.d deleted in HEAD and modified in DesCGENization of the BPF binutils port. Version DesCGENization of the BPF binutils port of gas/testsuite/gas/bpf/jump32-pseudoc.d left in tree. Auto-merging gas/testsuite/gas/bpf/jump.d CONFLICT (content): Merge conflict in gas/testsuite/gas/bpf/jump.d CONFLICT (modify/delete): gas/testsuite/gas/bpf/jump-pseudoc.d deleted in HEAD and modified in DesCGENization of the BPF binutils port. Version DesCGENization of the BPF binutils port of gas/testsuite/gas/bpf/jump-pseudoc.d left in tree. Auto-merging gas/testsuite/gas/bpf/jump-be.d CONFLICT (content): Merge conflict in gas/testsuite/gas/bpf/jump-be.d Auto-merging gas/testsuite/gas/bpf/indcall-1.d CONFLICT (content): Merge conflict in gas/testsuite/gas/bpf/indcall-1.d CONFLICT (modify/delete): gas/testsuite/gas/bpf/indcall-1-pseudoc.d deleted in HEAD and modified in DesCGENization of the BPF binutils port. Version DesCGENization of the BPF binutils port of gas/testsuite/gas/bpf/indcall-1-pseudoc.d left in tree. Auto-merging gas/testsuite/gas/bpf/bpf.exp CONFLICT (content): Merge conflict in gas/testsuite/gas/bpf/bpf.exp Auto-merging gas/testsuite/gas/bpf/atomic.d CONFLICT (content): Merge conflict in gas/testsuite/gas/bpf/atomic.d CONFLICT (modify/delete): gas/testsuite/gas/bpf/atomic-pseudoc.s deleted in HEAD and modified in DesCGENization of the BPF binutils port. Version DesCGENization of the BPF binutils port of gas/testsuite/gas/bpf/atomic-pseudoc.s left in tree. CONFLICT (modify/delete): gas/testsuite/gas/bpf/atomic-pseudoc.d deleted in HEAD and modified in DesCGENization of the BPF binutils port. Version DesCGENization of the BPF binutils port of gas/testsuite/gas/bpf/atomic-pseudoc.d left in tree. Auto-merging gas/testsuite/gas/bpf/atomic-be.d CONFLICT (content): Merge conflict in gas/testsuite/gas/bpf/atomic-be.d Auto-merging gas/testsuite/gas/bpf/alu32.d CONFLICT (content): Merge conflict in gas/testsuite/gas/bpf/alu32.d CONFLICT (modify/delete): gas/testsuite/gas/bpf/alu32-pseudoc.s deleted in HEAD and modified in DesCGENization of the BPF binutils port. Version DesCGENization of the BPF binutils port of gas/testsuite/gas/bpf/alu32-pseudoc.s left in tree. CONFLICT (modify/delete): gas/testsuite/gas/bpf/alu32-pseudoc.d deleted in HEAD and modified in DesCGENization of the BPF binutils port. Version DesCGENization of the BPF binutils port of gas/testsuite/gas/bpf/alu32-pseudoc.d left in tree. Auto-merging gas/testsuite/gas/bpf/alu32-be.d CONFLICT (content): Merge conflict in gas/testsuite/gas/bpf/alu32-be.d CONFLICT (modify/delete): gas/testsuite/gas/bpf/alu32-be-pseudoc.d deleted in HEAD and modified in DesCGENization of the BPF binutils port. Version DesCGENization of the BPF binutils port of gas/testsuite/gas/bpf/alu32-be-pseudoc.d left in tree. Auto-merging gas/testsuite/gas/bpf/alu.d CONFLICT (content): Merge conflict in gas/testsuite/gas/bpf/alu.d CONFLICT (modify/delete): gas/testsuite/gas/bpf/alu-pseudoc.s deleted in HEAD and modified in DesCGENization of the BPF binutils port. Version DesCGENization of the BPF binutils port of gas/testsuite/gas/bpf/alu-pseudoc.s left in tree. CONFLICT (modify/delete): gas/testsuite/gas/bpf/alu-pseudoc.d deleted in HEAD and modified in DesCGENization of the BPF binutils port. Version DesCGENization of the BPF binutils port of gas/testsuite/gas/bpf/alu-pseudoc.d left in tree. Auto-merging gas/testsuite/gas/bpf/alu-be.d CONFLICT (content): Merge conflict in gas/testsuite/gas/bpf/alu-be.d CONFLICT (modify/delete): gas/testsuite/gas/bpf/alu-be-pseudoc.d deleted in HEAD and modified in DesCGENization of the BPF binutils port. Version DesCGENization of the BPF binutils port of gas/testsuite/gas/bpf/alu-be-pseudoc.d left in tree. Auto-merging gas/testsuite/gas/all/gas.exp Auto-merging gas/doc/c-bpf.texi CONFLICT (content): Merge conflict in gas/doc/c-bpf.texi Auto-merging gas/configure.ac Auto-merging gas/configure Auto-merging gas/config/tc-bpf.h CONFLICT (content): Merge conflict in gas/config/tc-bpf.h Auto-merging gas/config/tc-bpf.c CONFLICT (content): Merge conflict in gas/config/tc-bpf.c Auto-merging bfd/reloc.c Auto-merging bfd/libbfd.h Auto-merging bfd/bfd-in2.h CONFLICT (content): Merge conflict in bfd/bfd-in2.h error: Failed to merge in the changes. hint: Use '\''\'\'''\''\'\''\'\'''\'''\''\'\'''\''git am --show-current-patch=diff'\''\'\'''\''\'\''\'\'''\'''\''\'\'''\'' to see the failed patch Patch failed at 0001 DesCGENization of the BPF binutils port When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort".'\''\'\'''\'' +++ bret=128'\'' ++ declare -p berr declare -- berr="++++ git_am https://patchwork.plctlab.org/project/binutils-gdb/patch/20230721103336.22880-1-jose.marchesi@oracle.com/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/binutils-gdb/patch/20230721103336.22880-1-jose.marchesi@oracle.com/mbox/ ++++ curl https://patchwork.plctlab.org/project/binutils-gdb/patch/20230721103336.22880-1-jose.marchesi@oracle.com/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 308k 100 308k 0 0 5064k 0 --:--:-- --:--:-- --:--:-- 5064k +++ bout='\''Applying: DesCGENization of the BPF binutils port .git/rebase-apply/patch:367: indent with spaces. asm_dialect = DIALECT_NORMAL; .git/rebase-apply/patch:369: indent with spaces. asm_dialect = DIALECT_PSEUDOC; .git/rebase-apply/patch:371: indent with spaces. as_fatal (_(\"-mdialect=%s is not valid. Expected normal or pseudoc\"), .git/rebase-apply/patch:372: indent with spaces. arg); .git/rebase-apply/patch:376: indent with spaces. isa_spec = BPF_V1; warning: squelched 646 whitespace errors warning: 651 lines add whitespace errors. Using index info to reconstruct a base tree... M bfd/bfd-in2.h M bfd/libbfd.h M bfd/reloc.c M gas/config/tc-bpf.c M gas/config/tc-bpf.h M gas/configure M gas/configure.ac M gas/doc/c-bpf.texi M gas/testsuite/gas/all/assign-bad-recursive.d M gas/testsuite/gas/all/eqv-dot.d M gas/testsuite/gas/all/gas.exp A gas/testsuite/gas/bpf/alu-be-pseudoc.d M gas/testsuite/gas/bpf/alu-be.d A gas/testsuite/gas/bpf/alu-pseudoc.d A gas/testsuite/gas/bpf/alu-pseudoc.s M gas/testsuite/gas/bpf/alu.d A gas/testsuite/gas/bpf/alu32-be-pseudoc.d M gas/testsuite/gas/bpf/alu32-be.d A gas/testsuite/gas/bpf/alu32-pseudoc.d A gas/testsuite/gas/bpf/alu32-pseudoc.s M gas/testsuite/gas/bpf/alu32.d M gas/testsuite/gas/bpf/atomic-be.d A gas/testsuite/gas/bpf/atomic-pseudoc.d A gas/testsuite/gas/bpf/atomic-pseudoc.s M gas/testsuite/gas/bpf/atomic.d M gas/testsuite/gas/bpf/bpf.exp A gas/testsuite/gas/bpf/indcall-1-pseudoc.d M gas/testsuite/gas/bpf/indcall-1.d M gas/testsuite/gas/bpf/jump-be.d A gas/testsuite/gas/bpf/jump-pseudoc.d M gas/testsuite/gas/bpf/jump.d A gas/testsuite/gas/bpf/jump32-pseudoc.d M gas/testsuite/gas/bpf/jump32.d A gas/testsuite/gas/bpf/lddw-be-pseudoc.d M gas/testsuite/gas/bpf/lddw-be.d A gas/testsuite/gas/bpf/lddw-pseudoc.d M gas/testsuite/gas/bpf/lddw.d M gas/testsuite/gas/bpf/mem-be.d A gas/testsuite/gas/bpf/mem-pseudoc.d A gas/testsuite/gas/bpf/mem-pseudoc.s M gas/testsuite/gas/bpf/mem.d M opcodes/configure M opcodes/disassemble.c Falling back to patching base and 3-way merge... Auto-merging opcodes/disassemble.c Auto-merging opcodes/configure Auto-merging gas/testsuite/gas/bpf/mem.d CONFLICT (content): Merge conflict in gas/testsuite/gas/bpf/mem.d CONFLICT (modify/delete): gas/testsuite/gas/bpf/mem-pseudoc.s deleted in HEAD and modified in DesCGENization of the BPF binutils port. Version DesCGENization of the BPF binutils port of gas/testsuite/gas/bpf/mem-pseudoc.s left in tree. CONFLICT (modify/delete): gas/testsuite/gas/bpf/mem-pseudoc.d deleted in HEAD and modified in DesCGENization of the BPF binutils port. Version DesCGENization of the BPF binutils port of gas/testsuite/gas/bpf/mem-pseudoc.d left in tree. Auto-merging gas/testsuite/gas/bpf/mem-be.d CONFLICT (content): Merge conflict in gas/testsuite/gas/bpf/mem-be.d Auto-merging gas/testsuite/gas/bpf/lddw.d CONFLICT (content): Merge conflict in gas/testsuite/gas/bpf/lddw.d CONFLICT (modify/delete): gas/testsuite/gas/bpf/lddw-pseudoc.d deleted in HEAD and modified in DesCGENization of the BPF binutils port. Version DesCGENization of the BPF binutils port of gas/testsuite/gas/bpf/lddw-pseudoc.d left in tree. Auto-merging gas/testsuite/gas/bpf/lddw-be.d CONFLICT (content): Merge conflict in gas/testsuite/gas/bpf/lddw-be.d CONFLICT (modify/delete): gas/testsuite/gas/bpf/lddw-be-pseudoc.d deleted in HEAD and modified in DesCGENization of the BPF binutils port. Version DesCGENization of the BPF binutils port of gas/testsuite/gas/bpf/lddw-be-pseudoc.d left in tree. Auto-merging gas/testsuite/gas/bpf/jump32.d CONFLICT (content): Merge conflict in gas/testsuite/gas/bpf/jump32.d CONFLICT (modify/delete): gas/testsuite/gas/bpf/jump32-pseudoc.d deleted in HEAD and modified in DesCGENization of the BPF binutils port. Version DesCGENization of the BPF binutils port of gas/testsuite/gas/bpf/jump32-pseudoc.d left in tree. Auto-merging gas/testsuite/gas/bpf/jump.d CONFLICT (content): Merge conflict in gas/testsuite/gas/bpf/jump.d CONFLICT (modify/delete): gas/testsuite/gas/bpf/jump-pseudoc.d deleted in HEAD and modified in DesCGENization of the BPF binutils port. Version DesCGENization of the BPF binutils port of gas/testsuite/gas/bpf/jump-pseudoc.d left in tree. Auto-merging gas/testsuite/gas/bpf/jump-be.d CONFLICT (content): Merge conflict in gas/testsuite/gas/bpf/jump-be.d Auto-merging gas/testsuite/gas/bpf/indcall-1.d CONFLICT (content): Merge conflict in gas/testsuite/gas/bpf/indcall-1.d CONFLICT (modify/delete): gas/testsuite/gas/bpf/indcall-1-pseudoc.d deleted in HEAD and modified in DesCGENization of the BPF binutils port. Version DesCGENization of the BPF binutils port of gas/testsuite/gas/bpf/indcall-1-pseudoc.d left in tree. Auto-merging gas/testsuite/gas/bpf/bpf.exp CONFLICT (content): Merge conflict in gas/testsuite/gas/bpf/bpf.exp Auto-merging gas/testsuite/gas/bpf/atomic.d CONFLICT (content): Merge conflict in gas/testsuite/gas/bpf/atomic.d CONFLICT (modify/delete): gas/testsuite/gas/bpf/atomic-pseudoc.s deleted in HEAD and modified in DesCGENization of the BPF binutils port. Version DesCGENization of the BPF binutils port of gas/testsuite/gas/bpf/atomic-pseudoc.s left in tree. CONFLICT (modify/delete): gas/testsuite/gas/bpf/atomic-pseudoc.d deleted in HEAD and modified in DesCGENization of the BPF binutils port. Version DesCGENization of the BPF binutils port of gas/testsuite/gas/bpf/atomic-pseudoc.d left in tree. Auto-merging gas/testsuite/gas/bpf/atomic-be.d CONFLICT (content): Merge conflict in gas/testsuite/gas/bpf/atomic-be.d Auto-merging gas/testsuite/gas/bpf/alu32.d CONFLICT (content): Merge conflict in gas/testsuite/gas/bpf/alu32.d CONFLICT (modify/delete): gas/testsuite/gas/bpf/alu32-pseudoc.s deleted in HEAD and modified in DesCGENization of the BPF binutils port. Version DesCGENization of the BPF binutils port of gas/testsuite/gas/bpf/alu32-pseudoc.s left in tree. CONFLICT (modify/delete): gas/testsuite/gas/bpf/alu32-pseudoc.d deleted in HEAD and modified in DesCGENization of the BPF binutils port. Version DesCGENization of the BPF binutils port of gas/testsuite/gas/bpf/alu32-pseudoc.d left in tree. Auto-merging gas/testsuite/gas/bpf/alu32-be.d CONFLICT (content): Merge conflict in gas/testsuite/gas/bpf/alu32-be.d CONFLICT (modify/delete): gas/testsuite/gas/bpf/alu32-be-pseudoc.d deleted in HEAD and modified in DesCGENization of the BPF binutils port. Version DesCGENization of the BPF binutils port of gas/testsuite/gas/bpf/alu32-be-pseudoc.d left in tree. Auto-merging gas/testsuite/gas/bpf/alu.d CONFLICT (content): Merge conflict in gas/testsuite/gas/bpf/alu.d CONFLICT (modify/delete): gas/testsuite/gas/bpf/alu-pseudoc.s deleted in HEAD and modified in DesCGENization of the BPF binutils port. Version DesCGENization of the BPF binutils port of gas/testsuite/gas/bpf/alu-pseudoc.s left in tree. CONFLICT (modify/delete): gas/testsuite/gas/bpf/alu-pseudoc.d deleted in HEAD and modified in DesCGENization of the BPF binutils port. Version DesCGENization of the BPF binutils port of gas/testsuite/gas/bpf/alu-pseudoc.d left in tree. Auto-merging gas/testsuite/gas/bpf/alu-be.d CONFLICT (content): Merge conflict in gas/testsuite/gas/bpf/alu-be.d CONFLICT (modify/delete): gas/testsuite/gas/bpf/alu-be-pseudoc.d deleted in HEAD and modified in DesCGENization of the BPF binutils port. Version DesCGENization of the BPF binutils port of gas/testsuite/gas/bpf/alu-be-pseudoc.d left in tree. Auto-merging gas/testsuite/gas/all/gas.exp Auto-merging gas/doc/c-bpf.texi CONFLICT (content): Merge conflict in gas/doc/c-bpf.texi Auto-merging gas/configure.ac Auto-merging gas/configure Auto-merging gas/config/tc-bpf.h CONFLICT (content): Merge conflict in gas/config/tc-bpf.h Auto-merging gas/config/tc-bpf.c CONFLICT (content): Merge conflict in gas/config/tc-bpf.c Auto-merging bfd/reloc.c Auto-merging bfd/libbfd.h Auto-merging bfd/bfd-in2.h CONFLICT (content): Merge conflict in bfd/bfd-in2.h error: Failed to merge in the changes. hint: Use '\''\\'\'''\''git am --show-current-patch=diff'\''\\'\'''\'' to see the failed patch Patch failed at 0001 DesCGENization of the BPF binutils port When you have resolved this problem, run \"git am --continue\". If you prefer to skip this patch, run \"git am --skip\" instead. To restore the original branch and stop patching, run \"git am --abort\".'\'' +++ bret=128"' ++ +++ declare -p bout bret /tmp/jenkins11257582287573373425.sh: line 124: +++: command not found ++ declare -- 'bout=Applying: DesCGENization of the BPF binutils port .git/rebase-apply/patch:367: indent with spaces. asm_dialect = DIALECT_NORMAL; .git/rebase-apply/patch:369: indent with spaces. asm_dialect = DIALECT_PSEUDOC; .git/rebase-apply/patch:371: indent with spaces. as_fatal (_("-mdialect=%s is not valid. Expected normal or pseudoc"), .git/rebase-apply/patch:372: indent with spaces. arg); .git/rebase-apply/patch:376: indent with spaces. isa_spec = BPF_V1; warning: squelched 646 whitespace errors warning: 651 lines add whitespace errors. Using index info to reconstruct a base tree... M bfd/bfd-in2.h M bfd/libbfd.h M bfd/reloc.c M gas/config/tc-bpf.c M gas/config/tc-bpf.h M gas/configure M gas/configure.ac M gas/doc/c-bpf.texi M gas/testsuite/gas/all/assign-bad-recursive.d M gas/testsuite/gas/all/eqv-dot.d M gas/testsuite/gas/all/gas.exp A gas/testsuite/gas/bpf/alu-be-pseudoc.d M gas/testsuite/gas/bpf/alu-be.d A gas/testsuite/gas/bpf/alu-pseudoc.d A gas/testsuite/gas/bpf/alu-pseudoc.s M gas/testsuite/gas/bpf/alu.d A gas/testsuite/gas/bpf/alu32-be-pseudoc.d M gas/testsuite/gas/bpf/alu32-be.d A gas/testsuite/gas/bpf/alu32-pseudoc.d A gas/testsuite/gas/bpf/alu32-pseudoc.s M gas/testsuite/gas/bpf/alu32.d M gas/testsuite/gas/bpf/atomic-be.d A gas/testsuite/gas/bpf/atomic-pseudoc.d A gas/testsuite/gas/bpf/atomic-pseudoc.s M gas/testsuite/gas/bpf/atomic.d M gas/testsuite/gas/bpf/bpf.exp A gas/testsuite/gas/bpf/indcall-1-pseudoc.d M gas/testsuite/gas/bpf/indcall-1.d M gas/testsuite/gas/bpf/jump-be.d A gas/testsuite/gas/bpf/jump-pseudoc.d M gas/testsuite/gas/bpf/jump.d A gas/testsuite/gas/bpf/jump32-pseudoc.d M gas/testsuite/gas/bpf/jump32.d A gas/testsuite/gas/bpf/lddw-be-pseudoc.d M gas/testsuite/gas/bpf/lddw-be.d A gas/testsuite/gas/bpf/lddw-pseudoc.d M gas/testsuite/gas/bpf/lddw.d M gas/testsuite/gas/bpf/mem-be.d A gas/testsuite/gas/bpf/mem-pseudoc.d A gas/testsuite/gas/bpf/mem-pseudoc.s M gas/testsuite/gas/bpf/mem.d M opcodes/configure M opcodes/disassemble.c Falling back to patching base and 3-way merge... Auto-merging opcodes/disassemble.c Auto-merging opcodes/configure Auto-merging gas/testsuite/gas/bpf/mem.d CONFLICT (content): Merge conflict in gas/testsuite/gas/bpf/mem.d CONFLICT (modify/delete): gas/testsuite/gas/bpf/mem-pseudoc.s deleted in HEAD and modified in DesCGENization of the BPF binutils port. Version DesCGENization of the BPF binutils port of gas/testsuite/gas/bpf/mem-pseudoc.s left in tree. CONFLICT (modify/delete): gas/testsuite/gas/bpf/mem-pseudoc.d deleted in HEAD and modified in DesCGENization of the BPF binutils port. Version DesCGENization of the BPF binutils port of gas/testsuite/gas/bpf/mem-pseudoc.d left in tree. Auto-merging gas/testsuite/gas/bpf/mem-be.d CONFLICT (content): Merge conflict in gas/testsuite/gas/bpf/mem-be.d Auto-merging gas/testsuite/gas/bpf/lddw.d CONFLICT (content): Merge conflict in gas/testsuite/gas/bpf/lddw.d CONFLICT (modify/delete): gas/testsuite/gas/bpf/lddw-pseudoc.d deleted in HEAD and modified in DesCGENization of the BPF binutils port. Version DesCGENization of the BPF binutils port of gas/testsuite/gas/bpf/lddw-pseudoc.d left in tree. Auto-merging gas/testsuite/gas/bpf/lddw-be.d CONFLICT (content): Merge conflict in gas/testsuite/gas/bpf/lddw-be.d CONFLICT (modify/delete): gas/testsuite/gas/bpf/lddw-be-pseudoc.d deleted in HEAD and modified in DesCGENization of the BPF binutils port. Version DesCGENization of the BPF binutils port of gas/testsuite/gas/bpf/lddw-be-pseudoc.d left in tree. Auto-merging gas/testsuite/gas/bpf/jump32.d CONFLICT (content): Merge conflict in gas/testsuite/gas/bpf/jump32.d CONFLICT (modify/delete): gas/testsuite/gas/bpf/jump32-pseudoc.d deleted in HEAD and modified in DesCGENization of the BPF binutils port. Version DesCGENization of the BPF binutils port of gas/testsuite/gas/bpf/jump32-pseudoc.d left in tree. Auto-merging gas/testsuite/gas/bpf/jump.d CONFLICT (content): Merge conflict in gas/testsuite/gas/bpf/jump.d CONFLICT (modify/delete): gas/testsuite/gas/bpf/jump-pseudoc.d deleted in HEAD and modified in DesCGENization of the BPF binutils port. Version DesCGENization of the BPF binutils port of gas/testsuite/gas/bpf/jump-pseudoc.d left in tree. Auto-merging gas/testsuite/gas/bpf/jump-be.d CONFLICT (content): Merge conflict in gas/testsuite/gas/bpf/jump-be.d Auto-merging gas/testsuite/gas/bpf/indcall-1.d CONFLICT (content): Merge conflict in gas/testsuite/gas/bpf/indcall-1.d CONFLICT (modify/delete): gas/testsuite/gas/bpf/indcall-1-pseudoc.d deleted in HEAD and modified in DesCGENization of the BPF binutils port. Version DesCGENization of the BPF binutils port of gas/testsuite/gas/bpf/indcall-1-pseudoc.d left in tree. Auto-merging gas/testsuite/gas/bpf/bpf.exp CONFLICT (content): Merge conflict in gas/testsuite/gas/bpf/bpf.exp Auto-merging gas/testsuite/gas/bpf/atomic.d CONFLICT (content): Merge conflict in gas/testsuite/gas/bpf/atomic.d CONFLICT (modify/delete): gas/testsuite/gas/bpf/atomic-pseudoc.s deleted in HEAD and modified in DesCGENization of the BPF binutils port. Version DesCGENization of the BPF binutils port of gas/testsuite/gas/bpf/atomic-pseudoc.s left in tree. CONFLICT (modify/delete): gas/testsuite/gas/bpf/atomic-pseudoc.d deleted in HEAD and modified in DesCGENization of the BPF binutils port. Version DesCGENization of the BPF binutils port of gas/testsuite/gas/bpf/atomic-pseudoc.d left in tree. Auto-merging gas/testsuite/gas/bpf/atomic-be.d CONFLICT (content): Merge conflict in gas/testsuite/gas/bpf/atomic-be.d Auto-merging gas/testsuite/gas/bpf/alu32.d CONFLICT (content): Merge conflict in gas/testsuite/gas/bpf/alu32.d CONFLICT (modify/delete): gas/testsuite/gas/bpf/alu32-pseudoc.s deleted in HEAD and modified in DesCGENization of the BPF binutils port. Version DesCGENization of the BPF binutils port of gas/testsuite/gas/bpf/alu32-pseudoc.s left in tree. CONFLICT (modify/delete): gas/testsuite/gas/bpf/alu32-pseudoc.d deleted in HEAD and modified in DesCGENization of the BPF binutils port. Version DesCGENization of the BPF binutils port of gas/testsuite/gas/bpf/alu32-pseudoc.d left in tree. Auto-merging gas/testsuite/gas/bpf/alu32-be.d CONFLICT (content): Merge conflict in gas/testsuite/gas/bpf/alu32-be.d CONFLICT (modify/delete): gas/testsuite/gas/bpf/alu32-be-pseudoc.d deleted in HEAD and modified in DesCGENization of the BPF binutils port. Version DesCGENization of the BPF binutils port of gas/testsuite/gas/bpf/alu32-be-pseudoc.d left in tree. Auto-merging gas/testsuite/gas/bpf/alu.d CONFLICT (content): Merge conflict in gas/testsuite/gas/bpf/alu.d CONFLICT (modify/delete): gas/testsuite/gas/bpf/alu-pseudoc.s deleted in HEAD and modified in DesCGENization of the BPF binutils port. Version DesCGENization of the BPF binutils port of gas/testsuite/gas/bpf/alu-pseudoc.s left in tree. CONFLICT (modify/delete): gas/testsuite/gas/bpf/alu-pseudoc.d deleted in HEAD and modified in DesCGENization of the BPF binutils port. Version DesCGENization of the BPF binutils port of gas/testsuite/gas/bpf/alu-pseudoc.d left in tree. Auto-merging gas/testsuite/gas/bpf/alu-be.d CONFLICT (content): Merge conflict in gas/testsuite/gas/bpf/alu-be.d CONFLICT (modify/delete): gas/testsuite/gas/bpf/alu-be-pseudoc.d deleted in HEAD and modified in DesCGENization of the BPF binutils port. Version DesCGENization of the BPF binutils port of gas/testsuite/gas/bpf/alu-be-pseudoc.d left in tree. Auto-merging gas/testsuite/gas/all/gas.exp Auto-merging gas/doc/c-bpf.texi CONFLICT (content): Merge conflict in gas/doc/c-bpf.texi Auto-merging gas/configure.ac Auto-merging gas/configure Auto-merging gas/config/tc-bpf.h CONFLICT (content): Merge conflict in gas/config/tc-bpf.h Auto-merging gas/config/tc-bpf.c CONFLICT (content): Merge conflict in gas/config/tc-bpf.c Auto-merging bfd/reloc.c Auto-merging bfd/libbfd.h Auto-merging bfd/bfd-in2.h CONFLICT (content): Merge conflict in bfd/bfd-in2.h error: Failed to merge in the changes. hint: Use '\''git am --show-current-patch=diff'\'' to see the failed patch Patch failed at 0001 DesCGENization of the BPF binutils port When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort".' ++ declare -- bret=128 ++ ++ 'berr=++++ git_am https://patchwork.plctlab.org/project/binutils-gdb/patch/20230721103336.22880-1-jose.marchesi@oracle.com/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/binutils-gdb/patch/20230721103336.22880-1-jose.marchesi@oracle.com/mbox/ ++++ curl https://patchwork.plctlab.org/project/binutils-gdb/patch/20230721103336.22880-1-jose.marchesi@oracle.com/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 308k 100 308k 0 0 5064k 0 --:--:-- --:--:-- --:--:-- 5064k +++ bout='\''Applying: DesCGENization of the BPF binutils port .git/rebase-apply/patch:367: indent with spaces. asm_dialect = DIALECT_NORMAL; .git/rebase-apply/patch:369: indent with spaces. asm_dialect = DIALECT_PSEUDOC; .git/rebase-apply/patch:371: indent with spaces. as_fatal (_("-mdialect=%s is not valid. Expected normal or pseudoc"), .git/rebase-apply/patch:372: indent with spaces. arg); .git/rebase-apply/patch:376: indent with spaces. isa_spec = BPF_V1; warning: squelched 646 whitespace errors warning: 651 lines add whitespace errors. Using index info to reconstruct a base tree... M bfd/bfd-in2.h M bfd/libbfd.h M bfd/reloc.c M gas/config/tc-bpf.c M gas/config/tc-bpf.h M gas/configure M gas/configure.ac M gas/doc/c-bpf.texi M gas/testsuite/gas/all/assign-bad-recursive.d M gas/testsuite/gas/all/eqv-dot.d M gas/testsuite/gas/all/gas.exp A gas/testsuite/gas/bpf/alu-be-pseudoc.d M gas/testsuite/gas/bpf/alu-be.d A gas/testsuite/gas/bpf/alu-pseudoc.d A gas/testsuite/gas/bpf/alu-pseudoc.s M gas/testsuite/gas/bpf/alu.d A gas/testsuite/gas/bpf/alu32-be-pseudoc.d M gas/testsuite/gas/bpf/alu32-be.d A gas/testsuite/gas/bpf/alu32-pseudoc.d A gas/testsuite/gas/bpf/alu32-pseudoc.s M gas/testsuite/gas/bpf/alu32.d M gas/testsuite/gas/bpf/atomic-be.d A gas/testsuite/gas/bpf/atomic-pseudoc.d A gas/testsuite/gas/bpf/atomic-pseudoc.s M gas/testsuite/gas/bpf/atomic.d M gas/testsuite/gas/bpf/bpf.exp A gas/testsuite/gas/bpf/indcall-1-pseudoc.d M gas/testsuite/gas/bpf/indcall-1.d M gas/testsuite/gas/bpf/jump-be.d A gas/testsuite/gas/bpf/jump-pseudoc.d M gas/testsuite/gas/bpf/jump.d A gas/testsuite/gas/bpf/jump32-pseudoc.d M gas/testsuite/gas/bpf/jump32.d A gas/testsuite/gas/bpf/lddw-be-pseudoc.d M gas/testsuite/gas/bpf/lddw-be.d A gas/testsuite/gas/bpf/lddw-pseudoc.d M gas/testsuite/gas/bpf/lddw.d M gas/testsuite/gas/bpf/mem-be.d A gas/testsuite/gas/bpf/mem-pseudoc.d A gas/testsuite/gas/bpf/mem-pseudoc.s M gas/testsuite/gas/bpf/mem.d M opcodes/configure M opcodes/disassemble.c Falling back to patching base and 3-way merge... Auto-merging opcodes/disassemble.c Auto-merging opcodes/configure Auto-merging gas/testsuite/gas/bpf/mem.d CONFLICT (content): Merge conflict in gas/testsuite/gas/bpf/mem.d CONFLICT (modify/delete): gas/testsuite/gas/bpf/mem-pseudoc.s deleted in HEAD and modified in DesCGENization of the BPF binutils port. Version DesCGENization of the BPF binutils port of gas/testsuite/gas/bpf/mem-pseudoc.s left in tree. CONFLICT (modify/delete): gas/testsuite/gas/bpf/mem-pseudoc.d deleted in HEAD and modified in DesCGENization of the BPF binutils port. Version DesCGENization of the BPF binutils port of gas/testsuite/gas/bpf/mem-pseudoc.d left in tree. Auto-merging gas/testsuite/gas/bpf/mem-be.d CONFLICT (content): Merge conflict in gas/testsuite/gas/bpf/mem-be.d Auto-merging gas/testsuite/gas/bpf/lddw.d CONFLICT (content): Merge conflict in gas/testsuite/gas/bpf/lddw.d CONFLICT (modify/delete): gas/testsuite/gas/bpf/lddw-pseudoc.d deleted in HEAD and modified in DesCGENization of the BPF binutils port. Version DesCGENization of the BPF binutils port of gas/testsuite/gas/bpf/lddw-pseudoc.d left in tree. Auto-merging gas/testsuite/gas/bpf/lddw-be.d CONFLICT (content): Merge conflict in gas/testsuite/gas/bpf/lddw-be.d CONFLICT (modify/delete): gas/testsuite/gas/bpf/lddw-be-pseudoc.d deleted in HEAD and modified in DesCGENization of the BPF binutils port. Version DesCGENization of the BPF binutils port of gas/testsuite/gas/bpf/lddw-be-pseudoc.d left in tree. Auto-merging gas/testsuite/gas/bpf/jump32.d CONFLICT (content): Merge conflict in gas/testsuite/gas/bpf/jump32.d CONFLICT (modify/delete): gas/testsuite/gas/bpf/jump32-pseudoc.d deleted in HEAD and modified in DesCGENization of the BPF binutils port. Version DesCGENization of the BPF binutils port of gas/testsuite/gas/bpf/jump32-pseudoc.d left in tree. Auto-merging gas/testsuite/gas/bpf/jump.d CONFLICT (content): Merge conflict in gas/testsuite/gas/bpf/jump.d CONFLICT (modify/delete): gas/testsuite/gas/bpf/jump-pseudoc.d deleted in HEAD and modified in DesCGENization of the BPF binutils port. Version DesCGENization of the BPF binutils port of gas/testsuite/gas/bpf/jump-pseudoc.d left in tree. Auto-merging gas/testsuite/gas/bpf/jump-be.d CONFLICT (content): Merge conflict in gas/testsuite/gas/bpf/jump-be.d Auto-merging gas/testsuite/gas/bpf/indcall-1.d CONFLICT (content): Merge conflict in gas/testsuite/gas/bpf/indcall-1.d CONFLICT (modify/delete): gas/testsuite/gas/bpf/indcall-1-pseudoc.d deleted in HEAD and modified in DesCGENization of the BPF binutils port. Version DesCGENization of the BPF binutils port of gas/testsuite/gas/bpf/indcall-1-pseudoc.d left in tree. Auto-merging gas/testsuite/gas/bpf/bpf.exp CONFLICT (content): Merge conflict in gas/testsuite/gas/bpf/bpf.exp Auto-merging gas/testsuite/gas/bpf/atomic.d CONFLICT (content): Merge conflict in gas/testsuite/gas/bpf/atomic.d CONFLICT (modify/delete): gas/testsuite/gas/bpf/atomic-pseudoc.s deleted in HEAD and modified in DesCGENization of the BPF binutils port. Version DesCGENization of the BPF binutils port of gas/testsuite/gas/bpf/atomic-pseudoc.s left in tree. CONFLICT (modify/delete): gas/testsuite/gas/bpf/atomic-pseudoc.d deleted in HEAD and modified in DesCGENization of the BPF binutils port. Version DesCGENization of the BPF binutils port of gas/testsuite/gas/bpf/atomic-pseudoc.d left in tree. Auto-merging gas/testsuite/gas/bpf/atomic-be.d CONFLICT (content): Merge conflict in gas/testsuite/gas/bpf/atomic-be.d Auto-merging gas/testsuite/gas/bpf/alu32.d CONFLICT (content): Merge conflict in gas/testsuite/gas/bpf/alu32.d CONFLICT (modify/delete): gas/testsuite/gas/bpf/alu32-pseudoc.s deleted in HEAD and modified in DesCGENization of the BPF binutils port. Version DesCGENization of the BPF binutils port of gas/testsuite/gas/bpf/alu32-pseudoc.s left in tree. CONFLICT (modify/delete): gas/testsuite/gas/bpf/alu32-pseudoc.d deleted in HEAD and modified in DesCGENization of the BPF binutils port. Version DesCGENization of the BPF binutils port of gas/testsuite/gas/bpf/alu32-pseudoc.d left in tree. Auto-merging gas/testsuite/gas/bpf/alu32-be.d CONFLICT (content): Merge conflict in gas/testsuite/gas/bpf/alu32-be.d CONFLICT (modify/delete): gas/testsuite/gas/bpf/alu32-be-pseudoc.d deleted in HEAD and modified in DesCGENization of the BPF binutils port. Version DesCGENization of the BPF binutils port of gas/testsuite/gas/bpf/alu32-be-pseudoc.d left in tree. Auto-merging gas/testsuite/gas/bpf/alu.d CONFLICT (content): Merge conflict in gas/testsuite/gas/bpf/alu.d CONFLICT (modify/delete): gas/testsuite/gas/bpf/alu-pseudoc.s deleted in HEAD and modified in DesCGENization of the BPF binutils port. Version DesCGENization of the BPF binutils port of gas/testsuite/gas/bpf/alu-pseudoc.s left in tree. CONFLICT (modify/delete): gas/testsuite/gas/bpf/alu-pseudoc.d deleted in HEAD and modified in DesCGENization of the BPF binutils port. Version DesCGENization of the BPF binutils port of gas/testsuite/gas/bpf/alu-pseudoc.d left in tree. Auto-merging gas/testsuite/gas/bpf/alu-be.d CONFLICT (content): Merge conflict in gas/testsuite/gas/bpf/alu-be.d CONFLICT (modify/delete): gas/testsuite/gas/bpf/alu-be-pseudoc.d deleted in HEAD and modified in DesCGENization of the BPF binutils port. Version DesCGENization of the BPF binutils port of gas/testsuite/gas/bpf/alu-be-pseudoc.d left in tree. Auto-merging gas/testsuite/gas/all/gas.exp Auto-merging gas/doc/c-bpf.texi CONFLICT (content): Merge conflict in gas/doc/c-bpf.texi Auto-merging gas/configure.ac Auto-merging gas/configure Auto-merging gas/config/tc-bpf.h CONFLICT (content): Merge conflict in gas/config/tc-bpf.h Auto-merging gas/config/tc-bpf.c CONFLICT (content): Merge conflict in gas/config/tc-bpf.c Auto-merging bfd/reloc.c Auto-merging bfd/libbfd.h Auto-merging bfd/bfd-in2.h CONFLICT (content): Merge conflict in bfd/bfd-in2.h error: Failed to merge in the changes. hint: Use '\''\'\'''\''git am --show-current-patch=diff'\''\'\'''\'' to see the failed patch Patch failed at 0001 DesCGENization of the BPF binutils port When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort".'\'' +++ bret=128' /tmp/jenkins11257582287573373425.sh: line 381: ++: command not found ++ ++ declare -p berr /tmp/jenkins11257582287573373425.sh: line 382: ++: command not found ++ declare -- 'berr=++++ git_am https://patchwork.plctlab.org/project/binutils-gdb/patch/20230721103336.22880-1-jose.marchesi@oracle.com/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/binutils-gdb/patch/20230721103336.22880-1-jose.marchesi@oracle.com/mbox/ ++++ curl https://patchwork.plctlab.org/project/binutils-gdb/patch/20230721103336.22880-1-jose.marchesi@oracle.com/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 308k 100 308k 0 0 5064k 0 --:--:-- --:--:-- --:--:-- 5064k +++ bout='\''Applying: DesCGENization of the BPF binutils port .git/rebase-apply/patch:367: indent with spaces. asm_dialect = DIALECT_NORMAL; .git/rebase-apply/patch:369: indent with spaces. asm_dialect = DIALECT_PSEUDOC; .git/rebase-apply/patch:371: indent with spaces. as_fatal (_("-mdialect=%s is not valid. Expected normal or pseudoc"), .git/rebase-apply/patch:372: indent with spaces. arg); .git/rebase-apply/patch:376: indent with spaces. isa_spec = BPF_V1; warning: squelched 646 whitespace errors warning: 651 lines add whitespace errors. Using index info to reconstruct a base tree... M bfd/bfd-in2.h M bfd/libbfd.h M bfd/reloc.c M gas/config/tc-bpf.c M gas/config/tc-bpf.h M gas/configure M gas/configure.ac M gas/doc/c-bpf.texi M gas/testsuite/gas/all/assign-bad-recursive.d M gas/testsuite/gas/all/eqv-dot.d M gas/testsuite/gas/all/gas.exp A gas/testsuite/gas/bpf/alu-be-pseudoc.d M gas/testsuite/gas/bpf/alu-be.d A gas/testsuite/gas/bpf/alu-pseudoc.d A gas/testsuite/gas/bpf/alu-pseudoc.s M gas/testsuite/gas/bpf/alu.d A gas/testsuite/gas/bpf/alu32-be-pseudoc.d M gas/testsuite/gas/bpf/alu32-be.d A gas/testsuite/gas/bpf/alu32-pseudoc.d A gas/testsuite/gas/bpf/alu32-pseudoc.s M gas/testsuite/gas/bpf/alu32.d M gas/testsuite/gas/bpf/atomic-be.d A gas/testsuite/gas/bpf/atomic-pseudoc.d A gas/testsuite/gas/bpf/atomic-pseudoc.s M gas/testsuite/gas/bpf/atomic.d M gas/testsuite/gas/bpf/bpf.exp A gas/testsuite/gas/bpf/indcall-1-pseudoc.d M gas/testsuite/gas/bpf/indcall-1.d M gas/testsuite/gas/bpf/jump-be.d A gas/testsuite/gas/bpf/jump-pseudoc.d M gas/testsuite/gas/bpf/jump.d A gas/testsuite/gas/bpf/jump32-pseudoc.d M gas/testsuite/gas/bpf/jump32.d A gas/testsuite/gas/bpf/lddw-be-pseudoc.d M gas/testsuite/gas/bpf/lddw-be.d A gas/testsuite/gas/bpf/lddw-pseudoc.d M gas/testsuite/gas/bpf/lddw.d M gas/testsuite/gas/bpf/mem-be.d A gas/testsuite/gas/bpf/mem-pseudoc.d A gas/testsuite/gas/bpf/mem-pseudoc.s M gas/testsuite/gas/bpf/mem.d M opcodes/configure M opcodes/disassemble.c Falling back to patching base and 3-way merge... Auto-merging opcodes/disassemble.c Auto-merging opcodes/configure Auto-merging gas/testsuite/gas/bpf/mem.d CONFLICT (content): Merge conflict in gas/testsuite/gas/bpf/mem.d CONFLICT (modify/delete): gas/testsuite/gas/bpf/mem-pseudoc.s deleted in HEAD and modified in DesCGENization of the BPF binutils port. Version DesCGENization of the BPF binutils port of gas/testsuite/gas/bpf/mem-pseudoc.s left in tree. CONFLICT (modify/delete): gas/testsuite/gas/bpf/mem-pseudoc.d deleted in HEAD and modified in DesCGENization of the BPF binutils port. Version DesCGENization of the BPF binutils port of gas/testsuite/gas/bpf/mem-pseudoc.d left in tree. Auto-merging gas/testsuite/gas/bpf/mem-be.d CONFLICT (content): Merge conflict in gas/testsuite/gas/bpf/mem-be.d Auto-merging gas/testsuite/gas/bpf/lddw.d CONFLICT (content): Merge conflict in gas/testsuite/gas/bpf/lddw.d CONFLICT (modify/delete): gas/testsuite/gas/bpf/lddw-pseudoc.d deleted in HEAD and modified in DesCGENization of the BPF binutils port. Version DesCGENization of the BPF binutils port of gas/testsuite/gas/bpf/lddw-pseudoc.d left in tree. Auto-merging gas/testsuite/gas/bpf/lddw-be.d CONFLICT (content): Merge conflict in gas/testsuite/gas/bpf/lddw-be.d CONFLICT (modify/delete): gas/testsuite/gas/bpf/lddw-be-pseudoc.d deleted in HEAD and modified in DesCGENization of the BPF binutils port. Version DesCGENization of the BPF binutils port of gas/testsuite/gas/bpf/lddw-be-pseudoc.d left in tree. Auto-merging gas/testsuite/gas/bpf/jump32.d CONFLICT (content): Merge conflict in gas/testsuite/gas/bpf/jump32.d CONFLICT (modify/delete): gas/testsuite/gas/bpf/jump32-pseudoc.d deleted in HEAD and modified in DesCGENization of the BPF binutils port. Version DesCGENization of the BPF binutils port of gas/testsuite/gas/bpf/jump32-pseudoc.d left in tree. Auto-merging gas/testsuite/gas/bpf/jump.d CONFLICT (content): Merge conflict in gas/testsuite/gas/bpf/jump.d CONFLICT (modify/delete): gas/testsuite/gas/bpf/jump-pseudoc.d deleted in HEAD and modified in DesCGENization of the BPF binutils port. Version DesCGENization of the BPF binutils port of gas/testsuite/gas/bpf/jump-pseudoc.d left in tree. Auto-merging gas/testsuite/gas/bpf/jump-be.d CONFLICT (content): Merge conflict in gas/testsuite/gas/bpf/jump-be.d Auto-merging gas/testsuite/gas/bpf/indcall-1.d CONFLICT (content): Merge conflict in gas/testsuite/gas/bpf/indcall-1.d CONFLICT (modify/delete): gas/testsuite/gas/bpf/indcall-1-pseudoc.d deleted in HEAD and modified in DesCGENization of the BPF binutils port. Version DesCGENization of the BPF binutils port of gas/testsuite/gas/bpf/indcall-1-pseudoc.d left in tree. Auto-merging gas/testsuite/gas/bpf/bpf.exp CONFLICT (content): Merge conflict in gas/testsuite/gas/bpf/bpf.exp Auto-merging gas/testsuite/gas/bpf/atomic.d CONFLICT (content): Merge conflict in gas/testsuite/gas/bpf/atomic.d CONFLICT (modify/delete): gas/testsuite/gas/bpf/atomic-pseudoc.s deleted in HEAD and modified in DesCGENization of the BPF binutils port. Version DesCGENization of the BPF binutils port of gas/testsuite/gas/bpf/atomic-pseudoc.s left in tree. CONFLICT (modify/delete): gas/testsuite/gas/bpf/atomic-pseudoc.d deleted in HEAD and modified in DesCGENization of the BPF binutils port. Version DesCGENization of the BPF binutils port of gas/testsuite/gas/bpf/atomic-pseudoc.d left in tree. Auto-merging gas/testsuite/gas/bpf/atomic-be.d CONFLICT (content): Merge conflict in gas/testsuite/gas/bpf/atomic-be.d Auto-merging gas/testsuite/gas/bpf/alu32.d CONFLICT (content): Merge conflict in gas/testsuite/gas/bpf/alu32.d CONFLICT (modify/delete): gas/testsuite/gas/bpf/alu32-pseudoc.s deleted in HEAD and modified in DesCGENization of the BPF binutils port. Version DesCGENization of the BPF binutils port of gas/testsuite/gas/bpf/alu32-pseudoc.s left in tree. CONFLICT (modify/delete): gas/testsuite/gas/bpf/alu32-pseudoc.d deleted in HEAD and modified in DesCGENization of the BPF binutils port. Version DesCGENization of the BPF binutils port of gas/testsuite/gas/bpf/alu32-pseudoc.d left in tree. Auto-merging gas/testsuite/gas/bpf/alu32-be.d CONFLICT (content): Merge conflict in gas/testsuite/gas/bpf/alu32-be.d CONFLICT (modify/delete): gas/testsuite/gas/bpf/alu32-be-pseudoc.d deleted in HEAD and modified in DesCGENization of the BPF binutils port. Version DesCGENization of the BPF binutils port of gas/testsuite/gas/bpf/alu32-be-pseudoc.d left in tree. Auto-merging gas/testsuite/gas/bpf/alu.d CONFLICT (content): Merge conflict in gas/testsuite/gas/bpf/alu.d CONFLICT (modify/delete): gas/testsuite/gas/bpf/alu-pseudoc.s deleted in HEAD and modified in DesCGENization of the BPF binutils port. Version DesCGENization of the BPF binutils port of gas/testsuite/gas/bpf/alu-pseudoc.s left in tree. CONFLICT (modify/delete): gas/testsuite/gas/bpf/alu-pseudoc.d deleted in HEAD and modified in DesCGENization of the BPF binutils port. Version DesCGENization of the BPF binutils port of gas/testsuite/gas/bpf/alu-pseudoc.d left in tree. Auto-merging gas/testsuite/gas/bpf/alu-be.d CONFLICT (content): Merge conflict in gas/testsuite/gas/bpf/alu-be.d CONFLICT (modify/delete): gas/testsuite/gas/bpf/alu-be-pseudoc.d deleted in HEAD and modified in DesCGENization of the BPF binutils port. Version DesCGENization of the BPF binutils port of gas/testsuite/gas/bpf/alu-be-pseudoc.d left in tree. Auto-merging gas/testsuite/gas/all/gas.exp Auto-merging gas/doc/c-bpf.texi CONFLICT (content): Merge conflict in gas/doc/c-bpf.texi Auto-merging gas/configure.ac Auto-merging gas/configure Auto-merging gas/config/tc-bpf.h CONFLICT (content): Merge conflict in gas/config/tc-bpf.h Auto-merging gas/config/tc-bpf.c CONFLICT (content): Merge conflict in gas/config/tc-bpf.c Auto-merging bfd/reloc.c Auto-merging bfd/libbfd.h Auto-merging bfd/bfd-in2.h CONFLICT (content): Merge conflict in bfd/bfd-in2.h error: Failed to merge in the changes. hint: Use '\''\'\'''\''git am --show-current-patch=diff'\''\'\'''\'' to see the failed patch Patch failed at 0001 DesCGENization of the BPF binutils port When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort".'\'' +++ bret=128' ++ git rev-parse HEAD + commitid_after=324998b47364528f407666512015370c12ab83a1 + '[' 128 = 0 ']' + [[ ++++ git_am https://patchwork.plctlab.org/project/binutils-gdb/patch/20230721103336.22880-1-jose.marchesi@oracle.com/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/binutils-gdb/patch/20230721103336.22880-1-jose.marchesi@oracle.com/mbox/ ++++ curl https://patchwork.plctlab.org/project/binutils-gdb/patch/20230721103336.22880-1-jose.marchesi@oracle.com/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 308k 100 308k 0 0 5064k 0 --:--:-- --:--:-- --:--:-- 5064k +++ bout='Applying: DesCGENization of the BPF binutils port .git/rebase-apply/patch:367: indent with spaces. asm_dialect = DIALECT_NORMAL; .git/rebase-apply/patch:369: indent with spaces. asm_dialect = DIALECT_PSEUDOC; .git/rebase-apply/patch:371: indent with spaces. as_fatal (_("-mdialect=%s is not valid. Expected normal or pseudoc"), .git/rebase-apply/patch:372: indent with spaces. arg); .git/rebase-apply/patch:376: indent with spaces. isa_spec = BPF_V1; warning: squelched 646 whitespace errors warning: 651 lines add whitespace errors. Using index info to reconstruct a base tree... M bfd/bfd-in2.h M bfd/libbfd.h M bfd/reloc.c M gas/config/tc-bpf.c M gas/config/tc-bpf.h M gas/configure M gas/configure.ac M gas/doc/c-bpf.texi M gas/testsuite/gas/all/assign-bad-recursive.d M gas/testsuite/gas/all/eqv-dot.d M gas/testsuite/gas/all/gas.exp A gas/testsuite/gas/bpf/alu-be-pseudoc.d M gas/testsuite/gas/bpf/alu-be.d A gas/testsuite/gas/bpf/alu-pseudoc.d A gas/testsuite/gas/bpf/alu-pseudoc.s M gas/testsuite/gas/bpf/alu.d A gas/testsuite/gas/bpf/alu32-be-pseudoc.d M gas/testsuite/gas/bpf/alu32-be.d A gas/testsuite/gas/bpf/alu32-pseudoc.d A gas/testsuite/gas/bpf/alu32-pseudoc.s M gas/testsuite/gas/bpf/alu32.d M gas/testsuite/gas/bpf/atomic-be.d A gas/testsuite/gas/bpf/atomic-pseudoc.d A gas/testsuite/gas/bpf/atomic-pseudoc.s M gas/testsuite/gas/bpf/atomic.d M gas/testsuite/gas/bpf/bpf.exp A gas/testsuite/gas/bpf/indcall-1-pseudoc.d M gas/testsuite/gas/bpf/indcall-1.d M gas/testsuite/gas/bpf/jump-be.d A gas/testsuite/gas/bpf/jump-pseudoc.d M gas/testsuite/gas/bpf/jump.d A gas/testsuite/gas/bpf/jump32-pseudoc.d M gas/testsuite/gas/bpf/jump32.d A gas/testsuite/gas/bpf/lddw-be-pseudoc.d M gas/testsuite/gas/bpf/lddw-be.d A gas/testsuite/gas/bpf/lddw-pseudoc.d M gas/testsuite/gas/bpf/lddw.d M gas/testsuite/gas/bpf/mem-be.d A gas/testsuite/gas/bpf/mem-pseudoc.d A gas/testsuite/gas/bpf/mem-pseudoc.s M gas/testsuite/gas/bpf/mem.d M opcodes/configure M opcodes/disassemble.c Falling back to patching base and 3-way merge... Auto-merging opcodes/disassemble.c Auto-merging opcodes/configure Auto-merging gas/testsuite/gas/bpf/mem.d CONFLICT (content): Merge conflict in gas/testsuite/gas/bpf/mem.d CONFLICT (modify/delete): gas/testsuite/gas/bpf/mem-pseudoc.s deleted in HEAD and modified in DesCGENization of the BPF binutils port. Version DesCGENization of the BPF binutils port of gas/testsuite/gas/bpf/mem-pseudoc.s left in tree. CONFLICT (modify/delete): gas/testsuite/gas/bpf/mem-pseudoc.d deleted in HEAD and modified in DesCGENization of the BPF binutils port. Version DesCGENization of the BPF binutils port of gas/testsuite/gas/bpf/mem-pseudoc.d left in tree. Auto-merging gas/testsuite/gas/bpf/mem-be.d CONFLICT (content): Merge conflict in gas/testsuite/gas/bpf/mem-be.d Auto-merging gas/testsuite/gas/bpf/lddw.d CONFLICT (content): Merge conflict in gas/testsuite/gas/bpf/lddw.d CONFLICT (modify/delete): gas/testsuite/gas/bpf/lddw-pseudoc.d deleted in HEAD and modified in DesCGENization of the BPF binutils port. Version DesCGENization of the BPF binutils port of gas/testsuite/gas/bpf/lddw-pseudoc.d left in tree. Auto-merging gas/testsuite/gas/bpf/lddw-be.d CONFLICT (content): Merge conflict in gas/testsuite/gas/bpf/lddw-be.d CONFLICT (modify/delete): gas/testsuite/gas/bpf/lddw-be-pseudoc.d deleted in HEAD and modified in DesCGENization of the BPF binutils port. Version DesCGENization of the BPF binutils port of gas/testsuite/gas/bpf/lddw-be-pseudoc.d left in tree. Auto-merging gas/testsuite/gas/bpf/jump32.d CONFLICT (content): Merge conflict in gas/testsuite/gas/bpf/jump32.d CONFLICT (modify/delete): gas/testsuite/gas/bpf/jump32-pseudoc.d deleted in HEAD and modified in DesCGENization of the BPF binutils port. Version DesCGENization of the BPF binutils port of gas/testsuite/gas/bpf/jump32-pseudoc.d left in tree. Auto-merging gas/testsuite/gas/bpf/jump.d CONFLICT (content): Merge conflict in gas/testsuite/gas/bpf/jump.d CONFLICT (modify/delete): gas/testsuite/gas/bpf/jump-pseudoc.d deleted in HEAD and modified in DesCGENization of the BPF binutils port. Version DesCGENization of the BPF binutils port of gas/testsuite/gas/bpf/jump-pseudoc.d left in tree. Auto-merging gas/testsuite/gas/bpf/jump-be.d CONFLICT (content): Merge conflict in gas/testsuite/gas/bpf/jump-be.d Auto-merging gas/testsuite/gas/bpf/indcall-1.d CONFLICT (content): Merge conflict in gas/testsuite/gas/bpf/indcall-1.d CONFLICT (modify/delete): gas/testsuite/gas/bpf/indcall-1-pseudoc.d deleted in HEAD and modified in DesCGENization of the BPF binutils port. Version DesCGENization of the BPF binutils port of gas/testsuite/gas/bpf/indcall-1-pseudoc.d left in tree. Auto-merging gas/testsuite/gas/bpf/bpf.exp CONFLICT (content): Merge conflict in gas/testsuite/gas/bpf/bpf.exp Auto-merging gas/testsuite/gas/bpf/atomic.d CONFLICT (content): Merge conflict in gas/testsuite/gas/bpf/atomic.d CONFLICT (modify/delete): gas/testsuite/gas/bpf/atomic-pseudoc.s deleted in HEAD and modified in DesCGENization of the BPF binutils port. Version DesCGENization of the BPF binutils port of gas/testsuite/gas/bpf/atomic-pseudoc.s left in tree. CONFLICT (modify/delete): gas/testsuite/gas/bpf/atomic-pseudoc.d deleted in HEAD and modified in DesCGENization of the BPF binutils port. Version DesCGENization of the BPF binutils port of gas/testsuite/gas/bpf/atomic-pseudoc.d left in tree. Auto-merging gas/testsuite/gas/bpf/atomic-be.d CONFLICT (content): Merge conflict in gas/testsuite/gas/bpf/atomic-be.d Auto-merging gas/testsuite/gas/bpf/alu32.d CONFLICT (content): Merge conflict in gas/testsuite/gas/bpf/alu32.d CONFLICT (modify/delete): gas/testsuite/gas/bpf/alu32-pseudoc.s deleted in HEAD and modified in DesCGENization of the BPF binutils port. Version DesCGENization of the BPF binutils port of gas/testsuite/gas/bpf/alu32-pseudoc.s left in tree. CONFLICT (modify/delete): gas/testsuite/gas/bpf/alu32-pseudoc.d deleted in HEAD and modified in DesCGENization of the BPF binutils port. Version DesCGENization of the BPF binutils port of gas/testsuite/gas/bpf/alu32-pseudoc.d left in tree. Auto-merging gas/testsuite/gas/bpf/alu32-be.d CONFLICT (content): Merge conflict in gas/testsuite/gas/bpf/alu32-be.d CONFLICT (modify/delete): gas/testsuite/gas/bpf/alu32-be-pseudoc.d deleted in HEAD and modified in DesCGENization of the BPF binutils port. Version DesCGENization of the BPF binutils port of gas/testsuite/gas/bpf/alu32-be-pseudoc.d left in tree. Auto-merging gas/testsuite/gas/bpf/alu.d CONFLICT (content): Merge conflict in gas/testsuite/gas/bpf/alu.d CONFLICT (modify/delete): gas/testsuite/gas/bpf/alu-pseudoc.s deleted in HEAD and modified in DesCGENization of the BPF binutils port. Version DesCGENization of the BPF binutils port of gas/testsuite/gas/bpf/alu-pseudoc.s left in tree. CONFLICT (modify/delete): gas/testsuite/gas/bpf/alu-pseudoc.d deleted in HEAD and modified in DesCGENization of the BPF binutils port. Version DesCGENization of the BPF binutils port of gas/testsuite/gas/bpf/alu-pseudoc.d left in tree. Auto-merging gas/testsuite/gas/bpf/alu-be.d CONFLICT (content): Merge conflict in gas/testsuite/gas/bpf/alu-be.d CONFLICT (modify/delete): gas/testsuite/gas/bpf/alu-be-pseudoc.d deleted in HEAD and modified in DesCGENization of the BPF binutils port. Version DesCGENization of the BPF binutils port of gas/testsuite/gas/bpf/alu-be-pseudoc.d left in tree. Auto-merging gas/testsuite/gas/all/gas.exp Auto-merging gas/doc/c-bpf.texi CONFLICT (content): Merge conflict in gas/doc/c-bpf.texi Auto-merging gas/configure.ac Auto-merging gas/configure Auto-merging gas/config/tc-bpf.h CONFLICT (content): Merge conflict in gas/config/tc-bpf.h Auto-merging gas/config/tc-bpf.c CONFLICT (content): Merge conflict in gas/config/tc-bpf.c Auto-merging bfd/reloc.c Auto-merging bfd/libbfd.h Auto-merging bfd/bfd-in2.h CONFLICT (content): Merge conflict in bfd/bfd-in2.h error: Failed to merge in the changes. hint: Use '\''git am --show-current-patch=diff'\'' to see the failed patch Patch failed at 0001 DesCGENization of the BPF binutils port When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort".' +++ bret=128 =~ sha1 information is lacking or useless ]] + [[ ++++ git_am https://patchwork.plctlab.org/project/binutils-gdb/patch/20230721103336.22880-1-jose.marchesi@oracle.com/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/binutils-gdb/patch/20230721103336.22880-1-jose.marchesi@oracle.com/mbox/ ++++ curl https://patchwork.plctlab.org/project/binutils-gdb/patch/20230721103336.22880-1-jose.marchesi@oracle.com/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 308k 100 308k 0 0 5064k 0 --:--:-- --:--:-- --:--:-- 5064k +++ bout='Applying: DesCGENization of the BPF binutils port .git/rebase-apply/patch:367: indent with spaces. asm_dialect = DIALECT_NORMAL; .git/rebase-apply/patch:369: indent with spaces. asm_dialect = DIALECT_PSEUDOC; .git/rebase-apply/patch:371: indent with spaces. as_fatal (_("-mdialect=%s is not valid. Expected normal or pseudoc"), .git/rebase-apply/patch:372: indent with spaces. arg); .git/rebase-apply/patch:376: indent with spaces. isa_spec = BPF_V1; warning: squelched 646 whitespace errors warning: 651 lines add whitespace errors. Using index info to reconstruct a base tree... M bfd/bfd-in2.h M bfd/libbfd.h M bfd/reloc.c M gas/config/tc-bpf.c M gas/config/tc-bpf.h M gas/configure M gas/configure.ac M gas/doc/c-bpf.texi M gas/testsuite/gas/all/assign-bad-recursive.d M gas/testsuite/gas/all/eqv-dot.d M gas/testsuite/gas/all/gas.exp A gas/testsuite/gas/bpf/alu-be-pseudoc.d M gas/testsuite/gas/bpf/alu-be.d A gas/testsuite/gas/bpf/alu-pseudoc.d A gas/testsuite/gas/bpf/alu-pseudoc.s M gas/testsuite/gas/bpf/alu.d A gas/testsuite/gas/bpf/alu32-be-pseudoc.d M gas/testsuite/gas/bpf/alu32-be.d A gas/testsuite/gas/bpf/alu32-pseudoc.d A gas/testsuite/gas/bpf/alu32-pseudoc.s M gas/testsuite/gas/bpf/alu32.d M gas/testsuite/gas/bpf/atomic-be.d A gas/testsuite/gas/bpf/atomic-pseudoc.d A gas/testsuite/gas/bpf/atomic-pseudoc.s M gas/testsuite/gas/bpf/atomic.d M gas/testsuite/gas/bpf/bpf.exp A gas/testsuite/gas/bpf/indcall-1-pseudoc.d M gas/testsuite/gas/bpf/indcall-1.d M gas/testsuite/gas/bpf/jump-be.d A gas/testsuite/gas/bpf/jump-pseudoc.d M gas/testsuite/gas/bpf/jump.d A gas/testsuite/gas/bpf/jump32-pseudoc.d M gas/testsuite/gas/bpf/jump32.d A gas/testsuite/gas/bpf/lddw-be-pseudoc.d M gas/testsuite/gas/bpf/lddw-be.d A gas/testsuite/gas/bpf/lddw-pseudoc.d M gas/testsuite/gas/bpf/lddw.d M gas/testsuite/gas/bpf/mem-be.d A gas/testsuite/gas/bpf/mem-pseudoc.d A gas/testsuite/gas/bpf/mem-pseudoc.s M gas/testsuite/gas/bpf/mem.d M opcodes/configure M opcodes/disassemble.c Falling back to patching base and 3-way merge... Auto-merging opcodes/disassemble.c Auto-merging opcodes/configure Auto-merging gas/testsuite/gas/bpf/mem.d CONFLICT (content): Merge conflict in gas/testsuite/gas/bpf/mem.d CONFLICT (modify/delete): gas/testsuite/gas/bpf/mem-pseudoc.s deleted in HEAD and modified in DesCGENization of the BPF binutils port. Version DesCGENization of the BPF binutils port of gas/testsuite/gas/bpf/mem-pseudoc.s left in tree. CONFLICT (modify/delete): gas/testsuite/gas/bpf/mem-pseudoc.d deleted in HEAD and modified in DesCGENization of the BPF binutils port. Version DesCGENization of the BPF binutils port of gas/testsuite/gas/bpf/mem-pseudoc.d left in tree. Auto-merging gas/testsuite/gas/bpf/mem-be.d CONFLICT (content): Merge conflict in gas/testsuite/gas/bpf/mem-be.d Auto-merging gas/testsuite/gas/bpf/lddw.d CONFLICT (content): Merge conflict in gas/testsuite/gas/bpf/lddw.d CONFLICT (modify/delete): gas/testsuite/gas/bpf/lddw-pseudoc.d deleted in HEAD and modified in DesCGENization of the BPF binutils port. Version DesCGENization of the BPF binutils port of gas/testsuite/gas/bpf/lddw-pseudoc.d left in tree. Auto-merging gas/testsuite/gas/bpf/lddw-be.d CONFLICT (content): Merge conflict in gas/testsuite/gas/bpf/lddw-be.d CONFLICT (modify/delete): gas/testsuite/gas/bpf/lddw-be-pseudoc.d deleted in HEAD and modified in DesCGENization of the BPF binutils port. Version DesCGENization of the BPF binutils port of gas/testsuite/gas/bpf/lddw-be-pseudoc.d left in tree. Auto-merging gas/testsuite/gas/bpf/jump32.d CONFLICT (content): Merge conflict in gas/testsuite/gas/bpf/jump32.d CONFLICT (modify/delete): gas/testsuite/gas/bpf/jump32-pseudoc.d deleted in HEAD and modified in DesCGENization of the BPF binutils port. Version DesCGENization of the BPF binutils port of gas/testsuite/gas/bpf/jump32-pseudoc.d left in tree. Auto-merging gas/testsuite/gas/bpf/jump.d CONFLICT (content): Merge conflict in gas/testsuite/gas/bpf/jump.d CONFLICT (modify/delete): gas/testsuite/gas/bpf/jump-pseudoc.d deleted in HEAD and modified in DesCGENization of the BPF binutils port. Version DesCGENization of the BPF binutils port of gas/testsuite/gas/bpf/jump-pseudoc.d left in tree. Auto-merging gas/testsuite/gas/bpf/jump-be.d CONFLICT (content): Merge conflict in gas/testsuite/gas/bpf/jump-be.d Auto-merging gas/testsuite/gas/bpf/indcall-1.d CONFLICT (content): Merge conflict in gas/testsuite/gas/bpf/indcall-1.d CONFLICT (modify/delete): gas/testsuite/gas/bpf/indcall-1-pseudoc.d deleted in HEAD and modified in DesCGENization of the BPF binutils port. Version DesCGENization of the BPF binutils port of gas/testsuite/gas/bpf/indcall-1-pseudoc.d left in tree. Auto-merging gas/testsuite/gas/bpf/bpf.exp CONFLICT (content): Merge conflict in gas/testsuite/gas/bpf/bpf.exp Auto-merging gas/testsuite/gas/bpf/atomic.d CONFLICT (content): Merge conflict in gas/testsuite/gas/bpf/atomic.d CONFLICT (modify/delete): gas/testsuite/gas/bpf/atomic-pseudoc.s deleted in HEAD and modified in DesCGENization of the BPF binutils port. Version DesCGENization of the BPF binutils port of gas/testsuite/gas/bpf/atomic-pseudoc.s left in tree. CONFLICT (modify/delete): gas/testsuite/gas/bpf/atomic-pseudoc.d deleted in HEAD and modified in DesCGENization of the BPF binutils port. Version DesCGENization of the BPF binutils port of gas/testsuite/gas/bpf/atomic-pseudoc.d left in tree. Auto-merging gas/testsuite/gas/bpf/atomic-be.d CONFLICT (content): Merge conflict in gas/testsuite/gas/bpf/atomic-be.d Auto-merging gas/testsuite/gas/bpf/alu32.d CONFLICT (content): Merge conflict in gas/testsuite/gas/bpf/alu32.d CONFLICT (modify/delete): gas/testsuite/gas/bpf/alu32-pseudoc.s deleted in HEAD and modified in DesCGENization of the BPF binutils port. Version DesCGENization of the BPF binutils port of gas/testsuite/gas/bpf/alu32-pseudoc.s left in tree. CONFLICT (modify/delete): gas/testsuite/gas/bpf/alu32-pseudoc.d deleted in HEAD and modified in DesCGENization of the BPF binutils port. Version DesCGENization of the BPF binutils port of gas/testsuite/gas/bpf/alu32-pseudoc.d left in tree. Auto-merging gas/testsuite/gas/bpf/alu32-be.d CONFLICT (content): Merge conflict in gas/testsuite/gas/bpf/alu32-be.d CONFLICT (modify/delete): gas/testsuite/gas/bpf/alu32-be-pseudoc.d deleted in HEAD and modified in DesCGENization of the BPF binutils port. Version DesCGENization of the BPF binutils port of gas/testsuite/gas/bpf/alu32-be-pseudoc.d left in tree. Auto-merging gas/testsuite/gas/bpf/alu.d CONFLICT (content): Merge conflict in gas/testsuite/gas/bpf/alu.d CONFLICT (modify/delete): gas/testsuite/gas/bpf/alu-pseudoc.s deleted in HEAD and modified in DesCGENization of the BPF binutils port. Version DesCGENization of the BPF binutils port of gas/testsuite/gas/bpf/alu-pseudoc.s left in tree. CONFLICT (modify/delete): gas/testsuite/gas/bpf/alu-pseudoc.d deleted in HEAD and modified in DesCGENization of the BPF binutils port. Version DesCGENization of the BPF binutils port of gas/testsuite/gas/bpf/alu-pseudoc.d left in tree. Auto-merging gas/testsuite/gas/bpf/alu-be.d CONFLICT (content): Merge conflict in gas/testsuite/gas/bpf/alu-be.d CONFLICT (modify/delete): gas/testsuite/gas/bpf/alu-be-pseudoc.d deleted in HEAD and modified in DesCGENization of the BPF binutils port. Version DesCGENization of the BPF binutils port of gas/testsuite/gas/bpf/alu-be-pseudoc.d left in tree. Auto-merging gas/testsuite/gas/all/gas.exp Auto-merging gas/doc/c-bpf.texi CONFLICT (content): Merge conflict in gas/doc/c-bpf.texi Auto-merging gas/configure.ac Auto-merging gas/configure Auto-merging gas/config/tc-bpf.h CONFLICT (content): Merge conflict in gas/config/tc-bpf.h Auto-merging gas/config/tc-bpf.c CONFLICT (content): Merge conflict in gas/config/tc-bpf.c Auto-merging bfd/reloc.c Auto-merging bfd/libbfd.h Auto-merging bfd/bfd-in2.h CONFLICT (content): Merge conflict in bfd/bfd-in2.h error: Failed to merge in the changes. hint: Use '\''git am --show-current-patch=diff'\'' to see the failed patch Patch failed at 0001 DesCGENization of the BPF binutils port When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort".' +++ bret=128 =~ Failed to merge in the changes ]] + submit_check warning Unresolved https://patchwork.plctlab.org/jenkins/job/binutils-gdb/2020/consoleText 'Git am fail log' + check_state=warning + patch_state=Unresolved + repo_url=https://patchwork.plctlab.org/jenkins/job/binutils-gdb/2020/consoleText + DESCRIPTION='Git am fail log' + curl -X POST -H 'Authorization: Token [*******]' -F state=warning -F target_url=https://patchwork.plctlab.org/jenkins/job/binutils-gdb/2020/consoleText -F context=binutils-gdb-check -F 'description=Git am fail log' https://patchwork.plctlab.org/api/patches/123757/checks/ % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 980 100 434 100 546 9041 11375 --:--:-- --:--:-- --:--:-- 20416 {"id":11074,"url":"https://patchwork.plctlab.org/api/patches/123757/checks/11074/","user":{"id":1,"url":"https://patchwork.plctlab.org/api/users/1/","username":"snail","first_name":"","last_name":"","email":"wangliu@iscas.ac.cn"},"date":"2023-07-21T11:16:24.308504","state":"warning","target_url":"https://patchwork.plctlab.org/jenkins/job/binutils-gdb/2020/consoleText","context":"binutils-gdb-check","description":"Git am fail log"}+ curl -X PATCH -H 'Authorization: Token [*******]' -F state=Unresolved https://patchwork.plctlab.org/api/1.2/patches/123757/ % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0{"id":123757,"url":"https://patchwork.plctlab.org/api/1.2/patches/123757/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230721103336.22880-1-jose.marchesi@oracle.com/","project":{"id":2,"url":"https://patchwork.plctlab.org/api/1.2/projects/2/","name":"binutils-gdb","link_name":"binutils-gdb","list_id":"binutils.sourceware.org","list_email":"binutils@sourceware.org","web_url":"https://github.com/wangliu-iscas/Patchwork-Bundles/blob/main/binutils-gdb.md","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20230721103336.22880-1-jose.marchesi@oracle.com>","list_archive_url":null,"date":"2023-07-21T10:33:36","name":"[COMMITTED] DesCGENization of the BPF binutils port","commit_ref":null,"pull_url":null,"state":"unresolved","archived":false,"hash":"7a2979252e041025c4634da3330bb2f708cd4a4f","submitter":{"id":82,"url":"https://patchwork.plctlab.org/api/1.2/people/82/","name":"Jose E. Marchesi","email":"jose.marchesi@oracle.com"},"delegate":null,"mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230721103336.22880-1-jose.marchesi@oracle.com/mbox/","series":[{"id":51043,"url":"https://patchwork.plctlab.org/api/1.2/series/51043/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/list/?series=51043","date":"2023-07-21T10:33:36","name":"[COMMITTED] DesCGENization of the BPF binutils port","version":1,"mbox":"https://patchwork.plctlab.org/series/51043/mbox/"}],"comments":"https://patchwork.plctlab.org/api/patches/123757/comments/","check":"warning","checks":"https://patchwork.plctlab.org/api/patches/123757/checks/","tags":{},"headers":{"Return-Path":"","Delivered-To":["ouuuleilei@gmail.com","binutils@sourceware.org"],"Received":["by 2002:a59:9010:0:b0:3e4:2afc:c1 with SMTP id l16csp110063vqg;\n Fri, 21 Jul 2023 03:35:37 -0700 (PDT)","from server2.sourceware.org (ip-8-43-85-97.sourceware.org.\n [8.43.85.97])\n by mx.google.com with ESMTPS id\n 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Marchesi via Binutils\" ","Reply-To":"\"Jose E. Marchesi\" ","Errors-To":"binutils-bounces+ouuuleilei=gmail.com@sourceware.org","Sender":"\"Binutils\" ","X-getmail-retrieved-from-mailbox":"INBOX","X-GMAIL-THRID":"1772026054761355418","X-GMAIL-MSGID":"1772026054761355418"},"content":"[Note that in this email I have removed all the thunks for deleted\n files, since otherwise it would be too big for the mailing list.\n Please see the summary below for the files that have been removed.]\n\nCGEN is cool, but the BPF architecture is simply too bizarre for it.\n\nThe weird way of BPF to handle endianness in instruction encoding, the\nweird C-like alternative assembly syntax, the weird abuse of\nmulti-byte (or infra-byte) instruction fields as opcodes, the unusual\npresence of opcodes beyond the first 32-bits of some instructions, are\nall examples of what makes it a PITA to continue using CGEN for this\nport. The bpf.cpu file is becoming so complex and so nested with\np-macros that it is very difficult to read, and quite challenging to\nupdate. Also, every time we are forced to change something in CGEN to\naccommodate BPF requirements (which is often) we have to do extensive\ntesting to make sure we do not break any other target using CGEN.\n\nThis is getting un-maintenable.\n\nSo I have decided to bite the bullet and revamp/rewrite the port so it\nno longer uses CGEN. Overall, this involved:\n\n* To remove the cpu/bpf.{cpu,opc} descriptions.\n\n* To remove the CGEN generated files.\n\n* To replace the CGEN generated opcodes table with a new hand-written\n opcodes table for BPF.\n\n* To replace the CGEN generated disassembler wih a new disassembler\n that uses the new opcodes.\n\n* To replace the CGEN generated assembler with a new assembler that uses the\n new opcodes.\n\n* To replace the CGEN generated simulator with a new simulator that uses the\n new opcodes. [This is pushed in GDB in another patch.]\n\n* To adapt the build systems to the new situation.\n\nAdditionally, this patch introduces some extensions and improvements:\n\n* A new BPF relocation BPF_RELOC_BPF_DISP16 plus corresponding ELF\n relocation R_BPF_GNU_64_16 are added to the BPF BFD port. These\n relocations are used for section-relative 16-bit offsets used in\n load/store instructions.\n\n* The disassembler now has support for the \"pseudo-c\" assembly syntax of\n BPF. What dialect to use when disassembling is controlled by a command\n line option.\n\n* The disassembler now has support for dumping instruction immediates in\n either octal, hexadecimal or decimal. The used output base is controlled\n by a new command-line option.\n\n* The GAS BPF test suite has been re-structured and expanded in order to\n test the disassembler pseudoc syntax support. Minor bugs have been also\n fixed there. The assembler generic tests that were disabled for bpf-*-*\n targets due to the previous implementation of pseudoc syntax are now\n re-enabled. Additional tests have been added to test the new features of\n the assembler. .dump files are no longer used.\n\n* The linker BPF test suite has been adapted to the command line options\n used by the new disassembler.\n\nThe result is very satisfactory. This patchs adds 3448 lines of code\nand removes 10542 lines of code.\n\nTested in:\n\n* Target bpf-unknown-none with 64-bit little-endian host and 32-bit\n little-endian host.\n\n* Target x86-64-linux-gnu with --enable-targets=all\n\nNote that I have not tested in a big-endian host yet. I will do so\nonce this lands upstream so I can use the GCC compiler farm.\n\nI have not included ChangeLog entries in this patch: these would be\nmassive and not very useful, considering this is pretty much a rewrite\nof the port. I beg the indulgence of the global maintainers.\n---\n bfd/bfd-in2.h | 1 +\n bfd/bpf-reloc.def | 15 +\n bfd/elf64-bpf.c | 2 +\n bfd/libbfd.h | 1 +\n bfd/reloc.c | 2 +\n cpu/bpf.cpu | 855 ------\n cpu/bpf.opc | 191 --\n gas/config/tc-bpf.c | 2519 +++++++-----------\n gas/config/tc-bpf.h | 4 +-\n gas/configure | 1 -\n gas/configure.ac | 1 -\n gas/doc/c-bpf.texi | 790 ++++--\n gas/testsuite/gas/all/assign-bad-recursive.d | 1 -\n gas/testsuite/gas/all/eqv-dot.d | 2 +-\n gas/testsuite/gas/all/gas.exp | 5 +-\n gas/testsuite/gas/bpf/alu-be-pseudoc.d | 66 +-\n gas/testsuite/gas/bpf/alu-be.d | 68 +-\n gas/testsuite/gas/bpf/alu-be.dump | 54 -\n gas/testsuite/gas/bpf/alu-pseudoc.d | 68 +-\n gas/testsuite/gas/bpf/alu-pseudoc.s | 8 +-\n gas/testsuite/gas/bpf/alu-xbpf.d | 17 -\n gas/testsuite/gas/bpf/alu-xbpf.s | 11 -\n gas/testsuite/gas/bpf/alu.d | 68 +-\n gas/testsuite/gas/bpf/alu.dump | 54 -\n gas/testsuite/gas/bpf/alu.s | 8 +-\n gas/testsuite/gas/bpf/alu32-be-pseudoc.d | 62 +-\n gas/testsuite/gas/bpf/alu32-be.d | 64 +-\n gas/testsuite/gas/bpf/alu32-be.dump | 60 -\n gas/testsuite/gas/bpf/alu32-pseudoc.d | 62 +-\n gas/testsuite/gas/bpf/alu32-pseudoc.s | 30 +-\n gas/testsuite/gas/bpf/alu32-xbpf.d | 17 -\n gas/testsuite/gas/bpf/alu32-xbpf.s | 11 -\n gas/testsuite/gas/bpf/alu32.d | 62 +-\n gas/testsuite/gas/bpf/alu32.dump | 60 -\n gas/testsuite/gas/bpf/alu32.s | 8 +-\n gas/testsuite/gas/bpf/atomic-be-pseudoc.d | 12 +\n gas/testsuite/gas/bpf/atomic-be.d | 5 +-\n gas/testsuite/gas/bpf/atomic-pseudoc.d | 15 +-\n gas/testsuite/gas/bpf/atomic-pseudoc.s | 4 +-\n gas/testsuite/gas/bpf/atomic.d | 13 +-\n gas/testsuite/gas/bpf/atomic.dump | 7 -\n gas/testsuite/gas/bpf/atomic.s | 4 +-\n gas/testsuite/gas/bpf/bpf.exp | 30 +-\n gas/testsuite/gas/bpf/call-be.d | 4 +-\n gas/testsuite/gas/bpf/call.d | 4 +-\n gas/testsuite/gas/bpf/data-be.d | 2 +-\n gas/testsuite/gas/bpf/data.d | 2 +-\n gas/testsuite/gas/bpf/exit-be.d | 4 +-\n gas/testsuite/gas/bpf/exit.d | 4 +-\n gas/testsuite/gas/bpf/indcall-1-pseudoc.d | 24 +-\n gas/testsuite/gas/bpf/indcall-1.d | 24 +-\n gas/testsuite/gas/bpf/indcall-1.dump | 18 -\n gas/testsuite/gas/bpf/indcall-bad-1.l | 5 -\n gas/testsuite/gas/bpf/indcall-bad-1.s | 1 -\n gas/testsuite/gas/bpf/jump-be-pseudoc.d | 32 +\n gas/testsuite/gas/bpf/jump-be.d | 5 +-\n gas/testsuite/gas/bpf/jump-pseudoc.d | 33 +-\n gas/testsuite/gas/bpf/jump.d | 33 +-\n gas/testsuite/gas/bpf/jump.dump | 27 -\n gas/testsuite/gas/bpf/jump32-be-pseudoc.d | 32 +\n gas/testsuite/gas/bpf/jump32-be.d | 32 +\n gas/testsuite/gas/bpf/jump32-pseudoc.d | 33 +-\n gas/testsuite/gas/bpf/jump32.d | 33 +-\n gas/testsuite/gas/bpf/jump32.dump | 27 -\n gas/testsuite/gas/bpf/lddw-be-pseudoc.d | 19 +-\n gas/testsuite/gas/bpf/lddw-be.d | 19 +-\n gas/testsuite/gas/bpf/lddw-be.dump | 13 -\n gas/testsuite/gas/bpf/lddw-pseudoc.d | 19 +-\n gas/testsuite/gas/bpf/lddw.d | 19 +-\n gas/testsuite/gas/bpf/lddw.dump | 13 -\n gas/testsuite/gas/bpf/mem-be-pseudoc.d | 30 +\n gas/testsuite/gas/bpf/mem-be.d | 11 +-\n gas/testsuite/gas/bpf/mem-pseudoc.d | 31 +-\n gas/testsuite/gas/bpf/mem-pseudoc.s | 8 +-\n gas/testsuite/gas/bpf/mem.d | 31 +-\n gas/testsuite/gas/bpf/mem.dump | 25 -\n gas/testsuite/gas/bpf/mem.s | 2 +-\n gas/testsuite/gas/bpf/pseudoc-normal-be.d | 214 --\n gas/testsuite/gas/bpf/pseudoc-normal.d | 214 --\n gas/testsuite/gas/bpf/pseudoc-normal.s | 196 --\n gas/testsuite/gas/bpf/spacing-pseudoc.d | 18 +\n gas/testsuite/gas/bpf/spacing-pseudoc.s | 9 +\n include/dis-asm.h | 1 +\n include/elf/bpf.h | 1 +\n include/opcode/bpf.h | 306 +++\n ld/testsuite/ld-bpf/call-1.d | 4 +-\n ld/testsuite/ld-bpf/call-2.d | 2 +-\n ld/testsuite/ld-bpf/reloc-insn-external-be.d | 4 +-\n ld/testsuite/ld-bpf/reloc-insn-external-le.d | 4 +-\n opcodes/Makefile.am | 16 -\n opcodes/Makefile.in | 20 -\n opcodes/bpf-asm.c | 590 ----\n opcodes/bpf-desc.c | 1939 --------------\n opcodes/bpf-desc.h | 268 --\n opcodes/bpf-dis.c | 795 ++----\n opcodes/bpf-ibld.c | 961 -------\n opcodes/bpf-opc.c | 2271 ++++------------\n opcodes/bpf-opc.h | 166 --\n opcodes/configure | 2 +-\n opcodes/configure.ac | 2 +-\n opcodes/disassemble.c | 30 +-\n 101 files changed, 3448 insertions(+), 10542 deletions(-)\n delete mode 100644 cpu/bpf.cpu\n delete mode 100644 cpu/bpf.opc\n delete mode 100644 gas/testsuite/gas/bpf/alu-be.dump\n delete mode 100644 gas/testsuite/gas/bpf/alu-xbpf.d\n delete mode 100644 gas/testsuite/gas/bpf/alu-xbpf.s\n delete mode 100644 gas/testsuite/gas/bpf/alu.dump\n delete mode 100644 gas/testsuite/gas/bpf/alu32-be.dump\n delete mode 100644 gas/testsuite/gas/bpf/alu32-xbpf.d\n delete mode 100644 gas/testsuite/gas/bpf/alu32-xbpf.s\n delete mode 100644 gas/testsuite/gas/bpf/alu32.dump\n create mode 100644 gas/testsuite/gas/bpf/atomic-be-pseudoc.d\n delete mode 100644 gas/testsuite/gas/bpf/atomic.dump\n delete mode 100644 gas/testsuite/gas/bpf/indcall-1.dump\n delete mode 100644 gas/testsuite/gas/bpf/indcall-bad-1.l\n delete mode 100644 gas/testsuite/gas/bpf/indcall-bad-1.s\n create mode 100644 gas/testsuite/gas/bpf/jump-be-pseudoc.d\n delete mode 100644 gas/testsuite/gas/bpf/jump.dump\n create mode 100644 gas/testsuite/gas/bpf/jump32-be-pseudoc.d\n create mode 100644 gas/testsuite/gas/bpf/jump32-be.d\n delete mode 100644 gas/testsuite/gas/bpf/jump32.dump\n delete mode 100644 gas/testsuite/gas/bpf/lddw-be.dump\n delete mode 100644 gas/testsuite/gas/bpf/lddw.dump\n create mode 100644 gas/testsuite/gas/bpf/mem-be-pseudoc.d\n delete mode 100644 gas/testsuite/gas/bpf/mem.dump\n delete mode 100644 gas/testsuite/gas/bpf/pseudoc-normal-be.d\n delete mode 100644 gas/testsuite/gas/bpf/pseudoc-normal.d\n delete mode 100644 gas/testsuite/gas/bpf/pseudoc-normal.s\n create mode 100644 gas/testsuite/gas/bpf/spacing-pseudoc.d\n create mode 100644 gas/testsuite/gas/bpf/spacing-pseudoc.s\n create mode 100644 include/opcode/bpf.h\n delete mode 100644 opcodes/bpf-asm.c\n delete mode 100644 opcodes/bpf-desc.c\n delete mode 100644 opcodes/bpf-desc.h\n delete mode 100644 opcodes/bpf-ibld.c\n delete mode 100644 opcodes/bpf-opc.h","diff":"diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h\nindex 1b9a801966c..ba7440c2768 100644\n--- a/bfd/bfd-in2.h\n+++ b/bfd/bfd-in2.h\n@@ -7148,6 +7148,7 @@ assembler and not (currently) written to any object files. */\n /* Linux eBPF relocations. */\n BFD_RELOC_BPF_64,\n BFD_RELOC_BPF_DISP32,\n+ BFD_RELOC_BPF_DISP16,\n \n /* Adapteva EPIPHANY - 8 bit signed pc-relative displacement */\n BFD_RELOC_EPIPHANY_SIMM8,\ndiff --git a/bfd/bpf-reloc.def b/bfd/bpf-reloc.def\nindex b1be2eb66f6..31f761d291d 100644\n--- a/bfd/bpf-reloc.def\n+++ b/bfd/bpf-reloc.def\n@@ -72,3 +72,18 @@\n 0xffffffff, /* src_mask */\n 0xffffffff, /* dst_mask */\n true) /* pcrel_offset */\n+\n+ /* 16-bit PC-relative address in load instructions. */\n+ BPF_HOWTO (R_BPF_GNU_64_16, /* type */\n+ 0, /* rightshift */\n+ 2, /* size */\n+ 16, /* bitsize */\n+ true, /* pc_relative */\n+ 16, /* bitpos */\n+ complain_overflow_signed, /* complain_on_overflow */\n+ bpf_elf_generic_reloc, /* special_function */\n+ \"R_BPF_GNU_64_16\", /* name */\n+ true, /* partial_inplace */\n+ 0xffff, /* src_mask */\n+ 0xffff, /* dst_mask */\n+ true) /* pcrel_offset */\ndiff --git a/bfd/elf64-bpf.c b/bfd/elf64-bpf.c\nindex 65418d1d740..23ede4e5d96 100644\n--- a/bfd/elf64-bpf.c\n+++ b/bfd/elf64-bpf.c\n@@ -89,6 +89,8 @@ bpf_reloc_type_lookup (bfd * abfd ATTRIBUTE_UNUSED,\n return &bpf_elf_howto_table[ (int) R_BPF_64_64_IDX];\n case BFD_RELOC_BPF_DISP32:\n return &bpf_elf_howto_table[ (int) R_BPF_64_32_IDX];\n+ case BFD_RELOC_BPF_DISP16:\n+ return &bpf_elf_howto_table[ (int) R_BPF_GNU_64_16_IDX];\n \n default:\n /* Pacify gcc -Wall. */\ndiff --git a/bfd/libbfd.h b/bfd/libbfd.h\nindex d4fb3107597..5dbb0871607 100644\n--- a/bfd/libbfd.h\n+++ b/bfd/libbfd.h\n@@ -3346,6 +3346,7 @@ static const char *const bfd_reloc_code_real_names[] = { \"@@uninitialized@@\",\n \"BFD_RELOC_TILEGX_IMM8_Y1_TLS_ADD\",\n \"BFD_RELOC_BPF_64\",\n \"BFD_RELOC_BPF_DISP32\",\n+ \"BFD_RELOC_BPF_DISP16\",\n \"BFD_RELOC_EPIPHANY_SIMM8\",\n \"BFD_RELOC_EPIPHANY_SIMM24\",\n \"BFD_RELOC_EPIPHANY_HIGH\",\ndiff --git a/bfd/reloc.c b/bfd/reloc.c\nindex fbc67ac7280..e71a510e26c 100644\n--- a/bfd/reloc.c\n+++ b/bfd/reloc.c\n@@ -7753,6 +7753,8 @@ ENUM\n BFD_RELOC_BPF_64\n ENUMX\n BFD_RELOC_BPF_DISP32\n+ENUMX\n+ BFD_RELOC_BPF_DISP16\n ENUMDOC\n Linux eBPF relocations.\n \ndiff --git a/gas/config/tc-bpf.c b/gas/config/tc-bpf.c\nindex 3b86f9c89cb..7a54faccb59 100644\n--- a/gas/config/tc-bpf.c\n+++ b/gas/config/tc-bpf.c\n@@ -22,42 +22,42 @@\n #include \"as.h\"\n #include \"subsegs.h\"\n #include \"symcat.h\"\n-#include \"opcodes/bpf-desc.h\"\n-#include \"opcodes/bpf-opc.h\"\n-#include \"cgen.h\"\n+#include \"opcode/bpf.h\"\n #include \"elf/common.h\"\n #include \"elf/bpf.h\"\n #include \"dwarf2dbg.h\"\n+#include \"libiberty.h\"\n #include \n \n+/* Data structure representing a parsed BPF instruction. */\n+\n+struct bpf_insn\n+{\n+ int size; /* Instruction size in bytes. */\n+ bpf_insn_word opcode;\n+ uint8_t dst;\n+ uint8_t src;\n+ expressionS offset16;\n+ expressionS imm32;\n+ expressionS imm64;\n+ expressionS disp16;\n+ expressionS disp32;\n+\n+ unsigned int has_dst : 1;\n+ unsigned int has_src : 1;\n+ unsigned int has_offset16 : 1;\n+ unsigned int has_disp16 : 1;\n+ unsigned int has_disp32 : 1;\n+ unsigned int has_imm32 : 1;\n+ unsigned int has_imm64 : 1;\n+};\n+\n const char comment_chars[] = \";\";\n const char line_comment_chars[] = \"#\";\n const char line_separator_chars[] = \"`\";\n const char EXP_CHARS[] = \"eE\";\n const char FLT_CHARS[] = \"fFdD\";\n \n-static const char *invalid_expression;\n-static char pseudoc_lex[256];\n-static const char symbol_chars[] =\n-\"_ABCDEFGHIJKLMNOPQRSTUVWXYZabcdefghijklmnopqrstuvwxyz0123456789\";\n-\n-static const char arithm_op[] = \"+-/<>%&|^\";\n-\n-static void init_pseudoc_lex (void);\n-\n-#define LEX_IS_SYMBOL_COMPONENT 1\n-#define LEX_IS_WHITESPACE 2\n-#define LEX_IS_NEWLINE 3\n-#define LEX_IS_ARITHM_OP 4\n-#define LEX_IS_STAR 6\n-#define LEX_IS_CLSE_BR 7\n-#define LEX_IS_OPEN_BR 8\n-#define LEX_IS_EQUAL 9\n-#define LEX_IS_EXCLA 10\n-\n-#define ST_EOI 100\n-#define MAX_TOKEN_SZ 100\n-\n /* Like s_lcomm_internal in gas/read.c but the alignment string\n is allowed to be optional. */\n \n@@ -110,18 +110,15 @@ const pseudo_typeS md_pseudo_table[] =\n \n \f\n \n-/* ISA handling. */\n-static CGEN_BITSET *bpf_isa;\n-\n-\f\n-\n /* Command-line options processing. */\n \n enum options\n {\n OPTION_LITTLE_ENDIAN = OPTION_MD_BASE,\n OPTION_BIG_ENDIAN,\n- OPTION_XBPF\n+ OPTION_XBPF,\n+ OPTION_DIALECT,\n+ OPTION_ISA_SPEC,\n };\n \n struct option md_longopts[] =\n@@ -129,6 +126,8 @@ struct option md_longopts[] =\n { \"EL\", no_argument, NULL, OPTION_LITTLE_ENDIAN },\n { \"EB\", no_argument, NULL, OPTION_BIG_ENDIAN },\n { \"mxbpf\", no_argument, NULL, OPTION_XBPF },\n+ { \"mdialect\", required_argument, NULL, OPTION_DIALECT},\n+ { \"misa-spec\", required_argument, NULL, OPTION_ISA_SPEC},\n { NULL, no_argument, NULL, 0 },\n };\n \n@@ -136,18 +135,34 @@ size_t md_longopts_size = sizeof (md_longopts);\n \n const char * md_shortopts = \"\";\n \n-extern int target_big_endian;\n+/* BPF supports little-endian and big-endian variants. The following\n+ global records what endianness to use. It can be configured using\n+ command-line options. It defaults to the host endianness\n+ initialized in md_begin. */\n \n-/* Whether target_big_endian has been set while parsing command-line\n- arguments. */\n static int set_target_endian = 0;\n+extern int target_big_endian;\n+\n+/* The ISA specification can be one of BPF_V1, BPF_V2, BPF_V3, BPF_V4\n+ or BPF_XPBF. The ISA spec to use can be configured using\n+ command-line options. It defaults to the latest BPF spec. */\n+\n+static int isa_spec = BPF_V4;\n \n-static int target_xbpf = 0;\n+/* The assembler supports two different dialects: \"normal\" syntax and\n+ \"pseudoc\" syntax. The dialect to use can be configured using\n+ command-line options. */\n \n-static int set_xbpf = 0;\n+enum target_asm_dialect\n+{\n+ DIALECT_NORMAL,\n+ DIALECT_PSEUDOC\n+};\n+\n+static int asm_dialect = DIALECT_NORMAL;\n \n int\n-md_parse_option (int c, const char * arg ATTRIBUTE_UNUSED)\n+md_parse_option (int c, const char * arg)\n {\n switch (c)\n {\n@@ -156,12 +171,36 @@ md_parse_option (int c, const char * arg ATTRIBUTE_UNUSED)\n target_big_endian = 1;\n break;\n case OPTION_LITTLE_ENDIAN:\n- set_target_endian = 1;\n+ set_target_endian = 0;\n target_big_endian = 0;\n break;\n+ case OPTION_DIALECT:\n+ if (strcmp (arg, \"normal\") == 0)\n+ asm_dialect = DIALECT_NORMAL;\n+ else if (strcmp (arg, \"pseudoc\") == 0)\n+ asm_dialect = DIALECT_PSEUDOC;\n+ else\n+ as_fatal (_(\"-mdialect=%s is not valid. Expected normal or pseudoc\"),\n+ arg);\n+ break;\n+ case OPTION_ISA_SPEC:\n+ if (strcmp (arg, \"v1\") == 0)\n+ isa_spec = BPF_V1;\n+ else if (strcmp (arg, \"v2\") == 0)\n+ isa_spec = BPF_V2;\n+ else if (strcmp (arg, \"v3\") == 0)\n+ isa_spec = BPF_V3;\n+ else if (strcmp (arg, \"v4\") == 0)\n+ isa_spec = BPF_V4;\n+ else if (strcmp (arg, \"xbpf\") == 0)\n+ isa_spec = BPF_XBPF;\n+ else\n+ as_fatal (_(\"-misa-spec=%s is not valid. Expected v1, v2, v3, v4 o xbpf\"),\n+ arg);\n+ break;\n case OPTION_XBPF:\n- set_xbpf = 1;\n- target_xbpf = 1;\n+ /* This is an alias for -misa-spec=xbpf. */\n+ isa_spec = BPF_XBPF;\n break;\n default:\n return 0;\n@@ -175,43 +214,22 @@ md_show_usage (FILE * stream)\n {\n fprintf (stream, _(\"\\nBPF options:\\n\"));\n fprintf (stream, _(\"\\\n- --EL\t\t\tgenerate code for a little endian machine\\n\\\n- --EB\t\t\tgenerate code for a big endian machine\\n\\\n- -mxbpf generate xBPF instructions\\n\"));\n+BPF options:\\n\\\n+ -EL generate code for a little endian machine\\n\\\n+ -EB generate code for a big endian machine\\n\\\n+ -mdialect=DIALECT set the assembly dialect (normal, pseudoc)\\n\\\n+ -misa-spec set the BPF ISA spec (v1, v2, v3, v4, xbpf)\\n\\\n+ -mxbpf alias for -misa-spec=xbpf\\n\"));\n }\n \n \f\n-\n-static void\n-init_pseudoc_lex (void)\n-{\n- const char *p;\n-\n- for (p = symbol_chars; *p; ++p)\n- pseudoc_lex[(unsigned char) *p] = LEX_IS_SYMBOL_COMPONENT;\n-\n- pseudoc_lex[' '] = LEX_IS_WHITESPACE;\n- pseudoc_lex['\\t'] = LEX_IS_WHITESPACE;\n- pseudoc_lex['\\r'] = LEX_IS_WHITESPACE;\n- pseudoc_lex['\\n'] = LEX_IS_NEWLINE;\n- pseudoc_lex['*'] = LEX_IS_STAR;\n- pseudoc_lex[')'] = LEX_IS_CLSE_BR;\n- pseudoc_lex['('] = LEX_IS_OPEN_BR;\n- pseudoc_lex[']'] = LEX_IS_CLSE_BR;\n- pseudoc_lex['['] = LEX_IS_OPEN_BR;\n-\n- for (p = arithm_op; *p; ++p)\n- pseudoc_lex[(unsigned char) *p] = LEX_IS_ARITHM_OP;\n-\n- pseudoc_lex['='] = LEX_IS_EQUAL;\n- pseudoc_lex['!'] = LEX_IS_EXCLA;\n-}\n+/* This function is called once, at assembler startup time. This\n+ should set up all the tables, etc that the MD part of the assembler\n+ needs. */\n \n void\n md_begin (void)\n {\n- /* Initialize the `cgen' interface. */\n-\n /* If not specified in the command line, use the host\n endianness. */\n if (!set_target_endian)\n@@ -223,50 +241,15 @@ md_begin (void)\n #endif\n }\n \n- /* If not specified in the command line, use eBPF rather\n- than xBPF. */\n- if (!set_xbpf)\n- target_xbpf = 0;\n-\n- /* Set the ISA, which depends on the target endianness. */\n- bpf_isa = cgen_bitset_create (ISA_MAX);\n- if (target_big_endian)\n- {\n- if (target_xbpf)\n-\tcgen_bitset_set (bpf_isa, ISA_XBPFBE);\n- else\n-\tcgen_bitset_set (bpf_isa, ISA_EBPFBE);\n- }\n- else\n- {\n- if (target_xbpf)\n-\tcgen_bitset_set (bpf_isa, ISA_XBPFLE);\n- else\n-\tcgen_bitset_set (bpf_isa, ISA_EBPFLE);\n- }\n-\n /* Ensure that lines can begin with '*' in BPF store pseudoc instruction. */\n lex_type['*'] |= LEX_BEGIN_NAME;\n \n- /* Set the machine number and endian. */\n- gas_cgen_cpu_desc = bpf_cgen_cpu_open (CGEN_CPU_OPEN_ENDIAN,\n- target_big_endian ?\n- CGEN_ENDIAN_BIG : CGEN_ENDIAN_LITTLE,\n- CGEN_CPU_OPEN_INSN_ENDIAN,\n- CGEN_ENDIAN_LITTLE,\n- CGEN_CPU_OPEN_ISAS,\n- bpf_isa,\n- CGEN_CPU_OPEN_END);\n- bpf_cgen_init_asm (gas_cgen_cpu_desc);\n-\n- /* This is a callback from cgen to gas to parse operands. */\n- cgen_set_parse_operand_fn (gas_cgen_cpu_desc, gas_cgen_parse_operand);\n-\n /* Set the machine type. */\n bfd_default_set_arch_mach (stdoutput, bfd_arch_bpf, bfd_mach_bpf);\n- init_pseudoc_lex();\n }\n \n+/* Round up a section size to the appropriate boundary. */\n+\n valueT\n md_section_align (segT segment, valueT size)\n {\n@@ -310,33 +293,48 @@ md_number_to_chars (char * buf, valueT val, int n)\n }\n \n arelent *\n-tc_gen_reloc (asection *sec, fixS *fix)\n+tc_gen_reloc (asection *sec ATTRIBUTE_UNUSED, fixS *fixP)\n {\n- return gas_cgen_tc_gen_reloc (sec, fix);\n-}\n+ bfd_reloc_code_real_type r_type = fixP->fx_r_type;\n+ arelent *reloc;\n \n-/* Return the bfd reloc type for OPERAND of INSN at fixup FIXP. This\n- is called when the operand is an expression that couldn't be fully\n- resolved. Returns BFD_RELOC_NONE if no reloc type can be found.\n- *FIXP may be modified if desired. */\n+ reloc = XNEW (arelent);\n \n-bfd_reloc_code_real_type\n-md_cgen_lookup_reloc (const CGEN_INSN *insn ATTRIBUTE_UNUSED,\n-\t\t const CGEN_OPERAND *operand,\n-\t\t fixS *fixP)\n-{\n- switch (operand->type)\n+ if (fixP->fx_pcrel)\n+ {\n+ r_type = (r_type == BFD_RELOC_8 ? BFD_RELOC_8_PCREL\n+ : r_type == BFD_RELOC_16 ? BFD_RELOC_16_PCREL\n+ : r_type == BFD_RELOC_24 ? BFD_RELOC_24_PCREL\n+ : r_type == BFD_RELOC_32 ? BFD_RELOC_32_PCREL\n+ : r_type == BFD_RELOC_64 ? BFD_RELOC_64_PCREL\n+ : r_type);\n+ }\n+\n+ reloc->howto = bfd_reloc_type_lookup (stdoutput, r_type);\n+\n+ if (reloc->howto == (reloc_howto_type *) NULL)\n {\n- case BPF_OPERAND_IMM64:\n- return BFD_RELOC_BPF_64;\n- case BPF_OPERAND_DISP32:\n- fixP->fx_pcrel = 1;\n- return BFD_RELOC_BPF_DISP32;\n- default:\n- break;\n+ as_bad_where (fixP->fx_file, fixP->fx_line,\n+\t\t _(\"relocation is not supported\"));\n+ return NULL;\n }\n- return BFD_RELOC_NONE;\n+\n+ //XXX gas_assert (!fixP->fx_pcrel == !reloc->howto->pc_relative);\n+\n+ reloc->sym_ptr_ptr = XNEW (asymbol *);\n+ *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixP->fx_addsy);\n+\n+ /* Use fx_offset for these cases. */\n+ if (fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY\n+ || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT)\n+ reloc->addend = fixP->fx_offset;\n+ else\n+ reloc->addend = fixP->fx_addnumber;\n+\n+ reloc->address = fixP->fx_frag->fr_address + fixP->fx_where;\n+ return reloc;\n }\n+\n \f\n /* *FRAGP has been relaxed to its final size, and now needs to have\n the bytes inside it modified to conform to the new size.\n@@ -362,1556 +360,821 @@ md_estimate_size_before_relax (fragS *fragP ATTRIBUTE_UNUSED,\n }\n \n \f\n+/* Apply a fixS (fixup of an instruction or data that we didn't have\n+ enough info to complete immediately) to the data in a frag. */\n+\n void\n-md_apply_fix (fixS *fixP, valueT *valP, segT seg)\n+md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)\n {\n- /* Some fixups for instructions require special attention. This is\n- handled in the code block below. */\n- if ((int) fixP->fx_r_type >= (int) BFD_RELOC_UNUSED)\n+ char *where = fixP->fx_frag->fr_literal + fixP->fx_where;\n+\n+ switch (fixP->fx_r_type)\n {\n- int opindex = (int) fixP->fx_r_type - (int) BFD_RELOC_UNUSED;\n- const CGEN_OPERAND *operand = cgen_operand_lookup_by_num (gas_cgen_cpu_desc,\n- opindex);\n- char *where;\n+ case BFD_RELOC_BPF_DISP16:\n+ /* Convert from bytes to number of 64-bit words to the target,\n+ minus one. */\n+ *valP = (((long) (*valP)) - 8) / 8;\n+ break;\n+ case BFD_RELOC_BPF_DISP32:\n+ /* eBPF supports two kind of CALL instructions: the so called\n+ pseudo calls (\"bpf to bpf\") and external calls (\"bpf to\n+ kernel\").\n+\n+ Both kind of calls use the same instruction (CALL). However,\n+ external calls are constructed by passing a constant argument\n+ to the instruction, whereas pseudo calls result from\n+ expressions involving symbols. In practice, instructions\n+ requiring a fixup are interpreted as pseudo-calls. If we are\n+ executing this code, this is a pseudo call.\n+\n+ The kernel expects for pseudo-calls to be annotated by having\n+ BPF_PSEUDO_CALL in the SRC field of the instruction. But\n+ beware the infamous nibble-swapping of eBPF and take\n+ endianness into account here.\n+\n+ Note that the CALL instruction has only one operand, so\n+ this code is executed only once per instruction. */\n+ md_number_to_chars (where + 1, target_big_endian ? 0x01 : 0x10, 1);\n+\n+ /* Convert from bytes to number of 64-bit words to the target,\n+ minus one. */\n+ *valP = (((long) (*valP)) - 8) / 8;\n+ break;\n+ case BFD_RELOC_16_PCREL:\n+ /* Convert from bytes to number of 64-bit words to the target,\n+ minus one. */\n+ *valP = (((long) (*valP)) - 8) / 8;\n+ break;\n+ default:\n+ break;\n+ }\n \n- switch (operand->type)\n- {\n- case BPF_OPERAND_DISP32:\n- /* eBPF supports two kind of CALL instructions: the so\n- called pseudo calls (\"bpf to bpf\") and external calls\n- (\"bpf to kernel\").\n-\n- Both kind of calls use the same instruction (CALL).\n- However, external calls are constructed by passing a\n- constant argument to the instruction, whereas pseudo\n- calls result from expressions involving symbols. In\n- practice, instructions requiring a fixup are interpreted\n- as pseudo-calls. If we are executing this code, this is\n- a pseudo call.\n-\n- The kernel expects for pseudo-calls to be annotated by\n- having BPF_PSEUDO_CALL in the SRC field of the\n- instruction. But beware the infamous nibble-swapping of\n- eBPF and take endianness into account here.\n-\n- Note that the CALL instruction has only one operand, so\n- this code is executed only once per instruction. */\n- where = fixP->fx_frag->fr_literal + fixP->fx_where + 1;\n- where[0] = target_big_endian ? 0x01 : 0x10;\n- /* Fallthrough. */\n- case BPF_OPERAND_DISP16:\n- /* The PC-relative displacement fields in jump instructions\n- shouldn't be in bytes. Instead, they hold the number of\n- 64-bit words to the target, _minus one_. */ \n- *valP = (((long) (*valP)) - 8) / 8;\n+ if (fixP->fx_addsy == (symbolS *) NULL)\n+ fixP->fx_done = 1;\n+\n+ if (fixP->fx_done)\n+ {\n+ /* We're finished with this fixup. Install it because\n+\t bfd_install_relocation won't be called to do it. */\n+ switch (fixP->fx_r_type)\n+\t{\n+\tcase BFD_RELOC_8:\n+\t md_number_to_chars (where, *valP, 1);\n+\t break;\n+\tcase BFD_RELOC_16:\n+\t md_number_to_chars (where, *valP, 2);\n+\t break;\n+\tcase BFD_RELOC_32:\n+\t md_number_to_chars (where, *valP, 4);\n+\t break;\n+\tcase BFD_RELOC_64:\n+\t md_number_to_chars (where, *valP, 8);\n+\t break;\n+ case BFD_RELOC_BPF_DISP16:\n+ md_number_to_chars (where + 2, (uint16_t) *valP, 2);\n break;\n- default:\n+ case BFD_RELOC_BPF_DISP32:\n+ md_number_to_chars (where + 4, (uint32_t) *valP, 4);\n break;\n- }\n+ case BFD_RELOC_16_PCREL:\n+ md_number_to_chars (where + 2, (uint32_t) *valP, 2);\n+ break;\n+\tdefault:\n+\t as_bad_where (fixP->fx_file, fixP->fx_line,\n+\t\t\t_(\"internal error: can't install fix for reloc type %d (`%s')\"),\n+\t\t\tfixP->fx_r_type, bfd_get_reloc_code_name (fixP->fx_r_type));\n+\t break;\n+\t}\n }\n \n- /* And now invoke CGEN's handler, which will eventually install\n- *valP into the corresponding operand. */\n- gas_cgen_md_apply_fix (fixP, valP, seg);\n+ /* Tuck `value' away for use by tc_gen_reloc.\n+ See the comment describing fx_addnumber in write.h.\n+ This field is misnamed (or misused :-). */\n+ fixP->fx_addnumber = *valP;\n }\n \n-/*\n- The BPF pseudo grammar:\n-\n-\tinstruction : bpf_alu_insn\n-\t\t | bpf_alu32_insn\n-\t\t | bpf_jump_insn\n-\t\t | bpf_load_store_insn\n-\t\t | bpf_load_store32_insn\n-\t\t | bpf_non_generic_load\n-\t\t | bpf_endianness_conv_insn\n-\t\t | bpf_64_imm_load_insn\n-\t\t | bpf_atomic_insn\n-\t\t ;\n-\n-\tbpf_alu_insn : BPF_REG bpf_alu_operator register_or_imm32\n-\t\t ;\n-\n-\tbpf_alu32_insn : BPF_REG32 bpf_alu_operator register32_or_imm32\n-\t\t ;\n-\n-\tbpf_jump_insn : BPF_JA offset\n-\t\t | IF BPF_REG bpf_jump_operator register_or_imm32 BPF_JA offset\n-\t\t | IF BPF_REG32 bpf_jump_operator register_or_imm32 BPF_JA offset\n-\t\t | BPF_CALL offset\n-\t\t | BPF_EXIT\n-\t\t ;\n-\n-\tbpf_load_store_insn : BPF_REG CHR_EQUAL bpf_size_cast BPF_CHR_OPEN_BR \\\n-\t\t\t register_and_offset BPF_CHR_CLSE_BR\n-\t\t\t | bpf_size_cast register_and_offset CHR_EQUAL BPF_REG\n-\t\t\t ;\n-\n-\tbpf_load_store32_insn : BPF_REG CHR_EQUAL bpf_size_cast BPF_CHR_OPEN_BR \\\n-\t\t\t\t register32_and_offset BPF_CHR_CLSE_BR\n-\t\t\t | bpf_size_cast register_and_offset CHR_EQUAL BPF_REG32\n-\t\t\t ;\n-\n-\tbpf_non_generic_load : BPF_REG_R0 CHR_EQUAL bpf_size_cast BPF_LD BPF_CHR_OPEN_BR \\\n-\t\t\t imm32 BPF_CHR_CLSE_BR\n-\t\t\t ;\n-\n-\tbpf_endianness_conv_insn : BPF_REG_N bpf_endianness_mnem BPF_REG_N\n-\t\t\t\t ;\n-\n-\tbpf_64_imm_load_insn : BPF_REG imm64 BPF_LL\n-\t\t\t ;\n-\n-\tbpf_atomic_insn : BPF_LOCK bpf_size_cast_32_64 register_and_offset BPF_ADD BPF_REG\n-\n-\tregister_and_offset : BPF_CHR_OPEN_BR BPF_REG offset BPF_CHR_CLSE_BR\n-\t\t\t ;\n-\n-\tregister32_and_offset : BPF_CHR_OPEN_BR BPF_REG32 offset BPF_CHR_CLSE_BR\n-\t\t\t ;\n-\n-\tbpf_size_cast : CHR_START BPF_CHR_OPEN_BR bpf_size CHR_START BPF_CHR_CLSE_BR\n-\t\t ;\n-\n-\tbpf_size_cast_32_64 : CHR_START BPF_CHR_OPEN_BR bpf_size_cast_32_64 CHR_STAR BPF_CHR_CLSE_BR\n-\t\t\t ;\n-\n-\tbpf_size_32_64 : BPF_CAST_U32\n-\t\t | BPF_CAST_U64\n-\t\t ;\n-\n-\tbpf_size : BPF_CAST_U8\n-\t\t | BPF_CAST_U16\n-\t\t | BPF_CAST_U32\n-\t\t | BPF_CAST_U64\n-\t\t ;\n-\n-\tbpf_jump_operator : BPF_JEQ\n-\t\t\t | BPF_JGT\n-\t\t\t | BPF_JGE\n-\t\t\t | BPF_JNE\n-\t\t\t | BPF_JSGT\n-\t\t\t | BPF_JSGE\n-\t\t\t | BPF_JLT\n-\t\t\t | BPF_JLE\n-\t\t\t | BPF_JSLT\n-\t\t\t | BPF_JSLE\n-\t\t\t ;\n-\n-\tbpf_alu_operator : BPF_ADD\n-\t\t\t | BPF_SUB\n-\t\t\t | BPF_MUL\n-\t\t\t | BPF_DIV\n-\t\t\t | BPF_OR\n-\t\t\t | BPF_AND\n-\t\t\t | BPF_LSH\n-\t\t\t | BPF_RSH\n-\t\t\t | BPF_NEG\n-\t\t\t | BPF_MOD\n-\t\t\t | BPF_XOR\n-\t\t\t | BPF_ARSH\n-\t\t\t | CHR_EQUAL\n-\t\t\t ;\n-\n-\tbpf_endianness_mnem : BPF_LE16\n-\t\t\t | BPF_LE32\n-\t\t\t | BPF_LE64\n-\t\t\t | BPF_BE16\n-\t\t\t | BPF_BE32\n-\t\t\t | BPF_BE64\n-\t\t\t ;\n-\n-\toffset : BPF_EXPR\n-\t | BPF_SYMBOL\n-\t ;\n-\n-\tregister_or_imm32 : BPF_REG\n-\t\t\t | expression\n-\t\t\t ;\n-\n-\tregister32_or_imm32 : BPF_REG32\n-\t\t\t | expression\n-\t\t\t ;\n-\n-\timm32 : BPF_EXPR\n-\t | BPF_SYMBOL\n-\t ;\n-\n-\timm64 : BPF_EXPR\n-\t | BPF_SYMBOL\n-\t ;\n-\n-\tregister_or_expression : BPF_EXPR\n-\t\t\t | BPF_REG\n-\t\t\t ;\n-\n-\tBPF_EXPR : GAS_EXPR\n-\n-*/\n-\n-enum bpf_token_type\n- {\n- /* Keep grouped to quickly access. */\n- BPF_ADD,\n- BPF_SUB,\n- BPF_MUL,\n- BPF_DIV,\n- BPF_OR,\n- BPF_AND,\n- BPF_LSH,\n- BPF_RSH,\n- BPF_MOD,\n- BPF_XOR,\n- BPF_MOV,\n- BPF_ARSH,\n- BPF_NEG,\n-\n- BPF_REG,\n-\n- BPF_IF,\n- BPF_GOTO,\n-\n- /* Keep grouped to quickly access. */\n- BPF_JEQ,\n- BPF_JGT,\n- BPF_JGE,\n- BPF_JLT,\n- BPF_JLE,\n- BPF_JSET,\n- BPF_JNE,\n- BPF_JSGT,\n- BPF_JSGE,\n- BPF_JSLT,\n- BPF_JSLE,\n-\n- BPF_SYMBOL,\n- BPF_CHR_CLSE_BR,\n- BPF_CHR_OPEN_BR,\n-\n- /* Keep grouped to quickly access. */\n- BPF_CAST_U8,\n- BPF_CAST_U16,\n- BPF_CAST_U32,\n- BPF_CAST_U64,\n-\n- /* Keep grouped to quickly access. */\n- BPF_LE16,\n- BPF_LE32,\n- BPF_LE64,\n- BPF_BE16,\n- BPF_BE32,\n- BPF_BE64,\n-\n- BPF_LOCK,\n-\n- BPF_IND_CALL,\n- BPF_LD,\n- BPF_LL,\n- BPF_EXPR,\n- BPF_UNKNOWN,\n- };\n-\n-static int\n-valid_expr (const char *e, const char **end_expr)\n-{\n- invalid_expression = NULL;\n- char *hold = input_line_pointer;\n- expressionS exp;\n-\n- input_line_pointer = (char *) e;\n- deferred_expression (&exp);\n- *end_expr = input_line_pointer;\n- input_line_pointer = hold;\n+/* Parse an operand expression. Returns the first character that is\n+ not part of the expression, or NULL in case of parse error.\n \n- return invalid_expression == NULL;\n-}\n+ See md_operand below to see how exp_parse_failed is used. */\n \n-static char *\n-build_bpf_non_generic_load (char *src, enum bpf_token_type cast,\n-\t\t\t const char *imm32)\n-{\n- char *bpf_insn;\n- static const char *cast_rw[] = {\"b\", \"h\", \"w\", \"dw\"};\n-\n- bpf_insn = xasprintf (\"%s%s%s %s%s%s%s\",\n-\t\t\t\"ld\",\n-\t\t\tsrc ? \"ind\" : \"abs\",\n-\t\t\tcast_rw[cast - BPF_CAST_U8],\n-\t\t\tsrc ? \"%\" : \"\",\n-\t\t\tsrc ? src : \"\",\n-\t\t\tsrc ? \",\" : \"\",\n-\t\t\timm32);\n- return bpf_insn;\n-}\n+static int exp_parse_failed = 0;\n \n static char *\n-build_bpf_atomic_insn (char *dst, char *src,\n-\t\t enum bpf_token_type atomic_insn,\n-\t\t enum bpf_token_type cast,\n-\t\t const char *offset)\n+parse_expression (char *s, expressionS *exp)\n {\n- char *bpf_insn;\n- static const char *cast_rw[] = {\"w\", \"dw\"};\n- static const char *mnem[] = {\"xadd\"};\n-\n- bpf_insn = xasprintf (\"%s%s [%%%s%s%s],%%%s\", mnem[atomic_insn - BPF_ADD],\n-\t\t\tcast_rw[cast - BPF_CAST_U32], dst,\n-\t\t\t*offset != '+' ? \"+\" : \"\",\n-\t\t\toffset, src);\n- return bpf_insn;\n-}\n+ char *saved_input_line_pointer = input_line_pointer;\n+ char *saved_s = s;\n \n-static char *\n-build_bpf_jmp_insn (char *dst, char *src,\n-\t\t char *imm32, enum bpf_token_type op,\n-\t\t const char *sym, const char *offset)\n-{\n- char *bpf_insn;\n- static const char *mnem[] =\n- {\n- \"jeq\", \"jgt\", \"jge\", \"jlt\",\n- \"jle\", \"jset\", \"jne\", \"jsgt\",\n- \"jsge\", \"jslt\", \"jsle\"\n- };\n-\n- const char *in32 = (*dst == 'w' ? \"32\" : \"\");\n-\n- *dst = 'r';\n- if (src)\n- *src = 'r';\n-\n- bpf_insn = xasprintf (\"%s%s %%%s,%s%s,%s\",\n-\t\t\tmnem[op - BPF_JEQ], in32, dst,\n-\t\t\tsrc ? \"%\" : \"\",\n-\t\t\tsrc ? src : imm32,\n-\t\t\toffset ? offset : sym);\n- return bpf_insn;\n-}\n+ exp_parse_failed = 0;\n+ input_line_pointer = s;\n+ expression (exp);\n+ s = input_line_pointer;\n+ input_line_pointer = saved_input_line_pointer;\n \n-static char *\n-build_bpf_arithm_insn (char *dst, char *src,\n-\t\t int load64, const char *imm32,\n-\t\t enum bpf_token_type type)\n-{\n- char *bpf_insn;\n- static const char *mnem[] =\n- {\n- \"add\", \"sub\", \"mul\", \"div\",\n- \"or\", \"and\", \"lsh\", \"rsh\",\n- \"mod\", \"xor\", \"mov\", \"arsh\",\n- \"neg\",\n- };\n- const char *in32 = (*dst == 'w' ? \"32\" : \"\");\n-\n- *dst = 'r';\n- if (src)\n- *src = 'r';\n-\n- if (type == BPF_NEG)\n- bpf_insn = xasprintf (\"%s%s %%%s\", mnem[type - BPF_ADD], in32, dst);\n- else if (load64)\n- bpf_insn = xasprintf (\"%s %%%s,%s\", \"lddw\", dst, imm32);\n- else\n- bpf_insn = xasprintf (\"%s%s %%%s,%s%s\", mnem[type - BPF_ADD],\n-\t\t\t in32, dst,\n-\t\t\t src ? \"%\" : \"\",\n-\t\t\t src ? src: imm32);\n- return bpf_insn;\n-}\n+ switch (exp->X_op == O_absent || exp_parse_failed)\n+ return NULL;\n \n-static char *\n-build_bpf_endianness (char *dst, enum bpf_token_type endianness)\n-{\n- char *bpf_insn;\n- static const char *size[] = {\"16\", \"32\", \"64\"};\n- int be = 1;\n-\n- if (endianness == BPF_LE16\n- || endianness == BPF_LE32\n- || endianness == BPF_LE64)\n- be = 0;\n- else\n- gas_assert (endianness == BPF_BE16 || endianness == BPF_BE32 || endianness == BPF_BE64);\n+ /* The expression parser may consume trailing whitespaces. We have\n+ to undo that since the instruction templates may be expecting\n+ these whitespaces. */\n+ {\n+ char *p;\n+ for (p = s - 1; p >= saved_s && *p == ' '; --p)\n+ --s;\n+ }\n \n- bpf_insn = xasprintf (\"%s %%%s,%s\", be ? \"endbe\" : \"endle\",\n-\t\t\tdst, be ? size[endianness - BPF_BE16] : size[endianness - BPF_LE16]);\n- return bpf_insn;\n+ return s;\n }\n \n-static char *\n-build_bpf_load_store_insn (char *dst, char *src,\n-\t\t\t enum bpf_token_type cast,\n-\t\t\t const char *offset, int isload)\n-{\n- char *bpf_insn;\n- static const char *cast_rw[] = {\"b\", \"h\", \"w\", \"dw\"};\n-\n- *dst = *src = 'r';\n- if (isload)\n- bpf_insn = xasprintf (\"%s%s %%%s,[%%%s%s%s]\", \"ldx\",\n-\t\t\t cast_rw[cast - BPF_CAST_U8], dst, src,\n-\t\t\t *offset != '+' ? \"+\" : \"\",\n-\t\t\t offset);\n- else\n- bpf_insn = xasprintf (\"%s%s [%%%s%s%s],%%%s\", \"stx\",\n-\t\t\t cast_rw[cast - BPF_CAST_U8], dst,\n-\t\t\t *offset != '+' ? \"+\" : \"\",\n-\t\t\t offset, src);\n- return bpf_insn;\n-}\n+/* Parse a BPF register name and return the corresponding register\n+ number. Return NULL in case of parse error, or a pointer to the\n+ first character in S that is not part of the register name. */\n \n-static int\n-look_for_reserved_word (const char *token, enum bpf_token_type *type)\n+static char *\n+parse_bpf_register (char *s, char rw, uint8_t *regno)\n {\n- int i;\n- static struct\n- {\n- const char *name;\n- enum bpf_token_type type;\n- } reserved_words[] =\n+ if (asm_dialect == DIALECT_NORMAL)\n {\n- {\n-\t.name = \"if\",\n-\t.type = BPF_IF\n- },\n- {\n-\t.name = \"goto\",\n-\t.type = BPF_GOTO\n- },\n- {\n-\t.name = \"le16\",\n-\t.type = BPF_LE16\n- },\n- {\n-\t.name = \"le32\",\n-\t.type = BPF_LE32\n- },\n- {\n-\t.name = \"le64\",\n-\t.type = BPF_LE64\n- },\n- {\n-\t.name = \"be16\",\n-\t.type = BPF_BE16\n- },\n- {\n-\t.name = \"be32\",\n-\t.type = BPF_BE32\n- },\n- {\n-\t.name = \"be64\",\n-\t.type = BPF_BE64\n-\t},\n- {\n-\t.name = \"lock\",\n-\t.type = BPF_LOCK\n- },\n- {\n-\t.name = \"callx\",\n-\t.type = BPF_IND_CALL\n- },\n- {\n-\t.name = \"skb\",\n-\t.type = BPF_LD\n- },\n- {\n-\t.name = \"ll\",\n-\t.type = BPF_LL\n- },\n- {\n-\t.name = NULL,\n- }\n- };\n+ rw = 'r';\n+ if (*s != '%')\n+\treturn NULL;\n+ s += 1;\n \n- for (i = 0; reserved_words[i].name; ++i)\n- if (*reserved_words[i].name == *token\n-\t&& !strcmp (reserved_words[i].name, token))\n- {\n-\t*type = reserved_words[i].type;\n-\treturn 1;\n- }\n+ if (*s == 'f' && *(s + 1) == 'p')\n+\t{\n+\t *regno = 10;\n+\t s += 2;\n+\t return s;\n+\t}\n+ }\n \n- return 0;\n-}\n+ if (*s != rw)\n+ return NULL;\n+ s += 1;\n \n-static int\n-is_register (const char *token, int len)\n-{\n- if (token[0] == 'r' || token[0] == 'w')\n- if ((len == 2 && isdigit (token[1]))\n-\t|| (len == 3 && token[1] == '1' && token[2] == '0'))\n- return 1;\n+ if (*s == '1')\n+ {\n+ if (*(s + 1) == '0')\n+ {\n+ *regno = 10;\n+ s += 2;\n+ }\n+ else\n+ {\n+ *regno = 1;\n+ s += 1;\n+ }\n+ }\n+ else if (*s >= '0' && *s <= '9')\n+ {\n+ *regno = *s - '0';\n+ s += 1;\n+ }\n \n- return 0;\n+ return s;\n }\n \n-static enum bpf_token_type\n-is_cast (const char *token)\n-{\n- static const char *cast_rw[] = {\"u8\", \"u16\", \"u32\", \"u64\"};\n- unsigned int i;\n-\n- for (i = 0; i < ARRAY_SIZE (cast_rw); ++i)\n- if (!strcmp (token, cast_rw[i]))\n- return BPF_CAST_U8 + i;\n+/* Collect a parse error message. */\n \n- return BPF_UNKNOWN;\n-}\n+static int partial_match_length = 0;\n+static char *errmsg = NULL;\n \n-static enum bpf_token_type\n-get_token (const char **insn, char *token, size_t *tlen)\n+static void\n+parse_error (int length, const char *fmt, ...)\n {\n-#define GET()\t\t\t\t\t\\\n- (*str == '\\0'\t\t\t\t\t\\\n- ? EOF\t\t\t\t\t\\\n- : *(unsigned char *)(str++))\n-\n-#define UNGET() (--str)\n-\n-#define START_EXPR()\t\t\t \\\n- do\t\t\t\t\t \\\n- {\t\t\t\t\t \\\n- if (expr == NULL)\t\t\t \\\n-\texpr = str - 1;\t\t\t \\\n- } while (0)\n-\n-#define SCANNER_SKIP_WHITESPACE()\t\t\\\n- do\t\t\t\t\t\t\\\n- {\t\t\t\t\t\t\\\n- do\t\t\t\t\t\\\n-\tch = GET ();\t\t\t\t\\\n- while (ch != EOF\t\t\t\t\\\n-\t && ((ch) == ' ' || (ch) == '\\t'));\t\\\n- if (ch != EOF)\t\t\t\t\\\n-\tUNGET ();\t\t\t\t\\\n- } while (0)\n-\n- const char *str = *insn;\n- int ch, ch2 = 0;\n- enum bpf_token_type ttype = BPF_UNKNOWN;\n- size_t len = 0;\n- const char *expr = NULL;\n- const char *end_expr = NULL;\n- int state = 0;\n- int return_token = 0;\n-\n- while (1)\n+ if (length > partial_match_length)\n {\n- ch = GET ();\n-\n- if (ch == EOF || len > MAX_TOKEN_SZ)\n-\tbreak;\n-\n- switch (pseudoc_lex[(unsigned char) ch])\n-\t{\n-\tcase LEX_IS_WHITESPACE:\n-\t SCANNER_SKIP_WHITESPACE ();\n-\t return_token = 1;\n-\n-\t switch (state)\n-\t {\n-\t case 12: /* >' ' */\n-\t ttype = BPF_JGT;\n-\t break;\n-\n-\t case 17: /* ==' ' */\n-\t ttype = BPF_JEQ;\n-\t break;\n-\n-\t case 18: /* <' ' */\n-\t ttype = BPF_JLT;\n-\t break;\n-\n-\t case 20: /* &' ' */\n-\t ttype = BPF_JSET;\n-\t break;\n-\n-\t case 22: /* s<' '*/\n-\t ttype = BPF_JSLT;\n-\t break;\n-\n-\t case 14: /* s> ' ' */\n-\t ttype = BPF_JSGT;\n-\t break;\n-\n-\t case 16: /* =' ' */\n-\t ttype = BPF_MOV;\n-\t break;\n-\n-\t default:\n-\t return_token = 0;\n-\t }\n-\t break;\n-\n-\tcase LEX_IS_EXCLA:\n-\t token[len++] = ch;\n-\t state = 21;\n-\t break;\n-\n-\tcase LEX_IS_ARITHM_OP:\n-\t if (state == 16)\n-\t {\n-\t /* ='-' is handle as '=' */\n-\t UNGET ();\n-\t ttype = BPF_MOV;\n-\t return_token = 1;\n-\t break;\n-\t }\n-\n-\t START_EXPR();\n-\t token[len++] = ch;\n-\t switch (ch)\n-\t {\n-#define BPF_ARITHM_OP(op, type)\t\t\t\\\n-\t case (op):\t\t\t\\\n-\t\tstate = 6;\t\t\t\\\n-\t\tttype = (type);\t\t\t\\\n-\t\tbreak;\n-\n-\t BPF_ARITHM_OP('+', BPF_ADD);\n-\t BPF_ARITHM_OP('-', BPF_SUB);\n-\t BPF_ARITHM_OP('*', BPF_MUL);\n-\t BPF_ARITHM_OP('/', BPF_DIV);\n-\t BPF_ARITHM_OP('|', BPF_OR);\n-\t BPF_ARITHM_OP('%', BPF_MOD);\n-\t BPF_ARITHM_OP('^', BPF_XOR);\n-\n-\t case '&':\n-\t state = 20; /* '&' */\n-\t break;\n-\n-\t case '<':\n-\t switch (state)\n-\t\t{\n-\t\tcase 0:\n-\t\t state = 18; /* '<' */\n-\t\t break;\n-\n-\t\tcase 18:\n-\t\t state = 19; /* <'<' */\n-\t\t break;\n-\n-\t\tcase 8:\n-\t\t state = 22; /* s'<' */\n-\t\t break;\n-\t\t}\n-\t break;\n-\n-\t case '>':\n-\t switch (state)\n-\t\t{\n-\t\tcase 0:\n-\t\t state = 12; /* '>' */\n-\t\t break;\n-\n-\t\tcase 12:\n-\t\t state = 13; /* >'>' */\n-\t\t break;\n-\n-\t\tcase 8:\n-\t\t state = 14; /* s'>' */\n-\t\t break;\n-\n-\t\tcase 14:\n-\t\t state = 15; /* s>'>' */\n-\t\t break;\n-\t\t}\n-\t break;\n-\t }\n-\t break;\n-\n-\tcase LEX_IS_STAR:\n-\t switch (state)\n-\t {\n-\t case 0:\n-\t token[len++] = ch;\n-\t START_EXPR ();\n-\t state = 2; /* '*', It could be the fist cast char. */\n-\t break;\n-\n-\t case 16: /* ='*' Not valid token. */\n-\t ttype = BPF_MOV;\n-\t return_token = 1;\n-\t UNGET ();\n-\t break;\n-\n-\t case 4: /* *(uXX'*' */\n-\t token[len++] = ch;\n-\t state = 5;\n-\t break;\n-\t }\n-\t break;\n-\n-\tcase LEX_IS_OPEN_BR:\n-\t START_EXPR ();\n-\t token[len++] = ch;\n-\t return_token = 1;\n-\n-\t switch (state)\n-\t {\n-\t case 2:\n-\t state = 3; /* *'(' second char of a cast or expr. */\n-\t return_token = 0;\n-\t break;\n-\n-\t case 6:\n-\t if (valid_expr (expr, &end_expr))\n-\t\t{\n-\t\t len = end_expr - expr;\n-\t\t memcpy (token, expr, len);\n-\t\t ttype = BPF_EXPR;\n-\t\t str = end_expr;\n-\t\t}\n-\t else\n-\t\t{\n-\t\t len = 0;\n-\t\t while (*invalid_expression)\n-\t\t token[len++] = *invalid_expression++;\n-\n-\t\t token[len] = 0;\n-\t\t ttype = BPF_UNKNOWN;\n-\t\t}\n-\t break;\n-\n-\t default:\n-\t ttype = BPF_CHR_OPEN_BR;\n-\t SCANNER_SKIP_WHITESPACE ();\n-\t ch2 = GET ();\n-\n-\t if ((isdigit (ch2) || ch2 == '(')\n-\t\t && valid_expr (expr, &end_expr))\n-\t\t{\n-\t\t len = end_expr - expr;\n-\t\t memcpy (token, expr, len);\n-\t\t ttype = BPF_EXPR;\n-\t\t str = end_expr;\n-\t\t}\n-\t else\n-\t\tUNGET ();\n-\t }\n-\t break;\n-\n-\tcase LEX_IS_CLSE_BR:\n-\t token[len++] = ch;\n-\n-\t if (state == 0)\n-\t {\n-\t ttype = BPF_CHR_CLSE_BR;\n-\t return_token = 1;\n-\t }\n-\t else if (state == 5) /* *(uXX*')' */\n-\t return_token = 1;\n-\t break;\n-\n-\tcase LEX_IS_EQUAL:\n-\t token[len++] = ch;\n-\t return_token = 1;\n-\n-\t switch (state)\n-\t {\n-\t case 0:\n-\t state = 16; /* '=' */\n-\t return_token = 0;\n-\t break;\n-\n-\t case 16:\n-\t state = 17; /* ='=' */\n-\t return_token = 0;\n-\t break;\n-\n-\t case 2: /* *'=' */\n-\t ttype = BPF_MUL;\n-\t break;\n-\n-\t case 10: /* s>>'=' */\n-\t ttype = BPF_ARSH;\n-\t break;\n-\n-\t case 12: /* >'=' */\n-\t ttype = BPF_JGE;\n-\t break;\n-\n-\t case 13: /* >>'=' */\n-\t ttype = BPF_RSH;\n-\t break;\n-\n-\t case 14: /* s>'=' */\n-\t ttype = BPF_JSGE;\n-\t break;\n-\n-\t case 15: /* s>>'=' */\n-\t ttype = BPF_ARSH;\n-\t break;\n-\n-\t case 18: /* <'=' */\n-\t ttype = BPF_JLE;\n-\t break;\n-\n-\t case 19: /* <<'=' */\n-\t ttype = BPF_LSH;\n-\t break;\n-\n-\t case 20: /* &'=' */\n-\t ttype = BPF_AND;\n-\t break;\n-\n-\t case 21: /* !'=' */\n-\t ttype = BPF_JNE;\n-\t break;\n-\n-\t case 22: /* s<'=' */\n-\t ttype = BPF_JSLE;\n-\t break;\n-\t }\n-\t break;\n-\n-\tcase LEX_IS_SYMBOL_COMPONENT:\n-\t return_token = 1;\n-\n-\t switch (state)\n-\t {\n-\t case 17: /* =='sym' */\n-\t ttype = BPF_JEQ;\n-\t break;\n-\n-\t case 12: /* >'sym' */\n-\t ttype = BPF_JGT;\n-\t break;\n-\n-\t case 18: /* <'sym' */\n-\t ttype = BPF_JLT;\n-\t break;\n-\n-\t case 20: /* &'sym' */\n-\t ttype = BPF_JSET;\n-\t break;\n-\n-\t case 14: /*s>'sym' */\n-\t ttype = BPF_JSGT;\n-\t break;\n-\n-\t case 22: /* s<'sym' */\n-\t ttype = BPF_JSLT;\n-\t break;\n-\n-\t case 16: /* ='sym' */\n-\t ttype = BPF_MOV;\n-\t break;\n-\n-\t default:\n-\t return_token = 0;\n-\t }\n-\n-\t if (return_token)\n-\t {\n-\t UNGET ();\n-\t break;\n-\t }\n-\n-\t START_EXPR ();\n-\t token[len++] = ch;\n-\n-\t while ((ch2 = GET ()) != EOF)\n-\t {\n-\t int type;\n-\n-\t type = pseudoc_lex[(unsigned char) ch2];\n-\t if (type != LEX_IS_SYMBOL_COMPONENT)\n-\t\tbreak;\n-\t token[len++] = ch2;\n-\t }\n-\n-\t if (ch2 != EOF)\n-\t UNGET ();\n-\n-\t if (state == 0)\n-\t {\n-\t if (len == 1 && ch == 's')\n-\t\tstate = 8; /* signed instructions: 's' */\n-\t else\n-\t\t{\n-\t\t ttype = BPF_SYMBOL;\n-\t\t if (is_register (token, len))\n-\t\t ttype = BPF_REG;\n-\t\t else if (look_for_reserved_word (token, &ttype))\n-\t\t ;\n-\t\t else if ((pseudoc_lex[(unsigned char) *token] == LEX_IS_ARITHM_OP\n-\t\t\t || *token == '(' || isdigit(*token))\n-\t\t\t && valid_expr (expr, &end_expr))\n-\t\t {\n-\t\t len = end_expr - expr;\n-\t\t token[len] = '\\0';\n-\t\t ttype = BPF_EXPR;\n-\t\t str = end_expr;\n-\t\t }\n-\n-\t\t return_token = 1;\n-\t\t}\n-\t }\n-\t else if (state == 3) /* *('sym' */\n-\t {\n-\t if ((ttype = is_cast (&token[2])) != BPF_UNKNOWN)\n-\t\tstate = 4; /* *('uXX' */\n-\t else\n-\t\t{\n-\t\t ttype = BPF_EXPR;\n-\t\t return_token = 1;\n-\t\t}\n-\t }\n-\t else if (state == 6)\n-\t {\n-\t if (ttype == BPF_SUB) /* neg */\n-\t\t{\n-\t\t if (is_register (&token[1], len - 1))\n-\t\t ttype = BPF_NEG;\n-\t\t else if (valid_expr(expr, &end_expr))\n-\t\t {\n-\t\t len = end_expr - expr;\n-\t\t memcpy(token, expr, len);\n-\t\t ttype = BPF_EXPR;\n-\t\t str = end_expr;\n-\t\t }\n-\t\t else\n-\t\t {\n-\t\t len = 0;\n-\t\t while (*invalid_expression)\n-\t\t\ttoken[len++] = *invalid_expression++;\n-\t\t token[len] = 0;\n-\t\t ttype = BPF_UNKNOWN;\n-\t\t }\n-\t\t}\n-\t else if (valid_expr (expr, &end_expr))\n-\t\t{\n-\t\t len = end_expr - expr;\n-\t\t memcpy(token, expr, len);\n-\t\t ttype = BPF_EXPR;\n-\t\t str = end_expr;\n-\t\t}\n-\t else\n-\t\tttype = BPF_UNKNOWN;\n-\n-\t return_token = 1;\n-\t }\n-\t break;\n-\t}\n+ va_list args;\n \n- if (return_token)\n-\t{\n-\t *tlen = len;\n-\t *insn = str;\n-\t break;\n-\t}\n+ free (errmsg);\n+ va_start (args, fmt);\n+ errmsg = xvasprintf (fmt, args);\n+ va_end (args);\n+ partial_match_length = length;\n }\n-\n- return ttype;\n-\n-#undef GET\n-#undef UNGET\n-#undef START_EXPR\n-#undef SCANNER_SKIP_WHITESPACE\n-#undef BPF_ARITHM_OP\n }\n \n-/*\n- The parser represent a FSM for the grammar described above. So for example\n- the following rule:\n-\n- ` bpf_alu_insn : BPF_REG bpf_alu_operator register_or_imm32'\n-\n- Is parser as follows:\n-\n- 1. It starts in state 0.\n+/* Assemble a machine instruction in STR and emit the frags/bytes it\n+ assembles to. */\n \n- 2. Consumes next token, e.g: `BPF_REG' and set `state' variable to a\n- particular state to helps to identify, in this case, that a register\n- token has been read, a comment surrounded by a single quote in the\n- pseudo-c token is added along with the new `state' value to indicate\n- what the scanner has read, e.g.:\n-\n- state = 6; // dst_reg = str_cast ( 'src_reg'\n-\n- So, in `state 6' the scanner has consumed: a destination register\n- (BPF_REG), an equal character (BPF_MOV), a cast token (BPF_CAST), an\n- open parenthesis (BPF_CHR_OPEN_BR) and the source register (BPF_REG).\n-\n- 3. If the accumulated tokens represent a complete BPF pseudo-c syntax\n- instruction then, a validation of the terms is made, for example: if\n- the registers have the same sizes (32/64 bits), if a specific\n- destination register must be used, etc., after that, a builder:\n- build_bfp_{non_generic_load,atomic_insn,jmp_insn,arithm_insn,endianness,load_store_insn}\n- is invoked, internally, it translates the BPF pseudo-c instruction to\n- a BPF GAS instruction using the previous terms recollected by the\n- scanner.\n-\n- 4. If a successful build of BPF GAS instruction was done, a final\n- state is set to `ST_EOI' (End Of Instruction) meaning that is not\n- expecting for more tokens in such instruction. Otherwise if the\n- conditions to calling builder are not satisfied an error is emitted\n- and `parse_err' is set.\n-*/\n-\n-static char *\n-bpf_pseudoc_to_normal_syntax (const char *str, char **errmsg)\n+void\n+md_assemble (char *str ATTRIBUTE_UNUSED)\n {\n-#define syntax_err(format, ...)\t\t\t\t\t\t\\\n- do\t\t\t\t\t\t\t\t\t\\\n- {\t\t\t\t\t\t\t\t\t\\\n- if (! parse_err)\t\t\t\t\t\t\t\\\n-\t{\t\t\t\t\t\t\t\t\\\n-\t parse_err = 1;\t\t\t\t\t\t\\\n-\t errbuf = xasprintf (format, ##__VA_ARGS__);\t\t\t\\\n-\t}\t\t\t\t\t\t\t\t\\\n- } while (0)\n-\n- enum bpf_token_type ttype;\n- enum bpf_token_type bpf_endianness = BPF_UNKNOWN,\n-\t\t bpf_atomic_insn;\n- enum bpf_token_type bpf_jmp_op = BPF_JEQ; /* Arbitrary. */\n- enum bpf_token_type bpf_cast = BPF_CAST_U8; /* Arbitrary. */\n- enum bpf_token_type bpf_arithm_op = BPF_ADD; /* Arbitrary. */\n- char *bpf_insn = NULL;\n- char *errbuf = NULL;\n- char src_reg[3] = {0};\n- char dst_reg[3] = {0};\n- char str_imm32[40] = {0};\n- char str_offset[40] = {0};\n- char str_symbol[MAX_TOKEN_SZ] = {0};\n- char token[MAX_TOKEN_SZ] = {0};\n- int state = 0;\n- int parse_err = 0;\n- size_t tlen;\n-\n- while (*str)\n+ /* There are two different syntaxes that can be used to write BPF\n+ instructions. One is very conventional and like any other\n+ assembly language where each instruction is conformed by an\n+ instruction mnemonic followed by its operands. This is what we\n+ call the \"normal\" syntax. The other syntax tries to look like C\n+ statements. We have to support both syntaxes in this assembler.\n+\n+ One of the many nuisances introduced by this eccentricity is that\n+ in the pseudo-c syntax it is not possible to hash the opcodes\n+ table by instruction mnemonic, because there is none. So we have\n+ no other choice than to try to parse all instruction opcodes\n+ until one matches. This is slow.\n+\n+ Another problem is that emitting detailed diagnostics becomes\n+ tricky, since the lack of mnemonic means it is not clear what\n+ instruction was intended by the user, and we cannot emit\n+ diagnostics for every attempted template. So if an instruction\n+ is not parsed, we report the diagnostic corresponding to the\n+ partially parsed instruction that was matched further. */\n+\n+ unsigned int idx = 0;\n+ struct bpf_insn insn;\n+ const struct bpf_opcode *opcode;\n+\n+ /* Initialize the global diagnostic variables. See the parse_error\n+ function above. */\n+ partial_match_length = 0;\n+ errmsg = NULL;\n+\n+#define PARSE_ERROR(...) parse_error (s - str, __VA_ARGS__)\n+\n+ while ((opcode = bpf_get_opcode (idx++)) != NULL)\n {\n- ttype = get_token (&str, token, &tlen);\n- if (ttype == BPF_UNKNOWN || state == ST_EOI)\n-\t{\n-\t syntax_err (\"unexpected token: '%s'\", token);\n-\t break;\n-\t}\n-\n- switch (ttype)\n-\t{\n-\tcase BPF_UNKNOWN:\n-\tcase BPF_LL:\n-\t break;\n-\n-\tcase BPF_REG:\n-\t switch (state)\n-\t {\n-\t case 0:\n-\t memcpy (dst_reg, token, tlen);\n-\t state = 1; /* 'dst_reg' */\n-\t break;\n-\n-\t case 3:\n-\t /* dst_reg bpf_op 'src_reg' */\n-\t memcpy (src_reg, token, tlen);\n-\t if (*dst_reg == *src_reg)\n-\t\tbpf_insn = build_bpf_arithm_insn (dst_reg, src_reg, 0,\n-\t\t\t\t\t\t NULL, bpf_arithm_op);\n-\t else\n-\t\t{\n-\t\t syntax_err (\"different register sizes: '%s', '%s'\",\n-\t\t\t dst_reg, src_reg);\n-\t\t break;\n-\t\t}\n-\t state = ST_EOI;\n-\t break;\n-\n-\t case 5:\n-\t memcpy (src_reg, token, tlen);\n-\t state = 6; /* dst_reg = str_cast ( 'src_reg' */\n-\t break;\n-\n-\t case 9:\n-\t memcpy (dst_reg, token, tlen);\n-\t state = 10; /* str_cast ( 'dst_reg' */\n-\t break;\n-\n-\t case 11:\n-\t /* str_cast ( dst_reg offset ) = 'src_reg' */\n-\t memcpy (src_reg, token, tlen);\n-\t bpf_insn = build_bpf_load_store_insn (dst_reg, src_reg,\n-\t\t\t\t\t\t bpf_cast, str_offset, 0);\n-\t state = ST_EOI;\n-\t break;\n-\n-\t case 14:\n-\t memcpy (dst_reg, token, tlen);\n-\t state = 15; /* if 'dst_reg' */\n-\t break;\n-\n-\t case 16:\n-\t memcpy (src_reg, token, tlen);\n-\t state = 17; /* if dst_reg jmp_op 'src_reg' */\n-\t break;\n-\n-\t case 24:\n-\t /* dst_reg = endianness src_reg */\n-\t memcpy (src_reg, token, tlen);\n-\t if (*dst_reg == 'r' && !strcmp (dst_reg, src_reg))\n-\t\tbpf_insn = build_bpf_endianness (dst_reg, bpf_endianness);\n-\t else\n-\t\tsyntax_err (\"invalid operand for instruction: '%s'\", token);\n-\n-\t state = ST_EOI;\n-\t break;\n-\n-\t case 28:\n-\t memcpy (dst_reg, token, tlen);\n-\t state = 29; /* lock str_cast ( 'dst_reg' */\n-\t break;\n-\n-\t case 32:\n-\t {\n-\t\t/* lock str_cast ( dst_reg offset ) atomic_insn 'src_reg' */\n-\t\tint with_offset = *str_offset != '\\0';\n-\n-\t\tmemcpy (src_reg, token, tlen);\n-\t\tif ((bpf_cast != BPF_CAST_U32\n-\t\t && bpf_cast != BPF_CAST_U64)\n-\t\t || *dst_reg != 'r'\n-\t\t || *src_reg != 'r')\n-\t\t syntax_err (\"invalid wide atomic instruction\");\n-\t\telse\n-\t\t bpf_insn = build_bpf_atomic_insn (dst_reg, src_reg, bpf_atomic_insn,\n-\t\t\t\t\t\t bpf_cast, with_offset ? str_offset : str_symbol);\n-\t }\n-\n-\t state = ST_EOI;\n-\t break;\n-\n-\t case 33:\n-\t /* callx 'dst_reg' */\n-\t bpf_insn = xasprintf (\"%s %%%s\", \"call\", token);\n-\t state = ST_EOI;\n-\t break;\n-\n-\t case 35:\n-\t memcpy (src_reg, token, tlen);\n-\t state = 36; /* dst_reg = str_cast skb [ 'src_reg' */\n-\t break;\n-\t }\n-\t break;\n-\n-\tcase BPF_MOV:\n-\tcase BPF_ADD:\n-\tcase BPF_SUB:\n-\tcase BPF_MUL:\n-\tcase BPF_DIV:\n-\tcase BPF_OR:\n-\tcase BPF_AND:\n-\tcase BPF_LSH:\n-\tcase BPF_RSH:\n-\tcase BPF_MOD:\n-\tcase BPF_XOR:\n-\tcase BPF_ARSH:\n-\tcase BPF_NEG:\n-\t switch (state)\n-\t {\n-\t case 1:\n-\t state = 3; /* dst_reg 'arith_op' */\n-\t bpf_arithm_op = ttype;\n-\t break;\n-\n-\t case 3:\n-\t if (ttype == BPF_NEG)\n-\t\t{\n-\t\t /* reg = -reg */\n-\t\t bpf_arithm_op = ttype;\n-\t\t memcpy (src_reg, token + 1, tlen - 1);\n-\t\t if (strcmp (dst_reg, src_reg))\n-\t\t {\n-\t\t syntax_err (\"found: '%s', expected: -%s\", token, dst_reg);\n-\t\t break;\n-\t\t }\n-\n-\t\t bpf_insn = build_bpf_arithm_insn (dst_reg, src_reg, 0,\n-\t\t\t\t\t\t NULL, bpf_arithm_op);\n-\t\t state = ST_EOI;\n-\t\t}\n-\t break;\n-\n-\t case 23:\n-\t memcpy (src_reg, token, tlen);\n-\t state = 11; /* str_cast ( dst_reg offset ) '=' */\n-\t break;\n-\n-\t case 12:\n-\t if (ttype == BPF_MOV)\n-\t\tstate = 13; /* str_cast ( dst_reg offset ) '=' */\n-\t break;\n-\n-\t case 31:\n-\t bpf_atomic_insn = ttype;\n-\t state = 32; /* lock str_cast ( dst_reg offset ) 'atomic_insn' */\n-\t break;\n-\n-\t default:\n-\t syntax_err (\"unexpected '%s'\", token);\n-\t state = ST_EOI;\n-\t }\n-\t break;\n-\n-\tcase BPF_CAST_U8:\n-\tcase BPF_CAST_U16:\n-\tcase BPF_CAST_U32:\n-\tcase BPF_CAST_U64:\n-\t bpf_cast = ttype;\n-\t switch (state)\n-\t {\n-\t case 3:\n-\t state = 4; /* dst_reg = 'str_cast' */\n-\t break;\n-\n-\t case 0:\n-\t state = 8; /* 'str_cast' */\n-\t break;\n-\n-\t case 26:\n-\t state = 27; /* lock 'str_cast' */\n-\t break;\n-\t }\n-\t break;\n-\n-\tcase BPF_CHR_OPEN_BR:\n-\t switch (state)\n-\t {\n-\t case 4:\n-\t state = 5; /* dst_reg = str_cast '(' */\n-\t break;\n-\n-\t case 8:\n-\t state = 9; /* str_cast '(' */\n-\t break;\n-\n-\t case 27:\n-\t state = 28; /* lock str_cast '(' */\n-\t break;\n-\n-\t case 34:\n-\t state = 35; /* dst_reg = str_cast skb '[' */\n-\t break;\n-\t }\n-\t break;\n+ const char *p;\n+ char *s;\n+ const char *template\n+ = (asm_dialect == DIALECT_PSEUDOC ? opcode->pseudoc : opcode->normal);\n+\n+ /* Do not try to match opcodes with a higher version than the\n+ selected ISA spec. */\n+ if (opcode->version > isa_spec)\n+ continue;\n+\n+ memset (&insn, 0, sizeof (struct bpf_insn));\n+ insn.size = 8;\n+ for (s = str, p = template; *p != '\\0';)\n+ {\n+ if (*p == ' ')\n+ {\n+ /* Expect zero or more spaces. */\n+ while (*s != '\\0' && (*s == ' ' || *s == '\\t'))\n+ s += 1;\n+ p += 1;\n+ }\n+ else if (*p == '%')\n+ {\n+ if (*(p + 1) == '%')\n+ {\n+ if (*s != '%')\n+ {\n+ PARSE_ERROR (\"expected '%%'\");\n+ break;\n+ }\n+ p += 2;\n+ s += 1;\n+ }\n+ else if (*(p + 1) == 'w')\n+ {\n+ /* Expect zero or more spaces. */\n+ while (*s != '\\0' && (*s == ' ' || *s == '\\t'))\n+ s += 1;\n+ p += 2;\n+ }\n+ else if (*(p + 1) == 'W')\n+ {\n+ /* Expect one or more spaces. */\n+ if (*s != ' ' && *s != '\\t')\n+ {\n+ PARSE_ERROR (\"expected white space, got '%s'\",\n+ s);\n+ break;\n+ }\n+ while (*s != '\\0' && (*s == ' ' || *s == '\\t'))\n+ s += 1;\n+ p += 2;\n+ }\n+ else if (strncmp (p, \"%dr\", 3) == 0)\n+ {\n+ uint8_t regno;\n+ char *news = parse_bpf_register (s, 'r', ®no);\n+\n+ if (news == NULL || (insn.has_dst && regno != insn.dst))\n+ {\n+ if (news != NULL)\n+ PARSE_ERROR (\"expected register r%d, got r%d\",\n+ insn.dst, regno);\n+ else\n+ PARSE_ERROR (\"expected register name, got '%s'\", s);\n+ break;\n+ }\n+ s = news;\n+ insn.dst = regno;\n+ insn.has_dst = 1;\n+ p += 3;\n+ }\n+ else if (strncmp (p, \"%sr\", 3) == 0)\n+ {\n+ uint8_t regno;\n+ char *news = parse_bpf_register (s, 'r', ®no);\n+\n+ if (news == NULL || (insn.has_src && regno != insn.src))\n+ {\n+ if (news != NULL)\n+ PARSE_ERROR (\"expected register r%d, got r%d\",\n+ insn.dst, regno);\n+ else\n+ PARSE_ERROR (\"expected register name, got '%s'\", s);\n+ break;\n+ }\n+ s = news;\n+ insn.src = regno;\n+ insn.has_src = 1;\n+ p += 3;\n+ }\n+ else if (strncmp (p, \"%dw\", 3) == 0)\n+ {\n+ uint8_t regno;\n+ char *news = parse_bpf_register (s, 'w', ®no);\n+\n+ if (news == NULL || (insn.has_dst && regno != insn.dst))\n+ {\n+ if (news != NULL)\n+ PARSE_ERROR (\"expected register r%d, got r%d\",\n+ insn.dst, regno);\n+ else\n+ PARSE_ERROR (\"expected register name, got '%s'\", s);\n+ break;\n+ }\n+ s = news;\n+ insn.dst = regno;\n+ insn.has_dst = 1;\n+ p += 3;\n+ }\n+ else if (strncmp (p, \"%sw\", 3) == 0)\n+ {\n+ uint8_t regno;\n+ char *news = parse_bpf_register (s, 'w', ®no);\n+\n+ if (news == NULL || (insn.has_src && regno != insn.src))\n+ {\n+ if (news != NULL)\n+ PARSE_ERROR (\"expected register r%d, got r%d\",\n+ insn.dst, regno);\n+ else\n+ PARSE_ERROR (\"expected register name, got '%s'\", s);\n+ break;\n+ }\n+ s = news;\n+ insn.src = regno;\n+ insn.has_src = 1;\n+ p += 3;\n+ }\n+ else if (strncmp (p, \"%i32\", 4) == 0\n+ || strncmp (p, \"%I32\", 4) == 0)\n+ {\n+ if (p[1] == 'I')\n+ {\n+ while (*s == ' ' || *s == '\\t')\n+ s += 1;\n+ if (*s != '+' && *s != '-')\n+ {\n+ PARSE_ERROR (\"expected `+' or `-', got `%c'\", *s);\n+ break;\n+ }\n+ }\n+\n+ s = parse_expression (s, &insn.imm32);\n+ if (s == NULL)\n+ {\n+ PARSE_ERROR (\"expected signed 32-bit immediate\");\n+ break;\n+ }\n+ insn.has_imm32 = 1;\n+ p += 4;\n+ }\n+ else if (strncmp (p, \"%o16\", 4) == 0)\n+ {\n+ while (*s == ' ' || *s == '\\t')\n+ s += 1;\n+ if (*s != '+' && *s != '-')\n+ {\n+ PARSE_ERROR (\"expected `+' or `-', got `%c'\", *s);\n+ break;\n+ }\n+\n+ s = parse_expression (s, &insn.offset16);\n+ if (s == NULL)\n+ {\n+ PARSE_ERROR (\"expected signed 16-bit offset\");\n+ break;\n+ }\n+ insn.has_offset16 = 1;\n+ p += 4;\n+ }\n+ else if (strncmp (p, \"%d16\", 4) == 0)\n+ {\n+ s = parse_expression (s, &insn.disp16);\n+ if (s == NULL)\n+ {\n+ PARSE_ERROR (\"expected signed 16-bit displacement\");\n+ break;\n+ }\n+ insn.has_disp16 = 1;\n+ p += 4;\n+ }\n+ else if (strncmp (p, \"%d32\", 4) == 0)\n+ {\n+ s = parse_expression (s, &insn.disp32);\n+ if (s == NULL)\n+ {\n+ PARSE_ERROR (\"expected signed 32-bit displacement\");\n+ break;\n+ }\n+ insn.has_disp32 = 1;\n+ p += 4;\n+ }\n+ else if (strncmp (p, \"%i64\", 4) == 0)\n+ {\n+ s = parse_expression (s, &insn.imm64);\n+ if (s == NULL)\n+ {\n+ PARSE_ERROR (\"expected signed 64-bit immediate\");\n+ break;\n+ }\n+ insn.has_imm64 = 1;\n+ insn.size = 16;\n+ p += 4;\n+ }\n+ else\n+ as_fatal (_(\"invalid %%-tag in BPF opcode '%s'\\n\"), template);\n+ }\n+ else\n+ {\n+ /* Match a literal character. */\n+ if (*s != *p)\n+ {\n+ if (*s == '\\0')\n+ PARSE_ERROR (\"expected '%c'\", *p);\n+ else if (*s == '%')\n+ {\n+ /* This is to workaround a bug in as_bad. */\n+ char tmp[3];\n+\n+ tmp[0] = '%';\n+ tmp[1] = '%';\n+ tmp[2] = '\\0';\n+\n+ PARSE_ERROR (\"expected '%c', got '%s'\", *p, tmp);\n+ }\n+ else\n+ PARSE_ERROR (\"expected '%c', got '%c'\", *p, *s);\n+ break;\n+ }\n+ p += 1;\n+ s += 1;\n+ }\n+ }\n \n-\tcase BPF_CHR_CLSE_BR:\n-\t switch (state)\n-\t {\n-\t case 7:\n-\t /* dst_reg = str_cast ( imm32 ')' */\n-\t bpf_insn = build_bpf_load_store_insn (dst_reg, src_reg,\n-\t\t\t\t\t\t bpf_cast, str_imm32, 1);\n-\t state = ST_EOI;\n-\t break;\n-\n-\t case 11:\n-\t state = 12; /* str_cast ( dst_reg imm32 ')' */\n-\t break;\n-\n-\t case 21:\n-\t /* dst_reg = str_cast ( src_reg offset ')' */\n-\t bpf_insn = build_bpf_load_store_insn (dst_reg, src_reg,\n-\t\t\t\t\t\t bpf_cast, str_offset, 1);\n-\t state = ST_EOI;\n-\t break;\n-\n-\t case 22:\n-\t state = 23; /* str_cast ( dst_reg offset ')' */\n-\t break;\n-\n-\t case 30:\n-\t state = 31; /* lock str_cast ( dst_reg offset ')' */\n-\t break;\n-\n-\t case 37:\n-\t /* dst_reg = str_cast skb [ src_reg imm32 ']' */\n-\t if (*dst_reg != 'w' && !strcmp (\"r0\", dst_reg))\n-\t\tbpf_insn = build_bpf_non_generic_load (*src_reg != '\\0' ? src_reg : NULL,\n-\t\t\t\t\t\t bpf_cast, str_imm32);\n-\t else\n-\t\tsyntax_err (\"invalid register operand: '%s'\", dst_reg);\n-\n-\t state = ST_EOI;\n-\t break;\n-\t }\n-\t break;\n+ if (*p == '\\0')\n+ {\n+ /* Allow white spaces at the end of the line. */\n+ while (*s != '\\0' && (*s == ' ' || *s == '\\t'))\n+ s += 1;\n+ if (*s == '\\0')\n+ /* We parsed an instruction successfully. */\n+ break;\n+ PARSE_ERROR (\"extra junk at end of line\");\n+ }\n+ }\n \n-\tcase BPF_EXPR:\n-\t switch (state)\n-\t {\n-\t case 3:\n-\t {\n-\t\t/* dst_reg bpf_arithm_op 'imm32' */\n-\t\tint load64 = 0;\n-\n-\t\tmemcpy (str_imm32, token, tlen);\n-\t\tmemset (token, 0, tlen);\n-\n-\t\tif ((ttype = get_token (&str, token, &tlen)) == BPF_LL\n-\t\t && bpf_arithm_op == BPF_MOV)\n-\t\t load64 = 1;\n-\t\telse if (ttype != BPF_UNKNOWN)\n-\t\t syntax_err (\"unexpected token: '%s'\", token);\n-\n-\t\tif (load64 && *dst_reg == 'w')\n-\t\t syntax_err (\"unexpected register size: '%s'\", dst_reg);\n-\n-\t\tif (! parse_err)\n-\t\t bpf_insn = build_bpf_arithm_insn (dst_reg, NULL, load64,\n-\t\t\t\t\t\t str_imm32, bpf_arithm_op);\n-\t\tstate = ST_EOI;\n-\t }\n-\t break;\n-\n-\t case 18:\n-\t {\n-\t\t/* if dst_reg jmp_op src_reg goto 'offset' */\n-\t\tint with_src = *src_reg != '\\0';\n-\n-\t\tmemcpy (str_offset, token, tlen);\n-\t\tif (with_src && *dst_reg != *src_reg)\n-\t\t syntax_err (\"different register size: '%s', '%s'\",\n-\t\t\t dst_reg, src_reg);\n-\t\telse\n-\t\t bpf_insn = build_bpf_jmp_insn (dst_reg, with_src ? src_reg : NULL,\n-\t\t\t\t\t\t with_src ? NULL: str_imm32,\n-\t\t\t\t\t\t bpf_jmp_op, NULL, str_offset);\n-\t\tstate = ST_EOI;\n-\t }\n-\t break;\n-\n-\t case 19:\n-\t /* goto 'offset' */\n-\t memcpy (str_offset, token, tlen);\n-\t bpf_insn = xasprintf (\"%s %s\", \"ja\", str_offset);\n-\t state = ST_EOI;\n-\t break;\n-\n-\t case 6:\n-\t memcpy (str_offset, token, tlen);\n-\t state = 21; /* dst_reg = str_cast ( src_reg 'offset' */\n-\t break;\n-\n-\t case 10:\n-\t memcpy (str_offset, token, tlen);\n-\t state = 22; /* str_cast ( dst_reg 'offset' */\n-\t break;\n-\n-\t case 16:\n-\t memcpy (str_imm32, token, tlen);\n-\t state = 25; /* if dst_reg jmp_op 'imm32' */\n-\t break;\n-\n-\t case 29:\n-\t memcpy (str_offset, token, tlen);\n-\t state = 30; /* lock str_cast ( dst_reg 'offset' */\n-\t break;\n-\n-\t case 34:\n-\t /* dst_reg = str_cast skb 'imm32' */\n-\t if (*dst_reg != 'w' && !strcmp (\"r0\", dst_reg))\n-\t\t{\n-\t\t memcpy (str_imm32, token, tlen);\n-\t\t bpf_insn = build_bpf_non_generic_load (*src_reg != '\\0' ? src_reg : NULL,\n-\t\t\t\t\t\t\t bpf_cast, str_imm32);\n-\t\t}\n-\t else\n-\t\tsyntax_err (\"invalid register operand: '%s'\", dst_reg);\n-\n-\t state = ST_EOI;\n-\t break;\n-\n-\t case 36:\n-\t memcpy (str_imm32, token, tlen);\n-\t state = 37; /* dst_reg = str_cast skb [ src_reg 'imm32' */\n-\t break;\n-\t }\n-\t break;\n+ if (opcode == NULL)\n+ {\n+ as_bad (_(\"unrecognized instruction `%s'\"), str);\n+ if (errmsg != NULL)\n+ {\n+ as_bad (errmsg);\n+ free (errmsg);\n+ }\n \n-\tcase BPF_IF:\n-\t if (state == 0)\n-\t state = 14;\n-\t break;\n+ return;\n+ }\n+ insn.opcode = opcode->opcode;\n \n-\tcase BPF_JSGT:\n-\tcase BPF_JSLT:\n-\tcase BPF_JSLE:\n-\tcase BPF_JSGE:\n-\tcase BPF_JGT:\n-\tcase BPF_JGE:\n-\tcase BPF_JLE:\n-\tcase BPF_JSET:\n-\tcase BPF_JNE:\n-\tcase BPF_JLT:\n-\tcase BPF_JEQ:\n-\t if (state == 15)\n-\t {\n-\t bpf_jmp_op = ttype;\n-\t state = 16; /* if dst_reg 'jmp_op' */\n-\t }\n-\t break;\n+#undef PARSE_ERROR\n \n-\tcase BPF_GOTO:\n-\t switch (state)\n-\t {\n-\t case 17:\n-\t case 25:\n-\t state = 18; /* if dst_reg jmp_op src_reg|imm32 'goto' */\n-\t break;\n-\n-\t case 0:\n-\t state = 19;\n-\t break;\n-\t }\n-\t break;\n+ /* Generate the frags and fixups for the parsed instruction. */\n+ {\n+ char *this_frag = frag_more (insn.size);\n+ char bytes[16];\n+ uint8_t src, dst;\n+ int i;\n+\n+ /* Zero all the bytes. */\n+ memset (bytes, 0, 16);\n+\n+ /* First encode the opcodes. Note that we have to handle the\n+ endianness groups of the BPF instructions: 8 | 4 | 4 | 16 |\n+ 32. */\n+ if (target_big_endian)\n+ {\n+ /* code */\n+ bytes[0] = (insn.opcode >> 56) & 0xff;\n+ /* regs */\n+ bytes[1] = (insn.opcode >> 48) & 0xff;\n+ /* offset16 */\n+ bytes[2] = (insn.opcode >> 40) & 0xff;\n+ bytes[3] = (insn.opcode >> 32) & 0xff;\n+ /* imm32 */\n+ bytes[4] = (insn.opcode >> 24) & 0xff;\n+ bytes[5] = (insn.opcode >> 16) & 0xff;\n+ bytes[6] = (insn.opcode >> 8) & 0xff;\n+ bytes[7] = insn.opcode & 0xff;\n+ }\n+ else\n+ {\n+ /* code */\n+ bytes[0] = (insn.opcode >> 56) & 0xff;\n+ /* regs */\n+ bytes[1] = (((((insn.opcode >> 48) & 0xff) & 0xf) << 4)\n+ | (((insn.opcode >> 48) & 0xff) & 0xf));\n+ /* offset16 */\n+ bytes[3] = (insn.opcode >> 40) & 0xff;\n+ bytes[2] = (insn.opcode >> 32) & 0xff;\n+ /* imm32 */\n+ bytes[7] = (insn.opcode >> 24) & 0xff;\n+ bytes[6] = (insn.opcode >> 16) & 0xff;\n+ bytes[5] = (insn.opcode >> 8) & 0xff;\n+ bytes[4] = insn.opcode & 0xff;\n+ }\n \n-\tcase BPF_SYMBOL:\n-\t switch (state)\n-\t {\n-\t case 18:\n-\t {\n-\t\t/* if dst_reg jmp_op src_reg goto 'sym' */\n-\t\tint with_src = *src_reg != '\\0';\n-\n-\t\tmemcpy (str_symbol, token, tlen);\n-\t\tif (with_src && *dst_reg != *src_reg)\n-\t\t syntax_err (\"different register size: '%s', '%s'\",\n-\t\t\t dst_reg, src_reg);\n-\t\telse\n-\t\t bpf_insn = build_bpf_jmp_insn (dst_reg, with_src ? src_reg : NULL,\n-\t\t\t\t\t\t with_src ? NULL: str_imm32,\n-\t\t\t\t\t\t bpf_jmp_op, str_symbol, NULL);\n-\t\tstate = ST_EOI;\n-\t }\n-\t break;\n-\n-\t case 19:\n-\t /* goto 'sym' */\n-\t memcpy (str_symbol, token, tlen);\n-\t bpf_insn = xasprintf (\"%s %s\", \"ja\", str_symbol);\n-\t state = ST_EOI;\n-\t break;\n-\n-\t case 0:\n-\t state = ST_EOI;\n-\t break;\n-\n-\t case 3:\n-\t {\n-\t\t/* dst_reg arithm_op 'sym' */\n-\t\tint load64 = 0;\n-\t\t\n-\t\tmemcpy (str_symbol, token, tlen);\n-\t\tmemset (token, 0, tlen);\n-\n-\t\tif ((ttype = get_token (&str, token, &tlen)) == BPF_LL\n-\t\t && bpf_arithm_op == BPF_MOV)\n-\t\t load64 = 1;\n-\t\telse if (ttype != BPF_UNKNOWN)\n-\t\t syntax_err (\"unexpected token: '%s'\", token);\n-\n-\t\tif (load64 && *dst_reg == 'w')\n-\t\t syntax_err (\"unexpected register size: '%s'\", dst_reg);\n-\n-\t\tif (! parse_err)\n-\t\t bpf_insn = build_bpf_arithm_insn (dst_reg, NULL, load64,\n-\t\t\t\t\t\t str_symbol, bpf_arithm_op);\n-\t\tstate = ST_EOI;\n-\t }\n-\t break;\n-\t }\n-\t break;\n+ /* Now the registers. */\n+ src = insn.has_src ? insn.src : 0;\n+ dst = insn.has_dst ? insn.dst : 0;\n \n-\tcase BPF_LE16:\n-\tcase BPF_LE32:\n-\tcase BPF_LE64:\n-\tcase BPF_BE16:\n-\tcase BPF_BE32:\n-\tcase BPF_BE64:\n-\t bpf_endianness = ttype;\n-\t state = 24; /* dst_reg = 'endianness' */\n-\t break;\n+ if (target_big_endian)\n+ bytes[1] = ((dst & 0xf) << 4) | (src & 0xf);\n+ else\n+ bytes[1] = ((src & 0xf) << 4) | (dst & 0xf);\n \n-\tcase BPF_LOCK:\n-\t state = 26;\n-\t break;\n+ /* Now the immediates. */\n+ if (insn.has_imm64)\n+ {\n+ switch (insn.imm64.X_op)\n+ {\n+ case O_constant:\n+ {\n+ uint64_t imm64 = insn.imm64.X_add_number;\n+\n+ if (target_big_endian)\n+ {\n+ bytes[12] = (imm64 >> 56) & 0xff;\n+ bytes[13] = (imm64 >> 48) & 0xff;\n+ bytes[14] = (imm64 >> 40) & 0xff;\n+ bytes[15] = (imm64 >> 32) & 0xff;\n+ bytes[4] = (imm64 >> 24) & 0xff;\n+ bytes[5] = (imm64 >> 16) & 0xff;\n+ bytes[6] = (imm64 >> 8) & 0xff;\n+ bytes[7] = imm64 & 0xff;\n+ }\n+ else\n+ {\n+ bytes[15] = (imm64 >> 56) & 0xff;\n+ bytes[14] = (imm64 >> 48) & 0xff;\n+ bytes[13] = (imm64 >> 40) & 0xff;\n+ bytes[12] = (imm64 >> 32) & 0xff;\n+ bytes[7] = (imm64 >> 24) & 0xff;\n+ bytes[6] = (imm64 >> 16) & 0xff;\n+ bytes[5] = (imm64 >> 8) & 0xff;\n+ bytes[4] = imm64 & 0xff;\n+ }\n+ break;\n+ }\n+ case O_symbol:\n+ case O_subtract:\n+ case O_add:\n+ {\n+ reloc_howto_type *reloc_howto;\n+ int size;\n+\n+ reloc_howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_BPF_64);\n+ if (!reloc_howto)\n+ abort ();\n+\n+ size = bfd_get_reloc_size (reloc_howto);\n+\n+ fix_new_exp (frag_now, this_frag - frag_now->fr_literal,\n+ size, &insn.imm64, reloc_howto->pc_relative,\n+ BFD_RELOC_BPF_64);\n+ break;\n+ }\n+ default:\n+ abort ();\n+ }\n+ }\n \n-\tcase BPF_IND_CALL:\n-\t state = 33;\n-\t break;\n+ if (insn.has_imm32)\n+ {\n+ switch (insn.imm32.X_op)\n+ {\n+ case O_constant:\n+ {\n+ uint32_t imm32 = insn.imm32.X_add_number;\n+\n+ if (target_big_endian)\n+ {\n+ bytes[4] = (imm32 >> 24) & 0xff;\n+ bytes[5] = (imm32 >> 16) & 0xff;\n+ bytes[6] = (imm32 >> 8) & 0xff;\n+ bytes[7] = imm32 & 0xff;\n+ }\n+ else\n+ {\n+ bytes[7] = (imm32 >> 24) & 0xff;\n+ bytes[6] = (imm32 >> 16) & 0xff;\n+ bytes[5] = (imm32 >> 8) & 0xff;\n+ bytes[4] = imm32 & 0xff;\n+ }\n+ break;\n+ }\n+ case O_symbol:\n+ case O_subtract:\n+ case O_add:\n+ case O_uminus:\n+ {\n+ reloc_howto_type *reloc_howto;\n+ int size;\n+\n+ reloc_howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);\n+ if (!reloc_howto)\n+ abort ();\n+\n+ size = bfd_get_reloc_size (reloc_howto);\n+\n+ fix_new_exp (frag_now, this_frag - frag_now->fr_literal + 4,\n+ size, &insn.imm32, reloc_howto->pc_relative,\n+ BFD_RELOC_32);\n+ break;\n+ }\n+ default:\n+ abort ();\n+ }\n+ }\n \n-\tcase BPF_LD:\n-\t state = 34; /* dst_reg = str_cast 'skb' */\n-\t break;\n-\t}\n+ if (insn.has_disp32)\n+ {\n+ switch (insn.disp32.X_op)\n+ {\n+ case O_constant:\n+ {\n+ uint32_t disp32 = insn.disp32.X_add_number;\n+\n+ if (target_big_endian)\n+ {\n+ bytes[4] = (disp32 >> 24) & 0xff;\n+ bytes[5] = (disp32 >> 16) & 0xff;\n+ bytes[6] = (disp32 >> 8) & 0xff;\n+ bytes[7] = disp32 & 0xff;\n+ }\n+ else\n+ {\n+ bytes[7] = (disp32 >> 24) & 0xff;\n+ bytes[6] = (disp32 >> 16) & 0xff;\n+ bytes[5] = (disp32 >> 8) & 0xff;\n+ bytes[4] = disp32 & 0xff;\n+ }\n+ break;\n+ }\n+ case O_symbol:\n+ case O_subtract:\n+ case O_add:\n+ {\n+ reloc_howto_type *reloc_howto;\n+ int size;\n+\n+ reloc_howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_BPF_DISP32);\n+ if (!reloc_howto)\n+ abort ();\n+\n+ size = bfd_get_reloc_size (reloc_howto);\n+\n+ fix_new_exp (frag_now, this_frag - frag_now->fr_literal,\n+ size, &insn.disp32, reloc_howto->pc_relative,\n+ BFD_RELOC_BPF_DISP32);\n+ break;\n+ }\n+ default:\n+ abort ();\n+ }\n+ }\n \n- memset (token, 0, tlen);\n- }\n+ if (insn.has_offset16)\n+ {\n+ switch (insn.offset16.X_op)\n+ {\n+ case O_constant:\n+ {\n+ uint32_t offset16 = insn.offset16.X_add_number;\n+\n+ if (target_big_endian)\n+ {\n+ bytes[2] = (offset16 >> 8) & 0xff;\n+ bytes[3] = offset16 & 0xff;\n+ }\n+ else\n+ {\n+ bytes[3] = (offset16 >> 8) & 0xff;\n+ bytes[2] = offset16 & 0xff;\n+ }\n+ break;\n+ }\n+ case O_symbol:\n+ case O_subtract:\n+ case O_add:\n+ {\n+ reloc_howto_type *reloc_howto;\n+ int size;\n+\n+ reloc_howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_BPF_DISP16);\n+ if (!reloc_howto)\n+ abort ();\n+\n+ size = bfd_get_reloc_size (reloc_howto);\n+\n+ fix_new_exp (frag_now, this_frag - frag_now->fr_literal,\n+ size, &insn.offset16, reloc_howto->pc_relative,\n+ BFD_RELOC_BPF_DISP16);\n+ break;\n+ }\n+ default:\n+ abort ();\n+ }\n+ }\n \n- if (state != ST_EOI)\n- syntax_err (\"incomplete instruction\");\n+ if (insn.has_disp16)\n+ {\n+ switch (insn.disp16.X_op)\n+ {\n+ case O_constant:\n+ {\n+ uint32_t disp16 = insn.disp16.X_add_number;\n+\n+ if (target_big_endian)\n+ {\n+ bytes[2] = (disp16 >> 8) & 0xff;\n+ bytes[3] = disp16 & 0xff;\n+ }\n+ else\n+ {\n+ bytes[3] = (disp16 >> 8) & 0xff;\n+ bytes[2] = disp16 & 0xff;\n+ }\n+ break;\n+ }\n+ case O_symbol:\n+ case O_subtract:\n+ case O_add:\n+ {\n+ reloc_howto_type *reloc_howto;\n+ int size;\n+\n+ reloc_howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_BPF_DISP16);\n+ if (!reloc_howto)\n+ abort ();\n+\n+ size = bfd_get_reloc_size (reloc_howto);\n+\n+ fix_new_exp (frag_now, this_frag - frag_now->fr_literal,\n+ size, &insn.disp16, reloc_howto->pc_relative,\n+ BFD_RELOC_BPF_DISP16);\n+ break;\n+ }\n+ default:\n+ abort ();\n+ }\n+ }\n \n- *errmsg = errbuf;\n- return bpf_insn;\n+ /* Emit bytes. */\n+ for (i = 0; i < insn.size; ++i)\n+ {\n+ md_number_to_chars (this_frag, (valueT) bytes[i], 1);\n+ this_frag += 1;\n+ }\n+ }\n \n-#undef syntax_err\n+ /* Emit DWARF2 debugging information. */\n+ dwarf2_emit_insn (insn.size);\n }\n \n-void\n-md_assemble (char *str)\n-{\n- const CGEN_INSN *insn;\n- char *errmsg;\n- char *a_errmsg;\n- CGEN_FIELDS fields;\n- char *normal;\n-\n-#if CGEN_INT_INSN_P\n- CGEN_INSN_INT buffer[CGEN_MAX_INSN_SIZE / sizeof (CGEN_INT_INSN_P)];\n-#else\n- unsigned char buffer[CGEN_MAX_INSN_SIZE];\n-#endif\n-\n- gas_cgen_init_parse ();\n- insn = bpf_cgen_assemble_insn (gas_cgen_cpu_desc, str, &fields,\n- buffer, &errmsg);\n- if (insn == NULL)\n- {\n- normal = bpf_pseudoc_to_normal_syntax (str, &a_errmsg);\n- if (normal)\n-\t{\n-\t insn = bpf_cgen_assemble_insn (gas_cgen_cpu_desc, normal, &fields,\n-\t\t\t\t\t buffer, &a_errmsg);\n-\t xfree (normal);\n-\t}\n-\n- if (insn == NULL)\n-\t{\n-\t as_bad (\"%s\", errmsg);\n-\t if (a_errmsg)\n-\t {\n-\t as_bad (\"%s\", a_errmsg);\n-\t xfree (a_errmsg);\n-\t }\n-\t return;\n-\t}\n- }\n-\n- gas_cgen_finish_insn (insn, buffer, CGEN_FIELDS_BITSIZE (&fields),\n- 0, /* zero to ban relaxable insns. */\n- NULL); /* NULL so results not returned here. */\n-}\n+/* Parse an operand that is machine-specific. */\n \n void\n md_operand (expressionS *expressionP)\n {\n- invalid_expression = input_line_pointer - 1;\n- gas_cgen_md_operand (expressionP);\n+ /* If this hook is invoked it means GAS failed to parse a generic\n+ expression. We should inhibit the as_bad in expr.c, so we can fail\n+ while parsing instruction alternatives. To do that, we change the\n+ expression to not have an O_absent. But then we also need to set\n+ exp_parse_failed to parse_expression above does the right thing. */\n+ ++input_line_pointer;\n+ expressionP->X_op = O_constant;\n+ expressionP->X_add_number = 0;\n+ exp_parse_failed = 1;\n }\n \n-\n symbolS *\n md_undefined_symbol (char *name ATTRIBUTE_UNUSED)\n {\n@@ -1929,3 +1192,29 @@ md_atof (int type, char *litP, int *sizeP)\n {\n return ieee_md_atof (type, litP, sizeP, false);\n }\n+\n+\f\n+/* Determine whether the equal sign in the given string corresponds to\n+ a BPF instruction, i.e. when it is not to be considered a symbol\n+ assignment. */\n+\n+bool\n+bpf_tc_equal_in_insn (int c ATTRIBUTE_UNUSED, char *str ATTRIBUTE_UNUSED)\n+{\n+ uint8_t regno;\n+\n+ /* Only pseudo-c instructions can have equal signs, and of these,\n+ all that could be confused with a symbol assignment all start\n+ with a register name. */\n+ if (asm_dialect == DIALECT_PSEUDOC)\n+ {\n+ char *w = parse_bpf_register (str, 'w', ®no);\n+ char *r = parse_bpf_register (str, 'r', ®no);\n+\n+ if ((w != NULL && *w == '\\0')\n+ || (r != NULL && *r == '\\0'))\n+ return 1;\n+ }\n+\n+ return 0;\n+}\ndiff --git a/gas/config/tc-bpf.h b/gas/config/tc-bpf.h\nindex db604dbe8bc..d57a66fe460 100644\n--- a/gas/config/tc-bpf.h\n+++ b/gas/config/tc-bpf.h\n@@ -37,7 +37,6 @@\n \n /* .-foo gets turned into PC relative relocs. */\n #define DIFF_EXPR_OK 1\n-#define GAS_CGEN_PCREL_R_TYPE(R_TYPE) gas_cgen_pcrel_r_type (R_TYPE)\n \n /* Call md_pcrel_from_section(), not md_pcrel_from(). */\n #define MD_PCREL_FROM_SECTION(FIXP, SEC) md_pcrel_from_section (FIXP, SEC)\n@@ -52,4 +51,5 @@\n a jump to offset 0 means jump to the next instruction. */\n #define md_single_noop_insn \"ja 0\"\n \n-#define TC_EQUAL_IN_INSN(c, s) 1\n+#define TC_EQUAL_IN_INSN(c, s) bpf_tc_equal_in_insn ((c), (s))\n+extern bool bpf_tc_equal_in_insn (int, char *);\ndiff --git a/gas/configure b/gas/configure\nindex 86d90abf4e6..dbb3425b678 100755\n--- a/gas/configure\n+++ b/gas/configure\n@@ -12301,7 +12301,6 @@ cat >>confdefs.h <<_ACEOF\n _ACEOF\n \n \tfi\n- using_cgen=yes\n ;;\n epiphany | fr30 | ip2k | iq2000 | lm32 | m32r | or1k)\n \tusing_cgen=yes\ndiff --git a/gas/configure.ac b/gas/configure.ac\nindex 96eeb78db76..13adaad6123 100644\n--- a/gas/configure.ac\n+++ b/gas/configure.ac\n@@ -454,7 +454,6 @@ changequote([,])dnl\n \tif test $this_target = $target ; then\n \t AC_DEFINE_UNQUOTED(DEFAULT_ARCH, \"${arch}\", [Default architecture.])\n \tfi\n- using_cgen=yes\n ;;\n epiphany | fr30 | ip2k | iq2000 | lm32 | m32r | or1k)\n \tusing_cgen=yes\ndiff --git a/gas/doc/c-bpf.texi b/gas/doc/c-bpf.texi\nindex 0756796adc9..4742f89ea17 100644\n--- a/gas/doc/c-bpf.texi\n+++ b/gas/doc/c-bpf.texi\n@@ -15,15 +15,15 @@\n \n @cindex BPF support\n @menu\n-* BPF Options:: Options\n-* BPF Syntax::\t\t Syntax\n-* BPF Directives::\t\tMachine Directives\n-* BPF Opcodes::\t\t\tOpcodes\n-* BPF Pseudo-C Syntax:: Alternative Pseudo-C Assembly Syntax\n+* BPF Options:: BPF specific command-line options.\n+* BPF Special Characters:: Comments and statements.\n+* BPF Registers:: Register names.\n+* BPF Directives::\t\tMachine directives.\n+* BPF Instructions:: Machine instructions.\n @end menu\n \n @node BPF Options\n-@section Options\n+@section BPF Options\n @cindex BPF options (none)\n @cindex options for BPF (none)\n \n@@ -38,22 +38,29 @@ This option specifies that the assembler should emit big-endian eBPF.\n @item -EL\n This option specifies that the assembler should emit little-endian\n eBPF.\n+\n+@cindex @option{-mdialect} command-line options, BPF\n+@item -mdialect=@var{dialect}\n+This option specifies the assembly language dialect to recognize while\n+assembling. The assembler supports @option{normal} and\n+@option{pseudoc}.\n+\n+@cindex @option{-misa-spec} command-line options, BPF\n+@item -misa-spec=@var{spec}\n+This option specifies the version of the BPF instruction set to use\n+when assembling. The BPF ISA versions supported are @option{v1} @option{v2}, @option{v3} and @option{v4}.\n+\n+The value @option{xbpf} can be specified to recognize extra\n+instructions that are used by GCC for testing purposes. But beware\n+this is not valid BPF.\n @end table\n \n Note that if no endianness option is specified in the command line,\n the host endianness is used.\n @c man end\n \n-@node BPF Syntax\n-@section Syntax\n-@menu\n-* BPF-Chars:: Special Characters\n-* BPF-Regs:: Register Names\n-* BPF-Pseudo-Maps::\t Pseudo map fds\n-@end menu\n-\n-@node BPF-Chars\n-@subsection Special Characters\n+@node BPF Special Characters\n+@section BPF Special Characters\n \n @cindex line comment character, BPF\n @cindex BPF line comment character\n@@ -64,50 +71,49 @@ the first character of a line, the whole line is treated as a comment.\n @cindex statement separator, BPF\n Statements and assembly directives are separated by newlines.\n \n-@node BPF-Regs\n-@subsection Register Names\n+@node BPF Registers\n+@section BPF Registers\n \n @cindex BPF register names\n @cindex register names, BPF\n The eBPF processor provides ten general-purpose 64-bit registers,\n which are read-write, and a read-only frame pointer register:\n \n+@noindent\n+In normal syntax:\n+\n @table @samp\n @item %r0 .. %r9\n General-purpose registers.\n @item %r10\n-Frame pointer register.\n+@itemx %fp\n+Read-only frame pointer register.\n @end table\n \n-Some registers have additional names, to reflect their role in the\n-eBPF ABI:\n+All BPF registers are 64-bit long. However, in the Pseudo-C syntax\n+registers can be referred using different names, which actually\n+reflect the kind of instruction they appear on:\n+\n+@noindent\n+In pseudoc syntax:\n \n @table @samp\n-@item %a\n-This is @samp{%r0}.\n-@item %ctx\n-This is @samp{%r6}.\n-@item %fp\n-This is @samp{%r10}.\n+@item r0..r9\n+General-purpose register in an instruction that operates on its value\n+as if it was a 64-bit value.\n+@item w0..w9\n+General-purpose register in an instruction that operates on its value\n+as if it was a 32-bit value.\n+@item r10\n+Read-only frame pointer register.\n @end table\n \n-@node BPF-Pseudo-Maps\n-@subsection Pseudo Maps\n-\n-@cindex pseudo map fd, BPF\n-The @samp{LDDW} instruction can take a literal pseudo map file\n-descriptor as its second argument. This uses the syntax\n-@samp{%map_fd(N)} where @samp{N} is a signed number.\n-\n-For example, to load the address of the pseudo map with file\n-descriptor @samp{2} in register @samp{r1} we would do:\n-\n-@smallexample\n- lddw %r1, %map_fd(2)\n-@end smallexample\n+@noindent\n+Note that in the Pseudo-C syntax register names are not preceded by\n+@code{%} characters.\n \n @node BPF Directives\n-@section Machine Directives\n+@section BPF Directives\n \n @cindex machine directives, BPF\n \n@@ -128,8 +134,8 @@ The @code{.word} directive produces a 32 bit value.\n The @code{.dword} directive produces a 64 bit value.\n @end table\n \n-@node BPF Opcodes\n-@section Opcodes\n+@node BPF Instructions\n+@section BPF Instructions\n \n @cindex BPF opcodes\n @cindex opcodes for BPF\n@@ -137,10 +143,10 @@ In the instruction descriptions below the following field descriptors\n are used:\n \n @table @code\n-@item %d\n-Destination general-purpose register whose role is to be destination\n-of an operation.\n-@item %s\n+@item rd\n+Destination general-purpose register whose role is to be the\n+destination of an operation.\n+@item rs\n Source general-purpose register whose role is to be the source of an\n operation.\n @item disp16\n@@ -150,104 +156,237 @@ minus one.\n 32-bit signed PC-relative offset, measured in number of 64-bit words,\n minus one.\n @item offset16\n-Signed 16-bit immediate.\n+Signed 16-bit immediate representing an offset in bytes.\n+@item disp16\n+Signed 16-bit immediate representing a displacement to a target,\n+measured in number of 64-bit words @emph{minus one}.\n @item imm32\n Signed 32-bit immediate.\n @item imm64\n Signed 64-bit immediate.\n @end table\n \n-@subsubsection Arithmetic instructions\n+@subsection Arithmetic instructions\n \n The destination register in these instructions act like an\n accumulator.\n \n+Note that in pseudoc syntax these instructions should use @code{r}\n+registers.\n+\n @table @code\n-@item add %d, (%s|imm32)\n+@item add rd, rs\n+@itemx add rd, imm32\n+@itemx rd += rs\n+@itemx rd += imm32\n 64-bit arithmetic addition.\n-@item sub %d, (%s|imm32)\n+\n+@item sub rd, rs\n+@itemx sub rd, rs\n+@itemx rd -= rs\n+@itemx rd -= imm32\n 64-bit arithmetic subtraction.\n-@item mul %d, (%s|imm32)\n+\n+@item mul rd, rs\n+@itemx mul rd, imm32\n+@itemx rd *= rs\n+@itemx rd *= imm32\n 64-bit arithmetic multiplication.\n-@item div %d, (%s|imm32)\n+\n+@item div rd, rs\n+@itemx div rd, imm32\n+@itemx rd /= rs\n+@itemx rd /= imm32\n 64-bit arithmetic integer division.\n-@item mod %d, (%s|imm32)\n+\n+@item mod rd, rs\n+@itemx mod rd, imm32\n+@itemx rd %= rs\n+@itemx rd %= imm32\n 64-bit integer remainder.\n-@item and %d, (%s|imm32)\n+\n+@item and rd, rs\n+@itemx and rd, imm32\n+@itemx rd &= rs\n+@itemx rd &= imm32\n 64-bit bit-wise ``and'' operation.\n-@item or %d, (%s|imm32)\n+\n+@item or rd, rs\n+@itemx or rd, imm32\n+@itemx rd |= rs\n+@itemx rd |= imm32\n 64-bit bit-wise ``or'' operation.\n-@item xor %d, (%s|imm32)\n+\n+@item xor rd, imm32\n+@itemx xor rd, rs\n+@itemx rd ^= rs\n+@itemx rd ^= imm32\n 64-bit bit-wise exclusive-or operation.\n-@item lsh %d, (%s|imm32)\n-64-bit left shift, by @code{%s} or @code{imm32} bits.\n-@item rsh %d, (%s|imm32)\n-64-bit right logical shift, by @code{%s} or @code{imm32} bits.\n-@item arsh %d, (%s|imm32)\n-64-bit right arithmetic shift, by @code{%s} or @code{imm32} bits.\n-@item neg %d\n+\n+@item lsh rd, rs\n+@itemx ldh rd, imm32\n+@itemx rd <<= rs\n+@itemx rd <<= imm32\n+64-bit left shift, by @code{rs} or @code{imm32} bits.\n+\n+@item rsh %d, %s\n+@itemx rsh rd, imm32\n+@itemx rd >>= rs\n+@itemx rd >>= imm32\n+64-bit right logical shift, by @code{rs} or @code{imm32} bits.\n+\n+@item arsh rd, rs\n+@itemx arsh rd, imm32\n+@itemx rd s>>= rs\n+@itemx rd s>>= imm32\n+64-bit right arithmetic shift, by @code{rs} or @code{imm32} bits.\n+\n+@item neg rd, rs\n+@itemx neg rd, imm32\n+@itemx rd = - rs\n+@itemx rd = - imm32\n 64-bit arithmetic negation.\n-@item mov %d, (%s|imm32)\n-Move the 64-bit value of @code{%s} in @code{%d}, or load @code{imm32}\n-in @code{%d}.\n+\n+Note that in the @code{rd = - imm32} syntax there must be at least\n+one white space between @code{-} and @code{imm32}. Otherwise the\n+instruction is parsed as a @code{mov rd, imm32} instruction with a\n+negative 32-bit immediate. This is a consequence of a syntactic\n+ambiguity in the pseudoc syntax.\n+\n+@item mov rd, rs\n+@itemx mov rd, imm32\n+@itemx rd = rs\n+@itemx rd = imm32\n+Move the 64-bit value of @code{rs} in @code{rd}, or load @code{imm32}\n+in @code{rd}.\n @end table\n \n-@subsubsection 32-bit arithmetic instructions\n+@subsection 32-bit arithmetic instructions\n \n The destination register in these instructions act as an accumulator.\n \n+Note that in pseudoc syntax these instructions should use @code{w}\n+registers. It is not allowed to mix @code{w} and @code{r} registers\n+in the same instruction.\n+\n @table @code\n-@item add32 %d, (%s|imm32)\n+@item add32 rd, rs\n+@itemx add32 rd, imm32\n+@itemx rd += rs\n+@itemx rd += imm32\n 32-bit arithmetic addition.\n-@item sub32 %d, (%s|imm32)\n+\n+@item sub32 rd, rs\n+@itemx sub32 rd, imm32\n+@itemx rd -= rs\n+@itemx rd += imm32\n 32-bit arithmetic subtraction.\n-@item mul32 %d, (%s|imm32)\n+\n+@item mul32 rd, rs\n+@itemx mul32 rd, imm32\n+@itemx rd *= rs\n+@itemx rd *= imm32\n 32-bit arithmetic multiplication.\n-@item div32 %d, (%s|imm32)\n+\n+@item div32 rd, rs\n+@itemx div32 rd, imm32\n+@itemx rd /= rs\n+@itemx rd /= imm32\n 32-bit arithmetic integer division.\n-@item mod32 %d, (%s|imm32)\n+\n+@item mod32 rd, rs\n+@itemx mod32 rd, imm32\n+@itemx rd %= rs\n+@itemx rd %= imm32\n 32-bit integer remainder.\n-@item and32 %d, (%s|imm32)\n+\n+@item and32 rd, rs\n+@itemx and32 rd, imm32\n+@itemx rd &= rs\n+@itemx rd &= imm32\n 32-bit bit-wise ``and'' operation.\n-@item or32 %d, (%s|imm32)\n+\n+@item or32 rd, rs\n+@itemx or32 rd, imm32\n+@itemx rd |= rs\n+@itemx rd |= imm32\n 32-bit bit-wise ``or'' operation.\n-@item xor32 %d, (%s|imm32)\n+\n+@item xor32 rd, rs\n+@itemx xor32 rd, imm32\n+@itemx rd ^= rs\n+@itemx rd ^= imm32\n 32-bit bit-wise exclusive-or operation.\n-@item lsh32 %d, (%s|imm32)\n-32-bit left shift, by @code{%s} or @code{imm32} bits.\n-@item rsh32 %d, (%s|imm32)\n-32-bit right logical shift, by @code{%s} or @code{imm32} bits.\n-@item arsh32 %d, (%s|imm32)\n-32-bit right arithmetic shift, by @code{%s} or @code{imm32} bits.\n-@item neg32 %d\n+\n+@item lsh32 rd, rs\n+@itemx lsh32 rd, imm32\n+@itemx rd <<= rs\n+@itemx rd <<= imm32\n+32-bit left shift, by @code{rs} or @code{imm32} bits.\n+\n+@item rsh32 rd, rs\n+@itemx rsh32 rd, imm32\n+@itemx rd >>= rs\n+@itemx rd >>= imm32\n+32-bit right logical shift, by @code{rs} or @code{imm32} bits.\n+\n+@item arsh32 rd, rs\n+@itemx arsh32 rd, imm32\n+@itemx rd s>>= rs\n+@itemx rd s>>= imm32\n+32-bit right arithmetic shift, by @code{rs} or @code{imm32} bits.\n+\n+@item neg32 rd, rs\n+@itemx neg32 rd, imm32\n+@itemx rd = - rs\n+@itemx rd = - imm32\n 32-bit arithmetic negation.\n-@item mov32 %d, (%s|imm32)\n-Move the 32-bit value of @code{%s} in @code{%d}, or load @code{imm32}\n-in @code{%d}.\n+\n+Note that in the @code{rd = - imm32} syntax there must be at least\n+one white space between @code{-} and @code{imm32}. Otherwise the\n+instruction is parsed as a @code{mov32 rd, imm32} instruction with a\n+negative 32-bit immediate. This is a consequence of a syntactic\n+ambiguity in the pseudoc syntax.\n+\n+@item mov32 rd, rs\n+@itemx mov32 rd, imm32\n+@itemx rd = rs\n+@itemx rd = imm32\n+Move the 32-bit value of @code{rs} in @code{rd}, or load @code{imm32}\n+in @code{rd}.\n @end table\n \n-@subsubsection Endianness conversion instructions\n+@subsection Endianness conversion instructions\n \n @table @code\n-@item endle %d, (16|32|64)\n-Convert the 16-bit, 32-bit or 64-bit value in @code{%d} to\n-little-endian.\n-@item endbe %d, (16|32|64)\n-Convert the 16-bit, 32-bit or 64-bit value in @code{%d} to big-endian.\n+@item endle rd, 16\n+@itemx endle rd, 32\n+@itemx endle rd, 64\n+@itemx rd = le16 rd\n+@itemx rd = le32 rd\n+@itemx rd = le64 rd\n+Convert the 16-bit, 32-bit or 64-bit value in @code{rd} to\n+little-endian and store it back in @code{rd}.\n+@item endbe %d, 16\n+@itemx endbe %d, 32\n+@itemx endbe %d, 64\n+@itemx rd = be16 rd\n+@itemx rd = be32 rd\n+@itemx rd = be64 rd\n+Convert the 16-bit, 32-bit or 64-bit value in @code{rd} to big-endian\n+and store it back in @code{rd}.\n @end table\n \n-@subsubsection 64-bit load and pseudo maps\n+@subsection 64-bit load and pseudo maps\n \n @table @code\n-@item lddw %d, imm64\n-Load the given signed 64-bit immediate, or pseudo map descriptor, to\n-the destination register @code{%d}.\n-@item lddw %d, %map_fd(N)\n-Load the address of the given pseudo map fd @emph{N} to the\n-destination register @code{%d}.\n+@item lddw rd, imm64\n+@itemx rd = imm64 ll\n+Load the given signed 64-bit immediate to the destination register\n+@code{rd}.\n @end table\n \n-@subsubsection Load instructions for socket filters\n+@subsection Load instructions for socket filters\n \n The following instructions are intended to be used in socket filters,\n and are therefore not general-purpose: they make assumptions on the\n@@ -259,29 +398,43 @@ Absolute loads:\n \n @table @code\n @item ldabsdw imm32\n+@itemx r0 = *(u64 *) skb[imm32]\n Absolute 64-bit load.\n+\n @item ldabsw imm32\n+@itemx r0 = *(u32 *) skb[imm32]\n Absolute 32-bit load.\n+\n @item ldabsh imm32\n+@itemx r0 = *(u16 *) skb[imm32]\n Absolute 16-bit load.\n+\n @item ldabsb imm32\n+@itemx r0 = *(u8 *) skb[imm32]\n Absolute 8-bit load.\n @end table\n \n Indirect loads:\n \n @table @code\n-@item ldinddw %s, imm32\n+@item ldinddw rs, imm32\n+@itemx r0 = *(u64 *) skb[rs + imm32]\n Indirect 64-bit load.\n-@item ldindw %s, imm32\n+\n+@item ldindw rs, imm32\n+@itemx r0 = *(u32 *) skb[rs + imm32]\n Indirect 32-bit load.\n-@item ldindh %s, imm32\n+\n+@item ldindh rs, imm32\n+@itemx r0 = *(u16 *) skb[rs + imm32]\n Indirect 16-bit load.\n+\n @item ldindb %s, imm32\n+@itemx r0 = *(u8 *) skb[rs + imm32]\n Indirect 8-bit load.\n @end table\n \n-@subsubsection Generic load/store instructions\n+@subsection Generic load/store instructions\n \n General-purpose load and store instructions are provided for several\n word sizes.\n@@ -289,43 +442,64 @@ word sizes.\n Load to register instructions:\n \n @table @code\n-@item ldxdw %d, [%s+offset16]\n+@item ldxdw rd, [rs + offset16]\n+@itemx rd = *(u64 *) (rs + offset16)\n Generic 64-bit load.\n-@item ldxw %d, [%s+offset16]\n+\n+@item ldxw rd, [rs + offset16]\n+@itemx rd = *(u32 *) (rs + offset16)\n Generic 32-bit load.\n-@item ldxh %d, [%s+offset16]\n+\n+@item ldxh rd, [rs + offset16]\n+@itemx rd = *(u16 *) (rs + offset16)\n Generic 16-bit load.\n-@item ldxb %d, [%s+offset16]\n+\n+@item ldxb rd, [rs + offset16]\n+@itemx rd = *(u8 *) (rs + offset16)\n Generic 8-bit load.\n @end table\n \n Store from register instructions:\n \n @table @code\n-@item stxdw [%d+offset16], %s\n+@item stxdw [rd + offset16], %s\n+@itemx *(u64 *) (rd + offset16)\n Generic 64-bit store.\n-@item stxw [%d+offset16], %s\n+\n+@item stxw [rd + offset16], %s\n+@itemx *(u32 *) (rd + offset16)\n Generic 32-bit store.\n-@item stxh [%d+offset16], %s\n+\n+@item stxh [rd + offset16], %s\n+@itemx *(u16 *) (rd + offset16)\n Generic 16-bit store.\n-@item stxb [%d+offset16], %s\n+\n+@item stxb [rd + offset16], %s\n+@itemx *(u8 *) (rd + offset16)\n Generic 8-bit store.\n @end table\n \n Store from immediates instructions:\n \n @table @code\n-@item stddw [%d+offset16], imm32\n+@item stdw [rd + offset16], imm32\n+@itemx *(u64 *) (rd + offset16) = imm32\n Store immediate as 64-bit.\n-@item stdw [%d+offset16], imm32\n+\n+@item stw [rd + offset16], imm32\n+@itemx *(u32 *) (rd + offset16) = imm32\n Store immediate as 32-bit.\n-@item stdh [%d+offset16], imm32\n+\n+@item sth [rd + offset16], imm32\n+@itemx *(u16 *) (rd + offset16) = imm32\n Store immediate as 16-bit.\n-@item stdb [%d+offset16], imm32\n+\n+@item stb [rd + offset16], imm32\n+@itemx *(u8 *) (rd + offset16) = imm32\n Store immediate as 8-bit.\n @end table\n \n-@subsubsection Jump instructions\n+@subsection Jump instructions\n \n eBPF provides the following compare-and-jump instructions, which\n compare the values of the two given registers, or the values of a\n@@ -333,29 +507,74 @@ register and an immediate, and perform a branch in case the comparison\n holds true.\n \n @table @code\n-@item ja %d,(%s|imm32),disp16\n+@item ja disp16\n+@itemx goto disp16\n Jump-always.\n-@item jeq %d,(%s|imm32),disp16\n+\n+@item jeq rd, rs, disp16\n+@itemx jeq rd, imm32, disp16\n+@itemx if rd == rs goto disp16\n+@itemx if rd == imm32 goto disp16\n Jump if equal, unsigned.\n-@item jgt %d,(%s|imm32),disp16\n+\n+@item jgt rd, rs, disp16\n+@itemx jgt rd, imm32, disp16\n+@itemx if rd > rs goto disp16\n+@itemx if rd > imm32 goto disp16\n Jump if greater, unsigned.\n-@item jge %d,(%s|imm32),disp16\n+\n+@item jge rd, rs, disp16\n+@itemx jge rd, imm32, disp16\n+@itemx if rd >= rs goto disp16\n+@itemx if rd >= imm32 goto disp16\n Jump if greater or equal.\n-@item jlt %d,(%s|imm32),disp16\n+\n+@item jlt rd, rs, disp16\n+@itemx jlt rd, imm32, disp16\n+@itemx if rd < rs goto disp16\n+@itemx if rd < imm32 goto disp16\n Jump if lesser.\n-@item jle %d,(%s|imm32),disp16\n+\n+@item jle rd , rs, disp16\n+@itemx jle rd, imm32, disp16\n+@itemx if rd <= rs goto disp16\n+@itemx if rd <= imm32 goto disp16\n Jump if lesser or equal.\n-@item jset %d,(%s|imm32),disp16\n+\n+@item jset rd, rs, disp16\n+@itemx jset rd, imm32, disp16\n+@itemx if rd & rs goto disp16\n+@itemx if rd & imm32 goto disp16\n Jump if signed equal.\n-@item jne %d,(%s|imm32),disp16\n+\n+@item jne rd, rs, disp16\n+@itemx jne rd, imm32, disp16\n+@itemx if rd != rs goto disp16\n+@itemx if rd != imm32 goto disp16\n Jump if not equal.\n-@item jsgt %d,(%s|imm32),disp16\n+\n+@item jsgt rd, rs, disp16\n+@itemx jsgt rd, imm32, disp16\n+@itemx if rd s> rs goto disp16\n+@itemx if rd s> imm32 goto disp16\n Jump if signed greater.\n-@item jsge %d,(%s|imm32),disp16\n+\n+@item jsge rd, rs, disp16\n+@itemx jsge rd, imm32, disp16\n+@itemx if rd s>= rd goto disp16\n+@itemx if rd s>= imm32 goto disp16\n Jump if signed greater or equal.\n-@item jslt %d,(%s|imm32),disp16\n+\n+@item jslt rd, rs, disp16\n+@itemx jslt rd, imm32, disp16\n+@itemx if rd s< rs goto disp16\n+@itemx if rd s< imm32 goto disp16\n Jump if signed lesser.\n-@item jsle %d,(%s|imm32),disp16\n+\n+@item jsle rd, rs, disp16\n+@itemx jsle rd, imm32, disp16\n+@itemx if rd s<= rs goto disp16\n+@itemx if rd s<= imm32 goto disp16\n Jump if signed lesser or equal.\n @end table\n \n@@ -363,7 +582,8 @@ A call instruction is provided in order to perform calls to other eBPF\n functions, or to external kernel helpers:\n \n @table @code\n-@item call (disp32|imm32)\n+@item call disp32\n+@item call imm32\n Jump and link to the offset @emph{disp32}, or to the kernel helper\n function identified by @emph{imm32}.\n @end table\n@@ -375,203 +595,187 @@ Finally:\n Terminate the eBPF program.\n @end table\n \n-@subsubsection Atomic instructions\n+@subsection 32-bit jump instructions\n \n-Atomic exchange-and-add instructions are provided in two flavors: one\n-for swapping 64-bit quantities and another for 32-bit quantities.\n+eBPF provides the following compare-and-jump instructions, which\n+compare the 32-bit values of the two given registers, or the values of\n+a register and an immediate, and perform a branch in case the\n+comparison holds true.\n \n-@table @code\n-@item xadddw [%d+offset16],%s\n-Exchange-and-add a 64-bit value at the specified location.\n-@item xaddw [%d+offset16],%s\n-Exchange-and-add a 32-bit value at the specified location.\n-@end table\n+These instructions are only available in BPF v3 or later.\n \n-@node BPF Pseudo-C Syntax\n-@section BPF Pseudo-C Syntax\n+@table @code\n+@item jeq32 rd, rs, disp16\n+@itemx jeq32 rd, imm32, disp16\n+@itemx if rd == rs goto disp16\n+@itemx if rd == imm32 goto disp16\n+Jump if equal, unsigned.\n \n-This assembler supports another syntax to denote BPF instructions,\n-which is an alternative to the normal looking syntax documented above.\n-This alternatative syntax, which we call @dfn{pseudo-C syntax}, is\n-supported by the LLVM/clang integrated assembler.\n+@item jgt32 rd, rs, disp16\n+@itemx jgt32 rd, imm32, disp16\n+@itemx if rd > rs goto disp16\n+@itemx if rd > imm32 goto disp16\n+Jump if greater, unsigned.\n \n-This syntax is very unconventional, but we need to support it in order\n-to support inline assembly in existing BPF programs.\n+@item jge32 rd, rs, disp16\n+@itemx jge32 rd, imm32, disp16\n+@itemx if rd >= rs goto disp16\n+@itemx if rd >= imm32 goto disp16\n+Jump if greater or equal.\n \n-Note that the assembler is able to parse sources in which both\n-syntaxes coexist: some instructions can use the usual assembly like\n-syntax, whereas some other instructions in the same file can use the\n-pseudo-C syntax.\n+@item jlt32 rd, rs, disp16\n+@itemx jlt32 rd, imm32, disp16\n+@itemx if rd < rs goto disp16\n+@itemx if rd < imm32 goto disp16\n+Jump if lesser.\n \n-@subsubsection Pseudo-C Register Names\n+@item jle32 rd , rs, disp16\n+@itemx jle32 rd, imm32, disp16\n+@itemx if rd <= rs goto disp16\n+@itemx if rd <= imm32 goto disp16\n+Jump if lesser or equal.\n \n-All BPF registers are 64-bit long. However, in the Pseudo-C syntax\n-registers can be referred using different names, which actually\n-reflect the kind of instruction they appear on:\n+@item jset32 rd, rs, disp16\n+@itemx jset32 rd, imm32, disp16\n+@itemx if rd & rs goto disp16\n+@itemx if rd & imm32 goto disp16\n+Jump if signed equal.\n \n-@table @samp\n-@item r0..r9\n-General-purpose register in an instruction that operates on its value\n-as if it was a 64-bit value.\n-@item w0..w9\n-General-purpose register in an instruction that operates on its value\n-as if it was a 32-bit value.\n-@end table\n+@item jne32 rd, rs, disp16\n+@itemx jne32 rd, imm32, disp16\n+@itemx if rd != rs goto disp16\n+@itemx if rd != imm32 goto disp16\n+Jump if not equal.\n \n-@noindent\n-Note that in the Pseudo-C syntax register names are not preceded by\n-@code{%} characters.\n+@item jsgt32 rd, rs, disp16\n+@itemx jsgt32 rd, imm32, disp16\n+@itemx if rd s> rs goto disp16\n+@itemx if rd s> imm32 goto disp16\n+Jump if signed greater.\n \n-@subsubsection Arithmetic instructions\n+@item jsge32 rd, rs, disp16\n+@itemx jsge32 rd, imm32, disp16\n+@itemx if rd s>= rd goto disp16\n+@itemx if rd s>= imm32 goto disp16\n+Jump if signed greater or equal.\n \n-In all the instructions below, the operations are 64-bit or 32-bit\n-depending on the names used to refer to the registers. For example\n-@code{r3 += r2} will perform 64-bit addition, whereas @code{w3 += w2}\n-will perform 32-bit addition. Mixing register prefixes is an error,\n-for example @code{r3 += w2}.\n+@item jslt32 rd, rs, disp16\n+@itemx jslt32 rd, imm32, disp16\n+@itemx if rd s< rs goto disp16\n+@itemx if rd s< imm32 goto disp16\n+Jump if signed lesser.\n \n-@table @code\n-@item dst_reg += (imm32|src_reg)\n-Arithmetic addition.\n-@item dst_reg -= (imm32|src_reg)\n-Arithmetic subtraction.\n-@item dst_reg *= (imm32|src_reg)\n-Arithmetic multiplication.\n-@item dst_reg /= (imm32|src_reg)\n-Arithmetic integer unsigned division.\n-@item dst_reg %= (imm32|src_reg)\n-Arithmetic integer unsigned remainder.\n-@item dst_reg &= (imm32|src_reg)\n-Bit-wise ``and'' operation.\n-@item dst_reg |= (imm32|src_reg)\n-Bit-wise ``or'' operation.\n-@item dst_reg ^= (imm32|src_reg)\n-Bit-wise exclusive-or operation.\n-@item dst_reg <<= (imm32|src_reg)\n-Left shift, by whatever specified number of bits.\n-@item dst_reg >>= (imm32|src_reg)\n-Right logical shift, by whatever specified number of bits.\n-@item dst_reg s>>= (imm32|src_reg)\n-Right arithmetic shift, by whatever specified number of bits.\n-@item dst_reg = (imm32|src_reg)\n-Move the value in @code{imm32} or @code{src_reg} in @code{dst_reg}.\n-@item dst_reg = -dst_reg\n-Arithmetic negation.\n+@item jsle32 rd, rs, disp16\n+@itemx jsle32 rd, imm32, disp16\n+@itemx if rd s<= rs goto disp16\n+@itemx if rd s<= imm32 goto disp16\n+Jump if signed lesser or equal.\n @end table\n \n-@subsubsection Endianness conversion instructions\n+@subsection Atomic instructions\n+\n+Atomic exchange-and-add instructions are provided in two flavors: one\n+for swapping 64-bit quantities and another for 32-bit quantities.\n \n @table @code\n-@item dst_reg = le16 src_reg\n-Convert the 16-bit value in @code{src_reg} to little-endian.\n-@item dst_reg = le32 src_reg\n-Convert the 32-bit value in @code{src_reg} to little-endian.\n-@item dst_reg = le64 src_reg\n-Convert the 64-bit value in @code{src_reg} to little-endian.\n-@item dst_reg = be16 src_reg\n-Convert the 16-bit value in @code{src_reg} to big-endian.\n-@item dst_reg = be32 src_reg\n-Convert the 32-bit value in @code{src_reg} to big-endian.\n-@item dst_reg = be64 src_reg\n-Convert the 64-bit value in @code{src_reg} to big-endian.\n+@item aadd [rd + offset16], rs\n+@itemx *(u64 *)(rd + offset16) = rs\n+Atomic add instruction.\n+\n+@item aor [rd + offset16], rs\n+@itemx *(u64 *) (rd + offset16) |= rs\n+Atomic or instruction.\n+\n+@item aand [rd + offset16], rs\n+@itemx *(u64 *) (rd + offset16) &= rs\n+Atomic and instruction.\n+\n+@item axor [rd + offset16], rs\n+@itemx *(u64 *) (rd + offset16) ^= rs\n+Atomic xor instruction\n+@item xaddw [%d+offset16],%s\n+Exchange-and-add a 32-bit value at the specified location.\n @end table\n \n-@subsubsection 64-bit load and pseudo maps\n+@noindent\n+The following variants perform fetching before the atomic operation.\n \n @table @code\n-@item dst_reg = imm64 ll\n-Load the given signed 64-bit immediate, or pseudo map descriptor, to\n-the destination register @code{dst_reg}.\n+@item afadd [dr + offset16], rs\n+@itemx ???\n+Atomic fetch-and-add instruction.\n+\n+@item afor [dr + offset16], rs\n+@itemx ???\n+Atomic fetch-and-or instruction.\n+\n+@item afand [dr + offset16], rs\n+@itemx ???\n+Atomic fetch-and-and instruction.\n+\n+@item afxor [dr + offset16], rs\n+@itemx ???\n+Atomic fetch-and-or instruction\n @end table\n \n-@subsubsection Load instructions for socket filters\n+The above instructions were introduced in the V3 of the BPF\n+instruction set. The following instruction is supported for backwards\n+compatibility:\n \n @table @code\n-@item r0 = *(u8 *)skb[imm32]\n-Absolute 8-bit load.\n-@item r0 = *(u16 *)skb[imm32]\n-Absolute 16-bit load.\n-@item r0 = *(u32 *)skb[imm32]\n-Absolute 32-bit load.\n-@item r0 = *(u64 *)skb[imm32]\n-Absolute 64-bit load.\n-@item r0 = *(u8 *)skb[src_reg + imm32]\n-Indirect 8-bit load.\n-@item r0 = *(u16 *)skb[src_reg + imm32]\n-Indirect 16-bit load.\n-@item r0 = *(u32 *)skb[src_reg + imm32]\n-Indirect 32-bit load.\n-@item r0 = *(u64 *)skb[src_reg + imm32]\n-Indirect 64-bit load.\n+@item xadddw [rd + offset16], rs\n+Alias to @code{aadd}.\n @end table\n \n-@subsubsection Generic load/store instructions\n+@subsection 32-bit atomic instructions\n+\n+Atomic exchange-and-add instructions are provided in two flavors: one\n+for swapping 32-bit quantities and another for 32-bit quantities.\n \n @table @code\n-@item dst_reg = *(u8 *)(src_reg + offset16)\n-Generic 8-bit load.\n-@item dst_reg = *(u16 *)(src_reg + offset16)\n-Generic 16-bit load.\n-@item dst_reg = *(u32 *)(src_reg + offset16)\n-Generic 32-bit load.\n-@item dst_reg = *(u64 *)(src_reg + offset16)\n-Generic 64-bit load.\n-@c XXX stb\n-@c NO PSEUDOC-SYNTAX\n-@c XXX sth\n-@c NO PSEUDOC-SYNTAX\n-@c XXX stw\n-@c NO PSEUDOC-SYNTAX\n-@c XXX stdw\n-@c NO PSEUDOC-SYNTAX\n-@item *(u8 *)(dst_reg + offset16) = src_reg\n-Generic 8-bit store.\n-@item *(u16 *)(dst_reg + offset16) = src_reg\n-Generic 16-bit store.\n-@item *(u32 *)(dst_reg + offset16) = src_reg\n-Generic 32-bit store.\n-@item *(u64 *)(dst_reg + offset16) = src_reg\n-Generic 64-bit store.\n+@item aadd32 [rd + offset16], rs\n+@itemx *(u32 *)(rd + offset16) = rs\n+Atomic add instruction.\n+\n+@item aor32 [rd + offset16], rs\n+@itemx *(u32 *) (rd + offset16) |= rs\n+Atomic or instruction.\n+\n+@item aand32 [rd + offset16], rs\n+@itemx *(u32 *) (rd + offset16) &= rs\n+Atomic and instruction.\n+\n+@item axor32 [rd + offset16], rs\n+@itemx *(u32 *) (rd + offset16) ^= rs\n+Atomic xor instruction\n @end table\n \n-@subsubsection Jump instructions\n+@noindent\n+The following variants perform fetching before the atomic operation.\n \n @table @code\n-@item goto disp16\n-Jump-always.\n-@item if dst_reg == (imm32|src_reg) goto disp16\n-Jump if equal.\n-@item if dst_reg & (imm32|src_reg) goto disp16\n-Jump if signed equal.\n-@item if dst_reg != (imm32|src_reg) goto disp16\n-Jump if not equal.\n-@item if dst_reg > (imm32|src_reg) goto disp16\n-Jump if bigger, unsigned.\n-@item if dst_reg < (imm32|src_reg) goto disp16\n-Jump if smaller, unsigned.\n-@item if dst_reg >= (imm32|src_reg) goto disp16\n-Jump if bigger or equal, unsigned.\n-@item if dst_reg <= (imm32|src_reg) goto disp16\n-Jump if smaller or equal, unsigned.\n-@item if dst_reg s> (imm32|src_reg) goto disp16\n-Jump if bigger, signed.\n-@item if dst_reg s< (imm32|src_reg) goto disp16\n-Jump if smaller, signed.\n-@item if dst_reg s>= (imm32|src_reg) goto disp16\n-Jump if bigger or equal, signed.\n-@item if dst_reg s<= (imm32|src_reg) goto disp16\n-Jump if smaller or equal, signed.\n-@item call imm32\n-Jump and link.\n-@item exit\n-Terminate the eBPF program.\n+@item afadd32 [dr + offset16], rs\n+@itemx ???\n+Atomic fetch-and-add instruction.\n+\n+@item afor32 [dr + offset16], rs\n+@itemx ???\n+Atomic fetch-and-or instruction.\n+\n+@item afand32 [dr + offset16], rs\n+@itemx ???\n+Atomic fetch-and-and instruction.\n+\n+@item afxor32 [dr + offset16], rs\n+@itemx ???\n+Atomic fetch-and-or instruction\n @end table\n \n-@subsubsection Atomic instructions\n+The above instructions were introduced in the V3 of the BPF\n+instruction set. The following instruction is supported for backwards\n+compatibility:\n \n @table @code\n-@item lock *(u64 *)(dst_reg + offset16) += src_reg\n-Exchange-and-add a 64-bit value at the specified location.\n-@item lock *(u32 *)(dst_reg + offset16) += src_reg\n-Exchange-and-add a 32-bit value at the specified location.\n+@item xaddw [rd + offset16], rs\n+Alias to @code{aadd32}.\n @end table\ndiff --git a/gas/testsuite/gas/all/assign-bad-recursive.d b/gas/testsuite/gas/all/assign-bad-recursive.d\nindex 678be3e7c9f..aeec5d55f8a 100644\n--- a/gas/testsuite/gas/all/assign-bad-recursive.d\n+++ b/gas/testsuite/gas/all/assign-bad-recursive.d\n@@ -1,5 +1,4 @@\n #name: bad recursive assignments\n #source: assign-bad-recursive.s\n #xfail: bfin-*-*\n-#notarget: *bpf-*-*\n #error_output: assign-bad-recursive.l\ndiff --git a/gas/testsuite/gas/all/eqv-dot.d b/gas/testsuite/gas/all/eqv-dot.d\nindex d97db14995e..fc40b09f217 100644\n--- a/gas/testsuite/gas/all/eqv-dot.d\n+++ b/gas/testsuite/gas/all/eqv-dot.d\n@@ -2,7 +2,7 @@\n #name: eqv involving dot\n # bfin doesn't support 'symbol = expression'\n # tic30 and tic4x have 4 octets per byte, tic54x has 2 octets per byte\n-#notarget: bfin-*-* *c30-*-* *c4x-*-* *c54x-*-* *bpf-*-*\n+#notarget: bfin-*-* *c30-*-* *c4x-*-* *c54x-*-*\n # linkrelax targets don't handle equivalence expressions well (nor any\n # other forward expression). mep uses complex relocs\n #xfail: am33_2.0-*-* crx-*-* h8300-*-* mn10200-*-* mn10300-*-* mep-*-*\ndiff --git a/gas/testsuite/gas/all/gas.exp b/gas/testsuite/gas/all/gas.exp\nindex bab5a6c7ba5..007408f03d8 100644\n--- a/gas/testsuite/gas/all/gas.exp\n+++ b/gas/testsuite/gas/all/gas.exp\n@@ -105,7 +105,7 @@ if { [istarget \"pdp11-*-*\"] } then {\n run_dump_test eqv-dot\n }\n \n-if { ![istarget \"bfin-*-*\"] && ![istarget \"bpf-*-*\"] } then {\n+if { ![istarget \"bfin-*-*\"] } then {\n gas_test \"assign-ok.s\" \"\" \"\" \"== assignment support\"\n }\n gas_test_error \"assign-bad.s\" \"\" \"== assignment for symbol already set\"\n@@ -403,8 +403,7 @@ if { ([istarget \"i*86-*-*pe*\"] && ![istarget \"i*86-*-openbsd*\"]) \\\n gas_test \"fastcall.s\" \"\" \"\" \"fastcall labels\"\n }\n \n-if { ![istarget \"bfin-*-*\"] && ![istarget \"nds32*-*-*\"] \\\n- && ![istarget \"bpf-*-*\"] } then {\n+if { ![istarget \"bfin-*-*\"] && ![istarget \"nds32*-*-*\"] } then {\n run_dump_test assign\n }\n run_dump_test sleb128\ndiff --git a/gas/testsuite/gas/bpf/alu-be-pseudoc.d b/gas/testsuite/gas/bpf/alu-be-pseudoc.d\nindex 0355d196d77..8d8c29e91c7 100644\n--- a/gas/testsuite/gas/bpf/alu-be-pseudoc.d\n+++ b/gas/testsuite/gas/bpf/alu-be-pseudoc.d\n@@ -1,5 +1,65 @@\n-#as: --EB\n+#as: -EB -mdialect=pseudoc\n #source: alu-pseudoc.s\n-#objdump: -dr\n-#dump: alu-be.dump\n+#objdump: -dr -M hex,pseudoc\n #name: eBPF ALU64 instructions, big endian, pseudoc syntax\n+\n+.*: +file format .*bpf.*\n+\n+Disassembly of section .text:\n+\n+0+ <.text>:\n+ 0:\t07 20 00 00 00 00 02 9a \tr2\\+=0x29a\n+ 8:\t07 30 00 00 ff ff fd 66 \tr3\\+=0xfffffd66\n+ 10:\t07 40 00 00 7e ad be ef \tr4\\+=0x7eadbeef\n+ 18:\t0f 56 00 00 00 00 00 00 \tr5\\+=r6\n+ 20:\t17 20 00 00 00 00 02 9a \tr2-=0x29a\n+ 28:\t17 30 00 00 ff ff fd 66 \tr3-=0xfffffd66\n+ 30:\t17 40 00 00 7e ad be ef \tr4-=0x7eadbeef\n+ 38:\t1f 56 00 00 00 00 00 00 \tr5-=r6\n+ 40:\t27 20 00 00 00 00 02 9a \tr2\\*=0x29a\n+ 48:\t27 30 00 00 ff ff fd 66 \tr3\\*=0xfffffd66\n+ 50:\t27 40 00 00 7e ad be ef \tr4\\*=0x7eadbeef\n+ 58:\t2f 56 00 00 00 00 00 00 \tr5\\*=r6\n+ 60:\t37 20 00 00 00 00 02 9a \tr2/=0x29a\n+ 68:\t37 30 00 00 ff ff fd 66 \tr3/=0xfffffd66\n+ 70:\t37 40 00 00 7e ad be ef \tr4/=0x7eadbeef\n+ 78:\t3f 56 00 00 00 00 00 00 \tr5/=r6\n+ 80:\t47 20 00 00 00 00 02 9a \tr2|=0x29a\n+ 88:\t47 30 00 00 ff ff fd 66 \tr3|=0xfffffd66\n+ 90:\t47 40 00 00 7e ad be ef \tr4|=0x7eadbeef\n+ 98:\t4f 56 00 00 00 00 00 00 \tr5|=r6\n+ a0:\t57 20 00 00 00 00 02 9a \tr2&=0x29a\n+ a8:\t57 30 00 00 ff ff fd 66 \tr3&=0xfffffd66\n+ b0:\t57 40 00 00 7e ad be ef \tr4&=0x7eadbeef\n+ b8:\t5f 56 00 00 00 00 00 00 \tr5&=r6\n+ c0:\t67 20 00 00 00 00 02 9a \tr2<<=0x29a\n+ c8:\t67 30 00 00 ff ff fd 66 \tr3<<=0xfffffd66\n+ d0:\t67 40 00 00 7e ad be ef \tr4<<=0x7eadbeef\n+ d8:\t6f 56 00 00 00 00 00 00 \tr5<<=r6\n+ e0:\t77 20 00 00 00 00 02 9a \tr2>>=0x29a\n+ e8:\t77 30 00 00 ff ff fd 66 \tr3>>=0xfffffd66\n+ f0:\t77 40 00 00 7e ad be ef \tr4>>=0x7eadbeef\n+ f8:\t7f 56 00 00 00 00 00 00 \tr5>>=r6\n+ 100:\t97 20 00 00 00 00 02 9a \tr2%=0x29a\n+ 108:\t97 30 00 00 ff ff fd 66 \tr3%=0xfffffd66\n+ 110:\t97 40 00 00 7e ad be ef \tr4%=0x7eadbeef\n+ 118:\t9f 56 00 00 00 00 00 00 \tr5%=r6\n+ 120:\ta7 20 00 00 00 00 02 9a \tr2\\^=0x29a\n+ 128:\ta7 30 00 00 ff ff fd 66 \tr3\\^=0xfffffd66\n+ 130:\ta7 40 00 00 7e ad be ef \tr4\\^=0x7eadbeef\n+ 138:\taf 56 00 00 00 00 00 00 \tr5\\^=r6\n+ 140:\tb7 20 00 00 00 00 02 9a \tr2=0x29a\n+ 148:\tb7 30 00 00 ff ff fd 66 \tr3=0xfffffd66\n+ 150:\tb7 40 00 00 7e ad be ef \tr4=0x7eadbeef\n+ 158:\tbf 56 00 00 00 00 00 00 \tr5=r6\n+ 160:\tc7 20 00 00 00 00 02 9a \tr2 s>>=0x29a\n+ 168:\tc7 30 00 00 ff ff fd 66 \tr3 s>>=0xfffffd66\n+ 170:\tc7 40 00 00 7e ad be ef \tr4 s>>=0x7eadbeef\n+ 178:\tcf 56 00 00 00 00 00 00 \tr5 s>>=r6\n+ 180:\t8f 23 00 00 00 00 00 00 \tr2=-r3\n+ 188:\td4 90 00 00 00 00 00 10 \tr9=le16 r9\n+ 190:\td4 80 00 00 00 00 00 20 \tr8=le32 r8\n+ 198:\td4 70 00 00 00 00 00 40 \tr7=le64 r7\n+ 1a0:\tdc 60 00 00 00 00 00 10 \tr6=be16 r6\n+ 1a8:\tdc 50 00 00 00 00 00 20 \tr5=be32 r5\n+ 1b0:\tdc 40 00 00 00 00 00 40 \tr4=be64 r4\ndiff --git a/gas/testsuite/gas/bpf/alu-be.d b/gas/testsuite/gas/bpf/alu-be.d\nindex afd2a6cfd6d..170db4b853d 100644\n--- a/gas/testsuite/gas/bpf/alu-be.d\n+++ b/gas/testsuite/gas/bpf/alu-be.d\n@@ -1,5 +1,65 @@\n-#as: --EB\n+#as: -EB -mdialect=normal\n #source: alu.s\n-#objdump: -dr\n-#dump: alu-be.dump\n-#name: eBPF ALU64 instructions, big endian, normal syntax\n+#objdump: -dr -M hex\n+#name: eBPF ALU instructions, big endian, normal syntax\n+\n+.*: +file format .*bpf.*\n+\n+Disassembly of section .text:\n+\n+0+ <.text>:\n+ 0:\t07 20 00 00 00 00 02 9a \tadd %r2,0x29a\n+ 8:\t07 30 00 00 ff ff fd 66 \tadd %r3,0xfffffd66\n+ 10:\t07 40 00 00 7e ad be ef \tadd %r4,0x7eadbeef\n+ 18:\t0f 56 00 00 00 00 00 00 \tadd %r5,%r6\n+ 20:\t17 20 00 00 00 00 02 9a \tsub %r2,0x29a\n+ 28:\t17 30 00 00 ff ff fd 66 \tsub %r3,0xfffffd66\n+ 30:\t17 40 00 00 7e ad be ef \tsub %r4,0x7eadbeef\n+ 38:\t1f 56 00 00 00 00 00 00 \tsub %r5,%r6\n+ 40:\t27 20 00 00 00 00 02 9a \tmul %r2,0x29a\n+ 48:\t27 30 00 00 ff ff fd 66 \tmul %r3,0xfffffd66\n+ 50:\t27 40 00 00 7e ad be ef \tmul %r4,0x7eadbeef\n+ 58:\t2f 56 00 00 00 00 00 00 \tmul %r5,%r6\n+ 60:\t37 20 00 00 00 00 02 9a \tdiv %r2,0x29a\n+ 68:\t37 30 00 00 ff ff fd 66 \tdiv %r3,0xfffffd66\n+ 70:\t37 40 00 00 7e ad be ef \tdiv %r4,0x7eadbeef\n+ 78:\t3f 56 00 00 00 00 00 00 \tdiv %r5,%r6\n+ 80:\t47 20 00 00 00 00 02 9a \tor %r2,0x29a\n+ 88:\t47 30 00 00 ff ff fd 66 \tor %r3,0xfffffd66\n+ 90:\t47 40 00 00 7e ad be ef \tor %r4,0x7eadbeef\n+ 98:\t4f 56 00 00 00 00 00 00 \tor %r5,%r6\n+ a0:\t57 20 00 00 00 00 02 9a \tand %r2,0x29a\n+ a8:\t57 30 00 00 ff ff fd 66 \tand %r3,0xfffffd66\n+ b0:\t57 40 00 00 7e ad be ef \tand %r4,0x7eadbeef\n+ b8:\t5f 56 00 00 00 00 00 00 \tand %r5,%r6\n+ c0:\t67 20 00 00 00 00 02 9a \tlsh %r2,0x29a\n+ c8:\t67 30 00 00 ff ff fd 66 \tlsh %r3,0xfffffd66\n+ d0:\t67 40 00 00 7e ad be ef \tlsh %r4,0x7eadbeef\n+ d8:\t6f 56 00 00 00 00 00 00 \tlsh %r5,%r6\n+ e0:\t77 20 00 00 00 00 02 9a \trsh %r2,0x29a\n+ e8:\t77 30 00 00 ff ff fd 66 \trsh %r3,0xfffffd66\n+ f0:\t77 40 00 00 7e ad be ef \trsh %r4,0x7eadbeef\n+ f8:\t7f 56 00 00 00 00 00 00 \trsh %r5,%r6\n+ 100:\t97 20 00 00 00 00 02 9a \tmod %r2,0x29a\n+ 108:\t97 30 00 00 ff ff fd 66 \tmod %r3,0xfffffd66\n+ 110:\t97 40 00 00 7e ad be ef \tmod %r4,0x7eadbeef\n+ 118:\t9f 56 00 00 00 00 00 00 \tmod %r5,%r6\n+ 120:\ta7 20 00 00 00 00 02 9a \txor %r2,0x29a\n+ 128:\ta7 30 00 00 ff ff fd 66 \txor %r3,0xfffffd66\n+ 130:\ta7 40 00 00 7e ad be ef \txor %r4,0x7eadbeef\n+ 138:\taf 56 00 00 00 00 00 00 \txor %r5,%r6\n+ 140:\tb7 20 00 00 00 00 02 9a \tmov %r2,0x29a\n+ 148:\tb7 30 00 00 ff ff fd 66 \tmov %r3,0xfffffd66\n+ 150:\tb7 40 00 00 7e ad be ef \tmov %r4,0x7eadbeef\n+ 158:\tbf 56 00 00 00 00 00 00 \tmov %r5,%r6\n+ 160:\tc7 20 00 00 00 00 02 9a \tarsh %r2,0x29a\n+ 168:\tc7 30 00 00 ff ff fd 66 \tarsh %r3,0xfffffd66\n+ 170:\tc7 40 00 00 7e ad be ef \tarsh %r4,0x7eadbeef\n+ 178:\tcf 56 00 00 00 00 00 00 \tarsh %r5,%r6\n+ 180:\t8f 23 00 00 00 00 00 00 \tneg %r2,%r3\n+ 188:\td4 90 00 00 00 00 00 10 \tendle %r9,16\n+ 190:\td4 80 00 00 00 00 00 20 \tendle %r8,32\n+ 198:\td4 70 00 00 00 00 00 40 \tendle %r7,64\n+ 1a0:\tdc 60 00 00 00 00 00 10 \tendbe %r6,16\n+ 1a8:\tdc 50 00 00 00 00 00 20 \tendbe %r5,32\n+ 1b0:\tdc 40 00 00 00 00 00 40 \tendbe %r4,64\ndiff --git a/gas/testsuite/gas/bpf/alu-pseudoc.d b/gas/testsuite/gas/bpf/alu-pseudoc.d\nindex df130699b4f..5d69e68a4f0 100644\n--- a/gas/testsuite/gas/bpf/alu-pseudoc.d\n+++ b/gas/testsuite/gas/bpf/alu-pseudoc.d\n@@ -1,5 +1,65 @@\n-#as: --EL\n-#objdump: -dr\n+#as: -EL -mdialect=pseudoc\n+#objdump: -dr -M hex,pseudoc\n #source: alu-pseudoc.s\n-#dump: alu.dump\n-#name: eBPF ALU64 instructions, pseudo-c syntax\n+#name: eBPF ALU instructions, pseudo-c syntax\n+\n+.*: +file format .*bpf.*\n+\n+Disassembly of section .text:\n+\n+0+ <.text>:\n+ 0:\t07 02 00 00 9a 02 00 00 \tr2\\+=0x29a\n+ 8:\t07 03 00 00 66 fd ff ff \tr3\\+=0xfffffd66\n+ 10:\t07 04 00 00 ef be ad 7e \tr4\\+=0x7eadbeef\n+ 18:\t0f 65 00 00 00 00 00 00 \tr5\\+=r6\n+ 20:\t17 02 00 00 9a 02 00 00 \tr2-=0x29a\n+ 28:\t17 03 00 00 66 fd ff ff \tr3-=0xfffffd66\n+ 30:\t17 04 00 00 ef be ad 7e \tr4-=0x7eadbeef\n+ 38:\t1f 65 00 00 00 00 00 00 \tr5-=r6\n+ 40:\t27 02 00 00 9a 02 00 00 \tr2\\*=0x29a\n+ 48:\t27 03 00 00 66 fd ff ff \tr3\\*=0xfffffd66\n+ 50:\t27 04 00 00 ef be ad 7e \tr4\\*=0x7eadbeef\n+ 58:\t2f 65 00 00 00 00 00 00 \tr5\\*=r6\n+ 60:\t37 02 00 00 9a 02 00 00 \tr2/=0x29a\n+ 68:\t37 03 00 00 66 fd ff ff \tr3/=0xfffffd66\n+ 70:\t37 04 00 00 ef be ad 7e \tr4/=0x7eadbeef\n+ 78:\t3f 65 00 00 00 00 00 00 \tr5/=r6\n+ 80:\t47 02 00 00 9a 02 00 00 \tr2|=0x29a\n+ 88:\t47 03 00 00 66 fd ff ff \tr3|=0xfffffd66\n+ 90:\t47 04 00 00 ef be ad 7e \tr4|=0x7eadbeef\n+ 98:\t4f 65 00 00 00 00 00 00 \tr5|=r6\n+ a0:\t57 02 00 00 9a 02 00 00 \tr2&=0x29a\n+ a8:\t57 03 00 00 66 fd ff ff \tr3&=0xfffffd66\n+ b0:\t57 04 00 00 ef be ad 7e \tr4&=0x7eadbeef\n+ b8:\t5f 65 00 00 00 00 00 00 \tr5&=r6\n+ c0:\t67 02 00 00 9a 02 00 00 \tr2<<=0x29a\n+ c8:\t67 03 00 00 66 fd ff ff \tr3<<=0xfffffd66\n+ d0:\t67 04 00 00 ef be ad 7e \tr4<<=0x7eadbeef\n+ d8:\t6f 65 00 00 00 00 00 00 \tr5<<=r6\n+ e0:\t77 02 00 00 9a 02 00 00 \tr2>>=0x29a\n+ e8:\t77 03 00 00 66 fd ff ff \tr3>>=0xfffffd66\n+ f0:\t77 04 00 00 ef be ad 7e \tr4>>=0x7eadbeef\n+ f8:\t7f 65 00 00 00 00 00 00 \tr5>>=r6\n+ 100:\t97 02 00 00 9a 02 00 00 \tr2%=0x29a\n+ 108:\t97 03 00 00 66 fd ff ff \tr3%=0xfffffd66\n+ 110:\t97 04 00 00 ef be ad 7e \tr4%=0x7eadbeef\n+ 118:\t9f 65 00 00 00 00 00 00 \tr5%=r6\n+ 120:\ta7 02 00 00 9a 02 00 00 \tr2\\^=0x29a\n+ 128:\ta7 03 00 00 66 fd ff ff \tr3\\^=0xfffffd66\n+ 130:\ta7 04 00 00 ef be ad 7e \tr4\\^=0x7eadbeef\n+ 138:\taf 65 00 00 00 00 00 00 \tr5\\^=r6\n+ 140:\tb7 02 00 00 9a 02 00 00 \tr2=0x29a\n+ 148:\tb7 03 00 00 66 fd ff ff \tr3=0xfffffd66\n+ 150:\tb7 04 00 00 ef be ad 7e \tr4=0x7eadbeef\n+ 158:\tbf 65 00 00 00 00 00 00 \tr5=r6\n+ 160:\tc7 02 00 00 9a 02 00 00 \tr2 s>>=0x29a\n+ 168:\tc7 03 00 00 66 fd ff ff \tr3 s>>=0xfffffd66\n+ 170:\tc7 04 00 00 ef be ad 7e \tr4 s>>=0x7eadbeef\n+ 178:\tcf 65 00 00 00 00 00 00 \tr5 s>>=r6\n+ 180:\t8f 32 00 00 00 00 00 00 \tr2=-r3\n+ 188:\td4 09 00 00 10 00 00 00 \tr9=le16 r9\n+ 190:\td4 08 00 00 20 00 00 00 \tr8=le32 r8\n+ 198:\td4 07 00 00 40 00 00 00 \tr7=le64 r7\n+ 1a0:\tdc 06 00 00 10 00 00 00 \tr6=be16 r6\n+ 1a8:\tdc 05 00 00 20 00 00 00 \tr5=be32 r5\n+ 1b0:\tdc 04 00 00 40 00 00 00 \tr4=be64 r4\ndiff --git a/gas/testsuite/gas/bpf/alu-pseudoc.s b/gas/testsuite/gas/bpf/alu-pseudoc.s\nindex 0f79929ea0d..a271bef977d 100644\n--- a/gas/testsuite/gas/bpf/alu-pseudoc.s\n+++ b/gas/testsuite/gas/bpf/alu-pseudoc.s\n@@ -48,4 +48,10 @@\n \tr3 s>>= -666\n \tr4 s>>= 2125315823\n \tr5 s>>= r6\n-\tr2 = -r2\n+\tr2 = - r3\n+\tr9 = le16 r9\n+\tr8 = le32 r8\n+\tr7 = le64 r7\n+\tr6 = be16 r6\n+\tr5 = be32 r5\n+\tr4 = be64 r4\ndiff --git a/gas/testsuite/gas/bpf/alu.d b/gas/testsuite/gas/bpf/alu.d\nindex 764ae440d8f..476891b9afd 100644\n--- a/gas/testsuite/gas/bpf/alu.d\n+++ b/gas/testsuite/gas/bpf/alu.d\n@@ -1,5 +1,65 @@\n-#as: --EL\n-#objdump: -dr\n+#as: -EL -mdialect=normal\n+#objdump: -dr -M hex\n #source: alu.s\n-#dump: alu.dump\n-#name: eBPF ALU64 instructions, normal syntax\n+#name: eBPF ALU instructions, normal syntax\n+\n+.*: +file format .*bpf.*\n+\n+Disassembly of section .text:\n+\n+0+ <.text>:\n+ 0:\t07 02 00 00 9a 02 00 00 \tadd %r2,0x29a\n+ 8:\t07 03 00 00 66 fd ff ff \tadd %r3,0xfffffd66\n+ 10:\t07 04 00 00 ef be ad 7e \tadd %r4,0x7eadbeef\n+ 18:\t0f 65 00 00 00 00 00 00 \tadd %r5,%r6\n+ 20:\t17 02 00 00 9a 02 00 00 \tsub %r2,0x29a\n+ 28:\t17 03 00 00 66 fd ff ff \tsub %r3,0xfffffd66\n+ 30:\t17 04 00 00 ef be ad 7e \tsub %r4,0x7eadbeef\n+ 38:\t1f 65 00 00 00 00 00 00 \tsub %r5,%r6\n+ 40:\t27 02 00 00 9a 02 00 00 \tmul %r2,0x29a\n+ 48:\t27 03 00 00 66 fd ff ff \tmul %r3,0xfffffd66\n+ 50:\t27 04 00 00 ef be ad 7e \tmul %r4,0x7eadbeef\n+ 58:\t2f 65 00 00 00 00 00 00 \tmul %r5,%r6\n+ 60:\t37 02 00 00 9a 02 00 00 \tdiv %r2,0x29a\n+ 68:\t37 03 00 00 66 fd ff ff \tdiv %r3,0xfffffd66\n+ 70:\t37 04 00 00 ef be ad 7e \tdiv %r4,0x7eadbeef\n+ 78:\t3f 65 00 00 00 00 00 00 \tdiv %r5,%r6\n+ 80:\t47 02 00 00 9a 02 00 00 \tor %r2,0x29a\n+ 88:\t47 03 00 00 66 fd ff ff \tor %r3,0xfffffd66\n+ 90:\t47 04 00 00 ef be ad 7e \tor %r4,0x7eadbeef\n+ 98:\t4f 65 00 00 00 00 00 00 \tor %r5,%r6\n+ a0:\t57 02 00 00 9a 02 00 00 \tand %r2,0x29a\n+ a8:\t57 03 00 00 66 fd ff ff \tand %r3,0xfffffd66\n+ b0:\t57 04 00 00 ef be ad 7e \tand %r4,0x7eadbeef\n+ b8:\t5f 65 00 00 00 00 00 00 \tand %r5,%r6\n+ c0:\t67 02 00 00 9a 02 00 00 \tlsh %r2,0x29a\n+ c8:\t67 03 00 00 66 fd ff ff \tlsh %r3,0xfffffd66\n+ d0:\t67 04 00 00 ef be ad 7e \tlsh %r4,0x7eadbeef\n+ d8:\t6f 65 00 00 00 00 00 00 \tlsh %r5,%r6\n+ e0:\t77 02 00 00 9a 02 00 00 \trsh %r2,0x29a\n+ e8:\t77 03 00 00 66 fd ff ff \trsh %r3,0xfffffd66\n+ f0:\t77 04 00 00 ef be ad 7e \trsh %r4,0x7eadbeef\n+ f8:\t7f 65 00 00 00 00 00 00 \trsh %r5,%r6\n+ 100:\t97 02 00 00 9a 02 00 00 \tmod %r2,0x29a\n+ 108:\t97 03 00 00 66 fd ff ff \tmod %r3,0xfffffd66\n+ 110:\t97 04 00 00 ef be ad 7e \tmod %r4,0x7eadbeef\n+ 118:\t9f 65 00 00 00 00 00 00 \tmod %r5,%r6\n+ 120:\ta7 02 00 00 9a 02 00 00 \txor %r2,0x29a\n+ 128:\ta7 03 00 00 66 fd ff ff \txor %r3,0xfffffd66\n+ 130:\ta7 04 00 00 ef be ad 7e \txor %r4,0x7eadbeef\n+ 138:\taf 65 00 00 00 00 00 00 \txor %r5,%r6\n+ 140:\tb7 02 00 00 9a 02 00 00 \tmov %r2,0x29a\n+ 148:\tb7 03 00 00 66 fd ff ff \tmov %r3,0xfffffd66\n+ 150:\tb7 04 00 00 ef be ad 7e \tmov %r4,0x7eadbeef\n+ 158:\tbf 65 00 00 00 00 00 00 \tmov %r5,%r6\n+ 160:\tc7 02 00 00 9a 02 00 00 \tarsh %r2,0x29a\n+ 168:\tc7 03 00 00 66 fd ff ff \tarsh %r3,0xfffffd66\n+ 170:\tc7 04 00 00 ef be ad 7e \tarsh %r4,0x7eadbeef\n+ 178:\tcf 65 00 00 00 00 00 00 \tarsh %r5,%r6\n+ 180:\t8f 32 00 00 00 00 00 00 \tneg %r2,%r3\n+ 188:\td4 09 00 00 10 00 00 00 \tendle %r9,16\n+ 190:\td4 08 00 00 20 00 00 00 \tendle %r8,32\n+ 198:\td4 07 00 00 40 00 00 00 \tendle %r7,64\n+ 1a0:\tdc 06 00 00 10 00 00 00 \tendbe %r6,16\n+ 1a8:\tdc 05 00 00 20 00 00 00 \tendbe %r5,32\n+ 1b0:\tdc 04 00 00 40 00 00 00 \tendbe %r4,64\ndiff --git a/gas/testsuite/gas/bpf/alu.s b/gas/testsuite/gas/bpf/alu.s\nindex 18e60d5eaed..bb3f9265200 100644\n--- a/gas/testsuite/gas/bpf/alu.s\n+++ b/gas/testsuite/gas/bpf/alu.s\n@@ -48,4 +48,10 @@\n arsh\t%r3, -666\n arsh\t%r4, 0x7eadbeef\n arsh\t%r5, %r6\n- neg %r2\n+ neg %r2, %r3\n+\tendle\t%r9,16\n+ endle\t%r8,32\n+ endle\t%r7,64\n+ endbe\t%r6,16\n+ endbe\t%r5,32\n+ endbe\t%r4,64\ndiff --git a/gas/testsuite/gas/bpf/alu32-be-pseudoc.d b/gas/testsuite/gas/bpf/alu32-be-pseudoc.d\nindex 396d7d40603..6daad3b6926 100644\n--- a/gas/testsuite/gas/bpf/alu32-be-pseudoc.d\n+++ b/gas/testsuite/gas/bpf/alu32-be-pseudoc.d\n@@ -1,5 +1,59 @@\n-#as: --EB\n-#objdump: -dr\n+#as: -EB -mdialect=pseudoc\n+#objdump: -dr -M hex,pseudoc\n #source: alu32-pseudoc.s\n-#dump: alu32-be.dump\n-#name: eBPF ALU instructions, big-endian, pseudo-c syntax\n+#name: eBPF ALU32 instructions, big-endian, pseudo-c syntax\n+\n+.*: +file format .*bpf.*\n+\n+Disassembly of section .text:\n+\n+0+ <.text>:\n+ 0:\t04 20 00 00 00 00 02 9a \tw2\\+=0x29a\n+ 8:\t04 30 00 00 ff ff fd 66 \tw3\\+=0xfffffd66\n+ 10:\t04 40 00 00 7e ad be ef \tw4\\+=0x7eadbeef\n+ 18:\t0c 56 00 00 00 00 00 00 \tw5\\+=w6\n+ 20:\t14 20 00 00 00 00 02 9a \tw2-=0x29a\n+ 28:\t14 30 00 00 ff ff fd 66 \tw3-=0xfffffd66\n+ 30:\t14 40 00 00 7e ad be ef \tw4-=0x7eadbeef\n+ 38:\t1c 56 00 00 00 00 00 00 \tw5-=w6\n+ 40:\t24 20 00 00 00 00 02 9a \tw2\\*=0x29a\n+ 48:\t24 30 00 00 ff ff fd 66 \tw3\\*=0xfffffd66\n+ 50:\t24 40 00 00 7e ad be ef \tw4\\*=0x7eadbeef\n+ 58:\t2c 56 00 00 00 00 00 00 \tw5\\*=w6\n+ 60:\t34 20 00 00 00 00 02 9a \tw2/=0x29a\n+ 68:\t34 30 00 00 ff ff fd 66 \tw3/=0xfffffd66\n+ 70:\t34 40 00 00 7e ad be ef \tw4/=0x7eadbeef\n+ 78:\t3c 56 00 00 00 00 00 00 \tw5/=w6\n+ 80:\t44 20 00 00 00 00 02 9a \tw2|=0x29a\n+ 88:\t44 30 00 00 ff ff fd 66 \tw3|=0xfffffd66\n+ 90:\t44 40 00 00 7e ad be ef \tw4|=0x7eadbeef\n+ 98:\t4c 56 00 00 00 00 00 00 \tw5|=w6\n+ a0:\t54 20 00 00 00 00 02 9a \tw2&=0x29a\n+ a8:\t54 30 00 00 ff ff fd 66 \tw3&=0xfffffd66\n+ b0:\t54 40 00 00 7e ad be ef \tw4&=0x7eadbeef\n+ b8:\t5c 56 00 00 00 00 00 00 \tw5&=w6\n+ c0:\t64 20 00 00 00 00 02 9a \tw2<<=0x29a\n+ c8:\t64 30 00 00 ff ff fd 66 \tw3<<=0xfffffd66\n+ d0:\t64 40 00 00 7e ad be ef \tw4<<=0x7eadbeef\n+ d8:\t6c 56 00 00 00 00 00 00 \tw5<<=w6\n+ e0:\t74 20 00 00 00 00 02 9a \tw2>>=0x29a\n+ e8:\t74 30 00 00 ff ff fd 66 \tw3>>=0xfffffd66\n+ f0:\t74 40 00 00 7e ad be ef \tw4>>=0x7eadbeef\n+ f8:\t7c 56 00 00 00 00 00 00 \tw5>>=w6\n+ 100:\t94 20 00 00 00 00 02 9a \tw2%=0x29a\n+ 108:\t94 30 00 00 ff ff fd 66 \tw3%=0xfffffd66\n+ 110:\t94 40 00 00 7e ad be ef \tw4%=0x7eadbeef\n+ 118:\t9c 56 00 00 00 00 00 00 \tw5%=w6\n+ 120:\ta4 20 00 00 00 00 02 9a \tw2\\^=0x29a\n+ 128:\ta4 30 00 00 ff ff fd 66 \tw3\\^=0xfffffd66\n+ 130:\ta4 40 00 00 7e ad be ef \tw4\\^=0x7eadbeef\n+ 138:\tac 56 00 00 00 00 00 00 \tw5\\^=w6\n+ 140:\tb4 20 00 00 00 00 02 9a \tw2=0x29a\n+ 148:\tb4 30 00 00 ff ff fd 66 \tw3=0xfffffd66\n+ 150:\tb4 40 00 00 7e ad be ef \tw4=0x7eadbeef\n+ 158:\tbc 56 00 00 00 00 00 00 \tw5=w6\n+ 160:\tc4 20 00 00 00 00 02 9a \tw2 s>>=0x29a\n+ 168:\tc4 30 00 00 ff ff fd 66 \tw3 s>>=0xfffffd66\n+ 170:\tc4 40 00 00 7e ad be ef \tw4 s>>=0x7eadbeef\n+ 178:\tcc 56 00 00 00 00 00 00 \tw5 s>>=w6\n+ 180:\t8c 23 00 00 00 00 00 00 \tw2=-w3\ndiff --git a/gas/testsuite/gas/bpf/alu32-be.d b/gas/testsuite/gas/bpf/alu32-be.d\nindex 6ed9e556bf4..6de8f0660d8 100644\n--- a/gas/testsuite/gas/bpf/alu32-be.d\n+++ b/gas/testsuite/gas/bpf/alu32-be.d\n@@ -1,5 +1,59 @@\n-#as: --EB\n-#objdump: -dr\n-#source: alu32-pseudoc.s\n-#dump: alu32-be.dump\n-#name: eBPF ALU instructions, big-endian, normal syntax\n+#as: -EB -mdialect=normal\n+#objdump: -dr -M hex\n+#source: alu32.s\n+#name: eBPF ALU32 instructions, big-endian, normal syntax\n+\n+.*: +file format .*bpf.*\n+\n+Disassembly of section .text:\n+\n+0+ <.text>:\n+ 0:\t04 20 00 00 00 00 02 9a \tadd32 %r2,0x29a\n+ 8:\t04 30 00 00 ff ff fd 66 \tadd32 %r3,0xfffffd66\n+ 10:\t04 40 00 00 7e ad be ef \tadd32 %r4,0x7eadbeef\n+ 18:\t0c 56 00 00 00 00 00 00 \tadd32 %r5,%r6\n+ 20:\t14 20 00 00 00 00 02 9a \tsub32 %r2,0x29a\n+ 28:\t14 30 00 00 ff ff fd 66 \tsub32 %r3,0xfffffd66\n+ 30:\t14 40 00 00 7e ad be ef \tsub32 %r4,0x7eadbeef\n+ 38:\t1c 56 00 00 00 00 00 00 \tsub32 %r5,%r6\n+ 40:\t24 20 00 00 00 00 02 9a \tmul32 %r2,0x29a\n+ 48:\t24 30 00 00 ff ff fd 66 \tmul32 %r3,0xfffffd66\n+ 50:\t24 40 00 00 7e ad be ef \tmul32 %r4,0x7eadbeef\n+ 58:\t2c 56 00 00 00 00 00 00 \tmul32 %r5,%r6\n+ 60:\t34 20 00 00 00 00 02 9a \tdiv32 %r2,0x29a\n+ 68:\t34 30 00 00 ff ff fd 66 \tdiv32 %r3,0xfffffd66\n+ 70:\t34 40 00 00 7e ad be ef \tdiv32 %r4,0x7eadbeef\n+ 78:\t3c 56 00 00 00 00 00 00 \tdiv32 %r5,%r6\n+ 80:\t44 20 00 00 00 00 02 9a \tor32 %r2,0x29a\n+ 88:\t44 30 00 00 ff ff fd 66 \tor32 %r3,0xfffffd66\n+ 90:\t44 40 00 00 7e ad be ef \tor32 %r4,0x7eadbeef\n+ 98:\t4c 56 00 00 00 00 00 00 \tor32 %r5,%r6\n+ a0:\t54 20 00 00 00 00 02 9a \tand32 %r2,0x29a\n+ a8:\t54 30 00 00 ff ff fd 66 \tand32 %r3,0xfffffd66\n+ b0:\t54 40 00 00 7e ad be ef \tand32 %r4,0x7eadbeef\n+ b8:\t5c 56 00 00 00 00 00 00 \tand32 %r5,%r6\n+ c0:\t64 20 00 00 00 00 02 9a \tlsh32 %r2,0x29a\n+ c8:\t64 30 00 00 ff ff fd 66 \tlsh32 %r3,0xfffffd66\n+ d0:\t64 40 00 00 7e ad be ef \tlsh32 %r4,0x7eadbeef\n+ d8:\t6c 56 00 00 00 00 00 00 \tlsh32 %r5,%r6\n+ e0:\t74 20 00 00 00 00 02 9a \trsh32 %r2,0x29a\n+ e8:\t74 30 00 00 ff ff fd 66 \trsh32 %r3,0xfffffd66\n+ f0:\t74 40 00 00 7e ad be ef \trsh32 %r4,0x7eadbeef\n+ f8:\t7c 56 00 00 00 00 00 00 \trsh32 %r5,%r6\n+ 100:\t94 20 00 00 00 00 02 9a \tmod32 %r2,0x29a\n+ 108:\t94 30 00 00 ff ff fd 66 \tmod32 %r3,0xfffffd66\n+ 110:\t94 40 00 00 7e ad be ef \tmod32 %r4,0x7eadbeef\n+ 118:\t9c 56 00 00 00 00 00 00 \tmod32 %r5,%r6\n+ 120:\ta4 20 00 00 00 00 02 9a \txor32 %r2,0x29a\n+ 128:\ta4 30 00 00 ff ff fd 66 \txor32 %r3,0xfffffd66\n+ 130:\ta4 40 00 00 7e ad be ef \txor32 %r4,0x7eadbeef\n+ 138:\tac 56 00 00 00 00 00 00 \txor32 %r5,%r6\n+ 140:\tb4 20 00 00 00 00 02 9a \tmov32 %r2,0x29a\n+ 148:\tb4 30 00 00 ff ff fd 66 \tmov32 %r3,0xfffffd66\n+ 150:\tb4 40 00 00 7e ad be ef \tmov32 %r4,0x7eadbeef\n+ 158:\tbc 56 00 00 00 00 00 00 \tmov32 %r5,%r6\n+ 160:\tc4 20 00 00 00 00 02 9a \tarsh32 %r2,0x29a\n+ 168:\tc4 30 00 00 ff ff fd 66 \tarsh32 %r3,0xfffffd66\n+ 170:\tc4 40 00 00 7e ad be ef \tarsh32 %r4,0x7eadbeef\n+ 178:\tcc 56 00 00 00 00 00 00 \tarsh32 %r5,%r6\n+ 180:\t8c 23 00 00 00 00 00 00 \tneg32 %r2,%r3\ndiff --git a/gas/testsuite/gas/bpf/alu32-pseudoc.d b/gas/testsuite/gas/bpf/alu32-pseudoc.d\nindex 98b99215b27..f339c808d26 100644\n--- a/gas/testsuite/gas/bpf/alu32-pseudoc.d\n+++ b/gas/testsuite/gas/bpf/alu32-pseudoc.d\n@@ -1,5 +1,59 @@\n-#as: --EL\n-#objdump: -dr\n+#as: -EL -mdialect=pseudoc\n+#objdump: -dr -M hex,pseudoc\n #source: alu32-pseudoc.s\n-#dump: alu32.dump\n-#name: eBPF ALU instructions, pseudo-c syntax\n+#name: eBPF ALU32 instructions, pseudo-c syntax\n+\n+.*: +file format .*bpf.*\n+\n+Disassembly of section .text:\n+\n+0+ <.text>:\n+ 0:\t04 02 00 00 9a 02 00 00 \tw2\\+=0x29a\n+ 8:\t04 03 00 00 66 fd ff ff \tw3\\+=0xfffffd66\n+ 10:\t04 04 00 00 ef be ad 7e \tw4\\+=0x7eadbeef\n+ 18:\t0c 65 00 00 00 00 00 00 \tw5\\+=w6\n+ 20:\t14 02 00 00 9a 02 00 00 \tw2-=0x29a\n+ 28:\t14 03 00 00 66 fd ff ff \tw3-=0xfffffd66\n+ 30:\t14 04 00 00 ef be ad 7e \tw4-=0x7eadbeef\n+ 38:\t1c 65 00 00 00 00 00 00 \tw5-=w6\n+ 40:\t24 02 00 00 9a 02 00 00 \tw2\\*=0x29a\n+ 48:\t24 03 00 00 66 fd ff ff \tw3\\*=0xfffffd66\n+ 50:\t24 04 00 00 ef be ad 7e \tw4\\*=0x7eadbeef\n+ 58:\t2c 65 00 00 00 00 00 00 \tw5\\*=w6\n+ 60:\t34 02 00 00 9a 02 00 00 \tw2/=0x29a\n+ 68:\t34 03 00 00 66 fd ff ff \tw3/=0xfffffd66\n+ 70:\t34 04 00 00 ef be ad 7e \tw4/=0x7eadbeef\n+ 78:\t3c 65 00 00 00 00 00 00 \tw5/=w6\n+ 80:\t44 02 00 00 9a 02 00 00 \tw2|=0x29a\n+ 88:\t44 03 00 00 66 fd ff ff \tw3|=0xfffffd66\n+ 90:\t44 04 00 00 ef be ad 7e \tw4|=0x7eadbeef\n+ 98:\t4c 65 00 00 00 00 00 00 \tw5|=w6\n+ a0:\t54 02 00 00 9a 02 00 00 \tw2&=0x29a\n+ a8:\t54 03 00 00 66 fd ff ff \tw3&=0xfffffd66\n+ b0:\t54 04 00 00 ef be ad 7e \tw4&=0x7eadbeef\n+ b8:\t5c 65 00 00 00 00 00 00 \tw5&=w6\n+ c0:\t64 02 00 00 9a 02 00 00 \tw2<<=0x29a\n+ c8:\t64 03 00 00 66 fd ff ff \tw3<<=0xfffffd66\n+ d0:\t64 04 00 00 ef be ad 7e \tw4<<=0x7eadbeef\n+ d8:\t6c 65 00 00 00 00 00 00 \tw5<<=w6\n+ e0:\t74 02 00 00 9a 02 00 00 \tw2>>=0x29a\n+ e8:\t74 03 00 00 66 fd ff ff \tw3>>=0xfffffd66\n+ f0:\t74 04 00 00 ef be ad 7e \tw4>>=0x7eadbeef\n+ f8:\t7c 65 00 00 00 00 00 00 \tw5>>=w6\n+ 100:\t94 02 00 00 9a 02 00 00 \tw2%=0x29a\n+ 108:\t94 03 00 00 66 fd ff ff \tw3%=0xfffffd66\n+ 110:\t94 04 00 00 ef be ad 7e \tw4%=0x7eadbeef\n+ 118:\t9c 65 00 00 00 00 00 00 \tw5%=w6\n+ 120:\ta4 02 00 00 9a 02 00 00 \tw2\\^=0x29a\n+ 128:\ta4 03 00 00 66 fd ff ff \tw3\\^=0xfffffd66\n+ 130:\ta4 04 00 00 ef be ad 7e \tw4\\^=0x7eadbeef\n+ 138:\tac 65 00 00 00 00 00 00 \tw5\\^=w6\n+ 140:\tb4 02 00 00 9a 02 00 00 \tw2=0x29a\n+ 148:\tb4 03 00 00 66 fd ff ff \tw3=0xfffffd66\n+ 150:\tb4 04 00 00 ef be ad 7e \tw4=0x7eadbeef\n+ 158:\tbc 65 00 00 00 00 00 00 \tw5=w6\n+ 160:\tc4 02 00 00 9a 02 00 00 \tw2 s>>=0x29a\n+ 168:\tc4 03 00 00 66 fd ff ff \tw3 s>>=0xfffffd66\n+ 170:\tc4 04 00 00 ef be ad 7e \tw4 s>>=0x7eadbeef\n+ 178:\tcc 65 00 00 00 00 00 00 \tw5 s>>=w6\n+ 180:\t8c 32 00 00 00 00 00 00 \tw2=-w3\ndiff --git a/gas/testsuite/gas/bpf/alu32-pseudoc.s b/gas/testsuite/gas/bpf/alu32-pseudoc.s\nindex a29f6ea0336..0a0d41fdf46 100644\n--- a/gas/testsuite/gas/bpf/alu32-pseudoc.s\n+++ b/gas/testsuite/gas/bpf/alu32-pseudoc.s\n@@ -1,16 +1,16 @@\n # Tests for the ALU eBPF pseudo-C instructions\n .text\n-\tW2 += 666\n-\tW3 += -666\n-\tW4 += 2125315823\n-\tW5 += w6\n-\tW2 -= 666\n-\tW3 -= -666\n-\tW4 -= 2125315823\n-\tW5 -= w6\n-\tW2 *= 666\n-\tW3 *= -666\n-\tW4 *= 2125315823\n+\tw2 += 666\n+\tw3 += -666\n+\tw4 += 2125315823\n+\tw5 += w6\n+\tw2 -= 666\n+\tw3 -= -666\n+\tw4 -= 2125315823\n+\tw5 -= w6\n+\tw2 *= 666\n+\tw3 *= -666\n+\tw4 *= 2125315823\n \tw5 *= w6\n \tw2 /= 666\n \tw3 /= -666\n@@ -48,10 +48,4 @@\n \tw3 s>>= -666\n \tw4 s>>= 2125315823\n \tw5 s>>= w6\n-\tw2 = -w2\n-\tr9 = le16 r9\n-\tr8 = le32 r8\n-\tr7 = le64 r7\n-\tr6 = be16 r6\n-\tr5 = be32 r5\n-\tr4 = be64 r4\n+\tw2 = - w3\ndiff --git a/gas/testsuite/gas/bpf/alu32.d b/gas/testsuite/gas/bpf/alu32.d\nindex 87efc20ba30..712d1c7328e 100644\n--- a/gas/testsuite/gas/bpf/alu32.d\n+++ b/gas/testsuite/gas/bpf/alu32.d\n@@ -1,5 +1,59 @@\n-#as: --EL\n-#objdump: -dr\n+#as: -EL -mdialect=normal\n+#objdump: -dr -M hex\n #source: alu32.s\n-#dump: alu32.dump\n-#name: eBPF ALU instructions, normal syntax\n+#name: eBPF ALU32 instructions, normal syntax\n+\n+.*: +file format .*bpf.*\n+\n+Disassembly of section .text:\n+\n+0+ <.text>:\n+ 0:\t04 02 00 00 9a 02 00 00 \tadd32 %r2,0x29a\n+ 8:\t04 03 00 00 66 fd ff ff \tadd32 %r3,0xfffffd66\n+ 10:\t04 04 00 00 ef be ad 7e \tadd32 %r4,0x7eadbeef\n+ 18:\t0c 65 00 00 00 00 00 00 \tadd32 %r5,%r6\n+ 20:\t14 02 00 00 9a 02 00 00 \tsub32 %r2,0x29a\n+ 28:\t14 03 00 00 66 fd ff ff \tsub32 %r3,0xfffffd66\n+ 30:\t14 04 00 00 ef be ad 7e \tsub32 %r4,0x7eadbeef\n+ 38:\t1c 65 00 00 00 00 00 00 \tsub32 %r5,%r6\n+ 40:\t24 02 00 00 9a 02 00 00 \tmul32 %r2,0x29a\n+ 48:\t24 03 00 00 66 fd ff ff \tmul32 %r3,0xfffffd66\n+ 50:\t24 04 00 00 ef be ad 7e \tmul32 %r4,0x7eadbeef\n+ 58:\t2c 65 00 00 00 00 00 00 \tmul32 %r5,%r6\n+ 60:\t34 02 00 00 9a 02 00 00 \tdiv32 %r2,0x29a\n+ 68:\t34 03 00 00 66 fd ff ff \tdiv32 %r3,0xfffffd66\n+ 70:\t34 04 00 00 ef be ad 7e \tdiv32 %r4,0x7eadbeef\n+ 78:\t3c 65 00 00 00 00 00 00 \tdiv32 %r5,%r6\n+ 80:\t44 02 00 00 9a 02 00 00 \tor32 %r2,0x29a\n+ 88:\t44 03 00 00 66 fd ff ff \tor32 %r3,0xfffffd66\n+ 90:\t44 04 00 00 ef be ad 7e \tor32 %r4,0x7eadbeef\n+ 98:\t4c 65 00 00 00 00 00 00 \tor32 %r5,%r6\n+ a0:\t54 02 00 00 9a 02 00 00 \tand32 %r2,0x29a\n+ a8:\t54 03 00 00 66 fd ff ff \tand32 %r3,0xfffffd66\n+ b0:\t54 04 00 00 ef be ad 7e \tand32 %r4,0x7eadbeef\n+ b8:\t5c 65 00 00 00 00 00 00 \tand32 %r5,%r6\n+ c0:\t64 02 00 00 9a 02 00 00 \tlsh32 %r2,0x29a\n+ c8:\t64 03 00 00 66 fd ff ff \tlsh32 %r3,0xfffffd66\n+ d0:\t64 04 00 00 ef be ad 7e \tlsh32 %r4,0x7eadbeef\n+ d8:\t6c 65 00 00 00 00 00 00 \tlsh32 %r5,%r6\n+ e0:\t74 02 00 00 9a 02 00 00 \trsh32 %r2,0x29a\n+ e8:\t74 03 00 00 66 fd ff ff \trsh32 %r3,0xfffffd66\n+ f0:\t74 04 00 00 ef be ad 7e \trsh32 %r4,0x7eadbeef\n+ f8:\t7c 65 00 00 00 00 00 00 \trsh32 %r5,%r6\n+ 100:\t94 02 00 00 9a 02 00 00 \tmod32 %r2,0x29a\n+ 108:\t94 03 00 00 66 fd ff ff \tmod32 %r3,0xfffffd66\n+ 110:\t94 04 00 00 ef be ad 7e \tmod32 %r4,0x7eadbeef\n+ 118:\t9c 65 00 00 00 00 00 00 \tmod32 %r5,%r6\n+ 120:\ta4 02 00 00 9a 02 00 00 \txor32 %r2,0x29a\n+ 128:\ta4 03 00 00 66 fd ff ff \txor32 %r3,0xfffffd66\n+ 130:\ta4 04 00 00 ef be ad 7e \txor32 %r4,0x7eadbeef\n+ 138:\tac 65 00 00 00 00 00 00 \txor32 %r5,%r6\n+ 140:\tb4 02 00 00 9a 02 00 00 \tmov32 %r2,0x29a\n+ 148:\tb4 03 00 00 66 fd ff ff \tmov32 %r3,0xfffffd66\n+ 150:\tb4 04 00 00 ef be ad 7e \tmov32 %r4,0x7eadbeef\n+ 158:\tbc 65 00 00 00 00 00 00 \tmov32 %r5,%r6\n+ 160:\tc4 02 00 00 9a 02 00 00 \tarsh32 %r2,0x29a\n+ 168:\tc4 03 00 00 66 fd ff ff \tarsh32 %r3,0xfffffd66\n+ 170:\tc4 04 00 00 ef be ad 7e \tarsh32 %r4,0x7eadbeef\n+ 178:\tcc 65 00 00 00 00 00 00 \tarsh32 %r5,%r6\n+ 180:\t8c 32 00 00 00 00 00 00 \tneg32 %r2,%r3\ndiff --git a/gas/testsuite/gas/bpf/alu32.s b/gas/testsuite/gas/bpf/alu32.s\nindex 7b6f014e8be..f43ea4a4d23 100644\n--- a/gas/testsuite/gas/bpf/alu32.s\n+++ b/gas/testsuite/gas/bpf/alu32.s\n@@ -48,10 +48,4 @@\n arsh32\t%r3, -666\n arsh32\t%r4, 0x7eadbeef\n arsh32\t%r5, %r6\n- neg32\t%r2\n-\tendle\t%r9,16\n- endle\t%r8,32\n- endle\t%r7,64\n- endbe\t%r6,16\n- endbe\t%r5,32\n- endbe\t%r4,64\n+ neg32\t%r2, %r3\ndiff --git a/gas/testsuite/gas/bpf/atomic-be-pseudoc.d b/gas/testsuite/gas/bpf/atomic-be-pseudoc.d\nnew file mode 100644\nindex 00000000000..a57322e49d9\n--- /dev/null\n+++ b/gas/testsuite/gas/bpf/atomic-be-pseudoc.d\n@@ -0,0 +1,12 @@\n+#as: -EB -mdialect=pseudoc\n+#objdump: -dr -M hex,pseudoc\n+#source: atomic-pseudoc.s\n+#name: eBPF atomic instructions, pseudoc syntax, big endian\n+\n+.*: +file format .*bpf.*\n+\n+Disassembly of section .text:\n+\n+0+ <.text>:\n+ 0:\tdb 12 1e ef 00 00 00 00 \t\\*\\(u64\\*\\)\\(r1\\+0x1eef\\)\\+=r2\n+ 8:\tc3 12 1e ef 00 00 00 00 \t\\*\\(u32\\*\\)\\(r1\\+0x1eef\\)\\+=r2\ndiff --git a/gas/testsuite/gas/bpf/atomic-be.d b/gas/testsuite/gas/bpf/atomic-be.d\nindex b252571e5fd..fa81d8f6ffb 100644\n--- a/gas/testsuite/gas/bpf/atomic-be.d\n+++ b/gas/testsuite/gas/bpf/atomic-be.d\n@@ -1,7 +1,6 @@\n-#as: --EB\n+#as: -EB -mdialect=normal\n #source: atomic.s\n-#source: atomic-pseudoc.s\n-#objdump: -dr\n+#objdump: -dr -M hex,v1\n #name: eBPF atomic instructions, big endian\n \n .*: +file format .*bpf.*\ndiff --git a/gas/testsuite/gas/bpf/atomic-pseudoc.d b/gas/testsuite/gas/bpf/atomic-pseudoc.d\nindex 3b0e5c567be..3aafd47e0d8 100644\n--- a/gas/testsuite/gas/bpf/atomic-pseudoc.d\n+++ b/gas/testsuite/gas/bpf/atomic-pseudoc.d\n@@ -1,5 +1,12 @@\n-#as: --EL\n-#objdump: -dr\n+#as: -EL -mdialect=pseudoc\n+#objdump: -dr -M hex,pseudoc\n #source: atomic-pseudoc.s\n-#dump: atomic.dump\n-#name: eBPF atomic instructions, normal syntax\n+#name: eBPF atomic instructions, pseudoc syntax\n+\n+.*: +file format .*bpf.*\n+\n+Disassembly of section .text:\n+\n+0+ <.text>:\n+ 0:\tdb 21 ef 1e 00 00 00 00 \t\\*\\(u64\\*\\)\\(r1\\+0x1eef\\)\\+=r2\n+ 8:\tc3 21 ef 1e 00 00 00 00 \t\\*\\(u32\\*\\)\\(r1\\+0x1eef\\)\\+=r2\ndiff --git a/gas/testsuite/gas/bpf/atomic-pseudoc.s b/gas/testsuite/gas/bpf/atomic-pseudoc.s\nindex 1a4f218ccb7..ac73cadf999 100644\n--- a/gas/testsuite/gas/bpf/atomic-pseudoc.s\n+++ b/gas/testsuite/gas/bpf/atomic-pseudoc.s\n@@ -1,4 +1,4 @@\n # Test for eBPF ADDW and ADDDW pseudo-C instructions\n .text\n-\tlock *(u64 *)(r1 + 7919) += r2\n-\tlock *(u32 *)(r1 + 7919) += r2\n+\t*(u64 *)(r1 + 7919) += r2\n+\t*(u32 *)(r1 + 7919) += r2\ndiff --git a/gas/testsuite/gas/bpf/atomic.d b/gas/testsuite/gas/bpf/atomic.d\nindex c48ba9aabda..0a27cae0019 100644\n--- a/gas/testsuite/gas/bpf/atomic.d\n+++ b/gas/testsuite/gas/bpf/atomic.d\n@@ -1,5 +1,12 @@\n-#as: --EL\n-#objdump: -dr\n+#as: -EL -mdialect=normal\n+#objdump: -dr -M hex\n #source: atomic.s\n-#dump: atomic.dump\n #name: eBPF atomic instructions, normal syntax\n+\n+.*: +file format .*bpf.*\n+\n+Disassembly of section .text:\n+\n+0+ <.text>:\n+ 0:\tdb 21 ef 1e 00 00 00 00 \taadd \\[%r1\\+0x1eef\\],%r2\n+ 8:\tc3 21 ef 1e 00 00 00 00 \taadd32 \\[%r1\\+0x1eef\\],%r2\ndiff --git a/gas/testsuite/gas/bpf/atomic.s b/gas/testsuite/gas/bpf/atomic.s\nindex 0119b24c8bb..4669f4adf04 100644\n--- a/gas/testsuite/gas/bpf/atomic.s\n+++ b/gas/testsuite/gas/bpf/atomic.s\n@@ -1,5 +1,5 @@\n # Test for eBPF ADDW and ADDDW instructions\n .text\n- xadddw\t[%r1+0x1eef], %r2\n- xaddw\t[%r1+0x1eef], %r2\n+ aadd\t[%r1+0x1eef], %r2\n+ aadd32\t[%r1+0x1eef], %r2\n \ndiff --git a/gas/testsuite/gas/bpf/bpf.exp b/gas/testsuite/gas/bpf/bpf.exp\nindex 5d91805f478..adf413f834c 100644\n--- a/gas/testsuite/gas/bpf/bpf.exp\n+++ b/gas/testsuite/gas/bpf/bpf.exp\n@@ -18,6 +18,10 @@\n # Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. \n \n if {[istarget bpf*-*-*]} {\n+ # Little-endian BPF tests\n+ run_dump_test call\n+ run_dump_test exit\n+ run_dump_test data\n run_dump_test lddw\n run_dump_test lddw-pseudoc\n run_dump_test alu\n@@ -30,13 +34,15 @@ if {[istarget bpf*-*-*]} {\n run_dump_test jump-pseudoc\n run_dump_test jump32\n run_dump_test jump32-pseudoc\n- run_dump_test call\n- run_dump_test exit\n run_dump_test atomic\n run_dump_test atomic-pseudoc\n- run_dump_test data\n- run_dump_test pseudoc-normal\n+ run_dump_test indcall-1\n+ run_dump_test indcall-1-pseudoc\n \n+ # Big-endian BPF tests\n+ run_dump_test call-be\n+ run_dump_test exit-be\n+ run_dump_test data-be\n run_dump_test lddw-be\n run_dump_test lddw-be-pseudoc\n run_dump_test alu-be\n@@ -44,17 +50,11 @@ if {[istarget bpf*-*-*]} {\n run_dump_test alu32-be\n run_dump_test alu32-be-pseudoc\n run_dump_test mem-be\n+ run_dump_test mem-be-pseudoc\n run_dump_test jump-be\n- run_dump_test call-be\n- run_dump_test exit-be\n+ run_dump_test jump-be-pseudoc\n+ run_dump_test jump32-be\n+ run_dump_test jump32-be-pseudoc\n run_dump_test atomic-be\n- run_dump_test data-be\n- run_dump_test pseudoc-normal-be\n-\n- run_dump_test indcall-1\n- run_dump_test indcall-1-pseudoc\n- run_list_test indcall-bad-1\n-\n- run_dump_test alu-xbpf\n- run_dump_test alu32-xbpf\n+ run_dump_test atomic-be-pseudoc\n }\ndiff --git a/gas/testsuite/gas/bpf/call-be.d b/gas/testsuite/gas/bpf/call-be.d\nindex bd3b50f36b2..55e4e700ab4 100644\n--- a/gas/testsuite/gas/bpf/call-be.d\n+++ b/gas/testsuite/gas/bpf/call-be.d\n@@ -1,6 +1,6 @@\n-#as: --EB\n+#as: -EB -mdialect=normal\n #source: call.s\n-#objdump: -dr\n+#objdump: -dr -M dec\n #name: eBPF CALL instruction, big endian\n \n .*: +file format .*bpf.*\ndiff --git a/gas/testsuite/gas/bpf/call.d b/gas/testsuite/gas/bpf/call.d\nindex daefbd08022..a85cb7f58ab 100644\n--- a/gas/testsuite/gas/bpf/call.d\n+++ b/gas/testsuite/gas/bpf/call.d\n@@ -1,5 +1,5 @@\n-#as: --EL\n-#objdump: -dr\n+#as: -EL -mdialect=normal\n+#objdump: -dr -M dec\n #name: eBPF CALL instruction\n \n .*: +file format .*bpf.*\ndiff --git a/gas/testsuite/gas/bpf/data-be.d b/gas/testsuite/gas/bpf/data-be.d\nindex 010f08f2508..3a8b68bd1d2 100644\n--- a/gas/testsuite/gas/bpf/data-be.d\n+++ b/gas/testsuite/gas/bpf/data-be.d\n@@ -1,4 +1,4 @@\n-#as: --EB\n+#as: -EB -mdialect=normal\n #source: data.s\n #objdump: -s -j .data\n #name: eBPF data directives, big endian\ndiff --git a/gas/testsuite/gas/bpf/data.d b/gas/testsuite/gas/bpf/data.d\nindex 6824e8b8b5a..9fa108b6542 100644\n--- a/gas/testsuite/gas/bpf/data.d\n+++ b/gas/testsuite/gas/bpf/data.d\n@@ -1,4 +1,4 @@\n-#as: --EL\n+#as: -EL -mdialect=normal\n #objdump: -s -j .data\n #name: eBPF data directives\n \ndiff --git a/gas/testsuite/gas/bpf/exit-be.d b/gas/testsuite/gas/bpf/exit-be.d\nindex d3b88c7373a..b83af3eacab 100644\n--- a/gas/testsuite/gas/bpf/exit-be.d\n+++ b/gas/testsuite/gas/bpf/exit-be.d\n@@ -1,6 +1,6 @@\n-#as: --EB\n+#as: -EB -mdialect=normal\n #source: exit.s\n-#objdump: -dr\n+#objdump: -dr -M hex\n #name: eBPF EXIT instruction, big endian\n \n .*: +file format .*bpf.*\ndiff --git a/gas/testsuite/gas/bpf/exit.d b/gas/testsuite/gas/bpf/exit.d\nindex 87bc91b2d2e..68ef9020185 100644\n--- a/gas/testsuite/gas/bpf/exit.d\n+++ b/gas/testsuite/gas/bpf/exit.d\n@@ -1,5 +1,5 @@\n-#as: --EL\n-#objdump: -dr\n+#as: -EL -mdialect=normal\n+#objdump: -dr -M hex\n #name: eBPF EXIT instruction\n \n .*: +file format .*bpf.*\ndiff --git a/gas/testsuite/gas/bpf/indcall-1-pseudoc.d b/gas/testsuite/gas/bpf/indcall-1-pseudoc.d\nindex b04e656bd82..7a95bad8e65 100644\n--- a/gas/testsuite/gas/bpf/indcall-1-pseudoc.d\n+++ b/gas/testsuite/gas/bpf/indcall-1-pseudoc.d\n@@ -1,5 +1,23 @@\n-#as: -mxbpf --EL\n-#objdump: -mxbpf -dr\n+#as: -EL -mdialect=pseudoc -misa-spec=xbpf\n+#objdump: -M xbpf,pseudoc,dec -dr\n #source: indcall-1-pseudoc.s\n-#dump: indcall-1.dump\n #name: BPF indirect call 1, pseudoc syntax\n+\n+.*: +file format .*bpf.*\n+\n+Disassembly of section \\.text:\n+\n+0000000000000000
:\n+ 0:\tb7 00 00 00 01 00 00 00 \tr0=1\n+ 8:\tb7 01 00 00 01 00 00 00 \tr1=1\n+ 10:\tb7 02 00 00 02 00 00 00 \tr2=2\n+ 18:\t18 06 00 00 38 00 00 00 \tr6=56 ll\n+ 20:\t00 00 00 00 00 00 00 00[ ]*\n+\t\t\t18: R_BPF_64_64\t.text\n+ 28:\t8d 06 00 00 00 00 00 00 \tcallx r6\n+ 30:\t95 00 00 00 00 00 00 00 \texit\n+\n+0000000000000038 :\n+ 38:\tb7 00 00 00 00 00 00 00 \tr0=0\n+ 40:\t95 00 00 00 00 00 00 00 \texit\n+#pass\ndiff --git a/gas/testsuite/gas/bpf/indcall-1.d b/gas/testsuite/gas/bpf/indcall-1.d\nindex e04b98b175b..51103bba2a1 100644\n--- a/gas/testsuite/gas/bpf/indcall-1.d\n+++ b/gas/testsuite/gas/bpf/indcall-1.d\n@@ -1,5 +1,23 @@\n-#as: -mxbpf --EL\n-#objdump: -mxbpf -dr\n+#as: -EL -misa-spec=xbpf\n+#objdump: -dr -M xbpf,dec\n #source: indcall-1.s\n-#dump: indcall-1.dump\n #name: BPF indirect call 1, normal syntax\n+\n+.*: +file format .*bpf.*\n+\n+Disassembly of section \\.text:\n+\n+0000000000000000
:\n+ 0:\tb7 00 00 00 01 00 00 00 \tmov %r0,1\n+ 8:\tb7 01 00 00 01 00 00 00 \tmov %r1,1\n+ 10:\tb7 02 00 00 02 00 00 00 \tmov %r2,2\n+ 18:\t18 06 00 00 38 00 00 00 \tlddw %r6,56\n+ 20:\t00 00 00 00 00 00 00 00[ ]*\n+\t\t\t18: R_BPF_64_64\t.text\n+ 28:\t8d 06 00 00 00 00 00 00 \tcall %r6\n+ 30:\t95 00 00 00 00 00 00 00 \texit\n+\n+0000000000000038 :\n+ 38:\tb7 00 00 00 00 00 00 00 \tmov %r0,0\n+ 40:\t95 00 00 00 00 00 00 00 \texit\n+#pass\ndiff --git a/gas/testsuite/gas/bpf/jump-be-pseudoc.d b/gas/testsuite/gas/bpf/jump-be-pseudoc.d\nnew file mode 100644\nindex 00000000000..3874d58f73a\n--- /dev/null\n+++ b/gas/testsuite/gas/bpf/jump-be-pseudoc.d\n@@ -0,0 +1,32 @@\n+#as: -EB -mdialect=pseudoc\n+#source: jump-pseudoc.s\n+#objdump: -dr -M dec,pseudoc\n+#name: eBPF JUMP instructions, big endian\n+\n+.*: +file format .*bpf.*\n+\n+Disassembly of section .text:\n+\n+0+ <.text>:\n+ 0:\t05 00 00 03 00 00 00 00 \tgoto 3\n+ 8:\t0f 11 00 00 00 00 00 00 \tr1\\+=r1\n+ 10:\t15 30 00 01 00 00 00 03 \tif r3==3 goto 1\n+ 18:\t1d 34 00 00 00 00 00 00 \tif r3==r4 goto 0\n+ 20:\t35 30 ff fd 00 00 00 03 \tif r3>=3 goto -3\n+ 28:\t3d 34 ff fc 00 00 00 00 \tif r3>=r4 goto -4\n+ 30:\ta5 30 00 01 00 00 00 03 \tif r3<3 goto 1\n+ 38:\tad 34 00 00 00 00 00 00 \tif r33 goto 1\n+ 78:\t6d 34 00 00 00 00 00 00 \tif r3s>r4 goto 0\n+ 80:\t75 30 00 01 00 00 00 03 \tif r3s>=3 goto 1\n+ 88:\t7d 34 00 00 00 00 00 00 \tif r3s>=r4 goto 0\n+ 90:\tc5 30 00 01 00 00 00 03 \tif r3s<3 goto 1\n+ 98:\tcd 34 00 00 00 00 00 00 \tif r3s:\n+ 0:\t05 00 03 00 00 00 00 00 \tgoto 3\n+ 8:\t0f 11 00 00 00 00 00 00 \tr1\\+=r1\n+ 10:\t15 03 01 00 03 00 00 00 \tif r3==3 goto 1\n+ 18:\t1d 43 00 00 00 00 00 00 \tif r3==r4 goto 0\n+ 20:\t35 03 fd ff 03 00 00 00 \tif r3>=3 goto -3\n+ 28:\t3d 43 fc ff 00 00 00 00 \tif r3>=r4 goto -4\n+ 30:\ta5 03 01 00 03 00 00 00 \tif r3<3 goto 1\n+ 38:\tad 43 00 00 00 00 00 00 \tif r33 goto 1\n+ 78:\t6d 43 00 00 00 00 00 00 \tif r3s>r4 goto 0\n+ 80:\t75 03 01 00 03 00 00 00 \tif r3s>=3 goto 1\n+ 88:\t7d 43 00 00 00 00 00 00 \tif r3s>=r4 goto 0\n+ 90:\tc5 03 01 00 03 00 00 00 \tif r3s<3 goto 1\n+ 98:\tcd 43 00 00 00 00 00 00 \tif r3s:\n+ 0:\t05 00 03 00 00 00 00 00 \tja 3\n+ 8:\t0f 11 00 00 00 00 00 00 \tadd %r1,%r1\n+ 10:\t15 03 01 00 03 00 00 00 \tjeq %r3,3,1\n+ 18:\t1d 43 00 00 00 00 00 00 \tjeq %r3,%r4,0\n+ 20:\t35 03 fd ff 03 00 00 00 \tjge %r3,3,-3\n+ 28:\t3d 43 fc ff 00 00 00 00 \tjge %r3,%r4,-4\n+ 30:\ta5 03 01 00 03 00 00 00 \tjlt %r3,3,1\n+ 38:\tad 43 00 00 00 00 00 00 \tjlt %r3,%r4,0\n+ 40:\tb5 03 01 00 03 00 00 00 \tjle %r3,3,1\n+ 48:\tbd 43 00 00 00 00 00 00 \tjle %r3,%r4,0\n+ 50:\t45 03 01 00 03 00 00 00 \tjset %r3,3,1\n+ 58:\t4d 43 00 00 00 00 00 00 \tjset %r3,%r4,0\n+ 60:\t55 03 01 00 03 00 00 00 \tjne %r3,3,1\n+ 68:\t5d 43 00 00 00 00 00 00 \tjne %r3,%r4,0\n+ 70:\t65 03 01 00 03 00 00 00 \tjsgt %r3,3,1\n+ 78:\t6d 43 00 00 00 00 00 00 \tjsgt %r3,%r4,0\n+ 80:\t75 03 01 00 03 00 00 00 \tjsge %r3,3,1\n+ 88:\t7d 43 00 00 00 00 00 00 \tjsge %r3,%r4,0\n+ 90:\tc5 03 01 00 03 00 00 00 \tjslt %r3,3,1\n+ 98:\tcd 43 00 00 00 00 00 00 \tjslt %r3,%r4,0\n+ a0:\td5 03 01 00 03 00 00 00 \tjsle %r3,3,1\n+ a8:\tdd 43 00 00 00 00 00 00 \tjsle %r3,%r4,0\ndiff --git a/gas/testsuite/gas/bpf/jump32-be-pseudoc.d b/gas/testsuite/gas/bpf/jump32-be-pseudoc.d\nnew file mode 100644\nindex 00000000000..ca20186e59b\n--- /dev/null\n+++ b/gas/testsuite/gas/bpf/jump32-be-pseudoc.d\n@@ -0,0 +1,32 @@\n+#as: -EB -mdialect=pseudoc\n+#objdump: -dr -M dec,pseudoc\n+#source: jump32-pseudoc.s\n+#name: eBPF JUMP32 instructions, pseudoc syntax, big-endian\n+\n+.*: +file format .*bpf.*\n+\n+Disassembly of section .text:\n+\n+0+ <.text>:\n+ 0:\t05 00 00 03 00 00 00 00 \tgoto 3\n+ 8:\t0f 11 00 00 00 00 00 00 \tr1\\+=r1\n+ 10:\t16 30 00 01 00 00 00 03 \tif w3==3 goto 1\n+ 18:\t1e 34 00 00 00 00 00 00 \tif w3==w4 goto 0\n+ 20:\t36 30 ff fd 00 00 00 03 \tif w3>=3 goto -3\n+ 28:\t3e 34 ff fc 00 00 00 00 \tif w3>=w4 goto -4\n+ 30:\ta6 30 00 01 00 00 00 03 \tif w3<3 goto 1\n+ 38:\tae 34 00 00 00 00 00 00 \tif w33 goto 1\n+ 78:\t6e 34 00 00 00 00 00 00 \tif w3s>w4 goto 0\n+ 80:\t76 30 00 01 00 00 00 03 \tif w3s>=3 goto 1\n+ 88:\t7e 34 00 00 00 00 00 00 \tif w3s>=w4 goto 0\n+ 90:\tc6 30 00 01 00 00 00 03 \tif w3s<3 goto 1\n+ 98:\tce 34 00 00 00 00 00 00 \tif w3s:\n+ 0:\t05 00 00 03 00 00 00 00 \tja 3\n+ 8:\t0f 11 00 00 00 00 00 00 \tadd %r1,%r1\n+ 10:\t16 30 00 01 00 00 00 03 \tjeq32 %r3,3,1\n+ 18:\t1e 34 00 00 00 00 00 00 \tjeq32 %r3,%r4,0\n+ 20:\t36 30 ff fd 00 00 00 03 \tjge32 %r3,3,-3\n+ 28:\t3e 34 ff fc 00 00 00 00 \tjge32 %r3,%r4,-4\n+ 30:\ta6 30 00 01 00 00 00 03 \tjlt32 %r3,3,1\n+ 38:\tae 34 00 00 00 00 00 00 \tjlt32 %r3,%r4,0\n+ 40:\tb6 30 00 01 00 00 00 03 \tjle32 %r3,3,1\n+ 48:\tbe 34 00 00 00 00 00 00 \tjle32 %r3,%r4,0\n+ 50:\t46 30 00 01 00 00 00 03 \tjset32 %r3,3,1\n+ 58:\t4e 34 00 00 00 00 00 00 \tjset32 %r3,%r4,0\n+ 60:\t56 30 00 01 00 00 00 03 \tjne32 %r3,3,1\n+ 68:\t5e 34 00 00 00 00 00 00 \tjne32 %r3,%r4,0\n+ 70:\t66 30 00 01 00 00 00 03 \tjsgt32 %r3,3,1\n+ 78:\t6e 34 00 00 00 00 00 00 \tjsgt32 %r3,%r4,0\n+ 80:\t76 30 00 01 00 00 00 03 \tjsge32 %r3,3,1\n+ 88:\t7e 34 00 00 00 00 00 00 \tjsge32 %r3,%r4,0\n+ 90:\tc6 30 00 01 00 00 00 03 \tjslt32 %r3,3,1\n+ 98:\tce 34 00 00 00 00 00 00 \tjslt32 %r3,%r4,0\n+ a0:\td6 30 00 01 00 00 00 03 \tjsle32 %r3,3,1\n+ a8:\tde 34 00 00 00 00 00 00 \tjsle32 %r3,%r4,0\ndiff --git a/gas/testsuite/gas/bpf/jump32-pseudoc.d b/gas/testsuite/gas/bpf/jump32-pseudoc.d\nindex 55fb97b82db..27367d36594 100644\n--- a/gas/testsuite/gas/bpf/jump32-pseudoc.d\n+++ b/gas/testsuite/gas/bpf/jump32-pseudoc.d\n@@ -1,5 +1,32 @@\n-#as: --EL\n-#objdump: -dr\n+#as: -EL -mdialect=pseudoc\n+#objdump: -dr -M dec,pseudoc\n #source: jump32-pseudoc.s\n-#dump: jump32.dump\n #name: eBPF JUMP32 instructions, pseudoc syntax\n+\n+.*: +file format .*bpf.*\n+\n+Disassembly of section .text:\n+\n+0+ <.text>:\n+ 0:\t05 00 03 00 00 00 00 00 \tgoto 3\n+ 8:\t0f 11 00 00 00 00 00 00 \tr1\\+=r1\n+ 10:\t16 03 01 00 03 00 00 00 \tif w3==3 goto 1\n+ 18:\t1e 43 00 00 00 00 00 00 \tif w3==w4 goto 0\n+ 20:\t36 03 fd ff 03 00 00 00 \tif w3>=3 goto -3\n+ 28:\t3e 43 fc ff 00 00 00 00 \tif w3>=w4 goto -4\n+ 30:\ta6 03 01 00 03 00 00 00 \tif w3<3 goto 1\n+ 38:\tae 43 00 00 00 00 00 00 \tif w33 goto 1\n+ 78:\t6e 43 00 00 00 00 00 00 \tif w3s>w4 goto 0\n+ 80:\t76 03 01 00 03 00 00 00 \tif w3s>=3 goto 1\n+ 88:\t7e 43 00 00 00 00 00 00 \tif w3s>=w4 goto 0\n+ 90:\tc6 03 01 00 03 00 00 00 \tif w3s<3 goto 1\n+ 98:\tce 43 00 00 00 00 00 00 \tif w3s:\n+ 0:\t05 00 03 00 00 00 00 00 \tja 3\n+ 8:\t0f 11 00 00 00 00 00 00 \tadd %r1,%r1\n+ 10:\t16 03 01 00 03 00 00 00 \tjeq32 %r3,3,1\n+ 18:\t1e 43 00 00 00 00 00 00 \tjeq32 %r3,%r4,0\n+ 20:\t36 03 fd ff 03 00 00 00 \tjge32 %r3,3,-3\n+ 28:\t3e 43 fc ff 00 00 00 00 \tjge32 %r3,%r4,-4\n+ 30:\ta6 03 01 00 03 00 00 00 \tjlt32 %r3,3,1\n+ 38:\tae 43 00 00 00 00 00 00 \tjlt32 %r3,%r4,0\n+ 40:\tb6 03 01 00 03 00 00 00 \tjle32 %r3,3,1\n+ 48:\tbe 43 00 00 00 00 00 00 \tjle32 %r3,%r4,0\n+ 50:\t46 03 01 00 03 00 00 00 \tjset32 %r3,3,1\n+ 58:\t4e 43 00 00 00 00 00 00 \tjset32 %r3,%r4,0\n+ 60:\t56 03 01 00 03 00 00 00 \tjne32 %r3,3,1\n+ 68:\t5e 43 00 00 00 00 00 00 \tjne32 %r3,%r4,0\n+ 70:\t66 03 01 00 03 00 00 00 \tjsgt32 %r3,3,1\n+ 78:\t6e 43 00 00 00 00 00 00 \tjsgt32 %r3,%r4,0\n+ 80:\t76 03 01 00 03 00 00 00 \tjsge32 %r3,3,1\n+ 88:\t7e 43 00 00 00 00 00 00 \tjsge32 %r3,%r4,0\n+ 90:\tc6 03 01 00 03 00 00 00 \tjslt32 %r3,3,1\n+ 98:\tce 43 00 00 00 00 00 00 \tjslt32 %r3,%r4,0\n+ a0:\td6 03 01 00 03 00 00 00 \tjsle32 %r3,3,1\n+ a8:\tde 43 00 00 00 00 00 00 \tjsle32 %r3,%r4,0\ndiff --git a/gas/testsuite/gas/bpf/lddw-be-pseudoc.d b/gas/testsuite/gas/bpf/lddw-be-pseudoc.d\nindex e7b477ac4ca..940780b81a2 100644\n--- a/gas/testsuite/gas/bpf/lddw-be-pseudoc.d\n+++ b/gas/testsuite/gas/bpf/lddw-be-pseudoc.d\n@@ -1,5 +1,18 @@\n-#as: --EB\n+#as: -EB -mdialect=pseudoc\n #source: lddw-pseudoc.s\n-#objdump: -dr\n-#dump: lddw-be.dump\n+#objdump: -dr -M hex,pseudoc\n #name: eBPF LDDW, big-endian, pseudoc syntax\n+\n+.*: +file format .*bpf.*\n+\n+Disassembly of section .text:\n+\n+0+ <.text>:\n+ 0:\t18 30 00 00 00 00 00 01 \tr3=0x1 ll\n+ 8:\t00 00 00 00 00 00 00 00 \n+ 10:\t18 40 00 00 de ad be ef \tr4=0xdeadbeef ll\n+ 18:\t00 00 00 00 00 00 00 00 \n+ 20:\t18 50 00 00 55 66 77 88 \tr5=0x1122334455667788 ll\n+ 28:\t00 00 00 00 11 22 33 44 \n+ 30:\t18 60 00 00 ff ff ff fe \tr6=0xfffffffffffffffe ll\n+ 38:\t00 00 00 00 ff ff ff ff \ndiff --git a/gas/testsuite/gas/bpf/lddw-be.d b/gas/testsuite/gas/bpf/lddw-be.d\nindex cf1bfba9b3d..c1043787dcd 100644\n--- a/gas/testsuite/gas/bpf/lddw-be.d\n+++ b/gas/testsuite/gas/bpf/lddw-be.d\n@@ -1,5 +1,18 @@\n-#as: --EB\n+#as: -EB -mdialect=normal\n #source: lddw.s\n-#objdump: -dr\n-#dump: lddw-be.dump\n+#objdump: -dr -M hex\n #name: eBPF LDDW, big-endian, normal syntax\n+\n+.*: +file format .*bpf.*\n+\n+Disassembly of section .text:\n+\n+0+ <.text>:\n+ 0:\t18 30 00 00 00 00 00 01 \tlddw %r3,0x1\n+ 8:\t00 00 00 00 00 00 00 00 \n+ 10:\t18 40 00 00 de ad be ef \tlddw %r4,0xdeadbeef\n+ 18:\t00 00 00 00 00 00 00 00 \n+ 20:\t18 50 00 00 55 66 77 88 \tlddw %r5,0x1122334455667788\n+ 28:\t00 00 00 00 11 22 33 44 \n+ 30:\t18 60 00 00 ff ff ff fe \tlddw %r6,0xfffffffffffffffe\n+ 38:\t00 00 00 00 ff ff ff ff \ndiff --git a/gas/testsuite/gas/bpf/lddw-pseudoc.d b/gas/testsuite/gas/bpf/lddw-pseudoc.d\nindex 838e012be0b..3a5ce86ff95 100644\n--- a/gas/testsuite/gas/bpf/lddw-pseudoc.d\n+++ b/gas/testsuite/gas/bpf/lddw-pseudoc.d\n@@ -1,5 +1,18 @@\n-#as: --EL\n-#objdump: -dr\n+#as: -EL -mdialect=pseudoc\n+#objdump: -dr -M hex,pseudoc\n #source: lddw-pseudoc.s\n-#dump: lddw.dump\n #name: eBPF LDDW, pseudoc syntax\n+\n+.*: +file format .*bpf.*\n+\n+Disassembly of section .text:\n+\n+0+ <.text>:\n+ 0:\t18 03 00 00 01 00 00 00 \tr3=0x1 ll\n+ 8:\t00 00 00 00 00 00 00 00 \n+ 10:\t18 04 00 00 ef be ad de \tr4=0xdeadbeef ll\n+ 18:\t00 00 00 00 00 00 00 00 \n+ 20:\t18 05 00 00 88 77 66 55 \tr5=0x1122334455667788 ll\n+ 28:\t00 00 00 00 44 33 22 11 \n+ 30:\t18 06 00 00 fe ff ff ff \tr6=0xfffffffffffffffe ll\n+ 38:\t00 00 00 00 ff ff ff ff \ndiff --git a/gas/testsuite/gas/bpf/lddw.d b/gas/testsuite/gas/bpf/lddw.d\nindex 82ff1b47bc4..c7a08098fb8 100644\n--- a/gas/testsuite/gas/bpf/lddw.d\n+++ b/gas/testsuite/gas/bpf/lddw.d\n@@ -1,5 +1,18 @@\n-#as: --EL\n-#objdump: -dr\n+#as: -EL -mdialect=normal\n+#objdump: -dr -M hex\n #source: lddw.s\n-#dump: lddw.dump\n #name: eBPF LDDW, normal syntax\n+\n+.*: +file format .*bpf.*\n+\n+Disassembly of section .text:\n+\n+0+ <.text>:\n+ 0:\t18 03 00 00 01 00 00 00 \tlddw %r3,0x1\n+ 8:\t00 00 00 00 00 00 00 00 \n+ 10:\t18 04 00 00 ef be ad de \tlddw %r4,0xdeadbeef\n+ 18:\t00 00 00 00 00 00 00 00 \n+ 20:\t18 05 00 00 88 77 66 55 \tlddw %r5,0x1122334455667788\n+ 28:\t00 00 00 00 44 33 22 11 \n+ 30:\t18 06 00 00 fe ff ff ff \tlddw %r6,0xfffffffffffffffe\n+ 38:\t00 00 00 00 ff ff ff ff \ndiff --git a/gas/testsuite/gas/bpf/mem-be-pseudoc.d b/gas/testsuite/gas/bpf/mem-be-pseudoc.d\nnew file mode 100644\nindex 00000000000..ef13fe1f8a4\n--- /dev/null\n+++ b/gas/testsuite/gas/bpf/mem-be-pseudoc.d\n@@ -0,0 +1,30 @@\n+#as: -EB -mdialect=pseudoc\n+#objdump: -dr -M hex,pseudoc\n+#source: mem-pseudoc.s\n+#name: eBPF MEM instructions, modulus lddw, pseudo-c syntax, big-endian\n+\n+.*: +file format .*bpf.*\n+\n+Disassembly of section .text:\n+\n+0+ <.text>:\n+ 0:\t20 00 00 00 00 00 be ef \tr0=\\*\\(u32\\*\\)skb\\[0xbeef\\]\n+ 8:\t28 00 00 00 00 00 be ef \tr0=\\*\\(u16\\*\\)skb\\[0xbeef\\]\n+ 10:\t30 00 00 00 00 00 be ef \tr0=\\*\\(u8\\*\\)skb\\[0xbeef\\]\n+ 18:\t38 00 00 00 00 00 be ef \tr0=\\*\\(u64\\*\\)skb\\[0xbeef\\]\n+ 20:\t40 03 00 00 00 00 be ef \tr0=\\*\\(u32\\*\\)skb\\[r3\\+0xbeef\\]\n+ 28:\t48 05 00 00 00 00 be ef \tr0=\\*\\(u16\\*\\)skb\\[r5\\+0xbeef\\]\n+ 30:\t50 07 00 00 00 00 be ef \tr0=\\*\\(u8\\*\\)skb\\[r7\\+0xbeef\\]\n+ 38:\t58 09 00 00 00 00 be ef \tr0=\\*\\(u64\\*\\)skb\\[r9\\+0xbeef\\]\n+ 40:\t61 21 7e ef 00 00 00 00 \tr2=\\*\\(u32\\*\\)\\(r1\\+0x7eef\\)\n+ 48:\t69 21 7e ef 00 00 00 00 \tr2=\\*\\(u16\\*\\)\\(r1\\+0x7eef\\)\n+ 50:\t71 21 7e ef 00 00 00 00 \tr2=\\*\\(u8\\*\\)\\(r1\\+0x7eef\\)\n+ 58:\t79 21 ff fe 00 00 00 00 \tr2=\\*\\(u64\\*\\)\\(r1\\+0xfffe\\)\n+ 60:\t63 12 7e ef 00 00 00 00 \t\\*\\(u32\\*\\)\\(r1\\+0x7eef\\)=r2\n+ 68:\t6b 12 7e ef 00 00 00 00 \t\\*\\(u16\\*\\)\\(r1\\+0x7eef\\)=r2\n+ 70:\t73 12 7e ef 00 00 00 00 \t\\*\\(u8\\*\\)\\(r1\\+0x7eef\\)=r2\n+ 78:\t7b 12 ff fe 00 00 00 00 \t\\*\\(u64\\*\\)\\(r1\\+0xfffe\\)=r2\n+ 80:\t72 10 7e ef 11 22 33 44 \t\\*\\(u8\\*\\)\\(r1\\+0x7eef\\)=0x11223344\n+ 88:\t6a 10 7e ef 11 22 33 44 \t\\*\\(u16\\*\\)\\(r1\\+0x7eef\\)=0x11223344\n+ 90:\t62 10 7e ef 11 22 33 44 \t\\*\\(u32\\*\\)\\(r1\\+0x7eef\\)=0x11223344\n+ 98:\t7a 10 ff fe 11 22 33 44 \t\\*\\(u64\\*\\)\\(r1\\+0xfffe\\)=0x11223344\ndiff --git a/gas/testsuite/gas/bpf/mem-be.d b/gas/testsuite/gas/bpf/mem-be.d\nindex 148c55a3491..f24efaa4c7b 100644\n--- a/gas/testsuite/gas/bpf/mem-be.d\n+++ b/gas/testsuite/gas/bpf/mem-be.d\n@@ -1,7 +1,6 @@\n-#as: --EB\n+#as: -EB -mdialect=normal\n #source: mem.s\n-#source: mem-pseudoc.s\n-#objdump: -dr\n+#objdump: -dr -M hex\n #name: eBPF MEM instructions, modulus lddw, big endian\n \n .*: +file format .*bpf.*\n@@ -20,12 +19,12 @@ Disassembly of section .text:\n 40:\t61 21 7e ef 00 00 00 00 \tldxw %r2,\\[%r1\\+0x7eef\\]\n 48:\t69 21 7e ef 00 00 00 00 \tldxh %r2,\\[%r1\\+0x7eef\\]\n 50:\t71 21 7e ef 00 00 00 00 \tldxb %r2,\\[%r1\\+0x7eef\\]\n- 58:\t79 21 ff fe 00 00 00 00 \tldxdw %r2,\\[%r1\\+-2\\]\n+ 58:\t79 21 ff fe 00 00 00 00 \tldxdw %r2,\\[%r1\\+0xfffe\\]\n 60:\t63 12 7e ef 00 00 00 00 \tstxw \\[%r1\\+0x7eef\\],%r2\n 68:\t6b 12 7e ef 00 00 00 00 \tstxh \\[%r1\\+0x7eef\\],%r2\n 70:\t73 12 7e ef 00 00 00 00 \tstxb \\[%r1\\+0x7eef\\],%r2\n- 78:\t7b 12 ff fe 00 00 00 00 \tstxdw \\[%r1\\+-2\\],%r2\n+ 78:\t7b 12 ff fe 00 00 00 00 \tstxdw \\[%r1\\+0xfffe\\],%r2\n 80:\t72 10 7e ef 11 22 33 44 \tstb \\[%r1\\+0x7eef\\],0x11223344\n 88:\t6a 10 7e ef 11 22 33 44 \tsth \\[%r1\\+0x7eef\\],0x11223344\n 90:\t62 10 7e ef 11 22 33 44 \tstw \\[%r1\\+0x7eef\\],0x11223344\n- 98:\t7a 10 ff fe 11 22 33 44 \tstdw \\[%r1\\+-2\\],0x11223344\n+ 98:\t7a 10 ff fe 11 22 33 44 \tstdw \\[%r1\\+0xfffe\\],0x11223344\ndiff --git a/gas/testsuite/gas/bpf/mem-pseudoc.d b/gas/testsuite/gas/bpf/mem-pseudoc.d\nindex ef5b8957d64..4e8b7d012e3 100644\n--- a/gas/testsuite/gas/bpf/mem-pseudoc.d\n+++ b/gas/testsuite/gas/bpf/mem-pseudoc.d\n@@ -1,5 +1,30 @@\n-#as: --EL\n-#objdump: -dr\n+#as: -EL -mdialect=pseudoc\n+#objdump: -dr -M hex,pseudoc\n #source: mem-pseudoc.s\n-#dump: mem.dump\n #name: eBPF MEM instructions, modulus lddw, pseudo-c syntax\n+\n+.*: +file format .*bpf.*\n+\n+Disassembly of section .text:\n+\n+0+ <.text>:\n+ 0:\t20 00 00 00 ef be 00 00 \tr0=\\*\\(u32\\*\\)skb\\[0xbeef\\]\n+ 8:\t28 00 00 00 ef be 00 00 \tr0=\\*\\(u16\\*\\)skb\\[0xbeef\\]\n+ 10:\t30 00 00 00 ef be 00 00 \tr0=\\*\\(u8\\*\\)skb\\[0xbeef\\]\n+ 18:\t38 00 00 00 ef be 00 00 \tr0=\\*\\(u64\\*\\)skb\\[0xbeef\\]\n+ 20:\t40 30 00 00 ef be 00 00 \tr0=\\*\\(u32\\*\\)skb\\[r3\\+0xbeef\\]\n+ 28:\t48 50 00 00 ef be 00 00 \tr0=\\*\\(u16\\*\\)skb\\[r5\\+0xbeef\\]\n+ 30:\t50 70 00 00 ef be 00 00 \tr0=\\*\\(u8\\*\\)skb\\[r7\\+0xbeef\\]\n+ 38:\t58 90 00 00 ef be 00 00 \tr0=\\*\\(u64\\*\\)skb\\[r9\\+0xbeef\\]\n+ 40:\t61 12 ef 7e 00 00 00 00 \tr2=\\*\\(u32\\*\\)\\(r1\\+0x7eef\\)\n+ 48:\t69 12 ef 7e 00 00 00 00 \tr2=\\*\\(u16\\*\\)\\(r1\\+0x7eef\\)\n+ 50:\t71 12 ef 7e 00 00 00 00 \tr2=\\*\\(u8\\*\\)\\(r1\\+0x7eef\\)\n+ 58:\t79 12 fe ff 00 00 00 00 \tr2=\\*\\(u64\\*\\)\\(r1\\+0xfffe\\)\n+ 60:\t63 21 ef 7e 00 00 00 00 \t\\*\\(u32\\*\\)\\(r1\\+0x7eef\\)=r2\n+ 68:\t6b 21 ef 7e 00 00 00 00 \t\\*\\(u16\\*\\)\\(r1\\+0x7eef\\)=r2\n+ 70:\t73 21 ef 7e 00 00 00 00 \t\\*\\(u8\\*\\)\\(r1\\+0x7eef\\)=r2\n+ 78:\t7b 21 fe ff 00 00 00 00 \t\\*\\(u64\\*\\)\\(r1\\+0xfffe\\)=r2\n+ 80:\t72 01 ef 7e 44 33 22 11 \t\\*\\(u8\\*\\)\\(r1\\+0x7eef\\)=0x11223344\n+ 88:\t6a 01 ef 7e 44 33 22 11 \t\\*\\(u16\\*\\)\\(r1\\+0x7eef\\)=0x11223344\n+ 90:\t62 01 ef 7e 44 33 22 11 \t\\*\\(u32\\*\\)\\(r1\\+0x7eef\\)=0x11223344\n+ 98:\t7a 01 fe ff 44 33 22 11 \t\\*\\(u64\\*\\)\\(r1\\+0xfffe\\)=0x11223344\ndiff --git a/gas/testsuite/gas/bpf/mem-pseudoc.s b/gas/testsuite/gas/bpf/mem-pseudoc.s\nindex 06c2cfcdde9..7b8c832eb40 100644\n--- a/gas/testsuite/gas/bpf/mem-pseudoc.s\n+++ b/gas/testsuite/gas/bpf/mem-pseudoc.s\n@@ -17,7 +17,7 @@\n \t*(u16 *)(r1 + 32495) = r2\n \t*(u8 *)(r1 + 32495) = r2\n \t*(u64 *)(r1 - 2) = r2\n-\tstb [%r1+0x7eef], 0x11223344\n-\tsth [%r1+0x7eef], 0x11223344\n-\tstw [%r1+0x7eef], 0x11223344\n-\tstdw [%r1+-2], 0x11223344\n+ *(u8 *)(r1 + 0x7eef) = 0x11223344\n+\t*(u16 *)(r1 + 0x7eef) = 0x11223344\n+\t*(u32 *)(r1 + 0x7eef) = 0x11223344\n+\t*(u64 *)(r1 + -2) = 0x11223344\ndiff --git a/gas/testsuite/gas/bpf/mem.d b/gas/testsuite/gas/bpf/mem.d\nindex b01bdaaf241..669aae36ce7 100644\n--- a/gas/testsuite/gas/bpf/mem.d\n+++ b/gas/testsuite/gas/bpf/mem.d\n@@ -1,5 +1,30 @@\n-#as: --EL\n-#objdump: -dr\n+#as: -EL -mdialect=normal\n+#objdump: -dr -M hex\n #source: mem.s\n-#dump: mem.dump\n #name: eBPF MEM instructions, modulus lddw, normal syntax\n+\n+.*: +file format .*bpf.*\n+\n+Disassembly of section .text:\n+\n+0+ <.text>:\n+ 0:\t20 00 00 00 ef be 00 00 \tldabsw 0xbeef\n+ 8:\t28 00 00 00 ef be 00 00 \tldabsh 0xbeef\n+ 10:\t30 00 00 00 ef be 00 00 \tldabsb 0xbeef\n+ 18:\t38 00 00 00 ef be 00 00 \tldabsdw 0xbeef\n+ 20:\t40 30 00 00 ef be 00 00 \tldindw %r3,0xbeef\n+ 28:\t48 50 00 00 ef be 00 00 \tldindh %r5,0xbeef\n+ 30:\t50 70 00 00 ef be 00 00 \tldindb %r7,0xbeef\n+ 38:\t58 90 00 00 ef be 00 00 \tldinddw %r9,0xbeef\n+ 40:\t61 12 ef 7e 00 00 00 00 \tldxw %r2,\\[%r1\\+0x7eef\\]\n+ 48:\t69 12 ef 7e 00 00 00 00 \tldxh %r2,\\[%r1\\+0x7eef\\]\n+ 50:\t71 12 ef 7e 00 00 00 00 \tldxb %r2,\\[%r1\\+0x7eef\\]\n+ 58:\t79 12 fe ff 00 00 00 00 \tldxdw %r2,\\[%r1\\+0xfffe\\]\n+ 60:\t63 21 ef 7e 00 00 00 00 \tstxw \\[%r1\\+0x7eef\\],%r2\n+ 68:\t6b 21 ef 7e 00 00 00 00 \tstxh \\[%r1\\+0x7eef\\],%r2\n+ 70:\t73 21 ef 7e 00 00 00 00 \tstxb \\[%r1\\+0x7eef\\],%r2\n+ 78:\t7b 21 fe ff 00 00 00 00 \tstxdw \\[%r1\\+0xfffe\\],%r2\n+ 80:\t72 01 ef 7e 44 33 22 11 \tstb \\[%r1\\+0x7eef\\],0x11223344\n+ 88:\t6a 01 ef 7e 44 33 22 11 \tsth \\[%r1\\+0x7eef\\],0x11223344\n+ 90:\t62 01 ef 7e 44 33 22 11 \tstw \\[%r1\\+0x7eef\\],0x11223344\n+ 98:\t7a 01 fe ff 44 33 22 11 \tstdw \\[%r1\\+0xfffe\\],0x11223344\ndiff --git a/gas/testsuite/gas/bpf/mem.s b/gas/testsuite/gas/bpf/mem.s\nindex af6f41b0db0..798a18e2436 100644\n--- a/gas/testsuite/gas/bpf/mem.s\n+++ b/gas/testsuite/gas/bpf/mem.s\n@@ -21,4 +21,4 @@\n \tstb [%r1+0x7eef], 0x11223344\n \tsth [%r1+0x7eef], 0x11223344\n \tstw [%r1+0x7eef], 0x11223344\n- \tstdw [%r1+-2], 0x11223344\n+ \tstdw [%r1-2], 0x11223344\ndiff --git a/gas/testsuite/gas/bpf/spacing-pseudoc.d b/gas/testsuite/gas/bpf/spacing-pseudoc.d\nnew file mode 100644\nindex 00000000000..16f5763aeb0\n--- /dev/null\n+++ b/gas/testsuite/gas/bpf/spacing-pseudoc.d\n@@ -0,0 +1,18 @@\n+#as: -EB -mdialect=pseudoc\n+#source: spacing-pseudoc.s\n+#objdump: -dr -M hex,pseudoc\n+#name: spacing, pseudoc syntax\n+\n+.*: +file format .*bpf.*\n+\n+Disassembly of section .text:\n+\n+0+ <.text>:\n+ 0:\tb7 04 00 00 ef be ad de \tr4=0xdeadbeef\n+ 8:\t18 04 00 00 ef be ad de \tr4=0xdeadbeef ll\n+ 10:\t00 00 00 00 00 00 00 00 \n+ 18:\t05 00 01 00 00 00 00 00 \tgoto 0x1\n+ 20:\t05 00 01 00 00 00 00 00 \tgoto 0x1\n+ 28:\t05 00 01 00 00 00 00 00 \tgoto 0x1\n+ 30:\t16 03 01 00 03 00 00 00 \tif w3==0x3 goto 0x1\n+ 38:\t16 03 01 00 03 00 00 00 \tif w3==0x3 goto 0x1\ndiff --git a/gas/testsuite/gas/bpf/spacing-pseudoc.s b/gas/testsuite/gas/bpf/spacing-pseudoc.s\nnew file mode 100644\nindex 00000000000..3c19d9a5073\n--- /dev/null\n+++ b/gas/testsuite/gas/bpf/spacing-pseudoc.s\n@@ -0,0 +1,9 @@\n+ ;; This test checks that flexible spacing is supported in the\n+ ;; pseudoc syntax.\n+ r4 = 0xdeadbeefll\n+ r4 = 0xdeadbeef ll\n+ goto +1\n+ goto+1\n+ goto1\n+ if w3==3 goto+1\n+ if w3==3 goto1\ndiff --git a/include/dis-asm.h b/include/dis-asm.h\nindex d356429f3c5..c76185f5b3c 100644\n--- a/include/dis-asm.h\n+++ b/include/dis-asm.h\n@@ -388,6 +388,7 @@ extern void print_arc_disassembler_options (FILE *);\n extern void print_s390_disassembler_options (FILE *);\n extern void print_wasm32_disassembler_options (FILE *);\n extern void print_loongarch_disassembler_options (FILE *);\n+extern void print_bpf_disassembler_options (FILE *);\n extern bool aarch64_symbol_is_valid (asymbol *, struct disassemble_info *);\n extern bool arm_symbol_is_valid (asymbol *, struct disassemble_info *);\n extern bool csky_symbol_is_valid (asymbol *, struct disassemble_info *);\ndiff --git a/include/elf/bpf.h b/include/elf/bpf.h\nindex fb1936010bf..d0fad08c24a 100644\n--- a/include/elf/bpf.h\n+++ b/include/elf/bpf.h\n@@ -34,6 +34,7 @@ START_RELOC_NUMBERS (elf_bpf_reloc_type)\n * It is kept in this file to remind that the value is already taken. */\n RELOC_NUMBER (R_BPF_64_NODYLD32, \t\t4)\n RELOC_NUMBER (R_BPF_64_32, \t\t10)\n+ RELOC_NUMBER (R_BPF_GNU_64_16, 256)\n END_RELOC_NUMBERS (R_BPF_max)\n \n #endif /* _ELF_BPF_H */\ndiff --git a/include/opcode/bpf.h b/include/opcode/bpf.h\nnew file mode 100644\nindex 00000000000..f928979f86f\n--- /dev/null\n+++ b/include/opcode/bpf.h\n@@ -0,0 +1,306 @@\n+/* bpf.h - BPF opcode list for binutils.\n+ Copyright (C) 2023 Free Software Foundation, Inc.\n+\n+ Contributed by Oracle Inc.\n+\n+ This file is part of the GNU binutils.\n+\n+ This is free software; you can redistribute them and/or modify them\n+ under the terms of the GNU General Public License as published by\n+ the Free Software Foundation; either version 3, or (at your option)\n+ any later version.\n+\n+ This program is distributed in the hope that it will be useful, but\n+ WITHOUT ANY WARRANTY; without even the implied warranty of\n+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU\n+ General Public License for more details.\n+\n+ You should have received a copy of the GNU General Public License\n+ along with this program; see the file COPYING3. If not,\n+ see . */\n+\n+#ifndef _BPF_H_\n+#define _BPF_H_\n+\n+#include \n+\n+/* The BPF ISA has little-endian and big-endian variants. */\n+\n+enum bpf_endian\n+{\n+ BPF_ENDIAN_LITTLE,\n+ BPF_ENDIAN_BIG\n+};\n+\n+/* Most BPF instructions are conformed by a single 64-bit instruction\n+ word. The lddw instruction is conformed by two consecutive 64-bit\n+ instruction words. */\n+\n+typedef uint64_t bpf_insn_word;\n+\n+/* There are several versions of the BPF ISA. */\n+\n+#define BPF_V1 0x1\n+#define BPF_V2 0x2\n+#define BPF_V3 0x3\n+#define BPF_V4 0x4\n+#define BPF_XBPF 0xff\n+\n+/* Masks for the several instruction fields in a BPF instruction.\n+ These assume big-endian BPF instructions. */\n+\n+#define BPF_CODE 0xff00000000000000UL\n+#define BPF_REGS 0x00ff000000000000UL\n+#define BPF_DST 0x00f0000000000000UL\n+#define BPF_SRC 0x000f000000000000UL\n+#define BPF_OFFSET16 0x0000ffff00000000UL\n+#define BPF_IMM32 0x00000000ffffffffUL\n+\n+/* The BPF opcode instruction field is eight bits long and its\n+ interpretation depends on the instruction class.\n+\n+ For arithmetic and jump instructions the 8-bit opcode field is\n+ subdivided in:\n+\n+ op-code:4 op-src:1 op-class:3\n+\n+ For load/store instructions, the 8-bit opcode field is subdivided\n+ in:\n+\n+ op-mode:3 op-size:2 op-class:3\n+\n+ All the constants defined below are to be applied on the first\n+ 64-bit word of a BPF instruction. Please define them assuming\n+ big-endian instructions; the matching and writing routines using\n+ the instruction table know how to handle the endianness groups. */\n+\n+#define BPF_SRC_X ((uint64_t)0x08 << 56)\n+#define BPF_SRC_K ((uint64_t)0x00 << 56)\n+\n+#define BPF_CODE_ADD ((uint64_t)0x00 << 56)\n+#define BPF_CODE_SUB ((uint64_t)0x10 << 56)\n+#define BPF_CODE_MUL ((uint64_t)0x20 << 56)\n+#define BPF_CODE_DIV ((uint64_t)0x30 << 56)\n+#define BPF_CODE_OR ((uint64_t)0x40 << 56)\n+#define BPF_CODE_AND ((uint64_t)0x50 << 56)\n+#define BPF_CODE_LSH ((uint64_t)0x60 << 56)\n+#define BPF_CODE_RSH ((uint64_t)0x70 << 56)\n+#define BPF_CODE_NEG ((uint64_t)0x80 << 56)\n+#define BPF_CODE_MOD ((uint64_t)0x90 << 56)\n+#define BPF_CODE_XOR ((uint64_t)0xa0 << 56)\n+#define BPF_CODE_MOV ((uint64_t)0xb0 << 56)\n+#define BPF_CODE_ARSH ((uint64_t)0xc0 << 56)\n+#define BPF_CODE_END ((uint64_t)0xd0 << 56)\n+\n+#define BPF_CODE_JA ((uint64_t)0x00 << 56)\n+#define BPF_CODE_JEQ ((uint64_t)0x10 << 56)\n+#define BPF_CODE_JGT ((uint64_t)0x20 << 56)\n+#define BPF_CODE_JGE ((uint64_t)0x30 << 56)\n+#define BPF_CODE_JSET ((uint64_t)0x40 << 56)\n+#define BPF_CODE_JNE ((uint64_t)0x50 << 56)\n+#define BPF_CODE_JSGT ((uint64_t)0x60 << 56)\n+#define BPF_CODE_JSGE ((uint64_t)0x70 << 56)\n+#define BPF_CODE_CALL ((uint64_t)0x80 << 56)\n+#define BPF_CODE_EXIT ((uint64_t)0x90 << 56)\n+#define BPF_CODE_JLT ((uint64_t)0xa0 << 56)\n+#define BPF_CODE_JLE ((uint64_t)0xb0 << 56)\n+#define BPF_CODE_JSLT ((uint64_t)0xc0 << 56)\n+#define BPF_CODE_JSLE ((uint64_t)0xd0 << 56)\n+\n+#define BPF_MODE_IMM ((uint64_t)0x00 << 56)\n+#define BPF_MODE_ABS ((uint64_t)0x20 << 56)\n+#define BPF_MODE_IND ((uint64_t)0x40 << 56)\n+#define BPF_MODE_MEM ((uint64_t)0x60 << 56)\n+#define BPF_MODE_ATOMIC ((uint64_t)0xc0 << 56)\n+\n+#define BPF_SIZE_W ((uint64_t)0x00 << 56)\n+#define BPF_SIZE_H ((uint64_t)0x08 << 56)\n+#define BPF_SIZE_B ((uint64_t)0x10 << 56)\n+#define BPF_SIZE_DW ((uint64_t)0x18 << 56)\n+\n+#define BPF_CLASS_LD ((uint64_t)0x00 << 56)\n+#define BPF_CLASS_LDX ((uint64_t)0x01 << 56)\n+#define BPF_CLASS_ST ((uint64_t)0x02 << 56)\n+#define BPF_CLASS_STX ((uint64_t)0x03 << 56)\n+#define BPF_CLASS_ALU ((uint64_t)0x04 << 56)\n+#define BPF_CLASS_JMP ((uint64_t)0x05 << 56)\n+#define BPF_CLASS_JMP32 ((uint64_t)0x06 << 56)\n+#define BPF_CLASS_ALU64 ((uint64_t)0x07 << 56)\n+\n+/* Certain instructions (ab)use other instruction fields as opcodes,\n+ even if these are multi-byte or infra-byte. Bleh. */\n+\n+#define BPF_OFFSET16_SDIVMOD ((uint64_t)0x1 << 32)\n+\n+#define BPF_IMM32_END16 ((uint64_t)0x00000010)\n+#define BPF_IMM32_END32 ((uint64_t)0x00000020)\n+#define BPF_IMM32_END64 ((uint64_t)0x00000040)\n+\n+#define BPF_IMM32_AADD ((uint64_t)0x00000000)\n+#define BPF_IMM32_AOR ((uint64_t)0x00000040)\n+#define BPF_IMM32_AAND ((uint64_t)0x00000050)\n+#define BPF_IMM32_AXOR ((uint64_t)0x000000a0)\n+#define BPF_IMM32_AFADD ((uint64_t)0x00000001)\n+#define BPF_IMM32_AFOR ((uint64_t)0x00000041)\n+#define BPF_IMM32_AFAND ((uint64_t)0x00000051)\n+#define BPF_IMM32_AFXOR ((uint64_t)0x000000a1)\n+#define BPF_IMM32_AXCHG ((uint64_t)0x000000e1)\n+#define BPF_IMM32_ACMP ((uint64_t)b0x000000f1)\n+\n+/* Unique identifiers for BPF instructions. */\n+\n+enum bpf_insn_id\n+{\n+ BPF_NOINSN = 0,\n+ /* 64-bit load instruction. */\n+ BPF_INSN_LDDW,\n+ /* ALU instructions. */\n+ BPF_INSN_ADDR, BPF_INSN_ADDI, BPF_INSN_SUBR, BPF_INSN_SUBI,\n+ BPF_INSN_MULR, BPF_INSN_MULI, BPF_INSN_SDIVR, BPF_INSN_SDIVI,\n+ BPF_INSN_SMODR, BPF_INSN_SMODI, BPF_INSN_DIVR, BPF_INSN_DIVI,\n+ BPF_INSN_MODR, BPF_INSN_MODI, BPF_INSN_ORR, BPF_INSN_ORI,\n+ BPF_INSN_ANDR, BPF_INSN_ANDI, BPF_INSN_XORR, BPF_INSN_XORI,\n+ BPF_INSN_NEGR, BPF_INSN_NEGI, BPF_INSN_LSHR, BPF_INSN_LSHI,\n+ BPF_INSN_RSHR, BPF_INSN_RSHI, BPF_INSN_ARSHR, BPF_INSN_ARSHI,\n+ BPF_INSN_MOVR, BPF_INSN_MOVI,\n+ /* ALU32 instructions. */\n+ BPF_INSN_ADD32R, BPF_INSN_ADD32I, BPF_INSN_SUB32R, BPF_INSN_SUB32I,\n+ BPF_INSN_MUL32R, BPF_INSN_MUL32I, BPF_INSN_SDIV32R, BPF_INSN_SDIV32I,\n+ BPF_INSN_SMOD32R, BPF_INSN_SMOD32I, BPF_INSN_DIV32R, BPF_INSN_DIV32I,\n+ BPF_INSN_MOD32R, BPF_INSN_MOD32I, BPF_INSN_OR32R, BPF_INSN_OR32I,\n+ BPF_INSN_AND32R, BPF_INSN_AND32I, BPF_INSN_XOR32R, BPF_INSN_XOR32I,\n+ BPF_INSN_NEG32R, BPF_INSN_NEG32I, BPF_INSN_LSH32R, BPF_INSN_LSH32I,\n+ BPF_INSN_RSH32R, BPF_INSN_RSH32I, BPF_INSN_ARSH32R, BPF_INSN_ARSH32I,\n+ BPF_INSN_MOV32R, BPF_INSN_MOV32I,\n+ /* Endianness conversion instructions. */\n+ BPF_INSN_ENDLE16, BPF_INSN_ENDLE32, BPF_INSN_ENDLE64,\n+ BPF_INSN_ENDBE16, BPF_INSN_ENDBE32, BPF_INSN_ENDBE64,\n+ /* Absolute load instructions. */\n+ BPF_INSN_LDABSB, BPF_INSN_LDABSH, BPF_INSN_LDABSW, BPF_INSN_LDABSDW,\n+ /* Indirect load instructions. */\n+ BPF_INSN_LDINDB, BPF_INSN_LDINDH, BPF_INSN_LDINDW, BPF_INSN_LDINDDW,\n+ /* Generic load instructions (to register.) */\n+ BPF_INSN_LDXB, BPF_INSN_LDXH, BPF_INSN_LDXW, BPF_INSN_LDXDW,\n+ /* Generic store instructions (from register.) */\n+ BPF_INSN_STXBR, BPF_INSN_STXHR, BPF_INSN_STXWR, BPF_INSN_STXDWR,\n+ BPF_INSN_STXBI, BPF_INSN_STXHI, BPF_INSN_STXWI, BPF_INSN_STXDWI,\n+ /* Compare-and-jump instructions (reg OP reg.) */\n+ BPF_INSN_JAR, BPF_INSN_JEQR, BPF_INSN_JGTR, BPF_INSN_JSGTR,\n+ BPF_INSN_JGER, BPF_INSN_JSGER, BPF_INSN_JLTR, BPF_INSN_JSLTR,\n+ BPF_INSN_JSLER, BPF_INSN_JLER, BPF_INSN_JSETR, BPF_INSN_JNER,\n+ BPF_INSN_CALLR, BPF_INSN_CALL, BPF_INSN_EXIT,\n+ /* Compare-and-jump instructions (reg OP imm.) */\n+ BPF_INSN_JEQI, BPF_INSN_JGTI, BPF_INSN_JSGTI,\n+ BPF_INSN_JGEI, BPF_INSN_JSGEI, BPF_INSN_JLTI, BPF_INSN_JSLTI,\n+ BPF_INSN_JSLEI, BPF_INSN_JLEI, BPF_INSN_JSETI, BPF_INSN_JNEI,\n+ BPF_INSN_CALLI,\n+ /* 32-bit compare-and-jump instructions (reg OP reg.) */\n+ BPF_INSN_JEQ32R, BPF_INSN_JGT32R, BPF_INSN_JSGT32R,\n+ BPF_INSN_JGE32R, BPF_INSN_JSGE32R, BPF_INSN_JLT32R, BPF_INSN_JSLT32R,\n+ BPF_INSN_JSLE32R, BPF_INSN_JLE32R, BPF_INSN_JSET32R, BPF_INSN_JNE32R,\n+ /* 32-bit compare-and-jump instructions (reg OP imm.) */\n+ BPF_INSN_JEQ32I, BPF_INSN_JGT32I, BPF_INSN_JSGT32I,\n+ BPF_INSN_JGE32I, BPF_INSN_JSGE32I, BPF_INSN_JLT32I, BPF_INSN_JSLT32I,\n+ BPF_INSN_JSLE32I, BPF_INSN_JLE32I, BPF_INSN_JSET32I, BPF_INSN_JNE32I,\n+ /* Atomic instructions. */\n+ BPF_INSN_AADD, BPF_INSN_AOR, BPF_INSN_AAND, BPF_INSN_AXOR,\n+ /* Atomic instructions with fetching. */\n+ BPF_INSN_AFADD, BPF_INSN_AFOR, BPF_INSN_AFAND, BPF_INSN_AFXOR,\n+ /* Atomic instructions (32-bit.) */\n+ BPF_INSN_AADD32, BPF_INSN_AOR32, BPF_INSN_AAND32, BPF_INSN_AXOR32,\n+ /* Atomic instructions with fetching (32-bit.) */\n+ BPF_INSN_AFADD32, BPF_INSN_AFOR32, BPF_INSN_AFAND32, BPF_INSN_AFXOR32,\n+ /* GNU simulator specific instruction. */\n+ BPF_INSN_BRKPT,\n+};\n+\n+/* Entry for a BPF instruction in the opcodes table. */\n+\n+struct bpf_opcode\n+{\n+ /* Unique numerical code for the instruction. */\n+ enum bpf_insn_id id;\n+\n+ /* The instruction template defines both the syntax of the\n+ instruction and the set of the different operands that appear in\n+ the instruction.\n+\n+ Tags:\n+ %% - literal %.\n+ %dr - destination 64-bit register.\n+ %dw - destination 32-bit register.\n+ %sr - source 64-bit register.\n+ %sw - source 32-bit register.\n+ %d32 - 32-bit signed displacement (in 64-bit words minus one.)\n+ %d16 - 16-bit signed displacement (in 64-bit words minus one.)\n+ %o16 - 16-bit signed offset (in bytes.)\n+ %i32 - 32-bit signed immediate.\n+ %I32 - Like %i32.\n+ %i64 - 64-bit signed immediate.\n+ %w - expect zero or more white spaces and print a single space.\n+ %W - expect one or more white spaces and print a single space.\n+\n+ When parsing and printing %o16 and %I32 (but not %i32) an\n+ explicit sign is always expected and included. Therefore, to\n+ denote something like `[%r3 + 10]', please use a template like `[\n+ %sr %o16]' instead of `[ %sr + %o16 ]'.\n+ \n+ If %dr, %dw, %sr or %sw are found multiple times in a template,\n+ they refer to the same register, i.e. `%rd = le64 %rd' denotes\n+ `r2 = le64 r2', but not `r2 = le64 r1'.\n+\n+ If %i64 appears in a template then the instruction is 128-bits\n+ long and composed by two consecutive 64-bit instruction words.\n+\n+ A white space character means to expect zero or more white\n+ spaces, and to print no space.\n+\n+ There are two templates defined per instruction, corresponding to\n+ two used different dialects: a \"normal\" assembly-like syntax and\n+ a \"pseudo-c\" syntax. Some toolchains support just one of these\n+ dialects. The GNU Toolchain supports both. */\n+ const char *normal;\n+ const char *pseudoc;\n+\n+ /* The version that introduced this instruction. Instructions are\n+ generally not removed once they get introduced. */\n+ uint8_t version;\n+\n+ /* Maks marking the opcode fields in the instruction, and the\n+ opcodes characterizing it.\n+\n+ In multi-word instructions these apply to the first word in the\n+ instruction. Note that these values assumes big-endian\n+ instructions; code using these field must be aware of the\n+ endianness groups to which BPF instructions must conform to and\n+ DTRT. */\n+ bpf_insn_word mask;\n+ bpf_insn_word opcode;\n+};\n+\n+/* Try to match a BPF instruction given its first instruction word.\n+ If no matching instruction is found, return NULL. */\n+\n+const struct bpf_opcode *bpf_match_insn (bpf_insn_word word,\n+ enum bpf_endian endian,\n+ int version);\n+\n+/* Operand extractors.\n+\n+ These all get big-endian instruction words. Note how the extractor\n+ for 64-bit signed immediates requires two instruction words. */\n+\n+uint8_t bpf_extract_src (bpf_insn_word word, enum bpf_endian endian);\n+uint8_t bpf_extract_dst (bpf_insn_word word, enum bpf_endian endian);\n+int16_t bpf_extract_offset16 (bpf_insn_word word, enum bpf_endian endian);\n+int32_t bpf_extract_imm32 (bpf_insn_word word, enum bpf_endian endian);\n+int64_t bpf_extract_imm64 (bpf_insn_word word1, bpf_insn_word word2,\n+ enum bpf_endian endian);\n+\n+/* Get the opcode occupying the INDEX position in the opcodes table.\n+ The INDEX is zero based. If the provided index overflows the\n+ opcodes table then NULL is returned. */\n+\n+const struct bpf_opcode *bpf_get_opcode (unsigned int index);\n+\n+#endif /* !_BPF_H_ */\ndiff --git a/ld/testsuite/ld-bpf/call-1.d b/ld/testsuite/ld-bpf/call-1.d\nindex aad51d5cedc..ae455882e0f 100644\n--- a/ld/testsuite/ld-bpf/call-1.d\n+++ b/ld/testsuite/ld-bpf/call-1.d\n@@ -1,7 +1,7 @@\n-#as: --EL\n+#as: --EL -mdialect=normal\n #source: foo.s\n #source: bar.s\n-#objdump: -dr\n+#objdump: -dr -M dec\n #ld: -EL\n #name: CALL with 64_32 reloc\n \ndiff --git a/ld/testsuite/ld-bpf/call-2.d b/ld/testsuite/ld-bpf/call-2.d\nindex 3d09095f6be..d00fabaa9b1 100644\n--- a/ld/testsuite/ld-bpf/call-2.d\n+++ b/ld/testsuite/ld-bpf/call-2.d\n@@ -1,7 +1,7 @@\n #as: --EL\n #source: call-2.s\n #source: bar.s\n-#objdump: -dr\n+#objdump: -dr -M dec\n #ld: -EL\n #name: CALL with disp32 reloc and addend\n \ndiff --git a/ld/testsuite/ld-bpf/reloc-insn-external-be.d b/ld/testsuite/ld-bpf/reloc-insn-external-be.d\nindex 455daa701f7..b22ebbd99a2 100644\n--- a/ld/testsuite/ld-bpf/reloc-insn-external-be.d\n+++ b/ld/testsuite/ld-bpf/reloc-insn-external-be.d\n@@ -1,7 +1,7 @@\n-#as: --EB\n+#as: -EB -mdialect=normal\n #source: reloc-data.s\n #source: reloc-insn-external.s\n-#objdump: -dr\n+#objdump: -dr -M hex\n #ld: -Tdata=0x20 -EB\n #name: reloc insn external BE\n \ndiff --git a/ld/testsuite/ld-bpf/reloc-insn-external-le.d b/ld/testsuite/ld-bpf/reloc-insn-external-le.d\nindex 51066388e84..ba9c305851d 100644\n--- a/ld/testsuite/ld-bpf/reloc-insn-external-le.d\n+++ b/ld/testsuite/ld-bpf/reloc-insn-external-le.d\n@@ -1,7 +1,7 @@\n-#as: --EL\n+#as: -EL -mdialect=normal\n #source: reloc-data.s\n #source: reloc-insn-external.s\n-#objdump: -dr\n+#objdump: -dr -M hex\n #ld: -Tdata=0x20 -EL\n #name: reloc insn external LE\n \ndiff --git a/opcodes/Makefile.am b/opcodes/Makefile.am\nindex 578fdc056c5..7cc16d58cbc 100644\n--- a/opcodes/Makefile.am\n+++ b/opcodes/Makefile.am\n@@ -59,7 +59,6 @@ BUILD_LIB_DEPS = @BUILD_LIB_DEPS@\n # Header files.\n HFILES = \\\n \taarch64-asm.h aarch64-dis.h aarch64-opc.h aarch64-tbl.h \\\n-\tbpf-desc.h bpf-opc.h \\\n \tcris-desc.h cris-opc.h \\\n \tepiphany-desc.h epiphany-opc.h \\\n \tfr30-desc.h fr30-opc.h \\\n@@ -94,10 +93,6 @@ TARGET64_LIBOPCODES_CFILES = \\\n \taarch64-opc-2.c \\\n \talpha-dis.c \\\n \talpha-opc.c \\\n-\tbpf-asm.c \\\n-\tbpf-desc.c \\\n-\tbpf-dis.c \\\n-\tbpf-ibld.c \\\n \tbpf-opc.c \\\n \tia64-dis.c \\\n \tia64-opc.c \\\n@@ -352,7 +347,6 @@ CGENDEPS = \\\n CGEN_CPUS = cris epiphany fr30 frv ip2k iq2000 lm32 m32c m32r mep mt or1k xstormy16\n \n if CGEN_MAINT\n-BPF_DEPS = stamp-bpf\n CRIS_DEPS = stamp-cris\n EPIPHANY_DEPS = stamp-epiphany\n FR30_DEPS = stamp-fr30\n@@ -367,7 +361,6 @@ MT_DEPS = stamp-mt\n OR1K_DEPS = stamp-or1k\n XSTORMY16_DEPS = stamp-xstormy16\n else\n-BPF_DEPS =\n CRIS_DEPS =\n EPIPHANY_DEPS =\n FR30_DEPS =\n@@ -400,15 +393,6 @@ run-cgen-all:\n \n # For now, require developers to configure with --enable-cgen-maint.\n \n-$(srcdir)/bpf-desc.h $(srcdir)/bpf-desc.c $(srcdir)/bpf-opc.h \\\n-\t\t$(srcdir)/bpf-opc.c $(srcdir)/bpf-ibld.c \\\n-\t\t$(srcdir)/bpf-asm.c $(srcdir)/bpf-dis.c: $(BPF_DEPS)\n-\t@true\n-\n-stamp-bpf: $(CGENDEPS) $(CPUDIR)/bpf.cpu $(CPUDIR)/bpf.opc\n-\t$(MAKE) run-cgen arch=bpf prefix=bpf \\\n-\t\tarchfile=$(CPUDIR)/bpf.cpu opcfile=$(CPUDIR)/bpf.opc\n-\n $(srcdir)/cris-desc.h $(srcdir)/cris-desc.c $(srcdir)/cris-opc.h: $(CRIS_DEPS)\n \t@true\n \ndiff --git a/opcodes/Makefile.in b/opcodes/Makefile.in\nindex 2db307e8d7c..dcd0e9f2dce 100644\n--- a/opcodes/Makefile.in\n+++ b/opcodes/Makefile.in\n@@ -450,7 +450,6 @@ BFD_H = ../bfd/bfd.h\n # Header files.\n HFILES = \\\n \taarch64-asm.h aarch64-dis.h aarch64-opc.h aarch64-tbl.h \\\n-\tbpf-desc.h bpf-opc.h \\\n \tcris-desc.h cris-opc.h \\\n \tepiphany-desc.h epiphany-opc.h \\\n \tfr30-desc.h fr30-opc.h \\\n@@ -486,10 +485,6 @@ TARGET64_LIBOPCODES_CFILES = \\\n \taarch64-opc-2.c \\\n \talpha-dis.c \\\n \talpha-opc.c \\\n-\tbpf-asm.c \\\n-\tbpf-desc.c \\\n-\tbpf-dis.c \\\n-\tbpf-ibld.c \\\n \tbpf-opc.c \\\n \tia64-dis.c \\\n \tia64-opc.c \\\n@@ -708,8 +703,6 @@ CGENDEPS = \\\n \tcgen-asm.in cgen-dis.in cgen-ibld.in\n \n CGEN_CPUS = cris epiphany fr30 frv ip2k iq2000 lm32 m32c m32r mep mt or1k xstormy16\n-@CGEN_MAINT_FALSE@BPF_DEPS = \n-@CGEN_MAINT_TRUE@BPF_DEPS = stamp-bpf\n @CGEN_MAINT_FALSE@CRIS_DEPS = \n @CGEN_MAINT_TRUE@CRIS_DEPS = stamp-cris\n @CGEN_MAINT_FALSE@EPIPHANY_DEPS = \n@@ -883,10 +876,6 @@ distclean-compile:\n @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/arm-dis.Plo@am__quote@\n @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/avr-dis.Plo@am__quote@\n @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/bfin-dis.Plo@am__quote@\n-@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/bpf-asm.Plo@am__quote@\n-@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/bpf-desc.Plo@am__quote@\n-@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/bpf-dis.Plo@am__quote@\n-@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/bpf-ibld.Plo@am__quote@\n @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/bpf-opc.Plo@am__quote@\n @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cgen-asm.Plo@am__quote@\n @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cgen-bitset.Plo@am__quote@\n@@ -1385,15 +1374,6 @@ run-cgen-all:\n \n # For now, require developers to configure with --enable-cgen-maint.\n \n-$(srcdir)/bpf-desc.h $(srcdir)/bpf-desc.c $(srcdir)/bpf-opc.h \\\n-\t\t$(srcdir)/bpf-opc.c $(srcdir)/bpf-ibld.c \\\n-\t\t$(srcdir)/bpf-asm.c $(srcdir)/bpf-dis.c: $(BPF_DEPS)\n-\t@true\n-\n-stamp-bpf: $(CGENDEPS) $(CPUDIR)/bpf.cpu $(CPUDIR)/bpf.opc\n-\t$(MAKE) run-cgen arch=bpf prefix=bpf \\\n-\t\tarchfile=$(CPUDIR)/bpf.cpu opcfile=$(CPUDIR)/bpf.opc\n-\n $(srcdir)/cris-desc.h $(srcdir)/cris-desc.c $(srcdir)/cris-opc.h: $(CRIS_DEPS)\n \t@true\n \ndiff --git a/opcodes/bpf-dis.c b/opcodes/bpf-dis.c\nindex 0a345179569..a4dc3dc2523 100644\n--- a/opcodes/bpf-dis.c\n+++ b/opcodes/bpf-dis.c\n@@ -1,631 +1,284 @@\n-/* DO NOT EDIT! -*- buffer-read-only: t -*- vi:set ro: */\n-/* Disassembler interface for targets using CGEN. -*- C -*-\n- CGEN: Cpu tools GENerator\n+/* bpf-dis.c - BPF disassembler.\n+ Copyright (C) 2023 Free Software Foundation, Inc.\n \n- THIS FILE IS MACHINE GENERATED WITH CGEN.\n- - the resultant file is machine generated, cgen-dis.in isn't\n+ Contributed by Oracle Inc.\n \n- Copyright (C) 1996-2023 Free Software Foundation, Inc.\n+ This file is part of the GNU binutils.\n \n- This file is part of libopcodes.\n-\n- This library is free software; you can redistribute it and/or modify\n- it under the terms of the GNU General Public License as published by\n+ This is free software; you can redistribute them and/or modify them\n+ under the terms of the GNU General Public License as published by\n the Free Software Foundation; either version 3, or (at your option)\n any later version.\n \n- It is distributed in the hope that it will be useful, but WITHOUT\n- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\n- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public\n- License for more details.\n+ This program is distributed in the hope that it will be useful, but\n+ WITHOUT ANY WARRANTY; without even the implied warranty of\n+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU\n+ General Public License for more details.\n \n You should have received a copy of the GNU General Public License\n- along with this program; if not, write to the Free Software Foundation, Inc.,\n- 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */\n-\n-/* ??? Eventually more and more of this stuff can go to cpu-independent files.\n- Keep that in mind. */\n+ along with this program; see the file COPYING3. If not,\n+ see . */\n \n #include \"sysdep.h\"\n-#include \n-#include \"ansidecl.h\"\n #include \"disassemble.h\"\n-#include \"bfd.h\"\n-#include \"symcat.h\"\n #include \"libiberty.h\"\n-#include \"bpf-desc.h\"\n-#include \"bpf-opc.h\"\n #include \"opintl.h\"\n+#include \"opcode/bpf.h\"\n \n-/* Default text to print if an instruction isn't recognized. */\n-#define UNKNOWN_INSN_MSG _(\"*unknown*\")\n-\n-static void print_normal\n- (CGEN_CPU_DESC, void *, long, unsigned int, bfd_vma, int);\n-static void print_address\n- (CGEN_CPU_DESC, void *, bfd_vma, unsigned int, bfd_vma, int) ATTRIBUTE_UNUSED;\n-static void print_keyword\n- (CGEN_CPU_DESC, void *, CGEN_KEYWORD *, long, unsigned int) ATTRIBUTE_UNUSED;\n-static void print_insn_normal\n- (CGEN_CPU_DESC, void *, const CGEN_INSN *, CGEN_FIELDS *, bfd_vma, int);\n-static int print_insn\n- (CGEN_CPU_DESC, bfd_vma, disassemble_info *, bfd_byte *, unsigned);\n-static int default_print_insn\n- (CGEN_CPU_DESC, bfd_vma, disassemble_info *) ATTRIBUTE_UNUSED;\n-static int read_insn\n- (CGEN_CPU_DESC, bfd_vma, disassemble_info *, bfd_byte *, int, CGEN_EXTRACT_INFO *,\n- unsigned long *);\n-\f\n-/* -- disassembler routines inserted here. */\n-\n-/* -- dis.c */\n-\n-/* We need to customize the disassembler a bit:\n- - Use 8 bytes per line by default.\n-*/\n-\n-#define CGEN_PRINT_INSN bpf_print_insn\n-\n-static int\n-bpf_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info)\n-{\n- bfd_byte buf[CGEN_MAX_INSN_SIZE];\n- int buflen;\n- int status;\n-\n- info->bytes_per_chunk = 1;\n- info->bytes_per_line = 8;\n-\n- /* Attempt to read the base part of the insn. */\n- buflen = cd->base_insn_bitsize / 8;\n- status = (*info->read_memory_func) (pc, buf, buflen, info);\n-\n- /* Try again with the minimum part, if min < base. */\n- if (status != 0 && (cd->min_insn_bitsize < cd->base_insn_bitsize))\n- {\n- buflen = cd->min_insn_bitsize / 8;\n- status = (*info->read_memory_func) (pc, buf, buflen, info);\n- }\n-\n- if (status != 0)\n- {\n- (*info->memory_error_func) (status, pc, info);\n- return -1;\n- }\n-\n- return print_insn (cd, pc, info, buf, buflen);\n-}\n+#include \n+#include \n \n-/* Signed immediates should be printed in hexadecimal. */\n+/* This disassembler supports two different syntaxes for BPF assembly.\n+ One is called \"normal\" and has the typical form for assembly\n+ languages, with mnemonics and the like. The othe is called\n+ \"pseudoc\" and looks like C. */\n \n-static void\n-print_immediate (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,\n- void *dis_info,\n- int64_t value,\n- unsigned int attrs ATTRIBUTE_UNUSED,\n- bfd_vma pc ATTRIBUTE_UNUSED,\n- int length ATTRIBUTE_UNUSED)\n+enum bpf_dialect\n {\n- disassemble_info *info = (disassemble_info *) dis_info;\n-\n- if (value <= 9)\n- (*info->fprintf_func) (info->stream, \"%\" PRId64, value);\n- else\n- (*info->fprintf_func) (info->stream, \"%#\" PRIx64, value);\n-\n- /* This is to avoid -Wunused-function for print_normal. */\n- if (0)\n- print_normal (cd, dis_info, value, attrs, pc, length);\n-}\n-\n-/* Endianness bit sizes should be printed in decimal. */\n-\n-static void\n-print_endsize (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,\n- void *dis_info,\n- unsigned long value,\n- unsigned int attrs ATTRIBUTE_UNUSED,\n- bfd_vma pc ATTRIBUTE_UNUSED,\n- int length ATTRIBUTE_UNUSED)\n-{\n- disassemble_info *info = (disassemble_info *) dis_info;\n- (*info->fprintf_func) (info->stream, \"%lu\", value);\n-}\n-\n-\f\n-/* -- */\n-\n-void bpf_cgen_print_operand\n- (CGEN_CPU_DESC, int, void *, CGEN_FIELDS *, void const *, bfd_vma, int);\n+ BPF_DIALECT_NORMAL,\n+ BPF_DIALECT_PSEUDOC\n+};\n \n-/* Main entry point for printing operands.\n- XINFO is a `void *' and not a `disassemble_info *' to not put a requirement\n- of dis-asm.h on cgen.h.\n+/* Global configuration for the disassembler. */\n \n- This function is basically just a big switch statement. Earlier versions\n- used tables to look up the function to use, but\n- - if the table contains both assembler and disassembler functions then\n- the disassembler contains much of the assembler and vice-versa,\n- - there's a lot of inlining possibilities as things grow,\n- - using a switch statement avoids the function call overhead.\n+static enum bpf_dialect asm_dialect = BPF_DIALECT_NORMAL;\n+static int asm_bpf_version = BPF_V4;\n+static int asm_obase = 10;\n \n- This function could be moved into `print_insn_normal', but keeping it\n- separate makes clear the interface between `print_insn_normal' and each of\n- the handlers. */\n+/* Print BPF specific command-line options. */\n \n void\n-bpf_cgen_print_operand (CGEN_CPU_DESC cd,\n-\t\t\t int opindex,\n-\t\t\t void * xinfo,\n-\t\t\t CGEN_FIELDS *fields,\n-\t\t\t void const *attrs ATTRIBUTE_UNUSED,\n-\t\t\t bfd_vma pc,\n-\t\t\t int length)\n+print_bpf_disassembler_options (FILE *stream)\n {\n- disassemble_info *info = (disassemble_info *) xinfo;\n-\n- switch (opindex)\n- {\n- case BPF_OPERAND_DISP16 :\n- print_normal (cd, info, fields->f_offset16, 0|(1<f_imm32, 0|(1<f_dstbe, 0);\n- break;\n- case BPF_OPERAND_DSTLE :\n- print_keyword (cd, info, & bpf_cgen_opval_h_gpr, fields->f_dstle, 0);\n- break;\n- case BPF_OPERAND_ENDSIZE :\n- print_endsize (cd, info, fields->f_imm32, 0, pc, length);\n- break;\n- case BPF_OPERAND_IMM32 :\n- print_immediate (cd, info, fields->f_imm32, 0|(1<f_imm64, 0|(1<f_offset16, 0|(1<f_srcbe, 0);\n- break;\n- case BPF_OPERAND_SRCLE :\n- print_keyword (cd, info, & bpf_cgen_opval_h_gpr, fields->f_srcle, 0);\n- break;\n-\n- default :\n- /* xgettext:c-format */\n- opcodes_error_handler\n-\t(_(\"internal error: unrecognized field %d while printing insn\"),\n-\t opindex);\n- abort ();\n- }\n+ fprintf (stream, _(\"\\n\\\n+The following BPF specific disassembler options are supported for use\\n\\\n+with the -M switch (multiple options should be separated by commas):\\n\"));\n+ fprintf (stream, \"\\n\");\n+ fprintf (stream, _(\"\\\n+ pseudoc Use pseudo-c syntax.\\n\\\n+ v1,v2,v3,v4,xbpf Version of the BPF ISA to use.\\n\\\n+ hex,oct,dec Output numerical base for immediates.\\n\"));\n }\n \n-cgen_print_fn * const bpf_cgen_print_handlers[] =\n-{\n- print_insn_normal,\n-};\n-\n-\n-void\n-bpf_cgen_init_dis (CGEN_CPU_DESC cd)\n-{\n- bpf_cgen_init_opcode_table (cd);\n- bpf_cgen_init_ibld_table (cd);\n- cd->print_handlers = & bpf_cgen_print_handlers[0];\n- cd->print_operand = bpf_cgen_print_operand;\n-}\n-\n-\f\n-/* Default print handler. */\n+/* Parse BPF specific command-line options. */\n \n static void\n-print_normal (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,\n-\t void *dis_info,\n-\t long value,\n-\t unsigned int attrs,\n-\t bfd_vma pc ATTRIBUTE_UNUSED,\n-\t int length ATTRIBUTE_UNUSED)\n+parse_bpf_dis_option (const char *option)\n {\n- disassemble_info *info = (disassemble_info *) dis_info;\n-\n- /* Print the operand as directed by the attributes. */\n- if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY))\n- ; /* nothing to do */\n- else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED))\n- (*info->fprintf_func) (info->stream, \"%ld\", value);\n+ if (strcmp (option, \"pseudoc\") == 0)\n+ asm_dialect = BPF_DIALECT_PSEUDOC;\n+ else if (strcmp (option, \"v1\") == 0)\n+ asm_bpf_version = BPF_V1;\n+ else if (strcmp (option, \"v2\") == 0)\n+ asm_bpf_version = BPF_V2;\n+ else if (strcmp (option, \"v3\") == 0)\n+ asm_bpf_version = BPF_V3;\n+ else if (strcmp (option, \"v4\") == 0)\n+ asm_bpf_version = BPF_V4;\n+ else if (strcmp (option, \"xbpf\") == 0)\n+ asm_bpf_version = BPF_XBPF;\n+ else if (strcmp (option, \"hex\") == 0)\n+ asm_obase = 16;\n+ else if (strcmp (option, \"oct\") == 0)\n+ asm_obase = 8;\n+ else if (strcmp (option, \"dec\") == 0)\n+ asm_obase = 10;\n else\n- (*info->fprintf_func) (info->stream, \"0x%lx\", value);\n+ /* xgettext:c-format */\n+ opcodes_error_handler (_(\"unrecognized disassembler option: %s\"), option);\n }\n \n-/* Default address handler. */\n-\n static void\n-print_address (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,\n-\t void *dis_info,\n-\t bfd_vma value,\n-\t unsigned int attrs,\n-\t bfd_vma pc ATTRIBUTE_UNUSED,\n-\t int length ATTRIBUTE_UNUSED)\n+parse_bpf_dis_options (const char *opts_in)\n {\n- disassemble_info *info = (disassemble_info *) dis_info;\n-\n- /* Print the operand as directed by the attributes. */\n- if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY))\n- ; /* Nothing to do. */\n- else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_PCREL_ADDR))\n- (*info->print_address_func) (value, info);\n- else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_ABS_ADDR))\n- (*info->print_address_func) (value, info);\n- else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED))\n- (*info->fprintf_func) (info->stream, \"%ld\", (long) value);\n- else\n- (*info->fprintf_func) (info->stream, \"0x%lx\", (long) value);\n-}\n+ char *opts = xstrdup (opts_in), *opt = opts, *opt_end = opts;\n \n-/* Keyword print handler. */\n-\n-static void\n-print_keyword (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,\n-\t void *dis_info,\n-\t CGEN_KEYWORD *keyword_table,\n-\t long value,\n-\t unsigned int attrs ATTRIBUTE_UNUSED)\n-{\n- disassemble_info *info = (disassemble_info *) dis_info;\n- const CGEN_KEYWORD_ENTRY *ke;\n+ for ( ; opt_end != NULL; opt = opt_end + 1)\n+ {\n+ if ((opt_end = strchr (opt, ',')) != NULL)\n+\t*opt_end = 0;\n+ parse_bpf_dis_option (opt);\n+ }\n \n- ke = cgen_keyword_lookup_value (keyword_table, value);\n- if (ke != NULL)\n- (*info->fprintf_func) (info->stream, \"%s\", ke->name);\n- else\n- (*info->fprintf_func) (info->stream, \"???\");\n+ free (opts);\n }\n-\f\n-/* Default insn printer.\n \n- DIS_INFO is defined as `void *' so the disassembler needn't know anything\n- about disassemble_info. */\n+/* Auxiliary function used in print_insn_bpf below. */\n \n static void\n-print_insn_normal (CGEN_CPU_DESC cd,\n-\t\t void *dis_info,\n-\t\t const CGEN_INSN *insn,\n-\t\t CGEN_FIELDS *fields,\n-\t\t bfd_vma pc,\n-\t\t int length)\n+print_register (disassemble_info *info,\n+ const char *tag, uint8_t regno)\n {\n- const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);\n- disassemble_info *info = (disassemble_info *) dis_info;\n- const CGEN_SYNTAX_CHAR_TYPE *syn;\n-\n- CGEN_INIT_PRINT (cd);\n-\n- for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn)\n- {\n- if (CGEN_SYNTAX_MNEMONIC_P (*syn))\n-\t{\n-\t (*info->fprintf_func) (info->stream, \"%s\", CGEN_INSN_MNEMONIC (insn));\n-\t continue;\n-\t}\n- if (CGEN_SYNTAX_CHAR_P (*syn))\n-\t{\n-\t (*info->fprintf_func) (info->stream, \"%c\", CGEN_SYNTAX_CHAR (*syn));\n-\t continue;\n-\t}\n-\n- /* We have an operand. */\n- bpf_cgen_print_operand (cd, CGEN_SYNTAX_FIELD (*syn), info,\n-\t\t\t\t fields, CGEN_INSN_ATTRS (insn), pc, length);\n- }\n+ const char *fmt\n+ = (asm_dialect == BPF_DIALECT_NORMAL\n+ ? \"%%r%d\"\n+ : ((*(tag + 2) == 'w')\n+ ? \"w%d\"\n+ : \"r%d\"));\n+\n+ (*info->fprintf_styled_func) (info->stream, dis_style_register, fmt, regno);\n }\n-\f\n-/* Subroutine of print_insn. Reads an insn into the given buffers and updates\n- the extract info.\n- Returns 0 if all is well, non-zero otherwise. */\n-\n-static int\n-read_insn (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,\n-\t bfd_vma pc,\n-\t disassemble_info *info,\n-\t bfd_byte *buf,\n-\t int buflen,\n-\t CGEN_EXTRACT_INFO *ex_info,\n-\t unsigned long *insn_value)\n-{\n- int status = (*info->read_memory_func) (pc, buf, buflen, info);\n \n- if (status != 0)\n- {\n- (*info->memory_error_func) (status, pc, info);\n- return -1;\n- }\n-\n- ex_info->dis_info = info;\n- ex_info->valid = (1 << buflen) - 1;\n- ex_info->insn_bytes = buf;\n-\n- *insn_value = bfd_get_bits (buf, buflen * 8, info->endian == BFD_ENDIAN_BIG);\n- return 0;\n-}\n+/* Main entry point.\n+ Print one instruction from PC on INFO->STREAM.\n+ Return the size of the instruction (in bytes). */\n \n-/* Utility to print an insn.\n- BUF is the base part of the insn, target byte order, BUFLEN bytes long.\n- The result is the size of the insn in bytes or zero for an unknown insn\n- or -1 if an error occurs fetching data (memory_error_func will have\n- been called). */\n-\n-static int\n-print_insn (CGEN_CPU_DESC cd,\n-\t bfd_vma pc,\n-\t disassemble_info *info,\n-\t bfd_byte *buf,\n-\t unsigned int buflen)\n+int\n+print_insn_bpf (bfd_vma pc, disassemble_info *info)\n {\n- CGEN_INSN_INT insn_value;\n- const CGEN_INSN_LIST *insn_list;\n- CGEN_EXTRACT_INFO ex_info;\n- int basesize;\n-\n- /* Extract base part of instruction, just in case CGEN_DIS_* uses it. */\n- basesize = cd->base_insn_bitsize < buflen * 8 ?\n- cd->base_insn_bitsize : buflen * 8;\n- insn_value = cgen_get_insn_value (cd, buf, basesize, cd->insn_endian);\n-\n-\n- /* Fill in ex_info fields like read_insn would. Don't actually call\n- read_insn, since the incoming buffer is already read (and possibly\n- modified a la m32r). */\n- ex_info.valid = (1 << buflen) - 1;\n- ex_info.dis_info = info;\n- ex_info.insn_bytes = buf;\n-\n- /* The instructions are stored in hash lists.\n- Pick the first one and keep trying until we find the right one. */\n-\n- insn_list = CGEN_DIS_LOOKUP_INSN (cd, (char *) buf, insn_value);\n- while (insn_list != NULL)\n+ int insn_size = 8, status;\n+ bfd_byte insn_bytes[16];\n+ bpf_insn_word word = 0;\n+ const struct bpf_opcode *insn = NULL;\n+ enum bpf_endian endian = (info->endian == BFD_ENDIAN_LITTLE\n+ ? BPF_ENDIAN_LITTLE : BPF_ENDIAN_BIG);\n+\n+ /* Handle bpf-specific command-line options. */\n+ if (info->disassembler_options != NULL)\n {\n- const CGEN_INSN *insn = insn_list->insn;\n- CGEN_FIELDS fields;\n- int length;\n- unsigned long insn_value_cropped;\n-\n-#ifdef CGEN_VALIDATE_INSN_SUPPORTED\n- /* Not needed as insn shouldn't be in hash lists if not supported. */\n- /* Supported by this cpu? */\n- if (! bpf_cgen_insn_supported (cd, insn))\n- {\n- insn_list = CGEN_DIS_NEXT_INSN (insn_list);\n-\t continue;\n- }\n-#endif\n-\n- /* Basic bit mask must be correct. */\n- /* ??? May wish to allow target to defer this check until the extract\n-\t handler. */\n-\n- /* Base size may exceed this instruction's size. Extract the\n- relevant part from the buffer. */\n- if ((unsigned) (CGEN_INSN_BITSIZE (insn) / 8) < buflen &&\n-\t (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))\n-\tinsn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn),\n-\t\t\t\t\t info->endian == BFD_ENDIAN_BIG);\n- else\n-\tinsn_value_cropped = insn_value;\n-\n- if ((insn_value_cropped & CGEN_INSN_BASE_MASK (insn))\n-\t == CGEN_INSN_BASE_VALUE (insn))\n-\t{\n-\t /* Printing is handled in two passes. The first pass parses the\n-\t machine insn and extracts the fields. The second pass prints\n-\t them. */\n-\n-\t /* Make sure the entire insn is loaded into insn_value, if it\n-\t can fit. */\n-\t if (((unsigned) CGEN_INSN_BITSIZE (insn) > cd->base_insn_bitsize) &&\n-\t (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))\n-\t {\n-\t unsigned long full_insn_value;\n-\t int rc = read_insn (cd, pc, info, buf,\n-\t\t\t\t CGEN_INSN_BITSIZE (insn) / 8,\n-\t\t\t\t & ex_info, & full_insn_value);\n-\t if (rc != 0)\n-\t\treturn rc;\n-\t length = CGEN_EXTRACT_FN (cd, insn)\n-\t\t(cd, insn, &ex_info, full_insn_value, &fields, pc);\n-\t }\n-\t else\n-\t length = CGEN_EXTRACT_FN (cd, insn)\n-\t (cd, insn, &ex_info, insn_value_cropped, &fields, pc);\n-\n-\t /* Length < 0 -> error. */\n-\t if (length < 0)\n-\t return length;\n-\t if (length > 0)\n-\t {\n-\t CGEN_PRINT_FN (cd, insn) (cd, info, insn, &fields, pc, length);\n-\t /* Length is in bits, result is in bytes. */\n-\t return length / 8;\n-\t }\n-\t}\n-\n- insn_list = CGEN_DIS_NEXT_INSN (insn_list);\n+ parse_bpf_dis_options (info->disassembler_options);\n+ /* Avoid repeteadly parsing the options. */\n+ info->disassembler_options = NULL;\n }\n \n- return 0;\n-}\n-\n-/* Default value for CGEN_PRINT_INSN.\n- The result is the size of the insn in bytes or zero for an unknown insn\n- or -1 if an error occured fetching bytes. */\n-\n-#ifndef CGEN_PRINT_INSN\n-#define CGEN_PRINT_INSN default_print_insn\n-#endif\n-\n-static int\n-default_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info)\n-{\n- bfd_byte buf[CGEN_MAX_INSN_SIZE];\n- int buflen;\n- int status;\n-\n- /* Attempt to read the base part of the insn. */\n- buflen = cd->base_insn_bitsize / 8;\n- status = (*info->read_memory_func) (pc, buf, buflen, info);\n-\n- /* Try again with the minimum part, if min < base. */\n- if (status != 0 && (cd->min_insn_bitsize < cd->base_insn_bitsize))\n- {\n- buflen = cd->min_insn_bitsize / 8;\n- status = (*info->read_memory_func) (pc, buf, buflen, info);\n- }\n+ /* Print eight bytes per line. */\n+ info->bytes_per_chunk = 1;\n+ info->bytes_per_line = 8;\n \n+ /* Read an instruction word. */\n+ status = (*info->read_memory_func) (pc, insn_bytes, 8, info);\n if (status != 0)\n {\n (*info->memory_error_func) (status, pc, info);\n return -1;\n }\n+ word = (bpf_insn_word) bfd_getb64 (insn_bytes);\n \n- return print_insn (cd, pc, info, buf, buflen);\n-}\n+ /* Try to match an instruction with it. */\n+ insn = bpf_match_insn (word, endian, asm_bpf_version);\n \n-/* Main entry point.\n- Print one instruction from PC on INFO->STREAM.\n- Return the size of the instruction (in bytes). */\n-\n-typedef struct cpu_desc_list\n-{\n- struct cpu_desc_list *next;\n- CGEN_BITSET *isa;\n- int mach;\n- int endian;\n- int insn_endian;\n- CGEN_CPU_DESC cd;\n-} cpu_desc_list;\n-\n-int\n-print_insn_bpf (bfd_vma pc, disassemble_info *info)\n-{\n- static cpu_desc_list *cd_list = 0;\n- cpu_desc_list *cl = 0;\n- static CGEN_CPU_DESC cd = 0;\n- static CGEN_BITSET *prev_isa;\n- static int prev_mach;\n- static int prev_endian;\n- static int prev_insn_endian;\n- int length;\n- CGEN_BITSET *isa;\n- int mach;\n- int endian = (info->endian == BFD_ENDIAN_BIG\n-\t\t? CGEN_ENDIAN_BIG\n-\t\t: CGEN_ENDIAN_LITTLE);\n- int insn_endian = (info->endian_code == BFD_ENDIAN_BIG\n- ? CGEN_ENDIAN_BIG\n- : CGEN_ENDIAN_LITTLE);\n- enum bfd_architecture arch;\n-\n- /* ??? gdb will set mach but leave the architecture as \"unknown\" */\n-#ifndef CGEN_BFD_ARCH\n-#define CGEN_BFD_ARCH bfd_arch_bpf\n-#endif\n- arch = info->arch;\n- if (arch == bfd_arch_unknown)\n- arch = CGEN_BFD_ARCH;\n-\n- /* There's no standard way to compute the machine or isa number\n- so we leave it to the target. */\n-#ifdef CGEN_COMPUTE_MACH\n- mach = CGEN_COMPUTE_MACH (info);\n-#else\n- mach = info->mach;\n-#endif\n-\n-#ifdef CGEN_COMPUTE_ISA\n- {\n- static CGEN_BITSET *permanent_isa;\n-\n- if (!permanent_isa)\n- permanent_isa = cgen_bitset_create (MAX_ISAS);\n- isa = permanent_isa;\n- cgen_bitset_clear (isa);\n- cgen_bitset_add (isa, CGEN_COMPUTE_ISA (info));\n- }\n-#else\n- isa = info->private_data;\n-#endif\n-\n- /* If we've switched cpu's, try to find a handle we've used before */\n- if (cd\n- && (cgen_bitset_compare (isa, prev_isa) != 0\n-\t || mach != prev_mach\n-\t || endian != prev_endian))\n+ /* Print it out. */\n+ if (insn)\n {\n- cd = 0;\n- for (cl = cd_list; cl; cl = cl->next)\n-\t{\n-\t if (cgen_bitset_compare (cl->isa, isa) == 0 &&\n-\t cl->mach == mach &&\n-\t cl->endian == endian)\n-\t {\n-\t cd = cl->cd;\n- \t prev_isa = cd->isas;\n-\t break;\n-\t }\n-\t}\n- }\n+ const char *insn_tmpl\n+ = asm_dialect == BPF_DIALECT_NORMAL ? insn->normal : insn->pseudoc;\n+ const char *p = insn_tmpl;\n \n- /* If we haven't initialized yet, initialize the opcode table. */\n- if (! cd)\n- {\n- const bfd_arch_info_type *arch_type = bfd_lookup_arch (arch, mach);\n- const char *mach_name;\n-\n- if (!arch_type)\n-\tabort ();\n- mach_name = arch_type->printable_name;\n-\n- prev_isa = cgen_bitset_copy (isa);\n- prev_mach = mach;\n- prev_endian = endian;\n- prev_insn_endian = insn_endian;\n- cd = bpf_cgen_cpu_open (CGEN_CPU_OPEN_ISAS, prev_isa,\n-\t\t\t\t CGEN_CPU_OPEN_BFDMACH, mach_name,\n-\t\t\t\t CGEN_CPU_OPEN_ENDIAN, prev_endian,\n- CGEN_CPU_OPEN_INSN_ENDIAN, prev_insn_endian,\n-\t\t\t\t CGEN_CPU_OPEN_END);\n- if (!cd)\n-\tabort ();\n-\n- /* Save this away for future reference. */\n- cl = xmalloc (sizeof (struct cpu_desc_list));\n- cl->cd = cd;\n- cl->isa = prev_isa;\n- cl->mach = mach;\n- cl->endian = endian;\n- cl->next = cd_list;\n- cd_list = cl;\n-\n- bpf_cgen_init_dis (cd);\n+ /* Print the template contents completed with the instruction\n+ operands. */\n+ for (p = insn_tmpl; *p != '\\0';)\n+ {\n+ switch (*p)\n+ {\n+ case ' ':\n+ /* Single space prints to nothing. */\n+ p += 1;\n+ break;\n+ case '%':\n+ if (*(p + 1) == '%')\n+ {\n+ (*info->fprintf_styled_func) (info->stream, dis_style_text, \"%%\");\n+ p += 2;\n+ }\n+ else if (*(p + 1) == 'w' || *(p + 1) == 'W')\n+ {\n+ /* %W prints to a single space. */\n+ (*info->fprintf_styled_func) (info->stream, dis_style_text, \" \");\n+ p += 2;\n+ }\n+ else if (strncmp (p, \"%dr\", 3) == 0)\n+ {\n+ print_register (info, p, bpf_extract_dst (word, endian));\n+ p += 3;\n+ }\n+ else if (strncmp (p, \"%sr\", 3) == 0)\n+ {\n+ print_register (info, p, bpf_extract_src (word, endian));\n+ p += 3;\n+ }\n+ else if (strncmp (p, \"%dw\", 3) == 0)\n+ {\n+ print_register (info, p, bpf_extract_dst (word, endian));\n+ p += 3;\n+ }\n+ else if (strncmp (p, \"%sw\", 3) == 0)\n+ {\n+ print_register (info, p, bpf_extract_src (word, endian));\n+ p += 3;\n+ }\n+ else if (strncmp (p, \"%i32\", 4) == 0\n+ || strncmp (p, \"%d32\", 4) == 0\n+ || strncmp (p, \"%I32\", 4) == 0)\n+ {\n+ int32_t imm32 = bpf_extract_imm32 (word, endian);\n+\n+ if (p[1] == 'I')\n+ (*info->fprintf_styled_func) (info->stream, dis_style_immediate,\n+ \"%s\",\n+ asm_obase != 10 || imm32 > 0 ? \"+\" : \"\");\n+ (*info->fprintf_styled_func) (info->stream, dis_style_immediate,\n+ asm_obase == 10 ? \"%\" PRIi32\n+ : asm_obase == 8 ? \"%\" PRIo32\n+ : \"0x%\" PRIx32,\n+ imm32);\n+ p += 4;\n+ }\n+ else if (strncmp (p, \"%o16\", 4) == 0\n+ || strncmp (p, \"%d16\", 4) == 0)\n+ {\n+ int16_t offset16 = bpf_extract_offset16 (word, endian);\n+\n+ if (p[1] == 'o')\n+ (*info->fprintf_styled_func) (info->stream, dis_style_immediate,\n+ \"%s\",\n+ asm_obase != 10 || offset16 > 0 ? \"+\" : \"\");\n+ if (asm_obase == 16 || asm_obase == 8)\n+ (*info->fprintf_styled_func) (info->stream, dis_style_immediate,\n+ asm_obase == 8 ? \"0%\" PRIo16 : \"0x%\" PRIx16,\n+ (uint16_t) offset16);\n+ else\n+ (*info->fprintf_styled_func) (info->stream, dis_style_immediate,\n+ \"%\" PRIi16, offset16);\n+ p += 4;\n+ }\n+ else if (strncmp (p, \"%i64\", 4) == 0)\n+ {\n+ bpf_insn_word word2 = 0;\n+\n+ status = (*info->read_memory_func) (pc + 8, insn_bytes + 8,\n+ 8, info);\n+ if (status != 0)\n+ {\n+ (*info->memory_error_func) (status, pc + 8, info);\n+ return -1;\n+ }\n+ word2 = (bpf_insn_word) bfd_getb64 (insn_bytes + 8);\n+\n+ (*info->fprintf_styled_func) (info->stream, dis_style_immediate,\n+ asm_obase == 10 ? \"%\" PRIi64\n+ : asm_obase == 8 ? \"0%\" PRIo64\n+ : \"0x%\" PRIx64,\n+ bpf_extract_imm64 (word, word2, endian));\n+ insn_size = 16;\n+ p += 4;\n+ }\n+ else\n+ {\n+ /* xgettext:c-format */\n+ opcodes_error_handler (_(\"# internal error, unknown tag in opcode template (%s)\"),\n+ insn_tmpl);\n+ return -1;\n+ }\n+ break;\n+ default:\n+ /* Any other character is printed literally. */\n+ (*info->fprintf_styled_func) (info->stream, dis_style_text, \"%c\", *p);\n+ p += 1;\n+ }\n+ }\n }\n+ else\n+ (*info->fprintf_styled_func) (info->stream, dis_style_text, \"\");\n \n- /* We try to have as much common code as possible.\n- But at this point some targets need to take over. */\n- /* ??? Some targets may need a hook elsewhere. Try to avoid this,\n- but if not possible try to move this hook elsewhere rather than\n- have two hooks. */\n- length = CGEN_PRINT_INSN (cd, pc, info);\n- if (length > 0)\n- return length;\n- if (length < 0)\n- return -1;\n-\n- (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG);\n- return cd->default_insn_bitsize / 8;\n+ return insn_size;\n }\ndiff --git a/opcodes/bpf-opc.c b/opcodes/bpf-opc.c\nindex 1cc06f7cbf6..f89d93a5c78 100644\n--- a/opcodes/bpf-opc.c\n+++ b/opcodes/bpf-opc.c\n@@ -1,1863 +1,484 @@\n-/* DO NOT EDIT! -*- buffer-read-only: t -*- vi:set ro: */\n-/* Instruction opcode table for bpf.\n+/* bpf-opc.c - BPF opcodes.\n+ Copyright (C) 2023 Free Software Foundation, Inc.\n \n-THIS FILE IS MACHINE GENERATED WITH CGEN.\n+ Contributed by Oracle Inc.\n \n-Copyright (C) 1996-2023 Free Software Foundation, Inc.\n+ This file is part of the GNU binutils.\n \n-This file is part of the GNU Binutils and/or GDB, the GNU debugger.\n-\n- This file is free software; you can redistribute it and/or modify\n- it under the terms of the GNU General Public License as published by\n+ This is free software; you can redistribute them and/or modify them\n+ under the terms of the GNU General Public License as published by\n the Free Software Foundation; either version 3, or (at your option)\n any later version.\n \n- It is distributed in the hope that it will be useful, but WITHOUT\n- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\n- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public\n- License for more details.\n-\n- You should have received a copy of the GNU General Public License along\n- with this program; if not, write to the Free Software Foundation, Inc.,\n- 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.\n-\n-*/\n-\n-#include \"sysdep.h\"\n-#include \"ansidecl.h\"\n-#include \"bfd.h\"\n-#include \"symcat.h\"\n-#include \"bpf-desc.h\"\n-#include \"bpf-opc.h\"\n-#include \"libiberty.h\"\n-\n-/* -- opc.c */\n-\f\n-/* -- asm.c */\n-/* The hash functions are recorded here to help keep assembler code out of\n- the disassembler and vice versa. */\n-\n-static int asm_hash_insn_p (const CGEN_INSN *);\n-static unsigned int asm_hash_insn (const char *);\n-static int dis_hash_insn_p (const CGEN_INSN *);\n-static unsigned int dis_hash_insn (const char *, CGEN_INSN_INT);\n-\n-/* Instruction formats. */\n-\n-#define F(f) & bpf_cgen_ifld_table[BPF_##f]\n-static const CGEN_IFMT ifmt_empty ATTRIBUTE_UNUSED = {\n- 0, 0, 0x0, { { 0 } }\n-};\n-\n-static const CGEN_IFMT ifmt_addile ATTRIBUTE_UNUSED = {\n- 64, 64, 0xfffff0ff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_CODE) }, { F (F_DSTLE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }\n-};\n-\n-static const CGEN_IFMT ifmt_addrle ATTRIBUTE_UNUSED = {\n- 64, 64, 0xffffffffffff00ff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_CODE) }, { F (F_DSTLE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }\n-};\n-\n-static const CGEN_IFMT ifmt_negle ATTRIBUTE_UNUSED = {\n- 64, 64, 0xfffffffffffff0ff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_CODE) }, { F (F_DSTLE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }\n-};\n-\n-static const CGEN_IFMT ifmt_addibe ATTRIBUTE_UNUSED = {\n- 64, 64, 0xffff0fff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_DSTBE) }, { F (F_OP_CODE) }, { F (F_SRCBE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }\n-};\n-\n-static const CGEN_IFMT ifmt_addrbe ATTRIBUTE_UNUSED = {\n- 64, 64, 0xffffffffffff00ff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_DSTBE) }, { F (F_OP_CODE) }, { F (F_SRCBE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }\n-};\n-\n-static const CGEN_IFMT ifmt_negbe ATTRIBUTE_UNUSED = {\n- 64, 64, 0xffffffffffff0fff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_DSTBE) }, { F (F_OP_CODE) }, { F (F_SRCBE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }\n-};\n-\n-static const CGEN_IFMT ifmt_endlele ATTRIBUTE_UNUSED = {\n- 64, 64, 0xfffff0ff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_CODE) }, { F (F_DSTLE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }\n-};\n-\n-static const CGEN_IFMT ifmt_endlebe ATTRIBUTE_UNUSED = {\n- 64, 64, 0xffff0fff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_DSTBE) }, { F (F_OP_CODE) }, { F (F_SRCBE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }\n-};\n-\n-static const CGEN_IFMT ifmt_lddwle ATTRIBUTE_UNUSED = {\n- 64, 128, 0xfffff0ff, { { F (F_IMM64) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_MODE) }, { F (F_OP_SIZE) }, { F (F_DSTLE) }, { F (F_OP_CLASS) }, { 0 } }\n-};\n-\n-static const CGEN_IFMT ifmt_lddwbe ATTRIBUTE_UNUSED = {\n- 64, 128, 0xffff0fff, { { F (F_IMM64) }, { F (F_OFFSET16) }, { F (F_DSTBE) }, { F (F_OP_MODE) }, { F (F_OP_SIZE) }, { F (F_SRCBE) }, { F (F_OP_CLASS) }, { 0 } }\n-};\n-\n-static const CGEN_IFMT ifmt_ldabsw ATTRIBUTE_UNUSED = {\n- 64, 64, 0xffffffff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_REGS) }, { F (F_OP_MODE) }, { F (F_OP_SIZE) }, { F (F_OP_CLASS) }, { 0 } }\n-};\n-\n-static const CGEN_IFMT ifmt_ldindwle ATTRIBUTE_UNUSED = {\n- 64, 64, 0xffff0fff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_MODE) }, { F (F_OP_SIZE) }, { F (F_DSTLE) }, { F (F_OP_CLASS) }, { 0 } }\n-};\n-\n-static const CGEN_IFMT ifmt_ldindwbe ATTRIBUTE_UNUSED = {\n- 64, 64, 0xfffff0ff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_DSTBE) }, { F (F_OP_MODE) }, { F (F_OP_SIZE) }, { F (F_SRCBE) }, { F (F_OP_CLASS) }, { 0 } }\n-};\n-\n-static const CGEN_IFMT ifmt_ldxwle ATTRIBUTE_UNUSED = {\n- 64, 64, 0xffffffff000000ff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_MODE) }, { F (F_OP_SIZE) }, { F (F_DSTLE) }, { F (F_OP_CLASS) }, { 0 } }\n-};\n-\n-static const CGEN_IFMT ifmt_ldxwbe ATTRIBUTE_UNUSED = {\n- 64, 64, 0xffffffff000000ff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_DSTBE) }, { F (F_OP_MODE) }, { F (F_OP_SIZE) }, { F (F_SRCBE) }, { F (F_OP_CLASS) }, { 0 } }\n-};\n-\n-static const CGEN_IFMT ifmt_stble ATTRIBUTE_UNUSED = {\n- 64, 64, 0xf0ff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_MODE) }, { F (F_OP_SIZE) }, { F (F_DSTLE) }, { F (F_OP_CLASS) }, { 0 } }\n-};\n-\n-static const CGEN_IFMT ifmt_stbbe ATTRIBUTE_UNUSED = {\n- 64, 64, 0xfff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_DSTBE) }, { F (F_OP_MODE) }, { F (F_OP_SIZE) }, { F (F_SRCBE) }, { F (F_OP_CLASS) }, { 0 } }\n-};\n-\n-static const CGEN_IFMT ifmt_jeqile ATTRIBUTE_UNUSED = {\n- 64, 64, 0xf0ff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_CODE) }, { F (F_DSTLE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }\n-};\n-\n-static const CGEN_IFMT ifmt_jeqrle ATTRIBUTE_UNUSED = {\n- 64, 64, 0xffffffff000000ff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_CODE) }, { F (F_DSTLE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }\n-};\n-\n-static const CGEN_IFMT ifmt_jeqibe ATTRIBUTE_UNUSED = {\n- 64, 64, 0xfff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_DSTBE) }, { F (F_OP_CODE) }, { F (F_SRCBE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }\n-};\n-\n-static const CGEN_IFMT ifmt_jeqrbe ATTRIBUTE_UNUSED = {\n- 64, 64, 0xffffffff000000ff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_DSTBE) }, { F (F_OP_CODE) }, { F (F_SRCBE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }\n-};\n-\n-static const CGEN_IFMT ifmt_callle ATTRIBUTE_UNUSED = {\n- 64, 64, 0xffff0fff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_CODE) }, { F (F_DSTLE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }\n-};\n-\n-static const CGEN_IFMT ifmt_callbe ATTRIBUTE_UNUSED = {\n- 64, 64, 0xfffff0ff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_DSTBE) }, { F (F_OP_CODE) }, { F (F_SRCBE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }\n-};\n+ This program is distributed in the hope that it will be useful, but\n+ WITHOUT ANY WARRANTY; without even the implied warranty of\n+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU\n+ General Public License for more details.\n \n-static const CGEN_IFMT ifmt_ja ATTRIBUTE_UNUSED = {\n- 64, 64, 0xffffffff0000ffff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_REGS) }, { F (F_OP_CODE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }\n-};\n+ You should have received a copy of the GNU General Public License\n+ along with this program; see the file COPYING3. If not,\n+ see . */\n \n-static const CGEN_IFMT ifmt_exit ATTRIBUTE_UNUSED = {\n- 64, 64, 0xffffffffffffffff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_REGS) }, { F (F_OP_CODE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }\n-};\n+#include \"config.h\"\n+#include \n+#include \"opcode/bpf.h\"\n \n-#undef F\n+/* Note that the entries in the opcodes table below are accessed\n+ sequentially when matching instructions per opcode, and also when\n+ parsing. Please take care to keep the entries sorted\n+ accordingly! */\n \n-#define A(a) (1 << CGEN_INSN_##a)\n-#define OPERAND(op) BPF_OPERAND_##op\n-#define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */\n-#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))\n-\n-/* The instruction table. */\n-\n-static const CGEN_OPCODE bpf_cgen_insn_opcode_table[MAX_INSNS] =\n+const struct bpf_opcode bpf_opcodes[] =\n {\n- /* Special null first entry.\n- A `num' value of zero is thus invalid.\n- Also, the special `invalid' insn resides here. */\n- { { 0, 0, 0, 0 }, {{0}}, 0, {0}},\n-/* add $dstle,$imm32 */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), 0 } },\n- & ifmt_addile, { 0x7 }\n- },\n-/* add $dstle,$srcle */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), 0 } },\n- & ifmt_addrle, { 0xf }\n- },\n-/* add32 $dstle,$imm32 */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), 0 } },\n- & ifmt_addile, { 0x4 }\n- },\n-/* add32 $dstle,$srcle */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), 0 } },\n- & ifmt_addrle, { 0xc }\n- },\n-/* sub $dstle,$imm32 */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), 0 } },\n- & ifmt_addile, { 0x17 }\n- },\n-/* sub $dstle,$srcle */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), 0 } },\n- & ifmt_addrle, { 0x1f }\n- },\n-/* sub32 $dstle,$imm32 */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), 0 } },\n- & ifmt_addile, { 0x14 }\n- },\n-/* sub32 $dstle,$srcle */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), 0 } },\n- & ifmt_addrle, { 0x1c }\n- },\n-/* mul $dstle,$imm32 */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), 0 } },\n- & ifmt_addile, { 0x27 }\n- },\n-/* mul $dstle,$srcle */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), 0 } },\n- & ifmt_addrle, { 0x2f }\n- },\n-/* mul32 $dstle,$imm32 */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), 0 } },\n- & ifmt_addile, { 0x24 }\n- },\n-/* mul32 $dstle,$srcle */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), 0 } },\n- & ifmt_addrle, { 0x2c }\n- },\n-/* div $dstle,$imm32 */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), 0 } },\n- & ifmt_addile, { 0x37 }\n- },\n-/* div $dstle,$srcle */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), 0 } },\n- & ifmt_addrle, { 0x3f }\n- },\n-/* div32 $dstle,$imm32 */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), 0 } },\n- & ifmt_addile, { 0x34 }\n- },\n-/* div32 $dstle,$srcle */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), 0 } },\n- & ifmt_addrle, { 0x3c }\n- },\n-/* or $dstle,$imm32 */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), 0 } },\n- & ifmt_addile, { 0x47 }\n- },\n-/* or $dstle,$srcle */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), 0 } },\n- & ifmt_addrle, { 0x4f }\n- },\n-/* or32 $dstle,$imm32 */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), 0 } },\n- & ifmt_addile, { 0x44 }\n- },\n-/* or32 $dstle,$srcle */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), 0 } },\n- & ifmt_addrle, { 0x4c }\n- },\n-/* and $dstle,$imm32 */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), 0 } },\n- & ifmt_addile, { 0x57 }\n- },\n-/* and $dstle,$srcle */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), 0 } },\n- & ifmt_addrle, { 0x5f }\n- },\n-/* and32 $dstle,$imm32 */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), 0 } },\n- & ifmt_addile, { 0x54 }\n- },\n-/* and32 $dstle,$srcle */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), 0 } },\n- & ifmt_addrle, { 0x5c }\n- },\n-/* lsh $dstle,$imm32 */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), 0 } },\n- & ifmt_addile, { 0x67 }\n- },\n-/* lsh $dstle,$srcle */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), 0 } },\n- & ifmt_addrle, { 0x6f }\n- },\n-/* lsh32 $dstle,$imm32 */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), 0 } },\n- & ifmt_addile, { 0x64 }\n- },\n-/* lsh32 $dstle,$srcle */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), 0 } },\n- & ifmt_addrle, { 0x6c }\n- },\n-/* rsh $dstle,$imm32 */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), 0 } },\n- & ifmt_addile, { 0x77 }\n- },\n-/* rsh $dstle,$srcle */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), 0 } },\n- & ifmt_addrle, { 0x7f }\n- },\n-/* rsh32 $dstle,$imm32 */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), 0 } },\n- & ifmt_addile, { 0x74 }\n- },\n-/* rsh32 $dstle,$srcle */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), 0 } },\n- & ifmt_addrle, { 0x7c }\n- },\n-/* mod $dstle,$imm32 */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), 0 } },\n- & ifmt_addile, { 0x97 }\n- },\n-/* mod $dstle,$srcle */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), 0 } },\n- & ifmt_addrle, { 0x9f }\n- },\n-/* mod32 $dstle,$imm32 */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), 0 } },\n- & ifmt_addile, { 0x94 }\n- },\n-/* mod32 $dstle,$srcle */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), 0 } },\n- & ifmt_addrle, { 0x9c }\n- },\n-/* xor $dstle,$imm32 */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), 0 } },\n- & ifmt_addile, { 0xa7 }\n- },\n-/* xor $dstle,$srcle */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), 0 } },\n- & ifmt_addrle, { 0xaf }\n- },\n-/* xor32 $dstle,$imm32 */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), 0 } },\n- & ifmt_addile, { 0xa4 }\n- },\n-/* xor32 $dstle,$srcle */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), 0 } },\n- & ifmt_addrle, { 0xac }\n- },\n-/* arsh $dstle,$imm32 */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), 0 } },\n- & ifmt_addile, { 0xc7 }\n- },\n-/* arsh $dstle,$srcle */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), 0 } },\n- & ifmt_addrle, { 0xcf }\n- },\n-/* arsh32 $dstle,$imm32 */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), 0 } },\n- & ifmt_addile, { 0xc4 }\n- },\n-/* arsh32 $dstle,$srcle */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), 0 } },\n- & ifmt_addrle, { 0xcc }\n- },\n-/* sdiv $dstle,$imm32 */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), 0 } },\n- & ifmt_addile, { 0xe7 }\n- },\n-/* sdiv $dstle,$srcle */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), 0 } },\n- & ifmt_addrle, { 0xef }\n- },\n-/* sdiv32 $dstle,$imm32 */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), 0 } },\n- & ifmt_addile, { 0xe4 }\n- },\n-/* sdiv32 $dstle,$srcle */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), 0 } },\n- & ifmt_addrle, { 0xec }\n- },\n-/* smod $dstle,$imm32 */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), 0 } },\n- & ifmt_addile, { 0xf7 }\n- },\n-/* smod $dstle,$srcle */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), 0 } },\n- & ifmt_addrle, { 0xff }\n- },\n-/* smod32 $dstle,$imm32 */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), 0 } },\n- & ifmt_addile, { 0xf4 }\n- },\n-/* smod32 $dstle,$srcle */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), 0 } },\n- & ifmt_addrle, { 0xfc }\n- },\n-/* neg $dstle */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTLE), 0 } },\n- & ifmt_negle, { 0x87 }\n- },\n-/* neg32 $dstle */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTLE), 0 } },\n- & ifmt_negle, { 0x84 }\n- },\n-/* mov $dstle,$imm32 */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), 0 } },\n- & ifmt_addile, { 0xb7 }\n- },\n-/* mov $dstle,$srcle */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), 0 } },\n- & ifmt_addrle, { 0xbf }\n- },\n-/* mov32 $dstle,$imm32 */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), 0 } },\n- & ifmt_addile, { 0xb4 }\n- },\n-/* mov32 $dstle,$srcle */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), 0 } },\n- & ifmt_addrle, { 0xbc }\n- },\n-/* add $dstbe,$imm32 */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), 0 } },\n- & ifmt_addibe, { 0x7 }\n- },\n-/* add $dstbe,$srcbe */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), 0 } },\n- & ifmt_addrbe, { 0xf }\n- },\n-/* add32 $dstbe,$imm32 */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), 0 } },\n- & ifmt_addibe, { 0x4 }\n- },\n-/* add32 $dstbe,$srcbe */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), 0 } },\n- & ifmt_addrbe, { 0xc }\n- },\n-/* sub $dstbe,$imm32 */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), 0 } },\n- & ifmt_addibe, { 0x17 }\n- },\n-/* sub $dstbe,$srcbe */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), 0 } },\n- & ifmt_addrbe, { 0x1f }\n- },\n-/* sub32 $dstbe,$imm32 */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), 0 } },\n- & ifmt_addibe, { 0x14 }\n- },\n-/* sub32 $dstbe,$srcbe */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), 0 } },\n- & ifmt_addrbe, { 0x1c }\n- },\n-/* mul $dstbe,$imm32 */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), 0 } },\n- & ifmt_addibe, { 0x27 }\n- },\n-/* mul $dstbe,$srcbe */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), 0 } },\n- & ifmt_addrbe, { 0x2f }\n- },\n-/* mul32 $dstbe,$imm32 */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), 0 } },\n- & ifmt_addibe, { 0x24 }\n- },\n-/* mul32 $dstbe,$srcbe */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), 0 } },\n- & ifmt_addrbe, { 0x2c }\n- },\n-/* div $dstbe,$imm32 */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), 0 } },\n- & ifmt_addibe, { 0x37 }\n- },\n-/* div $dstbe,$srcbe */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), 0 } },\n- & ifmt_addrbe, { 0x3f }\n- },\n-/* div32 $dstbe,$imm32 */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), 0 } },\n- & ifmt_addibe, { 0x34 }\n- },\n-/* div32 $dstbe,$srcbe */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), 0 } },\n- & ifmt_addrbe, { 0x3c }\n- },\n-/* or $dstbe,$imm32 */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), 0 } },\n- & ifmt_addibe, { 0x47 }\n- },\n-/* or $dstbe,$srcbe */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), 0 } },\n- & ifmt_addrbe, { 0x4f }\n- },\n-/* or32 $dstbe,$imm32 */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), 0 } },\n- & ifmt_addibe, { 0x44 }\n- },\n-/* or32 $dstbe,$srcbe */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), 0 } },\n- & ifmt_addrbe, { 0x4c }\n- },\n-/* and $dstbe,$imm32 */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), 0 } },\n- & ifmt_addibe, { 0x57 }\n- },\n-/* and $dstbe,$srcbe */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), 0 } },\n- & ifmt_addrbe, { 0x5f }\n- },\n-/* and32 $dstbe,$imm32 */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), 0 } },\n- & ifmt_addibe, { 0x54 }\n- },\n-/* and32 $dstbe,$srcbe */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), 0 } },\n- & ifmt_addrbe, { 0x5c }\n- },\n-/* lsh $dstbe,$imm32 */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), 0 } },\n- & ifmt_addibe, { 0x67 }\n- },\n-/* lsh $dstbe,$srcbe */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), 0 } },\n- & ifmt_addrbe, { 0x6f }\n- },\n-/* lsh32 $dstbe,$imm32 */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), 0 } },\n- & ifmt_addibe, { 0x64 }\n- },\n-/* lsh32 $dstbe,$srcbe */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), 0 } },\n- & ifmt_addrbe, { 0x6c }\n- },\n-/* rsh $dstbe,$imm32 */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), 0 } },\n- & ifmt_addibe, { 0x77 }\n- },\n-/* rsh $dstbe,$srcbe */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), 0 } },\n- & ifmt_addrbe, { 0x7f }\n- },\n-/* rsh32 $dstbe,$imm32 */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), 0 } },\n- & ifmt_addibe, { 0x74 }\n- },\n-/* rsh32 $dstbe,$srcbe */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), 0 } },\n- & ifmt_addrbe, { 0x7c }\n- },\n-/* mod $dstbe,$imm32 */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), 0 } },\n- & ifmt_addibe, { 0x97 }\n- },\n-/* mod $dstbe,$srcbe */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), 0 } },\n- & ifmt_addrbe, { 0x9f }\n- },\n-/* mod32 $dstbe,$imm32 */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), 0 } },\n- & ifmt_addibe, { 0x94 }\n- },\n-/* mod32 $dstbe,$srcbe */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), 0 } },\n- & ifmt_addrbe, { 0x9c }\n- },\n-/* xor $dstbe,$imm32 */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), 0 } },\n- & ifmt_addibe, { 0xa7 }\n- },\n-/* xor $dstbe,$srcbe */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), 0 } },\n- & ifmt_addrbe, { 0xaf }\n- },\n-/* xor32 $dstbe,$imm32 */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), 0 } },\n- & ifmt_addibe, { 0xa4 }\n- },\n-/* xor32 $dstbe,$srcbe */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), 0 } },\n- & ifmt_addrbe, { 0xac }\n- },\n-/* arsh $dstbe,$imm32 */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), 0 } },\n- & ifmt_addibe, { 0xc7 }\n- },\n-/* arsh $dstbe,$srcbe */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), 0 } },\n- & ifmt_addrbe, { 0xcf }\n- },\n-/* arsh32 $dstbe,$imm32 */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), 0 } },\n- & ifmt_addibe, { 0xc4 }\n- },\n-/* arsh32 $dstbe,$srcbe */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), 0 } },\n- & ifmt_addrbe, { 0xcc }\n- },\n-/* sdiv $dstbe,$imm32 */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), 0 } },\n- & ifmt_addibe, { 0xe7 }\n- },\n-/* sdiv $dstbe,$srcbe */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), 0 } },\n- & ifmt_addrbe, { 0xef }\n- },\n-/* sdiv32 $dstbe,$imm32 */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), 0 } },\n- & ifmt_addibe, { 0xe4 }\n- },\n-/* sdiv32 $dstbe,$srcbe */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), 0 } },\n- & ifmt_addrbe, { 0xec }\n- },\n-/* smod $dstbe,$imm32 */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), 0 } },\n- & ifmt_addibe, { 0xf7 }\n- },\n-/* smod $dstbe,$srcbe */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), 0 } },\n- & ifmt_addrbe, { 0xff }\n- },\n-/* smod32 $dstbe,$imm32 */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), 0 } },\n- & ifmt_addibe, { 0xf4 }\n- },\n-/* smod32 $dstbe,$srcbe */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), 0 } },\n- & ifmt_addrbe, { 0xfc }\n- },\n-/* neg $dstbe */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTBE), 0 } },\n- & ifmt_negbe, { 0x87 }\n- },\n-/* neg32 $dstbe */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTBE), 0 } },\n- & ifmt_negbe, { 0x84 }\n- },\n-/* mov $dstbe,$imm32 */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), 0 } },\n- & ifmt_addibe, { 0xb7 }\n- },\n-/* mov $dstbe,$srcbe */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), 0 } },\n- & ifmt_addrbe, { 0xbf }\n- },\n-/* mov32 $dstbe,$imm32 */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), 0 } },\n- & ifmt_addibe, { 0xb4 }\n- },\n-/* mov32 $dstbe,$srcbe */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), 0 } },\n- & ifmt_addrbe, { 0xbc }\n- },\n-/* endle $dstle,$endsize */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTLE), ',', OP (ENDSIZE), 0 } },\n- & ifmt_endlele, { 0xd4 }\n- },\n-/* endbe $dstle,$endsize */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTLE), ',', OP (ENDSIZE), 0 } },\n- & ifmt_endlele, { 0xdc }\n- },\n-/* endle $dstbe,$endsize */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTBE), ',', OP (ENDSIZE), 0 } },\n- & ifmt_endlebe, { 0xd4 }\n- },\n-/* endbe $dstbe,$endsize */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTBE), ',', OP (ENDSIZE), 0 } },\n- & ifmt_endlebe, { 0xdc }\n- },\n-/* lddw $dstle,$imm64 */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTLE), ',', OP (IMM64), 0 } },\n- & ifmt_lddwle, { 0x18 }\n- },\n-/* lddw $dstbe,$imm64 */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTBE), ',', OP (IMM64), 0 } },\n- & ifmt_lddwbe, { 0x18 }\n- },\n-/* ldabsw $imm32 */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (IMM32), 0 } },\n- & ifmt_ldabsw, { 0x20 }\n- },\n-/* ldabsh $imm32 */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (IMM32), 0 } },\n- & ifmt_ldabsw, { 0x28 }\n- },\n-/* ldabsb $imm32 */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (IMM32), 0 } },\n- & ifmt_ldabsw, { 0x30 }\n- },\n-/* ldabsdw $imm32 */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (IMM32), 0 } },\n- & ifmt_ldabsw, { 0x38 }\n- },\n-/* ldindw $srcle,$imm32 */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (SRCLE), ',', OP (IMM32), 0 } },\n- & ifmt_ldindwle, { 0x40 }\n- },\n-/* ldindh $srcle,$imm32 */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (SRCLE), ',', OP (IMM32), 0 } },\n- & ifmt_ldindwle, { 0x48 }\n- },\n-/* ldindb $srcle,$imm32 */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (SRCLE), ',', OP (IMM32), 0 } },\n- & ifmt_ldindwle, { 0x50 }\n- },\n-/* ldinddw $srcle,$imm32 */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (SRCLE), ',', OP (IMM32), 0 } },\n- & ifmt_ldindwle, { 0x58 }\n- },\n-/* ldindw $srcbe,$imm32 */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (SRCBE), ',', OP (IMM32), 0 } },\n- & ifmt_ldindwbe, { 0x40 }\n- },\n-/* ldindh $srcbe,$imm32 */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (SRCBE), ',', OP (IMM32), 0 } },\n- & ifmt_ldindwbe, { 0x48 }\n- },\n-/* ldindb $srcbe,$imm32 */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (SRCBE), ',', OP (IMM32), 0 } },\n- & ifmt_ldindwbe, { 0x50 }\n- },\n-/* ldinddw $srcbe,$imm32 */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (SRCBE), ',', OP (IMM32), 0 } },\n- & ifmt_ldindwbe, { 0x58 }\n- },\n-/* ldxw $dstle,[$srcle+$offset16] */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTLE), ',', '[', OP (SRCLE), '+', OP (OFFSET16), ']', 0 } },\n- & ifmt_ldxwle, { 0x61 }\n- },\n-/* ldxh $dstle,[$srcle+$offset16] */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTLE), ',', '[', OP (SRCLE), '+', OP (OFFSET16), ']', 0 } },\n- & ifmt_ldxwle, { 0x69 }\n- },\n-/* ldxb $dstle,[$srcle+$offset16] */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTLE), ',', '[', OP (SRCLE), '+', OP (OFFSET16), ']', 0 } },\n- & ifmt_ldxwle, { 0x71 }\n- },\n-/* ldxdw $dstle,[$srcle+$offset16] */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTLE), ',', '[', OP (SRCLE), '+', OP (OFFSET16), ']', 0 } },\n- & ifmt_ldxwle, { 0x79 }\n- },\n-/* stxw [$dstle+$offset16],$srcle */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', '[', OP (DSTLE), '+', OP (OFFSET16), ']', ',', OP (SRCLE), 0 } },\n- & ifmt_ldxwle, { 0x63 }\n- },\n-/* stxh [$dstle+$offset16],$srcle */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', '[', OP (DSTLE), '+', OP (OFFSET16), ']', ',', OP (SRCLE), 0 } },\n- & ifmt_ldxwle, { 0x6b }\n- },\n-/* stxb [$dstle+$offset16],$srcle */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', '[', OP (DSTLE), '+', OP (OFFSET16), ']', ',', OP (SRCLE), 0 } },\n- & ifmt_ldxwle, { 0x73 }\n- },\n-/* stxdw [$dstle+$offset16],$srcle */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', '[', OP (DSTLE), '+', OP (OFFSET16), ']', ',', OP (SRCLE), 0 } },\n- & ifmt_ldxwle, { 0x7b }\n- },\n-/* ldxw $dstbe,[$srcbe+$offset16] */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTBE), ',', '[', OP (SRCBE), '+', OP (OFFSET16), ']', 0 } },\n- & ifmt_ldxwbe, { 0x61 }\n- },\n-/* ldxh $dstbe,[$srcbe+$offset16] */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTBE), ',', '[', OP (SRCBE), '+', OP (OFFSET16), ']', 0 } },\n- & ifmt_ldxwbe, { 0x69 }\n- },\n-/* ldxb $dstbe,[$srcbe+$offset16] */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTBE), ',', '[', OP (SRCBE), '+', OP (OFFSET16), ']', 0 } },\n- & ifmt_ldxwbe, { 0x71 }\n- },\n-/* ldxdw $dstbe,[$srcbe+$offset16] */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTBE), ',', '[', OP (SRCBE), '+', OP (OFFSET16), ']', 0 } },\n- & ifmt_ldxwbe, { 0x79 }\n- },\n-/* stxw [$dstbe+$offset16],$srcbe */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', '[', OP (DSTBE), '+', OP (OFFSET16), ']', ',', OP (SRCBE), 0 } },\n- & ifmt_ldxwbe, { 0x63 }\n- },\n-/* stxh [$dstbe+$offset16],$srcbe */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', '[', OP (DSTBE), '+', OP (OFFSET16), ']', ',', OP (SRCBE), 0 } },\n- & ifmt_ldxwbe, { 0x6b }\n- },\n-/* stxb [$dstbe+$offset16],$srcbe */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', '[', OP (DSTBE), '+', OP (OFFSET16), ']', ',', OP (SRCBE), 0 } },\n- & ifmt_ldxwbe, { 0x73 }\n- },\n-/* stxdw [$dstbe+$offset16],$srcbe */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', '[', OP (DSTBE), '+', OP (OFFSET16), ']', ',', OP (SRCBE), 0 } },\n- & ifmt_ldxwbe, { 0x7b }\n- },\n-/* stb [$dstle+$offset16],$imm32 */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', '[', OP (DSTLE), '+', OP (OFFSET16), ']', ',', OP (IMM32), 0 } },\n- & ifmt_stble, { 0x72 }\n- },\n-/* sth [$dstle+$offset16],$imm32 */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', '[', OP (DSTLE), '+', OP (OFFSET16), ']', ',', OP (IMM32), 0 } },\n- & ifmt_stble, { 0x6a }\n- },\n-/* stw [$dstle+$offset16],$imm32 */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', '[', OP (DSTLE), '+', OP (OFFSET16), ']', ',', OP (IMM32), 0 } },\n- & ifmt_stble, { 0x62 }\n- },\n-/* stdw [$dstle+$offset16],$imm32 */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', '[', OP (DSTLE), '+', OP (OFFSET16), ']', ',', OP (IMM32), 0 } },\n- & ifmt_stble, { 0x7a }\n- },\n-/* stb [$dstbe+$offset16],$imm32 */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', '[', OP (DSTBE), '+', OP (OFFSET16), ']', ',', OP (IMM32), 0 } },\n- & ifmt_stbbe, { 0x72 }\n- },\n-/* sth [$dstbe+$offset16],$imm32 */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', '[', OP (DSTBE), '+', OP (OFFSET16), ']', ',', OP (IMM32), 0 } },\n- & ifmt_stbbe, { 0x6a }\n- },\n-/* stw [$dstbe+$offset16],$imm32 */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', '[', OP (DSTBE), '+', OP (OFFSET16), ']', ',', OP (IMM32), 0 } },\n- & ifmt_stbbe, { 0x62 }\n- },\n-/* stdw [$dstbe+$offset16],$imm32 */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', '[', OP (DSTBE), '+', OP (OFFSET16), ']', ',', OP (IMM32), 0 } },\n- & ifmt_stbbe, { 0x7a }\n- },\n-/* jeq $dstle,$imm32,$disp16 */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), ',', OP (DISP16), 0 } },\n- & ifmt_jeqile, { 0x15 }\n- },\n-/* jeq $dstle,$srcle,$disp16 */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), ',', OP (DISP16), 0 } },\n- & ifmt_jeqrle, { 0x1d }\n- },\n-/* jeq32 $dstle,$imm32,$disp16 */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), ',', OP (DISP16), 0 } },\n- & ifmt_jeqile, { 0x16 }\n- },\n-/* jeq32 $dstle,$srcle,$disp16 */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), ',', OP (DISP16), 0 } },\n- & ifmt_jeqrle, { 0x1e }\n- },\n-/* jgt $dstle,$imm32,$disp16 */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), ',', OP (DISP16), 0 } },\n- & ifmt_jeqile, { 0x25 }\n- },\n-/* jgt $dstle,$srcle,$disp16 */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), ',', OP (DISP16), 0 } },\n- & ifmt_jeqrle, { 0x2d }\n- },\n-/* jgt32 $dstle,$imm32,$disp16 */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), ',', OP (DISP16), 0 } },\n- & ifmt_jeqile, { 0x26 }\n- },\n-/* jgt32 $dstle,$srcle,$disp16 */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), ',', OP (DISP16), 0 } },\n- & ifmt_jeqrle, { 0x2e }\n- },\n-/* jge $dstle,$imm32,$disp16 */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), ',', OP (DISP16), 0 } },\n- & ifmt_jeqile, { 0x35 }\n- },\n-/* jge $dstle,$srcle,$disp16 */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), ',', OP (DISP16), 0 } },\n- & ifmt_jeqrle, { 0x3d }\n- },\n-/* jge32 $dstle,$imm32,$disp16 */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), ',', OP (DISP16), 0 } },\n- & ifmt_jeqile, { 0x36 }\n- },\n-/* jge32 $dstle,$srcle,$disp16 */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), ',', OP (DISP16), 0 } },\n- & ifmt_jeqrle, { 0x3e }\n- },\n-/* jlt $dstle,$imm32,$disp16 */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), ',', OP (DISP16), 0 } },\n- & ifmt_jeqile, { 0xa5 }\n- },\n-/* jlt $dstle,$srcle,$disp16 */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), ',', OP (DISP16), 0 } },\n- & ifmt_jeqrle, { 0xad }\n- },\n-/* jlt32 $dstle,$imm32,$disp16 */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), ',', OP (DISP16), 0 } },\n- & ifmt_jeqile, { 0xa6 }\n- },\n-/* jlt32 $dstle,$srcle,$disp16 */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), ',', OP (DISP16), 0 } },\n- & ifmt_jeqrle, { 0xae }\n- },\n-/* jle $dstle,$imm32,$disp16 */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), ',', OP (DISP16), 0 } },\n- & ifmt_jeqile, { 0xb5 }\n- },\n-/* jle $dstle,$srcle,$disp16 */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), ',', OP (DISP16), 0 } },\n- & ifmt_jeqrle, { 0xbd }\n- },\n-/* jle32 $dstle,$imm32,$disp16 */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), ',', OP (DISP16), 0 } },\n- & ifmt_jeqile, { 0xb6 }\n- },\n-/* jle32 $dstle,$srcle,$disp16 */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), ',', OP (DISP16), 0 } },\n- & ifmt_jeqrle, { 0xbe }\n- },\n-/* jset $dstle,$imm32,$disp16 */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), ',', OP (DISP16), 0 } },\n- & ifmt_jeqile, { 0x45 }\n- },\n-/* jset $dstle,$srcle,$disp16 */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), ',', OP (DISP16), 0 } },\n- & ifmt_jeqrle, { 0x4d }\n- },\n-/* jset32 $dstle,$imm32,$disp16 */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), ',', OP (DISP16), 0 } },\n- & ifmt_jeqile, { 0x46 }\n- },\n-/* jset32 $dstle,$srcle,$disp16 */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), ',', OP (DISP16), 0 } },\n- & ifmt_jeqrle, { 0x4e }\n- },\n-/* jne $dstle,$imm32,$disp16 */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), ',', OP (DISP16), 0 } },\n- & ifmt_jeqile, { 0x55 }\n- },\n-/* jne $dstle,$srcle,$disp16 */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), ',', OP (DISP16), 0 } },\n- & ifmt_jeqrle, { 0x5d }\n- },\n-/* jne32 $dstle,$imm32,$disp16 */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), ',', OP (DISP16), 0 } },\n- & ifmt_jeqile, { 0x56 }\n- },\n-/* jne32 $dstle,$srcle,$disp16 */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), ',', OP (DISP16), 0 } },\n- & ifmt_jeqrle, { 0x5e }\n- },\n-/* jsgt $dstle,$imm32,$disp16 */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), ',', OP (DISP16), 0 } },\n- & ifmt_jeqile, { 0x65 }\n- },\n-/* jsgt $dstle,$srcle,$disp16 */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), ',', OP (DISP16), 0 } },\n- & ifmt_jeqrle, { 0x6d }\n- },\n-/* jsgt32 $dstle,$imm32,$disp16 */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), ',', OP (DISP16), 0 } },\n- & ifmt_jeqile, { 0x66 }\n- },\n-/* jsgt32 $dstle,$srcle,$disp16 */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), ',', OP (DISP16), 0 } },\n- & ifmt_jeqrle, { 0x6e }\n- },\n-/* jsge $dstle,$imm32,$disp16 */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), ',', OP (DISP16), 0 } },\n- & ifmt_jeqile, { 0x75 }\n- },\n-/* jsge $dstle,$srcle,$disp16 */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), ',', OP (DISP16), 0 } },\n- & ifmt_jeqrle, { 0x7d }\n- },\n-/* jsge32 $dstle,$imm32,$disp16 */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), ',', OP (DISP16), 0 } },\n- & ifmt_jeqile, { 0x76 }\n- },\n-/* jsge32 $dstle,$srcle,$disp16 */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), ',', OP (DISP16), 0 } },\n- & ifmt_jeqrle, { 0x7e }\n- },\n-/* jslt $dstle,$imm32,$disp16 */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), ',', OP (DISP16), 0 } },\n- & ifmt_jeqile, { 0xc5 }\n- },\n-/* jslt $dstle,$srcle,$disp16 */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), ',', OP (DISP16), 0 } },\n- & ifmt_jeqrle, { 0xcd }\n- },\n-/* jslt32 $dstle,$imm32,$disp16 */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), ',', OP (DISP16), 0 } },\n- & ifmt_jeqile, { 0xc6 }\n- },\n-/* jslt32 $dstle,$srcle,$disp16 */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), ',', OP (DISP16), 0 } },\n- & ifmt_jeqrle, { 0xce }\n- },\n-/* jsle $dstle,$imm32,$disp16 */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), ',', OP (DISP16), 0 } },\n- & ifmt_jeqile, { 0xd5 }\n- },\n-/* jsle $dstle,$srcle,$disp16 */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), ',', OP (DISP16), 0 } },\n- & ifmt_jeqrle, { 0xdd }\n- },\n-/* jsle32 $dstle,$imm32,$disp16 */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), ',', OP (DISP16), 0 } },\n- & ifmt_jeqile, { 0xd6 }\n- },\n-/* jsle32 $dstle,$srcle,$disp16 */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), ',', OP (DISP16), 0 } },\n- & ifmt_jeqrle, { 0xde }\n- },\n-/* jeq $dstbe,$imm32,$disp16 */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), ',', OP (DISP16), 0 } },\n- & ifmt_jeqibe, { 0x15 }\n- },\n-/* jeq $dstbe,$srcbe,$disp16 */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), ',', OP (DISP16), 0 } },\n- & ifmt_jeqrbe, { 0x1d }\n- },\n-/* jeq32 $dstbe,$imm32,$disp16 */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), ',', OP (DISP16), 0 } },\n- & ifmt_jeqibe, { 0x16 }\n- },\n-/* jeq32 $dstbe,$srcbe,$disp16 */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), ',', OP (DISP16), 0 } },\n- & ifmt_jeqrbe, { 0x1e }\n- },\n-/* jgt $dstbe,$imm32,$disp16 */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), ',', OP (DISP16), 0 } },\n- & ifmt_jeqibe, { 0x25 }\n- },\n-/* jgt $dstbe,$srcbe,$disp16 */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), ',', OP (DISP16), 0 } },\n- & ifmt_jeqrbe, { 0x2d }\n- },\n-/* jgt32 $dstbe,$imm32,$disp16 */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), ',', OP (DISP16), 0 } },\n- & ifmt_jeqibe, { 0x26 }\n- },\n-/* jgt32 $dstbe,$srcbe,$disp16 */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), ',', OP (DISP16), 0 } },\n- & ifmt_jeqrbe, { 0x2e }\n- },\n-/* jge $dstbe,$imm32,$disp16 */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), ',', OP (DISP16), 0 } },\n- & ifmt_jeqibe, { 0x35 }\n- },\n-/* jge $dstbe,$srcbe,$disp16 */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), ',', OP (DISP16), 0 } },\n- & ifmt_jeqrbe, { 0x3d }\n- },\n-/* jge32 $dstbe,$imm32,$disp16 */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), ',', OP (DISP16), 0 } },\n- & ifmt_jeqibe, { 0x36 }\n- },\n-/* jge32 $dstbe,$srcbe,$disp16 */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), ',', OP (DISP16), 0 } },\n- & ifmt_jeqrbe, { 0x3e }\n- },\n-/* jlt $dstbe,$imm32,$disp16 */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), ',', OP (DISP16), 0 } },\n- & ifmt_jeqibe, { 0xa5 }\n- },\n-/* jlt $dstbe,$srcbe,$disp16 */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), ',', OP (DISP16), 0 } },\n- & ifmt_jeqrbe, { 0xad }\n- },\n-/* jlt32 $dstbe,$imm32,$disp16 */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), ',', OP (DISP16), 0 } },\n- & ifmt_jeqibe, { 0xa6 }\n- },\n-/* jlt32 $dstbe,$srcbe,$disp16 */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), ',', OP (DISP16), 0 } },\n- & ifmt_jeqrbe, { 0xae }\n- },\n-/* jle $dstbe,$imm32,$disp16 */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), ',', OP (DISP16), 0 } },\n- & ifmt_jeqibe, { 0xb5 }\n- },\n-/* jle $dstbe,$srcbe,$disp16 */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), ',', OP (DISP16), 0 } },\n- & ifmt_jeqrbe, { 0xbd }\n- },\n-/* jle32 $dstbe,$imm32,$disp16 */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), ',', OP (DISP16), 0 } },\n- & ifmt_jeqibe, { 0xb6 }\n- },\n-/* jle32 $dstbe,$srcbe,$disp16 */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), ',', OP (DISP16), 0 } },\n- & ifmt_jeqrbe, { 0xbe }\n- },\n-/* jset $dstbe,$imm32,$disp16 */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), ',', OP (DISP16), 0 } },\n- & ifmt_jeqibe, { 0x45 }\n- },\n-/* jset $dstbe,$srcbe,$disp16 */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), ',', OP (DISP16), 0 } },\n- & ifmt_jeqrbe, { 0x4d }\n- },\n-/* jset32 $dstbe,$imm32,$disp16 */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), ',', OP (DISP16), 0 } },\n- & ifmt_jeqibe, { 0x46 }\n- },\n-/* jset32 $dstbe,$srcbe,$disp16 */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), ',', OP (DISP16), 0 } },\n- & ifmt_jeqrbe, { 0x4e }\n- },\n-/* jne $dstbe,$imm32,$disp16 */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), ',', OP (DISP16), 0 } },\n- & ifmt_jeqibe, { 0x55 }\n- },\n-/* jne $dstbe,$srcbe,$disp16 */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), ',', OP (DISP16), 0 } },\n- & ifmt_jeqrbe, { 0x5d }\n- },\n-/* jne32 $dstbe,$imm32,$disp16 */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), ',', OP (DISP16), 0 } },\n- & ifmt_jeqibe, { 0x56 }\n- },\n-/* jne32 $dstbe,$srcbe,$disp16 */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), ',', OP (DISP16), 0 } },\n- & ifmt_jeqrbe, { 0x5e }\n- },\n-/* jsgt $dstbe,$imm32,$disp16 */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), ',', OP (DISP16), 0 } },\n- & ifmt_jeqibe, { 0x65 }\n- },\n-/* jsgt $dstbe,$srcbe,$disp16 */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), ',', OP (DISP16), 0 } },\n- & ifmt_jeqrbe, { 0x6d }\n- },\n-/* jsgt32 $dstbe,$imm32,$disp16 */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), ',', OP (DISP16), 0 } },\n- & ifmt_jeqibe, { 0x66 }\n- },\n-/* jsgt32 $dstbe,$srcbe,$disp16 */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), ',', OP (DISP16), 0 } },\n- & ifmt_jeqrbe, { 0x6e }\n- },\n-/* jsge $dstbe,$imm32,$disp16 */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), ',', OP (DISP16), 0 } },\n- & ifmt_jeqibe, { 0x75 }\n- },\n-/* jsge $dstbe,$srcbe,$disp16 */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), ',', OP (DISP16), 0 } },\n- & ifmt_jeqrbe, { 0x7d }\n- },\n-/* jsge32 $dstbe,$imm32,$disp16 */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), ',', OP (DISP16), 0 } },\n- & ifmt_jeqibe, { 0x76 }\n- },\n-/* jsge32 $dstbe,$srcbe,$disp16 */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), ',', OP (DISP16), 0 } },\n- & ifmt_jeqrbe, { 0x7e }\n- },\n-/* jslt $dstbe,$imm32,$disp16 */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), ',', OP (DISP16), 0 } },\n- & ifmt_jeqibe, { 0xc5 }\n- },\n-/* jslt $dstbe,$srcbe,$disp16 */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), ',', OP (DISP16), 0 } },\n- & ifmt_jeqrbe, { 0xcd }\n- },\n-/* jslt32 $dstbe,$imm32,$disp16 */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), ',', OP (DISP16), 0 } },\n- & ifmt_jeqibe, { 0xc6 }\n- },\n-/* jslt32 $dstbe,$srcbe,$disp16 */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), ',', OP (DISP16), 0 } },\n- & ifmt_jeqrbe, { 0xce }\n- },\n-/* jsle $dstbe,$imm32,$disp16 */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), ',', OP (DISP16), 0 } },\n- & ifmt_jeqibe, { 0xd5 }\n- },\n-/* jsle $dstbe,$srcbe,$disp16 */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), ',', OP (DISP16), 0 } },\n- & ifmt_jeqrbe, { 0xdd }\n- },\n-/* jsle32 $dstbe,$imm32,$disp16 */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), ',', OP (DISP16), 0 } },\n- & ifmt_jeqibe, { 0xd6 }\n- },\n-/* jsle32 $dstbe,$srcbe,$disp16 */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), ',', OP (DISP16), 0 } },\n- & ifmt_jeqrbe, { 0xde }\n- },\n-/* call $disp32 */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DISP32), 0 } },\n- & ifmt_callle, { 0x85 }\n- },\n-/* call $disp32 */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DISP32), 0 } },\n- & ifmt_callbe, { 0x85 }\n- },\n-/* call $dstle */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTLE), 0 } },\n- & ifmt_negle, { 0x8d }\n- },\n-/* call $dstbe */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DSTBE), 0 } },\n- & ifmt_negbe, { 0x8d }\n- },\n-/* ja $disp16 */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', OP (DISP16), 0 } },\n- & ifmt_ja, { 0x5 }\n- },\n-/* exit */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, 0 } },\n- & ifmt_exit, { 0x95 }\n- },\n-/* xadddw [$dstle+$offset16],$srcle */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', '[', OP (DSTLE), '+', OP (OFFSET16), ']', ',', OP (SRCLE), 0 } },\n- & ifmt_ldxwle, { 0xdb }\n- },\n-/* xaddw [$dstle+$offset16],$srcle */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', '[', OP (DSTLE), '+', OP (OFFSET16), ']', ',', OP (SRCLE), 0 } },\n- & ifmt_ldxwle, { 0xc3 }\n- },\n-/* xadddw [$dstbe+$offset16],$srcbe */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', '[', OP (DSTBE), '+', OP (OFFSET16), ']', ',', OP (SRCBE), 0 } },\n- & ifmt_ldxwbe, { 0xdb }\n- },\n-/* xaddw [$dstbe+$offset16],$srcbe */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, ' ', '[', OP (DSTBE), '+', OP (OFFSET16), ']', ',', OP (SRCBE), 0 } },\n- & ifmt_ldxwbe, { 0xc3 }\n- },\n-/* brkpt */\n- {\n- { 0, 0, 0, 0 },\n- { { MNEM, 0 } },\n- & ifmt_exit, { 0x8c }\n- },\n+ /* id, normal, pseudoc, version, mask, opcodes */\n+\n+ /* ALU instructions. */\n+ {BPF_INSN_ADDR, \"add%W%dr , %sr\", \"%dr += %sr\",\n+ BPF_V1, BPF_CODE, BPF_CLASS_ALU64|BPF_CODE_ADD|BPF_SRC_X},\n+ {BPF_INSN_ADDI, \"add%W%dr , %i32\", \"%dr += %i32\",\n+ BPF_V1, BPF_CODE, BPF_CLASS_ALU64|BPF_CODE_ADD|BPF_SRC_K},\n+ {BPF_INSN_SUBR, \"sub%W%dr , %sr\", \"%dr -= %sr\",\n+ BPF_V1, BPF_CODE, BPF_CLASS_ALU64|BPF_CODE_SUB|BPF_SRC_X},\n+ {BPF_INSN_SUBI, \"sub%W%dr , %i32\", \"%dr -= %i32\",\n+ BPF_V1, BPF_CODE, BPF_CLASS_ALU64|BPF_CODE_SUB|BPF_SRC_K},\n+ {BPF_INSN_MULR, \"mul%W%dr , %sr\", \"%dr *= %sr\",\n+ BPF_V1, BPF_CODE, BPF_CLASS_ALU64|BPF_CODE_MUL|BPF_SRC_X},\n+ {BPF_INSN_MULI, \"mul%W%dr , %i32\", \"%dr *= %i32\",\n+ BPF_V1, BPF_CODE, BPF_CLASS_ALU64|BPF_CODE_MUL|BPF_SRC_K},\n+ {BPF_INSN_SDIVR, \"sdiv%W%dr, %sr\", \"%dr s/= %sr\",\n+ BPF_V4, BPF_CODE|BPF_OFFSET16, BPF_CLASS_ALU64|BPF_CODE_DIV|BPF_SRC_X|BPF_OFFSET16_SDIVMOD},\n+ {BPF_INSN_SDIVI, \"sdiv%W%dr , %i32\",\"%dr s/= %i32\",\n+ BPF_V4, BPF_CODE|BPF_OFFSET16, BPF_CLASS_ALU64|BPF_CODE_DIV|BPF_SRC_K|BPF_OFFSET16_SDIVMOD},\n+ {BPF_INSN_SMODR, \"smod%W%dr , %sr\", \"%dr s%%= %sr\",\n+ BPF_V4, BPF_CODE|BPF_OFFSET16, BPF_CLASS_ALU64|BPF_CODE_MOD|BPF_SRC_X|BPF_OFFSET16_SDIVMOD},\n+ {BPF_INSN_SMODI, \"smod%W%dr , %i32\", \"%dr s%%= %i32\",\n+ BPF_V4, BPF_CODE|BPF_OFFSET16, BPF_CLASS_ALU64|BPF_CODE_MOD|BPF_SRC_K|BPF_OFFSET16_SDIVMOD},\n+ {BPF_INSN_DIVR, \"div%W%dr , %sr\", \"%dr /= %sr\",\n+ BPF_V1, BPF_CODE, BPF_CLASS_ALU64|BPF_CODE_DIV|BPF_SRC_X},\n+ {BPF_INSN_DIVI, \"div%W%dr , %i32\", \"%dr /= %i32\",\n+ BPF_V1, BPF_CODE, BPF_CLASS_ALU64|BPF_CODE_DIV|BPF_SRC_K},\n+ {BPF_INSN_MODR, \"mod%W%dr , %sr\", \"%dr %%= %sr\",\n+ BPF_V1, BPF_CODE, BPF_CLASS_ALU64|BPF_CODE_MOD|BPF_SRC_X},\n+ {BPF_INSN_MODI, \"mod%W%dr , %i32\", \"%dr %%= %i32\",\n+ BPF_V1, BPF_CODE, BPF_CLASS_ALU64|BPF_CODE_MOD|BPF_SRC_K},\n+ {BPF_INSN_ORR, \"or%W%dr , %sr\", \"%dr |= %sr\",\n+ BPF_V1, BPF_CODE, BPF_CLASS_ALU64|BPF_CODE_OR|BPF_SRC_X},\n+ {BPF_INSN_ORI, \"or%W%dr , %i32\", \"%dr |= %i32\",\n+ BPF_V1, BPF_CODE, BPF_CLASS_ALU64|BPF_CODE_OR|BPF_SRC_K},\n+ {BPF_INSN_ANDR, \"and%W%dr , %sr\", \"%dr &= %sr\",\n+ BPF_V1, BPF_CODE, BPF_CLASS_ALU64|BPF_CODE_AND|BPF_SRC_X},\n+ {BPF_INSN_ANDI, \"and%W%dr , %i32\", \"%dr &= %i32\",\n+ BPF_V1, BPF_CODE, BPF_CLASS_ALU64|BPF_CODE_AND|BPF_SRC_K},\n+ {BPF_INSN_XORR, \"xor%W%dr , %sr\", \"%dr ^= %sr\",\n+ BPF_V1, BPF_CODE, BPF_CLASS_ALU64|BPF_CODE_XOR|BPF_SRC_X},\n+ {BPF_INSN_XORI, \"xor%W%dr , %i32\", \"%dr ^= %i32\",\n+ BPF_V1, BPF_CODE, BPF_CLASS_ALU64|BPF_CODE_XOR|BPF_SRC_K},\n+ {BPF_INSN_NEGR, \"neg%W%dr, %sr\", \"%dr = - %sr\",\n+ BPF_V1, BPF_CODE, BPF_CLASS_ALU64|BPF_CODE_NEG|BPF_SRC_X},\n+ {BPF_INSN_NEGI, \"neg%W%dr , %i32\", \"%dr = -%W%i32\",\n+ BPF_V1, BPF_CODE, BPF_CLASS_ALU64|BPF_CODE_NEG|BPF_SRC_K},\n+ {BPF_INSN_LSHR, \"lsh%W%dr , %sr\", \"%dr <<= %sr\",\n+ BPF_V1, BPF_CODE, BPF_CLASS_ALU64|BPF_CODE_LSH|BPF_SRC_X},\n+ {BPF_INSN_LSHI, \"lsh%W%dr , %i32\", \"%dr <<= %i32\",\n+ BPF_V1, BPF_CODE, BPF_CLASS_ALU64|BPF_CODE_LSH|BPF_SRC_K},\n+ {BPF_INSN_RSHR, \"rsh%W%dr , %sr\", \"%dr >>= %sr\",\n+ BPF_V1, BPF_CODE, BPF_CLASS_ALU64|BPF_CODE_RSH|BPF_SRC_X},\n+ {BPF_INSN_RSHI, \"rsh%W%dr , %i32\", \"%dr >>= %i32\",\n+ BPF_V1, BPF_CODE, BPF_CLASS_ALU64|BPF_CODE_RSH|BPF_SRC_K},\n+ {BPF_INSN_ARSHR, \"arsh%W%dr , %sr\", \"%dr%ws>>= %sr\",\n+ BPF_V1, BPF_CODE, BPF_CLASS_ALU64|BPF_CODE_ARSH|BPF_SRC_X},\n+ {BPF_INSN_ARSHI, \"arsh%W%dr , %i32\", \"%dr%ws>>= %i32\",\n+ BPF_V1, BPF_CODE, BPF_CLASS_ALU64|BPF_CODE_ARSH|BPF_SRC_K},\n+ {BPF_INSN_MOVR, \"mov%W%dr , %sr\", \"%dr = %sr\",\n+ BPF_V1, BPF_CODE, BPF_CLASS_ALU64|BPF_CODE_MOV|BPF_SRC_X},\n+ {BPF_INSN_MOVI, \"mov%W%dr , %i32\", \"%dr = %i32\",\n+ BPF_V1, BPF_CODE, BPF_CLASS_ALU64|BPF_CODE_MOV|BPF_SRC_K},\n+\n+ /* ALU32 instructions. */\n+ {BPF_INSN_ADD32R, \"add32%W%dr , %sr\", \"%dw += %sw\",\n+ BPF_V1, BPF_CODE, BPF_CLASS_ALU|BPF_CODE_ADD|BPF_SRC_X},\n+ {BPF_INSN_ADD32I, \"add32%W%dr , %i32\", \"%dw += %i32\",\n+ BPF_V1, BPF_CODE, BPF_CLASS_ALU|BPF_CODE_ADD|BPF_SRC_K},\n+ {BPF_INSN_SUB32R, \"sub32%W%dr , %sr\", \"%dw -= %sw\",\n+ BPF_V1, BPF_CODE, BPF_CLASS_ALU|BPF_CODE_SUB|BPF_SRC_X},\n+ {BPF_INSN_SUB32I, \"sub32%W%dr , %i32\", \"%dw -= %i32\",\n+ BPF_V1, BPF_CODE, BPF_CLASS_ALU|BPF_CODE_SUB|BPF_SRC_K},\n+ {BPF_INSN_MUL32R, \"mul32%W%dr , %sr\", \"%dw *= %sw\",\n+ BPF_V1, BPF_CODE, BPF_CLASS_ALU|BPF_CODE_MUL|BPF_SRC_X},\n+ {BPF_INSN_MUL32I, \"mul32%W%dr , %i32\", \"%dw *= %i32\",\n+ BPF_V1, BPF_CODE, BPF_CLASS_ALU|BPF_CODE_MUL|BPF_SRC_K},\n+ {BPF_INSN_SDIV32R, \"sdiv32%W%dr , %sr\", \"%dw s/= %sw\",\n+ BPF_V4, BPF_CODE|BPF_OFFSET16, BPF_CLASS_ALU|BPF_CODE_DIV|BPF_SRC_X|BPF_OFFSET16_SDIVMOD},\n+ {BPF_INSN_SDIV32I, \"sdiv32%W%dr , %i32\", \"%dw s/= %i32\",\n+ BPF_V4, BPF_CODE|BPF_OFFSET16, BPF_CLASS_ALU|BPF_CODE_DIV|BPF_SRC_K|BPF_OFFSET16_SDIVMOD},\n+ {BPF_INSN_SMOD32R, \"smod32%W%dr , %sr\", \"%dw s%%= %sw\",\n+ BPF_V4, BPF_CODE|BPF_OFFSET16, BPF_CLASS_ALU|BPF_CODE_MOD|BPF_SRC_X|BPF_OFFSET16_SDIVMOD},\n+ {BPF_INSN_SMOD32I, \"smod32%W%dr , %i32\", \"%dw s%%= %i32\",\n+ BPF_V4, BPF_CODE|BPF_OFFSET16, BPF_CLASS_ALU|BPF_CODE_MOD|BPF_SRC_K|BPF_OFFSET16_SDIVMOD},\n+ {BPF_INSN_DIV32R, \"div32%W%dr , %sr\", \"%dw /= %sw\",\n+ BPF_V1, BPF_CODE, BPF_CLASS_ALU|BPF_CODE_DIV|BPF_SRC_X},\n+ {BPF_INSN_DIV32I, \"div32%W%dr , %i32\", \"%dw /= %i32\",\n+ BPF_V1, BPF_CODE, BPF_CLASS_ALU|BPF_CODE_DIV|BPF_SRC_K},\n+ {BPF_INSN_MOD32R, \"mod32%W%dr , %sr\", \"%dw %%= %sw\",\n+ BPF_V1, BPF_CODE, BPF_CLASS_ALU|BPF_CODE_MOD|BPF_SRC_X},\n+ {BPF_INSN_MOD32I, \"mod32%W%dr , %i32\", \"%dw %%= %i32\",\n+ BPF_V1, BPF_CODE, BPF_CLASS_ALU|BPF_CODE_MOD|BPF_SRC_K},\n+ {BPF_INSN_OR32R, \"or32%W%dr , %sr\", \"%dw |= %sw\",\n+ BPF_V1, BPF_CODE, BPF_CLASS_ALU|BPF_CODE_OR|BPF_SRC_X},\n+ {BPF_INSN_OR32I, \"or32%W%dr , %i32\", \"%dw |= %i32\",\n+ BPF_V1, BPF_CODE, BPF_CLASS_ALU|BPF_CODE_OR|BPF_SRC_K},\n+ {BPF_INSN_AND32R, \"and32%W%dr , %sr\", \"%dw &= %sw\",\n+ BPF_V1, BPF_CODE, BPF_CLASS_ALU|BPF_CODE_AND|BPF_SRC_X},\n+ {BPF_INSN_AND32I, \"and32%W%dr , %i32\", \"%dw &= %i32\",\n+ BPF_V1, BPF_CODE, BPF_CLASS_ALU|BPF_CODE_AND|BPF_SRC_K},\n+ {BPF_INSN_XOR32R, \"xor32%W%dr , %sr\", \"%dw ^= %sw\",\n+ BPF_V1, BPF_CODE, BPF_CLASS_ALU|BPF_CODE_XOR|BPF_SRC_X},\n+ {BPF_INSN_XOR32I, \"xor32%W%dr , %i32\", \"%dw ^= %i32\",\n+ BPF_V1, BPF_CODE, BPF_CLASS_ALU|BPF_CODE_XOR|BPF_SRC_K},\n+ {BPF_INSN_NEG32R, \"neg32%W%dr , %sr\", \"%dw = - %sw\",\n+ BPF_V1, BPF_CODE, BPF_CLASS_ALU|BPF_CODE_NEG|BPF_SRC_X},\n+ {BPF_INSN_NEG32I, \"neg32%W%dr , %i32\", \"%dw = -%W%i32\",\n+ BPF_V1, BPF_CODE, BPF_CLASS_ALU|BPF_CODE_NEG|BPF_SRC_K},\n+ {BPF_INSN_LSH32R, \"lsh32%W%dr , %sr\", \"%dw <<= %sw\",\n+ BPF_V1, BPF_CODE, BPF_CLASS_ALU|BPF_CODE_LSH|BPF_SRC_X},\n+ {BPF_INSN_LSH32I, \"lsh32%W%dr , %i32\", \"%dw <<= %i32\",\n+ BPF_V1, BPF_CODE, BPF_CLASS_ALU|BPF_CODE_LSH|BPF_SRC_K},\n+ {BPF_INSN_RSH32R, \"rsh32%W%dr , %sr\", \"%dw >>= %sw\",\n+ BPF_V1, BPF_CODE, BPF_CLASS_ALU|BPF_CODE_RSH|BPF_SRC_X},\n+ {BPF_INSN_RSH32I, \"rsh32%W%dr , %i32\", \"%dw >>= %i32\",\n+ BPF_V1, BPF_CODE, BPF_CLASS_ALU|BPF_CODE_RSH|BPF_SRC_K},\n+ {BPF_INSN_ARSH32R, \"arsh32%W%dr , %sr\", \"%dw%ws>>= %sw\",\n+ BPF_V1, BPF_CODE, BPF_CLASS_ALU|BPF_CODE_ARSH|BPF_SRC_X},\n+ {BPF_INSN_ARSH32I, \"arsh32%W%dr , %i32\", \"%dw%Ws>>= %i32\",\n+ BPF_V1, BPF_CODE, BPF_CLASS_ALU|BPF_CODE_ARSH|BPF_SRC_K},\n+ {BPF_INSN_MOV32R, \"mov32%W%dr , %sr\", \"%dw = %sw\",\n+ BPF_V1, BPF_CODE, BPF_CLASS_ALU|BPF_CODE_MOV|BPF_SRC_X},\n+ {BPF_INSN_MOV32I, \"mov32%W%dr , %i32\", \"%dw = %i32\",\n+ BPF_V1, BPF_CODE, BPF_CLASS_ALU|BPF_CODE_MOV|BPF_SRC_K},\n+\n+ /* Endianness conversion instructions. */\n+ {BPF_INSN_ENDLE16, \"endle%W%dr , 16\", \"%dr = le16%w%dr\",\n+ BPF_V1, BPF_CODE|BPF_IMM32, BPF_CLASS_ALU|BPF_CODE_END|BPF_SRC_K|BPF_IMM32_END16},\n+ {BPF_INSN_ENDLE32, \"endle%W%dr , 32\", \"%dr = le32%w%dr\",\n+ BPF_V1, BPF_CODE|BPF_IMM32, BPF_CLASS_ALU|BPF_CODE_END|BPF_SRC_K|BPF_IMM32_END32},\n+ {BPF_INSN_ENDLE64, \"endle%W%dr , 64\", \"%dr = le64%w%dr\",\n+ BPF_V1, BPF_CODE|BPF_IMM32, BPF_CLASS_ALU|BPF_CODE_END|BPF_SRC_K|BPF_IMM32_END64},\n+ {BPF_INSN_ENDBE16, \"endbe%W%dr , 16\", \"%dr = be16%w%dr\",\n+ BPF_V1, BPF_CODE|BPF_IMM32, BPF_CLASS_ALU|BPF_CODE_END|BPF_SRC_X|BPF_IMM32_END16},\n+ {BPF_INSN_ENDBE32, \"endbe%W%dr , 32\", \"%dr = be32%w%dr\",\n+ BPF_V1, BPF_CODE|BPF_IMM32, BPF_CLASS_ALU|BPF_CODE_END|BPF_SRC_X|BPF_IMM32_END32},\n+ {BPF_INSN_ENDBE64, \"endbe%W%dr , 64\", \"%dr = be64%w%dr\",\n+ BPF_V1, BPF_CODE|BPF_IMM32, BPF_CLASS_ALU|BPF_CODE_END|BPF_SRC_X|BPF_IMM32_END64},\n+\n+ /* 64-bit load instruction. */\n+ {BPF_INSN_LDDW, \"lddw%W%dr , %i64\", \"%dr = %i64%wll\",\n+ BPF_V1, BPF_CODE, BPF_CLASS_LD|BPF_SIZE_DW|BPF_MODE_IMM},\n+\n+ /* Indirect load instructions, designed to be used in socket\n+ filters. */\n+ {BPF_INSN_LDINDB, \"ldindb%W%sr , %i32\", \"r0 = * ( u8 * ) skb [ %sr %I32 ]\",\n+ BPF_V1, BPF_CODE, BPF_CLASS_LD|BPF_SIZE_B|BPF_MODE_IND},\n+ {BPF_INSN_LDINDH, \"ldindh%W%sr , %i32\", \"r0 = * ( u16 * ) skb [ %sr %I32 ]\",\n+ BPF_V1, BPF_CODE, BPF_CLASS_LD|BPF_SIZE_H|BPF_MODE_IND},\n+ {BPF_INSN_LDINDW, \"ldindw%W%sr , %i32\", \"r0 = * ( u32 * ) skb [ %sr %I32 ]\",\n+ BPF_V1, BPF_CODE, BPF_CLASS_LD|BPF_SIZE_W|BPF_MODE_IND},\n+ {BPF_INSN_LDINDDW, \"ldinddw%W%sr , %i32\", \"r0 = * ( u64 * ) skb [ %sr %I32 ]\",\n+ BPF_V1, BPF_CODE, BPF_CLASS_LD|BPF_SIZE_DW|BPF_MODE_IND},\n+\n+ /* Absolute load instructions, designed to be used in socket filters. */\n+ {BPF_INSN_LDABSB, \"ldabsb%W%i32\", \"r0 = * ( u8 * ) skb [ %i32 ]\",\n+ BPF_V1, BPF_CODE, BPF_CLASS_LD|BPF_SIZE_B|BPF_MODE_ABS},\n+ {BPF_INSN_LDABSH, \"ldabsh%W%i32\", \"r0 = * ( u16 * ) skb [ %i32 ]\",\n+ BPF_V1, BPF_CODE, BPF_CLASS_LD|BPF_SIZE_H|BPF_MODE_ABS},\n+ {BPF_INSN_LDABSW, \"ldabsw%W%i32\", \"r0 = * ( u32 * ) skb [ %i32 ]\",\n+ BPF_V1, BPF_CODE, BPF_CLASS_LD|BPF_SIZE_W|BPF_MODE_ABS},\n+ {BPF_INSN_LDABSDW, \"ldabsdw%W%i32\", \"r0 = * ( u64 * ) skb [ %i32 ]\",\n+ BPF_V1, BPF_CODE, BPF_CLASS_LD|BPF_SIZE_DW|BPF_MODE_ABS},\n+\n+ /* Generic load instructions (to register.) */\n+ {BPF_INSN_LDXB, \"ldxb%W%dr , [ %sr %o16 ]\", \"%dr = * ( u8 * ) ( %sr %o16 )\",\n+ BPF_V1, BPF_CODE, BPF_CLASS_LDX|BPF_SIZE_B|BPF_MODE_MEM},\n+ {BPF_INSN_LDXH, \"ldxh%W%dr , [ %sr %o16 ]\", \"%dr = * ( u16 * ) ( %sr %o16 )\",\n+ BPF_V1, BPF_CODE, BPF_CLASS_LDX|BPF_SIZE_H|BPF_MODE_MEM},\n+ {BPF_INSN_LDXW, \"ldxw%W%dr , [ %sr %o16 ]\", \"%dr = * ( u32 * ) ( %sr %o16 )\",\n+ BPF_V1, BPF_CODE, BPF_CLASS_LDX|BPF_SIZE_W|BPF_MODE_MEM},\n+ {BPF_INSN_LDXDW, \"ldxdw%W%dr , [ %sr %o16 ]\",\"%dr = * ( u64 * ) ( %sr %o16 )\",\n+ BPF_V1, BPF_CODE, BPF_CLASS_LDX|BPF_SIZE_DW|BPF_MODE_MEM},\n+\n+ /* Generic store instructions (from register.) */\n+ {BPF_INSN_STXBR, \"stxb%W[ %dr %o16 ] , %sr\", \"* ( u8 * ) ( %dr %o16 ) = %sr\",\n+ BPF_V1, BPF_CODE, BPF_CLASS_STX|BPF_SIZE_B|BPF_MODE_MEM},\n+ {BPF_INSN_STXHR, \"stxh%W[ %dr %o16 ] , %sr\", \"* ( u16 * ) ( %dr %o16 ) = %sr\",\n+ BPF_V1, BPF_CODE, BPF_CLASS_STX|BPF_SIZE_H|BPF_MODE_MEM},\n+ {BPF_INSN_STXWR, \"stxw%W[ %dr %o16 ], %sr\", \"* ( u32 * ) ( %dr %o16 ) = %sr\",\n+ BPF_V1, BPF_CODE, BPF_CLASS_STX|BPF_SIZE_W|BPF_MODE_MEM},\n+ {BPF_INSN_STXDWR, \"stxdw%W[ %dr %o16 ] , %sr\", \"* ( u64 * ) ( %dr %o16 ) = %sr\",\n+ BPF_V1, BPF_CODE, BPF_CLASS_STX|BPF_SIZE_DW|BPF_MODE_MEM},\n+\n+ /* Generic store instructions (from 32-bit immediate.) */\n+ {BPF_INSN_STXBI, \"stb%W[ %dr %o16 ] , %i32\", \"* ( u8 * ) ( %dr %o16 ) = %i32\",\n+ BPF_V1, BPF_CODE, BPF_CLASS_ST|BPF_SIZE_B|BPF_MODE_MEM},\n+ {BPF_INSN_STXHI, \"sth%W[ %dr %o16 ] , %i32\", \"* ( u16 * ) ( %dr %o16 ) = %i32\",\n+ BPF_V1, BPF_CODE, BPF_CLASS_ST|BPF_SIZE_H|BPF_MODE_MEM},\n+ {BPF_INSN_STXWI, \"stw%W[ %dr %o16 ] , %i32\", \"* ( u32 * ) ( %dr %o16 ) = %i32\",\n+ BPF_V1, BPF_CODE, BPF_CLASS_ST|BPF_SIZE_W|BPF_MODE_MEM},\n+ {BPF_INSN_STXDWI, \"stdw%W[ %dr %o16 ] , %i32\", \"* ( u64 * ) ( %dr %o16 ) = %i32\",\n+ BPF_V1, BPF_CODE, BPF_CLASS_ST|BPF_SIZE_DW|BPF_MODE_MEM},\n+\n+ /* Compare-and-jump instructions (reg OP reg). */\n+ {BPF_INSN_JAR, \"ja%W%d16\", \"goto%w%d16\",\n+ BPF_V1, BPF_CODE, BPF_CLASS_JMP|BPF_CODE_JA|BPF_SRC_K},\n+ {BPF_INSN_JEQR, \"jeq%W%dr , %sr , %d16\", \"if%w%dr == %sr%wgoto%w%d16\",\n+ BPF_V1, BPF_CODE, BPF_CLASS_JMP|BPF_CODE_JEQ|BPF_SRC_X},\n+ {BPF_INSN_JGTR, \"jgt%W%dr , %sr , %d16\", \"if%w%dr > %sr%wgoto%w%d16\",\n+ BPF_V1, BPF_CODE, BPF_CLASS_JMP|BPF_CODE_JGT|BPF_SRC_X},\n+ {BPF_INSN_JSGTR, \"jsgt%W%dr, %sr , %d16\", \"if%w%dr s> %sr%wgoto%w%d16\",\n+ BPF_V1, BPF_CODE, BPF_CLASS_JMP|BPF_CODE_JSGT|BPF_SRC_X},\n+ {BPF_INSN_JGER, \"jge%W%dr , %sr , %d16\", \"if%w%dr >= %sr%wgoto%w%d16\",\n+ BPF_V1, BPF_CODE, BPF_CLASS_JMP|BPF_CODE_JGE|BPF_SRC_X},\n+ {BPF_INSN_JSGER, \"jsge%W%dr , %sr , %d16\", \"if%w%dr s>= %sr%wgoto%w%d16\",\n+ BPF_V1, BPF_CODE, BPF_CLASS_JMP|BPF_CODE_JSGE|BPF_SRC_X},\n+ {BPF_INSN_JLTR, \"jlt%W%dr , %sr , %d16\", \"if%w%dr < %sr%wgoto%w%d16\",\n+ BPF_V1, BPF_CODE, BPF_CLASS_JMP|BPF_CODE_JLT|BPF_SRC_X},\n+ {BPF_INSN_JSLTR, \"jslt%W%dr , %sr , %d16\", \"if%w%dr s< %sr%wgoto%w%d16\",\n+ BPF_V1, BPF_CODE, BPF_CLASS_JMP|BPF_CODE_JSLT|BPF_SRC_X},\n+ {BPF_INSN_JLER, \"jle%W%dr , %sr , %d16\", \"if%w%dr <= %sr%wgoto%w%d16\",\n+ BPF_V1, BPF_CODE, BPF_CLASS_JMP|BPF_CODE_JLE|BPF_SRC_X},\n+ {BPF_INSN_JSLER, \"jsle%W%dr , %sr , %d16\", \"if%w%dr s<= %sr%wgoto%w%d16\",\n+ BPF_V1, BPF_CODE, BPF_CLASS_JMP|BPF_CODE_JSLE|BPF_SRC_X},\n+ {BPF_INSN_JSETR, \"jset%W%dr , %sr , %d16\", \"if%w%dr & %sr%wgoto%w%d16\",\n+ BPF_V1, BPF_CODE, BPF_CLASS_JMP|BPF_CODE_JSET|BPF_SRC_X},\n+ {BPF_INSN_JNER, \"jne%W%dr , %sr , %d16\", \"if%w%dr != %sr%wgoto%w%d16\",\n+ BPF_V1, BPF_CODE, BPF_CLASS_JMP|BPF_CODE_JNE|BPF_SRC_X},\n+ {BPF_INSN_CALLR, \"call%W%dr\", \"callx%w%dr\",\n+ BPF_XBPF, BPF_CODE, BPF_CLASS_JMP|BPF_CODE_CALL|BPF_SRC_X},\n+ {BPF_INSN_CALL, \"call%W%d32\", \"call%w%d32\",\n+ BPF_V1, BPF_CODE, BPF_CLASS_JMP|BPF_CODE_CALL|BPF_SRC_K},\n+ {BPF_INSN_EXIT, \"exit\", \"exit\",\n+ BPF_V1, BPF_CODE, BPF_CLASS_JMP|BPF_CODE_EXIT|BPF_SRC_K},\n+\n+ /* Compare-and-jump instructions (reg OP imm). */\n+ {BPF_INSN_JEQI, \"jeq%W%dr , %i32 , %d16\", \"if%w%dr == %i32%wgoto%w%d16\",\n+ BPF_V1, BPF_CODE, BPF_CLASS_JMP|BPF_CODE_JEQ|BPF_SRC_K},\n+ {BPF_INSN_JGTI, \"jgt%W%dr , %i32 , %d16\", \"if%w%dr > %i32%wgoto%w%d16\",\n+ BPF_V1, BPF_CODE, BPF_CLASS_JMP|BPF_CODE_JGT|BPF_SRC_K},\n+ {BPF_INSN_JSGTI, \"jsgt%W%dr, %i32 , %d16\", \"if%w%dr s> %i32%wgoto%w%d16\",\n+ BPF_V1, BPF_CODE, BPF_CLASS_JMP|BPF_CODE_JSGT|BPF_SRC_K},\n+ {BPF_INSN_JGEI, \"jge%W%dr , %i32 , %d16\", \"if%w%dr >= %i32%wgoto%w%d16\",\n+ BPF_V1, BPF_CODE, BPF_CLASS_JMP|BPF_CODE_JGE|BPF_SRC_K},\n+ {BPF_INSN_JSGEI, \"jsge%W%dr , %i32 , %d16\", \"if%w%dr s>= %i32%wgoto%w%d16\",\n+ BPF_V1, BPF_CODE, BPF_CLASS_JMP|BPF_CODE_JSGE|BPF_SRC_K},\n+ {BPF_INSN_JLTI, \"jlt%W%dr , %i32 , %d16\", \"if%w%dr < %i32%wgoto%w%d16\",\n+ BPF_V1, BPF_CODE, BPF_CLASS_JMP|BPF_CODE_JLT|BPF_SRC_K},\n+ {BPF_INSN_JSLTI, \"jslt%W%dr , %i32, %d16\", \"if%w%dr s< %i32%wgoto%w%d16\",\n+ BPF_V1, BPF_CODE, BPF_CLASS_JMP|BPF_CODE_JSLT|BPF_SRC_K},\n+ {BPF_INSN_JLEI, \"jle%W%dr , %i32 , %d16\", \"if%w%dr <= %i32%wgoto%w%d16\",\n+ BPF_V1, BPF_CODE, BPF_CLASS_JMP|BPF_CODE_JLE|BPF_SRC_K},\n+ {BPF_INSN_JSLEI, \"jsle%W%dr , %i32 , %d16\", \"if%w%dr s<= %i32%wgoto%w%d16\",\n+ BPF_V1, BPF_CODE, BPF_CLASS_JMP|BPF_CODE_JSLE|BPF_SRC_K},\n+ {BPF_INSN_JSETI, \"jset%W%dr , %i32 , %d16\", \"if%w%dr & %i32%wgoto%w%d16\",\n+ BPF_V1, BPF_CODE, BPF_CLASS_JMP|BPF_CODE_JSET|BPF_SRC_K},\n+ {BPF_INSN_JNEI, \"jne%W%dr , %i32 , %d16\", \"if%w%dr != %i32%wgoto%w%d16\",\n+ BPF_V1, BPF_CODE, BPF_CLASS_JMP|BPF_CODE_JNE|BPF_SRC_K},\n+\n+ /* 32-bit compare-and-jump instructions (reg OP reg). */\n+ {BPF_INSN_JEQ32R, \"jeq32%W%dr , %sr , %d16\", \"if%w%dw == %sw%wgoto%w%d16\",\n+ BPF_V3, BPF_CODE, BPF_CLASS_JMP32|BPF_CODE_JEQ|BPF_SRC_X},\n+ {BPF_INSN_JGT32R, \"jgt32%W%dr , %sr , %d16\", \"if%w%dw > %sw%wgoto%w%d16\",\n+ BPF_V3, BPF_CODE, BPF_CLASS_JMP32|BPF_CODE_JGT|BPF_SRC_X},\n+ {BPF_INSN_JSGT32R, \"jsgt32%W%dr, %sr , %d16\", \"if%w%dw s> %sw%wgoto%w%d16\",\n+ BPF_V3, BPF_CODE, BPF_CLASS_JMP32|BPF_CODE_JSGT|BPF_SRC_X},\n+ {BPF_INSN_JGE32R, \"jge32%W%dr , %sr , %d16\", \"if%w%dw >= %sw%wgoto%w%d16\",\n+ BPF_V3, BPF_CODE, BPF_CLASS_JMP32|BPF_CODE_JGE|BPF_SRC_X},\n+ {BPF_INSN_JSGE32R, \"jsge32%W%dr , %sr , %d16\", \"if%w%dw s>= %sw%wgoto%w%d16\",\n+ BPF_V3, BPF_CODE, BPF_CLASS_JMP32|BPF_CODE_JSGE|BPF_SRC_X},\n+ {BPF_INSN_JLT32R, \"jlt32%W%dr , %sr , %d16\", \"if%w%dw < %sw%wgoto%w%d16\",\n+ BPF_V3, BPF_CODE, BPF_CLASS_JMP32|BPF_CODE_JLT|BPF_SRC_X},\n+ {BPF_INSN_JSLT32R, \"jslt32%W%dr , %sr , %d16\", \"if%w%dw s< %sw%wgoto%w%d16\",\n+ BPF_V3, BPF_CODE, BPF_CLASS_JMP32|BPF_CODE_JSLT|BPF_SRC_X},\n+ {BPF_INSN_JLE32R, \"jle32%W%dr , %sr , %d16\", \"if%w%dw <= %sw%wgoto%w%d16\",\n+ BPF_V3, BPF_CODE, BPF_CLASS_JMP32|BPF_CODE_JLE|BPF_SRC_X},\n+ {BPF_INSN_JSLE32R, \"jsle32%W%dr , %sr , %d16\", \"if%w%dw s<= %sw%wgoto%w%d16\",\n+ BPF_V3, BPF_CODE, BPF_CLASS_JMP32|BPF_CODE_JSLE|BPF_SRC_X},\n+ {BPF_INSN_JSET32R, \"jset32%W%dr , %sr , %d16\", \"if%w%dw & %sw%wgoto%w%d16\",\n+ BPF_V3, BPF_CODE, BPF_CLASS_JMP32|BPF_CODE_JSET|BPF_SRC_X},\n+ {BPF_INSN_JNE32R, \"jne32%W%dr , %sr , %d16\", \"if%w%dw != %sw%wgoto%w%d16\",\n+ BPF_V3, BPF_CODE, BPF_CLASS_JMP32|BPF_CODE_JNE|BPF_SRC_X},\n+\n+ /* 32-bit compare-and-jump instructions (reg OP imm). */\n+ {BPF_INSN_JEQ32I, \"jeq32%W%dr , %i32 , %d16\", \"if%w%dw == %i32%wgoto%w%d16\",\n+ BPF_V3, BPF_CODE, BPF_CLASS_JMP32|BPF_CODE_JEQ|BPF_SRC_K},\n+ {BPF_INSN_JGT32I, \"jgt32%W%dr , %i32 , %d16\", \"if%w%dw > %i32%wgoto%w%d16\",\n+ BPF_V3, BPF_CODE, BPF_CLASS_JMP32|BPF_CODE_JGT|BPF_SRC_K},\n+ {BPF_INSN_JSGT32I, \"jsgt32%W%dr, %i32 , %d16\", \"if%w%dw s> %i32%wgoto%w%d16\",\n+ BPF_V3, BPF_CODE, BPF_CLASS_JMP32|BPF_CODE_JSGT|BPF_SRC_K},\n+ {BPF_INSN_JGE32I, \"jge32%W%dr , %i32 , %d16\", \"if%w%dw >= %i32%wgoto%w%d16\",\n+ BPF_V3, BPF_CODE, BPF_CLASS_JMP32|BPF_CODE_JGE|BPF_SRC_K},\n+ {BPF_INSN_JSGE32I, \"jsge32%W%dr , %i32 , %d16\", \"if%w%dw s>= %i32%wgoto%w%d16\",\n+ BPF_V3, BPF_CODE, BPF_CLASS_JMP32|BPF_CODE_JSGE|BPF_SRC_K},\n+ {BPF_INSN_JLT32I, \"jlt32%W%dr , %i32 , %d16\", \"if%w%dw < %i32%wgoto%w%d16\",\n+ BPF_V3, BPF_CODE, BPF_CLASS_JMP32|BPF_CODE_JLT|BPF_SRC_K},\n+ {BPF_INSN_JSLT32I, \"jslt32%W%dr , %i32, %d16\", \"if%w%dw s< %i32%wgoto%w%d16\",\n+ BPF_V3, BPF_CODE, BPF_CLASS_JMP32|BPF_CODE_JSLT|BPF_SRC_K},\n+ {BPF_INSN_JLE32I, \"jle32%W%dr , %i32 , %d16\", \"if%w%dw <= %i32%wgoto%w%d16\",\n+ BPF_V3, BPF_CODE, BPF_CLASS_JMP32|BPF_CODE_JLE|BPF_SRC_K},\n+ {BPF_INSN_JSLE32I, \"jsle32%W%dr , %i32 , %d16\", \"if%w%dw s<= %i32%wgoto%w%d16\",\n+ BPF_V3, BPF_CODE, BPF_CLASS_JMP32|BPF_CODE_JSLE|BPF_SRC_K},\n+ {BPF_INSN_JSET32I, \"jset32%W%dr , %i32 , %d16\", \"if%w%dw & %i32%wgoto%w%d16\",\n+ BPF_V3, BPF_CODE, BPF_CLASS_JMP32|BPF_CODE_JSET|BPF_SRC_K},\n+ {BPF_INSN_JNE32I, \"jne32%W%dr , %i32 , %d16\", \"if%w%dw != %i32%wgoto%w%d16\",\n+ BPF_V3, BPF_CODE, BPF_CLASS_JMP32|BPF_CODE_JNE|BPF_SRC_K},\n+\n+ /* Atomic instructions. */\n+ {BPF_INSN_AADD, \"aadd%W[ %dr %o16 ] , %sr\", \"* ( u64 * ) ( %dr %o16 ) += %sr\",\n+ BPF_V3, BPF_CODE|BPF_IMM32, BPF_CLASS_STX|BPF_SIZE_DW|BPF_MODE_ATOMIC|BPF_IMM32_AADD},\n+ {BPF_INSN_AOR, \"aor%W[ %dr %o16 ] , %sr\", \"* ( u64 * ) ( %dr %o16 ) |= %sr\",\n+ BPF_V3, BPF_CODE|BPF_IMM32, BPF_CLASS_STX|BPF_SIZE_DW|BPF_MODE_ATOMIC|BPF_IMM32_AOR},\n+ {BPF_INSN_AAND, \"aand%W[ %dr %o16 ] , %sr\", \"* ( u64 * ) ( %dr %o16 ) &= %sr\",\n+ BPF_V3, BPF_CODE|BPF_IMM32, BPF_CLASS_STX|BPF_SIZE_DW|BPF_MODE_ATOMIC|BPF_IMM32_AAND},\n+ {BPF_INSN_AXOR, \"axor%W[ %dr %o16 ] , %sr\", \"* ( u64 * ) ( %dr %o16 ) ^= %sr\",\n+ BPF_V3, BPF_CODE|BPF_IMM32, BPF_CLASS_STX|BPF_SIZE_DW|BPF_MODE_ATOMIC|BPF_IMM32_AXOR},\n+\n+ /* Atomic instructions with fetching. */\n+ {BPF_INSN_AFADD, \"afadd%W[ %dr %o16 ] , %sr\", \"???\",\n+ BPF_V3, BPF_CODE|BPF_IMM32, BPF_CLASS_STX|BPF_SIZE_DW|BPF_MODE_ATOMIC|BPF_IMM32_AFADD},\n+ {BPF_INSN_AFOR, \"afor%W[ %dr %o16 ] , %sr\", \"???\",\n+ BPF_V3, BPF_CODE|BPF_IMM32, BPF_CLASS_STX|BPF_SIZE_DW|BPF_MODE_ATOMIC|BPF_IMM32_AFOR},\n+ {BPF_INSN_AFAND, \"afand%W[ %dr %o16 ] , %sr\", \"???\",\n+ BPF_V3, BPF_CODE|BPF_IMM32, BPF_CLASS_STX|BPF_SIZE_DW|BPF_MODE_ATOMIC|BPF_IMM32_AFAND},\n+ {BPF_INSN_AFXOR, \"afxor%W[ %dr %o16 ] , %sr\", \"???\",\n+ BPF_V3, BPF_CODE|BPF_IMM32, BPF_CLASS_STX|BPF_SIZE_DW|BPF_MODE_ATOMIC|BPF_IMM32_AFXOR},\n+\n+ /* Atomic instructions (32-bit.) */\n+ {BPF_INSN_AADD32, \"aadd32%W[ %dr %o16 ] , %sr\", \"* ( u32 * ) ( %dr %o16 ) += %sr\",\n+ BPF_V3, BPF_CODE|BPF_IMM32, BPF_CLASS_STX|BPF_SIZE_W|BPF_MODE_ATOMIC|BPF_IMM32_AADD},\n+ {BPF_INSN_AOR32, \"aor32%W[ %dr %o16 ] , %sr\", \"* ( u32 * ) ( %dr %o16 ) |= %sr\",\n+ BPF_V3, BPF_CODE|BPF_IMM32, BPF_CLASS_STX|BPF_SIZE_W|BPF_MODE_ATOMIC|BPF_IMM32_AOR},\n+ {BPF_INSN_AAND32, \"aand32%W[ %dr %o16 ] , %sr\", \"* ( u32 * ) ( %dr %o16 ) &= %sr\",\n+ BPF_V3, BPF_CODE|BPF_IMM32, BPF_CLASS_STX|BPF_SIZE_W|BPF_MODE_ATOMIC|BPF_IMM32_AAND},\n+ {BPF_INSN_AXOR32, \"axor32%W[ %dr %o16 ] , %sr\", \"* ( u32 * ) ( %dr %o16 ) ^= %sr\",\n+ BPF_V3, BPF_CODE|BPF_IMM32, BPF_CLASS_STX|BPF_SIZE_W|BPF_MODE_ATOMIC|BPF_IMM32_AXOR},\n+\n+ /* Atomic instructions with fetching (32-bit.) */\n+ {BPF_INSN_AFADD32, \"afadd32 %W[ %dr %o16 ] , %sr\", \"???\",\n+ BPF_V3, BPF_CODE|BPF_IMM32, BPF_CLASS_STX|BPF_SIZE_W|BPF_MODE_ATOMIC|BPF_IMM32_AFADD},\n+ {BPF_INSN_AFOR32, \"afor32%W[ %dr %o16 ] , %sr\", \"???\",\n+ BPF_V3, BPF_CODE|BPF_IMM32, BPF_CLASS_STX|BPF_SIZE_W|BPF_MODE_ATOMIC|BPF_IMM32_AFOR},\n+ {BPF_INSN_AFAND32, \"afand32%W[ %dr %o16 ] , %sr\", \"???\",\n+ BPF_V3, BPF_CODE|BPF_IMM32, BPF_CLASS_STX|BPF_SIZE_W|BPF_MODE_ATOMIC|BPF_IMM32_AFAND},\n+ {BPF_INSN_AFXOR32, \"afxor32%W[ %dr %o16 ] , %sr\", \"???\",\n+ BPF_V3, BPF_CODE|BPF_IMM32, BPF_CLASS_STX|BPF_SIZE_W|BPF_MODE_ATOMIC|BPF_IMM32_AFXOR},\n+\n+ /* Old versions of aadd and aadd32. */\n+ {BPF_INSN_AADD, \"xadddw%W[ %dr %o16 ] , %sr\", \"* ( u64 * ) ( %dr %o16 ) += %sr\",\n+ BPF_V1, BPF_CODE|BPF_IMM32, BPF_CLASS_STX|BPF_SIZE_DW|BPF_MODE_ATOMIC|BPF_IMM32_AADD},\n+ {BPF_INSN_AADD32, \"xaddw%W[ %dr %o16 ] , %sr\", \"* ( u32 * ) ( %dr %o16 ) += %sr\",\n+ BPF_V1, BPF_CODE|BPF_IMM32, BPF_CLASS_STX|BPF_SIZE_W|BPF_MODE_ATOMIC|BPF_IMM32_AADD},\n+\n+ /* the brkpt instruction is used by the BPF simulator and it doesn't\n+ really belong to the BPF instruction set. */\n+ {BPF_INSN_BRKPT, \"brkpt\", \"brkpt\",\n+ BPF_XBPF, BPF_CODE, BPF_CLASS_ALU|BPF_SRC_X|BPF_CODE_NEG},\n+\n+ /* Sentinel. */\n+ {BPF_NOINSN, NULL, NULL, 0, 0UL, 0UL},\n };\n \n-#undef A\n-#undef OPERAND\n-#undef MNEM\n-#undef OP\n-\n-/* Formats for ALIAS macro-insns. */\n-\n-#define F(f) & bpf_cgen_ifld_table[BPF_##f]\n-#undef F\n-\n-/* Each non-simple macro entry points to an array of expansion possibilities. */\n-\n-#define A(a) (1 << CGEN_INSN_##a)\n-#define OPERAND(op) BPF_OPERAND_##op\n-#define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */\n-#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))\n-\n-/* The macro instruction table. */\n-\n-static const CGEN_IBASE bpf_cgen_macro_insn_table[] =\n+static bpf_insn_word\n+bpf_handle_endianness (bpf_insn_word word, enum bpf_endian endian)\n {\n-};\n+ if (endian == BPF_ENDIAN_LITTLE)\n+ {\n+ /* Endianness groups: 8 | 4 | 4 | 16 | 32 */\n+\n+ bpf_insn_word code = (word >> 56) & 0xff;\n+ bpf_insn_word dst = (word >> 48) & 0xf;\n+ bpf_insn_word src = (word >> 52) & 0xf;\n+ bpf_insn_word offset16 = (word >> 32) & 0xffff;\n+ bpf_insn_word imm32 = word & 0xffffffff;\n+\n+ return ((code << 56)\n+ | dst << 52\n+ | src << 48\n+ | (offset16 & 0xff) << 40\n+ | ((offset16 >> 8) & 0xff) << 32\n+ | (imm32 & 0xff) << 24\n+ | ((imm32 >> 8) & 0xff) << 16\n+ | ((imm32 >> 16) & 0xff) << 8\n+ | ((imm32 >> 24) & 0xff));\n+ }\n \n-/* The macro instruction opcode table. */\n+ return word;\n+}\n \n-static const CGEN_OPCODE bpf_cgen_macro_insn_opcode_table[] =\n+const struct bpf_opcode *\n+bpf_match_insn (bpf_insn_word word,\n+ enum bpf_endian endian,\n+ int version)\n {\n-};\n-\n-#undef A\n-#undef OPERAND\n-#undef MNEM\n-#undef OP\n+ unsigned int i = 0;\n \n-#ifndef CGEN_ASM_HASH_P\n-#define CGEN_ASM_HASH_P(insn) 1\n-#endif\n-\n-#ifndef CGEN_DIS_HASH_P\n-#define CGEN_DIS_HASH_P(insn) 1\n-#endif\n+ while (bpf_opcodes[i].normal != NULL)\n+ {\n+ bpf_insn_word cword\n+ = bpf_handle_endianness (word, endian);\n+\n+ /* Attempt match using mask and opcodes. */\n+ if (bpf_opcodes[i].version <= version\n+ && (cword & bpf_opcodes[i].mask) == bpf_opcodes[i].opcode)\n+ return &bpf_opcodes[i];\n+ i++;\n+ }\n \n-/* Return non-zero if INSN is to be added to the hash table.\n- Targets are free to override CGEN_{ASM,DIS}_HASH_P in the .opc file. */\n+ /* No maching instruction found. */\n+ return NULL;\n+}\n \n-static int\n-asm_hash_insn_p (const CGEN_INSN *insn ATTRIBUTE_UNUSED)\n+uint8_t\n+bpf_extract_src (bpf_insn_word word, enum bpf_endian endian)\n {\n- return CGEN_ASM_HASH_P (insn);\n+ word = bpf_handle_endianness (word, endian);\n+ return (uint8_t) ((word >> 48) & 0xf);\n }\n \n-static int\n-dis_hash_insn_p (const CGEN_INSN *insn)\n+uint8_t\n+bpf_extract_dst (bpf_insn_word word, enum bpf_endian endian)\n {\n- /* If building the hash table and the NO-DIS attribute is present,\n- ignore. */\n- if (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_NO_DIS))\n- return 0;\n- return CGEN_DIS_HASH_P (insn);\n+ word = bpf_handle_endianness (word, endian);\n+ return (uint8_t) ((word >> 52) & 0xf);\n }\n \n-#ifndef CGEN_ASM_HASH\n-#define CGEN_ASM_HASH_SIZE 127\n-#ifdef CGEN_MNEMONIC_OPERANDS\n-#define CGEN_ASM_HASH(mnem) (*(unsigned char *) (mnem) % CGEN_ASM_HASH_SIZE)\n-#else\n-#define CGEN_ASM_HASH(mnem) (*(unsigned char *) (mnem) % CGEN_ASM_HASH_SIZE) /*FIXME*/\n-#endif\n-#endif\n-\n-/* It doesn't make much sense to provide a default here,\n- but while this is under development we do.\n- BUFFER is a pointer to the bytes of the insn, target order.\n- VALUE is the first base_insn_bitsize bits as an int in host order. */\n-\n-#ifndef CGEN_DIS_HASH\n-#define CGEN_DIS_HASH_SIZE 256\n-#define CGEN_DIS_HASH(buf, value) (*(unsigned char *) (buf))\n-#endif\n-\n-/* The result is the hash value of the insn.\n- Targets are free to override CGEN_{ASM,DIS}_HASH in the .opc file. */\n-\n-static unsigned int\n-asm_hash_insn (const char *mnem)\n+int16_t\n+bpf_extract_offset16 (bpf_insn_word word, enum bpf_endian endian)\n {\n- return CGEN_ASM_HASH (mnem);\n+ word = bpf_handle_endianness (word, endian);\n+ return (int16_t) ((word >> 32) & 0xffff);\n }\n \n-/* BUF is a pointer to the bytes of the insn, target order.\n- VALUE is the first base_insn_bitsize bits as an int in host order. */\n-\n-static unsigned int\n-dis_hash_insn (const char *buf ATTRIBUTE_UNUSED,\n-\t\t CGEN_INSN_INT value ATTRIBUTE_UNUSED)\n+int32_t\n+bpf_extract_imm32 (bpf_insn_word word, enum bpf_endian endian)\n {\n- return CGEN_DIS_HASH (buf, value);\n+ word = bpf_handle_endianness (word, endian);\n+ return (int32_t) (word & 0xffffffff);\n }\n \n-/* Set the recorded length of the insn in the CGEN_FIELDS struct. */\n-\n-static void\n-set_fields_bitsize (CGEN_FIELDS *fields, int size)\n+int64_t\n+bpf_extract_imm64 (bpf_insn_word word1, bpf_insn_word word2,\n+ enum bpf_endian endian)\n {\n- CGEN_FIELDS_BITSIZE (fields) = size;\n+ word1 = bpf_handle_endianness (word1, endian);\n+ word2 = bpf_handle_endianness (word2, endian);\n+ return (int64_t) (((word2 & 0xffffffff) << 32) | (word1 & 0xffffffff));\n }\n \n-/* Function to call before using the operand instance table.\n- This plugs the opcode entries and macro instructions into the cpu table. */\n-\n-void\n-bpf_cgen_init_opcode_table (CGEN_CPU_DESC cd)\n+const struct bpf_opcode *\n+bpf_get_opcode (unsigned int index)\n {\n- int i;\n- int num_macros = (sizeof (bpf_cgen_macro_insn_table) /\n-\t\t sizeof (bpf_cgen_macro_insn_table[0]));\n- const CGEN_IBASE *ib = & bpf_cgen_macro_insn_table[0];\n- const CGEN_OPCODE *oc = & bpf_cgen_macro_insn_opcode_table[0];\n- CGEN_INSN *insns = xmalloc (num_macros * sizeof (CGEN_INSN));\n-\n- /* This test has been added to avoid a warning generated\n- if memset is called with a third argument of value zero. */\n- if (num_macros >= 1)\n- memset (insns, 0, num_macros * sizeof (CGEN_INSN));\n- for (i = 0; i < num_macros; ++i)\n- {\n- insns[i].base = &ib[i];\n- insns[i].opcode = &oc[i];\n- bpf_cgen_build_insn_regex (& insns[i]);\n- }\n- cd->macro_insn_table.init_entries = insns;\n- cd->macro_insn_table.entry_size = sizeof (CGEN_IBASE);\n- cd->macro_insn_table.num_init_entries = num_macros;\n-\n- oc = & bpf_cgen_insn_opcode_table[0];\n- insns = (CGEN_INSN *) cd->insn_table.init_entries;\n- for (i = 0; i < MAX_INSNS; ++i)\n- {\n- insns[i].opcode = &oc[i];\n- bpf_cgen_build_insn_regex (& insns[i]);\n- }\n-\n- cd->sizeof_fields = sizeof (CGEN_FIELDS);\n- cd->set_fields_bitsize = set_fields_bitsize;\n-\n- cd->asm_hash_p = asm_hash_insn_p;\n- cd->asm_hash = asm_hash_insn;\n- cd->asm_hash_size = CGEN_ASM_HASH_SIZE;\n+ unsigned int i = 0;\n \n- cd->dis_hash_p = dis_hash_insn_p;\n- cd->dis_hash = dis_hash_insn;\n- cd->dis_hash_size = CGEN_DIS_HASH_SIZE;\n+ while (bpf_opcodes[i].normal != NULL && i < index)\n+ ++i;\n+ return (bpf_opcodes[i].normal == NULL\n+ ? NULL\n+ : &bpf_opcodes[i]);\n }\ndiff --git a/opcodes/configure b/opcodes/configure\nindex 84f8c2057fd..a9648baccb9 100755\n--- a/opcodes/configure\n+++ b/opcodes/configure\n@@ -12597,7 +12597,7 @@ if test x${all_targets} = xfalse ; then\n \tbfd_xtensa_arch)\tta=\"$ta xtensa-dis.lo\" ;;\n \tbfd_z80_arch)\t\tta=\"$ta z80-dis.lo\" ;;\n \tbfd_z8k_arch)\t\tta=\"$ta z8k-dis.lo\" ;;\n-\tbfd_bpf_arch)\t\tta=\"$ta bpf-asm.lo bpf-desc.lo bpf-dis.lo bpf-ibld.lo bpf-opc.lo\" using_cgen=yes ;;\n+\tbfd_bpf_arch)\t\tta=\"$ta bpf-dis.lo bpf-opc.lo\" ;;\n \tbfd_loongarch_arch)\tta=\"$ta loongarch-dis.lo loongarch-opc.lo loongarch-coder.lo\" ;;\n \n \t\"\")\t\t\t;;\ndiff --git a/opcodes/configure.ac b/opcodes/configure.ac\nindex 1beb72e87e0..7f508089c6f 100644\n--- a/opcodes/configure.ac\n+++ b/opcodes/configure.ac\n@@ -345,7 +345,7 @@ if test x${all_targets} = xfalse ; then\n \tbfd_xtensa_arch)\tta=\"$ta xtensa-dis.lo\" ;;\n \tbfd_z80_arch)\t\tta=\"$ta z80-dis.lo\" ;;\n \tbfd_z8k_arch)\t\tta=\"$ta z8k-dis.lo\" ;;\n-\tbfd_bpf_arch)\t\tta=\"$ta bpf-asm.lo bpf-desc.lo bpf-dis.lo bpf-ibld.lo bpf-opc.lo\" using_cgen=yes ;;\n+\tbfd_bpf_arch)\t\tta=\"$ta bpf-dis.lo bpf-opc.lo\" ;;\n \tbfd_loongarch_arch)\tta=\"$ta loongarch-dis.lo loongarch-opc.lo loongarch-coder.lo\" ;;\n \n \t\"\")\t\t\t;;\ndiff --git a/opcodes/disassemble.c b/opcodes/disassemble.c\nindex 7a4a641c2b9..a5cb396badb 100644\n--- a/opcodes/disassemble.c\n+++ b/opcodes/disassemble.c\n@@ -108,23 +108,6 @@\n #include \"m32c-desc.h\"\n #endif\n \n-#ifdef ARCH_bpf\n-/* XXX this should be including bpf-desc.h instead of this hackery,\n- but at the moment it is not possible to include several CGEN\n- generated *-desc.h files simultaneously. To be fixed in\n- CGEN... */\n-\n-# ifdef ARCH_m32c\n-enum epbf_isa_attr\n-{\n- ISA_EBPFLE, ISA_EBPFBE, ISA_XBPFLE, ISA_XBPFBE, ISA_EBPFMAX\n-};\n-# else\n-# include \"bpf-desc.h\"\n-# define ISA_EBPFMAX ISA_MAX\n-# endif\n-#endif /* ARCH_bpf */\n-\n disassembler_ftype\n disassembler (enum bfd_architecture a,\n \t bool big ATTRIBUTE_UNUSED,\n@@ -594,7 +577,9 @@ disassembler_usage (FILE *stream ATTRIBUTE_UNUSED)\n #ifdef ARCH_loongarch\n print_loongarch_disassembler_options (stream);\n #endif\n-\n+#ifdef ARCH_bpf\n+ print_bpf_disassembler_options (stream);\n+#endif\n return;\n }\n \n@@ -695,6 +680,9 @@ disassemble_init_fo 100 325k 100 324k 100 150 3913k 1807 --:--:-- --:--:-- --:--:-- 3915k r_target (struct disassemble_info * info)\n #endif\n #ifdef ARCH_bpf\n case bfd_arch_bpf:\n+ /* XXX option for dialect */\n+ info->created_styled_output = true;\n+#if 0\n info->endian_code = BFD_ENDIAN_LITTLE;\n if (!info->private_data)\n \t{\n@@ -712,6 +700,7 @@ disassemble_init_for_target (struct disassemble_info * info)\n \t\tcgen_bitset_set (info->private_data, ISA_XBPFLE);\n \t }\n \t}\n+#endif\n break;\n #endif\n #ifdef ARCH_pru\n@@ -768,13 +757,10 @@ disassemble_free_target (struct disassemble_info *info)\n default:\n return;\n \n-#ifdef ARCH_bpf\n- case bfd_arch_bpf:\n-#endif\n #ifdef ARCH_m32c\n case bfd_arch_m32c:\n #endif\n-#if defined ARCH_bpf || defined ARCH_m32c\n+#if defined ARCH_m32c\n if (info->private_data)\n \t{\n \t CGEN_BITSET *mask = info->private_data;\n","prefixes":["COMMITTED"]}+ exit 1 Build step 'Execute shell' marked build as failure Finished: FAILURE