Started by user snail Running as SYSTEM [EnvInject] - Loading node environment variables. Building remotely on docker-jenkins-agent in workspace /home/jenkins/agent/workspace/binutils-gdb [WS-CLEANUP] Deleting project workspace... [WS-CLEANUP] Deferred wipeout is used... [WS-CLEANUP] Done The recommended git tool is: NONE using credential 0adb5fc7-caa2-429d-97d2-c7fa2fa1d884 Cloning the remote Git repository Using shallow clone with depth 1 Avoid fetching tags Cloning repository git@github.com:wangliu-iscas/binutils-gdb.git/ > git init /home/jenkins/agent/workspace/binutils-gdb # timeout=10 Fetching upstream changes from git@github.com:wangliu-iscas/binutils-gdb.git/ > git --version # timeout=10 > git --version # 'git version 2.37.2' using GIT_SSH to set credentials patchwork github wangliu-iscas git ssh key Verifying host key using known hosts file, will automatically accept unseen keys > git fetch --no-tags --force --progress --depth=1 -- git@github.com:wangliu-iscas/binutils-gdb.git/ +refs/heads/*:refs/remotes/origin/* # timeout=10 > git config remote.origin.url git@github.com:wangliu-iscas/binutils-gdb.git/ # timeout=10 > git config --add remote.origin.fetch +refs/heads/*:refs/remotes/origin/* # timeout=10 Avoid second fetch > git rev-parse refs/remotes/origin/master^{commit} # timeout=10 Checking out Revision 05bb930a054c80b6f8aecd93dafbcb464a403bc5 (refs/remotes/origin/master) > git config core.sparsecheckout # timeout=10 > git checkout -f 05bb930a054c80b6f8aecd93dafbcb464a403bc5 # timeout=10 Commit message: "x86: consolidate VPCLMUL tests" > git rev-list --no-walk 05bb930a054c80b6f8aecd93dafbcb464a403bc5 # timeout=10 [EnvInject] - Mask passwords that will be passed as build parameters. [EnvInject] - Executing scripts and injecting environment variables after the SCM step. [EnvInject] - Injecting as environment variables the properties content GITHUB_REPO=https://github.com/wangliu-iscas/ PATCHWORK_URL=https://patchwork.plctlab.org [EnvInject] - Variables injected successfully. [binutils-gdb] $ /usr/bin/env bash /tmp/jenkins9913742993618280903.sh + git config pw.server https://patchwork.plctlab.org/api/1.2/ + git config pw.project binutils-gdb + git config pw.token [*******] ++ date +%Y-%m + now_date=2022-10 + echo 2022-10 2022-10 ++ curl -s -H 'Authorization: Token [*******]' 'https://patchwork.plctlab.org/api/1.2/bundles/?project=binutils-gdb&per_page=999' + bundle_response='[{"id":6,"url":"https://patchwork.plctlab.org/api/1.2/bundles/6/","web_url":"https://patchwork.plctlab.org/bundle/patchwork-bot/binutils-gdb_2022-10/","project":{"id":2,"url":"https://patchwork.plctlab.org/api/1.2/projects/2/","name":"binutils-gdb","link_name":"binutils-gdb","list_id":"binutils.sourceware.org","list_email":"binutils@sourceware.org","web_url":"https://sourceware.org/mailman/listinfo/binutils","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"name":"binutils-gdb_2022-10","owner":{"id":3,"url":"https://patchwork.plctlab.org/api/1.2/users/3/","username":"patchwork-bot","first_name":"","last_name":"","email":"ouuuleilei@gmail.com"},"patches":[{"id":1592,"url":"https://patchwork.plctlab.org/api/1.2/patches/1592/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/385d01fd-7e57-1f3f-1bae-30aa0c313d63@suse.com/","msgid":"<385d01fd-7e57-1f3f-1bae-30aa0c313d63@suse.com>","list_archive_url":null,"date":"2022-09-30T11:59:45","name":"[3/4] RISC-V/gas: don'\''t open-code insn_length()","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/385d01fd-7e57-1f3f-1bae-30aa0c313d63@suse.com/mbox/"},{"id":1594,"url":"https://patchwork.plctlab.org/api/1.2/patches/1594/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f5757acf-7b90-a0e3-5eea-3b97cc226930@suse.com/","msgid":"","list_archive_url":null,"date":"2022-09-30T12:00:12","name":"[4/4] RISC-V/gas: allow generating up to 176-bit instructions with .insn","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f5757acf-7b90-a0e3-5eea-3b97cc226930@suse.com/mbox/"},{"id":1596,"url":"https://patchwork.plctlab.org/api/1.2/patches/1596/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930140503.38233-1-chigot@adacore.com/","msgid":"<20220930140503.38233-1-chigot@adacore.com>","list_archive_url":null,"date":"2022-09-30T14:05:03","name":"ld/testsuite: consistently add board_ldflags when linking with GCC","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930140503.38233-1-chigot@adacore.com/mbox/"},{"id":1619,"url":"https://patchwork.plctlab.org/api/1.2/patches/1619/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221001014451.532772-1-maskray@google.com/","msgid":"<20221001014451.532772-1-maskray@google.com>","list_archive_url":null,"date":"2022-10-01T01:44:51","name":"gold, dwp: support zstd compressed input debug sections [PR 29641]","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221001014451.532772-1-maskray@google.com/mbox/"},{"id":1620,"url":"https://patchwork.plctlab.org/api/1.2/patches/1620/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221001023846.590825-1-maskray@google.com/","msgid":"<20221001023846.590825-1-maskray@google.com>","list_archive_url":null,"date":"2022-10-01T02:38:46","name":"gold: add --compress-debug-sections=zstd [PR 29641]","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221001023846.590825-1-maskray@google.com/mbox/"},{"id":1623,"url":"https://patchwork.plctlab.org/api/1.2/patches/1623/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b4477c7f666bdeb7f8e998633c7b0cb62310b9ef.1664599545.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-01T04:45:52","name":"[RFC,1/1] RISC-V: Implement common register pair framework","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b4477c7f666bdeb7f8e998633c7b0cb62310b9ef.1664599545.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1625,"url":"https://patchwork.plctlab.org/api/1.2/patches/1625/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/53a265a1f14d17a6f7b106082f610994c5d546e0.1664602025.git.research_trasio@irq.a4lg.com/","msgid":"<53a265a1f14d17a6f7b106082f610994c5d546e0.1664602025.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-01T05:27:31","name":"[RFC,1/1] RISC-V: Implement extension variants","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/53a265a1f14d17a6f7b106082f610994c5d546e0.1664602025.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1626,"url":"https://patchwork.plctlab.org/api/1.2/patches/1626/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8db04962aba9c780f133840a8934353a58f223fe.1664602716.git.research_trasio@irq.a4lg.com/","msgid":"<8db04962aba9c780f133840a8934353a58f223fe.1664602716.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-01T05:39:26","name":"[1/1] RISC-V: Move supervisor instructions after all unprivileged ones","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8db04962aba9c780f133840a8934353a58f223fe.1664602716.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1627,"url":"https://patchwork.plctlab.org/api/1.2/patches/1627/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221001062057.681440-1-maskray@google.com/","msgid":"<20221001062057.681440-1-maskray@google.com>","list_archive_url":null,"date":"2022-10-01T06:20:57","name":"readelf: support zstd compressed debug sections [PR 29640]","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221001062057.681440-1-maskray@google.com/mbox/"},{"id":1631,"url":"https://patchwork.plctlab.org/api/1.2/patches/1631/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/619f112539c0bdecd58e25664f1250a3479a37f5.1664707612.git.aburgess@redhat.com/","msgid":"<619f112539c0bdecd58e25664f1250a3479a37f5.1664707612.git.aburgess@redhat.com>","list_archive_url":null,"date":"2022-10-02T10:47:52","name":"[PATCHv2,2/2] opcodes/arm: add disassembler styling for arm","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/619f112539c0bdecd58e25664f1250a3479a37f5.1664707612.git.aburgess@redhat.com/mbox/"},{"id":1635,"url":"https://patchwork.plctlab.org/api/1.2/patches/1635/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221002185433.gl7dvytfh5wthifx@lug-owl.de/","msgid":"<20221002185433.gl7dvytfh5wthifx@lug-owl.de>","list_archive_url":null,"date":"2022-10-02T18:54:33","name":"diagnostics.h: GCC 13 got -Wself-move, breaks GDB build","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221002185433.gl7dvytfh5wthifx@lug-owl.de/mbox/"},{"id":1637,"url":"https://patchwork.plctlab.org/api/1.2/patches/1637/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003014313.28766-1-mark@harmstone.com/","msgid":"<20221003014313.28766-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-03T01:43:12","name":"[1/2] ld: Add --pdb option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003014313.28766-1-mark@harmstone.com/mbox/"},{"id":1638,"url":"https://patchwork.plctlab.org/api/1.2/patches/1638/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003014313.28766-2-mark@harmstone.com/","msgid":"<20221003014313.28766-2-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-03T01:43:13","name":"[2/2] ld: Add minimal pdb generation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003014313.28766-2-mark@harmstone.com/mbox/"},{"id":1640,"url":"https://patchwork.plctlab.org/api/1.2/patches/1640/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/597ed978-d121-220c-b56b-2ffb94bd091c@suse.cz/","msgid":"<597ed978-d121-220c-b56b-2ffb94bd091c@suse.cz>","list_archive_url":null,"date":"2022-10-03T07:50:38","name":"[1/2] refactor usage of compressed_debug_section_type","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/597ed978-d121-220c-b56b-2ffb94bd091c@suse.cz/mbox/"},{"id":1641,"url":"https://patchwork.plctlab.org/api/1.2/patches/1641/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b8acdd83-f33a-74b8-e21a-23719a0b1a60@suse.cz/","msgid":"","list_archive_url":null,"date":"2022-10-03T07:50:44","name":"[2/2] add --enable-default-compressed-debug-sections-algorithm configure option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b8acdd83-f33a-74b8-e21a-23719a0b1a60@suse.cz/mbox/"},{"id":1642,"url":"https://patchwork.plctlab.org/api/1.2/patches/1642/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003101328.1790113-1-aburgess@redhat.com/","msgid":"<20221003101328.1790113-1-aburgess@redhat.com>","list_archive_url":null,"date":"2022-10-03T10:13:28","name":"opcodes/riscv: style csr names as registers","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003101328.1790113-1-aburgess@redhat.com/mbox/"},{"id":1643,"url":"https://patchwork.plctlab.org/api/1.2/patches/1643/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7ba14fc4472ce97d4f7a4433cad8a571e89f82f4.1664793840.git.research_trasio@irq.a4lg.com/","msgid":"<7ba14fc4472ce97d4f7a4433cad8a571e89f82f4.1664793840.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-03T10:43:59","name":"[v3,1/6] RISC-V: Fix immediates to have \"immediate\" style","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7ba14fc4472ce97d4f7a4433cad8a571e89f82f4.1664793840.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1644,"url":"https://patchwork.plctlab.org/api/1.2/patches/1644/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a498bec37c1fd1dcda57cbf95e5f8cfba09b31d3.1664793840.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-03T10:44:00","name":"[v3,2/6] RISC-V: Fix printf argument types corresponding %x","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a498bec37c1fd1dcda57cbf95e5f8cfba09b31d3.1664793840.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1647,"url":"https://patchwork.plctlab.org/api/1.2/patches/1647/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0002ea716713ace4998a33dde0b81f4f890d10bf.1664793840.git.research_trasio@irq.a4lg.com/","msgid":"<0002ea716713ace4998a33dde0b81f4f890d10bf.1664793840.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-03T10:44:01","name":"[v3,3/6] RISC-V: Optimize riscv_disassemble_data printf","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0002ea716713ace4998a33dde0b81f4f890d10bf.1664793840.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1646,"url":"https://patchwork.plctlab.org/api/1.2/patches/1646/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c65fc3e9aa58965d6768a28c9fd7467fea9897a5.1664793840.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-03T10:44:02","name":"[v3,4/6] RISC-V: Print comma and tabs as the \"text\" style","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c65fc3e9aa58965d6768a28c9fd7467fea9897a5.1664793840.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1648,"url":"https://patchwork.plctlab.org/api/1.2/patches/1648/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5abe1d8a7694417b990e11d8f6cd6789573872e5.1664793840.git.research_trasio@irq.a4lg.com/","msgid":"<5abe1d8a7694417b990e11d8f6cd6789573872e5.1664793840.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-03T10:44:03","name":"[v3,5/6] RISC-V: Fix T-Head immediate types on printing","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5abe1d8a7694417b990e11d8f6cd6789573872e5.1664793840.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1649,"url":"https://patchwork.plctlab.org/api/1.2/patches/1649/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0b68af932117258c908db62cf87c3a15d3cdec41.1664793840.git.research_trasio@irq.a4lg.com/","msgid":"<0b68af932117258c908db62cf87c3a15d3cdec41.1664793840.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-03T10:44:04","name":"[v3,6/6] RISC-V: Print XTheadMemPair literal as \"immediate\"","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0b68af932117258c908db62cf87c3a15d3cdec41.1664793840.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1656,"url":"https://patchwork.plctlab.org/api/1.2/patches/1656/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/87lepxcd6x.fsf@redhat.com/","msgid":"<87lepxcd6x.fsf@redhat.com>","list_archive_url":null,"date":"2022-10-03T12:19:02","name":"Commit: readelf: Do not load section data from offset 0","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/87lepxcd6x.fsf@redhat.com/mbox/"},{"id":1659,"url":"https://patchwork.plctlab.org/api/1.2/patches/1659/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e0d369d419da9c0441f415da7f54352aead8f655.1664707612.git.aburgess@redhat.com/","msgid":"","list_archive_url":null,"date":"2022-10-03T16:37:36","name":"[PATCHv2,1/2] opcodes/arm: use '\''@'\'' consistently for the comment character","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e0d369d419da9c0441f415da7f54352aead8f655.1664707612.git.aburgess@redhat.com/mbox/"},{"id":1660,"url":"https://patchwork.plctlab.org/api/1.2/patches/1660/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003165848.11142-1-palmer@rivosinc.com/","msgid":"<20221003165848.11142-1-palmer@rivosinc.com>","list_archive_url":null,"date":"2022-10-03T16:58:48","name":"gas: NEWS: Mention the T-Head extensions that were recently added","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003165848.11142-1-palmer@rivosinc.com/mbox/"},{"id":1671,"url":"https://patchwork.plctlab.org/api/1.2/patches/1671/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/YzvrMEdkXjIn5Lfz@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-04T08:13:36","name":"Support objcopy changing compression to or from zstd","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/YzvrMEdkXjIn5Lfz@squeak.grove.modra.org/mbox/"},{"id":1673,"url":"https://patchwork.plctlab.org/api/1.2/patches/1673/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0bc857d306bb7c8130e5328dbe6b9ed2fed3ef87.1664873933.git.research_trasio@irq.a4lg.com/","msgid":"<0bc857d306bb7c8130e5328dbe6b9ed2fed3ef87.1664873933.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-04T08:59:07","name":"[1/2] RISC-V: Fix buffer overflow on print_insn_riscv","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0bc857d306bb7c8130e5328dbe6b9ed2fed3ef87.1664873933.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1672,"url":"https://patchwork.plctlab.org/api/1.2/patches/1672/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/89612fe01d902007bf84a7dfb0df5f85d5c166e4.1664873933.git.research_trasio@irq.a4lg.com/","msgid":"<89612fe01d902007bf84a7dfb0df5f85d5c166e4.1664873933.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-04T08:59:08","name":"[2/2] gdb/riscv: Fix buffer overflow on riscv_insn::fetch_instruction","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/89612fe01d902007bf84a7dfb0df5f85d5c166e4.1664873933.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1676,"url":"https://patchwork.plctlab.org/api/1.2/patches/1676/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fc849c94f4adcac1c4ccc5508c7a145a2f13b2a9.1664876744.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-04T09:45:49","name":"[v2,1/2] RISC-V: Fix buffer overflow on print_insn_riscv","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fc849c94f4adcac1c4ccc5508c7a145a2f13b2a9.1664876744.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1677,"url":"https://patchwork.plctlab.org/api/1.2/patches/1677/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4eb6e59ae2e790dbbf2bc92477edd281648d8814.1664876744.git.research_trasio@irq.a4lg.com/","msgid":"<4eb6e59ae2e790dbbf2bc92477edd281648d8814.1664876744.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-04T09:45:50","name":"[v2,2/2] gdb/riscv: Partial support for instructions up to 176-bits","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4eb6e59ae2e790dbbf2bc92477edd281648d8814.1664876744.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1678,"url":"https://patchwork.plctlab.org/api/1.2/patches/1678/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ebf16f9e1f45115d0793952ccb4a94d4233303f9.1664882725.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-04T11:25:56","name":"[v3,1/2] RISC-V: Fix buffer overflow on print_insn_riscv","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ebf16f9e1f45115d0793952ccb4a94d4233303f9.1664882725.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1679,"url":"https://patchwork.plctlab.org/api/1.2/patches/1679/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/83464b09b8649525259c69c853dfa2c9575a204b.1664882725.git.research_trasio@irq.a4lg.com/","msgid":"<83464b09b8649525259c69c853dfa2c9575a204b.1664882725.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-04T11:25:57","name":"[v3,2/2] gdb/riscv: Partial support for instructions up to 176-bit","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/83464b09b8649525259c69c853dfa2c9575a204b.1664882725.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1681,"url":"https://patchwork.plctlab.org/api/1.2/patches/1681/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ffa9c1d7-e8c2-a62b-ef3e-b565c0ffbe5b@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-04T13:56:27","name":"RISC-V: Zicbo{m,p,z} adjustments to riscv_multi_subset_supports_ext()","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ffa9c1d7-e8c2-a62b-ef3e-b565c0ffbe5b@suse.com/mbox/"},{"id":1690,"url":"https://patchwork.plctlab.org/api/1.2/patches/1690/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221004161720.1963953-1-vladimir.mezentsev@oracle.com/","msgid":"<20221004161720.1963953-1-vladimir.mezentsev@oracle.com>","list_archive_url":null,"date":"2022-10-04T16:17:20","name":"gprofng: fix build with --enable-pgo-build=lto","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221004161720.1963953-1-vladimir.mezentsev@oracle.com/mbox/"},{"id":1691,"url":"https://patchwork.plctlab.org/api/1.2/patches/1691/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c0211bc9c57be6c79c6d878ce147f63b657f461d.camel@espressif.com/","msgid":"","list_archive_url":null,"date":"2022-10-04T16:22:05","name":"bfd: xtensa: fix __stop_SECTION literal drop,","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c0211bc9c57be6c79c6d878ce147f63b657f461d.camel@espressif.com/mbox/"},{"id":1702,"url":"https://patchwork.plctlab.org/api/1.2/patches/1702/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5f482299-6c60-b2b3-9abe-f4a55a5a26c5@univ-grenoble-alpes.fr/","msgid":"<5f482299-6c60-b2b3-9abe-f4a55a5a26c5@univ-grenoble-alpes.fr>","list_archive_url":null,"date":"2022-10-04T20:03:20","name":"[RFC] bfd: use bfd_vma for the 64-bit version of put[lb] and get[lb]","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5f482299-6c60-b2b3-9abe-f4a55a5a26c5@univ-grenoble-alpes.fr/mbox/"},{"id":1711,"url":"https://patchwork.plctlab.org/api/1.2/patches/1711/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Yz0Gsxdxe0TePbJT@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-05T04:23:15","name":"PR29647, objdump -S looping","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Yz0Gsxdxe0TePbJT@squeak.grove.modra.org/mbox/"},{"id":1712,"url":"https://patchwork.plctlab.org/api/1.2/patches/1712/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/02d747d2-f57b-0fb5-b893-842b6cc41f2f@suse.com/","msgid":"<02d747d2-f57b-0fb5-b893-842b6cc41f2f@suse.com>","list_archive_url":null,"date":"2022-10-05T07:20:47","name":"[v3,1/7] x86: constify parse_insn()'\''s input","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/02d747d2-f57b-0fb5-b893-842b6cc41f2f@suse.com/mbox/"},{"id":1713,"url":"https://patchwork.plctlab.org/api/1.2/patches/1713/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/925cb740-4e1b-abc4-8526-aaab6faae5e1@suse.com/","msgid":"<925cb740-4e1b-abc4-8526-aaab6faae5e1@suse.com>","list_archive_url":null,"date":"2022-10-05T07:22:19","name":"[v3,2/7] x86: introduce Pass2 insn attribute","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/925cb740-4e1b-abc4-8526-aaab6faae5e1@suse.com/mbox/"},{"id":1714,"url":"https://patchwork.plctlab.org/api/1.2/patches/1714/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e16d3e78-39ca-f715-508f-a4104b8ab9a9@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-05T07:23:51","name":"[v3,3/7] x86: re-work insn/suffix recognition","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e16d3e78-39ca-f715-508f-a4104b8ab9a9@suse.com/mbox/"},{"id":1715,"url":"https://patchwork.plctlab.org/api/1.2/patches/1715/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e4e4b80b-794c-7485-1997-685adab8fb27@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-05T07:24:20","name":"[v3,4/7] x86-64: further re-work insn/suffix recognition to also cover MOVSL","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e4e4b80b-794c-7485-1997-685adab8fb27@suse.com/mbox/"},{"id":1716,"url":"https://patchwork.plctlab.org/api/1.2/patches/1716/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/540678fc-8bff-ec68-c97c-478d2631998c@suse.com/","msgid":"<540678fc-8bff-ec68-c97c-478d2631998c@suse.com>","list_archive_url":null,"date":"2022-10-05T07:24:55","name":"[v3,5/7] ix86: don'\''t recognize/derive Q suffix in the common case","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/540678fc-8bff-ec68-c97c-478d2631998c@suse.com/mbox/"},{"id":1718,"url":"https://patchwork.plctlab.org/api/1.2/patches/1718/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e4692495-7d3d-074d-14f9-364d4a9a998c@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-05T07:25:25","name":"[v3,6/7] x86-64: allow HLE store of accumulator to absolute 32-bit address","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e4692495-7d3d-074d-14f9-364d4a9a998c@suse.com/mbox/"},{"id":1717,"url":"https://patchwork.plctlab.org/api/1.2/patches/1717/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e8014ebd-d16b-17a7-9f34-3700fc164136@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-05T07:25:57","name":"[v3,7/7] x86: move bad-use-of-TLS-reloc check","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e8014ebd-d16b-17a7-9f34-3700fc164136@suse.com/mbox/"},{"id":1719,"url":"https://patchwork.plctlab.org/api/1.2/patches/1719/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1266f001-4511-2662-dba9-14b4d0317c57@suse.com/","msgid":"<1266f001-4511-2662-dba9-14b4d0317c57@suse.com>","list_archive_url":null,"date":"2022-10-05T07:40:50","name":"x86: drop \"regmask\" static variable","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1266f001-4511-2662-dba9-14b4d0317c57@suse.com/mbox/"},{"id":1751,"url":"https://patchwork.plctlab.org/api/1.2/patches/1751/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/af45c5d57c221e43101c2aa38b14f4b4ac12d011.1665031170.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-06T04:40:15","name":"[v2,1/2] RISC-V: Fallback for instructions longer than 64b","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/af45c5d57c221e43101c2aa38b14f4b4ac12d011.1665031170.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1752,"url":"https://patchwork.plctlab.org/api/1.2/patches/1752/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c6e55781245dd3e8e9b8debd6130fc5449dfbd55.1665031170.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-06T04:40:16","name":"[v2,2/2] RISC-V: Improve \"bits undefined\" diagnostics","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c6e55781245dd3e8e9b8debd6130fc5449dfbd55.1665031170.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1776,"url":"https://patchwork.plctlab.org/api/1.2/patches/1776/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d52952119e15357c0e823f8a2398999359588b4d.1665050099.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-06T09:56:30","name":"[v3,1/2] RISC-V: Fallback for instructions longer than 64b","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d52952119e15357c0e823f8a2398999359588b4d.1665050099.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1777,"url":"https://patchwork.plctlab.org/api/1.2/patches/1777/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d907b1997f60ff7823c4a23e281ec9d8ddcbf3f1.1665050099.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-06T09:56:31","name":"[v3,2/2] RISC-V: Improve \"bits undefined\" diagnostics","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d907b1997f60ff7823c4a23e281ec9d8ddcbf3f1.1665050099.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1781,"url":"https://patchwork.plctlab.org/api/1.2/patches/1781/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221006114628.304185-1-chigot@adacore.com/","msgid":"<20221006114628.304185-1-chigot@adacore.com>","list_archive_url":null,"date":"2022-10-06T11:46:28","name":"RISC-V: fix linker message when relaxation deletes bytes","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221006114628.304185-1-chigot@adacore.com/mbox/"},{"id":1801,"url":"https://patchwork.plctlab.org/api/1.2/patches/1801/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Yz+Yhyg7UewC9/kp@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-07T03:09:59","name":"PR29653, objcopy/strip: fuzzed small input file induces large output file","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Yz+Yhyg7UewC9/kp@squeak.grove.modra.org/mbox/"},{"id":1803,"url":"https://patchwork.plctlab.org/api/1.2/patches/1803/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/PH1P110MB16505D9D39EC5B1DE22FE3D5EC5F9@PH1P110MB1650.NAMP110.PROD.OUTLOOK.COM/","msgid":"","list_archive_url":null,"date":"2022-10-07T04:10:07","name":"@CPP_FOR_BUILD@ problem since binutils-2.38","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/PH1P110MB16505D9D39EC5B1DE22FE3D5EC5F9@PH1P110MB1650.NAMP110.PROD.OUTLOOK.COM/mbox/"},{"id":1827,"url":"https://patchwork.plctlab.org/api/1.2/patches/1827/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8e13bce108ac10a0c1dd911e23ec572926f7ae44.1665203374.git.research_trasio@irq.a4lg.com/","msgid":"<8e13bce108ac10a0c1dd911e23ec572926f7ae44.1665203374.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-08T04:29:53","name":"[v2,1/1] RISC-V: Test DWARF register numbers for \"fp\"","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8e13bce108ac10a0c1dd911e23ec572926f7ae44.1665203374.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1828,"url":"https://patchwork.plctlab.org/api/1.2/patches/1828/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0883001b3572e54d3fba264429c7ade2adb66610.1665203441.git.research_trasio@irq.a4lg.com/","msgid":"<0883001b3572e54d3fba264429c7ade2adb66610.1665203441.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-08T04:31:15","name":"[1/1] RISC-V: Move standard hints before all instructions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0883001b3572e54d3fba264429c7ade2adb66610.1665203441.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1829,"url":"https://patchwork.plctlab.org/api/1.2/patches/1829/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/58e16a241d7376fcae2515c6bd5a2b41d275eeba.1665203531.git.research_trasio@irq.a4lg.com/","msgid":"<58e16a241d7376fcae2515c6bd5a2b41d275eeba.1665203531.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-08T04:32:18","name":"[RFC,1/1] RISC-V: Imply '\''Zicsr'\'' from privileged extensions with CSRs","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/58e16a241d7376fcae2515c6bd5a2b41d275eeba.1665203531.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1830,"url":"https://patchwork.plctlab.org/api/1.2/patches/1830/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/cb5076fc96e8f2097779a3abcde843dcdd660031.1665203660.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-08T04:34:23","name":"[1/5] opcodes/riscv-dis.c: Tidying with comments/clarity","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/cb5076fc96e8f2097779a3abcde843dcdd660031.1665203660.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1832,"url":"https://patchwork.plctlab.org/api/1.2/patches/1832/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1f1aa0838bf9c4f10a45fcfe3c682f7efc79d9ae.1665203660.git.research_trasio@irq.a4lg.com/","msgid":"<1f1aa0838bf9c4f10a45fcfe3c682f7efc79d9ae.1665203660.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-08T04:34:24","name":"[2/5] opcodes/riscv-dis.c: Tidying with spacing","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1f1aa0838bf9c4f10a45fcfe3c682f7efc79d9ae.1665203660.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1831,"url":"https://patchwork.plctlab.org/api/1.2/patches/1831/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/740bc5e2d2618d236519b39fedd1a1d7ae4e05da.1665203660.git.research_trasio@irq.a4lg.com/","msgid":"<740bc5e2d2618d236519b39fedd1a1d7ae4e05da.1665203660.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-08T04:34:25","name":"[3/5] opcodes/riscv-dis.c: Use bool type whenever possible","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/740bc5e2d2618d236519b39fedd1a1d7ae4e05da.1665203660.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1833,"url":"https://patchwork.plctlab.org/api/1.2/patches/1833/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6e3a9c235e317f441b4383b3daa68f2051bdc149.1665203660.git.research_trasio@irq.a4lg.com/","msgid":"<6e3a9c235e317f441b4383b3daa68f2051bdc149.1665203660.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-08T04:34:26","name":"[4/5] opcodes/riscv-dis.c: Make XLEN variable static","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6e3a9c235e317f441b4383b3daa68f2051bdc149.1665203660.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1834,"url":"https://patchwork.plctlab.org/api/1.2/patches/1834/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ad929233a62d887495122721340b2f9c80392963.1665203660.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-08T04:34:27","name":"[5/5] opcodes/riscv-dis.c: Remove last_map_state","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ad929233a62d887495122721340b2f9c80392963.1665203660.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1836,"url":"https://patchwork.plctlab.org/api/1.2/patches/1836/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d07e2b6f36ea2fd5830924a9bfeda941b774b687.1665290422.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-09T05:09:22","name":"RISC-V: Move certain arrays to riscv-opc.c","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d07e2b6f36ea2fd5830924a9bfeda941b774b687.1665290422.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1844,"url":"https://patchwork.plctlab.org/api/1.2/patches/1844/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010004623.16582-1-mark@harmstone.com/","msgid":"<20221010004623.16582-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-10T00:46:22","name":"[v2,1/2] ld: Add --pdb option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010004623.16582-1-mark@harmstone.com/mbox/"},{"id":1845,"url":"https://patchwork.plctlab.org/api/1.2/patches/1845/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010004623.16582-2-mark@harmstone.com/","msgid":"<20221010004623.16582-2-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-10T00:46:23","name":"[v2,2/2] ld: Add minimal pdb generation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010004623.16582-2-mark@harmstone.com/mbox/"},{"id":1890,"url":"https://patchwork.plctlab.org/api/1.2/patches/1890/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010200433.414320-1-vladimir.mezentsev@oracle.com/","msgid":"<20221010200433.414320-1-vladimir.mezentsev@oracle.com>","list_archive_url":null,"date":"2022-10-10T20:04:33","name":"gprofng: run tests without installation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010200433.414320-1-vladimir.mezentsev@oracle.com/mbox/"},{"id":1893,"url":"https://patchwork.plctlab.org/api/1.2/patches/1893/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010230426.719238-1-vladimir.mezentsev@oracle.com/","msgid":"<20221010230426.719238-1-vladimir.mezentsev@oracle.com>","list_archive_url":null,"date":"2022-10-10T23:04:26","name":"[2/2] gprofng: use the --libdir path to find libraries","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010230426.719238-1-vladimir.mezentsev@oracle.com/mbox/"},{"id":1894,"url":"https://patchwork.plctlab.org/api/1.2/patches/1894/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010235155.842469-1-vladimir.mezentsev@oracle.com/","msgid":"<20221010235155.842469-1-vladimir.mezentsev@oracle.com>","list_archive_url":null,"date":"2022-10-10T23:51:55","name":"[3/3] gprofng: no need to build version.texi","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010235155.842469-1-vladimir.mezentsev@oracle.com/mbox/"},{"id":1895,"url":"https://patchwork.plctlab.org/api/1.2/patches/1895/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011003702.4287-1-mark@harmstone.com/","msgid":"<20221011003702.4287-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-11T00:37:01","name":"[v3,1/2] ld: Add --pdb option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011003702.4287-1-mark@harmstone.com/mbox/"},{"id":1897,"url":"https://patchwork.plctlab.org/api/1.2/patches/1897/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011003702.4287-2-mark@harmstone.com/","msgid":"<20221011003702.4287-2-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-11T00:37:02","name":"[v3,2/2] ld: Add minimal pdb generation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011003702.4287-2-mark@harmstone.com/mbox/"},{"id":1928,"url":"https://patchwork.plctlab.org/api/1.2/patches/1928/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011175332.17156-1-mark@harmstone.com/","msgid":"<20221011175332.17156-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-11T17:53:31","name":"[v4,1/2] ld: Add --pdb option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011175332.17156-1-mark@harmstone.com/mbox/"},{"id":1929,"url":"https://patchwork.plctlab.org/api/1.2/patches/1929/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011175332.17156-2-mark@harmstone.com/","msgid":"<20221011175332.17156-2-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-11T17:53:32","name":"[v4,2/2] ld: Add minimal pdb generation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011175332.17156-2-mark@harmstone.com/mbox/"},{"id":1941,"url":"https://patchwork.plctlab.org/api/1.2/patches/1941/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221012031005.237446-1-simon.marchi@polymtl.ca/","msgid":"<20221012031005.237446-1-simon.marchi@polymtl.ca>","list_archive_url":null,"date":"2022-10-12T03:10:05","name":"[pushed] Re-apply \"Pass PKG_CONFIG_PATH down from top-level Makefile\"","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221012031005.237446-1-simon.marchi@polymtl.ca/mbox/"},{"id":1976,"url":"https://patchwork.plctlab.org/api/1.2/patches/1976/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1216a3f8-2273-8681-f528-9493a66891f0@suse.com/","msgid":"<1216a3f8-2273-8681-f528-9493a66891f0@suse.com>","list_archive_url":null,"date":"2022-10-13T08:16:49","name":"[v4,1/8] x86: constify parse_insn()'\''s input","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1216a3f8-2273-8681-f528-9493a66891f0@suse.com/mbox/"},{"id":1977,"url":"https://patchwork.plctlab.org/api/1.2/patches/1977/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/11599bbe-c779-aa9f-4d5d-c2243f0e69dc@suse.com/","msgid":"<11599bbe-c779-aa9f-4d5d-c2243f0e69dc@suse.com>","list_archive_url":null,"date":"2022-10-13T08:17:17","name":"[v4,2/8] x86: introduce Pass2 insn attribute","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/11599bbe-c779-aa9f-4d5d-c2243f0e69dc@suse.com/mbox/"},{"id":1978,"url":"https://patchwork.plctlab.org/api/1.2/patches/1978/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/357273a3-060c-23db-72da-3fc9d1be3d2a@suse.com/","msgid":"<357273a3-060c-23db-72da-3fc9d1be3d2a@suse.com>","list_archive_url":null,"date":"2022-10-13T08:18:09","name":"[v4,3/8] x86: re-work insn/suffix recognition","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/357273a3-060c-23db-72da-3fc9d1be3d2a@suse.com/mbox/"},{"id":1979,"url":"https://patchwork.plctlab.org/api/1.2/patches/1979/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0ec0587f-6a7b-45b6-8346-e5d774e73636@suse.com/","msgid":"<0ec0587f-6a7b-45b6-8346-e5d774e73636@suse.com>","list_archive_url":null,"date":"2022-10-13T08:18:39","name":"[v4,4/8] x86-64: further re-work insn/suffix recognition to also cover MOVSL","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0ec0587f-6a7b-45b6-8346-e5d774e73636@suse.com/mbox/"},{"id":1980,"url":"https://patchwork.plctlab.org/api/1.2/patches/1980/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fb617d0b-8759-3169-5a65-1178b7fef3d7@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-13T08:19:34","name":"[v4,5/8] ix86: don'\''t recognize/derive Q suffix in the common case","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fb617d0b-8759-3169-5a65-1178b7fef3d7@suse.com/mbox/"},{"id":1981,"url":"https://patchwork.plctlab.org/api/1.2/patches/1981/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1df3bd01-99c5-f56c-d937-970edd42b2b8@suse.com/","msgid":"<1df3bd01-99c5-f56c-d937-970edd42b2b8@suse.com>","list_archive_url":null,"date":"2022-10-13T08:20:14","name":"[v4,6/8] x86-64: allow HLE store of accumulator to absolute 32-bit address","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1df3bd01-99c5-f56c-d937-970edd42b2b8@suse.com/mbox/"},{"id":1982,"url":"https://patchwork.plctlab.org/api/1.2/patches/1982/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8486a218-39ec-16b2-5c6c-5037196b93cf@suse.com/","msgid":"<8486a218-39ec-16b2-5c6c-5037196b93cf@suse.com>","list_archive_url":null,"date":"2022-10-13T08:21:00","name":"[v4,7/8] x86: move bad-use-of-TLS-reloc check","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8486a218-39ec-16b2-5c6c-5037196b93cf@suse.com/mbox/"},{"id":1983,"url":"https://patchwork.plctlab.org/api/1.2/patches/1983/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7d82692d-93df-fbee-9efb-2f44e8a91df3@suse.com/","msgid":"<7d82692d-93df-fbee-9efb-2f44e8a91df3@suse.com>","list_archive_url":null,"date":"2022-10-13T08:22:00","name":"[v4,8/8] x86: drop (now) stray IsString","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7d82692d-93df-fbee-9efb-2f44e8a91df3@suse.com/mbox/"},{"id":2013,"url":"https://patchwork.plctlab.org/api/1.2/patches/2013/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8ab93d7a617ad480dd786210f46db0e5aa07d1ac.1665655719.git.research_trasio@irq.a4lg.com/","msgid":"<8ab93d7a617ad480dd786210f46db0e5aa07d1ac.1665655719.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-13T10:11:41","name":"include: Declare getopt function on old GNU libc","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8ab93d7a617ad480dd786210f46db0e5aa07d1ac.1665655719.git.research_trasio@irq.a4lg.com/mbox/"},{"id":2352,"url":"https://patchwork.plctlab.org/api/1.2/patches/2352/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221013201332.2747246-1-maskray@google.com/","msgid":"<20221013201332.2747246-1-maskray@google.com>","list_archive_url":null,"date":"2022-10-13T20:13:32","name":"ld: Add --undefined-version","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221013201332.2747246-1-maskray@google.com/mbox/"},{"id":2532,"url":"https://patchwork.plctlab.org/api/1.2/patches/2532/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014063520.1428330-2-zengxiao@eswincomputing.com/","msgid":"<20221014063520.1428330-2-zengxiao@eswincomputing.com>","list_archive_url":null,"date":"2022-10-14T06:35:20","name":"[1/1] RISC-V: Make R_RISCV_SUB6 conforms to riscv abi standard","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014063520.1428330-2-zengxiao@eswincomputing.com/mbox/"},{"id":2560,"url":"https://patchwork.plctlab.org/api/1.2/patches/2560/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/027ae69a-636b-6757-297a-eec42936401e@linaro.org/","msgid":"<027ae69a-636b-6757-297a-eec42936401e@linaro.org>","list_archive_url":null,"date":"2022-10-14T07:58:22","name":"[v3] aarch64-pe support for LD, GAS and BFD","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/027ae69a-636b-6757-297a-eec42936401e@linaro.org/mbox/"},{"id":2602,"url":"https://patchwork.plctlab.org/api/1.2/patches/2602/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-2-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-2-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:39","name":"[01/10] Support Intel AVX-IFMA","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-2-haochen.jiang@intel.com/mbox/"},{"id":2608,"url":"https://patchwork.plctlab.org/api/1.2/patches/2608/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-3-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-3-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:40","name":"[02/10] Support Intel AVX-VNNI-INT8","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-3-haochen.jiang@intel.com/mbox/"},{"id":2611,"url":"https://patchwork.plctlab.org/api/1.2/patches/2611/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-4-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-4-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:41","name":"[03/10] Support Intel AVX-NE-CONVERT","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-4-haochen.jiang@intel.com/mbox/"},{"id":2610,"url":"https://patchwork.plctlab.org/api/1.2/patches/2610/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-5-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-5-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:42","name":"[04/10] Support Intel CMPccXADD","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-5-haochen.jiang@intel.com/mbox/"},{"id":2601,"url":"https://patchwork.plctlab.org/api/1.2/patches/2601/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-6-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-6-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:43","name":"[05/10] Add handler for more i386_cpu_flags","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-6-haochen.jiang@intel.com/mbox/"},{"id":2606,"url":"https://patchwork.plctlab.org/api/1.2/patches/2606/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-7-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-7-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:44","name":"[06/10] Support Intel RAO-INT","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-7-haochen.jiang@intel.com/mbox/"},{"id":2609,"url":"https://patchwork.plctlab.org/api/1.2/patches/2609/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-8-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-8-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:45","name":"[07/10] Support Intel WRMSRNS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-8-haochen.jiang@intel.com/mbox/"},{"id":2605,"url":"https://patchwork.plctlab.org/api/1.2/patches/2605/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-9-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-9-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:46","name":"[08/10] Support Intel MSRLIST","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-9-haochen.jiang@intel.com/mbox/"},{"id":2607,"url":"https://patchwork.plctlab.org/api/1.2/patches/2607/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-10-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-10-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:47","name":"[09/10] Support Intel AMX-FP16","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-10-haochen.jiang@intel.com/mbox/"},{"id":2604,"url":"https://patchwork.plctlab.org/api/1.2/patches/2604/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-11-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-11-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:48","name":"[10/10] Support Intel PREFETCHI","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-11-haochen.jiang@intel.com/mbox/"},{"id":2643,"url":"https://patchwork.plctlab.org/api/1.2/patches/2643/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7bac66be-535e-9051-d674-f2f5ba180e17@suse.com/","msgid":"<7bac66be-535e-9051-d674-f2f5ba180e17@suse.com>","list_archive_url":null,"date":"2022-10-14T10:22:34","name":"x86: fold AVX512-VNNI disassembler entries with AVX-VNNI ones","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7bac66be-535e-9051-d674-f2f5ba180e17@suse.com/mbox/"},{"id":2654,"url":"https://patchwork.plctlab.org/api/1.2/patches/2654/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0lIo5+ncY/MqBEq@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-14T11:31:47","name":"PR29677, Field `the_bfd` of `asymbol` is uninitialised","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0lIo5+ncY/MqBEq@squeak.grove.modra.org/mbox/"},{"id":2656,"url":"https://patchwork.plctlab.org/api/1.2/patches/2656/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0lJksn49ZpABY89@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-14T11:35:46","name":"e200 LSP support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0lJksn49ZpABY89@squeak.grove.modra.org/mbox/"},{"id":2657,"url":"https://patchwork.plctlab.org/api/1.2/patches/2657/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0lJxxYoeD5iDYAD@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-14T11:36:39","name":"PowerPC SPE disassembly and tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0lJxxYoeD5iDYAD@squeak.grove.modra.org/mbox/"},{"id":2695,"url":"https://patchwork.plctlab.org/api/1.2/patches/2695/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/DM6PR12MB4219611F6CC2A0702884A602E7249@DM6PR12MB4219.namprd12.prod.outlook.com/","msgid":"","list_archive_url":null,"date":"2022-10-14T13:29:40","name":"Binutils: Adding new testcase for addr2line.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/DM6PR12MB4219611F6CC2A0702884A602E7249@DM6PR12MB4219.namprd12.prod.outlook.com/mbox/"},{"id":2700,"url":"https://patchwork.plctlab.org/api/1.2/patches/2700/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9fd2c88d-98b2-99a4-419f-c7235b2cf960@suse.com/","msgid":"<9fd2c88d-98b2-99a4-419f-c7235b2cf960@suse.com>","list_archive_url":null,"date":"2022-10-14T14:11:35","name":"x86: properly decode EVEX.W for AVX512_4{FMAPS,VNNIW} insns","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9fd2c88d-98b2-99a4-419f-c7235b2cf960@suse.com/mbox/"},{"id":2981,"url":"https://patchwork.plctlab.org/api/1.2/patches/2981/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0uLzalqjm4C87GN@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-16T04:42:53","name":"PowerPC se_rfmci and VLE, SPE2 and LSP insns with -many","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0uLzalqjm4C87GN@squeak.grove.modra.org/mbox/"},{"id":3152,"url":"https://patchwork.plctlab.org/api/1.2/patches/3152/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221016232419.1135-1-mark@harmstone.com/","msgid":"<20221016232419.1135-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-16T23:24:18","name":"[v5,1/2] ld: Add --pdb option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221016232419.1135-1-mark@harmstone.com/mbox/"},{"id":3151,"url":"https://patchwork.plctlab.org/api/1.2/patches/3151/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221016232419.1135-2-mark@harmstone.com/","msgid":"<20221016232419.1135-2-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-16T23:24:19","name":"[v5,2/2] ld: Add minimal pdb generation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221016232419.1135-2-mark@harmstone.com/mbox/"},{"id":3258,"url":"https://patchwork.plctlab.org/api/1.2/patches/3258/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/19c08747-fa5b-1e67-3dd2-c891a2c0c1fa@suse.com/","msgid":"<19c08747-fa5b-1e67-3dd2-c891a2c0c1fa@suse.com>","list_archive_url":null,"date":"2022-10-17T07:44:51","name":"x86: correct CPU_AMX_{BF16,INT8}_FLAGS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/19c08747-fa5b-1e67-3dd2-c891a2c0c1fa@suse.com/mbox/"},{"id":3272,"url":"https://patchwork.plctlab.org/api/1.2/patches/3272/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/85dd526c-d3a7-72dc-5444-ed5573eebec1@suse.com/","msgid":"<85dd526c-d3a7-72dc-5444-ed5573eebec1@suse.com>","list_archive_url":null,"date":"2022-10-17T08:30:12","name":"x86: generalize gas documentation for disabling of ISA extensions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/85dd526c-d3a7-72dc-5444-ed5573eebec1@suse.com/mbox/"},{"id":3759,"url":"https://patchwork.plctlab.org/api/1.2/patches/3759/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-2-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-2-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:15:58","name":"[V2,01/15] sframe.h: Add SFrame format definition","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-2-indu.bhagat@oracle.com/mbox/"},{"id":3762,"url":"https://patchwork.plctlab.org/api/1.2/patches/3762/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-3-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-3-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:15:59","name":"[V2,02/15] gas: add new command line option --gsframe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-3-indu.bhagat@oracle.com/mbox/"},{"id":3761,"url":"https://patchwork.plctlab.org/api/1.2/patches/3761/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-4-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-4-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:00","name":"[V2,03/15] gas: generate .sframe from CFI directives","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-4-indu.bhagat@oracle.com/mbox/"},{"id":3760,"url":"https://patchwork.plctlab.org/api/1.2/patches/3760/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-5-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-5-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:01","name":"[V2,04/15] gas: testsuite: add new tests for SFrame unwind info","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-5-indu.bhagat@oracle.com/mbox/"},{"id":3764,"url":"https://patchwork.plctlab.org/api/1.2/patches/3764/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-6-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-6-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:02","name":"[V2,05/15] libsframe: add the SFrame library","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-6-indu.bhagat@oracle.com/mbox/"},{"id":3766,"url":"https://patchwork.plctlab.org/api/1.2/patches/3766/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-7-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-7-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:03","name":"[V2,06/15] bfd: linker: merge .sframe sections","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-7-indu.bhagat@oracle.com/mbox/"},{"id":3763,"url":"https://patchwork.plctlab.org/api/1.2/patches/3763/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-8-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-8-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:04","name":"[V2,07/15] readelf/objdump: support for SFrame section","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-8-indu.bhagat@oracle.com/mbox/"},{"id":3765,"url":"https://patchwork.plctlab.org/api/1.2/patches/3765/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-9-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-9-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:05","name":"[V2,08/15] unwinder: generate backtrace using SFrame format","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-9-indu.bhagat@oracle.com/mbox/"},{"id":3770,"url":"https://patchwork.plctlab.org/api/1.2/patches/3770/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-10-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-10-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:06","name":"[V2,09/15] unwinder: Add SFrame unwinder tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-10-indu.bhagat@oracle.com/mbox/"},{"id":3769,"url":"https://patchwork.plctlab.org/api/1.2/patches/3769/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-11-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-11-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:07","name":"[V2,10/15] gdb: sim: buildsystem changes to accommodate libsframe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-11-indu.bhagat@oracle.com/mbox/"},{"id":3771,"url":"https://patchwork.plctlab.org/api/1.2/patches/3771/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-12-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-12-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:08","name":"[V2,11/15] libctf: add libsframe to LDFLAGS and LIBS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-12-indu.bhagat@oracle.com/mbox/"},{"id":3768,"url":"https://patchwork.plctlab.org/api/1.2/patches/3768/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-13-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-13-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:09","name":"[V2,12/15] src-release.sh: Add libsframe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-13-indu.bhagat@oracle.com/mbox/"},{"id":3767,"url":"https://patchwork.plctlab.org/api/1.2/patches/3767/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-14-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-14-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:10","name":"[V2,13/15] binutils/NEWS: add text for SFrame support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-14-indu.bhagat@oracle.com/mbox/"},{"id":3772,"url":"https://patchwork.plctlab.org/api/1.2/patches/3772/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-15-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-15-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:11","name":"[V2,14/15] gas/NEWS: add text about new command line option and SFrame support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-15-indu.bhagat@oracle.com/mbox/"},{"id":3773,"url":"https://patchwork.plctlab.org/api/1.2/patches/3773/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-16-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-16-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:12","name":"[V2,15/15] doc: add SFrame spec file","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-16-indu.bhagat@oracle.com/mbox/"},{"id":3999,"url":"https://patchwork.plctlab.org/api/1.2/patches/3999/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221018081205.17880-1-krebbel@linux.ibm.com/","msgid":"<20221018081205.17880-1-krebbel@linux.ibm.com>","list_archive_url":null,"date":"2022-10-18T08:12:05","name":"[1/1] IBM zSystems: Issue error for *DBL relocs on misaligned symbols","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221018081205.17880-1-krebbel@linux.ibm.com/mbox/"},{"id":4141,"url":"https://patchwork.plctlab.org/api/1.2/patches/4141/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/baffaf673f17692b7bcbd604b31800b189988596.camel@espressif.com/","msgid":"","list_archive_url":null,"date":"2022-10-18T12:12:07","name":"xtensa: use definitions from xtensa-config.h","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/baffaf673f17692b7bcbd604b31800b189988596.camel@espressif.com/mbox/"},{"id":4272,"url":"https://patchwork.plctlab.org/api/1.2/patches/4272/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221018174914.470062-1-hjl.tools@gmail.com/","msgid":"<20221018174914.470062-1-hjl.tools@gmail.com>","list_archive_url":null,"date":"2022-10-18T17:49:14","name":"x86: Disable AVX-VNNI when disabling AVX2","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221018174914.470062-1-hjl.tools@gmail.com/mbox/"},{"id":4998,"url":"https://patchwork.plctlab.org/api/1.2/patches/4998/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c2f76e95-09f6-1d92-7ef4-38a3c2955fcd@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-19T09:52:46","name":"x86: re-work AVX-VNNI support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c2f76e95-09f6-1d92-7ef4-38a3c2955fcd@suse.com/mbox/"},{"id":5276,"url":"https://patchwork.plctlab.org/api/1.2/patches/5276/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0/lLtlKqqsmAx0s@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-19T11:53:18","name":"Fix addr2line test for ppc64 elfv1 and mingw","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0/lLtlKqqsmAx0s@squeak.grove.modra.org/mbox/"},{"id":5424,"url":"https://patchwork.plctlab.org/api/1.2/patches/5424/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/07bfebbf3843b47e13d82d4fa16eb14fec942ef7.1666184962.git.research_trasio@irq.a4lg.com/","msgid":"<07bfebbf3843b47e13d82d4fa16eb14fec942ef7.1666184962.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:09:54","name":"binutils: Remove unused substitution PROGRAM","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/07bfebbf3843b47e13d82d4fa16eb14fec942ef7.1666184962.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5433,"url":"https://patchwork.plctlab.org/api/1.2/patches/5433/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2fa7ff719223232402e82a9c91331aea22ace1bb.1666185116.git.research_trasio@irq.a4lg.com/","msgid":"<2fa7ff719223232402e82a9c91331aea22ace1bb.1666185116.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:11:55","name":"[v2,1/8] RISC-V: Add a space at the end of pinfo","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2fa7ff719223232402e82a9c91331aea22ace1bb.1666185116.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5435,"url":"https://patchwork.plctlab.org/api/1.2/patches/5435/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1b30cce5db2cce3b8edca42ab5da114d0b8c9e93.1666185116.git.research_trasio@irq.a4lg.com/","msgid":"<1b30cce5db2cce3b8edca42ab5da114d0b8c9e93.1666185116.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:11:56","name":"[v2,2/8] RISC-V: Fix obvious misalignments ('\''Zbb'\''/'\''Zba'\'')","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1b30cce5db2cce3b8edca42ab5da114d0b8c9e93.1666185116.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5437,"url":"https://patchwork.plctlab.org/api/1.2/patches/5437/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6b0857aa1a2d15ca1cf00b4dcaae0032efbb88ff.1666185116.git.research_trasio@irq.a4lg.com/","msgid":"<6b0857aa1a2d15ca1cf00b4dcaae0032efbb88ff.1666185116.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:11:57","name":"[v2,3/8] RISC-V: Remove spaces in opcode entries","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6b0857aa1a2d15ca1cf00b4dcaae0032efbb88ff.1666185116.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5436,"url":"https://patchwork.plctlab.org/api/1.2/patches/5436/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/889d956caac0f2e95543a14afaeed97188ce384c.1666185116.git.research_trasio@irq.a4lg.com/","msgid":"<889d956caac0f2e95543a14afaeed97188ce384c.1666185116.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:11:58","name":"[v2,4/8] RISC-V: Remove unused instruction macros","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/889d956caac0f2e95543a14afaeed97188ce384c.1666185116.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5440,"url":"https://patchwork.plctlab.org/api/1.2/patches/5440/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8f226ee20d8a5ef6ad7b6c4408b44794a99d542a.1666185116.git.research_trasio@irq.a4lg.com/","msgid":"<8f226ee20d8a5ef6ad7b6c4408b44794a99d542a.1666185116.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:11:59","name":"[v2,5/8] RISC-V: Complete tidying up with SCALL and SBREAK","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8f226ee20d8a5ef6ad7b6c4408b44794a99d542a.1666185116.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5442,"url":"https://patchwork.plctlab.org/api/1.2/patches/5442/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4070184c454a05a39adf0790951e5856e6b2ecb6.1666185116.git.research_trasio@irq.a4lg.com/","msgid":"<4070184c454a05a39adf0790951e5856e6b2ecb6.1666185116.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:12:00","name":"[v2,6/8] RISC-V: Tidying up with fmv.w.x and fmv.x.w","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4070184c454a05a39adf0790951e5856e6b2ecb6.1666185116.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5438,"url":"https://patchwork.plctlab.org/api/1.2/patches/5438/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c1ccda3e7c8fb297eda46dab3936d5c5977178fc.1666185116.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-19T13:12:01","name":"[v2,7/8] RISC-V: Make alias instructions aliases","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c1ccda3e7c8fb297eda46dab3936d5c5977178fc.1666185116.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5441,"url":"https://patchwork.plctlab.org/api/1.2/patches/5441/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/413cfca82c7e8d8a2e977dfda9135903c9cb7c57.1666185116.git.research_trasio@irq.a4lg.com/","msgid":"<413cfca82c7e8d8a2e977dfda9135903c9cb7c57.1666185116.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:12:02","name":"[v2,8/8] RISC-V: Use defined mask and match values","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/413cfca82c7e8d8a2e977dfda9135903c9cb7c57.1666185116.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5439,"url":"https://patchwork.plctlab.org/api/1.2/patches/5439/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/345c5c3b3a53eab04a1e6e91197de2642095c94f.1666185237.git.research_trasio@irq.a4lg.com/","msgid":"<345c5c3b3a53eab04a1e6e91197de2642095c94f.1666185237.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:14:01","name":"RISC-V: Remove RV32EF conflict","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/345c5c3b3a53eab04a1e6e91197de2642095c94f.1666185237.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5616,"url":"https://patchwork.plctlab.org/api/1.2/patches/5616/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019145608.45213-5-haochen.jiang@intel.com/","msgid":"<20221019145608.45213-5-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T14:56:02","name":"[04/10] Support Intel CMPccXADD","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019145608.45213-5-haochen.jiang@intel.com/mbox/"},{"id":5614,"url":"https://patchwork.plctlab.org/api/1.2/patches/5614/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019145608.45213-6-haochen.jiang@intel.com/","msgid":"<20221019145608.45213-6-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T14:56:03","name":"[05/10] Add handler for more i386_cpu_flags","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019145608.45213-6-haochen.jiang@intel.com/mbox/"},{"id":5672,"url":"https://patchwork.plctlab.org/api/1.2/patches/5672/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-2-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-2-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:25","name":"[01/10] Support Intel AVX-IFMA","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-2-haochen.jiang@intel.com/mbox/"},{"id":5691,"url":"https://patchwork.plctlab.org/api/1.2/patches/5691/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-3-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-3-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:26","name":"[02/10] Support Intel AVX-VNNI-INT8","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-3-haochen.jiang@intel.com/mbox/"},{"id":5690,"url":"https://patchwork.plctlab.org/api/1.2/patches/5690/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-4-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-4-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:27","name":"[03/10] Support Intel AVX-NE-CONVERT","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-4-haochen.jiang@intel.com/mbox/"},{"id":5689,"url":"https://patchwork.plctlab.org/api/1.2/patches/5689/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-5-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-5-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:28","name":"[04/10] Support Intel CMPccXADD","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-5-haochen.jiang@intel.com/mbox/"},{"id":5676,"url":"https://patchwork.plctlab.org/api/1.2/patches/5676/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-6-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-6-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:29","name":"[05/10] Add handler for more i386_cpu_flags","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-6-haochen.jiang@intel.com/mbox/"},{"id":5677,"url":"https://patchwork.plctlab.org/api/1.2/patches/5677/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-7-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-7-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:30","name":"[06/10] Support Intel RAO-INT","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-7-haochen.jiang@intel.com/mbox/"},{"id":5681,"url":"https://patchwork.plctlab.org/api/1.2/patches/5681/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-8-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-8-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:31","name":"[07/10] Support Intel WRMSRNS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-8-haochen.jiang@intel.com/mbox/"},{"id":5682,"url":"https://patchwork.plctlab.org/api/1.2/patches/5682/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-9-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-9-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:32","name":"[08/10] Support Intel MSRLIST","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-9-haochen.jiang@intel.com/mbox/"},{"id":5673,"url":"https://patchwork.plctlab.org/api/1.2/patches/5673/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-10-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-10-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:33","name":"[09/10] Support Intel AMX-FP16","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-10-haochen.jiang@intel.com/mbox/"},{"id":5686,"url":"https://patchwork.plctlab.org/api/1.2/patches/5686/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-11-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-11-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:34","name":"[10/10] Support Intel PREFETCHI","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-11-haochen.jiang@intel.com/mbox/"}],"public":true,"mbox":"https://patchwork.plctlab.org/bundle/patchwork-bot/binutils-gdb_2022-10/mbox/"},{"id":7,"url":"https://patchwork.plctlab.org/api/1.2/bundles/7/","web_url":"https://patchwork.plctlab.org/bundle/patchwork-bot/binutils-gdb_2022-09/","project":{"id":2,"url":"https://patchwork.plctlab.org/api/1.2/projects/2/","name":"binutils-gdb","link_name":"binutils-gdb","list_id":"binutils.sourceware.org","list_email":"binutils@sourceware.org","web_url":"https://sourceware.org/mailman/listinfo/binutils","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"name":"binutils-gdb_2022-09","owner":{"id":3,"url":"https://patchwork.plctlab.org/api/1.2/users/3/","username":"patchwork-bot","first_name":"","last_name":"","email":"ouuuleilei@gmail.com"},"patches":[{"id":1573,"url":"https://patchwork.plctlab.org/api/1.2/patches/1573/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930073211.2634-1-jiawei@iscas.ac.cn/","msgid":"<20220930073211.2634-1-jiawei@iscas.ac.cn>","list_archive_url":null,"date":"2022-09-30T07:32:11","name":"[V2] RISC-V: Add Smepmp CSR '\''mseccfg'\'' define and testcases.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930073211.2634-1-jiawei@iscas.ac.cn/mbox/"},{"id":1577,"url":"https://patchwork.plctlab.org/api/1.2/patches/1577/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/76fa0c3c-2303-ebdf-a765-ac4731581517@suse.com/","msgid":"<76fa0c3c-2303-ebdf-a765-ac4731581517@suse.com>","list_archive_url":null,"date":"2022-09-30T08:54:18","name":"objcopy: avoid \"shadowing\" of remove() function name","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/76fa0c3c-2303-ebdf-a765-ac4731581517@suse.com/mbox/"},{"id":1579,"url":"https://patchwork.plctlab.org/api/1.2/patches/1579/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930085852.71213-1-nelson@rivosinc.com/","msgid":"<20220930085852.71213-1-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-09-30T08:58:51","name":"[1/2] RISC-V: Output mapping symbols with ISA string.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930085852.71213-1-nelson@rivosinc.com/mbox/"},{"id":1578,"url":"https://patchwork.plctlab.org/api/1.2/patches/1578/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930085852.71213-2-nelson@rivosinc.com/","msgid":"<20220930085852.71213-2-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-09-30T08:58:52","name":"[2/2] RISC-V: Refer mapping symbol to R_RISCV_RELAX for rvc relaxations.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930085852.71213-2-nelson@rivosinc.com/mbox/"},{"id":1581,"url":"https://patchwork.plctlab.org/api/1.2/patches/1581/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930092058.71286-1-nelson@rivosinc.com/","msgid":"<20220930092058.71286-1-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-09-30T09:20:57","name":"[1/2] RISC-V: Output mapping symbols with ISA string.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930092058.71286-1-nelson@rivosinc.com/mbox/"},{"id":1580,"url":"https://patchwork.plctlab.org/api/1.2/patches/1580/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930092058.71286-2-nelson@rivosinc.com/","msgid":"<20220930092058.71286-2-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-09-30T09:20:58","name":"[2/2] RISC-V: Refer mapping symbol to R_RISCV_RELAX for rvc relaxations.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930092058.71286-2-nelson@rivosinc.com/mbox/"},{"id":1582,"url":"https://patchwork.plctlab.org/api/1.2/patches/1582/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5874dd79-0cf5-d65c-7ea2-13adfc799c0f@suse.com/","msgid":"<5874dd79-0cf5-d65c-7ea2-13adfc799c0f@suse.com>","list_archive_url":null,"date":"2022-09-30T09:41:29","name":"RISC-V: fix build after \"Add support for arbitrary immediate encoding formats\"","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5874dd79-0cf5-d65c-7ea2-13adfc799c0f@suse.com/mbox/"},{"id":1583,"url":"https://patchwork.plctlab.org/api/1.2/patches/1583/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/57d8ac2a-5757-3776-9924-99c17ca69938@suse.com/","msgid":"<57d8ac2a-5757-3776-9924-99c17ca69938@suse.com>","list_archive_url":null,"date":"2022-09-30T09:42:08","name":"RISC-V: fallout from \"re-arrange opcode table for consistent alias handling\"","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/57d8ac2a-5757-3776-9924-99c17ca69938@suse.com/mbox/"},{"id":1584,"url":"https://patchwork.plctlab.org/api/1.2/patches/1584/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e76ef8f7-72b9-5103-cb43-9608af01d017@suse.com/","msgid":"","list_archive_url":null,"date":"2022-09-30T09:42:50","name":"RISC-V: don'\''t cast expressions'\'' X_add_number to long in diagnostics","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e76ef8f7-72b9-5103-cb43-9608af01d017@suse.com/mbox/"},{"id":1585,"url":"https://patchwork.plctlab.org/api/1.2/patches/1585/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/61355429-24b3-17d0-ab03-6fa57ee861d5@suse.cz/","msgid":"<61355429-24b3-17d0-ab03-6fa57ee861d5@suse.cz>","list_archive_url":null,"date":"2022-09-30T09:48:52","name":"[RFC] add --enable-zstd-compressed-debug-sections configure option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/61355429-24b3-17d0-ab03-6fa57ee861d5@suse.cz/mbox/"},{"id":1586,"url":"https://patchwork.plctlab.org/api/1.2/patches/1586/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930103919.323690-1-christoph.muellner@vrull.eu/","msgid":"<20220930103919.323690-1-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2022-09-30T10:39:19","name":"RISC-V: Eliminate long-casts of X_add_number in diagnostics","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930103919.323690-1-christoph.muellner@vrull.eu/mbox/"},{"id":1590,"url":"https://patchwork.plctlab.org/api/1.2/patches/1590/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/DM6PR12MB4219C943049C6D883DEA3E55E7569@DM6PR12MB4219.namprd12.prod.outlook.com/","msgid":"","list_archive_url":null,"date":"2022-09-30T11:41:37","name":"[V2] Ignore DWARF debug information for -gsplit-dwarf with dwarf-5.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/DM6PR12MB4219C943049C6D883DEA3E55E7569@DM6PR12MB4219.namprd12.prod.outlook.com/mbox/"},{"id":1591,"url":"https://patchwork.plctlab.org/api/1.2/patches/1591/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c10321f9-d289-ef84-d263-bc278fb3d31b@suse.com/","msgid":"","list_archive_url":null,"date":"2022-09-30T11:59:04","name":"[1/4] RISC-V/gas: drop riscv_subsets static variable","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c10321f9-d289-ef84-d263-bc278fb3d31b@suse.com/mbox/"},{"id":1593,"url":"https://patchwork.plctlab.org/api/1.2/patches/1593/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3244eea0-c18c-e49a-4588-d69423130226@suse.com/","msgid":"<3244eea0-c18c-e49a-4588-d69423130226@suse.com>","list_archive_url":null,"date":"2022-09-30T11:59:23","name":"[2/4] RISC-V/gas: drop stray call to install_insn()","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3244eea0-c18c-e49a-4588-d69423130226@suse.com/mbox/"},{"id":1592,"url":"https://patchwork.plctlab.org/api/1.2/patches/1592/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/385d01fd-7e57-1f3f-1bae-30aa0c313d63@suse.com/","msgid":"<385d01fd-7e57-1f3f-1bae-30aa0c313d63@suse.com>","list_archive_url":null,"date":"2022-09-30T11:59:45","name":"[3/4] RISC-V/gas: don'\''t open-code insn_length()","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/385d01fd-7e57-1f3f-1bae-30aa0c313d63@suse.com/mbox/"},{"id":1594,"url":"https://patchwork.plctlab.org/api/1.2/patches/1594/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f5757acf-7b90-a0e3-5eea-3b97cc226930@suse.com/","msgid":"","list_archive_url":null,"date":"2022-09-30T12:00:12","name":"[4/4] RISC-V/gas: allow generating up to 176-bit instructions with .insn","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f5757acf-7b90-a0e3-5eea-3b97cc226930@suse.com/mbox/"},{"id":1596,"url":"https://patchwork.plctlab.org/api/1.2/patches/1596/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930140503.38233-1-chigot@adacore.com/","msgid":"<20220930140503.38233-1-chigot@adacore.com>","list_archive_url":null,"date":"2022-09-30T14:05:03","name":"ld/testsuite: consistently add board_ldflags when linking with GCC","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930140503.38233-1-chigot@adacore.com/mbox/"}],"public":true,"mbox":"https://patchwork.plctlab.org/bundle/patchwork-bot/binutils-gdb_2022-09/mbox/"}]' + bundle_name=binutils-gdb_2022-10 ++ jq -rc '.[].name' ++ echo '[{"id":6,"url":"https://patchwork.plctlab.org/api/1.2/bundles/6/","web_url":"https://patchwork.plctlab.org/bundle/patchwork-bot/binutils-gdb_2022-10/","project":{"id":2,"url":"https://patchwork.plctlab.org/api/1.2/projects/2/","name":"binutils-gdb","link_name":"binutils-gdb","list_id":"binutils.sourceware.org","list_email":"binutils@sourceware.org","web_url":"https://sourceware.org/mailman/listinfo/binutils","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"name":"binutils-gdb_2022-10","owner":{"id":3,"url":"https://patchwork.plctlab.org/api/1.2/users/3/","username":"patchwork-bot","first_name":"","last_name":"","email":"ouuuleilei@gmail.com"},"patches":[{"id":1592,"url":"https://patchwork.plctlab.org/api/1.2/patches/1592/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/385d01fd-7e57-1f3f-1bae-30aa0c313d63@suse.com/","msgid":"<385d01fd-7e57-1f3f-1bae-30aa0c313d63@suse.com>","list_archive_url":null,"date":"2022-09-30T11:59:45","name":"[3/4] RISC-V/gas: don'\''t open-code insn_length()","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/385d01fd-7e57-1f3f-1bae-30aa0c313d63@suse.com/mbox/"},{"id":1594,"url":"https://patchwork.plctlab.org/api/1.2/patches/1594/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f5757acf-7b90-a0e3-5eea-3b97cc226930@suse.com/","msgid":"","list_archive_url":null,"date":"2022-09-30T12:00:12","name":"[4/4] RISC-V/gas: allow generating up to 176-bit instructions with .insn","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f5757acf-7b90-a0e3-5eea-3b97cc226930@suse.com/mbox/"},{"id":1596,"url":"https://patchwork.plctlab.org/api/1.2/patches/1596/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930140503.38233-1-chigot@adacore.com/","msgid":"<20220930140503.38233-1-chigot@adacore.com>","list_archive_url":null,"date":"2022-09-30T14:05:03","name":"ld/testsuite: consistently add board_ldflags when linking with GCC","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930140503.38233-1-chigot@adacore.com/mbox/"},{"id":1619,"url":"https://patchwork.plctlab.org/api/1.2/patches/1619/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221001014451.532772-1-maskray@google.com/","msgid":"<20221001014451.532772-1-maskray@google.com>","list_archive_url":null,"date":"2022-10-01T01:44:51","name":"gold, dwp: support zstd compressed input debug sections [PR 29641]","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221001014451.532772-1-maskray@google.com/mbox/"},{"id":1620,"url":"https://patchwork.plctlab.org/api/1.2/patches/1620/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221001023846.590825-1-maskray@google.com/","msgid":"<20221001023846.590825-1-maskray@google.com>","list_archive_url":null,"date":"2022-10-01T02:38:46","name":"gold: add --compress-debug-sections=zstd [PR 29641]","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221001023846.590825-1-maskray@google.com/mbox/"},{"id":1623,"url":"https://patchwork.plctlab.org/api/1.2/patches/1623/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b4477c7f666bdeb7f8e998633c7b0cb62310b9ef.1664599545.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-01T04:45:52","name":"[RFC,1/1] RISC-V: Implement common register pair framework","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b4477c7f666bdeb7f8e998633c7b0cb62310b9ef.1664599545.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1625,"url":"https://patchwork.plctlab.org/api/1.2/patches/1625/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/53a265a1f14d17a6f7b106082f610994c5d546e0.1664602025.git.research_trasio@irq.a4lg.com/","msgid":"<53a265a1f14d17a6f7b106082f610994c5d546e0.1664602025.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-01T05:27:31","name":"[RFC,1/1] RISC-V: Implement extension variants","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/53a265a1f14d17a6f7b106082f610994c5d546e0.1664602025.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1626,"url":"https://patchwork.plctlab.org/api/1.2/patches/1626/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8db04962aba9c780f133840a8934353a58f223fe.1664602716.git.research_trasio@irq.a4lg.com/","msgid":"<8db04962aba9c780f133840a8934353a58f223fe.1664602716.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-01T05:39:26","name":"[1/1] RISC-V: Move supervisor instructions after all unprivileged ones","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8db04962aba9c780f133840a8934353a58f223fe.1664602716.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1627,"url":"https://patchwork.plctlab.org/api/1.2/patches/1627/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221001062057.681440-1-maskray@google.com/","msgid":"<20221001062057.681440-1-maskray@google.com>","list_archive_url":null,"date":"2022-10-01T06:20:57","name":"readelf: support zstd compressed debug sections [PR 29640]","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221001062057.681440-1-maskray@google.com/mbox/"},{"id":1631,"url":"https://patchwork.plctlab.org/api/1.2/patches/1631/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/619f112539c0bdecd58e25664f1250a3479a37f5.1664707612.git.aburgess@redhat.com/","msgid":"<619f112539c0bdecd58e25664f1250a3479a37f5.1664707612.git.aburgess@redhat.com>","list_archive_url":null,"date":"2022-10-02T10:47:52","name":"[PATCHv2,2/2] opcodes/arm: add disassembler styling for arm","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/619f112539c0bdecd58e25664f1250a3479a37f5.1664707612.git.aburgess@redhat.com/mbox/"},{"id":1635,"url":"https://patchwork.plctlab.org/api/1.2/patches/1635/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221002185433.gl7dvytfh5wthifx@lug-owl.de/","msgid":"<20221002185433.gl7dvytfh5wthifx@lug-owl.de>","list_archive_url":null,"date":"2022-10-02T18:54:33","name":"diagnostics.h: GCC 13 got -Wself-move, breaks GDB build","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221002185433.gl7dvytfh5wthifx@lug-owl.de/mbox/"},{"id":1637,"url":"https://patchwork.plctlab.org/api/1.2/patches/1637/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003014313.28766-1-mark@harmstone.com/","msgid":"<20221003014313.28766-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-03T01:43:12","name":"[1/2] ld: Add --pdb option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003014313.28766-1-mark@harmstone.com/mbox/"},{"id":1638,"url":"https://patchwork.plctlab.org/api/1.2/patches/1638/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003014313.28766-2-mark@harmstone.com/","msgid":"<20221003014313.28766-2-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-03T01:43:13","name":"[2/2] ld: Add minimal pdb generation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003014313.28766-2-mark@harmstone.com/mbox/"},{"id":1640,"url":"https://patchwork.plctlab.org/api/1.2/patches/1640/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/597ed978-d121-220c-b56b-2ffb94bd091c@suse.cz/","msgid":"<597ed978-d121-220c-b56b-2ffb94bd091c@suse.cz>","list_archive_url":null,"date":"2022-10-03T07:50:38","name":"[1/2] refactor usage of compressed_debug_section_type","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/597ed978-d121-220c-b56b-2ffb94bd091c@suse.cz/mbox/"},{"id":1641,"url":"https://patchwork.plctlab.org/api/1.2/patches/1641/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b8acdd83-f33a-74b8-e21a-23719a0b1a60@suse.cz/","msgid":"","list_archive_url":null,"date":"2022-10-03T07:50:44","name":"[2/2] add --enable-default-compressed-debug-sections-algorithm configure option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b8acdd83-f33a-74b8-e21a-23719a0b1a60@suse.cz/mbox/"},{"id":1642,"url":"https://patchwork.plctlab.org/api/1.2/patches/1642/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003101328.1790113-1-aburgess@redhat.com/","msgid":"<20221003101328.1790113-1-aburgess@redhat.com>","list_archive_url":null,"date":"2022-10-03T10:13:28","name":"opcodes/riscv: style csr names as registers","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003101328.1790113-1-aburgess@redhat.com/mbox/"},{"id":1643,"url":"https://patchwork.plctlab.org/api/1.2/patches/1643/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7ba14fc4472ce97d4f7a4433cad8a571e89f82f4.1664793840.git.research_trasio@irq.a4lg.com/","msgid":"<7ba14fc4472ce97d4f7a4433cad8a571e89f82f4.1664793840.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-03T10:43:59","name":"[v3,1/6] RISC-V: Fix immediates to have \"immediate\" style","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7ba14fc4472ce97d4f7a4433cad8a571e89f82f4.1664793840.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1644,"url":"https://patchwork.plctlab.org/api/1.2/patches/1644/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a498bec37c1fd1dcda57cbf95e5f8cfba09b31d3.1664793840.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-03T10:44:00","name":"[v3,2/6] RISC-V: Fix printf argument types corresponding %x","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a498bec37c1fd1dcda57cbf95e5f8cfba09b31d3.1664793840.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1647,"url":"https://patchwork.plctlab.org/api/1.2/patches/1647/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0002ea716713ace4998a33dde0b81f4f890d10bf.1664793840.git.research_trasio@irq.a4lg.com/","msgid":"<0002ea716713ace4998a33dde0b81f4f890d10bf.1664793840.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-03T10:44:01","name":"[v3,3/6] RISC-V: Optimize riscv_disassemble_data printf","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0002ea716713ace4998a33dde0b81f4f890d10bf.1664793840.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1646,"url":"https://patchwork.plctlab.org/api/1.2/patches/1646/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c65fc3e9aa58965d6768a28c9fd7467fea9897a5.1664793840.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-03T10:44:02","name":"[v3,4/6] RISC-V: Print comma and tabs as the \"text\" style","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c65fc3e9aa58965d6768a28c9fd7467fea9897a5.1664793840.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1648,"url":"https://patchwork.plctlab.org/api/1.2/patches/1648/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5abe1d8a7694417b990e11d8f6cd6789573872e5.1664793840.git.research_trasio@irq.a4lg.com/","msgid":"<5abe1d8a7694417b990e11d8f6cd6789573872e5.1664793840.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-03T10:44:03","name":"[v3,5/6] RISC-V: Fix T-Head immediate types on printing","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5abe1d8a7694417b990e11d8f6cd6789573872e5.1664793840.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1649,"url":"https://patchwork.plctlab.org/api/1.2/patches/1649/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0b68af932117258c908db62cf87c3a15d3cdec41.1664793840.git.research_trasio@irq.a4lg.com/","msgid":"<0b68af932117258c908db62cf87c3a15d3cdec41.1664793840.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-03T10:44:04","name":"[v3,6/6] RISC-V: Print XTheadMemPair literal as \"immediate\"","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0b68af932117258c908db62cf87c3a15d3cdec41.1664793840.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1656,"url":"https://patchwork.plctlab.org/api/1.2/patches/1656/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/87lepxcd6x.fsf@redhat.com/","msgid":"<87lepxcd6x.fsf@redhat.com>","list_archive_url":null,"date":"2022-10-03T12:19:02","name":"Commit: readelf: Do not load section data from offset 0","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/87lepxcd6x.fsf@redhat.com/mbox/"},{"id":1659,"url":"https://patchwork.plctlab.org/api/1.2/patches/1659/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e0d369d419da9c0441f415da7f54352aead8f655.1664707612.git.aburgess@redhat.com/","msgid":"","list_archive_url":null,"date":"2022-10-03T16:37:36","name":"[PATCHv2,1/2] opcodes/arm: use '\''@'\'' consistently for the comment character","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e0d369d419da9c0441f415da7f54352aead8f655.1664707612.git.aburgess@redhat.com/mbox/"},{"id":1660,"url":"https://patchwork.plctlab.org/api/1.2/patches/1660/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003165848.11142-1-palmer@rivosinc.com/","msgid":"<20221003165848.11142-1-palmer@rivosinc.com>","list_archive_url":null,"date":"2022-10-03T16:58:48","name":"gas: NEWS: Mention the T-Head extensions that were recently added","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003165848.11142-1-palmer@rivosinc.com/mbox/"},{"id":1671,"url":"https://patchwork.plctlab.org/api/1.2/patches/1671/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/YzvrMEdkXjIn5Lfz@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-04T08:13:36","name":"Support objcopy changing compression to or from zstd","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/YzvrMEdkXjIn5Lfz@squeak.grove.modra.org/mbox/"},{"id":1673,"url":"https://patchwork.plctlab.org/api/1.2/patches/1673/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0bc857d306bb7c8130e5328dbe6b9ed2fed3ef87.1664873933.git.research_trasio@irq.a4lg.com/","msgid":"<0bc857d306bb7c8130e5328dbe6b9ed2fed3ef87.1664873933.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-04T08:59:07","name":"[1/2] RISC-V: Fix buffer overflow on print_insn_riscv","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0bc857d306bb7c8130e5328dbe6b9ed2fed3ef87.1664873933.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1672,"url":"https://patchwork.plctlab.org/api/1.2/patches/1672/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/89612fe01d902007bf84a7dfb0df5f85d5c166e4.1664873933.git.research_trasio@irq.a4lg.com/","msgid":"<89612fe01d902007bf84a7dfb0df5f85d5c166e4.1664873933.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-04T08:59:08","name":"[2/2] gdb/riscv: Fix buffer overflow on riscv_insn::fetch_instruction","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/89612fe01d902007bf84a7dfb0df5f85d5c166e4.1664873933.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1676,"url":"https://patchwork.plctlab.org/api/1.2/patches/1676/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fc849c94f4adcac1c4ccc5508c7a145a2f13b2a9.1664876744.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-04T09:45:49","name":"[v2,1/2] RISC-V: Fix buffer overflow on print_insn_riscv","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fc849c94f4adcac1c4ccc5508c7a145a2f13b2a9.1664876744.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1677,"url":"https://patchwork.plctlab.org/api/1.2/patches/1677/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4eb6e59ae2e790dbbf2bc92477edd281648d8814.1664876744.git.research_trasio@irq.a4lg.com/","msgid":"<4eb6e59ae2e790dbbf2bc92477edd281648d8814.1664876744.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-04T09:45:50","name":"[v2,2/2] gdb/riscv: Partial support for instructions up to 176-bits","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4eb6e59ae2e790dbbf2bc92477edd281648d8814.1664876744.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1678,"url":"https://patchwork.plctlab.org/api/1.2/patches/1678/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ebf16f9e1f45115d0793952ccb4a94d4233303f9.1664882725.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-04T11:25:56","name":"[v3,1/2] RISC-V: Fix buffer overflow on print_insn_riscv","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ebf16f9e1f45115d0793952ccb4a94d4233303f9.1664882725.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1679,"url":"https://patchwork.plctlab.org/api/1.2/patches/1679/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/83464b09b8649525259c69c853dfa2c9575a204b.1664882725.git.research_trasio@irq.a4lg.com/","msgid":"<83464b09b8649525259c69c853dfa2c9575a204b.1664882725.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-04T11:25:57","name":"[v3,2/2] gdb/riscv: Partial support for instructions up to 176-bit","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/83464b09b8649525259c69c853dfa2c9575a204b.1664882725.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1681,"url":"https://patchwork.plctlab.org/api/1.2/patches/1681/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ffa9c1d7-e8c2-a62b-ef3e-b565c0ffbe5b@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-04T13:56:27","name":"RISC-V: Zicbo{m,p,z} adjustments to riscv_multi_subset_supports_ext()","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ffa9c1d7-e8c2-a62b-ef3e-b565c0ffbe5b@suse.com/mbox/"},{"id":1690,"url":"https://patchwork.plctlab.org/api/1.2/patches/1690/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221004161720.1963953-1-vladimir.mezentsev@oracle.com/","msgid":"<20221004161720.1963953-1-vladimir.mezentsev@oracle.com>","list_archive_url":null,"date":"2022-10-04T16:17:20","name":"gprofng: fix build with --enable-pgo-build=lto","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221004161720.1963953-1-vladimir.mezentsev@oracle.com/mbox/"},{"id":1691,"url":"https://patchwork.plctlab.org/api/1.2/patches/1691/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c0211bc9c57be6c79c6d878ce147f63b657f461d.camel@espressif.com/","msgid":"","list_archive_url":null,"date":"2022-10-04T16:22:05","name":"bfd: xtensa: fix __stop_SECTION literal drop,","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c0211bc9c57be6c79c6d878ce147f63b657f461d.camel@espressif.com/mbox/"},{"id":1702,"url":"https://patchwork.plctlab.org/api/1.2/patches/1702/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5f482299-6c60-b2b3-9abe-f4a55a5a26c5@univ-grenoble-alpes.fr/","msgid":"<5f482299-6c60-b2b3-9abe-f4a55a5a26c5@univ-grenoble-alpes.fr>","list_archive_url":null,"date":"2022-10-04T20:03:20","name":"[RFC] bfd: use bfd_vma for the 64-bit version of put[lb] and get[lb]","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5f482299-6c60-b2b3-9abe-f4a55a5a26c5@univ-grenoble-alpes.fr/mbox/"},{"id":1711,"url":"https://patchwork.plctlab.org/api/1.2/patches/1711/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Yz0Gsxdxe0TePbJT@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-05T04:23:15","name":"PR29647, objdump -S looping","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Yz0Gsxdxe0TePbJT@squeak.grove.modra.org/mbox/"},{"id":1712,"url":"https://patchwork.plctlab.org/api/1.2/patches/1712/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/02d747d2-f57b-0fb5-b893-842b6cc41f2f@suse.com/","msgid":"<02d747d2-f57b-0fb5-b893-842b6cc41f2f@suse.com>","list_archive_url":null,"date":"2022-10-05T07:20:47","name":"[v3,1/7] x86: constify parse_insn()'\''s input","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/02d747d2-f57b-0fb5-b893-842b6cc41f2f@suse.com/mbox/"},{"id":1713,"url":"https://patchwork.plctlab.org/api/1.2/patches/1713/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/925cb740-4e1b-abc4-8526-aaab6faae5e1@suse.com/","msgid":"<925cb740-4e1b-abc4-8526-aaab6faae5e1@suse.com>","list_archive_url":null,"date":"2022-10-05T07:22:19","name":"[v3,2/7] x86: introduce Pass2 insn attribute","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/925cb740-4e1b-abc4-8526-aaab6faae5e1@suse.com/mbox/"},{"id":1714,"url":"https://patchwork.plctlab.org/api/1.2/patches/1714/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e16d3e78-39ca-f715-508f-a4104b8ab9a9@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-05T07:23:51","name":"[v3,3/7] x86: re-work insn/suffix recognition","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e16d3e78-39ca-f715-508f-a4104b8ab9a9@suse.com/mbox/"},{"id":1715,"url":"https://patchwork.plctlab.org/api/1.2/patches/1715/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e4e4b80b-794c-7485-1997-685adab8fb27@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-05T07:24:20","name":"[v3,4/7] x86-64: further re-work insn/suffix recognition to also cover MOVSL","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e4e4b80b-794c-7485-1997-685adab8fb27@suse.com/mbox/"},{"id":1716,"url":"https://patchwork.plctlab.org/api/1.2/patches/1716/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/540678fc-8bff-ec68-c97c-478d2631998c@suse.com/","msgid":"<540678fc-8bff-ec68-c97c-478d2631998c@suse.com>","list_archive_url":null,"date":"2022-10-05T07:24:55","name":"[v3,5/7] ix86: don'\''t recognize/derive Q suffix in the common case","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/540678fc-8bff-ec68-c97c-478d2631998c@suse.com/mbox/"},{"id":1718,"url":"https://patchwork.plctlab.org/api/1.2/patches/1718/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e4692495-7d3d-074d-14f9-364d4a9a998c@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-05T07:25:25","name":"[v3,6/7] x86-64: allow HLE store of accumulator to absolute 32-bit address","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e4692495-7d3d-074d-14f9-364d4a9a998c@suse.com/mbox/"},{"id":1717,"url":"https://patchwork.plctlab.org/api/1.2/patches/1717/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e8014ebd-d16b-17a7-9f34-3700fc164136@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-05T07:25:57","name":"[v3,7/7] x86: move bad-use-of-TLS-reloc check","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e8014ebd-d16b-17a7-9f34-3700fc164136@suse.com/mbox/"},{"id":1719,"url":"https://patchwork.plctlab.org/api/1.2/patches/1719/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1266f001-4511-2662-dba9-14b4d0317c57@suse.com/","msgid":"<1266f001-4511-2662-dba9-14b4d0317c57@suse.com>","list_archive_url":null,"date":"2022-10-05T07:40:50","name":"x86: drop \"regmask\" static variable","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1266f001-4511-2662-dba9-14b4d0317c57@suse.com/mbox/"},{"id":1751,"url":"https://patchwork.plctlab.org/api/1.2/patches/1751/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/af45c5d57c221e43101c2aa38b14f4b4ac12d011.1665031170.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-06T04:40:15","name":"[v2,1/2] RISC-V: Fallback for instructions longer than 64b","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/af45c5d57c221e43101c2aa38b14f4b4ac12d011.1665031170.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1752,"url":"https://patchwork.plctlab.org/api/1.2/patches/1752/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c6e55781245dd3e8e9b8debd6130fc5449dfbd55.1665031170.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-06T04:40:16","name":"[v2,2/2] RISC-V: Improve \"bits undefined\" diagnostics","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c6e55781245dd3e8e9b8debd6130fc5449dfbd55.1665031170.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1776,"url":"https://patchwork.plctlab.org/api/1.2/patches/1776/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d52952119e15357c0e823f8a2398999359588b4d.1665050099.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-06T09:56:30","name":"[v3,1/2] RISC-V: Fallback for instructions longer than 64b","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d52952119e15357c0e823f8a2398999359588b4d.1665050099.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1777,"url":"https://patchwork.plctlab.org/api/1.2/patches/1777/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d907b1997f60ff7823c4a23e281ec9d8ddcbf3f1.1665050099.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-06T09:56:31","name":"[v3,2/2] RISC-V: Improve \"bits undefined\" diagnostics","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d907b1997f60ff7823c4a23e281ec9d8ddcbf3f1.1665050099.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1781,"url":"https://patchwork.plctlab.org/api/1.2/patches/1781/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221006114628.304185-1-chigot@adacore.com/","msgid":"<20221006114628.304185-1-chigot@adacore.com>","list_archive_url":null,"date":"2022-10-06T11:46:28","name":"RISC-V: fix linker message when relaxation deletes bytes","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221006114628.304185-1-chigot@adacore.com/mbox/"},{"id":1801,"url":"https://patchwork.plctlab.org/api/1.2/patches/1801/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Yz+Yhyg7UewC9/kp@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-07T03:09:59","name":"PR29653, objcopy/strip: fuzzed small input file induces large output file","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Yz+Yhyg7UewC9/kp@squeak.grove.modra.org/mbox/"},{"id":1803,"url":"https://patchwork.plctlab.org/api/1.2/patches/1803/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/PH1P110MB16505D9D39EC5B1DE22FE3D5EC5F9@PH1P110MB1650.NAMP110.PROD.OUTLOOK.COM/","msgid":"","list_archive_url":null,"date":"2022-10-07T04:10:07","name":"@CPP_FOR_BUILD@ problem since binutils-2.38","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/PH1P110MB16505D9D39EC5B1DE22FE3D5EC5F9@PH1P110MB1650.NAMP110.PROD.OUTLOOK.COM/mbox/"},{"id":1827,"url":"https://patchwork.plctlab.org/api/1.2/patches/1827/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8e13bce108ac10a0c1dd911e23ec572926f7ae44.1665203374.git.research_trasio@irq.a4lg.com/","msgid":"<8e13bce108ac10a0c1dd911e23ec572926f7ae44.1665203374.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-08T04:29:53","name":"[v2,1/1] RISC-V: Test DWARF register numbers for \"fp\"","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8e13bce108ac10a0c1dd911e23ec572926f7ae44.1665203374.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1828,"url":"https://patchwork.plctlab.org/api/1.2/patches/1828/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0883001b3572e54d3fba264429c7ade2adb66610.1665203441.git.research_trasio@irq.a4lg.com/","msgid":"<0883001b3572e54d3fba264429c7ade2adb66610.1665203441.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-08T04:31:15","name":"[1/1] RISC-V: Move standard hints before all instructions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0883001b3572e54d3fba264429c7ade2adb66610.1665203441.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1829,"url":"https://patchwork.plctlab.org/api/1.2/patches/1829/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/58e16a241d7376fcae2515c6bd5a2b41d275eeba.1665203531.git.research_trasio@irq.a4lg.com/","msgid":"<58e16a241d7376fcae2515c6bd5a2b41d275eeba.1665203531.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-08T04:32:18","name":"[RFC,1/1] RISC-V: Imply '\''Zicsr'\'' from privileged extensions with CSRs","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/58e16a241d7376fcae2515c6bd5a2b41d275eeba.1665203531.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1830,"url":"https://patchwork.plctlab.org/api/1.2/patches/1830/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/cb5076fc96e8f2097779a3abcde843dcdd660031.1665203660.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-08T04:34:23","name":"[1/5] opcodes/riscv-dis.c: Tidying with comments/clarity","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/cb5076fc96e8f2097779a3abcde843dcdd660031.1665203660.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1832,"url":"https://patchwork.plctlab.org/api/1.2/patches/1832/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1f1aa0838bf9c4f10a45fcfe3c682f7efc79d9ae.1665203660.git.research_trasio@irq.a4lg.com/","msgid":"<1f1aa0838bf9c4f10a45fcfe3c682f7efc79d9ae.1665203660.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-08T04:34:24","name":"[2/5] opcodes/riscv-dis.c: Tidying with spacing","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1f1aa0838bf9c4f10a45fcfe3c682f7efc79d9ae.1665203660.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1831,"url":"https://patchwork.plctlab.org/api/1.2/patches/1831/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/740bc5e2d2618d236519b39fedd1a1d7ae4e05da.1665203660.git.research_trasio@irq.a4lg.com/","msgid":"<740bc5e2d2618d236519b39fedd1a1d7ae4e05da.1665203660.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-08T04:34:25","name":"[3/5] opcodes/riscv-dis.c: Use bool type whenever possible","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/740bc5e2d2618d236519b39fedd1a1d7ae4e05da.1665203660.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1833,"url":"https://patchwork.plctlab.org/api/1.2/patches/1833/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6e3a9c235e317f441b4383b3daa68f2051bdc149.1665203660.git.research_trasio@irq.a4lg.com/","msgid":"<6e3a9c235e317f441b4383b3daa68f2051bdc149.1665203660.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-08T04:34:26","name":"[4/5] opcodes/riscv-dis.c: Make XLEN variable static","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6e3a9c235e317f441b4383b3daa68f2051bdc149.1665203660.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1834,"url":"https://patchwork.plctlab.org/api/1.2/patches/1834/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ad929233a62d887495122721340b2f9c80392963.1665203660.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-08T04:34:27","name":"[5/5] opcodes/riscv-dis.c: Remove last_map_state","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ad929233a62d887495122721340b2f9c80392963.1665203660.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1836,"url":"https://patchwork.plctlab.org/api/1.2/patches/1836/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d07e2b6f36ea2fd5830924a9bfeda941b774b687.1665290422.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-09T05:09:22","name":"RISC-V: Move certain arrays to riscv-opc.c","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d07e2b6f36ea2fd5830924a9bfeda941b774b687.1665290422.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1844,"url":"https://patchwork.plctlab.org/api/1.2/patches/1844/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010004623.16582-1-mark@harmstone.com/","msgid":"<20221010004623.16582-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-10T00:46:22","name":"[v2,1/2] ld: Add --pdb option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010004623.16582-1-mark@harmstone.com/mbox/"},{"id":1845,"url":"https://patchwork.plctlab.org/api/1.2/patches/1845/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010004623.16582-2-mark@harmstone.com/","msgid":"<20221010004623.16582-2-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-10T00:46:23","name":"[v2,2/2] ld: Add minimal pdb generation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010004623.16582-2-mark@harmstone.com/mbox/"},{"id":1890,"url":"https://patchwork.plctlab.org/api/1.2/patches/1890/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010200433.414320-1-vladimir.mezentsev@oracle.com/","msgid":"<20221010200433.414320-1-vladimir.mezentsev@oracle.com>","list_archive_url":null,"date":"2022-10-10T20:04:33","name":"gprofng: run tests without installation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010200433.414320-1-vladimir.mezentsev@oracle.com/mbox/"},{"id":1893,"url":"https://patchwork.plctlab.org/api/1.2/patches/1893/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010230426.719238-1-vladimir.mezentsev@oracle.com/","msgid":"<20221010230426.719238-1-vladimir.mezentsev@oracle.com>","list_archive_url":null,"date":"2022-10-10T23:04:26","name":"[2/2] gprofng: use the --libdir path to find libraries","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010230426.719238-1-vladimir.mezentsev@oracle.com/mbox/"},{"id":1894,"url":"https://patchwork.plctlab.org/api/1.2/patches/1894/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010235155.842469-1-vladimir.mezentsev@oracle.com/","msgid":"<20221010235155.842469-1-vladimir.mezentsev@oracle.com>","list_archive_url":null,"date":"2022-10-10T23:51:55","name":"[3/3] gprofng: no need to build version.texi","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010235155.842469-1-vladimir.mezentsev@oracle.com/mbox/"},{"id":1895,"url":"https://patchwork.plctlab.org/api/1.2/patches/1895/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011003702.4287-1-mark@harmstone.com/","msgid":"<20221011003702.4287-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-11T00:37:01","name":"[v3,1/2] ld: Add --pdb option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011003702.4287-1-mark@harmstone.com/mbox/"},{"id":1897,"url":"https://patchwork.plctlab.org/api/1.2/patches/1897/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011003702.4287-2-mark@harmstone.com/","msgid":"<20221011003702.4287-2-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-11T00:37:02","name":"[v3,2/2] ld: Add minimal pdb generation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011003702.4287-2-mark@harmstone.com/mbox/"},{"id":1928,"url":"https://patchwork.plctlab.org/api/1.2/patches/1928/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011175332.17156-1-mark@harmstone.com/","msgid":"<20221011175332.17156-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-11T17:53:31","name":"[v4,1/2] ld: Add --pdb option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011175332.17156-1-mark@harmstone.com/mbox/"},{"id":1929,"url":"https://patchwork.plctlab.org/api/1.2/patches/1929/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011175332.17156-2-mark@harmstone.com/","msgid":"<20221011175332.17156-2-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-11T17:53:32","name":"[v4,2/2] ld: Add minimal pdb generation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011175332.17156-2-mark@harmstone.com/mbox/"},{"id":1941,"url":"https://patchwork.plctlab.org/api/1.2/patches/1941/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221012031005.237446-1-simon.marchi@polymtl.ca/","msgid":"<20221012031005.237446-1-simon.marchi@polymtl.ca>","list_archive_url":null,"date":"2022-10-12T03:10:05","name":"[pushed] Re-apply \"Pass PKG_CONFIG_PATH down from top-level Makefile\"","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221012031005.237446-1-simon.marchi@polymtl.ca/mbox/"},{"id":1976,"url":"https://patchwork.plctlab.org/api/1.2/patches/1976/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1216a3f8-2273-8681-f528-9493a66891f0@suse.com/","msgid":"<1216a3f8-2273-8681-f528-9493a66891f0@suse.com>","list_archive_url":null,"date":"2022-10-13T08:16:49","name":"[v4,1/8] x86: constify parse_insn()'\''s input","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1216a3f8-2273-8681-f528-9493a66891f0@suse.com/mbox/"},{"id":1977,"url":"https://patchwork.plctlab.org/api/1.2/patches/1977/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/11599bbe-c779-aa9f-4d5d-c2243f0e69dc@suse.com/","msgid":"<11599bbe-c779-aa9f-4d5d-c2243f0e69dc@suse.com>","list_archive_url":null,"date":"2022-10-13T08:17:17","name":"[v4,2/8] x86: introduce Pass2 insn attribute","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/11599bbe-c779-aa9f-4d5d-c2243f0e69dc@suse.com/mbox/"},{"id":1978,"url":"https://patchwork.plctlab.org/api/1.2/patches/1978/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/357273a3-060c-23db-72da-3fc9d1be3d2a@suse.com/","msgid":"<357273a3-060c-23db-72da-3fc9d1be3d2a@suse.com>","list_archive_url":null,"date":"2022-10-13T08:18:09","name":"[v4,3/8] x86: re-work insn/suffix recognition","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/357273a3-060c-23db-72da-3fc9d1be3d2a@suse.com/mbox/"},{"id":1979,"url":"https://patchwork.plctlab.org/api/1.2/patches/1979/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0ec0587f-6a7b-45b6-8346-e5d774e73636@suse.com/","msgid":"<0ec0587f-6a7b-45b6-8346-e5d774e73636@suse.com>","list_archive_url":null,"date":"2022-10-13T08:18:39","name":"[v4,4/8] x86-64: further re-work insn/suffix recognition to also cover MOVSL","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0ec0587f-6a7b-45b6-8346-e5d774e73636@suse.com/mbox/"},{"id":1980,"url":"https://patchwork.plctlab.org/api/1.2/patches/1980/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fb617d0b-8759-3169-5a65-1178b7fef3d7@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-13T08:19:34","name":"[v4,5/8] ix86: don'\''t recognize/derive Q suffix in the common case","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fb617d0b-8759-3169-5a65-1178b7fef3d7@suse.com/mbox/"},{"id":1981,"url":"https://patchwork.plctlab.org/api/1.2/patches/1981/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1df3bd01-99c5-f56c-d937-970edd42b2b8@suse.com/","msgid":"<1df3bd01-99c5-f56c-d937-970edd42b2b8@suse.com>","list_archive_url":null,"date":"2022-10-13T08:20:14","name":"[v4,6/8] x86-64: allow HLE store of accumulator to absolute 32-bit address","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1df3bd01-99c5-f56c-d937-970edd42b2b8@suse.com/mbox/"},{"id":1982,"url":"https://patchwork.plctlab.org/api/1.2/patches/1982/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8486a218-39ec-16b2-5c6c-5037196b93cf@suse.com/","msgid":"<8486a218-39ec-16b2-5c6c-5037196b93cf@suse.com>","list_archive_url":null,"date":"2022-10-13T08:21:00","name":"[v4,7/8] x86: move bad-use-of-TLS-reloc check","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8486a218-39ec-16b2-5c6c-5037196b93cf@suse.com/mbox/"},{"id":1983,"url":"https://patchwork.plctlab.org/api/1.2/patches/1983/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7d82692d-93df-fbee-9efb-2f44e8a91df3@suse.com/","msgid":"<7d82692d-93df-fbee-9efb-2f44e8a91df3@suse.com>","list_archive_url":null,"date":"2022-10-13T08:22:00","name":"[v4,8/8] x86: drop (now) stray IsString","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7d82692d-93df-fbee-9efb-2f44e8a91df3@suse.com/mbox/"},{"id":2013,"url":"https://patchwork.plctlab.org/api/1.2/patches/2013/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8ab93d7a617ad480dd786210f46db0e5aa07d1ac.1665655719.git.research_trasio@irq.a4lg.com/","msgid":"<8ab93d7a617ad480dd786210f46db0e5aa07d1ac.1665655719.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-13T10:11:41","name":"include: Declare getopt function on old GNU libc","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8ab93d7a617ad480dd786210f46db0e5aa07d1ac.1665655719.git.research_trasio@irq.a4lg.com/mbox/"},{"id":2352,"url":"https://patchwork.plctlab.org/api/1.2/patches/2352/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221013201332.2747246-1-maskray@google.com/","msgid":"<20221013201332.2747246-1-maskray@google.com>","list_archive_url":null,"date":"2022-10-13T20:13:32","name":"ld: Add --undefined-version","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221013201332.2747246-1-maskray@google.com/mbox/"},{"id":2532,"url":"https://patchwork.plctlab.org/api/1.2/patches/2532/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014063520.1428330-2-zengxiao@eswincomputing.com/","msgid":"<20221014063520.1428330-2-zengxiao@eswincomputing.com>","list_archive_url":null,"date":"2022-10-14T06:35:20","name":"[1/1] RISC-V: Make R_RISCV_SUB6 conforms to riscv abi standard","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014063520.1428330-2-zengxiao@eswincomputing.com/mbox/"},{"id":2560,"url":"https://patchwork.plctlab.org/api/1.2/patches/2560/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/027ae69a-636b-6757-297a-eec42936401e@linaro.org/","msgid":"<027ae69a-636b-6757-297a-eec42936401e@linaro.org>","list_archive_url":null,"date":"2022-10-14T07:58:22","name":"[v3] aarch64-pe support for LD, GAS and BFD","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/027ae69a-636b-6757-297a-eec42936401e@linaro.org/mbox/"},{"id":2602,"url":"https://patchwork.plctlab.org/api/1.2/patches/2602/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-2-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-2-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:39","name":"[01/10] Support Intel AVX-IFMA","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-2-haochen.jiang@intel.com/mbox/"},{"id":2608,"url":"https://patchwork.plctlab.org/api/1.2/patches/2608/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-3-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-3-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:40","name":"[02/10] Support Intel AVX-VNNI-INT8","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-3-haochen.jiang@intel.com/mbox/"},{"id":2611,"url":"https://patchwork.plctlab.org/api/1.2/patches/2611/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-4-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-4-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:41","name":"[03/10] Support Intel AVX-NE-CONVERT","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-4-haochen.jiang@intel.com/mbox/"},{"id":2610,"url":"https://patchwork.plctlab.org/api/1.2/patches/2610/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-5-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-5-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:42","name":"[04/10] Support Intel CMPccXADD","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-5-haochen.jiang@intel.com/mbox/"},{"id":2601,"url":"https://patchwork.plctlab.org/api/1.2/patches/2601/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-6-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-6-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:43","name":"[05/10] Add handler for more i386_cpu_flags","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-6-haochen.jiang@intel.com/mbox/"},{"id":2606,"url":"https://patchwork.plctlab.org/api/1.2/patches/2606/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-7-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-7-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:44","name":"[06/10] Support Intel RAO-INT","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-7-haochen.jiang@intel.com/mbox/"},{"id":2609,"url":"https://patchwork.plctlab.org/api/1.2/patches/2609/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-8-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-8-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:45","name":"[07/10] Support Intel WRMSRNS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-8-haochen.jiang@intel.com/mbox/"},{"id":2605,"url":"https://patchwork.plctlab.org/api/1.2/patches/2605/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-9-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-9-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:46","name":"[08/10] Support Intel MSRLIST","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-9-haochen.jiang@intel.com/mbox/"},{"id":2607,"url":"https://patchwork.plctlab.org/api/1.2/patches/2607/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-10-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-10-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:47","name":"[09/10] Support Intel AMX-FP16","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-10-haochen.jiang@intel.com/mbox/"},{"id":2604,"url":"https://patchwork.plctlab.org/api/1.2/patches/2604/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-11-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-11-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:48","name":"[10/10] Support Intel PREFETCHI","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-11-haochen.jiang@intel.com/mbox/"},{"id":2643,"url":"https://patchwork.plctlab.org/api/1.2/patches/2643/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7bac66be-535e-9051-d674-f2f5ba180e17@suse.com/","msgid":"<7bac66be-535e-9051-d674-f2f5ba180e17@suse.com>","list_archive_url":null,"date":"2022-10-14T10:22:34","name":"x86: fold AVX512-VNNI disassembler entries with AVX-VNNI ones","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7bac66be-535e-9051-d674-f2f5ba180e17@suse.com/mbox/"},{"id":2654,"url":"https://patchwork.plctlab.org/api/1.2/patches/2654/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0lIo5+ncY/MqBEq@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-14T11:31:47","name":"PR29677, Field `the_bfd` of `asymbol` is uninitialised","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0lIo5+ncY/MqBEq@squeak.grove.modra.org/mbox/"},{"id":2656,"url":"https://patchwork.plctlab.org/api/1.2/patches/2656/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0lJksn49ZpABY89@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-14T11:35:46","name":"e200 LSP support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0lJksn49ZpABY89@squeak.grove.modra.org/mbox/"},{"id":2657,"url":"https://patchwork.plctlab.org/api/1.2/patches/2657/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0lJxxYoeD5iDYAD@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-14T11:36:39","name":"PowerPC SPE disassembly and tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0lJxxYoeD5iDYAD@squeak.grove.modra.org/mbox/"},{"id":2695,"url":"https://patchwork.plctlab.org/api/1.2/patches/2695/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/DM6PR12MB4219611F6CC2A0702884A602E7249@DM6PR12MB4219.namprd12.prod.outlook.com/","msgid":"","list_archive_url":null,"date":"2022-10-14T13:29:40","name":"Binutils: Adding new testcase for addr2line.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/DM6PR12MB4219611F6CC2A0702884A602E7249@DM6PR12MB4219.namprd12.prod.outlook.com/mbox/"},{"id":2700,"url":"https://patchwork.plctlab.org/api/1.2/patches/2700/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9fd2c88d-98b2-99a4-419f-c7235b2cf960@suse.com/","msgid":"<9fd2c88d-98b2-99a4-419f-c7235b2cf960@suse.com>","list_archive_url":null,"date":"2022-10-14T14:11:35","name":"x86: properly decode EVEX.W for AVX512_4{FMAPS,VNNIW} insns","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9fd2c88d-98b2-99a4-419f-c7235b2cf960@suse.com/mbox/"},{"id":2981,"url":"https://patchwork.plctlab.org/api/1.2/patches/2981/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0uLzalqjm4C87GN@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-16T04:42:53","name":"PowerPC se_rfmci and VLE, SPE2 and LSP insns with -many","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0uLzalqjm4C87GN@squeak.grove.modra.org/mbox/"},{"id":3152,"url":"https://patchwork.plctlab.org/api/1.2/patches/3152/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221016232419.1135-1-mark@harmstone.com/","msgid":"<20221016232419.1135-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-16T23:24:18","name":"[v5,1/2] ld: Add --pdb option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221016232419.1135-1-mark@harmstone.com/mbox/"},{"id":3151,"url":"https://patchwork.plctlab.org/api/1.2/patches/3151/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221016232419.1135-2-mark@harmstone.com/","msgid":"<20221016232419.1135-2-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-16T23:24:19","name":"[v5,2/2] ld: Add minimal pdb generation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221016232419.1135-2-mark@harmstone.com/mbox/"},{"id":3258,"url":"https://patchwork.plctlab.org/api/1.2/patches/3258/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/19c08747-fa5b-1e67-3dd2-c891a2c0c1fa@suse.com/","msgid":"<19c08747-fa5b-1e67-3dd2-c891a2c0c1fa@suse.com>","list_archive_url":null,"date":"2022-10-17T07:44:51","name":"x86: correct CPU_AMX_{BF16,INT8}_FLAGS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/19c08747-fa5b-1e67-3dd2-c891a2c0c1fa@suse.com/mbox/"},{"id":3272,"url":"https://patchwork.plctlab.org/api/1.2/patches/3272/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/85dd526c-d3a7-72dc-5444-ed5573eebec1@suse.com/","msgid":"<85dd526c-d3a7-72dc-5444-ed5573eebec1@suse.com>","list_archive_url":null,"date":"2022-10-17T08:30:12","name":"x86: generalize gas documentation for disabling of ISA extensions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/85dd526c-d3a7-72dc-5444-ed5573eebec1@suse.com/mbox/"},{"id":3759,"url":"https://patchwork.plctlab.org/api/1.2/patches/3759/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-2-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-2-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:15:58","name":"[V2,01/15] sframe.h: Add SFrame format definition","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-2-indu.bhagat@oracle.com/mbox/"},{"id":3762,"url":"https://patchwork.plctlab.org/api/1.2/patches/3762/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-3-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-3-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:15:59","name":"[V2,02/15] gas: add new command line option --gsframe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-3-indu.bhagat@oracle.com/mbox/"},{"id":3761,"url":"https://patchwork.plctlab.org/api/1.2/patches/3761/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-4-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-4-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:00","name":"[V2,03/15] gas: generate .sframe from CFI directives","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-4-indu.bhagat@oracle.com/mbox/"},{"id":3760,"url":"https://patchwork.plctlab.org/api/1.2/patches/3760/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-5-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-5-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:01","name":"[V2,04/15] gas: testsuite: add new tests for SFrame unwind info","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-5-indu.bhagat@oracle.com/mbox/"},{"id":3764,"url":"https://patchwork.plctlab.org/api/1.2/patches/3764/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-6-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-6-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:02","name":"[V2,05/15] libsframe: add the SFrame library","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-6-indu.bhagat@oracle.com/mbox/"},{"id":3766,"url":"https://patchwork.plctlab.org/api/1.2/patches/3766/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-7-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-7-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:03","name":"[V2,06/15] bfd: linker: merge .sframe sections","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-7-indu.bhagat@oracle.com/mbox/"},{"id":3763,"url":"https://patchwork.plctlab.org/api/1.2/patches/3763/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-8-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-8-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:04","name":"[V2,07/15] readelf/objdump: support for SFrame section","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-8-indu.bhagat@oracle.com/mbox/"},{"id":3765,"url":"https://patchwork.plctlab.org/api/1.2/patches/3765/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-9-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-9-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:05","name":"[V2,08/15] unwinder: generate backtrace using SFrame format","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-9-indu.bhagat@oracle.com/mbox/"},{"id":3770,"url":"https://patchwork.plctlab.org/api/1.2/patches/3770/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-10-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-10-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:06","name":"[V2,09/15] unwinder: Add SFrame unwinder tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-10-indu.bhagat@oracle.com/mbox/"},{"id":3769,"url":"https://patchwork.plctlab.org/api/1.2/patches/3769/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-11-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-11-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:07","name":"[V2,10/15] gdb: sim: buildsystem changes to accommodate libsframe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-11-indu.bhagat@oracle.com/mbox/"},{"id":3771,"url":"https://patchwork.plctlab.org/api/1.2/patches/3771/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-12-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-12-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:08","name":"[V2,11/15] libctf: add libsframe to LDFLAGS and LIBS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-12-indu.bhagat@oracle.com/mbox/"},{"id":3768,"url":"https://patchwork.plctlab.org/api/1.2/patches/3768/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-13-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-13-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:09","name":"[V2,12/15] src-release.sh: Add libsframe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-13-indu.bhagat@oracle.com/mbox/"},{"id":3767,"url":"https://patchwork.plctlab.org/api/1.2/patches/3767/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-14-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-14-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:10","name":"[V2,13/15] binutils/NEWS: add text for SFrame support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-14-indu.bhagat@oracle.com/mbox/"},{"id":3772,"url":"https://patchwork.plctlab.org/api/1.2/patches/3772/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-15-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-15-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:11","name":"[V2,14/15] gas/NEWS: add text about new command line option and SFrame support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-15-indu.bhagat@oracle.com/mbox/"},{"id":3773,"url":"https://patchwork.plctlab.org/api/1.2/patches/3773/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-16-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-16-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:12","name":"[V2,15/15] doc: add SFrame spec file","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-16-indu.bhagat@oracle.com/mbox/"},{"id":3999,"url":"https://patchwork.plctlab.org/api/1.2/patches/3999/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221018081205.17880-1-krebbel@linux.ibm.com/","msgid":"<20221018081205.17880-1-krebbel@linux.ibm.com>","list_archive_url":null,"date":"2022-10-18T08:12:05","name":"[1/1] IBM zSystems: Issue error for *DBL relocs on misaligned symbols","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221018081205.17880-1-krebbel@linux.ibm.com/mbox/"},{"id":4141,"url":"https://patchwork.plctlab.org/api/1.2/patches/4141/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/baffaf673f17692b7bcbd604b31800b189988596.camel@espressif.com/","msgid":"","list_archive_url":null,"date":"2022-10-18T12:12:07","name":"xtensa: use definitions from xtensa-config.h","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/baffaf673f17692b7bcbd604b31800b189988596.camel@espressif.com/mbox/"},{"id":4272,"url":"https://patchwork.plctlab.org/api/1.2/patches/4272/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221018174914.470062-1-hjl.tools@gmail.com/","msgid":"<20221018174914.470062-1-hjl.tools@gmail.com>","list_archive_url":null,"date":"2022-10-18T17:49:14","name":"x86: Disable AVX-VNNI when disabling AVX2","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221018174914.470062-1-hjl.tools@gmail.com/mbox/"},{"id":4998,"url":"https://patchwork.plctlab.org/api/1.2/patches/4998/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c2f76e95-09f6-1d92-7ef4-38a3c2955fcd@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-19T09:52:46","name":"x86: re-work AVX-VNNI support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c2f76e95-09f6-1d92-7ef4-38a3c2955fcd@suse.com/mbox/"},{"id":5276,"url":"https://patchwork.plctlab.org/api/1.2/patches/5276/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0/lLtlKqqsmAx0s@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-19T11:53:18","name":"Fix addr2line test for ppc64 elfv1 and mingw","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0/lLtlKqqsmAx0s@squeak.grove.modra.org/mbox/"},{"id":5424,"url":"https://patchwork.plctlab.org/api/1.2/patches/5424/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/07bfebbf3843b47e13d82d4fa16eb14fec942ef7.1666184962.git.research_trasio@irq.a4lg.com/","msgid":"<07bfebbf3843b47e13d82d4fa16eb14fec942ef7.1666184962.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:09:54","name":"binutils: Remove unused substitution PROGRAM","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/07bfebbf3843b47e13d82d4fa16eb14fec942ef7.1666184962.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5433,"url":"https://patchwork.plctlab.org/api/1.2/patches/5433/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2fa7ff719223232402e82a9c91331aea22ace1bb.1666185116.git.research_trasio@irq.a4lg.com/","msgid":"<2fa7ff719223232402e82a9c91331aea22ace1bb.1666185116.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:11:55","name":"[v2,1/8] RISC-V: Add a space at the end of pinfo","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2fa7ff719223232402e82a9c91331aea22ace1bb.1666185116.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5435,"url":"https://patchwork.plctlab.org/api/1.2/patches/5435/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1b30cce5db2cce3b8edca42ab5da114d0b8c9e93.1666185116.git.research_trasio@irq.a4lg.com/","msgid":"<1b30cce5db2cce3b8edca42ab5da114d0b8c9e93.1666185116.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:11:56","name":"[v2,2/8] RISC-V: Fix obvious misalignments ('\''Zbb'\''/'\''Zba'\'')","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1b30cce5db2cce3b8edca42ab5da114d0b8c9e93.1666185116.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5437,"url":"https://patchwork.plctlab.org/api/1.2/patches/5437/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6b0857aa1a2d15ca1cf00b4dcaae0032efbb88ff.1666185116.git.research_trasio@irq.a4lg.com/","msgid":"<6b0857aa1a2d15ca1cf00b4dcaae0032efbb88ff.1666185116.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:11:57","name":"[v2,3/8] RISC-V: Remove spaces in opcode entries","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6b0857aa1a2d15ca1cf00b4dcaae0032efbb88ff.1666185116.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5436,"url":"https://patchwork.plctlab.org/api/1.2/patches/5436/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/889d956caac0f2e95543a14afaeed97188ce384c.1666185116.git.research_trasio@irq.a4lg.com/","msgid":"<889d956caac0f2e95543a14afaeed97188ce384c.1666185116.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:11:58","name":"[v2,4/8] RISC-V: Remove unused instruction macros","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/889d956caac0f2e95543a14afaeed97188ce384c.1666185116.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5440,"url":"https://patchwork.plctlab.org/api/1.2/patches/5440/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8f226ee20d8a5ef6ad7b6c4408b44794a99d542a.1666185116.git.research_trasio@irq.a4lg.com/","msgid":"<8f226ee20d8a5ef6ad7b6c4408b44794a99d542a.1666185116.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:11:59","name":"[v2,5/8] RISC-V: Complete tidying up with SCALL and SBREAK","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8f226ee20d8a5ef6ad7b6c4408b44794a99d542a.1666185116.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5442,"url":"https://patchwork.plctlab.org/api/1.2/patches/5442/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4070184c454a05a39adf0790951e5856e6b2ecb6.1666185116.git.research_trasio@irq.a4lg.com/","msgid":"<4070184c454a05a39adf0790951e5856e6b2ecb6.1666185116.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:12:00","name":"[v2,6/8] RISC-V: Tidying up with fmv.w.x and fmv.x.w","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4070184c454a05a39adf0790951e5856e6b2ecb6.1666185116.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5438,"url":"https://patchwork.plctlab.org/api/1.2/patches/5438/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c1ccda3e7c8fb297eda46dab3936d5c5977178fc.1666185116.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-19T13:12:01","name":"[v2,7/8] RISC-V: Make alias instructions aliases","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c1ccda3e7c8fb297eda46dab3936d5c5977178fc.1666185116.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5441,"url":"https://patchwork.plctlab.org/api/1.2/patches/5441/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/413cfca82c7e8d8a2e977dfda9135903c9cb7c57.1666185116.git.research_trasio@irq.a4lg.com/","msgid":"<413cfca82c7e8d8a2e977dfda9135903c9cb7c57.1666185116.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:12:02","name":"[v2,8/8] RISC-V: Use defined mask and match values","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/413cfca82c7e8d8a2e977dfda9135903c9cb7c57.1666185116.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5439,"url":"https://patchwork.plctlab.org/api/1.2/patches/5439/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/345c5c3b3a53eab04a1e6e91197de2642095c94f.1666185237.git.research_trasio@irq.a4lg.com/","msgid":"<345c5c3b3a53eab04a1e6e91197de2642095c94f.1666185237.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:14:01","name":"RISC-V: Remove RV32EF conflict","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/345c5c3b3a53eab04a1e6e91197de2642095c94f.1666185237.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5616,"url":"https://patchwork.plctlab.org/api/1.2/patches/5616/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019145608.45213-5-haochen.jiang@intel.com/","msgid":"<20221019145608.45213-5-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T14:56:02","name":"[04/10] Support Intel CMPccXADD","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019145608.45213-5-haochen.jiang@intel.com/mbox/"},{"id":5614,"url":"https://patchwork.plctlab.org/api/1.2/patches/5614/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019145608.45213-6-haochen.jiang@intel.com/","msgid":"<20221019145608.45213-6-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T14:56:03","name":"[05/10] Add handler for more i386_cpu_flags","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019145608.45213-6-haochen.jiang@intel.com/mbox/"},{"id":5672,"url":"https://patchwork.plctlab.org/api/1.2/patches/5672/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-2-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-2-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:25","name":"[01/10] Support Intel AVX-IFMA","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-2-haochen.jiang@intel.com/mbox/"},{"id":5691,"url":"https://patchwork.plctlab.org/api/1.2/patches/5691/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-3-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-3-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:26","name":"[02/10] Support Intel AVX-VNNI-INT8","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-3-haochen.jiang@intel.com/mbox/"},{"id":5690,"url":"https://patchwork.plctlab.org/api/1.2/patches/5690/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-4-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-4-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:27","name":"[03/10] Support Intel AVX-NE-CONVERT","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-4-haochen.jiang@intel.com/mbox/"},{"id":5689,"url":"https://patchwork.plctlab.org/api/1.2/patches/5689/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-5-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-5-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:28","name":"[04/10] Support Intel CMPccXADD","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-5-haochen.jiang@intel.com/mbox/"},{"id":5676,"url":"https://patchwork.plctlab.org/api/1.2/patches/5676/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-6-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-6-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:29","name":"[05/10] Add handler for more i386_cpu_flags","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-6-haochen.jiang@intel.com/mbox/"},{"id":5677,"url":"https://patchwork.plctlab.org/api/1.2/patches/5677/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-7-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-7-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:30","name":"[06/10] Support Intel RAO-INT","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-7-haochen.jiang@intel.com/mbox/"},{"id":5681,"url":"https://patchwork.plctlab.org/api/1.2/patches/5681/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-8-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-8-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:31","name":"[07/10] Support Intel WRMSRNS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-8-haochen.jiang@intel.com/mbox/"},{"id":5682,"url":"https://patchwork.plctlab.org/api/1.2/patches/5682/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-9-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-9-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:32","name":"[08/10] Support Intel MSRLIST","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-9-haochen.jiang@intel.com/mbox/"},{"id":5673,"url":"https://patchwork.plctlab.org/api/1.2/patches/5673/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-10-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-10-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:33","name":"[09/10] Support Intel AMX-FP16","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-10-haochen.jiang@intel.com/mbox/"},{"id":5686,"url":"https://patchwork.plctlab.org/api/1.2/patches/5686/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-11-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-11-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:34","name":"[10/10] Support Intel PREFETCHI","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-11-haochen.jiang@intel.com/mbox/"}],"public":true,"mbox":"https://patchwork.plctlab.org/bundle/patchwork-bot/binutils-gdb_2022-10/mbox/"},{"id":7,"url":"https://patchwork.plctlab.org/api/1.2/bundles/7/","web_url":"https://patchwork.plctlab.org/bundle/patchwork-bot/binutils-gdb_2022-09/","project":{"id":2,"url":"https://patchwork.plctlab.org/api/1.2/projects/2/","name":"binutils-gdb","link_name":"binutils-gdb","list_id":"binutils.sourceware.org","list_email":"binutils@sourceware.org","web_url":"https://sourceware.org/mailman/listinfo/binutils","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"name":"binutils-gdb_2022-09","owner":{"id":3,"url":"https://patchwork.plctlab.org/api/1.2/users/3/","username":"patchwork-bot","first_name":"","last_name":"","email":"ouuuleilei@gmail.com"},"patches":[{"id":1573,"url":"https://patchwork.plctlab.org/api/1.2/patches/1573/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930073211.2634-1-jiawei@iscas.ac.cn/","msgid":"<20220930073211.2634-1-jiawei@iscas.ac.cn>","list_archive_url":null,"date":"2022-09-30T07:32:11","name":"[V2] RISC-V: Add Smepmp CSR '\''mseccfg'\'' define and testcases.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930073211.2634-1-jiawei@iscas.ac.cn/mbox/"},{"id":1577,"url":"https://patchwork.plctlab.org/api/1.2/patches/1577/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/76fa0c3c-2303-ebdf-a765-ac4731581517@suse.com/","msgid":"<76fa0c3c-2303-ebdf-a765-ac4731581517@suse.com>","list_archive_url":null,"date":"2022-09-30T08:54:18","name":"objcopy: avoid \"shadowing\" of remove() function name","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/76fa0c3c-2303-ebdf-a765-ac4731581517@suse.com/mbox/"},{"id":1579,"url":"https://patchwork.plctlab.org/api/1.2/patches/1579/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930085852.71213-1-nelson@rivosinc.com/","msgid":"<20220930085852.71213-1-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-09-30T08:58:51","name":"[1/2] RISC-V: Output mapping symbols with ISA string.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930085852.71213-1-nelson@rivosinc.com/mbox/"},{"id":1578,"url":"https://patchwork.plctlab.org/api/1.2/patches/1578/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930085852.71213-2-nelson@rivosinc.com/","msgid":"<20220930085852.71213-2-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-09-30T08:58:52","name":"[2/2] RISC-V: Refer mapping symbol to R_RISCV_RELAX for rvc relaxations.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930085852.71213-2-nelson@rivosinc.com/mbox/"},{"id":1581,"url":"https://patchwork.plctlab.org/api/1.2/patches/1581/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930092058.71286-1-nelson@rivosinc.com/","msgid":"<20220930092058.71286-1-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-09-30T09:20:57","name":"[1/2] RISC-V: Output mapping symbols with ISA string.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930092058.71286-1-nelson@rivosinc.com/mbox/"},{"id":1580,"url":"https://patchwork.plctlab.org/api/1.2/patches/1580/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930092058.71286-2-nelson@rivosinc.com/","msgid":"<20220930092058.71286-2-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-09-30T09:20:58","name":"[2/2] RISC-V: Refer mapping symbol to R_RISCV_RELAX for rvc relaxations.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930092058.71286-2-nelson@rivosinc.com/mbox/"},{"id":1582,"url":"https://patchwork.plctlab.org/api/1.2/patches/1582/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5874dd79-0cf5-d65c-7ea2-13adfc799c0f@suse.com/","msgid":"<5874dd79-0cf5-d65c-7ea2-13adfc799c0f@suse.com>","list_archive_url":null,"date":"2022-09-30T09:41:29","name":"RISC-V: fix build after \"Add support for arbitrary immediate encoding formats\"","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5874dd79-0cf5-d65c-7ea2-13adfc799c0f@suse.com/mbox/"},{"id":1583,"url":"https://patchwork.plctlab.org/api/1.2/patches/1583/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/57d8ac2a-5757-3776-9924-99c17ca69938@suse.com/","msgid":"<57d8ac2a-5757-3776-9924-99c17ca69938@suse.com>","list_archive_url":null,"date":"2022-09-30T09:42:08","name":"RISC-V: fallout from \"re-arrange opcode table for consistent alias handling\"","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/57d8ac2a-5757-3776-9924-99c17ca69938@suse.com/mbox/"},{"id":1584,"url":"https://patchwork.plctlab.org/api/1.2/patches/1584/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e76ef8f7-72b9-5103-cb43-9608af01d017@suse.com/","msgid":"","list_archive_url":null,"date":"2022-09-30T09:42:50","name":"RISC-V: don'\''t cast expressions'\'' X_add_number to long in diagnostics","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e76ef8f7-72b9-5103-cb43-9608af01d017@suse.com/mbox/"},{"id":1585,"url":"https://patchwork.plctlab.org/api/1.2/patches/1585/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/61355429-24b3-17d0-ab03-6fa57ee861d5@suse.cz/","msgid":"<61355429-24b3-17d0-ab03-6fa57ee861d5@suse.cz>","list_archive_url":null,"date":"2022-09-30T09:48:52","name":"[RFC] add --enable-zstd-compressed-debug-sections configure option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/61355429-24b3-17d0-ab03-6fa57ee861d5@suse.cz/mbox/"},{"id":1586,"url":"https://patchwork.plctlab.org/api/1.2/patches/1586/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930103919.323690-1-christoph.muellner@vrull.eu/","msgid":"<20220930103919.323690-1-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2022-09-30T10:39:19","name":"RISC-V: Eliminate long-casts of X_add_number in diagnostics","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930103919.323690-1-christoph.muellner@vrull.eu/mbox/"},{"id":1590,"url":"https://patchwork.plctlab.org/api/1.2/patches/1590/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/DM6PR12MB4219C943049C6D883DEA3E55E7569@DM6PR12MB4219.namprd12.prod.outlook.com/","msgid":"","list_archive_url":null,"date":"2022-09-30T11:41:37","name":"[V2] Ignore DWARF debug information for -gsplit-dwarf with dwarf-5.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/DM6PR12MB4219C943049C6D883DEA3E55E7569@DM6PR12MB4219.namprd12.prod.outlook.com/mbox/"},{"id":1591,"url":"https://patchwork.plctlab.org/api/1.2/patches/1591/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c10321f9-d289-ef84-d263-bc278fb3d31b@suse.com/","msgid":"","list_archive_url":null,"date":"2022-09-30T11:59:04","name":"[1/4] RISC-V/gas: drop riscv_subsets static variable","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c10321f9-d289-ef84-d263-bc278fb3d31b@suse.com/mbox/"},{"id":1593,"url":"https://patchwork.plctlab.org/api/1.2/patches/1593/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3244eea0-c18c-e49a-4588-d69423130226@suse.com/","msgid":"<3244eea0-c18c-e49a-4588-d69423130226@suse.com>","list_archive_url":null,"date":"2022-09-30T11:59:23","name":"[2/4] RISC-V/gas: drop stray call to install_insn()","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3244eea0-c18c-e49a-4588-d69423130226@suse.com/mbox/"},{"id":1592,"url":"https://patchwork.plctlab.org/api/1.2/patches/1592/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/385d01fd-7e57-1f3f-1bae-30aa0c313d63@suse.com/","msgid":"<385d01fd-7e57-1f3f-1bae-30aa0c313d63@suse.com>","list_archive_url":null,"date":"2022-09-30T11:59:45","name":"[3/4] RISC-V/gas: don'\''t open-code insn_length()","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/385d01fd-7e57-1f3f-1bae-30aa0c313d63@suse.com/mbox/"},{"id":1594,"url":"https://patchwork.plctlab.org/api/1.2/patches/1594/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f5757acf-7b90-a0e3-5eea-3b97cc226930@suse.com/","msgid":"","list_archive_url":null,"date":"2022-09-30T12:00:12","name":"[4/4] RISC-V/gas: allow generating up to 176-bit instructions with .insn","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f5757acf-7b90-a0e3-5eea-3b97cc226930@suse.com/mbox/"},{"id":1596,"url":"https://patchwork.plctlab.org/api/1.2/patches/1596/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930140503.38233-1-chigot@adacore.com/","msgid":"<20220930140503.38233-1-chigot@adacore.com>","list_archive_url":null,"date":"2022-09-30T14:05:03","name":"ld/testsuite: consistently add board_ldflags when linking with GCC","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930140503.38233-1-chigot@adacore.com/mbox/"}],"public":true,"mbox":"https://patchwork.plctlab.org/bundle/patchwork-bot/binutils-gdb_2022-09/mbox/"}]' + bundle_name_list='binutils-gdb_2022-10 binutils-gdb_2022-09' + [[ binutils-gdb_2022-10 binutils-gdb_2022-09 =~ 2022-10 ]] ++ jq -rc --arg bundle_name binutils-gdb_2022-10 '.[] | select(.name==$bundle_name) | (.id|tostring)' ++ echo '[{"id":6,"url":"https://patchwork.plctlab.org/api/1.2/bundles/6/","web_url":"https://patchwork.plctlab.org/bundle/patchwork-bot/binutils-gdb_2022-10/","project":{"id":2,"url":"https://patchwork.plctlab.org/api/1.2/projects/2/","name":"binutils-gdb","link_name":"binutils-gdb","list_id":"binutils.sourceware.org","list_email":"binutils@sourceware.org","web_url":"https://sourceware.org/mailman/listinfo/binutils","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"name":"binutils-gdb_2022-10","owner":{"id":3,"url":"https://patchwork.plctlab.org/api/1.2/users/3/","username":"patchwork-bot","first_name":"","last_name":"","email":"ouuuleilei@gmail.com"},"patches":[{"id":1592,"url":"https://patchwork.plctlab.org/api/1.2/patches/1592/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/385d01fd-7e57-1f3f-1bae-30aa0c313d63@suse.com/","msgid":"<385d01fd-7e57-1f3f-1bae-30aa0c313d63@suse.com>","list_archive_url":null,"date":"2022-09-30T11:59:45","name":"[3/4] RISC-V/gas: don'\''t open-code insn_length()","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/385d01fd-7e57-1f3f-1bae-30aa0c313d63@suse.com/mbox/"},{"id":1594,"url":"https://patchwork.plctlab.org/api/1.2/patches/1594/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f5757acf-7b90-a0e3-5eea-3b97cc226930@suse.com/","msgid":"","list_archive_url":null,"date":"2022-09-30T12:00:12","name":"[4/4] RISC-V/gas: allow generating up to 176-bit instructions with .insn","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f5757acf-7b90-a0e3-5eea-3b97cc226930@suse.com/mbox/"},{"id":1596,"url":"https://patchwork.plctlab.org/api/1.2/patches/1596/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930140503.38233-1-chigot@adacore.com/","msgid":"<20220930140503.38233-1-chigot@adacore.com>","list_archive_url":null,"date":"2022-09-30T14:05:03","name":"ld/testsuite: consistently add board_ldflags when linking with GCC","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930140503.38233-1-chigot@adacore.com/mbox/"},{"id":1619,"url":"https://patchwork.plctlab.org/api/1.2/patches/1619/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221001014451.532772-1-maskray@google.com/","msgid":"<20221001014451.532772-1-maskray@google.com>","list_archive_url":null,"date":"2022-10-01T01:44:51","name":"gold, dwp: support zstd compressed input debug sections [PR 29641]","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221001014451.532772-1-maskray@google.com/mbox/"},{"id":1620,"url":"https://patchwork.plctlab.org/api/1.2/patches/1620/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221001023846.590825-1-maskray@google.com/","msgid":"<20221001023846.590825-1-maskray@google.com>","list_archive_url":null,"date":"2022-10-01T02:38:46","name":"gold: add --compress-debug-sections=zstd [PR 29641]","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221001023846.590825-1-maskray@google.com/mbox/"},{"id":1623,"url":"https://patchwork.plctlab.org/api/1.2/patches/1623/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b4477c7f666bdeb7f8e998633c7b0cb62310b9ef.1664599545.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-01T04:45:52","name":"[RFC,1/1] RISC-V: Implement common register pair framework","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b4477c7f666bdeb7f8e998633c7b0cb62310b9ef.1664599545.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1625,"url":"https://patchwork.plctlab.org/api/1.2/patches/1625/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/53a265a1f14d17a6f7b106082f610994c5d546e0.1664602025.git.research_trasio@irq.a4lg.com/","msgid":"<53a265a1f14d17a6f7b106082f610994c5d546e0.1664602025.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-01T05:27:31","name":"[RFC,1/1] RISC-V: Implement extension variants","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/53a265a1f14d17a6f7b106082f610994c5d546e0.1664602025.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1626,"url":"https://patchwork.plctlab.org/api/1.2/patches/1626/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8db04962aba9c780f133840a8934353a58f223fe.1664602716.git.research_trasio@irq.a4lg.com/","msgid":"<8db04962aba9c780f133840a8934353a58f223fe.1664602716.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-01T05:39:26","name":"[1/1] RISC-V: Move supervisor instructions after all unprivileged ones","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8db04962aba9c780f133840a8934353a58f223fe.1664602716.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1627,"url":"https://patchwork.plctlab.org/api/1.2/patches/1627/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221001062057.681440-1-maskray@google.com/","msgid":"<20221001062057.681440-1-maskray@google.com>","list_archive_url":null,"date":"2022-10-01T06:20:57","name":"readelf: support zstd compressed debug sections [PR 29640]","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221001062057.681440-1-maskray@google.com/mbox/"},{"id":1631,"url":"https://patchwork.plctlab.org/api/1.2/patches/1631/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/619f112539c0bdecd58e25664f1250a3479a37f5.1664707612.git.aburgess@redhat.com/","msgid":"<619f112539c0bdecd58e25664f1250a3479a37f5.1664707612.git.aburgess@redhat.com>","list_archive_url":null,"date":"2022-10-02T10:47:52","name":"[PATCHv2,2/2] opcodes/arm: add disassembler styling for arm","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/619f112539c0bdecd58e25664f1250a3479a37f5.1664707612.git.aburgess@redhat.com/mbox/"},{"id":1635,"url":"https://patchwork.plctlab.org/api/1.2/patches/1635/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221002185433.gl7dvytfh5wthifx@lug-owl.de/","msgid":"<20221002185433.gl7dvytfh5wthifx@lug-owl.de>","list_archive_url":null,"date":"2022-10-02T18:54:33","name":"diagnostics.h: GCC 13 got -Wself-move, breaks GDB build","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221002185433.gl7dvytfh5wthifx@lug-owl.de/mbox/"},{"id":1637,"url":"https://patchwork.plctlab.org/api/1.2/patches/1637/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003014313.28766-1-mark@harmstone.com/","msgid":"<20221003014313.28766-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-03T01:43:12","name":"[1/2] ld: Add --pdb option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003014313.28766-1-mark@harmstone.com/mbox/"},{"id":1638,"url":"https://patchwork.plctlab.org/api/1.2/patches/1638/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003014313.28766-2-mark@harmstone.com/","msgid":"<20221003014313.28766-2-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-03T01:43:13","name":"[2/2] ld: Add minimal pdb generation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003014313.28766-2-mark@harmstone.com/mbox/"},{"id":1640,"url":"https://patchwork.plctlab.org/api/1.2/patches/1640/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/597ed978-d121-220c-b56b-2ffb94bd091c@suse.cz/","msgid":"<597ed978-d121-220c-b56b-2ffb94bd091c@suse.cz>","list_archive_url":null,"date":"2022-10-03T07:50:38","name":"[1/2] refactor usage of compressed_debug_section_type","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/597ed978-d121-220c-b56b-2ffb94bd091c@suse.cz/mbox/"},{"id":1641,"url":"https://patchwork.plctlab.org/api/1.2/patches/1641/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b8acdd83-f33a-74b8-e21a-23719a0b1a60@suse.cz/","msgid":"","list_archive_url":null,"date":"2022-10-03T07:50:44","name":"[2/2] add --enable-default-compressed-debug-sections-algorithm configure option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b8acdd83-f33a-74b8-e21a-23719a0b1a60@suse.cz/mbox/"},{"id":1642,"url":"https://patchwork.plctlab.org/api/1.2/patches/1642/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003101328.1790113-1-aburgess@redhat.com/","msgid":"<20221003101328.1790113-1-aburgess@redhat.com>","list_archive_url":null,"date":"2022-10-03T10:13:28","name":"opcodes/riscv: style csr names as registers","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003101328.1790113-1-aburgess@redhat.com/mbox/"},{"id":1643,"url":"https://patchwork.plctlab.org/api/1.2/patches/1643/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7ba14fc4472ce97d4f7a4433cad8a571e89f82f4.1664793840.git.research_trasio@irq.a4lg.com/","msgid":"<7ba14fc4472ce97d4f7a4433cad8a571e89f82f4.1664793840.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-03T10:43:59","name":"[v3,1/6] RISC-V: Fix immediates to have \"immediate\" style","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7ba14fc4472ce97d4f7a4433cad8a571e89f82f4.1664793840.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1644,"url":"https://patchwork.plctlab.org/api/1.2/patches/1644/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a498bec37c1fd1dcda57cbf95e5f8cfba09b31d3.1664793840.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-03T10:44:00","name":"[v3,2/6] RISC-V: Fix printf argument types corresponding %x","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a498bec37c1fd1dcda57cbf95e5f8cfba09b31d3.1664793840.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1647,"url":"https://patchwork.plctlab.org/api/1.2/patches/1647/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0002ea716713ace4998a33dde0b81f4f890d10bf.1664793840.git.research_trasio@irq.a4lg.com/","msgid":"<0002ea716713ace4998a33dde0b81f4f890d10bf.1664793840.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-03T10:44:01","name":"[v3,3/6] RISC-V: Optimize riscv_disassemble_data printf","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0002ea716713ace4998a33dde0b81f4f890d10bf.1664793840.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1646,"url":"https://patchwork.plctlab.org/api/1.2/patches/1646/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c65fc3e9aa58965d6768a28c9fd7467fea9897a5.1664793840.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-03T10:44:02","name":"[v3,4/6] RISC-V: Print comma and tabs as the \"text\" style","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c65fc3e9aa58965d6768a28c9fd7467fea9897a5.1664793840.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1648,"url":"https://patchwork.plctlab.org/api/1.2/patches/1648/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5abe1d8a7694417b990e11d8f6cd6789573872e5.1664793840.git.research_trasio@irq.a4lg.com/","msgid":"<5abe1d8a7694417b990e11d8f6cd6789573872e5.1664793840.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-03T10:44:03","name":"[v3,5/6] RISC-V: Fix T-Head immediate types on printing","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5abe1d8a7694417b990e11d8f6cd6789573872e5.1664793840.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1649,"url":"https://patchwork.plctlab.org/api/1.2/patches/1649/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0b68af932117258c908db62cf87c3a15d3cdec41.1664793840.git.research_trasio@irq.a4lg.com/","msgid":"<0b68af932117258c908db62cf87c3a15d3cdec41.1664793840.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-03T10:44:04","name":"[v3,6/6] RISC-V: Print XTheadMemPair literal as \"immediate\"","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0b68af932117258c908db62cf87c3a15d3cdec41.1664793840.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1656,"url":"https://patchwork.plctlab.org/api/1.2/patches/1656/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/87lepxcd6x.fsf@redhat.com/","msgid":"<87lepxcd6x.fsf@redhat.com>","list_archive_url":null,"date":"2022-10-03T12:19:02","name":"Commit: readelf: Do not load section data from offset 0","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/87lepxcd6x.fsf@redhat.com/mbox/"},{"id":1659,"url":"https://patchwork.plctlab.org/api/1.2/patches/1659/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e0d369d419da9c0441f415da7f54352aead8f655.1664707612.git.aburgess@redhat.com/","msgid":"","list_archive_url":null,"date":"2022-10-03T16:37:36","name":"[PATCHv2,1/2] opcodes/arm: use '\''@'\'' consistently for the comment character","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e0d369d419da9c0441f415da7f54352aead8f655.1664707612.git.aburgess@redhat.com/mbox/"},{"id":1660,"url":"https://patchwork.plctlab.org/api/1.2/patches/1660/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003165848.11142-1-palmer@rivosinc.com/","msgid":"<20221003165848.11142-1-palmer@rivosinc.com>","list_archive_url":null,"date":"2022-10-03T16:58:48","name":"gas: NEWS: Mention the T-Head extensions that were recently added","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003165848.11142-1-palmer@rivosinc.com/mbox/"},{"id":1671,"url":"https://patchwork.plctlab.org/api/1.2/patches/1671/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/YzvrMEdkXjIn5Lfz@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-04T08:13:36","name":"Support objcopy changing compression to or from zstd","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/YzvrMEdkXjIn5Lfz@squeak.grove.modra.org/mbox/"},{"id":1673,"url":"https://patchwork.plctlab.org/api/1.2/patches/1673/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0bc857d306bb7c8130e5328dbe6b9ed2fed3ef87.1664873933.git.research_trasio@irq.a4lg.com/","msgid":"<0bc857d306bb7c8130e5328dbe6b9ed2fed3ef87.1664873933.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-04T08:59:07","name":"[1/2] RISC-V: Fix buffer overflow on print_insn_riscv","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0bc857d306bb7c8130e5328dbe6b9ed2fed3ef87.1664873933.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1672,"url":"https://patchwork.plctlab.org/api/1.2/patches/1672/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/89612fe01d902007bf84a7dfb0df5f85d5c166e4.1664873933.git.research_trasio@irq.a4lg.com/","msgid":"<89612fe01d902007bf84a7dfb0df5f85d5c166e4.1664873933.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-04T08:59:08","name":"[2/2] gdb/riscv: Fix buffer overflow on riscv_insn::fetch_instruction","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/89612fe01d902007bf84a7dfb0df5f85d5c166e4.1664873933.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1676,"url":"https://patchwork.plctlab.org/api/1.2/patches/1676/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fc849c94f4adcac1c4ccc5508c7a145a2f13b2a9.1664876744.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-04T09:45:49","name":"[v2,1/2] RISC-V: Fix buffer overflow on print_insn_riscv","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fc849c94f4adcac1c4ccc5508c7a145a2f13b2a9.1664876744.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1677,"url":"https://patchwork.plctlab.org/api/1.2/patches/1677/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4eb6e59ae2e790dbbf2bc92477edd281648d8814.1664876744.git.research_trasio@irq.a4lg.com/","msgid":"<4eb6e59ae2e790dbbf2bc92477edd281648d8814.1664876744.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-04T09:45:50","name":"[v2,2/2] gdb/riscv: Partial support for instructions up to 176-bits","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4eb6e59ae2e790dbbf2bc92477edd281648d8814.1664876744.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1678,"url":"https://patchwork.plctlab.org/api/1.2/patches/1678/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ebf16f9e1f45115d0793952ccb4a94d4233303f9.1664882725.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-04T11:25:56","name":"[v3,1/2] RISC-V: Fix buffer overflow on print_insn_riscv","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ebf16f9e1f45115d0793952ccb4a94d4233303f9.1664882725.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1679,"url":"https://patchwork.plctlab.org/api/1.2/patches/1679/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/83464b09b8649525259c69c853dfa2c9575a204b.1664882725.git.research_trasio@irq.a4lg.com/","msgid":"<83464b09b8649525259c69c853dfa2c9575a204b.1664882725.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-04T11:25:57","name":"[v3,2/2] gdb/riscv: Partial support for instructions up to 176-bit","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/83464b09b8649525259c69c853dfa2c9575a204b.1664882725.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1681,"url":"https://patchwork.plctlab.org/api/1.2/patches/1681/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ffa9c1d7-e8c2-a62b-ef3e-b565c0ffbe5b@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-04T13:56:27","name":"RISC-V: Zicbo{m,p,z} adjustments to riscv_multi_subset_supports_ext()","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ffa9c1d7-e8c2-a62b-ef3e-b565c0ffbe5b@suse.com/mbox/"},{"id":1690,"url":"https://patchwork.plctlab.org/api/1.2/patches/1690/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221004161720.1963953-1-vladimir.mezentsev@oracle.com/","msgid":"<20221004161720.1963953-1-vladimir.mezentsev@oracle.com>","list_archive_url":null,"date":"2022-10-04T16:17:20","name":"gprofng: fix build with --enable-pgo-build=lto","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221004161720.1963953-1-vladimir.mezentsev@oracle.com/mbox/"},{"id":1691,"url":"https://patchwork.plctlab.org/api/1.2/patches/1691/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c0211bc9c57be6c79c6d878ce147f63b657f461d.camel@espressif.com/","msgid":"","list_archive_url":null,"date":"2022-10-04T16:22:05","name":"bfd: xtensa: fix __stop_SECTION literal drop,","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c0211bc9c57be6c79c6d878ce147f63b657f461d.camel@espressif.com/mbox/"},{"id":1702,"url":"https://patchwork.plctlab.org/api/1.2/patches/1702/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5f482299-6c60-b2b3-9abe-f4a55a5a26c5@univ-grenoble-alpes.fr/","msgid":"<5f482299-6c60-b2b3-9abe-f4a55a5a26c5@univ-grenoble-alpes.fr>","list_archive_url":null,"date":"2022-10-04T20:03:20","name":"[RFC] bfd: use bfd_vma for the 64-bit version of put[lb] and get[lb]","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5f482299-6c60-b2b3-9abe-f4a55a5a26c5@univ-grenoble-alpes.fr/mbox/"},{"id":1711,"url":"https://patchwork.plctlab.org/api/1.2/patches/1711/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Yz0Gsxdxe0TePbJT@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-05T04:23:15","name":"PR29647, objdump -S looping","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Yz0Gsxdxe0TePbJT@squeak.grove.modra.org/mbox/"},{"id":1712,"url":"https://patchwork.plctlab.org/api/1.2/patches/1712/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/02d747d2-f57b-0fb5-b893-842b6cc41f2f@suse.com/","msgid":"<02d747d2-f57b-0fb5-b893-842b6cc41f2f@suse.com>","list_archive_url":null,"date":"2022-10-05T07:20:47","name":"[v3,1/7] x86: constify parse_insn()'\''s input","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/02d747d2-f57b-0fb5-b893-842b6cc41f2f@suse.com/mbox/"},{"id":1713,"url":"https://patchwork.plctlab.org/api/1.2/patches/1713/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/925cb740-4e1b-abc4-8526-aaab6faae5e1@suse.com/","msgid":"<925cb740-4e1b-abc4-8526-aaab6faae5e1@suse.com>","list_archive_url":null,"date":"2022-10-05T07:22:19","name":"[v3,2/7] x86: introduce Pass2 insn attribute","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/925cb740-4e1b-abc4-8526-aaab6faae5e1@suse.com/mbox/"},{"id":1714,"url":"https://patchwork.plctlab.org/api/1.2/patches/1714/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e16d3e78-39ca-f715-508f-a4104b8ab9a9@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-05T07:23:51","name":"[v3,3/7] x86: re-work insn/suffix recognition","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e16d3e78-39ca-f715-508f-a4104b8ab9a9@suse.com/mbox/"},{"id":1715,"url":"https://patchwork.plctlab.org/api/1.2/patches/1715/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e4e4b80b-794c-7485-1997-685adab8fb27@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-05T07:24:20","name":"[v3,4/7] x86-64: further re-work insn/suffix recognition to also cover MOVSL","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e4e4b80b-794c-7485-1997-685adab8fb27@suse.com/mbox/"},{"id":1716,"url":"https://patchwork.plctlab.org/api/1.2/patches/1716/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/540678fc-8bff-ec68-c97c-478d2631998c@suse.com/","msgid":"<540678fc-8bff-ec68-c97c-478d2631998c@suse.com>","list_archive_url":null,"date":"2022-10-05T07:24:55","name":"[v3,5/7] ix86: don'\''t recognize/derive Q suffix in the common case","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/540678fc-8bff-ec68-c97c-478d2631998c@suse.com/mbox/"},{"id":1718,"url":"https://patchwork.plctlab.org/api/1.2/patches/1718/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e4692495-7d3d-074d-14f9-364d4a9a998c@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-05T07:25:25","name":"[v3,6/7] x86-64: allow HLE store of accumulator to absolute 32-bit address","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e4692495-7d3d-074d-14f9-364d4a9a998c@suse.com/mbox/"},{"id":1717,"url":"https://patchwork.plctlab.org/api/1.2/patches/1717/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e8014ebd-d16b-17a7-9f34-3700fc164136@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-05T07:25:57","name":"[v3,7/7] x86: move bad-use-of-TLS-reloc check","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e8014ebd-d16b-17a7-9f34-3700fc164136@suse.com/mbox/"},{"id":1719,"url":"https://patchwork.plctlab.org/api/1.2/patches/1719/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1266f001-4511-2662-dba9-14b4d0317c57@suse.com/","msgid":"<1266f001-4511-2662-dba9-14b4d0317c57@suse.com>","list_archive_url":null,"date":"2022-10-05T07:40:50","name":"x86: drop \"regmask\" static variable","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1266f001-4511-2662-dba9-14b4d0317c57@suse.com/mbox/"},{"id":1751,"url":"https://patchwork.plctlab.org/api/1.2/patches/1751/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/af45c5d57c221e43101c2aa38b14f4b4ac12d011.1665031170.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-06T04:40:15","name":"[v2,1/2] RISC-V: Fallback for instructions longer than 64b","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/af45c5d57c221e43101c2aa38b14f4b4ac12d011.1665031170.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1752,"url":"https://patchwork.plctlab.org/api/1.2/patches/1752/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c6e55781245dd3e8e9b8debd6130fc5449dfbd55.1665031170.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-06T04:40:16","name":"[v2,2/2] RISC-V: Improve \"bits undefined\" diagnostics","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c6e55781245dd3e8e9b8debd6130fc5449dfbd55.1665031170.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1776,"url":"https://patchwork.plctlab.org/api/1.2/patches/1776/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d52952119e15357c0e823f8a2398999359588b4d.1665050099.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-06T09:56:30","name":"[v3,1/2] RISC-V: Fallback for instructions longer than 64b","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d52952119e15357c0e823f8a2398999359588b4d.1665050099.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1777,"url":"https://patchwork.plctlab.org/api/1.2/patches/1777/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d907b1997f60ff7823c4a23e281ec9d8ddcbf3f1.1665050099.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-06T09:56:31","name":"[v3,2/2] RISC-V: Improve \"bits undefined\" diagnostics","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d907b1997f60ff7823c4a23e281ec9d8ddcbf3f1.1665050099.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1781,"url":"https://patchwork.plctlab.org/api/1.2/patches/1781/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221006114628.304185-1-chigot@adacore.com/","msgid":"<20221006114628.304185-1-chigot@adacore.com>","list_archive_url":null,"date":"2022-10-06T11:46:28","name":"RISC-V: fix linker message when relaxation deletes bytes","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221006114628.304185-1-chigot@adacore.com/mbox/"},{"id":1801,"url":"https://patchwork.plctlab.org/api/1.2/patches/1801/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Yz+Yhyg7UewC9/kp@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-07T03:09:59","name":"PR29653, objcopy/strip: fuzzed small input file induces large output file","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Yz+Yhyg7UewC9/kp@squeak.grove.modra.org/mbox/"},{"id":1803,"url":"https://patchwork.plctlab.org/api/1.2/patches/1803/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/PH1P110MB16505D9D39EC5B1DE22FE3D5EC5F9@PH1P110MB1650.NAMP110.PROD.OUTLOOK.COM/","msgid":"","list_archive_url":null,"date":"2022-10-07T04:10:07","name":"@CPP_FOR_BUILD@ problem since binutils-2.38","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/PH1P110MB16505D9D39EC5B1DE22FE3D5EC5F9@PH1P110MB1650.NAMP110.PROD.OUTLOOK.COM/mbox/"},{"id":1827,"url":"https://patchwork.plctlab.org/api/1.2/patches/1827/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8e13bce108ac10a0c1dd911e23ec572926f7ae44.1665203374.git.research_trasio@irq.a4lg.com/","msgid":"<8e13bce108ac10a0c1dd911e23ec572926f7ae44.1665203374.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-08T04:29:53","name":"[v2,1/1] RISC-V: Test DWARF register numbers for \"fp\"","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8e13bce108ac10a0c1dd911e23ec572926f7ae44.1665203374.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1828,"url":"https://patchwork.plctlab.org/api/1.2/patches/1828/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0883001b3572e54d3fba264429c7ade2adb66610.1665203441.git.research_trasio@irq.a4lg.com/","msgid":"<0883001b3572e54d3fba264429c7ade2adb66610.1665203441.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-08T04:31:15","name":"[1/1] RISC-V: Move standard hints before all instructions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0883001b3572e54d3fba264429c7ade2adb66610.1665203441.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1829,"url":"https://patchwork.plctlab.org/api/1.2/patches/1829/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/58e16a241d7376fcae2515c6bd5a2b41d275eeba.1665203531.git.research_trasio@irq.a4lg.com/","msgid":"<58e16a241d7376fcae2515c6bd5a2b41d275eeba.1665203531.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-08T04:32:18","name":"[RFC,1/1] RISC-V: Imply '\''Zicsr'\'' from privileged extensions with CSRs","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/58e16a241d7376fcae2515c6bd5a2b41d275eeba.1665203531.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1830,"url":"https://patchwork.plctlab.org/api/1.2/patches/1830/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/cb5076fc96e8f2097779a3abcde843dcdd660031.1665203660.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-08T04:34:23","name":"[1/5] opcodes/riscv-dis.c: Tidying with comments/clarity","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/cb5076fc96e8f2097779a3abcde843dcdd660031.1665203660.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1832,"url":"https://patchwork.plctlab.org/api/1.2/patches/1832/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1f1aa0838bf9c4f10a45fcfe3c682f7efc79d9ae.1665203660.git.research_trasio@irq.a4lg.com/","msgid":"<1f1aa0838bf9c4f10a45fcfe3c682f7efc79d9ae.1665203660.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-08T04:34:24","name":"[2/5] opcodes/riscv-dis.c: Tidying with spacing","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1f1aa0838bf9c4f10a45fcfe3c682f7efc79d9ae.1665203660.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1831,"url":"https://patchwork.plctlab.org/api/1.2/patches/1831/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/740bc5e2d2618d236519b39fedd1a1d7ae4e05da.1665203660.git.research_trasio@irq.a4lg.com/","msgid":"<740bc5e2d2618d236519b39fedd1a1d7ae4e05da.1665203660.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-08T04:34:25","name":"[3/5] opcodes/riscv-dis.c: Use bool type whenever possible","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/740bc5e2d2618d236519b39fedd1a1d7ae4e05da.1665203660.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1833,"url":"https://patchwork.plctlab.org/api/1.2/patches/1833/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6e3a9c235e317f441b4383b3daa68f2051bdc149.1665203660.git.research_trasio@irq.a4lg.com/","msgid":"<6e3a9c235e317f441b4383b3daa68f2051bdc149.1665203660.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-08T04:34:26","name":"[4/5] opcodes/riscv-dis.c: Make XLEN variable static","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6e3a9c235e317f441b4383b3daa68f2051bdc149.1665203660.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1834,"url":"https://patchwork.plctlab.org/api/1.2/patches/1834/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ad929233a62d887495122721340b2f9c80392963.1665203660.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-08T04:34:27","name":"[5/5] opcodes/riscv-dis.c: Remove last_map_state","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ad929233a62d887495122721340b2f9c80392963.1665203660.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1836,"url":"https://patchwork.plctlab.org/api/1.2/patches/1836/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d07e2b6f36ea2fd5830924a9bfeda941b774b687.1665290422.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-09T05:09:22","name":"RISC-V: Move certain arrays to riscv-opc.c","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d07e2b6f36ea2fd5830924a9bfeda941b774b687.1665290422.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1844,"url":"https://patchwork.plctlab.org/api/1.2/patches/1844/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010004623.16582-1-mark@harmstone.com/","msgid":"<20221010004623.16582-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-10T00:46:22","name":"[v2,1/2] ld: Add --pdb option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010004623.16582-1-mark@harmstone.com/mbox/"},{"id":1845,"url":"https://patchwork.plctlab.org/api/1.2/patches/1845/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010004623.16582-2-mark@harmstone.com/","msgid":"<20221010004623.16582-2-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-10T00:46:23","name":"[v2,2/2] ld: Add minimal pdb generation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010004623.16582-2-mark@harmstone.com/mbox/"},{"id":1890,"url":"https://patchwork.plctlab.org/api/1.2/patches/1890/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010200433.414320-1-vladimir.mezentsev@oracle.com/","msgid":"<20221010200433.414320-1-vladimir.mezentsev@oracle.com>","list_archive_url":null,"date":"2022-10-10T20:04:33","name":"gprofng: run tests without installation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010200433.414320-1-vladimir.mezentsev@oracle.com/mbox/"},{"id":1893,"url":"https://patchwork.plctlab.org/api/1.2/patches/1893/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010230426.719238-1-vladimir.mezentsev@oracle.com/","msgid":"<20221010230426.719238-1-vladimir.mezentsev@oracle.com>","list_archive_url":null,"date":"2022-10-10T23:04:26","name":"[2/2] gprofng: use the --libdir path to find libraries","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010230426.719238-1-vladimir.mezentsev@oracle.com/mbox/"},{"id":1894,"url":"https://patchwork.plctlab.org/api/1.2/patches/1894/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010235155.842469-1-vladimir.mezentsev@oracle.com/","msgid":"<20221010235155.842469-1-vladimir.mezentsev@oracle.com>","list_archive_url":null,"date":"2022-10-10T23:51:55","name":"[3/3] gprofng: no need to build version.texi","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010235155.842469-1-vladimir.mezentsev@oracle.com/mbox/"},{"id":1895,"url":"https://patchwork.plctlab.org/api/1.2/patches/1895/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011003702.4287-1-mark@harmstone.com/","msgid":"<20221011003702.4287-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-11T00:37:01","name":"[v3,1/2] ld: Add --pdb option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011003702.4287-1-mark@harmstone.com/mbox/"},{"id":1897,"url":"https://patchwork.plctlab.org/api/1.2/patches/1897/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011003702.4287-2-mark@harmstone.com/","msgid":"<20221011003702.4287-2-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-11T00:37:02","name":"[v3,2/2] ld: Add minimal pdb generation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011003702.4287-2-mark@harmstone.com/mbox/"},{"id":1928,"url":"https://patchwork.plctlab.org/api/1.2/patches/1928/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011175332.17156-1-mark@harmstone.com/","msgid":"<20221011175332.17156-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-11T17:53:31","name":"[v4,1/2] ld: Add --pdb option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011175332.17156-1-mark@harmstone.com/mbox/"},{"id":1929,"url":"https://patchwork.plctlab.org/api/1.2/patches/1929/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011175332.17156-2-mark@harmstone.com/","msgid":"<20221011175332.17156-2-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-11T17:53:32","name":"[v4,2/2] ld: Add minimal pdb generation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011175332.17156-2-mark@harmstone.com/mbox/"},{"id":1941,"url":"https://patchwork.plctlab.org/api/1.2/patches/1941/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221012031005.237446-1-simon.marchi@polymtl.ca/","msgid":"<20221012031005.237446-1-simon.marchi@polymtl.ca>","list_archive_url":null,"date":"2022-10-12T03:10:05","name":"[pushed] Re-apply \"Pass PKG_CONFIG_PATH down from top-level Makefile\"","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221012031005.237446-1-simon.marchi@polymtl.ca/mbox/"},{"id":1976,"url":"https://patchwork.plctlab.org/api/1.2/patches/1976/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1216a3f8-2273-8681-f528-9493a66891f0@suse.com/","msgid":"<1216a3f8-2273-8681-f528-9493a66891f0@suse.com>","list_archive_url":null,"date":"2022-10-13T08:16:49","name":"[v4,1/8] x86: constify parse_insn()'\''s input","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1216a3f8-2273-8681-f528-9493a66891f0@suse.com/mbox/"},{"id":1977,"url":"https://patchwork.plctlab.org/api/1.2/patches/1977/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/11599bbe-c779-aa9f-4d5d-c2243f0e69dc@suse.com/","msgid":"<11599bbe-c779-aa9f-4d5d-c2243f0e69dc@suse.com>","list_archive_url":null,"date":"2022-10-13T08:17:17","name":"[v4,2/8] x86: introduce Pass2 insn attribute","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/11599bbe-c779-aa9f-4d5d-c2243f0e69dc@suse.com/mbox/"},{"id":1978,"url":"https://patchwork.plctlab.org/api/1.2/patches/1978/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/357273a3-060c-23db-72da-3fc9d1be3d2a@suse.com/","msgid":"<357273a3-060c-23db-72da-3fc9d1be3d2a@suse.com>","list_archive_url":null,"date":"2022-10-13T08:18:09","name":"[v4,3/8] x86: re-work insn/suffix recognition","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/357273a3-060c-23db-72da-3fc9d1be3d2a@suse.com/mbox/"},{"id":1979,"url":"https://patchwork.plctlab.org/api/1.2/patches/1979/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0ec0587f-6a7b-45b6-8346-e5d774e73636@suse.com/","msgid":"<0ec0587f-6a7b-45b6-8346-e5d774e73636@suse.com>","list_archive_url":null,"date":"2022-10-13T08:18:39","name":"[v4,4/8] x86-64: further re-work insn/suffix recognition to also cover MOVSL","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0ec0587f-6a7b-45b6-8346-e5d774e73636@suse.com/mbox/"},{"id":1980,"url":"https://patchwork.plctlab.org/api/1.2/patches/1980/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fb617d0b-8759-3169-5a65-1178b7fef3d7@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-13T08:19:34","name":"[v4,5/8] ix86: don'\''t recognize/derive Q suffix in the common case","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fb617d0b-8759-3169-5a65-1178b7fef3d7@suse.com/mbox/"},{"id":1981,"url":"https://patchwork.plctlab.org/api/1.2/patches/1981/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1df3bd01-99c5-f56c-d937-970edd42b2b8@suse.com/","msgid":"<1df3bd01-99c5-f56c-d937-970edd42b2b8@suse.com>","list_archive_url":null,"date":"2022-10-13T08:20:14","name":"[v4,6/8] x86-64: allow HLE store of accumulator to absolute 32-bit address","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1df3bd01-99c5-f56c-d937-970edd42b2b8@suse.com/mbox/"},{"id":1982,"url":"https://patchwork.plctlab.org/api/1.2/patches/1982/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8486a218-39ec-16b2-5c6c-5037196b93cf@suse.com/","msgid":"<8486a218-39ec-16b2-5c6c-5037196b93cf@suse.com>","list_archive_url":null,"date":"2022-10-13T08:21:00","name":"[v4,7/8] x86: move bad-use-of-TLS-reloc check","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8486a218-39ec-16b2-5c6c-5037196b93cf@suse.com/mbox/"},{"id":1983,"url":"https://patchwork.plctlab.org/api/1.2/patches/1983/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7d82692d-93df-fbee-9efb-2f44e8a91df3@suse.com/","msgid":"<7d82692d-93df-fbee-9efb-2f44e8a91df3@suse.com>","list_archive_url":null,"date":"2022-10-13T08:22:00","name":"[v4,8/8] x86: drop (now) stray IsString","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7d82692d-93df-fbee-9efb-2f44e8a91df3@suse.com/mbox/"},{"id":2013,"url":"https://patchwork.plctlab.org/api/1.2/patches/2013/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8ab93d7a617ad480dd786210f46db0e5aa07d1ac.1665655719.git.research_trasio@irq.a4lg.com/","msgid":"<8ab93d7a617ad480dd786210f46db0e5aa07d1ac.1665655719.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-13T10:11:41","name":"include: Declare getopt function on old GNU libc","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8ab93d7a617ad480dd786210f46db0e5aa07d1ac.1665655719.git.research_trasio@irq.a4lg.com/mbox/"},{"id":2352,"url":"https://patchwork.plctlab.org/api/1.2/patches/2352/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221013201332.2747246-1-maskray@google.com/","msgid":"<20221013201332.2747246-1-maskray@google.com>","list_archive_url":null,"date":"2022-10-13T20:13:32","name":"ld: Add --undefined-version","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221013201332.2747246-1-maskray@google.com/mbox/"},{"id":2532,"url":"https://patchwork.plctlab.org/api/1.2/patches/2532/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014063520.1428330-2-zengxiao@eswincomputing.com/","msgid":"<20221014063520.1428330-2-zengxiao@eswincomputing.com>","list_archive_url":null,"date":"2022-10-14T06:35:20","name":"[1/1] RISC-V: Make R_RISCV_SUB6 conforms to riscv abi standard","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014063520.1428330-2-zengxiao@eswincomputing.com/mbox/"},{"id":2560,"url":"https://patchwork.plctlab.org/api/1.2/patches/2560/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/027ae69a-636b-6757-297a-eec42936401e@linaro.org/","msgid":"<027ae69a-636b-6757-297a-eec42936401e@linaro.org>","list_archive_url":null,"date":"2022-10-14T07:58:22","name":"[v3] aarch64-pe support for LD, GAS and BFD","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/027ae69a-636b-6757-297a-eec42936401e@linaro.org/mbox/"},{"id":2602,"url":"https://patchwork.plctlab.org/api/1.2/patches/2602/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-2-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-2-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:39","name":"[01/10] Support Intel AVX-IFMA","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-2-haochen.jiang@intel.com/mbox/"},{"id":2608,"url":"https://patchwork.plctlab.org/api/1.2/patches/2608/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-3-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-3-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:40","name":"[02/10] Support Intel AVX-VNNI-INT8","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-3-haochen.jiang@intel.com/mbox/"},{"id":2611,"url":"https://patchwork.plctlab.org/api/1.2/patches/2611/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-4-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-4-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:41","name":"[03/10] Support Intel AVX-NE-CONVERT","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-4-haochen.jiang@intel.com/mbox/"},{"id":2610,"url":"https://patchwork.plctlab.org/api/1.2/patches/2610/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-5-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-5-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:42","name":"[04/10] Support Intel CMPccXADD","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-5-haochen.jiang@intel.com/mbox/"},{"id":2601,"url":"https://patchwork.plctlab.org/api/1.2/patches/2601/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-6-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-6-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:43","name":"[05/10] Add handler for more i386_cpu_flags","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-6-haochen.jiang@intel.com/mbox/"},{"id":2606,"url":"https://patchwork.plctlab.org/api/1.2/patches/2606/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-7-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-7-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:44","name":"[06/10] Support Intel RAO-INT","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-7-haochen.jiang@intel.com/mbox/"},{"id":2609,"url":"https://patchwork.plctlab.org/api/1.2/patches/2609/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-8-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-8-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:45","name":"[07/10] Support Intel WRMSRNS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-8-haochen.jiang@intel.com/mbox/"},{"id":2605,"url":"https://patchwork.plctlab.org/api/1.2/patches/2605/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-9-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-9-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:46","name":"[08/10] Support Intel MSRLIST","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-9-haochen.jiang@intel.com/mbox/"},{"id":2607,"url":"https://patchwork.plctlab.org/api/1.2/patches/2607/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-10-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-10-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:47","name":"[09/10] Support Intel AMX-FP16","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-10-haochen.jiang@intel.com/mbox/"},{"id":2604,"url":"https://patchwork.plctlab.org/api/1.2/patches/2604/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-11-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-11-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:48","name":"[10/10] Support Intel PREFETCHI","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-11-haochen.jiang@intel.com/mbox/"},{"id":2643,"url":"https://patchwork.plctlab.org/api/1.2/patches/2643/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7bac66be-535e-9051-d674-f2f5ba180e17@suse.com/","msgid":"<7bac66be-535e-9051-d674-f2f5ba180e17@suse.com>","list_archive_url":null,"date":"2022-10-14T10:22:34","name":"x86: fold AVX512-VNNI disassembler entries with AVX-VNNI ones","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7bac66be-535e-9051-d674-f2f5ba180e17@suse.com/mbox/"},{"id":2654,"url":"https://patchwork.plctlab.org/api/1.2/patches/2654/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0lIo5+ncY/MqBEq@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-14T11:31:47","name":"PR29677, Field `the_bfd` of `asymbol` is uninitialised","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0lIo5+ncY/MqBEq@squeak.grove.modra.org/mbox/"},{"id":2656,"url":"https://patchwork.plctlab.org/api/1.2/patches/2656/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0lJksn49ZpABY89@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-14T11:35:46","name":"e200 LSP support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0lJksn49ZpABY89@squeak.grove.modra.org/mbox/"},{"id":2657,"url":"https://patchwork.plctlab.org/api/1.2/patches/2657/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0lJxxYoeD5iDYAD@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-14T11:36:39","name":"PowerPC SPE disassembly and tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0lJxxYoeD5iDYAD@squeak.grove.modra.org/mbox/"},{"id":2695,"url":"https://patchwork.plctlab.org/api/1.2/patches/2695/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/DM6PR12MB4219611F6CC2A0702884A602E7249@DM6PR12MB4219.namprd12.prod.outlook.com/","msgid":"","list_archive_url":null,"date":"2022-10-14T13:29:40","name":"Binutils: Adding new testcase for addr2line.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/DM6PR12MB4219611F6CC2A0702884A602E7249@DM6PR12MB4219.namprd12.prod.outlook.com/mbox/"},{"id":2700,"url":"https://patchwork.plctlab.org/api/1.2/patches/2700/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9fd2c88d-98b2-99a4-419f-c7235b2cf960@suse.com/","msgid":"<9fd2c88d-98b2-99a4-419f-c7235b2cf960@suse.com>","list_archive_url":null,"date":"2022-10-14T14:11:35","name":"x86: properly decode EVEX.W for AVX512_4{FMAPS,VNNIW} insns","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9fd2c88d-98b2-99a4-419f-c7235b2cf960@suse.com/mbox/"},{"id":2981,"url":"https://patchwork.plctlab.org/api/1.2/patches/2981/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0uLzalqjm4C87GN@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-16T04:42:53","name":"PowerPC se_rfmci and VLE, SPE2 and LSP insns with -many","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0uLzalqjm4C87GN@squeak.grove.modra.org/mbox/"},{"id":3152,"url":"https://patchwork.plctlab.org/api/1.2/patches/3152/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221016232419.1135-1-mark@harmstone.com/","msgid":"<20221016232419.1135-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-16T23:24:18","name":"[v5,1/2] ld: Add --pdb option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221016232419.1135-1-mark@harmstone.com/mbox/"},{"id":3151,"url":"https://patchwork.plctlab.org/api/1.2/patches/3151/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221016232419.1135-2-mark@harmstone.com/","msgid":"<20221016232419.1135-2-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-16T23:24:19","name":"[v5,2/2] ld: Add minimal pdb generation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221016232419.1135-2-mark@harmstone.com/mbox/"},{"id":3258,"url":"https://patchwork.plctlab.org/api/1.2/patches/3258/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/19c08747-fa5b-1e67-3dd2-c891a2c0c1fa@suse.com/","msgid":"<19c08747-fa5b-1e67-3dd2-c891a2c0c1fa@suse.com>","list_archive_url":null,"date":"2022-10-17T07:44:51","name":"x86: correct CPU_AMX_{BF16,INT8}_FLAGS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/19c08747-fa5b-1e67-3dd2-c891a2c0c1fa@suse.com/mbox/"},{"id":3272,"url":"https://patchwork.plctlab.org/api/1.2/patches/3272/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/85dd526c-d3a7-72dc-5444-ed5573eebec1@suse.com/","msgid":"<85dd526c-d3a7-72dc-5444-ed5573eebec1@suse.com>","list_archive_url":null,"date":"2022-10-17T08:30:12","name":"x86: generalize gas documentation for disabling of ISA extensions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/85dd526c-d3a7-72dc-5444-ed5573eebec1@suse.com/mbox/"},{"id":3759,"url":"https://patchwork.plctlab.org/api/1.2/patches/3759/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-2-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-2-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:15:58","name":"[V2,01/15] sframe.h: Add SFrame format definition","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-2-indu.bhagat@oracle.com/mbox/"},{"id":3762,"url":"https://patchwork.plctlab.org/api/1.2/patches/3762/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-3-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-3-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:15:59","name":"[V2,02/15] gas: add new command line option --gsframe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-3-indu.bhagat@oracle.com/mbox/"},{"id":3761,"url":"https://patchwork.plctlab.org/api/1.2/patches/3761/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-4-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-4-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:00","name":"[V2,03/15] gas: generate .sframe from CFI directives","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-4-indu.bhagat@oracle.com/mbox/"},{"id":3760,"url":"https://patchwork.plctlab.org/api/1.2/patches/3760/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-5-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-5-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:01","name":"[V2,04/15] gas: testsuite: add new tests for SFrame unwind info","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-5-indu.bhagat@oracle.com/mbox/"},{"id":3764,"url":"https://patchwork.plctlab.org/api/1.2/patches/3764/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-6-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-6-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:02","name":"[V2,05/15] libsframe: add the SFrame library","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-6-indu.bhagat@oracle.com/mbox/"},{"id":3766,"url":"https://patchwork.plctlab.org/api/1.2/patches/3766/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-7-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-7-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:03","name":"[V2,06/15] bfd: linker: merge .sframe sections","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-7-indu.bhagat@oracle.com/mbox/"},{"id":3763,"url":"https://patchwork.plctlab.org/api/1.2/patches/3763/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-8-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-8-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:04","name":"[V2,07/15] readelf/objdump: support for SFrame section","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-8-indu.bhagat@oracle.com/mbox/"},{"id":3765,"url":"https://patchwork.plctlab.org/api/1.2/patches/3765/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-9-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-9-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:05","name":"[V2,08/15] unwinder: generate backtrace using SFrame format","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-9-indu.bhagat@oracle.com/mbox/"},{"id":3770,"url":"https://patchwork.plctlab.org/api/1.2/patches/3770/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-10-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-10-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:06","name":"[V2,09/15] unwinder: Add SFrame unwinder tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-10-indu.bhagat@oracle.com/mbox/"},{"id":3769,"url":"https://patchwork.plctlab.org/api/1.2/patches/3769/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-11-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-11-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:07","name":"[V2,10/15] gdb: sim: buildsystem changes to accommodate libsframe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-11-indu.bhagat@oracle.com/mbox/"},{"id":3771,"url":"https://patchwork.plctlab.org/api/1.2/patches/3771/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-12-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-12-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:08","name":"[V2,11/15] libctf: add libsframe to LDFLAGS and LIBS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-12-indu.bhagat@oracle.com/mbox/"},{"id":3768,"url":"https://patchwork.plctlab.org/api/1.2/patches/3768/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-13-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-13-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:09","name":"[V2,12/15] src-release.sh: Add libsframe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-13-indu.bhagat@oracle.com/mbox/"},{"id":3767,"url":"https://patchwork.plctlab.org/api/1.2/patches/3767/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-14-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-14-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:10","name":"[V2,13/15] binutils/NEWS: add text for SFrame support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-14-indu.bhagat@oracle.com/mbox/"},{"id":3772,"url":"https://patchwork.plctlab.org/api/1.2/patches/3772/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-15-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-15-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:11","name":"[V2,14/15] gas/NEWS: add text about new command line option and SFrame support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-15-indu.bhagat@oracle.com/mbox/"},{"id":3773,"url":"https://patchwork.plctlab.org/api/1.2/patches/3773/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-16-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-16-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:12","name":"[V2,15/15] doc: add SFrame spec file","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-16-indu.bhagat@oracle.com/mbox/"},{"id":3999,"url":"https://patchwork.plctlab.org/api/1.2/patches/3999/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221018081205.17880-1-krebbel@linux.ibm.com/","msgid":"<20221018081205.17880-1-krebbel@linux.ibm.com>","list_archive_url":null,"date":"2022-10-18T08:12:05","name":"[1/1] IBM zSystems: Issue error for *DBL relocs on misaligned symbols","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221018081205.17880-1-krebbel@linux.ibm.com/mbox/"},{"id":4141,"url":"https://patchwork.plctlab.org/api/1.2/patches/4141/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/baffaf673f17692b7bcbd604b31800b189988596.camel@espressif.com/","msgid":"","list_archive_url":null,"date":"2022-10-18T12:12:07","name":"xtensa: use definitions from xtensa-config.h","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/baffaf673f17692b7bcbd604b31800b189988596.camel@espressif.com/mbox/"},{"id":4272,"url":"https://patchwork.plctlab.org/api/1.2/patches/4272/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221018174914.470062-1-hjl.tools@gmail.com/","msgid":"<20221018174914.470062-1-hjl.tools@gmail.com>","list_archive_url":null,"date":"2022-10-18T17:49:14","name":"x86: Disable AVX-VNNI when disabling AVX2","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221018174914.470062-1-hjl.tools@gmail.com/mbox/"},{"id":4998,"url":"https://patchwork.plctlab.org/api/1.2/patches/4998/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c2f76e95-09f6-1d92-7ef4-38a3c2955fcd@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-19T09:52:46","name":"x86: re-work AVX-VNNI support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c2f76e95-09f6-1d92-7ef4-38a3c2955fcd@suse.com/mbox/"},{"id":5276,"url":"https://patchwork.plctlab.org/api/1.2/patches/5276/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0/lLtlKqqsmAx0s@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-19T11:53:18","name":"Fix addr2line test for ppc64 elfv1 and mingw","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0/lLtlKqqsmAx0s@squeak.grove.modra.org/mbox/"},{"id":5424,"url":"https://patchwork.plctlab.org/api/1.2/patches/5424/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/07bfebbf3843b47e13d82d4fa16eb14fec942ef7.1666184962.git.research_trasio@irq.a4lg.com/","msgid":"<07bfebbf3843b47e13d82d4fa16eb14fec942ef7.1666184962.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:09:54","name":"binutils: Remove unused substitution PROGRAM","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/07bfebbf3843b47e13d82d4fa16eb14fec942ef7.1666184962.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5433,"url":"https://patchwork.plctlab.org/api/1.2/patches/5433/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2fa7ff719223232402e82a9c91331aea22ace1bb.1666185116.git.research_trasio@irq.a4lg.com/","msgid":"<2fa7ff719223232402e82a9c91331aea22ace1bb.1666185116.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:11:55","name":"[v2,1/8] RISC-V: Add a space at the end of pinfo","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/2fa7ff719223232402e82a9c91331aea22ace1bb.1666185116.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5435,"url":"https://patchwork.plctlab.org/api/1.2/patches/5435/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1b30cce5db2cce3b8edca42ab5da114d0b8c9e93.1666185116.git.research_trasio@irq.a4lg.com/","msgid":"<1b30cce5db2cce3b8edca42ab5da114d0b8c9e93.1666185116.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:11:56","name":"[v2,2/8] RISC-V: Fix obvious misalignments ('\''Zbb'\''/'\''Zba'\'')","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1b30cce5db2cce3b8edca42ab5da114d0b8c9e93.1666185116.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5437,"url":"https://patchwork.plctlab.org/api/1.2/patches/5437/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6b0857aa1a2d15ca1cf00b4dcaae0032efbb88ff.1666185116.git.research_trasio@irq.a4lg.com/","msgid":"<6b0857aa1a2d15ca1cf00b4dcaae0032efbb88ff.1666185116.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:11:57","name":"[v2,3/8] RISC-V: Remove spaces in opcode entries","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6b0857aa1a2d15ca1cf00b4dcaae0032efbb88ff.1666185116.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5436,"url":"https://patchwork.plctlab.org/api/1.2/patches/5436/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/889d956caac0f2e95543a14afaeed97188ce384c.1666185116.git.research_trasio@irq.a4lg.com/","msgid":"<889d956caac0f2e95543a14afaeed97188ce384c.1666185116.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:11:58","name":"[v2,4/8] RISC-V: Remove unused instruction macros","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/889d956caac0f2e95543a14afaeed97188ce384c.1666185116.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5440,"url":"https://patchwork.plctlab.org/api/1.2/patches/5440/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8f226ee20d8a5ef6ad7b6c4408b44794a99d542a.1666185116.git.research_trasio@irq.a4lg.com/","msgid":"<8f226ee20d8a5ef6ad7b6c4408b44794a99d542a.1666185116.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:11:59","name":"[v2,5/8] RISC-V: Complete tidying up with SCALL and SBREAK","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8f226ee20d8a5ef6ad7b6c4408b44794a99d542a.1666185116.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5442,"url":"https://patchwork.plctlab.org/api/1.2/patches/5442/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4070184c454a05a39adf0790951e5856e6b2ecb6.1666185116.git.research_trasio@irq.a4lg.com/","msgid":"<4070184c454a05a39adf0790951e5856e6b2ecb6.1666185116.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:12:00","name":"[v2,6/8] RISC-V: Tidying up with fmv.w.x and fmv.x.w","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4070184c454a05a39adf0790951e5856e6b2ecb6.1666185116.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5438,"url":"https://patchwork.plctlab.org/api/1.2/patches/5438/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c1ccda3e7c8fb297eda46dab3936d5c5977178fc.1666185116.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-19T13:12:01","name":"[v2,7/8] RISC-V: Make alias instructions aliases","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c1ccda3e7c8fb297eda46dab3936d5c5977178fc.1666185116.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5441,"url":"https://patchwork.plctlab.org/api/1.2/patches/5441/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/413cfca82c7e8d8a2e977dfda9135903c9cb7c57.1666185116.git.research_trasio@irq.a4lg.com/","msgid":"<413cfca82c7e8d8a2e977dfda9135903c9cb7c57.1666185116.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:12:02","name":"[v2,8/8] RISC-V: Use defined mask and match values","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/413cfca82c7e8d8a2e977dfda9135903c9cb7c57.1666185116.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5439,"url":"https://patchwork.plctlab.org/api/1.2/patches/5439/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/345c5c3b3a53eab04a1e6e91197de2642095c94f.1666185237.git.research_trasio@irq.a4lg.com/","msgid":"<345c5c3b3a53eab04a1e6e91197de2642095c94f.1666185237.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-19T13:14:01","name":"RISC-V: Remove RV32EF conflict","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/345c5c3b3a53eab04a1e6e91197de2642095c94f.1666185237.git.research_trasio@irq.a4lg.com/mbox/"},{"id":5616,"url":"https://patchwork.plctlab.org/api/1.2/patches/5616/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019145608.45213-5-haochen.jiang@intel.com/","msgid":"<20221019145608.45213-5-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T14:56:02","name":"[04/10] Support Intel CMPccXADD","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019145608.45213-5-haochen.jiang@intel.com/mbox/"},{"id":5614,"url":"https://patchwork.plctlab.org/api/1.2/patches/5614/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019145608.45213-6-haochen.jiang@intel.com/","msgid":"<20221019145608.45213-6-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T14:56:03","name":"[05/10] Add handler for more i386_cpu_flags","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019145608.45213-6-haochen.jiang@intel.com/mbox/"},{"id":5672,"url":"https://patchwork.plctlab.org/api/1.2/patches/5672/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-2-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-2-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:25","name":"[01/10] Support Intel AVX-IFMA","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-2-haochen.jiang@intel.com/mbox/"},{"id":5691,"url":"https://patchwork.plctlab.org/api/1.2/patches/5691/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-3-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-3-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:26","name":"[02/10] Support Intel AVX-VNNI-INT8","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-3-haochen.jiang@intel.com/mbox/"},{"id":5690,"url":"https://patchwork.plctlab.org/api/1.2/patches/5690/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-4-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-4-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:27","name":"[03/10] Support Intel AVX-NE-CONVERT","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-4-haochen.jiang@intel.com/mbox/"},{"id":5689,"url":"https://patchwork.plctlab.org/api/1.2/patches/5689/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-5-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-5-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:28","name":"[04/10] Support Intel CMPccXADD","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-5-haochen.jiang@intel.com/mbox/"},{"id":5676,"url":"https://patchwork.plctlab.org/api/1.2/patches/5676/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-6-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-6-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:29","name":"[05/10] Add handler for more i386_cpu_flags","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-6-haochen.jiang@intel.com/mbox/"},{"id":5677,"url":"https://patchwork.plctlab.org/api/1.2/patches/5677/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-7-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-7-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:30","name":"[06/10] Support Intel RAO-INT","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-7-haochen.jiang@intel.com/mbox/"},{"id":5681,"url":"https://patchwork.plctlab.org/api/1.2/patches/5681/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-8-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-8-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:31","name":"[07/10] Support Intel WRMSRNS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-8-haochen.jiang@intel.com/mbox/"},{"id":5682,"url":"https://patchwork.plctlab.org/api/1.2/patches/5682/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-9-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-9-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:32","name":"[08/10] Support Intel MSRLIST","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-9-haochen.jiang@intel.com/mbox/"},{"id":5673,"url":"https://patchwork.plctlab.org/api/1.2/patches/5673/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-10-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-10-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:33","name":"[09/10] Support Intel AMX-FP16","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-10-haochen.jiang@intel.com/mbox/"},{"id":5686,"url":"https://patchwork.plctlab.org/api/1.2/patches/5686/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-11-haochen.jiang@intel.com/","msgid":"<20221019151534.45521-11-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-19T15:15:34","name":"[10/10] Support Intel PREFETCHI","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221019151534.45521-11-haochen.jiang@intel.com/mbox/"}],"public":true,"mbox":"https://patchwork.plctlab.org/bundle/patchwork-bot/binutils-gdb_2022-10/mbox/"},{"id":7,"url":"https://patchwork.plctlab.org/api/1.2/bundles/7/","web_url":"https://patchwork.plctlab.org/bundle/patchwork-bot/binutils-gdb_2022-09/","project":{"id":2,"url":"https://patchwork.plctlab.org/api/1.2/projects/2/","name":"binutils-gdb","link_name":"binutils-gdb","list_id":"binutils.sourceware.org","list_email":"binutils@sourceware.org","web_url":"https://sourceware.org/mailman/listinfo/binutils","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"name":"binutils-gdb_2022-09","owner":{"id":3,"url":"https://patchwork.plctlab.org/api/1.2/users/3/","username":"patchwork-bot","first_name":"","last_name":"","email":"ouuuleilei@gmail.com"},"patches":[{"id":1573,"url":"https://patchwork.plctlab.org/api/1.2/patches/1573/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930073211.2634-1-jiawei@iscas.ac.cn/","msgid":"<20220930073211.2634-1-jiawei@iscas.ac.cn>","list_archive_url":null,"date":"2022-09-30T07:32:11","name":"[V2] RISC-V: Add Smepmp CSR '\''mseccfg'\'' define and testcases.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930073211.2634-1-jiawei@iscas.ac.cn/mbox/"},{"id":1577,"url":"https://patchwork.plctlab.org/api/1.2/patches/1577/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/76fa0c3c-2303-ebdf-a765-ac4731581517@suse.com/","msgid":"<76fa0c3c-2303-ebdf-a765-ac4731581517@suse.com>","list_archive_url":null,"date":"2022-09-30T08:54:18","name":"objcopy: avoid \"shadowing\" of remove() function name","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/76fa0c3c-2303-ebdf-a765-ac4731581517@suse.com/mbox/"},{"id":1579,"url":"https://patchwork.plctlab.org/api/1.2/patches/1579/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930085852.71213-1-nelson@rivosinc.com/","msgid":"<20220930085852.71213-1-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-09-30T08:58:51","name":"[1/2] RISC-V: Output mapping symbols with ISA string.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930085852.71213-1-nelson@rivosinc.com/mbox/"},{"id":1578,"url":"https://patchwork.plctlab.org/api/1.2/patches/1578/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930085852.71213-2-nelson@rivosinc.com/","msgid":"<20220930085852.71213-2-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-09-30T08:58:52","name":"[2/2] RISC-V: Refer mapping symbol to R_RISCV_RELAX for rvc relaxations.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930085852.71213-2-nelson@rivosinc.com/mbox/"},{"id":1581,"url":"https://patchwork.plctlab.org/api/1.2/patches/1581/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930092058.71286-1-nelson@rivosinc.com/","msgid":"<20220930092058.71286-1-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-09-30T09:20:57","name":"[1/2] RISC-V: Output mapping symbols with ISA string.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930092058.71286-1-nelson@rivosinc.com/mbox/"},{"id":1580,"url":"https://patchwork.plctlab.org/api/1.2/patches/1580/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930092058.71286-2-nelson@rivosinc.com/","msgid":"<20220930092058.71286-2-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-09-30T09:20:58","name":"[2/2] RISC-V: Refer mapping symbol to R_RISCV_RELAX for rvc relaxations.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930092058.71286-2-nelson@rivosinc.com/mbox/"},{"id":1582,"url":"https://patchwork.plctlab.org/api/1.2/patches/1582/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5874dd79-0cf5-d65c-7ea2-13adfc799c0f@suse.com/","msgid":"<5874dd79-0cf5-d65c-7ea2-13adfc799c0f@suse.com>","list_archive_url":null,"date":"2022-09-30T09:41:29","name":"RISC-V: fix build after \"Add support for arbitrary immediate encoding formats\"","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5874dd79-0cf5-d65c-7ea2-13adfc799c0f@suse.com/mbox/"},{"id":1583,"url":"https://patchwork.plctlab.org/api/1.2/patches/1583/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/57d8ac2a-5757-3776-9924-99c17ca69938@suse.com/","msgid":"<57d8ac2a-5757-3776-9924-99c17ca69938@suse.com>","list_archive_url":null,"date":"2022-09-30T09:42:08","name":"RISC-V: fallout from \"re-arrange opcode table for consistent alias handling\"","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/57d8ac2a-5757-3776-9924-99c17ca69938@suse.com/mbox/"},{"id":1584,"url":"https://patchwork.plctlab.org/api/1.2/patches/1584/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e76ef8f7-72b9-5103-cb43-9608af01d017@suse.com/","msgid":"","list_archive_url":null,"date":"2022-09-30T09:42:50","name":"RISC-V: don'\''t cast expressions'\'' X_add_number to long in diagnostics","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e76ef8f7-72b9-5103-cb43-9608af01d017@suse.com/mbox/"},{"id":1585,"url":"https://patchwork.plctlab.org/api/1.2/patches/1585/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/61355429-24b3-17d0-ab03-6fa57ee861d5@suse.cz/","msgid":"<61355429-24b3-17d0-ab03-6fa57ee861d5@suse.cz>","list_archive_url":null,"date":"2022-09-30T09:48:52","name":"[RFC] add --enable-zstd-compressed-debug-sections configure option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/61355429-24b3-17d0-ab03-6fa57ee861d5@suse.cz/mbox/"},{"id":1586,"url":"https://patchwork.plctlab.org/api/1.2/patches/1586/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930103919.323690-1-christoph.muellner@vrull.eu/","msgid":"<20220930103919.323690-1-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2022-09-30T10:39:19","name":"RISC-V: Eliminate long-casts of X_add_number in diagnostics","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930103919.323690-1-christoph.muellner@vrull.eu/mbox/"},{"id":1590,"url":"https://patchwork.plctlab.org/api/1.2/patches/1590/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/DM6PR12MB4219C943049C6D883DEA3E55E7569@DM6PR12MB4219.namprd12.prod.outlook.com/","msgid":"","list_archive_url":null,"date":"2022-09-30T11:41:37","name":"[V2] Ignore DWARF debug information for -gsplit-dwarf with dwarf-5.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/DM6PR12MB4219C943049C6D883DEA3E55E7569@DM6PR12MB4219.namprd12.prod.outlook.com/mbox/"},{"id":1591,"url":"https://patchwork.plctlab.org/api/1.2/patches/1591/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c10321f9-d289-ef84-d263-bc278fb3d31b@suse.com/","msgid":"","list_archive_url":null,"date":"2022-09-30T11:59:04","name":"[1/4] RISC-V/gas: drop riscv_subsets static variable","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c10321f9-d289-ef84-d263-bc278fb3d31b@suse.com/mbox/"},{"id":1593,"url":"https://patchwork.plctlab.org/api/1.2/patches/1593/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3244eea0-c18c-e49a-4588-d69423130226@suse.com/","msgid":"<3244eea0-c18c-e49a-4588-d69423130226@suse.com>","list_archive_url":null,"date":"2022-09-30T11:59:23","name":"[2/4] RISC-V/gas: drop stray call to install_insn()","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3244eea0-c18c-e49a-4588-d69423130226@suse.com/mbox/"},{"id":1592,"url":"https://patchwork.plctlab.org/api/1.2/patches/1592/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/385d01fd-7e57-1f3f-1bae-30aa0c313d63@suse.com/","msgid":"<385d01fd-7e57-1f3f-1bae-30aa0c313d63@suse.com>","list_archive_url":null,"date":"2022-09-30T11:59:45","name":"[3/4] RISC-V/gas: don'\''t open-code insn_length()","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/385d01fd-7e57-1f3f-1bae-30aa0c313d63@suse.com/mbox/"},{"id":1594,"url":"https://patchwork.plctlab.org/api/1.2/patches/1594/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f5757acf-7b90-a0e3-5eea-3b97cc226930@suse.com/","msgid":"","list_archive_url":null,"date":"2022-09-30T12:00:12","name":"[4/4] RISC-V/gas: allow generating up to 176-bit instructions with .insn","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f5757acf-7b90-a0e3-5eea-3b97cc226930@suse.com/mbox/"},{"id":1596,"url":"https://patchwork.plctlab.org/api/1.2/patches/1596/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930140503.38233-1-chigot@adacore.com/","msgid":"<20220930140503.38233-1-chigot@adacore.com>","list_archive_url":null,"date":"2022-09-30T14:05:03","name":"ld/testsuite: consistently add board_ldflags when linking with GCC","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930140503.38233-1-chigot@adacore.com/mbox/"}],"public":true,"mbox":"https://patchwork.plctlab.org/bundle/patchwork-bot/binutils-gdb_2022-09/mbox/"}]' + bundle_id=6 + git-pw bundle add 6 7891 {'detail': 'You do not have permission to perform this action.'} + git config pull.rebase false + git fetch origin master From github.com:wangliu-iscas/binutils-gdb * branch master -> FETCH_HEAD + git checkout master Switched to a new branch 'master' branch 'master' set up to track 'origin/master'. + git pull origin master From github.com:wangliu-iscas/binutils-gdb * branch master -> FETCH_HEAD Already up to date. + git fetch origin upstream-master From github.com:wangliu-iscas/binutils-gdb * branch upstream-master -> FETCH_HEAD + git checkout upstream-master Switched to a new branch 'upstream-master' branch 'upstream-master' set up to track 'origin/upstream-master'. + git remote add upstream https://sourceware.org/git/binutils-gdb.git + git pull upstream master From https://sourceware.org/git/binutils-gdb * branch master -> FETCH_HEAD * [new branch] master -> upstream/master Already up to date. + git push -u origin upstream-master Everything up-to-date branch 'upstream-master' set up to track 'origin/upstream-master'. + git checkout master Switched to branch 'master' Your branch is up to date with 'origin/master'. + git merge upstream-master Already up to date. + git push -u origin master Everything up-to-date branch 'master' set up to track 'origin/master'. + branchname=series3501-patch7891 ++ git branch -a ++ grep 'series3501-patch7891$' + checkbranch= + checkbranchresult=null + '[' null = series3501-patch7891 ']' + git checkout -b series3501-patch7891 Switched to a new branch 'series3501-patch7891' ++ curl https://patchwork.plctlab.org/api/1.2/series/3501/ % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 3511 100 3511 0 0 90025 0 --:--:-- --:--:-- --:--:-- 92394 + series_response='{"id":3501,"url":"https://patchwork.plctlab.org/api/1.2/series/3501/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/list/?series=3501","project":{"id":2,"url":"https://patchwork.plctlab.org/api/1.2/projects/2/","name":"binutils-gdb","link_name":"binutils-gdb","list_id":"binutils.sourceware.org","list_email":"binutils@sourceware.org","web_url":"https://sourceware.org/mailman/listinfo/binutils","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"name":"Add Xtensa ESP chips support","date":"2022-10-22T12:51:12","submitter":{"id":209,"url":"https://patchwork.plctlab.org/api/1.2/people/209/","name":"Alexey Lapshin","email":"alexey.lapshin@espressif.com"},"version":1,"total":5,"received_total":4,"received_all":false,"mbox":"https://patchwork.plctlab.org/series/3501/mbox/","cover_letter":{"id":531,"url":"https://patchwork.plctlab.org/api/1.2/covers/531/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/cover/94fd668465b77e94f3c000982c694e7da8f828f1.camel@espressif.com/","msgid":"<94fd668465b77e94f3c000982c694e7da8f828f1.camel@espressif.com>","list_archive_url":null,"date":"2022-10-22T12:51:12","name":"[0/5] Add Xtensa ESP chips support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/cover/94fd668465b77e94f3c000982c694e7da8f828f1.camel@espressif.com/mbox/"},"patches":[{"id":7884,"url":"https://patchwork.plctlab.org/api/1.2/patches/7884/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7e53b7980f2b3b74d2250bc87f5db94b1d888a2d.camel@espressif.com/","msgid":"<7e53b7980f2b3b74d2250bc87f5db94b1d888a2d.camel@espressif.com>","list_archive_url":null,"date":"2022-10-22T12:53:54","name":"[1/5] bfd: xtensa: move common code from ld and gas","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7e53b7980f2b3b74d2250bc87f5db94b1d888a2d.camel@espressif.com/mbox/"},{"id":7885,"url":"https://patchwork.plctlab.org/api/1.2/patches/7885/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/63f2699e6ef3e6d1ca415a6ed1187d4f64297521.camel@espressif.com/","msgid":"<63f2699e6ef3e6d1ca415a6ed1187d4f64297521.camel@espressif.com>","list_archive_url":null,"date":"2022-10-22T12:55:16","name":"[2/5] gas: xtensa: add endianness, loops, booleans options","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/63f2699e6ef3e6d1ca415a6ed1187d4f64297521.camel@espressif.com/mbox/"},{"id":7886,"url":"https://patchwork.plctlab.org/api/1.2/patches/7886/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/34d2f747237aeeda595560cfded8096d9bd1c28c.camel@espressif.com/","msgid":"<34d2f747237aeeda595560cfded8096d9bd1c28c.camel@espressif.com>","list_archive_url":null,"date":"2022-10-22T12:56:02","name":"[3/5] ld: xtensa: use default LD command line options for endianness","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/34d2f747237aeeda595560cfded8096d9bd1c28c.camel@espressif.com/mbox/"},{"id":7891,"url":"https://patchwork.plctlab.org/api/1.2/patches/7891/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/535b6208c1718b9acf3258575e1ebc0a65af9f07.camel@espressif.com/","msgid":"<535b6208c1718b9acf3258575e1ebc0a65af9f07.camel@espressif.com>","list_archive_url":null,"date":"2022-10-22T13:56:44","name":"[5/5] gdb: xtensa: add support for esp32, esp32s2, esp32s3 isa-modules","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/535b6208c1718b9acf3258575e1ebc0a65af9f07.camel@espressif.com/mbox/"}]}' ++ jq '.patches[] | (.id|tostring) + "," + .mbox' ++ echo '{"id":3501,"url":"https://patchwork.plctlab.org/api/1.2/series/3501/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/list/?series=3501","project":{"id":2,"url":"https://patchwork.plctlab.org/api/1.2/projects/2/","name":"binutils-gdb","link_name":"binutils-gdb","list_id":"binutils.sourceware.org","list_email":"binutils@sourceware.org","web_url":"https://sourceware.org/mailman/listinfo/binutils","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"name":"Add Xtensa ESP chips support","date":"2022-10-22T12:51:12","submitter":{"id":209,"url":"https://patchwork.plctlab.org/api/1.2/people/209/","name":"Alexey Lapshin","email":"alexey.lapshin@espressif.com"},"version":1,"total":5,"received_total":4,"received_all":false,"mbox":"https://patchwork.plctlab.org/series/3501/mbox/","cover_letter":{"id":531,"url":"https://patchwork.plctlab.org/api/1.2/covers/531/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/cover/94fd668465b77e94f3c000982c694e7da8f828f1.camel@espressif.com/","msgid":"<94fd668465b77e94f3c000982c694e7da8f828f1.camel@espressif.com>","list_archive_url":null,"date":"2022-10-22T12:51:12","name":"[0/5] Add Xtensa ESP chips support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/cover/94fd668465b77e94f3c000982c694e7da8f828f1.camel@espressif.com/mbox/"},"patches":[{"id":7884,"url":"https://patchwork.plctlab.org/api/1.2/patches/7884/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7e53b7980f2b3b74d2250bc87f5db94b1d888a2d.camel@espressif.com/","msgid":"<7e53b7980f2b3b74d2250bc87f5db94b1d888a2d.camel@espressif.com>","list_archive_url":null,"date":"2022-10-22T12:53:54","name":"[1/5] bfd: xtensa: move common code from ld and gas","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7e53b7980f2b3b74d2250bc87f5db94b1d888a2d.camel@espressif.com/mbox/"},{"id":7885,"url":"https://patchwork.plctlab.org/api/1.2/patches/7885/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/63f2699e6ef3e6d1ca415a6ed1187d4f64297521.camel@espressif.com/","msgid":"<63f2699e6ef3e6d1ca415a6ed1187d4f64297521.camel@espressif.com>","list_archive_url":null,"date":"2022-10-22T12:55:16","name":"[2/5] gas: xtensa: add endianness, loops, booleans options","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/63f2699e6ef3e6d1ca415a6ed1187d4f64297521.camel@espressif.com/mbox/"},{"id":7886,"url":"https://patchwork.plctlab.org/api/1.2/patches/7886/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/34d2f747237aeeda595560cfded8096d9bd1c28c.camel@espressif.com/","msgid":"<34d2f747237aeeda595560cfded8096d9bd1c28c.camel@espressif.com>","list_archive_url":null,"date":"2022-10-22T12:56:02","name":"[3/5] ld: xtensa: use default LD command line options for endianness","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/34d2f747237aeeda595560cfded8096d9bd1c28c.camel@espressif.com/mbox/"},{"id":7891,"url":"https://patchwork.plctlab.org/api/1.2/patches/7891/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/535b6208c1718b9acf3258575e1ebc0a65af9f07.camel@espressif.com/","msgid":"<535b6208c1718b9acf3258575e1ebc0a65af9f07.camel@espressif.com>","list_archive_url":null,"date":"2022-10-22T13:56:44","name":"[5/5] gdb: xtensa: add support for esp32, esp32s2, esp32s3 isa-modules","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/535b6208c1718b9acf3258575e1ebc0a65af9f07.camel@espressif.com/mbox/"}]}' + patchid_patchurl='"7884,https://patchwork.plctlab.org/project/binutils-gdb/patch/7e53b7980f2b3b74d2250bc87f5db94b1d888a2d.camel@espressif.com/mbox/" "7885,https://patchwork.plctlab.org/project/binutils-gdb/patch/63f2699e6ef3e6d1ca415a6ed1187d4f64297521.camel@espressif.com/mbox/" "7886,https://patchwork.plctlab.org/project/binutils-gdb/patch/34d2f747237aeeda595560cfded8096d9bd1c28c.camel@espressif.com/mbox/" "7891,https://patchwork.plctlab.org/project/binutils-gdb/patch/535b6208c1718b9acf3258575e1ebc0a65af9f07.camel@espressif.com/mbox/"' + echo '"7884,https://patchwork.plctlab.org/project/binutils-gdb/patch/7e53b7980f2b3b74d2250bc87f5db94b1d888a2d.camel@espressif.com/mbox/" "7885,https://patchwork.plctlab.org/project/binutils-gdb/patch/63f2699e6ef3e6d1ca415a6ed1187d4f64297521.camel@espressif.com/mbox/" "7886,https://patchwork.plctlab.org/project/binutils-gdb/patch/34d2f747237aeeda595560cfded8096d9bd1c28c.camel@espressif.com/mbox/" + IFS=, + read -r series_patch_id series_patch_url "7891,https://patchwork.plctlab.org/project/binutils-gdb/patch/535b6208c1718b9acf3258575e1ebc0a65af9f07.camel@espressif.com/mbox/"' ++ echo '"7884' ++ sed 's/"//g' + series_patch_id=7884 ++ echo 'https://patchwork.plctlab.org/project/binutils-gdb/patch/7e53b7980f2b3b74d2250bc87f5db94b1d888a2d.camel@espressif.com/mbox/"' ++ sed 's/"//g' + series_patch_url=https://patchwork.plctlab.org/project/binutils-gdb/patch/7e53b7980f2b3b74d2250bc87f5db94b1d888a2d.camel@espressif.com/mbox/ ++ git rev-parse HEAD + commitid_before=05bb930a054c80b6f8aecd93dafbcb464a403bc5 + eval '+++ declare -p bout bret declare -- bout="Applying: bfd: xtensa: move common code from ld and gas error: patch fragment without header at line 16: @@ -423,6 +340,7 @@ check_xtensa_info (bfd *abfd, asection *info_sec) error: could not build fake ancestor hint: Use '\''git am --show-current-patch=diff'\'' to see the failed patch Patch failed at 0001 bfd: xtensa: move common code from ld and gas When you have resolved this problem, run \"git am --continue\". If you prefer to skip this patch, run \"git am --skip\" instead. To restore the original branch and stop patching, run \"git am --abort\"." declare -- bret="128" ++ berr='\''++++ git_am https://patchwork.plctlab.org/project/binutils-gdb/patch/7e53b7980f2b3b74d2250bc87f5db94b1d888a2d.camel@espressif.com/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/binutils-gdb/patch/7e53b7980f2b3b74d2250bc87f5db94b1d888a2d.camel@espressif.com/mbox/ ++++ curl https://patchwork.plctlab.org/project/binutils-gdb/patch/7e53b7980f2b3b74d2250bc87f5db94b1d888a2d.camel@espressif.com/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 20486 100 20486 0 0 294k 0 --:--:-- --:--:-- --:--:-- 294k +++ bout='\''\'\'''\''Applying: bfd: xtensa: move common code from ld and gas error: patch fragment without header at line 16: @@ -423,6 +340,7 @@ check_xtensa_info (bfd *abfd, asection *info_sec) error: could not build fake ancestor hint: Use '\''\'\'''\''\'\''\'\'''\'''\''\'\'''\''git am --show-current-patch=diff'\''\'\'''\''\'\''\'\'''\'''\''\'\'''\'' to see the failed patch Patch failed at 0001 bfd: xtensa: move common code from ld and gas When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort".'\''\'\'''\'' +++ bret=128'\'' ++ declare -p berr declare -- berr="++++ git_am https://patchwork.plctlab.org/project/binutils-gdb/patch/7e53b7980f2b3b74d2250bc87f5db94b1d888a2d.camel@espressif.com/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/binutils-gdb/patch/7e53b7980f2b3b74d2250bc87f5db94b1d888a2d.camel@espressif.com/mbox/ ++++ curl https://patchwork.plctlab.org/project/binutils-gdb/patch/7e53b7980f2b3b74d2250bc87f5db94b1d888a2d.camel@espressif.com/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 20486 100 20486 0 0 294k 0 --:--:-- --:--:-- --:--:-- 294k +++ bout='\''Applying: bfd: xtensa: move common code from ld and gas error: patch fragment without header at line 16: @@ -423,6 +340,7 @@ check_xtensa_info (bfd *abfd, asection *info_sec) error: could not build fake ancestor hint: Use '\''\\'\'''\''git am --show-current-patch=diff'\''\\'\'''\'' to see the failed patch Patch failed at 0001 bfd: xtensa: move common code from ld and gas When you have resolved this problem, run \"git am --continue\". If you prefer to skip this patch, run \"git am --skip\" instead. To restore the original branch and stop patching, run \"git am --abort\".'\'' +++ bret=128"' ++ +++ declare -p bout bret /tmp/jenkins9913742993618280903.sh: line 113: +++: command not found ++ declare -- 'bout=Applying: bfd: xtensa: move common code from ld and gas error: patch fragment without header at line 16: @@ -423,6 +340,7 @@ check_xtensa_info (bfd *abfd, asection *info_sec) error: could not build fake ancestor hint: Use '\''git am --show-current-patch=diff'\'' to see the failed patch Patch failed at 0001 bfd: xtensa: move common code from ld and gas When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort".' ++ declare -- bret=128 ++ ++ 'berr=++++ git_am https://patchwork.plctlab.org/project/binutils-gdb/patch/7e53b7980f2b3b74d2250bc87f5db94b1d888a2d.camel@espressif.com/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/binutils-gdb/patch/7e53b7980f2b3b74d2250bc87f5db94b1d888a2d.camel@espressif.com/mbox/ ++++ curl https://patchwork.plctlab.org/project/binutils-gdb/patch/7e53b7980f2b3b74d2250bc87f5db94b1d888a2d.camel@espressif.com/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 20486 100 20486 0 0 294k 0 --:--:-- --:--:-- --:--:-- 294k +++ bout='\''Applying: bfd: xtensa: move common code from ld and gas error: patch fragment without header at line 16: @@ -423,6 +340,7 @@ check_xtensa_info (bfd *abfd, asection *info_sec) error: could not build fake ancestor hint: Use '\''\'\'''\''git am --show-current-patch=diff'\''\'\'''\'' to see the failed patch Patch failed at 0001 bfd: xtensa: move common code from ld and gas When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort".'\'' +++ bret=128' /tmp/jenkins9913742993618280903.sh: line 138: ++: command not found ++ ++ declare -p berr /tmp/jenkins9913742993618280903.sh: line 139: ++: command not found ++ declare -- 'berr=++++ git_am https://patchwork.plctlab.org/project/binutils-gdb/patch/7e53b7980f2b3b74d2250bc87f5db94b1d888a2d.camel@espressif.com/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/binutils-gdb/patch/7e53b7980f2b3b74d2250bc87f5db94b1d888a2d.camel@espressif.com/mbox/ ++++ curl https://patchwork.plctlab.org/project/binutils-gdb/patch/7e53b7980f2b3b74d2250bc87f5db94b1d888a2d.camel@espressif.com/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 20486 100 20486 0 0 294k 0 --:--:-- --:--:-- --:--:-- 294k +++ bout='\''Applying: bfd: xtensa: move common code from ld and gas error: patch fragment without header at line 16: @@ -423,6 +340,7 @@ check_xtensa_info (bfd *abfd, asection *info_sec) error: could not build fake ancestor hint: Use '\''\'\'''\''git am --show-current-patch=diff'\''\'\'''\'' to see the failed patch Patch failed at 0001 bfd: xtensa: move common code from ld and gas When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort".'\'' +++ bret=128' ++ git rev-parse HEAD + commitid_after=05bb930a054c80b6f8aecd93dafbcb464a403bc5 + '[' 128 = 0 ']' + [[ ++++ git_am https://patchwork.plctlab.org/project/binutils-gdb/patch/7e53b7980f2b3b74d2250bc87f5db94b1d888a2d.camel@espressif.com/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/binutils-gdb/patch/7e53b7980f2b3b74d2250bc87f5db94b1d888a2d.camel@espressif.com/mbox/ ++++ curl https://patchwork.plctlab.org/project/binutils-gdb/patch/7e53b7980f2b3b74d2250bc87f5db94b1d888a2d.camel@espressif.com/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 20486 100 20486 0 0 294k 0 --:--:-- --:--:-- --:--:-- 294k +++ bout='Applying: bfd: xtensa: move common code from ld and gas error: patch fragment without header at line 16: @@ -423,6 +340,7 @@ check_xtensa_info (bfd *abfd, asection *info_sec) error: could not build fake ancestor hint: Use '\''git am --show-current-patch=diff'\'' to see the failed patch Patch failed at 0001 bfd: xtensa: move common code from ld and gas When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort".' +++ bret=128 =~ sha1 information is lacking or useless ]] + [[ ++++ git_am https://patchwork.plctlab.org/project/binutils-gdb/patch/7e53b7980f2b3b74d2250bc87f5db94b1d888a2d.camel@espressif.com/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/binutils-gdb/patch/7e53b7980f2b3b74d2250bc87f5db94b1d888a2d.camel@espressif.com/mbox/ ++++ curl https://patchwork.plctlab.org/project/binutils-gdb/patch/7e53b7980f2b3b74d2250bc87f5db94b1d888a2d.camel@espressif.com/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 20486 100 20486 0 0 294k 0 --:--:-- --:--:-- --:--:-- 294k +++ bout='Applying: bfd: xtensa: move common code from ld and gas error: patch fragment without header at line 16: @@ -423,6 +340,7 @@ check_xtensa_info (bfd *abfd, asection *info_sec) error: could not build fake ancestor hint: Use '\''git am --show-current-patch=diff'\'' to see the failed patch Patch failed at 0001 bfd: xtensa: move common code from ld and gas When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort".' +++ bret=128 =~ Failed to merge in the changes ]] + [[ ++++ git_am https://patchwork.plctlab.org/project/binutils-gdb/patch/7e53b7980f2b3b74d2250bc87f5db94b1d888a2d.camel@espressif.com/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/binutils-gdb/patch/7e53b7980f2b3b74d2250bc87f5db94b1d888a2d.camel@espressif.com/mbox/ ++++ curl https://patchwork.plctlab.org/project/binutils-gdb/patch/7e53b7980f2b3b74d2250bc87f5db94b1d888a2d.camel@espressif.com/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 20486 100 20486 0 0 294k 0 --:--:-- --:--:-- --:--:-- 294k +++ bout='Applying: bfd: xtensa: move common code from ld and gas error: patch fragment without header at line 16: @@ -423,6 +340,7 @@ check_xtensa_info (bfd *abfd, asection *info_sec) error: could not build fake ancestor hint: Use '\''git am --show-current-patch=diff'\'' to see the failed patch Patch failed at 0001 bfd: xtensa: move common code from ld and gas When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort".' +++ bret=128 =~ corrupt patch at ]] + [[ ++++ git_am https://patchwork.plctlab.org/project/binutils-gdb/patch/7e53b7980f2b3b74d2250bc87f5db94b1d888a2d.camel@espressif.com/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/binutils-gdb/patch/7e53b7980f2b3b74d2250bc87f5db94b1d888a2d.camel@espressif.com/mbox/ ++++ curl https://patchwork.plctlab.org/project/binutils-gdb/patch/7e53b7980f2b3b74d2250bc87f5db94b1d888a2d.camel@espressif.com/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 20486 100 20486 0 0 294k 0 --:--:-- --:--:-- --:--:-- 294k +++ bout='Applying: bfd: xtensa: move common code from ld and gas error: patch fragment without header at line 16: @@ -423,6 +340,7 @@ check_xtensa_info (bfd *abfd, asection *info_sec) error: could not build fake ancestor hint: Use '\''git am --show-current-patch=diff'\'' to see the failed patch Patch failed at 0001 bfd: xtensa: move common code from ld and gas When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort".' +++ bret=128 =~ patch fragment without header at ]] + submit_check warning Unresolved https://patchwork.plctlab.org/jenkins/job/binutils-gdb/200/consoleText 'Git am fail log' + check_state=warning + patch_state=Unresolved + repo_url=https://patchwork.plctlab.org/jenkins/job/binutils-gdb/200/consoleText + DESCRIPTION='Git am fail log' + curl -X POST -H 'Authorization: Token [*******]' -F state=warning -F target_url=https://patchwork.plctlab.org/jenkins/job/binutils-gdb/200/consoleText -F context=binutils-gdb-check -F 'description=Git am fail log' https://patchwork.plctlab.org/api/patches/7891/checks/ % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 974 100 429 100 545 11594 14729 --:--:-- --:--:-- --:--:-- 26324 {"id":1296,"url":"https://patchwork.plctlab.org/api/patches/7891/checks/1296/","user":{"id":1,"url":"https://patchwork.plctlab.org/api/users/1/","username":"snail","first_name":"","last_name":"","email":"wangliu@iscas.ac.cn"},"date":"2022-10-24T08:19:38.330995","state":"warning","target_url":"https://patchwork.plctlab.org/jenkins/job/binutils-gdb/200/consoleText","context":"binutils-gdb-check","description":"Git am fail log"}+ curl -X PATCH -H 'Authorization: Token [*******]' -F state=Unresolved https://patchwork.plctlab.org/api/1.2/patches/7891/ % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0{"id":7891,"url":"https://patchwork.plctlab.org/api/1.2/patches/7891/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/535b6208c1718b9acf3258575e1ebc0a65af9f07.camel@espressif.com/","project":{"id":2,"url":"https://patchwork.plctlab.org/api/1.2/projects/2/","name":"binutils-gdb","link_name":"binutils-gdb","list_id":"binutils.sourceware.org","list_email":"binutils@sourceware.org","web_url":"https://sourceware.org/mailman/listinfo/binutils","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<535b6208c1718b9acf3258575e1ebc0a65af9f07.camel@espressif.com>","list_archive_url":null,"date":"2022-10-22T13:56:44","name":"[5/5] gdb: xtensa: add support for esp32, esp32s2, esp32s3 isa-modules","commit_ref":null,"pull_url":null,"state":"unresolved","archived":false,"hash":"391749d78741d7f76764b7fd0914df578b7732cf","submitter":{"id":209,"url":"https://patchwork.plctlab.org/api/1.2/people/209/","name":"Alexey Lapshin","email":"alexey.lapshin@espressif.com"},"delegate":null,"mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/535b6208c1718b9acf3258575e1ebc0a65af9f07.camel@espressif.com/mbox/","series":[{"id":3501,"url":"https://patchwork.plctlab.org/api/1.2/series/3501/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/list/?series=3501","date":"2022-10-22T12:51:12","name":"Add Xtensa ESP chips support","version":1,"mbox":"https://patchwork.plctlab.org/series/3501/mbox/"}],"comments":"https://patchwork.plctlab.org/api/patches/7891/comments/","check":"warning","checks":"https://patchwork.plctlab.org/api/patches/7891/checks/","tags":{},"headers":{"Return-Path":"","Delivered-To":["ouuuleilei@gmail.com","binutils@sourceware.org"],"Received":["by 2002:a5d:4242:0:0:0:0:0 with SMTP id s2csp1216191wrr;\n Sat, 22 Oct 2022 06:57:14 -0700 (PDT)","from sourceware.org (server2.sourceware.org.\n [2620:52:3:1:0:246e:9693:128c])\n by mx.google.com with ESMTPS id\n gb22-20020a170907961600b0072fc714c92fsi24348159ejc.902.2022.10.22.06.57.13\n for \n (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256);\n Sat, 22 Oct 2022 06:57:14 -0700 (PDT)","from server2.sourceware.org (localhost [IPv6:::1])\n\tby sourceware.org (Postfix) with ESMTP id C333C3857B92\n\tfor ; Sat, 22 Oct 2022 13:57:10 +0000 (GMT)","from APC01-TYZ-obe.outbound.protection.outlook.com\n (mail-tyzapc01on2126.outbound.protection.outlook.com [40.107.117.126])\n by sourceware.org (Postfix) with ESMTPS id EEC743858419\n for ; Sat, 22 Oct 2022 13:56:55 +0000 (GMT)","from TYZPR04MB5736.apcprd04.prod.outlook.com (2603:1096:400:1fa::7)\n by PSAPR04MB4453.apcprd04.prod.outlook.com (2603:1096:301:30::11)\n with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5746.21; Sat, 22 Oct\n 2022 13:56:44 +0000","from TYZPR04MB5736.apcprd04.prod.outlook.com\n ([fe80::e64d:5c85:a83c:5898]) by TYZPR04MB5736.apcprd04.prod.outlook.com\n ([fe80::e64d:5c85:a83c:5898%4]) with mapi id 15.20.5723.032; Sat, 22 Oct 2022\n 13:56:44 +0000"],"X-Google-Smtp-Source":"\n AMsMyM4bFxZXU94DnZT7TbpmO5R094x3NnSzhRHQln1JmkUHDx+Cd5fOkJzHCPmjZna1pRwrR/8/","X-Received":"by 2002:a50:fd94:0:b0:461:5131:d3c with SMTP id\n o20-20020a50fd94000000b0046151310d3cmr6861487edt.112.1666447034399;\n Sat, 22 Oct 2022 06:57:14 -0700 (PDT)","Received-SPF":"pass (google.com: domain of\n binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates\n 2620:52:3:1:0:246e:9693:128c as permitted sender)\n client-ip=2620:52:3:1:0:246e:9693:128c;","Authentication-Results":"mx.google.com;\n dkim=pass header.i=@sourceware.org header.s=default header.b=Zq1QLLQZ;\n arc=fail (signature failed);\n spf=pass (google.com: domain of\n binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates\n 2620:52:3:1:0:246e:9693:128c as permitted sender)\n smtp.mailfrom=\"binutils-bounces+ouuuleilei=gmail.com@sourceware.org\";\n dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=sourceware.org","DKIM-Filter":"OpenDKIM Filter v2.11.0 sourceware.org C333C3857B92","DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org;\n\ts=default; t=1666447030;\n\tbh=HqV0zaiiEp/eqxDRZ1tR4SFub8IfYqFa8+e5lbIUq4c=;\n\th=To:Subject:Date:References:In-Reply-To:List-Id:List-Unsubscribe:\n\t List-Archive:List-Post:List-Help:List-Subscribe:From:Reply-To:Cc:\n\t From;\n\tb=Zq1QLLQZ31jv9j+wc9tZRxwVz+x2b0pu+SmEV127qcNcR23y8wKKl15o1yX9jvUMB\n\t nNMOSKIkRdB2aVq3ZBStHFYTUdj98/e3o7v0e69THTED+03HKyj8QbQogkuq/F7S+H\n\t LPB2B55ueHAgLu27CJNkAkBPv6OFVDNc+d1ZqVoM=","X-Original-To":"binutils@sourceware.org","DMARC-Filter":"OpenDMARC Filter v1.4.1 sourceware.org EEC743858419","ARC-Seal":"i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none;\n b=SSb0LCwrqCcNbA0g/GoINzI45vgzlaNaCMKn/L03a3wQWkM1hfQrFZZlzdbXgeDrBxPE+fIg0NLsnF7t4/4Dk+f+CkxrxtIDZCV1XBE0+IqGZ+JibeQvk+thZqz14Bgsq66ms3G+fub/9hBG9/QFhm1eRIZedp+qjRjGAUqT5BN/GeFeOoKj+sT1CBWt+XyjRiyyAHI8VK4vVzA45WlyiKdFvnnjfn/cu3YHH1kllGbS2QcjBjXRR910e/EWMYHyzSoIz/cCFxP4Pz7rBYZA+6uqsXTve+O393Tn8cYp+2hId4VsBOu09JRvR2+KRnvZNIYPBNG6sKn4M+Hr8fBC+g==","ARC-Message-Signature":"i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com;\n s=arcselector9901;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1;\n bh=HqV0zaiiEp/eqxDRZ1tR4SFub8IfYqFa8+e5lbIUq4c=;\n b=C0qcaCPPXpyPN3/31n63p5Rrm0kUWDs3r8PyquLTGT/fDYaLX0Y3LId9YSgJ2Z4As3BiMICFmdvsXOfh2jP1xJtAK9qG2GLXyfPOrZxTp/lVY+tTdxaVVlBgHRqmOUGwYTBEtC4NL1gtL9tZYHvHgag7+AOVcmJ3fveSEKDDm7DzJ5NVqi7JuzRW4Mq5nP0a2zqIk2UKax4d/aJkH2POsUGPxZ3Z/VAO/dE09Q8jFvBAo5t49dpmATSOjhh3pWnKBNxcIeBJXiCe3qcRuxnywPlJw6QL1IlTRT4Ab5OSKGTI8lsfiQHWWiLbfMPkhT4IZ2smaT+UiqMwt+u6vWONlA==","ARC-Authentication-Results":"i=1; mx.microsoft.com 1; spf=pass\n smtp.mailfrom=espressif.com; dmarc=pass action=none\n header.from=espressif.com; dkim=pass header.d=espressif.com; arc=none","To":"\"binutils@sourceware.org\" ","Subject":"[PATCH 5/5] gdb: xtensa: add support for esp32, esp32s2, esp32s3\n isa-modules","Thread-Topic":"[PATCH 5/5] gdb: xtensa: add support for esp32, esp32s2, esp32s3\n isa-modules","Thread-Index":"AQHY5h4ego+5joh4l0eAMRv93cjccA==","Date":"Sat, 22 Oct 2022 13:56:44 +0000","Message-ID":"<535b6208c1718b9acf3258575e1ebc0a65af9f07.camel@espressif.com>","References":"<94fd668465b77e94f3c000982c694e7da8f828f1.camel@espressif.com>","In-Reply-To":"<94fd668465b77e94f3c000982c694e7da8f828f1.camel@espressif.com>","Accept-Language":"en-US","Content-Language":"en-US","X-MS-Has-Attach":"","X-MS-TNEF-Correlator":"","x-ms-publictraffictype":"Email","x-ms-traffictypediagnostic":"TYZPR04MB5736:EE_|PSAPR04MB4453:EE_","x-ms-office365-filtering-correlation-id":"7002d1b0-6377-43d8-0737-08dab435412f","x-ms-exchange-senderadcheck":"1","x-ms-exchange-antispam-relay":"0","x-microsoft-antispam":"BCL:0;","x-microsoft-antispam-message-info":"\n wmfMmqNoQ5RC+Ef/qVx9iurdNf0/v+BdCkNZJeARnRjH57cmYgLE7bG+xSUGWx0jnwRqsI8lnVXE+LtyLAr0satNKJCLNxpv/iXXI9y3UMfKH0RvVx0VblCMQnR3RbybIeAo3GpswMdLkJ33pL/FbjUpb2I2KosN0XuDCY0XyM2hqg82pyoCswQITrf6+URqN2fuaNjwB9dkJmuHkbahjofCtCVY6rhvjBFQKf6HyspnYbl7Z53kkFIuMF3giNGWAiJQMflWN0bKpZHBIYPODNO5YJAJgEVoTYg209Yfyj04+JG42aNBwMckro2merruqNQiAfiUM/TUQMKlelvgCJsv4k2yb9tyCcavpxv98b8hNerYyrP72JqwIxCHsENBb9L1oE2KGdJB25iMCcMlJGZ3NYA7cEM8RumDnXTph2W5tbsROBrdu8hoQzVUnnSFxl5BNQdd8ysgbJbQgnUIFwFbp9JQ9ms+IzvNVEOMZlML38wbdGNdTER9GhFxGdXuflEzh6ejPitZEqWdxP92WKxYgF5PpbNMGsonFlKggsUp/6Y/Qjgzedy6Jca5UWvnaarwJ/FU3yDz13CEjOtY5pZpaa1RHSd6AHGXUtSBbc6y8TkQf4x2zdCnx9aJ06yP2VeiKfUr4QP8IG5/oL+A6MuzRnvZfKKi237VouDybQAkDKQUlsuGUBl89CSmdiK1cLjp/zW5Cvv4OMKPktzUh6NSPRT6TORSQaBOqryVYJXPvz3JbpmlZnufKtUaFbC7wqQU/ob8n27XmxxQwLAmSw==","x-forefront-antispam-report":"CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:;\n IPV:NLI; SFV:NSPM; H:TYZPR04MB5736.apcprd04.prod.outlook.com; PTR:; CAT:NONE;\n SFS:(13230022)(4636009)(136003)(39840400004)(346002)(366004)(376002)(396003)(451199015)(66899015)(478600001)(8936002)(6916009)(54906003)(6486002)(38070700005)(83380400001)(30864003)(36756003)(2906002)(5660300002)(91956017)(41300700001)(66476007)(66446008)(64756008)(71200400001)(66556008)(76116006)(66946007)(316002)(4326008)(8676002)(44832011)(6512007)(186003)(107886003)(2616005)(122000001)(38100700002)(86362001)(26005)(6506007)(579004)(559001);\n DIR:OUT; SFP:1102;","x-ms-exchange-antispam-messagedata-chunkcount":"1","x-ms-exchange-antispam-messagedata-0":"=?utf-8?q?wMRQI24CrVErPuRDuML8OcbMb20U?=\n\t=?utf-8?q?NJw/VWXAKt+fufteb2o8s7aHu+HVL+KKUvOpTe3/VajQlW987K9gsoB0QBYcG16DQ?=\n\t=?utf-8?q?V1Zd7cJCZvKXX4rEM7CR3B4ujzaS6RQCG+LPSdL5tc2nYSsqqkAFyXdnTv+hmHdl8?=\n\t=?utf-8?q?D3hZB2ktmOUdJtzCHC/DuS4Q+9NK2fqXu/452nRV1z/GsreQa0DCos6RA4SNLtb0L?=\n\t=?utf-8?q?XSTeAxbmmqACfi9rAjjt/jp8bAgv78jPV2GagMhGgQC9bV8YzWu2XqhyYDF7CUUj3?=\n\t=?utf-8?q?WQbaks/65dIOjXTNNbmBwtRCdoNGwla8Voa38axPsese69cM+gAtILOR+fXvtrssK?=\n\t=?utf-8?q?Uf8/gZ14BCrBzneH1PXlCYnvqSj1A4AEHtcbiX1bhd0fZ4WTK344/AX5bX2oyzMnZ?=\n\t=?utf-8?q?kAESrjtZv2zoQKboyQujkJKQ5Frl0wv7DNSHogXJVOfrpyfaKnCtuxXtWel7Vj7ZA?=\n\t=?utf-8?q?ZhQgPtb2jHY7aZs+OhSvzukL0rsRwVn2nFPRUoxj7Rb9xQ1ArZHB0UkZNVf17QL/K?=\n\t=?utf-8?q?qTc9agAL8rPpj1xBldDf4RORKShQaTTd1x1fDmOPzimbXc5glQoyqRjItYXY1Id9f?=\n\t=?utf-8?q?PYkAINHHoo/tPAznrssvVosj8T0AhcJLL7fa2v0QQhxFxb7BrQY2qpJjXF+aVMKd0?=\n\t=?utf-8?q?wThNW355cdlwEvIojVyC54GMDLD6H8XTLmmdhuglApDBU8dH2hc0gSpeisuqZfSnI?=\n\t=?utf-8?q?oERp3+xamEkU9Iq+y3lJif+UgNGSdT1XNn8cj52smopBn7Zbf3ZSdDKQD9lbyUb0/?=\n\t=?utf-8?q?M1xPTbx4jmqC/YDEOx9NTdnhQKqsx1mUxLJjj59xPz0K15PanAM/9PNrxrGKhlbna?=\n\t=?utf-8?q?MhErehtJmCzElffPoTsMRwP1TSA/PzqkgUirJsvsoXj2/NgWJkydODp8snU3lA0QL?=\n\t=?utf-8?q?yNt8XzIUJnYfnRLl8ezaVGvQicHF0bWu6SByGhz1b0HEADqhN1ChtFicYwNv0WFd4?=\n\t=?utf-8?q?jvssnX4J0JtJQT1HF+Y9eE+VmFyCmGeSoGsMybbT4SYK787w/lZQepgjdQre5PctW?=\n\t=?utf-8?q?cElKFC9xMJUnrnuPs2bwC5JOMuccujmSPj8k4/XYgHcNfBsI6oYJdd/K97iMued8T?=\n\t=?utf-8?q?m+VDdRQ1Qk6LY33Kg3FMWBbyP0hTvyw54sy56Kby/R89EfS0NLLpJr3jtwegtfDb/?=\n\t=?utf-8?q?cLddjEzap8H+g3cpfVfSTZw+RrglG4t2gaWtQNIHCNde4eyKXnzMCfzliuzpkwEch?=\n\t=?utf-8?q?s1Z5t7iJzUsFhzTuPv1jDq5DD60qsCXCITYfMG0nFnY4FvBiV2kogZxWHjBH/XYCP?=\n\t=?utf-8?q?84KEx9Arji7eEEJXer9hdqNdXNoy2uq672iIIAlze2DNWLgqGJdZR6gqrXCfvWIs4?=\n\t=?utf-8?q?rOOaf4D6kxeH9o9n2+YPrsqq4kbO25UlbRZwRVZz/BwbSkZwHqhFrdNPEHmuQaJuo?=\n\t=?utf-8?q?5cNnuGFWwwDIXomM6oeaH05kyDLo4ImQXLMCxZd76sdYOAHDSPSD0ZyVpAHTWtZ0E?=\n\t=?utf-8?q?4FJ7rwHKAEABruAUXoNaSxTlt6xGdDfvZTvyAGtBN8iDIx/tlZmvwCgRJ2DVxrxAi?=\n\t=?utf-8?q?uOgnLMAVk6DrvGdmU9X7KXQVEEkZyXqKGkq8+pTdFcZZwRxiQiofzdk=3D?=","Content-Type":"text/plain; charset=\"utf-8\"","Content-ID":"","Content-Transfer-Encoding":"base64","MIME-Version":"1.0","X-OriginatorOrg":"espressif.com","X-MS-Exchange-CrossTenant-AuthAs":"Internal","X-MS-Exchange-CrossTenant-AuthSource":"TYZPR04MB5736.apcprd04.prod.outlook.com","X-MS-Exchange-CrossTenant-Network-Message-Id":"\n 7002d1b0-6377-43d8-0737-08dab435412f","X-MS-Exchange-CrossTenant-originalarrivaltime":"22 Oct 2022 13:56:44.5901 (UTC)","X-MS-Exchange-CrossTenant-fromentityheader":"Hosted","X-MS-Exchange-CrossTenant-id":"5faf27fd-3557-4294-9545-8ea74a409f39","X-MS-Exchange-CrossTenant-mailboxtype":"HOSTED","X-MS-Exchange-CrossTenant-userprincipalname":"\n swiUQ+bAR9nTGr6eR3yygLQZdMpOZ7E4zyW0y/DoGHEXqmSZTuEa7MuLObclaW713IBr7LhQ+PnsQFt27QEzofXxB/jJOFOUZi/OUbmXUfg=","X-MS-Exchange-Transport-CrossTenantHeadersStamped":"PSAPR04MB4453","X-Spam-Status":"No, score=-13.3 required=5.0 tests=BAYES_00, DKIM_SIGNED,\n DKIM_VALID, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2,\n SPF_HELO_PASS,\n SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6","X-Spam-Checker-Version":"SpamAssassin 3.4.6 (2021-04-09) on\n server2.sourceware.org","X-BeenThere":"binutils@sourceware.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"Binutils mailing list ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","From":"Alexey Lapshin via Binutils ","Reply-To":"Alexey Lapshin ","Cc":"Anton Maklakov ,\n Alexey Gerenkov ,\n Ivan Grokhotkov ","Errors-To":"binutils-bounces+ouuuleilei=gmail.com@sourceware.org","Sender":"\"Binutils\" ","X-getmail-retrieved-from-mailbox":"=?utf-8?q?INBOX?=","X-GMAIL-THRID":"=?utf-8?q?1747396365810434835?=","X-GMAIL-MSGID":"=?utf-8?q?1747396365810434835?="},"content":"Added Xtensa ESP chips support for gdb.\nA chip isa-module gets from .xtensa.info section.\n\n---\n gdb/Makefile.in | 10 +-\n gdb/configure.tgt | 2 +-\n ...tensa-config.c => xtensa-config-default.c} | 66 +--\n gdb/xtensa-config-esp32.c | 389 ++++++++++++++\n gdb/xtensa-config-esp32s2.c | 271 ++++++++++\n gdb/xtensa-config-esp32s3.c | 496 ++++++++++++++++++\n gdb/xtensa-tdep.c | 70 ++-\n gdb/xtensa-tdep.h | 2 +-\n 8 files changed, 1263 insertions(+), 43 deletions(-)\n rename gdb/{xtensa-config.c => xtensa-config-default.c} (84%)\n create mode 100644 gdb/xtensa-config-esp32.c\n create mode 100644 gdb/xtensa-config-esp32s2.c\n create mode 100644 gdb/xtensa-config-esp32s3.c\n\n {#name, ofs, (xtensa_register_type_t) (ty), \\\n \t((xtensa_register_group_t) \\\n-- \n2.34.1","diff":"diff --git a/gdb/Makefile.in b/gdb/Makefile.in\r\nindex 911daa2607b..6a60b53ae5a 100644\r\n--- a/gdb/Makefile.in\r\n+++ b/gdb/Makefile.in\r\n@@ -867,7 +867,10 @@ ALL_TARGET_OBS = \\\r\n \tx86-tdep.o \\\r\n \txcoffread.o \\\r\n \txstormy16-tdep.o \\\r\n-\txtensa-config.o \\\r\n+\txtensa-config-default.o \\\r\n+\txtensa-config-esp32.o \\\r\n+\txtensa-config-esp32s2.o \\\r\n+\txtensa-config-esp32s3.o \\\r\n \txtensa-linux-tdep.o \\\r\n \txtensa-tdep.o \\\r\n \tz80-tdep.o\r\n@@ -1822,7 +1825,10 @@ ALLDEPFILES = \\\r\n \tx86-tdep.c \\\r\n \txcoffread.c \\\r\n \txstormy16-tdep.c \\\r\n-\txtensa-config.c \\\r\n+\txtensa-config-default.c \\\r\n+\txtensa-config-esp32.c \\\r\n+\txtensa-config-esp32s2.c \\\r\n+\txtensa-config-esp32s3.c \\\r\n \txtensa-linux-nat.c \\\r\n \txtensa-linux-tdep.c \\\r\n \txtensa-tdep.c \\\r\ndiff --git a/gdb/configure.tgt b/gdb/configure.tgt\r\nindex 0705ccf32b8..2e547f586f8 100644\r\n--- a/gdb/configure.tgt\r\n+++ b/gdb/configure.tgt\r\n@@ -105,7 +105,7 @@ x86_64-*-*)\r\n \r\n xtensa*)\r\n \t# Target: Tensilica Xtensa processors\r\n-\tcpu_obs=\"xtensa-tdep.o xtensa-config.o solib-svr4.o\"\r\n+\tcpu_obs=\"xtensa-tdep.o xtensa-config-default.o xtensa-config-\r\nesp32.o xtensa-config-esp32s2.o xtensa-config-esp32s3.o solib-svr4.o\"\r\n \t;;\r\n \r\n esac\r\ndiff --git a/gdb/xtensa-config.c b/gdb/xtensa-config-default.c\r\nsimilarity index 84%\r\nrename from gdb/xtensa-config.c\r\nrename to gdb/xtensa-config-default.c\r\nindex a28ffd58c96..e654325c460 100644\r\n--- a/gdb/xtensa-config.c\r\n+++ b/gdb/xtensa-config-default.c\r\n@@ -27,38 +27,38 @@\r\n \r\n \r\n /* Masked registers. */\r\n-xtensa_reg_mask_t xtensa_submask0[] = { { 42, 0, 4 } };\r\n-const xtensa_mask_t xtensa_mask0 = { 1, xtensa_submask0 };\r\n-xtensa_reg_mask_t xtensa_submask1[] = { { 42, 5, 1 } };\r\n-const xtensa_mask_t xtensa_mask1 = { 1, xtensa_submask1 };\r\n-xtensa_reg_mask_t xtensa_submask2[] = { { 42, 18, 1 } };\r\n-const xtensa_mask_t xtensa_mask2 = { 1, xtensa_submask2 };\r\n-xtensa_reg_mask_t xtensa_submask3[] = { { 42, 6, 2 } };\r\n-const xtensa_mask_t xtensa_mask3 = { 1, xtensa_submask3 };\r\n-xtensa_reg_mask_t xtensa_submask4[] = { { 42, 4, 1 } };\r\n-const xtensa_mask_t xtensa_mask4 = { 1, xtensa_submask4 };\r\n-xtensa_reg_mask_t xtensa_submask5[] = { { 42, 16, 2 } };\r\n-const xtensa_mask_t xtensa_mask5 = { 1, xtensa_submask5 };\r\n-xtensa_reg_mask_t xtensa_submask6[] = { { 42, 8, 4 } };\r\n-const xtensa_mask_t xtensa_mask6 = { 1, xtensa_submask6 };\r\n-xtensa_reg_mask_t xtensa_submask7[] = { { 37, 12, 20 } };\r\n-const xtensa_mask_t xtensa_mask7 = { 1, xtensa_submask7 };\r\n-xtensa_reg_mask_t xtensa_submask8[] = { { 37, 0, 1 } };\r\n-const xtensa_mask_t xtensa_mask8 = { 1, xtensa_submask8 };\r\n-xtensa_reg_mask_t xtensa_submask9[] = { { 86, 8, 4 } };\r\n-const xtensa_mask_t xtensa_mask9 = { 1, xtensa_submask9 };\r\n-xtensa_reg_mask_t xtensa_submask10[] = { { 47, 24, 8 } };\r\n-const xtensa_mask_t xtensa_mask10 = { 1, xtensa_submask10 };\r\n-xtensa_reg_mask_t xtensa_submask11[] = { { 47, 16, 8 } };\r\n-const xtensa_mask_t xtensa_mask11 = { 1, xtensa_submask11 };\r\n-xtensa_reg_mask_t xtensa_submask12[] = { { 47, 8, 8 } };\r\n-const xtensa_mask_t xtensa_mask12 = { 1, xtensa_submask12 };\r\n-xtensa_reg_mask_t xtensa_submask13[] = { { 48, 16, 2 } };\r\n-const xtensa_mask_t xtensa_mask13 = { 1, xtensa_submask13 };\r\n-xtensa_reg_mask_t xtensa_submask14[] = { { 49, 16, 2 } };\r\n-const xtensa_mask_t xtensa_mask14 = { 1, xtensa_submask14 };\r\n-xtensa_reg_mask_t xtensa_submask15[] = { { 45, 22, 10 } };\r\n-const xtensa_mask_t xtensa_mask15 = { 1, xtensa_submask15 };\r\n+static xtensa_reg_mask_t xtensa_submask0[] = { { 42, 0, 4 } };\r\n+static const xtensa_mask_t xtensa_mask0 = { 1, xtensa_submask0 };\r\n+static xtensa_reg_mask_t xtensa_submask1[] = { { 42, 5, 1 } };\r\n+static const xtensa_mask_t xtensa_mask1 = { 1, xtensa_submask1 };\r\n+static xtensa_reg_mask_t xtensa_submask2[] = { { 42, 18, 1 } };\r\n+static const xtensa_mask_t xtensa_mask2 = { 1, xtensa_submask2 };\r\n+static xtensa_reg_mask_t xtensa_submask3[] = { { 42, 6, 2 } };\r\n+static const xtensa_mask_t xtensa_mask3 = { 1, xtensa_submask3 };\r\n+static xtensa_reg_mask_t xtensa_submask4[] = { { 42, 4, 1 } };\r\n+static const xtensa_mask_t xtensa_mask4 = { 1, xtensa_submask4 };\r\n+static xtensa_reg_mask_t xtensa_submask5[] = { { 42, 16, 2 } };\r\n+static const xtensa_mask_t xtensa_mask5 = { 1, xtensa_submask5 };\r\n+static xtensa_reg_mask_t xtensa_submask6[] = { { 42, 8, 4 } };\r\n+static const xtensa_mask_t xtensa_mask6 = { 1, xtensa_submask6 };\r\n+static xtensa_reg_mask_t xtensa_submask7[] = { { 37, 12, 20 } };\r\n+static const xtensa_mask_t xtensa_mask7 = { 1, xtensa_submask7 };\r\n+static xtensa_reg_mask_t xtensa_submask8[] = { { 37, 0, 1 } };\r\n+static const xtensa_mask_t xtensa_mask8 = { 1, xtensa_submask8 };\r\n+static xtensa_reg_mask_t xtensa_submask9[] = { { 86, 8, 4 } };\r\n+static const xtensa_mask_t xtensa_mask9 = { 1, xtensa_submask9 };\r\n+static xtensa_reg_mask_t xtensa_submask10[] = { { 47, 24, 8 } };\r\n+static const xtensa_mask_t xtensa_mask10 = { 1, xtensa_submask10 };\r\n+static xtensa_reg_mask_t xtensa_submask11[] = { { 47, 16, 8 } };\r\n+static const xtensa_mask_t xtensa_mask11 = { 1, xtensa_submask11 };\r\n+static xtensa_reg_mask_t xtensa_submask12[] = { { 47, 8, 8 } };\r\n+static const xtensa_mask_t xtensa_mask12 = { 1, xtensa_submask12 };\r\n+static xtensa_reg_mask_t xtensa_submask13[] = { { 48, 16, 2 } };\r\n+static const xtensa_mask_t xtensa_mask13 = { 1, xtensa_submask13 };\r\n+static xtensa_reg_mask_t xtensa_submask14[] = { { 49, 16, 2 } };\r\n+static const xtensa_mask_t xtensa_mask14 = { 1, xtensa_submask14 };\r\n+static xtensa_reg_mask_t xtensa_submask15[] = { { 45, 22, 10 } };\r\n+static const xtensa_mask_t xtensa_mask15 = { 1, xtensa_submask15 };\r\n \r\n \r\n /* Register map. */\r\n@@ -213,4 +213,4 @@ static xtensa_register_t rmap[] =\r\n XTREG_END\r\n };\r\n \r\n-xtensa_gdbarch_tdep xtensa_tdep (rmap);\r\n+xtensa_gdbarch_tdep xtensa_tdep_default (rmap);\r\ndiff --git a/gdb/xtensa-config-esp32.c b/gdb/xtensa-config-esp32.c\r\nnew file mode 100644\r\nindex 00000000000..923bee640d3\r\n--- /dev/null\r\n+++ b/gdb/xtensa-config-esp32.c\r\n@@ -0,0 +1,389 @@\r\n+/* Configuration for the Xtensa architecture for GDB, the GNU\r\ndebugger.\r\n+\r\n+ Copyright (c) 2003-2016 Tensilica Inc.\r\n+\r\n+ Permission is hereby granted, free of charge, to any person\r\nobtaining\r\n+ a copy of this software and associated documentation files (the\r\n+ \"Software\"), to deal in the Software without restriction, including\r\n+ without limitation the rights to use, copy, modify, merge, publish,\r\n+ distribute, sublicense, and/or sell copies of the Software, and to\r\n+ permit persons to whom the Software is furnished to do so, subject\r\nto\r\n+ the following conditions:\r\n+\r\n+ The above copyright notice and this permission notice shall be\r\nincluded\r\n+ in all copies or substantial portions of the Software.\r\n+\r\n+ THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\r\n+ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r\n+ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r\nNONINFRINGEMENT.\r\n+ IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR\r\nANY\r\n+ CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF\r\nCONTRACT,\r\n+ TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE\r\n+ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */\r\n+\r\n+#define XTENSA_CONFIG_VERSION 0x60\r\n+\r\n+#include \"defs.h\"\r\n+#include \"xtensa-config.h\"\r\n+#include \"xtensa-tdep.h\"\r\n+\r\n+\r\n+\r\n+/* Masked registers. */\r\n+static xtensa_reg_mask_t xtensa_submask0[] = { { 75, 0, 1 } };\r\n+static const xtensa_mask_t xtensa_mask0 = { 1, xtensa_submask0 };\r\n+static xtensa_reg_mask_t xtensa_submask1[] = { { 75, 1, 1 } };\r\n+static const xtensa_mask_t xtensa_mask1 = { 1, xtensa_submask1 };\r\n+static xtensa_reg_mask_t xtensa_submask2[] = { { 75, 2, 1 } };\r\n+static const xtensa_mask_t xtensa_mask2 = { 1, xtensa_submask2 };\r\n+static xtensa_reg_mask_t xtensa_submask3[] = { { 75, 3, 1 } };\r\n+static const xtensa_mask_t xtensa_mask3 = { 1, xtensa_submask3 };\r\n+static xtensa_reg_mask_t xtensa_submask4[] = { { 75, 4, 1 } };\r\n+static const xtensa_mask_t xtensa_mask4 = { 1, xtensa_submask4 };\r\n+static xtensa_reg_mask_t xtensa_submask5[] = { { 75, 5, 1 } };\r\n+static const xtensa_mask_t xtensa_mask5 = { 1, xtensa_submask5 };\r\n+static xtensa_reg_mask_t xtensa_submask6[] = { { 75, 6, 1 } };\r\n+static const xtensa_mask_t xtensa_mask6 = { 1, xtensa_submask6 };\r\n+static xtensa_reg_mask_t xtensa_submask7[] = { { 75, 7, 1 } };\r\n+static const xtensa_mask_t xtensa_mask7 = { 1, xtensa_submask7 };\r\n+static xtensa_reg_mask_t xtensa_submask8[] = { { 75, 8, 1 } };\r\n+static const xtensa_mask_t xtensa_mask8 = { 1, xtensa_submask8 };\r\n+static xtensa_reg_mask_t xtensa_submask9[] = { { 75, 9, 1 } };\r\n+static const xtensa_mask_t xtensa_mask9 = { 1, xtensa_submask9 };\r\n+static xtensa_reg_mask_t xtensa_submask10[] = { { 75, 10, 1 } };\r\n+static const xtensa_mask_t xtensa_mask10 = { 1, xtensa_submask10 };\r\n+static xtensa_reg_mask_t xtensa_submask11[] = { { 75, 11, 1 } };\r\n+static const xtensa_mask_t xtensa_mask11 = { 1, xtensa_submask11 };\r\n+static xtensa_reg_mask_t xtensa_submask12[] = { { 75, 12, 1 } };\r\n+static const xtensa_mask_t xtensa_mask12 = { 1, xtensa_submask12 };\r\n+static xtensa_reg_mask_t xtensa_submask13[] = { { 75, 13, 1 } };\r\n+static const xtensa_mask_t xtensa_mask13 = { 1, xtensa_submask13 };\r\n+static xtensa_reg_mask_t xtensa_submask14[] = { { 75, 14, 1 } };\r\n+static const xtensa_mask_t xtensa_mask14 = { 1, xtensa_submask14 };\r\n+static xtensa_reg_mask_t xtensa_submask15[] = { { 75, 15, 1 } };\r\n+static const xtensa_mask_t xtensa_mask15 = { 1, xtensa_submask15 };\r\n+static xtensa_reg_mask_t xtensa_submask16[] = { { 73, 0, 4 } };\r\n+static const xtensa_mask_t xtensa_mask16 = { 1, xtensa_submask16 };\r\n+static xtensa_reg_mask_t xtensa_submask17[] = { { 73, 5, 1 } };\r\n+static const xtensa_mask_t xtensa_mask17 = { 1, xtensa_submask17 };\r\n+static xtensa_reg_mask_t xtensa_submask18[] = { { 73, 18, 1 } };\r\n+static const xtensa_mask_t xtensa_mask18 = { 1, xtensa_submask18 };\r\n+static xtensa_reg_mask_t xtensa_submask19[] = { { 73, 4, 1 } };\r\n+static const xtensa_mask_t xtensa_mask19 = { 1, xtensa_submask19 };\r\n+static xtensa_reg_mask_t xtensa_submask20[] = { { 73, 16, 2 } };\r\n+static const xtensa_mask_t xtensa_mask20 = { 1, xtensa_submask20 };\r\n+static xtensa_reg_mask_t xtensa_submask21[] = { { 73, 8, 4 } };\r\n+static const xtensa_mask_t xtensa_mask21 = { 1, xtensa_submask21 };\r\n+static xtensa_reg_mask_t xtensa_submask22[] = { { 77, 0, 32 }, { 78,\r\n0, 8 } };\r\n+static const xtensa_mask_t xtensa_mask22 = { 2, xtensa_submask22 };\r\n+static xtensa_reg_mask_t xtensa_submask23[] = { { 144, 8, 4 } };\r\n+static const xtensa_mask_t xtensa_mask23 = { 1, xtensa_submask23 };\r\n+static xtensa_reg_mask_t xtensa_submask24[] = { { 84, 0, 32 }, { 85,\r\n0, 32 } };\r\n+static const xtensa_mask_t xtensa_mask24 = { 2, xtensa_submask24 };\r\n+static xtensa_reg_mask_t xtensa_submask25[] = { { 103, 0, 2 } };\r\n+static const xtensa_mask_t xtensa_mask25 = { 1, xtensa_submask25 };\r\n+static xtensa_reg_mask_t xtensa_submask26[] = { { 103, 6, 1 } };\r\n+static const xtensa_mask_t xtensa_mask26 = { 1, xtensa_submask26 };\r\n+static xtensa_reg_mask_t xtensa_submask27[] = { { 103, 5, 1 } };\r\n+static const xtensa_mask_t xtensa_mask27 = { 1, xtensa_submask27 };\r\n+static xtensa_reg_mask_t xtensa_submask28[] = { { 103, 4, 1 } };\r\n+static const xtensa_mask_t xtensa_mask28 = { 1, xtensa_submask28 };\r\n+static xtensa_reg_mask_t xtensa_submask29[] = { { 103, 3, 1 } };\r\n+static const xtensa_mask_t xtensa_mask29 = { 1, xtensa_submask29 };\r\n+static xtensa_reg_mask_t xtensa_submask30[] = { { 103, 2, 1 } };\r\n+static const xtensa_mask_t xtensa_mask30 = { 1, xtensa_submask30 };\r\n+static xtensa_reg_mask_t xtensa_submask31[] = { { 104, 11, 1 } };\r\n+static const xtensa_mask_t xtensa_mask31 = { 1, xtensa_submask31 };\r\n+static xtensa_reg_mask_t xtensa_submask32[] = { { 104, 10, 1 } };\r\n+static const xtensa_mask_t xtensa_mask32 = { 1, xtensa_submask32 };\r\n+static xtensa_reg_mask_t xtensa_submask33[] = { { 104, 9, 1 } };\r\n+static const xtensa_mask_t xtensa_mask33 = { 1, xtensa_submask33 };\r\n+static xtensa_reg_mask_t xtensa_submask34[] = { { 104, 8, 1 } };\r\n+static const xtensa_mask_t xtensa_mask34 = { 1, xtensa_submask34 };\r\n+static xtensa_reg_mask_t xtensa_submask35[] = { { 104, 7, 1 } };\r\n+static const xtensa_mask_t xtensa_mask35 = { 1, xtensa_submask35 };\r\n+static xtensa_reg_mask_t xtensa_submask36[] = { { 103, 12, 20 } };\r\n+static const xtensa_mask_t xtensa_mask36 = { 1, xtensa_submask36 };\r\n+static xtensa_reg_mask_t xtensa_submask37[] = { { 104, 12, 20 } };\r\n+static const xtensa_mask_t xtensa_mask37 = { 1, xtensa_submask37 };\r\n+static xtensa_reg_mask_t xtensa_submask38[] = { { 103, 7, 5 } };\r\n+static const xtensa_mask_t xtensa_mask38 = { 1, xtensa_submask38 };\r\n+static xtensa_reg_mask_t xtensa_submask39[] = { { 104, 0, 7 } };\r\n+static const xtensa_mask_t xtensa_mask39 = { 1, xtensa_submask39 };\r\n+\r\n+\r\n+/* Register map. */\r\n+static xtensa_register_t rmap[] = \r\n+{\r\n+ /* idx ofs bi sz al targno flags cp typ group name */\r\n+ XTREG( 0, 0,32, 4, 4,0x0020,0x0006,-2, 9,0x0100,pc, \r\n0,0,0,0,0,0)\r\n+ XTREG( 1, 4,32, 4, 4,0x0100,0x0006,-2, 1,0x0002,ar0, \r\n0,0,0,0,0,0)\r\n+ XTREG( 2, 8,32, 4, 4,0x0101,0x0006,-2, 1,0x0002,ar1, \r\n0,0,0,0,0,0)\r\n+ XTREG( 3, 12,32, 4, 4,0x0102,0x0006,-2, 1,0x0002,ar2, \r\n0,0,0,0,0,0)\r\n+ XTREG( 4, 16,32, 4, 4,0x0103,0x0006,-2, 1,0x0002,ar3, \r\n0,0,0,0,0,0)\r\n+ XTREG( 5, 20,32, 4, 4,0x0104,0x0006,-2, 1,0x0002,ar4, \r\n0,0,0,0,0,0)\r\n+ XTREG( 6, 24,32, 4, 4,0x0105,0x0006,-2, 1,0x0002,ar5, \r\n0,0,0,0,0,0)\r\n+ XTREG( 7, 28,32, 4, 4,0x0106,0x0006,-2, 1,0x0002,ar6, \r\n0,0,0,0,0,0)\r\n+ XTREG( 8, 32,32, 4, 4,0x0107,0x0006,-2, 1,0x0002,ar7, \r\n0,0,0,0,0,0)\r\n+ XTREG( 9, 36,32, 4, 4,0x0108,0x0006,-2, 1,0x0002,ar8, \r\n0,0,0,0,0,0)\r\n+ XTREG( 10, 40,32, 4, 4,0x0109,0x0006,-2, 1,0x0002,ar9, \r\n0,0,0,0,0,0)\r\n+ XTREG( 11, 44,32, 4, 4,0x010a,0x0006,-2, 1,0x0002,ar10, \r\n0,0,0,0,0,0)\r\n+ XTREG( 12, 48,32, 4, 4,0x010b,0x0006,-2, 1,0x0002,ar11, \r\n0,0,0,0,0,0)\r\n+ XTREG( 13, 52,32, 4, 4,0x010c,0x0006,-2, 1,0x0002,ar12, \r\n0,0,0,0,0,0)\r\n+ XTREG( 14, 56,32, 4, 4,0x010d,0x0006,-2, 1,0x0002,ar13, \r\n0,0,0,0,0,0)\r\n+ XTREG( 15, 60,32, 4, 4,0x010e,0x0006,-2, 1,0x0002,ar14, \r\n0,0,0,0,0,0)\r\n+ XTREG( 16, 64,32, 4, 4,0x010f,0x0006,-2, 1,0x0002,ar15, \r\n0,0,0,0,0,0)\r\n+ XTREG( 17, 68,32, 4, 4,0x0110,0x0006,-2, 1,0x0002,ar16, \r\n0,0,0,0,0,0)\r\n+ XTREG( 18, 72,32, 4, 4,0x0111,0x0006,-2, 1,0x0002,ar17, \r\n0,0,0,0,0,0)\r\n+ XTREG( 19, 76,32, 4, 4,0x0112,0x0006,-2, 1,0x0002,ar18, \r\n0,0,0,0,0,0)\r\n+ XTREG( 20, 80,32, 4, 4,0x0113,0x0006,-2, 1,0x0002,ar19, \r\n0,0,0,0,0,0)\r\n+ XTREG( 21, 84,32, 4, 4,0x0114,0x0006,-2, 1,0x0002,ar20, \r\n0,0,0,0,0,0)\r\n+ XTREG( 22, 88,32, 4, 4,0x0115,0x0006,-2, 1,0x0002,ar21, \r\n0,0,0,0,0,0)\r\n+ XTREG( 23, 92,32, 4, 4,0x0116,0x0006,-2, 1,0x0002,ar22, \r\n0,0,0,0,0,0)\r\n+ XTREG( 24, 96,32, 4, 4,0x0117,0x0006,-2, 1,0x0002,ar23, \r\n0,0,0,0,0,0)\r\n+ XTREG( 25,100,32, 4, 4,0x0118,0x0006,-2, 1,0x0002,ar24, \r\n0,0,0,0,0,0)\r\n+ XTREG( 26,104,32, 4, 4,0x0119,0x0006,-2, 1,0x0002,ar25, \r\n0,0,0,0,0,0)\r\n+ XTREG( 27,108,32, 4, 4,0x011a,0x0006,-2, 1,0x0002,ar26, \r\n0,0,0,0,0,0)\r\n+ XTREG( 28,112,32, 4, 4,0x011b,0x0006,-2, 1,0x0002,ar27, \r\n0,0,0,0,0,0)\r\n+ XTREG( 29,116,32, 4, 4,0x011c,0x0006,-2, 1,0x0002,ar28, \r\n0,0,0,0,0,0)\r\n+ XTREG( 30,120,32, 4, 4,0x011d,0x0006,-2, 1,0x0002,ar29, \r\n0,0,0,0,0,0)\r\n+ XTREG( 31,124,32, 4, 4,0x011e,0x0006,-2, 1,0x0002,ar30, \r\n0,0,0,0,0,0)\r\n+ XTREG( 32,128,32, 4, 4,0x011f,0x0006,-2, 1,0x0002,ar31, \r\n0,0,0,0,0,0)\r\n+ XTREG( 33,132,32, 4, 4,0x0120,0x0006,-2, 1,0x0002,ar32, \r\n0,0,0,0,0,0)\r\n+ XTREG( 34,136,32, 4, 4,0x0121,0x0006,-2, 1,0x0002,ar33, \r\n0,0,0,0,0,0)\r\n+ XTREG( 35,140,32, 4, 4,0x0122,0x0006,-2, 1,0x0002,ar34, \r\n0,0,0,0,0,0)\r\n+ XTREG( 36,144,32, 4, 4,0x0123,0x0006,-2, 1,0x0002,ar35, \r\n0,0,0,0,0,0)\r\n+ XTREG( 37,148,32, 4, 4,0x0124,0x0006,-2, 1,0x0002,ar36, \r\n0,0,0,0,0,0)\r\n+ XTREG( 38,152,32, 4, 4,0x0125,0x0006,-2, 1,0x0002,ar37, \r\n0,0,0,0,0,0)\r\n+ XTREG( 39,156,32, 4, 4,0x0126,0x0006,-2, 1,0x0002,ar38, \r\n0,0,0,0,0,0)\r\n+ XTREG( 40,160,32, 4, 4,0x0127,0x0006,-2, 1,0x0002,ar39, \r\n0,0,0,0,0,0)\r\n+ XTREG( 41,164,32, 4, 4,0x0128,0x0006,-2, 1,0x0002,ar40, \r\n0,0,0,0,0,0)\r\n+ XTREG( 42,168,32, 4, 4,0x0129,0x0006,-2, 1,0x0002,ar41, \r\n0,0,0,0,0,0)\r\n+ XTREG( 43,172,32, 4, 4,0x012a,0x0006,-2, 1,0x0002,ar42, \r\n0,0,0,0,0,0)\r\n+ XTREG( 44,176,32, 4, 4,0x012b,0x0006,-2, 1,0x0002,ar43, \r\n0,0,0,0,0,0)\r\n+ XTREG( 45,180,32, 4, 4,0x012c,0x0006,-2, 1,0x0002,ar44, \r\n0,0,0,0,0,0)\r\n+ XTREG( 46,184,32, 4, 4,0x012d,0x0006,-2, 1,0x0002,ar45, \r\n0,0,0,0,0,0)\r\n+ XTREG( 47,188,32, 4, 4,0x012e,0x0006,-2, 1,0x0002,ar46, \r\n0,0,0,0,0,0)\r\n+ XTREG( 48,192,32, 4, 4,0x012f,0x0006,-2, 1,0x0002,ar47, \r\n0,0,0,0,0,0)\r\n+ XTREG( 49,196,32, 4, 4,0x0130,0x0006,-2, 1,0x0002,ar48, \r\n0,0,0,0,0,0)\r\n+ XTREG( 50,200,32, 4, 4,0x0131,0x0006,-2, 1,0x0002,ar49, \r\n0,0,0,0,0,0)\r\n+ XTREG( 51,204,32, 4, 4,0x0132,0x0006,-2, 1,0x0002,ar50, \r\n0,0,0,0,0,0)\r\n+ XTREG( 52,208,32, 4, 4,0x0133,0x0006,-2, 1,0x0002,ar51, \r\n0,0,0,0,0,0)\r\n+ XTREG( 53,212,32, 4, 4,0x0134,0x0006,-2, 1,0x0002,ar52, \r\n0,0,0,0,0,0)\r\n+ XTREG( 54,216,32, 4, 4,0x0135,0x0006,-2, 1,0x0002,ar53, \r\n0,0,0,0,0,0)\r\n+ XTREG( 55,220,32, 4, 4,0x0136,0x0006,-2, 1,0x0002,ar54, \r\n0,0,0,0,0,0)\r\n+ XTREG( 56,224,32, 4, 4,0x0137,0x0006,-2, 1,0x0002,ar55, \r\n0,0,0,0,0,0)\r\n+ XTREG( 57,228,32, 4, 4,0x0138,0x0006,-2, 1,0x0002,ar56, \r\n0,0,0,0,0,0)\r\n+ XTREG( 58,232,32, 4, 4,0x0139,0x0006,-2, 1,0x0002,ar57, \r\n0,0,0,0,0,0)\r\n+ XTREG( 59,236,32, 4, 4,0x013a,0x0006,-2, 1,0x0002,ar58, \r\n0,0,0,0,0,0)\r\n+ XTREG( 60,240,32, 4, 4,0x013b,0x0006,-2, 1,0x0002,ar59, \r\n0,0,0,0,0,0)\r\n+ XTREG( 61,244,32, 4, 4,0x013c,0x0006,-2, 1,0x0002,ar60, \r\n0,0,0,0,0,0)\r\n+ XTREG( 62,248,32, 4, 4,0x013d,0x0006,-2, 1,0x0002,ar61, \r\n0,0,0,0,0,0)\r\n+ XTREG( 63,252,32, 4, 4,0x013e,0x0006,-2, 1,0x0002,ar62, \r\n0,0,0,0,0,0)\r\n+ XTREG( 64,256,32, 4, 4,0x013f,0x0006,-2, 1,0x0002,ar63, \r\n0,0,0,0,0,0)\r\n+ XTREG( 65,260,32, 4, 4,0x0200,0x0006,-2, 2,0x1100,lbeg, \r\n0,0,0,0,0,0)\r\n+ XTREG( 66,264,32, 4, 4,0x0201,0x0006,-2, 2,0x1100,lend, \r\n0,0,0,0,0,0)\r\n+ XTREG( 67,268,32, 4, 4,0x0202,0x0006,-2, 2,0x1100,lcount, \r\n0,0,0,0,0,0)\r\n+ XTREG( 68,272, 6, 4, 4,0x0203,0x0006,-2, 2,0x1100,sar, \r\n0,0,0,0,0,0)\r\n+ XTREG( 69,276, 4, 4, 4,0x0248,0x0006,-2, 2,0x1002,windowbase, \r\n0,0,0,0,0,0)\r\n+ XTREG( 70,280,16, 4, 4,0x0249,0x0006,-2, 2,0x1002,windowstart,\r\n0,0,0,0,0,0)\r\n+ XTREG( 71,284,32, 4, 4,0x02b0,0x0002,-2, 2,0x1000,configid0, \r\n0,0,0,0,0,0)\r\n+ XTREG( 72,288,32, 4, 4,0x02d0,0x0002,-2, 2,0x1000,configid1, \r\n0,0,0,0,0,0)\r\n+ XTREG( 73,292,19, 4, 4,0x02e6,0x0006,-2, 2,0x1100,ps, \r\n0,0,0,0,0,0)\r\n+ XTREG( 74,296,32, 4, 4,0x03e7,0x0006,-2, 3,0x0110,threadptr, \r\n0,0,0,0,0,0)\r\n+ XTREG( 75,300,16, 4, 4,0x0204,0x0006,-1, 2,0x1100,br, \r\n0,0,0,0,0,0)\r\n+ XTREG( 76,304,32, 4, 4,0x020c,0x0006,-1, 2,0x1100,scompare1, \r\n0,0,0,0,0,0)\r\n+ XTREG( 77,308,32, 4, 4,0x0210,0x0006,-1, 2,0x1100,acclo, \r\n0,0,0,0,0,0)\r\n+ XTREG( 78,312, 8, 4, 4,0x0211,0x0006,-1, 2,0x1100,acchi, \r\n0,0,0,0,0,0)\r\n+ XTREG( 79,316,32, 4, 4,0x0220,0x0006,-1, 2,0x1100,m0, \r\n0,0,0,0,0,0)\r\n+ XTREG( 80,320,32, 4, 4,0x0221,0x0006,-1, 2,0x1100,m1, \r\n0,0,0,0,0,0)\r\n+ XTREG( 81,324,32, 4, 4,0x0222,0x0006,-1, 2,0x1100,m2, \r\n0,0,0,0,0,0)\r\n+ XTREG( 82,328,32, 4, 4,0x0223,0x0006,-1, 2,0x1100,m3, \r\n0,0,0,0,0,0)\r\n+ XTREG( 83,332,32, 4, 4,0x03e6,0x000e,-1, 3,0x0110,expstate, \r\n0,0,0,0,0,0)\r\n+ XTREG( 84,336,32, 4, 4,0x03ea,0x0006,-1, 3,0x0100,f64r_lo, \r\n0,0,0,0,0,0)\r\n+ XTREG( 85,340,32, 4, 4,0x03eb,0x0006,-1, 3,0x0100,f64r_hi, \r\n0,0,0,0,0,0)\r\n+ XTREG( 86,344,32, 4, 4,0x03ec,0x0006,-1, 3,0x0110,f64s, \r\n0,0,0,0,0,0)\r\n+ XTREG( 87,348,32, 4, 4,0x0030,0x0006, 0, 4,0x0401,f0,\r\n+ \"03:03:44:00\",\"03:03:04:00\",0,0,0,0)\r\n+ XTREG( 88,352,32, 4, 4,0x0031,0x0006, 0, 4,0x0401,f1,\r\n+ \"03:13:44:00\",\"03:13:04:00\",0,0,0,0)\r\n+ XTREG( 89,356,32, 4, 4,0x0032,0x0006, 0, 4,0x0401,f2,\r\n+ \"03:23:44:00\",\"03:23:04:00\",0,0,0,0)\r\n+ XTREG( 90,360,32, 4, 4,0x0033,0x0006, 0, 4,0x0401,f3,\r\n+ \"03:33:44:00\",\"03:33:04:00\",0,0,0,0)\r\n+ XTREG( 91,364,32, 4, 4,0x0034,0x0006, 0, 4,0x0401,f4,\r\n+ \"03:43:44:00\",\"03:43:04:00\",0,0,0,0)\r\n+ XTREG( 92,368,32, 4, 4,0x0035,0x0006, 0, 4,0x0401,f5,\r\n+ \"03:53:44:00\",\"03:53:04:00\",0,0,0,0)\r\n+ XTREG( 93,372,32, 4, 4,0x0036,0x0006, 0, 4,0x0401,f6,\r\n+ \"03:63:44:00\",\"03:63:04:00\",0,0,0,0)\r\n+ XTREG( 94,376,32, 4, 4,0x0037,0x0006, 0, 4,0x0401,f7,\r\n+ \"03:73:44:00\",\"03:73:04:00\",0,0,0,0)\r\n+ XTREG( 95,380,32, 4, 4,0x0038,0x0006, 0, 4,0x0401,f8,\r\n+ \"03:83:44:00\",\"03:83:04:00\",0,0,0,0)\r\n+ XTREG( 96,384,32, 4, 4,0x0039,0x0006, 0, 4,0x0401,f9,\r\n+ \"03:93:44:00\",\"03:93:04:00\",0,0,0,0)\r\n+ XTREG( 97,388,32, 4, 4,0x003a,0x0006, 0, 4,0x0401,f10,\r\n+ \"03:a3:44:00\",\"03:a3:04:00\",0,0,0,0)\r\n+ XTREG( 98,392,32, 4, 4,0x003b,0x0006, 0, 4,0x0401,f11,\r\n+ \"03:b3:44:00\",\"03:b3:04:00\",0,0,0,0)\r\n+ XTREG( 99,396,32, 4, 4,0x003c,0x0006, 0, 4,0x0401,f12,\r\n+ \"03:c3:44:00\",\"03:c3:04:00\",0,0,0,0)\r\n+ XTREG(100,400,32, 4, 4,0x003d,0x0006, 0, 4,0x0401,f13,\r\n+ \"03:d3:44:00\",\"03:d3:04:00\",0,0,0,0)\r\n+ XTREG(101,404,32, 4, 4,0x003e,0x0006, 0, 4,0x0401,f14,\r\n+ \"03:e3:44:00\",\"03:e3:04:00\",0,0,0,0)\r\n+ XTREG(102,408,32, 4, 4,0x003f,0x0006, 0, 4,0x0401,f15,\r\n+ \"03:f3:44:00\",\"03:f3:04:00\",0,0,0,0)\r\n+ XTREG(103,412,32, 4, 4,0x03e8,0x0006, 0, 3,0x0100,fcr, \r\n0,0,0,0,0,0)\r\n+ XTREG(104,416,32, 4, 4,0x03e9,0x0006, 0, 3,0x0100,fsr, \r\n0,0,0,0,0,0)\r\n+ XTREG(105,420,32, 4, 4,0x0259,0x000d,-2, 2,0x1000,mmid, \r\n0,0,0,0,0,0)\r\n+ XTREG(106,424, 2, 4, 4,0x0260,0x0007,-2,\r\n2,0x1000,ibreakenable,0,0,0,0,0,0)\r\n+ XTREG(107,428, 1, 4, 4,0x0261,0x0007,-2, 2,0x1000,memctl, \r\n0,0,0,0,0,0)\r\n+ XTREG(108,432, 6, 4, 4,0x0263,0x0007,-2, 2,0x1000,atomctl, \r\n0,0,0,0,0,0)\r\n+ XTREG(109,436,32, 4, 4,0x0268,0x0007,-2, 2,0x1000,ddr, \r\n0,0,0,0,0,0)\r\n+ XTREG(110,440,32, 4, 4,0x0280,0x0007,-2, 2,0x1000,ibreaka0, \r\n0,0,0,0,0,0)\r\n+ XTREG(111,444,32, 4, 4,0x0281,0x0007,-2, 2,0x1000,ibreaka1, \r\n0,0,0,0,0,0)\r\n+ XTREG(112,448,32, 4, 4,0x0290,0x0007,-2, 2,0x1000,dbreaka0, \r\n0,0,0,0,0,0)\r\n+ XTREG(113,452,32, 4, 4,0x0291,0x0007,-2, 2,0x1000,dbreaka1, \r\n0,0,0,0,0,0)\r\n+ XTREG(114,456,32, 4, 4,0x02a0,0x0007,-2, 2,0x1000,dbreakc0, \r\n0,0,0,0,0,0)\r\n+ XTREG(115,460,32, 4, 4,0x02a1,0x0007,-2, 2,0x1000,dbreakc1, \r\n0,0,0,0,0,0)\r\n+ XTREG(116,464,32, 4, 4,0x02b1,0x0007,-2, 2,0x1000,epc1, \r\n0,0,0,0,0,0)\r\n+ XTREG(117,468,32, 4, 4,0x02b2,0x0007,-2, 2,0x1000,epc2, \r\n0,0,0,0,0,0)\r\n+ XTREG(118,472,32, 4, 4,0x02b3,0x0007,-2, 2,0x1000,epc3, \r\n0,0,0,0,0,0)\r\n+ XTREG(119,476,32, 4, 4,0x02b4,0x0007,-2, 2,0x1000,epc4, \r\n0,0,0,0,0,0)\r\n+ XTREG(120,480,32, 4, 4,0x02b5,0x0007,-2, 2,0x1000,epc5, \r\n0,0,0,0,0,0)\r\n+ XTREG(121,484,32, 4, 4,0x02b6,0x0007,-2, 2,0x1000,epc6, \r\n0,0,0,0,0,0)\r\n+ XTREG(122,488,32, 4, 4,0x02b7,0x0007,-2, 2,0x1000,epc7, \r\n0,0,0,0,0,0)\r\n+ XTREG(123,492,32, 4, 4,0x02c0,0x0007,-2, 2,0x1000,depc, \r\n0,0,0,0,0,0)\r\n+ XTREG(124,496,19, 4, 4,0x02c2,0x0007,-2, 2,0x1000,eps2, \r\n0,0,0,0,0,0)\r\n+ XTREG(125,500,19, 4, 4,0x02c3,0x0007,-2, 2,0x1000,eps3, \r\n0,0,0,0,0,0)\r\n+ XTREG(126,504,19, 4, 4,0x02c4,0x0007,-2, 2,0x1000,eps4, \r\n0,0,0,0,0,0)\r\n+ XTREG(127,508,19, 4, 4,0x02c5,0x0007,-2, 2,0x1000,eps5, \r\n0,0,0,0,0,0)\r\n+ XTREG(128,512,19, 4, 4,0x02c6,0x0007,-2, 2,0x1000,eps6, \r\n0,0,0,0,0,0)\r\n+ XTREG(129,516,19, 4, 4,0x02c7,0x0007,-2, 2,0x1000,eps7, \r\n0,0,0,0,0,0)\r\n+ XTREG(130,520,32, 4, 4,0x02d1,0x0007,-2, 2,0x1000,excsave1, \r\n0,0,0,0,0,0)\r\n+ XTREG(131,524,32, 4, 4,0x02d2,0x0007,-2, 2,0x1000,excsave2, \r\n0,0,0,0,0,0)\r\n+ XTREG(132,528,32, 4, 4,0x02d3,0x0007,-2, 2,0x1000,excsave3, \r\n0,0,0,0,0,0)\r\n+ XTREG(133,532,32, 4, 4,0x02d4,0x0007,-2, 2,0x1000,excsave4, \r\n0,0,0,0,0,0)\r\n+ XTREG(134,536,32, 4, 4,0x02d5,0x0007,-2, 2,0x1000,excsave5, \r\n0,0,0,0,0,0)\r\n+ XTREG(135,540,32, 4, 4,0x02d6,0x0007,-2, 2,0x1000,excsave6, \r\n0,0,0,0,0,0)\r\n+ XTREG(136,544,32, 4, 4,0x02d7,0x0007,-2, 2,0x1000,excsave7, \r\n0,0,0,0,0,0)\r\n+ XTREG(137,548, 8, 4, 4,0x02e0,0x0007,-2, 2,0x1000,cpenable, \r\n0,0,0,0,0,0)\r\n+ XTREG(138,552,32, 4, 4,0x02e2,0x000b,-2, 2,0x1000,interrupt, \r\n0,0,0,0,0,0)\r\n+ XTREG(139,556,32, 4, 4,0x02e2,0x000d,-2, 2,0x1000,intset, \r\n0,0,0,0,0,0)\r\n+ XTREG(140,560,32, 4, 4,0x02e3,0x000d,-2, 2,0x1000,intclear, \r\n0,0,0,0,0,0)\r\n+ XTREG(141,564,32, 4, 4,0x02e4,0x0007,-2, 2,0x1000,intenable, \r\n0,0,0,0,0,0)\r\n+ XTREG(142,568,32, 4, 4,0x02e7,0x0007,-2, 2,0x1000,vecbase, \r\n0,0,0,0,0,0)\r\n+ XTREG(143,572, 6, 4, 4,0x02e8,0x0007,-2, 2,0x1000,exccause, \r\n0,0,0,0,0,0)\r\n+ XTREG(144,576,12, 4, 4,0x02e9,0x0003,-2, 2,0x1000,debugcause, \r\n0,0,0,0,0,0)\r\n+ XTREG(145,580,32, 4, 4,0x02ea,0x000f,-2, 2,0x1000,ccount, \r\n0,0,0,0,0,0)\r\n+ XTREG(146,584,32, 4, 4,0x02eb,0x0003,-2, 2,0x1000,prid, \r\n0,0,0,0,0,0)\r\n+ XTREG(147,588,32, 4, 4,0x02ec,0x000f,-2, 2,0x1000,icount, \r\n0,0,0,0,0,0)\r\n+ XTREG(148,592, 4, 4, 4,0x02ed,0x0007,-2, 2,0x1000,icountlevel,\r\n0,0,0,0,0,0)\r\n+ XTREG(149,596,32, 4, 4,0x02ee,0x0007,-2, 2,0x1000,excvaddr, \r\n0,0,0,0,0,0)\r\n+ XTREG(150,600,32, 4, 4,0x02f0,0x000f,-2, 2,0x1000,ccompare0, \r\n0,0,0,0,0,0)\r\n+ XTREG(151,604,32, 4, 4,0x02f1,0x000f,-2, 2,0x1000,ccompare1, \r\n0,0,0,0,0,0)\r\n+ XTREG(152,608,32, 4, 4,0x02f2,0x000f,-2, 2,0x1000,ccompare2, \r\n0,0,0,0,0,0)\r\n+ XTREG(153,612,32, 4, 4,0x02f4,0x0007,-2, 2,0x1000,misc0, \r\n0,0,0,0,0,0)\r\n+ XTREG(154,616,32, 4, 4,0x02f5,0x0007,-2, 2,0x1000,misc1, \r\n0,0,0,0,0,0)\r\n+ XTREG(155,620,32, 4, 4,0x02f6,0x0007,-2, 2,0x1000,misc2, \r\n0,0,0,0,0,0)\r\n+ XTREG(156,624,32, 4, 4,0x02f7,0x0007,-2, 2,0x1000,misc3, \r\n0,0,0,0,0,0)\r\n+ XTREG(157,628,32, 4, 4,0x0000,0x0006,-2, 8,0x0100,a0, \r\n0,0,0,0,0,0)\r\n+ XTREG(158,632,32, 4, 4,0x0001,0x0006,-2, 8,0x0100,a1, \r\n0,0,0,0,0,0)\r\n+ XTREG(159,636,32, 4, 4,0x0002,0x0006,-2, 8,0x0100,a2, \r\n0,0,0,0,0,0)\r\n+ XTREG(160,640,32, 4, 4,0x0003,0x0006,-2, 8,0x0100,a3, \r\n0,0,0,0,0,0)\r\n+ XTREG(161,644,32, 4, 4,0x0004,0x0006,-2, 8,0x0100,a4, \r\n0,0,0,0,0,0)\r\n+ XTREG(162,648,32, 4, 4,0x0005,0x0006,-2, 8,0x0100,a5, \r\n0,0,0,0,0,0)\r\n+ XTREG(163,652,32, 4, 4,0x0006,0x0006,-2, 8,0x0100,a6, \r\n0,0,0,0,0,0)\r\n+ XTREG(164,656,32, 4, 4,0x0007,0x0006,-2, 8,0x0100,a7, \r\n0,0,0,0,0,0)\r\n+ XTREG(165,660,32, 4, 4,0x0008,0x0006,-2, 8,0x0100,a8, \r\n0,0,0,0,0,0)\r\n+ XTREG(166,664,32, 4, 4,0x0009,0x0006,-2, 8,0x0100,a9, \r\n0,0,0,0,0,0)\r\n+ XTREG(167,668,32, 4, 4,0x000a,0x0006,-2, 8,0x0100,a10, \r\n0,0,0,0,0,0)\r\n+ XTREG(168,672,32, 4, 4,0x000b,0x0006,-2, 8,0x0100,a11, \r\n0,0,0,0,0,0)\r\n+ XTREG(169,676,32, 4, 4,0x000c,0x0006,-2, 8,0x0100,a12, \r\n0,0,0,0,0,0)\r\n+ XTREG(170,680,32, 4, 4,0x000d,0x0006,-2, 8,0x0100,a13, \r\n0,0,0,0,0,0)\r\n+ XTREG(171,684,32, 4, 4,0x000e,0x0006,-2, 8,0x0100,a14, \r\n0,0,0,0,0,0)\r\n+ XTREG(172,688,32, 4, 4,0x000f,0x0006,-2, 8,0x0100,a15, \r\n0,0,0,0,0,0)\r\n+ XTREG(173,692, 1, 1, 1,0x0010,0x0006,-2, 6,0x1010,b0,\r\n+ 0,0,&xtensa_mask0,0,0,0)\r\n+ XTREG(174,693, 1, 1, 1,0x0011,0x0006,-2, 6,0x1010,b1,\r\n+ 0,0,&xtensa_mask1,0,0,0)\r\n+ XTREG(175,694, 1, 1, 1,0x0012,0x0006,-2, 6,0x1010,b2,\r\n+ 0,0,&xtensa_mask2,0,0,0)\r\n+ XTREG(176,695, 1, 1, 1,0x0013,0x0006,-2, 6,0x1010,b3,\r\n+ 0,0,&xtensa_mask3,0,0,0)\r\n+ XTREG(177,696, 1, 1, 1,0x0014,0x0006,-2, 6,0x1010,b4,\r\n+ 0,0,&xtensa_mask4,0,0,0)\r\n+ XTREG(178,697, 1, 1, 1,0x0015,0x0006,-2, 6,0x1010,b5,\r\n+ 0,0,&xtensa_mask5,0,0,0)\r\n+ XTREG(179,698, 1, 1, 1,0x0016,0x0006,-2, 6,0x1010,b6,\r\n+ 0,0,&xtensa_mask6,0,0,0)\r\n+ XTREG(180,699, 1, 1, 1,0x0017,0x0006,-2, 6,0x1010,b7,\r\n+ 0,0,&xtensa_mask7,0,0,0)\r\n+ XTREG(181,700, 1, 1, 1,0x0018,0x0006,-2, 6,0x1010,b8,\r\n+ 0,0,&xtensa_mask8,0,0,0)\r\n+ XTREG(182,701, 1, 1, 1,0x0019,0x0006,-2, 6,0x1010,b9,\r\n+ 0,0,&xtensa_mask9,0,0,0)\r\n+ XTREG(183,702, 1, 1, 1,0x001a,0x0006,-2, 6,0x1010,b10,\r\n+ 0,0,&xtensa_mask10,0,0,0)\r\n+ XTREG(184,703, 1, 1, 1,0x001b,0x0006,-2, 6,0x1010,b11,\r\n+ 0,0,&xtensa_mask11,0,0,0)\r\n+ XTREG(185,704, 1, 1, 1,0x001c,0x0006,-2, 6,0x1010,b12,\r\n+ 0,0,&xtensa_mask12,0,0,0)\r\n+ XTREG(186,705, 1, 1, 1,0x001d,0x0006,-2, 6,0x1010,b13,\r\n+ 0,0,&xtensa_mask13,0,0,0)\r\n+ XTREG(187,706, 1, 1, 1,0x001e,0x0006,-2, 6,0x1010,b14,\r\n+ 0,0,&xtensa_mask14,0,0,0)\r\n+ XTREG(188,707, 1, 1, 1,0x001f,0x0006,-2, 6,0x1010,b15,\r\n+ 0,0,&xtensa_mask15,0,0,0)\r\n+ XTREG(189,708, 4, 4, 4,0x2008,0x0006,-2, 6,0x1010,psintlevel,\r\n+ 0,0,&xtensa_mask16,0,0,0)\r\n+ XTREG(190,712, 1, 4, 4,0x2009,0x0006,-2, 6,0x1010,psum,\r\n+ 0,0,&xtensa_mask17,0,0,0)\r\n+ XTREG(191,716, 1, 4, 4,0x200a,0x0006,-2, 6,0x1010,pswoe,\r\n+ 0,0,&xtensa_mask18,0,0,0)\r\n+ XTREG(192,720, 1, 4, 4,0x200b,0x0006,-2, 6,0x1010,psexcm,\r\n+ 0,0,&xtensa_mask19,0,0,0)\r\n+ XTREG(193,724, 2, 4, 4,0x200c,0x0006,-2, 6,0x1010,pscallinc,\r\n+ 0,0,&xtensa_mask20,0,0,0)\r\n+ XTREG(194,728, 4, 4, 4,0x200d,0x0006,-2, 6,0x1010,psowb,\r\n+ 0,0,&xtensa_mask21,0,0,0)\r\n+ XTREG(195,732,40, 8, 4,0x200e,0x0006,-2, 6,0x1010,acc,\r\n+ 0,0,&xtensa_mask22,0,0,0)\r\n+ XTREG(196,740, 4, 4, 4,0x2013,0x0006,-2, 6,0x1010,dbnum,\r\n+ 0,0,&xtensa_mask23,0,0,0)\r\n+ XTREG(197,744,64, 8, 4,0x2015,0x0006,-2, 5,0x1010,f64r,\r\n+ 0,0,&xtensa_mask24,0,0,0)\r\n+ XTREG(198,752, 2, 4, 4,0x2016,0x0006, 0, 5,0x1010,roundmode,\r\n+ 0,0,&xtensa_mask25,0,0,0)\r\n+ XTREG(199,756, 1, 4, 4,0x2017,0x0006, 0, 5,0x1010,invalidenable,\r\n+ 0,0,&xtensa_mask26,0,0,0)\r\n+ XTREG(200,760, 1, 4, 4,0x2018,0x0006, 0, 5,0x1010,divzeroenable,\r\n+ 0,0,&xtensa_mask27,0,0,0)\r\n+ XTREG(201,764, 1, 4, 4,0x2019,0x0006, 0, 5,0x1010,overflowenable,\r\n+ 0,0,&xtensa_mask28,0,0,0)\r\n+ XTREG(202,768, 1, 4, 4,0x201a,0x0006, 0, 5,0x1010,underflowenable,\r\n+ 0,0,&xtensa_mask29,0,0,0)\r\n+ XTREG(203,772, 1, 4, 4,0x201b,0x0006, 0, 5,0x1010,inexactenable,\r\n+ 0,0,&xtensa_mask30,0,0,0)\r\n+ XTREG(204,776, 1, 4, 4,0x201c,0x0006, 0, 5,0x1010,invalidflag,\r\n+ 0,0,&xtensa_mask31,0,0,0)\r\n+ XTREG(205,780, 1, 4, 4,0x201d,0x0006, 0, 5,0x1010,divzeroflag,\r\n+ 0,0,&xtensa_mask32,0,0,0)\r\n+ XTREG(206,784, 1, 4, 4,0x201e,0x0006, 0, 5,0x1010,overflowflag,\r\n+ 0,0,&xtensa_mask33,0,0,0)\r\n+ XTREG(207,788, 1, 4, 4,0x201f,0x0006, 0, 5,0x1010,underflowflag,\r\n+ 0,0,&xtensa_mask34,0,0,0)\r\n+ XTREG(208,792, 1, 4, 4,0x2020,0x0006, 0, 5,0x1010,inexactflag,\r\n+ 0,0,&xtensa_mask35,0,0,0)\r\n+ XTREG(209,796,20, 4, 4,0x2021,0x0006, 0, 5,0x1010,fpreserved20,\r\n+ 0,0,&xtensa_mask36,0,0,0)\r\n+ XTREG(210,800,20, 4, 4,0x2022,0x0006, 0, 5,0x1010,fpreserved20a,\r\n+ 0,0,&xtensa_mask37,0,0,0)\r\n+ XTREG(211,804, 5, 4, 4,0x2023,0x0006, 0, 5,0x1010,fpreserved5,\r\n+ 0,0,&xtensa_mask38,0,0,0)\r\n+ XTREG_END\r\n+};\r\n+\r\n+xtensa_gdbarch_tdep xtensa_tdep_esp32 (rmap);\r\ndiff --git a/gdb/xtensa-config-esp32s2.c b/gdb/xtensa-config-esp32s2.c\r\nnew file mode 100644\r\nindex 00000000000..a12f129f4d9\r\n--- /dev/null\r\n+++ b/gdb/xtensa-config-esp32s2.c\r\n@@ -0,0 +1,271 @@\r\n+/* Configuration for the Xtensa architecture for GDB, the GNU\r\ndebugger.\r\n+\r\n+ Customer ID=14525; Build=0x787b1; Copyright (c) 2003-2018 Tensilica\r\nInc.\r\n+\r\n+ Permission is hereby granted, free of charge, to any person\r\nobtaining\r\n+ a copy of this software and associated documentation files (the\r\n+ \"Software\"), to deal in the Software without restriction, including\r\n+ without limitation the rights to use, copy, modify, merge, publish,\r\n+ distribute, sublicense, and/or sell copies of the Software, and to\r\n+ permit persons to whom the Software is furnished to do so, subject\r\nto\r\n+ the following conditions:\r\n+\r\n+ The above copyright notice and this permission notice shall be\r\nincluded\r\n+ in all copies or substantial portions of the Software.\r\n+\r\n+ THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\r\n+ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r\n+ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r\nNONINFRINGEMENT.\r\n+ IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR\r\nANY\r\n+ CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF\r\nCONTRACT,\r\n+ TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE\r\n+ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */\r\n+\r\n+#define XTENSA_CONFIG_VERSION 0x60\r\n+\r\n+#include \"defs.h\"\r\n+#include \"xtensa-config.h\"\r\n+#include \"xtensa-tdep.h\"\r\n+\r\n+\r\n+\r\n+/* Masked registers. */\r\n+static xtensa_reg_mask_t xtensa_submask0[] = { { 70, 0, 4 } };\r\n+static const xtensa_mask_t xtensa_mask0 = { 1, xtensa_submask0 };\r\n+static xtensa_reg_mask_t xtensa_submask1[] = { { 70, 5, 1 } };\r\n+static const xtensa_mask_t xtensa_mask1 = { 1, xtensa_submask1 };\r\n+static xtensa_reg_mask_t xtensa_submask2[] = { { 70, 18, 1 } };\r\n+static const xtensa_mask_t xtensa_mask2 = { 1, xtensa_submask2 };\r\n+static xtensa_reg_mask_t xtensa_submask3[] = { { 70, 4, 1 } };\r\n+static const xtensa_mask_t xtensa_mask3 = { 1, xtensa_submask3 };\r\n+static xtensa_reg_mask_t xtensa_submask4[] = { { 70, 16, 2 } };\r\n+static const xtensa_mask_t xtensa_mask4 = { 1, xtensa_submask4 };\r\n+static xtensa_reg_mask_t xtensa_submask5[] = { { 70, 8, 4 } };\r\n+static const xtensa_mask_t xtensa_mask5 = { 1, xtensa_submask5 };\r\n+static xtensa_reg_mask_t xtensa_submask6[] = { { 110, 8, 4 } };\r\n+static const xtensa_mask_t xtensa_mask6 = { 1, xtensa_submask6 };\r\n+\r\n+\r\n+/* Register map. */\r\n+static xtensa_register_t rmap[] = \r\n+{\r\n+ /* idx ofs bi sz al targno flags cp typ group name */\r\n+ XTREG( 0, 0,32, 4, 4,0x0020,0x0006,-2, 9,0x2100,pc, \r\n0,0,0,0,0,0)\r\n+ XTREG( 1, 4,32, 4, 4,0x0100,0x0006,-2, 1,0x0002,ar0, \r\n0,0,0,0,0,0)\r\n+ XTREG( 2, 8,32, 4, 4,0x0101,0x0006,-2, 1,0x0002,ar1, \r\n0,0,0,0,0,0)\r\n+ XTREG( 3, 12,32, 4, 4,0x0102,0x0006,-2, 1,0x0002,ar2, \r\n0,0,0,0,0,0)\r\n+ XTREG( 4, 16,32, 4, 4,0x0103,0x0006,-2, 1,0x0002,ar3, \r\n0,0,0,0,0,0)\r\n+ XTREG( 5, 20,32, 4, 4,0x0104,0x0006,-2, 1,0x0002,ar4, \r\n0,0,0,0,0,0)\r\n+ XTREG( 6, 24,32, 4, 4,0x0105,0x0006,-2, 1,0x0002,ar5, \r\n0,0,0,0,0,0)\r\n+ XTREG( 7, 28,32, 4, 4,0x0106,0x0006,-2, 1,0x0002,ar6, \r\n0,0,0,0,0,0)\r\n+ XTREG( 8, 32,32, 4, 4,0x0107,0x0006,-2, 1,0x0002,ar7, \r\n0,0,0,0,0,0)\r\n+ XTREG( 9, 36,32, 4, 4,0x0108,0x0006,-2, 1,0x0002,ar8, \r\n0,0,0,0,0,0)\r\n+ XTREG( 10, 40,32, 4, 4,0x0109,0x0006,-2, 1,0x0002,ar9, \r\n0,0,0,0,0,0)\r\n+ XTREG( 11, 44,32, 4, 4,0x010a,0x0006,-2, 1,0x0002,ar10, \r\n0,0,0,0,0,0)\r\n+ XTREG( 12, 48,32, 4, 4,0x010b,0x0006,-2, 1,0x0002,ar11, \r\n0,0,0,0,0,0)\r\n+ XTREG( 13, 52,32, 4, 4,0x010c,0x0006,-2, 1,0x0002,ar12, \r\n0,0,0,0,0,0)\r\n+ XTREG( 14, 56,32, 4, 4,0x010d,0x0006,-2, 1,0x0002,ar13, \r\n0,0,0,0,0,0)\r\n+ XTREG( 15, 60,32, 4, 4,0x010e,0x0006,-2, 1,0x0002,ar14, \r\n0,0,0,0,0,0)\r\n+ XTREG( 16, 64,32, 4, 4,0x010f,0x0006,-2, 1,0x0002,ar15, \r\n0,0,0,0,0,0)\r\n+ XTREG( 17, 68,32, 4, 4,0x0110,0x0006,-2, 1,0x0002,ar16, \r\n0,0,0,0,0,0)\r\n+ XTREG( 18, 72,32, 4, 4,0x0111,0x0006,-2, 1,0x0002,ar17, \r\n0,0,0,0,0,0)\r\n+ XTREG( 19, 76,32, 4, 4,0x0112,0x0006,-2, 1,0x0002,ar18, \r\n0,0,0,0,0,0)\r\n+ XTREG( 20, 80,32, 4, 4,0x0113,0x0006,-2, 1,0x0002,ar19, \r\n0,0,0,0,0,0)\r\n+ XTREG( 21, 84,32, 4, 4,0x0114,0x0006,-2, 1,0x0002,ar20, \r\n0,0,0,0,0,0)\r\n+ XTREG( 22, 88,32, 4, 4,0x0115,0x0006,-2, 1,0x0002,ar21, \r\n0,0,0,0,0,0)\r\n+ XTREG( 23, 92,32, 4, 4,0x0116,0x0006,-2, 1,0x0002,ar22, \r\n0,0,0,0,0,0)\r\n+ XTREG( 24, 96,32, 4, 4,0x0117,0x0006,-2, 1,0x0002,ar23, \r\n0,0,0,0,0,0)\r\n+ XTREG( 25,100,32, 4, 4,0x0118,0x0006,-2, 1,0x0002,ar24, \r\n0,0,0,0,0,0)\r\n+ XTREG( 26,104,32, 4, 4,0x0119,0x0006,-2, 1,0x0002,ar25, \r\n0,0,0,0,0,0)\r\n+ XTREG( 27,108,32, 4, 4,0x011a,0x0006,-2, 1,0x0002,ar26, \r\n0,0,0,0,0,0)\r\n+ XTREG( 28,112,32, 4, 4,0x011b,0x0006,-2, 1,0x0002,ar27, \r\n0,0,0,0,0,0)\r\n+ XTREG( 29,116,32, 4, 4,0x011c,0x0006,-2, 1,0x0002,ar28, \r\n0,0,0,0,0,0)\r\n+ XTREG( 30,120,32, 4, 4,0x011d,0x0006,-2, 1,0x0002,ar29, \r\n0,0,0,0,0,0)\r\n+ XTREG( 31,124,32, 4, 4,0x011e,0x0006,-2, 1,0x0002,ar30, \r\n0,0,0,0,0,0)\r\n+ XTREG( 32,128,32, 4, 4,0x011f,0x0006,-2, 1,0x0002,ar31, \r\n0,0,0,0,0,0)\r\n+ XTREG( 33,132,32, 4, 4,0x0120,0x0006,-2, 1,0x0002,ar32, \r\n0,0,0,0,0,0)\r\n+ XTREG( 34,136,32, 4, 4,0x0121,0x0006,-2, 1,0x0002,ar33, \r\n0,0,0,0,0,0)\r\n+ XTREG( 35,140,32, 4, 4,0x0122,0x0006,-2, 1,0x0002,ar34, \r\n0,0,0,0,0,0)\r\n+ XTREG( 36,144,32, 4, 4,0x0123,0x0006,-2, 1,0x0002,ar35, \r\n0,0,0,0,0,0)\r\n+ XTREG( 37,148,32, 4, 4,0x0124,0x0006,-2, 1,0x0002,ar36, \r\n0,0,0,0,0,0)\r\n+ XTREG( 38,152,32, 4, 4,0x0125,0x0006,-2, 1,0x0002,ar37, \r\n0,0,0,0,0,0)\r\n+ XTREG( 39,156,32, 4, 4,0x0126,0x0006,-2, 1,0x0002,ar38, \r\n0,0,0,0,0,0)\r\n+ XTREG( 40,160,32, 4, 4,0x0127,0x0006,-2, 1,0x0002,ar39, \r\n0,0,0,0,0,0)\r\n+ XTREG( 41,164,32, 4, 4,0x0128,0x0006,-2, 1,0x0002,ar40, \r\n0,0,0,0,0,0)\r\n+ XTREG( 42,168,32, 4, 4,0x0129,0x0006,-2, 1,0x0002,ar41, \r\n0,0,0,0,0,0)\r\n+ XTREG( 43,172,32, 4, 4,0x012a,0x0006,-2, 1,0x0002,ar42, \r\n0,0,0,0,0,0)\r\n+ XTREG( 44,176,32, 4, 4,0x012b,0x0006,-2, 1,0x0002,ar43, \r\n0,0,0,0,0,0)\r\n+ XTREG( 45,180,32, 4, 4,0x012c,0x0006,-2, 1,0x0002,ar44, \r\n0,0,0,0,0,0)\r\n+ XTREG( 46,184,32, 4, 4,0x012d,0x0006,-2, 1,0x0002,ar45, \r\n0,0,0,0,0,0)\r\n+ XTREG( 47,188,32, 4, 4,0x012e,0x0006,-2, 1,0x0002,ar46, \r\n0,0,0,0,0,0)\r\n+ XTREG( 48,192,32, 4, 4,0x012f,0x0006,-2, 1,0x0002,ar47, \r\n0,0,0,0,0,0)\r\n+ XTREG( 49,196,32, 4, 4,0x0130,0x0006,-2, 1,0x0002,ar48, \r\n0,0,0,0,0,0)\r\n+ XTREG( 50,200,32, 4, 4,0x0131,0x0006,-2, 1,0x0002,ar49, \r\n0,0,0,0,0,0)\r\n+ XTREG( 51,204,32, 4, 4,0x0132,0x0006,-2, 1,0x0002,ar50, \r\n0,0,0,0,0,0)\r\n+ XTREG( 52,208,32, 4, 4,0x0133,0x0006,-2, 1,0x0002,ar51, \r\n0,0,0,0,0,0)\r\n+ XTREG( 53,212,32, 4, 4,0x0134,0x0006,-2, 1,0x0002,ar52, \r\n0,0,0,0,0,0)\r\n+ XTREG( 54,216,32, 4, 4,0x0135,0x0006,-2, 1,0x0002,ar53, \r\n0,0,0,0,0,0)\r\n+ XTREG( 55,220,32, 4, 4,0x0136,0x0006,-2, 1,0x0002,ar54, \r\n0,0,0,0,0,0)\r\n+ XTREG( 56,224,32, 4, 4,0x0137,0x0006,-2, 1,0x0002,ar55, \r\n0,0,0,0,0,0)\r\n+ XTREG( 57,228,32, 4, 4,0x0138,0x0006,-2, 1,0x0002,ar56, \r\n0,0,0,0,0,0)\r\n+ XTREG( 58,232,32, 4, 4,0x0139,0x0006,-2, 1,0x0002,ar57, \r\n0,0,0,0,0,0)\r\n+ XTREG( 59,236,32, 4, 4,0x013a,0x0006,-2, 1,0x0002,ar58, \r\n0,0,0,0,0,0)\r\n+ XTREG( 60,240,32, 4, 4,0x013b,0x0006,-2, 1,0x0002,ar59, \r\n0,0,0,0,0,0)\r\n+ XTREG( 61,244,32, 4, 4,0x013c,0x0006,-2, 1,0x0002,ar60, \r\n0,0,0,0,0,0)\r\n+ XTREG( 62,248,32, 4, 4,0x013d,0x0006,-2, 1,0x0002,ar61, \r\n0,0,0,0,0,0)\r\n+ XTREG( 63,252,32, 4, 4,0x013e,0x0006,-2, 1,0x0002,ar62, \r\n0,0,0,0,0,0)\r\n+ XTREG( 64,256,32, 4, 4,0x013f,0x0006,-2, 1,0x0002,ar63, \r\n0,0,0,0,0,0)\r\n+ XTREG( 65,260, 6, 4, 4,0x0203,0x0006,-2, 2,0x1100,sar, \r\n0,0,0,0,0,0)\r\n+ XTREG( 66,264, 4, 4, 4,0x0248,0x0006,-2, 2,0x1002,windowbase, \r\n0,0,0,0,0,0)\r\n+ XTREG( 67,268,16, 4, 4,0x0249,0x0006,-2, 2,0x1002,windowstart,\r\n0,0,0,0,0,0)\r\n+ XTREG( 68,272,32, 4, 4,0x02b0,0x0002,-2, 2,0x1000,configid0, \r\n0,0,0,0,0,0)\r\n+ XTREG( 69,276,32, 4, 4,0x02d0,0x0002,-2, 2,0x1000,configid1, \r\n0,0,0,0,0,0)\r\n+ XTREG( 70,280,19, 4, 4,0x02e6,0x0006,-2, 2,0x1100,ps, \r\n0,0,0,0,0,0)\r\n+ XTREG( 71,284,32, 4, 4,0x03e7,0x0006,-2, 3,0x0110,threadptr, \r\n0,0,0,0,0,0)\r\n+ XTREG( 72,288, 8, 4, 4,0x0300,0x000e,-1, 3,0x0210,gpio_out, \r\n0,0,0,0,0,0)\r\n+ XTREG( 73,292,32, 4, 4,0x0259,0x000d,-2, 2,0x1000,mmid, \r\n0,0,0,0,0,0)\r\n+ XTREG( 74,296, 2, 4, 4,0x0260,0x0007,-2,\r\n2,0x1000,ibreakenable,0,0,0,0,0,0)\r\n+ XTREG( 75,300,32, 4, 4,0x0268,0x0007,-2, 2,0x1000,ddr, \r\n0,0,0,0,0,0)\r\n+ XTREG( 76,304,32, 4, 4,0x0280,0x0007,-2, 2,0x1000,ibreaka0, \r\n0,0,0,0,0,0)\r\n+ XTREG( 77,308,32, 4, 4,0x0281,0x0007,-2, 2,0x1000,ibreaka1, \r\n0,0,0,0,0,0)\r\n+ XTREG( 78,312,32, 4, 4,0x0290,0x0007,-2, 2,0x1000,dbreaka0, \r\n0,0,0,0,0,0)\r\n+ XTREG( 79,316,32, 4, 4,0x0291,0x0007,-2, 2,0x1000,dbreaka1, \r\n0,0,0,0,0,0)\r\n+ XTREG( 80,320,32, 4, 4,0x02a0,0x0007,-2, 2,0x1000,dbreakc0, \r\n0,0,0,0,0,0)\r\n+ XTREG( 81,324,32, 4, 4,0x02a1,0x0007,-2, 2,0x1000,dbreakc1, \r\n0,0,0,0,0,0)\r\n+ XTREG( 82,328,32, 4, 4,0x02b1,0x0007,-2, 2,0x1000,epc1, \r\n0,0,0,0,0,0)\r\n+ XTREG( 83,332,32, 4, 4,0x02b2,0x0007,-2, 2,0x1000,epc2, \r\n0,0,0,0,0,0)\r\n+ XTREG( 84,336,32, 4, 4,0x02b3,0x0007,-2, 2,0x1000,epc3, \r\n0,0,0,0,0,0)\r\n+ XTREG( 85,340,32, 4, 4,0x02b4,0x0007,-2, 2,0x1000,epc4, \r\n0,0,0,0,0,0)\r\n+ XTREG( 86,344,32, 4, 4,0x02b5,0x0007,-2, 2,0x1000,epc5, \r\n0,0,0,0,0,0)\r\n+ XTREG( 87,348,32, 4, 4,0x02b6,0x0007,-2, 2,0x1000,epc6, \r\n0,0,0,0,0,0)\r\n+ XTREG( 88,352,32, 4, 4,0x02b7,0x0007,-2, 2,0x1000,epc7, \r\n0,0,0,0,0,0)\r\n+ XTREG( 89,356,32, 4, 4,0x02c0,0x0007,-2, 2,0x1000,depc, \r\n0,0,0,0,0,0)\r\n+ XTREG( 90,360,19, 4, 4,0x02c2,0x0007,-2, 2,0x1000,eps2, \r\n0,0,0,0,0,0)\r\n+ XTREG( 91,364,19, 4, 4,0x02c3,0x0007,-2, 2,0x1000,eps3, \r\n0,0,0,0,0,0)\r\n+ XTREG( 92,368,19, 4, 4,0x02c4,0x0007,-2, 2,0x1000,eps4, \r\n0,0,0,0,0,0)\r\n+ XTREG( 93,372,19, 4, 4,0x02c5,0x0007,-2, 2,0x1000,eps5, \r\n0,0,0,0,0,0)\r\n+ XTREG( 94,376,19, 4, 4,0x02c6,0x0007,-2, 2,0x1000,eps6, \r\n0,0,0,0,0,0)\r\n+ XTREG( 95,380,19, 4, 4,0x02c7,0x0007,-2, 2,0x1000,eps7, \r\n0,0,0,0,0,0)\r\n+ XTREG( 96,384,32, 4, 4,0x02d1,0x0007,-2, 2,0x1000,excsave1, \r\n0,0,0,0,0,0)\r\n+ XTREG( 97,388,32, 4, 4,0x02d2,0x0007,-2, 2,0x1000,excsave2, \r\n0,0,0,0,0,0)\r\n+ XTREG( 98,392,32, 4, 4,0x02d3,0x0007,-2, 2,0x1000,excsave3, \r\n0,0,0,0,0,0)\r\n+ XTREG( 99,396,32, 4, 4,0x02d4,0x0007,-2, 2,0x1000,excsave4, \r\n0,0,0,0,0,0)\r\n+ XTREG(100,400,32, 4, 4,0x02d5,0x0007,-2, 2,0x1000,excsave5, \r\n0,0,0,0,0,0)\r\n+ XTREG(101,404,32, 4, 4,0x02d6,0x0007,-2, 2,0x1000,excsave6, \r\n0,0,0,0,0,0)\r\n+ XTREG(102,408,32, 4, 4,0x02d7,0x0007,-2, 2,0x1000,excsave7, \r\n0,0,0,0,0,0)\r\n+ XTREG(103,412, 8, 4, 4,0x02e0,0x0007,-2, 2,0x1000,cpenable, \r\n0,0,0,0,0,0)\r\n+ XTREG(104,416,32, 4, 4,0x02e2,0x000b,-2, 2,0x1000,interrupt, \r\n0,0,0,0,0,0)\r\n+ XTREG(105,420,32, 4, 4,0x02e2,0x000d,-2, 2,0x1000,intset, \r\n0,0,0,0,0,0)\r\n+ XTREG(106,424,32, 4, 4,0x02e3,0x000d,-2, 2,0x1000,intclear, \r\n0,0,0,0,0,0)\r\n+ XTREG(107,428,32, 4, 4,0x02e4,0x0007,-2, 2,0x1000,intenable, \r\n0,0,0,0,0,0)\r\n+ XTREG(108,432,32, 4, 4,0x02e7,0x0007,-2, 2,0x1000,vecbase, \r\n0,0,0,0,0,0)\r\n+ XTREG(109,436, 6, 4, 4,0x02e8,0x0007,-2, 2,0x1000,exccause, \r\n0,0,0,0,0,0)\r\n+ XTREG(110,440,12, 4, 4,0x02e9,0x0003,-2, 2,0x1000,debugcause, \r\n0,0,0,0,0,0)\r\n+ XTREG(111,444,32, 4, 4,0x02ea,0x000f,-2, 2,0x1000,ccount, \r\n0,0,0,0,0,0)\r\n+ XTREG(112,448,32, 4, 4,0x02eb,0x0003,-2, 2,0x1000,prid, \r\n0,0,0,0,0,0)\r\n+ XTREG(113,452,32, 4, 4,0x02ec,0x000f,-2, 2,0x1000,icount, \r\n0,0,0,0,0,0)\r\n+ XTREG(114,456, 4, 4, 4,0x02ed,0x0007,-2, 2,0x1000,icountlevel,\r\n0,0,0,0,0,0)\r\n+ XTREG(115,460,32, 4, 4,0x02ee,0x0007,-2, 2,0x1000,excvaddr, \r\n0,0,0,0,0,0)\r\n+ XTREG(116,464,32, 4, 4,0x02f0,0x000f,-2, 2,0x1000,ccompare0, \r\n0,0,0,0,0,0)\r\n+ XTREG(117,468,32, 4, 4,0x02f1,0x000f,-2, 2,0x1000,ccompare1, \r\n0,0,0,0,0,0)\r\n+ XTREG(118,472,32, 4, 4,0x02f2,0x000f,-2, 2,0x1000,ccompare2, \r\n0,0,0,0,0,0)\r\n+ XTREG(119,476,32, 4, 4,0x02f4,0x0007,-2, 2,0x1000,misc0, \r\n0,0,0,0,0,0)\r\n+ XTREG(120,480,32, 4, 4,0x02f5,0x0007,-2, 2,0x1000,misc1, \r\n0,0,0,0,0,0)\r\n+ XTREG(121,484,32, 4, 4,0x02f6,0x0007,-2, 2,0x1000,misc2, \r\n0,0,0,0,0,0)\r\n+ XTREG(122,488,32, 4, 4,0x02f7,0x0007,-2, 2,0x1000,misc3, \r\n0,0,0,0,0,0)\r\n+ XTREG(123,492,32, 4, 4,0x2014,0x000f,-2, 4,0x0101,pwrctl,\r\n+ \r\n\"03:52:64:01:03:62:64:02:03:52:a4:0c:03:60:55:11:03:52:c5:20:03:60:65:4\r\n0:03:62:64:00:03:52:24:01:03:62:24:02\",\"03:52:64:01:03:62:64:02:03:52:a\r\n4:0c:03:60:55:11:03:52:c5:20:03:62:24:00:03:60:75:40:03:52:24:01:03:62:\r\n24:02\",0,0,0,0)\r\n+ XTREG(124,496,32, 4, 4,0x2015,0x000f,-2, 4,0x0101,pwrstat,\r\n+ \r\n\"03:52:64:01:03:62:64:02:03:52:a4:0c:03:60:55:11:03:52:c5:24:03:60:65:4\r\n0:03:62:64:00:03:52:24:01:03:62:24:02\",\"03:52:64:01:03:62:64:02:03:52:a\r\n4:0c:03:60:55:11:03:52:c5:24:03:62:24:00:03:60:75:40:03:52:24:01:03:62:\r\n24:02\",0,0,0,0)\r\n+ XTREG(125,500, 1, 4, 4,0x2016,0x000f,-2, 4,0x0101,eristat,\r\n+ \r\n\"03:52:64:01:03:62:64:02:03:52:a4:0c:03:60:55:11:03:52:c5:28:03:60:65:4\r\n0:03:62:64:00:03:52:24:01:03:62:24:02\",\"03:52:64:01:03:62:64:02:03:52:a\r\n4:0c:03:60:55:11:03:52:c5:28:03:62:24:00:03:60:75:40:03:52:24:01:03:62:\r\n24:02\",0,0,0,0)\r\n+ XTREG(126,504,32, 4, 4,0x2017,0x000f,-2, 4,0x0101,cs_itctrl,\r\n+ \r\n\"03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:d5:03:03:60:65:4\r\n0:03:62:64:00:03:52:24:01:03:62:24:02\",\"03:52:64:01:03:62:64:02:03:52:a\r\n4:0f:03:60:55:11:03:52:d5:03:03:62:24:00:03:60:75:40:03:52:24:01:03:62:\r\n24:02\",0,0,0,0)\r\n+ XTREG(127,508,16, 4, 4,0x2018,0x000f,-2, 4,0x0101,cs_claimset,\r\n+ \r\n\"03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:c5:a0:03:52:d5:0\r\n4:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02\",\"03:52:64:01:03:62:6\r\n4:02:03:52:a4:0f:03:60:55:11:03:52:c5:a0:03:52:d5:04:03:62:24:00:03:60:\r\n75:40:03:52:24:01:03:62:24:02\",0,0,0,0)\r\n+ XTREG(128,512,16, 4, 4,0x2019,0x000f,-2, 4,0x0101,cs_claimclr,\r\n+ \r\n\"03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:c5:a4:03:52:d5:0\r\n4:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02\",\"03:52:64:01:03:62:6\r\n4:02:03:52:a4:0f:03:60:55:11:03:52:c5:a4:03:52:d5:04:03:62:24:00:03:60:\r\n75:40:03:52:24:01:03:62:24:02\",0,0,0,0)\r\n+ XTREG(129,516,32, 4, 4,0x201a,0x000d,-2, 4,0x0101,cs_lockaccess,\r\n+ \r\n\"03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:c5:b0:03:52:d5:0\r\n4:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02\",\"03:52:64:01:03:62:6\r\n4:02:03:52:a4:0f:03:60:55:11:03:52:c5:b0:03:52:d5:04:03:62:24:00:03:60:\r\n75:40:03:52:24:01:03:62:24:02\",0,0,0,0)\r\n+ XTREG(130,520,32, 4, 4,0x201b,0x000b,-2, 4,0x0101,cs_lockstatus,\r\n+ \r\n\"03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:c5:b4:03:52:d5:0\r\n4:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02\",\"03:52:64:01:03:62:6\r\n4:02:03:52:a4:0f:03:60:55:11:03:52:c5:b4:03:52:d5:04:03:62:24:00:03:60:\r\n75:40:03:52:24:01:03:62:24:02\",0,0,0,0)\r\n+ XTREG(131,524, 1, 4, 4,0x201c,0x000b,-2, 4,0x0101,cs_authstatus,\r\n+ \r\n\"03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:c5:b8:03:52:d5:0\r\n4:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02\",\"03:52:64:01:03:62:6\r\n4:02:03:52:a4:0f:03:60:55:11:03:52:c5:b8:03:52:d5:04:03:62:24:00:03:60:\r\n75:40:03:52:24:01:03:62:24:02\",0,0,0,0)\r\n+ XTREG(132,528,32, 4, 4,0x202b,0x000f,-2, 4,0x0101,fault_info,\r\n+ \r\n\"03:52:64:01:03:62:64:02:03:52:a4:0c:03:60:55:11:03:52:c5:30:03:60:65:4\r\n0:03:62:64:00:03:52:24:01:03:62:24:02\",\"03:52:64:01:03:62:64:02:03:52:a\r\n4:0c:03:60:55:11:03:52:c5:30:03:62:24:00:03:60:75:40:03:52:24:01:03:62:\r\n24:02\",0,0,0,0)\r\n+ XTREG(133,532,32, 4, 4,0x202c,0x0003,-2, 4,0x0101,trax_id,\r\n+ \r\n\"03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:60:65:40:03:62:64:0\r\n0:03:52:24:01:03:62:24:02\",\"03:52:64:01:03:62:64:02:03:52:a4:00:03:60:5\r\n5:11:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02\",0,0,0,0)\r\n+ XTREG(134,536,32, 4, 4,0x202d,0x000f,-2, 4,0x0101,trax_control,\r\n+ \r\n\"03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:04:03:60:65:4\r\n0:03:62:64:00:03:52:24:01:03:62:24:02\",\"03:52:64:01:03:62:64:02:03:52:a\r\n4:00:03:60:55:11:03:52:c5:04:03:62:24:00:03:60:75:40:03:52:24:01:03:62:\r\n24:02\",0,0,0,0)\r\n+ XTREG(135,540,32, 4, 4,0x202e,0x000b,-2, 4,0x0101,trax_status,\r\n+ \r\n\"03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:08:03:60:65:4\r\n0:03:62:64:00:03:52:24:01:03:62:24:02\",\"03:52:64:01:03:62:64:02:03:52:a\r\n4:00:03:60:55:11:03:52:c5:08:03:62:24:00:03:60:75:40:03:52:24:01:03:62:\r\n24:02\",0,0,0,0)\r\n+ XTREG(136,544,32, 4, 4,0x202f,0x000f,-2, 4,0x0101,trax_data,\r\n+ \r\n\"03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:0c:03:60:65:4\r\n0:03:62:64:00:03:52:24:01:03:62:24:02\",\"03:52:64:01:03:62:64:02:03:52:a\r\n4:00:03:60:55:11:03:52:c5:0c:03:62:24:00:03:60:75:40:03:52:24:01:03:62:\r\n24:02\",0,0,0,0)\r\n+ XTREG(137,548,32, 4, 4,0x2030,0x000f,-2, 4,0x0101,trax_address,\r\n+ \r\n\"03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:10:03:60:65:4\r\n0:03:62:64:00:03:52:24:01:03:62:24:02\",\"03:52:64:01:03:62:64:02:03:52:a\r\n4:00:03:60:55:11:03:52:c5:10:03:62:24:00:03:60:75:40:03:52:24:01:03:62:\r\n24:02\",0,0,0,0)\r\n+ XTREG(138,552,32, 4, 4,0x2031,0x000f,-2, 4,0x0101,trax_pctrigger,\r\n+ \r\n\"03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:14:03:60:65:4\r\n0:03:62:64:00:03:52:24:01:03:62:24:02\",\"03:52:64:01:03:62:64:02:03:52:a\r\n4:00:03:60:55:11:03:52:c5:14:03:62:24:00:03:60:75:40:03:52:24:01:03:62:\r\n24:02\",0,0,0,0)\r\n+ XTREG(139,556,32, 4, 4,0x2032,0x000f,-2, 4,0x0101,trax_pcmatch,\r\n+ \r\n\"03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:18:03:60:65:4\r\n0:03:62:64:00:03:52:24:01:03:62:24:02\",\"03:52:64:01:03:62:64:02:03:52:a\r\n4:00:03:60:55:11:03:52:c5:18:03:62:24:00:03:60:75:40:03:52:24:01:03:62:\r\n24:02\",0,0,0,0)\r\n+ XTREG(140,560,32, 4, 4,0x2033,0x000f,-2, 4,0x0101,trax_delay,\r\n+ \r\n\"03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:1c:03:60:65:4\r\n0:03:62:64:00:03:52:24:01:03:62:24:02\",\"03:52:64:01:03:62:64:02:03:52:a\r\n4:00:03:60:55:11:03:52:c5:1c:03:62:24:00:03:60:75:40:03:52:24:01:03:62:\r\n24:02\",0,0,0,0)\r\n+ XTREG(141,564,32, 4, 4,0x2034,0x000f,-2, 4,0x0101,trax_memstart,\r\n+ \r\n\"03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:20:03:60:65:4\r\n0:03:62:64:00:03:52:24:01:03:62:24:02\",\"03:52:64:01:03:62:64:02:03:52:a\r\n4:00:03:60:55:11:03:52:c5:20:03:62:24:00:03:60:75:40:03:52:24:01:03:62:\r\n24:02\",0,0,0,0)\r\n+ XTREG(142,568,32, 4, 4,0x2035,0x000f,-2, 4,0x0101,trax_memend,\r\n+ \r\n\"03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:24:03:60:65:4\r\n0:03:62:64:00:03:52:24:01:03:62:24:02\",\"03:52:64:01:03:62:64:02:03:52:a\r\n4:00:03:60:55:11:03:52:c5:24:03:62:24:00:03:60:75:40:03:52:24:01:03:62:\r\n24:02\",0,0,0,0)\r\n+ XTREG(143,572,32, 4, 4,0x2043,0x000f,-2, 4,0x0101,pmg,\r\n+ \r\n\"03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:60:65:40:03:62:64:0\r\n0:03:52:24:01:03:62:24:02\",\"03:52:64:01:03:62:64:02:03:52:a4:04:03:60:5\r\n5:11:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02\",0,0,0,0)\r\n+ XTREG(144,576,32, 4, 4,0x2044,0x000f,-2, 4,0x0101,pmpc,\r\n+ \r\n\"03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:04:03:60:65:4\r\n0:03:62:64:00:03:52:24:01:03:62:24:02\",\"03:52:64:01:03:62:64:02:03:52:a\r\n4:04:03:60:55:11:03:52:c5:04:03:62:24:00:03:60:75:40:03:52:24:01:03:62:\r\n24:02\",0,0,0,0)\r\n+ XTREG(145,580,32, 4, 4,0x2045,0x000f,-2, 4,0x0101,pm0,\r\n+ \r\n\"03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:80:03:52:d5:0\r\n1:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02\",\"03:52:64:01:03:62:6\r\n4:02:03:52:a4:04:03:60:55:11:03:52:c5:80:03:52:d5:01:03:62:24:00:03:60:\r\n75:40:03:52:24:01:03:62:24:02\",0,0,0,0)\r\n+ XTREG(146,584,32, 4, 4,0x2046,0x000f,-2, 4,0x0101,pm1,\r\n+ \r\n\"03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:80:03:52:d5:0\r\n1:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02\",\"03:52:64:01:03:62:6\r\n4:02:03:52:a4:04:03:60:55:11:03:52:c5:80:03:52:d5:01:03:62:24:00:03:60:\r\n75:40:03:52:24:01:03:62:24:02\",0,0,0,0)\r\n+ XTREG(147,588,32, 4, 4,0x2047,0x000f,-2, 4,0x0101,pmctrl0,\r\n+ \r\n\"03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:d5:01:03:60:65:4\r\n0:03:62:64:00:03:52:24:01:03:62:24:02\",\"03:52:64:01:03:62:64:02:03:52:a\r\n4:04:03:60:55:11:03:52:d5:01:03:62:24:00:03:60:75:40:03:52:24:01:03:62:\r\n24:02\",0,0,0,0)\r\n+ XTREG(148,592,32, 4, 4,0x2048,0x000f,-2, 4,0x0101,pmctrl1,\r\n+ \r\n\"03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:d5:01:03:60:65:4\r\n0:03:62:64:00:03:52:24:01:03:62:24:02\",\"03:52:64:01:03:62:64:02:03:52:a\r\n4:04:03:60:55:11:03:52:d5:01:03:62:24:00:03:60:75:40:03:52:24:01:03:62:\r\n24:02\",0,0,0,0)\r\n+ XTREG(149,596,32, 4, 4,0x2049,0x000f,-2, 4,0x0101,pmstat0,\r\n+ \r\n\"03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:80:03:52:d5:0\r\n2:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02\",\"03:52:64:01:03:62:6\r\n4:02:03:52:a4:04:03:60:55:11:03:52:c5:80:03:52:d5:02:03:62:24:00:03:60:\r\n75:40:03:52:24:01:03:62:24:02\",0,0,0,0)\r\n+ XTREG(150,600,32, 4, 4,0x204a,0x000f,-2, 4,0x0101,pmstat1,\r\n+ \r\n\"03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:80:03:52:d5:0\r\n2:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02\",\"03:52:64:01:03:62:6\r\n4:02:03:52:a4:04:03:60:55:11:03:52:c5:80:03:52:d5:02:03:62:24:00:03:60:\r\n75:40:03:52:24:01:03:62:24:02\",0,0,0,0)\r\n+ XTREG(151,604,32, 4, 4,0x204b,0x0003,-2, 4,0x0101,ocdid,\r\n+ \r\n\"03:52:64:01:03:62:64:02:03:52:a4:08:03:60:55:11:03:60:65:40:03:62:64:0\r\n0:03:52:24:01:03:62:24:02\",\"03:52:64:01:03:62:64:02:03:52:a4:08:03:60:5\r\n5:11:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02\",0,0,0,0)\r\n+ XTREG(152,608,32, 4, 4,0x204c,0x000f,-2, 4,0x0101,ocd_dcrclr,\r\n+ \r\n\"03:52:64:01:03:62:64:02:03:52:a4:08:03:60:55:11:03:52:c5:08:03:60:65:4\r\n0:03:62:64:00:03:52:24:01:03:62:24:02\",\"03:52:64:01:03:62:64:02:03:52:a\r\n4:08:03:60:55:11:03:52:c5:08:03:62:24:00:03:60:75:40:03:52:24:01:03:62:\r\n24:02\",0,0,0,0)\r\n+ XTREG(153,612,32, 4, 4,0x204d,0x000f,-2, 4,0x0101,ocd_dcrset,\r\n+ \r\n\"03:52:64:01:03:62:64:02:03:52:a4:08:03:60:55:11:03:52:c5:0c:03:60:65:4\r\n0:03:62:64:00:03:52:24:01:03:62:24:02\",\"03:52:64:01:03:62:64:02:03:52:a\r\n4:08:03:60:55:11:03:52:c5:0c:03:62:24:00:03:60:75:40:03:52:24:01:03:62:\r\n24:02\",0,0,0,0)\r\n+ XTREG(154,616,32, 4, 4,0x204e,0x000f,-2, 4,0x0101,ocd_dsr,\r\n+ \r\n\"03:52:64:01:03:62:64:02:03:52:a4:08:03:60:55:11:03:52:c5:10:03:60:65:4\r\n0:03:62:64:00:03:52:24:01:03:62:24:02\",\"03:52:64:01:03:62:64:02:03:52:a\r\n4:08:03:60:55:11:03:52:c5:10:03:62:24:00:03:60:75:40:03:52:24:01:03:62:\r\n24:02\",0,0,0,0)\r\n+ XTREG(155,620,32, 4, 4,0x0000,0x0006,-2, 8,0x2100,a0, \r\n0,0,0,0,0,0)\r\n+ XTREG(156,624,32, 4, 4,0x0001,0x0006,-2, 8,0x2100,a1, \r\n0,0,0,0,0,0)\r\n+ XTREG(157,628,32, 4, 4,0x0002,0x0006,-2, 8,0x2100,a2, \r\n0,0,0,0,0,0)\r\n+ XTREG(158,632,32, 4, 4,0x0003,0x0006,-2, 8,0x2100,a3, \r\n0,0,0,0,0,0)\r\n+ XTREG(159,636,32, 4, 4,0x0004,0x0006,-2, 8,0x2100,a4, \r\n0,0,0,0,0,0)\r\n+ XTREG(160,640,32, 4, 4,0x0005,0x0006,-2, 8,0x2100,a5, \r\n0,0,0,0,0,0)\r\n+ XTREG(161,644,32, 4, 4,0x0006,0x0006,-2, 8,0x2100,a6, \r\n0,0,0,0,0,0)\r\n+ XTREG(162,648,32, 4, 4,0x0007,0x0006,-2, 8,0x2100,a7, \r\n0,0,0,0,0,0)\r\n+ XTREG(163,652,32, 4, 4,0x0008,0x0006,-2, 8,0x2100,a8, \r\n0,0,0,0,0,0)\r\n+ XTREG(164,656,32, 4, 4,0x0009,0x0006,-2, 8,0x2100,a9, \r\n0,0,0,0,0,0)\r\n+ XTREG(165,660,32, 4, 4,0x000a,0x0006,-2, 8,0x2100,a10, \r\n0,0,0,0,0,0)\r\n+ XTREG(166,664,32, 4, 4,0x000b,0x0006,-2, 8,0x2100,a11, \r\n0,0,0,0,0,0)\r\n+ XTREG(167,668,32, 4, 4,0x000c,0x0006,-2, 8,0x2100,a12, \r\n0,0,0,0,0,0)\r\n+ XTREG(168,672,32, 4, 4,0x000d,0x0006,-2, 8,0x2100,a13, \r\n0,0,0,0,0,0)\r\n+ XTREG(169,676,32, 4, 4,0x000e,0x0006,-2, 8,0x2100,a14, \r\n0,0,0,0,0,0)\r\n+ XTREG(170,680,32, 4, 4,0x000f,0x0006,-2, 8,0x2100,a15, \r\n0,0,0,0,0,0)\r\n+ XTREG(171,684, 4, 4, 4,0x2008,0x0006,-2, 6,0x1010,psintlevel,\r\n+ 0,0,&xtensa_mask0,0,0,0)\r\n+ XTREG(172,688, 1, 4, 4,0x2009,0x0006,-2, 6,0x1010,psum,\r\n+ 0,0,&xtensa_mask1,0,0,0)\r\n+ XTREG(173,692, 1, 4, 4,0x200a,0x0006,-2, 6,0x1010,pswoe,\r\n+ 0,0,&xtensa_mask2,0,0,0)\r\n+ XTREG(174,696, 1, 4, 4,0x200b,0x0006,-2, 6,0x1010,psexcm,\r\n+ 0,0,&xtensa_mask3,0,0,0)\r\n+ XTREG(175,700, 2, 4, 4,0x200c,0x0006,-2, 6,0x1010,pscallinc,\r\n+ 0,0,&xtensa_mask4,0,0,0)\r\n+ XTREG(176,704, 4, 4, 4,0x200d,0x0006,-2, 6,0x1010,psowb,\r\n+ 0,0,&xtensa_mask5,0,0,0)\r\n+ XTREG_END\r\n+};\r\n+\r\n+xtensa_gdbarch_tdep xtensa_tdep_esp32s2 (rmap);\r\ndiff --git a/gdb/xtensa-config-esp32s3.c b/gdb/xtensa-config-esp32s3.c\r\nnew file mode 100644\r\nindex 00000000000..658b12b8903\r\n--- /dev/null\r\n+++ b/gdb/xtensa-config-esp32s3.c\r\n@@ -0,0 +1,496 @@\r\n+/* Configuration for the Xtensa architecture for GDB, the GNU\r\ndebugger.\r\n+\r\n+ Customer ID=15128; Build=0x90f1f; Copyright (c) 2003-2021 Tensilica\r\nInc.\r\n+\r\n+ Permission is hereby granted, free of charge, to any person\r\nobtaining\r\n+ a copy of this software and associated documentation files (the\r\n+ \"Software\"), to deal in the Software without restriction, including\r\n+ without limitation the rights to use, copy, modify, merge, publish,\r\n+ distribute, sublicense, and/or sell copies of the Software, and to\r\n+ permit persons to whom the Software is furnished to do so, subject\r\nto\r\n+ the following conditions:\r\n+\r\n+ The above copyright notice and this permission notice shall be\r\nincluded\r\n+ in all copies or substantial portions of the Software.\r\n+\r\n+ THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\r\n+ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r\n+ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r\nNONINFRINGEMENT.\r\n+ IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR\r\nANY\r\n+ CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF\r\nCONTRACT,\r\n+ TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE\r\n+ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */\r\n+\r\n+#define XTENSA_CONFIG_VERSION 0x60\r\n+\r\n+#include \"defs.h\"\r\n+#include \"xtensa-config.h\"\r\n+#include \"xtensa-tdep.h\"\r\n+\r\n+\r\n+\r\n+/* Masked registers. */\r\n+static xtensa_reg_mask_t xtensa_submask0[] = { { 75, 0, 1 } };\r\n+static const xtensa_mask_t xtensa_mask0 = { 1, xtensa_submask0 };\r\n+static xtensa_reg_mask_t xtensa_submask1[] = { { 75, 1, 1 } };\r\n+static const xtensa_mask_t xtensa_mask1 = { 1, xtensa_submask1 };\r\n+static xtensa_reg_mask_t xtensa_submask2[] = { { 75, 2, 1 } };\r\n+static const xtensa_mask_t xtensa_mask2 = { 1, xtensa_submask2 };\r\n+static xtensa_reg_mask_t xtensa_submask3[] = { { 75, 3, 1 } };\r\n+static const xtensa_mask_t xtensa_mask3 = { 1, xtensa_submask3 };\r\n+static xtensa_reg_mask_t xtensa_submask4[] = { { 75, 4, 1 } };\r\n+static const xtensa_mask_t xtensa_mask4 = { 1, xtensa_submask4 };\r\n+static xtensa_reg_mask_t xtensa_submask5[] = { { 75, 5, 1 } };\r\n+static const xtensa_mask_t xtensa_mask5 = { 1, xtensa_submask5 };\r\n+static xtensa_reg_mask_t xtensa_submask6[] = { { 75, 6, 1 } };\r\n+static const xtensa_mask_t xtensa_mask6 = { 1, xtensa_submask6 };\r\n+static xtensa_reg_mask_t xtensa_submask7[] = { { 75, 7, 1 } };\r\n+static const xtensa_mask_t xtensa_mask7 = { 1, xtensa_submask7 };\r\n+static xtensa_reg_mask_t xtensa_submask8[] = { { 75, 8, 1 } };\r\n+static const xtensa_mask_t xtensa_mask8 = { 1, xtensa_submask8 };\r\n+static xtensa_reg_mask_t xtensa_submask9[] = { { 75, 9, 1 } };\r\n+static const xtensa_mask_t xtensa_mask9 = { 1, xtensa_submask9 };\r\n+static xtensa_reg_mask_t xtensa_submask10[] = { { 75, 10, 1 } };\r\n+static const xtensa_mask_t xtensa_mask10 = { 1, xtensa_submask10 };\r\n+static xtensa_reg_mask_t xtensa_submask11[] = { { 75, 11, 1 } };\r\n+static const xtensa_mask_t xtensa_mask11 = { 1, xtensa_submask11 };\r\n+static xtensa_reg_mask_t xtensa_submask12[] = { { 75, 12, 1 } };\r\n+static const xtensa_mask_t xtensa_mask12 = { 1, xtensa_submask12 };\r\n+static xtensa_reg_mask_t xtensa_submask13[] = { { 75, 13, 1 } };\r\n+static const xtensa_mask_t xtensa_mask13 = { 1, xtensa_submask13 };\r\n+static xtensa_reg_mask_t xtensa_submask14[] = { { 75, 14, 1 } };\r\n+static const xtensa_mask_t xtensa_mask14 = { 1, xtensa_submask14 };\r\n+static xtensa_reg_mask_t xtensa_submask15[] = { { 75, 15, 1 } };\r\n+static const xtensa_mask_t xtensa_mask15 = { 1, xtensa_submask15 };\r\n+static xtensa_reg_mask_t xtensa_submask16[] = { { 73, 0, 4 } };\r\n+static const xtensa_mask_t xtensa_mask16 = { 1, xtensa_submask16 };\r\n+static xtensa_reg_mask_t xtensa_submask17[] = { { 73, 5, 1 } };\r\n+static const xtensa_mask_t xtensa_mask17 = { 1, xtensa_submask17 };\r\n+static xtensa_reg_mask_t xtensa_submask18[] = { { 73, 18, 1 } };\r\n+static const xtensa_mask_t xtensa_mask18 = { 1, xtensa_submask18 };\r\n+static xtensa_reg_mask_t xtensa_submask19[] = { { 73, 4, 1 } };\r\n+static const xtensa_mask_t xtensa_mask19 = { 1, xtensa_submask19 };\r\n+static xtensa_reg_mask_t xtensa_submask20[] = { { 73, 16, 2 } };\r\n+static const xtensa_mask_t xtensa_mask20 = { 1, xtensa_submask20 };\r\n+static xtensa_reg_mask_t xtensa_submask21[] = { { 73, 8, 4 } };\r\n+static const xtensa_mask_t xtensa_mask21 = { 1, xtensa_submask21 };\r\n+static xtensa_reg_mask_t xtensa_submask22[] = { { 77, 0, 32 }, { 78,\r\n0, 8 } };\r\n+static const xtensa_mask_t xtensa_mask22 = { 2, xtensa_submask22 };\r\n+static xtensa_reg_mask_t xtensa_submask23[] = { { 167, 8, 4 } };\r\n+static const xtensa_mask_t xtensa_mask23 = { 1, xtensa_submask23 };\r\n+static xtensa_reg_mask_t xtensa_submask24[] = { { 100, 0, 2 } };\r\n+static const xtensa_mask_t xtensa_mask24 = { 1, xtensa_submask24 };\r\n+static xtensa_reg_mask_t xtensa_submask25[] = { { 100, 6, 1 } };\r\n+static const xtensa_mask_t xtensa_mask25 = { 1, xtensa_submask25 };\r\n+static xtensa_reg_mask_t xtensa_submask26[] = { { 100, 5, 1 } };\r\n+static const xtensa_mask_t xtensa_mask26 = { 1, xtensa_submask26 };\r\n+static xtensa_reg_mask_t xtensa_submask27[] = { { 100, 4, 1 } };\r\n+static const xtensa_mask_t xtensa_mask27 = { 1, xtensa_submask27 };\r\n+static xtensa_reg_mask_t xtensa_submask28[] = { { 100, 3, 1 } };\r\n+static const xtensa_mask_t xtensa_mask28 = { 1, xtensa_submask28 };\r\n+static xtensa_reg_mask_t xtensa_submask29[] = { { 100, 2, 1 } };\r\n+static const xtensa_mask_t xtensa_mask29 = { 1, xtensa_submask29 };\r\n+static xtensa_reg_mask_t xtensa_submask30[] = { { 101, 11, 1 } };\r\n+static const xtensa_mask_t xtensa_mask30 = { 1, xtensa_submask30 };\r\n+static xtensa_reg_mask_t xtensa_submask31[] = { { 101, 10, 1 } };\r\n+static const xtensa_mask_t xtensa_mask31 = { 1, xtensa_submask31 };\r\n+static xtensa_reg_mask_t xtensa_submask32[] = { { 101, 9, 1 } };\r\n+static const xtensa_mask_t xtensa_mask32 = { 1, xtensa_submask32 };\r\n+static xtensa_reg_mask_t xtensa_submask33[] = { { 101, 8, 1 } };\r\n+static const xtensa_mask_t xtensa_mask33 = { 1, xtensa_submask33 };\r\n+static xtensa_reg_mask_t xtensa_submask34[] = { { 101, 7, 1 } };\r\n+static const xtensa_mask_t xtensa_mask34 = { 1, xtensa_submask34 };\r\n+static xtensa_reg_mask_t xtensa_submask35[] = { { 100, 12, 20 } };\r\n+static const xtensa_mask_t xtensa_mask35 = { 1, xtensa_submask35 };\r\n+static xtensa_reg_mask_t xtensa_submask36[] = { { 101, 12, 20 } };\r\n+static const xtensa_mask_t xtensa_mask36 = { 1, xtensa_submask36 };\r\n+static xtensa_reg_mask_t xtensa_submask37[] = { { 100, 7, 5 } };\r\n+static const xtensa_mask_t xtensa_mask37 = { 1, xtensa_submask37 };\r\n+static xtensa_reg_mask_t xtensa_submask38[] = { { 101, 0, 7 } };\r\n+static const xtensa_mask_t xtensa_mask38 = { 1, xtensa_submask38 };\r\n+static xtensa_reg_mask_t xtensa_submask39[] = { { 102, 0, 32 }, { 103,\r\n0, 8 } };\r\n+static const xtensa_mask_t xtensa_mask39 = { 2, xtensa_submask39 };\r\n+static xtensa_reg_mask_t xtensa_submask40[] = { { 104, 0, 32 }, { 105,\r\n0, 32 }, { 106, 0, 32 }, { 107, 0, 32 }, { 108, 0, 32 } };\r\n+static const xtensa_mask_t xtensa_mask40 = { 5, xtensa_submask40 };\r\n+static xtensa_reg_mask_t xtensa_submask41[] = { { 109, 0, 32 }, { 110,\r\n0, 32 }, { 111, 0, 32 }, { 112, 0, 32 }, { 113, 0, 32 } };\r\n+static const xtensa_mask_t xtensa_mask41 = { 5, xtensa_submask41 };\r\n+static xtensa_reg_mask_t xtensa_submask42[] = { { 116, 0, 32 }, { 117,\r\n0, 32 }, { 118, 0, 32 }, { 119, 0, 32 } };\r\n+static const xtensa_mask_t xtensa_mask42 = { 4, xtensa_submask42 };\r\n+\r\n+\r\n+/* Register map. */\r\n+static xtensa_register_t rmap[] = \r\n+{\r\n+ /* idx ofs bi sz al targno flags cp typ group name */\r\n+ XTREG( 0, 0,32, 4, 4,0x0020,0x0006,-2, 9,0x2100,pc, \r\n0,0,0,0,0,0)\r\n+ XTREG( 1, 4,32, 4, 4,0x0100,0x0006,-2, 1,0x0002,ar0, \r\n0,0,0,0,0,0)\r\n+ XTREG( 2, 8,32, 4, 4,0x0101,0x0006,-2, 1,0x0002,ar1, \r\n0,0,0,0,0,0)\r\n+ XTREG( 3, 12,32, 4, 4,0x0102,0x0006,-2, 1,0x0002,ar2, \r\n0,0,0,0,0,0)\r\n+ XTREG( 4, 16,32, 4, 4,0x0103,0x0006,-2, 1,0x0002,ar3, \r\n0,0,0,0,0,0)\r\n+ XTREG( 5, 20,32, 4, 4,0x0104,0x0006,-2, 1,0x0002,ar4, \r\n0,0,0,0,0,0)\r\n+ XTREG( 6, 24,32, 4, 4,0x0105,0x0006,-2, 1,0x0002,ar5, \r\n0,0,0,0,0,0)\r\n+ XTREG( 7, 28,32, 4, 4,0x0106,0x0006,-2, 1,0x0002,ar6, \r\n0,0,0,0,0,0)\r\n+ XTREG( 8, 32,32, 4, 4,0x0107,0x0006,-2, 1,0x0002,ar7, \r\n0,0,0,0,0,0)\r\n+ XTREG( 9, 36,32, 4, 4,0x0108,0x0006,-2, 1,0x0002,ar8, \r\n0,0,0,0,0,0)\r\n+ XTREG( 10, 40,32, 4, 4,0x0109,0x0006,-2, 1,0x0002,ar9, \r\n0,0,0,0,0,0)\r\n+ XTREG( 11, 44,32, 4, 4,0x010a,0x0006,-2, 1,0x0002,ar10, \r\n0,0,0,0,0,0)\r\n+ XTREG( 12, 48,32, 4, 4,0x010b,0x0006,-2, 1,0x0002,ar11, \r\n0,0,0,0,0,0)\r\n+ XTREG( 13, 52,32, 4, 4,0x010c,0x0006,-2, 1,0x0002,ar12, \r\n0,0,0,0,0,0)\r\n+ XTREG( 14, 56,32, 4, 4,0x010d,0x0006,-2, 1,0x0002,ar13, \r\n0,0,0,0,0,0)\r\n+ XTREG( 15, 60,32, 4, 4,0x010e,0x0006,-2, 1,0x0002,ar14, \r\n0,0,0,0,0,0)\r\n+ XTREG( 16, 64,32, 4, 4,0x010f,0x0006,-2, 1,0x0002,ar15, \r\n0,0,0,0,0,0)\r\n+ XTREG( 17, 68,32, 4, 4,0x0110,0x0006,-2, 1,0x0002,ar16, \r\n0,0,0,0,0,0)\r\n+ XTREG( 18, 72,32, 4, 4,0x0111,0x0006,-2, 1,0x0002,ar17, \r\n0,0,0,0,0,0)\r\n+ XTREG( 19, 76,32, 4, 4,0x0112,0x0006,-2, 1,0x0002,ar18, \r\n0,0,0,0,0,0)\r\n+ XTREG( 20, 80,32, 4, 4,0x0113,0x0006,-2, 1,0x0002,ar19, \r\n0,0,0,0,0,0)\r\n+ XTREG( 21, 84,32, 4, 4,0x0114,0x0006,-2, 1,0x0002,ar20, \r\n0,0,0,0,0,0)\r\n+ XTREG( 22, 88,32, 4, 4,0x0115,0x0006,-2, 1,0x0002,ar21, \r\n0,0,0,0,0,0)\r\n+ XTREG( 23, 92,32, 4, 4,0x0116,0x0006,-2, 1,0x0002,ar22, \r\n0,0,0,0,0,0)\r\n+ XTREG( 24, 96,32, 4, 4,0x0117,0x0006,-2, 1,0x0002,ar23, \r\n0,0,0,0,0,0)\r\n+ XTREG( 25,100,32, 4, 4,0x0118,0x0006,-2, 1,0x0002,ar24, \r\n0,0,0,0,0,0)\r\n+ XTREG( 26,104,32, 4, 4,0x0119,0x0006,-2, 1,0x0002,ar25, \r\n0,0,0,0,0,0)\r\n+ XTREG( 27,108,32, 4, 4,0x011a,0x0006,-2, 1,0x0002,ar26, \r\n0,0,0,0,0,0)\r\n+ XTREG( 28,112,32, 4, 4,0x011b,0x0006,-2, 1,0x0002,ar27, \r\n0,0,0,0,0,0)\r\n+ XTREG( 29,116,32, 4, 4,0x011c,0x0006,-2, 1,0x0002,ar28, \r\n0,0,0,0,0,0)\r\n+ XTREG( 30,120,32, 4, 4,0x011d,0x0006,-2, 1,0x0002,ar29, \r\n0,0,0,0,0,0)\r\n+ XTREG( 31,124,32, 4, 4,0x011e,0x0006,-2, 1,0x0002,ar30, \r\n0,0,0,0,0,0)\r\n+ XTREG( 32,128,32, 4, 4,0x011f,0x0006,-2, 1,0x0002,ar31, \r\n0,0,0,0,0,0)\r\n+ XTREG( 33,132,32, 4, 4,0x0120,0x0006,-2, 1,0x0002,ar32, \r\n0,0,0,0,0,0)\r\n+ XTREG( 34,136,32, 4, 4,0x0121,0x0006,-2, 1,0x0002,ar33, \r\n0,0,0,0,0,0)\r\n+ XTREG( 35,140,32, 4, 4,0x0122,0x0006,-2, 1,0x0002,ar34, \r\n0,0,0,0,0,0)\r\n+ XTREG( 36,144,32, 4, 4,0x0123,0x0006,-2, 1,0x0002,ar35, \r\n0,0,0,0,0,0)\r\n+ XTREG( 37,148,32, 4, 4,0x0124,0x0006,-2, 1,0x0002,ar36, \r\n0,0,0,0,0,0)\r\n+ XTREG( 38,152,32, 4, 4,0x0125,0x0006,-2, 1,0x0002,ar37, \r\n0,0,0,0,0,0)\r\n+ XTREG( 39,156,32, 4, 4,0x0126,0x0006,-2, 1,0x0002,ar38, \r\n0,0,0,0,0,0)\r\n+ XTREG( 40,160,32, 4, 4,0x0127,0x0006,-2, 1,0x0002,ar39, \r\n0,0,0,0,0,0)\r\n+ XTREG( 41,164,32, 4, 4,0x0128,0x0006,-2, 1,0x0002,ar40, \r\n0,0,0,0,0,0)\r\n+ XTREG( 42,168,32, 4, 4,0x0129,0x0006,-2, 1,0x0002,ar41, \r\n0,0,0,0,0,0)\r\n+ XTREG( 43,172,32, 4, 4,0x012a,0x0006,-2, 1,0x0002,ar42, \r\n0,0,0,0,0,0)\r\n+ XTREG( 44,176,32, 4, 4,0x012b,0x0006,-2, 1,0x0002,ar43, \r\n0,0,0,0,0,0)\r\n+ XTREG( 45,180,32, 4, 4,0x012c,0x0006,-2, 1,0x0002,ar44, \r\n0,0,0,0,0,0)\r\n+ XTREG( 46,184,32, 4, 4,0x012d,0x0006,-2, 1,0x0002,ar45, \r\n0,0,0,0,0,0)\r\n+ XTREG( 47,188,32, 4, 4,0x012e,0x0006,-2, 1,0x0002,ar46, \r\n0,0,0,0,0,0)\r\n+ XTREG( 48,192,32, 4, 4,0x012f,0x0006,-2, 1,0x0002,ar47, \r\n0,0,0,0,0,0)\r\n+ XTREG( 49,196,32, 4, 4,0x0130,0x0006,-2, 1,0x0002,ar48, \r\n0,0,0,0,0,0)\r\n+ XTREG( 50,200,32, 4, 4,0x0131,0x0006,-2, 1,0x0002,ar49, \r\n0,0,0,0,0,0)\r\n+ XTREG( 51,204,32, 4, 4,0x0132,0x0006,-2, 1,0x0002,ar50, \r\n0,0,0,0,0,0)\r\n+ XTREG( 52,208,32, 4, 4,0x0133,0x0006,-2, 1,0x0002,ar51, \r\n0,0,0,0,0,0)\r\n+ XTREG( 53,212,32, 4, 4,0x0134,0x0006,-2, 1,0x0002,ar52, \r\n0,0,0,0,0,0)\r\n+ XTREG( 54,216,32, 4, 4,0x0135,0x0006,-2, 1,0x0002,ar53, \r\n0,0,0,0,0,0)\r\n+ XTREG( 55,220,32, 4, 4,0x0136,0x0006,-2, 1,0x0002,ar54, \r\n0,0,0,0,0,0)\r\n+ XTREG( 56,224,32, 4, 4,0x0137,0x0006,-2, 1,0x0002,ar55, \r\n0,0,0,0,0,0)\r\n+ XTREG( 57,228,32, 4, 4,0x0138,0x0006,-2, 1,0x0002,ar56, \r\n0,0,0,0,0,0)\r\n+ XTREG( 58,232,32, 4, 4,0x0139,0x0006,-2, 1,0x0002,ar57, \r\n0,0,0,0,0,0)\r\n+ XTREG( 59,236,32, 4, 4,0x013a,0x0006,-2, 1,0x0002,ar58, \r\n0,0,0,0,0,0)\r\n+ XTREG( 60,240,32, 4, 4,0x013b,0x0006,-2, 1,0x0002,ar59, \r\n0,0,0,0,0,0)\r\n+ XTREG( 61,244,32, 4, 4,0x013c,0x0006,-2, 1,0x0002,ar60, \r\n0,0,0,0,0,0)\r\n+ XTREG( 62,248,32, 4, 4,0x013d,0x0006,-2, 1,0x0002,ar61, \r\n0,0,0,0,0,0)\r\n+ XTREG( 63,252,32, 4, 4,0x013e,0x0006,-2, 1,0x0002,ar62, \r\n0,0,0,0,0,0)\r\n+ XTREG( 64,256,32, 4, 4,0x013f,0x0006,-2, 1,0x0002,ar63, \r\n0,0,0,0,0,0)\r\n+ XTREG( 65,260,32, 4, 4,0x0200,0x0006,-2, 2,0x1100,lbeg, \r\n0,0,0,0,0,0)\r\n+ XTREG( 66,264,32, 4, 4,0x0201,0x0006,-2, 2,0x1100,lend, \r\n0,0,0,0,0,0)\r\n+ XTREG( 67,268,32, 4, 4,0x0202,0x0006,-2, 2,0x1100,lcount, \r\n0,0,0,0,0,0)\r\n+ XTREG( 68,272, 6, 4, 4,0x0203,0x0006,-2, 2,0x1100,sar, \r\n0,0,0,0,0,0)\r\n+ XTREG( 69,276, 4, 4, 4,0x0248,0x0006,-2, 2,0x1002,windowbase, \r\n0,0,0,0,0,0)\r\n+ XTREG( 70,280,16, 4, 4,0x0249,0x0006,-2, 2,0x1002,windowstart,\r\n0,0,0,0,0,0)\r\n+ XTREG( 71,284,32, 4, 4,0x02b0,0x0002,-2, 2,0x1000,configid0, \r\n0,0,0,0,0,0)\r\n+ XTREG( 72,288,32, 4, 4,0x02d0,0x0002,-2, 2,0x1000,configid1, \r\n0,0,0,0,0,0)\r\n+ XTREG( 73,292,19, 4, 4,0x02e6,0x0006,-2, 2,0x1100,ps, \r\n0,0,0,0,0,0)\r\n+ XTREG( 74,296,32, 4, 4,0x03e7,0x0006,-2, 3,0x0110,threadptr, \r\n0,0,0,0,0,0)\r\n+ XTREG( 75,300,16, 4, 4,0x0204,0x0006,-1, 2,0x1100,br, \r\n0,0,0,0,0,0)\r\n+ XTREG( 76,304,32, 4, 4,0x020c,0x0006,-1, 2,0x1100,scompare1, \r\n0,0,0,0,0,0)\r\n+ XTREG( 77,308,32, 4, 4,0x0210,0x0006,-1, 2,0x1100,acclo, \r\n0,0,0,0,0,0)\r\n+ XTREG( 78,312, 8, 4, 4,0x0211,0x0006,-1, 2,0x1100,acchi, \r\n0,0,0,0,0,0)\r\n+ XTREG( 79,316,32, 4, 4,0x0220,0x0006,-1, 2,0x1100,m0, \r\n0,0,0,0,0,0)\r\n+ XTREG( 80,320,32, 4, 4,0x0221,0x0006,-1, 2,0x1100,m1, \r\n0,0,0,0,0,0)\r\n+ XTREG( 81,324,32, 4, 4,0x0222,0x0006,-1, 2,0x1100,m2, \r\n0,0,0,0,0,0)\r\n+ XTREG( 82,328,32, 4, 4,0x0223,0x0006,-1, 2,0x1100,m3, \r\n0,0,0,0,0,0)\r\n+ XTREG( 83,332, 8, 4, 4,0x030c,0x000e,-1, 3,0x0210,gpio_out, \r\n0,0,0,0,0,0)\r\n+ XTREG( 84,336,32, 4, 4,0x0030,0x0006, 0, 4,0x0401,f0,\r\n+ \"03:03:44:00\",\"03:03:04:00\",0,0,0,0)\r\n+ XTREG( 85,340,32, 4, 4,0x0031,0x0006, 0, 4,0x0401,f1,\r\n+ \"03:13:44:00\",\"03:13:04:00\",0,0,0,0)\r\n+ XTREG( 86,344,32, 4, 4,0x0032,0x0006, 0, 4,0x0401,f2,\r\n+ \"03:23:44:00\",\"03:23:04:00\",0,0,0,0)\r\n+ XTREG( 87,348,32, 4, 4,0x0033,0x0006, 0, 4,0x0401,f3,\r\n+ \"03:33:44:00\",\"03:33:04:00\",0,0,0,0)\r\n+ XTREG( 88,352,32, 4, 4,0x0034,0x0006, 0, 4,0x0401,f4,\r\n+ \"03:43:44:00\",\"03:43:04:00\",0,0,0,0)\r\n+ XTREG( 89,356,32, 4, 4,0x0035,0x0006, 0, 4,0x0401,f5,\r\n+ \"03:53:44:00\",\"03:53:04:00\",0,0,0,0)\r\n+ XTREG( 90,360,32, 4, 4,0x0036,0x0006, 0, 4,0x0401,f6,\r\n+ \"03:63:44:00\",\"03:63:04:00\",0,0,0,0)\r\n+ XTREG( 91,364,32, 4, 4,0x0037,0x0006, 0, 4,0x0401,f7,\r\n+ \"03:73:44:00\",\"03:73:04:00\",0,0,0,0)\r\n+ XTREG( 92,368,32, 4, 4,0x0038,0x0006, 0, 4,0x0401,f8,\r\n+ \"03:83:44:00\",\"03:83:04:00\",0,0,0,0)\r\n+ XTREG( 93,372,32, 4, 4,0x0039,0x0006, 0, 4,0x0401,f9,\r\n+ \"03:93:44:00\",\"03:93:04:00\",0,0,0,0)\r\n+ XTREG( 94,376,32, 4, 4,0x003a,0x0006, 0, 4,0x0401,f10,\r\n+ \"03:a3:44:00\",\"03:a3:04:00\",0,0,0,0)\r\n+ XTREG( 95,380,32, 4, 4,0x003b,0x0006, 0, 4,0x0401,f11,\r\n+ \"03:b3:44:00\",\"03:b3:04:00\",0,0,0,0)\r\n+ XTREG( 96,384,32, 4, 4,0x003c,0x0006, 0, 4,0x0401,f12,\r\n+ \"03:c3:44:00\",\"03:c3:04:00\",0,0,0,0)\r\n+ XTREG( 97,388,32, 4, 4,0x003d,0x0006, 0, 4,0x0401,f13,\r\n+ \"03:d3:44:00\",\"03:d3:04:00\",0,0,0,0)\r\n+ XTREG( 98,392,32, 4, 4,0x003e,0x0006, 0, 4,0x0401,f14,\r\n+ \"03:e3:44:00\",\"03:e3:04:00\",0,0,0,0)\r\n+ XTREG( 99,396,32, 4, 4,0x003f,0x0006, 0, 4,0x0401,f15,\r\n+ \"03:f3:44:00\",\"03:f3:04:00\",0,0,0,0)\r\n+ XTREG(100,400,32, 4, 4,0x03e8,0x0006, 0, 3,0x0100,fcr, \r\n0,0,0,0,0,0)\r\n+ XTREG(101,404,32, 4, 4,0x03e9,0x0006, 0, 3,0x0100,fsr, \r\n0,0,0,0,0,0)\r\n+ XTREG(102,408,32, 4, 4,0x0300,0x0006, 3, 3,0x0200,accx_0, \r\n0,0,0,0,0,0)\r\n+ XTREG(103,412, 8, 4, 4,0x0301,0x0006, 3, 3,0x0200,accx_1, \r\n0,0,0,0,0,0)\r\n+ XTREG(104,416,32, 4, 4,0x0302,0x0006, 3, 3,0x0200,qacc_h_0, \r\n0,0,0,0,0,0)\r\n+ XTREG(105,420,32, 4, 4,0x0303,0x0006, 3, 3,0x0200,qacc_h_1, \r\n0,0,0,0,0,0)\r\n+ XTREG(106,424,32, 4, 4,0x0304,0x0006, 3, 3,0x0200,qacc_h_2, \r\n0,0,0,0,0,0)\r\n+ XTREG(107,428,32, 4, 4,0x0305,0x0006, 3, 3,0x0200,qacc_h_3, \r\n0,0,0,0,0,0)\r\n+ XTREG(108,432,32, 4, 4,0x0306,0x0006, 3, 3,0x0200,qacc_h_4, \r\n0,0,0,0,0,0)\r\n+ XTREG(109,436,32, 4, 4,0x0307,0x0006, 3, 3,0x0200,qacc_l_0, \r\n0,0,0,0,0,0)\r\n+ XTREG(110,440,32, 4, 4,0x0308,0x0006, 3, 3,0x0200,qacc_l_1, \r\n0,0,0,0,0,0)\r\n+ XTREG(111,444,32, 4, 4,0x0309,0x0006, 3, 3,0x0200,qacc_l_2, \r\n0,0,0,0,0,0)\r\n+ XTREG(112,448,32, 4, 4,0x030a,0x0006, 3, 3,0x0200,qacc_l_3, \r\n0,0,0,0,0,0)\r\n+ XTREG(113,452,32, 4, 4,0x030b,0x0006, 3, 3,0x0200,qacc_l_4, \r\n0,0,0,0,0,0)\r\n+ XTREG(114,456, 4, 4, 4,0x030d,0x0006, 3, 3,0x0210,sar_byte, \r\n0,0,0,0,0,0)\r\n+ XTREG(115,460, 4, 4, 4,0x030e,0x0006, 3,\r\n3,0x0210,fft_bit_width,0,0,0,0,0,0)\r\n+ XTREG(116,464,32, 4, 4,0x030f,0x0006, 3, 3,0x0200,ua_state_0, \r\n0,0,0,0,0,0)\r\n+ XTREG(117,468,32, 4, 4,0x0310,0x0006, 3, 3,0x0200,ua_state_1, \r\n0,0,0,0,0,0)\r\n+ XTREG(118,472,32, 4, 4,0x0311,0x0006, 3, 3,0x0200,ua_state_2, \r\n0,0,0,0,0,0)\r\n+ XTREG(119,476,32, 4, 4,0x0312,0x0006, 3, 3,0x0200,ua_state_3, \r\n0,0,0,0,0,0)\r\n+ XTREG(120,480,128,16,16,0x1008,0x0006, 3, 4,0x0201,q0,\r\n+ \"03:44:60:cd\",\"03:44:20:cd\",0,0,0,0)\r\n+ XTREG(121,496,128,16,16,0x1009,0x0006, 3, 4,0x0201,q1,\r\n+ \"03:44:e0:cd\",\"03:44:a0:cd\",0,0,0,0)\r\n+ XTREG(122,512,128,16,16,0x100a,0x0006, 3, 4,0x0201,q2,\r\n+ \"03:44:60:dd\",\"03:44:20:dd\",0,0,0,0)\r\n+ XTREG(123,528,128,16,16,0x100b,0x0006, 3, 4,0x0201,q3,\r\n+ \"03:44:e0:dd\",\"03:44:a0:dd\",0,0,0,0)\r\n+ XTREG(124,544,128,16,16,0x100c,0x0006, 3, 4,0x0201,q4,\r\n+ \"03:44:60:ed\",\"03:44:20:ed\",0,0,0,0)\r\n+ XTREG(125,560,128,16,16,0x100d,0x0006, 3, 4,0x0201,q5,\r\n+ \"03:44:e0:ed\",\"03:44:a0:ed\",0,0,0,0)\r\n+ XTREG(126,576,128,16,16,0x100e,0x0006, 3, 4,0x0201,q6,\r\n+ \"03:44:60:fd\",\"03:44:20:fd\",0,0,0,0)\r\n+ XTREG(127,592,128,16,16,0x100f,0x0006, 3, 4,0x0201,q7,\r\n+ \"03:44:e0:fd\",\"03:44:a0:fd\",0,0,0,0)\r\n+ XTREG(128,608,32, 4, 4,0x0259,0x000d,-2, 2,0x1000,mmid, \r\n0,0,0,0,0,0)\r\n+ XTREG(129,612, 2, 4, 4,0x0260,0x0007,-2,\r\n2,0x1000,ibreakenable,0,0,0,0,0,0)\r\n+ XTREG(130,616, 1, 4, 4,0x0261,0x0007,-2, 2,0x1000,memctl, \r\n0,0,0,0,0,0)\r\n+ XTREG(131,620, 6, 4, 4,0x0263,0x0007,-2, 2,0x1000,atomctl, \r\n0,0,0,0,0,0)\r\n+ XTREG(132,624,32, 4, 4,0x0268,0x0007,-2, 2,0x1000,ddr, \r\n0,0,0,0,0,0)\r\n+ XTREG(133,628,32, 4, 4,0x0280,0x0007,-2, 2,0x1000,ibreaka0, \r\n0,0,0,0,0,0)\r\n+ XTREG(134,632,32, 4, 4,0x0281,0x0007,-2, 2,0x1000,ibreaka1, \r\n0,0,0,0,0,0)\r\n+ XTREG(135,636,32, 4, 4,0x0290,0x0007,-2, 2,0x1000,dbreaka0, \r\n0,0,0,0,0,0)\r\n+ XTREG(136,640,32, 4, 4,0x0291,0x0007,-2, 2,0x1000,dbreaka1, \r\n0,0,0,0,0,0)\r\n+ XTREG(137,644,32, 4, 4,0x02a0,0x0007,-2, 2,0x1000,dbreakc0, \r\n0,0,0,0,0,0)\r\n+ XTREG(138,648,32, 4, 4,0x02a1,0x0007,-2, 2,0x1000,dbreakc1, \r\n0,0,0,0,0,0)\r\n+ XTREG(139,652,32, 4, 4,0x02b1,0x0007,-2, 2,0x1000,epc1, \r\n0,0,0,0,0,0)\r\n+ XTREG(140,656,32, 4, 4,0x02b2,0x0007,-2, 2,0x1000,epc2, \r\n0,0,0,0,0,0)\r\n+ XTREG(141,660,32, 4, 4,0x02b3,0x0007,-2, 2,0x1000,epc3, \r\n0,0,0,0,0,0)\r\n+ XTREG(142,664,32, 4, 4,0x02b4,0x0007,-2, 2,0x1000,epc4, \r\n0,0,0,0,0,0)\r\n+ XTREG(143,668,32, 4, 4,0x02b5,0x0007,-2, 2,0x1000,epc5, \r\n0,0,0,0,0,0)\r\n+ XTREG(144,672,32, 4, 4,0x02b6,0x0007,-2, 2,0x1000,epc6, \r\n0,0,0,0,0,0)\r\n+ XTREG(145,676,32, 4, 4,0x02b7,0x0007,-2, 2,0x1000,epc7, \r\n0,0,0,0,0,0)\r\n+ XTREG(146,680,32, 4, 4,0x02c0,0x0007,-2, 2,0x1000,depc, \r\n0,0,0,0,0,0)\r\n+ XTREG(147,684,19, 4, 4,0x02c2,0x0007,-2, 2,0x1000,eps2, \r\n0,0,0,0,0,0)\r\n+ XTREG(148,688,19, 4, 4,0x02c3,0x0007,-2, 2,0x1000,eps3, \r\n0,0,0,0,0,0)\r\n+ XTREG(149,692,19, 4, 4,0x02c4,0x0007,-2, 2,0x1000,eps4, \r\n0,0,0,0,0,0)\r\n+ XTREG(150,696,19, 4, 4,0x02c5,0x0007,-2, 2,0x1000,eps5, \r\n0,0,0,0,0,0)\r\n+ XTREG(151,700,19, 4, 4,0x02c6,0x0007,-2, 2,0x1000,eps6, \r\n0,0,0,0,0,0)\r\n+ XTREG(152,704,19, 4, 4,0x02c7,0x0007,-2, 2,0x1000,eps7, \r\n0,0,0,0,0,0)\r\n+ XTREG(153,708,32, 4, 4,0x02d1,0x0007,-2, 2,0x1000,excsave1, \r\n0,0,0,0,0,0)\r\n+ XTREG(154,712,32, 4, 4,0x02d2,0x0007,-2, 2,0x1000,excsave2, \r\n0,0,0,0,0,0)\r\n+ XTREG(155,716,32, 4, 4,0x02d3,0x0007,-2, 2,0x1000,excsave3, \r\n0,0,0,0,0,0)\r\n+ XTREG(156,720,32, 4, 4,0x02d4,0x0007,-2, 2,0x1000,excsave4, \r\n0,0,0,0,0,0)\r\n+ XTREG(157,724,32, 4, 4,0x02d5,0x0007,-2, 2,0x1000,excsave5, \r\n0,0,0,0,0,0)\r\n+ XTREG(158,728,32, 4, 4,0x02d6,0x0007,-2, 2,0x1000,excsave6, \r\n0,0,0,0,0,0)\r\n+ XTREG(159,732,32, 4, 4,0x02d7,0x0007,-2, 2,0x1000,excsave7, \r\n0,0,0,0,0,0)\r\n+ XTREG(160,736, 8, 4, 4,0x02e0,0x0007,-2, 2,0x1000,cpenable, \r\n0,0,0,0,0,0)\r\n+ XTREG(161,740,32, 4, 4,0x02e2,0x000b,-2, 2,0x1000,interrupt, \r\n0,0,0,0,0,0)\r\n+ XTREG(162,744,32, 4, 4,0x02e2,0x000d,-2, 2,0x1000,intset, \r\n0,0,0,0,0,0)\r\n+ XTREG(163,748,32, 4, 4,0x02e3,0x000d,-2, 2,0x1000,intclear, \r\n0,0,0,0,0,0)\r\n+ XTREG(164,752,32, 4, 4,0x02e4,0x0007,-2, 2,0x1000,intenable, \r\n0,0,0,0,0,0)\r\n+ XTREG(165,756,32, 4, 4,0x02e7,0x0007,-2, 2,0x1000,vecbase, \r\n0,0,0,0,0,0)\r\n+ XTREG(166,760, 6, 4, 4,0x02e8,0x0007,-2, 2,0x1000,exccause, \r\n0,0,0,0,0,0)\r\n+ XTREG(167,764,12, 4, 4,0x02e9,0x0003,-2, 2,0x1000,debugcause, \r\n0,0,0,0,0,0)\r\n+ XTREG(168,768,32, 4, 4,0x02ea,0x000f,-2, 2,0x1000,ccount, \r\n0,0,0,0,0,0)\r\n+ XTREG(169,772,32, 4, 4,0x02eb,0x0003,-2, 2,0x1000,prid, \r\n0,0,0,0,0,0)\r\n+ XTREG(170,776,32, 4, 4,0x02ec,0x000f,-2, 2,0x1000,icount, \r\n0,0,0,0,0,0)\r\n+ XTREG(171,780, 4, 4, 4,0x02ed,0x0007,-2, 2,0x1000,icountlevel,\r\n0,0,0,0,0,0)\r\n+ XTREG(172,784,32, 4, 4,0x02ee,0x0007,-2, 2,0x1000,excvaddr, \r\n0,0,0,0,0,0)\r\n+ XTREG(173,788,32, 4, 4,0x02f0,0x000f,-2, 2,0x1000,ccompare0, \r\n0,0,0,0,0,0)\r\n+ XTREG(174,792,32, 4, 4,0x02f1,0x000f,-2, 2,0x1000,ccompare1, \r\n0,0,0,0,0,0)\r\n+ XTREG(175,796,32, 4, 4,0x02f2,0x000f,-2, 2,0x1000,ccompare2, \r\n0,0,0,0,0,0)\r\n+ XTREG(176,800,32, 4, 4,0x02f4,0x0007,-2, 2,0x1000,misc0, \r\n0,0,0,0,0,0)\r\n+ XTREG(177,804,32, 4, 4,0x02f5,0x0007,-2, 2,0x1000,misc1, \r\n0,0,0,0,0,0)\r\n+ XTREG(178,808,32, 4, 4,0x02f6,0x0007,-2, 2,0x1000,misc2, \r\n0,0,0,0,0,0)\r\n+ XTREG(179,812,32, 4, 4,0x02f7,0x0007,-2, 2,0x1000,misc3, \r\n0,0,0,0,0,0)\r\n+ XTREG(180,816,32, 4, 4,0x2028,0x000f,-2, 4,0x0101,pwrctl,\r\n+ \r\n\"03:52:64:01:03:62:64:02:03:52:a4:0c:03:60:55:11:03:52:c5:20:03:60:65:4\r\n0:03:62:64:00:03:52:24:01:03:62:24:02\",\"03:52:64:01:03:62:64:02:03:52:a\r\n4:0c:03:60:55:11:03:52:c5:20:03:62:24:00:03:60:75:40:03:52:24:01:03:62:\r\n24:02\",0,0,0,0)\r\n+ XTREG(181,820,32, 4, 4,0x2029,0x000f,-2, 4,0x0101,pwrstat,\r\n+ \r\n\"03:52:64:01:03:62:64:02:03:52:a4:0c:03:60:55:11:03:52:c5:24:03:60:65:4\r\n0:03:62:64:00:03:52:24:01:03:62:24:02\",\"03:52:64:01:03:62:64:02:03:52:a\r\n4:0c:03:60:55:11:03:52:c5:24:03:62:24:00:03:60:75:40:03:52:24:01:03:62:\r\n24:02\",0,0,0,0)\r\n+ XTREG(182,824, 1, 4, 4,0x202a,0x000f,-2, 4,0x0101,eristat,\r\n+ \r\n\"03:52:64:01:03:62:64:02:03:52:a4:0c:03:60:55:11:03:52:c5:28:03:60:65:4\r\n0:03:62:64:00:03:52:24:01:03:62:24:02\",\"03:52:64:01:03:62:64:02:03:52:a\r\n4:0c:03:60:55:11:03:52:c5:28:03:62:24:00:03:60:75:40:03:52:24:01:03:62:\r\n24:02\",0,0,0,0)\r\n+ XTREG(183,828,32, 4, 4,0x202b,0x000f,-2, 4,0x0101,cs_itctrl,\r\n+ \r\n\"03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:d5:03:03:60:65:4\r\n0:03:62:64:00:03:52:24:01:03:62:24:02\",\"03:52:64:01:03:62:64:02:03:52:a\r\n4:0f:03:60:55:11:03:52:d5:03:03:62:24:00:03:60:75:40:03:52:24:01:03:62:\r\n24:02\",0,0,0,0)\r\n+ XTREG(184,832,16, 4, 4,0x202c,0x000f,-2, 4,0x0101,cs_claimset,\r\n+ \r\n\"03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:c5:a0:03:52:d5:0\r\n4:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02\",\"03:52:64:01:03:62:6\r\n4:02:03:52:a4:0f:03:60:55:11:03:52:c5:a0:03:52:d5:04:03:62:24:00:03:60:\r\n75:40:03:52:24:01:03:62:24:02\",0,0,0,0)\r\n+ XTREG(185,836,16, 4, 4,0x202d,0x000f,-2, 4,0x0101,cs_claimclr,\r\n+ \r\n\"03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:c5:a4:03:52:d5:0\r\n4:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02\",\"03:52:64:01:03:62:6\r\n4:02:03:52:a4:0f:03:60:55:11:03:52:c5:a4:03:52:d5:04:03:62:24:00:03:60:\r\n75:40:03:52:24:01:03:62:24:02\",0,0,0,0)\r\n+ XTREG(186,840,32, 4, 4,0x202e,0x000d,-2, 4,0x0101,cs_lockaccess,\r\n+ \r\n\"03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:c5:b0:03:52:d5:0\r\n4:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02\",\"03:52:64:01:03:62:6\r\n4:02:03:52:a4:0f:03:60:55:11:03:52:c5:b0:03:52:d5:04:03:62:24:00:03:60:\r\n75:40:03:52:24:01:03:62:24:02\",0,0,0,0)\r\n+ XTREG(187,844,32, 4, 4,0x202f,0x000b,-2, 4,0x0101,cs_lockstatus,\r\n+ \r\n\"03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:c5:b4:03:52:d5:0\r\n4:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02\",\"03:52:64:01:03:62:6\r\n4:02:03:52:a4:0f:03:60:55:11:03:52:c5:b4:03:52:d5:04:03:62:24:00:03:60:\r\n75:40:03:52:24:01:03:62:24:02\",0,0,0,0)\r\n+ XTREG(188,848, 1, 4, 4,0x2030,0x000b,-2, 4,0x0101,cs_authstatus,\r\n+ \r\n\"03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:c5:b8:03:52:d5:0\r\n4:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02\",\"03:52:64:01:03:62:6\r\n4:02:03:52:a4:0f:03:60:55:11:03:52:c5:b8:03:52:d5:04:03:62:24:00:03:60:\r\n75:40:03:52:24:01:03:62:24:02\",0,0,0,0)\r\n+ XTREG(189,852,32, 4, 4,0x203f,0x000f,-2, 4,0x0101,fault_info,\r\n+ \r\n\"03:52:64:01:03:62:64:02:03:52:a4:0c:03:60:55:11:03:52:c5:30:03:60:65:4\r\n0:03:62:64:00:03:52:24:01:03:62:24:02\",\"03:52:64:01:03:62:64:02:03:52:a\r\n4:0c:03:60:55:11:03:52:c5:30:03:62:24:00:03:60:75:40:03:52:24:01:03:62:\r\n24:02\",0,0,0,0)\r\n+ XTREG(190,856,32, 4, 4,0x2040,0x0003,-2, 4,0x0101,trax_id,\r\n+ \r\n\"03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:60:65:40:03:62:64:0\r\n0:03:52:24:01:03:62:24:02\",\"03:52:64:01:03:62:64:02:03:52:a4:00:03:60:5\r\n5:11:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02\",0,0,0,0)\r\n+ XTREG(191,860,32, 4, 4,0x2041,0x000f,-2, 4,0x0101,trax_control,\r\n+ \r\n\"03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:04:03:60:65:4\r\n0:03:62:64:00:03:52:24:01:03:62:24:02\",\"03:52:64:01:03:62:64:02:03:52:a\r\n4:00:03:60:55:11:03:52:c5:04:03:62:24:00:03:60:75:40:03:52:24:01:03:62:\r\n24:02\",0,0,0,0)\r\n+ XTREG(192,864,32, 4, 4,0x2042,0x000b,-2, 4,0x0101,trax_status,\r\n+ \r\n\"03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:08:03:60:65:4\r\n0:03:62:64:00:03:52:24:01:03:62:24:02\",\"03:52:64:01:03:62:64:02:03:52:a\r\n4:00:03:60:55:11:03:52:c5:08:03:62:24:00:03:60:75:40:03:52:24:01:03:62:\r\n24:02\",0,0,0,0)\r\n+ XTREG(193,868,32, 4, 4,0x2043,0x000f,-2, 4,0x0101,trax_data,\r\n+ \r\n\"03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:0c:03:60:65:4\r\n0:03:62:64:00:03:52:24:01:03:62:24:02\",\"03:52:64:01:03:62:64:02:03:52:a\r\n4:00:03:60:55:11:03:52:c5:0c:03:62:24:00:03:60:75:40:03:52:24:01:03:62:\r\n24:02\",0,0,0,0)\r\n+ XTREG(194,872,32, 4, 4,0x2044,0x000f,-2, 4,0x0101,trax_address,\r\n+ \r\n\"03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:10:03:60:65:4\r\n0:03:62:64:00:03:52:24:01:03:62:24:02\",\"03:52:64:01:03:62:64:02:03:52:a\r\n4:00:03:60:55:11:03:52:c5:10:03:62:24:00:03:60:75:40:03:52:24:01:03:62:\r\n24:02\",0,0,0,0)\r\n+ XTREG(195,876,32, 4, 4,0x2045,0x000f,-2, 4,0x0101,trax_pctrigger,\r\n+ \r\n\"03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:14:03:60:65:4\r\n0:03:62:64:00:03:52:24:01:03:62:24:02\",\"03:52:64:01:03:62:64:02:03:52:a\r\n4:00:03:60:55:11:03:52:c5:14:03:62:24:00:03:60:75:40:03:52:24:01:03:62:\r\n24:02\",0,0,0,0)\r\n+ XTREG(196,880,32, 4, 4,0x2046,0x000f,-2, 4,0x0101,trax_pcmatch,\r\n+ \r\n\"03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:18:03:60:65:4\r\n0:03:62:64:00:03:52:24:01:03:62:24:02\",\"03:52:64:01:03:62:64:02:03:52:a\r\n4:00:03:60:55:11:03:52:c5:18:03:62:24:00:03:60:75:40:03:52:24:01:03:62:\r\n24:02\",0,0,0,0)\r\n+ XTREG(197,884,32, 4, 4,0x2047,0x000f,-2, 4,0x0101,trax_delay,\r\n+ \r\n\"03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:1c:03:60:65:4\r\n0:03:62:64:00:03:52:24:01:03:62:24:02\",\"03:52:64:01:03:62:64:02:03:52:a\r\n4:00:03:60:55:11:03:52:c5:1c:03:62:24:00:03:60:75:40:03:52:24:01:03:62:\r\n24:02\",0,0,0,0)\r\n+ XTREG(198,888,32, 4, 4,0x2048,0x000f,-2, 4,0x0101,trax_memstart,\r\n+ \r\n\"03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:20:03:60:65:4\r\n0:03:62:64:00:03:52:24:01:03:62:24:02\",\"03:52:64:01:03:62:64:02:03:52:a\r\n4:00:03:60:55:11:03:52:c5:20:03:62:24:00:03:60:75:40:03:52:24:01:03:62:\r\n24:02\",0,0,0,0)\r\n+ XTREG(199,892,32, 4, 4,0x2049,0x000f,-2, 4,0x0101,trax_memend,\r\n+ \r\n\"03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:24:03:60:65:4\r\n0:03:62:64:00:03:52:24:01:03:62:24:02\",\"03:52:64:01:03:62:64:02:03:52:a\r\n4:00:03:60:55:11:03:52:c5:24:03:62:24:00:03:60:75:40:03:52:24:01:03:62:\r\n24:02\",0,0,0,0)\r\n+ XTREG(200,896,32, 4, 4,0x2057,0x000f,-2, 4,0x0101,pmg,\r\n+ \r\n\"03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:60:65:40:03:62:64:0\r\n0:03:52:24:01:03:62:24:02\",\"03:52:64:01:03:62:64:02:03:52:a4:04:03:60:5\r\n5:11:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02\",0,0,0,0)\r\n+ XTREG(201,900,32, 4, 4,0x2058,0x000f,-2, 4,0x0101,pmpc,\r\n+ \r\n\"03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:04:03:60:65:4\r\n0:03:62:64:00:03:52:24:01:03:62:24:02\",\"03:52:64:01:03:62:64:02:03:52:a\r\n4:04:03:60:55:11:03:52:c5:04:03:62:24:00:03:60:75:40:03:52:24:01:03:62:\r\n24:02\",0,0,0,0)\r\n+ XTREG(202,904,32, 4, 4,0x2059,0x000f,-2, 4,0x0101,pm0,\r\n+ \r\n\"03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:80:03:52:d5:0\r\n1:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02\",\"03:52:64:01:03:62:6\r\n4:02:03:52:a4:04:03:60:55:11:03:52:c5:80:03:52:d5:01:03:62:24:00:03:60:\r\n75:40:03:52:24:01:03:62:24:02\",0,0,0,0)\r\n+ XTREG(203,908,32, 4, 4,0x205a,0x000f,-2, 4,0x0101,pm1,\r\n+ \r\n\"03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:80:03:52:d5:0\r\n1:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02\",\"03:52:64:01:03:62:6\r\n4:02:03:52:a4:04:03:60:55:11:03:52:c5:80:03:52:d5:01:03:62:24:00:03:60:\r\n75:40:03:52:24:01:03:62:24:02\",0,0,0,0)\r\n+ XTREG(204,912,32, 4, 4,0x205b,0x000f,-2, 4,0x0101,pmctrl0,\r\n+ \r\n\"03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:d5:01:03:60:65:4\r\n0:03:62:64:00:03:52:24:01:03:62:24:02\",\"03:52:64:01:03:62:64:02:03:52:a\r\n4:04:03:60:55:11:03:52:d5:01:03:62:24:00:03:60:75:40:03:52:24:01:03:62:\r\n24:02\",0,0,0,0)\r\n+ XTREG(205,916,32, 4, 4,0x205c,0x000f,-2, 4,0x0101,pmctrl1,\r\n+ \r\n\"03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:d5:01:03:60:65:4\r\n0:03:62:64:00:03:52:24:01:03:62:24:02\",\"03:52:64:01:03:62:64:02:03:52:a\r\n4:04:03:60:55:11:03:52:d5:01:03:62:24:00:03:60:75:40:03:52:24:01:03:62:\r\n24:02\",0,0,0,0)\r\n+ XTREG(206,920,32, 4, 4,0x205d,0x000f,-2, 4,0x0101,pmstat0,\r\n+ \r\n\"03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:80:03:52:d5:0\r\n2:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02\",\"03:52:64:01:03:62:6\r\n4:02:03:52:a4:04:03:60:55:11:03:52:c5:80:03:52:d5:02:03:62:24:00:03:60:\r\n75:40:03:52:24:01:03:62:24:02\",0,0,0,0)\r\n+ XTREG(207,924,32, 4, 4,0x205e,0x000f,-2, 4,0x0101,pmstat1,\r\n+ \r\n\"03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:80:03:52:d5:0\r\n2:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02\",\"03:52:64:01:03:62:6\r\n4:02:03:52:a4:04:03:60:55:11:03:52:c5:80:03:52:d5:02:03:62:24:00:03:60:\r\n75:40:03:52:24:01:03:62:24:02\",0,0,0,0)\r\n+ XTREG(208,928,32, 4, 4,0x205f,0x0003,-2, 4,0x0101,ocdid,\r\n+ \r\n\"03:52:64:01:03:62:64:02:03:52:a4:08:03:60:55:11:03:60:65:40:03:62:64:0\r\n0:03:52:24:01:03:62:24:02\",\"03:52:64:01:03:62:64:02:03:52:a4:08:03:60:5\r\n5:11:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02\",0,0,0,0)\r\n+ XTREG(209,932,32, 4, 4,0x2060,0x000f,-2, 4,0x0101,ocd_dcrclr,\r\n+ \r\n\"03:52:64:01:03:62:64:02:03:52:a4:08:03:60:55:11:03:52:c5:08:03:60:65:4\r\n0:03:62:64:00:03:52:24:01:03:62:24:02\",\"03:52:64:01:03:62:64:02:03:52:a\r\n4:08:03:60:55:11:03:52:c5:08:03:62:24:00:03:60:75:40:03:52:24:01:03:62:\r\n24:02\",0,0,0,0)\r\n+ XTREG(210,936,32, 4, 4,0x2061,0x000f,-2, 4,0x0101,ocd_dcrset,\r\n+ \r\n\"03:52:64:01:03:62:64:02:03:52:a4:08:03:60:55:11:03:52:c5:0c:03:60:65:4\r\n0:03:62:64:00:03:52:24:01:03:62:24:02\",\"03:52:64:01:03:62:64:02:03:52:a\r\n4:08:03:60:55:11:03:52:c5:0c:03:62:24:00:03:60:75:40:03:52:24:01:03:62:\r\n24:02\",0,0,0,0)\r\n+ XTREG(211,940,32, 4, 4,0x2062,0x000f,-2, 4,0x0101,ocd_dsr,\r\n+ \r\n\"03:52:64:01:03:62:64:02:03:52:a4:08:03:60:55:11:03:52:c5:10:03:60:65:4\r\n0:03:62:64:00:03:52:24:01:03:62:24:02\",\"03:52:64:01:03:62:64:02:03:52:a\r\n4:08:03:60:55:11:03:52:c5:10:03:62:24:00:03:60:75:40:03:52:24:01:03:62:\r\n24:02\",0,0,0,0)\r\n+ XTREG(212,944,32, 4, 4,0x0000,0x0006,-2, 8,0x2100,a0, \r\n0,0,0,0,0,0)\r\n+ XTREG(213,948,32, 4, 4,0x0001,0x0006,-2, 8,0x2100,a1, \r\n0,0,0,0,0,0)\r\n+ XTREG(214,952,32, 4, 4,0x0002,0x0006,-2, 8,0x2100,a2, \r\n0,0,0,0,0,0)\r\n+ XTREG(215,956,32, 4, 4,0x0003,0x0006,-2, 8,0x2100,a3, \r\n0,0,0,0,0,0)\r\n+ XTREG(216,960,32, 4, 4,0x0004,0x0006,-2, 8,0x2100,a4, \r\n0,0,0,0,0,0)\r\n+ XTREG(217,964,32, 4, 4,0x0005,0x0006,-2, 8,0x2100,a5, \r\n0,0,0,0,0,0)\r\n+ XTREG(218,968,32, 4, 4,0x0006,0x0006,-2, 8,0x2100,a6, \r\n0,0,0,0,0,0)\r\n+ XTREG(219,972,32, 4, 4,0x0007,0x0006,-2, 8,0x2100,a7, \r\n0,0,0,0,0,0)\r\n+ XTREG(220,976,32, 4, 4,0x0008,0x0006,-2, 8,0x2100,a8, \r\n0,0,0,0,0,0)\r\n+ XTREG(221,980,32, 4, 4,0x0009,0x0006,-2, 8,0x2100,a9, \r\n0,0,0,0,0,0)\r\n+ XTREG(222,984,32, 4, 4,0x000a,0x0006,-2, 8,0x2100,a10, \r\n0,0,0,0,0,0)\r\n+ XTREG(223,988,32, 4, 4,0x000b,0x0006,-2, 8,0x2100,a11, \r\n0,0,0,0,0,0)\r\n+ XTREG(224,992,32, 4, 4,0x000c,0x0006,-2, 8,0x2100,a12, \r\n0,0,0,0,0,0)\r\n+ XTREG(225,996,32, 4, 4,0x000d,0x0006,-2, 8,0x2100,a13, \r\n0,0,0,0,0,0)\r\n+ XTREG(226,1000,32, 4, 4,0x000e,0x0006,-2, 8,0x2100,a14, \r\n0,0,0,0,0,0)\r\n+ XTREG(227,1004,32, 4, 4,0x000f,0x0006,-2, 8,0x2100,a15, \r\n0,0,0,0,0,0)\r\n+ XTREG(228,1008, 1, 1, 1,0x0010,0x0006,-2, 6,0x1010,b0,\r\n+ 0,0,&xtensa_mask0,0,0,0)\r\n+ XTREG(229,1009, 1, 1, 1,0x0011,0x0006,-2, 6,0x1010,b1,\r\n+ 0,0,&xtensa_mask1,0,0,0)\r\n+ XTREG(230,1010, 1, 1, 1,0x0012,0x0006,-2, 6,0x1010,b2,\r\n+ 0,0,&xtensa_mask2,0,0,0)\r\n+ XTREG(231,1011, 1, 1, 1,0x0013,0x0006,-2, 6,0x1010,b3,\r\n+ 0,0,&xtensa_mask3,0,0,0)\r\n+ XTREG(232,1012, 1, 1, 1,0x0014,0x0006,-2, 6,0x1010,b4,\r\n+ 0,0,&xtensa_mask4,0,0,0)\r\n+ XTREG(233,1013, 1, 1, 1,0x0015,0x0006,-2, 6,0x1010,b5,\r\n+ 0,0,&xtensa_mask5,0,0,0)\r\n+ XTREG(234,1014, 1, 1, 1,0x0016,0x0006,-2, 6,0x1010,b6,\r\n+ 0,0,&xtensa_mask6,0,0,0)\r\n+ XTREG(235,1015, 1, 1, 1,0x0017,0x0006,-2, 6,0x1010,b7,\r\n+ 0,0,&xtensa_mask7,0,0,0)\r\n+ XTREG(236,1016, 1, 1, 1,0x0018,0x0006,-2, 6,0x1010,b8,\r\n+ 0,0,&xtensa_mask8,0,0,0)\r\n+ XTREG(237,1017, 1, 1, 1,0x0019,0x0006,-2, 6,0x1010,b9,\r\n+ 0,0,&xtensa_mask9,0,0,0)\r\n+ XTREG(238,1018, 1, 1, 1,0x001a,0x0006,-2, 6,0x1010,b10,\r\n+ 0,0,&xtensa_mask10,0,0,0)\r\n+ XTREG(239,1019, 1, 1, 1,0x001b,0x0006,-2, 6,0x1010,b11,\r\n+ 0,0,&xtensa_mask11,0,0,0)\r\n+ XTREG(240,1020, 1, 1, 1,0x001c,0x0006,-2, 6,0x1010,b12,\r\n+ 0,0,&xtensa_mask12,0,0,0)\r\n+ XTREG(241,1021, 1, 1, 1,0x001d,0x0006,-2, 6,0x1010,b13,\r\n+ 0,0,&xtensa_mask13,0,0,0)\r\n+ XTREG(242,1022, 1, 1, 1,0x001e,0x0006,-2, 6,0x1010,b14,\r\n+ 0,0,&xtensa_mask14,0,0,0)\r\n+ XTREG(243,1023, 1, 1, 1,0x001f,0x0006,-2, 6,0x1010,b15,\r\n+ 0,0,&xtensa_mask15,0,0,0)\r\n+ XTREG(244,1024, 4, 4, 4,0x2008,0x0006,-2, 6,0x1010,psintlevel,\r\n+ 0,0,&xtensa_mask16,0,0,0)\r\n+ XTREG(245,1028, 1, 4, 4,0x2009,0x0006,-2, 6,0x1010,psum,\r\n+ 0,0,&xtensa_mask17,0,0,0)\r\n+ XTREG(246,1032, 1, 4, 4,0x200a,0x0006,-2, 6,0x1010,pswoe,\r\n+ 0,0,&xtensa_mask18,0,0,0)\r\n+ XTREG(247,1036, 1, 4, 4,0x200b,0x0006,-2, 6,0x1010,psexcm,\r\n+ 0,0,&xtensa_mask19,0,0,0)\r\n+ XTREG(248,1040, 2, 4, 4,0x200c,0x0006,-2, 6,0x1010,pscallinc,\r\n+ 0,0,&xtensa_mask20,0,0,0)\r\n+ XTREG(249,1044, 4, 4, 4,0x200d,0x0006,-2, 6,0x1010,psowb,\r\n+ 0,0,&xtensa_mask21,0,0,0)\r\n+ XTREG(250,1048,40, 8, 4,0x200e,0x0006,-2, 6,0x1010,acc,\r\n+ 0,0,&xtensa_mask22,0,0,0)\r\n+ XTREG(251,1056, 4, 4, 4,0x2013,0x0006,-2, 6,0x1010,dbnum,\r\n+ 0,0,&xtensa_mask23,0,0,0)\r\n+ XTREG(252,1060, 2, 4, 4,0x2015,0x0006, 0, 5,0x1010,roundmode,\r\n+ 0,0,&xtensa_mask24,0,0,0)\r\n+ XTREG(253,1064, 1, 4, 4,0x2016,0x0006, 0, 5,0x1010,invalidenable,\r\n+ 0,0,&xtensa_mask25,0,0,0)\r\n+ XTREG(254,1068, 1, 4, 4,0x2017,0x0006, 0, 5,0x1010,divzeroenable,\r\n+ 0,0,&xtensa_mask26,0,0,0)\r\n+ XTREG(255,1072, 1, 4, 4,0x2018,0x0006, 0, 5,0x1010,overflowenable,\r\n+ 0,0,&xtensa_mask27,0,0,0)\r\n+ XTREG(256,1076, 1, 4, 4,0x2019,0x0006, 0, 5,0x1010,underflowenable,\r\n+ 0,0,&xtensa_mask28,0,0,0)\r\n+ XTREG(257,1080, 1, 4, 4,0x201a,0x0006, 0, 5,0x1010,inexactenable,\r\n+ 0,0,&xtensa_mask29,0,0,0)\r\n+ XTREG(258,1084, 1, 4, 4,0x201b,0x0006, 0, 5,0x1010,invalidflag,\r\n+ 0,0,&xtensa_mask30,0,0,0)\r\n+ XTREG(259,1088, 1, 4, 4,0x201c,0x0006, 0, 5,0x1010,divzeroflag,\r\n+ 0,0,&xtensa_mask31,0,0,0)\r\n+ XTREG(260,1092, 1, 4, 4,0x201d,0x0006, 0, 5,0x1010,overflowflag,\r\n+ 0,0,&xtensa_mask32,0,0,0)\r\n+ XTREG(261,1096, 1, 4, 4,0x201e,0x0006, 0, 5,0x1010,underflowflag,\r\n+ 0,0,&xtensa_mask33,0,0,0)\r\n+ XTREG(262,1100, 1, 4, 4,0x201f,0x0006, 0, 5,0x1010,inexactflag,\r\n+ 0,0,&xtensa_mask34,0,0,0)\r\n+ XTREG(263,1104,20, 4, 4,0x2020,0x0006, 0, 5,0x1010,fpreserved20,\r\n+ 0,0,&xtensa_mask35,0,0,0)\r\n+ XTREG(264,1108,20, 4, 4,0x2021,0x0006, 0, 5,0x1010,fpreserved20a,\r\n+ 0,0,&xtensa_mask36,0,0,0)\r\n+ XTREG(265,1112, 5, 4, 4,0x2022,0x0006, 0, 5,0x1010,fpreserved5,\r\n+ 0,0,&xtensa_mask37,0,0,0)\r\n+ XTREG(266,1116, 7, 4, 4,0x2023,0x0006, 0, 5,0x1010,fpreserved7,\r\n+ 0,0,&xtensa_mask38,0,0,0)\r\n+ XTREG(267,1120,40, 8, 4,0x2024,0x0006, 3, 5,0x0210,accx,\r\n+ 0,0,&xtensa_mask39,0,0,0)\r\n+ XTREG(268,1128,160,20, 4,0x2025,0x0006, 3, 5,0x0210,qacc_h,\r\n+ 0,0,&xtensa_mask40,0,0,0)\r\n+ XTREG(269,1148,160,20, 4,0x2026,0x0006, 3, 5,0x0210,qacc_l,\r\n+ 0,0,&xtensa_mask41,0,0,0)\r\n+ XTREG_END\r\n+};\r\n+\r\n+xtensa_gdbarch_tdep xtensa_tdep_esp32s3 (rmap);\r\ndiff --git a/gdb/xtensa-tdep.c b/gdb/xtensa-tdep.c\r\nindex b6558838e44..5a884cc1175 100644\r\n--- a/gdb/xtensa-tdep.c\r\n+++ b/gdb/xtensa-tdep.c\r\n@@ -42,6 +42,7 @@\r\n #include \"xtensa-isa.h\"\r\n #include \"xtensa-tdep.h\"\r\n #include \"xtensa-config.h\"\r\n+#include \"elf/xtensa.h\"\r\n #include \r\n \r\n \r\n@@ -930,6 +931,7 @@ typedef struct xtensa_windowed_frame_cache\r\n #define C0_NOSTK -1\t/* to_stk value if register has not been\r\nstored. */\r\n \r\n extern xtensa_isa xtensa_default_isa;\r\n+extern xtensa_isa xtensa_modules;\r\n \r\n typedef struct xtensa_c0reg\r\n {\r\n@@ -3152,9 +3154,66 @@ xtensa_derive_tdep (xtensa_gdbarch_t 100 115k 100 115k 100 150 2022k 2631 --:--:-- --:--:-- --:--:-- 2024k dep *tdep)\r\n tdep->max_register_virtual_size = max_size;\r\n }\r\n \r\n-/* Module \"constructor\" function. */\r\n+extern xtensa_gdbarch_tdep xtensa_tdep_default;\r\n+extern xtensa_gdbarch_tdep xtensa_tdep_esp32;\r\n+extern xtensa_gdbarch_tdep xtensa_tdep_esp32s2;\r\n+extern xtensa_gdbarch_tdep xtensa_tdep_esp32s3;\r\n+\r\n+xtensa_gdbarch_tdep *current_tdep = &xtensa_tdep_default;\r\n+/* Keep it synced with xtensa_isa_modules. */\r\n+xtensa_gdbarch_tdep *xtensa_tdeps[] =\r\n+{\r\n+ &xtensa_tdep_default,\r\n+ &xtensa_tdep_esp32,\r\n+ &xtensa_tdep_esp32s2,\r\n+ &xtensa_tdep_esp32s2\r\n+};\r\n+\r\n+static void\r\n+apply_xtensa_info_config (bfd *abfd)\r\n+{\r\n+ asection *info_sec;\r\n+ xtensa_info_entries xtensa_info;\r\n \r\n-extern xtensa_gdbarch_tdep xtensa_tdep;\r\n+ if (! abfd)\r\n+ return;\r\n+\r\n+ info_sec = bfd_get_section_by_name (abfd, \".xtensa.info\");\r\n+\r\n+ if (! info_sec)\r\n+ return;\r\n+\r\n+ if (! read_xtensa_info (abfd, info_sec, &xtensa_info))\r\n+ return;\r\n+\r\n+ /* Process ISA_MODULE */\r\n+ if (xtensa_info.isa_module < 0\r\n+ || xtensa_info.isa_module >= xtensa_isa_modules_count)\r\n+ {\r\n+ warning (_(\"Unknown xtensa isa-module, use the default.\"));\r\n+ xtensa_info.isa_module = 0;\r\n+ }\r\n+\r\n+ xtensa_default_isa = NULL;\r\n+ xtensa_modules =\r\nxtensa_isa_modules[xtensa_info.isa_module].isa_module;\r\n+ current_tdep = xtensa_tdeps[xtensa_info.isa_module];\r\n+\r\n+ if (xtensa_info.isa_module > 0)\r\n+ {\r\n+ current_tdep->num_aregs =\r\nxtensa_regfile_num_entries(xtensa_modules, 0);\r\n+ }\r\n+\r\n+ /* Process ABI */\r\n+ current_tdep->call_abi = (xtensa_info.abi == XTHAL_ABI_CALL0\r\n+ ? CallAbiCall0Only : CallAbiDefault);\r\n+ current_tdep->isa_use_windowed_registers = xtensa_info.abi !=\r\n+ XTHAL_ABI_CALL0;\r\n+\r\n+ /* Process USE_ABSOLUTE_LITERALS */\r\n+ current_tdep->isa_use_ext_l32r = xtensa_info.use_absolute_literals;\r\n+}\r\n+\r\n+/* Module \"constructor\" function. */\r\n \r\n static struct gdbarch *\r\n xtensa_gdbarch_init (struct gdbarch_info info, struct gdbarch_list\r\n*arches)\r\n@@ -3163,13 +3222,12 @@ xtensa_gdbarch_init (struct gdbarch_info info,\r\nstruct gdbarch_list *arches)\r\n \r\n DEBUGTRACE (\"gdbarch_init()\\n\");\r\n \r\n+ apply_xtensa_info_config(info.abfd);\r\n+\r\n if (!xtensa_default_isa)\r\n xtensa_default_isa = xtensa_isa_init (0, 0);\r\n \r\n- /* We have to set the byte order before we call gdbarch_alloc. */\r\n- info.byte_order = XCHAL_HAVE_BE ? BFD_ENDIAN_BIG :\r\nBFD_ENDIAN_LITTLE;\r\n-\r\n- xtensa_gdbarch_tdep *tdep = &xtensa_tdep;\r\n+ xtensa_gdbarch_tdep *tdep = current_tdep;\r\n gdbarch = gdbarch_alloc (&info, tdep);\r\n xtensa_derive_tdep (tdep);\r\n \r\ndiff --git a/gdb/xtensa-tdep.h b/gdb/xtensa-tdep.h\r\nindex 1840ef98b49..bdd06bc28fc 100644\r\n--- a/gdb/xtensa-tdep.h\r\n+++ b/gdb/xtensa-tdep.h\r\n@@ -126,7 +126,7 @@ typedef struct\r\n const char *store;\t\t/* Instruction sequence to store\r\nregister. */\r\n } xtensa_register_t;\r\n \r\n-/* For xtensa-config.c to expand to the structure above. */\r\n+/* For xtensa-config-*.c to expand to the structure above. */\r\n #define\r\nXTREG(index,ofs,bsz,sz,al,tnum,flg,cp,ty,gr,name,fet,sto,mas,ct,x,y) \\\r\n","prefixes":["5/5"]}+ exit 1 Build step 'Execute shell' marked build as failure Finished: FAILURE