Started by user snail Running as SYSTEM [EnvInject] - Loading node environment variables. Building remotely on docker-jenkins-agent in workspace /home/jenkins/agent/workspace/binutils-gdb [WS-CLEANUP] Deleting project workspace... [WS-CLEANUP] Deferred wipeout is used... [WS-CLEANUP] Done The recommended git tool is: NONE using credential 0adb5fc7-caa2-429d-97d2-c7fa2fa1d884 Cloning the remote Git repository Using shallow clone with depth 1 Avoid fetching tags Cloning repository git@github.com:plctlab/patchwork-binutils-gdb.git > git init /home/jenkins/agent/workspace/binutils-gdb # timeout=10 Fetching upstream changes from git@github.com:plctlab/patchwork-binutils-gdb.git > git --version # timeout=10 > git --version # 'git version 2.37.2' using GIT_SSH to set credentials patchwork github wangliu-iscas git ssh key Verifying host key using known hosts file, will automatically accept unseen keys > git fetch --no-tags --force --progress --depth=1 -- git@github.com:plctlab/patchwork-binutils-gdb.git +refs/heads/*:refs/remotes/origin/* # timeout=10 > git config remote.origin.url git@github.com:plctlab/patchwork-binutils-gdb.git # timeout=10 > git config --add remote.origin.fetch +refs/heads/*:refs/remotes/origin/* # timeout=10 Avoid second fetch > git rev-parse refs/remotes/origin/master^{commit} # timeout=10 Checking out Revision 324998b47364528f407666512015370c12ab83a1 (refs/remotes/origin/master) > git config core.sparsecheckout # timeout=10 > git checkout -f 324998b47364528f407666512015370c12ab83a1 # timeout=10 Commit message: "Automatic date update in version.in" > git rev-list --no-walk 324998b47364528f407666512015370c12ab83a1 # timeout=10 [EnvInject] - Mask passwords that will be passed as build parameters. [EnvInject] - Executing scripts and injecting environment variables after the SCM step. [EnvInject] - Injecting as environment variables the properties content GITHUB_REPO=https://github.com/plctlab/patchwork-binutils-gdb PATCHWORK_URL=https://patchwork.plctlab.org [EnvInject] - Variables injected successfully. [binutils-gdb] $ /usr/bin/env bash /tmp/jenkins9391484015519060633.sh + git config pw.server https://patchwork.plctlab.org/api/1.2/ + git config pw.project binutils-gdb + git config pw.token [*******] ++ date +%Y-%m + now_date=2023-03 ++ date +%Y + now_date_year=2023 + bundle_name=binutils-gdb_2023-03 ++ curl -s -H 'Authorization: Token [*******]' 'https://patchwork.plctlab.org/api/1.2/bundles/?project=binutils-gdb&per_page=999' + bundle_response='[{"id":6,"url":"https://patchwork.plctlab.org/api/1.2/bundles/6/","web_url":"https://patchwork.plctlab.org/bundle/patchwork-bot/binutils-gdb_2022-10/","project":{"id":2,"url":"https://patchwork.plctlab.org/api/1.2/projects/2/","name":"binutils-gdb","link_name":"binutils-gdb","list_id":"binutils.sourceware.org","list_email":"binutils@sourceware.org","web_url":"https://github.com/wangliu-iscas/Patchwork-Bundles/blob/main/binutils-gdb.md","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"name":"binutils-gdb_2022-10","owner":{"id":3,"url":"https://patchwork.plctlab.org/api/1.2/users/3/","username":"patchwork-bot","first_name":"","last_name":"","email":"ouuuleilei@gmail.com"},"patches":[{"id":1592,"url":"https://patchwork.plctlab.org/api/1.2/patches/1592/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/385d01fd-7e57-1f3f-1bae-30aa0c313d63@suse.com/","msgid":"<385d01fd-7e57-1f3f-1bae-30aa0c313d63@suse.com>","list_archive_url":null,"date":"2022-09-30T11:59:45","name":"[3/4] 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instructions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102646.3327818-12-richard.sandiford@arm.com/mbox/"}],"public":true,"mbox":"https://patchwork.plctlab.org/bundle/patchwork-bot/binutils-gdb_2023-03/mbox/"}]' + bundle_name_list='binutils-gdb_2022-10 binutils-gdb_2022-09 binutils-gdb_2022-11 binutils-gdb_2022-12 binutils-gdb_2023-01 binutils-gdb_2023-02 binutils-gdb_2023-03' + [[ binutils-gdb_2022-10 binutils-gdb_2022-09 binutils-gdb_2022-11 binutils-gdb_2022-12 binutils-gdb_2023-01 binutils-gdb_2023-02 binutils-gdb_2023-03 =~ 2023-03 ]] ++ jq -rc --arg bundle_name binutils-gdb_2023-03 '.[] | select(.name==$bundle_name) | (.id|tostring)' ++ echo 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RISC-V/gas: don'\''t open-code insn_length()","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/385d01fd-7e57-1f3f-1bae-30aa0c313d63@suse.com/mbox/"},{"id":1594,"url":"https://patchwork.plctlab.org/api/1.2/patches/1594/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f5757acf-7b90-a0e3-5eea-3b97cc226930@suse.com/","msgid":"","list_archive_url":null,"date":"2022-09-30T12:00:12","name":"[4/4] RISC-V/gas: allow generating up to 176-bit instructions with .insn","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f5757acf-7b90-a0e3-5eea-3b97cc226930@suse.com/mbox/"},{"id":1596,"url":"https://patchwork.plctlab.org/api/1.2/patches/1596/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930140503.38233-1-chigot@adacore.com/","msgid":"<20220930140503.38233-1-chigot@adacore.com>","list_archive_url":null,"date":"2022-09-30T14:05:03","name":"ld/testsuite: consistently add board_ldflags when linking with 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instructions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102646.3327818-12-richard.sandiford@arm.com/mbox/"}],"public":true,"mbox":"https://patchwork.plctlab.org/bundle/patchwork-bot/binutils-gdb_2023-03/mbox/"}]' + bundle_id=17 + git-pw bundle add 17 77087 +------------+-------------------------------------------------------------------------------------------+ | Property | Value | |------------+-------------------------------------------------------------------------------------------| | ID | 17 | | Name | binutils-gdb_2023-03 | | URL | https://patchwork.plctlab.org/bundle/patchwork-bot/binutils-gdb_2023-03/ | | Owner | patchwork-bot | | Project | binutils-gdb | | Public | True | | Patches | 62751 Memory leak in gas do_repeat | | | 62752 gas s_fill caused internal error in frag_new | | | 62753 Catch overflow in gas s_space | | | 62932 [v6,01/11] DIGEST: LICENSING | | | 62934 [v6,02/11] DIGEST: NEWS | | | 62935 [v6,03/11] DIGEST: Documentation | | | 62933 [v6,04/11] DIGEST: testsuite | | | 62937 [v6,05/11] DIGEST: ldlex.l | | | 62941 [v6,06/11] DIGEST: ldgram.y | | | 62939 [v6,07/11] DIGEST: ldmain.c | | | 62940 [v6,08/11] DIGEST: ldlang.*: add timestamp | | | 62944 [v6,09/11] DIGEST: calculation | | | 62936 [v6,10/11] DIGEST: Makefile.* | | | 62947 [v6,11/11] Build ldint | | | 62967 [v7,01/11] DIGEST: LICENSING | | | 62966 [v7,02/11] DIGEST: NEWS | | | 62971 [v7,03/11] DIGEST: Documentation | | | 62973 [v7,04/11] DIGEST: testsuite | | | 62972 [v7,05/11] DIGEST: ldlex.l | | | 62974 [v7,06/11] DIGEST: ldgram.y | | | 62968 [v7,07/11] DIGEST: ldmain.c | | | 62994 [v7,08/11] DIGEST: ldlang.*: add timestamp | | | 62997 [v7,09/11] DIGEST: calculation | | | 62995 [v7,10/11] DIGEST: Makefile.* | | | 62996 [v7,11/11] Build ldint | | | 62999 [v8,01/11] DIGEST: LICENSING | | | 63002 [v8,02/11] DIGEST: NEWS | | | 63000 [v8,03/11] DIGEST: Documentation | | | 63001 [v8,04/11] DIGEST: testsuite | | | 63005 [v8,05/11] DIGEST: ldlex.l | | | 63006 [v8,06/11] DIGEST: ldgram.y | | | 63007 [v8,07/11] DIGEST: ldmain.c | | | 63008 [v8,08/11] DIGEST: ldlang.*: add timestamp | | | 63010 [v8,09/11] DIGEST: calculation | | | 63011 [v8,10/11] DIGEST: Makefile.* | | | 63004 [v8,11/11] Build ldint | | | 63103 Using .mri in assembly | | | 63104 More bounds checking in macro_expand | | | 63167 [v2] MIPS: make mipsisa32 and mipsisa64 link more systematic | | | 63263 elfedit: add support for editing e_flags | | | 63267 [RESEND] elfedit: add support for editing e_flags | | | 63360 BPF relocations review / refactoring | | | 63387 Don't write zeros to a gap in the output file | | | 63554 [v2] ld: Allow R_X86_64_GOTPCREL for call *__tls_get_addr@GOTPCREL(%rip) | | | 63555 [v2] ld: Allow R_386_GOT32 for call *__tls_get_addr@GOT(%reg) | | | 63603 [v9,01/11,gdb/testsuite] Fix gdb.rust/watch.exp on ppc64le | | | 63598 [v9,02/11] Remove value_in | | | 63607 [v9,03/11,gdb/testsuite] Fix gdb.python/py-breakpoint.exp timeouts | | | 63602 [v9,04/11] gdb: add HtabPrinter to gdb-gdb.py.in | | | 63608 [v9,05/11] Automatic date update in version.in | | | 63609 [v9,06/11] Memory leak in gas do_repeat | | | 63599 [v9,07/11] gas s_fill caused internal error in frag_new | | | 63610 [v9,08/11] Catch overflow in gas s_space | | | 63606 [v9,09/11,gdb/testsuite] Add another xfail case in gdb.python/py-record-btrace.exp | | | 63605 [v9,10/11] Fix btrace regression | | | 63601 [v9,11/11] Fix typo with my email address | | | 63630 [v10,01/11] DIGEST: LICENSING | | | 63632 [v10,02/11] DIGEST: NEWS | | | 63635 [v10,03/11] DIGEST: Documentation | | | 63633 [v10,04/11] DIGEST: testsuite | | | 63631 [v10,05/11] DIGEST: ldlex.l | | | 63636 [v10,06/11] DIGEST: ldgram.y | | | 63634 [v10,07/11] DIGEST: ldmain.c | | | 63640 [v10,08/11] DIGEST: ldlang.*: add timestamp | | | 63642 [v10,09/11] DIGEST: calculation | | | 63641 [v10,10/11] DIGEST: Makefile.* | | | 63644 [v10,11/11] Build ldint | | | 63749 binutils coff type list | | | 63750 Tidy type handling in binutils/rdcoff.c | | | 63885 [01/18] x86: introduce .insn directive | | | 63887 [02/18] x86: parse VEX and alike specifiers for .insn | | | 63889 [03/18] x86: parse special opcode modifiers for .insn | | | 63892 [04/18] x86: use set_rex_vrex() also for short-form handling | | | 63893 [05/18] x86: move more disp processing out of md_assemble() | | | 63895 [06/18] x86-64: adjust REX-prefix part of SSE2AVX test | | | 63896 [07/18] x86: re-work build_modrm_byte()'s register assignment | | | 63897 [08/18] x86: VexVVVV is now merely a boolean | | | 63898 [09/18] x86: drop "shimm" special case template expansions | | | 63899 [10/18] x86/AT&T: restrict recognition of the "absolute branch" prefix character | | | 63900 [11/18] x86: process instruction operands for .insn | | | 63902 [12/18] x86: decouple broadcast type and bytes fields | | | 63903 [13/18] x86: handle EVEX Disp8 for .insn | | | 63904 [14/18] x86: allow for multiple immediates in output_disp() | | | 63905 [15/18] x86: handle immediate operands for .insn | | | 63906 [16/18] x86: document .insn | | | 63907 [17/18] x86: convert testcases to use .insn | | | 63908 [RFC,18/18] x86: .insn example - VEX-encoded instructions of original Xeon Phi | | | 63958 [v11,01/11] DIGEST: LICENSING | | | 63953 [v11,02/11] DIGEST: NEWS | | | 63954 [v11,03/11] DIGEST: Documentation | | | 63966 [v11,04/11] DIGEST: testsuite | | | 63962 [v11,05/11] DIGEST: ldlex.l | | | 63960 [v11,06/11] DIGEST: ldgram.y | | | 63964 [v11,07/11] DIGEST: ldmain.c | | | 63961 [v11,08/11] DIGEST: ldlang.*: add timestamp | | | 63955 [v11,09/11] DIGEST: calculation | | | 63967 [v11,10/11] DIGEST: Makefile.* | | | 63965 [v11,11/11] Build ldint | | | 64411 Correct objdump command line error handling | | | 64412 Move nm.c cached line number info to bfd usrdata | | | 64413 Downgrade nm fatal errors to non-fatal | | | 64414 Downgrade addr2line fatal errors to non-fatal | | | 64415 Downgrade objdump fatal errors to non-fatal | | | 64416 Correct odd loop in ecoff lookup_line | | | 64418 More _bfd_ecoff_locate_line sanity checks | | | 64417 PR30198, Assertion and segfault when linking x86_64 elf and coff | | | 64619 macho null dereference read | | | 64651 [v12,01/11] DIGEST: LICENSING | | | 64652 [v12,02/11] DIGEST: NEWS | | | 64653 [v12,03/11] DIGEST: Documentation | | | 64657 [v12,04/11] DIGEST: testsuite | | | 64654 [v12,05/11] DIGEST: ldlex.l | | | 64655 [v12,06/11] DIGEST: ldgram.y | | | 64656 [v12,07/11] DIGEST: ldmain.c | | | 64658 [v12,08/11] DIGEST: ldlang.*: add timestamp | | | 64661 [v12,09/11] DIGEST: calculation | | | 64660 [v12,10/11] DIGEST: Makefile.* | | | 64659 [v12,11/11] Build ldint | | | 65273 [Review,is,needed] gprofng: read Dwarf 5 | | | 65986 z8 and z80 coff_reloc16_extra_cases sanity checks | | | 65987 Regen potfiles | | | 66046 Tidy pe_ILF_build_a_bfd a little | | | 66183 [v1] DIGEST: Disable 64-bit CRC for 32-bit BFD | | | 66328 [1/4] gas: drop function pointer parameter from macro_init() | | | 66329 [2/4] gas: isolate macro_strip_at to macro.c | | | 66332 [3/4] gas: use flag_mri directly in macro processing | | | 66336 [4/4] gas: expose flag_macro_alternate globally | | | 66649 RISC-V: Segment fault in riscv_elf_append_rela. | | | 66827 Allow frag address wrapping in absolute section | | | 66828 objdump: report no section contents | | | 67175 [v1,1/7] SECTOR: NEWS | | | 67174 [v1,2/7] SECTOR: ld.texi | | | 67177 [v1,3/7] SECTOR: ldlex.l | | | 67179 [v1,4/7] SECTOR: ldgram.y | | | 67180 [v1,5/7] SECTOR: language additions | | | 67176 [v1,6/7] SECTOR: add testsuite | | | 67178 [v1,7/7] SECTOR: Makefile.* | | | 67202 eh static data | | | 67293 [v2,1/7] RISC-V: minor effort reduction in relocation specifier parsing | | | 67294 [v2,2/7] RISC-V: drop "percent_op" parameter from my_getOpcodeExpression() | | | 67296 [v2,3/7] RISC-V: avoid redundant and misleading/wrong error messages | | | 67297 [v2,4/7] RISC-V: don't recognize bogus relocations | | | 67302 [v2,5/7] RISC-V: relax post-relocation-operator separator expectation | | | 67301 [v2,6/7] RISC-V: test for expected / no unexpected symbols | | | 67305 [v2,7/7] RISC-V: adjust logic to avoid register name symbols | | | 67308 [RFC] RISC-V: alter the special character used in FAKE_LABEL_NAME | | | 67313 gas: apply md_register_arithmetic also to unary '+' | | | 67317 x86: drop identifier_chars[] | | | 67319 [v2,01/14] x86: introduce .insn directive | | | 67320 [v2,02/14] x86: parse VEX and alike specifiers for .insn | | | 67321 [v2,03/14] x86: parse special opcode modifiers for .insn | | | 67322 [v2,04/14] x86: re-work build_modrm_byte()'s register assignment | | | 67325 [v2,05/14] x86: VexVVVV is now merely a boolean | | | 67323 [v2,06/14] x86: drop "shimm" special case template expansions | | | 67326 [v2,07/14] x86/AT&T: restrict recognition of the "absolute branch" prefix character | | | 67327 [v2,08/14] x86: process instruction operands for .insn | | | 67328 [v2,09/14] x86: handle EVEX Disp8 for .insn | | | 67329 [v2,10/14] x86: allow for multiple immediates in output_disp() | | | 67330 [v2,11/14] x86: handle immediate operands for .insn | | | 67331 [v2,12/14] x86: document .insn | | | 67332 [v2,13/14] x86: convert testcases to use .insn | | | 67333 [RFC,v2,14/14] x86: .insn example - VEX-encoded instructions of original Xeon Phi | | | 68729 Fix emit-relocs for aarch64 gold | | | 69242 gas/compress-debug.c init all of strm | | | 69243 gas/ecoff.c: don't use zero struct copies to init | | | 69245 gas/dwarf2dbg.c init more statics | | | 69244 gas .include and .incbin | | | 69246 gas/read.c: init more statics | | | 69247 Sanity check read_section_stabs_debugging_info | | | 69248 objdump segfault after symbol table error | | | 69845 [v1,1/3] CHIP: ldlex.l | | | 69843 [v1,2/3] CHIP: ldgram.y | | | 69844 [v1,3/3] CHIP: language additions | | | 70532 PR30217, dynamic relocations using local dynamic symbols | | | 70595 cpu/mem.opc whitespace tidy | | | 70703 [1/5] configure: add new target aarch64-*-nto* | | | 70705 [2/5] readelf: add support for QNT_STACK note subsections | | | 70706 [3/5] ld: add support of QNX stack arguments for aarch64nto | | | 70704 [4/5] ld/testsuite: add aarch64nto to ld-aarch64 | | | 70707 [5/5] ld/testsuite: disable ilp32 tests for aarch64-qnx | | | 70782 Re: Add --enable-linker-version option | | | 71031 RISC-V: Adjust the 'print_insn' return value of disassembling. | | | 71117 Add support to readelf for the PT_OPENBSD_MUTABLE segment type. | | | 71230 strange segfault i386-dis.c:9815:28 | | | 71234 Another source_sh | | | 71237 mach-o: out of memory in get_dynamic_reloc_upper_bound | | | 71244 RISC-V: Clarify link behaviors of R_RISCV_32/64 relocations with ABS symbol. | | | 71345 [1/2] Reloc howto access broken for BPF | | | 71346 [2/2] Changed ld and gas BPF tests | | | 71521 [Review,is,neded] gprofng: Use prototype to call libc functions | | | 71749 ctf segfaults | | | 71751 Another sanity check for read_section_stabs_debugging_info | | | 71752 rewrite_elf_program_header and want_p_paddr_set_to_zero | | | 71753 XCOFF archive sanity check | | | 71754 Regen ld/po/BLD-POTFILES.in | | | 71942 [v2] RISC-V: Fix disassemble fetch fail return value. | | | 72083 libctf: unused variable | | | 72295 x86: Check unbalanced braces in memory reference | | | 72904 [1/3] bfd: aarch64: Refactor stub sizing code | | | 72903 [2/3] bfd: aarch64: Fix stubs that may break BTI PR30076 | | | 72905 [3/3] bfd: aarch64: Optimize BTI stubs PR30076 | | | 73096 gas: expand_irp memory leaks | | | 73098 XCOFF: use bfd_coff_close_and_cleanup | | | 73100 PE fake section for C_SECTION syms | | | 73101 PR17910 sym string offset check | | | 73102 Sanity check coff-sh and coff-mcore sym string offset | | | 73105 Remove unnecessary memsets in sframe-dump.c | | | 73115 coff_get_normalized_symtab bfd_release | | | 73996 MIPS: fix loongson3 llsc workaround | | | 74094 Arm64/ELF: accept relocations against STN_UNDEF | | | 74480 Tidy dwarf1 cached section contents | | | 74481 Tidy string_ptr increment | | | 74544 [1/4] libctf: fix assertion failure with no system qsort_r | | | 74545 [2/4] libctf: work around an uninitialized variable warning | | | 74547 [3/4] libctf: fix a comment typo | | | 74546 [4/4] libctf: get the offsets of fields of unnamed structs/unions right | | | 74560 [Bug,gold/30187] ld.bfd and ld.gold versions in .comment section of ELF files | | | 74795 [1/3] RISC-V: Extract the ld code which are too complicated, and may be reused. | | | 74798 [2/3] RISC-V: Clarify link behaviors of R_RISCV_32/64 relocations with ABS symbol. | | | 74796 [3/3] RISC-V: PR28789, Reject R_RISCV_PCREL relocations with ABS symbol in PIC/PIE. | | | 75166 [Review,is,neded] gprofng: 30089 [display text] Invalid number of threads | | | 75242 [RFC,v2,1/2] RISC-V: Allocate "various" operand type | | | 75245 [RFC,v2,2/2] RISC-V: Add support for the Zfa extension | | | 75347 XCOFF sanity check | | | 75348 Duplicate DW_AT_call_file leak | | | 75350 coffgrok access of u.auxent.x_sym.x_tagndx.p | | | 75351 Set proper union selector tag | | | 75353 Use stdint types in coff internal_auxent | | | 75354 Remove coff_pointerize_aux table_end param | | | 75355 Tidy tc-ppc.c XCOFF auxent access | | | 75768 ubsan: elfnn-aarch64.c:4595:19: runtime error: load of value 190 | | | 75974 Avoid undefined behaviour in m68hc11 md_begin | | | 76299 [1/3] Add Allegrex CPU as a MIPS2-based CPU | | | 76298 [2/3] Add rotation instructions to allegrex CPU | | | 76300 [3/3] Adding more instructions to Allegrex CPU | | | 76303 ld testsuite CFLAGS_FOR_TARGET | | | 76347 Sanity check section size in bfd_init_section_compress_status | | | 76561 RFC: Add ELF note for description with JSON data | | | 76636 RFC: Can static executables contain relocations against symbols ? | | | 76860 [COMMITTED] Fix typo in ld manual --enable-non-contiguous-regions example | | | 76881 Tidy memory on addr2line failures | | | 76882 Tidy leaked objcopy memory | | | 76887 Fix memory leak in bfd_get_debug_link_info_1 | | | 77007 aarch64: Add sme-i16i64 and sme-f64f64 aliases | | | 77019 [01/43] aarch64: Fix PSEL opcode mask | | | 77024 [02/43] aarch64: Restrict range of PRFM opcodes | | | 77016 [03/43] aarch64: Fix SVE2 register/immediate distinction | | | 77017 [04/43] aarch64: Make SME instructions use F_STRICT | | | 77031 [05/43] aarch64: Use aarch64_operand_error more widely | | | 77021 [06/43] aarch64: Rename REG_TYPE_ZA* to REG_TYPE_ZAT* | | | 77018 [07/43] aarch64: Add REG_TYPE_ZATHV | | | 77020 [08/43] aarch64: Move vectype_to_qualifier further up | | | 77022 [09/43] aarch64: Rework parse_typed_reg interface | | | 77027 [10/43] aarch64: Reuse parse_typed_reg for ZA tiles | | | 77037 [11/43] aarch64: Consolidate ZA tile range checks | | | 77034 [12/43] aarch64: Treat ZA as a register | | | 77029 [13/43] aarch64: Rename za_tile_vector to za_index | | | 77043 [14/43] aarch64: Make indexed_za use 64-bit immediates | | | 77041 [15/43] aarch64: Pass aarch64_indexed_za to parsers | | | 77045 [16/43] aarch64: Move ZA range checks to aarch64-opc.c | | | 77048 [17/43] aarch64: Consolidate ZA slice parsing | | | 77046 [18/43] aarch64: Commonise index parsing | | | 77053 [19/43] aarch64: Move w12-w15 range check to libopcodes | | | 77032 [20/43] aarch64: Tweak error for missing immediate offset | | | 77058 [21/43] aarch64: Tweak errors for base & offset registers | | | 77056 [22/43] aarch64: Tweak parsing of integer & FP registers | | | 77052 [23/43] aarch64: Improve errors for malformed register lists | | | 77064 [24/43] aarch64: Try to avoid inappropriate default errors | | | 77070 [25/43] aarch64: Rework reporting of failed register checks | | | 77050 [26/43] aarch64: Update operand_mismatch_kind_names | | | 77054 [27/43] aarch64: Deprioritise AARCH64_OPDE_REG_LIST | | | 77042 [28/43] aarch64: Add an error code for out-of-range registers | | | 77060 [29/43] aarch64: Commonise checks for index operands | | | 77066 [30/43] aarch64: Add an operand class for SVE register lists | | | 77067 [31/43] aarch64: Make AARCH64_OPDE_REG_LIST take a bitfield | | | 77047 [32/43] aarch64: Tweak register list errors | | | 77072 [33/43] aarch64: Try to report invalid variants against the closest match | | | 77051 [34/43] aarch64: Tweak priorities of parsing-related errors | | | 77079 [35/43] aarch64: Rename aarch64-tbl.h OP_SME_* macros | | | 77055 [36/43] aarch64: Reorder some OP_SVE_* macros | | | 77082 [37/43] aarch64: Add a aarch64_cpu_supports_inst_p helper | | | 77068 [38/43] aarch64: Rename some of GAS's REG_TYPE_* macros | | | 77073 [39/43] aarch64: Regularise FLD_* suffixes | | | 77084 [40/43] aarch64: Resync field names | | | 77077 [41/43] aarch64: Sort fields alphanumerically | | | 77063 [42/43] aarch64: Add support for strided register lists | | | 77078 [43/43] aarch64: Prefer register ranges & support wrapping | | | 77086 [01/31] aarch64: Add +sme2 | | | 77076 [03/31] aarch64: Add _off4 suffix to AARCH64_OPND_SME_ZA_array | | | 77083 [04/31] aarch64: Add support for vgx2 and vgx4 | | | 77081 [05/31] aarch64; Add support for vector offset ranges | | | 77085 [07/31] aarch64: Add the SME2 MOVA instructions | | | 77071 [10/31] aarch64: Add the SME2 ZT0 instructions | | | 77080 [11/31] aarch64: Add the SME2 ADD and SUB instructions | | | 77087 [13/31] aarch64: Add the SME2 FMLA and FMLS instructions | +------------+-------------------------------------------------------------------------------------------+ + git config pull.rebase false + git fetch origin master From github.com:plctlab/patchwork-binutils-gdb * branch master -> FETCH_HEAD + git checkout master Switched to a new branch 'master' branch 'master' set up to track 'origin/master'. + git pull origin master From github.com:plctlab/patchwork-binutils-gdb * branch master -> FETCH_HEAD Already up to date. + git fetch origin upstream-master From github.com:plctlab/patchwork-binutils-gdb * branch upstream-master -> FETCH_HEAD + git checkout upstream-master Switched to a new branch 'upstream-master' branch 'upstream-master' set up to track 'origin/upstream-master'. + git remote add upstream https://sourceware.org/git/binutils-gdb.git + git pull upstream master From https://sourceware.org/git/binutils-gdb * branch master -> FETCH_HEAD * [new branch] master -> upstream/master Already up to date. + git push -u origin upstream-master Everything up-to-date branch 'upstream-master' set up to track 'origin/upstream-master'. + git checkout master Switched to branch 'master' Your branch is up to date with 'origin/master'. + git merge upstream-master fatal: refusing to merge unrelated histories + git push -u origin master Everything up-to-date branch 'master' set up to track 'origin/master'. + branchname=series31215-patch77087 ++ git branch -a ++ grep 'series31215-patch77087$' + checkbranch= + checkbranchresult=null + '[' null = series31215-patch77087 ']' + git checkout -b series31215-patch77087 Switched to a new branch 'series31215-patch77087' ++ curl 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aarch64: Add +sme2","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102646.3327818-2-richard.sandiford@arm.com/mbox/"},{"id":77090,"url":"https://patchwork.plctlab.org/api/1.2/patches/77090/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102646.3327818-3-richard.sandiford@arm.com/","msgid":"<20230330102646.3327818-3-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:26:17","name":"[02/31] aarch64: Add a _10 suffix to FLD_imm3","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102646.3327818-3-richard.sandiford@arm.com/mbox/"},{"id":77076,"url":"https://patchwork.plctlab.org/api/1.2/patches/77076/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102646.3327818-4-richard.sandiford@arm.com/","msgid":"<20230330102646.3327818-4-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:26:18","name":"[03/31] aarch64: Add _off4 suffix to AARCH64_OPND_SME_ZA_array","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102646.3327818-4-richard.sandiford@arm.com/mbox/"},{"id":77083,"url":"https://patchwork.plctlab.org/api/1.2/patches/77083/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102646.3327818-5-richard.sandiford@arm.com/","msgid":"<20230330102646.3327818-5-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:26:19","name":"[04/31] aarch64: Add support for vgx2 and vgx4","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102646.3327818-5-richard.sandiford@arm.com/mbox/"},{"id":77081,"url":"https://patchwork.plctlab.org/api/1.2/patches/77081/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102646.3327818-6-richard.sandiford@arm.com/","msgid":"<20230330102646.3327818-6-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:26:20","name":"[05/31] aarch64; Add support for vector offset ranges","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102646.3327818-6-richard.sandiford@arm.com/mbox/"},{"id":77085,"url":"https://patchwork.plctlab.org/api/1.2/patches/77085/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102646.3327818-8-richard.sandiford@arm.com/","msgid":"<20230330102646.3327818-8-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:26:22","name":"[07/31] aarch64: Add the SME2 MOVA instructions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102646.3327818-8-richard.sandiford@arm.com/mbox/"},{"id":77071,"url":"https://patchwork.plctlab.org/api/1.2/patches/77071/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102646.3327818-11-richard.sandiford@arm.com/","msgid":"<20230330102646.3327818-11-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:26:25","name":"[10/31] aarch64: Add the SME2 ZT0 instructions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102646.3327818-11-richard.sandiford@arm.com/mbox/"},{"id":77080,"url":"https://patchwork.plctlab.org/api/1.2/patches/77080/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102646.3327818-12-richard.sandiford@arm.com/","msgid":"<20230330102646.3327818-12-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:26:26","name":"[11/31] aarch64: Add the SME2 ADD and SUB instructions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102646.3327818-12-richard.sandiford@arm.com/mbox/"},{"id":77087,"url":"https://patchwork.plctlab.org/api/1.2/patches/77087/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102646.3327818-14-richard.sandiford@arm.com/","msgid":"<20230330102646.3327818-14-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:26:28","name":"[13/31] aarch64: Add the SME2 FMLA and FMLS instructions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102646.3327818-14-richard.sandiford@arm.com/mbox/"},{"id":77093,"url":"https://patchwork.plctlab.org/api/1.2/patches/77093/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102646.3327818-23-richard.sandiford@arm.com/","msgid":"<20230330102646.3327818-23-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:26:37","name":"[22/31] aarch64: Add the SME2 saturating conversion instructions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102646.3327818-23-richard.sandiford@arm.com/mbox/"},{"id":77091,"url":"https://patchwork.plctlab.org/api/1.2/patches/77091/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102646.3327818-24-richard.sandiford@arm.com/","msgid":"<20230330102646.3327818-24-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:26:38","name":"[23/31] aarch64: Add the SME2 shift instructions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102646.3327818-24-richard.sandiford@arm.com/mbox/"},{"id":77095,"url":"https://patchwork.plctlab.org/api/1.2/patches/77095/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102646.3327818-25-richard.sandiford@arm.com/","msgid":"<20230330102646.3327818-25-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:26:39","name":"[24/31] aarch64: Add the SME2 UNPK instructions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102646.3327818-25-richard.sandiford@arm.com/mbox/"},{"id":77092,"url":"https://patchwork.plctlab.org/api/1.2/patches/77092/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102646.3327818-26-richard.sandiford@arm.com/","msgid":"<20230330102646.3327818-26-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:26:40","name":"[25/31] aarch64: Add the SME2 UZP and ZIP instructions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102646.3327818-26-richard.sandiford@arm.com/mbox/"}]}' ++ jq '.patches[] | (.id|tostring) + "," + .mbox' ++ echo '{"id":31215,"url":"https://patchwork.plctlab.org/api/1.2/series/31215/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/list/?series=31215","project":{"id":2,"url":"https://patchwork.plctlab.org/api/1.2/projects/2/","name":"binutils-gdb","link_name":"binutils-gdb","list_id":"binutils.sourceware.org","list_email":"binutils@sourceware.org","web_url":"https://github.com/wangliu-iscas/Patchwork-Bundles/blob/main/binutils-gdb.md","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"name":"aarch64: Add SME2 support","date":"2023-03-30T10:26:25","submitter":{"id":45,"url":"https://patchwork.plctlab.org/api/1.2/people/45/","name":"Richard Sandiford","email":"richard.sandiford@arm.com"},"version":1,"total":31,"received_total":13,"received_all":false,"mbox":"https://patchwork.plctlab.org/series/31215/mbox/","cover_letter":{"id":7460,"url":"https://patchwork.plctlab.org/api/1.2/covers/7460/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/cover/20230330102646.3327818-1-richard.sandiford@arm.com/","msgid":"<20230330102646.3327818-1-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:26:15","name":"[00/31] aarch64: Add SME2 support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/cover/20230330102646.3327818-1-richard.sandiford@arm.com/mbox/"},"patches":[{"id":77086,"url":"https://patchwork.plctlab.org/api/1.2/patches/77086/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102646.3327818-2-richard.sandiford@arm.com/","msgid":"<20230330102646.3327818-2-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:26:16","name":"[01/31] aarch64: Add +sme2","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102646.3327818-2-richard.sandiford@arm.com/mbox/"},{"id":77090,"url":"https://patchwork.plctlab.org/api/1.2/patches/77090/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102646.3327818-3-richard.sandiford@arm.com/","msgid":"<20230330102646.3327818-3-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:26:17","name":"[02/31] aarch64: Add a _10 suffix to FLD_imm3","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102646.3327818-3-richard.sandiford@arm.com/mbox/"},{"id":77076,"url":"https://patchwork.plctlab.org/api/1.2/patches/77076/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102646.3327818-4-richard.sandiford@arm.com/","msgid":"<20230330102646.3327818-4-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:26:18","name":"[03/31] aarch64: Add _off4 suffix to AARCH64_OPND_SME_ZA_array","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102646.3327818-4-richard.sandiford@arm.com/mbox/"},{"id":77083,"url":"https://patchwork.plctlab.org/api/1.2/patches/77083/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102646.3327818-5-richard.sandiford@arm.com/","msgid":"<20230330102646.3327818-5-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:26:19","name":"[04/31] aarch64: Add support for vgx2 and vgx4","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102646.3327818-5-richard.sandiford@arm.com/mbox/"},{"id":77081,"url":"https://patchwork.plctlab.org/api/1.2/patches/77081/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102646.3327818-6-richard.sandiford@arm.com/","msgid":"<20230330102646.3327818-6-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:26:20","name":"[05/31] aarch64; Add support for vector offset ranges","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102646.3327818-6-richard.sandiford@arm.com/mbox/"},{"id":77085,"url":"https://patchwork.plctlab.org/api/1.2/patches/77085/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102646.3327818-8-richard.sandiford@arm.com/","msgid":"<20230330102646.3327818-8-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:26:22","name":"[07/31] aarch64: Add the SME2 MOVA instructions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102646.3327818-8-richard.sandiford@arm.com/mbox/"},{"id":77071,"url":"https://patchwork.plctlab.org/api/1.2/patches/77071/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102646.3327818-11-richard.sandiford@arm.com/","msgid":"<20230330102646.3327818-11-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:26:25","name":"[10/31] aarch64: Add the SME2 ZT0 instructions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102646.3327818-11-richard.sandiford@arm.com/mbox/"},{"id":77080,"url":"https://patchwork.plctlab.org/api/1.2/patches/77080/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102646.3327818-12-richard.sandiford@arm.com/","msgid":"<20230330102646.3327818-12-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:26:26","name":"[11/31] aarch64: Add the SME2 ADD and SUB instructions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102646.3327818-12-richard.sandiford@arm.com/mbox/"},{"id":77087,"url":"https://patchwork.plctlab.org/api/1.2/patches/77087/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102646.3327818-14-richard.sandiford@arm.com/","msgid":"<20230330102646.3327818-14-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:26:28","name":"[13/31] aarch64: Add the SME2 FMLA and FMLS instructions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102646.3327818-14-richard.sandiford@arm.com/mbox/"},{"id":77093,"url":"https://patchwork.plctlab.org/api/1.2/patches/77093/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102646.3327818-23-richard.sandiford@arm.com/","msgid":"<20230330102646.3327818-23-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:26:37","name":"[22/31] aarch64: Add the SME2 saturating conversion instructions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102646.3327818-23-richard.sandiford@arm.com/mbox/"},{"id":77091,"url":"https://patchwork.plctlab.org/api/1.2/patches/77091/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102646.3327818-24-richard.sandiford@arm.com/","msgid":"<20230330102646.3327818-24-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:26:38","name":"[23/31] aarch64: Add the SME2 shift instructions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102646.3327818-24-richard.sandiford@arm.com/mbox/"},{"id":77095,"url":"https://patchwork.plctlab.org/api/1.2/patches/77095/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102646.3327818-25-richard.sandiford@arm.com/","msgid":"<20230330102646.3327818-25-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:26:39","name":"[24/31] aarch64: Add the SME2 UNPK instructions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102646.3327818-25-richard.sandiford@arm.com/mbox/"},{"id":77092,"url":"https://patchwork.plctlab.org/api/1.2/patches/77092/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102646.3327818-26-richard.sandiford@arm.com/","msgid":"<20230330102646.3327818-26-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:26:40","name":"[25/31] aarch64: Add the SME2 UZP and ZIP instructions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102646.3327818-26-richard.sandiford@arm.com/mbox/"}]}' + patchid_patchurl='"77086,https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102646.3327818-2-richard.sandiford@arm.com/mbox/" "77090,https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102646.3327818-3-richard.sandiford@arm.com/mbox/" "77076,https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102646.3327818-4-richard.sandiford@arm.com/mbox/" "77083,https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102646.3327818-5-richard.sandiford@arm.com/mbox/" "77081,https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102646.3327818-6-richard.sandiford@arm.com/mbox/" "77085,https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102646.3327818-8-richard.sandiford@arm.com/mbox/" "77071,https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102646.3327818-11-richard.sandiford@arm.com/mbox/" "77080,https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102646.3327818-12-richard.sandiford@arm.com/mbox/" "77087,https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102646.3327818-14-richard.sandiford@arm.com/mbox/" "77093,https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102646.3327818-23-richard.sandiford@arm.com/mbox/" "77091,https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102646.3327818-24-richard.sandiford@arm.com/mbox/" "77095,https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102646.3327818-25-richard.sandiford@arm.com/mbox/" "77092,https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102646.3327818-26-richard.sandiford@arm.com/mbox/"' + IFS=, + read -r series_patch_id series_patch_url + echo '"77086,https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102646.3327818-2-richard.sandiford@arm.com/mbox/" "77090,https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102646.3327818-3-richard.sandiford@arm.com/mbox/" "77076,https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102646.3327818-4-richard.sandiford@arm.com/mbox/" "77083,https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102646.3327818-5-richard.sandiford@arm.com/mbox/" "77081,https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102646.3327818-6-richard.sandiford@arm.com/mbox/" "77085,https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102646.3327818-8-richard.sandiford@arm.com/mbox/" "77071,https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102646.3327818-11-richard.sandiford@arm.com/mbox/" "77080,https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102646.3327818-12-richard.sandiford@arm.com/mbox/" "77087,https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102646.3327818-14-richard.sandiford@arm.com/mbox/" "77093,https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102646.3327818-23-richard.sandiford@arm.com/mbox/" "77091,https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102646.3327818-24-richard.sandiford@arm.com/mbox/" "77095,https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102646.3327818-25-richard.sandiford@arm.com/mbox/" "77092,https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102646.3327818-26-richard.sandiford@arm.com/mbox/"' ++ echo '"77086' ++ sed 's/"//g' + series_patch_id=77086 ++ echo 'https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102646.3327818-2-richard.sandiford@arm.com/mbox/"' ++ sed 's/"//g' + series_patch_url=https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102646.3327818-2-richard.sandiford@arm.com/mbox/ ++ git rev-parse HEAD + commitid_before=324998b47364528f407666512015370c12ab83a1 + eval '+++ declare -p bout bret declare -- bout="Applying: aarch64: Add +sme2 error: sha1 information is lacking or useless (gas/config/tc-aarch64.c). error: could not build fake ancestor hint: Use '\''git am --show-current-patch=diff'\'' to see the failed patch Patch failed at 0001 aarch64: Add +sme2 When you have resolved this problem, run \"git am --continue\". If you prefer to skip this patch, run \"git am --skip\" instead. To restore the original branch and stop patching, run \"git am --abort\"." declare -- bret="128" ++ berr='\''++++ git_am https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102646.3327818-2-richard.sandiford@arm.com/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102646.3327818-2-richard.sandiford@arm.com/mbox/ ++++ curl https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102646.3327818-2-richard.sandiford@arm.com/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 9133 100 9133 0 0 146k 0 --:--:-- --:--:-- --:--:-- 146k +++ bout='\''\'\'''\''Applying: aarch64: Add +sme2 error: sha1 information is lacking or useless (gas/config/tc-aarch64.c). error: could not build fake ancestor hint: Use '\''\'\'''\''\'\''\'\'''\'''\''\'\'''\''git am --show-current-patch=diff'\''\'\'''\''\'\''\'\'''\'''\''\'\'''\'' to see the failed patch Patch failed at 0001 aarch64: Add +sme2 When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort".'\''\'\'''\'' +++ bret=128'\'' ++ declare -p berr declare -- berr="++++ git_am https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102646.3327818-2-richard.sandiford@arm.com/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102646.3327818-2-richard.sandiford@arm.com/mbox/ ++++ curl https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102646.3327818-2-richard.sandiford@arm.com/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 9133 100 9133 0 0 146k 0 --:--:-- --:--:-- --:--:-- 146k +++ bout='\''Applying: aarch64: Add +sme2 error: sha1 information is lacking or useless (gas/config/tc-aarch64.c). error: could not build fake ancestor hint: Use '\''\\'\'''\''git am --show-current-patch=diff'\''\\'\'''\'' to see the failed patch Patch failed at 0001 aarch64: Add +sme2 When you have resolved this problem, run \"git am --continue\". If you prefer to skip this patch, run \"git am --skip\" instead. To restore the original branch and stop patching, run \"git am --abort\".'\'' +++ bret=128"' ++ +++ declare -p bout bret /tmp/jenkins9391484015519060633.sh: line 124: +++: command not found ++ declare -- 'bout=Applying: aarch64: Add +sme2 error: sha1 information is lacking or useless (gas/config/tc-aarch64.c). error: could not build fake ancestor hint: Use '\''git am --show-current-patch=diff'\'' to see the failed patch Patch failed at 0001 aarch64: Add +sme2 When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort".' ++ declare -- bret=128 ++ ++ 'berr=++++ git_am https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102646.3327818-2-richard.sandiford@arm.com/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102646.3327818-2-richard.sandiford@arm.com/mbox/ ++++ curl https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102646.3327818-2-richard.sandiford@arm.com/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 9133 100 9133 0 0 146k 0 --:--:-- --:--:-- --:--:-- 146k +++ bout='\''Applying: aarch64: Add +sme2 error: sha1 information is lacking or useless (gas/config/tc-aarch64.c). error: could not build fake ancestor hint: Use '\''\'\'''\''git am --show-current-patch=diff'\''\'\'''\'' to see the failed patch Patch failed at 0001 aarch64: Add +sme2 When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort".'\'' +++ bret=128' /tmp/jenkins9391484015519060633.sh: line 149: ++: command not found ++ ++ declare -p berr /tmp/jenkins9391484015519060633.sh: line 150: ++: command not found ++ declare -- 'berr=++++ git_am https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102646.3327818-2-richard.sandiford@arm.com/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102646.3327818-2-richard.sandiford@arm.com/mbox/ ++++ curl https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102646.3327818-2-richard.sandiford@arm.com/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 9133 100 9133 0 0 146k 0 --:--:-- --:--:-- --:--:-- 146k +++ bout='\''Applying: aarch64: Add +sme2 error: sha1 information is lacking or useless (gas/config/tc-aarch64.c). error: could not build fake ancestor hint: Use '\''\'\'''\''git am --show-current-patch=diff'\''\'\'''\'' to see the failed patch Patch failed at 0001 aarch64: Add +sme2 When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort".'\'' +++ bret=128' ++ git rev-parse HEAD + commitid_after=324998b47364528f407666512015370c12ab83a1 + '[' 128 = 0 ']' + [[ ++++ git_am https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102646.3327818-2-richard.sandiford@arm.com/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102646.3327818-2-richard.sandiford@arm.com/mbox/ ++++ curl https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102646.3327818-2-richard.sandiford@arm.com/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 9133 100 9133 0 0 146k 0 --:--:-- --:--:-- --:--:-- 146k +++ bout='Applying: aarch64: Add +sme2 error: sha1 information is lacking or useless (gas/config/tc-aarch64.c). error: could not build fake ancestor hint: Use '\''git am --show-current-patch=diff'\'' to see the failed patch Patch failed at 0001 aarch64: Add +sme2 When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort".' +++ bret=128 =~ sha1 information is lacking or useless ]] + submit_check warning Unresolved https://patchwork.plctlab.org/jenkins/job/binutils-gdb/1423/consoleText 'Git am fail log' + check_state=warning + patch_state=Unresolved + repo_url=https://patchwork.plctlab.org/jenkins/job/binutils-gdb/1423/consoleText + DESCRIPTION='Git am fail log' + curl -X POST -H 'Authorization: Token [*******]' -F state=warning -F target_url=https://patchwork.plctlab.org/jenkins/job/binutils-gdb/1423/consoleText -F context=binutils-gdb-check -F 'description=Git am fail log' https://patchwork.plctlab.org/api/patches/77087/checks/ % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 977 100 431 100 546 11051 14000 --:--:-- --:--:-- --:--:-- 25051 {"id":6742,"url":"https://patchwork.plctlab.org/api/patches/77087/checks/6742/","user":{"id":1,"url":"https://patchwork.plctlab.org/api/users/1/","username":"snail","first_name":"","last_name":"","email":"wangliu@iscas.ac.cn"},"date":"2023-03-30T11:52:59.652316","state":"warning","target_url":"https://patchwork.plctlab.org/jenkins/job/binutils-gdb/1423/consoleText","context":"binutils-gdb-check","description":"Git am fail log"}+ curl -X PATCH -H 'Authorization: Token [*******]' -F state=Unresolved https://patchwork.plctlab.org/api/1.2/patches/77087/ % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0{"id":77087,"url":"https://patchwork.plctlab.org/api/1.2/patches/77087/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102646.3327818-14-richard.sandiford@arm.com/","project":{"id":2,"url":"https://patchwork.plctlab.org/api/1.2/projects/2/","name":"binutils-gdb","link_name":"binutils-gdb","list_id":"binutils.sourceware.org","list_email":"binutils@sourceware.org","web_url":"https://github.com/wangliu-iscas/Patchwork-Bundles/blob/main/binutils-gdb.md","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20230330102646.3327818-14-richard.sandiford@arm.com>","list_archive_url":null,"date":"2023-03-30T10:26:28","name":"[13/31] aarch64: Add the SME2 FMLA and FMLS instructions","commit_ref":null,"pull_url":null,"state":"unresolved","archived":false,"hash":"0ded4a0a6cf33681dd6c72f9b9bb61d33559571e","submitter":{"id":45,"url":"https://patchwork.plctlab.org/api/1.2/people/45/","name":"Richard Sandiford","email":"richard.sandiford@arm.com"},"delegate":null,"mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20230330102646.3327818-14-richard.sandiford@arm.com/mbox/","series":[{"id":31215,"url":"https://patchwork.plctlab.org/api/1.2/series/31215/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/list/?series=31215","date":"2023-03-30T10:26:25","name":"aarch64: Add SME2 support","version":1,"mbox":"https://patchwork.plctlab.org/series/31215/mbox/"}],"comments":"https://patchwork.plctlab.org/api/patches/77087/comments/","check":"warning","checks":"https://patchwork.plctlab.org/api/patches/77087/checks/","tags":{},"headers":{"Return-Path":"","Delivered-To":["ouuuleilei@gmail.com","binutils@sourceware.org"],"Received":["by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp1037760vqo;\n Thu, 30 Mar 2023 04:01:29 -0700 (PDT)","from sourceware.org (server2.sourceware.org.\n [2620:52:3:1:0:246e:9693:128c])\n by mx.google.com with ESMTPS id\n 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Oit6TA4jC0GCNZkQ5HzNwDbYfcanb21j5HXbxuiU=","X-Original-To":"binutils@sourceware.org","DMARC-Filter":"OpenDMARC Filter v1.4.2 sourceware.org C3799385B52A","To":"binutils@sourceware.org","Cc":"Richard Sandiford ","Subject":"[PATCH 13/31] aarch64: Add the SME2 FMLA and FMLS instructions","Date":"Thu, 30 Mar 2023 11:26:28 +0100","Message-Id":"<20230330102646.3327818-14-richard.sandiford@arm.com>","X-Mailer":"git-send-email 2.25.1","In-Reply-To":"<20230330102646.3327818-1-richard.sandiford@arm.com>","References":"<20230330102646.3327818-1-richard.sandiford@arm.com>","MIME-Version":"1.0","Content-Transfer-Encoding":"8bit","X-Spam-Status":"No, score=-31.3 required=5.0 tests=BAYES_00, GIT_PATCH_0,\n KAM_DMARC_NONE, KAM_DMARC_STATUS, KAM_LAZY_DOMAIN_SECURITY,\n SCC_10_SHORT_WORD_LINES, SCC_5_SHORT_WORD_LINES, SPF_HELO_NONE, SPF_NONE,\n TXREP autolearn=ham autolearn_force=no version=3.4.6","X-Spam-Checker-Version":"SpamAssassin 3.4.6 (2021-04-09) on\n server2.sourceware.org","X-BeenThere":"binutils@sourceware.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"Binutils mailing list ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","From":"Richard Sandiford via Binutils ","Reply-To":"Richard Sandiford ","Errors-To":"binutils-bounces+ouuuleilei=gmail.com@sourceware.org","Sender":"\"Binutils\" ","X-getmail-retrieved-from-mailbox":"=?utf-8?q?INBOX?=","X-GMAIL-THRID":"=?utf-8?q?1761790225854077591?=","X-GMAIL-MSGID":"=?utf-8?q?1761790225854077591?="},"content":"---\n gas/config/tc-aarch64.c | 2 +\n gas/testsuite/gas/aarch64/sme2-11-invalid.d | 3 +\n gas/testsuite/gas/aarch64/sme2-11-invalid.l | 101 ++\n gas/testsuite/gas/aarch64/sme2-11-invalid.s | 91 ++\n gas/testsuite/gas/aarch64/sme2-11-noarch.d | 3 +\n gas/testsuite/gas/aarch64/sme2-11-noarch.l | 117 ++\n gas/testsuite/gas/aarch64/sme2-11.d | 125 ++\n gas/testsuite/gas/aarch64/sme2-11.s | 127 ++\n .../gas/aarch64/sme2-f64f64-2-invalid.d | 3 +\n .../gas/aarch64/sme2-f64f64-2-invalid.l | 98 ++\n .../gas/aarch64/sme2-f64f64-2-invalid.s | 87 ++\n .../gas/aarch64/sme2-f64f64-2-noarch.d | 3 +\n .../gas/aarch64/sme2-f64f64-2-noarch.l | 117 ++\n gas/testsuite/gas/aarch64/sme2-f64f64-2.d | 125 ++\n gas/testsuite/gas/aarch64/sme2-f64f64-2.s | 127 ++\n include/opcode/aarch64.h | 2 +\n opcodes/aarch64-asm-2.c | 18 +-\n opcodes/aarch64-dis-2.c | 1220 ++++++++++-------\n opcodes/aarch64-opc-2.c | 2 +\n opcodes/aarch64-opc.c | 12 +\n opcodes/aarch64-opc.h | 2 +\n opcodes/aarch64-tbl.h | 28 +\n 22 files changed, 1884 insertions(+), 529 deletions(-)\n create mode 100644 gas/testsuite/gas/aarch64/sme2-11-invalid.d\n create mode 100644 gas/testsuite/gas/aarch64/sme2-11-invalid.l\n create mode 100644 gas/testsuite/gas/aarch64/sme2-11-invalid.s\n create mode 100644 gas/testsuite/gas/aarch64/sme2-11-noarch.d\n create mode 100644 gas/testsuite/gas/aarch64/sme2-11-noarch.l\n create mode 100644 gas/testsuite/gas/aarch64/sme2-11.d\n create mode 100644 gas/testsuite/gas/aarch64/sme2-11.s\n create mode 100644 gas/testsuite/gas/aarch64/sme2-f64f64-2-invalid.d\n create mode 100644 gas/testsuite/gas/aarch64/sme2-f64f64-2-invalid.l\n create mode 100644 gas/testsuite/gas/aarch64/sme2-f64f64-2-invalid.s\n create mode 100644 gas/testsuite/gas/aarch64/sme2-f64f64-2-noarch.d\n create mode 100644 gas/testsuite/gas/aarch64/sme2-f64f64-2-noarch.l\n create mode 100644 gas/testsuite/gas/aarch64/sme2-f64f64-2.d\n create mode 100644 gas/testsuite/gas/aarch64/sme2-f64f64-2.s","diff":"diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c\nindex 5e023152c17..47ad7048372 100644\n--- a/gas/config/tc-aarch64.c\n+++ b/gas/config/tc-aarch64.c\n@@ -6727,6 +6727,8 @@ parse_operands (char *str, const aarch64_opcode *opcode)\n \tcase AARCH64_OPND_SVE_Zm4_11_INDEX:\n \tcase AARCH64_OPND_SVE_Zm4_INDEX:\n \tcase AARCH64_OPND_SVE_Zn_INDEX:\n+\tcase AARCH64_OPND_SME_Zm_INDEX1:\n+\tcase AARCH64_OPND_SME_Zm_INDEX2:\n \tcase AARCH64_OPND_SME_Zn_INDEX1_16:\n \tcase AARCH64_OPND_SME_Zn_INDEX2_15:\n \tcase AARCH64_OPND_SME_Zn_INDEX2_16:\ndiff --git a/gas/testsuite/gas/aarch64/sme2-11-invalid.d b/gas/testsuite/gas/aarch64/sme2-11-invalid.d\nnew file mode 100644\nindex 00000000000..1bc250965dd\n--- /dev/null\n+++ b/gas/testsuite/gas/aarch64/sme2-11-invalid.d\n@@ -0,0 +1,3 @@\n+#as: -march=armv8-a\n+#source: sme2-11-invalid.s\n+#error_output: sme2-11-invalid.l\ndiff --git a/gas/testsuite/gas/aarch64/sme2-11-invalid.l b/gas/testsuite/gas/aarch64/sme2-11-invalid.l\nnew file mode 100644\nindex 00000000000..8044d265750\n--- /dev/null\n+++ b/gas/testsuite/gas/aarch64/sme2-11-invalid.l\n@@ -0,0 +1,101 @@\n+[^ :]+: Assembler messages:\n+[^ :]+:[0-9]+: Error: expected a register at operand 1 -- `fmla 0,{z0\\.s-z1\\.s},z0\\.s\\[0\\]'\n+[^ :]+:[0-9]+: Error: expected '{' at operand 2 -- `fmla za\\.s\\[w8,0\\],0,z0\\.s\\[0\\]'\n+[^ :]+:[0-9]+: Error: expected a register or register list at operand 3 -- `fmla za\\.s\\[w8,0\\],{z0\\.s-z1\\.s},0'\n+[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmla za\\.s\\[w7,0\\],{z0\\.s-z1\\.s},z0\\.s\\[0\\]'\n+[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmla za\\.s\\[w12,0\\],{z0\\.s-z1\\.s},z0\\.s\\[0\\]'\n+[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `fmla za\\.s\\[w8,-1\\],{z0\\.s-z1\\.s},z0\\.s\\[0\\]'\n+[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `fmla za\\.s\\[w8,8\\],{z0\\.s-z1\\.s},z0\\.s\\[0\\]'\n+[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 2 -- `fmla za\\.s\\[w8,0,vgx4\\],{z0\\.s-z1\\.s},z0\\.s\\[0\\]'\n+[^ :]+:[0-9]+: Error: expected a list of 2 or 4 registers at operand 2 -- `fmla za\\.s\\[w8,0\\],{z0\\.s-z2\\.s},z0\\.s\\[0\\]'\n+[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `fmla za\\.s\\[w8,0\\],{z1\\.s-z2\\.s},z0\\.s\\[0\\]'\n+[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `fmla za\\.s\\[w8,0\\],{z0\\.s-z1\\.s},z16\\.s\\[0\\]'\n+[^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `fmla za\\.s\\[w8,0\\],{z0\\.s-z1\\.s},z0\\.s\\[-1\\]'\n+[^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `fmla za\\.s\\[w8,0\\],{z0\\.s-z1\\.s},z0\\.s\\[4\\]'\n+[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmla za\\.s\\[w7,0\\],{z0\\.s-z3\\.s},z0\\.s\\[0\\]'\n+[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmla za\\.s\\[w12,0\\],{z0\\.s-z3\\.s},z0\\.s\\[0\\]'\n+[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `fmla za\\.s\\[w8,-1\\],{z0\\.s-z3\\.s},z0\\.s\\[0\\]'\n+[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `fmla za\\.s\\[w8,8\\],{z0\\.s-z3\\.s},z0\\.s\\[0\\]'\n+[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 2 -- `fmla za\\.s\\[w8,0,vgx2\\],{z0\\.s-z3\\.s},z0\\.s\\[0\\]'\n+[^ :]+:[0-9]+: Error: too many registers in vector register list at operand 2 -- `fmla za\\.s\\[w8,0\\],{z0\\.s-z4\\.s},z0\\.s\\[0\\]'\n+[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `fmla za\\.s\\[w8,0\\],{z1\\.s-z4\\.s},z0\\.s\\[0\\]'\n+[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `fmla za\\.s\\[w8,0\\],{z2\\.s-z5\\.s},z0\\.s\\[0\\]'\n+[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `fmla za\\.s\\[w8,0\\],{z3\\.s-z6\\.s},z0\\.s\\[0\\]'\n+[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `fmla za\\.s\\[w8,0\\],{z0\\.s-z3\\.s},z16\\.s\\[0\\]'\n+[^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `fmla za\\.s\\[w8,0\\],{z0\\.s-z3\\.s},z0\\.s\\[-1\\]'\n+[^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `fmla za\\.s\\[w8,0\\],{z0\\.s-z3\\.s},z0\\.s\\[4\\]'\n+[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmla za\\.s\\[w0,0\\],{z0\\.s-z1\\.s},z0\\.s'\n+[^ :]+:[0-9]+: Error: expected a 32-bit selection register at operand 1 -- `fmla za\\.s\\[w31,0\\],{z0\\.s-z1\\.s},z0\\.s'\n+[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `fmla za\\.s\\[w8,1<<63\\],{z0\\.s-z1\\.s},z0\\.s'\n+[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `fmla za\\.s\\[w8,0\\],{z0\\.s-z1\\.s},z31\\.s'\n+[^ :]+:[0-9]+: Error: the last offset is equal to the first offset at operand 1 -- `fmla za\\.s\\[w8,0:0\\],{z0\\.s-z1\\.s},z0\\.s'\n+[^ :]+:[0-9]+: Error: the last offset is less than the first offset at operand 1 -- `fmla za\\.s\\[w8,0:-1\\],{z0\\.s-z1\\.s},z0\\.s'\n+[^ :]+:[0-9]+: Error: expected a single offset rather than a range at operand 1 -- `fmla za\\.s\\[w8,0:1\\],{z0\\.s-z1\\.s},z0\\.s'\n+[^ :]+:[0-9]+: Error: expected a single offset rather than a range at operand 1 -- `fmla za\\.s\\[w8,0:100\\],{z0\\.s-z1\\.s},z0\\.s'\n+[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmla za\\.s\\[w7,0\\],{z0\\.s-z1\\.s},z0\\.s'\n+[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmla za\\.s\\[w12,0\\],{z0\\.s-z1\\.s},z0\\.s'\n+[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `fmla za\\.s\\[w8,-1\\],{z0\\.s-z1\\.s},z0\\.s'\n+[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `fmla za\\.s\\[w8,8\\],{z0\\.s-z1\\.s},z0\\.s'\n+[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `fmla za\\.s\\[w8,0\\],{z0\\.s-z1\\.s},z16\\.s'\n+[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmla za\\.s\\[w7,0\\],{z0\\.s-z3\\.s},z0\\.s'\n+[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmla za\\.s\\[w12,0\\],{z0\\.s-z3\\.s},z0\\.s'\n+[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `fmla za\\.s\\[w8,-1\\],{z0\\.s-z3\\.s},z0\\.s'\n+[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `fmla za\\.s\\[w8,8\\],{z0\\.s-z3\\.s},z0\\.s'\n+[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `fmla za\\.s\\[w8,0\\],{z0\\.s-z3\\.s},z16\\.s'\n+[^ :]+:[0-9]+: Error: expected a list of 2 or 4 registers at operand 2 -- `fmla za\\.s\\[w8,0\\],{z0\\.s-z2\\.s},z0\\.s'\n+[^ :]+:[0-9]+: Error: too many registers in vector register list at operand 2 -- `fmla za\\.s\\[w8,0\\],{z0\\.s-z4\\.s},z0\\.s'\n+[^ :]+:[0-9]+: Error: expected a list of 2 or 4 registers at operand 2 -- `fmla za\\.s\\[w8,0\\],{z0\\.s,z1\\.s,z2\\.s},z0\\.s'\n+[^ :]+:[0-9]+: Error: invalid register list at operand 2 -- `fmla za\\.s\\[w8,0\\],{z0\\.s,z1\\.s,z5\\.s},z0\\.s'\n+[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 2 -- `fmla za\\.s\\[w8,0,vgx4\\],{z0\\.s-z1\\.s},z0\\.s'\n+[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 2 -- `fmla za\\.s\\[w8,0,vgx2\\],{z0\\.s-z3\\.s},z0\\.s'\n+[^ :]+:[0-9]+: Error: operand mismatch -- `fmla za\\[w8,0\\],{z0\\.s-z1\\.s},z0\\.s'\n+[^ :]+:[0-9]+: Info: did you mean this\\?\n+[^ :]+:[0-9]+: Info: \tfmla za\\.s\\[w8, 0\\], {z0\\.s-z1\\.s}, z0\\.s\n+[^ :]+:[0-9]+: Info: other valid variant\\(s\\):\n+[^ :]+:[0-9]+: Info: \tfmla za\\.d\\[w8, 0\\], {z0\\.d-z1\\.d}, z0\\.d\n+[^ :]+:[0-9]+: Error: missing type suffix at operand 2 -- `fmla za\\.s\\[w8,0\\],{z0-z1},z0\\.s'\n+[^ :]+:[0-9]+: Error: operand mismatch -- `fmla za\\.s\\[w8,0\\],{z0\\.s-z1\\.s},z0'\n+[^ :]+:[0-9]+: Info: did you mean this\\?\n+[^ :]+:[0-9]+: Info: \tfmla za\\.s\\[w8, 0\\], {z0\\.s-z1\\.s}, z0\\.s\n+[^ :]+:[0-9]+: Info: other valid variant\\(s\\):\n+[^ :]+:[0-9]+: Info: \tfmla za\\.d\\[w8, 0\\], {z0\\.d-z1\\.d}, z0\\.d\n+[^ :]+:[0-9]+: Error: operand mismatch -- `fmla za\\[w8,0\\],{z0\\.s-z1\\.s},z0'\n+[^ :]+:[0-9]+: Info: did you mean this\\?\n+[^ :]+:[0-9]+: Info: \tfmla za\\.s\\[w8, 0\\], {z0\\.s-z1\\.s}, z0\\.s\n+[^ :]+:[0-9]+: Info: other valid variant\\(s\\):\n+[^ :]+:[0-9]+: Info: \tfmla za\\.d\\[w8, 0\\], {z0\\.d-z1\\.d}, z0\\.d\n+[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmla za\\.s\\[w7,0\\],{z0\\.s-z1\\.s},{z0\\.s-z1\\.s}'\n+[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmla za\\.s\\[w12,0\\],{z0\\.s-z1\\.s},{z0\\.s-z1\\.s}'\n+[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `fmla za\\.s\\[w8,-1\\],{z0\\.s-z1\\.s},{z0\\.s-z1\\.s}'\n+[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `fmla za\\.s\\[w8,8\\],{z0\\.s-z1\\.s},{z0\\.s-z1\\.s}'\n+[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `fmla za\\.s\\[w8,0\\],{z1\\.s-z2\\.s},{z0\\.s-z1\\.s}'\n+[^ :]+:[0-9]+: Error: start register out of range at operand 3 -- `fmla za\\.s\\[w8,0\\],{z0\\.s-z1\\.s},{z15\\.s-z16\\.s}'\n+[^ :]+:[0-9]+: Error: start register out of range at operand 3 -- `fmla za\\.s\\[w8,0\\],{z0\\.s-z1\\.s},{z31\\.s,z0\\.s}'\n+[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmla za\\.s\\[w7,0\\],{z0\\.s-z3\\.s},{z0\\.s-z3\\.s}'\n+[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmla za\\.s\\[w12,0\\],{z0\\.s-z3\\.s},{z0\\.s-z3\\.s}'\n+[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `fmla za\\.s\\[w8,-1\\],{z0\\.s-z3\\.s},{z0\\.s-z3\\.s}'\n+[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `fmla za\\.s\\[w8,8\\],{z0\\.s-z3\\.s},{z0\\.s-z3\\.s}'\n+[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `fmla za\\.s\\[w8,0\\],{z1\\.s-z4\\.s},{z0\\.s-z3\\.s}'\n+[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `fmla za\\.s\\[w8,0\\],{z2\\.s-z5\\.s},{z0\\.s-z3\\.s}'\n+[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `fmla za\\.s\\[w8,0\\],{z3\\.s-z6\\.s},{z0\\.s-z3\\.s}'\n+[^ :]+:[0-9]+: Error: start register out of range at operand 3 -- `fmla za\\.s\\[w8,0\\],{z0\\.s-z3\\.s},{z15\\.s-z18\\.s}'\n+[^ :]+:[0-9]+: Error: start register out of range at operand 3 -- `fmla za\\.s\\[w8,0\\],{z0\\.s-z3\\.s},{z29\\.s,z30\\.s,z31\\.s,z0\\.s}'\n+[^ :]+:[0-9]+: Error: expected a list of 2 or 4 registers at operand 2 -- `fmla za\\.s\\[w8,0\\],{z0\\.s-z2\\.s},{z0\\.s-z1\\.s}'\n+[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 3 -- `fmla za\\.s\\[w8,0\\],{z0\\.s-z3\\.s},{z0\\.s-z1\\.s}'\n+[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 3 -- `fmla za\\.s\\[w8,0\\],{z0\\.s-z1\\.s},{z0\\.s-z2\\.s}'\n+[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 3 -- `fmla za\\.s\\[w8,0\\],{z0\\.s-z1\\.s},{z0\\.s-z3\\.s}'\n+[^ :]+:[0-9]+: Error: too many registers in vector register list at operand 3 -- `fmla za\\.s\\[w8,0\\],{z0\\.s-z1\\.s},{z0\\.s-z4\\.s}'\n+[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 2 -- `fmla za\\.s\\[w8,0,vgx4\\],{z0\\.s-z1\\.s},{z0\\.s-z3\\.s}'\n+[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 3 -- `fmla za\\.s\\[w8,0,vgx4\\],{z0\\.s-z3\\.s},{z0\\.s-z1\\.s}'\n+[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 3 -- `fmla za\\.s\\[w8,0,vgx2\\],{z0\\.s-z1\\.s},{z0\\.s-z3\\.s}'\n+[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 2 -- `fmla za\\.s\\[w8,0,vgx2\\],{z0\\.s-z3\\.s},{z0\\.s-z1\\.s}'\n+[^ :]+:[0-9]+: Error: operand mismatch -- `fmla za\\[w8,0\\],{z0\\.s-z1\\.s},{z0\\.s-z1\\.s}'\n+[^ :]+:[0-9]+: Info: did you mean this\\?\n+[^ :]+:[0-9]+: Info: \tfmla za\\.s\\[w8, 0\\], {z0\\.s-z1\\.s}, {z0\\.s-z1\\.s}\n+[^ :]+:[0-9]+: Info: other valid variant\\(s\\):\n+[^ :]+:[0-9]+: Info: \tfmla za\\.d\\[w8, 0\\], {z0\\.d-z1\\.d}, {z0\\.d-z1\\.d}\n+[^ :]+:[0-9]+: Error: operand mismatch -- `fmla za\\[w8,0\\],{z0\\.s-z3\\.s},{z0\\.s-z3\\.s}'\n+[^ :]+:[0-9]+: Info: did you mean this\\?\n+[^ :]+:[0-9]+: Info: \tfmla za\\.s\\[w8, 0\\], {z0\\.s-z3\\.s}, {z0\\.s-z3\\.s}\n+[^ :]+:[0-9]+: Info: other valid variant\\(s\\):\n+[^ :]+:[0-9]+: Info: \tfmla za\\.d\\[w8, 0\\], {z0\\.d-z3\\.d}, {z0\\.d-z3\\.d}\ndiff --git a/gas/testsuite/gas/aarch64/sme2-11-invalid.s b/gas/testsuite/gas/aarch64/sme2-11-invalid.s\nnew file mode 100644\nindex 00000000000..70ab0c42e36\n--- /dev/null\n+++ b/gas/testsuite/gas/aarch64/sme2-11-invalid.s\n@@ -0,0 +1,91 @@\n+\tfmla\t0, { z0.s - z1.s }, z0.s[0]\n+\tfmla\tza.s[w8, 0], 0, z0.s[0]\n+\tfmla\tza.s[w8, 0], { z0.s - z1.s }, 0\n+\n+\tfmla\tza.s[w7, 0], { z0.s - z1.s }, z0.s[0]\n+\tfmla\tza.s[w12, 0], { z0.s - z1.s }, z0.s[0]\n+\tfmla\tza.s[w8, -1], { z0.s - z1.s }, z0.s[0]\n+\tfmla\tza.s[w8, 8], { z0.s - z1.s }, z0.s[0]\n+\tfmla\tza.s[w8, 0, vgx4], { z0.s - z1.s }, z0.s[0]\n+\tfmla\tza.s[w8, 0], { z0.s - z2.s }, z0.s[0]\n+\tfmla\tza.s[w8, 0], { z1.s - z2.s }, z0.s[0]\n+\tfmla\tza.s[w8, 0], { z0.s - z1.s }, z16.s[0]\n+\tfmla\tza.s[w8, 0], { z0.s - z1.s }, z0.s[-1]\n+\tfmla\tza.s[w8, 0], { z0.s - z1.s }, z0.s[4]\n+\n+\tfmla\tza.s[w7, 0], { z0.s - z3.s }, z0.s[0]\n+\tfmla\tza.s[w12, 0], { z0.s - z3.s }, z0.s[0]\n+\tfmla\tza.s[w8, -1], { z0.s - z3.s }, z0.s[0]\n+\tfmla\tza.s[w8, 8], { z0.s - z3.s }, z0.s[0]\n+\tfmla\tza.s[w8, 0, vgx2], { z0.s - z3.s }, z0.s[0]\n+\tfmla\tza.s[w8, 0], { z0.s - z4.s }, z0.s[0]\n+\tfmla\tza.s[w8, 0], { z1.s - z4.s }, z0.s[0]\n+\tfmla\tza.s[w8, 0], { z2.s - z5.s }, z0.s[0]\n+\tfmla\tza.s[w8, 0], { z3.s - z6.s }, z0.s[0]\n+\tfmla\tza.s[w8, 0], { z0.s - z3.s }, z16.s[0]\n+\tfmla\tza.s[w8, 0], { z0.s - z3.s }, z0.s[-1]\n+\tfmla\tza.s[w8, 0], { z0.s - z3.s }, z0.s[4]\n+\n+\tfmla\tza.s[w0, 0], { z0.s - z1.s }, z0.s\n+\tfmla\tza.s[w31, 0], { z0.s - z1.s }, z0.s\n+\tfmla\tza.s[w8, 1<<63], { z0.s - z1.s }, z0.s\n+\tfmla\tza.s[w8, 0], { z0.s - z1.s }, z31.s\n+\tfmla\tza.s[w8, 0:0], { z0.s - z1.s }, z0.s\n+\tfmla\tza.s[w8, 0:-1], { z0.s - z1.s }, z0.s\n+\tfmla\tza.s[w8, 0:1], { z0.s - z1.s }, z0.s\n+\tfmla\tza.s[w8, 0:100], { z0.s - z1.s }, z0.s\n+\n+\tfmla\tza.s[w7, 0], { z0.s - z1.s }, z0.s\n+\tfmla\tza.s[w12, 0], { z0.s - z1.s }, z0.s\n+\tfmla\tza.s[w8, -1], { z0.s - z1.s }, z0.s\n+\tfmla\tza.s[w8, 8], { z0.s - z1.s }, z0.s\n+\tfmla\tza.s[w8, 0], { z0.s - z1.s }, z16.s\n+\n+\tfmla\tza.s[w7, 0], { z0.s - z3.s }, z0.s\n+\tfmla\tza.s[w12, 0], { z0.s - z3.s }, z0.s\n+\tfmla\tza.s[w8, -1], { z0.s - z3.s }, z0.s\n+\tfmla\tza.s[w8, 8], { z0.s - z3.s }, z0.s\n+\tfmla\tza.s[w8, 0], { z0.s - z3.s }, z16.s\n+\n+\tfmla\tza.s[w8, 0], { z0.s - z2.s }, z0.s\n+\tfmla\tza.s[w8, 0], { z0.s - z4.s }, z0.s\n+\tfmla\tza.s[w8, 0], { z0.s, z1.s, z2.s }, z0.s\n+\tfmla\tza.s[w8, 0], { z0.s, z1.s, z5.s }, z0.s\n+\n+\tfmla\tza.s[w8, 0, vgx4], { z0.s - z1.s }, z0.s\n+\tfmla\tza.s[w8, 0, vgx2], { z0.s - z3.s }, z0.s\n+\tfmla\tza[w8, 0], { z0.s - z1.s }, z0.s\n+\tfmla\tza.s[w8, 0], { z0 - z1 }, z0.s\n+\tfmla\tza.s[w8, 0], { z0.s - z1.s }, z0\n+\tfmla\tza[w8, 0], { z0.s - z1.s }, z0\n+\n+\tfmla\tza.s[w7, 0], { z0.s - z1.s }, { z0.s - z1.s }\n+\tfmla\tza.s[w12, 0], { z0.s - z1.s }, { z0.s - z1.s }\n+\tfmla\tza.s[w8, -1], { z0.s - z1.s }, { z0.s - z1.s }\n+\tfmla\tza.s[w8, 8], { z0.s - z1.s }, { z0.s - z1.s }\n+\tfmla\tza.s[w8, 0], { z1.s - z2.s }, { z0.s - z1.s }\n+\tfmla\tza.s[w8, 0], { z0.s - z1.s }, { z15.s - z16.s }\n+\tfmla\tza.s[w8, 0], { z0.s - z1.s }, { z31.s, z0.s }\n+\n+\tfmla\tza.s[w7, 0], { z0.s - z3.s }, { z0.s - z3.s }\n+\tfmla\tza.s[w12, 0], { z0.s - z3.s }, { z0.s - z3.s }\n+\tfmla\tza.s[w8, -1], { z0.s - z3.s }, { z0.s - z3.s }\n+\tfmla\tza.s[w8, 8], { z0.s - z3.s }, { z0.s - z3.s }\n+\tfmla\tza.s[w8, 0], { z1.s - z4.s }, { z0.s - z3.s }\n+\tfmla\tza.s[w8, 0], { z2.s - z5.s }, { z0.s - z3.s }\n+\tfmla\tza.s[w8, 0], { z3.s - z6.s }, { z0.s - z3.s }\n+\tfmla\tza.s[w8, 0], { z0.s - z3.s }, { z15.s - z18.s }\n+\tfmla\tza.s[w8, 0], { z0.s - z3.s }, { z29.s, z30.s, z31.s, z0.s }\n+\n+\tfmla\tza.s[w8, 0], { z0.s - z2.s }, { z0.s - z1.s }\n+\tfmla\tza.s[w8, 0], { z0.s - z3.s }, { z0.s - z1.s }\n+\tfmla\tza.s[w8, 0], { z0.s - z1.s }, { z0.s - z2.s }\n+\tfmla\tza.s[w8, 0], { z0.s - z1.s }, { z0.s - z3.s }\n+\tfmla\tza.s[w8, 0], { z0.s - z1.s }, { z0.s - z4.s }\n+\n+\tfmla\tza.s[w8, 0, vgx4], { z0.s - z1.s }, { z0.s - z3.s }\n+\tfmla\tza.s[w8, 0, vgx4], { z0.s - z3.s }, { z0.s - z1.s }\n+\tfmla\tza.s[w8, 0, vgx2], { z0.s - z1.s }, { z0.s - z3.s }\n+\tfmla\tza.s[w8, 0, vgx2], { z0.s - z3.s }, { z0.s - z1.s }\n+\tfmla\tza[w8, 0], { z0.s - z1.s }, { z0.s - z1.s }\n+\tfmla\tza[w8, 0], { z0.s - z3.s }, { z0.s - z3.s }\ndiff --git a/gas/testsuite/gas/aarch64/sme2-11-noarch.d b/gas/testsuite/gas/aarch64/sme2-11-noarch.d\nnew file mode 100644\nindex 00000000000..7dcb6a04885\n--- /dev/null\n+++ b/gas/testsuite/gas/aarch64/sme2-11-noarch.d\n@@ -0,0 +1,3 @@\n+#as: -march=armv8-a+sme\n+#source: sme2-11.s\n+#error_output: sme2-11-noarch.l\ndiff --git a/gas/testsuite/gas/aarch64/sme2-11-noarch.l b/gas/testsuite/gas/aarch64/sme2-11-noarch.l\nnew file mode 100644\nindex 00000000000..05c3139f3b7\n--- /dev/null\n+++ b/gas/testsuite/gas/aarch64/sme2-11-noarch.l\n@@ -0,0 +1,117 @@\n+[^ :]+: Assembler messages:\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\\.s\\[w8,0\\],{z0\\.s-z1\\.s},z0\\.s\\[0\\]'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\\.s\\[w8,0,vgx2\\],{z0\\.s-z1\\.s},z0\\.s\\[0\\]'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmla ZA\\.S\\[W8,0,VGx2\\],{Z0\\.S-Z1\\.S},Z0\\.S\\[0\\]'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\\.s\\[w11,0\\],{z0\\.s-z1\\.s},z0\\.s\\[0\\]'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\\.s\\[w8,7\\],{z0\\.s-z1\\.s},z0\\.s\\[0\\]'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\\.s\\[w8,0\\],{z30\\.s-z31\\.s},z0\\.s\\[0\\]'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\\.s\\[w8,0\\],{z0\\.s-z1\\.s},z15\\.s\\[0\\]'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\\.s\\[w8,0\\],{z0\\.s-z1\\.s},z0\\.s\\[3\\]'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\\.s\\[w9,6\\],{z12\\.s-z13\\.s},z1\\.s\\[2\\]'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\\.s\\[w8,0\\],{z0\\.s-z3\\.s},z0\\.s\\[0\\]'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\\.s\\[w8,0,vgx4\\],{z0\\.s-z3\\.s},z0\\.s\\[0\\]'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmla ZA\\.S\\[W8,0,VGX4\\],{Z0\\.S-Z3\\.S},Z0\\.S\\[0\\]'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\\.s\\[w11,0\\],{z0\\.s-z3\\.s},z0\\.s\\[0\\]'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\\.s\\[w8,7\\],{z0\\.s-z3\\.s},z0\\.s\\[0\\]'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\\.s\\[w8,0\\],{z28\\.s-z31\\.s},z0\\.s\\[0\\]'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\\.s\\[w8,0\\],{z0\\.s-z3\\.s},z15\\.s\\[0\\]'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\\.s\\[w8,0\\],{z0\\.s-z3\\.s},z0\\.s\\[3\\]'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\\.s\\[w10,4\\],{z4\\.s-z7\\.s},z9\\.s\\[1\\]'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\\.s\\[w8,0\\],{z0\\.s-z1\\.s},z0\\.s'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\\.s\\[w8,0,vgx2\\],{z0\\.s-z1\\.s},z0\\.s'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmla ZA\\.s\\[W8,0,VGx2\\],{Z0\\.s-Z1\\.s},Z0\\.s'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmla ZA\\.S\\[W8,0,VGX2\\],{Z0\\.S-Z1\\.S},Z0\\.S'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\\.s\\[w11,0\\],{z0\\.s-z1\\.s},z0\\.s'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\\.s\\[w8,7\\],{z0\\.s-z1\\.s},z0\\.s'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\\.s\\[w8,0\\],{z30\\.s-z31\\.s},z0\\.s'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\\.s\\[w8,0\\],{z31\\.s,z0\\.s},z0\\.s'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\\.s\\[w8,0\\],{z31\\.s-z0\\.s},z0\\.s'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\\.s\\[w8,0\\],{z0\\.s-z1\\.s},z15\\.s'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\\.s\\[w9,5\\],{z9\\.s-z10\\.s},z6\\.s'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\\.s\\[w8,0\\],{z0\\.s-z3\\.s},z0\\.s'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\\.s\\[w8,0,vgx4\\],{z0\\.s-z3\\.s},z0\\.s'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmla ZA\\.s\\[W8,0,VGx4\\],{Z0\\.s-Z3\\.s},Z0\\.s'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmla ZA\\.S\\[W8,0,VGX4\\],{Z0\\.S-Z3\\.S},Z0\\.S'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\\.s\\[w11,0\\],{z0\\.s-z3\\.s},z0\\.s'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\\.s\\[w8,7\\],{z0\\.s-z3\\.s},z0\\.s'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\\.s\\[w8,0\\],{z28\\.s-z31\\.s},z0\\.s'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\\.s\\[w8,0\\],{z31\\.s,z0\\.s,z1\\.s,z2\\.s},z0\\.s'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\\.s\\[w8,0\\],{z31\\.s-z2\\.s},z0\\.s'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\\.s\\[w8,0\\],{z0\\.s-z3\\.s},z15\\.s'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\\.s\\[w11,2\\],{z23\\.s-z26\\.s},z13\\.s'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\\.s\\[w8,0\\],{z0\\.s-z1\\.s},{z0\\.s-z1\\.s}'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\\.s\\[w8,0,vgx2\\],{z0\\.s-z1\\.s},{z0\\.s-z1\\.s}'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmla ZA\\.s\\[W8,0,VGx2\\],{Z0\\.s-Z1\\.s},{Z0\\.s-Z1\\.s}'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmla ZA\\.S\\[W8,0,VGX2\\],{Z0\\.S-Z1\\.S},{Z0\\.S-Z1\\.S}'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\\.s\\[w11,0\\],{z0\\.s-z1\\.s},{z0\\.s-z1\\.s}'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\\.s\\[w8,7\\],{z0\\.s-z1\\.s},{z0\\.s-z1\\.s}'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\\.s\\[w8,0\\],{z30\\.s-z31\\.s},{z0\\.s-z1\\.s}'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\\.s\\[w8,0\\],{z0\\.s-z1\\.s},{z30\\.s-z31\\.s}'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\\.s\\[w10,1\\],{z22\\.s-z23\\.s},{z18\\.s-z19\\.s}'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\\.s\\[w8,0\\],{z0\\.s-z3\\.s},{z0\\.s-z3\\.s}'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\\.s\\[w8,0,vgx4\\],{z0\\.s-z3\\.s},{z0\\.s-z3\\.s}'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmla ZA\\.s\\[W8,0,VGx4\\],{Z0\\.s-Z3\\.s},{Z0\\.s-Z3\\.s}'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmla ZA\\.S\\[W8,0,VGX4\\],{Z0\\.S-Z3\\.S},{Z0\\.S-Z3\\.S}'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\\.s\\[w11,0\\],{z0\\.s-z3\\.s},{z0\\.s-z3\\.s}'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\\.s\\[w8,7\\],{z0\\.s-z3\\.s},{z0\\.s-z3\\.s}'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\\.s\\[w8,0\\],{z28\\.s-z31\\.s},{z0\\.s-z3\\.s}'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\\.s\\[w8,0\\],{z0\\.s-z3\\.s},{z28\\.s-z31\\.s}'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\\.s\\[w11,3\\],{z16\\.s-z19\\.s},{z24\\.s-z27\\.s}'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\\.s\\[w8,0\\],{z0\\.s-z1\\.s},z0\\.s\\[0\\]'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\\.s\\[w8,0,vgx2\\],{z0\\.s-z1\\.s},z0\\.s\\[0\\]'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmls ZA\\.S\\[W8,0,VGx2\\],{Z0\\.S-Z1\\.S},Z0\\.S\\[0\\]'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\\.s\\[w11,0\\],{z0\\.s-z1\\.s},z0\\.s\\[0\\]'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\\.s\\[w8,7\\],{z0\\.s-z1\\.s},z0\\.s\\[0\\]'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\\.s\\[w8,0\\],{z30\\.s-z31\\.s},z0\\.s\\[0\\]'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\\.s\\[w8,0\\],{z0\\.s-z1\\.s},z15\\.s\\[0\\]'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\\.s\\[w8,0\\],{z0\\.s-z1\\.s},z0\\.s\\[3\\]'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\\.s\\[w9,6\\],{z12\\.s-z13\\.s},z1\\.s\\[2\\]'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\\.s\\[w8,0\\],{z0\\.s-z3\\.s},z0\\.s\\[0\\]'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\\.s\\[w8,0,vgx4\\],{z0\\.s-z3\\.s},z0\\.s\\[0\\]'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmls ZA\\.S\\[W8,0,VGX4\\],{Z0\\.S-Z3\\.S},Z0\\.S\\[0\\]'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\\.s\\[w11,0\\],{z0\\.s-z3\\.s},z0\\.s\\[0\\]'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\\.s\\[w8,7\\],{z0\\.s-z3\\.s},z0\\.s\\[0\\]'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\\.s\\[w8,0\\],{z28\\.s-z31\\.s},z0\\.s\\[0\\]'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\\.s\\[w8,0\\],{z0\\.s-z3\\.s},z15\\.s\\[0\\]'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\\.s\\[w8,0\\],{z0\\.s-z3\\.s},z0\\.s\\[3\\]'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\\.s\\[w10,4\\],{z4\\.s-z7\\.s},z9\\.s\\[1\\]'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\\.s\\[w8,0\\],{z0\\.s-z1\\.s},z0\\.s'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\\.s\\[w8,0,vgx2\\],{z0\\.s-z1\\.s},z0\\.s'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmls ZA\\.s\\[W8,0,VGx2\\],{Z0\\.s-Z1\\.s},Z0\\.s'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmls ZA\\.S\\[W8,0,VGX2\\],{Z0\\.S-Z1\\.S},Z0\\.S'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\\.s\\[w11,0\\],{z0\\.s-z1\\.s},z0\\.s'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\\.s\\[w8,7\\],{z0\\.s-z1\\.s},z0\\.s'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\\.s\\[w8,0\\],{z30\\.s-z31\\.s},z0\\.s'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\\.s\\[w8,0\\],{z31\\.s,z0\\.s},z0\\.s'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\\.s\\[w8,0\\],{z31\\.s-z0\\.s},z0\\.s'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\\.s\\[w8,0\\],{z0\\.s-z1\\.s},z15\\.s'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\\.s\\[w9,5\\],{z9\\.s-z10\\.s},z6\\.s'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\\.s\\[w8,0\\],{z0\\.s-z3\\.s},z0\\.s'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\\.s\\[w8,0,vgx4\\],{z0\\.s-z3\\.s},z0\\.s'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmls ZA\\.s\\[W8,0,VGx4\\],{Z0\\.s-Z3\\.s},Z0\\.s'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmls ZA\\.S\\[W8,0,VGX4\\],{Z0\\.S-Z3\\.S},Z0\\.S'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\\.s\\[w11,0\\],{z0\\.s-z3\\.s},z0\\.s'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\\.s\\[w8,7\\],{z0\\.s-z3\\.s},z0\\.s'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\\.s\\[w8,0\\],{z28\\.s-z31\\.s},z0\\.s'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\\.s\\[w8,0\\],{z31\\.s,z0\\.s,z1\\.s,z2\\.s},z0\\.s'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\\.s\\[w8,0\\],{z31\\.s-z2\\.s},z0\\.s'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\\.s\\[w8,0\\],{z0\\.s-z3\\.s},z15\\.s'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\\.s\\[w11,2\\],{z23\\.s-z26\\.s},z13\\.s'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\\.s\\[w8,0\\],{z0\\.s-z1\\.s},{z0\\.s-z1\\.s}'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\\.s\\[w8,0,vgx2\\],{z0\\.s-z1\\.s},{z0\\.s-z1\\.s}'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmls ZA\\.s\\[W8,0,VGx2\\],{Z0\\.s-Z1\\.s},{Z0\\.s-Z1\\.s}'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmls ZA\\.S\\[W8,0,VGX2\\],{Z0\\.S-Z1\\.S},{Z0\\.S-Z1\\.S}'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\\.s\\[w11,0\\],{z0\\.s-z1\\.s},{z0\\.s-z1\\.s}'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\\.s\\[w8,7\\],{z0\\.s-z1\\.s},{z0\\.s-z1\\.s}'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\\.s\\[w8,0\\],{z30\\.s-z31\\.s},{z0\\.s-z1\\.s}'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\\.s\\[w8,0\\],{z0\\.s-z1\\.s},{z30\\.s-z31\\.s}'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\\.s\\[w10,1\\],{z22\\.s-z23\\.s},{z18\\.s-z19\\.s}'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\\.s\\[w8,0\\],{z0\\.s-z3\\.s},{z0\\.s-z3\\.s}'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\\.s\\[w8,0,vgx4\\],{z0\\.s-z3\\.s},{z0\\.s-z3\\.s}'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmls ZA\\.s\\[W8,0,VGx4\\],{Z0\\.s-Z3\\.s},{Z0\\.s-Z3\\.s}'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmls ZA\\.S\\[W8,0,VGX4\\],{Z0\\.S-Z3\\.S},{Z0\\.S-Z3\\.S}'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\\.s\\[w11,0\\],{z0\\.s-z3\\.s},{z0\\.s-z3\\.s}'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\\.s\\[w8,7\\],{z0\\.s-z3\\.s},{z0\\.s-z3\\.s}'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\\.s\\[w8,0\\],{z28\\.s-z31\\.s},{z0\\.s-z3\\.s}'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\\.s\\[w8,0\\],{z0\\.s-z3\\.s},{z28\\.s-z31\\.s}'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\\.s\\[w11,3\\],{z16\\.s-z19\\.s},{z24\\.s-z27\\.s}'\ndiff --git a/gas/testsuite/gas/aarch64/sme2-11.d b/gas/testsuite/gas/aarch64/sme2-11.d\nnew file mode 100644\nindex 00000000000..7f077e3a614\n--- /dev/null\n+++ b/gas/testsuite/gas/aarch64/sme2-11.d\n@@ -0,0 +1,125 @@\n+#as: -march=armv8-a+sme2\n+#objdump: -dr\n+\n+[^:]+: file format .*\n+\n+\n+[^:]+:\n+\n+[^:]+:\n+[^:]+:\tc1500000 \tfmla\tza\\.s\\[w8, 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z0.s[0]\n+\tfmls\tza.s[w8, 7], { z0.s - z1.s }, z0.s[0]\n+\tfmls\tza.s[w8, 0], { z30.s - z31.s }, z0.s[0]\n+\tfmls\tza.s[w8, 0], { z0.s - z1.s }, z15.s[0]\n+\tfmls\tza.s[w8, 0], { z0.s - z1.s }, z0.s[3]\n+\tfmls\tza.s[w9, 6], { z12.s - z13.s }, z1.s[2]\n+\n+\tfmls\tza.s[w8, 0], { z0.s - z3.s }, z0.s[0]\n+\tfmls\tza.s[w8, 0, vgx4], { z0.s - z3.s }, z0.s[0]\n+\tFMLS\tZA.S[W8, 0, VGX4], { Z0.S - Z3.S }, Z0.S[0]\n+\tfmls\tza.s[w11, 0], { z0.s - z3.s }, z0.s[0]\n+\tfmls\tza.s[w8, 7], { z0.s - z3.s }, z0.s[0]\n+\tfmls\tza.s[w8, 0], { z28.s - z31.s }, z0.s[0]\n+\tfmls\tza.s[w8, 0], { z0.s - z3.s }, z15.s[0]\n+\tfmls\tza.s[w8, 0], { z0.s - z3.s }, z0.s[3]\n+\tfmls\tza.s[w10, 4], { z4.s - z7.s }, z9.s[1]\n+\n+\tfmls\tza.s[w8, 0], { z0.s - z1.s }, z0.s\n+\tfmls\tza.s[w8, 0, vgx2], { z0.s - z1.s }, z0.s\n+\tFMLS\tZA.s[W8, 0, VGx2], { Z0.s - Z1.s }, Z0.s\n+\tFMLS\tZA.S[W8, 0, VGX2], { Z0.S - Z1.S }, Z0.S\n+\tfmls\tza.s[w11, 0], { z0.s - z1.s }, z0.s\n+\tfmls\tza.s[w8, 7], { z0.s - z1.s }, z0.s\n+\tfmls\tza.s[w8, 0], { z30.s - z31.s }, z0.s\n+\tfmls\tza.s[w8, 0], { z31.s, z0.s }, z0.s\n+\tfmls\tza.s[w8, 0], { z31.s - z0.s }, z0.s\n+\tfmls\tza.s[w8, 0], { z0.s - z1.s }, z15.s\n+\tfmls\tza.s[w9, 5], { z9.s - z10.s }, z6.s\n+\n+\tfmls\tza.s[w8, 0], { z0.s - z3.s }, z0.s\n+\tfmls\tza.s[w8, 0, vgx4], { z0.s - z3.s }, z0.s\n+\tFMLS\tZA.s[W8, 0, VGx4], { Z0.s - Z3.s }, Z0.s\n+\tFMLS\tZA.S[W8, 0, VGX4], { Z0.S - Z3.S }, Z0.S\n+\tfmls\tza.s[w11, 0], { z0.s - z3.s }, z0.s\n+\tfmls\tza.s[w8, 7], { z0.s - z3.s }, z0.s\n+\tfmls\tza.s[w8, 0], { z28.s - z31.s }, z0.s\n+\tfmls\tza.s[w8, 0], { z31.s, z0.s, z1.s, z2.s }, z0.s\n+\tfmls\tza.s[w8, 0], { z31.s - z2.s }, z0.s\n+\tfmls\tza.s[w8, 0], { z0.s - z3.s }, z15.s\n+\tfmls\tza.s[w11, 2], { z23.s - z26.s }, z13.s\n+\n+\tfmls\tza.s[w8, 0], { z0.s - z1.s }, { z0.s - z1.s }\n+\tfmls\tza.s[w8, 0, vgx2], { z0.s - z1.s }, { z0.s - z1.s }\n+\tFMLS\tZA.s[W8, 0, VGx2], { Z0.s - Z1.s }, { Z0.s - Z1.s }\n+\tFMLS\tZA.S[W8, 0, VGX2], { Z0.S - Z1.S }, { Z0.S - Z1.S }\n+\tfmls\tza.s[w11, 0], { z0.s - z1.s }, { z0.s - z1.s }\n+\tfmls\tza.s[w8, 7], { z0.s - z1.s }, { z0.s - z1.s }\n+\tfmls\tza.s[w8, 0], { z30.s - z31.s }, { z0.s - z1.s }\n+\tfmls\tza.s[w8, 0], { z0.s - z1.s }, { z30.s - z31.s }\n+\tfmls\tza.s[w10, 1], { z22.s - z23.s }, { z18.s - z19.s }\n+\n+\tfmls\tza.s[w8, 0], { z0.s - z3.s }, { z0.s - z3.s }\n+\tfmls\tza.s[w8, 0, vgx4], { z0.s - z3.s }, { z0.s - z3.s }\n+\tFMLS\tZA.s[W8, 0, VGx4], { Z0.s - Z3.s }, { Z0.s - Z3.s }\n+\tFMLS\tZA.S[W8, 0, VGX4], { Z0.S - Z3.S }, { Z0.S - Z3.S }\n+\tfmls\tza.s[w11, 0], { z0.s - z3.s }, { z0.s - z3.s }\n+\tfmls\tza.s[w8, 7], { z0.s - z3.s }, { z0.s - z3.s }\n+\tfmls\tza.s[w8, 0], { z28.s - z31.s }, { z0.s - z3.s }\n+\tfmls\tza.s[w8, 0], { z0.s - z3.s }, { z28.s - z31.s }\n+\tfmls\tza.s[w11, 3], { z16.s - z19.s }, { z24.s - z27.s }\ndiff --git a/gas/testsuite/gas/aarch64/sme2-f64f64-2-invalid.d b/gas/testsuite/gas/aarch64/sme2-f64f64-2-invalid.d\nnew file mode 100644\nindex 00000000000..e2e4a7a7607\n--- /dev/null\n+++ b/gas/testsuite/gas/aarch64/sme2-f64f64-2-invalid.d\n@@ -0,0 +1,3 @@\n+#as: -march=armv8-a\n+#source: sme2-f64f64-2-invalid.s\n+#error_output: sme2-f64f64-2-invalid.l\ndiff --git a/gas/testsuite/gas/aarch64/sme2-f64f64-2-invalid.l b/gas/testsuite/gas/aarch64/sme2-f64f64-2-invalid.l\nnew file mode 100644\nindex 00000000000..97b0db12d6c\n--- /dev/null\n+++ b/gas/testsuite/gas/aarch64/sme2-f64f64-2-invalid.l\n@@ -0,0 +1,98 @@\n+[^ :]+: Assembler messages:\n+[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmla za\\.d\\[w7,0\\],{z0\\.d-z1\\.d},z0\\.d\\[0\\]'\n+[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmla za\\.d\\[w12,0\\],{z0\\.d-z1\\.d},z0\\.d\\[0\\]'\n+[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `fmla za\\.d\\[w8,-1\\],{z0\\.d-z1\\.d},z0\\.d\\[0\\]'\n+[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `fmla za\\.d\\[w8,8\\],{z0\\.d-z1\\.d},z0\\.d\\[0\\]'\n+[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 2 -- `fmla za\\.d\\[w8,0,vgx4\\],{z0\\.d-z1\\.d},z0\\.d\\[0\\]'\n+[^ :]+:[0-9]+: Error: expected a list of 2 or 4 registers at operand 2 -- `fmla za\\.d\\[w8,0\\],{z0\\.d-z2\\.d},z0\\.d\\[0\\]'\n+[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `fmla za\\.d\\[w8,0\\],{z1\\.d-z2\\.d},z0\\.d\\[0\\]'\n+[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `fmla za\\.d\\[w8,0\\],{z0\\.d-z1\\.d},z16\\.d\\[0\\]'\n+[^ :]+:[0-9]+: Error: register element index out of range 0 to 1 at operand 3 -- `fmla za\\.d\\[w8,0\\],{z0\\.d-z1\\.d},z0\\.d\\[-1\\]'\n+[^ :]+:[0-9]+: Error: register element index out of range 0 to 1 at operand 3 -- `fmla za\\.d\\[w8,0\\],{z0\\.d-z1\\.d},z0\\.d\\[2\\]'\n+[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmla za\\.d\\[w7,0\\],{z0\\.d-z3\\.d},z0\\.d\\[0\\]'\n+[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmla za\\.d\\[w12,0\\],{z0\\.d-z3\\.d},z0\\.d\\[0\\]'\n+[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `fmla za\\.d\\[w8,-1\\],{z0\\.d-z3\\.d},z0\\.d\\[0\\]'\n+[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `fmla za\\.d\\[w8,8\\],{z0\\.d-z3\\.d},z0\\.d\\[0\\]'\n+[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 2 -- `fmla za\\.d\\[w8,0,vgx2\\],{z0\\.d-z3\\.d},z0\\.d\\[0\\]'\n+[^ :]+:[0-9]+: Error: too many registers in vector register list at operand 2 -- `fmla za\\.d\\[w8,0\\],{z0\\.d-z4\\.d},z0\\.d\\[0\\]'\n+[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `fmla za\\.d\\[w8,0\\],{z1\\.d-z4\\.d},z0\\.d\\[0\\]'\n+[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `fmla za\\.d\\[w8,0\\],{z2\\.d-z5\\.d},z0\\.d\\[0\\]'\n+[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `fmla za\\.d\\[w8,0\\],{z3\\.d-z6\\.d},z0\\.d\\[0\\]'\n+[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `fmla za\\.d\\[w8,0\\],{z0\\.d-z3\\.d},z16\\.d\\[0\\]'\n+[^ :]+:[0-9]+: Error: register element index out of range 0 to 1 at operand 3 -- `fmla za\\.d\\[w8,0\\],{z0\\.d-z3\\.d},z0\\.d\\[-1\\]'\n+[^ :]+:[0-9]+: Error: register element index out of range 0 to 1 at operand 3 -- `fmla za\\.d\\[w8,0\\],{z0\\.d-z3\\.d},z0\\.d\\[2\\]'\n+[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmla za\\.d\\[w0,0\\],{z0\\.d-z1\\.d},z0\\.d'\n+[^ :]+:[0-9]+: Error: expected a 32-bit selection register at operand 1 -- `fmla za\\.d\\[w31,0\\],{z0\\.d-z1\\.d},z0\\.d'\n+[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `fmla za\\.d\\[w8,1<<63\\],{z0\\.d-z1\\.d},z0\\.d'\n+[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `fmla za\\.d\\[w8,0\\],{z0\\.d-z1\\.d},z31\\.d'\n+[^ :]+:[0-9]+: Error: the last offset is equal to the first offset at operand 1 -- `fmla za\\.d\\[w8,0:0\\],{z0\\.d-z1\\.d},z0\\.d'\n+[^ :]+:[0-9]+: Error: the last offset is less than the first offset at operand 1 -- `fmla za\\.d\\[w8,0:-1\\],{z0\\.d-z1\\.d},z0\\.d'\n+[^ :]+:[0-9]+: Error: expected a single offset rather than a range at operand 1 -- `fmla za\\.d\\[w8,0:1\\],{z0\\.d-z1\\.d},z0\\.d'\n+[^ :]+:[0-9]+: Error: expected a single offset rather than a range at operand 1 -- `fmla za\\.d\\[w8,0:100\\],{z0\\.d-z1\\.d},z0\\.d'\n+[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmla za\\.d\\[w7,0\\],{z0\\.d-z1\\.d},z0\\.d'\n+[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmla za\\.d\\[w12,0\\],{z0\\.d-z1\\.d},z0\\.d'\n+[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `fmla za\\.d\\[w8,-1\\],{z0\\.d-z1\\.d},z0\\.d'\n+[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `fmla za\\.d\\[w8,8\\],{z0\\.d-z1\\.d},z0\\.d'\n+[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `fmla za\\.d\\[w8,0\\],{z0\\.d-z1\\.d},z16\\.d'\n+[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmla za\\.d\\[w7,0\\],{z0\\.d-z3\\.d},z0\\.d'\n+[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmla za\\.d\\[w12,0\\],{z0\\.d-z3\\.d},z0\\.d'\n+[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `fmla za\\.d\\[w8,-1\\],{z0\\.d-z3\\.d},z0\\.d'\n+[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `fmla za\\.d\\[w8,8\\],{z0\\.d-z3\\.d},z0\\.d'\n+[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `fmla za\\.d\\[w8,0\\],{z0\\.d-z3\\.d},z16\\.d'\n+[^ :]+:[0-9]+: Error: expected a list of 2 or 4 registers at operand 2 -- `fmla za\\.d\\[w8,0\\],{z0\\.d-z2\\.d},z0\\.d'\n+[^ :]+:[0-9]+: Error: too many registers in vector register list at operand 2 -- `fmla za\\.d\\[w8,0\\],{z0\\.d-z4\\.d},z0\\.d'\n+[^ :]+:[0-9]+: Error: expected a list of 2 or 4 registers at operand 2 -- `fmla za\\.d\\[w8,0\\],{z0\\.d,z1\\.d,z2\\.d},z0\\.d'\n+[^ :]+:[0-9]+: Error: invalid register list at operand 2 -- `fmla za\\.d\\[w8,0\\],{z0\\.d,z1\\.d,z5\\.d},z0\\.d'\n+[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 2 -- `fmla za\\.d\\[w8,0,vgx4\\],{z0\\.d-z1\\.d},z0\\.d'\n+[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 2 -- `fmla za\\.d\\[w8,0,vgx2\\],{z0\\.d-z3\\.d},z0\\.d'\n+[^ :]+:[0-9]+: Error: operand mismatch -- `fmla za\\[w8,0\\],{z0\\.d-z1\\.d},z0\\.d'\n+[^ :]+:[0-9]+: Info: did you mean this\\?\n+[^ :]+:[0-9]+: Info: \tfmla za\\.d\\[w8, 0\\], {z0\\.d-z1\\.d}, z0\\.d\n+[^ :]+:[0-9]+: Info: other valid variant\\(s\\):\n+[^ :]+:[0-9]+: Info: \tfmla za\\.s\\[w8, 0\\], {z0\\.s-z1\\.s}, z0\\.s\n+[^ :]+:[0-9]+: Error: missing type suffix at operand 2 -- `fmla za\\.d\\[w8,0\\],{z0-z1},z0\\.d'\n+[^ :]+:[0-9]+: Error: operand mismatch -- `fmla za\\.d\\[w8,0\\],{z0\\.d-z1\\.d},z0'\n+[^ :]+:[0-9]+: Info: did you mean this\\?\n+[^ :]+:[0-9]+: Info: \tfmla za\\.d\\[w8, 0\\], {z0\\.d-z1\\.d}, z0\\.d\n+[^ :]+:[0-9]+: Info: other valid variant\\(s\\):\n+[^ :]+:[0-9]+: Info: \tfmla za\\.s\\[w8, 0\\], {z0\\.s-z1\\.s}, z0\\.s\n+[^ :]+:[0-9]+: Error: operand mismatch -- `fmla za\\[w8,0\\],{z0\\.d-z1\\.d},z0'\n+[^ :]+:[0-9]+: Info: did you mean this\\?\n+[^ :]+:[0-9]+: Info: \tfmla za\\.d\\[w8, 0\\], {z0\\.d-z1\\.d}, z0\\.d\n+[^ :]+:[0-9]+: Info: other valid variant\\(s\\):\n+[^ :]+:[0-9]+: Info: \tfmla za\\.s\\[w8, 0\\], {z0\\.s-z1\\.s}, z0\\.s\n+[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmla za\\.d\\[w7,0\\],{z0\\.d-z1\\.d},{z0\\.d-z1\\.d}'\n+[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmla za\\.d\\[w12,0\\],{z0\\.d-z1\\.d},{z0\\.d-z1\\.d}'\n+[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `fmla za\\.d\\[w8,-1\\],{z0\\.d-z1\\.d},{z0\\.d-z1\\.d}'\n+[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `fmla za\\.d\\[w8,8\\],{z0\\.d-z1\\.d},{z0\\.d-z1\\.d}'\n+[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `fmla za\\.d\\[w8,0\\],{z1\\.d-z2\\.d},{z0\\.d-z1\\.d}'\n+[^ :]+:[0-9]+: Error: start register out of range at operand 3 -- `fmla za\\.d\\[w8,0\\],{z0\\.d-z1\\.d},{z15\\.d-z16\\.d}'\n+[^ :]+:[0-9]+: Error: start register out of range at operand 3 -- `fmla za\\.d\\[w8,0\\],{z0\\.d-z1\\.d},{z31\\.d,z0\\.d}'\n+[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmla za\\.d\\[w7,0\\],{z0\\.d-z3\\.d},{z0\\.d-z3\\.d}'\n+[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmla za\\.d\\[w12,0\\],{z0\\.d-z3\\.d},{z0\\.d-z3\\.d}'\n+[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `fmla za\\.d\\[w8,-1\\],{z0\\.d-z3\\.d},{z0\\.d-z3\\.d}'\n+[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `fmla za\\.d\\[w8,8\\],{z0\\.d-z3\\.d},{z0\\.d-z3\\.d}'\n+[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `fmla za\\.d\\[w8,0\\],{z1\\.d-z4\\.d},{z0\\.d-z3\\.d}'\n+[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `fmla za\\.d\\[w8,0\\],{z2\\.d-z5\\.d},{z0\\.d-z3\\.d}'\n+[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `fmla za\\.d\\[w8,0\\],{z3\\.d-z6\\.d},{z0\\.d-z3\\.d}'\n+[^ :]+:[0-9]+: Error: start register out of range at operand 3 -- `fmla za\\.d\\[w8,0\\],{z0\\.d-z3\\.d},{z15\\.d-z18\\.d}'\n+[^ :]+:[0-9]+: Error: start register out of range at operand 3 -- `fmla za\\.d\\[w8,0\\],{z0\\.d-z3\\.d},{z29\\.d,z30\\.d,z31\\.d,z0\\.d}'\n+[^ :]+:[0-9]+: Error: expected a list of 2 or 4 registers at operand 2 -- `fmla za\\.d\\[w8,0\\],{z0\\.d-z2\\.d},{z0\\.d-z1\\.d}'\n+[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 3 -- `fmla za\\.d\\[w8,0\\],{z0\\.d-z3\\.d},{z0\\.d-z1\\.d}'\n+[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 3 -- `fmla za\\.d\\[w8,0\\],{z0\\.d-z1\\.d},{z0\\.d-z2\\.d}'\n+[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 3 -- `fmla za\\.d\\[w8,0\\],{z0\\.d-z1\\.d},{z0\\.d-z3\\.d}'\n+[^ :]+:[0-9]+: Error: too many registers in vector register list at operand 3 -- `fmla za\\.d\\[w8,0\\],{z0\\.d-z1\\.d},{z0\\.d-z4\\.d}'\n+[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 2 -- `fmla za\\.d\\[w8,0,vgx4\\],{z0\\.d-z1\\.d},{z0\\.d-z3\\.d}'\n+[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 3 -- `fmla za\\.d\\[w8,0,vgx4\\],{z0\\.d-z3\\.d},{z0\\.d-z1\\.d}'\n+[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 3 -- `fmla za\\.d\\[w8,0,vgx2\\],{z0\\.d-z1\\.d},{z0\\.d-z3\\.d}'\n+[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 2 -- `fmla za\\.d\\[w8,0,vgx2\\],{z0\\.d-z3\\.d},{z0\\.d-z1\\.d}'\n+[^ :]+:[0-9]+: Error: operand mismatch -- `fmla za\\[w8,0\\],{z0\\.d-z1\\.d},{z0\\.d-z1\\.d}'\n+[^ :]+:[0-9]+: Info: did you mean this\\?\n+[^ :]+:[0-9]+: Info: \tfmla za\\.d\\[w8, 0\\], {z0\\.d-z1\\.d}, {z0\\.d-z1\\.d}\n+[^ :]+:[0-9]+: Info: other valid variant\\(s\\):\n+[^ :]+:[0-9]+: Info: \tfmla za\\.s\\[w8, 0\\], {z0\\.s-z1\\.s}, {z0\\.s-z1\\.s}\n+[^ :]+:[0-9]+: Error: operand mismatch -- `fmla za\\[w8,0\\],{z0\\.d-z3\\.d},{z0\\.d-z3\\.d}'\n+[^ :]+:[0-9]+: Info: did you mean this\\?\n+[^ :]+:[0-9]+: Info: \tfmla za\\.d\\[w8, 0\\], {z0\\.d-z3\\.d}, {z0\\.d-z3\\.d}\n+[^ :]+:[0-9]+: Info: other valid variant\\(s\\):\n+[^ :]+:[0-9]+: Info: \tfmla za\\.s\\[w8, 0\\], {z0\\.s-z3\\.s}, {z0\\.s-z3\\.s}\ndiff --git a/gas/testsuite/gas/aarch64/sme2-f64f64-2-invalid.s b/gas/testsuite/gas/aarch64/sme2-f64f64-2-invalid.s\nnew file mode 100644\nindex 00000000000..9839bfe8011\n--- /dev/null\n+++ b/gas/testsuite/gas/aarch64/sme2-f64f64-2-invalid.s\n@@ -0,0 +1,87 @@\n+\tfmla\tza.d[w7, 0], { z0.d - z1.d }, z0.d[0]\n+\tfmla\tza.d[w12, 0], { z0.d - z1.d }, z0.d[0]\n+\tfmla\tza.d[w8, -1], { z0.d - z1.d }, z0.d[0]\n+\tfmla\tza.d[w8, 8], { z0.d - z1.d }, z0.d[0]\n+\tfmla\tza.d[w8, 0, vgx4], { z0.d - z1.d }, z0.d[0]\n+\tfmla\tza.d[w8, 0], { z0.d - z2.d }, z0.d[0]\n+\tfmla\tza.d[w8, 0], { z1.d - z2.d }, z0.d[0]\n+\tfmla\tza.d[w8, 0], { z0.d - z1.d }, z16.d[0]\n+\tfmla\tza.d[w8, 0], { z0.d - z1.d }, z0.d[-1]\n+\tfmla\tza.d[w8, 0], { z0.d - z1.d }, z0.d[2]\n+\n+\tfmla\tza.d[w7, 0], { z0.d - z3.d }, z0.d[0]\n+\tfmla\tza.d[w12, 0], { z0.d - z3.d }, z0.d[0]\n+\tfmla\tza.d[w8, -1], { z0.d - z3.d }, z0.d[0]\n+\tfmla\tza.d[w8, 8], { z0.d - z3.d }, z0.d[0]\n+\tfmla\tza.d[w8, 0, vgx2], { z0.d - z3.d }, z0.d[0]\n+\tfmla\tza.d[w8, 0], { z0.d - z4.d }, z0.d[0]\n+\tfmla\tza.d[w8, 0], { z1.d - z4.d }, z0.d[0]\n+\tfmla\tza.d[w8, 0], { z2.d - z5.d }, z0.d[0]\n+\tfmla\tza.d[w8, 0], { z3.d - z6.d }, z0.d[0]\n+\tfmla\tza.d[w8, 0], { z0.d - z3.d }, z16.d[0]\n+\tfmla\tza.d[w8, 0], { z0.d - z3.d }, z0.d[-1]\n+\tfmla\tza.d[w8, 0], { z0.d - z3.d }, z0.d[2]\n+\n+\tfmla\tza.d[w0, 0], { z0.d - z1.d }, z0.d\n+\tfmla\tza.d[w31, 0], { z0.d - z1.d }, z0.d\n+\tfmla\tza.d[w8, 1<<63], { z0.d - z1.d }, z0.d\n+\tfmla\tza.d[w8, 0], { z0.d - z1.d }, z31.d\n+\tfmla\tza.d[w8, 0:0], { z0.d - z1.d }, z0.d\n+\tfmla\tza.d[w8, 0:-1], { z0.d - z1.d }, z0.d\n+\tfmla\tza.d[w8, 0:1], { z0.d - z1.d }, z0.d\n+\tfmla\tza.d[w8, 0:100], { z0.d - z1.d }, z0.d\n+\n+\tfmla\tza.d[w7, 0], { z0.d - z1.d }, z0.d\n+\tfmla\tza.d[w12, 0], { z0.d - z1.d }, z0.d\n+\tfmla\tza.d[w8, -1], { z0.d - z1.d }, z0.d\n+\tfmla\tza.d[w8, 8], { z0.d - z1.d }, z0.d\n+\tfmla\tza.d[w8, 0], { z0.d - z1.d }, z16.d\n+\n+\tfmla\tza.d[w7, 0], { z0.d - z3.d }, z0.d\n+\tfmla\tza.d[w12, 0], { z0.d - z3.d }, z0.d\n+\tfmla\tza.d[w8, -1], { z0.d - z3.d }, z0.d\n+\tfmla\tza.d[w8, 8], { z0.d - z3.d }, z0.d\n+\tfmla\tza.d[w8, 0], { z0.d - z3.d }, z16.d\n+\n+\tfmla\tza.d[w8, 0], { z0.d - z2.d }, z0.d\n+\tfmla\tza.d[w8, 0], { z0.d - z4.d }, z0.d\n+\tfmla\tza.d[w8, 0], { z0.d, z1.d, z2.d }, z0.d\n+\tfmla\tza.d[w8, 0], { z0.d, z1.d, z5.d }, z0.d\n+\n+\tfmla\tza.d[w8, 0, vgx4], { z0.d - z1.d }, z0.d\n+\tfmla\tza.d[w8, 0, vgx2], { z0.d - z3.d }, z0.d\n+\tfmla\tza[w8, 0], { z0.d - z1.d }, z0.d\n+\tfmla\tza.d[w8, 0], { z0 - z1 }, z0.d\n+\tfmla\tza.d[w8, 0], { z0.d - z1.d }, z0\n+\tfmla\tza[w8, 0], { z0.d - z1.d }, z0\n+\n+\tfmla\tza.d[w7, 0], { z0.d - z1.d }, { z0.d - z1.d }\n+\tfmla\tza.d[w12, 0], { z0.d - z1.d }, { z0.d - z1.d }\n+\tfmla\tza.d[w8, -1], { z0.d - z1.d }, { z0.d - z1.d }\n+\tfmla\tza.d[w8, 8], { z0.d - z1.d }, { z0.d - z1.d }\n+\tfmla\tza.d[w8, 0], { z1.d - z2.d }, { z0.d - z1.d }\n+\tfmla\tza.d[w8, 0], { z0.d - z1.d }, { z15.d - z16.d }\n+\tfmla\tza.d[w8, 0], { z0.d - z1.d }, { z31.d, z0.d }\n+\n+\tfmla\tza.d[w7, 0], { z0.d - z3.d }, { z0.d - z3.d }\n+\tfmla\tza.d[w12, 0], { z0.d - z3.d }, { z0.d - z3.d }\n+\tfmla\tza.d[w8, -1], { z0.d - z3.d }, { z0.d - z3.d }\n+\tfmla\tza.d[w8, 8], { z0.d - z3.d }, { z0.d - z3.d }\n+\tfmla\tza.d[w8, 0], { z1.d - z4.d }, { z0.d - z3.d }\n+\tfmla\tza.d[w8, 0], { z2.d - z5.d }, { z0.d - z3.d }\n+\tfmla\tza.d[w8, 0], { z3.d - z6.d }, { z0.d - z3.d }\n+\tfmla\tza.d[w8, 0], { z0.d - z3.d }, { z15.d - z18.d }\n+\tfmla\tza.d[w8, 0], { z0.d - z3.d }, { z29.d, z30.d, z31.d, z0.d }\n+\n+\tfmla\tza.d[w8, 0], { z0.d - z2.d }, { z0.d - z1.d }\n+\tfmla\tza.d[w8, 0], { z0.d - z3.d }, { z0.d - z1.d }\n+\tfmla\tza.d[w8, 0], { z0.d - z1.d }, { z0.d - z2.d }\n+\tfmla\tza.d[w8, 0], { z0.d - z1.d }, { z0.d - z3.d }\n+\tfmla\tza.d[w8, 0], { z0.d - z1.d }, { z0.d - z4.d }\n+\n+\tfmla\tza.d[w8, 0, vgx4], { z0.d - z1.d }, { z0.d - z3.d }\n+\tfmla\tza.d[w8, 0, vgx4], { z0.d - z3.d }, { z0.d - z1.d }\n+\tfmla\tza.d[w8, 0, vgx2], { z0.d - z1.d }, { z0.d - z3.d }\n+\tfmla\tza.d[w8, 0, vgx2], { z0.d - z3.d }, { z0.d - z1.d }\n+\tfmla\tza[w8, 0], { z0.d - z1.d }, { z0.d - z1.d }\n+\tfmla\tza[w8, 0], { z0.d - z3.d }, { z0.d - z3.d }\ndiff --git a/gas/testsuite/gas/aarch64/sme2-f64f64-2-noarch.d b/gas/testsuite/gas/aarch64/sme2-f64f64-2-noarch.d\nnew file mode 100644\nindex 00000000000..23c66a9aaee\n--- /dev/null\n+++ b/gas/testsuite/gas/aarch64/sme2-f64f64-2-noarch.d\n@@ -0,0 +1,3 @@\n+#as: -march=armv8-a+sme2\n+#source: sme2-f64f64-2.s\n+#error_output: sme2-f64f64-2-noarch.l\ndiff --git a/gas/testsuite/gas/aarch64/sme2-f64f64-2-noarch.l b/gas/testsuite/gas/aarch64/sme2-f64f64-2-noarch.l\nnew file mode 100644\nindex 00000000000..5ab290d4080\n--- /dev/null\n+++ b/gas/testsuite/gas/aarch64/sme2-f64f64-2-noarch.l\n@@ -0,0 +1,117 @@\n+[^ :]+: Assembler messages:\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\\.d\\[w8,0\\],{z0\\.d-z1\\.d},z0\\.d\\[0\\]'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\\.d\\[w8,0,vgx2\\],{z0\\.d-z1\\.d},z0\\.d\\[0\\]'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmla ZA\\.d\\[W8,0,VGx2\\],{Z0\\.d-Z1\\.d},Z0\\.d\\[0\\]'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\\.d\\[w11,0\\],{z0\\.d-z1\\.d},z0\\.d\\[0\\]'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\\.d\\[w8,7\\],{z0\\.d-z1\\.d},z0\\.d\\[0\\]'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\\.d\\[w8,0\\],{z30\\.d-z31\\.d},z0\\.d\\[0\\]'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\\.d\\[w8,0\\],{z0\\.d-z1\\.d},z15\\.d\\[0\\]'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\\.d\\[w8,0\\],{z0\\.d-z1\\.d},z0\\.d\\[1\\]'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\\.d\\[w10,2\\],{z6\\.d-z7\\.d},z5\\.d\\[1\\]'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\\.d\\[w8,0\\],{z0\\.d-z3\\.d},z0\\.d\\[0\\]'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\\.d\\[w8,0,vgx4\\],{z0\\.d-z3\\.d},z0\\.d\\[0\\]'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmla ZA\\.D\\[W8,0,VGX4\\],{Z0\\.D-Z3\\.D},Z0\\.D\\[0\\]'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\\.d\\[w11,0\\],{z0\\.d-z3\\.d},z0\\.d\\[0\\]'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\\.d\\[w8,7\\],{z0\\.d-z3\\.d},z0\\.d\\[0\\]'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\\.d\\[w8,0\\],{z28\\.d-z31\\.d},z0\\.d\\[0\\]'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\\.d\\[w8,0\\],{z0\\.d-z3\\.d},z15\\.d\\[0\\]'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\\.d\\[w8,0\\],{z0\\.d-z3\\.d},z0\\.d\\[1\\]'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\\.d\\[w9,3\\],{z8\\.d-z11\\.d},z14\\.d\\[1\\]'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\\.d\\[w8,0\\],{z0\\.d-z1\\.d},z0\\.d'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\\.d\\[w8,0,vgx2\\],{z0\\.d-z1\\.d},z0\\.d'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmla ZA\\.d\\[W8,0,VGx2\\],{Z0\\.d-Z1\\.d},Z0\\.d'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmla ZA\\.D\\[W8,0,VGX2\\],{Z0\\.D-Z1\\.D},Z0\\.D'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\\.d\\[w11,0\\],{z0\\.d-z1\\.d},z0\\.d'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\\.d\\[w8,7\\],{z0\\.d-z1\\.d},z0\\.d'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\\.d\\[w8,0\\],{z30\\.d-z31\\.d},z0\\.d'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\\.d\\[w8,0\\],{z31\\.d,z0\\.d},z0\\.d'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\\.d\\[w8,0\\],{z31\\.d-z0\\.d},z0\\.d'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\\.d\\[w8,0\\],{z0\\.d-z1\\.d},z15\\.d'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\\.d\\[w9,5\\],{z9\\.d-z10\\.d},z6\\.d'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\\.d\\[w8,0\\],{z0\\.d-z3\\.d},z0\\.d'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\\.d\\[w8,0,vgx4\\],{z0\\.d-z3\\.d},z0\\.d'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmla ZA\\.d\\[W8,0,VGx4\\],{Z0\\.d-Z3\\.d},Z0\\.d'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmla ZA\\.D\\[W8,0,VGX4\\],{Z0\\.D-Z3\\.D},Z0\\.D'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\\.d\\[w11,0\\],{z0\\.d-z3\\.d},z0\\.d'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\\.d\\[w8,7\\],{z0\\.d-z3\\.d},z0\\.d'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\\.d\\[w8,0\\],{z28\\.d-z31\\.d},z0\\.d'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\\.d\\[w8,0\\],{z31\\.d,z0\\.d,z1\\.d,z2\\.d},z0\\.d'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\\.d\\[w8,0\\],{z31\\.d-z2\\.d},z0\\.d'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\\.d\\[w8,0\\],{z0\\.d-z3\\.d},z15\\.d'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\\.d\\[w11,2\\],{z23\\.d-z26\\.d},z13\\.d'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\\.d\\[w8,0\\],{z0\\.d-z1\\.d},{z0\\.d-z1\\.d}'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\\.d\\[w8,0,vgx2\\],{z0\\.d-z1\\.d},{z0\\.d-z1\\.d}'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmla ZA\\.d\\[W8,0,VGx2\\],{Z0\\.d-Z1\\.d},{Z0\\.d-Z1\\.d}'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmla ZA\\.D\\[W8,0,VGX2\\],{Z0\\.D-Z1\\.D},{Z0\\.D-Z1\\.D}'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\\.d\\[w11,0\\],{z0\\.d-z1\\.d},{z0\\.d-z1\\.d}'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\\.d\\[w8,7\\],{z0\\.d-z1\\.d},{z0\\.d-z1\\.d}'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\\.d\\[w8,0\\],{z30\\.d-z31\\.d},{z0\\.d-z1\\.d}'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\\.d\\[w8,0\\],{z0\\.d-z1\\.d},{z30\\.d-z31\\.d}'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\\.d\\[w10,1\\],{z22\\.d-z23\\.d},{z18\\.d-z19\\.d}'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\\.d\\[w8,0\\],{z0\\.d-z3\\.d},{z0\\.d-z3\\.d}'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\\.d\\[w8,0,vgx4\\],{z0\\.d-z3\\.d},{z0\\.d-z3\\.d}'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmla ZA\\.d\\[W8,0,VGx4\\],{Z0\\.d-Z3\\.d},{Z0\\.d-Z3\\.d}'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmla ZA\\.D\\[W8,0,VGX4\\],{Z0\\.D-Z3\\.D},{Z0\\.D-Z3\\.D}'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\\.d\\[w11,0\\],{z0\\.d-z3\\.d},{z0\\.d-z3\\.d}'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\\.d\\[w8,7\\],{z0\\.d-z3\\.d},{z0\\.d-z3\\.d}'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\\.d\\[w8,0\\],{z28\\.d-z31\\.d},{z0\\.d-z3\\.d}'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\\.d\\[w8,0\\],{z0\\.d-z3\\.d},{z28\\.d-z31\\.d}'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\\.d\\[w11,3\\],{z16\\.d-z19\\.d},{z24\\.d-z27\\.d}'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\\.d\\[w8,0\\],{z0\\.d-z1\\.d},z0\\.d\\[0\\]'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\\.d\\[w8,0,vgx2\\],{z0\\.d-z1\\.d},z0\\.d\\[0\\]'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmls ZA\\.d\\[W8,0,VGx2\\],{Z0\\.d-Z1\\.d},Z0\\.d\\[0\\]'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\\.d\\[w11,0\\],{z0\\.d-z1\\.d},z0\\.d\\[0\\]'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\\.d\\[w8,7\\],{z0\\.d-z1\\.d},z0\\.d\\[0\\]'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\\.d\\[w8,0\\],{z30\\.d-z31\\.d},z0\\.d\\[0\\]'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\\.d\\[w8,0\\],{z0\\.d-z1\\.d},z15\\.d\\[0\\]'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\\.d\\[w8,0\\],{z0\\.d-z1\\.d},z0\\.d\\[1\\]'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\\.d\\[w10,2\\],{z6\\.d-z7\\.d},z5\\.d\\[1\\]'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\\.d\\[w8,0\\],{z0\\.d-z3\\.d},z0\\.d\\[0\\]'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\\.d\\[w8,0,vgx4\\],{z0\\.d-z3\\.d},z0\\.d\\[0\\]'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmls ZA\\.D\\[W8,0,VGX4\\],{Z0\\.D-Z3\\.D},Z0\\.D\\[0\\]'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\\.d\\[w11,0\\],{z0\\.d-z3\\.d},z0\\.d\\[0\\]'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\\.d\\[w8,7\\],{z0\\.d-z3\\.d},z0\\.d\\[0\\]'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\\.d\\[w8,0\\],{z28\\.d-z31\\.d},z0\\.d\\[0\\]'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\\.d\\[w8,0\\],{z0\\.d-z3\\.d},z15\\.d\\[0\\]'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\\.d\\[w8,0\\],{z0\\.d-z3\\.d},z0\\.d\\[1\\]'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\\.d\\[w9,3\\],{z8\\.d-z11\\.d},z14\\.d\\[1\\]'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\\.d\\[w8,0\\],{z0\\.d-z1\\.d},z0\\.d'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\\.d\\[w8,0,vgx2\\],{z0\\.d-z1\\.d},z0\\.d'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmls ZA\\.d\\[W8,0,VGx2\\],{Z0\\.d-Z1\\.d},Z0\\.d'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmls ZA\\.D\\[W8,0,VGX2\\],{Z0\\.D-Z1\\.D},Z0\\.D'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\\.d\\[w11,0\\],{z0\\.d-z1\\.d},z0\\.d'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\\.d\\[w8,7\\],{z0\\.d-z1\\.d},z0\\.d'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\\.d\\[w8,0\\],{z30\\.d-z31\\.d},z0\\.d'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\\.d\\[w8,0\\],{z31\\.d,z0\\.d},z0\\.d'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\\.d\\[w8,0\\],{z31\\.d-z0\\.d},z0\\.d'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\\.d\\[w8,0\\],{z0\\.d-z1\\.d},z15\\.d'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\\.d\\[w9,5\\],{z9\\.d-z10\\.d},z6\\.d'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\\.d\\[w8,0\\],{z0\\.d-z3\\.d},z0\\.d'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\\.d\\[w8,0,vgx4\\],{z0\\.d-z3\\.d},z0\\.d'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmls ZA\\.d\\[W8,0,VGx4\\],{Z0\\.d-Z3\\.d},Z0\\.d'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmls ZA\\.D\\[W8,0,VGX4\\],{Z0\\.D-Z3\\.D},Z0\\.D'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\\.d\\[w11,0\\],{z0\\.d-z3\\.d},z0\\.d'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\\.d\\[w8,7\\],{z0\\.d-z3\\.d},z0\\.d'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\\.d\\[w8,0\\],{z28\\.d-z31\\.d},z0\\.d'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\\.d\\[w8,0\\],{z31\\.d,z0\\.d,z1\\.d,z2\\.d},z0\\.d'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\\.d\\[w8,0\\],{z31\\.d-z2\\.d},z0\\.d'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\\.d\\[w8,0\\],{z0\\.d-z3\\.d},z15\\.d'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\\.d\\[w11,2\\],{z23\\.d-z26\\.d},z13\\.d'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\\.d\\[w8,0\\],{z0\\.d-z1\\.d},{z0\\.d-z1\\.d}'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\\.d\\[w8,0,vgx2\\],{z0\\.d-z1\\.d},{z0\\.d-z1\\.d}'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmls ZA\\.d\\[W8,0,VGx2\\],{Z0\\.d-Z1\\.d},{Z0\\.d-Z1\\.d}'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmls ZA\\.D\\[W8,0,VGX2\\],{Z0\\.D-Z1\\.D},{Z0\\.D-Z1\\.D}'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\\.d\\[w11,0\\],{z0\\.d-z1\\.d},{z0\\.d-z1\\.d}'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\\.d\\[w8,7\\],{z0\\.d-z1\\.d},{z0\\.d-z1\\.d}'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\\.d\\[w8,0\\],{z30\\.d-z31\\.d},{z0\\.d-z1\\.d}'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\\.d\\[w8,0\\],{z0\\.d-z1\\.d},{z30\\.d-z31\\.d}'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\\.d\\[w10,1\\],{z22\\.d-z23\\.d},{z18\\.d-z19\\.d}'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\\.d\\[w8,0\\],{z0\\.d-z3\\.d},{z0\\.d-z3\\.d}'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\\.d\\[w8,0,vgx4\\],{z0\\.d-z3\\.d},{z0\\.d-z3\\.d}'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmls ZA\\.d\\[W8,0,VGx4\\],{Z0\\.d-Z3\\.d},{Z0\\.d-Z3\\.d}'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmls ZA\\.D\\[W8,0,VGX4\\],{Z0\\.D-Z3\\.D},{Z0\\.D-Z3\\.D}'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\\.d\\[w11,0\\],{z0\\.d-z3\\.d},{z0\\.d-z3\\.d}'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\\.d\\[w8,7\\],{z0\\.d-z3\\.d},{z0\\.d-z3\\.d}'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\\.d\\[w8,0\\],{z28\\.d-z31\\.d},{z0\\.d-z3\\.d}'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\\.d\\[w8,0\\],{z0\\.d-z3\\.d},{z28\\.d-z31\\.d}'\n+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\\.d\\[w11,3\\],{z16\\.d-z19\\.d},{z24\\.d-z27\\.d}'\ndiff --git a/gas/testsuite/gas/aarch64/sme2-f64f64-2.d b/gas/testsuite/gas/aarch64/sme2-f64f64-2.d\nnew file mode 100644\nindex 00000000000..dbc8d65d2c9\n--- /dev/null\n+++ b/gas/testsuite/gas/aarch64/sme2-f64f64-2.d\n@@ -0,0 +1,125 @@\n+#as: -march=armv8-a+sme2+sme-f64f64\n+#objdump: -dr\n+\n+[^:]+: file format .*\n+\n+\n+[^:]+:\n+\n+[^:]+:\n+[^:]+:\tc1d00000 \tfmla\tza\\.d\\[w8, 0, vgx2\\], {z0\\.d-z1\\.d}, z0\\.d\\[0\\]\n+[^:]+:\tc1d00000 \tfmla\tza\\.d\\[w8, 0, vgx2\\], {z0\\.d-z1\\.d}, z0\\.d\\[0\\]\n+[^:]+:\tc1d00000 \tfmla\tza\\.d\\[w8, 0, vgx2\\], {z0\\.d-z1\\.d}, z0\\.d\\[0\\]\n+[^:]+:\tc1d06000 \tfmla\tza\\.d\\[w11, 0, vgx2\\], {z0\\.d-z1\\.d}, z0\\.d\\[0\\]\n+[^:]+:\tc1d00007 \tfmla\tza\\.d\\[w8, 7, vgx2\\], {z0\\.d-z1\\.d}, z0\\.d\\[0\\]\n+[^:]+:\tc1d003c0 \tfmla\tza\\.d\\[w8, 0, vgx2\\], {z30\\.d-z31\\.d}, z0\\.d\\[0\\]\n+[^:]+:\tc1df0000 \tfmla\tza\\.d\\[w8, 0, vgx2\\], {z0\\.d-z1\\.d}, z15\\.d\\[0\\]\n+[^:]+:\tc1d00400 \tfmla\tza\\.d\\[w8, 0, vgx2\\], {z0\\.d-z1\\.d}, z0\\.d\\[1\\]\n+[^:]+:\tc1d544c2 \tfmla\tza\\.d\\[w10, 2, vgx2\\], {z6\\.d-z7\\.d}, z5\\.d\\[1\\]\n+[^:]+:\tc1d08000 \tfmla\tza\\.d\\[w8, 0, vgx4\\], {z0\\.d-z3\\.d}, z0\\.d\\[0\\]\n+[^:]+:\tc1d08000 \tfmla\tza\\.d\\[w8, 0, vgx4\\], {z0\\.d-z3\\.d}, z0\\.d\\[0\\]\n+[^:]+:\tc1d08000 \tfmla\tza\\.d\\[w8, 0, vgx4\\], {z0\\.d-z3\\.d}, z0\\.d\\[0\\]\n+[^:]+:\tc1d0e000 \tfmla\tza\\.d\\[w11, 0, vgx4\\], {z0\\.d-z3\\.d}, z0\\.d\\[0\\]\n+[^:]+:\tc1d08007 \tfmla\tza\\.d\\[w8, 7, vgx4\\], {z0\\.d-z3\\.d}, z0\\.d\\[0\\]\n+[^:]+:\tc1d08380 \tfmla\tza\\.d\\[w8, 0, vgx4\\], {z28\\.d-z31\\.d}, z0\\.d\\[0\\]\n+[^:]+:\tc1df8000 \tfmla\tza\\.d\\[w8, 0, vgx4\\], {z0\\.d-z3\\.d}, z15\\.d\\[0\\]\n+[^:]+:\tc1d08400 \tfmla\tza\\.d\\[w8, 0, vgx4\\], {z0\\.d-z3\\.d}, z0\\.d\\[1\\]\n+[^:]+:\tc1dea503 \tfmla\tza\\.d\\[w9, 3, vgx4\\], {z8\\.d-z11\\.d}, z14\\.d\\[1\\]\n+[^:]+:\tc1601800 \tfmla\tza\\.d\\[w8, 0, vgx2\\], {z0\\.d-z1\\.d}, z0\\.d\n+[^:]+:\tc1601800 \tfmla\tza\\.d\\[w8, 0, vgx2\\], {z0\\.d-z1\\.d}, z0\\.d\n+[^:]+:\tc1601800 \tfmla\tza\\.d\\[w8, 0, vgx2\\], {z0\\.d-z1\\.d}, z0\\.d\n+[^:]+:\tc1601800 \tfmla\tza\\.d\\[w8, 0, vgx2\\], {z0\\.d-z1\\.d}, z0\\.d\n+[^:]+:\tc1607800 \tfmla\tza\\.d\\[w11, 0, vgx2\\], {z0\\.d-z1\\.d}, z0\\.d\n+[^:]+:\tc1601807 \tfmla\tza\\.d\\[w8, 7, vgx2\\], {z0\\.d-z1\\.d}, z0\\.d\n+[^:]+:\tc1601bc0 \tfmla\tza\\.d\\[w8, 0, vgx2\\], {z30\\.d-z31\\.d}, z0\\.d\n+[^:]+:\tc1601be0 \tfmla\tza\\.d\\[w8, 0, vgx2\\], {z31\\.d-z0\\.d}, z0\\.d\n+[^:]+:\tc1601be0 \tfmla\tza\\.d\\[w8, 0, vgx2\\], {z31\\.d-z0\\.d}, z0\\.d\n+[^:]+:\tc16f1800 \tfmla\tza\\.d\\[w8, 0, vgx2\\], {z0\\.d-z1\\.d}, z15\\.d\n+[^:]+:\tc1663925 \tfmla\tza\\.d\\[w9, 5, vgx2\\], {z9\\.d-z10\\.d}, z6\\.d\n+[^:]+:\tc1701800 \tfmla\tza\\.d\\[w8, 0, vgx4\\], {z0\\.d-z3\\.d}, z0\\.d\n+[^:]+:\tc1701800 \tfmla\tza\\.d\\[w8, 0, vgx4\\], {z0\\.d-z3\\.d}, z0\\.d\n+[^:]+:\tc1701800 \tfmla\tza\\.d\\[w8, 0, vgx4\\], {z0\\.d-z3\\.d}, z0\\.d\n+[^:]+:\tc1701800 \tfmla\tza\\.d\\[w8, 0, vgx4\\], {z0\\.d-z3\\.d}, z0\\.d\n+[^:]+:\tc1707800 \tfmla\tza\\.d\\[w11, 0, vgx4\\], {z0\\.d-z3\\.d}, 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z0.d - z3.d }, z15.d\n+\tfmla\tza.d[w11, 2], { z23.d - z26.d }, z13.d\n+\n+\tfmla\tza.d[w8, 0], { z0.d - z1.d }, { z0.d - z1.d }\n+\tfmla\tza.d[w8, 0, vgx2], { z0.d - z1.d }, { z0.d - z1.d }\n+\tFMLA\tZA.d[W8, 0, VGx2], { Z0.d - Z1.d }, { Z0.d - Z1.d }\n+\tFMLA\tZA.D[W8, 0, VGX2], { Z0.D - Z1.D }, { Z0.D - Z1.D }\n+\tfmla\tza.d[w11, 0], { z0.d - z1.d }, { z0.d - z1.d }\n+\tfmla\tza.d[w8, 7], { z0.d - z1.d }, { z0.d - z1.d }\n+\tfmla\tza.d[w8, 0], { z30.d - z31.d }, { z0.d - z1.d }\n+\tfmla\tza.d[w8, 0], { z0.d - z1.d }, { z30.d - z31.d }\n+\tfmla\tza.d[w10, 1], { z22.d - z23.d }, { z18.d - z19.d }\n+\n+\tfmla\tza.d[w8, 0], { z0.d - z3.d }, { z0.d - z3.d }\n+\tfmla\tza.d[w8, 0, vgx4], { z0.d - z3.d }, { z0.d - z3.d }\n+\tFMLA\tZA.d[W8, 0, VGx4], { Z0.d - Z3.d }, { Z0.d - Z3.d }\n+\tFMLA\tZA.D[W8, 0, VGX4], { Z0.D - Z3.D }, { Z0.D - Z3.D }\n+\tfmla\tza.d[w11, 0], { z0.d - z3.d }, { z0.d - z3.d }\n+\tfmla\tza.d[w8, 7], { z0.d - z3.d }, { z0.d - z3.d }\n+\tfmla\tza.d[w8, 0], { z28.d - z31.d }, { z0.d - z3.d }\n+\tfmla\tza.d[w8, 0], { z0.d - z3.d }, { z28.d - z31.d }\n+\tfmla\tza.d[w11, 3], { z16.d - z19.d }, { z24.d - z27.d }\n+\n+\tfmls\tza.d[w8, 0], { z0.d - z1.d }, z0.d[0]\n+\tfmls\tza.d[w8, 0, vgx2], { z0.d - z1.d }, z0.d[0]\n+\tFMLS\tZA.d[W8, 0, VGx2], { Z0.d - Z1.d }, Z0.d[0]\n+\tfmls\tza.d[w11, 0], { z0.d - z1.d }, z0.d[0]\n+\tfmls\tza.d[w8, 7], { z0.d - z1.d }, z0.d[0]\n+\tfmls\tza.d[w8, 0], { z30.d - z31.d }, z0.d[0]\n+\tfmls\tza.d[w8, 0], { z0.d - z1.d }, z15.d[0]\n+\tfmls\tza.d[w8, 0], { z0.d - z1.d }, z0.d[1]\n+\tfmls\tza.d[w10, 2], { z6.d - z7.d }, z5.d[1]\n+\n+\tfmls\tza.d[w8, 0], { z0.d - z3.d }, z0.d[0]\n+\tfmls\tza.d[w8, 0, vgx4], { z0.d - z3.d }, z0.d[0]\n+\tFMLS\tZA.D[W8, 0, VGX4], { Z0.D - Z3.D }, Z0.D[0]\n+\tfmls\tza.d[w11, 0], { z0.d - z3.d }, z0.d[0]\n+\tfmls\tza.d[w8, 7], { z0.d - z3.d }, z0.d[0]\n+\tfmls\tza.d[w8, 0], { z28.d - z31.d }, z0.d[0]\n+\tfmls\tza.d[w8, 0], { z0.d - z3.d }, z15.d[0]\n+\tfmls\tza.d[w8, 0], { z0.d - z3.d }, z0.d[1]\n+\tfmls\tza.d[w9, 3], { z8.d - z11.d }, z14.d[1]\n+\n+\tfmls\tza.d[w8, 0], { z0.d - z1.d }, z0.d\n+\tfmls\tza.d[w8, 0, vgx2], { z0.d - z1.d }, z0.d\n+\tFMLS\tZA.d[W8, 0, VGx2], { Z0.d - Z1.d }, Z0.d\n+\tFMLS\tZA.D[W8, 0, VGX2], { Z0.D - Z1.D }, Z0.D\n+\tfmls\tza.d[w11, 0], { z0.d - z1.d }, z0.d\n+\tfmls\tza.d[w8, 7], { z0.d - z1.d }, z0.d\n+\tfmls\tza.d[w8, 0], { z30.d - z31.d }, z0.d\n+\tfmls\tza.d[w8, 0], { z31.d, z0.d }, z0.d\n+\tfmls\tza.d[w8, 0], { z31.d - z0.d }, z0.d\n+\tfmls\tza.d[w8, 0], { z0.d - z1.d }, z15.d\n+\tfmls\tza.d[w9, 5], { z9.d - z10.d }, z6.d\n+\n+\tfmls\tza.d[w8, 0], { z0.d - z3.d }, z0.d\n+\tfmls\tza.d[w8, 0, vgx4], { z0.d - z3.d }, z0.d\n+\tFMLS\tZA.d[W8, 0, VGx4], { Z0.d - Z3.d }, Z0.d\n+\tFMLS\tZA.D[W8, 0, VGX4], { Z0.D - Z3.D }, Z0.D\n+\tfmls\tza.d[w11, 0], { z0.d - z3.d }, z0.d\n+\tfmls\tza.d[w8, 7], { z0.d - z3.d }, z0.d\n+\tfmls\tza.d[w8, 0], { z28.d - z31.d }, z0.d\n+\tfmls\tza.d[w8, 0], { z31.d, z0.d, z1.d, z2.d }, z0.d\n+\tfmls\tza.d[w8, 0], { z31.d - z2.d }, z0.d\n+\tfmls\tza.d[w8, 0], { z0.d - z3.d }, z15.d\n+\tfmls\tza.d[w11, 2], { z23.d - z26.d }, z13.d\n+\n+\tfmls\tza.d[w8, 0], { z0.d - z1.d }, { z0.d - z1.d }\n+\tfmls\tza.d[w8, 0, vgx2], { z0.d - z1.d }, { z0.d - z1.d }\n+\tFMLS\tZA.d[W8, 0, VGx2], { Z0.d - Z1.d }, { Z0.d - Z1.d }\n+\tFMLS\tZA.D[W8, 0, VGX2], { Z0.D - Z1.D }, { Z0.D - Z1.D }\n+\tfmls\tza.d[w11, 0], { z0.d - z1.d }, { z0.d - z1.d }\n+\tfmls\tza.d[w8, 7], { z0.d - z1.d }, { z0.d - z1.d }\n+\tfmls\tza.d[w8, 0], { z30.d - z31.d }, { z0.d - z1.d }\n+\tfmls\tza.d[w8, 0], { z0.d - z1.d }, { z30.d - z31.d }\n+\tfmls\tza.d[w10, 1], { z22.d - z23.d }, { z18.d - z19.d }\n+\n+\tfmls\tza.d[w8, 0], { z0.d - z3.d }, { z0.d - z3.d }\n+\tfmls\tza.d[w8, 0, vgx4], { z0.d - z3.d }, { z0.d - z3.d }\n+\tFMLS\tZA.d[W8, 0, VGx4], { Z0.d - Z3.d }, { Z0.d - Z3.d }\n+\tFMLS\tZA.D[W8, 0, VGX4], { Z0.D - Z3.D }, { Z0.D - Z3.D }\n+\tfmls\tza.d[w11, 0], { z0.d - z3.d }, { z0.d - z3.d }\n+\tfmls\tza.d[w8, 7], { z0.d - z3.d }, { z0.d - z3.d }\n+\tfmls\tza.d[w8, 0], { z28.d - z31.d }, { z0.d - z3.d }\n+\tfmls\tza.d[w8, 0], { z0.d - z3.d }, { z28.d - z31.d }\n+\tfmls\tza.d[w11, 3], { z16.d - z19.d }, { z24.d - z27.d }\ndiff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h\nindex ff5367aedd7..8c7646a0ce3 100644\n--- a/include/opcode/aarch64.h\n+++ b/include/opcode/aarch64.h\n@@ -516,6 +516,8 @@ enum aarch64_opnd\n AARCH64_OPND_SME_ADDR_RI_U4xVL, /* SME [{, #, MUL VL}]. */\n AARCH64_OPND_SME_SM_ZA, /* SME {SM | ZA}. */\n AARCH64_OPND_SME_PnT_Wm_imm, /* SME .[, #]. */\n+ AARCH64_OPND_SME_Zm_INDEX1,\t /* Zn.T[index], bits [19:16,10]. */\n+ AARCH64_OPND_SME_Zm_INDEX2,\t /* Zn.T[index], bits [19:16,11:10]. */\n AARCH64_OPND_SME_Zn_INDEX1_16, /* Zn[index], bits [9:5] and [16:16]. */\n AARCH64_OPND_SME_Zn_INDEX2_15, /* Zn[index], bits [9:5] and [16:15]. */\n AARCH64_OPND_SME_Zn_INDEX2_16, /* Zn[index], bits [9:5] and [17:16]. */\ndiff --git a/opcodes/aarch64-asm-2.c b/opcodes/aarch64-asm-2.c\nindex 5dba041483c..b4ce19d8194 100644\n--- a/opcodes/aarch64-asm-2.c\n+++ b/opcodes/aarch64-asm-2.c\n@@ -685,7 +685,7 @@ aarch64_insert_operand (const aarch64_operand *self,\n case 33:\n case 34:\n case 35:\n- case 257:\n+ case 259:\n return aarch64_ins_reglane (self, info, code, inst, errors);\n case 36:\n return aarch64_ins_reglist (self, info, code, inst, errors);\n@@ -731,12 +731,12 @@ aarch64_insert_operand (const aarch64_operand *self,\n case 193:\n case 194:\n case 237:\n- case 251:\n- case 252:\n+ case 253:\n case 254:\n case 256:\n- case 261:\n- case 262:\n+ case 258:\n+ case 263:\n+ case 264:\n return aarch64_ins_imm (self, info, code, inst, errors);\n case 44:\n case 45:\n@@ -805,8 +805,8 @@ aarch64_insert_operand (const aarch64_operand *self,\n case 107:\n return aarch64_ins_prfop (self, info, code, inst, errors);\n case 108:\n- case 253:\n case 255:\n+ case 257:\n return aarch64_ins_none (self, info, code, inst, errors);\n case 109:\n return aarch64_ins_hint (self, info, code, inst, errors);\n@@ -925,6 +925,8 @@ aarch64_insert_operand (const aarch64_operand *self,\n case 248:\n case 249:\n case 250:\n+ case 251:\n+ case 252:\n return aarch64_ins_simple_index (self, info, code, inst, errors);\n case 239:\n case 240:\n@@ -936,9 +938,9 @@ aarch64_insert_operand (const aarch64_operand *self,\n return aarch64_ins_sme_sm_za (self, info, code, inst, errors);\n case 244:\n return aarch64_ins_sme_pred_reg_with_index (self, info, code, inst, errors);\n- case 258:\n- case 259:\n case 260:\n+ case 261:\n+ case 262:\n return aarch64_ins_x0_to_x30 (self, info, code, inst, errors);\n default: assert (0); abort ();\n }\ndiff --git a/opcodes/aarch64-dis-2.c b/opcodes/aarch64-dis-2.c\nindex 36e30f752b7..bfe2bc25e9d 100644\n--- a/opcodes/aarch64-dis-2.c\n+++ b/opcodes/aarch64-dis-2.c\n@@ -166,7 +166,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n x1000000x10x100xxxxxxxxxxxxxxxxx\n zero. */\n- return 2658;\n+ return 2670;\n }\n }\n }\n@@ -190,7 +190,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n x1000000x00x101xx0xxxxxxxxxxxxxx\n luti4. */\n- return 2527;\n+ return 2539;\n }\n else\n {\n@@ -198,7 +198,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n x1000000x00x101xx1xxxxxxxxxxxxxx\n luti4. */\n- return 2526;\n+ return 2538;\n }\n }\n else\n@@ -207,7 +207,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n x1000000x10x101xxxxxxxxxxxxxxxxx\n luti4. */\n- return 2525;\n+ return 2537;\n }\n }\n }\n@@ -226,7 +226,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n x1000000xx0x010xxxxx00xxxxxxxxxx\n mov. */\n- return 2534;\n+ return 2546;\n }\n else\n {\n@@ -234,7 +234,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n x1000000xx0x011xxxxx00xxxxxxxxxx\n mov. */\n- return 2530;\n+ return 2542;\n }\n }\n else\n@@ -247,7 +247,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n x1000000x00x11xxx0xx00xxxxxxxxxx\n luti2. */\n- return 2524;\n+ return 2536;\n }\n else\n {\n@@ -255,7 +255,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n x1000000x00x11xxx1xx00xxxxxxxxxx\n luti2. */\n- return 2523;\n+ return 2535;\n }\n }\n else\n@@ -268,7 +268,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n x1000000010x110xxxxx00xxxxxxxxxx\n movt. */\n- return 2545;\n+ return 2557;\n }\n else\n {\n@@ -276,7 +276,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n x1000000010x111xxxxx00xxxxxxxxxx\n movt. */\n- return 2544;\n+ return 2556;\n }\n }\n else\n@@ -285,7 +285,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n x1000000110x11xxxxxx00xxxxxxxxxx\n luti2. */\n- return 2522;\n+ return 2534;\n }\n }\n }\n@@ -298,7 +298,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n x1000000xx0xx10xxxxx10xxxxxxxxxx\n mov. */\n- return 2532;\n+ return 2544;\n }\n else\n {\n@@ -306,7 +306,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n x1000000xx0xx11xxxxx10xxxxxxxxxx\n mov. */\n- return 2528;\n+ return 2540;\n }\n }\n }\n@@ -320,7 +320,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n x1000000xx0xx10xxxxx01xxxxxxxxxx\n mov. */\n- return 2535;\n+ return 2547;\n }\n else\n {\n@@ -328,7 +328,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n x1000000xx0xx11xxxxx01xxxxxxxxxx\n mov. */\n- return 2531;\n+ return 2543;\n }\n }\n else\n@@ -339,7 +339,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n x1000000xx0xx10xxxxx11xxxxxxxxxx\n mov. */\n- return 2533;\n+ return 2545;\n }\n else\n {\n@@ -347,7 +347,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n x1000000xx0xx11xxxxx11xxxxxxxxxx\n mov. */\n- return 2529;\n+ return 2541;\n }\n }\n }\n@@ -374,7 +374,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n x0100000000xxxxx000xxxxxxxxxxxx0\n ld1b. */\n- return 2461;\n+ return 2473;\n }\n else\n {\n@@ -382,7 +382,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n x0100000000xxxxx100xxxxxxxxxxxx0\n ld1b. */\n- return 2462;\n+ return 2474;\n }\n }\n else\n@@ -393,7 +393,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n x0100000000xxxxx010xxxxxxxxxxxx0\n ld1w. */\n- return 2485;\n+ return 2497;\n }\n else\n {\n@@ -401,7 +401,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n x0100000000xxxxx110xxxxxxxxxxxx0\n ld1w. */\n- return 2486;\n+ return 2498;\n }\n }\n }\n@@ -415,7 +415,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n x0100000000xxxxx001xxxxxxxxxxxx0\n ld1h. */\n- return 2477;\n+ return 2489;\n }\n else\n {\n@@ -423,7 +423,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n x0100000000xxxxx101xxxxxxxxxxxx0\n ld1h. */\n- return 2478;\n+ return 2490;\n }\n }\n else\n@@ -434,7 +434,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n x0100000000xxxxx011xxxxxxxxxxxx0\n ld1d. */\n- return 2469;\n+ return 2481;\n }\n else\n {\n@@ -442,7 +442,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n x0100000000xxxxx111xxxxxxxxxxxx0\n ld1d. */\n- return 2470;\n+ return 2482;\n }\n }\n }\n@@ -459,7 +459,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n x0100000000xxxxx000xxxxxxxxxxxx1\n ldnt1b. */\n- return 2493;\n+ return 2505;\n }\n else\n {\n@@ -467,7 +467,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n x0100000000xxxxx100xxxxxxxxxxxx1\n ldnt1b. */\n- return 2494;\n+ return 2506;\n }\n }\n else\n@@ -478,7 +478,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n x0100000000xxxxx010xxxxxxxxxxxx1\n ldnt1w. */\n- return 2517;\n+ return 2529;\n }\n else\n {\n@@ -486,7 +486,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n x0100000000xxxxx110xxxxxxxxxxxx1\n ldnt1w. */\n- return 2518;\n+ return 2530;\n }\n }\n }\n@@ -500,7 +500,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n x0100000000xxxxx001xxxxxxxxxxxx1\n ldnt1h. */\n- return 2509;\n+ return 2521;\n }\n else\n {\n@@ -508,7 +508,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n x0100000000xxxxx101xxxxxxxxxxxx1\n ldnt1h. */\n- return 2510;\n+ return 2522;\n }\n }\n else\n@@ -519,7 +519,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n x0100000000xxxxx011xxxxxxxxxxxx1\n ldnt1d. */\n- return 2501;\n+ return 2513;\n }\n else\n {\n@@ -527,7 +527,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n x0100000000xxxxx111xxxxxxxxxxxx1\n ldnt1d. */\n- return 2502;\n+ return 2514;\n }\n }\n }\n@@ -591,7 +591,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n x0100000010xxxxx000xxxxxxxxxxxx0\n ld1b. */\n- return 2457;\n+ return 2469;\n }\n else\n {\n@@ -599,7 +599,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n x0100000010xxxxx100xxxxxxxxxxxx0\n ld1b. */\n- return 2458;\n+ return 2470;\n }\n }\n else\n@@ -610,7 +610,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n x0100000010xxxxx010xxxxxxxxxxxx0\n ld1w. */\n- return 2481;\n+ return 2493;\n }\n else\n {\n@@ -618,7 +618,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n x0100000010xxxxx110xxxxxxxxxxxx0\n ld1w. */\n- return 2482;\n+ return 2494;\n }\n }\n }\n@@ -632,7 +632,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n x0100000010xxxxx001xxxxxxxxxxxx0\n ld1h. */\n- return 2473;\n+ return 2485;\n }\n else\n {\n@@ -640,7 +640,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n x0100000010xxxxx101xxxxxxxxxxxx0\n ld1h. */\n- return 2474;\n+ return 2486;\n }\n }\n else\n@@ -651,7 +651,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n x0100000010xxxxx011xxxxxxxxxxxx0\n ld1d. */\n- return 2465;\n+ return 2477;\n }\n else\n {\n@@ -659,7 +659,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n x0100000010xxxxx111xxxxxxxxxxxx0\n ld1d. */\n- return 2466;\n+ return 2478;\n }\n }\n }\n@@ -676,7 +676,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n x0100000010xxxxx000xxxxxxxxxxxx1\n ldnt1b. */\n- return 2489;\n+ return 2501;\n }\n else\n {\n@@ -684,7 +684,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n x0100000010xxxxx100xxxxxxxxxxxx1\n ldnt1b. */\n- return 2490;\n+ return 2502;\n }\n }\n else\n@@ -695,7 +695,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n x0100000010xxxxx010xxxxxxxxxxxx1\n ldnt1w. */\n- return 2513;\n+ return 2525;\n }\n else\n {\n@@ -703,7 +703,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n x0100000010xxxxx110xxxxxxxxxxxx1\n ldnt1w. */\n- return 2514;\n+ return 2526;\n }\n }\n }\n@@ -717,7 +717,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n x0100000010xxxxx001xxxxxxxxxxxx1\n ldnt1h. */\n- return 2505;\n+ return 2517;\n }\n else\n {\n@@ -725,7 +725,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n x0100000010xxxxx101xxxxxxxxxxxx1\n ldnt1h. */\n- return 2506;\n+ return 2518;\n }\n }\n else\n@@ -736,7 +736,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n x0100000010xxxxx011xxxxxxxxxxxx1\n ldnt1d. */\n- return 2497;\n+ return 2509;\n }\n else\n {\n@@ -744,7 +744,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n x0100000010xxxxx111xxxxxxxxxxxx1\n ldnt1d. */\n- return 2498;\n+ return 2510;\n }\n }\n }\n@@ -812,7 +812,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n x0x00000001xxxxx000xxxxxxxxxxxx0\n st1b. */\n- return 2571;\n+ return 2583;\n }\n else\n {\n@@ -820,7 +820,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n x0x00000001xxxxx100xxxxxxxxxxxx0\n st1b. */\n- return 2572;\n+ return 2584;\n }\n }\n else\n@@ -831,7 +831,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n x0x00000001xxxxx010xxxxxxxxxxxx0\n st1w. */\n- return 2595;\n+ return 2607;\n }\n else\n {\n@@ -839,7 +839,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n x0x00000001xxxxx110xxxxxxxxxxxx0\n st1w. */\n- return 2596;\n+ return 2608;\n }\n }\n }\n@@ -853,7 +853,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n x0x00000001xxxxx001xxxxxxxxxxxx0\n st1h. */\n- return 2587;\n+ return 2599;\n }\n else\n {\n@@ -861,7 +861,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n x0x00000001xxxxx101xxxxxxxxxxxx0\n st1h. */\n- return 2588;\n+ return 2600;\n }\n }\n else\n@@ -872,7 +872,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n x0x00000001xxxxx011xxxxxxxxxxxx0\n st1d. */\n- return 2579;\n+ return 2591;\n }\n else\n {\n@@ -880,7 +880,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n x0x00000001xxxxx111xxxxxxxxxxxx0\n st1d. */\n- return 2580;\n+ return 2592;\n }\n }\n }\n@@ -897,7 +897,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n x0x00000001xxxxx000xxxxxxxxxxxx1\n stnt1b. */\n- return 2603;\n+ return 2615;\n }\n else\n {\n@@ -905,7 +905,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n x0x00000001xxxxx100xxxxxxxxxxxx1\n stnt1b. */\n- return 2604;\n+ return 2616;\n }\n }\n else\n@@ -916,7 +916,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n x0x00000001xxxxx010xxxxxxxxxxxx1\n stnt1w. */\n- return 2627;\n+ return 2639;\n }\n else\n {\n@@ -924,7 +924,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n x0x00000001xxxxx110xxxxxxxxxxxx1\n stnt1w. */\n- return 2628;\n+ return 2640;\n }\n }\n }\n@@ -938,7 +938,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n x0x00000001xxxxx001xxxxxxxxxxxx1\n stnt1h. */\n- return 2619;\n+ return 2631;\n }\n else\n {\n@@ -946,7 +946,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n x0x00000001xxxxx101xxxxxxxxxxxx1\n stnt1h. */\n- return 2620;\n+ return 2632;\n }\n }\n else\n@@ -957,7 +957,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n x0x00000001xxxxx011xxxxxxxxxxxx1\n stnt1d. */\n- return 2611;\n+ return 2623;\n }\n else\n {\n@@ -965,7 +965,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n x0x00000001xxxxx111xxxxxxxxxxxx1\n stnt1d. */\n- return 2612;\n+ return 2624;\n }\n }\n }\n@@ -1029,7 +1029,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n x0x00000011xxxxx000xxxxxxxxxxxx0\n st1b. */\n- return 2567;\n+ return 2579;\n }\n else\n {\n@@ -1037,7 +1037,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n x0x00000011xxxxx100xxxxxxxxxxxx0\n st1b. */\n- return 2568;\n+ return 2580;\n }\n }\n else\n@@ -1048,7 +1048,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n x0x00000011xxxxx010xxxxxxxxxxxx0\n st1w. */\n- return 2591;\n+ return 2603;\n }\n else\n {\n@@ -1056,7 +1056,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n x0x00000011xxxxx110xxxxxxxxxxxx0\n st1w. */\n- return 2592;\n+ return 2604;\n }\n }\n }\n@@ -1070,7 +1070,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n x0x00000011xxxxx001xxxxxxxxxxxx0\n st1h. */\n- return 2583;\n+ return 2595;\n }\n else\n {\n@@ -1078,7 +1078,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n x0x00000011xxxxx101xxxxxxxxxxxx0\n st1h. */\n- return 2584;\n+ return 2596;\n }\n }\n else\n@@ -1089,7 +1089,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n x0x00000011xxxxx011xxxxxxxxxxxx0\n st1d. */\n- return 2575;\n+ return 2587;\n }\n else\n {\n@@ -1097,7 +1097,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n x0x00000011xxxxx111xxxxxxxxxxxx0\n st1d. */\n- return 2576;\n+ return 2588;\n }\n }\n }\n@@ -1114,7 +1114,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n x0x00000011xxxxx000xxxxxxxxxxxx1\n stnt1b. */\n- return 2599;\n+ return 2611;\n }\n else\n {\n@@ -1122,7 +1122,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n x0x00000011xxxxx100xxxxxxxxxxxx1\n stnt1b. */\n- return 2600;\n+ return 2612;\n }\n }\n else\n@@ -1133,7 +1133,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n x0x00000011xxxxx010xxxxxxxxxxxx1\n stnt1w. */\n- return 2623;\n+ return 2635;\n }\n else\n {\n@@ -1141,7 +1141,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n x0x00000011xxxxx110xxxxxxxxxxxx1\n stnt1w. */\n- return 2624;\n+ return 2636;\n }\n }\n }\n@@ -1155,7 +1155,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n x0x00000011xxxxx001xxxxxxxxxxxx1\n stnt1h. */\n- return 2615;\n+ return 2627;\n }\n else\n {\n@@ -1163,7 +1163,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n x0x00000011xxxxx101xxxxxxxxxxxx1\n stnt1h. */\n- return 2616;\n+ return 2628;\n }\n }\n else\n@@ -1174,7 +1174,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n x0x00000011xxxxx011xxxxxxxxxxxx1\n stnt1d. */\n- return 2607;\n+ return 2619;\n }\n else\n {\n@@ -1182,7 +1182,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n x0x00000011xxxxx111xxxxxxxxxxxx1\n stnt1d. */\n- return 2608;\n+ return 2620;\n }\n }\n }\n@@ -1274,7 +1274,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n x0x00001000xxxxx000xxxxxxxxx0xxx\n ld1b. */\n- return 2463;\n+ return 2475;\n }\n else\n {\n@@ -1282,7 +1282,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n x0x00001000xxxxx010xxxxxxxxx0xxx\n ld1w. */\n- return 2487;\n+ return 2499;\n }\n }\n else\n@@ -1293,7 +1293,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n x0x00001000xxxxx001xxxxxxxxx0xxx\n ld1h. */\n- return 2479;\n+ return 2491;\n }\n else\n {\n@@ -1301,7 +1301,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n x0x00001000xxxxx011xxxxxxxxx0xxx\n ld1d. */\n- return 2471;\n+ return 2483;\n }\n }\n }\n@@ -1315,7 +1315,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n x0x00001000xxxxx000xxxxxxxxx1xxx\n ldnt1b. */\n- return 2495;\n+ return 2507;\n }\n else\n {\n@@ -1323,7 +1323,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n x0x00001000xxxxx010xxxxxxxxx1xxx\n ldnt1w. */\n- return 2519;\n+ return 2531;\n }\n }\n else\n@@ -1334,7 +1334,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n x0x00001000xxxxx001xxxxxxxxx1xxx\n ldnt1h. */\n- return 2511;\n+ return 2523;\n }\n else\n {\n@@ -1342,7 +1342,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n x0x00001000xxxxx011xxxxxxxxx1xxx\n ldnt1d. */\n- return 2503;\n+ return 2515;\n }\n }\n }\n@@ -1370,7 +1370,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n x0x00001000xxxxx100xxxxxxxxx0xxx\n ld1b. */\n- return 2464;\n+ return 2476;\n }\n else\n {\n@@ -1378,7 +1378,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n x1x00001000xxxxx100xxxxxxxxx0xxx\n ldr. */\n- return 2521;\n+ return 2533;\n }\n }\n else\n@@ -1387,7 +1387,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n xxx00001000xxxxx110xxxxxxxxx0xxx\n ld1w. */\n- return 2488;\n+ return 2500;\n }\n }\n else\n@@ -1398,7 +1398,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n xxx00001000xxxxx101xxxxxxxxx0xxx\n ld1h. */\n- return 2480;\n+ return 2492;\n }\n else\n {\n@@ -1406,7 +1406,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n xxx00001000xxxxx111xxxxxxxxx0xxx\n ld1d. */\n- return 2472;\n+ return 2484;\n }\n }\n }\n@@ -1420,7 +1420,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n xxx00001000xxxxx100xxxxxxxxx1xxx\n ldnt1b. */\n- return 2496;\n+ return 2508;\n }\n else\n {\n@@ -1428,7 +1428,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n xxx00001000xxxxx110xxxxxxxxx1xxx\n ldnt1w. */\n- return 2520;\n+ return 2532;\n }\n }\n else\n@@ -1439,7 +1439,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n xxx00001000xxxxx101xxxxxxxxx1xxx\n ldnt1h. */\n- return 2512;\n+ return 2524;\n }\n else\n {\n@@ -1447,7 +1447,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n xxx00001000xxxxx111xxxxxxxxx1xxx\n ldnt1d. */\n- return 2504;\n+ return 2516;\n }\n }\n }\n@@ -1501,85 +1501,129 @@ aarch64_opcode_lookup_1 (uint32_t word)\n {\n if (((word >> 3) & 0x1) == 0)\n {\n- if (((word >> 13) & 0x1) == 0)\n+ if (((word >> 15) & 0x1) == 0)\n {\n- if (((word >> 14) & 0x1) == 0)\n+ if (((word >> 20) & 0x1) == 0)\n {\n- if (((word >> 15) & 0x1) == 0)\n+ if (((word >> 13) & 0x1) == 0)\n {\n- /* 33222222222211111111110000000000\n- 10987654321098765432109876543210\n- xxx00001010xxxxx000xxxxxxxxx0xxx\n- ld1b. */\n- return 2459;\n+ if (((word >> 14) & 0x1) == 0)\n+ {\n+ /* 33222222222211111111110000000000\n+ 10987654321098765432109876543210\n+ xxx000010100xxxx000xxxxxxxxx0xxx\n+ ld1b. */\n+ return 2471;\n+ }\n+ else\n+ {\n+ /* 33222222222211111111110000000000\n+ 10987654321098765432109876543210\n+ xxx000010100xxxx010xxxxxxxxx0xxx\n+ ld1w. */\n+ return 2495;\n+ }\n }\n else\n {\n- /* 33222222222211111111110000000000\n- 10987654321098765432109876543210\n- xxx00001010xxxxx100xxxxxxxxx0xxx\n- ld1b. */\n- return 2460;\n+ if (((word >> 14) & 0x1) == 0)\n+ {\n+ /* 33222222222211111111110000000000\n+ 10987654321098765432109876543210\n+ xxx000010100xxxx001xxxxxxxxx0xxx\n+ ld1h. */\n+ return 2487;\n+ }\n+ else\n+ {\n+ /* 33222222222211111111110000000000\n+ 10987654321098765432109876543210\n+ xxx000010100xxxx011xxxxxxxxx0xxx\n+ ld1d. */\n+ return 2479;\n+ }\n }\n }\n else\n {\n- if (((word >> 15) & 0x1) == 0)\n+ if (((word >> 4) & 0x1) == 0)\n {\n /* 33222222222211111111110000000000\n 10987654321098765432109876543210\n- xxx00001010xxxxx010xxxxxxxxx0xxx\n- ld1w. */\n- return 2483;\n+ xxx000010101xxxx0xxxxxxxxxx00xxx\n+ fmla. */\n+ return 2455;\n }\n else\n {\n /* 33222222222211111111110000000000\n 10987654321098765432109876543210\n- xxx00001010xxxxx110xxxxxxxxx0xxx\n- ld1w. */\n- return 2484;\n+ xxx000010101xxxx0xxxxxxxxxx10xxx\n+ fmls. */\n+ return 2461;\n }\n }\n }\n else\n {\n- if (((word >> 14) & 0x1) == 0)\n+ if (((word >> 20) & 0x1) == 0)\n {\n- if (((word >> 15) & 0x1) == 0)\n+ if (((word >> 13) & 0x1) == 0)\n {\n- /* 33222222222211111111110000000000\n- 10987654321098765432109876543210\n- xxx00001010xxxxx001xxxxxxxxx0xxx\n- ld1h. */\n- return 2475;\n+ if (((word >> 14) & 0x1) == 0)\n+ {\n+ /* 33222222222211111111110000000000\n+ 10987654321098765432109876543210\n+ xxx000010100xxxx100xxxxxxxxx0xxx\n+ ld1b. */\n+ return 2472;\n+ }\n+ else\n+ {\n+ /* 33222222222211111111110000000000\n+ 10987654321098765432109876543210\n+ xxx000010100xxxx110xxxxxxxxx0xxx\n+ ld1w. */\n+ return 2496;\n+ }\n }\n else\n {\n- /* 33222222222211111111110000000000\n- 10987654321098765432109876543210\n- xxx00001010xxxxx101xxxxxxxxx0xxx\n- ld1h. */\n- return 2476;\n+ if (((word >> 14) & 0x1) == 0)\n+ {\n+ /* 33222222222211111111110000000000\n+ 10987654321098765432109876543210\n+ xxx000010100xxxx101xxxxxxxxx0xxx\n+ ld1h. */\n+ return 2488;\n+ }\n+ else\n+ {\n+ /* 33222222222211111111110000000000\n+ 10987654321098765432109876543210\n+ xxx000010100xxxx111xxxxxxxxx0xxx\n+ ld1d. */\n+ return 2480;\n+ }\n }\n }\n else\n {\n- if (((word >> 15) & 0x1) == 0)\n+ if (((word >> 4) & 0x1) == 0)\n {\n /* 33222222222211111111110000000000\n 10987654321098765432109876543210\n- xxx00001010xxxxx011xxxxxxxxx0xxx\n- ld1d. */\n- return 2467;\n+ xxx000010101xxxx1xxxxxxxxxx00xxx\n+ fmla. */\n+ return 2456;\n }\n else\n {\n /* 33222222222211111111110000000000\n 10987654321098765432109876543210\n- xxx00001010xxxxx111xxxxxxxxx0xxx\n- ld1d. */\n- return 2468;\n+ xxx000010101xxxx1xxxxxxxxxx10xxx\n+ fmls. */\n+ return 2462;\n }\n }\n }\n@@ -1596,7 +1640,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n xxx00001010xxxxx000xxxxxxxxx1xxx\n ldnt1b. */\n- return 2491;\n+ return 2503;\n }\n else\n {\n@@ -1604,7 +1648,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n xxx00001010xxxxx100xxxxxxxxx1xxx\n ldnt1b. */\n- return 2492;\n+ return 2504;\n }\n }\n else\n@@ -1615,7 +1659,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n xxx00001010xxxxx010xxxxxxxxx1xxx\n ldnt1w. */\n- return 2515;\n+ return 2527;\n }\n else\n {\n@@ -1623,7 +1667,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n xxx00001010xxxxx110xxxxxxxxx1xxx\n ldnt1w. */\n- return 2516;\n+ return 2528;\n }\n }\n }\n@@ -1637,7 +1681,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n xxx00001010xxxxx001xxxxxxxxx1xxx\n ldnt1h. */\n- return 2507;\n+ return 2519;\n }\n else\n {\n@@ -1645,7 +1689,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n xxx00001010xxxxx101xxxxxxxxx1xxx\n ldnt1h. */\n- return 2508;\n+ return 2520;\n }\n }\n else\n@@ -1656,7 +1700,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n xxx00001010xxxxx011xxxxxxxxx1xxx\n ldnt1d. */\n- return 2499;\n+ return 2511;\n }\n else\n {\n@@ -1664,7 +1708,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n xxx00001010xxxxx111xxxxxxxxx1xxx\n ldnt1d. */\n- return 2500;\n+ return 2512;\n }\n }\n }\n@@ -1674,30 +1718,74 @@ aarch64_opcode_lookup_1 (uint32_t word)\n {\n if (((word >> 4) & 0x1) == 0)\n {\n- if (((word >> 30) & 0x1) == 0)\n+ if (((word >> 29) & 0x1) == 0)\n {\n- /* 33222222222211111111110000000000\n- 10987654321098765432109876543210\n- x0x00001110xxxxxxxxxxxxxxxx0xxxx\n- usmopa. */\n- return 2385;\n+ if (((word >> 15) & 0x1) == 0)\n+ {\n+ /* 33222222222211111111110000000000\n+ 10987654321098765432109876543210\n+ xx000001110xxxxx0xxxxxxxxxx0xxxx\n+ fmla. */\n+ return 2671;\n+ }\n+ else\n+ {\n+ /* 33222222222211111111110000000000\n+ 10987654321098765432109876543210\n+ xx000001110xxxxx1xxxxxxxxxx0xxxx\n+ fmla. */\n+ return 2672;\n+ }\n }\n else\n {\n- /* 33222222222211111111110000000000\n- 10987654321098765432109876543210\n- x1x00001110xxxxxxxxxxxxxxxx0xxxx\n- ld1q. */\n- return 2397;\n+ if (((word >> 30) & 0x1) == 0)\n+ {\n+ /* 33222222222211111111110000000000\n+ 10987654321098765432109876543210\n+ x0100001110xxxxxxxxxxxxxxxx0xxxx\n+ usmopa. */\n+ return 2385;\n+ }\n+ else\n+ {\n+ /* 33222222222211111111110000000000\n+ 10987654321098765432109876543210\n+ x1100001110xxxxxxxxxxxxxxxx0xxxx\n+ ld1q. */\n+ return 2397;\n+ }\n }\n }\n else\n {\n- /* 33222222222211111111110000000000\n- 10987654321098765432109876543210\n- xxx00001110xxxxxxxxxxxxxxxx1xxxx\n- usmops. */\n- return 2387;\n+ if (((word >> 29) & 0x1) == 0)\n+ {\n+ if (((word >> 15) & 0x1) == 0)\n+ {\n+ /* 33222222222211111111110000000000\n+ 10987654321098765432109876543210\n+ xx000001110xxxxx0xxxxxxxxxx1xxxx\n+ fmls. */\n+ return 2673;\n+ }\n+ else\n+ {\n+ /* 33222222222211111111110000000000\n+ 10987654321098765432109876543210\n+ xx000001110xxxxx1xxxxxxxxxx1xxxx\n+ fmls. */\n+ return 2674;\n+ }\n+ }\n+ else\n+ {\n+ /* 33222222222211111111110000000000\n+ 10987654321098765432109876543210\n+ xx100001110xxxxxxxxxxxxxxxx1xxxx\n+ usmops. */\n+ return 2387;\n+ }\n }\n }\n }\n@@ -1733,21 +1821,65 @@ aarch64_opcode_lookup_1 (uint32_t word)\n {\n if (((word >> 4) & 0x1) == 0)\n {\n- if (((word >> 16) & 0x1) == 0)\n+ if (((word >> 10) & 0x1) == 0)\n {\n- /* 33222222222211111111110000000000\n- 10987654321098765432109876543210\n- x1000001xx1xxxx00xxxxxxxxxx00xxx\n- fadd. */\n- return 2437;\n+ if (((word >> 23) & 0x1) == 0)\n+ {\n+ if (((word >> 20) & 0x1) == 0)\n+ {\n+ /* 33222222222211111111110000000000\n+ 10987654321098765432109876543210\n+ x10000010x10xxxx0xxxx0xxxxx00xxx\n+ fmla. */\n+ return 2457;\n+ }\n+ else\n+ {\n+ /* 33222222222211111111110000000000\n+ 10987654321098765432109876543210\n+ x10000010x11xxxx0xxxx0xxxxx00xxx\n+ fmla. */\n+ return 2458;\n+ }\n+ }\n+ else\n+ {\n+ if (((word >> 16) & 0x1) == 0)\n+ {\n+ /* 33222222222211111111110000000000\n+ 10987654321098765432109876543210\n+ x10000011x1xxxx00xxxx0xxxxx00xxx\n+ fmla. */\n+ return 2459;\n+ }\n+ else\n+ {\n+ /* 33222222222211111111110000000000\n+ 10987654321098765432109876543210\n+ x10000011x1xxxx10xxxx0xxxxx00xxx\n+ fmla. */\n+ return 2460;\n+ }\n+ }\n }\n else\n {\n- /* 33222222222211111111110000000000\n- 10987654321098765432109876543210\n- x1000001xx1xxxx10xxxxxxxxxx00xxx\n- fadd. */\n- return 2438;\n+ if (((word >> 16) & 0x1) == 0)\n+ {\n+ /* 33222222222211111111110000000000\n+ 10987654321098765432109876543210\n+ x1000001xx1xxxx00xxxx1xxxxx00xxx\n+ fadd. */\n+ return 2437;\n+ }\n+ else\n+ {\n+ /* 33222222222211111111110000000000\n+ 10987654321098765432109876543210\n+ x1000001xx1xxxx10xxxx1xxxxx00xxx\n+ fadd. */\n+ return 2438;\n+ }\n }\n }\n else\n@@ -1818,21 +1950,65 @@ aarch64_opcode_lookup_1 (uint32_t word)\n {\n if (((word >> 4) & 0x1) == 0)\n {\n- if (((word >> 16) & 0x1) == 0)\n+ if (((word >> 10) & 0x1) == 0)\n {\n- /* 33222222222211111111110000000000\n- 10987654321098765432109876543210\n- x1000001xx1xxxx00xxxxxxxxxx01xxx\n- fsub. */\n- return 2455;\n+ if (((word >> 23) & 0x1) == 0)\n+ {\n+ if (((word >> 20) & 0x1) == 0)\n+ {\n+ /* 33222222222211111111110000000000\n+ 10987654321098765432109876543210\n+ x10000010x10xxxx0xxxx0xxxxx01xxx\n+ fmls. */\n+ return 2463;\n+ }\n+ else\n+ {\n+ /* 33222222222211111111110000000000\n+ 10987654321098765432109876543210\n+ x10000010x11xxxx0xxxx0xxxxx01xxx\n+ fmls. */\n+ return 2464;\n+ }\n+ }\n+ else\n+ {\n+ if (((word >> 16) & 0x1) == 0)\n+ {\n+ /* 33222222222211111111110000000000\n+ 10987654321098765432109876543210\n+ x10000011x1xxxx00xxxx0xxxxx01xxx\n+ fmls. */\n+ return 2465;\n+ }\n+ else\n+ {\n+ /* 33222222222211111111110000000000\n+ 10987654321098765432109876543210\n+ x10000011x1xxxx10xxxx0xxxxx01xxx\n+ fmls. */\n+ return 2466;\n+ }\n+ }\n }\n else\n {\n- /* 33222222222211111111110000000000\n- 10987654321098765432109876543210\n- x1000001xx1xxxx10xxxxxxxxxx01xxx\n- fsub. */\n- return 2456;\n+ if (((word >> 16) & 0x1) == 0)\n+ {\n+ /* 33222222222211111111110000000000\n+ 10987654321098765432109876543210\n+ x1000001xx1xxxx00xxxx1xxxxx01xxx\n+ fsub. */\n+ return 2467;\n+ }\n+ else\n+ {\n+ /* 33222222222211111111110000000000\n+ 10987654321098765432109876543210\n+ x1000001xx1xxxx10xxxx1xxxxx01xxx\n+ fsub. */\n+ return 2468;\n+ }\n }\n }\n else\n@@ -1847,7 +2023,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n x10000010x10xxxx0xxxx0xxxxx11xxx\n sub. */\n- return 2634;\n+ return 2646;\n }\n else\n {\n@@ -1855,7 +2031,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n x10000010x11xxxx0xxxx0xxxxx11xxx\n sub. */\n- return 2635;\n+ return 2647;\n }\n }\n else\n@@ -1866,7 +2042,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n x10000011x1xxxx00xxxx0xxxxx11xxx\n sub. */\n- return 2636;\n+ return 2648;\n }\n else\n {\n@@ -1874,7 +2050,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n x10000011x1xxxx10xxxx0xxxxx11xxx\n sub. */\n- return 2637;\n+ return 2649;\n }\n }\n }\n@@ -1886,7 +2062,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n x1000001xx1xxxx00xxxx1xxxxx11xxx\n sub. */\n- return 2632;\n+ return 2644;\n }\n else\n {\n@@ -1894,7 +2070,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n x1000001xx1xxxx10xxxx1xxxxx11xxx\n sub. */\n- return 2633;\n+ return 2645;\n }\n }\n }\n@@ -1914,7 +2090,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n x1000001xx1xxxx01x0xxxxxxx0xxxx0\n sel. */\n- return 2549;\n+ return 2561;\n }\n else\n {\n@@ -1922,7 +2098,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n x1000001xx1xxxx11x0xxxxxxx0xxxx0\n sel. */\n- return 2550;\n+ return 2562;\n }\n }\n else\n@@ -1939,7 +2115,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n x1000001xx1xxxxx1x1000x0xx0xxxx0\n smax. */\n- return 2551;\n+ return 2563;\n }\n else\n {\n@@ -1947,7 +2123,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n x1000001xx1xxxxx1x1100x0xx0xxxx0\n smax. */\n- return 2553;\n+ return 2565;\n }\n }\n else\n@@ -1958,7 +2134,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n x1000001xx1xxxxx1x1010x0xx0xxxx0\n smax. */\n- return 2552;\n+ return 2564;\n }\n else\n {\n@@ -1966,7 +2142,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n x1000001xx1xxxxx1x1110x0xx0xxxx0\n smax. */\n- return 2554;\n+ return 2566;\n }\n }\n }\n@@ -1980,7 +2156,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n x1000001xx1xxxxx1x1001x0xx0xxxx0\n sqdmulh. */\n- return 2559;\n+ return 2571;\n }\n else\n {\n@@ -1988,7 +2164,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n x1000001xx1xxxxx1x1101x0xx0xxxx0\n sqdmulh. */\n- return 2561;\n+ return 2573;\n }\n }\n else\n@@ -1999,7 +2175,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n x1000001xx1xxxxx1x1011x0xx0xxxx0\n sqdmulh. */\n- return 2560;\n+ return 2572;\n }\n else\n {\n@@ -2007,7 +2183,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n x1000001xx1xxxxx1x1111x0xx0xxxx0\n sqdmulh. */\n- return 2562;\n+ return 2574;\n }\n }\n }\n@@ -2091,7 +2267,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n x1000001xx1xxxxx1xx00x00xx1xxxx0\n smin. */\n- return 2555;\n+ return 2567;\n }\n else\n {\n@@ -2099,7 +2275,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n x1000001xx1xxxxx1xx10x00xx1xxxx0\n smin. */\n- return 2557;\n+ return 2569;\n }\n }\n else\n@@ -2110,7 +2286,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n x1000001xx1xxxxx1xx01x00xx1xxxx0\n smin. */\n- return 2556;\n+ return 2568;\n }\n else\n {\n@@ -2118,7 +2294,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n x1000001xx1xxxxx1xx11x00xx1xxxx0\n smin. */\n- return 2558;\n+ return 2570;\n }\n }\n }\n@@ -2132,7 +2308,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n x1000001xx1xxxxx1xx00x10xx1xxxx0\n srshl. */\n- return 2563;\n+ return 2575;\n }\n else\n {\n@@ -2140,7 +2316,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n x1000001xx1xxxxx1xx10x10xx1xxxx0\n srshl. */\n- return 2565;\n+ return 2577;\n }\n }\n else\n@@ -2151,7 +2327,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n x1000001xx1xxxxx1xx01x10xx1xxxx0\n srshl. */\n- return 2564;\n+ return 2576;\n }\n else\n {\n@@ -2159,7 +2335,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n x1000001xx1xxxxx1xx11x10xx1xxxx0\n srshl. */\n- return 2566;\n+ return 2578;\n }\n }\n }\n@@ -2221,7 +2397,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n x1000001xx1xxxxx1xx00xx0xx0xxxx1\n umax. */\n- return 2638;\n+ return 2650;\n }\n else\n {\n@@ -2229,7 +2405,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n x1000001xx1xxxxx1xx10xx0xx0xxxx1\n umax. */\n- return 2640;\n+ return 2652;\n }\n }\n else\n@@ -2240,7 +2416,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n x1000001xx1xxxxx1xx01xx0xx0xxxx1\n umax. */\n- return 2639;\n+ return 2651;\n }\n else\n {\n@@ -2248,7 +2424,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n x1000001xx1xxxxx1xx11xx0xx0xxxx1\n umax. */\n- return 2641;\n+ return 2653;\n }\n }\n }\n@@ -2308,7 +2484,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n x1000001xx1xxxxx1xx00x00xx1xxxx1\n umin. */\n- return 2642;\n+ return 2654;\n }\n else\n {\n@@ -2316,7 +2492,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n x1000001xx1xxxxx1xx10x00xx1xxxx1\n umin. */\n- return 2644;\n+ return 2656;\n }\n }\n else\n@@ -2327,7 +2503,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n x1000001xx1xxxxx1xx01x00xx1xxxx1\n umin. */\n- return 2643;\n+ return 2655;\n }\n else\n {\n@@ -2335,7 +2511,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n x1000001xx1xxxxx1xx11x00xx1xxxx1\n umin. */\n- return 2645;\n+ return 2657;\n }\n }\n }\n@@ -2349,7 +2525,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n x1000001xx1xxxxx1xx00x10xx1xxxx1\n urshl. */\n- return 2646;\n+ return 2658;\n }\n else\n {\n@@ -2357,7 +2533,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n x1000001xx1xxxxx1xx10x10xx1xxxx1\n urshl. */\n- return 2648;\n+ return 2660;\n }\n }\n else\n@@ -2368,7 +2544,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n x1000001xx1xxxxx1xx01x10xx1xxxx1\n urshl. */\n- return 2647;\n+ return 2659;\n }\n else\n {\n@@ -2376,7 +2552,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n x1000001xx1xxxxx1xx11x10xx1xxxx1\n urshl. */\n- return 2649;\n+ return 2661;\n }\n }\n }\n@@ -2447,7 +2623,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n x0100001001xxxxx000xxxxxxxxx0xxx\n st1b. */\n- return 2573;\n+ return 2585;\n }\n else\n {\n@@ -2455,7 +2631,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n x0100001001xxxxx010xxxxxxxxx0xxx\n st1w. */\n- return 2597;\n+ return 2609;\n }\n }\n else\n@@ -2466,7 +2642,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n x0100001001xxxxx001xxxxxxxxx0xxx\n st1h. */\n- return 2589;\n+ return 2601;\n }\n else\n {\n@@ -2474,7 +2650,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n x0100001001xxxxx011xxxxxxxxx0xxx\n st1d. */\n- return 2581;\n+ return 2593;\n }\n }\n }\n@@ -2488,7 +2664,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n x0100001001xxxxx000xxxxxxxxx1xxx\n stnt1b. */\n- return 2605;\n+ return 2617;\n }\n else\n {\n@@ -2496,7 +2672,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n x0100001001xxxxx010xxxxxxxxx1xxx\n stnt1w. */\n- return 2629;\n+ return 2641;\n }\n }\n else\n@@ -2507,7 +2683,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n x0100001001xxxxx001xxxxxxxxx1xxx\n stnt1h. */\n- return 2621;\n+ return 2633;\n }\n else\n {\n@@ -2515,7 +2691,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n x0100001001xxxxx011xxxxxxxxx1xxx\n stnt1d. */\n- return 2613;\n+ return 2625;\n }\n }\n }\n@@ -2543,7 +2719,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n x0100001001xxxxx100xxxxxxxxx0xxx\n st1b. */\n- return 2574;\n+ return 2586;\n }\n else\n {\n@@ -2551,7 +2727,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n x1100001001xxxxx100xxxxxxxxx0xxx\n str. */\n- return 2631;\n+ return 2643;\n }\n }\n else\n@@ -2560,7 +2736,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n xx100001001xxxxx110xxxxxxxxx0xxx\n st1w. */\n- return 2598;\n+ return 2610;\n }\n }\n else\n@@ -2571,7 +2747,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n xx100001001xxxxx101xxxxxxxxx0xxx\n st1h. */\n- return 2590;\n+ return 2602;\n }\n else\n {\n@@ -2579,7 +2755,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n xx100001001xxxxx111xxxxxxxxx0xxx\n st1d. */\n- return 2582;\n+ return 2594;\n }\n }\n }\n@@ -2593,7 +2769,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n xx100001001xxxxx100xxxxxxxxx1xxx\n stnt1b. */\n- return 2606;\n+ return 2618;\n }\n else\n {\n@@ -2601,7 +2777,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n xx100001001xxxxx110xxxxxxxxx1xxx\n stnt1w. */\n- return 2630;\n+ return 2642;\n }\n }\n else\n@@ -2612,7 +2788,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n xx100001001xxxxx101xxxxxxxxx1xxx\n stnt1h. */\n- return 2622;\n+ return 2634;\n }\n else\n {\n@@ -2620,7 +2796,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n xx100001001xxxxx111xxxxxxxxx1xxx\n stnt1d. */\n- return 2614;\n+ return 2626;\n }\n }\n }\n@@ -2662,7 +2838,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n xx100001011xxxxx000xxxxxxxxx0xxx\n st1b. */\n- return 2569;\n+ return 2581;\n }\n else\n {\n@@ -2670,7 +2846,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n xx100001011xxxxx100xxxxxxxxx0xxx\n st1b. */\n- return 2570;\n+ return 2582;\n }\n }\n else\n@@ -2681,7 +2857,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n xx100001011xxxxx010xxxxxxxxx0xxx\n st1w. */\n- return 2593;\n+ return 2605;\n }\n else\n {\n@@ -2689,7 +2865,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n xx100001011xxxxx110xxxxxxxxx0xxx\n st1w. */\n- return 2594;\n+ return 2606;\n }\n }\n }\n@@ -2703,7 +2879,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n xx100001011xxxxx001xxxxxxxxx0xxx\n st1h. */\n- return 2585;\n+ return 2597;\n }\n else\n {\n@@ -2711,7 +2887,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n xx100001011xxxxx101xxxxxxxxx0xxx\n st1h. */\n- return 2586;\n+ return 2598;\n }\n }\n else\n@@ -2722,7 +2898,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n xx100001011xxxxx011xxxxxxxxx0xxx\n st1d. */\n- return 2577;\n+ return 2589;\n }\n else\n {\n@@ -2730,7 +2906,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n xx100001011xxxxx111xxxxxxxxx0xxx\n st1d. */\n- return 2578;\n+ return 2590;\n }\n }\n }\n@@ -2747,7 +2923,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n xx100001011xxxxx000xxxxxxxxx1xxx\n stnt1b. */\n- return 2601;\n+ return 2613;\n }\n else\n {\n@@ -2755,7 +2931,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n xx100001011xxxxx100xxxxxxxxx1xxx\n stnt1b. */\n- return 2602;\n+ return 2614;\n }\n }\n else\n@@ -2766,7 +2942,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n xx100001011xxxxx010xxxxxxxxx1xxx\n stnt1w. */\n- return 2625;\n+ return 2637;\n }\n else\n {\n@@ -2774,7 +2950,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n xx100001011xxxxx110xxxxxxxxx1xxx\n stnt1w. */\n- return 2626;\n+ return 2638;\n }\n }\n }\n@@ -2788,7 +2964,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n xx100001011xxxxx001xxxxxxxxx1xxx\n stnt1h. */\n- return 2617;\n+ return 2629;\n }\n else\n {\n@@ -2796,7 +2972,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n xx100001011xxxxx101xxxxxxxxx1xxx\n stnt1h. */\n- return 2618;\n+ return 2630;\n }\n }\n else\n@@ -2807,7 +2983,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n xx100001011xxxxx011xxxxxxxxx1xxx\n stnt1d. */\n- return 2609;\n+ return 2621;\n }\n else\n {\n@@ -2815,7 +2991,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n xx100001011xxxxx111xxxxxxxxx1xxx\n stnt1d. */\n- return 2610;\n+ return 2622;\n }\n }\n }\n@@ -5217,7 +5393,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n 00011001000xxxxxxxxx00xxxxxxxxxx\n stlurb. */\n- return 2699;\n+ return 2715;\n }\n else\n {\n@@ -5225,7 +5401,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n 10011001000xxxxxxxxx00xxxxxxxxxx\n stlur. */\n- return 2707;\n+ return 2723;\n }\n }\n else\n@@ -5236,7 +5412,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n 01011001000xxxxxxxxx00xxxxxxxxxx\n stlurh. */\n- return 2703;\n+ return 2719;\n }\n else\n {\n@@ -5244,7 +5420,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n 11011001000xxxxxxxxx00xxxxxxxxxx\n stlur. */\n- return 2710;\n+ return 2726;\n }\n }\n }\n@@ -5282,7 +5458,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n xx011001000xxxxx0000x1xxxxxxxxxx\n cpyfp. */\n- return 2759;\n+ return 2775;\n }\n else\n {\n@@ -5290,7 +5466,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n xx011001000xxxxx1000x1xxxxxxxxxx\n cpyfprn. */\n- return 2765;\n+ return 2781;\n }\n }\n else\n@@ -5301,7 +5477,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n xx011001000xxxxx0100x1xxxxxxxxxx\n cpyfpwn. */\n- return 2762;\n+ return 2778;\n }\n else\n {\n@@ -5309,7 +5485,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n xx011001000xxxxx1100x1xxxxxxxxxx\n cpyfpn. */\n- return 2768;\n+ return 2784;\n }\n }\n }\n@@ -5323,7 +5499,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n xx011001000xxxxx0010x1xxxxxxxxxx\n cpyfprt. */\n- return 2783;\n+ return 2799;\n }\n else\n {\n@@ -5331,7 +5507,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n xx011001000xxxxx1010x1xxxxxxxxxx\n cpyfprtrn. */\n- return 2789;\n+ return 2805;\n }\n }\n else\n@@ -5342,7 +5518,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n xx011001000xxxxx0110x1xxxxxxxxxx\n cpyfprtwn. */\n- return 2786;\n+ return 2802;\n }\n else\n {\n@@ -5350,7 +5526,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n xx011001000xxxxx1110x1xxxxxxxxxx\n cpyfprtn. */\n- return 2792;\n+ return 2808;\n }\n }\n }\n@@ -5367,7 +5543,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n xx011001000xxxxx0001x1xxxxxxxxxx\n cpyfpwt. */\n- return 2771;\n+ return 2787;\n }\n else\n {\n@@ -5375,7 +5551,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n xx011001000xxxxx1001x1xxxxxxxxxx\n cpyfpwtrn. */\n- return 2777;\n+ return 2793;\n }\n }\n else\n@@ -5386,7 +5562,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n xx011001000xxxxx0101x1xxxxxxxxxx\n cpyfpwtwn. */\n- return 2774;\n+ return 2790;\n }\n else\n {\n@@ -5394,7 +5570,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n xx011001000xxxxx1101x1xxxxxxxxxx\n cpyfpwtn. */\n- return 2780;\n+ return 2796;\n }\n }\n }\n@@ -5408,7 +5584,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n xx011001000xxxxx0011x1xxxxxxxxxx\n cpyfpt. */\n- return 2795;\n+ return 2811;\n }\n else\n {\n@@ -5416,7 +5592,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n xx011001000xxxxx1011x1xxxxxxxxxx\n cpyfptrn. */\n- return 2801;\n+ return 2817;\n }\n }\n else\n@@ -5427,7 +5603,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n xx011001000xxxxx0111x1xxxxxxxxxx\n cpyfptwn. */\n- return 2798;\n+ return 2814;\n }\n else\n {\n@@ -5435,7 +5611,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n xx011001000xxxxx1111x1xxxxxxxxxx\n cpyfptn. */\n- return 2804;\n+ return 2820;\n }\n }\n }\n@@ -5500,7 +5676,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n 00011001010xxxxxxxxx00xxxxxxxxxx\n ldapurb. */\n- return 2700;\n+ return 2716;\n }\n else\n {\n@@ -5508,7 +5684,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n 10011001010xxxxxxxxx00xxxxxxxxxx\n ldapur. */\n- return 2708;\n+ return 2724;\n }\n }\n else\n@@ -5519,7 +5695,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n 01011001010xxxxxxxxx00xxxxxxxxxx\n ldapurh. */\n- return 2704;\n+ return 2720;\n }\n else\n {\n@@ -5527,7 +5703,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n 11011001010xxxxxxxxx00xxxxxxxxxx\n ldapur. */\n- return 2711;\n+ return 2727;\n }\n }\n }\n@@ -5565,7 +5741,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n xx011001010xxxxx0000x1xxxxxxxxxx\n cpyfm. */\n- return 2760;\n+ return 2776;\n }\n else\n {\n@@ -5573,7 +5749,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n xx011001010xxxxx1000x1xxxxxxxxxx\n cpyfmrn. */\n- return 2766;\n+ return 2782;\n }\n }\n else\n@@ -5584,7 +5760,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n xx011001010xxxxx0100x1xxxxxxxxxx\n cpyfmwn. */\n- return 2763;\n+ return 2779;\n }\n else\n {\n@@ -5592,7 +5768,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n xx011001010xxxxx1100x1xxxxxxxxxx\n cpyfmn. */\n- return 2769;\n+ return 2785;\n }\n }\n }\n@@ -5606,7 +5782,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n xx011001010xxxxx0010x1xxxxxxxxxx\n cpyfmrt. */\n- return 2784;\n+ return 2800;\n }\n else\n {\n@@ -5614,7 +5790,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n xx011001010xxxxx1010x1xxxxxxxxxx\n cpyfmrtrn. */\n- return 2790;\n+ return 2806;\n }\n }\n else\n@@ -5625,7 +5801,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n xx011001010xxxxx0110x1xxxxxxxxxx\n cpyfmrtwn. */\n- return 2787;\n+ return 2803;\n }\n else\n {\n@@ -5633,7 +5809,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n xx011001010xxxxx1110x1xxxxxxxxxx\n cpyfmrtn. */\n- return 2793;\n+ return 2809;\n }\n }\n }\n@@ -5650,7 +5826,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n xx011001010xxxxx0001x1xxxxxxxxxx\n cpyfmwt. */\n- return 2772;\n+ return 2788;\n }\n else\n {\n@@ -5658,7 +5834,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n xx011001010xxxxx1001x1xxxxxxxxxx\n cpyfmwtrn. */\n- return 2778;\n+ return 2794;\n }\n }\n else\n@@ -5669,7 +5845,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n xx011001010xxxxx0101x1xxxxxxxxxx\n cpyfmwtwn. */\n- return 2775;\n+ return 2791;\n }\n else\n {\n@@ -5677,7 +5853,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n xx011001010xxxxx1101x1xxxxxxxxxx\n cpyfmwtn. */\n- return 2781;\n+ return 2797;\n }\n }\n }\n@@ -5691,7 +5867,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n xx011001010xxxxx0011x1xxxxxxxxxx\n cpyfmt. */\n- return 2796;\n+ return 2812;\n }\n else\n {\n@@ -5699,7 +5875,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n xx011001010xxxxx1011x1xxxxxxxxxx\n cpyfmtrn. */\n- return 2802;\n+ return 2818;\n }\n }\n else\n@@ -5710,7 +5886,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n xx011001010xxxxx0111x1xxxxxxxxxx\n cpyfmtwn. */\n- return 2799;\n+ return 2815;\n }\n else\n {\n@@ -5718,7 +5894,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n xx011001010xxxxx1111x1xxxxxxxxxx\n cpyfmtn. */\n- return 2805;\n+ return 2821;\n }\n }\n }\n@@ -5786,7 +5962,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n 00011001100xxxxxxxxx00xxxxxxxxxx\n ldapursb. */\n- return 2702;\n+ return 2718;\n }\n else\n {\n@@ -5794,7 +5970,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n 10011001100xxxxxxxxx00xxxxxxxxxx\n ldapursw. */\n- return 2709;\n+ return 2725;\n }\n }\n else\n@@ -5803,7 +5979,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n x1011001100xxxxxxxxx00xxxxxxxxxx\n ldapursh. */\n- return 2706;\n+ return 2722;\n }\n }\n else\n@@ -5814,7 +5990,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n x0011001110xxxxxxxxx00xxxxxxxxxx\n ldapursb. */\n- return 2701;\n+ return 2717;\n }\n else\n {\n@@ -5822,7 +5998,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n x1011001110xxxxxxxxx00xxxxxxxxxx\n ldapursh. */\n- return 2705;\n+ return 2721;\n }\n }\n }\n@@ -5884,7 +6060,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n xx011001100xxxxx0000x1xxxxxxxxxx\n cpyfe. */\n- return 2761;\n+ return 2777;\n }\n else\n {\n@@ -5892,7 +6068,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n xx011001110xxxxx0000x1xxxxxxxxxx\n setp. */\n- return 2855;\n+ return 2871;\n }\n }\n else\n@@ -5903,7 +6079,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n xx011001100xxxxx1000x1xxxxxxxxxx\n cpyfern. */\n- return 2767;\n+ return 2783;\n }\n else\n {\n@@ -5911,7 +6087,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n xx011001110xxxxx1000x1xxxxxxxxxx\n sete. */\n- return 2857;\n+ return 2873;\n }\n }\n }\n@@ -5925,7 +6101,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n xx011001100xxxxx0100x1xxxxxxxxxx\n cpyfewn. */\n- return 2764;\n+ return 2780;\n }\n else\n {\n@@ -5933,7 +6109,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n xx011001110xxxxx0100x1xxxxxxxxxx\n setm. */\n- return 2856;\n+ return 2872;\n }\n }\n else\n@@ -5942,7 +6118,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n xx0110011x0xxxxx1100x1xxxxxxxxxx\n cpyfen. */\n- return 2770;\n+ return 2786;\n }\n }\n }\n@@ -5958,7 +6134,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n xx011001100xxxxx0010x1xxxxxxxxxx\n cpyfert. */\n- return 2785;\n+ return 2801;\n }\n else\n {\n@@ -5966,7 +6142,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n xx011001110xxxxx0010x1xxxxxxxxxx\n setpn. */\n- return 2861;\n+ return 2877;\n }\n }\n else\n@@ -5977,7 +6153,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n xx011001100xxxxx1010x1xxxxxxxxxx\n cpyfertrn. */\n- return 2791;\n+ return 2807;\n }\n else\n {\n@@ -5985,7 +6161,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n xx011001110xxxxx1010x1xxxxxxxxxx\n seten. */\n- return 2863;\n+ return 2879;\n }\n }\n }\n@@ -5999,7 +6175,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n xx011001100xxxxx0110x1xxxxxxxxxx\n cpyfertwn. */\n- return 2788;\n+ return 2804;\n }\n else\n {\n@@ -6007,7 +6183,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n xx011001110xxxxx0110x1xxxxxxxxxx\n setmn. */\n- return 2862;\n+ return 2878;\n }\n }\n else\n@@ -6016,7 +6192,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n xx0110011x0xxxxx1110x1xxxxxxxxxx\n cpyfertn. */\n- return 2794;\n+ return 2810;\n }\n }\n }\n@@ -6035,7 +6211,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n xx011001100xxxxx0001x1xxxxxxxxxx\n cpyfewt. */\n- return 2773;\n+ return 2789;\n }\n else\n {\n@@ -6043,7 +6219,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n xx011001110xxxxx0001x1xxxxxxxxxx\n setpt. */\n- return 2858;\n+ return 2874;\n }\n }\n else\n@@ -6054,7 +6230,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n xx011001100xxxxx1001x1xxxxxxxxxx\n cpyfewtrn. */\n- return 2779;\n+ return 2795;\n }\n else\n {\n@@ -6062,7 +6238,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n xx011001110xxxxx1001x1xxxxxxxxxx\n setet. */\n- return 2860;\n+ return 2876;\n }\n }\n }\n@@ -6076,7 +6252,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n xx011001100xxxxx0101x1xxxxxxxxxx\n cpyfewtwn. */\n- return 2776;\n+ return 2792;\n }\n else\n {\n@@ -6084,7 +6260,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n xx011001110xxxxx0101x1xxxxxxxxxx\n setmt. */\n- return 2859;\n+ return 2875;\n }\n }\n else\n@@ -6093,7 +6269,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n xx0110011x0xxxxx1101x1xxxxxxxxxx\n cpyfewtn. */\n- return 2782;\n+ return 2798;\n }\n }\n }\n@@ -6109,7 +6285,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n xx011001100xxxxx0011x1xxxxxxxxxx\n cpyfet. */\n- return 2797;\n+ return 2813;\n }\n else\n {\n@@ -6117,7 +6293,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n xx011001110xxxxx0011x1xxxxxxxxxx\n setptn. */\n- return 2864;\n+ return 2880;\n }\n }\n else\n@@ -6128,7 +6304,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n xx011001100xxxxx1011x1xxxxxxxxxx\n cpyfetrn. */\n- return 2803;\n+ return 2819;\n }\n else\n {\n@@ -6136,7 +6312,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n xx011001110xxxxx1011x1xxxxxxxxxx\n setetn. */\n- return 2866;\n+ return 2882;\n }\n }\n }\n@@ -6150,7 +6326,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n xx011001100xxxxx0111x1xxxxxxxxxx\n cpyfetwn. */\n- return 2800;\n+ return 2816;\n }\n else\n {\n@@ -6158,7 +6334,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n xx011001110xxxxx0111x1xxxxxxxxxx\n setmtn. */\n- return 2865;\n+ return 2881;\n }\n }\n else\n@@ -6167,7 +6343,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n xx0110011x0xxxxx1111x1xxxxxxxxxx\n cpyfetn. */\n- return 2806;\n+ return 2822;\n }\n }\n }\n@@ -6540,7 +6716,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n x1x11010110xxxx0x01000xxxxxxxxxx\n abs. */\n- return 2884;\n+ return 2900;\n }\n else\n {\n@@ -6558,7 +6734,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n xxx11010110xxxxxx11000xxxxxxxxxx\n smax. */\n- return 2887;\n+ return 2903;\n }\n }\n }\n@@ -6638,7 +6814,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n xxx11010x00xxxxxx0xx10xxxxxxxxxx\n setf8. */\n- return 2697;\n+ return 2713;\n }\n else\n {\n@@ -6646,7 +6822,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n xxx11010x00xxxxxx1xx10xxxxxxxxxx\n setf16. */\n- return 2698;\n+ return 2714;\n }\n }\n else\n@@ -6753,7 +6929,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n xxx11010110xxxxxx11010xxxxxxxxxx\n smin. */\n- return 2889;\n+ return 2905;\n }\n }\n }\n@@ -6769,7 +6945,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n xxx11010110xxxx0x00110xxxxxxxxxx\n ctz. */\n- return 2886;\n+ return 2902;\n }\n else\n {\n@@ -6814,7 +6990,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n xxx11010000xxxxxxxxx01xxxxxxxxxx\n rmif. */\n- return 2696;\n+ return 2712;\n }\n else\n {\n@@ -6908,7 +7084,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n xxx11010x10xxxxxx11001xxxxxxxxxx\n umax. */\n- return 2888;\n+ return 2904;\n }\n }\n }\n@@ -7038,7 +7214,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n xxx11010xx0xxxxxx11011xxxxxxxxxx\n umin. */\n- return 2890;\n+ return 2906;\n }\n }\n }\n@@ -7054,7 +7230,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n xxx11010xx0xxxx0x00111xxxxxxxxxx\n cnt. */\n- return 2885;\n+ return 2901;\n }\n else\n {\n@@ -7896,7 +8072,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n 010001x01x1xxxxx000110xxxxxxxxxx\n usdot. */\n- return 2716;\n+ return 2732;\n }\n }\n }\n@@ -7970,7 +8146,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n 010001x01x1xxxxx000111xxxxxxxxxx\n sudot. */\n- return 2717;\n+ return 2733;\n }\n }\n }\n@@ -10644,7 +10820,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n 010001x0xx0xxxxx011110xxxxxxxxxx\n usdot. */\n- return 2715;\n+ return 2731;\n }\n }\n }\n@@ -12348,7 +12524,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n 011001x0100xxx10101xxxxxxxxxxxxx\n bfcvtnt. */\n- return 2744;\n+ return 2760;\n }\n }\n else\n@@ -12591,7 +12767,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n 101001x00x1xxxxxx00xxxxxxxxxxxxx\n ld1rob. */\n- return 2720;\n+ return 2736;\n }\n else\n {\n@@ -12599,7 +12775,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n 101001x01x1xxxxxx00xxxxxxxxxxxxx\n ld1roh. */\n- return 2721;\n+ return 2737;\n }\n }\n else\n@@ -12831,7 +13007,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n 011001x0011xxxxx010xxxxxxxxxxxxx\n bfdot. */\n- return 2741;\n+ return 2757;\n }\n else\n {\n@@ -12852,7 +13028,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n 011001x0111xxxxx010xx0xxxxxxxxxx\n bfmlalb. */\n- return 2748;\n+ return 2764;\n }\n else\n {\n@@ -12860,7 +13036,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n 011001x0111xxxxx010xx1xxxxxxxxxx\n bfmlalt. */\n- return 2747;\n+ return 2763;\n }\n }\n else\n@@ -12915,7 +13091,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n x11001x0011xxxxx1x0xxxxxxxxxxxxx\n bfdot. */\n- return 2740;\n+ return 2756;\n }\n else\n {\n@@ -12927,7 +13103,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n 011001x0111xxxxx1x0xx0xxxxxxxxxx\n bfmlalb. */\n- return 2746;\n+ return 2762;\n }\n else\n {\n@@ -12935,7 +13111,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n 011001x0111xxxxx1x0xx1xxxxxxxxxx\n bfmlalt. */\n- return 2745;\n+ return 2761;\n }\n }\n else\n@@ -12986,7 +13162,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n 101001x00x1xxxxx001xxxxxxxxxxxxx\n ld1rob. */\n- return 2724;\n+ return 2740;\n }\n else\n {\n@@ -12994,7 +13170,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n 101001x01x1xxxxx001xxxxxxxxxxxxx\n ld1roh. */\n- return 2725;\n+ return 2741;\n }\n }\n else\n@@ -13353,7 +13529,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n 011001x0101xxxxx111xxxxxxxxxxxxx\n fmmla. */\n- return 2718;\n+ return 2734;\n }\n else\n {\n@@ -13386,7 +13562,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n 011001x0011xxxxx111xxxxxxxxxxxxx\n bfmmla. */\n- return 2742;\n+ return 2758;\n }\n else\n {\n@@ -13416,7 +13592,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n 011001x0111xxxxx111xxxxxxxxxxxxx\n fmmla. */\n- return 2719;\n+ return 2735;\n }\n else\n {\n@@ -13545,7 +13721,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n 000001x1101xxxxx000x00xxxxxxxxxx\n zip1. */\n- return 2728;\n+ return 2744;\n }\n else\n {\n@@ -13555,7 +13731,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n 000001x1101xxxxx000010xxxxxxxxxx\n uzp1. */\n- return 2730;\n+ return 2746;\n }\n else\n {\n@@ -13563,7 +13739,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n 000001x1101xxxxx000110xxxxxxxxxx\n trn1. */\n- return 2732;\n+ return 2748;\n }\n }\n }\n@@ -13575,7 +13751,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n 000001x1101xxxxx000x01xxxxxxxxxx\n zip2. */\n- return 2729;\n+ return 2745;\n }\n else\n {\n@@ -13585,7 +13761,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n 000001x1101xxxxx000011xxxxxxxxxx\n uzp2. */\n- return 2731;\n+ return 2747;\n }\n else\n {\n@@ -13593,7 +13769,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n 000001x1101xxxxx000111xxxxxxxxxx\n trn2. */\n- return 2733;\n+ return 2749;\n }\n }\n }\n@@ -14652,7 +14828,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n 010001x1000xxxxx100110xxxxxxxxxx\n smmla. */\n- return 2712;\n+ return 2728;\n }\n else\n {\n@@ -14660,7 +14836,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n 010001x1100xxxxx100110xxxxxxxxxx\n usmmla. */\n- return 2714;\n+ return 2730;\n }\n }\n else\n@@ -14669,7 +14845,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n 010001x1x10xxxxx100110xxxxxxxxxx\n ummla. */\n- return 2713;\n+ return 2729;\n }\n }\n }\n@@ -16165,7 +16341,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n 101001x10x1xxxxx000xxxxxxxxxxxxx\n ld1row. */\n- return 2722;\n+ return 2738;\n }\n else\n {\n@@ -16173,7 +16349,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n 101001x11x1xxxxx000xxxxxxxxxxxxx\n ld1rod. */\n- return 2723;\n+ return 2739;\n }\n }\n }\n@@ -16547,7 +16723,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n 101001x10x1xxxxx001xxxxxxxxxxxxx\n ld1row. */\n- return 2726;\n+ return 2742;\n }\n else\n {\n@@ -16555,7 +16731,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n 101001x11x1xxxxx001xxxxxxxxxxxxx\n ld1rod. */\n- return 2727;\n+ return 2743;\n }\n }\n }\n@@ -16916,7 +17092,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n 001001x1xx1xxxxx01x000xxxxx10xxx\n whilege. */\n- return 2650;\n+ return 2662;\n }\n else\n {\n@@ -16924,7 +17100,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n 001001x1xx1xxxxx01x000xxxxx11xxx\n whilegt. */\n- return 2651;\n+ return 2663;\n }\n }\n else\n@@ -16954,7 +17130,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n 001001x1xx1xxxxx011100xxxxx1xxxx\n pext. */\n- return 2546;\n+ return 2558;\n }\n }\n }\n@@ -16968,7 +17144,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n 001001x1xx1xxxxx01x010xxxxx10xxx\n whilehs. */\n- return 2653;\n+ return 2665;\n }\n else\n {\n@@ -16976,7 +17152,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n 001001x1xx1xxxxx01x010xxxxx11xxx\n whilehi. */\n- return 2652;\n+ return 2664;\n }\n }\n else\n@@ -17006,7 +17182,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n 001001x1xx1xxxxx011110xxxxx1xxxx\n ptrue. */\n- return 2548;\n+ return 2560;\n }\n }\n }\n@@ -17023,7 +17199,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n 001001x1xx1xxxxx01x001xxxxx10xxx\n whilelt. */\n- return 2657;\n+ return 2669;\n }\n else\n {\n@@ -17031,7 +17207,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n 001001x1xx1xxxxx01x001xxxxx11xxx\n whilele. */\n- return 2654;\n+ return 2666;\n }\n }\n else\n@@ -17061,7 +17237,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n 001001x1xx1xxxxx011101xxxxx1xxxx\n pext. */\n- return 2547;\n+ return 2559;\n }\n }\n }\n@@ -17075,7 +17251,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n 001001x1xx1xxxxx01x011xxxxx10xxx\n whilelo. */\n- return 2655;\n+ return 2667;\n }\n else\n {\n@@ -17083,7 +17259,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n 001001x1xx1xxxxx01x011xxxxx11xxx\n whilels. */\n- return 2656;\n+ return 2668;\n }\n }\n else\n@@ -18209,7 +18385,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n 011001x110001x10101xxxxxxxxxxxxx\n bfcvt. */\n- return 2743;\n+ return 2759;\n }\n }\n else\n@@ -19570,7 +19746,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n x1010100xxxxxxxxxxxxxxxxxxx1xxxx\n bc.c. */\n- return 2879;\n+ return 2895;\n }\n else\n {\n@@ -20150,7 +20326,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n xx01110100xxxxxx0000xxxxxxxxxxxx\n cpyp. */\n- return 2807;\n+ return 2823;\n }\n else\n {\n@@ -20158,7 +20334,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n xx01110110xxxxxx0000xxxxxxxxxxxx\n cpye. */\n- return 2809;\n+ return 2825;\n }\n }\n else\n@@ -20169,7 +20345,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n xx01110100xxxxxx1000xxxxxxxxxxxx\n cpyprn. */\n- return 2813;\n+ return 2829;\n }\n else\n {\n@@ -20177,7 +20353,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n xx01110110xxxxxx1000xxxxxxxxxxxx\n cpyern. */\n- return 2815;\n+ return 2831;\n }\n }\n }\n@@ -20191,7 +20367,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n xx01110100xxxxxx0100xxxxxxxxxxxx\n cpypwn. */\n- return 2810;\n+ return 2826;\n }\n else\n {\n@@ -20199,7 +20375,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n xx01110110xxxxxx0100xxxxxxxxxxxx\n cpyewn. */\n- return 2812;\n+ return 2828;\n }\n }\n else\n@@ -20210,7 +20386,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n xx01110100xxxxxx1100xxxxxxxxxxxx\n cpypn. */\n- return 2816;\n+ return 2832;\n }\n else\n {\n@@ -20218,7 +20394,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n xx01110110xxxxxx1100xxxxxxxxxxxx\n cpyen. */\n- return 2818;\n+ return 2834;\n }\n }\n }\n@@ -20235,7 +20411,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n xx01110100xxxxxx0010xxxxxxxxxxxx\n cpyprt. */\n- return 2831;\n+ return 2847;\n }\n else\n {\n@@ -20243,7 +20419,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n xx01110110xxxxxx0010xxxxxxxxxxxx\n cpyert. */\n- return 2833;\n+ return 2849;\n }\n }\n else\n@@ -20254,7 +20430,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n xx01110100xxxxxx1010xxxxxxxxxxxx\n cpyprtrn. */\n- return 2837;\n+ return 2853;\n }\n else\n {\n@@ -20262,7 +20438,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n xx01110110xxxxxx1010xxxxxxxxxxxx\n cpyertrn. */\n- return 2839;\n+ return 2855;\n }\n }\n }\n@@ -20276,7 +20452,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n xx01110100xxxxxx0110xxxxxxxxxxxx\n cpyprtwn. */\n- return 2834;\n+ return 2850;\n }\n else\n {\n@@ -20284,7 +20460,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n xx01110110xxxxxx0110xxxxxxxxxxxx\n cpyertwn. */\n- return 2836;\n+ return 2852;\n }\n }\n else\n@@ -20295,7 +20471,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n xx01110100xxxxxx1110xxxxxxxxxxxx\n cpyprtn. */\n- return 2840;\n+ return 2856;\n }\n else\n {\n@@ -20303,7 +20479,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n xx01110110xxxxxx1110xxxxxxxxxxxx\n cpyertn. */\n- return 2842;\n+ return 2858;\n }\n }\n }\n@@ -20323,7 +20499,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n xx01110100xxxxxx0001xxxxxxxxxxxx\n cpypwt. */\n- return 2819;\n+ return 2835;\n }\n else\n {\n@@ -20331,7 +20507,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n xx01110110xxxxxx0001xxxxxxxxxxxx\n cpyewt. */\n- return 2821;\n+ return 2837;\n }\n }\n else\n@@ -20342,7 +20518,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n xx01110100xxxxxx1001xxxxxxxxxxxx\n cpypwtrn. */\n- return 2825;\n+ return 2841;\n }\n else\n {\n@@ -20350,7 +20526,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n xx01110110xxxxxx1001xxxxxxxxxxxx\n cpyewtrn. */\n- return 2827;\n+ return 2843;\n }\n }\n }\n@@ -20364,7 +20540,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n xx01110100xxxxxx0101xxxxxxxxxxxx\n cpypwtwn. */\n- return 2822;\n+ return 2838;\n }\n else\n {\n@@ -20372,7 +20548,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n xx01110110xxxxxx0101xxxxxxxxxxxx\n cpyewtwn. */\n- return 2824;\n+ return 2840;\n }\n }\n else\n@@ -20383,7 +20559,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n xx01110100xxxxxx1101xxxxxxxxxxxx\n cpypwtn. */\n- return 2828;\n+ return 2844;\n }\n else\n {\n@@ -20391,7 +20567,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n xx01110110xxxxxx1101xxxxxxxxxxxx\n cpyewtn. */\n- return 2830;\n+ return 2846;\n }\n }\n }\n@@ -20408,7 +20584,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n xx01110100xxxxxx0011xxxxxxxxxxxx\n cpypt. */\n- return 2843;\n+ return 2859;\n }\n else\n {\n@@ -20416,7 +20592,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n xx01110110xxxxxx0011xxxxxxxxxxxx\n cpyet. */\n- return 2845;\n+ return 2861;\n }\n }\n else\n@@ -20427,7 +20603,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n xx01110100xxxxxx1011xxxxxxxxxxxx\n cpyptrn. */\n- return 2849;\n+ return 2865;\n }\n else\n {\n@@ -20435,7 +20611,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n xx01110110xxxxxx1011xxxxxxxxxxxx\n cpyetrn. */\n- return 2851;\n+ return 2867;\n }\n }\n }\n@@ -20449,7 +20625,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n xx01110100xxxxxx0111xxxxxxxxxxxx\n cpyptwn. */\n- return 2846;\n+ return 2862;\n }\n else\n {\n@@ -20457,7 +20633,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n xx01110110xxxxxx0111xxxxxxxxxxxx\n cpyetwn. */\n- return 2848;\n+ return 2864;\n }\n }\n else\n@@ -20468,7 +20644,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n xx01110100xxxxxx1111xxxxxxxxxxxx\n cpyptn. */\n- return 2852;\n+ return 2868;\n }\n else\n {\n@@ -20476,7 +20652,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n xx01110110xxxxxx1111xxxxxxxxxxxx\n cpyetn. */\n- return 2854;\n+ return 2870;\n }\n }\n }\n@@ -20510,7 +20686,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n xx01110101xxxxxx0000xxxxxxxxxxxx\n cpym. */\n- return 2808;\n+ return 2824;\n }\n else\n {\n@@ -20518,7 +20694,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n xx01110111xxxxxx0000xxxxxxxxxxxx\n setgp. */\n- return 2867;\n+ return 2883;\n }\n }\n else\n@@ -20529,7 +20705,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n xx01110101xxxxxx1000xxxxxxxxxxxx\n cpymrn. */\n- return 2814;\n+ return 2830;\n }\n else\n {\n@@ -20537,7 +20713,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n xx01110111xxxxxx1000xxxxxxxxxxxx\n setge. */\n- return 2869;\n+ return 2885;\n }\n }\n }\n@@ -20551,7 +20727,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n xx01110101xxxxxx0100xxxxxxxxxxxx\n cpymwn. */\n- return 2811;\n+ return 2827;\n }\n else\n {\n@@ -20559,7 +20735,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n xx01110111xxxxxx0100xxxxxxxxxxxx\n setgm. */\n- return 2868;\n+ return 2884;\n }\n }\n else\n@@ -20568,7 +20744,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n xx011101x1xxxxxx1100xxxxxxxxxxxx\n cpymn. */\n- return 2817;\n+ return 2833;\n }\n }\n }\n@@ -20584,7 +20760,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n xx01110101xxxxxx0010xxxxxxxxxxxx\n cpymrt. */\n- return 2832;\n+ return 2848;\n }\n else\n {\n@@ -20592,7 +20768,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n xx01110111xxxxxx0010xxxxxxxxxxxx\n setgpn. */\n- return 2873;\n+ return 2889;\n }\n }\n else\n@@ -20603,7 +20779,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n xx01110101xxxxxx1010xxxxxxxxxxxx\n cpymrtrn. */\n- return 2838;\n+ return 2854;\n }\n else\n {\n@@ -20611,7 +20787,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n xx01110111xxxxxx1010xxxxxxxxxxxx\n setgen. */\n- return 2875;\n+ return 2891;\n }\n }\n }\n@@ -20625,7 +20801,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n xx01110101xxxxxx0110xxxxxxxxxxxx\n cpymrtwn. */\n- return 2835;\n+ return 2851;\n }\n else\n {\n@@ -20633,7 +20809,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n xx01110111xxxxxx0110xxxxxxxxxxxx\n setgmn. */\n- return 2874;\n+ return 2890;\n }\n }\n else\n@@ -20642,7 +20818,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n xx011101x1xxxxxx1110xxxxxxxxxxxx\n cpymrtn. */\n- return 2841;\n+ return 2857;\n }\n }\n }\n@@ -20661,7 +20837,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n xx01110101xxxxxx0001xxxxxxxxxxxx\n cpymwt. */\n- return 2820;\n+ return 2836;\n }\n else\n {\n@@ -20669,7 +20845,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n xx01110111xxxxxx0001xxxxxxxxxxxx\n setgpt. */\n- return 2870;\n+ return 2886;\n }\n }\n else\n@@ -20680,7 +20856,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n xx01110101xxxxxx1001xxxxxxxxxxxx\n cpymwtrn. */\n- return 2826;\n+ return 2842;\n }\n else\n {\n@@ -20688,7 +20864,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n xx01110111xxxxxx1001xxxxxxxxxxxx\n setget. */\n- return 2872;\n+ return 2888;\n }\n }\n }\n@@ -20702,7 +20878,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n xx01110101xxxxxx0101xxxxxxxxxxxx\n cpymwtwn. */\n- return 2823;\n+ return 2839;\n }\n else\n {\n@@ -20710,7 +20886,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n xx01110111xxxxxx0101xxxxxxxxxxxx\n setgmt. */\n- return 2871;\n+ return 2887;\n }\n }\n else\n@@ -20719,7 +20895,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n xx011101x1xxxxxx1101xxxxxxxxxxxx\n cpymwtn. */\n- return 2829;\n+ return 2845;\n }\n }\n }\n@@ -20735,7 +20911,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n xx01110101xxxxxx0011xxxxxxxxxxxx\n cpymt. */\n- return 2844;\n+ return 2860;\n }\n else\n {\n@@ -20743,7 +20919,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n xx01110111xxxxxx0011xxxxxxxxxxxx\n setgptn. */\n- return 2876;\n+ return 2892;\n }\n }\n else\n@@ -20754,7 +20930,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n xx01110101xxxxxx1011xxxxxxxxxxxx\n cpymtrn. */\n- return 2850;\n+ return 2866;\n }\n else\n {\n@@ -20762,7 +20938,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n xx01110111xxxxxx1011xxxxxxxxxxxx\n setgetn. */\n- return 2878;\n+ return 2894;\n }\n }\n }\n@@ -20776,7 +20952,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n xx01110101xxxxxx0111xxxxxxxxxxxx\n cpymtwn. */\n- return 2847;\n+ return 2863;\n }\n else\n {\n@@ -20784,7 +20960,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n xx01110111xxxxxx0111xxxxxxxxxxxx\n setgmtn. */\n- return 2877;\n+ return 2893;\n }\n }\n else\n@@ -20793,7 +20969,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n xx011101x1xxxxxx1111xxxxxxxxxxxx\n cpymtn. */\n- return 2853;\n+ return 2869;\n }\n }\n }\n@@ -20960,7 +21136,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n 0x001110xx0xxxxx1x1001xxxxxxxxxx\n smmla. */\n- return 2734;\n+ return 2750;\n }\n }\n }\n@@ -20993,7 +21169,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n 0x001110xx0xxxxx1x0101xxxxxxxxxx\n sdot. */\n- return 2660;\n+ return 2676;\n }\n }\n else\n@@ -21067,7 +21243,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n 0x001110xx0xxxxx1x1011xxxxxxxxxx\n usmmla. */\n- return 2736;\n+ return 2752;\n }\n }\n }\n@@ -21100,7 +21276,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n 0x001110xx0xxxxx1x0111xxxxxxxxxx\n usdot. */\n- return 2737;\n+ return 2753;\n }\n }\n else\n@@ -21147,7 +21323,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n 1x001110000xxxxxxxxxxxxxxxxxxxxx\n eor3. */\n- return 2667;\n+ return 2683;\n }\n else\n {\n@@ -21155,7 +21331,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n 1x001110100xxxxxxxxxxxxxxxxxxxxx\n xar. */\n- return 2669;\n+ return 2685;\n }\n }\n else\n@@ -21166,7 +21342,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n 1x001110x10xxxxx0xxxxxxxxxxxxxxx\n sm3ss1. */\n- return 2671;\n+ return 2687;\n }\n else\n {\n@@ -21180,7 +21356,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n 1x001110010xxxxx1xxx00xxxxxxxxxx\n sm3tt1a. */\n- return 2672;\n+ return 2688;\n }\n else\n {\n@@ -21188,7 +21364,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n 1x001110110xxxxx1xxx00xxxxxxxxxx\n sha512su0. */\n- return 2665;\n+ return 2681;\n }\n }\n else\n@@ -21197,7 +21373,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n 1x001110x10xxxxx1xxx10xxxxxxxxxx\n sm3tt2a. */\n- return 2674;\n+ return 2690;\n }\n }\n else\n@@ -21210,7 +21386,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n 1x001110010xxxxx1xxx01xxxxxxxxxx\n sm3tt1b. */\n- return 2673;\n+ return 2689;\n }\n else\n {\n@@ -21218,7 +21394,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n 1x001110110xxxxx1xxx01xxxxxxxxxx\n sm4e. */\n- return 2678;\n+ return 2694;\n }\n }\n else\n@@ -21227,7 +21403,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n 1x001110x10xxxxx1xxx11xxxxxxxxxx\n sm3tt2b. */\n- return 2675;\n+ return 2691;\n }\n }\n }\n@@ -21408,7 +21584,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n xx101110xx0xxxxx100101xxxxxxxxxx\n udot. */\n- return 2659;\n+ return 2675;\n }\n }\n else\n@@ -21439,7 +21615,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n xx101110xx0xxxxx101x01xxxxxxxxxx\n ummla. */\n- return 2735;\n+ return 2751;\n }\n else\n {\n@@ -21458,7 +21634,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n xx101110xx0xxxxx1x1011xxxxxxxxxx\n bfmmla. */\n- return 2751;\n+ return 2767;\n }\n else\n {\n@@ -21468,7 +21644,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n xx1011100x0xxxxx1x1111xxxxxxxxxx\n bfdot. */\n- return 2749;\n+ return 2765;\n }\n else\n {\n@@ -21478,7 +21654,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n x01011101x0xxxxx1x1111xxxxxxxxxx\n bfmlalb. */\n- return 2756;\n+ return 2772;\n }\n else\n {\n@@ -21486,7 +21662,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n x11011101x0xxxxx1x1111xxxxxxxxxx\n bfmlalt. */\n- return 2755;\n+ return 2771;\n }\n }\n }\n@@ -22070,7 +22246,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n 000011101x1xxxx1011010xxxxxxxxxx\n bfcvtn. */\n- return 2752;\n+ return 2768;\n }\n else\n {\n@@ -22078,7 +22254,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n 010011101x1xxxx1011010xxxxxxxxxx\n bfcvtn2. */\n- return 2753;\n+ return 2769;\n }\n }\n }\n@@ -22396,7 +22572,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n 1x001110xx1xxxxx0xxxxxxxxxxxxxxx\n bcax. */\n- return 2670;\n+ return 2686;\n }\n }\n else\n@@ -23007,7 +23183,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n 11001110xx1xxxxx100000xxxxxxxxxx\n sha512h. */\n- return 2663;\n+ return 2679;\n }\n }\n }\n@@ -23059,7 +23235,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n 11001110xx1xxxxx110000xxxxxxxxxx\n sm3partw1. */\n- return 2676;\n+ return 2692;\n }\n }\n }\n@@ -23302,7 +23478,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n 1x001110xx1xxxxx100010xxxxxxxxxx\n sha512su1. */\n- return 2666;\n+ return 2682;\n }\n }\n else\n@@ -23378,7 +23554,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n 1x0011100x1xxxxx110010xxxxxxxxxx\n sm4ekey. */\n- return 2679;\n+ return 2695;\n }\n }\n else\n@@ -24204,7 +24380,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n 1x001110xx1xxxxx100001xxxxxxxxxx\n sha512h2. */\n- return 2664;\n+ return 2680;\n }\n }\n else\n@@ -24236,7 +24412,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n 1x0011100x1xxxxx110001xxxxxxxxxx\n sm3partw2. */\n- return 2677;\n+ return 2693;\n }\n }\n else\n@@ -24476,7 +24652,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n 1x001110xx1xxxxx100011xxxxxxxxxx\n rax1. */\n- return 2668;\n+ return 2684;\n }\n }\n else\n@@ -24508,7 +24684,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n x01011100x1xxxxx110011xxxxxxxxxx\n fmlal2. */\n- return 2682;\n+ return 2698;\n }\n else\n {\n@@ -24516,7 +24692,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n x11011100x1xxxxx110011xxxxxxxxxx\n fmlal2. */\n- return 2686;\n+ return 2702;\n }\n }\n }\n@@ -24538,7 +24714,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n x01011101x1xxxxx110011xxxxxxxxxx\n fmlsl2. */\n- return 2683;\n+ return 2699;\n }\n else\n {\n@@ -24546,7 +24722,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n x11011101x1xxxxx110011xxxxxxxxxx\n fmlsl2. */\n- return 2687;\n+ return 2703;\n }\n }\n }\n@@ -24585,7 +24761,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n x00011100x1xxxxx111011xxxxxxxxxx\n fmlal. */\n- return 2680;\n+ return 2696;\n }\n else\n {\n@@ -24593,7 +24769,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n x10011100x1xxxxx111011xxxxxxxxxx\n fmlal. */\n- return 2684;\n+ return 2700;\n }\n }\n else\n@@ -24615,7 +24791,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n x00011101x1xxxxx111011xxxxxxxxxx\n fmlsl. */\n- return 2681;\n+ return 2697;\n }\n else\n {\n@@ -24623,7 +24799,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n x10011101x1xxxxx111011xxxxxxxxxx\n fmlsl. */\n- return 2685;\n+ return 2701;\n }\n }\n else\n@@ -26431,7 +26607,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n x0001111xxxxxxxx0000x0xxxxxxxxxx\n fmlal. */\n- return 2688;\n+ return 2704;\n }\n else\n {\n@@ -26439,7 +26615,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n x1001111xxxxxxxx0000x0xxxxxxxxxx\n fmlal. */\n- return 2692;\n+ return 2708;\n }\n }\n else\n@@ -26461,7 +26637,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n x0001111xxxxxxxx0100x0xxxxxxxxxx\n fmlsl. */\n- return 2689;\n+ return 2705;\n }\n else\n {\n@@ -26469,7 +26645,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n x1001111xxxxxxxx0100x0xxxxxxxxxx\n fmlsl. */\n- return 2693;\n+ return 2709;\n }\n }\n else\n@@ -26975,7 +27151,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n x0101111xxxxxxxx1000x0xxxxxxxxxx\n fmlal2. */\n- return 2690;\n+ return 2706;\n }\n else\n {\n@@ -26983,7 +27159,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n x1101111xxxxxxxx1000x0xxxxxxxxxx\n fmlal2. */\n- return 2694;\n+ return 2710;\n }\n }\n }\n@@ -27005,7 +27181,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n x0101111xxxxxxxx1100x0xxxxxxxxxx\n fmlsl2. */\n- return 2691;\n+ return 2707;\n }\n else\n {\n@@ -27013,7 +27189,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n x1101111xxxxxxxx1100x0xxxxxxxxxx\n fmlsl2. */\n- return 2695;\n+ return 2711;\n }\n }\n }\n@@ -27069,7 +27245,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n xx001111xxxxxxxx1110x0xxxxxxxxxx\n sdot. */\n- return 2662;\n+ return 2678;\n }\n else\n {\n@@ -27077,7 +27253,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n xx101111xxxxxxxx1110x0xxxxxxxxxx\n udot. */\n- return 2661;\n+ return 2677;\n }\n }\n }\n@@ -27180,7 +27356,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n xx00111100xxxxxx1111x0xxxxxxxxxx\n sudot. */\n- return 2739;\n+ return 2755;\n }\n else\n {\n@@ -27188,7 +27364,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n xx00111110xxxxxx1111x0xxxxxxxxxx\n usdot. */\n- return 2738;\n+ return 2754;\n }\n }\n else\n@@ -27199,7 +27375,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n xx00111101xxxxxx1111x0xxxxxxxxxx\n bfdot. */\n- return 2750;\n+ return 2766;\n }\n else\n {\n@@ -27209,7 +27385,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n x000111111xxxxxx1111x0xxxxxxxxxx\n bfmlalb. */\n- return 2758;\n+ return 2774;\n }\n else\n {\n@@ -27217,7 +27393,7 @@ aarch64_opcode_lookup_1 (uint32_t word)\n 10987654321098765432109876543210\n x100111111xxxxxx1111x0xxxxxxxxxx\n bfmlalt. */\n- return 2757;\n+ return 2773;\n }\n }\n }\n@@ -27708,22 +27884,22 @@ aarch64_find_next_opcode (const aarch64_opcode *opcode)\n case 2391: return NULL;\t\t/* mova --> NULL. */\n case 2388: value = 2390; break;\t/* mov --> mova. */\n case 2390: return NULL;\t\t/* mova --> NULL. */\n- case 2534: value = 2542; break;\t/* mov --> mova. */\n- case 2542: return NULL;\t\t/* mova --> NULL. */\n- case 2530: value = 2538; break;\t/* mov --> mova. */\n- case 2538: return NULL;\t\t/* mova --> NULL. */\n- case 2532: value = 2540; break;\t/* mov --> mova. */\n- case 2540: return NULL;\t\t/* mova --> NULL. */\n- case 2528: value = 2536; break;\t/* mov --> mova. */\n- case 2536: return NULL;\t\t/* mova --> NULL. */\n- case 2535: value = 2543; break;\t/* mov --> mova. */\n- case 2543: return NULL;\t\t/* mova --> NULL. */\n- case 2531: value = 2539; break;\t/* mov --> mova. */\n- case 2539: return NULL;\t\t/* mova --> NULL. */\n- case 2533: value = 2541; break;\t/* mov --> mova. */\n- case 2541: return NULL;\t\t/* mova --> NULL. */\n- case 2529: value = 2537; break;\t/* mov --> mova. */\n- case 2537: return NULL;\t\t/* mova --> NULL. */\n+ case 2546: value = 2554; break;\t/* mov --> mova. */\n+ case 2554: return NULL;\t\t/* mova --> NULL. */\n+ case 2542: value = 2550; break;\t/* mov --> mova. */\n+ case 2550: return NULL;\t\t/* mova --> NULL. */\n+ case 2544: value = 2552; break;\t/* mov --> mova. */\n+ case 2552: return NULL;\t\t/* mova --> NULL. */\n+ case 2540: value = 2548; break;\t/* mov --> mova. */\n+ case 2548: return NULL;\t\t/* mova --> NULL. */\n+ case 2547: value = 2555; break;\t/* mov --> mova. */\n+ case 2555: return NULL;\t\t/* mova --> NULL. */\n+ case 2543: value = 2551; break;\t/* mov --> mova. */\n+ case 2551: return NULL;\t\t/* mova --> NULL. */\n+ case 2545: value = 2553; break;\t/* mov --> mova. */\n+ case 2553: return NULL;\t\t/* mova --> NULL. */\n+ case 2541: value = 2549; break;\t/* mov --> mova. */\n+ case 2549: return NULL;\t\t/* mova --> NULL. */\n case 2393: value = 2398; break;\t/* ld1b --> ld1b. */\n case 2398: return NULL;\t\t/* ld1b --> NULL. */\n case 2395: value = 2400; break;\t/* ld1w --> ld1w. */\n@@ -27745,11 +27921,11 @@ aarch64_find_next_opcode (const aarch64_opcode *opcode)\n case 2407: value = 2412; break;\t/* st1q --> st1q. */\n case 2412: return NULL;\t\t/* st1q --> NULL. */\n case 12: value = 19; break;\t/* add --> addg. */\n- case 19: value = 2880; break;\t/* addg --> smax. */\n- case 2880: value = 2881; break;\t/* smax --> umax. */\n- case 2881: value = 2882; break;\t/* umax --> smin. */\n- case 2882: value = 2883; break;\t/* smin --> umin. */\n- case 2883: return NULL;\t\t/* umin --> NULL. */\n+ case 19: value = 2896; break;\t/* addg --> smax. */\n+ case 2896: value = 2897; break;\t/* smax --> umax. */\n+ case 2897: value = 2898; break;\t/* umax --> smin. */\n+ case 2898: value = 2899; break;\t/* smin --> umin. */\n+ case 2899: return NULL;\t\t/* umin --> NULL. */\n case 16: value = 20; break;\t/* sub --> subg. */\n case 20: return NULL;\t\t/* subg --> NULL. */\n case 971: value = 975; break;\t/* stnp --> stp. */\n@@ -27907,8 +28083,8 @@ aarch64_find_next_opcode (const aarch64_opcode *opcode)\n case 824: return NULL;\t\t/* fsqrt --> NULL. */\n case 832: value = 833; break;\t/* frintz --> frintz. */\n case 833: return NULL;\t\t/* frintz --> NULL. */\n- case 825: value = 2754; break;\t/* fcvt --> bfcvt. */\n- case 2754: return NULL;\t\t/* bfcvt --> NULL. */\n+ case 825: value = 2770; break;\t/* fcvt --> bfcvt. */\n+ case 2770: return NULL;\t\t/* bfcvt --> NULL. */\n case 834: value = 835; break;\t/* frinta --> frinta. */\n case 835: return NULL;\t\t/* frinta --> NULL. */\n case 836: value = 837; break;\t/* frintx --> frintx. */\n@@ -28437,7 +28613,7 @@ aarch64_extract_operand (const aarch64_operand *self,\n case 33:\n case 34:\n case 35:\n- case 257:\n+ case 259:\n return aarch64_ext_reglane (self, info, code, inst, errors);\n case 36:\n return aarch64_ext_reglist (self, info, code, inst, errors);\n@@ -28484,12 +28660,12 @@ aarch64_extract_operand (const aarch64_operand *self,\n case 193:\n case 194:\n case 237:\n- case 251:\n- case 252:\n+ case 253:\n case 254:\n case 256:\n- case 261:\n- case 262:\n+ case 258:\n+ case 263:\n+ case 264:\n return aarch64_ext_imm (self, info, code, inst, errors);\n case 44:\n case 45:\n@@ -28560,8 +28736,8 @@ aarch64_extract_operand (const aarch64_operand *self,\n case 107:\n return aarch64_ext_prfop (self, info, code, inst, errors);\n case 108:\n- case 253:\n case 255:\n+ case 257:\n return aarch64_ext_none (self, info, code, inst, errors);\n case 109:\n return aarch64_ext_hint (self, info, code, inst, errors);\n@@ -28680,6 +28856,8 @@ aarch64_extract_operand (const aarch64_operand *self,\n case 248:\n case 249:\n case 250:\n+ case 251:\n+ case 252:\n return aarch64_ext_simple_index (self, info, code, inst, errors);\n case 239:\n case 240:\n@@ -28691,9 +28869,9 @@ aarch64_extract_operand (const aarch64_operand *self,\n return aarch64_ext_sme_sm_za (self, info, code, inst, errors);\n case 244:\n return aarch64_ext_sme_pred_reg_with_index (self, info, code, inst, errors);\n- case 258:\n- case 259:\n case 260:\n+ case 261:\n+ case 262:\n return aarch64_ext_x0_to_x30 (self, info, code, inst, errors);\n default: assert (0); abort ();\n }\ndiff --git a/opcodes/aarch64-opc-2.c b/opcodes/aarch64-opc-2.c\nindex 8658d07bf39..51415ceb033 100644\n--- a/opcodes/aarch64-opc-2.c\n+++ b/opcodes/aarch64-opc-2.c\n@@ -269,6 +269,8 @@ const struct aarch64_operand aarch64_operands[] =\n {AARCH64_OPND_CLASS_ADDRESS, \"SME_ADDR_RI_U4xVL\", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_imm4_0}, \"memory offset\"},\n {AARCH64_OPND_CLASS_ADDRESS, \"SME_SM_ZA\", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_CRm}, \"streaming mode\"},\n {AARCH64_OPND_CLASS_SVE_REG, \"SME_PnT_Wm_imm\", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Rm,FLD_SVE_Pn,FLD_SME_i1,FLD_SME_tszh,FLD_SME_tszl}, \"Source scalable predicate register with index \"},\n+ {AARCH64_OPND_CLASS_SVE_REG, \"SME_Zm_INDEX1\", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Zm, FLD_imm1_10}, \"an indexed SVE vector register\"},\n+ {AARCH64_OPND_CLASS_SVE_REG, \"SME_Zm_INDEX2\", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Zm, FLD_imm2_10}, \"an indexed SVE vector register\"},\n {AARCH64_OPND_CLASS_SVE_REG, \"SME_Zn_INDEX1_16\", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn, FLD_imm1_16}, \"an indexed SVE vector register\"},\n {AARCH64_OPND_CLASS_SVE_REG, \"SME_Zn_INDEX2_15\", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn, FLD_imm2_15}, \"an indexed SVE vector register\"},\n {AARCH64_OPND_CLASS_SVE_REG, \"SME_Zn_INDEX2_16\", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn, FLD_imm2_16}, \"an indexed SVE vector register\"},\ndiff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c\nindex d9cc0544e82..cd37f8ac910 100644\n--- a/opcodes/aarch64-opc.c\n+++ b/opcodes/aarch64-opc.c\n@@ -320,8 +320,10 @@ const aarch64_field fields[] =\n { 5, 5 },\t/* defgh: d:e:f:g:h bits in AdvSIMD modified immediate. */\n { 21, 2 },\t/* hw: in move wide constant instructions. */\n { 8, 1 },\t/* imm1_8: general immediate in bits [8]. */\n+ { 10, 1 },\t/* imm1_10: general immediate in bits [10]. */\n { 16, 1 },\t/* imm1_16: general immediate in bits [16]. */\n { 8, 2 },\t/* imm2_8: general immediate in bits [9:8]. */\n+ { 10, 2 }, /* imm2_10: 2-bit immediate, bits [11:10] */\n { 15, 2 }, /* imm2_15: 2-bit immediate, bits [16:15] */\n { 16, 2 }, /* imm2_16: 2-bit immediate, bits [17:16] */\n { 0, 3 },\t/* imm3_0: general immediate in bits [2:0]. */\n@@ -1765,6 +1767,14 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx,\n \t return 0;\n \t break;\n \n+\tcase AARCH64_OPND_SME_Zm_INDEX1:\n+\tcase AARCH64_OPND_SME_Zm_INDEX2:\n+\t size = get_operand_fields_width (get_operand_from_code (type)) - 4;\n+\t if (!check_reglane (opnd, mismatch_detail, idx, \"z\", 0, 15,\n+\t\t\t 0, (1 << size) - 1))\n+\t return 0;\n+\t break;\n+\n \tcase AARCH64_OPND_SME_Zm:\n \t if (opnd->reg.regno > 15)\n \t {\n@@ -3926,6 +3936,8 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc,\n case AARCH64_OPND_SVE_Zm4_11_INDEX:\n case AARCH64_OPND_SVE_Zm4_INDEX:\n case AARCH64_OPND_SVE_Zn_INDEX:\n+ case AARCH64_OPND_SME_Zm_INDEX1:\n+ case AARCH64_OPND_SME_Zm_INDEX2:\n case AARCH64_OPND_SME_Zn_INDEX1_16:\n case AARCH64_OPND_SME_Zn_INDEX2_15:\n case AARCH64_OPND_SME_Zn_INDEX2_16:\ndiff --git a/opcodes/aarch64-opc.h b/opcodes/aarch64-opc.h\nindex 1284dd47d4d..b0084257a94 100644\n--- a/opcodes/aarch64-opc.h\n+++ b/opcodes/aarch64-opc.h\n@@ -141,8 +141,10 @@ enum aarch64_field_kind\n FLD_defgh,\n FLD_hw,\n FLD_imm1_8,\n+ FLD_imm1_10,\n FLD_imm1_16,\n FLD_imm2_8,\n+ FLD_imm2_10,\n FLD_imm2_15,\n FLD_imm2_16,\n FLD_imm3_0,\ndiff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h\nindex 9bcec954d53..434b76c010c 100644\n--- a/opcodes/aarch64-tbl.h\n+++ b/opcodes/aarch64-tbl.h\n@@ -2509,6 +2509,8 @@ static const aarch64_feature_set aarch64_feature_sme_i16i64 =\n static const aarch64_feature_set aarch64_feature_sme2 =\n AARCH64_FEATURE (AARCH64_FEATURE_SVE2 | AARCH64_FEATURE_SME\n \t\t | AARCH64_FEATURE_SME2, 0);\n+static const aarch64_feature_set aarch64_feature_sme2_f64f64 =\n+ AARCH64_FEATURE (AARCH64_FEATURE_SME2 | AARCH64_FEATURE_SME_F64F64, 0);\n static const aarch64_feature_set aarch64_feature_v8_6 =\n AARCH64_FEATURE (AARCH64_FEATURE_V8_6, 0);\n static const aarch64_feature_set aarch64_feature_v8_7 =\n@@ -2578,6 +2580,7 @@ static const aarch64_feature_set aarch64_feature_cssc =\n #define SME_F64F64\t&aarch64_feature_sme_f64f64\n #define SME_I16I64\t&aarch64_feature_sme_i16i64\n #define SME2\t\t&aarch64_feature_sme2\n+#define SME2_F64F64\t&aarch64_feature_sme2_f64f64\n #define ARMV8_6\t\t&aarch64_feature_v8_6\n #define ARMV8_6_SVE\t\t&aarch64_feature_v8_6\n #define BFLOAT16_SVE\t&aarch64_feature_bfloat16_sve\n@@ -2692,6 +2695,9 @@ static const aarch64_feature_set aarch64_feature_cssc =\n #define SME2_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \\\n { NAME, OPCODE, MASK, CLASS, OP, SME2, OPS, QUALS, \\\n F_STRICT | FLAGS, 0, TIED, NULL }\n+#define SME2_F64F64_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \\\n+ { NAME, OPCODE, MASK, CLASS, OP, SME2_F64F64, OPS, QUALS, \\\n+ F_STRICT | FLAGS, 0, TIED, NULL }\n #define SVE2BITPERM_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \\\n { NAME, OPCODE, MASK, CLASS, OP, SVE2_BITPERM, OPS, QUALS, \\\n FLAGS | F_STRICT, 0, TIED, NULL }\n@@ -5352,6 +5358,18 @@ const struct aarch64_opcode aarch64_opcode_table[] =\n SME2_INSN (\"fminnm\", 0xc120a921, 0xff30ffe3, sme_size_22_hsd, 0, OP3 (SME_Zdnx4, SME_Zdnx4, SME_Zm), OP_SVE_VVV_HSD, 0, 1),\n SME2_INSN (\"fminnm\", 0xc120b121, 0xff21ffe1, sme_size_22_hsd, 0, OP3 (SME_Zdnx2, SME_Zdnx2, SME_Zmx2), OP_SVE_VVV_HSD, 0, 1),\n SME2_INSN (\"fminnm\", 0xc120b921, 0xff23ffe3, sme_size_22_hsd, 0, OP3 (SME_Zdnx4, SME_Zdnx4, SME_Zmx4), OP_SVE_VVV_HSD, 0, 1),\n+ SME2_INSN (\"fmla\", 0xc1500000, 0xfff09038, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx2, SME_Zm_INDEX2), OP_SVE_SSS, F_OD (2), 0),\n+ SME2_INSN (\"fmla\", 0xc1508000, 0xfff09078, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx4, SME_Zm_INDEX2), OP_SVE_SSS, F_OD (4), 0),\n+ SME2_INSN (\"fmla\", 0xc1201800, 0xffb09c18, sme_fp_sd, 0, OP3 (SME_ZA_array_off3_0, SVE_ZnxN, SME_Zm), OP_SVE_VVV_SD, F_OD (2), 0),\n+ SME2_INSN (\"fmla\", 0xc1301800, 0xffb09c18, sme_fp_sd, 0, OP3 (SME_ZA_array_off3_0, SVE_ZnxN, SME_Zm), OP_SVE_VVV_SD, F_OD (4), 0),\n+ SME2_INSN (\"fmla\", 0xc1a01800, 0xffa19c38, sme_fp_sd, 0, OP3 (SME_ZA_array_off3_0, SME_Znx2, SME_Zmx2), OP_SVE_VVV_SD, F_OD (2), 0),\n+ SME2_INSN (\"fmla\", 0xc1a11800, 0xffa39c78, sme_fp_sd, 0, OP3 (SME_ZA_array_off3_0, SME_Znx4, SME_Zmx4), OP_SVE_VVV_SD, F_OD (4), 0),\n+ SME2_INSN (\"fmls\", 0xc1500010, 0xfff09038, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx2, SME_Zm_INDEX2), OP_SVE_SSS, F_OD (2), 0),\n+ SME2_INSN (\"fmls\", 0xc1508010, 0xfff09078, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx4, SME_Zm_INDEX2), OP_SVE_SSS, F_OD (4), 0),\n+ SME2_INSN (\"fmls\", 0xc1201808, 0xffb09c18, sme_fp_sd, 0, OP3 (SME_ZA_array_off3_0, SVE_ZnxN, SME_Zm), OP_SVE_VVV_SD, F_OD (2), 0),\n+ SME2_INSN (\"fmls\", 0xc1301808, 0xffb09c18, sme_fp_sd, 0, OP3 (SME_ZA_array_off3_0, SVE_ZnxN, SME_Zm), OP_SVE_VVV_SD, F_OD (4), 0),\n+ SME2_INSN (\"fmls\", 0xc1a01808, 0xffa19c38, sme_fp_sd, 0, OP3 (SME_ZA_array_off3_0, SME_Znx2, SME_Zmx2), OP_SVE_VVV_SD, F_OD (2), 0),\n+ SME2_INSN (\"fmls\", 0xc1a11808, 0xffa39c78, sme_fp_sd, 0, OP3 (SME_ZA_array_off3_0, SME_Znx4, SME_Zmx4), OP_SVE_VVV_SD, F_OD (4), 0),\n SME2_INSN (\"fsub\", 0xc1a01c08, 0xffbf9c38, sme_fp_sd, 0, OP2 (SME_ZA_array_off3_0, SME_Znx2), OP_SVE_VVV_SD, F_OD (2), 0),\n SME2_INSN (\"fsub\", 0xc1a11c08, 0xffbf9c78, sme_fp_sd, 0, OP2 (SME_ZA_array_off3_0, SME_Znx4), OP_SVE_VVV_SD, F_OD (4), 0),\n SME2_INSN (\"ld1b\", 0xa0400000, 0xfff0e001, sve_misc, 0, OP3 (SME_Zdnx2, SME_PNg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_BZU, 0, 0),\n@@ -5557,6 +5575,12 @@ const struct aarch64_opcode aarch64_opcode_table[] =\n SME2_INSN (\"whilelt\", 0x25204410, 0xff20dc18, sme_size_22, 0, OP4 (SME_PNd3, Rn, Rm, SME_VLxN_13), OP_SVE_VXXU_BHSD, 0, 0),\n SME2_INSN (\"zero\", 0xc0480001, 0xffffffff, sme_misc, 0, OP1 (SME_ZT0_LIST), {}, 0, 0),\n \n+ /* SME2 F64F64 instructions. */\n+ SME2_F64F64_INSN (\"fmla\", 0xc1d00000, 0xfff09838, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx2, SME_Zm_INDEX1), OP_SVE_DDD, F_OD (2), 0),\n+ SME2_F64F64_INSN (\"fmla\", 0xc1d08000, 0xfff09878, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx4, SME_Zm_INDEX1), OP_SVE_DDD, F_OD (4), 0),\n+ SME2_F64F64_INSN (\"fmls\", 0xc1d00010, 0xfff09838, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx2, SME_Zm_INDEX1), OP_SVE_DDD, F_OD (2), 0),\n+ SME2_F64F64_INSN (\"fmls\", 0xc1d08010, 0xfff09878, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx4, SME_Zm_INDEX1), OP_SVE_DDD, F_OD (4), 0),\n+\n /* SIMD Dot Product (optional in v8.2-A). */\n DOT_INSN (\"udot\", 0x2e009400, 0xbf20fc00, dotproduct, OP3 (Vd, Vn, Vm), QL_V3DOT, F_SIZEQ),\n DOT_INSN (\"sdot\", 0xe009400, 0xbf20fc00, dotproduct, OP3 (Vd, Vn, Vm), QL_V3DOT, F_SIZEQ),\n@@ -6268,6 +6292,10 @@ const struct aarch64_opcode aarch64_opcode_table[] =\n 100 400k 100 400k 100 150 6164k 2307 --:--:-- --:--:-- --:--:-- 6166k Y(SVE_REG, sme_pred_reg_with_index, \"SME_PnT_Wm_imm\", 0,\t\t\\\n F(FLD_SME_Rm,FLD_SVE_Pn,FLD_SME_i1,FLD_SME_tszh,FLD_SME_tszl),\t\\\n \"Source scalable predicate register with index \")\t\\\n+ Y(SVE_REG, simple_index, \"SME_Zm_INDEX1\", 0,\t\t\t\\\n+ F(FLD_SME_Zm, FLD_imm1_10), \"an indexed SVE vector register\")\t\\\n+ Y(SVE_REG, simple_index, \"SME_Zm_INDEX2\", 0,\t\t\t\\\n+ F(FLD_SME_Zm, FLD_imm2_10), \"an indexed SVE vector register\")\t\\\n Y(SVE_REG, simple_index, \"SME_Zn_INDEX1_16\", 0,\t\t\t\\\n F(FLD_SVE_Zn, FLD_imm1_16), \"an indexed SVE vector register\")\t\\\n Y(SVE_REG, simple_index, \"SME_Zn_INDEX2_15\", 0,\t\t\t\\\n","prefixes":["13/31"]}+ exit 1 Build step 'Execute shell' marked build as failure Finished: FAILURE