Started by user snail Running as SYSTEM [EnvInject] - Loading node environment variables. Building remotely on docker-jenkins-agent in workspace /home/jenkins/agent/workspace/binutils-gdb [WS-CLEANUP] Deleting project workspace... [WS-CLEANUP] Deferred wipeout is used... [WS-CLEANUP] Done The recommended git tool is: NONE using credential 0adb5fc7-caa2-429d-97d2-c7fa2fa1d884 Cloning the remote Git repository Using shallow clone with depth 1 Avoid fetching tags Cloning repository git@github.com:wangliu-iscas/binutils-gdb.git/ > git init /home/jenkins/agent/workspace/binutils-gdb # timeout=10 Fetching upstream changes from git@github.com:wangliu-iscas/binutils-gdb.git/ > git --version # timeout=10 > git --version # 'git version 2.37.2' using GIT_SSH to set credentials patchwork github wangliu-iscas git ssh key Verifying host key using known hosts file, will automatically accept unseen keys > git fetch --no-tags --force --progress --depth=1 -- git@github.com:wangliu-iscas/binutils-gdb.git/ +refs/heads/*:refs/remotes/origin/* # timeout=10 > git config remote.origin.url git@github.com:wangliu-iscas/binutils-gdb.git/ # timeout=10 > git config --add remote.origin.fetch +refs/heads/*:refs/remotes/origin/* # timeout=10 Avoid second fetch > git rev-parse refs/remotes/origin/master^{commit} # timeout=10 Checking out Revision 02a8b5c25806339f801c80a5a364a963b2ece080 (refs/remotes/origin/master) > git config core.sparsecheckout # timeout=10 > git checkout -f 02a8b5c25806339f801c80a5a364a963b2ece080 # timeout=10 Commit message: "Automatic date update in version.in" > git rev-list --no-walk 02a8b5c25806339f801c80a5a364a963b2ece080 # timeout=10 [EnvInject] - Mask passwords that will be passed as build parameters. [EnvInject] - Executing scripts and injecting environment variables after the SCM step. [EnvInject] - Injecting as environment variables the properties content GITHUB_REPO=https://github.com/wangliu-iscas/ PATCHWORK_URL=https://patchwork.plctlab.org [EnvInject] - Variables injected successfully. [binutils-gdb] $ /usr/bin/env bash /tmp/jenkins595743820157110727.sh + git config pw.server https://patchwork.plctlab.org/api/1.2/ + git config pw.project binutils-gdb + git config pw.token [*******] ++ date +%Y-%m + now_date=2022-10 + echo 2022-10 2022-10 ++ curl -s -H 'Authorization: Token [*******]' 'https://patchwork.plctlab.org/api/1.2/bundles/?project=binutils-gdb&per_page=999' + bundle_response='[{"id":6,"url":"https://patchwork.plctlab.org/api/1.2/bundles/6/","web_url":"https://patchwork.plctlab.org/bundle/snail/binutils-gdb_2022-10/","project":{"id":2,"url":"https://patchwork.plctlab.org/api/1.2/projects/2/","name":"binutils-gdb","link_name":"binutils-gdb","list_id":"binutils.sourceware.org","list_email":"binutils@sourceware.org","web_url":"https://sourceware.org/mailman/listinfo/binutils","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"name":"binutils-gdb_2022-10","owner":{"id":1,"url":"https://patchwork.plctlab.org/api/1.2/users/1/","username":"snail","first_name":"","last_name":"","email":"wangliu@iscas.ac.cn"},"patches":[{"id":1592,"url":"https://patchwork.plctlab.org/api/1.2/patches/1592/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/385d01fd-7e57-1f3f-1bae-30aa0c313d63@suse.com/","msgid":"<385d01fd-7e57-1f3f-1bae-30aa0c313d63@suse.com>","list_archive_url":null,"date":"2022-09-30T11:59:45","name":"[3/4] RISC-V/gas: don'\''t open-code insn_length()","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/385d01fd-7e57-1f3f-1bae-30aa0c313d63@suse.com/mbox/"},{"id":1594,"url":"https://patchwork.plctlab.org/api/1.2/patches/1594/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f5757acf-7b90-a0e3-5eea-3b97cc226930@suse.com/","msgid":"","list_archive_url":null,"date":"2022-09-30T12:00:12","name":"[4/4] RISC-V/gas: allow generating up to 176-bit instructions with .insn","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f5757acf-7b90-a0e3-5eea-3b97cc226930@suse.com/mbox/"},{"id":1596,"url":"https://patchwork.plctlab.org/api/1.2/patches/1596/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930140503.38233-1-chigot@adacore.com/","msgid":"<20220930140503.38233-1-chigot@adacore.com>","list_archive_url":null,"date":"2022-09-30T14:05:03","name":"ld/testsuite: consistently add board_ldflags when linking with GCC","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930140503.38233-1-chigot@adacore.com/mbox/"},{"id":1619,"url":"https://patchwork.plctlab.org/api/1.2/patches/1619/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221001014451.532772-1-maskray@google.com/","msgid":"<20221001014451.532772-1-maskray@google.com>","list_archive_url":null,"date":"2022-10-01T01:44:51","name":"gold, dwp: support zstd compressed input debug sections [PR 29641]","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221001014451.532772-1-maskray@google.com/mbox/"},{"id":1620,"url":"https://patchwork.plctlab.org/api/1.2/patches/1620/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221001023846.590825-1-maskray@google.com/","msgid":"<20221001023846.590825-1-maskray@google.com>","list_archive_url":null,"date":"2022-10-01T02:38:46","name":"gold: add --compress-debug-sections=zstd [PR 29641]","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221001023846.590825-1-maskray@google.com/mbox/"},{"id":1623,"url":"https://patchwork.plctlab.org/api/1.2/patches/1623/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b4477c7f666bdeb7f8e998633c7b0cb62310b9ef.1664599545.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-01T04:45:52","name":"[RFC,1/1] RISC-V: Implement common register pair framework","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b4477c7f666bdeb7f8e998633c7b0cb62310b9ef.1664599545.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1625,"url":"https://patchwork.plctlab.org/api/1.2/patches/1625/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/53a265a1f14d17a6f7b106082f610994c5d546e0.1664602025.git.research_trasio@irq.a4lg.com/","msgid":"<53a265a1f14d17a6f7b106082f610994c5d546e0.1664602025.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-01T05:27:31","name":"[RFC,1/1] RISC-V: Implement extension variants","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/53a265a1f14d17a6f7b106082f610994c5d546e0.1664602025.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1626,"url":"https://patchwork.plctlab.org/api/1.2/patches/1626/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8db04962aba9c780f133840a8934353a58f223fe.1664602716.git.research_trasio@irq.a4lg.com/","msgid":"<8db04962aba9c780f133840a8934353a58f223fe.1664602716.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-01T05:39:26","name":"[1/1] RISC-V: Move supervisor instructions after all unprivileged ones","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8db04962aba9c780f133840a8934353a58f223fe.1664602716.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1627,"url":"https://patchwork.plctlab.org/api/1.2/patches/1627/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221001062057.681440-1-maskray@google.com/","msgid":"<20221001062057.681440-1-maskray@google.com>","list_archive_url":null,"date":"2022-10-01T06:20:57","name":"readelf: support zstd compressed debug sections [PR 29640]","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221001062057.681440-1-maskray@google.com/mbox/"},{"id":1631,"url":"https://patchwork.plctlab.org/api/1.2/patches/1631/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/619f112539c0bdecd58e25664f1250a3479a37f5.1664707612.git.aburgess@redhat.com/","msgid":"<619f112539c0bdecd58e25664f1250a3479a37f5.1664707612.git.aburgess@redhat.com>","list_archive_url":null,"date":"2022-10-02T10:47:52","name":"[PATCHv2,2/2] opcodes/arm: add disassembler styling for arm","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/619f112539c0bdecd58e25664f1250a3479a37f5.1664707612.git.aburgess@redhat.com/mbox/"},{"id":1635,"url":"https://patchwork.plctlab.org/api/1.2/patches/1635/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221002185433.gl7dvytfh5wthifx@lug-owl.de/","msgid":"<20221002185433.gl7dvytfh5wthifx@lug-owl.de>","list_archive_url":null,"date":"2022-10-02T18:54:33","name":"diagnostics.h: GCC 13 got -Wself-move, breaks GDB build","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221002185433.gl7dvytfh5wthifx@lug-owl.de/mbox/"},{"id":1637,"url":"https://patchwork.plctlab.org/api/1.2/patches/1637/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003014313.28766-1-mark@harmstone.com/","msgid":"<20221003014313.28766-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-03T01:43:12","name":"[1/2] ld: Add --pdb option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003014313.28766-1-mark@harmstone.com/mbox/"},{"id":1638,"url":"https://patchwork.plctlab.org/api/1.2/patches/1638/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003014313.28766-2-mark@harmstone.com/","msgid":"<20221003014313.28766-2-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-03T01:43:13","name":"[2/2] ld: Add minimal pdb generation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003014313.28766-2-mark@harmstone.com/mbox/"},{"id":1640,"url":"https://patchwork.plctlab.org/api/1.2/patches/1640/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/597ed978-d121-220c-b56b-2ffb94bd091c@suse.cz/","msgid":"<597ed978-d121-220c-b56b-2ffb94bd091c@suse.cz>","list_archive_url":null,"date":"2022-10-03T07:50:38","name":"[1/2] refactor usage of compressed_debug_section_type","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/597ed978-d121-220c-b56b-2ffb94bd091c@suse.cz/mbox/"},{"id":1641,"url":"https://patchwork.plctlab.org/api/1.2/patches/1641/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b8acdd83-f33a-74b8-e21a-23719a0b1a60@suse.cz/","msgid":"","list_archive_url":null,"date":"2022-10-03T07:50:44","name":"[2/2] add --enable-default-compressed-debug-sections-algorithm configure option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b8acdd83-f33a-74b8-e21a-23719a0b1a60@suse.cz/mbox/"},{"id":1642,"url":"https://patchwork.plctlab.org/api/1.2/patches/1642/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003101328.1790113-1-aburgess@redhat.com/","msgid":"<20221003101328.1790113-1-aburgess@redhat.com>","list_archive_url":null,"date":"2022-10-03T10:13:28","name":"opcodes/riscv: style csr names as registers","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003101328.1790113-1-aburgess@redhat.com/mbox/"},{"id":1643,"url":"https://patchwork.plctlab.org/api/1.2/patches/1643/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7ba14fc4472ce97d4f7a4433cad8a571e89f82f4.1664793840.git.research_trasio@irq.a4lg.com/","msgid":"<7ba14fc4472ce97d4f7a4433cad8a571e89f82f4.1664793840.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-03T10:43:59","name":"[v3,1/6] RISC-V: Fix immediates to have \"immediate\" style","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7ba14fc4472ce97d4f7a4433cad8a571e89f82f4.1664793840.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1644,"url":"https://patchwork.plctlab.org/api/1.2/patches/1644/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a498bec37c1fd1dcda57cbf95e5f8cfba09b31d3.1664793840.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-03T10:44:00","name":"[v3,2/6] RISC-V: Fix printf argument types corresponding %x","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a498bec37c1fd1dcda57cbf95e5f8cfba09b31d3.1664793840.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1647,"url":"https://patchwork.plctlab.org/api/1.2/patches/1647/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0002ea716713ace4998a33dde0b81f4f890d10bf.1664793840.git.research_trasio@irq.a4lg.com/","msgid":"<0002ea716713ace4998a33dde0b81f4f890d10bf.1664793840.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-03T10:44:01","name":"[v3,3/6] RISC-V: Optimize riscv_disassemble_data printf","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0002ea716713ace4998a33dde0b81f4f890d10bf.1664793840.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1646,"url":"https://patchwork.plctlab.org/api/1.2/patches/1646/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c65fc3e9aa58965d6768a28c9fd7467fea9897a5.1664793840.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-03T10:44:02","name":"[v3,4/6] RISC-V: Print comma and tabs as the \"text\" style","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c65fc3e9aa58965d6768a28c9fd7467fea9897a5.1664793840.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1648,"url":"https://patchwork.plctlab.org/api/1.2/patches/1648/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5abe1d8a7694417b990e11d8f6cd6789573872e5.1664793840.git.research_trasio@irq.a4lg.com/","msgid":"<5abe1d8a7694417b990e11d8f6cd6789573872e5.1664793840.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-03T10:44:03","name":"[v3,5/6] RISC-V: Fix T-Head immediate types on printing","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5abe1d8a7694417b990e11d8f6cd6789573872e5.1664793840.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1649,"url":"https://patchwork.plctlab.org/api/1.2/patches/1649/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0b68af932117258c908db62cf87c3a15d3cdec41.1664793840.git.research_trasio@irq.a4lg.com/","msgid":"<0b68af932117258c908db62cf87c3a15d3cdec41.1664793840.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-03T10:44:04","name":"[v3,6/6] RISC-V: Print XTheadMemPair literal as \"immediate\"","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0b68af932117258c908db62cf87c3a15d3cdec41.1664793840.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1656,"url":"https://patchwork.plctlab.org/api/1.2/patches/1656/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/87lepxcd6x.fsf@redhat.com/","msgid":"<87lepxcd6x.fsf@redhat.com>","list_archive_url":null,"date":"2022-10-03T12:19:02","name":"Commit: readelf: Do not load section data from offset 0","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/87lepxcd6x.fsf@redhat.com/mbox/"},{"id":1659,"url":"https://patchwork.plctlab.org/api/1.2/patches/1659/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e0d369d419da9c0441f415da7f54352aead8f655.1664707612.git.aburgess@redhat.com/","msgid":"","list_archive_url":null,"date":"2022-10-03T16:37:36","name":"[PATCHv2,1/2] opcodes/arm: use '\''@'\'' consistently for the comment character","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e0d369d419da9c0441f415da7f54352aead8f655.1664707612.git.aburgess@redhat.com/mbox/"},{"id":1660,"url":"https://patchwork.plctlab.org/api/1.2/patches/1660/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003165848.11142-1-palmer@rivosinc.com/","msgid":"<20221003165848.11142-1-palmer@rivosinc.com>","list_archive_url":null,"date":"2022-10-03T16:58:48","name":"gas: NEWS: Mention the T-Head extensions that were recently added","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003165848.11142-1-palmer@rivosinc.com/mbox/"},{"id":1671,"url":"https://patchwork.plctlab.org/api/1.2/patches/1671/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/YzvrMEdkXjIn5Lfz@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-04T08:13:36","name":"Support objcopy changing compression to or from zstd","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/YzvrMEdkXjIn5Lfz@squeak.grove.modra.org/mbox/"},{"id":1673,"url":"https://patchwork.plctlab.org/api/1.2/patches/1673/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0bc857d306bb7c8130e5328dbe6b9ed2fed3ef87.1664873933.git.research_trasio@irq.a4lg.com/","msgid":"<0bc857d306bb7c8130e5328dbe6b9ed2fed3ef87.1664873933.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-04T08:59:07","name":"[1/2] RISC-V: Fix buffer overflow on print_insn_riscv","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0bc857d306bb7c8130e5328dbe6b9ed2fed3ef87.1664873933.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1672,"url":"https://patchwork.plctlab.org/api/1.2/patches/1672/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/89612fe01d902007bf84a7dfb0df5f85d5c166e4.1664873933.git.research_trasio@irq.a4lg.com/","msgid":"<89612fe01d902007bf84a7dfb0df5f85d5c166e4.1664873933.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-04T08:59:08","name":"[2/2] gdb/riscv: Fix buffer overflow on riscv_insn::fetch_instruction","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/89612fe01d902007bf84a7dfb0df5f85d5c166e4.1664873933.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1676,"url":"https://patchwork.plctlab.org/api/1.2/patches/1676/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fc849c94f4adcac1c4ccc5508c7a145a2f13b2a9.1664876744.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-04T09:45:49","name":"[v2,1/2] RISC-V: Fix buffer overflow on print_insn_riscv","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fc849c94f4adcac1c4ccc5508c7a145a2f13b2a9.1664876744.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1677,"url":"https://patchwork.plctlab.org/api/1.2/patches/1677/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4eb6e59ae2e790dbbf2bc92477edd281648d8814.1664876744.git.research_trasio@irq.a4lg.com/","msgid":"<4eb6e59ae2e790dbbf2bc92477edd281648d8814.1664876744.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-04T09:45:50","name":"[v2,2/2] gdb/riscv: Partial support for instructions up to 176-bits","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4eb6e59ae2e790dbbf2bc92477edd281648d8814.1664876744.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1678,"url":"https://patchwork.plctlab.org/api/1.2/patches/1678/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ebf16f9e1f45115d0793952ccb4a94d4233303f9.1664882725.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-04T11:25:56","name":"[v3,1/2] RISC-V: Fix buffer overflow on print_insn_riscv","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ebf16f9e1f45115d0793952ccb4a94d4233303f9.1664882725.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1679,"url":"https://patchwork.plctlab.org/api/1.2/patches/1679/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/83464b09b8649525259c69c853dfa2c9575a204b.1664882725.git.research_trasio@irq.a4lg.com/","msgid":"<83464b09b8649525259c69c853dfa2c9575a204b.1664882725.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-04T11:25:57","name":"[v3,2/2] gdb/riscv: Partial support for instructions up to 176-bit","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/83464b09b8649525259c69c853dfa2c9575a204b.1664882725.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1681,"url":"https://patchwork.plctlab.org/api/1.2/patches/1681/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ffa9c1d7-e8c2-a62b-ef3e-b565c0ffbe5b@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-04T13:56:27","name":"RISC-V: Zicbo{m,p,z} adjustments to riscv_multi_subset_supports_ext()","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ffa9c1d7-e8c2-a62b-ef3e-b565c0ffbe5b@suse.com/mbox/"},{"id":1690,"url":"https://patchwork.plctlab.org/api/1.2/patches/1690/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221004161720.1963953-1-vladimir.mezentsev@oracle.com/","msgid":"<20221004161720.1963953-1-vladimir.mezentsev@oracle.com>","list_archive_url":null,"date":"2022-10-04T16:17:20","name":"gprofng: fix build with --enable-pgo-build=lto","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221004161720.1963953-1-vladimir.mezentsev@oracle.com/mbox/"},{"id":1691,"url":"https://patchwork.plctlab.org/api/1.2/patches/1691/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c0211bc9c57be6c79c6d878ce147f63b657f461d.camel@espressif.com/","msgid":"","list_archive_url":null,"date":"2022-10-04T16:22:05","name":"bfd: xtensa: fix __stop_SECTION literal drop,","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c0211bc9c57be6c79c6d878ce147f63b657f461d.camel@espressif.com/mbox/"},{"id":1702,"url":"https://patchwork.plctlab.org/api/1.2/patches/1702/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5f482299-6c60-b2b3-9abe-f4a55a5a26c5@univ-grenoble-alpes.fr/","msgid":"<5f482299-6c60-b2b3-9abe-f4a55a5a26c5@univ-grenoble-alpes.fr>","list_archive_url":null,"date":"2022-10-04T20:03:20","name":"[RFC] bfd: use bfd_vma for the 64-bit version of put[lb] and get[lb]","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5f482299-6c60-b2b3-9abe-f4a55a5a26c5@univ-grenoble-alpes.fr/mbox/"},{"id":1711,"url":"https://patchwork.plctlab.org/api/1.2/patches/1711/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Yz0Gsxdxe0TePbJT@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-05T04:23:15","name":"PR29647, objdump -S looping","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Yz0Gsxdxe0TePbJT@squeak.grove.modra.org/mbox/"},{"id":1712,"url":"https://patchwork.plctlab.org/api/1.2/patches/1712/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/02d747d2-f57b-0fb5-b893-842b6cc41f2f@suse.com/","msgid":"<02d747d2-f57b-0fb5-b893-842b6cc41f2f@suse.com>","list_archive_url":null,"date":"2022-10-05T07:20:47","name":"[v3,1/7] x86: constify parse_insn()'\''s input","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/02d747d2-f57b-0fb5-b893-842b6cc41f2f@suse.com/mbox/"},{"id":1713,"url":"https://patchwork.plctlab.org/api/1.2/patches/1713/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/925cb740-4e1b-abc4-8526-aaab6faae5e1@suse.com/","msgid":"<925cb740-4e1b-abc4-8526-aaab6faae5e1@suse.com>","list_archive_url":null,"date":"2022-10-05T07:22:19","name":"[v3,2/7] x86: introduce Pass2 insn attribute","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/925cb740-4e1b-abc4-8526-aaab6faae5e1@suse.com/mbox/"},{"id":1714,"url":"https://patchwork.plctlab.org/api/1.2/patches/1714/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e16d3e78-39ca-f715-508f-a4104b8ab9a9@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-05T07:23:51","name":"[v3,3/7] x86: re-work insn/suffix recognition","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e16d3e78-39ca-f715-508f-a4104b8ab9a9@suse.com/mbox/"},{"id":1715,"url":"https://patchwork.plctlab.org/api/1.2/patches/1715/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e4e4b80b-794c-7485-1997-685adab8fb27@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-05T07:24:20","name":"[v3,4/7] x86-64: further re-work insn/suffix recognition to also cover MOVSL","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e4e4b80b-794c-7485-1997-685adab8fb27@suse.com/mbox/"},{"id":1716,"url":"https://patchwork.plctlab.org/api/1.2/patches/1716/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/540678fc-8bff-ec68-c97c-478d2631998c@suse.com/","msgid":"<540678fc-8bff-ec68-c97c-478d2631998c@suse.com>","list_archive_url":null,"date":"2022-10-05T07:24:55","name":"[v3,5/7] ix86: don'\''t recognize/derive Q suffix in the common case","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/540678fc-8bff-ec68-c97c-478d2631998c@suse.com/mbox/"},{"id":1718,"url":"https://patchwork.plctlab.org/api/1.2/patches/1718/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e4692495-7d3d-074d-14f9-364d4a9a998c@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-05T07:25:25","name":"[v3,6/7] x86-64: allow HLE store of accumulator to absolute 32-bit address","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e4692495-7d3d-074d-14f9-364d4a9a998c@suse.com/mbox/"},{"id":1717,"url":"https://patchwork.plctlab.org/api/1.2/patches/1717/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e8014ebd-d16b-17a7-9f34-3700fc164136@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-05T07:25:57","name":"[v3,7/7] x86: move bad-use-of-TLS-reloc check","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e8014ebd-d16b-17a7-9f34-3700fc164136@suse.com/mbox/"},{"id":1719,"url":"https://patchwork.plctlab.org/api/1.2/patches/1719/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1266f001-4511-2662-dba9-14b4d0317c57@suse.com/","msgid":"<1266f001-4511-2662-dba9-14b4d0317c57@suse.com>","list_archive_url":null,"date":"2022-10-05T07:40:50","name":"x86: drop \"regmask\" static variable","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1266f001-4511-2662-dba9-14b4d0317c57@suse.com/mbox/"},{"id":1751,"url":"https://patchwork.plctlab.org/api/1.2/patches/1751/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/af45c5d57c221e43101c2aa38b14f4b4ac12d011.1665031170.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-06T04:40:15","name":"[v2,1/2] RISC-V: Fallback for instructions longer than 64b","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/af45c5d57c221e43101c2aa38b14f4b4ac12d011.1665031170.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1752,"url":"https://patchwork.plctlab.org/api/1.2/patches/1752/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c6e55781245dd3e8e9b8debd6130fc5449dfbd55.1665031170.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-06T04:40:16","name":"[v2,2/2] RISC-V: Improve \"bits undefined\" diagnostics","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c6e55781245dd3e8e9b8debd6130fc5449dfbd55.1665031170.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1776,"url":"https://patchwork.plctlab.org/api/1.2/patches/1776/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d52952119e15357c0e823f8a2398999359588b4d.1665050099.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-06T09:56:30","name":"[v3,1/2] RISC-V: Fallback for instructions longer than 64b","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d52952119e15357c0e823f8a2398999359588b4d.1665050099.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1777,"url":"https://patchwork.plctlab.org/api/1.2/patches/1777/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d907b1997f60ff7823c4a23e281ec9d8ddcbf3f1.1665050099.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-06T09:56:31","name":"[v3,2/2] RISC-V: Improve \"bits undefined\" diagnostics","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d907b1997f60ff7823c4a23e281ec9d8ddcbf3f1.1665050099.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1781,"url":"https://patchwork.plctlab.org/api/1.2/patches/1781/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221006114628.304185-1-chigot@adacore.com/","msgid":"<20221006114628.304185-1-chigot@adacore.com>","list_archive_url":null,"date":"2022-10-06T11:46:28","name":"RISC-V: fix linker message when relaxation deletes bytes","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221006114628.304185-1-chigot@adacore.com/mbox/"},{"id":1801,"url":"https://patchwork.plctlab.org/api/1.2/patches/1801/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Yz+Yhyg7UewC9/kp@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-07T03:09:59","name":"PR29653, objcopy/strip: fuzzed small input file induces large output file","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Yz+Yhyg7UewC9/kp@squeak.grove.modra.org/mbox/"},{"id":1803,"url":"https://patchwork.plctlab.org/api/1.2/patches/1803/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/PH1P110MB16505D9D39EC5B1DE22FE3D5EC5F9@PH1P110MB1650.NAMP110.PROD.OUTLOOK.COM/","msgid":"","list_archive_url":null,"date":"2022-10-07T04:10:07","name":"@CPP_FOR_BUILD@ problem since binutils-2.38","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/PH1P110MB16505D9D39EC5B1DE22FE3D5EC5F9@PH1P110MB1650.NAMP110.PROD.OUTLOOK.COM/mbox/"},{"id":1827,"url":"https://patchwork.plctlab.org/api/1.2/patches/1827/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8e13bce108ac10a0c1dd911e23ec572926f7ae44.1665203374.git.research_trasio@irq.a4lg.com/","msgid":"<8e13bce108ac10a0c1dd911e23ec572926f7ae44.1665203374.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-08T04:29:53","name":"[v2,1/1] RISC-V: Test DWARF register numbers for \"fp\"","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8e13bce108ac10a0c1dd911e23ec572926f7ae44.1665203374.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1828,"url":"https://patchwork.plctlab.org/api/1.2/patches/1828/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0883001b3572e54d3fba264429c7ade2adb66610.1665203441.git.research_trasio@irq.a4lg.com/","msgid":"<0883001b3572e54d3fba264429c7ade2adb66610.1665203441.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-08T04:31:15","name":"[1/1] RISC-V: Move standard hints before all instructions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0883001b3572e54d3fba264429c7ade2adb66610.1665203441.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1829,"url":"https://patchwork.plctlab.org/api/1.2/patches/1829/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/58e16a241d7376fcae2515c6bd5a2b41d275eeba.1665203531.git.research_trasio@irq.a4lg.com/","msgid":"<58e16a241d7376fcae2515c6bd5a2b41d275eeba.1665203531.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-08T04:32:18","name":"[RFC,1/1] RISC-V: Imply '\''Zicsr'\'' from privileged extensions with CSRs","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/58e16a241d7376fcae2515c6bd5a2b41d275eeba.1665203531.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1830,"url":"https://patchwork.plctlab.org/api/1.2/patches/1830/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/cb5076fc96e8f2097779a3abcde843dcdd660031.1665203660.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-08T04:34:23","name":"[1/5] opcodes/riscv-dis.c: Tidying with comments/clarity","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/cb5076fc96e8f2097779a3abcde843dcdd660031.1665203660.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1832,"url":"https://patchwork.plctlab.org/api/1.2/patches/1832/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1f1aa0838bf9c4f10a45fcfe3c682f7efc79d9ae.1665203660.git.research_trasio@irq.a4lg.com/","msgid":"<1f1aa0838bf9c4f10a45fcfe3c682f7efc79d9ae.1665203660.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-08T04:34:24","name":"[2/5] opcodes/riscv-dis.c: Tidying with spacing","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1f1aa0838bf9c4f10a45fcfe3c682f7efc79d9ae.1665203660.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1831,"url":"https://patchwork.plctlab.org/api/1.2/patches/1831/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/740bc5e2d2618d236519b39fedd1a1d7ae4e05da.1665203660.git.research_trasio@irq.a4lg.com/","msgid":"<740bc5e2d2618d236519b39fedd1a1d7ae4e05da.1665203660.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-08T04:34:25","name":"[3/5] opcodes/riscv-dis.c: Use bool type whenever possible","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/740bc5e2d2618d236519b39fedd1a1d7ae4e05da.1665203660.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1833,"url":"https://patchwork.plctlab.org/api/1.2/patches/1833/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6e3a9c235e317f441b4383b3daa68f2051bdc149.1665203660.git.research_trasio@irq.a4lg.com/","msgid":"<6e3a9c235e317f441b4383b3daa68f2051bdc149.1665203660.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-08T04:34:26","name":"[4/5] opcodes/riscv-dis.c: Make XLEN variable static","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6e3a9c235e317f441b4383b3daa68f2051bdc149.1665203660.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1834,"url":"https://patchwork.plctlab.org/api/1.2/patches/1834/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ad929233a62d887495122721340b2f9c80392963.1665203660.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-08T04:34:27","name":"[5/5] opcodes/riscv-dis.c: Remove last_map_state","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ad929233a62d887495122721340b2f9c80392963.1665203660.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1836,"url":"https://patchwork.plctlab.org/api/1.2/patches/1836/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d07e2b6f36ea2fd5830924a9bfeda941b774b687.1665290422.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-09T05:09:22","name":"RISC-V: Move certain arrays to riscv-opc.c","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d07e2b6f36ea2fd5830924a9bfeda941b774b687.1665290422.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1844,"url":"https://patchwork.plctlab.org/api/1.2/patches/1844/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010004623.16582-1-mark@harmstone.com/","msgid":"<20221010004623.16582-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-10T00:46:22","name":"[v2,1/2] ld: Add --pdb option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010004623.16582-1-mark@harmstone.com/mbox/"},{"id":1845,"url":"https://patchwork.plctlab.org/api/1.2/patches/1845/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010004623.16582-2-mark@harmstone.com/","msgid":"<20221010004623.16582-2-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-10T00:46:23","name":"[v2,2/2] ld: Add minimal pdb generation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010004623.16582-2-mark@harmstone.com/mbox/"},{"id":1890,"url":"https://patchwork.plctlab.org/api/1.2/patches/1890/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010200433.414320-1-vladimir.mezentsev@oracle.com/","msgid":"<20221010200433.414320-1-vladimir.mezentsev@oracle.com>","list_archive_url":null,"date":"2022-10-10T20:04:33","name":"gprofng: run tests without installation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010200433.414320-1-vladimir.mezentsev@oracle.com/mbox/"},{"id":1893,"url":"https://patchwork.plctlab.org/api/1.2/patches/1893/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010230426.719238-1-vladimir.mezentsev@oracle.com/","msgid":"<20221010230426.719238-1-vladimir.mezentsev@oracle.com>","list_archive_url":null,"date":"2022-10-10T23:04:26","name":"[2/2] gprofng: use the --libdir path to find libraries","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010230426.719238-1-vladimir.mezentsev@oracle.com/mbox/"},{"id":1894,"url":"https://patchwork.plctlab.org/api/1.2/patches/1894/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010235155.842469-1-vladimir.mezentsev@oracle.com/","msgid":"<20221010235155.842469-1-vladimir.mezentsev@oracle.com>","list_archive_url":null,"date":"2022-10-10T23:51:55","name":"[3/3] gprofng: no need to build version.texi","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010235155.842469-1-vladimir.mezentsev@oracle.com/mbox/"},{"id":1895,"url":"https://patchwork.plctlab.org/api/1.2/patches/1895/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011003702.4287-1-mark@harmstone.com/","msgid":"<20221011003702.4287-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-11T00:37:01","name":"[v3,1/2] ld: Add --pdb option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011003702.4287-1-mark@harmstone.com/mbox/"},{"id":1897,"url":"https://patchwork.plctlab.org/api/1.2/patches/1897/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011003702.4287-2-mark@harmstone.com/","msgid":"<20221011003702.4287-2-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-11T00:37:02","name":"[v3,2/2] ld: Add minimal pdb generation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011003702.4287-2-mark@harmstone.com/mbox/"},{"id":1928,"url":"https://patchwork.plctlab.org/api/1.2/patches/1928/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011175332.17156-1-mark@harmstone.com/","msgid":"<20221011175332.17156-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-11T17:53:31","name":"[v4,1/2] ld: Add --pdb option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011175332.17156-1-mark@harmstone.com/mbox/"},{"id":1929,"url":"https://patchwork.plctlab.org/api/1.2/patches/1929/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011175332.17156-2-mark@harmstone.com/","msgid":"<20221011175332.17156-2-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-11T17:53:32","name":"[v4,2/2] ld: Add minimal pdb generation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011175332.17156-2-mark@harmstone.com/mbox/"},{"id":1941,"url":"https://patchwork.plctlab.org/api/1.2/patches/1941/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221012031005.237446-1-simon.marchi@polymtl.ca/","msgid":"<20221012031005.237446-1-simon.marchi@polymtl.ca>","list_archive_url":null,"date":"2022-10-12T03:10:05","name":"[pushed] Re-apply \"Pass PKG_CONFIG_PATH down from top-level Makefile\"","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221012031005.237446-1-simon.marchi@polymtl.ca/mbox/"},{"id":1976,"url":"https://patchwork.plctlab.org/api/1.2/patches/1976/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1216a3f8-2273-8681-f528-9493a66891f0@suse.com/","msgid":"<1216a3f8-2273-8681-f528-9493a66891f0@suse.com>","list_archive_url":null,"date":"2022-10-13T08:16:49","name":"[v4,1/8] x86: constify parse_insn()'\''s input","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1216a3f8-2273-8681-f528-9493a66891f0@suse.com/mbox/"},{"id":1977,"url":"https://patchwork.plctlab.org/api/1.2/patches/1977/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/11599bbe-c779-aa9f-4d5d-c2243f0e69dc@suse.com/","msgid":"<11599bbe-c779-aa9f-4d5d-c2243f0e69dc@suse.com>","list_archive_url":null,"date":"2022-10-13T08:17:17","name":"[v4,2/8] x86: introduce Pass2 insn attribute","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/11599bbe-c779-aa9f-4d5d-c2243f0e69dc@suse.com/mbox/"},{"id":1978,"url":"https://patchwork.plctlab.org/api/1.2/patches/1978/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/357273a3-060c-23db-72da-3fc9d1be3d2a@suse.com/","msgid":"<357273a3-060c-23db-72da-3fc9d1be3d2a@suse.com>","list_archive_url":null,"date":"2022-10-13T08:18:09","name":"[v4,3/8] x86: re-work insn/suffix recognition","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/357273a3-060c-23db-72da-3fc9d1be3d2a@suse.com/mbox/"},{"id":1979,"url":"https://patchwork.plctlab.org/api/1.2/patches/1979/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0ec0587f-6a7b-45b6-8346-e5d774e73636@suse.com/","msgid":"<0ec0587f-6a7b-45b6-8346-e5d774e73636@suse.com>","list_archive_url":null,"date":"2022-10-13T08:18:39","name":"[v4,4/8] x86-64: further re-work insn/suffix recognition to also cover MOVSL","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0ec0587f-6a7b-45b6-8346-e5d774e73636@suse.com/mbox/"},{"id":1980,"url":"https://patchwork.plctlab.org/api/1.2/patches/1980/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fb617d0b-8759-3169-5a65-1178b7fef3d7@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-13T08:19:34","name":"[v4,5/8] ix86: don'\''t recognize/derive Q suffix in the common case","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fb617d0b-8759-3169-5a65-1178b7fef3d7@suse.com/mbox/"},{"id":1981,"url":"https://patchwork.plctlab.org/api/1.2/patches/1981/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1df3bd01-99c5-f56c-d937-970edd42b2b8@suse.com/","msgid":"<1df3bd01-99c5-f56c-d937-970edd42b2b8@suse.com>","list_archive_url":null,"date":"2022-10-13T08:20:14","name":"[v4,6/8] x86-64: allow HLE store of accumulator to absolute 32-bit address","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1df3bd01-99c5-f56c-d937-970edd42b2b8@suse.com/mbox/"},{"id":1982,"url":"https://patchwork.plctlab.org/api/1.2/patches/1982/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8486a218-39ec-16b2-5c6c-5037196b93cf@suse.com/","msgid":"<8486a218-39ec-16b2-5c6c-5037196b93cf@suse.com>","list_archive_url":null,"date":"2022-10-13T08:21:00","name":"[v4,7/8] x86: move bad-use-of-TLS-reloc check","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8486a218-39ec-16b2-5c6c-5037196b93cf@suse.com/mbox/"},{"id":1983,"url":"https://patchwork.plctlab.org/api/1.2/patches/1983/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7d82692d-93df-fbee-9efb-2f44e8a91df3@suse.com/","msgid":"<7d82692d-93df-fbee-9efb-2f44e8a91df3@suse.com>","list_archive_url":null,"date":"2022-10-13T08:22:00","name":"[v4,8/8] x86: drop (now) stray IsString","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7d82692d-93df-fbee-9efb-2f44e8a91df3@suse.com/mbox/"},{"id":2013,"url":"https://patchwork.plctlab.org/api/1.2/patches/2013/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8ab93d7a617ad480dd786210f46db0e5aa07d1ac.1665655719.git.research_trasio@irq.a4lg.com/","msgid":"<8ab93d7a617ad480dd786210f46db0e5aa07d1ac.1665655719.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-13T10:11:41","name":"include: Declare getopt function on old GNU libc","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8ab93d7a617ad480dd786210f46db0e5aa07d1ac.1665655719.git.research_trasio@irq.a4lg.com/mbox/"},{"id":2352,"url":"https://patchwork.plctlab.org/api/1.2/patches/2352/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221013201332.2747246-1-maskray@google.com/","msgid":"<20221013201332.2747246-1-maskray@google.com>","list_archive_url":null,"date":"2022-10-13T20:13:32","name":"ld: Add --undefined-version","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221013201332.2747246-1-maskray@google.com/mbox/"},{"id":2532,"url":"https://patchwork.plctlab.org/api/1.2/patches/2532/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014063520.1428330-2-zengxiao@eswincomputing.com/","msgid":"<20221014063520.1428330-2-zengxiao@eswincomputing.com>","list_archive_url":null,"date":"2022-10-14T06:35:20","name":"[1/1] RISC-V: Make R_RISCV_SUB6 conforms to riscv abi standard","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014063520.1428330-2-zengxiao@eswincomputing.com/mbox/"},{"id":2560,"url":"https://patchwork.plctlab.org/api/1.2/patches/2560/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/027ae69a-636b-6757-297a-eec42936401e@linaro.org/","msgid":"<027ae69a-636b-6757-297a-eec42936401e@linaro.org>","list_archive_url":null,"date":"2022-10-14T07:58:22","name":"[v3] aarch64-pe support for LD, GAS and BFD","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/027ae69a-636b-6757-297a-eec42936401e@linaro.org/mbox/"},{"id":2602,"url":"https://patchwork.plctlab.org/api/1.2/patches/2602/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-2-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-2-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:39","name":"[01/10] Support Intel AVX-IFMA","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-2-haochen.jiang@intel.com/mbox/"},{"id":2608,"url":"https://patchwork.plctlab.org/api/1.2/patches/2608/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-3-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-3-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:40","name":"[02/10] Support Intel AVX-VNNI-INT8","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-3-haochen.jiang@intel.com/mbox/"},{"id":2611,"url":"https://patchwork.plctlab.org/api/1.2/patches/2611/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-4-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-4-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:41","name":"[03/10] Support Intel AVX-NE-CONVERT","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-4-haochen.jiang@intel.com/mbox/"},{"id":2610,"url":"https://patchwork.plctlab.org/api/1.2/patches/2610/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-5-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-5-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:42","name":"[04/10] Support Intel CMPccXADD","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-5-haochen.jiang@intel.com/mbox/"},{"id":2601,"url":"https://patchwork.plctlab.org/api/1.2/patches/2601/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-6-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-6-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:43","name":"[05/10] Add handler for more i386_cpu_flags","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-6-haochen.jiang@intel.com/mbox/"},{"id":2606,"url":"https://patchwork.plctlab.org/api/1.2/patches/2606/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-7-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-7-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:44","name":"[06/10] Support Intel RAO-INT","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-7-haochen.jiang@intel.com/mbox/"},{"id":2609,"url":"https://patchwork.plctlab.org/api/1.2/patches/2609/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-8-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-8-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:45","name":"[07/10] Support Intel WRMSRNS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-8-haochen.jiang@intel.com/mbox/"},{"id":2605,"url":"https://patchwork.plctlab.org/api/1.2/patches/2605/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-9-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-9-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:46","name":"[08/10] Support Intel MSRLIST","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-9-haochen.jiang@intel.com/mbox/"},{"id":2607,"url":"https://patchwork.plctlab.org/api/1.2/patches/2607/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-10-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-10-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:47","name":"[09/10] Support Intel AMX-FP16","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-10-haochen.jiang@intel.com/mbox/"},{"id":2604,"url":"https://patchwork.plctlab.org/api/1.2/patches/2604/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-11-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-11-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:48","name":"[10/10] Support Intel PREFETCHI","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-11-haochen.jiang@intel.com/mbox/"},{"id":2643,"url":"https://patchwork.plctlab.org/api/1.2/patches/2643/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7bac66be-535e-9051-d674-f2f5ba180e17@suse.com/","msgid":"<7bac66be-535e-9051-d674-f2f5ba180e17@suse.com>","list_archive_url":null,"date":"2022-10-14T10:22:34","name":"x86: fold AVX512-VNNI disassembler entries with AVX-VNNI ones","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7bac66be-535e-9051-d674-f2f5ba180e17@suse.com/mbox/"},{"id":2654,"url":"https://patchwork.plctlab.org/api/1.2/patches/2654/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0lIo5+ncY/MqBEq@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-14T11:31:47","name":"PR29677, Field `the_bfd` of `asymbol` is uninitialised","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0lIo5+ncY/MqBEq@squeak.grove.modra.org/mbox/"},{"id":2656,"url":"https://patchwork.plctlab.org/api/1.2/patches/2656/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0lJksn49ZpABY89@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-14T11:35:46","name":"e200 LSP support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0lJksn49ZpABY89@squeak.grove.modra.org/mbox/"},{"id":2657,"url":"https://patchwork.plctlab.org/api/1.2/patches/2657/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0lJxxYoeD5iDYAD@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-14T11:36:39","name":"PowerPC SPE disassembly and tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0lJxxYoeD5iDYAD@squeak.grove.modra.org/mbox/"},{"id":2695,"url":"https://patchwork.plctlab.org/api/1.2/patches/2695/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/DM6PR12MB4219611F6CC2A0702884A602E7249@DM6PR12MB4219.namprd12.prod.outlook.com/","msgid":"","list_archive_url":null,"date":"2022-10-14T13:29:40","name":"Binutils: Adding new testcase for addr2line.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/DM6PR12MB4219611F6CC2A0702884A602E7249@DM6PR12MB4219.namprd12.prod.outlook.com/mbox/"},{"id":2700,"url":"https://patchwork.plctlab.org/api/1.2/patches/2700/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9fd2c88d-98b2-99a4-419f-c7235b2cf960@suse.com/","msgid":"<9fd2c88d-98b2-99a4-419f-c7235b2cf960@suse.com>","list_archive_url":null,"date":"2022-10-14T14:11:35","name":"x86: properly decode EVEX.W for AVX512_4{FMAPS,VNNIW} insns","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9fd2c88d-98b2-99a4-419f-c7235b2cf960@suse.com/mbox/"},{"id":2981,"url":"https://patchwork.plctlab.org/api/1.2/patches/2981/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0uLzalqjm4C87GN@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-16T04:42:53","name":"PowerPC se_rfmci and VLE, SPE2 and LSP insns with -many","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0uLzalqjm4C87GN@squeak.grove.modra.org/mbox/"},{"id":3152,"url":"https://patchwork.plctlab.org/api/1.2/patches/3152/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221016232419.1135-1-mark@harmstone.com/","msgid":"<20221016232419.1135-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-16T23:24:18","name":"[v5,1/2] ld: Add --pdb option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221016232419.1135-1-mark@harmstone.com/mbox/"},{"id":3151,"url":"https://patchwork.plctlab.org/api/1.2/patches/3151/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221016232419.1135-2-mark@harmstone.com/","msgid":"<20221016232419.1135-2-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-16T23:24:19","name":"[v5,2/2] ld: Add minimal pdb generation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221016232419.1135-2-mark@harmstone.com/mbox/"},{"id":3258,"url":"https://patchwork.plctlab.org/api/1.2/patches/3258/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/19c08747-fa5b-1e67-3dd2-c891a2c0c1fa@suse.com/","msgid":"<19c08747-fa5b-1e67-3dd2-c891a2c0c1fa@suse.com>","list_archive_url":null,"date":"2022-10-17T07:44:51","name":"x86: correct CPU_AMX_{BF16,INT8}_FLAGS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/19c08747-fa5b-1e67-3dd2-c891a2c0c1fa@suse.com/mbox/"},{"id":3272,"url":"https://patchwork.plctlab.org/api/1.2/patches/3272/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/85dd526c-d3a7-72dc-5444-ed5573eebec1@suse.com/","msgid":"<85dd526c-d3a7-72dc-5444-ed5573eebec1@suse.com>","list_archive_url":null,"date":"2022-10-17T08:30:12","name":"x86: generalize gas documentation for disabling of ISA extensions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/85dd526c-d3a7-72dc-5444-ed5573eebec1@suse.com/mbox/"},{"id":3759,"url":"https://patchwork.plctlab.org/api/1.2/patches/3759/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-2-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-2-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:15:58","name":"[V2,01/15] sframe.h: Add SFrame format definition","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-2-indu.bhagat@oracle.com/mbox/"},{"id":3762,"url":"https://patchwork.plctlab.org/api/1.2/patches/3762/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-3-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-3-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:15:59","name":"[V2,02/15] gas: add new command line option --gsframe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-3-indu.bhagat@oracle.com/mbox/"},{"id":3761,"url":"https://patchwork.plctlab.org/api/1.2/patches/3761/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-4-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-4-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:00","name":"[V2,03/15] gas: generate .sframe from CFI directives","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-4-indu.bhagat@oracle.com/mbox/"},{"id":3760,"url":"https://patchwork.plctlab.org/api/1.2/patches/3760/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-5-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-5-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:01","name":"[V2,04/15] gas: testsuite: add new tests for SFrame unwind info","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-5-indu.bhagat@oracle.com/mbox/"},{"id":3764,"url":"https://patchwork.plctlab.org/api/1.2/patches/3764/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-6-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-6-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:02","name":"[V2,05/15] libsframe: add the SFrame library","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-6-indu.bhagat@oracle.com/mbox/"},{"id":3763,"url":"https://patchwork.plctlab.org/api/1.2/patches/3763/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-8-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-8-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:04","name":"[V2,07/15] readelf/objdump: support for SFrame section","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-8-indu.bhagat@oracle.com/mbox/"}],"public":true,"mbox":"https://patchwork.plctlab.org/bundle/snail/binutils-gdb_2022-10/mbox/"},{"id":7,"url":"https://patchwork.plctlab.org/api/1.2/bundles/7/","web_url":"https://patchwork.plctlab.org/bundle/snail/binutils-gdb_2022-09/","project":{"id":2,"url":"https://patchwork.plctlab.org/api/1.2/projects/2/","name":"binutils-gdb","link_name":"binutils-gdb","list_id":"binutils.sourceware.org","list_email":"binutils@sourceware.org","web_url":"https://sourceware.org/mailman/listinfo/binutils","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"name":"binutils-gdb_2022-09","owner":{"id":1,"url":"https://patchwork.plctlab.org/api/1.2/users/1/","username":"snail","first_name":"","last_name":"","email":"wangliu@iscas.ac.cn"},"patches":[{"id":1573,"url":"https://patchwork.plctlab.org/api/1.2/patches/1573/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930073211.2634-1-jiawei@iscas.ac.cn/","msgid":"<20220930073211.2634-1-jiawei@iscas.ac.cn>","list_archive_url":null,"date":"2022-09-30T07:32:11","name":"[V2] RISC-V: Add Smepmp CSR '\''mseccfg'\'' define and testcases.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930073211.2634-1-jiawei@iscas.ac.cn/mbox/"},{"id":1577,"url":"https://patchwork.plctlab.org/api/1.2/patches/1577/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/76fa0c3c-2303-ebdf-a765-ac4731581517@suse.com/","msgid":"<76fa0c3c-2303-ebdf-a765-ac4731581517@suse.com>","list_archive_url":null,"date":"2022-09-30T08:54:18","name":"objcopy: avoid \"shadowing\" of remove() function name","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/76fa0c3c-2303-ebdf-a765-ac4731581517@suse.com/mbox/"},{"id":1579,"url":"https://patchwork.plctlab.org/api/1.2/patches/1579/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930085852.71213-1-nelson@rivosinc.com/","msgid":"<20220930085852.71213-1-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-09-30T08:58:51","name":"[1/2] RISC-V: Output mapping symbols with ISA string.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930085852.71213-1-nelson@rivosinc.com/mbox/"},{"id":1578,"url":"https://patchwork.plctlab.org/api/1.2/patches/1578/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930085852.71213-2-nelson@rivosinc.com/","msgid":"<20220930085852.71213-2-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-09-30T08:58:52","name":"[2/2] RISC-V: Refer mapping symbol to R_RISCV_RELAX for rvc relaxations.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930085852.71213-2-nelson@rivosinc.com/mbox/"},{"id":1581,"url":"https://patchwork.plctlab.org/api/1.2/patches/1581/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930092058.71286-1-nelson@rivosinc.com/","msgid":"<20220930092058.71286-1-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-09-30T09:20:57","name":"[1/2] RISC-V: Output mapping symbols with ISA string.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930092058.71286-1-nelson@rivosinc.com/mbox/"},{"id":1580,"url":"https://patchwork.plctlab.org/api/1.2/patches/1580/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930092058.71286-2-nelson@rivosinc.com/","msgid":"<20220930092058.71286-2-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-09-30T09:20:58","name":"[2/2] RISC-V: Refer mapping symbol to R_RISCV_RELAX for rvc relaxations.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930092058.71286-2-nelson@rivosinc.com/mbox/"},{"id":1582,"url":"https://patchwork.plctlab.org/api/1.2/patches/1582/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5874dd79-0cf5-d65c-7ea2-13adfc799c0f@suse.com/","msgid":"<5874dd79-0cf5-d65c-7ea2-13adfc799c0f@suse.com>","list_archive_url":null,"date":"2022-09-30T09:41:29","name":"RISC-V: fix build after \"Add support for arbitrary immediate encoding formats\"","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5874dd79-0cf5-d65c-7ea2-13adfc799c0f@suse.com/mbox/"},{"id":1583,"url":"https://patchwork.plctlab.org/api/1.2/patches/1583/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/57d8ac2a-5757-3776-9924-99c17ca69938@suse.com/","msgid":"<57d8ac2a-5757-3776-9924-99c17ca69938@suse.com>","list_archive_url":null,"date":"2022-09-30T09:42:08","name":"RISC-V: fallout from \"re-arrange opcode table for consistent alias handling\"","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/57d8ac2a-5757-3776-9924-99c17ca69938@suse.com/mbox/"},{"id":1584,"url":"https://patchwork.plctlab.org/api/1.2/patches/1584/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e76ef8f7-72b9-5103-cb43-9608af01d017@suse.com/","msgid":"","list_archive_url":null,"date":"2022-09-30T09:42:50","name":"RISC-V: don'\''t cast expressions'\'' X_add_number to long in diagnostics","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e76ef8f7-72b9-5103-cb43-9608af01d017@suse.com/mbox/"},{"id":1585,"url":"https://patchwork.plctlab.org/api/1.2/patches/1585/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/61355429-24b3-17d0-ab03-6fa57ee861d5@suse.cz/","msgid":"<61355429-24b3-17d0-ab03-6fa57ee861d5@suse.cz>","list_archive_url":null,"date":"2022-09-30T09:48:52","name":"[RFC] add --enable-zstd-compressed-debug-sections configure option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/61355429-24b3-17d0-ab03-6fa57ee861d5@suse.cz/mbox/"},{"id":1586,"url":"https://patchwork.plctlab.org/api/1.2/patches/1586/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930103919.323690-1-christoph.muellner@vrull.eu/","msgid":"<20220930103919.323690-1-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2022-09-30T10:39:19","name":"RISC-V: Eliminate long-casts of X_add_number in diagnostics","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930103919.323690-1-christoph.muellner@vrull.eu/mbox/"},{"id":1590,"url":"https://patchwork.plctlab.org/api/1.2/patches/1590/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/DM6PR12MB4219C943049C6D883DEA3E55E7569@DM6PR12MB4219.namprd12.prod.outlook.com/","msgid":"","list_archive_url":null,"date":"2022-09-30T11:41:37","name":"[V2] Ignore DWARF debug information for -gsplit-dwarf with dwarf-5.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/DM6PR12MB4219C943049C6D883DEA3E55E7569@DM6PR12MB4219.namprd12.prod.outlook.com/mbox/"},{"id":1591,"url":"https://patchwork.plctlab.org/api/1.2/patches/1591/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c10321f9-d289-ef84-d263-bc278fb3d31b@suse.com/","msgid":"","list_archive_url":null,"date":"2022-09-30T11:59:04","name":"[1/4] RISC-V/gas: drop riscv_subsets static variable","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c10321f9-d289-ef84-d263-bc278fb3d31b@suse.com/mbox/"},{"id":1593,"url":"https://patchwork.plctlab.org/api/1.2/patches/1593/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3244eea0-c18c-e49a-4588-d69423130226@suse.com/","msgid":"<3244eea0-c18c-e49a-4588-d69423130226@suse.com>","list_archive_url":null,"date":"2022-09-30T11:59:23","name":"[2/4] RISC-V/gas: drop stray call to install_insn()","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3244eea0-c18c-e49a-4588-d69423130226@suse.com/mbox/"},{"id":1592,"url":"https://patchwork.plctlab.org/api/1.2/patches/1592/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/385d01fd-7e57-1f3f-1bae-30aa0c313d63@suse.com/","msgid":"<385d01fd-7e57-1f3f-1bae-30aa0c313d63@suse.com>","list_archive_url":null,"date":"2022-09-30T11:59:45","name":"[3/4] RISC-V/gas: don'\''t open-code insn_length()","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/385d01fd-7e57-1f3f-1bae-30aa0c313d63@suse.com/mbox/"},{"id":1594,"url":"https://patchwork.plctlab.org/api/1.2/patches/1594/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f5757acf-7b90-a0e3-5eea-3b97cc226930@suse.com/","msgid":"","list_archive_url":null,"date":"2022-09-30T12:00:12","name":"[4/4] RISC-V/gas: allow generating up to 176-bit instructions with .insn","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f5757acf-7b90-a0e3-5eea-3b97cc226930@suse.com/mbox/"},{"id":1596,"url":"https://patchwork.plctlab.org/api/1.2/patches/1596/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930140503.38233-1-chigot@adacore.com/","msgid":"<20220930140503.38233-1-chigot@adacore.com>","list_archive_url":null,"date":"2022-09-30T14:05:03","name":"ld/testsuite: consistently add board_ldflags when linking with GCC","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930140503.38233-1-chigot@adacore.com/mbox/"}],"public":true,"mbox":"https://patchwork.plctlab.org/bundle/snail/binutils-gdb_2022-09/mbox/"}]' + bundle_name=binutils-gdb_2022-10 ++ jq -rc '.[].name' ++ echo '[{"id":6,"url":"https://patchwork.plctlab.org/api/1.2/bundles/6/","web_url":"https://patchwork.plctlab.org/bundle/snail/binutils-gdb_2022-10/","project":{"id":2,"url":"https://patchwork.plctlab.org/api/1.2/projects/2/","name":"binutils-gdb","link_name":"binutils-gdb","list_id":"binutils.sourceware.org","list_email":"binutils@sourceware.org","web_url":"https://sourceware.org/mailman/listinfo/binutils","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"name":"binutils-gdb_2022-10","owner":{"id":1,"url":"https://patchwork.plctlab.org/api/1.2/users/1/","username":"snail","first_name":"","last_name":"","email":"wangliu@iscas.ac.cn"},"patches":[{"id":1592,"url":"https://patchwork.plctlab.org/api/1.2/patches/1592/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/385d01fd-7e57-1f3f-1bae-30aa0c313d63@suse.com/","msgid":"<385d01fd-7e57-1f3f-1bae-30aa0c313d63@suse.com>","list_archive_url":null,"date":"2022-09-30T11:59:45","name":"[3/4] RISC-V/gas: don'\''t open-code insn_length()","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/385d01fd-7e57-1f3f-1bae-30aa0c313d63@suse.com/mbox/"},{"id":1594,"url":"https://patchwork.plctlab.org/api/1.2/patches/1594/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f5757acf-7b90-a0e3-5eea-3b97cc226930@suse.com/","msgid":"","list_archive_url":null,"date":"2022-09-30T12:00:12","name":"[4/4] RISC-V/gas: allow generating up to 176-bit instructions with .insn","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f5757acf-7b90-a0e3-5eea-3b97cc226930@suse.com/mbox/"},{"id":1596,"url":"https://patchwork.plctlab.org/api/1.2/patches/1596/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930140503.38233-1-chigot@adacore.com/","msgid":"<20220930140503.38233-1-chigot@adacore.com>","list_archive_url":null,"date":"2022-09-30T14:05:03","name":"ld/testsuite: consistently add board_ldflags when linking with GCC","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930140503.38233-1-chigot@adacore.com/mbox/"},{"id":1619,"url":"https://patchwork.plctlab.org/api/1.2/patches/1619/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221001014451.532772-1-maskray@google.com/","msgid":"<20221001014451.532772-1-maskray@google.com>","list_archive_url":null,"date":"2022-10-01T01:44:51","name":"gold, dwp: support zstd compressed input debug sections [PR 29641]","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221001014451.532772-1-maskray@google.com/mbox/"},{"id":1620,"url":"https://patchwork.plctlab.org/api/1.2/patches/1620/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221001023846.590825-1-maskray@google.com/","msgid":"<20221001023846.590825-1-maskray@google.com>","list_archive_url":null,"date":"2022-10-01T02:38:46","name":"gold: add --compress-debug-sections=zstd [PR 29641]","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221001023846.590825-1-maskray@google.com/mbox/"},{"id":1623,"url":"https://patchwork.plctlab.org/api/1.2/patches/1623/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b4477c7f666bdeb7f8e998633c7b0cb62310b9ef.1664599545.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-01T04:45:52","name":"[RFC,1/1] RISC-V: Implement common register pair framework","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b4477c7f666bdeb7f8e998633c7b0cb62310b9ef.1664599545.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1625,"url":"https://patchwork.plctlab.org/api/1.2/patches/1625/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/53a265a1f14d17a6f7b106082f610994c5d546e0.1664602025.git.research_trasio@irq.a4lg.com/","msgid":"<53a265a1f14d17a6f7b106082f610994c5d546e0.1664602025.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-01T05:27:31","name":"[RFC,1/1] RISC-V: Implement extension variants","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/53a265a1f14d17a6f7b106082f610994c5d546e0.1664602025.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1626,"url":"https://patchwork.plctlab.org/api/1.2/patches/1626/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8db04962aba9c780f133840a8934353a58f223fe.1664602716.git.research_trasio@irq.a4lg.com/","msgid":"<8db04962aba9c780f133840a8934353a58f223fe.1664602716.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-01T05:39:26","name":"[1/1] RISC-V: Move supervisor instructions after all unprivileged ones","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8db04962aba9c780f133840a8934353a58f223fe.1664602716.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1627,"url":"https://patchwork.plctlab.org/api/1.2/patches/1627/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221001062057.681440-1-maskray@google.com/","msgid":"<20221001062057.681440-1-maskray@google.com>","list_archive_url":null,"date":"2022-10-01T06:20:57","name":"readelf: support zstd compressed debug sections [PR 29640]","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221001062057.681440-1-maskray@google.com/mbox/"},{"id":1631,"url":"https://patchwork.plctlab.org/api/1.2/patches/1631/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/619f112539c0bdecd58e25664f1250a3479a37f5.1664707612.git.aburgess@redhat.com/","msgid":"<619f112539c0bdecd58e25664f1250a3479a37f5.1664707612.git.aburgess@redhat.com>","list_archive_url":null,"date":"2022-10-02T10:47:52","name":"[PATCHv2,2/2] opcodes/arm: add disassembler styling for arm","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/619f112539c0bdecd58e25664f1250a3479a37f5.1664707612.git.aburgess@redhat.com/mbox/"},{"id":1635,"url":"https://patchwork.plctlab.org/api/1.2/patches/1635/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221002185433.gl7dvytfh5wthifx@lug-owl.de/","msgid":"<20221002185433.gl7dvytfh5wthifx@lug-owl.de>","list_archive_url":null,"date":"2022-10-02T18:54:33","name":"diagnostics.h: GCC 13 got -Wself-move, breaks GDB build","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221002185433.gl7dvytfh5wthifx@lug-owl.de/mbox/"},{"id":1637,"url":"https://patchwork.plctlab.org/api/1.2/patches/1637/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003014313.28766-1-mark@harmstone.com/","msgid":"<20221003014313.28766-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-03T01:43:12","name":"[1/2] ld: Add --pdb option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003014313.28766-1-mark@harmstone.com/mbox/"},{"id":1638,"url":"https://patchwork.plctlab.org/api/1.2/patches/1638/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003014313.28766-2-mark@harmstone.com/","msgid":"<20221003014313.28766-2-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-03T01:43:13","name":"[2/2] ld: Add minimal pdb generation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003014313.28766-2-mark@harmstone.com/mbox/"},{"id":1640,"url":"https://patchwork.plctlab.org/api/1.2/patches/1640/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/597ed978-d121-220c-b56b-2ffb94bd091c@suse.cz/","msgid":"<597ed978-d121-220c-b56b-2ffb94bd091c@suse.cz>","list_archive_url":null,"date":"2022-10-03T07:50:38","name":"[1/2] refactor usage of compressed_debug_section_type","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/597ed978-d121-220c-b56b-2ffb94bd091c@suse.cz/mbox/"},{"id":1641,"url":"https://patchwork.plctlab.org/api/1.2/patches/1641/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b8acdd83-f33a-74b8-e21a-23719a0b1a60@suse.cz/","msgid":"","list_archive_url":null,"date":"2022-10-03T07:50:44","name":"[2/2] add --enable-default-compressed-debug-sections-algorithm configure option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b8acdd83-f33a-74b8-e21a-23719a0b1a60@suse.cz/mbox/"},{"id":1642,"url":"https://patchwork.plctlab.org/api/1.2/patches/1642/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003101328.1790113-1-aburgess@redhat.com/","msgid":"<20221003101328.1790113-1-aburgess@redhat.com>","list_archive_url":null,"date":"2022-10-03T10:13:28","name":"opcodes/riscv: style csr names as registers","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003101328.1790113-1-aburgess@redhat.com/mbox/"},{"id":1643,"url":"https://patchwork.plctlab.org/api/1.2/patches/1643/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7ba14fc4472ce97d4f7a4433cad8a571e89f82f4.1664793840.git.research_trasio@irq.a4lg.com/","msgid":"<7ba14fc4472ce97d4f7a4433cad8a571e89f82f4.1664793840.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-03T10:43:59","name":"[v3,1/6] RISC-V: Fix immediates to have \"immediate\" style","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7ba14fc4472ce97d4f7a4433cad8a571e89f82f4.1664793840.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1644,"url":"https://patchwork.plctlab.org/api/1.2/patches/1644/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a498bec37c1fd1dcda57cbf95e5f8cfba09b31d3.1664793840.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-03T10:44:00","name":"[v3,2/6] RISC-V: Fix printf argument types corresponding %x","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a498bec37c1fd1dcda57cbf95e5f8cfba09b31d3.1664793840.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1647,"url":"https://patchwork.plctlab.org/api/1.2/patches/1647/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0002ea716713ace4998a33dde0b81f4f890d10bf.1664793840.git.research_trasio@irq.a4lg.com/","msgid":"<0002ea716713ace4998a33dde0b81f4f890d10bf.1664793840.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-03T10:44:01","name":"[v3,3/6] RISC-V: Optimize riscv_disassemble_data printf","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0002ea716713ace4998a33dde0b81f4f890d10bf.1664793840.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1646,"url":"https://patchwork.plctlab.org/api/1.2/patches/1646/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c65fc3e9aa58965d6768a28c9fd7467fea9897a5.1664793840.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-03T10:44:02","name":"[v3,4/6] RISC-V: Print comma and tabs as the \"text\" style","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c65fc3e9aa58965d6768a28c9fd7467fea9897a5.1664793840.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1648,"url":"https://patchwork.plctlab.org/api/1.2/patches/1648/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5abe1d8a7694417b990e11d8f6cd6789573872e5.1664793840.git.research_trasio@irq.a4lg.com/","msgid":"<5abe1d8a7694417b990e11d8f6cd6789573872e5.1664793840.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-03T10:44:03","name":"[v3,5/6] RISC-V: Fix T-Head immediate types on printing","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5abe1d8a7694417b990e11d8f6cd6789573872e5.1664793840.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1649,"url":"https://patchwork.plctlab.org/api/1.2/patches/1649/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0b68af932117258c908db62cf87c3a15d3cdec41.1664793840.git.research_trasio@irq.a4lg.com/","msgid":"<0b68af932117258c908db62cf87c3a15d3cdec41.1664793840.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-03T10:44:04","name":"[v3,6/6] RISC-V: Print XTheadMemPair literal as \"immediate\"","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0b68af932117258c908db62cf87c3a15d3cdec41.1664793840.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1656,"url":"https://patchwork.plctlab.org/api/1.2/patches/1656/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/87lepxcd6x.fsf@redhat.com/","msgid":"<87lepxcd6x.fsf@redhat.com>","list_archive_url":null,"date":"2022-10-03T12:19:02","name":"Commit: readelf: Do not load section data from offset 0","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/87lepxcd6x.fsf@redhat.com/mbox/"},{"id":1659,"url":"https://patchwork.plctlab.org/api/1.2/patches/1659/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e0d369d419da9c0441f415da7f54352aead8f655.1664707612.git.aburgess@redhat.com/","msgid":"","list_archive_url":null,"date":"2022-10-03T16:37:36","name":"[PATCHv2,1/2] opcodes/arm: use '\''@'\'' consistently for the comment character","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e0d369d419da9c0441f415da7f54352aead8f655.1664707612.git.aburgess@redhat.com/mbox/"},{"id":1660,"url":"https://patchwork.plctlab.org/api/1.2/patches/1660/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003165848.11142-1-palmer@rivosinc.com/","msgid":"<20221003165848.11142-1-palmer@rivosinc.com>","list_archive_url":null,"date":"2022-10-03T16:58:48","name":"gas: NEWS: Mention the T-Head extensions that were recently added","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003165848.11142-1-palmer@rivosinc.com/mbox/"},{"id":1671,"url":"https://patchwork.plctlab.org/api/1.2/patches/1671/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/YzvrMEdkXjIn5Lfz@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-04T08:13:36","name":"Support objcopy changing compression to or from zstd","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/YzvrMEdkXjIn5Lfz@squeak.grove.modra.org/mbox/"},{"id":1673,"url":"https://patchwork.plctlab.org/api/1.2/patches/1673/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0bc857d306bb7c8130e5328dbe6b9ed2fed3ef87.1664873933.git.research_trasio@irq.a4lg.com/","msgid":"<0bc857d306bb7c8130e5328dbe6b9ed2fed3ef87.1664873933.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-04T08:59:07","name":"[1/2] RISC-V: Fix buffer overflow on print_insn_riscv","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0bc857d306bb7c8130e5328dbe6b9ed2fed3ef87.1664873933.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1672,"url":"https://patchwork.plctlab.org/api/1.2/patches/1672/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/89612fe01d902007bf84a7dfb0df5f85d5c166e4.1664873933.git.research_trasio@irq.a4lg.com/","msgid":"<89612fe01d902007bf84a7dfb0df5f85d5c166e4.1664873933.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-04T08:59:08","name":"[2/2] gdb/riscv: Fix buffer overflow on riscv_insn::fetch_instruction","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/89612fe01d902007bf84a7dfb0df5f85d5c166e4.1664873933.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1676,"url":"https://patchwork.plctlab.org/api/1.2/patches/1676/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fc849c94f4adcac1c4ccc5508c7a145a2f13b2a9.1664876744.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-04T09:45:49","name":"[v2,1/2] RISC-V: Fix buffer overflow on print_insn_riscv","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fc849c94f4adcac1c4ccc5508c7a145a2f13b2a9.1664876744.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1677,"url":"https://patchwork.plctlab.org/api/1.2/patches/1677/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4eb6e59ae2e790dbbf2bc92477edd281648d8814.1664876744.git.research_trasio@irq.a4lg.com/","msgid":"<4eb6e59ae2e790dbbf2bc92477edd281648d8814.1664876744.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-04T09:45:50","name":"[v2,2/2] gdb/riscv: Partial support for instructions up to 176-bits","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4eb6e59ae2e790dbbf2bc92477edd281648d8814.1664876744.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1678,"url":"https://patchwork.plctlab.org/api/1.2/patches/1678/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ebf16f9e1f45115d0793952ccb4a94d4233303f9.1664882725.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-04T11:25:56","name":"[v3,1/2] RISC-V: Fix buffer overflow on print_insn_riscv","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ebf16f9e1f45115d0793952ccb4a94d4233303f9.1664882725.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1679,"url":"https://patchwork.plctlab.org/api/1.2/patches/1679/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/83464b09b8649525259c69c853dfa2c9575a204b.1664882725.git.research_trasio@irq.a4lg.com/","msgid":"<83464b09b8649525259c69c853dfa2c9575a204b.1664882725.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-04T11:25:57","name":"[v3,2/2] gdb/riscv: Partial support for instructions up to 176-bit","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/83464b09b8649525259c69c853dfa2c9575a204b.1664882725.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1681,"url":"https://patchwork.plctlab.org/api/1.2/patches/1681/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ffa9c1d7-e8c2-a62b-ef3e-b565c0ffbe5b@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-04T13:56:27","name":"RISC-V: Zicbo{m,p,z} adjustments to riscv_multi_subset_supports_ext()","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ffa9c1d7-e8c2-a62b-ef3e-b565c0ffbe5b@suse.com/mbox/"},{"id":1690,"url":"https://patchwork.plctlab.org/api/1.2/patches/1690/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221004161720.1963953-1-vladimir.mezentsev@oracle.com/","msgid":"<20221004161720.1963953-1-vladimir.mezentsev@oracle.com>","list_archive_url":null,"date":"2022-10-04T16:17:20","name":"gprofng: fix build with --enable-pgo-build=lto","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221004161720.1963953-1-vladimir.mezentsev@oracle.com/mbox/"},{"id":1691,"url":"https://patchwork.plctlab.org/api/1.2/patches/1691/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c0211bc9c57be6c79c6d878ce147f63b657f461d.camel@espressif.com/","msgid":"","list_archive_url":null,"date":"2022-10-04T16:22:05","name":"bfd: xtensa: fix __stop_SECTION literal drop,","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c0211bc9c57be6c79c6d878ce147f63b657f461d.camel@espressif.com/mbox/"},{"id":1702,"url":"https://patchwork.plctlab.org/api/1.2/patches/1702/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5f482299-6c60-b2b3-9abe-f4a55a5a26c5@univ-grenoble-alpes.fr/","msgid":"<5f482299-6c60-b2b3-9abe-f4a55a5a26c5@univ-grenoble-alpes.fr>","list_archive_url":null,"date":"2022-10-04T20:03:20","name":"[RFC] bfd: use bfd_vma for the 64-bit version of put[lb] and get[lb]","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5f482299-6c60-b2b3-9abe-f4a55a5a26c5@univ-grenoble-alpes.fr/mbox/"},{"id":1711,"url":"https://patchwork.plctlab.org/api/1.2/patches/1711/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Yz0Gsxdxe0TePbJT@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-05T04:23:15","name":"PR29647, objdump -S looping","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Yz0Gsxdxe0TePbJT@squeak.grove.modra.org/mbox/"},{"id":1712,"url":"https://patchwork.plctlab.org/api/1.2/patches/1712/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/02d747d2-f57b-0fb5-b893-842b6cc41f2f@suse.com/","msgid":"<02d747d2-f57b-0fb5-b893-842b6cc41f2f@suse.com>","list_archive_url":null,"date":"2022-10-05T07:20:47","name":"[v3,1/7] x86: constify parse_insn()'\''s input","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/02d747d2-f57b-0fb5-b893-842b6cc41f2f@suse.com/mbox/"},{"id":1713,"url":"https://patchwork.plctlab.org/api/1.2/patches/1713/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/925cb740-4e1b-abc4-8526-aaab6faae5e1@suse.com/","msgid":"<925cb740-4e1b-abc4-8526-aaab6faae5e1@suse.com>","list_archive_url":null,"date":"2022-10-05T07:22:19","name":"[v3,2/7] x86: introduce Pass2 insn attribute","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/925cb740-4e1b-abc4-8526-aaab6faae5e1@suse.com/mbox/"},{"id":1714,"url":"https://patchwork.plctlab.org/api/1.2/patches/1714/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e16d3e78-39ca-f715-508f-a4104b8ab9a9@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-05T07:23:51","name":"[v3,3/7] x86: re-work insn/suffix recognition","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e16d3e78-39ca-f715-508f-a4104b8ab9a9@suse.com/mbox/"},{"id":1715,"url":"https://patchwork.plctlab.org/api/1.2/patches/1715/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e4e4b80b-794c-7485-1997-685adab8fb27@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-05T07:24:20","name":"[v3,4/7] x86-64: further re-work insn/suffix recognition to also cover MOVSL","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e4e4b80b-794c-7485-1997-685adab8fb27@suse.com/mbox/"},{"id":1716,"url":"https://patchwork.plctlab.org/api/1.2/patches/1716/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/540678fc-8bff-ec68-c97c-478d2631998c@suse.com/","msgid":"<540678fc-8bff-ec68-c97c-478d2631998c@suse.com>","list_archive_url":null,"date":"2022-10-05T07:24:55","name":"[v3,5/7] ix86: don'\''t recognize/derive Q suffix in the common case","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/540678fc-8bff-ec68-c97c-478d2631998c@suse.com/mbox/"},{"id":1718,"url":"https://patchwork.plctlab.org/api/1.2/patches/1718/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e4692495-7d3d-074d-14f9-364d4a9a998c@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-05T07:25:25","name":"[v3,6/7] x86-64: allow HLE store of accumulator to absolute 32-bit address","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e4692495-7d3d-074d-14f9-364d4a9a998c@suse.com/mbox/"},{"id":1717,"url":"https://patchwork.plctlab.org/api/1.2/patches/1717/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e8014ebd-d16b-17a7-9f34-3700fc164136@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-05T07:25:57","name":"[v3,7/7] x86: move bad-use-of-TLS-reloc check","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e8014ebd-d16b-17a7-9f34-3700fc164136@suse.com/mbox/"},{"id":1719,"url":"https://patchwork.plctlab.org/api/1.2/patches/1719/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1266f001-4511-2662-dba9-14b4d0317c57@suse.com/","msgid":"<1266f001-4511-2662-dba9-14b4d0317c57@suse.com>","list_archive_url":null,"date":"2022-10-05T07:40:50","name":"x86: drop \"regmask\" static variable","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1266f001-4511-2662-dba9-14b4d0317c57@suse.com/mbox/"},{"id":1751,"url":"https://patchwork.plctlab.org/api/1.2/patches/1751/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/af45c5d57c221e43101c2aa38b14f4b4ac12d011.1665031170.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-06T04:40:15","name":"[v2,1/2] RISC-V: Fallback for instructions longer than 64b","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/af45c5d57c221e43101c2aa38b14f4b4ac12d011.1665031170.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1752,"url":"https://patchwork.plctlab.org/api/1.2/patches/1752/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c6e55781245dd3e8e9b8debd6130fc5449dfbd55.1665031170.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-06T04:40:16","name":"[v2,2/2] RISC-V: Improve \"bits undefined\" diagnostics","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c6e55781245dd3e8e9b8debd6130fc5449dfbd55.1665031170.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1776,"url":"https://patchwork.plctlab.org/api/1.2/patches/1776/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d52952119e15357c0e823f8a2398999359588b4d.1665050099.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-06T09:56:30","name":"[v3,1/2] RISC-V: Fallback for instructions longer than 64b","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d52952119e15357c0e823f8a2398999359588b4d.1665050099.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1777,"url":"https://patchwork.plctlab.org/api/1.2/patches/1777/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d907b1997f60ff7823c4a23e281ec9d8ddcbf3f1.1665050099.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-06T09:56:31","name":"[v3,2/2] RISC-V: Improve \"bits undefined\" diagnostics","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d907b1997f60ff7823c4a23e281ec9d8ddcbf3f1.1665050099.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1781,"url":"https://patchwork.plctlab.org/api/1.2/patches/1781/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221006114628.304185-1-chigot@adacore.com/","msgid":"<20221006114628.304185-1-chigot@adacore.com>","list_archive_url":null,"date":"2022-10-06T11:46:28","name":"RISC-V: fix linker message when relaxation deletes bytes","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221006114628.304185-1-chigot@adacore.com/mbox/"},{"id":1801,"url":"https://patchwork.plctlab.org/api/1.2/patches/1801/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Yz+Yhyg7UewC9/kp@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-07T03:09:59","name":"PR29653, objcopy/strip: fuzzed small input file induces large output file","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Yz+Yhyg7UewC9/kp@squeak.grove.modra.org/mbox/"},{"id":1803,"url":"https://patchwork.plctlab.org/api/1.2/patches/1803/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/PH1P110MB16505D9D39EC5B1DE22FE3D5EC5F9@PH1P110MB1650.NAMP110.PROD.OUTLOOK.COM/","msgid":"","list_archive_url":null,"date":"2022-10-07T04:10:07","name":"@CPP_FOR_BUILD@ problem since binutils-2.38","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/PH1P110MB16505D9D39EC5B1DE22FE3D5EC5F9@PH1P110MB1650.NAMP110.PROD.OUTLOOK.COM/mbox/"},{"id":1827,"url":"https://patchwork.plctlab.org/api/1.2/patches/1827/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8e13bce108ac10a0c1dd911e23ec572926f7ae44.1665203374.git.research_trasio@irq.a4lg.com/","msgid":"<8e13bce108ac10a0c1dd911e23ec572926f7ae44.1665203374.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-08T04:29:53","name":"[v2,1/1] RISC-V: Test DWARF register numbers for \"fp\"","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8e13bce108ac10a0c1dd911e23ec572926f7ae44.1665203374.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1828,"url":"https://patchwork.plctlab.org/api/1.2/patches/1828/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0883001b3572e54d3fba264429c7ade2adb66610.1665203441.git.research_trasio@irq.a4lg.com/","msgid":"<0883001b3572e54d3fba264429c7ade2adb66610.1665203441.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-08T04:31:15","name":"[1/1] RISC-V: Move standard hints before all instructions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0883001b3572e54d3fba264429c7ade2adb66610.1665203441.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1829,"url":"https://patchwork.plctlab.org/api/1.2/patches/1829/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/58e16a241d7376fcae2515c6bd5a2b41d275eeba.1665203531.git.research_trasio@irq.a4lg.com/","msgid":"<58e16a241d7376fcae2515c6bd5a2b41d275eeba.1665203531.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-08T04:32:18","name":"[RFC,1/1] RISC-V: Imply '\''Zicsr'\'' from privileged extensions with CSRs","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/58e16a241d7376fcae2515c6bd5a2b41d275eeba.1665203531.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1830,"url":"https://patchwork.plctlab.org/api/1.2/patches/1830/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/cb5076fc96e8f2097779a3abcde843dcdd660031.1665203660.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-08T04:34:23","name":"[1/5] opcodes/riscv-dis.c: Tidying with comments/clarity","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/cb5076fc96e8f2097779a3abcde843dcdd660031.1665203660.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1832,"url":"https://patchwork.plctlab.org/api/1.2/patches/1832/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1f1aa0838bf9c4f10a45fcfe3c682f7efc79d9ae.1665203660.git.research_trasio@irq.a4lg.com/","msgid":"<1f1aa0838bf9c4f10a45fcfe3c682f7efc79d9ae.1665203660.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-08T04:34:24","name":"[2/5] opcodes/riscv-dis.c: Tidying with spacing","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1f1aa0838bf9c4f10a45fcfe3c682f7efc79d9ae.1665203660.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1831,"url":"https://patchwork.plctlab.org/api/1.2/patches/1831/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/740bc5e2d2618d236519b39fedd1a1d7ae4e05da.1665203660.git.research_trasio@irq.a4lg.com/","msgid":"<740bc5e2d2618d236519b39fedd1a1d7ae4e05da.1665203660.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-08T04:34:25","name":"[3/5] opcodes/riscv-dis.c: Use bool type whenever possible","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/740bc5e2d2618d236519b39fedd1a1d7ae4e05da.1665203660.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1833,"url":"https://patchwork.plctlab.org/api/1.2/patches/1833/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6e3a9c235e317f441b4383b3daa68f2051bdc149.1665203660.git.research_trasio@irq.a4lg.com/","msgid":"<6e3a9c235e317f441b4383b3daa68f2051bdc149.1665203660.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-08T04:34:26","name":"[4/5] opcodes/riscv-dis.c: Make XLEN variable static","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6e3a9c235e317f441b4383b3daa68f2051bdc149.1665203660.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1834,"url":"https://patchwork.plctlab.org/api/1.2/patches/1834/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ad929233a62d887495122721340b2f9c80392963.1665203660.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-08T04:34:27","name":"[5/5] opcodes/riscv-dis.c: Remove last_map_state","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ad929233a62d887495122721340b2f9c80392963.1665203660.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1836,"url":"https://patchwork.plctlab.org/api/1.2/patches/1836/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d07e2b6f36ea2fd5830924a9bfeda941b774b687.1665290422.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-09T05:09:22","name":"RISC-V: Move certain arrays to riscv-opc.c","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d07e2b6f36ea2fd5830924a9bfeda941b774b687.1665290422.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1844,"url":"https://patchwork.plctlab.org/api/1.2/patches/1844/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010004623.16582-1-mark@harmstone.com/","msgid":"<20221010004623.16582-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-10T00:46:22","name":"[v2,1/2] ld: Add --pdb option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010004623.16582-1-mark@harmstone.com/mbox/"},{"id":1845,"url":"https://patchwork.plctlab.org/api/1.2/patches/1845/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010004623.16582-2-mark@harmstone.com/","msgid":"<20221010004623.16582-2-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-10T00:46:23","name":"[v2,2/2] ld: Add minimal pdb generation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010004623.16582-2-mark@harmstone.com/mbox/"},{"id":1890,"url":"https://patchwork.plctlab.org/api/1.2/patches/1890/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010200433.414320-1-vladimir.mezentsev@oracle.com/","msgid":"<20221010200433.414320-1-vladimir.mezentsev@oracle.com>","list_archive_url":null,"date":"2022-10-10T20:04:33","name":"gprofng: run tests without installation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010200433.414320-1-vladimir.mezentsev@oracle.com/mbox/"},{"id":1893,"url":"https://patchwork.plctlab.org/api/1.2/patches/1893/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010230426.719238-1-vladimir.mezentsev@oracle.com/","msgid":"<20221010230426.719238-1-vladimir.mezentsev@oracle.com>","list_archive_url":null,"date":"2022-10-10T23:04:26","name":"[2/2] gprofng: use the --libdir path to find libraries","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010230426.719238-1-vladimir.mezentsev@oracle.com/mbox/"},{"id":1894,"url":"https://patchwork.plctlab.org/api/1.2/patches/1894/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010235155.842469-1-vladimir.mezentsev@oracle.com/","msgid":"<20221010235155.842469-1-vladimir.mezentsev@oracle.com>","list_archive_url":null,"date":"2022-10-10T23:51:55","name":"[3/3] gprofng: no need to build version.texi","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010235155.842469-1-vladimir.mezentsev@oracle.com/mbox/"},{"id":1895,"url":"https://patchwork.plctlab.org/api/1.2/patches/1895/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011003702.4287-1-mark@harmstone.com/","msgid":"<20221011003702.4287-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-11T00:37:01","name":"[v3,1/2] ld: Add --pdb option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011003702.4287-1-mark@harmstone.com/mbox/"},{"id":1897,"url":"https://patchwork.plctlab.org/api/1.2/patches/1897/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011003702.4287-2-mark@harmstone.com/","msgid":"<20221011003702.4287-2-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-11T00:37:02","name":"[v3,2/2] ld: Add minimal pdb generation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011003702.4287-2-mark@harmstone.com/mbox/"},{"id":1928,"url":"https://patchwork.plctlab.org/api/1.2/patches/1928/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011175332.17156-1-mark@harmstone.com/","msgid":"<20221011175332.17156-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-11T17:53:31","name":"[v4,1/2] ld: Add --pdb option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011175332.17156-1-mark@harmstone.com/mbox/"},{"id":1929,"url":"https://patchwork.plctlab.org/api/1.2/patches/1929/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011175332.17156-2-mark@harmstone.com/","msgid":"<20221011175332.17156-2-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-11T17:53:32","name":"[v4,2/2] ld: Add minimal pdb generation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011175332.17156-2-mark@harmstone.com/mbox/"},{"id":1941,"url":"https://patchwork.plctlab.org/api/1.2/patches/1941/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221012031005.237446-1-simon.marchi@polymtl.ca/","msgid":"<20221012031005.237446-1-simon.marchi@polymtl.ca>","list_archive_url":null,"date":"2022-10-12T03:10:05","name":"[pushed] Re-apply \"Pass PKG_CONFIG_PATH down from top-level Makefile\"","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221012031005.237446-1-simon.marchi@polymtl.ca/mbox/"},{"id":1976,"url":"https://patchwork.plctlab.org/api/1.2/patches/1976/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1216a3f8-2273-8681-f528-9493a66891f0@suse.com/","msgid":"<1216a3f8-2273-8681-f528-9493a66891f0@suse.com>","list_archive_url":null,"date":"2022-10-13T08:16:49","name":"[v4,1/8] x86: constify parse_insn()'\''s input","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1216a3f8-2273-8681-f528-9493a66891f0@suse.com/mbox/"},{"id":1977,"url":"https://patchwork.plctlab.org/api/1.2/patches/1977/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/11599bbe-c779-aa9f-4d5d-c2243f0e69dc@suse.com/","msgid":"<11599bbe-c779-aa9f-4d5d-c2243f0e69dc@suse.com>","list_archive_url":null,"date":"2022-10-13T08:17:17","name":"[v4,2/8] x86: introduce Pass2 insn attribute","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/11599bbe-c779-aa9f-4d5d-c2243f0e69dc@suse.com/mbox/"},{"id":1978,"url":"https://patchwork.plctlab.org/api/1.2/patches/1978/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/357273a3-060c-23db-72da-3fc9d1be3d2a@suse.com/","msgid":"<357273a3-060c-23db-72da-3fc9d1be3d2a@suse.com>","list_archive_url":null,"date":"2022-10-13T08:18:09","name":"[v4,3/8] x86: re-work insn/suffix recognition","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/357273a3-060c-23db-72da-3fc9d1be3d2a@suse.com/mbox/"},{"id":1979,"url":"https://patchwork.plctlab.org/api/1.2/patches/1979/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0ec0587f-6a7b-45b6-8346-e5d774e73636@suse.com/","msgid":"<0ec0587f-6a7b-45b6-8346-e5d774e73636@suse.com>","list_archive_url":null,"date":"2022-10-13T08:18:39","name":"[v4,4/8] x86-64: further re-work insn/suffix recognition to also cover MOVSL","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0ec0587f-6a7b-45b6-8346-e5d774e73636@suse.com/mbox/"},{"id":1980,"url":"https://patchwork.plctlab.org/api/1.2/patches/1980/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fb617d0b-8759-3169-5a65-1178b7fef3d7@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-13T08:19:34","name":"[v4,5/8] ix86: don'\''t recognize/derive Q suffix in the common case","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fb617d0b-8759-3169-5a65-1178b7fef3d7@suse.com/mbox/"},{"id":1981,"url":"https://patchwork.plctlab.org/api/1.2/patches/1981/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1df3bd01-99c5-f56c-d937-970edd42b2b8@suse.com/","msgid":"<1df3bd01-99c5-f56c-d937-970edd42b2b8@suse.com>","list_archive_url":null,"date":"2022-10-13T08:20:14","name":"[v4,6/8] x86-64: allow HLE store of accumulator to absolute 32-bit address","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1df3bd01-99c5-f56c-d937-970edd42b2b8@suse.com/mbox/"},{"id":1982,"url":"https://patchwork.plctlab.org/api/1.2/patches/1982/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8486a218-39ec-16b2-5c6c-5037196b93cf@suse.com/","msgid":"<8486a218-39ec-16b2-5c6c-5037196b93cf@suse.com>","list_archive_url":null,"date":"2022-10-13T08:21:00","name":"[v4,7/8] x86: move bad-use-of-TLS-reloc check","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8486a218-39ec-16b2-5c6c-5037196b93cf@suse.com/mbox/"},{"id":1983,"url":"https://patchwork.plctlab.org/api/1.2/patches/1983/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7d82692d-93df-fbee-9efb-2f44e8a91df3@suse.com/","msgid":"<7d82692d-93df-fbee-9efb-2f44e8a91df3@suse.com>","list_archive_url":null,"date":"2022-10-13T08:22:00","name":"[v4,8/8] x86: drop (now) stray IsString","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7d82692d-93df-fbee-9efb-2f44e8a91df3@suse.com/mbox/"},{"id":2013,"url":"https://patchwork.plctlab.org/api/1.2/patches/2013/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8ab93d7a617ad480dd786210f46db0e5aa07d1ac.1665655719.git.research_trasio@irq.a4lg.com/","msgid":"<8ab93d7a617ad480dd786210f46db0e5aa07d1ac.1665655719.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-13T10:11:41","name":"include: Declare getopt function on old GNU libc","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8ab93d7a617ad480dd786210f46db0e5aa07d1ac.1665655719.git.research_trasio@irq.a4lg.com/mbox/"},{"id":2352,"url":"https://patchwork.plctlab.org/api/1.2/patches/2352/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221013201332.2747246-1-maskray@google.com/","msgid":"<20221013201332.2747246-1-maskray@google.com>","list_archive_url":null,"date":"2022-10-13T20:13:32","name":"ld: Add --undefined-version","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221013201332.2747246-1-maskray@google.com/mbox/"},{"id":2532,"url":"https://patchwork.plctlab.org/api/1.2/patches/2532/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014063520.1428330-2-zengxiao@eswincomputing.com/","msgid":"<20221014063520.1428330-2-zengxiao@eswincomputing.com>","list_archive_url":null,"date":"2022-10-14T06:35:20","name":"[1/1] RISC-V: Make R_RISCV_SUB6 conforms to riscv abi standard","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014063520.1428330-2-zengxiao@eswincomputing.com/mbox/"},{"id":2560,"url":"https://patchwork.plctlab.org/api/1.2/patches/2560/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/027ae69a-636b-6757-297a-eec42936401e@linaro.org/","msgid":"<027ae69a-636b-6757-297a-eec42936401e@linaro.org>","list_archive_url":null,"date":"2022-10-14T07:58:22","name":"[v3] aarch64-pe support for LD, GAS and BFD","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/027ae69a-636b-6757-297a-eec42936401e@linaro.org/mbox/"},{"id":2602,"url":"https://patchwork.plctlab.org/api/1.2/patches/2602/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-2-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-2-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:39","name":"[01/10] Support Intel AVX-IFMA","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-2-haochen.jiang@intel.com/mbox/"},{"id":2608,"url":"https://patchwork.plctlab.org/api/1.2/patches/2608/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-3-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-3-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:40","name":"[02/10] Support Intel AVX-VNNI-INT8","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-3-haochen.jiang@intel.com/mbox/"},{"id":2611,"url":"https://patchwork.plctlab.org/api/1.2/patches/2611/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-4-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-4-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:41","name":"[03/10] Support Intel AVX-NE-CONVERT","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-4-haochen.jiang@intel.com/mbox/"},{"id":2610,"url":"https://patchwork.plctlab.org/api/1.2/patches/2610/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-5-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-5-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:42","name":"[04/10] Support Intel CMPccXADD","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-5-haochen.jiang@intel.com/mbox/"},{"id":2601,"url":"https://patchwork.plctlab.org/api/1.2/patches/2601/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-6-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-6-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:43","name":"[05/10] Add handler for more i386_cpu_flags","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-6-haochen.jiang@intel.com/mbox/"},{"id":2606,"url":"https://patchwork.plctlab.org/api/1.2/patches/2606/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-7-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-7-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:44","name":"[06/10] Support Intel RAO-INT","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-7-haochen.jiang@intel.com/mbox/"},{"id":2609,"url":"https://patchwork.plctlab.org/api/1.2/patches/2609/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-8-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-8-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:45","name":"[07/10] Support Intel WRMSRNS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-8-haochen.jiang@intel.com/mbox/"},{"id":2605,"url":"https://patchwork.plctlab.org/api/1.2/patches/2605/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-9-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-9-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:46","name":"[08/10] Support Intel MSRLIST","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-9-haochen.jiang@intel.com/mbox/"},{"id":2607,"url":"https://patchwork.plctlab.org/api/1.2/patches/2607/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-10-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-10-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:47","name":"[09/10] Support Intel AMX-FP16","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-10-haochen.jiang@intel.com/mbox/"},{"id":2604,"url":"https://patchwork.plctlab.org/api/1.2/patches/2604/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-11-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-11-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:48","name":"[10/10] Support Intel PREFETCHI","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-11-haochen.jiang@intel.com/mbox/"},{"id":2643,"url":"https://patchwork.plctlab.org/api/1.2/patches/2643/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7bac66be-535e-9051-d674-f2f5ba180e17@suse.com/","msgid":"<7bac66be-535e-9051-d674-f2f5ba180e17@suse.com>","list_archive_url":null,"date":"2022-10-14T10:22:34","name":"x86: fold AVX512-VNNI disassembler entries with AVX-VNNI ones","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7bac66be-535e-9051-d674-f2f5ba180e17@suse.com/mbox/"},{"id":2654,"url":"https://patchwork.plctlab.org/api/1.2/patches/2654/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0lIo5+ncY/MqBEq@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-14T11:31:47","name":"PR29677, Field `the_bfd` of `asymbol` is uninitialised","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0lIo5+ncY/MqBEq@squeak.grove.modra.org/mbox/"},{"id":2656,"url":"https://patchwork.plctlab.org/api/1.2/patches/2656/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0lJksn49ZpABY89@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-14T11:35:46","name":"e200 LSP support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0lJksn49ZpABY89@squeak.grove.modra.org/mbox/"},{"id":2657,"url":"https://patchwork.plctlab.org/api/1.2/patches/2657/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0lJxxYoeD5iDYAD@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-14T11:36:39","name":"PowerPC SPE disassembly and tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0lJxxYoeD5iDYAD@squeak.grove.modra.org/mbox/"},{"id":2695,"url":"https://patchwork.plctlab.org/api/1.2/patches/2695/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/DM6PR12MB4219611F6CC2A0702884A602E7249@DM6PR12MB4219.namprd12.prod.outlook.com/","msgid":"","list_archive_url":null,"date":"2022-10-14T13:29:40","name":"Binutils: Adding new testcase for addr2line.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/DM6PR12MB4219611F6CC2A0702884A602E7249@DM6PR12MB4219.namprd12.prod.outlook.com/mbox/"},{"id":2700,"url":"https://patchwork.plctlab.org/api/1.2/patches/2700/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9fd2c88d-98b2-99a4-419f-c7235b2cf960@suse.com/","msgid":"<9fd2c88d-98b2-99a4-419f-c7235b2cf960@suse.com>","list_archive_url":null,"date":"2022-10-14T14:11:35","name":"x86: properly decode EVEX.W for AVX512_4{FMAPS,VNNIW} insns","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9fd2c88d-98b2-99a4-419f-c7235b2cf960@suse.com/mbox/"},{"id":2981,"url":"https://patchwork.plctlab.org/api/1.2/patches/2981/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0uLzalqjm4C87GN@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-16T04:42:53","name":"PowerPC se_rfmci and VLE, SPE2 and LSP insns with -many","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0uLzalqjm4C87GN@squeak.grove.modra.org/mbox/"},{"id":3152,"url":"https://patchwork.plctlab.org/api/1.2/patches/3152/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221016232419.1135-1-mark@harmstone.com/","msgid":"<20221016232419.1135-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-16T23:24:18","name":"[v5,1/2] ld: Add --pdb option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221016232419.1135-1-mark@harmstone.com/mbox/"},{"id":3151,"url":"https://patchwork.plctlab.org/api/1.2/patches/3151/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221016232419.1135-2-mark@harmstone.com/","msgid":"<20221016232419.1135-2-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-16T23:24:19","name":"[v5,2/2] ld: Add minimal pdb generation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221016232419.1135-2-mark@harmstone.com/mbox/"},{"id":3258,"url":"https://patchwork.plctlab.org/api/1.2/patches/3258/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/19c08747-fa5b-1e67-3dd2-c891a2c0c1fa@suse.com/","msgid":"<19c08747-fa5b-1e67-3dd2-c891a2c0c1fa@suse.com>","list_archive_url":null,"date":"2022-10-17T07:44:51","name":"x86: correct CPU_AMX_{BF16,INT8}_FLAGS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/19c08747-fa5b-1e67-3dd2-c891a2c0c1fa@suse.com/mbox/"},{"id":3272,"url":"https://patchwork.plctlab.org/api/1.2/patches/3272/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/85dd526c-d3a7-72dc-5444-ed5573eebec1@suse.com/","msgid":"<85dd526c-d3a7-72dc-5444-ed5573eebec1@suse.com>","list_archive_url":null,"date":"2022-10-17T08:30:12","name":"x86: generalize gas documentation for disabling of ISA extensions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/85dd526c-d3a7-72dc-5444-ed5573eebec1@suse.com/mbox/"},{"id":3759,"url":"https://patchwork.plctlab.org/api/1.2/patches/3759/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-2-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-2-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:15:58","name":"[V2,01/15] sframe.h: Add SFrame format definition","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-2-indu.bhagat@oracle.com/mbox/"},{"id":3762,"url":"https://patchwork.plctlab.org/api/1.2/patches/3762/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-3-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-3-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:15:59","name":"[V2,02/15] gas: add new command line option --gsframe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-3-indu.bhagat@oracle.com/mbox/"},{"id":3761,"url":"https://patchwork.plctlab.org/api/1.2/patches/3761/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-4-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-4-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:00","name":"[V2,03/15] gas: generate .sframe from CFI directives","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-4-indu.bhagat@oracle.com/mbox/"},{"id":3760,"url":"https://patchwork.plctlab.org/api/1.2/patches/3760/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-5-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-5-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:01","name":"[V2,04/15] gas: testsuite: add new tests for SFrame unwind info","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-5-indu.bhagat@oracle.com/mbox/"},{"id":3764,"url":"https://patchwork.plctlab.org/api/1.2/patches/3764/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-6-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-6-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:02","name":"[V2,05/15] libsframe: add the SFrame library","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-6-indu.bhagat@oracle.com/mbox/"},{"id":3763,"url":"https://patchwork.plctlab.org/api/1.2/patches/3763/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-8-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-8-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:04","name":"[V2,07/15] readelf/objdump: support for SFrame section","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-8-indu.bhagat@oracle.com/mbox/"}],"public":true,"mbox":"https://patchwork.plctlab.org/bundle/snail/binutils-gdb_2022-10/mbox/"},{"id":7,"url":"https://patchwork.plctlab.org/api/1.2/bundles/7/","web_url":"https://patchwork.plctlab.org/bundle/snail/binutils-gdb_2022-09/","project":{"id":2,"url":"https://patchwork.plctlab.org/api/1.2/projects/2/","name":"binutils-gdb","link_name":"binutils-gdb","list_id":"binutils.sourceware.org","list_email":"binutils@sourceware.org","web_url":"https://sourceware.org/mailman/listinfo/binutils","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"name":"binutils-gdb_2022-09","owner":{"id":1,"url":"https://patchwork.plctlab.org/api/1.2/users/1/","username":"snail","first_name":"","last_name":"","email":"wangliu@iscas.ac.cn"},"patches":[{"id":1573,"url":"https://patchwork.plctlab.org/api/1.2/patches/1573/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930073211.2634-1-jiawei@iscas.ac.cn/","msgid":"<20220930073211.2634-1-jiawei@iscas.ac.cn>","list_archive_url":null,"date":"2022-09-30T07:32:11","name":"[V2] RISC-V: Add Smepmp CSR '\''mseccfg'\'' define and testcases.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930073211.2634-1-jiawei@iscas.ac.cn/mbox/"},{"id":1577,"url":"https://patchwork.plctlab.org/api/1.2/patches/1577/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/76fa0c3c-2303-ebdf-a765-ac4731581517@suse.com/","msgid":"<76fa0c3c-2303-ebdf-a765-ac4731581517@suse.com>","list_archive_url":null,"date":"2022-09-30T08:54:18","name":"objcopy: avoid \"shadowing\" of remove() function name","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/76fa0c3c-2303-ebdf-a765-ac4731581517@suse.com/mbox/"},{"id":1579,"url":"https://patchwork.plctlab.org/api/1.2/patches/1579/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930085852.71213-1-nelson@rivosinc.com/","msgid":"<20220930085852.71213-1-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-09-30T08:58:51","name":"[1/2] RISC-V: Output mapping symbols with ISA string.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930085852.71213-1-nelson@rivosinc.com/mbox/"},{"id":1578,"url":"https://patchwork.plctlab.org/api/1.2/patches/1578/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930085852.71213-2-nelson@rivosinc.com/","msgid":"<20220930085852.71213-2-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-09-30T08:58:52","name":"[2/2] RISC-V: Refer mapping symbol to R_RISCV_RELAX for rvc relaxations.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930085852.71213-2-nelson@rivosinc.com/mbox/"},{"id":1581,"url":"https://patchwork.plctlab.org/api/1.2/patches/1581/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930092058.71286-1-nelson@rivosinc.com/","msgid":"<20220930092058.71286-1-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-09-30T09:20:57","name":"[1/2] RISC-V: Output mapping symbols with ISA string.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930092058.71286-1-nelson@rivosinc.com/mbox/"},{"id":1580,"url":"https://patchwork.plctlab.org/api/1.2/patches/1580/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930092058.71286-2-nelson@rivosinc.com/","msgid":"<20220930092058.71286-2-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-09-30T09:20:58","name":"[2/2] RISC-V: Refer mapping symbol to R_RISCV_RELAX for rvc relaxations.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930092058.71286-2-nelson@rivosinc.com/mbox/"},{"id":1582,"url":"https://patchwork.plctlab.org/api/1.2/patches/1582/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5874dd79-0cf5-d65c-7ea2-13adfc799c0f@suse.com/","msgid":"<5874dd79-0cf5-d65c-7ea2-13adfc799c0f@suse.com>","list_archive_url":null,"date":"2022-09-30T09:41:29","name":"RISC-V: fix build after \"Add support for arbitrary immediate encoding formats\"","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5874dd79-0cf5-d65c-7ea2-13adfc799c0f@suse.com/mbox/"},{"id":1583,"url":"https://patchwork.plctlab.org/api/1.2/patches/1583/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/57d8ac2a-5757-3776-9924-99c17ca69938@suse.com/","msgid":"<57d8ac2a-5757-3776-9924-99c17ca69938@suse.com>","list_archive_url":null,"date":"2022-09-30T09:42:08","name":"RISC-V: fallout from \"re-arrange opcode table for consistent alias handling\"","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/57d8ac2a-5757-3776-9924-99c17ca69938@suse.com/mbox/"},{"id":1584,"url":"https://patchwork.plctlab.org/api/1.2/patches/1584/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e76ef8f7-72b9-5103-cb43-9608af01d017@suse.com/","msgid":"","list_archive_url":null,"date":"2022-09-30T09:42:50","name":"RISC-V: don'\''t cast expressions'\'' X_add_number to long in diagnostics","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e76ef8f7-72b9-5103-cb43-9608af01d017@suse.com/mbox/"},{"id":1585,"url":"https://patchwork.plctlab.org/api/1.2/patches/1585/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/61355429-24b3-17d0-ab03-6fa57ee861d5@suse.cz/","msgid":"<61355429-24b3-17d0-ab03-6fa57ee861d5@suse.cz>","list_archive_url":null,"date":"2022-09-30T09:48:52","name":"[RFC] add --enable-zstd-compressed-debug-sections configure option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/61355429-24b3-17d0-ab03-6fa57ee861d5@suse.cz/mbox/"},{"id":1586,"url":"https://patchwork.plctlab.org/api/1.2/patches/1586/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930103919.323690-1-christoph.muellner@vrull.eu/","msgid":"<20220930103919.323690-1-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2022-09-30T10:39:19","name":"RISC-V: Eliminate long-casts of X_add_number in diagnostics","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930103919.323690-1-christoph.muellner@vrull.eu/mbox/"},{"id":1590,"url":"https://patchwork.plctlab.org/api/1.2/patches/1590/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/DM6PR12MB4219C943049C6D883DEA3E55E7569@DM6PR12MB4219.namprd12.prod.outlook.com/","msgid":"","list_archive_url":null,"date":"2022-09-30T11:41:37","name":"[V2] Ignore DWARF debug information for -gsplit-dwarf with dwarf-5.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/DM6PR12MB4219C943049C6D883DEA3E55E7569@DM6PR12MB4219.namprd12.prod.outlook.com/mbox/"},{"id":1591,"url":"https://patchwork.plctlab.org/api/1.2/patches/1591/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c10321f9-d289-ef84-d263-bc278fb3d31b@suse.com/","msgid":"","list_archive_url":null,"date":"2022-09-30T11:59:04","name":"[1/4] RISC-V/gas: drop riscv_subsets static variable","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c10321f9-d289-ef84-d263-bc278fb3d31b@suse.com/mbox/"},{"id":1593,"url":"https://patchwork.plctlab.org/api/1.2/patches/1593/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3244eea0-c18c-e49a-4588-d69423130226@suse.com/","msgid":"<3244eea0-c18c-e49a-4588-d69423130226@suse.com>","list_archive_url":null,"date":"2022-09-30T11:59:23","name":"[2/4] RISC-V/gas: drop stray call to install_insn()","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3244eea0-c18c-e49a-4588-d69423130226@suse.com/mbox/"},{"id":1592,"url":"https://patchwork.plctlab.org/api/1.2/patches/1592/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/385d01fd-7e57-1f3f-1bae-30aa0c313d63@suse.com/","msgid":"<385d01fd-7e57-1f3f-1bae-30aa0c313d63@suse.com>","list_archive_url":null,"date":"2022-09-30T11:59:45","name":"[3/4] RISC-V/gas: don'\''t open-code insn_length()","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/385d01fd-7e57-1f3f-1bae-30aa0c313d63@suse.com/mbox/"},{"id":1594,"url":"https://patchwork.plctlab.org/api/1.2/patches/1594/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f5757acf-7b90-a0e3-5eea-3b97cc226930@suse.com/","msgid":"","list_archive_url":null,"date":"2022-09-30T12:00:12","name":"[4/4] RISC-V/gas: allow generating up to 176-bit instructions with .insn","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f5757acf-7b90-a0e3-5eea-3b97cc226930@suse.com/mbox/"},{"id":1596,"url":"https://patchwork.plctlab.org/api/1.2/patches/1596/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930140503.38233-1-chigot@adacore.com/","msgid":"<20220930140503.38233-1-chigot@adacore.com>","list_archive_url":null,"date":"2022-09-30T14:05:03","name":"ld/testsuite: consistently add board_ldflags when linking with GCC","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930140503.38233-1-chigot@adacore.com/mbox/"}],"public":true,"mbox":"https://patchwork.plctlab.org/bundle/snail/binutils-gdb_2022-09/mbox/"}]' + bundle_name_list='binutils-gdb_2022-10 binutils-gdb_2022-09' + [[ binutils-gdb_2022-10 binutils-gdb_2022-09 =~ 2022-10 ]] ++ jq -rc --arg bundle_name binutils-gdb_2022-10 '.[] | select(.name==$bundle_name) | (.id|tostring)' ++ echo '[{"id":6,"url":"https://patchwork.plctlab.org/api/1.2/bundles/6/","web_url":"https://patchwork.plctlab.org/bundle/snail/binutils-gdb_2022-10/","project":{"id":2,"url":"https://patchwork.plctlab.org/api/1.2/projects/2/","name":"binutils-gdb","link_name":"binutils-gdb","list_id":"binutils.sourceware.org","list_email":"binutils@sourceware.org","web_url":"https://sourceware.org/mailman/listinfo/binutils","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"name":"binutils-gdb_2022-10","owner":{"id":1,"url":"https://patchwork.plctlab.org/api/1.2/users/1/","username":"snail","first_name":"","last_name":"","email":"wangliu@iscas.ac.cn"},"patches":[{"id":1592,"url":"https://patchwork.plctlab.org/api/1.2/patches/1592/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/385d01fd-7e57-1f3f-1bae-30aa0c313d63@suse.com/","msgid":"<385d01fd-7e57-1f3f-1bae-30aa0c313d63@suse.com>","list_archive_url":null,"date":"2022-09-30T11:59:45","name":"[3/4] RISC-V/gas: don'\''t open-code insn_length()","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/385d01fd-7e57-1f3f-1bae-30aa0c313d63@suse.com/mbox/"},{"id":1594,"url":"https://patchwork.plctlab.org/api/1.2/patches/1594/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f5757acf-7b90-a0e3-5eea-3b97cc226930@suse.com/","msgid":"","list_archive_url":null,"date":"2022-09-30T12:00:12","name":"[4/4] RISC-V/gas: allow generating up to 176-bit instructions with .insn","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f5757acf-7b90-a0e3-5eea-3b97cc226930@suse.com/mbox/"},{"id":1596,"url":"https://patchwork.plctlab.org/api/1.2/patches/1596/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930140503.38233-1-chigot@adacore.com/","msgid":"<20220930140503.38233-1-chigot@adacore.com>","list_archive_url":null,"date":"2022-09-30T14:05:03","name":"ld/testsuite: consistently add board_ldflags when linking with GCC","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930140503.38233-1-chigot@adacore.com/mbox/"},{"id":1619,"url":"https://patchwork.plctlab.org/api/1.2/patches/1619/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221001014451.532772-1-maskray@google.com/","msgid":"<20221001014451.532772-1-maskray@google.com>","list_archive_url":null,"date":"2022-10-01T01:44:51","name":"gold, dwp: support zstd compressed input debug sections [PR 29641]","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221001014451.532772-1-maskray@google.com/mbox/"},{"id":1620,"url":"https://patchwork.plctlab.org/api/1.2/patches/1620/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221001023846.590825-1-maskray@google.com/","msgid":"<20221001023846.590825-1-maskray@google.com>","list_archive_url":null,"date":"2022-10-01T02:38:46","name":"gold: add --compress-debug-sections=zstd [PR 29641]","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221001023846.590825-1-maskray@google.com/mbox/"},{"id":1623,"url":"https://patchwork.plctlab.org/api/1.2/patches/1623/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b4477c7f666bdeb7f8e998633c7b0cb62310b9ef.1664599545.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-01T04:45:52","name":"[RFC,1/1] RISC-V: Implement common register pair framework","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b4477c7f666bdeb7f8e998633c7b0cb62310b9ef.1664599545.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1625,"url":"https://patchwork.plctlab.org/api/1.2/patches/1625/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/53a265a1f14d17a6f7b106082f610994c5d546e0.1664602025.git.research_trasio@irq.a4lg.com/","msgid":"<53a265a1f14d17a6f7b106082f610994c5d546e0.1664602025.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-01T05:27:31","name":"[RFC,1/1] RISC-V: Implement extension variants","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/53a265a1f14d17a6f7b106082f610994c5d546e0.1664602025.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1626,"url":"https://patchwork.plctlab.org/api/1.2/patches/1626/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8db04962aba9c780f133840a8934353a58f223fe.1664602716.git.research_trasio@irq.a4lg.com/","msgid":"<8db04962aba9c780f133840a8934353a58f223fe.1664602716.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-01T05:39:26","name":"[1/1] RISC-V: Move supervisor instructions after all unprivileged ones","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8db04962aba9c780f133840a8934353a58f223fe.1664602716.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1627,"url":"https://patchwork.plctlab.org/api/1.2/patches/1627/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221001062057.681440-1-maskray@google.com/","msgid":"<20221001062057.681440-1-maskray@google.com>","list_archive_url":null,"date":"2022-10-01T06:20:57","name":"readelf: support zstd compressed debug sections [PR 29640]","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221001062057.681440-1-maskray@google.com/mbox/"},{"id":1631,"url":"https://patchwork.plctlab.org/api/1.2/patches/1631/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/619f112539c0bdecd58e25664f1250a3479a37f5.1664707612.git.aburgess@redhat.com/","msgid":"<619f112539c0bdecd58e25664f1250a3479a37f5.1664707612.git.aburgess@redhat.com>","list_archive_url":null,"date":"2022-10-02T10:47:52","name":"[PATCHv2,2/2] opcodes/arm: add disassembler styling for arm","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/619f112539c0bdecd58e25664f1250a3479a37f5.1664707612.git.aburgess@redhat.com/mbox/"},{"id":1635,"url":"https://patchwork.plctlab.org/api/1.2/patches/1635/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221002185433.gl7dvytfh5wthifx@lug-owl.de/","msgid":"<20221002185433.gl7dvytfh5wthifx@lug-owl.de>","list_archive_url":null,"date":"2022-10-02T18:54:33","name":"diagnostics.h: GCC 13 got -Wself-move, breaks GDB build","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221002185433.gl7dvytfh5wthifx@lug-owl.de/mbox/"},{"id":1637,"url":"https://patchwork.plctlab.org/api/1.2/patches/1637/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003014313.28766-1-mark@harmstone.com/","msgid":"<20221003014313.28766-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-03T01:43:12","name":"[1/2] ld: Add --pdb option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003014313.28766-1-mark@harmstone.com/mbox/"},{"id":1638,"url":"https://patchwork.plctlab.org/api/1.2/patches/1638/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003014313.28766-2-mark@harmstone.com/","msgid":"<20221003014313.28766-2-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-03T01:43:13","name":"[2/2] ld: Add minimal pdb generation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003014313.28766-2-mark@harmstone.com/mbox/"},{"id":1640,"url":"https://patchwork.plctlab.org/api/1.2/patches/1640/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/597ed978-d121-220c-b56b-2ffb94bd091c@suse.cz/","msgid":"<597ed978-d121-220c-b56b-2ffb94bd091c@suse.cz>","list_archive_url":null,"date":"2022-10-03T07:50:38","name":"[1/2] refactor usage of compressed_debug_section_type","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/597ed978-d121-220c-b56b-2ffb94bd091c@suse.cz/mbox/"},{"id":1641,"url":"https://patchwork.plctlab.org/api/1.2/patches/1641/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b8acdd83-f33a-74b8-e21a-23719a0b1a60@suse.cz/","msgid":"","list_archive_url":null,"date":"2022-10-03T07:50:44","name":"[2/2] add --enable-default-compressed-debug-sections-algorithm configure option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/b8acdd83-f33a-74b8-e21a-23719a0b1a60@suse.cz/mbox/"},{"id":1642,"url":"https://patchwork.plctlab.org/api/1.2/patches/1642/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003101328.1790113-1-aburgess@redhat.com/","msgid":"<20221003101328.1790113-1-aburgess@redhat.com>","list_archive_url":null,"date":"2022-10-03T10:13:28","name":"opcodes/riscv: style csr names as registers","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003101328.1790113-1-aburgess@redhat.com/mbox/"},{"id":1643,"url":"https://patchwork.plctlab.org/api/1.2/patches/1643/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7ba14fc4472ce97d4f7a4433cad8a571e89f82f4.1664793840.git.research_trasio@irq.a4lg.com/","msgid":"<7ba14fc4472ce97d4f7a4433cad8a571e89f82f4.1664793840.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-03T10:43:59","name":"[v3,1/6] RISC-V: Fix immediates to have \"immediate\" style","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7ba14fc4472ce97d4f7a4433cad8a571e89f82f4.1664793840.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1644,"url":"https://patchwork.plctlab.org/api/1.2/patches/1644/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a498bec37c1fd1dcda57cbf95e5f8cfba09b31d3.1664793840.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-03T10:44:00","name":"[v3,2/6] RISC-V: Fix printf argument types corresponding %x","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/a498bec37c1fd1dcda57cbf95e5f8cfba09b31d3.1664793840.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1647,"url":"https://patchwork.plctlab.org/api/1.2/patches/1647/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0002ea716713ace4998a33dde0b81f4f890d10bf.1664793840.git.research_trasio@irq.a4lg.com/","msgid":"<0002ea716713ace4998a33dde0b81f4f890d10bf.1664793840.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-03T10:44:01","name":"[v3,3/6] RISC-V: Optimize riscv_disassemble_data printf","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0002ea716713ace4998a33dde0b81f4f890d10bf.1664793840.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1646,"url":"https://patchwork.plctlab.org/api/1.2/patches/1646/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c65fc3e9aa58965d6768a28c9fd7467fea9897a5.1664793840.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-03T10:44:02","name":"[v3,4/6] RISC-V: Print comma and tabs as the \"text\" style","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c65fc3e9aa58965d6768a28c9fd7467fea9897a5.1664793840.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1648,"url":"https://patchwork.plctlab.org/api/1.2/patches/1648/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5abe1d8a7694417b990e11d8f6cd6789573872e5.1664793840.git.research_trasio@irq.a4lg.com/","msgid":"<5abe1d8a7694417b990e11d8f6cd6789573872e5.1664793840.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-03T10:44:03","name":"[v3,5/6] RISC-V: Fix T-Head immediate types on printing","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5abe1d8a7694417b990e11d8f6cd6789573872e5.1664793840.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1649,"url":"https://patchwork.plctlab.org/api/1.2/patches/1649/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0b68af932117258c908db62cf87c3a15d3cdec41.1664793840.git.research_trasio@irq.a4lg.com/","msgid":"<0b68af932117258c908db62cf87c3a15d3cdec41.1664793840.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-03T10:44:04","name":"[v3,6/6] RISC-V: Print XTheadMemPair literal as \"immediate\"","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0b68af932117258c908db62cf87c3a15d3cdec41.1664793840.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1656,"url":"https://patchwork.plctlab.org/api/1.2/patches/1656/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/87lepxcd6x.fsf@redhat.com/","msgid":"<87lepxcd6x.fsf@redhat.com>","list_archive_url":null,"date":"2022-10-03T12:19:02","name":"Commit: readelf: Do not load section data from offset 0","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/87lepxcd6x.fsf@redhat.com/mbox/"},{"id":1659,"url":"https://patchwork.plctlab.org/api/1.2/patches/1659/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e0d369d419da9c0441f415da7f54352aead8f655.1664707612.git.aburgess@redhat.com/","msgid":"","list_archive_url":null,"date":"2022-10-03T16:37:36","name":"[PATCHv2,1/2] opcodes/arm: use '\''@'\'' consistently for the comment character","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e0d369d419da9c0441f415da7f54352aead8f655.1664707612.git.aburgess@redhat.com/mbox/"},{"id":1660,"url":"https://patchwork.plctlab.org/api/1.2/patches/1660/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003165848.11142-1-palmer@rivosinc.com/","msgid":"<20221003165848.11142-1-palmer@rivosinc.com>","list_archive_url":null,"date":"2022-10-03T16:58:48","name":"gas: NEWS: Mention the T-Head extensions that were recently added","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003165848.11142-1-palmer@rivosinc.com/mbox/"},{"id":1671,"url":"https://patchwork.plctlab.org/api/1.2/patches/1671/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/YzvrMEdkXjIn5Lfz@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-04T08:13:36","name":"Support objcopy changing compression to or from zstd","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/YzvrMEdkXjIn5Lfz@squeak.grove.modra.org/mbox/"},{"id":1673,"url":"https://patchwork.plctlab.org/api/1.2/patches/1673/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0bc857d306bb7c8130e5328dbe6b9ed2fed3ef87.1664873933.git.research_trasio@irq.a4lg.com/","msgid":"<0bc857d306bb7c8130e5328dbe6b9ed2fed3ef87.1664873933.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-04T08:59:07","name":"[1/2] RISC-V: Fix buffer overflow on print_insn_riscv","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0bc857d306bb7c8130e5328dbe6b9ed2fed3ef87.1664873933.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1672,"url":"https://patchwork.plctlab.org/api/1.2/patches/1672/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/89612fe01d902007bf84a7dfb0df5f85d5c166e4.1664873933.git.research_trasio@irq.a4lg.com/","msgid":"<89612fe01d902007bf84a7dfb0df5f85d5c166e4.1664873933.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-04T08:59:08","name":"[2/2] gdb/riscv: Fix buffer overflow on riscv_insn::fetch_instruction","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/89612fe01d902007bf84a7dfb0df5f85d5c166e4.1664873933.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1676,"url":"https://patchwork.plctlab.org/api/1.2/patches/1676/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fc849c94f4adcac1c4ccc5508c7a145a2f13b2a9.1664876744.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-04T09:45:49","name":"[v2,1/2] RISC-V: Fix buffer overflow on print_insn_riscv","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fc849c94f4adcac1c4ccc5508c7a145a2f13b2a9.1664876744.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1677,"url":"https://patchwork.plctlab.org/api/1.2/patches/1677/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4eb6e59ae2e790dbbf2bc92477edd281648d8814.1664876744.git.research_trasio@irq.a4lg.com/","msgid":"<4eb6e59ae2e790dbbf2bc92477edd281648d8814.1664876744.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-04T09:45:50","name":"[v2,2/2] gdb/riscv: Partial support for instructions up to 176-bits","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/4eb6e59ae2e790dbbf2bc92477edd281648d8814.1664876744.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1678,"url":"https://patchwork.plctlab.org/api/1.2/patches/1678/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ebf16f9e1f45115d0793952ccb4a94d4233303f9.1664882725.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-04T11:25:56","name":"[v3,1/2] RISC-V: Fix buffer overflow on print_insn_riscv","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ebf16f9e1f45115d0793952ccb4a94d4233303f9.1664882725.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1679,"url":"https://patchwork.plctlab.org/api/1.2/patches/1679/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/83464b09b8649525259c69c853dfa2c9575a204b.1664882725.git.research_trasio@irq.a4lg.com/","msgid":"<83464b09b8649525259c69c853dfa2c9575a204b.1664882725.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-04T11:25:57","name":"[v3,2/2] gdb/riscv: Partial support for instructions up to 176-bit","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/83464b09b8649525259c69c853dfa2c9575a204b.1664882725.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1681,"url":"https://patchwork.plctlab.org/api/1.2/patches/1681/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ffa9c1d7-e8c2-a62b-ef3e-b565c0ffbe5b@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-04T13:56:27","name":"RISC-V: Zicbo{m,p,z} adjustments to riscv_multi_subset_supports_ext()","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ffa9c1d7-e8c2-a62b-ef3e-b565c0ffbe5b@suse.com/mbox/"},{"id":1690,"url":"https://patchwork.plctlab.org/api/1.2/patches/1690/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221004161720.1963953-1-vladimir.mezentsev@oracle.com/","msgid":"<20221004161720.1963953-1-vladimir.mezentsev@oracle.com>","list_archive_url":null,"date":"2022-10-04T16:17:20","name":"gprofng: fix build with --enable-pgo-build=lto","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221004161720.1963953-1-vladimir.mezentsev@oracle.com/mbox/"},{"id":1691,"url":"https://patchwork.plctlab.org/api/1.2/patches/1691/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c0211bc9c57be6c79c6d878ce147f63b657f461d.camel@espressif.com/","msgid":"","list_archive_url":null,"date":"2022-10-04T16:22:05","name":"bfd: xtensa: fix __stop_SECTION literal drop,","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c0211bc9c57be6c79c6d878ce147f63b657f461d.camel@espressif.com/mbox/"},{"id":1702,"url":"https://patchwork.plctlab.org/api/1.2/patches/1702/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5f482299-6c60-b2b3-9abe-f4a55a5a26c5@univ-grenoble-alpes.fr/","msgid":"<5f482299-6c60-b2b3-9abe-f4a55a5a26c5@univ-grenoble-alpes.fr>","list_archive_url":null,"date":"2022-10-04T20:03:20","name":"[RFC] bfd: use bfd_vma for the 64-bit version of put[lb] and get[lb]","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5f482299-6c60-b2b3-9abe-f4a55a5a26c5@univ-grenoble-alpes.fr/mbox/"},{"id":1711,"url":"https://patchwork.plctlab.org/api/1.2/patches/1711/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Yz0Gsxdxe0TePbJT@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-05T04:23:15","name":"PR29647, objdump -S looping","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Yz0Gsxdxe0TePbJT@squeak.grove.modra.org/mbox/"},{"id":1712,"url":"https://patchwork.plctlab.org/api/1.2/patches/1712/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/02d747d2-f57b-0fb5-b893-842b6cc41f2f@suse.com/","msgid":"<02d747d2-f57b-0fb5-b893-842b6cc41f2f@suse.com>","list_archive_url":null,"date":"2022-10-05T07:20:47","name":"[v3,1/7] x86: constify parse_insn()'\''s input","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/02d747d2-f57b-0fb5-b893-842b6cc41f2f@suse.com/mbox/"},{"id":1713,"url":"https://patchwork.plctlab.org/api/1.2/patches/1713/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/925cb740-4e1b-abc4-8526-aaab6faae5e1@suse.com/","msgid":"<925cb740-4e1b-abc4-8526-aaab6faae5e1@suse.com>","list_archive_url":null,"date":"2022-10-05T07:22:19","name":"[v3,2/7] x86: introduce Pass2 insn attribute","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/925cb740-4e1b-abc4-8526-aaab6faae5e1@suse.com/mbox/"},{"id":1714,"url":"https://patchwork.plctlab.org/api/1.2/patches/1714/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e16d3e78-39ca-f715-508f-a4104b8ab9a9@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-05T07:23:51","name":"[v3,3/7] x86: re-work insn/suffix recognition","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e16d3e78-39ca-f715-508f-a4104b8ab9a9@suse.com/mbox/"},{"id":1715,"url":"https://patchwork.plctlab.org/api/1.2/patches/1715/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e4e4b80b-794c-7485-1997-685adab8fb27@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-05T07:24:20","name":"[v3,4/7] x86-64: further re-work insn/suffix recognition to also cover MOVSL","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e4e4b80b-794c-7485-1997-685adab8fb27@suse.com/mbox/"},{"id":1716,"url":"https://patchwork.plctlab.org/api/1.2/patches/1716/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/540678fc-8bff-ec68-c97c-478d2631998c@suse.com/","msgid":"<540678fc-8bff-ec68-c97c-478d2631998c@suse.com>","list_archive_url":null,"date":"2022-10-05T07:24:55","name":"[v3,5/7] ix86: don'\''t recognize/derive Q suffix in the common case","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/540678fc-8bff-ec68-c97c-478d2631998c@suse.com/mbox/"},{"id":1718,"url":"https://patchwork.plctlab.org/api/1.2/patches/1718/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e4692495-7d3d-074d-14f9-364d4a9a998c@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-05T07:25:25","name":"[v3,6/7] x86-64: allow HLE store of accumulator to absolute 32-bit address","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e4692495-7d3d-074d-14f9-364d4a9a998c@suse.com/mbox/"},{"id":1717,"url":"https://patchwork.plctlab.org/api/1.2/patches/1717/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e8014ebd-d16b-17a7-9f34-3700fc164136@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-05T07:25:57","name":"[v3,7/7] x86: move bad-use-of-TLS-reloc check","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e8014ebd-d16b-17a7-9f34-3700fc164136@suse.com/mbox/"},{"id":1719,"url":"https://patchwork.plctlab.org/api/1.2/patches/1719/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1266f001-4511-2662-dba9-14b4d0317c57@suse.com/","msgid":"<1266f001-4511-2662-dba9-14b4d0317c57@suse.com>","list_archive_url":null,"date":"2022-10-05T07:40:50","name":"x86: drop \"regmask\" static variable","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1266f001-4511-2662-dba9-14b4d0317c57@suse.com/mbox/"},{"id":1751,"url":"https://patchwork.plctlab.org/api/1.2/patches/1751/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/af45c5d57c221e43101c2aa38b14f4b4ac12d011.1665031170.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-06T04:40:15","name":"[v2,1/2] RISC-V: Fallback for instructions longer than 64b","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/af45c5d57c221e43101c2aa38b14f4b4ac12d011.1665031170.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1752,"url":"https://patchwork.plctlab.org/api/1.2/patches/1752/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c6e55781245dd3e8e9b8debd6130fc5449dfbd55.1665031170.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-06T04:40:16","name":"[v2,2/2] RISC-V: Improve \"bits undefined\" diagnostics","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c6e55781245dd3e8e9b8debd6130fc5449dfbd55.1665031170.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1776,"url":"https://patchwork.plctlab.org/api/1.2/patches/1776/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d52952119e15357c0e823f8a2398999359588b4d.1665050099.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-06T09:56:30","name":"[v3,1/2] RISC-V: Fallback for instructions longer than 64b","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d52952119e15357c0e823f8a2398999359588b4d.1665050099.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1777,"url":"https://patchwork.plctlab.org/api/1.2/patches/1777/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d907b1997f60ff7823c4a23e281ec9d8ddcbf3f1.1665050099.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-06T09:56:31","name":"[v3,2/2] RISC-V: Improve \"bits undefined\" diagnostics","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d907b1997f60ff7823c4a23e281ec9d8ddcbf3f1.1665050099.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1781,"url":"https://patchwork.plctlab.org/api/1.2/patches/1781/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221006114628.304185-1-chigot@adacore.com/","msgid":"<20221006114628.304185-1-chigot@adacore.com>","list_archive_url":null,"date":"2022-10-06T11:46:28","name":"RISC-V: fix linker message when relaxation deletes bytes","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221006114628.304185-1-chigot@adacore.com/mbox/"},{"id":1801,"url":"https://patchwork.plctlab.org/api/1.2/patches/1801/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Yz+Yhyg7UewC9/kp@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-07T03:09:59","name":"PR29653, objcopy/strip: fuzzed small input file induces large output file","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Yz+Yhyg7UewC9/kp@squeak.grove.modra.org/mbox/"},{"id":1803,"url":"https://patchwork.plctlab.org/api/1.2/patches/1803/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/PH1P110MB16505D9D39EC5B1DE22FE3D5EC5F9@PH1P110MB1650.NAMP110.PROD.OUTLOOK.COM/","msgid":"","list_archive_url":null,"date":"2022-10-07T04:10:07","name":"@CPP_FOR_BUILD@ problem since binutils-2.38","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/PH1P110MB16505D9D39EC5B1DE22FE3D5EC5F9@PH1P110MB1650.NAMP110.PROD.OUTLOOK.COM/mbox/"},{"id":1827,"url":"https://patchwork.plctlab.org/api/1.2/patches/1827/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8e13bce108ac10a0c1dd911e23ec572926f7ae44.1665203374.git.research_trasio@irq.a4lg.com/","msgid":"<8e13bce108ac10a0c1dd911e23ec572926f7ae44.1665203374.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-08T04:29:53","name":"[v2,1/1] RISC-V: Test DWARF register numbers for \"fp\"","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8e13bce108ac10a0c1dd911e23ec572926f7ae44.1665203374.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1828,"url":"https://patchwork.plctlab.org/api/1.2/patches/1828/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0883001b3572e54d3fba264429c7ade2adb66610.1665203441.git.research_trasio@irq.a4lg.com/","msgid":"<0883001b3572e54d3fba264429c7ade2adb66610.1665203441.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-08T04:31:15","name":"[1/1] RISC-V: Move standard hints before all instructions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0883001b3572e54d3fba264429c7ade2adb66610.1665203441.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1829,"url":"https://patchwork.plctlab.org/api/1.2/patches/1829/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/58e16a241d7376fcae2515c6bd5a2b41d275eeba.1665203531.git.research_trasio@irq.a4lg.com/","msgid":"<58e16a241d7376fcae2515c6bd5a2b41d275eeba.1665203531.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-08T04:32:18","name":"[RFC,1/1] RISC-V: Imply '\''Zicsr'\'' from privileged extensions with CSRs","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/58e16a241d7376fcae2515c6bd5a2b41d275eeba.1665203531.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1830,"url":"https://patchwork.plctlab.org/api/1.2/patches/1830/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/cb5076fc96e8f2097779a3abcde843dcdd660031.1665203660.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-08T04:34:23","name":"[1/5] opcodes/riscv-dis.c: Tidying with comments/clarity","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/cb5076fc96e8f2097779a3abcde843dcdd660031.1665203660.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1832,"url":"https://patchwork.plctlab.org/api/1.2/patches/1832/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1f1aa0838bf9c4f10a45fcfe3c682f7efc79d9ae.1665203660.git.research_trasio@irq.a4lg.com/","msgid":"<1f1aa0838bf9c4f10a45fcfe3c682f7efc79d9ae.1665203660.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-08T04:34:24","name":"[2/5] opcodes/riscv-dis.c: Tidying with spacing","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1f1aa0838bf9c4f10a45fcfe3c682f7efc79d9ae.1665203660.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1831,"url":"https://patchwork.plctlab.org/api/1.2/patches/1831/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/740bc5e2d2618d236519b39fedd1a1d7ae4e05da.1665203660.git.research_trasio@irq.a4lg.com/","msgid":"<740bc5e2d2618d236519b39fedd1a1d7ae4e05da.1665203660.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-08T04:34:25","name":"[3/5] opcodes/riscv-dis.c: Use bool type whenever possible","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/740bc5e2d2618d236519b39fedd1a1d7ae4e05da.1665203660.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1833,"url":"https://patchwork.plctlab.org/api/1.2/patches/1833/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6e3a9c235e317f441b4383b3daa68f2051bdc149.1665203660.git.research_trasio@irq.a4lg.com/","msgid":"<6e3a9c235e317f441b4383b3daa68f2051bdc149.1665203660.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-08T04:34:26","name":"[4/5] opcodes/riscv-dis.c: Make XLEN variable static","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/6e3a9c235e317f441b4383b3daa68f2051bdc149.1665203660.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1834,"url":"https://patchwork.plctlab.org/api/1.2/patches/1834/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ad929233a62d887495122721340b2f9c80392963.1665203660.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-08T04:34:27","name":"[5/5] opcodes/riscv-dis.c: Remove last_map_state","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/ad929233a62d887495122721340b2f9c80392963.1665203660.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1836,"url":"https://patchwork.plctlab.org/api/1.2/patches/1836/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d07e2b6f36ea2fd5830924a9bfeda941b774b687.1665290422.git.research_trasio@irq.a4lg.com/","msgid":"","list_archive_url":null,"date":"2022-10-09T05:09:22","name":"RISC-V: Move certain arrays to riscv-opc.c","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/d07e2b6f36ea2fd5830924a9bfeda941b774b687.1665290422.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1844,"url":"https://patchwork.plctlab.org/api/1.2/patches/1844/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010004623.16582-1-mark@harmstone.com/","msgid":"<20221010004623.16582-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-10T00:46:22","name":"[v2,1/2] ld: Add --pdb option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010004623.16582-1-mark@harmstone.com/mbox/"},{"id":1845,"url":"https://patchwork.plctlab.org/api/1.2/patches/1845/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010004623.16582-2-mark@harmstone.com/","msgid":"<20221010004623.16582-2-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-10T00:46:23","name":"[v2,2/2] ld: Add minimal pdb generation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010004623.16582-2-mark@harmstone.com/mbox/"},{"id":1890,"url":"https://patchwork.plctlab.org/api/1.2/patches/1890/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010200433.414320-1-vladimir.mezentsev@oracle.com/","msgid":"<20221010200433.414320-1-vladimir.mezentsev@oracle.com>","list_archive_url":null,"date":"2022-10-10T20:04:33","name":"gprofng: run tests without installation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010200433.414320-1-vladimir.mezentsev@oracle.com/mbox/"},{"id":1893,"url":"https://patchwork.plctlab.org/api/1.2/patches/1893/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010230426.719238-1-vladimir.mezentsev@oracle.com/","msgid":"<20221010230426.719238-1-vladimir.mezentsev@oracle.com>","list_archive_url":null,"date":"2022-10-10T23:04:26","name":"[2/2] gprofng: use the --libdir path to find libraries","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010230426.719238-1-vladimir.mezentsev@oracle.com/mbox/"},{"id":1894,"url":"https://patchwork.plctlab.org/api/1.2/patches/1894/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010235155.842469-1-vladimir.mezentsev@oracle.com/","msgid":"<20221010235155.842469-1-vladimir.mezentsev@oracle.com>","list_archive_url":null,"date":"2022-10-10T23:51:55","name":"[3/3] gprofng: no need to build version.texi","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221010235155.842469-1-vladimir.mezentsev@oracle.com/mbox/"},{"id":1895,"url":"https://patchwork.plctlab.org/api/1.2/patches/1895/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011003702.4287-1-mark@harmstone.com/","msgid":"<20221011003702.4287-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-11T00:37:01","name":"[v3,1/2] ld: Add --pdb option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011003702.4287-1-mark@harmstone.com/mbox/"},{"id":1897,"url":"https://patchwork.plctlab.org/api/1.2/patches/1897/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011003702.4287-2-mark@harmstone.com/","msgid":"<20221011003702.4287-2-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-11T00:37:02","name":"[v3,2/2] ld: Add minimal pdb generation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011003702.4287-2-mark@harmstone.com/mbox/"},{"id":1928,"url":"https://patchwork.plctlab.org/api/1.2/patches/1928/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011175332.17156-1-mark@harmstone.com/","msgid":"<20221011175332.17156-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-11T17:53:31","name":"[v4,1/2] ld: Add --pdb option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011175332.17156-1-mark@harmstone.com/mbox/"},{"id":1929,"url":"https://patchwork.plctlab.org/api/1.2/patches/1929/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011175332.17156-2-mark@harmstone.com/","msgid":"<20221011175332.17156-2-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-11T17:53:32","name":"[v4,2/2] ld: Add minimal pdb generation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221011175332.17156-2-mark@harmstone.com/mbox/"},{"id":1941,"url":"https://patchwork.plctlab.org/api/1.2/patches/1941/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221012031005.237446-1-simon.marchi@polymtl.ca/","msgid":"<20221012031005.237446-1-simon.marchi@polymtl.ca>","list_archive_url":null,"date":"2022-10-12T03:10:05","name":"[pushed] Re-apply \"Pass PKG_CONFIG_PATH down from top-level Makefile\"","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221012031005.237446-1-simon.marchi@polymtl.ca/mbox/"},{"id":1976,"url":"https://patchwork.plctlab.org/api/1.2/patches/1976/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1216a3f8-2273-8681-f528-9493a66891f0@suse.com/","msgid":"<1216a3f8-2273-8681-f528-9493a66891f0@suse.com>","list_archive_url":null,"date":"2022-10-13T08:16:49","name":"[v4,1/8] x86: constify parse_insn()'\''s input","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1216a3f8-2273-8681-f528-9493a66891f0@suse.com/mbox/"},{"id":1977,"url":"https://patchwork.plctlab.org/api/1.2/patches/1977/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/11599bbe-c779-aa9f-4d5d-c2243f0e69dc@suse.com/","msgid":"<11599bbe-c779-aa9f-4d5d-c2243f0e69dc@suse.com>","list_archive_url":null,"date":"2022-10-13T08:17:17","name":"[v4,2/8] x86: introduce Pass2 insn attribute","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/11599bbe-c779-aa9f-4d5d-c2243f0e69dc@suse.com/mbox/"},{"id":1978,"url":"https://patchwork.plctlab.org/api/1.2/patches/1978/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/357273a3-060c-23db-72da-3fc9d1be3d2a@suse.com/","msgid":"<357273a3-060c-23db-72da-3fc9d1be3d2a@suse.com>","list_archive_url":null,"date":"2022-10-13T08:18:09","name":"[v4,3/8] x86: re-work insn/suffix recognition","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/357273a3-060c-23db-72da-3fc9d1be3d2a@suse.com/mbox/"},{"id":1979,"url":"https://patchwork.plctlab.org/api/1.2/patches/1979/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0ec0587f-6a7b-45b6-8346-e5d774e73636@suse.com/","msgid":"<0ec0587f-6a7b-45b6-8346-e5d774e73636@suse.com>","list_archive_url":null,"date":"2022-10-13T08:18:39","name":"[v4,4/8] x86-64: further re-work insn/suffix recognition to also cover MOVSL","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/0ec0587f-6a7b-45b6-8346-e5d774e73636@suse.com/mbox/"},{"id":1980,"url":"https://patchwork.plctlab.org/api/1.2/patches/1980/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fb617d0b-8759-3169-5a65-1178b7fef3d7@suse.com/","msgid":"","list_archive_url":null,"date":"2022-10-13T08:19:34","name":"[v4,5/8] ix86: don'\''t recognize/derive Q suffix in the common case","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/fb617d0b-8759-3169-5a65-1178b7fef3d7@suse.com/mbox/"},{"id":1981,"url":"https://patchwork.plctlab.org/api/1.2/patches/1981/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1df3bd01-99c5-f56c-d937-970edd42b2b8@suse.com/","msgid":"<1df3bd01-99c5-f56c-d937-970edd42b2b8@suse.com>","list_archive_url":null,"date":"2022-10-13T08:20:14","name":"[v4,6/8] x86-64: allow HLE store of accumulator to absolute 32-bit address","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/1df3bd01-99c5-f56c-d937-970edd42b2b8@suse.com/mbox/"},{"id":1982,"url":"https://patchwork.plctlab.org/api/1.2/patches/1982/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8486a218-39ec-16b2-5c6c-5037196b93cf@suse.com/","msgid":"<8486a218-39ec-16b2-5c6c-5037196b93cf@suse.com>","list_archive_url":null,"date":"2022-10-13T08:21:00","name":"[v4,7/8] x86: move bad-use-of-TLS-reloc check","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8486a218-39ec-16b2-5c6c-5037196b93cf@suse.com/mbox/"},{"id":1983,"url":"https://patchwork.plctlab.org/api/1.2/patches/1983/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7d82692d-93df-fbee-9efb-2f44e8a91df3@suse.com/","msgid":"<7d82692d-93df-fbee-9efb-2f44e8a91df3@suse.com>","list_archive_url":null,"date":"2022-10-13T08:22:00","name":"[v4,8/8] x86: drop (now) stray IsString","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7d82692d-93df-fbee-9efb-2f44e8a91df3@suse.com/mbox/"},{"id":2013,"url":"https://patchwork.plctlab.org/api/1.2/patches/2013/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8ab93d7a617ad480dd786210f46db0e5aa07d1ac.1665655719.git.research_trasio@irq.a4lg.com/","msgid":"<8ab93d7a617ad480dd786210f46db0e5aa07d1ac.1665655719.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-13T10:11:41","name":"include: Declare getopt function on old GNU libc","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8ab93d7a617ad480dd786210f46db0e5aa07d1ac.1665655719.git.research_trasio@irq.a4lg.com/mbox/"},{"id":2352,"url":"https://patchwork.plctlab.org/api/1.2/patches/2352/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221013201332.2747246-1-maskray@google.com/","msgid":"<20221013201332.2747246-1-maskray@google.com>","list_archive_url":null,"date":"2022-10-13T20:13:32","name":"ld: Add --undefined-version","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221013201332.2747246-1-maskray@google.com/mbox/"},{"id":2532,"url":"https://patchwork.plctlab.org/api/1.2/patches/2532/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014063520.1428330-2-zengxiao@eswincomputing.com/","msgid":"<20221014063520.1428330-2-zengxiao@eswincomputing.com>","list_archive_url":null,"date":"2022-10-14T06:35:20","name":"[1/1] RISC-V: Make R_RISCV_SUB6 conforms to riscv abi standard","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014063520.1428330-2-zengxiao@eswincomputing.com/mbox/"},{"id":2560,"url":"https://patchwork.plctlab.org/api/1.2/patches/2560/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/027ae69a-636b-6757-297a-eec42936401e@linaro.org/","msgid":"<027ae69a-636b-6757-297a-eec42936401e@linaro.org>","list_archive_url":null,"date":"2022-10-14T07:58:22","name":"[v3] aarch64-pe support for LD, GAS and BFD","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/027ae69a-636b-6757-297a-eec42936401e@linaro.org/mbox/"},{"id":2602,"url":"https://patchwork.plctlab.org/api/1.2/patches/2602/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-2-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-2-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:39","name":"[01/10] Support Intel AVX-IFMA","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-2-haochen.jiang@intel.com/mbox/"},{"id":2608,"url":"https://patchwork.plctlab.org/api/1.2/patches/2608/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-3-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-3-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:40","name":"[02/10] Support Intel AVX-VNNI-INT8","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-3-haochen.jiang@intel.com/mbox/"},{"id":2611,"url":"https://patchwork.plctlab.org/api/1.2/patches/2611/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-4-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-4-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:41","name":"[03/10] Support Intel AVX-NE-CONVERT","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-4-haochen.jiang@intel.com/mbox/"},{"id":2610,"url":"https://patchwork.plctlab.org/api/1.2/patches/2610/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-5-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-5-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:42","name":"[04/10] Support Intel CMPccXADD","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-5-haochen.jiang@intel.com/mbox/"},{"id":2601,"url":"https://patchwork.plctlab.org/api/1.2/patches/2601/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-6-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-6-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:43","name":"[05/10] Add handler for more i386_cpu_flags","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-6-haochen.jiang@intel.com/mbox/"},{"id":2606,"url":"https://patchwork.plctlab.org/api/1.2/patches/2606/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-7-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-7-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:44","name":"[06/10] Support Intel RAO-INT","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-7-haochen.jiang@intel.com/mbox/"},{"id":2609,"url":"https://patchwork.plctlab.org/api/1.2/patches/2609/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-8-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-8-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:45","name":"[07/10] Support Intel WRMSRNS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-8-haochen.jiang@intel.com/mbox/"},{"id":2605,"url":"https://patchwork.plctlab.org/api/1.2/patches/2605/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-9-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-9-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:46","name":"[08/10] Support Intel MSRLIST","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-9-haochen.jiang@intel.com/mbox/"},{"id":2607,"url":"https://patchwork.plctlab.org/api/1.2/patches/2607/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-10-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-10-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:47","name":"[09/10] Support Intel AMX-FP16","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-10-haochen.jiang@intel.com/mbox/"},{"id":2604,"url":"https://patchwork.plctlab.org/api/1.2/patches/2604/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-11-haochen.jiang@intel.com/","msgid":"<20221014091248.4920-11-haochen.jiang@intel.com>","list_archive_url":null,"date":"2022-10-14T09:12:48","name":"[10/10] Support Intel PREFETCHI","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221014091248.4920-11-haochen.jiang@intel.com/mbox/"},{"id":2643,"url":"https://patchwork.plctlab.org/api/1.2/patches/2643/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7bac66be-535e-9051-d674-f2f5ba180e17@suse.com/","msgid":"<7bac66be-535e-9051-d674-f2f5ba180e17@suse.com>","list_archive_url":null,"date":"2022-10-14T10:22:34","name":"x86: fold AVX512-VNNI disassembler entries with AVX-VNNI ones","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7bac66be-535e-9051-d674-f2f5ba180e17@suse.com/mbox/"},{"id":2654,"url":"https://patchwork.plctlab.org/api/1.2/patches/2654/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0lIo5+ncY/MqBEq@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-14T11:31:47","name":"PR29677, Field `the_bfd` of `asymbol` is uninitialised","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0lIo5+ncY/MqBEq@squeak.grove.modra.org/mbox/"},{"id":2656,"url":"https://patchwork.plctlab.org/api/1.2/patches/2656/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0lJksn49ZpABY89@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-14T11:35:46","name":"e200 LSP support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0lJksn49ZpABY89@squeak.grove.modra.org/mbox/"},{"id":2657,"url":"https://patchwork.plctlab.org/api/1.2/patches/2657/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0lJxxYoeD5iDYAD@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-14T11:36:39","name":"PowerPC SPE disassembly and tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0lJxxYoeD5iDYAD@squeak.grove.modra.org/mbox/"},{"id":2695,"url":"https://patchwork.plctlab.org/api/1.2/patches/2695/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/DM6PR12MB4219611F6CC2A0702884A602E7249@DM6PR12MB4219.namprd12.prod.outlook.com/","msgid":"","list_archive_url":null,"date":"2022-10-14T13:29:40","name":"Binutils: Adding new testcase for addr2line.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/DM6PR12MB4219611F6CC2A0702884A602E7249@DM6PR12MB4219.namprd12.prod.outlook.com/mbox/"},{"id":2700,"url":"https://patchwork.plctlab.org/api/1.2/patches/2700/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9fd2c88d-98b2-99a4-419f-c7235b2cf960@suse.com/","msgid":"<9fd2c88d-98b2-99a4-419f-c7235b2cf960@suse.com>","list_archive_url":null,"date":"2022-10-14T14:11:35","name":"x86: properly decode EVEX.W for AVX512_4{FMAPS,VNNIW} insns","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/9fd2c88d-98b2-99a4-419f-c7235b2cf960@suse.com/mbox/"},{"id":2981,"url":"https://patchwork.plctlab.org/api/1.2/patches/2981/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0uLzalqjm4C87GN@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-16T04:42:53","name":"PowerPC se_rfmci and VLE, SPE2 and LSP insns with -many","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0uLzalqjm4C87GN@squeak.grove.modra.org/mbox/"},{"id":3152,"url":"https://patchwork.plctlab.org/api/1.2/patches/3152/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221016232419.1135-1-mark@harmstone.com/","msgid":"<20221016232419.1135-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-16T23:24:18","name":"[v5,1/2] ld: Add --pdb option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221016232419.1135-1-mark@harmstone.com/mbox/"},{"id":3151,"url":"https://patchwork.plctlab.org/api/1.2/patches/3151/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221016232419.1135-2-mark@harmstone.com/","msgid":"<20221016232419.1135-2-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-16T23:24:19","name":"[v5,2/2] ld: Add minimal pdb generation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221016232419.1135-2-mark@harmstone.com/mbox/"},{"id":3258,"url":"https://patchwork.plctlab.org/api/1.2/patches/3258/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/19c08747-fa5b-1e67-3dd2-c891a2c0c1fa@suse.com/","msgid":"<19c08747-fa5b-1e67-3dd2-c891a2c0c1fa@suse.com>","list_archive_url":null,"date":"2022-10-17T07:44:51","name":"x86: correct CPU_AMX_{BF16,INT8}_FLAGS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/19c08747-fa5b-1e67-3dd2-c891a2c0c1fa@suse.com/mbox/"},{"id":3272,"url":"https://patchwork.plctlab.org/api/1.2/patches/3272/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/85dd526c-d3a7-72dc-5444-ed5573eebec1@suse.com/","msgid":"<85dd526c-d3a7-72dc-5444-ed5573eebec1@suse.com>","list_archive_url":null,"date":"2022-10-17T08:30:12","name":"x86: generalize gas documentation for disabling of ISA extensions","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/85dd526c-d3a7-72dc-5444-ed5573eebec1@suse.com/mbox/"},{"id":3759,"url":"https://patchwork.plctlab.org/api/1.2/patches/3759/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-2-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-2-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:15:58","name":"[V2,01/15] sframe.h: Add SFrame format definition","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-2-indu.bhagat@oracle.com/mbox/"},{"id":3762,"url":"https://patchwork.plctlab.org/api/1.2/patches/3762/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-3-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-3-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:15:59","name":"[V2,02/15] gas: add new command line option --gsframe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-3-indu.bhagat@oracle.com/mbox/"},{"id":3761,"url":"https://patchwork.plctlab.org/api/1.2/patches/3761/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-4-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-4-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:00","name":"[V2,03/15] gas: generate .sframe from CFI directives","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-4-indu.bhagat@oracle.com/mbox/"},{"id":3760,"url":"https://patchwork.plctlab.org/api/1.2/patches/3760/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-5-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-5-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:01","name":"[V2,04/15] gas: testsuite: add new tests for SFrame unwind info","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-5-indu.bhagat@oracle.com/mbox/"},{"id":3764,"url":"https://patchwork.plctlab.org/api/1.2/patches/3764/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-6-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-6-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:02","name":"[V2,05/15] libsframe: add the SFrame library","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-6-indu.bhagat@oracle.com/mbox/"},{"id":3763,"url":"https://patchwork.plctlab.org/api/1.2/patches/3763/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-8-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-8-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:04","name":"[V2,07/15] readelf/objdump: support for SFrame section","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-8-indu.bhagat@oracle.com/mbox/"}],"public":true,"mbox":"https://patchwork.plctlab.org/bundle/snail/binutils-gdb_2022-10/mbox/"},{"id":7,"url":"https://patchwork.plctlab.org/api/1.2/bundles/7/","web_url":"https://patchwork.plctlab.org/bundle/snail/binutils-gdb_2022-09/","project":{"id":2,"url":"https://patchwork.plctlab.org/api/1.2/projects/2/","name":"binutils-gdb","link_name":"binutils-gdb","list_id":"binutils.sourceware.org","list_email":"binutils@sourceware.org","web_url":"https://sourceware.org/mailman/listinfo/binutils","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"name":"binutils-gdb_2022-09","owner":{"id":1,"url":"https://patchwork.plctlab.org/api/1.2/users/1/","username":"snail","first_name":"","last_name":"","email":"wangliu@iscas.ac.cn"},"patches":[{"id":1573,"url":"https://patchwork.plctlab.org/api/1.2/patches/1573/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930073211.2634-1-jiawei@iscas.ac.cn/","msgid":"<20220930073211.2634-1-jiawei@iscas.ac.cn>","list_archive_url":null,"date":"2022-09-30T07:32:11","name":"[V2] RISC-V: Add Smepmp CSR '\''mseccfg'\'' define and testcases.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930073211.2634-1-jiawei@iscas.ac.cn/mbox/"},{"id":1577,"url":"https://patchwork.plctlab.org/api/1.2/patches/1577/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/76fa0c3c-2303-ebdf-a765-ac4731581517@suse.com/","msgid":"<76fa0c3c-2303-ebdf-a765-ac4731581517@suse.com>","list_archive_url":null,"date":"2022-09-30T08:54:18","name":"objcopy: avoid \"shadowing\" of remove() function name","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/76fa0c3c-2303-ebdf-a765-ac4731581517@suse.com/mbox/"},{"id":1579,"url":"https://patchwork.plctlab.org/api/1.2/patches/1579/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930085852.71213-1-nelson@rivosinc.com/","msgid":"<20220930085852.71213-1-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-09-30T08:58:51","name":"[1/2] RISC-V: Output mapping symbols with ISA string.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930085852.71213-1-nelson@rivosinc.com/mbox/"},{"id":1578,"url":"https://patchwork.plctlab.org/api/1.2/patches/1578/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930085852.71213-2-nelson@rivosinc.com/","msgid":"<20220930085852.71213-2-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-09-30T08:58:52","name":"[2/2] RISC-V: Refer mapping symbol to R_RISCV_RELAX for rvc relaxations.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930085852.71213-2-nelson@rivosinc.com/mbox/"},{"id":1581,"url":"https://patchwork.plctlab.org/api/1.2/patches/1581/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930092058.71286-1-nelson@rivosinc.com/","msgid":"<20220930092058.71286-1-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-09-30T09:20:57","name":"[1/2] RISC-V: Output mapping symbols with ISA string.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930092058.71286-1-nelson@rivosinc.com/mbox/"},{"id":1580,"url":"https://patchwork.plctlab.org/api/1.2/patches/1580/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930092058.71286-2-nelson@rivosinc.com/","msgid":"<20220930092058.71286-2-nelson@rivosinc.com>","list_archive_url":null,"date":"2022-09-30T09:20:58","name":"[2/2] RISC-V: Refer mapping symbol to R_RISCV_RELAX for rvc relaxations.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930092058.71286-2-nelson@rivosinc.com/mbox/"},{"id":1582,"url":"https://patchwork.plctlab.org/api/1.2/patches/1582/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5874dd79-0cf5-d65c-7ea2-13adfc799c0f@suse.com/","msgid":"<5874dd79-0cf5-d65c-7ea2-13adfc799c0f@suse.com>","list_archive_url":null,"date":"2022-09-30T09:41:29","name":"RISC-V: fix build after \"Add support for arbitrary immediate encoding formats\"","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/5874dd79-0cf5-d65c-7ea2-13adfc799c0f@suse.com/mbox/"},{"id":1583,"url":"https://patchwork.plctlab.org/api/1.2/patches/1583/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/57d8ac2a-5757-3776-9924-99c17ca69938@suse.com/","msgid":"<57d8ac2a-5757-3776-9924-99c17ca69938@suse.com>","list_archive_url":null,"date":"2022-09-30T09:42:08","name":"RISC-V: fallout from \"re-arrange opcode table for consistent alias handling\"","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/57d8ac2a-5757-3776-9924-99c17ca69938@suse.com/mbox/"},{"id":1584,"url":"https://patchwork.plctlab.org/api/1.2/patches/1584/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e76ef8f7-72b9-5103-cb43-9608af01d017@suse.com/","msgid":"","list_archive_url":null,"date":"2022-09-30T09:42:50","name":"RISC-V: don'\''t cast expressions'\'' X_add_number to long in diagnostics","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/e76ef8f7-72b9-5103-cb43-9608af01d017@suse.com/mbox/"},{"id":1585,"url":"https://patchwork.plctlab.org/api/1.2/patches/1585/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/61355429-24b3-17d0-ab03-6fa57ee861d5@suse.cz/","msgid":"<61355429-24b3-17d0-ab03-6fa57ee861d5@suse.cz>","list_archive_url":null,"date":"2022-09-30T09:48:52","name":"[RFC] add --enable-zstd-compressed-debug-sections configure option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/61355429-24b3-17d0-ab03-6fa57ee861d5@suse.cz/mbox/"},{"id":1586,"url":"https://patchwork.plctlab.org/api/1.2/patches/1586/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930103919.323690-1-christoph.muellner@vrull.eu/","msgid":"<20220930103919.323690-1-christoph.muellner@vrull.eu>","list_archive_url":null,"date":"2022-09-30T10:39:19","name":"RISC-V: Eliminate long-casts of X_add_number in diagnostics","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930103919.323690-1-christoph.muellner@vrull.eu/mbox/"},{"id":1590,"url":"https://patchwork.plctlab.org/api/1.2/patches/1590/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/DM6PR12MB4219C943049C6D883DEA3E55E7569@DM6PR12MB4219.namprd12.prod.outlook.com/","msgid":"","list_archive_url":null,"date":"2022-09-30T11:41:37","name":"[V2] Ignore DWARF debug information for -gsplit-dwarf with dwarf-5.","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/DM6PR12MB4219C943049C6D883DEA3E55E7569@DM6PR12MB4219.namprd12.prod.outlook.com/mbox/"},{"id":1591,"url":"https://patchwork.plctlab.org/api/1.2/patches/1591/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c10321f9-d289-ef84-d263-bc278fb3d31b@suse.com/","msgid":"","list_archive_url":null,"date":"2022-09-30T11:59:04","name":"[1/4] RISC-V/gas: drop riscv_subsets static variable","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/c10321f9-d289-ef84-d263-bc278fb3d31b@suse.com/mbox/"},{"id":1593,"url":"https://patchwork.plctlab.org/api/1.2/patches/1593/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3244eea0-c18c-e49a-4588-d69423130226@suse.com/","msgid":"<3244eea0-c18c-e49a-4588-d69423130226@suse.com>","list_archive_url":null,"date":"2022-09-30T11:59:23","name":"[2/4] RISC-V/gas: drop stray call to install_insn()","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/3244eea0-c18c-e49a-4588-d69423130226@suse.com/mbox/"},{"id":1592,"url":"https://patchwork.plctlab.org/api/1.2/patches/1592/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/385d01fd-7e57-1f3f-1bae-30aa0c313d63@suse.com/","msgid":"<385d01fd-7e57-1f3f-1bae-30aa0c313d63@suse.com>","list_archive_url":null,"date":"2022-09-30T11:59:45","name":"[3/4] RISC-V/gas: don'\''t open-code insn_length()","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/385d01fd-7e57-1f3f-1bae-30aa0c313d63@suse.com/mbox/"},{"id":1594,"url":"https://patchwork.plctlab.org/api/1.2/patches/1594/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f5757acf-7b90-a0e3-5eea-3b97cc226930@suse.com/","msgid":"","list_archive_url":null,"date":"2022-09-30T12:00:12","name":"[4/4] RISC-V/gas: allow generating up to 176-bit instructions with .insn","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/f5757acf-7b90-a0e3-5eea-3b97cc226930@suse.com/mbox/"},{"id":1596,"url":"https://patchwork.plctlab.org/api/1.2/patches/1596/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930140503.38233-1-chigot@adacore.com/","msgid":"<20220930140503.38233-1-chigot@adacore.com>","list_archive_url":null,"date":"2022-09-30T14:05:03","name":"ld/testsuite: consistently add board_ldflags when linking with GCC","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930140503.38233-1-chigot@adacore.com/mbox/"}],"public":true,"mbox":"https://patchwork.plctlab.org/bundle/snail/binutils-gdb_2022-09/mbox/"}]' + bundle_id=6 + git-pw bundle add 6 3765 +------------+--------------------------------------------------------------------------------------+ | Property | Value | |------------+--------------------------------------------------------------------------------------| | ID | 6 | | Name | binutils-gdb_2022-10 | | URL | https://patchwork.plctlab.org/bundle/snail/binutils-gdb_2022-10/ | | Owner | snail | | Project | binutils-gdb | | Public | True | | Patches | 1592 [3/4] RISC-V/gas: don't open-code insn_length() | | | 1594 [4/4] RISC-V/gas: allow generating up to 176-bit instructions with .insn | | | 1596 ld/testsuite: consistently add board_ldflags when linking with GCC | | | 1619 gold, dwp: support zstd compressed input debug sections [PR 29641] | | | 1620 gold: add --compress-debug-sections=zstd [PR 29641] | | | 1623 [RFC,1/1] RISC-V: Implement common register pair framework | | | 1625 [RFC,1/1] RISC-V: Implement extension variants | | | 1626 [1/1] RISC-V: Move supervisor instructions after all unprivileged ones | | | 1627 readelf: support zstd compressed debug sections [PR 29640] | | | 1631 [PATCHv2,2/2] opcodes/arm: add disassembler styling for arm | | | 1635 diagnostics.h: GCC 13 got -Wself-move, breaks GDB build | | | 1637 [1/2] ld: Add --pdb option | | | 1638 [2/2] ld: Add minimal pdb generation | | | 1640 [1/2] refactor usage of compressed_debug_section_type | | | 1641 [2/2] add --enable-default-compressed-debug-sections-algorithm configure option | | | 1642 opcodes/riscv: style csr names as registers | | | 1643 [v3,1/6] RISC-V: Fix immediates to have "immediate" style | | | 1644 [v3,2/6] RISC-V: Fix printf argument types corresponding %x | | | 1647 [v3,3/6] RISC-V: Optimize riscv_disassemble_data printf | | | 1646 [v3,4/6] RISC-V: Print comma and tabs as the "text" style | | | 1648 [v3,5/6] RISC-V: Fix T-Head immediate types on printing | | | 1649 [v3,6/6] RISC-V: Print XTheadMemPair literal as "immediate" | | | 1656 Commit: readelf: Do not load section data from offset 0 | | | 1659 [PATCHv2,1/2] opcodes/arm: use '@' consistently for the comment character | | | 1660 gas: NEWS: Mention the T-Head extensions that were recently added | | | 1671 Support objcopy changing compression to or from zstd | | | 1673 [1/2] RISC-V: Fix buffer overflow on print_insn_riscv | | | 1672 [2/2] gdb/riscv: Fix buffer overflow on riscv_insn::fetch_instruction | | | 1676 [v2,1/2] RISC-V: Fix buffer overflow on print_insn_riscv | | | 1677 [v2,2/2] gdb/riscv: Partial support for instructions up to 176-bits | | | 1678 [v3,1/2] RISC-V: Fix buffer overflow on print_insn_riscv | | | 1679 [v3,2/2] gdb/riscv: Partial support for instructions up to 176-bit | | | 1681 RISC-V: Zicbo{m,p,z} adjustments to riscv_multi_subset_supports_ext() | | | 1690 gprofng: fix build with --enable-pgo-build=lto | | | 1691 bfd: xtensa: fix __stop_SECTION literal drop, | | | 1702 [RFC] bfd: use bfd_vma for the 64-bit version of put[lb] and get[lb] | | | 1711 PR29647, objdump -S looping | | | 1712 [v3,1/7] x86: constify parse_insn()'s input | | | 1713 [v3,2/7] x86: introduce Pass2 insn attribute | | | 1714 [v3,3/7] x86: re-work insn/suffix recognition | | | 1715 [v3,4/7] x86-64: further re-work insn/suffix recognition to also cover MOVSL | | | 1716 [v3,5/7] ix86: don't recognize/derive Q suffix in the common case | | | 1718 [v3,6/7] x86-64: allow HLE store of accumulator to absolute 32-bit address | | | 1717 [v3,7/7] x86: move bad-use-of-TLS-reloc check | | | 1719 x86: drop "regmask" static variable | | | 1751 [v2,1/2] RISC-V: Fallback for instructions longer than 64b | | | 1752 [v2,2/2] RISC-V: Improve "bits undefined" diagnostics | | | 1776 [v3,1/2] RISC-V: Fallback for instructions longer than 64b | | | 1777 [v3,2/2] RISC-V: Improve "bits undefined" diagnostics | | | 1781 RISC-V: fix linker message when relaxation deletes bytes | | | 1801 PR29653, objcopy/strip: fuzzed small input file induces large output file | | | 1803 @CPP_FOR_BUILD@ problem since binutils-2.38 | | | 1827 [v2,1/1] RISC-V: Test DWARF register numbers for "fp" | | | 1828 [1/1] RISC-V: Move standard hints before all instructions | | | 1829 [RFC,1/1] RISC-V: Imply 'Zicsr' from privileged extensions with CSRs | | | 1830 [1/5] opcodes/riscv-dis.c: Tidying with comments/clarity | | | 1832 [2/5] opcodes/riscv-dis.c: Tidying with spacing | | | 1831 [3/5] opcodes/riscv-dis.c: Use bool type whenever possible | | | 1833 [4/5] opcodes/riscv-dis.c: Make XLEN variable static | | | 1834 [5/5] opcodes/riscv-dis.c: Remove last_map_state | | | 1836 RISC-V: Move certain arrays to riscv-opc.c | | | 1844 [v2,1/2] ld: Add --pdb option | | | 1845 [v2,2/2] ld: Add minimal pdb generation | | | 1890 gprofng: run tests without installation | | | 1893 [2/2] gprofng: use the --libdir path to find libraries | | | 1894 [3/3] gprofng: no need to build version.texi | | | 1895 [v3,1/2] ld: Add --pdb option | | | 1897 [v3,2/2] ld: Add minimal pdb generation | | | 1928 [v4,1/2] ld: Add --pdb option | | | 1929 [v4,2/2] ld: Add minimal pdb generation | | | 1941 [pushed] Re-apply "Pass PKG_CONFIG_PATH down from top-level Makefile" | | | 1976 [v4,1/8] x86: constify parse_insn()'s input | | | 1977 [v4,2/8] x86: introduce Pass2 insn attribute | | | 1978 [v4,3/8] x86: re-work insn/suffix recognition | | | 1979 [v4,4/8] x86-64: further re-work insn/suffix recognition to also cover MOVSL | | | 1980 [v4,5/8] ix86: don't recognize/derive Q suffix in the common case | | | 1981 [v4,6/8] x86-64: allow HLE store of accumulator to absolute 32-bit address | | | 1982 [v4,7/8] x86: move bad-use-of-TLS-reloc check | | | 1983 [v4,8/8] x86: drop (now) stray IsString | | | 2013 include: Declare getopt function on old GNU libc | | | 2352 ld: Add --undefined-version | | | 2532 [1/1] RISC-V: Make R_RISCV_SUB6 conforms to riscv abi standard | | | 2560 [v3] aarch64-pe support for LD, GAS and BFD | | | 2602 [01/10] Support Intel AVX-IFMA | | | 2608 [02/10] Support Intel AVX-VNNI-INT8 | | | 2611 [03/10] Support Intel AVX-NE-CONVERT | | | 2610 [04/10] Support Intel CMPccXADD | | | 2601 [05/10] Add handler for more i386_cpu_flags | | | 2606 [06/10] Support Intel RAO-INT | | | 2609 [07/10] Support Intel WRMSRNS | | | 2605 [08/10] Support Intel MSRLIST | | | 2607 [09/10] Support Intel AMX-FP16 | | | 2604 [10/10] Support Intel PREFETCHI | | | 2643 x86: fold AVX512-VNNI disassembler entries with AVX-VNNI ones | | | 2654 PR29677, Field `the_bfd` of `asymbol` is uninitialised | | | 2656 e200 LSP support | | | 2657 PowerPC SPE disassembly and tests | | | 2695 Binutils: Adding new testcase for addr2line. | | | 2700 x86: properly decode EVEX.W for AVX512_4{FMAPS,VNNIW} insns | | | 2981 PowerPC se_rfmci and VLE, SPE2 and LSP insns with -many | | | 3152 [v5,1/2] ld: Add --pdb option | | | 3151 [v5,2/2] ld: Add minimal pdb generation | | | 3258 x86: correct CPU_AMX_{BF16,INT8}_FLAGS | | | 3272 x86: generalize gas documentation for disabling of ISA extensions | | | 3759 [V2,01/15] sframe.h: Add SFrame format definition | | | 3762 [V2,02/15] gas: add new command line option --gsframe | | | 3761 [V2,03/15] gas: generate .sframe from CFI directives | | | 3760 [V2,04/15] gas: testsuite: add new tests for SFrame unwind info | | | 3764 [V2,05/15] libsframe: add the SFrame library | | | 3763 [V2,07/15] readelf/objdump: support for SFrame section | | | 3765 [V2,08/15] unwinder: generate backtrace using SFrame format | +------------+--------------------------------------------------------------------------------------+ + git config pull.rebase false + git fetch origin master From github.com:wangliu-iscas/binutils-gdb * branch master -> FETCH_HEAD + git checkout master Switched to a new branch 'master' branch 'master' set up to track 'origin/master'. + git pull origin master From github.com:wangliu-iscas/binutils-gdb * branch master -> FETCH_HEAD Already up to date. + git fetch origin upstream-master From github.com:wangliu-iscas/binutils-gdb * branch upstream-master -> FETCH_HEAD + git checkout upstream-master Switched to a new branch 'upstream-master' branch 'upstream-master' set up to track 'origin/upstream-master'. + git remote add upstream https://sourceware.org/git/binutils-gdb.git + git pull upstream master From https://sourceware.org/git/binutils-gdb * branch master -> FETCH_HEAD * [new branch] master -> upstream/master Already up to date. + git push -u origin upstream-master Everything up-to-date branch 'upstream-master' set up to track 'origin/upstream-master'. + git checkout master Switched to branch 'master' Your branch is up to date with 'origin/master'. + git merge upstream-master Already up to date. + git push -u origin master Everything up-to-date branch 'master' set up to track 'origin/master'. + branchname=series2418-patch3765 ++ git branch -a ++ grep 'series2418-patch3765$' + checkbranch= + checkbranchresult=null + '[' null = series2418-patch3765 ']' + git checkout -b series2418-patch3765 Switched to a new branch 'series2418-patch3765' ++ curl https://patchwork.plctlab.org/api/1.2/series/2418/ % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 8628 100 8628 0 0 168k 0 --:--:-- --:--:-- --:--:-- 168k + series_response='{"id":2418,"url":"https://patchwork.plctlab.org/api/1.2/series/2418/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/list/?series=2418","project":{"id":2,"url":"https://patchwork.plctlab.org/api/1.2/projects/2/","name":"binutils-gdb","link_name":"binutils-gdb","list_id":"binutils.sourceware.org","list_email":"binutils@sourceware.org","web_url":"https://sourceware.org/mailman/listinfo/binutils","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"name":"Definition and support for SFrame unwind format","date":"2022-10-17T22:15:58","submitter":{"id":35,"url":"https://patchwork.plctlab.org/api/1.2/people/35/","name":"Indu Bhagat","email":"indu.bhagat@oracle.com"},"version":2,"total":15,"received_total":15,"received_all":true,"mbox":"https://patchwork.plctlab.org/series/2418/mbox/","cover_letter":{"id":240,"url":"https://patchwork.plctlab.org/api/1.2/covers/240/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/cover/20221017221612.495324-1-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-1-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:15:57","name":"[V2,00/15] Definition and support for SFrame unwind format","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/cover/20221017221612.495324-1-indu.bhagat@oracle.com/mbox/"},"patches":[{"id":3759,"url":"https://patchwork.plctlab.org/api/1.2/patches/3759/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-2-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-2-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:15:58","name":"[V2,01/15] sframe.h: Add SFrame format definition","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-2-indu.bhagat@oracle.com/mbox/"},{"id":3762,"url":"https://patchwork.plctlab.org/api/1.2/patches/3762/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-3-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-3-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:15:59","name":"[V2,02/15] gas: add new command line option --gsframe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-3-indu.bhagat@oracle.com/mbox/"},{"id":3761,"url":"https://patchwork.plctlab.org/api/1.2/patches/3761/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-4-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-4-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:00","name":"[V2,03/15] gas: generate .sframe from CFI directives","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-4-indu.bhagat@oracle.com/mbox/"},{"id":3760,"url":"https://patchwork.plctlab.org/api/1.2/patches/3760/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-5-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-5-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:01","name":"[V2,04/15] gas: testsuite: add new tests for SFrame unwind info","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-5-indu.bhagat@oracle.com/mbox/"},{"id":3764,"url":"https://patchwork.plctlab.org/api/1.2/patches/3764/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-6-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-6-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:02","name":"[V2,05/15] libsframe: add the SFrame library","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-6-indu.bhagat@oracle.com/mbox/"},{"id":3766,"url":"https://patchwork.plctlab.org/api/1.2/patches/3766/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-7-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-7-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:03","name":"[V2,06/15] bfd: linker: merge .sframe sections","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-7-indu.bhagat@oracle.com/mbox/"},{"id":3763,"url":"https://patchwork.plctlab.org/api/1.2/patches/3763/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-8-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-8-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:04","name":"[V2,07/15] readelf/objdump: support for SFrame section","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-8-indu.bhagat@oracle.com/mbox/"},{"id":3765,"url":"https://patchwork.plctlab.org/api/1.2/patches/3765/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-9-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-9-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:05","name":"[V2,08/15] unwinder: generate backtrace using SFrame format","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-9-indu.bhagat@oracle.com/mbox/"},{"id":3770,"url":"https://patchwork.plctlab.org/api/1.2/patches/3770/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-10-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-10-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:06","name":"[V2,09/15] unwinder: Add SFrame unwinder tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-10-indu.bhagat@oracle.com/mbox/"},{"id":3769,"url":"https://patchwork.plctlab.org/api/1.2/patches/3769/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-11-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-11-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:07","name":"[V2,10/15] gdb: sim: buildsystem changes to accommodate libsframe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-11-indu.bhagat@oracle.com/mbox/"},{"id":3771,"url":"https://patchwork.plctlab.org/api/1.2/patches/3771/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-12-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-12-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:08","name":"[V2,11/15] libctf: add libsframe to LDFLAGS and LIBS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-12-indu.bhagat@oracle.com/mbox/"},{"id":3768,"url":"https://patchwork.plctlab.org/api/1.2/patches/3768/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-13-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-13-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:09","name":"[V2,12/15] src-release.sh: Add libsframe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-13-indu.bhagat@oracle.com/mbox/"},{"id":3767,"url":"https://patchwork.plctlab.org/api/1.2/patches/3767/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-14-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-14-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:10","name":"[V2,13/15] binutils/NEWS: add text for SFrame support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-14-indu.bhagat@oracle.com/mbox/"},{"id":3772,"url":"https://patchwork.plctlab.org/api/1.2/patches/3772/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-15-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-15-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:11","name":"[V2,14/15] gas/NEWS: add text about new command line option and SFrame support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-15-indu.bhagat@oracle.com/mbox/"},{"id":3773,"url":"https://patchwork.plctlab.org/api/1.2/patches/3773/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-16-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-16-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:12","name":"[V2,15/15] doc: add SFrame spec file","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-16-indu.bhagat@oracle.com/mbox/"}]}' ++ echo '{"id":2418,"url":"https://patchwork.plctlab.org/api/1.2/series/2418/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/list/?series=2418","project":{"id":2,"url":"https://patchwork.plctlab.org/api/1.2/projects/2/","name":"binutils-gdb","link_name":"binutils-gdb","list_id":"binutils.sourceware.org","list_email":"binutils@sourceware.org","web_url":"https://sourceware.org/mailman/listinfo/binutils","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"name":"Definition and support for SFrame unwind format","date":"2022-10-17T22:15:58","submitter":{"id":35,"url":"https://patchwork.plctlab.org/api/1.2/people/35/","name":"Indu Bhagat","email":"indu.bhagat@oracle.com"},"version":2,"total":15,"received_total":15,"received_all":true,"mbox":"https://patchwork.plctlab.org/series/2418/mbox/","cover_letter":{"id":240,"url":"https://patchwork.plctlab.org/api/1.2/covers/240/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/cover/20221017221612.495324-1-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-1-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:15:57","name":"[V2,00/15] Definition and support for SFrame unwind format","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/cover/20221017221612.495324-1-indu.bhagat@oracle.com/mbox/"},"patches":[{"id":3759,"url":"https://patchwork.plctlab.org/api/1.2/patches/3759/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-2-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-2-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:15:58","name":"[V2,01/15] sframe.h: Add SFrame format definition","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-2-indu.bhagat@oracle.com/mbox/"},{"id":3762,"url":"https://patchwork.plctlab.org/api/1.2/patches/3762/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-3-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-3-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:15:59","name":"[V2,02/15] gas: add new command line option --gsframe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-3-indu.bhagat@oracle.com/mbox/"},{"id":3761,"url":"https://patchwork.plctlab.org/api/1.2/patches/3761/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-4-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-4-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:00","name":"[V2,03/15] gas: generate .sframe from CFI directives","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-4-indu.bhagat@oracle.com/mbox/"},{"id":3760,"url":"https://patchwork.plctlab.org/api/1.2/patches/3760/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-5-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-5-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:01","name":"[V2,04/15] gas: testsuite: add new tests for SFrame unwind info","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-5-indu.bhagat@oracle.com/mbox/"},{"id":3764,"url":"https://patchwork.plctlab.org/api/1.2/patches/3764/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-6-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-6-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:02","name":"[V2,05/15] libsframe: add the SFrame library","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-6-indu.bhagat@oracle.com/mbox/"},{"id":3766,"url":"https://patchwork.plctlab.org/api/1.2/patches/3766/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-7-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-7-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:03","name":"[V2,06/15] bfd: linker: merge .sframe sections","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-7-indu.bhagat@oracle.com/mbox/"},{"id":3763,"url":"https://patchwork.plctlab.org/api/1.2/patches/3763/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-8-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-8-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:04","name":"[V2,07/15] readelf/objdump: support for SFrame section","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-8-indu.bhagat@oracle.com/mbox/"},{"id":3765,"url":"https://patchwork.plctlab.org/api/1.2/patches/3765/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-9-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-9-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:05","name":"[V2,08/15] unwinder: generate backtrace using SFrame format","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-9-indu.bhagat@oracle.com/mbox/"},{"id":3770,"url":"https://patchwork.plctlab.org/api/1.2/patches/3770/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-10-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-10-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:06","name":"[V2,09/15] unwinder: Add SFrame unwinder tests","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-10-indu.bhagat@oracle.com/mbox/"},{"id":3769,"url":"https://patchwork.plctlab.org/api/1.2/patches/3769/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-11-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-11-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:07","name":"[V2,10/15] gdb: sim: buildsystem changes to accommodate libsframe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-11-indu.bhagat@oracle.com/mbox/"},{"id":3771,"url":"https://patchwork.plctlab.org/api/1.2/patches/3771/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-12-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-12-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:08","name":"[V2,11/15] libctf: add libsframe to LDFLAGS and LIBS","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-12-indu.bhagat@oracle.com/mbox/"},{"id":3768,"url":"https://patchwork.plctlab.org/api/1.2/patches/3768/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-13-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-13-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:09","name":"[V2,12/15] src-release.sh: Add libsframe","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-13-indu.bhagat@oracle.com/mbox/"},{"id":3767,"url":"https://patchwork.plctlab.org/api/1.2/patches/3767/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-14-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-14-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:10","name":"[V2,13/15] binutils/NEWS: add text for SFrame support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-14-indu.bhagat@oracle.com/mbox/"},{"id":3772,"url":"https://patchwork.plctlab.org/api/1.2/patches/3772/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-15-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-15-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:11","name":"[V2,14/15] gas/NEWS: add text about new command line option and SFrame support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-15-indu.bhagat@oracle.com/mbox/"},{"id":3773,"url":"https://patchwork.plctlab.org/api/1.2/patches/3773/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-16-indu.bhagat@oracle.com/","msgid":"<20221017221612.495324-16-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:12","name":"[V2,15/15] doc: add SFrame spec file","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-16-indu.bhagat@oracle.com/mbox/"}]}' ++ jq '.patches[] | (.id|tostring) + "," + .mbox' + patchid_patchurl='"3759,https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-2-indu.bhagat@oracle.com/mbox/" "3762,https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-3-indu.bhagat@oracle.com/mbox/" "3761,https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-4-indu.bhagat@oracle.com/mbox/" "3760,https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-5-indu.bhagat@oracle.com/mbox/" "3764,https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-6-indu.bhagat@oracle.com/mbox/" "3766,https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-7-indu.bhagat@oracle.com/mbox/" "3763,https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-8-indu.bhagat@oracle.com/mbox/" "3765,https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-9-indu.bhagat@oracle.com/mbox/" "3770,https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-10-indu.bhagat@oracle.com/mbox/" "3769,https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-11-indu.bhagat@oracle.com/mbox/" "3771,https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-12-indu.bhagat@oracle.com/mbox/" "3768,https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-13-indu.bhagat@oracle.com/mbox/" "3767,https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-14-indu.bhagat@oracle.com/mbox/" "3772,https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-15-indu.bhagat@oracle.com/mbox/" "3773,https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-16-indu.bhagat@oracle.com/mbox/"' + IFS=, + read -r series_patch_id series_patch_url + echo '"3759,https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-2-indu.bhagat@oracle.com/mbox/" "3762,https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-3-indu.bhagat@oracle.com/mbox/" "3761,https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-4-indu.bhagat@oracle.com/mbox/" "3760,https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-5-indu.bhagat@oracle.com/mbox/" "3764,https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-6-indu.bhagat@oracle.com/mbox/" "3766,https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-7-indu.bhagat@oracle.com/mbox/" "3763,https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-8-indu.bhagat@oracle.com/mbox/" "3765,https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-9-indu.bhagat@oracle.com/mbox/" "3770,https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-10-indu.bhagat@oracle.com/mbox/" "3769,https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-11-indu.bhagat@oracle.com/mbox/" "3771,https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-12-indu.bhagat@oracle.com/mbox/" "3768,https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-13-indu.bhagat@oracle.com/mbox/" "3767,https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-14-indu.bhagat@oracle.com/mbox/" "3772,https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-15-indu.bhagat@oracle.com/mbox/" "3773,https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-16-indu.bhagat@oracle.com/mbox/"' ++ echo '"3759' ++ sed 's/"//g' + series_patch_id=3759 ++ echo 'https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-2-indu.bhagat@oracle.com/mbox/"' ++ sed 's/"//g' + series_patch_url=https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-2-indu.bhagat@oracle.com/mbox/ ++ git rev-parse HEAD + commitid_before=02a8b5c25806339f801c80a5a364a963b2ece080 + eval '+++ declare -p bout bret declare -- bout="Applying: sframe.h: Add SFrame format definition" declare -- bret="0" ++ berr='\''++++ git_am https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-2-indu.bhagat@oracle.com/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-2-indu.bhagat@oracle.com/mbox/ ++++ curl https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-2-indu.bhagat@oracle.com/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 24791 100 24791 0 0 327k 0 --:--:-- --:--:-- --:--:-- 327k +++ bout='\''\'\'''\''Applying: sframe.h: Add SFrame format definition'\''\'\'''\'' +++ bret=0'\'' ++ declare -p berr declare -- berr="++++ git_am https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-2-indu.bhagat@oracle.com/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-2-indu.bhagat@oracle.com/mbox/ ++++ curl https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-2-indu.bhagat@oracle.com/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 24791 100 24791 0 0 327k 0 --:--:-- --:--:-- --:--:-- 327k +++ bout='\''Applying: sframe.h: Add SFrame format definition'\'' +++ bret=0"' ++ +++ declare -p bout bret /tmp/jenkins595743820157110727.sh: line 113: +++: command not found ++ declare -- 'bout=Applying: sframe.h: Add SFrame format definition' ++ declare -- bret=0 ++ ++ 'berr=++++ git_am https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-2-indu.bhagat@oracle.com/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-2-indu.bhagat@oracle.com/mbox/ ++++ curl https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-2-indu.bhagat@oracle.com/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 24791 100 24791 0 0 327k 0 --:--:-- --:--:-- --:--:-- 327k +++ bout='\''Applying: sframe.h: Add SFrame format definition'\'' +++ bret=0' /tmp/jenkins595743820157110727.sh: line 124: ++: command not found ++ ++ declare -p berr /tmp/jenkins595743820157110727.sh: line 125: ++: command not found ++ declare -- 'berr=++++ git_am https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-2-indu.bhagat@oracle.com/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-2-indu.bhagat@oracle.com/mbox/ ++++ curl https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-2-indu.bhagat@oracle.com/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 24791 100 24791 0 0 327k 0 --:--:-- --:--:-- --:--:-- 327k +++ bout='\''Applying: sframe.h: Add SFrame format definition'\'' +++ bret=0' ++ git rev-parse HEAD + commitid_after=ca7bb98256a2ec06f260132b20e13ceaa06708d4 + '[' 0 = 0 ']' + '[' ca7bb98256a2ec06f260132b20e13ceaa06708d4 = 02a8b5c25806339f801c80a5a364a963b2ece080 ']' + '[' 3759 = 3765 ']' + IFS=, + read -r series_patch_id series_patch_url ++ sed 's/"//g' ++ echo '"3762' + series_patch_id=3762 ++ echo 'https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-3-indu.bhagat@oracle.com/mbox/"' ++ sed 's/"//g' + series_patch_url=https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-3-indu.bhagat@oracle.com/mbox/ ++ git rev-parse HEAD + commitid_before=ca7bb98256a2ec06f260132b20e13ceaa06708d4 + eval '+++ declare -p bout bret declare -- bout="Applying: gas: add new command line option --gsframe" declare -- bret="0" ++ berr='\''++++ git_am https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-3-indu.bhagat@oracle.com/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-3-indu.bhagat@oracle.com/mbox/ ++++ curl https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-3-indu.bhagat@oracle.com/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 15099 100 15099 0 0 368k 0 --:--:-- --:--:-- --:--:-- 368k +++ bout='\''\'\'''\''Applying: gas: add new command line option --gsframe'\''\'\'''\'' +++ bret=0'\'' ++ declare -p berr declare -- berr="++++ git_am https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-3-indu.bhagat@oracle.com/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-3-indu.bhagat@oracle.com/mbox/ ++++ curl https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-3-indu.bhagat@oracle.com/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 15099 100 15099 0 0 368k 0 --:--:-- --:--:-- --:--:-- 368k +++ bout='\''Applying: gas: add new command line option --gsframe'\'' +++ bret=0"' ++ +++ declare -p bout bret /tmp/jenkins595743820157110727.sh: line 113: +++: command not found ++ declare -- 'bout=Applying: gas: add new command line option --gsframe' ++ declare -- bret=0 ++ ++ 'berr=++++ git_am https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-3-indu.bhagat@oracle.com/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-3-indu.bhagat@oracle.com/mbox/ ++++ curl https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-3-indu.bhagat@oracle.com/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 15099 100 15099 0 0 368k 0 --:--:-- --:--:-- --:--:-- 368k +++ bout='\''Applying: gas: add new command line option --gsframe'\'' +++ bret=0' /tmp/jenkins595743820157110727.sh: line 124: ++: command not found ++ ++ declare -p berr /tmp/jenkins595743820157110727.sh: line 125: ++: command not found ++ declare -- 'berr=++++ git_am https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-3-indu.bhagat@oracle.com/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-3-indu.bhagat@oracle.com/mbox/ ++++ curl https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-3-indu.bhagat@oracle.com/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 15099 100 15099 0 0 368k 0 --:--:-- --:--:-- --:--:-- 368k +++ bout='\''Applying: gas: add new command line option --gsframe'\'' +++ bret=0' ++ git rev-parse HEAD + commitid_after=a1ee9ff450ca723003d390978c7f6592770562c6 + '[' 0 = 0 ']' + '[' a1ee9ff450ca723003d390978c7f6592770562c6 = ca7bb98256a2ec06f260132b20e13ceaa06708d4 ']' + '[' 3762 = 3765 ']' + IFS=, + read -r series_patch_id series_patch_url ++ echo '"3761' ++ sed 's/"//g' + series_patch_id=3761 ++ echo 'https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-4-indu.bhagat@oracle.com/mbox/"' ++ sed 's/"//g' + series_patch_url=https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-4-indu.bhagat@oracle.com/mbox/ ++ git rev-parse HEAD + commitid_before=a1ee9ff450ca723003d390978c7f6592770562c6 + eval '+++ declare -p bout bret declare -- bout="Applying: gas: generate .sframe from CFI directives" declare -- bret="0" ++ berr='\''++++ git_am https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-4-indu.bhagat@oracle.com/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-4-indu.bhagat@oracle.com/mbox/ ++++ curl https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-4-indu.bhagat@oracle.com/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 82805 100 82805 0 0 1078k 0 --:--:-- --:--:-- --:--:-- 1078k +++ bout='\''\'\'''\''Applying: gas: generate .sframe from CFI directives'\''\'\'''\'' +++ bret=0'\'' ++ declare -p berr declare -- berr="++++ git_am https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-4-indu.bhagat@oracle.com/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-4-indu.bhagat@oracle.com/mbox/ ++++ curl https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-4-indu.bhagat@oracle.com/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 82805 100 82805 0 0 1078k 0 --:--:-- --:--:-- --:--:-- 1078k +++ bout='\''Applying: gas: generate .sframe from CFI directives'\'' +++ bret=0"' ++ +++ declare -p bout bret /tmp/jenkins595743820157110727.sh: line 113: +++: command not found ++ declare -- 'bout=Applying: gas: generate .sframe from CFI directives' ++ declare -- bret=0 ++ ++ 'berr=++++ git_am https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-4-indu.bhagat@oracle.com/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-4-indu.bhagat@oracle.com/mbox/ ++++ curl https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-4-indu.bhagat@oracle.com/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 82805 100 82805 0 0 1078k 0 --:--:-- --:--:-- --:--:-- 1078k +++ bout='\''Applying: gas: generate .sframe from CFI directives'\'' +++ bret=0' /tmp/jenkins595743820157110727.sh: line 124: ++: command not found ++ ++ declare -p berr /tmp/jenkins595743820157110727.sh: line 125: ++: command not found ++ declare -- 'berr=++++ git_am https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-4-indu.bhagat@oracle.com/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-4-indu.bhagat@oracle.com/mbox/ ++++ curl https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-4-indu.bhagat@oracle.com/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 82805 100 82805 0 0 1078k 0 --:--:-- --:--:-- --:--:-- 1078k +++ bout='\''Applying: gas: generate .sframe from CFI directives'\'' +++ bret=0' ++ git rev-parse HEAD + commitid_after=8c51c58034a00fe00264e1ec301b071d669fccd8 + '[' 0 = 0 ']' + '[' 8c51c58034a00fe00264e1ec301b071d669fccd8 = a1ee9ff450ca723003d390978c7f6592770562c6 ']' + '[' 3761 = 3765 ']' + IFS=, + read -r series_patch_id series_patch_url ++ sed 's/"//g' ++ echo '"3760' + series_patch_id=3760 ++ sed 's/"//g' ++ echo 'https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-5-indu.bhagat@oracle.com/mbox/"' + series_patch_url=https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-5-indu.bhagat@oracle.com/mbox/ ++ git rev-parse HEAD + commitid_before=8c51c58034a00fe00264e1ec301b071d669fccd8 + eval '+++ declare -p bout bret declare -- bout="Applying: gas: testsuite: add new tests for SFrame unwind info" declare -- bret="0" ++ berr='\''++++ git_am https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-5-indu.bhagat@oracle.com/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-5-indu.bhagat@oracle.com/mbox/ ++++ git am -3 --empty=drop ++++ curl https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-5-indu.bhagat@oracle.com/mbox/ % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 37022 100 37022 0 0 344k 0 --:--:-- --:--:-- --:--:-- 344k +++ bout='\''\'\'''\''Applying: gas: testsuite: add new tests for SFrame unwind info'\''\'\'''\'' +++ bret=0'\'' ++ declare -p berr declare -- berr="++++ git_am https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-5-indu.bhagat@oracle.com/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-5-indu.bhagat@oracle.com/mbox/ ++++ git am -3 --empty=drop ++++ curl https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-5-indu.bhagat@oracle.com/mbox/ % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 37022 100 37022 0 0 344k 0 --:--:-- --:--:-- --:--:-- 344k +++ bout='\''Applying: gas: testsuite: add new tests for SFrame unwind info'\'' +++ bret=0"' ++ +++ declare -p bout bret /tmp/jenkins595743820157110727.sh: line 113: +++: command not found ++ declare -- 'bout=Applying: gas: testsuite: add new tests for SFrame unwind info' ++ declare -- bret=0 ++ ++ 'berr=++++ git_am https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-5-indu.bhagat@oracle.com/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-5-indu.bhagat@oracle.com/mbox/ ++++ git am -3 --empty=drop ++++ curl https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-5-indu.bhagat@oracle.com/mbox/ % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 37022 100 37022 0 0 344k 0 --:--:-- --:--:-- --:--:-- 344k +++ bout='\''Applying: gas: testsuite: add new tests for SFrame unwind info'\'' +++ bret=0' /tmp/jenkins595743820157110727.sh: line 124: ++: command not found ++ ++ declare -p berr /tmp/jenkins595743820157110727.sh: line 125: ++: command not found ++ declare -- 'berr=++++ git_am https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-5-indu.bhagat@oracle.com/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-5-indu.bhagat@oracle.com/mbox/ ++++ git am -3 --empty=drop ++++ curl https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-5-indu.bhagat@oracle.com/mbox/ % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 37022 100 37022 0 0 344k 0 --:--:-- --:--:-- --:--:-- 344k +++ bout='\''Applying: gas: testsuite: add new tests for SFrame unwind info'\'' +++ bret=0' ++ git rev-parse HEAD + commitid_after=a31da5c293a35a2e2f85cb4db1f37aa63c863dd9 + '[' 0 = 0 ']' + '[' a31da5c293a35a2e2f85cb4db1f37aa63c863dd9 = 8c51c58034a00fe00264e1ec301b071d669fccd8 ']' + '[' 3760 = 3765 ']' + IFS=, + read -r series_patch_id series_patch_url ++ sed 's/"//g' ++ echo '"3764' + series_patch_id=3764 ++ sed 's/"//g' ++ echo 'https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-6-indu.bhagat@oracle.com/mbox/"' + series_patch_url=https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-6-indu.bhagat@oracle.com/mbox/ ++ git rev-parse HEAD + commitid_before=a31da5c293a35a2e2f85cb4db1f37aa63c863dd9 + eval '+++ declare -p bout bret declare -- bout="git: apply.c:3717: check_preimage: Assertion \`patch->is_new <= 0'\'' failed." declare -- bret="134" ++ berr='\''++++ git_am https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-6-indu.bhagat@oracle.com/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-6-indu.bhagat@oracle.com/mbox/ ++++ git am -3 --empty=drop ++++ curl https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-6-indu.bhagat@oracle.com/mbox/ % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 317k 100 317k 0 0 2129k 0 --:--:-- --:--:-- --:--:-- 2114k +++ bout='\''\'\'''\''git: apply.c:3717: check_preimage: Assertion `patch->is_new <= 0'\''\'\'''\''\'\''\'\'''\'''\''\'\'''\'' failed.'\''\'\'''\'' +++ bret=134'\'' ++ declare -p berr declare -- berr="++++ git_am https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-6-indu.bhagat@oracle.com/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-6-indu.bhagat@oracle.com/mbox/ ++++ git am -3 --empty=drop ++++ curl https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-6-indu.bhagat@oracle.com/mbox/ % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 317k 100 317k 0 0 2129k 0 --:--:-- --:--:-- --:--:-- 2114k +++ bout='\''git: apply.c:3717: check_preimage: Assertion \`patch->is_new <= 0'\''\\'\'''\'' failed.'\'' +++ bret=134"' ++ +++ declare -p bout bret /tmp/jenkins595743820157110727.sh: line 113: +++: command not found ++ declare -- 'bout=git: apply.c:3717: check_preimage: Assertion `patch->is_new <= 0'\'' failed.' ++ declare -- bret=134 ++ ++ 'berr=++++ git_am https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-6-indu.bhagat@oracle.com/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-6-indu.bhagat@oracle.com/mbox/ ++++ git am -3 --empty=drop ++++ curl https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-6-indu.bhagat@oracle.com/mbox/ % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 317k 100 317k 0 0 2129k 0 --:--:-- --:--:-- --:--:-- 2114k +++ bout='\''git: apply.c:3717: check_preimage: Assertion `patch->is_new <= 0'\''\'\'''\'' failed.'\'' +++ bret=134' /tmp/jenkins595743820157110727.sh: line 124: ++: command not found ++ ++ declare -p berr /tmp/jenkins595743820157110727.sh: line 125: ++: command not found ++ declare -- 'berr=++++ git_am https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-6-indu.bhagat@oracle.com/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-6-indu.bhagat@oracle.com/mbox/ ++++ git am -3 --empty=drop ++++ curl https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-6-indu.bhagat@oracle.com/mbox/ % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 317k 100 317k 0 0 2129k 0 --:--:-- --:--:-- --:--:-- 2114k +++ bout='\''git: apply.c:3717: check_preimage: Assertion `patch->is_new <= 0'\''\'\'''\'' failed.'\'' +++ bret=134' ++ git rev-parse HEAD + commitid_after=a31da5c293a35a2e2f85cb4db1f37aa63c863dd9 + '[' 134 = 0 ']' + [[ ++++ git_am https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-6-indu.bhagat@oracle.com/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-6-indu.bhagat@oracle.com/mbox/ ++++ git am -3 --empty=drop ++++ curl https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-6-indu.bhagat@oracle.com/mbox/ % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 317k 100 317k 0 0 2129k 0 --:--:-- --:--:-- --:--:-- 2114k +++ bout='git: apply.c:3717: check_preimage: Assertion `patch->is_new <= 0'\'' failed.' +++ bret=134 =~ sha1 information is lacking or useless ]] + [[ ++++ git_am https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-6-indu.bhagat@oracle.com/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-6-indu.bhagat@oracle.com/mbox/ ++++ git am -3 --empty=drop ++++ curl https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-6-indu.bhagat@oracle.com/mbox/ % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 317k 100 317k 0 0 2129k 0 --:--:-- --:--:-- --:--:-- 2114k +++ bout='git: apply.c:3717: check_preimage: Assertion `patch->is_new <= 0'\'' failed.' +++ bret=134 =~ Failed to merge in the changes ]] + [[ ++++ git_am https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-6-indu.bhagat@oracle.com/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-6-indu.bhagat@oracle.com/mbox/ ++++ git am -3 --empty=drop ++++ curl https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-6-indu.bhagat@oracle.com/mbox/ % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 317k 100 317k 0 0 2129k 0 --:--:-- --:--:-- --:--:-- 2114k +++ bout='git: apply.c:3717: check_preimage: Assertion `patch->is_new <= 0'\'' failed.' +++ bret=134 =~ corrupt patch at ]] + submit_check fail 'Not Applicable' https://patchwork.plctlab.org/jenkins/job/binutils-gdb/131/consoleText 'Git am fail log' + check_state=fail + patch_state='Not Applicable' + repo_url=https://patchwork.plctlab.org/jenkins/job/binutils-gdb/131/consoleText + DESCRIPTION='Git am fail log' + curl -X POST -H 'Authorization: Token [*******]' -F state=fail -F target_url=https://patchwork.plctlab.org/jenkins/job/binutils-gdb/131/consoleText -F context=binutils-gdb-check -F 'description=Git am fail log' https://patchwork.plctlab.org/api/patches/3765/checks/ % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 968 100 426 100 542 17750 22583 --:--:-- --:--:-- --:--:-- 40333 {"id":1071,"url":"https://patchwork.plctlab.org/api/patches/3765/checks/1071/","user":{"id":1,"url":"https://patchwork.plctlab.org/api/users/1/","username":"snail","first_name":"","last_name":"","email":"wangliu@iscas.ac.cn"},"date":"2022-10-18T01:18:42.331250","state":"fail","target_url":"https://patchwork.plctlab.org/jenkins/job/binutils-gdb/131/consoleText","context":"binutils-gdb-check","description":"Git am fail log"}+ curl -X PATCH -H 'Authorization: Token [*******]' -F 'state=Not Applicable' https://patchwork.plctlab.org/api/1.2/patches/3765/ % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0{"id":3765,"url":"https://patchwork.plctlab.org/api/1.2/patches/3765/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-9-indu.bhagat@oracle.com/","project":{"id":2,"url":"https://patchwork.plctlab.org/api/1.2/projects/2/","name":"binutils-gdb","link_name":"binutils-gdb","list_id":"binutils.sourceware.org","list_email":"binutils@sourceware.org","web_url":"https://sourceware.org/mailman/listinfo/binutils","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20221017221612.495324-9-indu.bhagat@oracle.com>","list_archive_url":null,"date":"2022-10-17T22:16:05","name":"[V2,08/15] unwinder: generate backtrace using SFrame format","commit_ref":null,"pull_url":null,"state":"not-applicable","archived":false,"hash":"3c42b97a5fade3d988c4ce006ffe8aa0ca540854","submitter":{"id":35,"url":"https://patchwork.plctlab.org/api/1.2/people/35/","name":"Indu Bhagat","email":"indu.bhagat@oracle.com"},"delegate":null,"mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221017221612.495324-9-indu.bhagat@oracle.com/mbox/","series":[{"id":2418,"url":"https://patchwork.plctlab.org/api/1.2/series/2418/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/list/?series=2418","date":"2022-10-17T22:15:58","name":"Definition and support for SFrame unwind format","version":2,"mbox":"https://patchwork.plctlab.org/series/2418/mbox/"}],"comments":"https://patchwork.plctlab.org/api/patches/3765/comments/","check":"fail","checks":"https://patchwork.plctlab.org/api/patches/3765/checks/","tags":{},"headers":{"Return-Path":"","Delivered-To":["ouuuleilei@gmail.com","binutils@sourceware.org"],"Received":["by 2002:a5d:4ac7:0:0:0:0:0 with SMTP id y7csp1667219wrs;\n Mon, 17 Oct 2022 15:21:30 -0700 (PDT)","from sourceware.org (server2.sourceware.org. [8.43.85.97])\n by mx.google.com with ESMTPS id\n f21-20020a50fc95000000b004550b5a8f20si9348028edq.422.2022.10.17.15.21.30\n for \n (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256);\n Mon, 17 Oct 2022 15:21:30 -0700 (PDT)","from server2.sourceware.org (localhost [IPv6:::1])\n\tby sourceware.org (Postfix) with ESMTP id AEBC2384BC2B\n\tfor ; Mon, 17 Oct 2022 22:19:13 +0000 (GMT)","from mx0b-00069f02.pphosted.com (mx0b-00069f02.pphosted.com\n [205.220.177.32])\n by sourceware.org (Postfix) with ESMTPS id 0A3483854835\n for ; Mon, 17 Oct 2022 22:17:22 +0000 (GMT)","from pps.filterd (m0246632.ppops.net [127.0.0.1])\n by mx0b-00069f02.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id\n 29HLmj0F008250;\n Mon, 17 Oct 2022 22:17:20 GMT","from phxpaimrmta02.imrmtpd1.prodappphxaev1.oraclevcn.com\n (phxpaimrmta02.appoci.oracle.com [147.154.114.232])\n by mx0b-00069f02.pphosted.com (PPS) with ESMTPS id 3k7mtyw471-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK);\n Mon, 17 Oct 2022 22:17:19 +0000","from pps.filterd\n (phxpaimrmta02.imrmtpd1.prodappphxaev1.oraclevcn.com [127.0.0.1])\n by phxpaimrmta02.imrmtpd1.prodappphxaev1.oraclevcn.com (8.17.1.5/8.17.1.5)\n with ESMTP id 29HKYYp4019181; Mon, 17 Oct 2022 22:17:18 GMT","from nam12-bn8-obe.outbound.protection.outlook.com\n (mail-bn8nam12lp2177.outbound.protection.outlook.com [104.47.55.177])\n by phxpaimrmta02.imrmtpd1.prodappphxaev1.oraclevcn.com (PPS) with ESMTPS id\n 3k8j0prhm3-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK);\n Mon, 17 Oct 2022 22:17:18 +0000","from BN6PR1001MB2147.namprd10.prod.outlook.com\n (2603:10b6:405:2e::26) by MW4PR10MB5862.namprd10.prod.outlook.com\n (2603:10b6:303:18f::7) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5723.26; Mon, 17 Oct\n 2022 22:17:15 +0000","from BN6PR1001MB2147.namprd10.prod.outlook.com\n ([fe80::c713:91f4:e197:acd2]) by BN6PR1001MB2147.namprd10.prod.outlook.com\n ([fe80::c713:91f4:e197:acd2%5]) with mapi id 15.20.5709.028; Mon, 17 Oct 2022\n 22:17:15 +0000"],"X-Google-Smtp-Source":"\n AMsMyM7BVPVC4XztHrAidMkCuzSjl0mtjg/PAO2aikb9MzoUeX/jsKnARZmSZD9xdxfh3LMdO2eS","X-Received":"by 2002:a17:906:4fcb:b0:791:9a26:376f with SMTP id\n i11-20020a1709064fcb00b007919a26376fmr1312419ejw.431.1666045290597;\n Mon, 17 Oct 2022 15:21:30 -0700 (PDT)","Received-SPF":"pass (google.com: domain of\n binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 8.43.85.97 as\n permitted sender) client-ip=8.43.85.97;","Authentication-Results":"mx.google.com;\n dkim=pass header.i=@sourceware.org header.s=default\n header.b=\"T/l8HYRS\";\n arc=fail (signature failed);\n spf=pass (google.com: domain of\n binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 8.43.85.97 as\n permitted sender)\n smtp.mailfrom=\"binutils-bounces+ouuuleilei=gmail.com@sourceware.org\";\n dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=sourceware.org","DKIM-Filter":"OpenDKIM Filter v2.11.0 sourceware.org AEBC2384BC2B","DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org;\n\ts=default; t=1666045153;\n\tbh=QtTN9KasW7Y/L3N2GIyVyUQ/ADl6tUftPPoC6lBh5/8=;\n\th=To:Subject:Date:In-Reply-To:References:List-Id:List-Unsubscribe:\n\t List-Archive:List-Post:List-Help:List-Subscribe:From:Reply-To:\n\t From;\n\tb=T/l8HYRSQAlJVb+IclB5I8FCf4k1RplKKFAr+icDW7V8SdSPvHtwxfVFJzh5bgebW\n\t eZcJu4XPIzTUMGUfs6NiMwrZyEeRe1jDVPi+LfKMh2IGBswIgCU5aL8OThJKpR+z9c\n\t y0Qp+kRshMyySZqpaK2hQ67G+dybM55SbhA1ZcGk=","X-Original-To":"binutils@sourceware.org","DMARC-Filter":"OpenDMARC Filter v1.4.1 sourceware.org 0A3483854835","ARC-Seal":"i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none;\n b=OzIN2bjyhaAdP9yT/fflCmp0nJ7X6LDcZ5ZhvSjo26GKRQxemm/OyJuvIq64BgTpgX5zsETbrIJNR92WeNk0LZ+4LqVIsLTXaYEN7SBLSEDBq4p8kvhvadZme0fL8rws85G9U964FijUQqrP9k0e3FZHCRD8Lc1HXBC4/Yn9EvtnS7PPjW3xsIY4ovFx+16f3UJGXagVx1rts5kNfNhPN34LEvntrcKCDZMCgESQPP91D40RL1SgoLSgf+y0L9CiZWrAw+KucwK/20X13M+n2wd6svn9rVJRQE5Xu75EUMTmQ4b/LTNKR2NAo9eRVsgFpmhHDqUxOd6U15It+0v0fg==","ARC-Message-Signature":"i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com;\n s=arcselector9901;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1;\n bh=QtTN9KasW7Y/L3N2GIyVyUQ/ADl6tUftPPoC6lBh5/8=;\n b=U1ojiT3AGOA00TOEQtzDgkwoWeSPWBpfX6a0nNCVkugvnG69L4ZeJcbId8scpsdsaQIapkC4NnVKehCl3eA/44P+TSwZiJJYXc2bilsWBx0aBDM+8e6BY96qYT6WBodkFwV/smKurcAqdkTEDnH+uUvhPbTt/7HVT2egS8xGH5RQYZXXNVLQkcC1ePZAqo4DHSWsZRq1aRAidYuBxFR1WymcliV1xIWQ90ytm9ovSquh29CEOeqsUJIVCBJoU6IVDgsbTq5R8/NQdIEmydGvjQeOqIAdfjxLyn17ngkDeGHFJq5PB/koKV/TY3rAsHal807Q/lrcy/P5+ZTe6mKK8Q==","ARC-Authentication-Results":"i=1; mx.microsoft.com 1; spf=pass\n smtp.mailfrom=oracle.com; dmarc=pass action=none header.from=oracle.com;\n dkim=pass header.d=oracle.com; arc=none","To":"binutils@sourceware.org","Subject":"[PATCH,V2 08/15] unwinder: generate backtrace using SFrame format","Date":"Mon, 17 Oct 2022 15:16:05 -0700","Message-Id":"<20221017221612.495324-9-indu.bhagat@oracle.com>","X-Mailer":"git-send-email 2.37.2","In-Reply-To":"<20221017221612.495324-1-indu.bhagat@oracle.com>","References":"<20221017221612.495324-1-indu.bhagat@oracle.com>","Content-Transfer-Encoding":"8bit","Content-Type":"text/plain","X-ClientProxiedBy":"MW4PR03CA0254.namprd03.prod.outlook.com\n (2603:10b6:303:b4::19) To BN6PR1001MB2147.namprd10.prod.outlook.com\n (2603:10b6:405:2e::26)","MIME-Version":"1.0","X-MS-PublicTrafficType":"Email","X-MS-TrafficTypeDiagnostic":"BN6PR1001MB2147:EE_|MW4PR10MB5862:EE_","X-MS-Office365-Filtering-Correlation-Id":"42f2e614-c351-4004-e84a-08dab08d58d8","X-MS-Exchange-SenderADCheck":"1","X-MS-Exchange-AntiSpam-Relay":"0","X-Microsoft-Antispam":"BCL:0;","X-Microsoft-Antispam-Message-Info":"\n 7nd+1X9dmJMaChXPnkNR+ESUq8YarkvqM2BHMg4HOCyu9k/pBzBgwnDqI0CBYgma8zAizYq6OtDMShLAx0Tr2bybqxK7PCxOnT2dZdqDz7G5atKWr+apfMPwH412rr5zrYoJqvY067gTZuiRGuvxaGYkMLbfX/ltY+A0chXrZTgvykgYzHkCvTI1LKjULGrPlwwPdeYI80dEicidBuOKfBtnpFjVYi/q/OzZ/69fGEkmvB4noZTs3Z17LYnff012alRuM9GMn7JlbQZ+qBvfx8xE/sBXWj5miA8m6xHHkQuI7jTp00ACUoJmVZRiSJ0GbxVVHX/FeZNVqDmysU4d5h5ai71VUm9+h6m4GCgTnqHTwThdXvzF0ud7JLnjEGbhpe1zkMHsttxrpq7CGdu8NKiERZodEgUx4zUyDfxS0iCHGGK+exFEz7Io7xAAbehVH+HZJhHNftVWOKQAru6GuVYj/3/oha7X+znhZ9AbBWId+iy1wAojOTMJUylEvmnDAnVUHku079z6ou0XNYbIJ8HvlrZA8q/iykimavWiU2SKul2XzPbjQnEN4OYufdhN6STgutmv3Lz3y46ixQ8lxYsXSH5S2xx0C/zFAkI5RNLBbxTqS/UTQQamz7rBC4TbQdeZvU07xsyDllZXST3bG5O21zk+CsEiWQlJSRyI52wOttDBdSMDwkCH2kIqTgClq5hfUCdwtiO+PcG9qGEPuCMETagXDyOusyEIec3NFUie2DxrC9VhbYGtc5TvAfLWH8Wi1k4DX7h+E/fSHxm1EQ==","X-Forefront-Antispam-Report":"CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:;\n IPV:NLI; SFV:NSPM; H:BN6PR1001MB2147.namprd10.prod.outlook.com; PTR:;\n CAT:NONE;\n SFS:(13230022)(396003)(366004)(39860400002)(136003)(376002)(346002)(451199015)(83380400001)(36756003)(86362001)(38100700002)(107886003)(6666004)(66946007)(66556008)(6916009)(316002)(5660300002)(44832011)(30864003)(8936002)(186003)(66476007)(6486002)(1076003)(2906002)(2616005)(478600001)(6506007)(6512007)(41300700001)(4326008)(8676002)(2004002);\n DIR:OUT; SFP:1101;","X-MS-Exchange-AntiSpam-MessageData-ChunkCount":"1","X-MS-Exchange-AntiSpam-MessageData-0":"\n X0ohdLPM/ZFY2DeQSQ2RfCJkhz1Jk6zjJDIjOKvtC+gXy8vFMbOOwQ/J4jlIJe9GlD1D1BbMXexTXsIpCvKtgJQ9dO+5iD4gVAXKWBBnhK9Y6f54EWcsknaJCcoyksdAdX2d0mRj8Ho85zKUKCreUNfHkmV6GK/wi2N2wy1M9x7O35Ynsnredo3p8fcKMkXuxlY24m4oXkLAE91KwQWwE5r9L9mEGfsalVxAWHNjeJv6z5ETTFOVBlWpsxjTUtQ65530pyhgy4QKGEc4GgqTGCMFmpXPvp/SceLE4aARz/fTAwd8LZvw5bjOKAQd39KtOsUL4gvWNExVh0JNc5SYvDP4j870BkyCbLiJtVRyL/e5sRjU4g8sMcX8OAZkoA6RrB6k9onMhOLDmGueGB5/ZmpY2VYxLoSp29Z6uriTui9VnBcGnTqqa+xmdm+0eGn0R/wWD0ixWNdObhOCM7GsUMjKWMGZ+nJdVavJ2VhjC5SjsH50GX0Qk1dJT9fgI4H/cm7Wd/BViDnZkUhJ2nwt2EjttuE912tkb+3+Z9Ptqnhg+1urfSiO+xn3LbRmtR0Suhxy0E253A9QDQeM+PxUXoEgTvxNZpCGTXQzSC9+d9lMyI7cSdtLdxjPs6bUt2YTJCRkhYElVYTuQ0tfcoY+3cQKD2Pt0PdB0Oo3upwAeuKA3wKNZlh5uRBzxT51qL4hMbn/hAjXg1jIbHNnJo1JeK6KaYbz0/jL2M78a+9eNfvkxUHGFAQ3iSstEXxVougnmlSeXYGhy0KNH32r78gHZalSUpAWUp+rhrUxTn2jQVpbCtV1th3Z904QagN5hiw6S77rQM2thxQHEm6OPU6YDCxpQDf6uRlqW6shhEF6tD89L7lDtG87Ou/8u8Kk8AAl1qcds85LUF1RRUSWzTwyhgfCMIMUO124Jf/z8QMzykU6XgUxqZK9BBRY+19qme3oSEqkr2VEuX74KXYrWuMT0v55k0yexnvKK+O+UOVcf2yT3v0R0qEKdNNJzPLVy1o9zx30GkjFI4jmZUyZBD45HKNBX2Ql4qvmc8p6objcvzAEfli91y2f3orDKOVWIY42AzoHINhxmFWlCllUxyVdPSwliXq67jAvQIIenGImkqHTdmkDyAPfBV1a/1kANQa4/n2SSbZeFL6pCDqXq8Xt7wKogpdHHxqUnDx3UCevxwJFbhe/YbG8HCwBiw9jXxgzTx6ompD5O+AJmbdwRExpgqUj2e+C/o7l9/Rm9txozs6W7Yd0uSFtWXztQ+QJJHaB07O37nYxYE9z0EQxqo3Q7rWBFBika1Q4W8v50ITI9wt8y2S06UTKxW8J17uERP4QEO+oObJUroMWu2oPSv2CEcWLqBci8uFMBHwwbUfL+T+L/bho6sQJeGaJMRkZ9Gc4MqtnVJ2bZwFjr9ycnxIJOKTxlK8xwCyqvcLqhzPB7HPkafjUG9fj+m/mE2TcvSboQbrg1/o2p8IioCX5nIDtKBb6Ik3kA1dD3EuPozlwHpTProyD4OfV55hRMokLiNM16LLvEeQCro9AnW5RT165c2fQK2+4DnpJJATKeNSkQJ3mdCknsjRYFfXJxEJNqlWBVV/4eh3/gHQcKQf6DZRhLEvUYnfPae+KNYWx5vdrw2w=","X-OriginatorOrg":"oracle.com","X-MS-Exchange-CrossTenant-Network-Message-Id":"\n 42f2e614-c351-4004-e84a-08dab08d58d8","X-MS-Exchange-CrossTenant-AuthSource":"\n BN6PR1001MB2147.namprd10.prod.outlook.com","X-MS-Exchange-CrossTenant-AuthAs":"Internal","X-MS-Exchange-CrossTenant-OriginalArrivalTime":"17 Oct 2022 22:17:15.6021 (UTC)","X-MS-Exchange-CrossTenant-FromEntityHeader":"Hosted","X-MS-Exchange-CrossTenant-Id":"4e2c6054-71cb-48f1-bd6c-3a9705aca71b","X-MS-Exchange-CrossTenant-MailboxType":"HOSTED","X-MS-Exchange-CrossTenant-UserPrincipalName":"\n Z/quApqxeoZZ/HQ8iswSPl8b//sDXpxFXhk41VAkZW/SqSYYyNQaRnsBg8CskxME7Wt1u5tdMIQUQpuimlJgJA==","X-MS-Exchange-Transport-CrossTenantHeadersStamped":"MW4PR10MB5862","X-Proofpoint-Virus-Version":"vendor=baseguard\n engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.545,FMLib:17.11.122.1\n definitions=2022-10-17_13,2022-10-17_02,2022-06-22_01","X-Proofpoint-Spam-Details":"rule=notspam policy=default score=0 spamscore=0\n bulkscore=0 mlxscore=0\n suspectscore=0 mlxlogscore=999 phishscore=0 malwarescore=0 adultscore=0\n classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2209130000\n definitions=main-2210170127","X-Proofpoint-ORIG-GUID":"w-w3i5rgucFY1BCS38UJWHmgpVhqrCsX","X-Proofpoint-GUID":"w-w3i5rgucFY1BCS38UJWHmgpVhqrCsX","X-Spam-Status":"No, score=-13.3 required=5.0 tests=BAYES_00, DKIM_SIGNED,\n DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT,\n RCVD_IN_DNSWL_LOW, RCVD_IN_MSPIKE_H2, SPF_HELO_NONE, SPF_NONE,\n TXREP autolearn=ham autolearn_force=no version=3.4.6","X-Spam-Checker-Version":"SpamAssassin 3.4.6 (2021-04-09) on\n server2.sourceware.org","X-BeenThere":"binutils@sourceware.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"Binutils mailing list ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","From":"Indu Bhagat via Binutils ","Reply-To":"Indu Bhagat ","Errors-To":"binutils-bounces+ouuuleilei=gmail.com@sourceware.org","Sender":"\"Binutils\" ","X-getmail-retrieved-from-mailbox":"=?utf-8?q?INBOX?=","X-GMAIL-THRID":"=?utf-8?q?1746975107063251018?=","X-GMAIL-MSGID":"=?utf-8?q?1746975107063251018?="},"content":"From: Weimin Pan \n\n[Changes in V2]\n - Minor formatting fixes.\n[End of changes in V2]\n\nA simple unwinder based on SFrame format.\n\nThe unwinder is made available via libsframebt library.\n\nBuildsystem changes have been made to build libsframebt only when\n--gsframe support is available in the assembler. These buildsystem\nchanges are necessary because the SFrame based unwinder the SFrame\nunwind info for itself to work.\n\nPS: libsframe/configure has NOT been included in the patch. Please\nregenerate.\n\nconfig/ChangeLog:\n\n\t* sframe.m4: New file.\n\ninclude/ChangeLog:\n\n\t* sframe-backtrace-api.h: New file.\n\nChangeLog:\n\n\t* libsframe/Makefile.am: Build backtrace functionality in its\n\town library. Install libsframebt conditionally.\n\t* libsframe/Makefile.in: Regenerate.\n\t* libsframe/aclocal.m4: Regenerate.\n\t* libsframe/configure: Regenerate. <-- [REMOVED FROM THE PATCH.\n\t PLEASE REGENERATE. ]\n\t* libsframe/configure.ac: Check if gas supports --gsframe\n\tcommand line option.\n\t* libsframe/sframe-backtrace-err.c: New file.\n\t* libsframe/sframe-backtrace.c: New file.\n---\n config/sframe.m4 | 16 +\n include/sframe-backtrace-api.h | 57 ++\n libsframe/Makefile.am | 12 +\n libsframe/Makefile.in | 58 +-\n libsframe/aclocal.m4 | 1 +\n libsframe/configure.ac | 7 +\n libsframe/sframe-backtrace-err.c | 46 ++\n libsframe/sframe-backtrace.c | 620 ++++++++++++++++++\n libsframe/testsuite/Makefile.in | 1 +\n .../testsuite/libsframe.decode/Makefile.in | 1 +\n .../testsuite/libsframe.encode/Makefile.in | 1 +\n 11 files changed, 813 insertions(+), 7 deletions(-)\n create mode 100644 config/sframe.m4\n create mode 100644 include/sframe-backtrace-api.h\n create mode 100644 libsframe/sframe-backtrace-err.c\n create mode 100644 libsframe/sframe-backtrace.c","diff":"diff --git a/config/sframe.m4 b/config/sframe.m4\nnew file mode 100644\nindex 00000000000..9f149fda9ef\n--- /dev/null\n+++ b/config/sframe.m4\n@@ -0,0 +1,16 @@\n+# SFRAME_CHECK_AS_SFRAME\n+# ----------------------\n+# Check whether the assembler supports generation of SFrame\n+# unwind information.\n+#\n+# Defines:\n+# ac_cv_have_sframe\n+\n+AC_DEFUN([SFRAME_CHECK_AS_SFRAME],[\n+ ac_save_CFLAGS=\"$CFLAGS\"\n+ CFLAGS=\"$CFLAGS -Wa,--gsframe\"\n+ AC_MSG_CHECKING([for as that supports --gsframe])\n+ AC_TRY_COMPILE([], [return 0;], [ac_cv_have_sframe=yes], [ac_cv_have_sframe=no])\n+ AC_MSG_RESULT($ac_cv_have_sframe)\n+ CFLAGS=\"$ac_save_CFLAGS\"\n+])\ndiff --git a/include/sframe-backtrace-api.h b/include/sframe-backtrace-api.h\nnew file mode 100644\nindex 00000000000..ad8f6bed024\n--- /dev/null\n+++ b/include/sframe-backtrace-api.h\n@@ -0,0 +1,57 @@\n+/* Public API to SFrame backtrace.\n+\n+ Copyright (C) 2022 Free Software Foundation, Inc.\n+\n+ This file is part of libsframebt.\n+\n+ This program is free software; you can redistribute it and/or modify\n+ it under the terms of the GNU General Public License as published by\n+ the Free Software Foundation; either version 3 of the License, or\n+ (at your option) any later version.\n+\n+ This program is distributed in the hope that it will be useful,\n+ but WITHOUT ANY WARRANTY; without even the implied warranty of\n+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n+ GNU General Public License for more details.\n+\n+ You should have received a copy of the GNU General Public License\n+ along with this program. If not, see . */\n+\n+#ifndef\t_SFRAME_BACKTRACE_API_H\n+#define\t_SFRAME_BACKTRACE_API_H\n+\n+#ifdef\t__cplusplus\n+extern \"C\"\n+{\n+#endif\n+\n+enum sframe_bt_errcode\n+{\n+ SFRAME_BT_OK,\n+ SFRAME_BT_ERR_NOTPRESENT,\n+ SFRAME_BT_ERR_PHDR,\n+ SFRAME_BT_ERR_ARG,\n+ SFRAME_BT_ERR_MALLOC,\n+ SFRAME_BT_ERR_REALLOC,\n+ SFRAME_BT_ERR_OPEN,\n+ SFRAME_BT_ERR_READLINK,\n+ SFRAME_BT_ERR_LSEEK,\n+ SFRAME_BT_ERR_READ,\n+ SFRAME_BT_ERR_GETCONTEXT,\n+ SFRAME_BT_ERR_DECODE,\n+ SFRAME_BT_ERR_CFA_OFFSET,\n+};\n+\n+/* Get the backtrace of the calling program by storing return addresses\n+ in BUFFER. The SIZE argument specifies the maximum number of addresses\n+ that can be stored in the buffer. Return the number of return addresses\n+ collected or -1 if there is any error. */\n+extern int sframe_backtrace (void **buffer, int size, int *errp);\n+\n+extern const char *sframe_bt_errmsg (enum sframe_bt_errcode ecode);\n+\n+#ifdef\t__cplusplus\n+}\n+#endif\n+\n+#endif\t\t\t\t/* _SFRAME_BACKTRACE_API_H */\ndiff --git a/libsframe/Makefile.am b/libsframe/Makefile.am\nindex 31576429816..1b8a1081975 100644\n--- a/libsframe/Makefile.am\n+++ b/libsframe/Makefile.am\n@@ -40,3 +40,15 @@ endif\n libsframe_la_SOURCES = sframe.c sframe-dump.c sframe-error.c\n libsframe_la_CPPFLAGS = -D_GNU_SOURCE -I$(srcdir) -I$(srcdir)/../include \\\n \t\t\t-I$(srcdir)/../libctf\n+\n+if HAVE_SFRAME_AS\n+ libsframebt_la_SOURCES = sframe-backtrace.c sframe-backtrace-err.c\n+ libsframebt_la_CPPFLAGS = -I$(srcdir) -I$(srcdir)/../include\n+ libsframebt_la_CFLAGS = -Wa,--gsframe\n+if INSTALL_LIBBFD\n+ lib_LTLIBRARIES += libsframebt.la\n+ include_HEADERS += $(INCDIR)/sframe-backtrace-api.h\n+else\n+ noinst_LTLIBRARIES += libsframebt.la\n+endif\n+endif\ndiff --git a/libsframe/Makefile.in b/libsframe/Makefile.in\nindex f4c2415be1c..63e3cba1805 100644\n--- a/libsframe/Makefile.in\n+++ b/libsframe/Makefile.in\n@@ -107,6 +107,9 @@ PRE_UNINSTALL = :\n POST_UNINSTALL = :\n build_triplet = @build@\n host_triplet = @host@\n+@HAVE_SFRAME_AS_TRUE@@INSTALL_LIBBFD_TRUE@am__append_1 = libsframebt.la\n+@HAVE_SFRAME_AS_TRUE@@INSTALL_LIBBFD_TRUE@am__append_2 = $(INCDIR)/sframe-backtrace-api.h\n+@HAVE_SFRAME_AS_TRUE@@INSTALL_LIBBFD_FALSE@am__append_3 = libsframebt.la\n subdir = .\n ACLOCAL_M4 = $(top_srcdir)/aclocal.m4\n am__aclocal_m4_deps = $(top_srcdir)/../bfd/acinclude.m4 \\\n@@ -116,6 +119,7 @@ am__aclocal_m4_deps = $(top_srcdir)/../bfd/acinclude.m4 \\\n \t$(top_srcdir)/../config/jobserver.m4 \\\n \t$(top_srcdir)/../config/lead-dot.m4 \\\n \t$(top_srcdir)/../config/override.m4 \\\n+\t$(top_srcdir)/../config/sframe.m4 \\\n \t$(top_srcdir)/../config/warnings.m4 \\\n \t$(top_srcdir)/../libtool.m4 $(top_srcdir)/../ltoptions.m4 \\\n \t$(top_srcdir)/../ltsugar.m4 $(top_srcdir)/../ltversion.m4 \\\n@@ -170,6 +174,20 @@ am__v_lt_0 = --silent\n am__v_lt_1 = \n @INSTALL_LIBBFD_FALSE@am_libsframe_la_rpath =\n @INSTALL_LIBBFD_TRUE@am_libsframe_la_rpath = -rpath $(libdir)\n+libsframebt_la_LIBADD =\n+am__libsframebt_la_SOURCES_DIST = sframe-backtrace.c \\\n+\tsframe-backtrace-err.c\n+@HAVE_SFRAME_AS_TRUE@am_libsframebt_la_OBJECTS = \\\n+@HAVE_SFRAME_AS_TRUE@\tlibsframebt_la-sframe-backtrace.lo \\\n+@HAVE_SFRAME_AS_TRUE@\tlibsframebt_la-sframe-backtrace-err.lo\n+libsframebt_la_OBJECTS = $(am_libsframebt_la_OBJECTS)\n+libsframebt_la_LINK = $(LIBTOOL) $(AM_V_lt) --tag=CC \\\n+\t$(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=link $(CCLD) \\\n+\t$(libsframebt_la_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) $(LDFLAGS) -o \\\n+\t$@\n+@HAVE_SFRAME_AS_TRUE@@INSTALL_LIBBFD_FALSE@am_libsframebt_la_rpath =\n+@HAVE_SFRAME_AS_TRUE@@INSTALL_LIBBFD_TRUE@am_libsframebt_la_rpath = \\\n+@HAVE_SFRAME_AS_TRUE@@INSTALL_LIBBFD_TRUE@\t-rpath $(libdir)\n AM_V_P = $(am__v_P_@AM_V@)\n am__v_P_ = $(am__v_P_@AM_DEFAULT_V@)\n am__v_P_0 = false\n@@ -204,8 +222,9 @@ AM_V_CCLD = $(am__v_CCLD_@AM_V@)\n am__v_CCLD_ = $(am__v_CCLD_@AM_DEFAULT_V@)\n am__v_CCLD_0 = @echo \" CCLD \" $@;\n am__v_CCLD_1 = \n-SOURCES = $(libsframe_la_SOURCES)\n-DIST_SOURCES = $(libsframe_la_SOURCES)\n+SOURCES = $(libsframe_la_SOURCES) $(libsframebt_la_SOURCES)\n+DIST_SOURCES = $(libsframe_la_SOURCES) \\\n+\t$(am__libsframebt_la_SOURCES_DIST)\n RECURSIVE_TARGETS = all-recursive check-recursive cscopelist-recursive \\\n \tctags-recursive dvi-recursive html-recursive info-recursive \\\n \tinstall-data-recursive install-dvi-recursive \\\n@@ -219,7 +238,8 @@ am__can_run_installinfo = \\\n n|no|NO) false;; \\\n *) (install-info --version) >/dev/null 2>&1;; \\\n esac\n-am__include_HEADERS_DIST = $(INCDIR)/sframe.h $(INCDIR)/sframe-api.h\n+am__include_HEADERS_DIST = $(INCDIR)/sframe-backtrace-api.h \\\n+\t$(INCDIR)/sframe.h $(INCDIR)/sframe-api.h\n HEADERS = $(include_HEADERS)\n RECURSIVE_CLEAN_TARGETS = mostlyclean-recursive clean-recursive\t\\\n distclean-recursive maintainer-clean-recursive\n@@ -428,14 +448,19 @@ INCDIR = $(srcdir)/../include\n # include libctf for swap.h\n AM_CPPFLAGS = -D_GNU_SOURCE -I$(srcdir) -I$(srcdir)/../include -I$(srcdir)/../libctf\n AM_CFLAGS = -std=gnu99 @ac_libsframe_warn_cflags@ @warn@ @c_warn@ @WARN_PEDANTIC@ @WERROR@\n-@INSTALL_LIBBFD_TRUE@lib_LTLIBRARIES = libsframe.la\n-@INSTALL_LIBBFD_FALSE@include_HEADERS = \n-@INSTALL_LIBBFD_TRUE@include_HEADERS = $(INCDIR)/sframe.h $(INCDIR)/sframe-api.h\n-@INSTALL_LIBBFD_FALSE@noinst_LTLIBRARIES = libsframe.la\n+@INSTALL_LIBBFD_TRUE@lib_LTLIBRARIES = libsframe.la $(am__append_1)\n+@INSTALL_LIBBFD_FALSE@include_HEADERS = $(am__append_2)\n+@INSTALL_LIBBFD_TRUE@include_HEADERS = $(INCDIR)/sframe.h \\\n+@INSTALL_LIBBFD_TRUE@\t$(INCDIR)/sframe-api.h $(am__append_2)\n+@INSTALL_LIBBFD_FALSE@noinst_LTLIBRARIES = libsframe.la \\\n+@INSTALL_LIBBFD_FALSE@\t$(am__append_3)\n libsframe_la_SOURCES = sframe.c sframe-dump.c sframe-error.c\n libsframe_la_CPPFLAGS = -D_GNU_SOURCE -I$(srcdir) -I$(srcdir)/../include \\\n \t\t\t-I$(srcdir)/../libctf\n \n+@HAVE_SFRAME_AS_TRUE@libsframebt_la_SOURCES = sframe-backtrace.c sframe-backtrace-err.c\n+@HAVE_SFRAME_AS_TRUE@libsframebt_la_CPPFLAGS = -I$(srcdir) -I$(srcdir)/../include\n+@HAVE_SFRAME_AS_TRUE@libsframebt_la_CFLAGS = -Wa,--gsframe\n all: config.h\n \t$(MAKE) $(AM_MAKEFLAGS) all-recursive\n \n@@ -539,6 +564,9 @@ clean-noinstLTLIBRARIES:\n libsframe.la: $(libsframe_la_OBJECTS) $(libsframe_la_DEPENDENCIES) $(EXTRA_libsframe_la_DEPENDENCIES) \n \t$(AM_V_CCLD)$(LINK) $(am_libsframe_la_rpath) $(libsframe_la_OBJECTS) $(libsframe_la_LIBADD) $(LIBS)\n \n+libsframebt.la: $(libsframebt_la_OBJECTS) $(libsframebt_la_DEPENDENCIES) $(EXTRA_libsframebt_la_DEPENDENCIES) \n+\t$(AM_V_CCLD)$(libsframebt_la_LINK) $(am_libsframebt_la_rpath) $(libsframebt_la_OBJECTS) $(libsframebt_la_LIBADD) $(LIBS)\n+\n mostlyclean-compile:\n \t-rm -f *.$(OBJEXT)\n \n@@ -548,6 +576,8 @@ distclean-compile:\n @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libsframe_la-sframe-dump.Plo@am__quote@\n @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libsframe_la-sframe-error.Plo@am__quote@\n @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libsframe_la-sframe.Plo@am__quote@\n+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libsframebt_la-sframe-backtrace-err.Plo@am__quote@\n+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libsframebt_la-sframe-backtrace.Plo@am__quote@\n \n .c.o:\n @am__fastdepCC_TRUE@\t$(AM_V_CC)$(COMPILE) -MT $@ -MD -MP -MF $(DEPDIR)/$*.Tpo -c -o $@ $<\n@@ -591,6 +621,20 @@ libsframe_la-sframe-error.lo: sframe-error.c\n @AMDEP_TRUE@@am__fastdepCC_FALSE@\tDEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@\n @am__fastdepCC_FALSE@\t$(AM_V_CC@am__nodep@)$(LIBTOOL) $(AM_V_lt) --tag=CC $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libsframe_la_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -c -o libsframe_la-sframe-error.lo `test -f 'sframe-error.c' || echo '$(srcdir)/'`sframe-error.c\n \n+libsframebt_la-sframe-backtrace.lo: sframe-backtrace.c\n+@am__fastdepCC_TRUE@\t$(AM_V_CC)$(LIBTOOL) $(AM_V_lt) --tag=CC $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libsframebt_la_CPPFLAGS) $(CPPFLAGS) $(libsframebt_la_CFLAGS) $(CFLAGS) -MT libsframebt_la-sframe-backtrace.lo -MD -MP -MF $(DEPDIR)/libsframebt_la-sframe-backtrace.Tpo -c -o libsframebt_la-sframe-backtrace.lo `test -f 'sframe-backtrace.c' || echo '$(srcdir)/'`sframe-backtrace.c\n+@am__fastdepCC_TRUE@\t$(AM_V_at)$(am__mv) $(DEPDIR)/libsframebt_la-sframe-backtrace.Tpo $(DEPDIR)/libsframebt_la-sframe-backtrace.Plo\n+@AMDEP_TRUE@@am__fastdepCC_FALSE@\t$(AM_V_CC)source='sframe-backtrace.c' object='libsframebt_la-sframe-backtrace.lo' libtool=yes @AMDEPBACKSLASH@\n+@AMDEP_TRUE@@am__fastdepCC_FALSE@\tDEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@\n+@am__fastdepCC_FALSE@\t$(AM_V_CC@am__nodep@)$(LIBTOOL) $(AM_V_lt) --tag=CC $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libsframebt_la_CPPFLAGS) $(CPPFLAGS) $(libsframebt_la_CFLAGS) $(CFLAGS) -c -o libsframebt_la-sframe-backtrace.lo `test -f 'sframe-backtrace.c' || echo '$(srcdir)/'`sframe-backtrace.c\n+\n+libsframebt_la-sframe-backtrace-err.lo: sframe-backtrace-err.c\n+@am__fastdepCC_TRUE@\t$(AM_V_CC)$(LIBTOOL) $(AM_V_lt) --tag=CC $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libsframebt_la_CPPFLAGS) $(CPPFLAGS) $(libsframebt_la_CFLAGS) $(CFLAGS) -MT libsframebt_la-sframe-backtrace-err.lo -MD -MP -MF $(DEPDIR)/libsframebt_la-sframe-backtrace-err.Tpo -c -o libsframebt_la-sframe-backtrace-err.lo `test -f 'sframe-backtrace-err.c' || echo '$(srcdir)/'`sframe-backtrace-err.c\n+@am__fastdepCC_TRUE@\t$(AM_V_at)$(am__mv) $(DEPDIR)/libsframebt_la-sframe-backtrace-err.Tpo $(DEPDIR)/libsframebt_la-sframe-backtrace-err.Plo\n+@AMDEP_TRUE@@am__fastdepCC_FALSE@\t$(AM_V_CC)source='sframe-backtrace-err.c' object='libsframebt_la-sframe-backtrace-err.lo' libtool=yes @AMDEPBACKSLASH@\n+@AMDEP_TRUE@@am__fastdepCC_FALSE@\tDEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@\n+@am__fastdepCC_FALSE@\t$(AM_V_CC@am__nodep@)$(LIBTOOL) $(AM_V_lt) --tag=CC $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libsframebt_la_CPPFLAGS) $(CPPFLAGS) $(libsframebt_la_CFLAGS) $(CFLAGS) -c -o libsframebt_la-sframe-backtrace-err.lo `test -f 'sframe-backtrace-err.c' || echo '$(srcdir)/'`sframe-backtrace-err.c\n+\n mostlyclean-libtool:\n \t-rm -f *.lo\n \ndiff --git a/libsframe/aclocal.m4 b/libsframe/aclocal.m4\nindex b0cdd6b184d..1bceeeab5a3 100644\n--- a/libsframe/aclocal.m4\n+++ b/libsframe/aclocal.m4\n@@ -1234,6 +1234,7 @@ m4_include([../config/depstand.m4])\n m4_include([../config/jobserver.m4])\n m4_include([../config/lead-dot.m4])\n m4_include([../config/override.m4])\n+m4_include([../config/sframe.m4])\n m4_include([../config/warnings.m4])\n m4_include([../libtool.m4])\n m4_include([../ltoptions.m4])\ndiff --git a/libsframe/configure.ac b/libsframe/configure.ac\nindex 0312c988f1a..359f4dc9992 100644\n--- a/libsframe/configure.ac\n+++ b/libsframe/configure.ac\n@@ -67,6 +67,13 @@ AM_CONDITIONAL([HAVE_COMPAT_DEJAGNU], [test \"x$ac_cv_dejagnu_compat\" = \"xyes\"])\n COMPAT_DEJAGNU=$ac_cv_dejagnu_compat\n AC_SUBST(COMPAT_DEJAGNU)\n \n+dnl The libsframebt library needs to be built with SFrame info.\n+dnl If the build assembler is not capable of generate SFrame then\n+dnl the library is not built.\n+\n+SFRAME_CHECK_AS_SFRAME\n+AM_CONDITIONAL([HAVE_SFRAME_AS], [test \"x$ac_cv_have_sframe\" = \"xyes\"])\n+\n AM_MAINTAINER_MODE\n AM_INSTALL_LIBBFD\n ACX_PROG_CC_WARNING_OPTS([-Wall], [ac_libsframe_warn_cflags])\ndiff --git a/libsframe/sframe-backtrace-err.c b/libsframe/sframe-backtrace-err.c\nnew file mode 100644\nindex 00000000000..70bd55ccf35\n--- /dev/null\n+++ b/libsframe/sframe-backtrace-err.c\n@@ -0,0 +1,46 @@\n+/* sframe-backtrace-err.c - SFrame Backtrace Error table.\n+\n+ Copyright (C) 2022 Free Software Foundation, Inc.\n+\n+ This file is part of libsframebt.\n+\n+ This program is free software; you can redistribute it and/or modify\n+ it under the terms of the GNU General Public License as published by\n+ the Free Software Foundation; either version 3 of the License, or\n+ (at your option) any later version.\n+\n+ This program is distributed in the hope that it will be useful,\n+ but WITHOUT ANY WARRANTY; without even the implied warranty of\n+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n+ GNU General Public License for more details.\n+\n+ You should have received a copy of the GNU General Public License\n+ along with this program. If not, see . */\n+\n+#include \"config.h\"\n+#include \"sframe-backtrace-api.h\"\n+\n+/* SFrame backtrace error messages. */\n+static const char *const sframe_bt_errlist[] =\n+{\n+ \"\",\n+ \"File does not contain SFrame data\",\n+ \"Iterating shared object reading error\",\n+ \"Failed to malloc memory space\",\n+ \"Failed to realloc memory space\",\n+ \"Failed to open file\",\n+ \"Failed on resolve canonical file name\",\n+ \"Failed to reposition file offset\",\n+ \"Failed to read from a file descriptor\",\n+ \"Failed to get the user context\",\n+ \"Failed to set up decode data\",\n+ \"Illegal CFA offset\"\n+};\n+\n+/* Return the error message associated with the error code. */\n+\n+const char *\n+sframe_bt_errmsg (enum sframe_bt_errcode ecode)\n+{\n+ return sframe_bt_errlist[ecode];\n+}\ndiff --git a/libsframe/sframe-backtrace.c b/libsframe/sframe-backtrace.c\nnew file mode 100644\nindex 00000000000..9dc95244f72\n--- /dev/null\n+++ b/libsframe/sframe-backtrace.c\n@@ -0,0 +1,620 @@\n+/* sframe-backtrace.c - The SFrame backtracer.\n+\n+ Copyright (C) 2022 Free Software Foundation, Inc.\n+\n+ This file is part of libsframebt.\n+\n+ This program is free software; you can redistribute it and/or modify\n+ it under the terms of the GNU General Public License as published by\n+ the Free Software Foundation; either version 3 of the License, or\n+ (at your option) any later version.\n+\n+ This program is distributed in the hope that it will be useful,\n+ but WITHOUT ANY WARRANTY; without even the implied warranty of\n+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n+ GNU General Public License for more details.\n+\n+ You should have received a copy of the GNU General Public License\n+ along with this program. If not, see . */\n+\n+#ifndef _GNU_SOURCE\n+#define _GNU_SOURCE\n+#endif\n+\n+#include \"config.h\"\n+#include \n+#include \n+#include \n+#include \n+#include \n+#include \n+#include \n+#include \n+#include \n+#include \n+#include \n+#include \"ansidecl.h\"\n+#include \"sframe-api.h\"\n+#include \"sframe-backtrace-api.h\"\n+\n+#ifndef PT_SFRAME\n+#define PT_SFRAME 0x6474e554\t\t/* FIXME. */\n+#endif\n+\n+#define _sf_printflike_(string_index,first_to_check) \\\n+ __attribute__ ((__format__ (__printf__, (string_index), (first_to_check))))\n+\n+static int _sframe_unwind_debug;\t/* Control for printing out debug info. */\n+static int no_of_entries = 32;\n+\n+/* SFrame decode data for the main module or a DSO. */\n+struct sframe_decode_data\n+{\n+ char *sfdd_data;\t\t\t/* SFrame decode data. */\n+ int sfdd_data_size;\t\t\t/* SFrame decode data size. */\n+ uint64_t sfdd_text_vma;\t\t/* Text segment's virtual address. */\n+ int sfdd_text_size;\t\t\t/* Text segment's size. */\n+ uint64_t sfdd_sframe_vma;\t\t/* SFrame segment's virtual address. */\n+ sframe_decoder_ctx *sfdd_sframe_ctx;\t/* SFrame decoder context. */\n+};\n+\n+/* List that holds SFrame info for the shared libraries. */\n+struct dso_cfi_list\n+{\n+ int alloced;\t\t\t\t/* Entries allocated. */\n+ int used;\t\t\t\t/* Entries used. */\n+ struct sframe_decode_data *entry;\t/* DSO's decode data. */\n+};\n+\n+/* Data that's passed through sframe_callback. */\n+struct sframe_unwind_info\n+{\n+ int sui_fd;\t\t\t\t/* File descriptor. */\n+ struct sframe_decode_data sui_ctx;\t/* The decode data. */\n+ struct dso_cfi_list sui_dsos;\t\t/* The DSO list. */\n+};\n+\n+static void\n+sframe_unwind_init_debug (void)\n+{\n+ static int inited;\n+\n+ if (!inited)\n+ {\n+ _sframe_unwind_debug = getenv (\"SFRAME_UNWIND_DEBUG\") != NULL;\n+ inited = 1;\n+ }\n+}\n+\n+_sf_printflike_ (1, 2)\n+static void\n+debug_printf (const char *format, ...)\n+{\n+ if (_sframe_unwind_debug)\n+ {\n+ va_list args;\n+\n+ va_start (args, format);\n+ __builtin_vprintf (format, args);\n+ va_end (args);\n+ }\n+}\n+\n+/* sframe_bt_errno - Check if there is error code in ERRP. */\n+\n+static int\n+sframe_bt_errno (int *errp)\n+{\n+ if (errp == NULL)\n+ return 0;\n+\n+ return (*errp != SFRAME_BT_OK);\n+}\n+\n+/* sframe_bt_set_errno - Store the specified error code ERROR into ERRP if\n+ it is non-NULL. */\n+\n+static void\n+sframe_bt_set_errno (int *errp, int error)\n+{\n+ if (errp != NULL)\n+ *errp = error;\n+}\n+\n+/* sframe_add_dso - Add .sframe info in D_DATA, which is associated with\n+ a dynamic shared object, to D_LIST. */\n+\n+static void\n+sframe_add_dso (struct dso_cfi_list *d_list,\n+\t\tstruct sframe_decode_data d_data,\n+\t\tint *errp)\n+{\n+ if (d_list->alloced == 0)\n+ {\n+ d_list->entry = malloc (no_of_entries * sizeof (struct sframe_decode_data));\n+ if (d_list->entry == NULL)\n+\t{\n+\t sframe_bt_set_errno (errp, SFRAME_BT_ERR_MALLOC);\n+\t return;\n+\t}\n+ memset (d_list->entry, 0,\n+\t no_of_entries * sizeof (struct sframe_decode_data));\n+ d_list->alloced = no_of_entries;\n+ }\n+ else if (d_list->used == d_list->alloced)\n+ {\n+ d_list->entry = realloc (d_list->entry,\n+\t\t\t ((d_list->alloced + no_of_entries)\n+\t\t\t\t* sizeof (struct sframe_decode_data)));\n+ if (d_list->entry == NULL)\n+\t{\n+\t sframe_bt_set_errno (errp, SFRAME_BT_ERR_REALLOC);\n+\t return;\n+\t}\n+\n+ memset (&d_list->entry[d_list->alloced], 0,\n+\t no_of_entries * sizeof (struct sframe_decode_data));\n+ d_list->alloced += no_of_entries;\n+ }\n+\n+ sframe_bt_set_errno (errp, SFRAME_BT_OK);\n+ d_list->entry[d_list->used++] = d_data;\n+}\n+\n+/* sframe_free_cfi - Free up space allocated for .sframe info for CF. */\n+\n+static void\n+sframe_free_cfi (struct sframe_unwind_info *sf)\n+{\n+ struct dso_cfi_list *d_list;\n+ int i;\n+\n+ if (sf == NULL)\n+ return;\n+\n+ free (sf->sui_ctx.sfdd_data);\n+ sframe_decoder_free (&sf->sui_ctx.sfdd_sframe_ctx);\n+ close (sf->sui_fd);\n+\n+ d_list = &sf-> sui_dsos;\n+ if (d_list == NULL)\n+ return;\n+\n+ for (i = 0; i < d_list->used; ++i)\n+ {\n+ free (d_list->entry[i].sfdd_data);\n+ sframe_decoder_free (&d_list->entry[i].sfdd_sframe_ctx);\n+ }\n+\n+ free (d_list->entry);\n+}\n+\n+/* sframe_find_context - Find the decode data that contains ADDR from CF.\n+ Return the pointer to the decode data or NULL. */\n+\n+static struct sframe_decode_data *\n+sframe_find_context (struct sframe_unwind_info *sf, uint64_t addr)\n+{\n+ struct dso_cfi_list *d_list;\n+ struct sframe_decode_data sdec_data;\n+ int i;\n+\n+ if (sf == NULL)\n+ return NULL;\n+\n+ if (sf->sui_ctx.sfdd_text_vma < addr\n+ && sf->sui_ctx.sfdd_text_vma + sf->sui_ctx.sfdd_text_size > addr)\n+ return &sf->sui_ctx;\n+\n+ d_list = &sf->sui_dsos;\n+ for (i = 0; i < sf->sui_dsos.used; ++i)\n+ {\n+ sdec_data = d_list->entry[i];\n+ if ((sdec_data.sfdd_text_vma <= addr)\n+\t && (sdec_data.sfdd_text_vma + sdec_data.sfdd_text_size >= addr))\n+\treturn &d_list->entry[i];\n+ }\n+\n+ return NULL;\n+}\n+\n+/* sframe_valid_addr - Check if ADDR is valid in CF. The address is considered\n+ invalid, with regards to SFrame, if it's not in any address range of the\n+ main module or any of its DSO's. Return 1 if valid, 0 otherwise. */\n+\n+static int\n+sframe_valid_addr (struct sframe_unwind_info *sf, uint64_t addr)\n+{\n+ struct sframe_decode_data *cdp;\n+\n+ if (sf == NULL)\n+ return 0;\n+\n+ cdp = sframe_find_context (sf, addr);\n+ return cdp ? 1 : 0;\n+}\n+\n+/* sframe_load_ctx - Call decoder to create and set up the SFrame info for\n+ either the main module or one of the DSOs from CF, based on the input\n+ RADDR argument. Return the newly created decode context or NULL. */\n+\n+static sframe_decoder_ctx *\n+sframe_load_ctx (struct sframe_unwind_info *sf, uint64_t raddr)\n+{\n+ sframe_decoder_ctx *nctx;\n+ struct sframe_decode_data *cdp;\n+\n+ if (sf == NULL)\n+ return NULL;\n+\n+ cdp = sframe_find_context (sf, raddr);\n+ if (cdp == NULL)\n+ return NULL;\n+\n+ if (cdp->sfdd_sframe_ctx == NULL)\n+ {\n+ int err;\n+ nctx = sframe_decode (cdp->sfdd_data, cdp->sfdd_data_size, &err);\n+ if (nctx == NULL)\n+\treturn NULL;\n+ cdp->sfdd_sframe_ctx = nctx;\n+ return nctx;\n+ }\n+\n+ return NULL;\n+}\n+\n+/* sframe_update_ctx - Check if need to do a decode context switch, based on\n+ the input RADDR argument, from CF. A new decode context will be created\n+ and set up if it isn't already done so. Return the new decode context in\n+ CTX and vma in CFI_VMA. */\n+\n+static void\n+sframe_update_ctx (struct sframe_unwind_info *sf, uint64_t raddr,\n+\t\t sframe_decoder_ctx **ctx, uint64_t *cfi_vma)\n+{\n+ sframe_decoder_ctx *nctx;\n+ struct sframe_decode_data *cdp;\n+\n+ cdp = sframe_find_context (sf, raddr);\n+ if (cdp != NULL)\n+ {\n+ if (cdp->sfdd_sframe_ctx == NULL)\n+\t{\n+\t int err;\n+\t nctx = sframe_decode (cdp->sfdd_data, cdp->sfdd_data_size, &err);\n+\t if (nctx == NULL)\n+\t {\n+\t *ctx = NULL;\n+\t return;\n+\t }\n+\t cdp->sfdd_sframe_ctx = nctx;\n+\t}\n+\t*ctx = cdp->sfdd_sframe_ctx;\n+\t*cfi_vma = cdp->sfdd_sframe_vma;\n+ }\n+}\n+\n+/* get_contents - Return contents at ADDR from file descriptor FD. */\n+\n+static uint64_t\n+get_contents (int fd, uint64_t addr, int *errp)\n+{\n+ uint64_t data;\n+ size_t sz;\n+\n+ sframe_bt_set_errno (errp, SFRAME_BT_OK);\n+ if (lseek (fd, addr, SEEK_SET) == -1)\n+ {\n+ sframe_bt_set_errno (errp, SFRAME_BT_ERR_LSEEK);\n+ return 0;\n+ }\n+ sz = read (fd, &data, sizeof (uint64_t));\n+ if (sz != sizeof (uint64_t))\n+ {\n+ sframe_bt_set_errno (errp, SFRAME_BT_ERR_READ);\n+ return 0;\n+ }\n+\n+ return data;\n+}\n+\n+/* sframe_fd_open - Open /proc image associated with the process id and return\n+ the file descriptor. */\n+\n+static int\n+sframe_fd_open (int *errp)\n+{\n+ char filename[PATH_MAX];\n+ pid_t pid;\n+ int fd;\n+\n+ pid = getpid ();\n+ snprintf (filename, sizeof filename, \"/proc/%d/task/%d/mem\", pid, pid);\n+ if ((fd = open (filename, O_RDONLY)) == -1)\n+ {\n+ sframe_bt_set_errno (errp, SFRAME_BT_ERR_OPEN);\n+ return -1;\n+ }\n+\n+ return fd;\n+}\n+\n+/* sframe_callback - The callback from dl_iterate_phdr with header info\n+ in INFO.\n+ Return SFrame info for either the main module or a DSO in DATA. */\n+\n+static int\n+sframe_callback (struct dl_phdr_info *info,\n+\t\t size_t size ATTRIBUTE_UNUSED,\n+\t\t void *data)\n+{\n+ struct sframe_unwind_info *sf = (struct sframe_unwind_info *) data;\n+ int p_type, i, fd, sframe_err;\n+ ssize_t len;\n+ uint64_t text_vma = 0;\n+ int text_size = 0;\n+\n+ if (data == NULL || info == NULL)\n+ return 1;\n+\n+ debug_printf (\"-- name: %s %14p\\n\", info->dlpi_name, (void *)info->dlpi_addr);\n+\n+ for (i = 0; i < info->dlpi_phnum; i++)\n+ {\n+ debug_printf(\" %2d: [%14p; memsz:%7lx] flags: 0x%x; \\n\", i,\n+\t\t (void *) info->dlpi_phdr[i].p_vaddr,\n+\t\t info->dlpi_phdr[i].p_memsz,\n+\t\t info->dlpi_phdr[i].p_flags);\n+\n+ p_type = info->dlpi_phdr[i].p_type;\n+ if (p_type == PT_LOAD && info->dlpi_phdr[i].p_flags & PF_X)\n+\t{\n+\t text_vma = info->dlpi_addr + info->dlpi_phdr[i].p_vaddr;\n+\t text_size = info->dlpi_phdr[i].p_memsz;\n+\t continue;\n+\t}\n+ if (p_type != PT_SFRAME)\n+\tcontinue;\n+\n+ if (info->dlpi_name[0] == '\\0')\t\t/* the main module. */\n+\t{\n+\t fd = sframe_fd_open (&sframe_err);\n+\t if (fd == -1)\n+\t return 1;\n+\t if (lseek (fd, info->dlpi_addr + info->dlpi_phdr[i].p_vaddr,\n+\t\t SEEK_SET) == -1)\n+\t {\n+\t sframe_bt_set_errno (&sframe_err, SFRAME_BT_ERR_LSEEK);\n+\t return 1;\n+\t }\n+\n+\t sf->sui_ctx.sfdd_data = (char *) malloc (info->dlpi_phdr[i].p_memsz);\n+\t if (sf->sui_ctx.sfdd_data == NULL)\n+\t {\n+\t sframe_bt_set_errno (&sframe_err, SFRAME_BT_ERR_MALLOC);\n+\t return 1;\n+\t }\n+\n+\t len = read (fd, sf->sui_ctx.sfdd_data, info->dlpi_phdr[i].p_memsz);\n+\t if (len == -1 || len != (ssize_t) info->dlpi_phdr[i].p_memsz)\n+\t {\n+\t sframe_bt_set_errno (&sframe_err, SFRAME_BT_ERR_READ);\n+\t return 1;\n+\t }\n+\n+\t assert (text_vma);\n+\t sf->sui_ctx.sfdd_data_size = len;\n+\t sf->sui_ctx.sfdd_sframe_vma = info->dlpi_addr + info->dlpi_phdr[i].p_vaddr;\n+\t sf->sui_fd = fd;\n+\t sf->sui_ctx.sfdd_text_vma = text_vma;\n+\t sf->sui_ctx.sfdd_text_size = text_size;\n+\t text_vma = 0;\n+\t return 0;\n+\t}\n+ else\n+\t{\t\t\t\t\t/* a dynamic shared object. */\n+\t struct sframe_decode_data dt;\n+\t memset (&dt, 0, sizeof (struct sframe_decode_data));\n+\t assert (sf->sui_fd);\n+\t if (lseek (sf->sui_fd, info->dlpi_addr + info->dlpi_phdr[i].p_vaddr,\n+\t\t SEEK_SET) == -1)\n+\t {\n+\t sframe_bt_set_errno (&sframe_err, SFRAME_BT_ERR_LSEEK);\n+\t return 1;\n+\t }\n+\n+\t dt.sfdd_data = (char *) malloc (info->dlpi_phdr[i].p_memsz);\n+\t if (dt.sfdd_data == NULL)\n+\t {\n+\t sframe_bt_set_errno (&sframe_err, SFRAME_BT_ERR_MALLOC);\n+\t return 1;\n+\t }\n+\n+\t len = read (sf->sui_fd, dt.sfdd_data, info->dlpi_phdr[i].p_memsz);\n+\t if (len == -1 || len != (ssize_t) info->dlpi_phdr[i].p_memsz)\n+\t {\n+\t sframe_bt_set_errno (&sframe_err, SFRAME_BT_ERR_READ);\n+\t return 1;\n+\t }\n+\n+\t assert (text_vma);\n+\t dt.sfdd_data_size = len;\n+\t dt.sfdd_sframe_vma = info->dlpi_addr + info->dlpi_phdr[i].p_vaddr;\n+\t dt.sfdd_text_vma = text_vma;\n+\t dt.sfdd_text_size = text_size;\n+\t text_vma = 0;\n+\t sframe_add_dso (&sf->sui_dsos, dt, &sframe_err);\n+\t if (sframe_err != SFRAME_BT_OK)\n+\t return 1;\n+\t return 0;\n+\t}\n+ }\n+\n+ return 0;\n+}\n+\n+/* sframe_unwind - Unwind the stack backtrace for CF. If successful,\n+ store the return addresses in RA_LST. The RA_SIZE argument specifies\n+ the maximum number of return addresses that can be stored in RA_LST\n+ and contains the number of the addresses collected. */\n+\n+static void\n+sframe_unwind (struct sframe_unwind_info *sf, void **ra_lst,\n+\t int *ra_size, int *errp)\n+{\n+ uint64_t cfa, return_addr, ra_stack_loc, rfp_stack_loc;\n+ sframe_decoder_ctx *ctx;\n+ int cfa_offset, rfp_offset, errnum, i, count;\n+ sframe_frame_row_entry fred, *frep = &fred;\n+ uint64_t pc, rfp, rsp, cfi_vma;\n+ ucontext_t context, *cp = &context;\n+\n+ if (sf == NULL || ra_lst == NULL || ra_size == NULL)\n+ {\n+ sframe_bt_set_errno (errp, SFRAME_BT_ERR_ARG);\n+ return;\n+ }\n+\n+ /* Get the user context for its registers. */\n+ if (getcontext (cp) != 0)\n+ {\n+ sframe_bt_set_errno (errp, SFRAME_BT_ERR_GETCONTEXT);\n+ return;\n+ }\n+ sframe_bt_set_errno (errp, SFRAME_BT_OK);\n+\n+#ifdef __x86_64__\n+ pc = cp->uc_mcontext.gregs[REG_RIP];\n+ rsp = cp->uc_mcontext.gregs[REG_RSP];\n+ rfp = cp->uc_mcontext.gregs[REG_RBP];\n+#else\n+#ifdef __aarch64__\n+#define UNWIND_AARCH64_X29\t\t29\t/* 64-bit frame pointer. */\n+#define UNWIND_AARCH64_X30\t\t30\t/* 64-bit link pointer. */\n+ pc = cp->uc_mcontext.pc;\n+ rsp = cp->uc_mcontext.sp;\n+ rfp = cp->uc_mcontext.regs[UNWIND_AARCH64_X29];\n+ uint64_t ra = cp->uc_mcontext.regs[UNWIND_AARCH64_X30];\n+#endif\n+#endif\n+\n+ /* Load and set up the decoder. */\n+ ctx = sframe_load_ctx (sf, pc);\n+ if (ctx == NULL)\n+ {\n+ sframe_bt_set_errno (errp, SFRAME_BT_ERR_DECODE);\n+ return;\n+ }\n+ cfi_vma = sf->sui_ctx.sfdd_sframe_vma;\n+ count = *ra_size;\n+\n+ for (i = 0; i < count; ++i)\n+ {\n+ pc -= cfi_vma;\n+ errnum = sframe_find_fre (ctx, pc, frep);\n+ if (errnum == 0)\n+\t{\n+\t cfa_offset = sframe_fre_get_cfa_offset (frep, &errnum);\n+\t if (errnum == ESFRAME_FREOFFSET_NOPRESENT)\n+\t {\n+\t sframe_bt_set_errno (errp, SFRAME_BT_ERR_CFA_OFFSET);\n+\t return;\n+\t }\n+\n+\t cfa = ((frep->fre_info & 0x1) == SFRAME_BASE_REG_SP\n+\t ? rsp : rfp) + cfa_offset;\n+\n+#ifdef __x86_64__\n+\t /* For x86, read the return address from cfa - 8. */\n+\t ra_stack_loc = cfa - 8;\n+\t return_addr = get_contents (sf->sui_fd, ra_stack_loc, errp);\n+\t if (sframe_bt_errno (errp))\n+\t return;\n+#else\n+#ifdef __aarch64__\n+\t int ra_offset = sframe_fre_get_ra_offset (frep, &errnum);\n+\t if (errnum == 0)\n+\t {\n+\t ra_stack_loc = cfa + ra_offset;\n+\t return_addr = get_contents (sf->sui_fd, ra_stack_loc, errp);\n+\t if (sframe_bt_errno (errp))\n+\t\treturn;\n+\t }\n+\t else\n+\t return_addr = ra;\n+#endif\n+#endif\n+\n+\t /* Validate and add return address to the list. */\n+\t if (sframe_valid_addr (sf, return_addr) == 0)\n+\t {\n+\t i -= 1;\n+\t goto find_fre_ra_err;\n+\t }\n+\t if (i != 0)\t\t/* exclude self. */\n+\t ra_lst[i-1] = (void *)return_addr;\n+\n+\t /* Set up for the next frame. */\n+\t rfp_offset = sframe_fre_get_fp_offset (frep, &errnum);\n+\t if (errnum == 0)\n+\t {\n+\t rfp_stack_loc = cfa + rfp_offset;\n+\t rfp = get_contents (sf->sui_fd, rfp_stack_loc, errp);\n+\t if (sframe_bt_errno (errp))\n+\t\treturn;\n+\t }\n+\t rsp = cfa;\n+\t pc = return_addr;\n+\n+\t /* Check if need to update the decoder context and vma. */\n+\t sframe_update_ctx (sf, return_addr, &ctx, &cfi_vma);\n+\t if (ctx == NULL)\n+\t {\n+\t sframe_bt_set_errno (errp, SFRAME_BT_ERR_DECODE);\n+\t return;\n+\t }\n+\t}\n+ else\n+\t{\n+\t i -= 1;\n+\t goto find_fre_ra_err;\n+\t}\n+ }\n+\n+find_fre_ra_err:\n+ *ra_size = i;\n+}\n+\n+/* sframe_backtrace - Main API that user program calls to get a backtrace.\n+ The BUFFER argument provides space for the list of the return addresses\n+ and the SIZE argument specifies the maximum number of addresses that\n+ can be stored in the buffer. Return the number of return addresses\n+ collected or -1 if there is any error. */\n+\n+int\n+sframe_backtrace (void **buffer, int size, int *errp)\n+{\n+ struct sframe_unwind_info sframeinfo;\n+\n+ sframe_unwind_init_debug ();\n+\n+ memset (&sframeinfo, 0, sizeof (struct sframe_unwind_info));\n+\n+ /* find and set up the .sframe sections. */\n+ (void) dl_iterate_phdr (sframe_callback, (void *)&sframeinfo);\n+ if (sframeinfo.sui_fd == 0)\n+ {\n+ sframe_bt_set_errno (errp, SFRAME_BT_ERR_NOTPRESENT);\n+ return -1;\n+ }\n+\n+ /* Do the stack unwinding. */\n+ sframe_unwind (&sframeinfo, buffer, &size, errp);\n+ if (sframe_bt_errno (errp))\n+ return -1;\n+\n+ sframe_free_cfi (&sframeinfo);\n+\n+ return size;\n+}\ndiff --git a/libsframe/testsuite/Makefile.in b/libsframe/testsuite/Makefile.in\nindex d8c14162cea..14d6ef64cd2 100644\n--- a/libsframe/testsuite/Makefile.in\n+++ b/libsframe/testsuite/Makefile.in\n@@ -96,6 +96,7 @@ am__aclocal_m4_deps = $(top_srcdir)/../bfd/acinclude.m4 \\\n \t$(top_srcdir)/../config/jobserver.m4 \\\n \t$(top_srcdir)/../config/lead-dot.m4 \\\n \t$(top_srcdir)/../config/override.m4 \\\n+\t$(top_srcdir)/../config/sframe.m4 \\\n \t$(top_srcdir)/../config/w 100 50853 100 50699 100 154 1338k 4162 --:--:-- --:--:-- --:--:-- 1342k arnings.m4 \\\n \t$(top_srcdir)/../libtool.m4 $(top_srcdir)/../ltoptions.m4 \\\n \t$(top_srcdir)/../ltsugar.m4 $(top_srcdir)/../ltversion.m4 \\\ndiff --git a/libsframe/testsuite/libsframe.decode/Makefile.in b/libsframe/testsuite/libsframe.decode/Makefile.in\nindex ee0757a793c..b8acacadf9d 100644\n--- a/libsframe/testsuite/libsframe.decode/Makefile.in\n+++ b/libsframe/testsuite/libsframe.decode/Makefile.in\n@@ -98,6 +98,7 @@ am__aclocal_m4_deps = $(top_srcdir)/../bfd/acinclude.m4 \\\n \t$(top_srcdir)/../config/jobserver.m4 \\\n \t$(top_srcdir)/../config/lead-dot.m4 \\\n \t$(top_srcdir)/../config/override.m4 \\\n+\t$(top_srcdir)/../config/sframe.m4 \\\n \t$(top_srcdir)/../config/warnings.m4 \\\n \t$(top_srcdir)/../libtool.m4 $(top_srcdir)/../ltoptions.m4 \\\n \t$(top_srcdir)/../ltsugar.m4 $(top_srcdir)/../ltversion.m4 \\\ndiff --git a/libsframe/testsuite/libsframe.encode/Makefile.in b/libsframe/testsuite/libsframe.encode/Makefile.in\nindex 26f92edb3c2..bbc76994785 100644\n--- a/libsframe/testsuite/libsframe.encode/Makefile.in\n+++ b/libsframe/testsuite/libsframe.encode/Makefile.in\n@@ -97,6 +97,7 @@ am__aclocal_m4_deps = $(top_srcdir)/../bfd/acinclude.m4 \\\n \t$(top_srcdir)/../config/jobserver.m4 \\\n \t$(top_srcdir)/../config/lead-dot.m4 \\\n \t$(top_srcdir)/../config/override.m4 \\\n+\t$(top_srcdir)/../config/sframe.m4 \\\n \t$(top_srcdir)/../config/warnings.m4 \\\n \t$(top_srcdir)/../libtool.m4 $(top_srcdir)/../ltoptions.m4 \\\n \t$(top_srcdir)/../ltsugar.m4 $(top_srcdir)/../ltversion.m4 \\\n","prefixes":["V2","08/15"]}+ exit 1 Build step 'Execute shell' marked build as failure Finished: FAILURE