Started by user snail Running as SYSTEM [EnvInject] - Loading node environment variables. Building remotely on docker-jenkins-agent in workspace /home/jenkins/agent/workspace/binutils-gdb [WS-CLEANUP] Deleting project workspace... [WS-CLEANUP] Deferred wipeout is used... [WS-CLEANUP] Done The recommended git tool is: NONE using credential 0adb5fc7-caa2-429d-97d2-c7fa2fa1d884 Cloning the remote Git repository Using shallow clone with depth 1 Avoid fetching tags Cloning repository git@github.com:wangliu-iscas/binutils-gdb.git/ > git init /home/jenkins/agent/workspace/binutils-gdb # timeout=10 Fetching upstream changes from git@github.com:wangliu-iscas/binutils-gdb.git/ > git --version # timeout=10 > git --version # 'git version 2.37.2' using GIT_SSH to set credentials patchwork github wangliu-iscas git ssh key Verifying host key using known hosts file, will automatically accept unseen keys > git fetch --no-tags --force --progress --depth=1 -- git@github.com:wangliu-iscas/binutils-gdb.git/ +refs/heads/*:refs/remotes/origin/* # timeout=10 > git config remote.origin.url git@github.com:wangliu-iscas/binutils-gdb.git/ # timeout=10 > git config --add remote.origin.fetch +refs/heads/*:refs/remotes/origin/* # timeout=10 Avoid second fetch > git rev-parse refs/remotes/origin/master^{commit} # timeout=10 Checking out Revision 07a33c2bc17fc86bbd0e8ad08f3649d852f4965f (refs/remotes/origin/master) > git config core.sparsecheckout # timeout=10 > git checkout -f 07a33c2bc17fc86bbd0e8ad08f3649d852f4965f # timeout=10 Commit message: "Automatic date update in version.in" > git rev-list --no-walk 07a33c2bc17fc86bbd0e8ad08f3649d852f4965f # timeout=10 [EnvInject] - Mask passwords that will be passed as build parameters. [EnvInject] - Executing scripts and injecting environment variables after the SCM step. [EnvInject] - Injecting as environment variables the properties content GITHUB_REPO=https://github.com/wangliu-iscas/ PATCHWORK_URL=https://patchwork.plctlab.org [EnvInject] - Variables injected successfully. [binutils-gdb] $ /usr/bin/env bash /tmp/jenkins2904010026236598035.sh + git config pw.server https://patchwork.plctlab.org/api/1.2/ + git config pw.project binutils-gdb + git config pw.token [*******] ++ date +%Y-%m + now_date=2022-10 + echo 2022-10 2022-10 ++ curl -s -H 'Authorization: Token [*******]' 'https://patchwork.plctlab.org/api/1.2/bundles/?project=binutils-gdb&per_page=999' + bundle_response='[{"id":6,"url":"https://patchwork.plctlab.org/api/1.2/bundles/6/","web_url":"https://patchwork.plctlab.org/bundle/snail/binutils-gdb_2022-10/","project":{"id":2,"url":"https://patchwork.plctlab.org/api/1.2/projects/2/","name":"binutils-gdb","link_name":"binutils-gdb","list_id":"binutils.sourceware.org","list_email":"binutils@sourceware.org","web_url":"https://sourceware.org/mailman/listinfo/binutils","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"name":"binutils-gdb_2022-10","owner":{"id":1,"url":"https://patchwork.plctlab.org/api/1.2/users/1/","username":"snail","first_name":"","last_name":"","email":"wangliu@iscas.ac.cn"},"patches":[{"id":1592,"url":"https://patchwork.plctlab.org/api/1.2/patches/1592/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/385d01fd-7e57-1f3f-1bae-30aa0c313d63@suse.com/","msgid":"<385d01fd-7e57-1f3f-1bae-30aa0c313d63@suse.com>","list_archive_url":null,"date":"2022-09-30T11:59:45","name":"[3/4] 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ones","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/8db04962aba9c780f133840a8934353a58f223fe.1664602716.git.research_trasio@irq.a4lg.com/mbox/"},{"id":1627,"url":"https://patchwork.plctlab.org/api/1.2/patches/1627/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221001062057.681440-1-maskray@google.com/","msgid":"<20221001062057.681440-1-maskray@google.com>","list_archive_url":null,"date":"2022-10-01T06:20:57","name":"readelf: support zstd compressed debug sections [PR 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arm","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/619f112539c0bdecd58e25664f1250a3479a37f5.1664707612.git.aburgess@redhat.com/mbox/"},{"id":1635,"url":"https://patchwork.plctlab.org/api/1.2/patches/1635/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221002185433.gl7dvytfh5wthifx@lug-owl.de/","msgid":"<20221002185433.gl7dvytfh5wthifx@lug-owl.de>","list_archive_url":null,"date":"2022-10-02T18:54:33","name":"diagnostics.h: GCC 13 got -Wself-move, breaks GDB build","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221002185433.gl7dvytfh5wthifx@lug-owl.de/mbox/"},{"id":1637,"url":"https://patchwork.plctlab.org/api/1.2/patches/1637/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003014313.28766-1-mark@harmstone.com/","msgid":"<20221003014313.28766-1-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-03T01:43:12","name":"[1/2] ld: Add --pdb option","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003014313.28766-1-mark@harmstone.com/mbox/"},{"id":1638,"url":"https://patchwork.plctlab.org/api/1.2/patches/1638/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003014313.28766-2-mark@harmstone.com/","msgid":"<20221003014313.28766-2-mark@harmstone.com>","list_archive_url":null,"date":"2022-10-03T01:43:13","name":"[2/2] ld: Add minimal pdb generation","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003014313.28766-2-mark@harmstone.com/mbox/"},{"id":1640,"url":"https://patchwork.plctlab.org/api/1.2/patches/1640/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/597ed978-d121-220c-b56b-2ffb94bd091c@suse.cz/","msgid":"<597ed978-d121-220c-b56b-2ffb94bd091c@suse.cz>","list_archive_url":null,"date":"2022-10-03T07:50:38","name":"[1/2] refactor usage of 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registers","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20221003101328.1790113-1-aburgess@redhat.com/mbox/"},{"id":1643,"url":"https://patchwork.plctlab.org/api/1.2/patches/1643/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/7ba14fc4472ce97d4f7a4433cad8a571e89f82f4.1664793840.git.research_trasio@irq.a4lg.com/","msgid":"<7ba14fc4472ce97d4f7a4433cad8a571e89f82f4.1664793840.git.research_trasio@irq.a4lg.com>","list_archive_url":null,"date":"2022-10-03T10:43:59","name":"[v3,1/6] RISC-V: Fix immediates to have \"immediate\" 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GCC","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/20220930140503.38233-1-chigot@adacore.com/mbox/"}],"public":true,"mbox":"https://patchwork.plctlab.org/bundle/snail/binutils-gdb_2022-09/mbox/"}]' + bundle_id=6 + git-pw bundle add 6 2656 +------------+--------------------------------------------------------------------------------------+ | Property | Value | |------------+--------------------------------------------------------------------------------------| | ID | 6 | | Name | binutils-gdb_2022-10 | | URL | https://patchwork.plctlab.org/bundle/snail/binutils-gdb_2022-10/ | | Owner | snail | | Project | binutils-gdb | | Public | True | | Patches | 1592 [3/4] RISC-V/gas: don't open-code insn_length() | | | 1594 [4/4] RISC-V/gas: allow generating up to 176-bit instructions with .insn | | | 1596 ld/testsuite: consistently add board_ldflags when linking with GCC | | | 1619 gold, dwp: support zstd compressed input debug sections [PR 29641] | | | 1620 gold: add --compress-debug-sections=zstd [PR 29641] | | | 1623 [RFC,1/1] RISC-V: Implement common register pair framework | | | 1625 [RFC,1/1] RISC-V: Implement extension variants | | | 1626 [1/1] RISC-V: Move supervisor instructions after all unprivileged ones | | | 1627 readelf: support zstd compressed debug sections [PR 29640] | | | 1631 [PATCHv2,2/2] opcodes/arm: add disassembler styling for arm | | | 1635 diagnostics.h: GCC 13 got -Wself-move, breaks GDB build | | | 1637 [1/2] ld: Add --pdb option | | | 1638 [2/2] ld: Add minimal pdb generation | | | 1640 [1/2] refactor usage of compressed_debug_section_type | | | 1641 [2/2] add --enable-default-compressed-debug-sections-algorithm configure option | | | 1642 opcodes/riscv: style csr names as registers | | | 1643 [v3,1/6] RISC-V: Fix immediates to have "immediate" style | | | 1644 [v3,2/6] RISC-V: Fix printf argument types corresponding %x | | | 1647 [v3,3/6] RISC-V: Optimize riscv_disassemble_data printf | | | 1646 [v3,4/6] RISC-V: Print comma and tabs as the "text" style | | | 1648 [v3,5/6] RISC-V: Fix T-Head immediate types on printing | | | 1649 [v3,6/6] RISC-V: Print XTheadMemPair literal as "immediate" | | | 1656 Commit: readelf: Do not load section data from offset 0 | | | 1659 [PATCHv2,1/2] opcodes/arm: use '@' consistently for the comment character | | | 1660 gas: NEWS: Mention the T-Head extensions that were recently added | | | 1671 Support objcopy changing compression to or from zstd | | | 1673 [1/2] RISC-V: Fix buffer overflow on print_insn_riscv | | | 1672 [2/2] gdb/riscv: Fix buffer overflow on riscv_insn::fetch_instruction | | | 1676 [v2,1/2] RISC-V: Fix buffer overflow on print_insn_riscv | | | 1677 [v2,2/2] gdb/riscv: Partial support for instructions up to 176-bits | | | 1678 [v3,1/2] RISC-V: Fix buffer overflow on print_insn_riscv | | | 1679 [v3,2/2] gdb/riscv: Partial support for instructions up to 176-bit | | | 1681 RISC-V: Zicbo{m,p,z} adjustments to riscv_multi_subset_supports_ext() | | | 1690 gprofng: fix build with --enable-pgo-build=lto | | | 1691 bfd: xtensa: fix __stop_SECTION literal drop, | | | 1702 [RFC] bfd: use bfd_vma for the 64-bit version of put[lb] and get[lb] | | | 1711 PR29647, objdump -S looping | | | 1712 [v3,1/7] x86: constify parse_insn()'s input | | | 1713 [v3,2/7] x86: introduce Pass2 insn attribute | | | 1714 [v3,3/7] x86: re-work insn/suffix recognition | | | 1715 [v3,4/7] x86-64: further re-work insn/suffix recognition to also cover MOVSL | | | 1716 [v3,5/7] ix86: don't recognize/derive Q suffix in the common case | | | 1718 [v3,6/7] x86-64: allow HLE store of accumulator to absolute 32-bit address | | | 1717 [v3,7/7] x86: move bad-use-of-TLS-reloc check | | | 1719 x86: drop "regmask" static variable | | | 1751 [v2,1/2] RISC-V: Fallback for instructions longer than 64b | | | 1752 [v2,2/2] RISC-V: Improve "bits undefined" diagnostics | | | 1776 [v3,1/2] RISC-V: Fallback for instructions longer than 64b | | | 1777 [v3,2/2] RISC-V: Improve "bits undefined" diagnostics | | | 1781 RISC-V: fix linker message when relaxation deletes bytes | | | 1801 PR29653, objcopy/strip: fuzzed small input file induces large output file | | | 1803 @CPP_FOR_BUILD@ problem since binutils-2.38 | | | 1827 [v2,1/1] RISC-V: Test DWARF register numbers for "fp" | | | 1828 [1/1] RISC-V: Move standard hints before all instructions | | | 1829 [RFC,1/1] RISC-V: Imply 'Zicsr' from privileged extensions with CSRs | | | 1830 [1/5] opcodes/riscv-dis.c: Tidying with comments/clarity | | | 1832 [2/5] opcodes/riscv-dis.c: Tidying with spacing | | | 1831 [3/5] opcodes/riscv-dis.c: Use bool type whenever possible | | | 1833 [4/5] opcodes/riscv-dis.c: Make XLEN variable static | | | 1834 [5/5] opcodes/riscv-dis.c: Remove last_map_state | | | 1836 RISC-V: Move certain arrays to riscv-opc.c | | | 1844 [v2,1/2] ld: Add --pdb option | | | 1845 [v2,2/2] ld: Add minimal pdb generation | | | 1890 gprofng: run tests without installation | | | 1893 [2/2] gprofng: use the --libdir path to find libraries | | | 1894 [3/3] gprofng: no need to build version.texi | | | 1895 [v3,1/2] ld: Add --pdb option | | | 1897 [v3,2/2] ld: Add minimal pdb generation | | | 1928 [v4,1/2] ld: Add --pdb option | | | 1929 [v4,2/2] ld: Add minimal pdb generation | | | 1941 [pushed] Re-apply "Pass PKG_CONFIG_PATH down from top-level Makefile" | | | 1976 [v4,1/8] x86: constify parse_insn()'s input | | | 1977 [v4,2/8] x86: introduce Pass2 insn attribute | | | 1978 [v4,3/8] x86: re-work insn/suffix recognition | | | 1979 [v4,4/8] x86-64: further re-work insn/suffix recognition to also cover MOVSL | | | 1980 [v4,5/8] ix86: don't recognize/derive Q suffix in the common case | | | 1981 [v4,6/8] x86-64: allow HLE store of accumulator to absolute 32-bit address | | | 1982 [v4,7/8] x86: move bad-use-of-TLS-reloc check | | | 1983 [v4,8/8] x86: drop (now) stray IsString | | | 2013 include: Declare getopt function on old GNU libc | | | 2352 ld: Add --undefined-version | | | 2532 [1/1] RISC-V: Make R_RISCV_SUB6 conforms to riscv abi standard | | | 2560 [v3] aarch64-pe support for LD, GAS and BFD | | | 2602 [01/10] Support Intel AVX-IFMA | | | 2608 [02/10] Support Intel AVX-VNNI-INT8 | | | 2611 [03/10] Support Intel AVX-NE-CONVERT | | | 2610 [04/10] Support Intel CMPccXADD | | | 2601 [05/10] Add handler for more i386_cpu_flags | | | 2606 [06/10] Support Intel RAO-INT | | | 2609 [07/10] Support Intel WRMSRNS | | | 2605 [08/10] Support Intel MSRLIST | | | 2607 [09/10] Support Intel AMX-FP16 | | | 2604 [10/10] Support Intel PREFETCHI | | | 2643 x86: fold AVX512-VNNI disassembler entries with AVX-VNNI ones | | | 2654 PR29677, Field `the_bfd` of `asymbol` is uninitialised | | | 2656 e200 LSP support | | | 2657 PowerPC SPE disassembly and tests | | | 2695 Binutils: Adding new testcase for addr2line. | | | 2700 x86: properly decode EVEX.W for AVX512_4{FMAPS,VNNIW} insns | | | 2981 PowerPC se_rfmci and VLE, SPE2 and LSP insns with -many | +------------+--------------------------------------------------------------------------------------+ + git config pull.rebase false + git fetch origin master From github.com:wangliu-iscas/binutils-gdb * branch master -> FETCH_HEAD + git checkout master Switched to a new branch 'master' branch 'master' set up to track 'origin/master'. + git pull origin master From github.com:wangliu-iscas/binutils-gdb * branch master -> FETCH_HEAD Already up to date. + git fetch origin upstream-master From github.com:wangliu-iscas/binutils-gdb * branch upstream-master -> FETCH_HEAD + git checkout upstream-master Switched to a new branch 'upstream-master' branch 'upstream-master' set up to track 'origin/upstream-master'. + git remote add upstream https://sourceware.org/git/binutils-gdb.git + git pull upstream master From https://sourceware.org/git/binutils-gdb * branch master -> FETCH_HEAD * [new branch] master -> upstream/master Already up to date. + git push -u origin upstream-master Everything up-to-date branch 'upstream-master' set up to track 'origin/upstream-master'. + git checkout master Switched to branch 'master' Your branch is up to date with 'origin/master'. + git merge upstream-master Already up to date. + git push -u origin master Everything up-to-date branch 'master' set up to track 'origin/master'. + branchname=series1937-patch2656 ++ git branch -a ++ grep 'series1937-patch2656$' + checkbranch= + checkbranchresult=null + '[' null = series1937-patch2656 ']' + git checkout -b series1937-patch2656 Switched to a new branch 'series1937-patch2656' ++ curl https://patchwork.plctlab.org/api/1.2/series/1937/ % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 1274 100 1274 0 0 37470 0 --:--:-- --:--:-- --:--:-- 37470 + series_response='{"id":1937,"url":"https://patchwork.plctlab.org/api/1.2/series/1937/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/list/?series=1937","project":{"id":2,"url":"https://patchwork.plctlab.org/api/1.2/projects/2/","name":"binutils-gdb","link_name":"binutils-gdb","list_id":"binutils.sourceware.org","list_email":"binutils@sourceware.org","web_url":"https://sourceware.org/mailman/listinfo/binutils","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"name":"e200 LSP support","date":"2022-10-14T11:35:46","submitter":{"id":207,"url":"https://patchwork.plctlab.org/api/1.2/people/207/","name":"Alan Modra","email":"amodra@gmail.com"},"version":1,"total":1,"received_total":1,"received_all":true,"mbox":"https://patchwork.plctlab.org/series/1937/mbox/","cover_letter":null,"patches":[{"id":2656,"url":"https://patchwork.plctlab.org/api/1.2/patches/2656/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0lJksn49ZpABY89@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-14T11:35:46","name":"e200 LSP support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0lJksn49ZpABY89@squeak.grove.modra.org/mbox/"}]}' ++ echo '{"id":1937,"url":"https://patchwork.plctlab.org/api/1.2/series/1937/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/list/?series=1937","project":{"id":2,"url":"https://patchwork.plctlab.org/api/1.2/projects/2/","name":"binutils-gdb","link_name":"binutils-gdb","list_id":"binutils.sourceware.org","list_email":"binutils@sourceware.org","web_url":"https://sourceware.org/mailman/listinfo/binutils","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"name":"e200 LSP support","date":"2022-10-14T11:35:46","submitter":{"id":207,"url":"https://patchwork.plctlab.org/api/1.2/people/207/","name":"Alan Modra","email":"amodra@gmail.com"},"version":1,"total":1,"received_total":1,"received_all":true,"mbox":"https://patchwork.plctlab.org/series/1937/mbox/","cover_letter":null,"patches":[{"id":2656,"url":"https://patchwork.plctlab.org/api/1.2/patches/2656/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0lJksn49ZpABY89@squeak.grove.modra.org/","msgid":"","list_archive_url":null,"date":"2022-10-14T11:35:46","name":"e200 LSP support","mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0lJksn49ZpABY89@squeak.grove.modra.org/mbox/"}]}' ++ jq '.patches[] | (.id|tostring) + "," + .mbox' + patchid_patchurl='"2656,https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0lJksn49ZpABY89@squeak.grove.modra.org/mbox/"' + echo '"2656,https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0lJksn49ZpABY89@squeak.grove.modra.org/mbox/"' + IFS=, + read -r series_patch_id series_patch_url ++ echo '"2656' ++ sed 's/"//g' + series_patch_id=2656 ++ echo 'https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0lJksn49ZpABY89@squeak.grove.modra.org/mbox/"' ++ sed 's/"//g' + series_patch_url=https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0lJksn49ZpABY89@squeak.grove.modra.org/mbox/ ++ git rev-parse HEAD + commitid_before=07a33c2bc17fc86bbd0e8ad08f3649d852f4965f + eval '+++ declare -p bout bret declare -- bout="Applying: e200 LSP support Using index info to reconstruct a base tree... M binutils/doc/binutils.texi M gas/config/tc-ppc.c M gas/doc/c-ppc.texi M gas/testsuite/gas/ppc/lsp-checks.d M gas/testsuite/gas/ppc/lsp.d M gas/testsuite/gas/ppc/ppc.exp M include/opcode/ppc.h M opcodes/ppc-dis.c M opcodes/ppc-opc.c Falling back to patching base and 3-way merge... Auto-merging opcodes/ppc-opc.c CONFLICT (content): Merge conflict in opcodes/ppc-opc.c Auto-merging opcodes/ppc-dis.c Auto-merging gas/testsuite/gas/ppc/ppc.exp CONFLICT (content): Merge conflict in gas/testsuite/gas/ppc/ppc.exp Auto-merging gas/config/tc-ppc.c error: Failed to merge in the changes. hint: Use '\''git am --show-current-patch=diff'\'' to see the failed patch Patch failed at 0001 e200 LSP support When you have resolved this problem, run \"git am --continue\". If you prefer to skip this patch, run \"git am --skip\" instead. To restore the original branch and stop patching, run \"git am --abort\"." declare -- bret="128" ++ berr='\''++++ git_am https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0lJksn49ZpABY89@squeak.grove.modra.org/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0lJksn49ZpABY89@squeak.grove.modra.org/mbox/ ++++ curl https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0lJksn49ZpABY89@squeak.grove.modra.org/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 66134 100 66134 0 0 872k 0 --:--:-- --:--:-- --:--:-- 872k +++ bout='\''\'\'''\''Applying: e200 LSP support Using index info to reconstruct a base tree... M binutils/doc/binutils.texi M gas/config/tc-ppc.c M gas/doc/c-ppc.texi M gas/testsuite/gas/ppc/lsp-checks.d M gas/testsuite/gas/ppc/lsp.d M gas/testsuite/gas/ppc/ppc.exp M include/opcode/ppc.h M opcodes/ppc-dis.c M opcodes/ppc-opc.c Falling back to patching base and 3-way merge... Auto-merging opcodes/ppc-opc.c CONFLICT (content): Merge conflict in opcodes/ppc-opc.c Auto-merging opcodes/ppc-dis.c Auto-merging gas/testsuite/gas/ppc/ppc.exp CONFLICT (content): Merge conflict in gas/testsuite/gas/ppc/ppc.exp Auto-merging gas/config/tc-ppc.c error: Failed to merge in the changes. hint: Use '\''\'\'''\''\'\''\'\'''\'''\''\'\'''\''git am --show-current-patch=diff'\''\'\'''\''\'\''\'\'''\'''\''\'\'''\'' to see the failed patch Patch failed at 0001 e200 LSP support When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort".'\''\'\'''\'' +++ bret=128'\'' ++ declare -p berr declare -- berr="++++ git_am https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0lJksn49ZpABY89@squeak.grove.modra.org/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0lJksn49ZpABY89@squeak.grove.modra.org/mbox/ ++++ curl https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0lJksn49ZpABY89@squeak.grove.modra.org/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 66134 100 66134 0 0 872k 0 --:--:-- --:--:-- --:--:-- 872k +++ bout='\''Applying: e200 LSP support Using index info to reconstruct a base tree... M binutils/doc/binutils.texi M gas/config/tc-ppc.c M gas/doc/c-ppc.texi M gas/testsuite/gas/ppc/lsp-checks.d M gas/testsuite/gas/ppc/lsp.d M gas/testsuite/gas/ppc/ppc.exp M include/opcode/ppc.h M opcodes/ppc-dis.c M opcodes/ppc-opc.c Falling back to patching base and 3-way merge... Auto-merging opcodes/ppc-opc.c CONFLICT (content): Merge conflict in opcodes/ppc-opc.c Auto-merging opcodes/ppc-dis.c Auto-merging gas/testsuite/gas/ppc/ppc.exp CONFLICT (content): Merge conflict in gas/testsuite/gas/ppc/ppc.exp Auto-merging gas/config/tc-ppc.c error: Failed to merge in the changes. hint: Use '\''\\'\'''\''git am --show-current-patch=diff'\''\\'\'''\'' to see the failed patch Patch failed at 0001 e200 LSP support When you have resolved this problem, run \"git am --continue\". If you prefer to skip this patch, run \"git am --skip\" instead. To restore the original branch and stop patching, run \"git am --abort\".'\'' +++ bret=128"' ++ +++ declare -p bout bret /tmp/jenkins2904010026236598035.sh: line 113: +++: command not found ++ declare -- 'bout=Applying: e200 LSP support Using index info to reconstruct a base tree... M binutils/doc/binutils.texi M gas/config/tc-ppc.c M gas/doc/c-ppc.texi M gas/testsuite/gas/ppc/lsp-checks.d M gas/testsuite/gas/ppc/lsp.d M gas/testsuite/gas/ppc/ppc.exp M include/opcode/ppc.h M opcodes/ppc-dis.c M opcodes/ppc-opc.c Falling back to patching base and 3-way merge... Auto-merging opcodes/ppc-opc.c CONFLICT (content): Merge conflict in opcodes/ppc-opc.c Auto-merging opcodes/ppc-dis.c Auto-merging gas/testsuite/gas/ppc/ppc.exp CONFLICT (content): Merge conflict in gas/testsuite/gas/ppc/ppc.exp Auto-merging gas/config/tc-ppc.c error: Failed to merge in the changes. hint: Use '\''git am --show-current-patch=diff'\'' to see the failed patch Patch failed at 0001 e200 LSP support When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort".' ++ declare -- bret=128 ++ ++ 'berr=++++ git_am https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0lJksn49ZpABY89@squeak.grove.modra.org/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0lJksn49ZpABY89@squeak.grove.modra.org/mbox/ ++++ curl https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0lJksn49ZpABY89@squeak.grove.modra.org/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 66134 100 66134 0 0 872k 0 --:--:-- --:--:-- --:--:-- 872k +++ bout='\''Applying: e200 LSP support Using index info to reconstruct a base tree... M binutils/doc/binutils.texi M gas/config/tc-ppc.c M gas/doc/c-ppc.texi M gas/testsuite/gas/ppc/lsp-checks.d M gas/testsuite/gas/ppc/lsp.d M gas/testsuite/gas/ppc/ppc.exp M include/opcode/ppc.h M opcodes/ppc-dis.c M opcodes/ppc-opc.c Falling back to patching base and 3-way merge... Auto-merging opcodes/ppc-opc.c CONFLICT (content): Merge conflict in opcodes/ppc-opc.c Auto-merging opcodes/ppc-dis.c Auto-merging gas/testsuite/gas/ppc/ppc.exp CONFLICT (content): Merge conflict in gas/testsuite/gas/ppc/ppc.exp Auto-merging gas/config/tc-ppc.c error: Failed to merge in the changes. hint: Use '\''\'\'''\''git am --show-current-patch=diff'\''\'\'''\'' to see the failed patch Patch failed at 0001 e200 LSP support When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort".'\'' +++ bret=128' /tmp/jenkins2904010026236598035.sh: line 170: ++: command not found ++ ++ declare -p berr /tmp/jenkins2904010026236598035.sh: line 171: ++: command not found ++ declare -- 'berr=++++ git_am https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0lJksn49ZpABY89@squeak.grove.modra.org/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0lJksn49ZpABY89@squeak.grove.modra.org/mbox/ ++++ curl https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0lJksn49ZpABY89@squeak.grove.modra.org/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 66134 100 66134 0 0 872k 0 --:--:-- --:--:-- --:--:-- 872k +++ bout='\''Applying: e200 LSP support Using index info to reconstruct a base tree... M binutils/doc/binutils.texi M gas/config/tc-ppc.c M gas/doc/c-ppc.texi M gas/testsuite/gas/ppc/lsp-checks.d M gas/testsuite/gas/ppc/lsp.d M gas/testsuite/gas/ppc/ppc.exp M include/opcode/ppc.h M opcodes/ppc-dis.c M opcodes/ppc-opc.c Falling back to patching base and 3-way merge... Auto-merging opcodes/ppc-opc.c CONFLICT (content): Merge conflict in opcodes/ppc-opc.c Auto-merging opcodes/ppc-dis.c Auto-merging gas/testsuite/gas/ppc/ppc.exp CONFLICT (content): Merge conflict in gas/testsuite/gas/ppc/ppc.exp Auto-merging gas/config/tc-ppc.c error: Failed to merge in the changes. hint: Use '\''\'\'''\''git am --show-current-patch=diff'\''\'\'''\'' to see the failed patch Patch failed at 0001 e200 LSP support When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort".'\'' +++ bret=128' ++ git rev-parse HEAD + commitid_after=07a33c2bc17fc86bbd0e8ad08f3649d852f4965f + '[' 128 = 0 ']' + [[ ++++ git_am https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0lJksn49ZpABY89@squeak.grove.modra.org/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0lJksn49ZpABY89@squeak.grove.modra.org/mbox/ ++++ curl https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0lJksn49ZpABY89@squeak.grove.modra.org/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 66134 100 66134 0 0 872k 0 --:--:-- --:--:-- --:--:-- 872k +++ bout='Applying: e200 LSP support Using index info to reconstruct a base tree... M binutils/doc/binutils.texi M gas/config/tc-ppc.c M gas/doc/c-ppc.texi M gas/testsuite/gas/ppc/lsp-checks.d M gas/testsuite/gas/ppc/lsp.d M gas/testsuite/gas/ppc/ppc.exp M include/opcode/ppc.h M opcodes/ppc-dis.c M opcodes/ppc-opc.c Falling back to patching base and 3-way merge... Auto-merging opcodes/ppc-opc.c CONFLICT (content): Merge conflict in opcodes/ppc-opc.c Auto-merging opcodes/ppc-dis.c Auto-merging gas/testsuite/gas/ppc/ppc.exp CONFLICT (content): Merge conflict in gas/testsuite/gas/ppc/ppc.exp Auto-merging gas/config/tc-ppc.c error: Failed to merge in the changes. hint: Use '\''git am --show-current-patch=diff'\'' to see the failed patch Patch failed at 0001 e200 LSP support When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort".' +++ bret=128 =~ sha1 information is lacking or useless ]] + [[ ++++ git_am https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0lJksn49ZpABY89@squeak.grove.modra.org/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0lJksn49ZpABY89@squeak.grove.modra.org/mbox/ ++++ curl https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0lJksn49ZpABY89@squeak.grove.modra.org/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 66134 100 66134 0 0 872k 0 --:--:-- --:--:-- --:--:-- 872k +++ bout='Applying: e200 LSP support Using index info to reconstruct a base tree... M binutils/doc/binutils.texi M gas/config/tc-ppc.c M gas/doc/c-ppc.texi M gas/testsuite/gas/ppc/lsp-checks.d M gas/testsuite/gas/ppc/lsp.d M gas/testsuite/gas/ppc/ppc.exp M include/opcode/ppc.h M opcodes/ppc-dis.c M opcodes/ppc-opc.c Falling back to patching base and 3-way merge... Auto-merging opcodes/ppc-opc.c CONFLICT (content): Merge conflict in opcodes/ppc-opc.c Auto-merging opcodes/ppc-dis.c Auto-merging gas/testsuite/gas/ppc/ppc.exp CONFLICT (content): Merge conflict in gas/testsuite/gas/ppc/ppc.exp Auto-merging gas/config/tc-ppc.c error: Failed to merge in the changes. hint: Use '\''git am --show-current-patch=diff'\'' to see the failed patch Patch failed at 0001 e200 LSP support When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort".' +++ bret=128 =~ Failed to merge in the changes ]] + submit_check warning Unresolved https://patchwork.plctlab.org/jenkins/job/binutils-gdb/115/consoleText 'Git am fail log' + check_state=warning + patch_state=Unresolved + repo_url=https://patchwork.plctlab.org/jenkins/job/binutils-gdb/115/consoleText + DESCRIPTION='Git am fail log' + curl -X POST -H 'Authorization: Token [*******]' -F state=warning -F target_url=https://patchwork.plctlab.org/jenkins/job/binutils-gdb/115/consoleText -F context=binutils-gdb-check -F 'description=Git am fail log' https://patchwork.plctlab.org/api/patches/2656/checks/ % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 974 100 429 100 545 5430 6898 --:--:-- --:--:-- --:--:-- 12329 {"id":1032,"url":"https://patchwork.plctlab.org/api/patches/2656/checks/1032/","user":{"id":1,"url":"https://patchwork.plctlab.org/api/users/1/","username":"snail","first_name":"","last_name":"","email":"wangliu@iscas.ac.cn"},"date":"2022-10-17T02:03:27.386943","state":"warning","target_url":"https://patchwork.plctlab.org/jenkins/job/binutils-gdb/115/consoleText","context":"binutils-gdb-check","description":"Git am fail log"}+ curl -X PATCH -H 'Authorization: Token [*******]' -F state=Unresolved https://patchwork.plctlab.org/api/1.2/patches/2656/ % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0{"id":2656,"url":"https://patchwork.plctlab.org/api/1.2/patches/2656/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0lJksn49ZpABY89@squeak.grove.modra.org/","project":{"id":2,"url":"https://patchwork.plctlab.org/api/1.2/projects/2/","name":"binutils-gdb","link_name":"binutils-gdb","list_id":"binutils.sourceware.org","list_email":"binutils@sourceware.org","web_url":"https://sourceware.org/mailman/listinfo/binutils","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"","list_archive_url":null,"date":"2022-10-14T11:35:46","name":"e200 LSP support","commit_ref":null,"pull_url":null,"state":"unresolved","archived":false,"hash":"09d0ccde141246b612f6514812872dc02c4eddab","submitter":{"id":207,"url":"https://patchwork.plctlab.org/api/1.2/people/207/","name":"Alan Modra","email":"amodra@gmail.com"},"delegate":null,"mbox":"https://patchwork.plctlab.org/project/binutils-gdb/patch/Y0lJksn49ZpABY89@squeak.grove.modra.org/mbox/","series":[{"id":1937,"url":"https://patchwork.plctlab.org/api/1.2/series/1937/","web_url":"https://patchwork.plctlab.org/project/binutils-gdb/list/?series=1937","date":"2022-10-14T11:35:46","name":"e200 LSP support","version":1,"mbox":"https://patchwork.plctlab.org/series/1937/mbox/"}],"comments":"https://patchwork.plctlab.org/api/patches/2656/comments/","check":"warning","checks":"https://patchwork.plctlab.org/api/patches/2656/checks/","tags":{},"headers":{"Return-Path":"","Delivered-To":["ouuuleilei@gmail.com","binutils@sourceware.org"],"Received":["by 2002:a5d:4ac7:0:0:0:0:0 with SMTP id y7csp132838wrs;\n Fri, 14 Oct 2022 04:36:08 -0700 (PDT)","from sourceware.org (server2.sourceware.org. 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charset=us-ascii","Content-Disposition":"inline","X-Spam-Status":"No, score=-3036.3 required=5.0 tests=BAYES_00, DKIM_SIGNED,\n DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0,\n RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS,\n TXREP autolearn=ham autolearn_force=no version=3.4.6","X-Spam-Checker-Version":"SpamAssassin 3.4.6 (2021-04-09) on\n server2.sourceware.org","X-BeenThere":"binutils@sourceware.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"Binutils mailing list ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","From":"Alan Modra via Binutils ","Reply-To":"Alan Modra ","Errors-To":"binutils-bounces+ouuuleilei=gmail.com@sourceware.org","Sender":"\"Binutils\" ","X-getmail-retrieved-from-mailbox":"=?utf-8?q?INBOX?=","X-GMAIL-THRID":"=?utf-8?q?1746662712651094833?=","X-GMAIL-MSGID":"=?utf-8?q?1746662712651094833?="},"content":"It has bothered me for a long time that we have disabled LSP (and SPE)\ntests. Also the LSP test comment indicating there is something wrong\nwith get_powerpc_dialect. I don't think there is. Decoding of a VLE\ninstruction depends on whether the processor is in VLE mode (some\nprocessors support both VLE and standard PPC) which we flag per\nsection with SHF_PPC_VLE for decoding when disassembling.\n\nBackground: Some versions of powerpc e200 have \"Lightweight Signal\nProcessing\" support, examples being e200z215 and e200z425. As far as\nI can tell, LSP and SPE are mutually exclusive. This seems to be\nborne out by insn encoding, for example LSP \"zvaddih\" and SPE \"evaddw\"\nhave the same encoding. So none of the processor descriptions in\nppc_opts ought to have both PPC_OPCODE_LSP and PPC_OPCODE_SPE/2, if we\nwant disassembly to work. I also could not find anything to suggest\nthat the LSP insns are enabled only in VLE mode, which means the LSP\ninsns should not be in vle_opcodes.\n\nFix all this by moving the LSP insns to their own table, and add a new\ne200z2 cpu entry with LSP support, removing LSP from -me200z4 and from\n-mvle. (Yes, I know, as I said above some of the e200z4 processors\nhave LSP. Others have SPE. It's hard to choose good options. Think\nof z2 as meaning earlier, z4 as later.) Also add -mlsp to allow\nadding the LSP insn set.\n\ninclude/\n\t* opcode/ppc.h (lsp_opcodes, lsp_num_opcodes): Declare.\n\t(LSP_OP_TO_SEG): Define.\nbinutils/\n\t* doc/binutils.texi: Update ppc docs.\ngas/\n\t* config/tc-ppc.c (ppc_setup_opcodes): Add lsp opcodes to ppc_hash.\n\t* doc/c-ppc.texi: Document e200 and lsp.\n\t* testsuite/gas/ppc/lsp-checks.d: Assemble with -me200z2.\n\t* testsuite/gas/ppc/lsp.d: Likewise, disassembly too.\n\t* testsuite/gas/ppc/ppc.exp: Don't xfail lsp test.\nopcodes/\n\t* ppc-dis.c (ppc_opts): Add e200z2 and lsp. Don't set\n\tPPC_OPCODE_LSP for e200z4 or vle.\n\t(ppc_parse_cpu): Mutually exclude LSP and SPE.\n\t(LSP_OPCD_SEGS): Define.\n\t(lsp_opcd_indices): New array.\n\t(disassemble_init_powerpc): Init lsp_opcd_indices.\n\t(lookup_lsp): New function.\n\t(print_insn_powerpc): Call it.\n\t* ppc-opc.c: Include libiberty.h for ARRAY_SIZE and use throughout.\n\t(vle_opcodes): Move LSP opcodes to..\n\t(lsp_opcodes): ..here, and sort.\n\t(lsp_num_opcodes): New.","diff":"diff --git a/binutils/doc/binutils.texi b/binutils/doc/binutils.texi\nindex 5ea95edecf1..6eea08fb91b 100644\n--- a/binutils/doc/binutils.texi\n+++ b/binutils/doc/binutils.texi\n@@ -2632,7 +2632,7 @@ rather than @code{li}. All of the @option{-m} arguments for\n @option{601}, @option{603}, @option{604}, @option{620}, @option{7400},\n @option{7410}, @option{7450}, @option{7455}, @option{750cl},\n @option{821}, @option{850}, @option{860}, @option{a2}, @option{booke},\n-@option{booke32}, @option{cell}, @option{com}, @option{e200z4},\n+@option{booke32}, @option{cell}, @option{com}, @option{e200z2}, @option{e200z4},\n @option{e300}, @option{e500}, @option{e500mc}, @option{e500mc64},\n @option{e500x2}, @option{e5500}, @option{e6500}, @option{efs},\n @option{power4}, @option{power5}, @option{power6}, @option{power7},\n@@ -2643,9 +2643,10 @@ rather than @code{li}. All of the @option{-m} arguments for\n @option{pwrx}, @option{titan}, @option{vle}, and @option{future}.\n @option{32} and @option{64} modify the default or a prior CPU\n selection, disabling and enabling 64-bit insns respectively. In\n-addition, @option{altivec}, @option{any}, @option{htm}, @option{vsx},\n-and @option{spe} add capabilities to a previous @emph{or later} CPU\n-selection. @option{any} will disassemble any opcode known to\n+addition, @option{altivec}, @option{any}, @option{lsp}, @option{htm},\n+@option{vsx}, @option{spe} and @option{spe2} add capabilities to a\n+previous @emph{or later} CPU selection.\n+@option{any} will disassemble any opcode known to\n binutils, but in cases where an opcode has two different meanings or\n different arguments, you may not see the disassembly you expect.\n If you disassemble without giving a CPU selection, a default will be\ndiff --git a/gas/config/tc-ppc.c b/gas/config/tc-ppc.c\nindex d20fd757091..5077e055401 100644\n--- a/gas/config/tc-ppc.c\n+++ b/gas/config/tc-ppc.c\n@@ -1810,6 +1810,30 @@ ppc_setup_opcodes (void)\n \t}\n }\n \n+ /* LSP instructions */\n+ if ((ppc_cpu & PPC_OPCODE_LSP) != 0)\n+ {\n+ unsigned int prev_seg = 0;\n+ unsigned int seg;\n+ op_end = lsp_opcodes + lsp_num_opcodes;\n+ for (op = lsp_opcodes; op < op_end; op++)\n+\t{\n+\t if (ENABLE_CHECKING)\n+\t {\n+\t seg = LSP_OP_TO_SEG (op->opcode);\n+\t if (seg < prev_seg)\n+\t\t{\n+\t\t as_bad (_(\"opcode is not sorted for %s\"), op->name);\n+\t\t bad_insn = true;\n+\t\t}\n+\t prev_seg = seg;\n+\t bad_insn |= insn_validate (op);\n+\t }\n+\n+\t str_hash_insert (ppc_hash, op->name, op, 0);\n+\t}\n+ }\n+\n /* SPE2 instructions */\n if ((ppc_cpu & PPC_OPCODE_SPE2) == PPC_OPCODE_SPE2)\n {\ndiff --git a/gas/doc/c-ppc.texi b/gas/doc/c-ppc.texi\nindex 2986d3de7f8..4a9addcdc4e 100644\n--- a/gas/doc/c-ppc.texi\n+++ b/gas/doc/c-ppc.texi\n@@ -81,6 +81,12 @@ Generate code for PowerPC 821/850/860.\n @item -mppc64, -m620\n Generate code for PowerPC 620/625/630.\n \n+@item -me200z2, -me200z4\n+Generate code for e200 variants, e200z2 with LSP, e200z4 with SPE.\n+\n+@item -me300\n+Generate code for PowerPC e300 family.\n+\n @item -me500, -me500x2\n Generate code for Motorola e500 core complex.\n \n@@ -96,11 +102,14 @@ Generate code for Freescale e5500 core complex.\n @item -me6500\n Generate code for Freescale e6500 core complex.\n \n+@item -mlsp\n+Enable LSP instructions. (Disables SPE and SPE2.)\n+\n @item -mspe\n-Generate code for Motorola SPE instructions.\n+Generate code for Motorola SPE instructions. (Disables LSP.)\n \n @item -mspe2\n-Generate code for Freescale SPE2 instructions.\n+Generate code for Freescale SPE2 instructions. (Disables LSP.)\n \n @item -mtitan\n Generate code for AppliedMicro Titan core complex.\n@@ -114,9 +123,6 @@ Generate code for 32-bit BookE.\n @item -ma2\n Generate code for A2 architecture.\n \n-@item -me300\n-Generate code for PowerPC e300 family.\n-\n @item -maltivec\n Generate code for processors with AltiVec instructions.\n \ndiff --git a/gas/testsuite/gas/ppc/lsp-checks.d b/gas/testsuite/gas/ppc/lsp-checks.d\nindex d74151f148f..d654da6bcab 100644\n--- a/gas/testsuite/gas/ppc/lsp-checks.d\n+++ b/gas/testsuite/gas/ppc/lsp-checks.d\n@@ -1,3 +1,3 @@\n #name: Test LSP operands checks\n-#as: -a32 -mbig -mvle\n+#as: -a32 -mbig -me200z2\n #error_output: lsp-checks.l\ndiff --git a/gas/testsuite/gas/ppc/lsp.d b/gas/testsuite/gas/ppc/lsp.d\nindex ca45a364c0f..311e0086e9c 100644\n--- a/gas/testsuite/gas/ppc/lsp.d\n+++ b/gas/testsuite/gas/ppc/lsp.d\n@@ -1,5 +1,5 @@\n-#as: -a32 -mbig -mvle\n-#objdump: -d -Mvle\n+#as: -a32 -mbig -me200z2\n+#objdump: -d -Me200z2\n #name: Validate LSP instructions\n \n .*: +file format elf.*-powerpc.*\ndiff --git a/gas/testsuite/gas/ppc/ppc.exp b/gas/testsuite/gas/ppc/ppc.exp\nindex 53c2d0dc328..9a18ce2e2ff 100644\n--- a/gas/testsuite/gas/ppc/ppc.exp\n+++ b/gas/testsuite/gas/ppc/ppc.exp\n@@ -87,11 +87,7 @@ run_dump_test \"vle-simple-4\"\n run_dump_test \"vle-simple-5\"\n run_dump_test \"vle-simple-6\"\n run_dump_test \"vle-mult-ld-st-insns\"\n-\n-#fail expected until get_powerpc_dialect() patch not applied\n-setup_xfail \"*-*-*\"\n run_dump_test \"lsp\"\n-\n run_dump_test \"lsp-checks\"\n run_dump_test \"efs\"\n run_dump_test \"efs2\"\ndiff --git a/include/opcode/ppc.h b/include/opcode/ppc.h\nindex c5d96a265a8..930d13d3026 100644\n--- a/include/opcode/ppc.h\n+++ b/include/opcode/ppc.h\n@@ -78,6 +78,8 @@ extern const struct powerpc_opcode prefix_opcodes[];\n extern const unsigned int prefix_num_opcodes;\n extern const struct powerpc_opcode vle_opcodes[];\n extern const unsigned int vle_num_opcodes;\n+extern const struct powerpc_opcode lsp_opcodes[];\n+extern const unsigned int lsp_num_opcodes;\n extern const struct powerpc_opcode spe2_opcodes[];\n extern const unsigned int spe2_num_opcodes;\n \n@@ -255,6 +257,9 @@ extern const unsigned int spe2_num_opcodes;\n /* A macro to convert a VLE opcode to a VLE opcode segment. */\n #define VLE_OP_TO_SEG(i) ((i) >> 1)\n \n+/* Map LSP insn to lookup segment for disassembly. */\n+#define LSP_OP_TO_SEG(i) (((i) & 0x7ff) >> 6)\n+\n /* A macro to extract the extended opcode from a SPE2 instruction. */\n #define SPE2_XOP(i) ((i) & 0x7ff)\n \ndiff --git a/opcodes/ppc-dis.c b/opcodes/ppc-dis.c\nindex 3ba06274b21..cc9328c106a 100644\n--- a/opcodes/ppc-dis.c\n+++ b/opcodes/ppc-dis.c\n@@ -131,11 +131,17 @@ struct ppc_mopt ppc_opts[] = {\n 0 },\n { \"com\", PPC_OPCODE_COMMON,\n 0 },\n- { \"e200z4\", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE| PPC_OPCODE_SPE\n+ { \"e200z2\", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_LSP\n \t\t| PPC_OPCODE_ISEL | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK\n \t\t| PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI\n \t\t| PPC_OPCODE_E500 | PPC_OPCODE_VLE | PPC_OPCODE_E200Z4\n-\t\t| PPC_OPCODE_EFS2 | PPC_OPCODE_LSP),\n+\t\t| PPC_OPCODE_EFS2),\n+ 0 },\n+ { \"e200z4\", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_SPE\n+\t\t| PPC_OPCODE_ISEL | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK\n+\t\t| PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI\n+\t\t| PPC_OPCODE_E500 | PPC_OPCODE_VLE | PPC_OPCODE_E200Z4\n+\t\t| PPC_OPCODE_EFS2),\n 0 },\n { \"e300\", PPC_OPCODE_PPC | PPC_OPCODE_E300,\n 0 },\n@@ -173,6 +179,8 @@ struct ppc_mopt ppc_opts[] = {\n 0 },\n { \"efs2\", PPC_OPCODE_PPC | PPC_OPCODE_EFS | PPC_OPCODE_EFS2,\n 0 },\n+ { \"lsp\", PPC_OPCODE_PPC,\n+ PPC_OPCODE_LSP },\n { \"power4\", PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4,\n 0 },\n { \"power5\", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4\n@@ -270,10 +278,10 @@ struct ppc_mopt ppc_opts[] = {\n { \"titan\", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_PMR\n \t\t| PPC_OPCODE_RFMCI | PPC_OPCODE_TITAN),\n 0 },\n- { \"vle\", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE| PPC_OPCODE_SPE\n+ { \"vle\", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_SPE\n \t\t| PPC_OPCODE_ISEL | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK\n \t\t| PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI\n-\t\t| PPC_OPCODE_LSP | PPC_OPCODE_EFS2 | PPC_OPCODE_SPE2),\n+\t\t| PPC_OPCODE_EFS2 | PPC_OPCODE_SPE2),\n PPC_OPCODE_VLE },\n { \"vsx\", PPC_OPCODE_PPC,\n PPC_OPCODE_VSX },\n@@ -321,7 +329,15 @@ ppc_parse_cpu (ppc_cpu_t ppc_cpu, ppc_cpu_t *sticky, const char *arg)\n if (i >= ARRAY_SIZE (ppc_opts))\n return 0;\n \n+ /* SPE and LSP are mutually exclusive, don't allow them both in\n+ sticky options. However do allow them both in ppc_cpu, so that\n+ for example, -mvle -mlsp enables both SPE and LSP for assembly. */\n+ if ((ppc_opts[i].sticky & PPC_OPCODE_LSP) != 0)\n+ *sticky &= ~(PPC_OPCODE_SPE | PPC_OPCODE_SPE2);\n+ else if ((ppc_opts[i].sticky & (PPC_OPCODE_SPE | PPC_OPCODE_SPE2)) != 0)\n+ *sticky &= ~PPC_OPCODE_LSP;\n ppc_cpu |= *sticky;\n+\n return ppc_cpu;\n }\n \n@@ -412,6 +428,8 @@ static unsigned short powerpc_opcd_indices[PPC_OPCD_SEGS + 1];\n static unsigned short prefix_opcd_indices[PREFIX_OPCD_SEGS + 1];\n #define VLE_OPCD_SEGS (1 + VLE_OP_TO_SEG (VLE_OP (-1, 0xffff)))\n static unsigned short vle_opcd_indices[VLE_OPCD_SEGS + 1];\n+#define LSP_OPCD_SEGS (1 + LSP_OP_TO_SEG (-1))\n+static unsigned short lsp_opcd_indices[LSP_OPCD_SEGS + 1];\n #define SPE2_OPCD_SEGS (1 + SPE2_XOP_TO_SEG (SPE2_XOP (-1)))\n static unsigned short spe2_opcd_indices[SPE2_OPCD_SEGS + 1];\n \n@@ -479,6 +497,15 @@ disassemble_init_powerpc (struct disassemble_info *info)\n \t }\n \t}\n \n+ /* LSP opcodes */\n+ for (seg = 0, idx = 0; seg <= LSP_OPCD_SEGS; seg++)\n+\t{\n+\t lsp_opcd_indices[seg] = idx;\n+\t for (; idx < lsp_num_opcodes; idx++)\n+\t if (seg < LSP_OP_TO_SEG (lsp_opcodes[idx].opcode))\n+\t break;\n+\t}\n+\n /* SPE2 opcodes */\n for (seg = 0, idx = 0; seg <= SPE2_OPCD_SEGS; seg++)\n \t{\n@@ -728,6 +755,51 @@ lookup_vle (uint64_t insn, ppc_cpu_t dialect)\n return NULL;\n }\n \n+/* Find a match for INSN in the LSP opcode table. */\n+\n+static const struct powerpc_opcode *\n+lookup_lsp (uint64_t insn, ppc_cpu_t dialect)\n+{\n+ const struct powerpc_opcode *opcode, *opcode_end;\n+ unsigned op, seg;\n+\n+ op = PPC_OP (insn);\n+ if (op != 0x4)\n+ return NULL;\n+\n+ seg = LSP_OP_TO_SEG (insn);\n+\n+ /* Find the first match in the opcode table for this opcode. */\n+ opcode_end = lsp_opcodes + lsp_opcd_indices[seg + 1];\n+ for (opcode = lsp_opcodes + lsp_opcd_indices[seg];\n+ opcode < opcode_end;\n+ ++opcode)\n+ {\n+ const ppc_opindex_t *opindex;\n+ const struct powerpc_operand *operand;\n+ int invalid;\n+\n+ if ((insn & opcode->mask) != opcode->opcode\n+\t || (opcode->deprecated & dialect) != 0)\n+\tcontinue;\n+\n+ /* Check validity of operands. */\n+ invalid = 0;\n+ for (opindex = opcode->operands; *opindex != 0; ++opindex)\n+\t{\n+\t operand = powerpc_operands + *opindex;\n+\t if (operand->extract)\n+\t (*operand->extract) (insn, (ppc_cpu_t) 0, &invalid);\n+\t}\n+ if (invalid)\n+\tcontinue;\n+\n+ return opcode;\n+ }\n+\n+ return NULL;\n+}\n+\n /* Find a match for INSN in the SPE2 opcode table. */\n \n static const struct powerpc_opcode *\n@@ -746,7 +818,7 @@ lookup_spe2 (uint64_t insn, ppc_cpu_t dialect)\n xop = SPE2_XOP (insn);\n seg = SPE2_XOP_TO_SEG (xop);\n \n- /* Find the first match in the opcode table for this major opcode. */\n+ /* Find the first match in the opcode table for this opcode. */\n opcode_end = spe2_opcodes + spe2_opcd_indices[seg + 1];\n for (opcode = spe2_opcodes + spe2_opcd_indices[seg];\n opcode < opcode_end;\n@@ -936,6 +1008,8 @@ print_insn_powerpc (bfd_vma memaddr,\n }\n if (opcode == NULL && insn_length == 4)\n {\n+ if ((dialect & PPC_OPCODE_LSP) != 0)\n+\topcode = lookup_lsp (insn, dialect);\n if ((dialect & PPC_OPCODE_SPE2) != 0)\n \topcode = lookup_spe2 (insn, dialect);\n if (opcode == NULL)\ndiff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c\nindex 25c96ba87b7..1d274c39147 100644\n--- a/opcodes/ppc-opc.c\n+++ b/opcodes/ppc-opc.c\n@@ -23,6 +23,7 @@\n #include \n #include \"opcode/ppc.h\"\n #include \"opintl.h\"\n+#include \"libiberty.h\"\n \n /* This file holds the PowerPC opcode table. The opcode table\n includes almost all of the extended instruction mnemonics. This\n@@ -3873,8 +3874,7 @@ const struct powerpc_operand powerpc_operands[] =\n { 0x3, 15, NULL, NULL, 0 },\n };\n \n-const unsigned int num_powerpc_operands = (sizeof (powerpc_operands)\n-\t\t\t\t\t / sizeof (powerpc_operands[0]));\n+const unsigned int num_powerpc_operands = ARRAY_SIZE (powerpc_operands);\n \f\n /* Macros used to form opcodes. */\n \n@@ -9582,8 +9582,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {\n {\"dctfixqq\",\tXVA(63,994,1),\tXVA_MASK, POWER10,\tPPCVLE,\t\t{VD, FRBp}},\n };\n \n-const unsigned int powerpc_num_opcodes =\n- sizeof (powerpc_opcodes) / sizeof (powerpc_opcodes[0]);\n+const unsigned int powerpc_num_opcodes = ARRAY_SIZE (powerpc_opcodes);\n \f\n /* The opcode table for 8-byte prefix instructions.\n \n@@ -9659,8 +9658,7 @@ const struct powerpc_opcode prefix_opcodes[] = {\n {\"pstxvp\",\t P8LS|OP(62),\t P_D_MASK,\tPOWER10, 0,\t{XTP, D34, PRA0, PCREL}},\n };\n \n-const unsigned int prefix_num_opcodes =\n- sizeof (prefix_opcodes) / sizeof (prefix_opcodes[0]);\n+const unsigned int prefix_num_opcodes = ARRAY_SIZE (prefix_opcodes);\n \f\n /* The VLE opcode table.\n \n@@ -9702,6 +9700,224 @@ const struct powerpc_opcode vle_opcodes[] = {\n {\"se_cmphl\",\tSE_RR(3,3),\tSE_RR_MASK,\tPPCVLE,\t0,\t\t{RX, RY}},\n \n /* by major opcode */\n+{\"e_cmpi\",\tSCI8BF(6,0,21),\tSCI8BF_MASK,\tPPCVLE,\t0,\t\t{CRD32, RA, SCLSCI8}},\n+{\"e_cmpwi\",\tSCI8BF(6,0,21),\tSCI8BF_MASK,\tPPCVLE,\t0,\t\t{CRD32, RA, SCLSCI8}},\n+{\"e_cmpli\",\tSCI8BF(6,1,21),\tSCI8BF_MASK,\tPPCVLE,\t0,\t\t{CRD32, RA, SCLSCI8}},\n+{\"e_cmplwi\",\tSCI8BF(6,1,21),\tSCI8BF_MASK,\tPPCVLE,\t0,\t\t{CRD32, RA, SCLSCI8}},\n+{\"e_addi\",\tSCI8(6,16),\tSCI8_MASK,\tPPCVLE,\t0,\t\t{RT, RA, SCLSCI8}},\n+{\"e_subi\",\tSCI8(6,16),\tSCI8_MASK,\tPPCVLE,\t0,\t\t{RT, RA, SCLSCI8N}},\n+{\"e_addi.\",\tSCI8(6,17),\tSCI8_MASK,\tPPCVLE,\t0,\t\t{RT, RA, SCLSCI8}},\n+{\"e_addic\",\tSCI8(6,18),\tSCI8_MASK,\tPPCVLE,\t0,\t\t{RT, RA, SCLSCI8}},\n+{\"e_subic\",\tSCI8(6,18),\tSCI8_MASK,\tPPCVLE,\tEXT,\t\t{RT, RA, SCLSCI8N}},\n+{\"e_addic.\",\tSCI8(6,19),\tSCI8_MASK,\tPPCVLE,\t0,\t\t{RT, RA, SCLSCI8}},\n+{\"e_subic.\",\tSCI8(6,19),\tSCI8_MASK,\tPPCVLE,\tEXT,\t\t{RT, RA, SCLSCI8N}},\n+{\"e_mulli\",\tSCI8(6,20),\tSCI8_MASK,\tPPCVLE,\t0,\t\t{RT, RA, SCLSCI8}},\n+{\"e_subfic\",\tSCI8(6,22),\tSCI8_MASK,\tPPCVLE,\t0,\t\t{RT, RA, SCLSCI8}},\n+{\"e_subfic.\",\tSCI8(6,23),\tSCI8_MASK,\tPPCVLE,\t0,\t\t{RT, RA, SCLSCI8}},\n+{\"e_andi\",\tSCI8(6,24),\tSCI8_MASK,\tPPCVLE,\t0,\t\t{RA, RS, SCLSCI8}},\n+{\"e_andi.\",\tSCI8(6,25),\tSCI8_MASK,\tPPCVLE,\t0,\t\t{RA, RS, SCLSCI8}},\n+{\"e_nop\",\tSCI8(6,26),\t0xffffffff,\tPPCVLE,\tEXT,\t\t{0}},\n+{\"e_ori\",\tSCI8(6,26),\tSCI8_MASK,\tPPCVLE,\t0,\t\t{RA, RS, SCLSCI8}},\n+{\"e_ori.\",\tSCI8(6,27),\tSCI8_MASK,\tPPCVLE,\t0,\t\t{RA, RS, SCLSCI8}},\n+{\"e_xori\",\tSCI8(6,28),\tSCI8_MASK,\tPPCVLE,\t0,\t\t{RA, RS, SCLSCI8}},\n+{\"e_xori.\",\tSCI8(6,29),\tSCI8_MASK,\tPPCVLE,\t0,\t\t{RA, RS, SCLSCI8}},\n+{\"e_lbzu\",\tOPVUP(6,0),\tOPVUP_MASK,\tPPCVLE,\t0,\t\t{RT, D8, RA0}},\n+{\"e_lhau\",\tOPVUP(6,3),\tOPVUP_MASK,\tPPCVLE,\t0,\t\t{RT, D8, RA0}},\n+{\"e_lhzu\",\tOPVUP(6,1),\tOPVUP_MASK,\tPPCVLE,\t0,\t\t{RT, D8, RA0}},\n+{\"e_lmw\",\tOPVUP(6,8),\tOPVUP_MASK,\tPPCVLE,\t0,\t\t{RT, D8, RA0}},\n+{\"e_lwzu\",\tOPVUP(6,2),\tOPVUP_MASK,\tPPCVLE,\t0,\t\t{RT, D8, RA0}},\n+{\"e_stbu\",\tOPVUP(6,4),\tOPVUP_MASK,\tPPCVLE,\t0,\t\t{RT, D8, RA0}},\n+{\"e_sthu\",\tOPVUP(6,5),\tOPVUP_MASK,\tPPCVLE,\t0,\t\t{RT, D8, RA0}},\n+{\"e_stwu\",\tOPVUP(6,6),\tOPVUP_MASK,\tPPCVLE,\t0,\t\t{RT, D8, RA0}},\n+{\"e_stmw\",\tOPVUP(6,9),\tOPVUP_MASK,\tPPCVLE,\t0,\t\t{RT, D8, RA0}},\n+{\"e_lmvgprw\",\tOPVUPRT(6,16,0),OPVUPRT_MASK,\tPPCVLE,\t0,\t\t{D8, RA0}},\n+{\"e_ldmvgprw\",\tOPVUPRT(6,16,0),OPVUPRT_MASK,\tPPCVLE,\t0,\t\t{D8, RA0}},\n+{\"e_stmvgprw\",\tOPVUPRT(6,17,0),OPVUPRT_MASK,\tPPCVLE,\t0,\t\t{D8, RA0}},\n+{\"e_lmvsprw\",\tOPVUPRT(6,16,1),OPVUPRT_MASK,\tPPCVLE,\t0,\t\t{D8, RA0}},\n+{\"e_ldmvsprw\",\tOPVUPRT(6,16,1),OPVUPRT_MASK,\tPPCVLE,\t0,\t\t{D8, RA0}},\n+{\"e_stmvsprw\",\tOPVUPRT(6,17,1),OPVUPRT_MASK,\tPPCVLE,\t0,\t\t{D8, RA0}},\n+{\"e_lmvsrrw\",\tOPVUPRT(6,16,4),OPVUPRT_MASK,\tPPCVLE,\t0,\t\t{D8, RA0}},\n+{\"e_ldmvsrrw\",\tOPVUPRT(6,16,4),OPVUPRT_MASK,\tPPCVLE,\t0,\t\t{D8, RA0}},\n+{\"e_stmvsrrw\",\tOPVUPRT(6,17,4),OPVUPRT_MASK,\tPPCVLE,\t0,\t\t{D8, RA0}},\n+{\"e_lmvcsrrw\",\tOPVUPRT(6,16,5),OPVUPRT_MASK,\tPPCVLE,\t0,\t\t{D8, RA0}},\n+{\"e_ldmvcsrrw\",\tOPVUPRT(6,16,5),OPVUPRT_MASK,\tPPCVLE,\t0,\t\t{D8, RA0}},\n+{\"e_stmvcsrrw\",\tOPVUPRT(6,17,5),OPVUPRT_MASK,\tPPCVLE,\t0,\t\t{D8, RA0}},\n+{\"e_lmvdsrrw\",\tOPVUPRT(6,16,6),OPVUPRT_MASK,\tPPCVLE,\t0,\t\t{D8, RA0}},\n+{\"e_ldmvdsrrw\",\tOPVUPRT(6,16,6),OPVUPRT_MASK,\tPPCVLE,\t0,\t\t{D8, RA0}},\n+{\"e_stmvdsrrw\",\tOPVUPRT(6,17,6),OPVUPRT_MASK,\tPPCVLE,\t0,\t\t{D8, RA0}},\n+{\"e_lmvmcsrrw\",\tOPVUPRT(6,16,7),OPVUPRT_MASK,\tPPCVLE,\t0,\t\t{D8, RA0}},\n+{\"e_stmvmcsrrw\",\tOPVUPRT(6,17,7),OPVUPRT_MASK,\tPPCVLE,\t0,\t\t{D8, RA0}},\n+{\"e_add16i\",\tOP(7),\t\tOP_MASK,\tPPCVLE,\t0,\t\t{RT, RA, SI}},\n+{\"e_la\",\tOP(7),\t\tOP_MASK,\tPPCVLE,\tEXT,\t\t{RT, D, RA0}},\n+{\"e_sub16i\",\tOP(7),\t\tOP_MASK,\tPPCVLE,\tEXT,\t\t{RT, RA, NSI}},\n+\n+{\"se_addi\",\tSE_IM5(8,0),\tSE_IM5_MASK,\tPPCVLE,\t0,\t\t{RX, OIMM5}},\n+{\"se_cmpli\",\tSE_IM5(8,1),\tSE_IM5_MASK,\tPPCVLE,\t0,\t\t{RX, OIMM5}},\n+{\"se_subi\",\tSE_IM5(9,0),\tSE_IM5_MASK,\tPPCVLE,\t0,\t\t{RX, OIMM5}},\n+{\"se_subi.\",\tSE_IM5(9,1),\tSE_IM5_MASK,\tPPCVLE,\t0,\t\t{RX, OIMM5}},\n+{\"se_cmpi\",\tSE_IM5(10,1),\tSE_IM5_MASK,\tPPCVLE,\t0,\t\t{RX, UI5}},\n+{\"se_bmaski\",\tSE_IM5(11,0),\tSE_IM5_MASK,\tPPCVLE,\t0,\t\t{RX, UI5}},\n+{\"se_andi\",\tSE_IM5(11,1),\tSE_IM5_MASK,\tPPCVLE,\t0,\t\t{RX, UI5}},\n+\n+{\"e_lbz\",\tOP(12),\t\tOP_MASK,\tPPCVLE,\t0,\t\t{RT, D, RA0}},\n+{\"e_stb\",\tOP(13),\t\tOP_MASK,\tPPCVLE,\t0,\t\t{RT, D, RA0}},\n+{\"e_lha\",\tOP(14),\t\tOP_MASK,\tPPCVLE,\t0,\t\t{RT, D, RA0}},\n+\n+{\"se_srw\",\tSE_RR(16,0),\tSE_RR_MASK,\tPPCVLE,\t0,\t\t{RX, RY}},\n+{\"se_sraw\",\tSE_RR(16,1),\tSE_RR_MASK,\tPPCVLE,\t0,\t\t{RX, RY}},\n+{\"se_slw\",\tSE_RR(16,2),\tSE_RR_MASK,\tPPCVLE,\t0,\t\t{RX, RY}},\n+{\"se_nop\",\tSE_RR(17,0),\t0xffff,\t\tPPCVLE,\tEXT,\t\t{0}},\n+{\"se_or\",\tSE_RR(17,0),\tSE_RR_MASK,\tPPCVLE,\t0,\t\t{RX, RY}},\n+{\"se_andc\",\tSE_RR(17,1),\tSE_RR_MASK,\tPPCVLE,\t0,\t\t{RX, RY}},\n+{\"se_and\",\tSE_RR(17,2),\tSE_RR_MASK,\tPPCVLE,\t0,\t\t{RX, RY}},\n+{\"se_and.\",\tSE_RR(17,3),\tSE_RR_MASK,\tPPCVLE,\t0,\t\t{RX, RY}},\n+{\"se_li\",\tIM7(9),\t\tIM7_MASK,\tPPCVLE,\t0,\t\t{RX, UI7}},\n+\n+{\"e_lwz\",\tOP(20),\t\tOP_MASK,\tPPCVLE,\t0,\t\t{RT, D, RA0}},\n+{\"e_stw\",\tOP(21),\t\tOP_MASK,\tPPCVLE,\t0,\t\t{RT, D, RA0}},\n+{\"e_lhz\",\tOP(22),\t\tOP_MASK,\tPPCVLE,\t0,\t\t{RT, D, RA0}},\n+{\"e_sth\",\tOP(23),\t\tOP_MASK,\tPPCVLE,\t0,\t\t{RT, D, RA0}},\n+\n+{\"se_bclri\",\tSE_IM5(24,0),\tSE_IM5_MASK,\tPPCVLE,\t0,\t\t{RX, UI5}},\n+{\"se_bgeni\",\tSE_IM5(24,1),\tSE_IM5_MASK,\tPPCVLE,\t0,\t\t{RX, UI5}},\n+{\"se_bseti\",\tSE_IM5(25,0),\tSE_IM5_MASK,\tPPCVLE,\t0,\t\t{RX, UI5}},\n+{\"se_btsti\",\tSE_IM5(25,1),\tSE_IM5_MASK,\tPPCVLE,\t0,\t\t{RX, UI5}},\n+{\"se_srwi\",\tSE_IM5(26,0),\tSE_IM5_MASK,\tPPCVLE,\t0,\t\t{RX, UI5}},\n+{\"se_srawi\",\tSE_IM5(26,1),\tSE_IM5_MASK,\tPPCVLE,\t0,\t\t{RX, UI5}},\n+{\"se_slwi\",\tSE_IM5(27,0),\tSE_IM5_MASK,\tPPCVLE,\t0,\t\t{RX, UI5}},\n+\n+{\"e_lis\",\tI16L(28,28),\tI16L_MASK,\tPPCVLE,\t0,\t\t{RD, VLEUIMML}},\n+{\"e_and2is.\",\tI16L(28,29),\tI16L_MASK,\tPPCVLE,\t0,\t\t{RD, VLEUIMML}},\n+{\"e_or2is\",\tI16L(28,26),\tI16L_MASK,\tPPCVLE,\t0,\t\t{RD, VLEUIMML}},\n+{\"e_and2i.\",\tI16L(28,25),\tI16L_MASK,\tPPCVLE,\t0,\t\t{RD, VLEUIMML}},\n+{\"e_or2i\",\tI16L(28,24),\tI16L_MASK,\tPPCVLE,\t0,\t\t{RD, VLEUIMML}},\n+{\"e_cmphl16i\",\tIA16(28,23),\tIA16_MASK,\tPPCVLE,\t0,\t\t{RA, VLEUIMM}},\n+{\"e_cmph16i\",\tIA16(28,22),\tIA16_MASK,\tPPCVLE,\t0,\t\t{RA, VLESIMM}},\n+{\"e_cmpl16i\",\tI16A(28,21),\tI16A_MASK,\tPPCVLE,\t0,\t\t{RA, VLEUIMM}},\n+{\"e_mull2i\",\tI16A(28,20),\tI16A_MASK,\tPPCVLE,\t0,\t\t{RA, VLESIMM}},\n+{\"e_cmp16i\",\tIA16(28,19),\tIA16_MASK,\tPPCVLE,\t0,\t\t{RA, VLESIMM}},\n+{\"e_sub2is\",\tI16A(28,18),\tI16A_MASK,\tPPCVLE,\tEXT,\t\t{RA, VLENSIMM}},\n+{\"e_add2is\",\tI16A(28,18),\tI16A_MASK,\tPPCVLE,\t0,\t\t{RA, VLESIMM}},\n+{\"e_sub2i.\",\tI16A(28,17),\tI16A_MASK,\tPPCVLE,\tEXT,\t\t{RA, VLENSIMM}},\n+{\"e_add2i.\",\tI16A(28,17),\tI16A_MASK,\tPPCVLE,\t0,\t\t{RA, VLESIMM}},\n+{\"e_li\",\tLI20(28,0),\tLI20_MASK,\tPPCVLE,\t0,\t\t{RT, IMM20}},\n+{\"e_rlwimi\",\tM(29,0),\tM_MASK,\t\tPPCVLE,\t0,\t\t{RA, RS, SH, MB, ME}},\n+{\"e_inslwi\",\tM(29,0),\tM_MASK,\t\tPPCVLE, EXT,\t\t{RA, RS, ILWn, ILWb}},\n+{\"e_insrwi\",\tM(29,0),\tM_MASK,\t\tPPCVLE, EXT,\t\t{RA, RS, IRWn, IRWb}},\n+{\"e_rotlwi\",\tMME(29,31,1),\tMMBME_MASK,\tPPCVLE, EXT,\t\t{RA, RS, SH}},\n+{\"e_rotrwi\",\tMME(29,31,1),\tMMBME_MASK,\tPPCVLE, EXT,\t\t{RA, RS, RRWn}},\n+{\"e_clrlwi\",\tMME(29,31,1),\tMSHME_MASK,\tPPCVLE, EXT,\t\t{RA, RS, MB}},\n+{\"e_clrrwi\",\tM(29,1),\tMSHMB_MASK,\tPPCVLE, EXT,\t\t{RA, RS, CRWn}},\n+{\"e_rlwinm\",\tM(29,1),\tM_MASK,\t\tPPCVLE,\t0,\t\t{RA, RS, SH, MBE, ME}},\n+{\"e_extlwi\",\tM(29,1),\tMMB_MASK,\tPPCVLE, EXT,\t\t{RA, RS, ELWn, SH}},\n+{\"e_extrwi\",\tMME(29,31,1),\tMME_MASK,\tPPCVLE, EXT,\t\t{RA, RS, ERWn, ERWb}},\n+{\"e_clrlslwi\",\tM(29,1),\tM_MASK,\t\tPPCVLE, EXT,\t\t{RA, RS, CSLWb, CSLWn}},\n+{\"e_b\",\t\tBD24(30,0,0),\tBD24_MASK,\tPPCVLE,\t0,\t\t{B24}},\n+{\"e_bl\",\tBD24(30,0,1),\tBD24_MASK,\tPPCVLE,\t0,\t\t{B24}},\n+{\"e_bdnz\",\tEBD15(30,8,BO32DNZ,0),\tEBD15_MASK, PPCVLE, EXT,\t{B15}},\n+{\"e_bdnzl\",\tEBD15(30,8,BO32DNZ,1),\tEBD15_MASK, PPCVLE, EXT,\t{B15}},\n+{\"e_bdz\",\tEBD15(30,8,BO32DZ,0),\tEBD15_MASK, PPCVLE, EXT,\t{B15}},\n+{\"e_bdzl\",\tEBD15(30,8,BO32DZ,1),\tEBD15_MASK, PPCVLE, EXT,\t{B15}},\n+{\"e_bge\",\tEBD15BI(30,8,BO32F,CBLT,0), EBD15BI_MASK, PPCVLE, EXT,\t{CRS,B15}},\n+{\"e_bgel\",\tEBD15BI(30,8,BO32F,CBLT,1), EBD15BI_MASK, PPCVLE, EXT,\t{CRS,B15}},\n+{\"e_bnl\",\tEBD15BI(30,8,BO32F,CBLT,0), EBD15BI_MASK, PPCVLE, EXT,\t{CRS,B15}},\n+{\"e_bnll\",\tEBD15BI(30,8,BO32F,CBLT,1), EBD15BI_MASK, PPCVLE, EXT,\t{CRS,B15}},\n+{\"e_blt\",\tEBD15BI(30,8,BO32T,CBLT,0), EBD15BI_MASK, PPCVLE, EXT,\t{CRS,B15}},\n+{\"e_bltl\",\tEBD15BI(30,8,BO32T,CBLT,1), EBD15BI_MASK, PPCVLE, EXT,\t{CRS,B15}},\n+{\"e_bgt\",\tEBD15BI(30,8,BO32T,CBGT,0), EBD15BI_MASK, PPCVLE, EXT,\t{CRS,B15}},\n+{\"e_bgtl\",\tEBD15BI(30,8,BO32T,CBGT,1), EBD15BI_MASK, PPCVLE, EXT,\t{CRS,B15}},\n+{\"e_ble\",\tEBD15BI(30,8,BO32F,CBGT,0), EBD15BI_MASK, PPCVLE, EXT,\t{CRS,B15}},\n+{\"e_blel\",\tEBD15BI(30,8,BO32F,CBGT,1), EBD15BI_MASK, PPCVLE, EXT,\t{CRS,B15}},\n+{\"e_bng\",\tEBD15BI(30,8,BO32F,CBGT,0), EBD15BI_MASK, PPCVLE, EXT,\t{CRS,B15}},\n+{\"e_bngl\",\tEBD15BI(30,8,BO32F,CBGT,1), EBD15BI_MASK, PPCVLE, EXT,\t{CRS,B15}},\n+{\"e_bne\",\tEBD15BI(30,8,BO32F,CBEQ,0), EBD15BI_MASK, PPCVLE, EXT,\t{CRS,B15}},\n+{\"e_bnel\",\tEBD15BI(30,8,BO32F,CBEQ,1), EBD15BI_MASK, PPCVLE, EXT,\t{CRS,B15}},\n+{\"e_beq\",\tEBD15BI(30,8,BO32T,CBEQ,0), EBD15BI_MASK, PPCVLE, EXT,\t{CRS,B15}},\n+{\"e_beql\",\tEBD15BI(30,8,BO32T,CBEQ,1), EBD15BI_MASK, PPCVLE, EXT,\t{CRS,B15}},\n+{\"e_bso\",\tEBD15BI(30,8,BO32T,CBSO,0), EBD15BI_MASK, PPCVLE, EXT,\t{CRS,B15}},\n+{\"e_bsol\",\tEBD15BI(30,8,BO32T,CBSO,1), EBD15BI_MASK, PPCVLE, EXT,\t{CRS,B15}},\n+{\"e_bun\",\tEBD15BI(30,8,BO32T,CBSO,0), EBD15BI_MASK, PPCVLE, EXT,\t{CRS,B15}},\n+{\"e_bunl\",\tEBD15BI(30,8,BO32T,CBSO,1), EBD15BI_MASK, PPCVLE, EXT,\t{CRS,B15}},\n+{\"e_bns\",\tEBD15BI(30,8,BO32F,CBSO,0), EBD15BI_MASK, PPCVLE, EXT,\t{CRS,B15}},\n+{\"e_bnsl\",\tEBD15BI(30,8,BO32F,CBSO,1), EBD15BI_MASK, PPCVLE, EXT,\t{CRS,B15}},\n+{\"e_bnu\",\tEBD15BI(30,8,BO32F,CBSO,0), EBD15BI_MASK, PPCVLE, EXT,\t{CRS,B15}},\n+{\"e_bnul\",\tEBD15BI(30,8,BO32F,CBSO,1), EBD15BI_MASK, PPCVLE, EXT,\t{CRS,B15}},\n+{\"e_bc\",\tBD15(30,8,0),\tBD15_MASK,\tPPCVLE,\t0,\t\t{BO32, BI32, B15}},\n+{\"e_bcl\",\tBD15(30,8,1),\tBD15_MASK,\tPPCVLE,\t0,\t\t{BO32, BI32, B15}},\n+\n+{\"e_bf\",\tEBD15(30,8,BO32F,0), EBD15_MASK, PPCVLE, EXT,\t\t{BI32,B15}},\n+{\"e_bfl\",\tEBD15(30,8,BO32F,1), EBD15_MASK, PPCVLE, EXT,\t\t{BI32,B15}},\n+{\"e_bt\",\tEBD15(30,8,BO32T,0), EBD15_MASK, PPCVLE, EXT,\t\t{BI32,B15}},\n+{\"e_btl\",\tEBD15(30,8,BO32T,1), EBD15_MASK, PPCVLE, EXT,\t\t{BI32,B15}},\n+\n+{\"e_cmph\",\tX(31,14),\tX_MASK,\t\tPPCVLE,\t0,\t\t{CRD, RA, RB}},\n+{\"e_sc\",\tX(31,36),\tXRTRA_MASK,\tPPCVLE,\t0,\t\t{ELEV}},\n+{\"e_cmphl\",\tX(31,46),\tX_MASK,\t\tPPCVLE,\t0,\t\t{CRD, RA, RB}},\n+{\"e_crandc\",\tXL(31,129),\tXL_MASK,\tPPCVLE,\t0,\t\t{BT, BA, BB}},\n+{\"e_crnand\",\tXL(31,225),\tXL_MASK,\tPPCVLE,\t0,\t\t{BT, BA, BB}},\n+{\"e_crnot\",\tXL(31,33),\tXL_MASK,\tPPCVLE,\tEXT,\t\t{BT, BAB}},\n+{\"e_crnor\",\tXL(31,33),\tXL_MASK,\tPPCVLE,\t0,\t\t{BT, BA, BB}},\n+{\"e_crclr\",\tXL(31,193),\tXL_MASK,\tPPCVLE,\tEXT,\t\t{BTAB}},\n+{\"e_crxor\",\tXL(31,193),\tXL_MASK,\tPPCVLE,\t0,\t\t{BT, BA, BB}},\n+{\"e_mcrf\",\tXL(31,16),\tXL_MASK,\tPPCVLE,\t0,\t\t{CRD, CR}},\n+{\"e_slwi\",\tEX(31,112),\tEX_MASK,\tPPCVLE,\t0,\t\t{RA, RS, SH}},\n+{\"e_slwi.\",\tEX(31,113),\tEX_MASK,\tPPCVLE,\t0,\t\t{RA, RS, SH}},\n+\n+{\"e_crand\",\tXL(31,257),\tXL_MASK,\tPPCVLE,\t0,\t\t{BT, BA, BB}},\n+\n+{\"e_rlw\",\tEX(31,560),\tEX_MASK,\tPPCVLE,\t0,\t\t{RA, RS, RB}},\n+{\"e_rlw.\",\tEX(31,561),\tEX_MASK,\tPPCVLE,\t0,\t\t{RA, RS, RB}},\n+\n+{\"e_crset\",\tXL(31,289),\tXL_MASK,\tPPCVLE,\tEXT,\t\t{BTAB}},\n+{\"e_creqv\",\tXL(31,289),\tXL_MASK,\tPPCVLE,\t0,\t\t{BT, BA, BB}},\n+\n+{\"e_rlwi\",\tEX(31,624),\tEX_MASK,\tPPCVLE,\t0,\t\t{RA, RS, SH}},\n+{\"e_rlwi.\",\tEX(31,625),\tEX_MASK,\tPPCVLE,\t0,\t\t{RA, RS, SH}},\n+\n+{\"e_crorc\",\tXL(31,417),\tXL_MASK,\tPPCVLE,\t0,\t\t{BT, BA, BB}},\n+\n+{\"e_crmove\",\tXL(31,449),\tXL_MASK,\tPPCVLE,\tEXT,\t\t{BT, BAB}},\n+{\"e_cror\",\tXL(31,449),\tXL_MASK,\tPPCVLE,\t0,\t\t{BT, BA, BB}},\n+\n+{\"mtmas1\",\tXSPR(31,467,625), XSPR_MASK,\tPPCVLE,\tEXT,\t\t{RS}},\n+\n+{\"e_srwi\",\tEX(31,1136),\tEX_MASK,\tPPCVLE,\t0,\t\t{RA, RS, SH}},\n+{\"e_srwi.\",\tEX(31,1137),\tEX_MASK,\tPPCVLE,\t0,\t\t{RA, RS, SH}},\n+\n+{\"se_lbz\",\tSD4(8),\t\tSD4_MASK,\tPPCVLE,\t0,\t\t{RZ, SE_SD, RX}},\n+\n+{\"se_stb\",\tSD4(9),\t\tSD4_MASK,\tPPCVLE,\t0,\t\t{RZ, SE_SD, RX}},\n+\n+{\"se_lhz\",\tSD4(10),\tSD4_MASK,\tPPCVLE,\t0,\t\t{RZ, SE_SDH, RX}},\n+\n+{\"se_sth\",\tSD4(11),\tSD4_MASK,\tPPCVLE,\t0,\t\t{RZ, SE_SDH, RX}},\n+\n+{\"se_lwz\",\tSD4(12),\tSD4_MASK,\tPPCVLE,\t0,\t\t{RZ, SE_SDW, RX}},\n+\n+{\"se_stw\",\tSD4(13),\tSD4_MASK,\tPPCVLE,\t0,\t\t{RZ, SE_SDW, RX}},\n+\n+{\"se_bge\",\tEBD8IO(28,0,0),\tEBD8IO3_MASK,\tPPCVLE,\tEXT,\t\t{B8}},\n+{\"se_bnl\",\tEBD8IO(28,0,0),\tEBD8IO3_MASK,\tPPCVLE,\tEXT,\t\t{B8}},\n+{\"se_ble\",\tEBD8IO(28,0,1),\tEBD8IO3_MASK,\tPPCVLE,\tEXT,\t\t{B8}},\n+{\"se_bng\",\tEBD8IO(28,0,1),\tEBD8IO3_MASK,\tPPCVLE,\tEXT,\t\t{B8}},\n+{\"se_bne\",\tEBD8IO(28,0,2),\tEBD8IO3_MASK,\tPPCVLE,\tEXT,\t\t{B8}},\n+{\"se_bns\",\tEBD8IO(28,0,3),\tEBD8IO3_MASK,\tPPCVLE,\tEXT,\t\t{B8}},\n+{\"se_bnu\",\tEBD8IO(28,0,3),\tEBD8IO3_MASK,\tPPCVLE,\tEXT,\t\t{B8}},\n+{\"se_bf\",\tEBD8IO(28,0,0),\tEBD8IO2_MASK,\tPPCVLE,\tEXT,\t\t{BI16, B8}},\n+{\"se_blt\",\tEBD8IO(28,1,0),\tEBD8IO3_MASK,\tPPCVLE,\tEXT,\t\t{B8}},\n+{\"se_bgt\",\tEBD8IO(28,1,1),\tEBD8IO3_MASK,\tPPCVLE,\tEXT,\t\t{B8}},\n+{\"se_beq\",\tEBD8IO(28,1,2),\tEBD8IO3_MASK,\tPPCVLE,\tEXT,\t\t{B8}},\n+{\"se_bso\",\tEBD8IO(28,1,3),\tEBD8IO3_MASK,\tPPCVLE,\tEXT,\t\t{B8}},\n+{\"se_bun\",\tEBD8IO(28,1,3),\tEBD8IO3_MASK,\tPPCVLE,\tEXT,\t\t{B8}},\n+{\"se_bt\",\tEBD8IO(28,1,0),\tEBD8IO2_MASK,\tPPCVLE,\tEXT,\t\t{BI16, B8}},\n+{\"se_bc\",\tBD8IO(28),\tBD8IO_MASK,\tPPCVLE,\t0,\t\t{BO16, BI16, B8}},\n+{\"se_b\",\tBD8(58,0,0),\tBD8_MASK,\tPPCVLE,\t0,\t\t{B8}},\n+{\"se_bl\",\tBD8(58,0,1),\tBD8_MASK,\tPPCVLE,\t0,\t\t{B8}},\n+};\n+\n+const unsigned int vle_num_opcodes = ARRAY_SIZE (vle_opcodes);\n+\n+const struct powerpc_opcode lsp_opcodes[] = {\n {\"zvaddih\",\t VX(4, 0x200), VX_MASK,\tPPCLSP, 0,\t\t{RD, RA, EVUIMM}},\n {\"zvsubifh\",\t VX(4, 0x201), VX_MASK,\tPPCLSP, 0,\t\t{RD, RA, EVUIMM}},\n {\"zvaddh\",\t VX(4, 0x204), VX_MASK,\tPPCLSP, 0,\t\t{RD, RA, RB}},\n@@ -9798,6 +10014,114 @@ const struct powerpc_opcode vle_opcodes[] = {\n {\"zslwss\",\t VX(4, 0x27D), VX_MASK,\tPPCLSP, 0,\t\t{RD, RA, RB}},\n {\"zslwius\",\t VX(4, 0x27E), VX_MASK,\tPPCLSP, 0,\t\t{RD, RA, EVUIMM}},\n {\"zslwiss\",\t VX(4, 0x27F), VX_MASK,\tPPCLSP, 0,\t\t{RD, RA, EVUIMM}},\n+{\"zlddx\",\t VX(4, 0x300), VX_MASK,\tPPCLSP, 0,\t\t{RD_EVEN, RA, RB}},\n+{\"zldd\",\t VX(4, 0x301), VX_MASK,\tPPCLSP, 0,\t\t{RD_EVEN, EVUIMM_8, RA}},\n+{\"zldwx\",\t VX(4, 0x302), VX_MASK,\tPPCLSP, 0,\t\t{RD_EVEN, RA, RB}},\n+{\"zldw\",\t VX(4, 0x303), VX_MASK,\tPPCLSP, 0,\t\t{RD_EVEN, EVUIMM_8, RA}},\n+{\"zldhx\",\t VX(4, 0x304), VX_MASK,\tPPCLSP, 0,\t\t{RD_EVEN, RA, RB}},\n+{\"zldh\",\t VX(4, 0x305), VX_MASK,\tPPCLSP, 0,\t\t{RD_EVEN, EVUIMM_8, RA}},\n+{\"zlwgsfdx\",\t VX(4, 0x308), VX_MASK,\tPPCLSP, 0,\t\t{RD_EVEN, RA, RB}},\n+{\"zlwgsfd\",\t VX(4, 0x309), VX_MASK,\tPPCLSP, 0,\t\t{RD_EVEN, EVUIMM_4, RA}},\n+{\"zlwwosdx\",\t VX(4, 0x30A), VX_MASK,\tPPCLSP, 0,\t\t{RD_EVEN, RA, RB}},\n+{\"zlwwosd\",\t VX(4, 0x30B), VX_MASK,\tPPCLSP, 0,\t\t{RD_EVEN, EVUIMM_4, RA}},\n+{\"zlwhsplatwdx\", VX(4, 0x30C), VX_MASK,\tPPCLSP, 0,\t\t{RD_EVEN, RA, RB}},\n+{\"zlwhsplatwd\",\t VX(4, 0x30D), VX_MASK,\tPPCLSP, 0,\t\t{RD_EVEN, EVUIMM_4, RA}},\n+{\"zlwhsplatdx\",\t VX(4, 0x30E), VX_MASK,\tPPCLSP, 0,\t\t{RD_EVEN, RA, RB}},\n+{\"zlwhsplatd\",\t VX(4, 0x30F), VX_MASK,\tPPCLSP, 0,\t\t{RD_EVEN, EVUIMM_4, RA}},\n+{\"zlwhgwsfdx\",\t VX(4, 0x310), VX_MASK,\tPPCLSP, 0,\t\t{RD_EVEN, RA, RB}},\n+{\"zlwhgwsfd\",\t VX(4, 0x311), VX_MASK,\tPPCLSP, 0,\t\t{RD_EVEN, EVUIMM_4, RA}},\n+{\"zlwhedx\",\t VX(4, 0x312), VX_MASK,\tPPCLSP, 0,\t\t{RD_EVEN, RA, RB}},\n+{\"zlwhed\",\t VX(4, 0x313), VX_MASK,\tPPCLSP, 0,\t\t{RD_EVEN, EVUIMM_4, RA}},\n+{\"zlwhosdx\",\t VX(4, 0x314), VX_MASK,\tPPCLSP, 0,\t\t{RD_EVEN, RA, RB}},\n+{\"zlwhosd\",\t VX(4, 0x315), VX_MASK,\tPPCLSP, 0,\t\t{RD_EVEN, EVUIMM_4, RA}},\n+{\"zlwhoudx\",\t VX(4, 0x316), VX_MASK,\tPPCLSP, 0,\t\t{RD_EVEN, RA, RB}},\n+{\"zlwhoud\",\t VX(4, 0x317), VX_MASK,\tPPCLSP, 0,\t\t{RD_EVEN, EVUIMM_4, RA}},\n+{\"zlwhx\",\t VX(4, 0x318), VX_MASK,\tPPCLSP, 0,\t\t{RD, RA, RB}},\n+{\"zlwh\",\t VX(4, 0x319), VX_MASK,\tPPCLSP, 0,\t\t{RD, EVUIMM_4, RA}},\n+{\"zlwwx\",\t VX(4, 0x31A), VX_MASK,\tPPCLSP, 0,\t\t{RD, RA, RB}},\n+{\"zlww\",\t VX(4, 0x31B), VX_MASK,\tPPCLSP, 0,\t\t{RD, EVUIMM_4, RA}},\n+{\"zlhgwsfx\",\t VX(4, 0x31C), VX_MASK,\tPPCLSP, 0,\t\t{RD, RA, RB}},\n+{\"zlhgwsf\",\t VX(4, 0x31D), VX_MASK,\tPPCLSP, 0,\t\t{RD, EVUIMM_2, RA}},\n+{\"zlhhsplatx\",\t VX(4, 0x31E), VX_MASK,\tPPCLSP, 0,\t\t{RD, RA, RB}},\n+{\"zlhhsplat\",\t VX(4, 0x31F), VX_MASK,\tPPCLSP, 0,\t\t{RD, EVUIMM_2, RA}},\n+{\"zstddx\",\t VX(4, 0x320), VX_MASK,\tPPCLSP, 0,\t\t{RS_EVEN, RA, RB}},\n+{\"zstdd\",\t VX(4, 0x321), VX_MASK,\tPPCLSP, 0,\t\t{RS_EVEN, EVUIMM_8, RA}},\n+{\"zstdwx\",\t VX(4, 0x322), VX_MASK,\tPPCLSP, 0,\t\t{RS_EVEN, RA, RB}},\n+{\"zstdw\",\t VX(4, 0x323), VX_MASK,\tPPCLSP, 0,\t\t{RS_EVEN, EVUIMM_8, RA}},\n+{\"zstdhx\",\t VX(4, 0x324), VX_MASK,\tPPCLSP, 0,\t\t{RS_EVEN, RA, RB}},\n+{\"zstdh\",\t VX(4, 0x325), VX_MASK,\tPPCLSP, 0,\t\t{RS_EVEN, EVUIMM_8, RA}},\n+{\"zstwhedx\",\t VX(4, 0x328), VX_MASK,\tPPCLSP, 0,\t\t{RS_EVEN, RA, RB}},\n+{\"zstwhed\",\t VX(4, 0x329), VX_MASK,\tPPCLSP, 0,\t\t{RS_EVEN, EVUIMM_4, RA}},\n+{\"zstwhodx\",\t VX(4, 0x32A), VX_MASK,\tPPCLSP, 0,\t\t{RS_EVEN, RA, RB}},\n+{\"zstwhod\",\t VX(4, 0x32B), VX_MASK,\tPPCLSP, 0,\t\t{RS_EVEN, EVUIMM_4, RA}},\n+{\"zlhhex\",\t VX(4, 0x330), VX_MASK,\tPPCLSP, 0,\t\t{RD, RA, RB}},\n+{\"zlhhe\",\t VX(4, 0x331), VX_MASK,\tPPCLSP, 0,\t\t{RD, EVUIMM_2, RA}},\n+{\"zlhhosx\",\t VX(4, 0x332), VX_MASK,\tPPCLSP, 0,\t\t{RD, RA, RB}},\n+{\"zlhhos\",\t VX(4, 0x333), VX_MASK,\tPPCLSP, 0,\t\t{RD, EVUIMM_2, RA}},\n+{\"zlhhoux\",\t VX(4, 0x334), VX_MASK,\tPPCLSP, 0,\t\t{RD, RA, RB}},\n+{\"zlhhou\",\t VX(4, 0x335), VX_MASK,\tPPCLSP, 0,\t\t{RD, EVUIMM_2, RA}},\n+{\"zsthex\",\t VX(4, 0x338), VX_MASK,\tPPCLSP, 0,\t\t{RS, RA, RB}},\n+{\"zsthe\",\t VX(4, 0x339), VX_MASK,\tPPCLSP, 0,\t\t{RS, EVUIMM_2, RA}},\n+{\"zsthox\",\t VX(4, 0x33A), VX_MASK,\tPPCLSP, 0,\t\t{RS, RA, RB}},\n+{\"zstho\",\t VX(4, 0x33B), VX_MASK,\tPPCLSP, 0,\t\t{RS, EVUIMM_2, RA}},\n+{\"zstwhx\",\t VX(4, 0x33C), VX_MASK,\tPPCLSP, 0,\t\t{RS, RA, RB}},\n+{\"zstwh\",\t VX(4, 0x33D), VX_MASK,\tPPCLSP, 0,\t\t{RS, EVUIMM_4, RA}},\n+{\"zstwwx\",\t VX(4, 0x33E), VX_MASK,\tPPCLSP, 0,\t\t{RS, RA, RB}},\n+{\"zstww\",\t VX(4, 0x33F), VX_MASK,\tPPCLSP, 0,\t\t{RS, EVUIMM_4, RA}},\n+{\"zlddmx\",\t VX(4, 0x340), VX_MASK,\tPPCLSP, 0,\t\t{RD_EVEN, RA, RB}},\n+{\"zlddu\",\t VX(4, 0x341), VX_MASK,\tPPCLSP, 0,\t\t{RD_EVEN, EVUIMM_8_EX0, RA}},\n+{\"zldwmx\",\t VX(4, 0x342), VX_MASK,\tPPCLSP, 0,\t\t{RD_EVEN, RA, RB}},\n+{\"zldwu\",\t VX(4, 0x343), VX_MASK,\tPPCLSP, 0,\t\t{RD_EVEN, EVUIMM_8_EX0, RA}},\n+{\"zldhmx\",\t VX(4, 0x344), VX_MASK,\tPPCLSP, 0,\t\t{RD_EVEN, RA, RB}},\n+{\"zldhu\",\t VX(4, 0x345), VX_MASK,\tPPCLSP, 0,\t\t{RD_EVEN, EVUIMM_8_EX0, RA}},\n+{\"zlwgsfdmx\",\t VX(4, 0x348), VX_MASK,\tPPCLSP, 0,\t\t{RD_EVEN, RA, RB}},\n+{\"zlwgsfdu\",\t VX(4, 0x349), VX_MASK,\tPPCLSP, 0,\t\t{RD_EVEN, EVUIMM_4_EX0, RA}},\n+{\"zlwwosdmx\",\t VX(4, 0x34A), VX_MASK,\tPPCLSP, 0,\t\t{RD_EVEN, RA, RB}},\n+{\"zlwwosdu\",\t VX(4, 0x34B), VX_MASK,\tPPCLSP, 0,\t\t{RD_EVEN, EVUIMM_4_EX0, RA}},\n+{\"zlwhsplatwdmx\", VX(4, 0x34C), VX_MASK,\tPPCLSP, 0,\t\t{RD_EVEN, RA, RB}},\n+{\"zlwhsplatwdu\", VX(4, 0x34D), VX_MASK,\tPPCLSP, 0,\t\t{RD_EVEN, EVUIMM_4_EX0, RA}},\n+{\"zlwhsplatdmx\", VX(4, 0x34E), VX_MASK,\tPPCLSP, 0,\t\t{RD_EVEN, RA, RB}},\n+{\"zlwhsplatdu\",\t VX(4, 0x34F), VX_MASK,\tPPCLSP, 0,\t\t{RD_EVEN, EVUIMM_4_EX0, RA}},\n+{\"zlwhgwsfdmx\",\t VX(4, 0x350), VX_MASK,\tPPCLSP, 0,\t\t{RD_EVEN, RA, RB}},\n+{\"zlwhgwsfdu\",\t VX(4, 0x351), VX_MASK,\tPPCLSP, 0,\t\t{RD_EVEN, EVUIMM_4_EX0, RA}},\n+{\"zlwhedmx\",\t VX(4, 0x352), VX_MASK,\tPPCLSP, 0,\t\t{RD_EVEN, RA, RB}},\n+{\"zlwhedu\",\t VX(4, 0x353), VX_MASK,\tPPCLSP, 0,\t\t{RD_EVEN, EVUIMM_4_EX0, RA}},\n+{\"zlwhosdmx\",\t VX(4, 0x354), VX_MASK,\tPPCLSP, 0,\t\t{RD_EVEN, RA, RB}},\n+{\"zlwhosdu\",\t VX(4, 0x355), VX_MASK,\tPPCLSP, 0,\t\t{RD_EVEN, EVUIMM_4_EX0, RA}},\n+{\"zlwhoudmx\",\t VX(4, 0x356), VX_MASK,\tPPCLSP, 0,\t\t{RD_EVEN, RA, RB}},\n+{\"zlwhoudu\",\t VX(4, 0x357), VX_MASK,\tPPCLSP, 0,\t\t{RD_EVEN, EVUIMM_4_EX0, RA}},\n+{\"zlwhmx\",\t VX(4, 0x358), VX_MASK,\tPPCLSP, 0,\t\t{RD, RA, RB}},\n+{\"zlwhu\",\t VX(4, 0x359), VX_MASK,\tPPCLSP, 0,\t\t{RD, EVUIMM_4_EX0, RA}},\n+{\"zlwwmx\",\t VX(4, 0x35A), VX_MASK,\tPPCLSP, 0,\t\t{RD, RA, RB}},\n+{\"zlwwu\",\t VX(4, 0x35B), VX_MASK,\tPPCLSP, 0,\t\t{RD, EVUIMM_4_EX0, RA}},\n+{\"zlhgwsfmx\",\t VX(4, 0x35C), VX_MASK,\tPPCLSP, 0,\t\t{RD, RA, RB}},\n+{\"zlhgwsfu\",\t VX(4, 0x35D), VX_MASK,\tPPCLSP, 0,\t\t{RD, EVUIMM_2_EX0, RA}},\n+{\"zlhhsplatmx\",\t VX(4, 0x35E), VX_MASK,\tPPCLSP, 0,\t\t{RD, RA, RB}},\n+{\"zlhhsplatu\",\t VX(4, 0x35F), VX_MASK,\tPPCLSP, 0,\t\t{RD, EVUIMM_2_EX0, RA}},\n+{\"zstddmx\",\t VX(4, 0x360), VX_MASK,\tPPCLSP, 0,\t\t{RS_EVEN, RA, RB}},\n+{\"zstddu\",\t VX(4, 0x361), VX_MASK,\tPPCLSP, 0,\t\t{RS, EVUIMM_8_EX0, RA}},\n+{\"zstdwmx\",\t VX(4, 0x362), VX_MASK,\tPPCLSP, 0,\t\t{RS_EVEN, RA, RB}},\n+{\"zstdwu\",\t VX(4, 0x363), VX_MASK,\tPPCLSP, 0,\t\t{RS_EVEN, EVUIMM_8_EX0, RA}},\n+{\"zstdhmx\",\t VX(4, 0x364), VX_MASK,\tPPCLSP, 0,\t\t{RS_EVEN, RA, RB}},\n+{\"zstdhu\",\t VX(4, 0x365), VX_MASK,\tPPCLSP, 0,\t\t{RS_EVEN, EVUIMM_8_EX0, RA}},\n+{\"zstwhedmx\",\t VX(4, 0x368), VX_MASK,\tPPCLSP, 0,\t\t{RS_EVEN, RA, RB}},\n+{\"zstwhedu\",\t VX(4, 0x369), VX_MASK,\tPPCLSP, 0,\t\t{RS_EVEN, EVUIMM_4_EX0, RA}},\n+{\"zstwhodmx\",\t VX(4, 0x36A), VX_MASK,\tPPCLSP, 0,\t\t{RS_EVEN, RA, RB}},\n+{\"zstwhodu\",\t VX(4, 0x36B), VX_MASK,\tPPCLSP, 0,\t\t{RS_EVEN, EVUIMM_4_EX0, RA}},\n+{\"zlhhemx\",\t VX(4, 0x370), VX_MASK,\tPPCLSP, 0,\t\t{RD, RA, RB}},\n+{\"zlhheu\",\t VX(4, 0x371), VX_MASK,\tPPCLSP, 0,\t\t{RD, EVUIMM_2_EX0, RA}},\n+{\"zlhhosmx\",\t VX(4, 0x372), VX_MASK,\tPPCLSP, 0,\t\t{RD, RA, RB}},\n+{\"zlhhosu\",\t VX(4, 0x373), VX_MASK,\tPPCLSP, 0,\t\t{RD, EVUIMM_2_EX0, RA}},\n+{\"zlhhoumx\",\t VX(4, 0x374), VX_MASK,\tPPCLSP, 0,\t\t{RD, RA, RB}},\n+{\"zlhhouu\",\t VX(4, 0x375), VX_MASK,\tPPCLSP, 0,\t\t{RD, EVUIMM_2_EX0, RA}},\n+{\"zsthemx\",\t VX(4, 0x378), VX_MASK,\tPPCLSP, 0,\t\t{RS, RA, RB}},\n+{\"zstheu\",\t VX(4, 0x379), VX_MASK,\tPPCLSP, 0,\t\t{RS, EVUIMM_2_EX0, RA}},\n+{\"zsthomx\",\t VX(4, 0x37A), VX_MASK,\tPPCLSP, 0,\t\t{RS, RA, RB}},\n+{\"zsthou\",\t VX(4, 0x37B), VX_MASK,\tPPCLSP, 0,\t\t{RS, EVUIMM_2_EX0, RA}},\n+{\"zstwhmx\",\t VX(4, 0x37C), VX_MASK,\tPPCLSP, 0,\t\t{RS, RA, RB}},\n+{\"zstwhu\",\t VX(4, 0x37D), VX_MASK,\tPPCLSP, 0,\t\t{RS, EVUIMM_4_EX0, RA}},\n+{\"zstwwmx\",\t VX(4, 0x37E), VX_MASK,\tPPCLSP, 0,\t\t{RS, RA, RB}},\n+{\"zstwwu\",\t VX(4, 0x37F), VX_MASK,\tPPCLSP, 0,\t\t{RS, EVUIMM_4_EX0, RA}},\n {\"zaddwgui\",\t VX(4, 0x460), VX_MASK,\tPPCLSP, 0,\t\t{RD_EVEN, RA, RB}},\n {\"zsubfwgui\",\t VX(4, 0x461), VX_MASK,\tPPCLSP, 0,\t\t{RD_EVEN, RA, RB}},\n {\"zaddd\",\t VX(4, 0x462), VX_MASK,\tPPCLSP, 0,\t\t{RD_EVEN, RA, RB}},\n@@ -10272,332 +10596,9 @@ const struct powerpc_opcode vle_opcodes[] = {\n {\"zmwsfraas\",\t VX(4, 0x6FB), VX_MASK,\tPPCLSP, 0,\t\t{RD, RA, RB}},\n {\"zmwsfans\",\t VX(4, 0x6FC), VX_MASK,\tPPCLSP, 0,\t\t{RD, RA, RB}},\n {\"zmwsfrans\",\t VX(4, 0x6FD), VX_MASK,\tPPCLSP, 0,\t\t{RD, RA, RB}},\n-{\"zlddx\",\t VX(4, 0x300), VX_MASK,\tPPCLSP, 0,\t\t{RD_EVEN, RA, RB}},\n-{\"zldd\",\t VX(4, 0x301), VX_MASK,\tPPCLSP, 0,\t\t{RD_EVEN, EVUIMM_8, RA}},\n-{\"zldwx\",\t VX(4, 0x302), VX_MASK,\tPPCLSP, 0,\t\t{RD_EVEN, RA, RB}},\n-{\"zldw\",\t VX(4, 0x303), VX_MASK,\tPPCLSP, 0,\t\t{RD_EVEN, EVUIMM_8, RA}},\n-{\"zldhx\",\t VX(4, 0x304), VX_MASK,\tPPCLSP, 0,\t\t{RD_EVEN, RA, RB}},\n-{\"zldh\",\t VX(4, 0x305), VX_MASK,\tPPCLSP, 0,\t\t{RD_EVEN, EVUIMM_8, RA}},\n-{\"zlwgsfdx\",\t VX(4, 0x308), VX_MASK,\tPPCLSP, 0,\t\t{RD_EVEN, RA, RB}},\n-{\"zlwgsfd\",\t VX(4, 0x309), VX_MASK,\tPPCLSP, 0,\t\t{RD_EVEN, EVUIMM_4, RA}},\n-{\"zlwwosdx\",\t VX(4, 0x30A), VX_MASK,\tPPCLSP, 0,\t\t{RD_EVEN, RA, RB}},\n-{\"zlwwosd\",\t VX(4, 0x30B), VX_MASK,\tPPCLSP, 0,\t\t{RD_EVEN, EVUIMM_4, RA}},\n-{\"zlwhsplatwdx\", VX(4, 0x30C), VX_MASK,\tPPCLSP, 0,\t\t{RD_EVEN, RA, RB}},\n-{\"zlwhsplatwd\",\t VX(4, 0x30D), VX_MASK,\tPPCLSP, 0,\t\t{RD_EVEN, EVUIMM_4, RA}},\n-{\"zlwhsplatdx\",\t VX(4, 0x30E), VX_MASK,\tPPCLSP, 0,\t\t{RD_EVEN, RA, RB}},\n-{\"zlwhsplatd\",\t VX(4, 0x30F), VX_MASK,\tPPCLSP, 0,\t\t{RD_EVEN, EVUIMM_4, RA}},\n-{\"zlwhgwsfdx\",\t VX(4, 0x310), VX_MASK,\tPPCLSP, 0,\t\t{RD_EVEN, RA, RB}},\n-{\"zlwhgwsfd\",\t VX(4, 0x311), VX_MASK,\tPPCLSP, 0,\t\t{RD_EVEN, EVUIMM_4, RA}},\n-{\"zlwhedx\",\t VX(4, 0x312), VX_MASK,\tPPCLSP, 0,\t\t{RD_EVEN, RA, RB}},\n-{\"zlwhed\",\t VX(4, 0x313), VX_MASK,\tPPCLSP, 0,\t\t{RD_EVEN, EVUIMM_4, RA}},\n-{\"zlwhosdx\",\t VX(4, 0x314), VX_MASK,\tPPCLSP, 0,\t\t{RD_EVEN, RA, RB}},\n-{\"zlwhosd\",\t VX(4, 0x315), VX_MASK,\tPPCLSP, 0,\t\t{RD_EVEN, EVUIMM_4, RA}},\n-{\"zlwhoudx\",\t VX(4, 0x316), VX_MASK,\tPPCLSP, 0,\t\t{RD_EVEN, RA, RB}},\n-{\"zlwhoud\",\t VX(4, 0x317), VX_MASK,\tPPCLSP, 0,\t\t{RD_EVEN, EVUIMM_4, RA}},\n-{\"zlwhx\",\t VX(4, 0x318), VX_MASK,\tPPCLSP, 0,\t\t{RD, RA, RB}},\n-{\"zlwh\",\t VX(4, 0x319), VX_MASK,\tPPCLSP, 0,\t\t{RD, EVUIMM_4, RA}},\n-{\"zlwwx\",\t VX(4, 0x31A), VX_MASK,\tPPCLSP, 0,\t\t{RD, RA, RB}},\n-{\"zlww\",\t VX(4, 0x31B), VX_MASK,\tPPCLSP, 0,\t\t{RD, EVUIMM_4, RA}},\n-{\"zlhgwsfx\",\t VX(4, 0x31C), VX_MASK,\tPPCLSP, 0,\t\t{RD, RA, RB}},\n-{\"zlhgwsf\",\t VX(4, 0x31D), VX_MASK,\tPPCLSP, 0,\t\t{RD, EVUIMM_2, RA}},\n-{\"zlhhsplatx\",\t VX(4, 0x31E), VX_MASK,\tPPCLSP, 0,\t\t{RD, RA, RB}},\n-{\"zlhhsplat\",\t VX(4, 0x31F), VX_MASK,\tPPCLSP, 0,\t\t{RD, EVUIMM_2, RA}},\n-{\"zstddx\",\t VX(4, 0x320), VX_MASK,\tPPCLSP, 0,\t\t{RS_EVEN, RA, RB}},\n-{\"zstdd\",\t VX(4, 0x321), VX_MASK,\tPPCLSP, 0,\t\t{RS_EVEN, EVUIMM_8, RA}},\n-{\"zstdwx\",\t VX(4, 0x322), VX_MASK,\tPPCLSP, 0,\t\t{RS_EVEN, RA, RB}},\n-{\"zstdw\",\t VX(4, 0x323), VX_MASK,\tPPCLSP, 0,\t\t{RS_EVEN, EVUIMM_8, RA}},\n-{\"zstdhx\",\t VX(4, 0x324), VX_MASK,\tPPCLSP, 0,\t\t{RS_EVEN, RA, RB}},\n-{\"zstdh\",\t VX(4, 0x325), VX_MASK,\tPPCLSP, 0,\t\t{RS_EVEN, EVUIMM_8, RA}},\n-{\"zstwhedx\",\t VX(4, 0x328), VX_MASK,\tPPCLSP, 0,\t\t{RS_EVEN, RA, RB}},\n-{\"zstwhed\",\t VX(4, 0x329), VX_MASK,\tPPCLSP, 0,\t\t{RS_EVEN, EVUIMM_4, RA}},\n-{\"zstwhodx\",\t VX(4, 0x32A), VX_MASK,\tPPCLSP, 0,\t\t{RS_EVEN, RA, RB}},\n-{\"zstwhod\",\t VX(4, 0x32B), VX_MASK,\tPPCLSP, 0,\t\t{RS_EVEN, EVUIMM_4, RA}},\n-{\"zlhhex\",\t VX(4, 0x330), VX_MASK,\tPPCLSP, 0,\t\t{RD, RA, RB}},\n-{\"zlhhe\",\t VX(4, 0x331), VX_MASK,\tPPCLSP, 0,\t\t{RD, EVUIMM_2, RA}},\n-{\"zlhhosx\",\t VX(4, 0x332), VX_MASK,\tPPCLSP, 0,\t\t{RD, RA, RB}},\n-{\"zlhhos\",\t VX(4, 0x333), VX_MASK,\tPPCLSP, 0,\t\t{RD, EVUIMM_2, RA}},\n-{\"zlhhoux\",\t VX(4, 0x334), VX_MASK,\tPPCLSP, 0,\t\t{RD, RA, RB}},\n-{\"zlhhou\",\t VX(4, 0x335), VX_MASK,\tPPCLSP, 0,\t\t{RD, EVUIMM_2, RA}},\n-{\"zsthex\",\t VX(4, 0x338), VX_MASK,\tPPCLSP, 0,\t\t{RS, RA, RB}},\n-{\"zsthe\",\t VX(4, 0x339), VX_MASK,\tPPCLSP, 0,\t\t{RS, EVUIMM_2, RA}},\n-{\"zsthox\",\t VX(4, 0x33A), VX_MASK,\tPPCLSP, 0,\t\t{RS, RA, RB}},\n-{\"zstho\",\t VX(4, 0x33B), VX_MASK,\tPPCLSP, 0,\t\t{RS, EVUIMM_2, RA}},\n-{\"zstwhx\",\t VX(4, 0x33C), VX_MASK,\tPPCLSP, 0,\t\t{RS, RA, RB}},\n-{\"zstwh\",\t VX(4, 0x33D), VX_MASK,\tPPCLSP, 0,\t\t{RS, EVUIMM_4, RA}},\n-{\"zstwwx\",\t VX(4, 0x33E), VX_MASK,\tPPCLSP, 0,\t\t{RS, RA, RB}},\n-{\"zstww\",\t VX(4, 0x33F), VX_MASK,\tPPCLSP, 0,\t\t{RS, EVUIMM_4, RA}},\n-{\"zlddmx\",\t VX(4, 0x340), VX_MASK,\tPPCLSP, 0,\t\t{RD_EVEN, RA, RB}},\n-{\"zlddu\",\t VX(4, 0x341), VX_MASK,\tPPCLSP, 0,\t\t{RD_EVEN, EVUIMM_8_EX0, RA}},\n-{\"zldwmx\",\t VX(4, 0x342), VX_MASK,\tPPCLSP, 0,\t\t{RD_EVEN, RA, RB}},\n-{\"zldwu\",\t VX(4, 0x343), VX_MASK,\tPPCLSP, 0,\t\t{RD_EVEN, EVUIMM_8_EX0, RA}},\n-{\"zldhmx\",\t VX(4, 0x344), VX_MASK,\tPPCLSP, 0,\t\t{RD_EVEN, RA, RB}},\n-{\"zldhu\",\t VX(4, 0x345), VX_MASK,\tPPCLSP, 0,\t\t{RD_EVEN, EVUIMM_8_EX0, RA}},\n-{\"zlwgsfdmx\",\t VX(4, 0x348), VX_MASK,\tPPCLSP, 0,\t\t{RD_EVEN, RA, RB}},\n-{\"zlwgsfdu\",\t VX(4, 0x349), VX_MASK,\tPPCLSP, 0,\t\t{RD_EVEN, EVUIMM_4_EX0, RA}},\n-{\"zlwwosdmx\",\t VX(4, 0x34A), VX_MASK,\tPPCLSP, 0,\t\t{RD_EVEN, RA, RB}},\n-{\"zlwwosdu\",\t VX(4, 0x34B), VX_MASK,\tPPCLSP, 0,\t\t{RD_EVEN, EVUIMM_4_EX0, RA}},\n-{\"zlwhsplatwdmx\", VX(4, 0x34C), VX_MASK,\tPPCLSP, 0,\t\t{RD_EVEN, RA, RB}},\n-{\"zlwhsplatwdu\", VX(4, 0x34D), VX_MASK,\tPPCLSP, 0,\t\t{RD_EVEN, EVUIMM_4_EX0, RA}},\n-{\"zlwhsplatdmx\", VX(4, 0x34E), VX_MASK,\tPPCLSP, 0,\t\t{RD_EVEN, RA, RB}},\n-{\"zlwhsplatdu\",\t VX(4, 0x34F), VX_MASK,\tPPCLSP, 0,\t\t{RD_EVEN, EVUIMM_4_EX0, RA}},\n-{\"zlwhgwsfdmx\",\t VX(4, 0x350), VX_MASK,\tPPCLSP, 0,\t\t{RD_EVEN, RA, RB}},\n-{\"zlwhgwsfdu\",\t VX(4, 0x351), VX_MASK,\tPPCLSP, 0,\t\t{RD_EVEN, EVUIMM_4_EX0, RA}},\n-{\"zlwhedmx\",\t VX(4, 0x352), VX_MASK,\tPPCLSP, 0,\t\t{RD_EVEN, RA, RB}},\n-{\"zlwhedu\",\t VX(4, 0x353), VX_MASK,\tPPCLSP, 0,\t\t{RD_EVEN, EVUIMM_4_EX0, RA}},\n-{\"zlwhosdmx\",\t VX(4, 0x354), VX_MASK,\tPPCLSP, 0,\t\t{RD_EVEN, RA, RB}},\n-{\"zlwhosdu\",\t VX(4, 0x355), VX_MASK,\tPPCLSP, 0,\t\t{RD_EVEN, EVUIMM_4_EX0, RA}},\n-{\"zlwhoudmx\",\t VX(4, 0x356), VX_MASK,\tPPCLSP, 0,\t\t{RD_EVEN, RA, RB}},\n-{\"zlwhoudu\",\t VX(4, 0x357), VX_MASK,\tPPCLSP, 0,\t\t{RD_EVEN, EVUIMM_4_EX0, RA}},\n-{\"zlwhmx\",\t VX(4, 0x358), VX_MASK,\tPPCLSP, 0,\t\t{RD, RA, RB}},\n-{\"zlwhu\",\t VX(4, 0x359), VX_MASK,\tPPCLSP, 0,\t\t{RD, EVUIMM_4_EX0, RA}},\n-{\"zlwwmx\",\t VX(4, 0x35A), VX_MASK,\tPPCLSP, 0,\t\t{RD, RA, RB}},\n-{\"zlwwu\",\t VX(4, 0x35B), VX_MASK,\tPPCLSP, 0,\t\t{RD, EVUIMM_4_EX0, RA}},\n-{\"zlhgwsfmx\",\t VX(4, 0x35C), VX_MASK,\tPPCLSP, 0,\t\t{RD, RA, RB}},\n-{\"zlhgwsfu\",\t VX(4, 0x35D), VX_MASK,\tPPCLSP, 0,\t\t{RD, EVUIMM_2_EX0, RA}},\n-{\"zlhhsplatmx\",\t VX(4, 0x35E), VX_MASK,\tPPCLSP, 0,\t\t{RD, RA, RB}},\n-{\"zlhhsplatu\",\t VX(4, 0x35F), VX_MASK,\tPPCLSP, 0,\t\t{RD, EVUIMM_2_EX0, RA}},\n-{\"zstddmx\",\t VX(4, 0x360), VX_MASK,\tPPCLSP, 0,\t\t{RS_EVEN, RA, RB}},\n-{\"zstddu\",\t VX(4, 0x361), VX_MASK,\tPPCLSP, 0,\t\t{RS, EVUIMM_8_EX0, RA}},\n-{\"zstdwmx\",\t VX(4, 0x362), VX_MASK,\tPPCLSP, 0,\t\t{RS_EVEN, RA, RB}},\n-{\"zstdwu\",\t VX(4, 0x363), VX_MASK,\tPPCLSP, 0,\t\t{RS_EVEN, EVUIMM_8_EX0, RA}},\n-{\"zstdhmx\",\t VX(4, 0x364), VX_MASK,\tPPCLSP, 0,\t\t{RS_EVEN, RA, RB}},\n-{\"zstdhu\",\t VX(4, 0x365), VX_MASK,\tPPCLSP, 0,\t\t{RS_EVEN, EVUIMM_8_EX0, RA}},\n-{\"zstwhedmx\",\t VX(4, 0x368), VX_MASK,\tPPCLSP, 0,\t\t{RS_EVEN, RA, RB}},\n-{\"zstwhedu\",\t VX(4, 0x369), VX_MASK,\tPPCLSP, 0,\t\t{RS_EVEN, EVUIMM_4_EX0, RA}},\n-{\"zstwhodmx\",\t VX(4, 0x36A), VX_MASK,\tPPCLSP, 0,\t\t{RS_EVEN, RA, RB}},\n-{\"zstwhodu\",\t VX(4, 0x36B), VX_MASK,\tPPCLSP, 0,\t\t{RS_EVEN, EVUIMM_4_EX0, RA}},\n-{\"zlhhemx\",\t VX(4, 0x370), VX_MASK,\tPPCLSP, 0,\t\t{RD, RA, RB}},\n-{\"zlhheu\",\t VX(4, 0x371), VX_MASK,\tPPCLSP, 0,\t\t{RD, EVUIMM_2_EX0, RA}},\n-{\"zlhhosmx\",\t VX(4, 0x372), VX_MASK,\tPPCLSP, 0,\t\t{RD, RA, RB}},\n-{\"zlhhosu\",\t VX(4, 0x373), VX_MASK,\tPPCLSP, 0,\t\t{RD, EVUIMM_2_EX0, RA}},\n-{\"zlhhoumx\",\t VX(4, 0x374), VX_MASK,\tPPCLSP, 0,\t\t{RD, RA, RB}},\n-{\"zlhhouu\",\t VX(4, 0x375), VX_MASK,\tPPCLSP, 0,\t\t{RD, EVUIMM_2_EX0, RA}},\n-{\"zsthemx\",\t VX(4, 0x378), VX_MASK,\tPPCLSP, 0,\t\t{RS, RA, RB}},\n-{\"zstheu\",\t VX(4, 0x379), VX_MASK,\tPPCLSP, 0,\t\t{RS, EVUIMM_2_EX0, RA}},\n-{\"zsthomx\",\t VX(4, 0x37A), VX_MASK,\tPPCLSP, 0,\t\t{RS, RA, RB}},\n-{\"zsthou\",\t VX(4, 0x37B), VX_MASK,\tPPCLSP, 0,\t\t{RS, EVUIMM_2_EX0, RA}},\n-{\"zstwhmx\",\t VX(4, 0x37C), VX_MASK,\tPPCLSP, 0,\t\t{RS, RA, RB}},\n-{\"zstwhu\",\t VX(4, 0x37D), VX_MASK,\tPPCLSP, 0,\t\t{RS, EVUIMM_4_EX0, RA}},\n-{\"zstwwmx\",\t VX(4, 0x37E), VX_MASK,\tPPCLSP, 0,\t\t{RS, RA, RB}},\n-{\"zstwwu\",\t VX(4, 0x37F), VX_MASK,\tPPCLSP, 0,\t\t{RS, EVUIMM_4_EX0, RA}},\n-\n-{\"e_cmpi\",\tSCI8BF(6,0,21),\tSCI8BF_MASK,\tPPCVLE,\t0,\t\t{CRD32, RA, SCLSCI8}},\n-{\"e_cmpwi\",\tSCI8BF(6,0,21),\tSCI8BF_MASK,\tPPCVLE,\t0,\t\t{CRD32, RA, SCLSCI8}},\n-{\"e_cmpli\",\tSCI8BF(6,1,21),\tSCI8BF_MASK,\tPPCVLE,\t0,\t\t{CRD32, RA, SCLSCI8}},\n-{\"e_cmplwi\",\tSCI8BF(6,1,21),\tSCI8BF_MASK,\tPPCVLE,\t0,\t\t{CRD32, RA, SCLSCI8}},\n-{\"e_addi\",\tSCI8(6,16),\tSCI8_MASK,\tPPCVLE,\t0,\t\t{RT, RA, SCLSCI8}},\n-{\"e_subi\",\tSCI8(6,16),\tSCI8_MASK,\tPPCVLE,\t0,\t\t{RT, RA, SCLSCI8N}},\n-{\"e_addi.\",\tSCI8(6,17),\tSCI8_MASK,\tPPCVLE,\t0,\t\t{RT, RA, SCLSCI8}},\n-{\"e_addic\",\tSCI8(6,18),\tSCI8_MASK,\tPPCVLE,\t0,\t\t{RT, RA, SCLSCI8}},\n-{\"e_subic\",\tSCI8(6,18),\tSCI8_MASK,\tPPCVLE,\tEXT,\t\t{RT, RA, SCLSCI8N}},\n-{\"e_addic.\",\tSCI8(6,19),\tSCI8_MASK,\tPPCVLE,\t0,\t\t{RT, RA, SCLSCI8}},\n-{\"e_subic.\",\tSCI8(6,19),\tSCI8_MASK,\tPPCVLE,\tEXT,\t\t{RT, RA, SCLSCI8N}},\n-{\"e_mulli\",\tSCI8(6,20),\tSCI8_MASK,\tPPCVLE,\t0,\t\t{RT, RA, SCLSCI8}},\n-{\"e_subfic\",\tSCI8(6,22),\tSCI8_MASK,\tPPCVLE,\t0,\t\t{RT, RA, SCLSCI8}},\n-{\"e_subfic.\",\tSCI8(6,23),\tSCI8_MASK,\tPPCVLE,\t0,\t\t{RT, RA, SCLSCI8}},\n-{\"e_andi\",\tSCI8(6,24),\tSCI8_MASK,\tPPCVLE,\t0,\t\t{RA, RS, SCLSCI8}},\n-{\"e_andi.\",\tSCI8(6,25),\tSCI8_MASK,\tPPCVLE,\t0,\t\t{RA, RS, SCLSCI8}},\n-{\"e_nop\",\tSCI8(6,26),\t0xffffffff,\tPPCVLE,\tEXT,\t\t{0}},\n-{\"e_ori\",\tSCI8(6,26),\tSCI8_MASK,\tPPCVLE,\t0,\t\t{RA, RS, SCLSCI8}},\n-{\"e_ori.\",\tSCI8(6,27),\tSCI8_MASK,\tPPCVLE,\t0,\t\t{RA, RS, SCLSCI8}},\n-{\"e_xori\",\tSCI8(6,28),\tSCI8_MASK,\tPPCVLE,\t0,\t\t{RA, RS, SCLSCI8}},\n-{\"e_xori.\",\tSCI8(6,29),\tSCI8_MASK,\tPPCVLE,\t0,\t\t{RA, RS, SCLSCI8}},\n-{\"e_lbzu\",\tOPVUP(6,0),\tOPVUP_MASK,\tPPCVLE,\t0,\t\t{RT, D8, RA0}},\n-{\"e_lhau\",\tOPVUP(6,3),\tOPVUP_MASK,\tPPCVLE,\t0,\t\t{RT, D8, RA0}},\n-{\"e_lhzu\",\tOPVUP(6,1),\tOPVUP_MASK,\tPPCVLE,\t0,\t\t{RT, D8, RA0}},\n-{\"e_lmw\",\tOPVUP(6,8),\tOPVUP_MASK,\tPPCVLE,\t0,\t\t{RT, D8, RA0}},\n-{\"e_lwzu\",\tOPVUP(6,2),\tOPVUP_MASK,\tPPCVLE,\t0,\t\t{RT, D8, RA0}},\n-{\"e_stbu\",\tOPVUP(6,4),\tOPVUP_MASK,\tPPCVLE,\t0,\t\t{RT, D8, RA0}},\n-{\"e_sthu\",\tOPVUP(6,5),\tOPVUP_MASK,\tPPCVLE,\t0,\t\t{RT, D8, RA0}},\n-{\"e_stwu\",\tOPVUP(6,6),\tOPVUP_MASK,\tPPCVLE,\t0,\t\t{RT, D8, RA0}},\n-{\"e_stmw\",\tOPVUP(6,9),\tOPVUP_MASK,\tPPCVLE,\t0,\t\t{RT, D8, RA0}},\n-{\"e_lmvgprw\",\tOPVUPRT(6,16,0),OPVUPRT_MASK,\tPPCVLE,\t0,\t\t{D8, RA0}},\n-{\"e_ldmvgprw\",\tOPVUPRT(6,16,0),OPVUPRT_MASK,\tPPCVLE,\t0,\t\t{D8, RA0}},\n-{\"e_stmvgprw\",\tOPVUPRT(6,17,0),OPVUPRT_MASK,\tPPCVLE,\t0,\t\t{D8, RA0}},\n-{\"e_lmvsprw\",\tOPVUPRT(6,16,1),OPVUPRT_MASK,\tPPCVLE,\t0,\t\t{D8, RA0}},\n-{\"e_ldmvsprw\",\tOPVUPRT(6,16,1),OPVUPRT_MASK,\tPPCVLE,\t0,\t\t{D8, RA0}},\n-{\"e_stmvsprw\",\tOPVUPRT(6,17,1),OPVUPRT_MASK,\tPPCVLE,\t0,\t\t{D8, RA0}},\n-{\"e_lmvsrrw\",\tOPVUPRT(6,16,4),OPVUPRT_MASK,\tPPCVLE,\t0,\t\t{D8, RA0}},\n-{\"e_ldmvsrrw\",\tOPVUPRT(6,16,4),OPVUPRT_MASK,\tPPCVLE,\t0,\t\t{D8, RA0}},\n-{\"e_stmvsrrw\",\tOPVUPRT(6,17,4),OPVUPRT_MASK,\tPPCVLE,\t0,\t\t{D8, RA0}},\n-{\"e_lmvcsrrw\",\tOPVUPRT(6,16,5),OPVUPRT_MASK,\tPPCVLE,\t0,\t\t{D8, RA0}},\n-{\"e_ldmvcsrrw\",\tOPVUPRT(6,16,5),OPVUPRT_MASK,\tPPCVLE,\t0,\t\t{D8, RA0}},\n-{\"e_stmvcsrrw\",\tOPVUPRT(6,17,5),OPVUPRT_MASK,\tPPCVLE,\t0,\t\t{D8, RA0}},\n-{\"e_lmvdsrrw\",\tOPVUPRT(6,16,6),OPVUPRT_MASK,\tPPCVLE,\t0,\t\t{D8, RA0}},\n-{\"e_ldmvdsrrw\",\tOPVUPRT(6,16,6),OPVUPRT_MASK,\tPPCVLE,\t0,\t\t{D8, RA0}},\n-{\"e_stmvdsrrw\",\tOPVUPRT(6,17,6),OPVUPRT_MASK,\tPPCVLE,\t0,\t\t{D8, RA0}},\n-{\"e_lmvmcsrrw\",\tOPVUPRT(6,16,7),OPVUPRT_MASK,\tPPCVLE,\t0,\t\t{D8, RA0}},\n-{\"e_stmvmcsrrw\",\tOPVUPRT(6,17,7),OPVUPRT_MASK,\tPPCVLE,\t0,\t\t{D8, RA0}},\n-{\"e_add16i\",\tOP(7),\t\tOP_MASK,\tPPCVLE,\t0,\t\t{RT, RA, SI}},\n-{\"e_la\",\tOP(7),\t\tOP_MASK,\tPPCVLE,\tEXT,\t\t{RT, D, RA0}},\n-{\"e_sub16i\",\tOP(7),\t\tOP_MASK,\tPPCVLE,\tEXT,\t\t{RT, RA, NSI}},\n-\n-{\"se_addi\",\tSE_IM5(8,0),\tSE_IM5_MASK,\tPPCVLE,\t0,\t\t{RX, OIMM5}},\n-{\"se_cmpli\",\tSE_IM5(8,1),\tSE_IM5_MASK,\tPPCVLE,\t0,\t\t{RX, OIMM5}},\n-{\"se_subi\",\tSE_IM5(9,0),\tSE_IM5_MASK,\tPPCVLE,\t0,\t\t{RX, OIMM5}},\n-{\"se_subi.\",\tSE_IM5(9,1),\tSE_IM5_MASK,\tPPCVLE,\t0,\t\t{RX, OIMM5}},\n-{\"se_cmpi\",\tSE_IM5(10,1),\tSE_IM5_MASK,\tPPCVLE,\t0,\t\t{RX, UI5}},\n-{\"se_bmaski\",\tSE_IM5(11,0),\tSE_IM5_MASK,\tPPCVLE,\t0,\t\t{RX, UI5}},\n-{\"se_andi\",\tSE_IM5(11,1),\tSE_IM5_MASK,\tPPCVLE,\t0,\t\t{RX, UI5}},\n-\n-{\"e_lbz\",\tOP(12),\t\tOP_MASK,\tPPCVLE,\t0,\t\t{RT, D, RA0}},\n-{\"e_stb\",\tOP(13),\t\tOP_MASK,\tPPCVLE,\t0,\t\t{RT, D, RA0}},\n-{\"e_lha\",\tOP(14),\t\tOP_MASK,\tPPCVLE,\t0,\t\t{RT, D, RA0}},\n-\n-{\"se_srw\",\tSE_RR(16,0),\tSE_RR_MASK,\tPPCVLE,\t0,\t\t{RX, RY}},\n-{\"se_sraw\",\tSE_RR(16,1),\tSE_RR_MASK,\tPPCVLE,\t0,\t\t{RX, RY}},\n-{\"se_slw\",\tSE_RR(16,2),\tSE_RR_MASK,\tPPCVLE,\t0,\t\t{RX, RY}},\n-{\"se_nop\",\tSE_RR(17,0),\t0xffff,\t\tPPCVLE,\tEXT,\t\t{0}},\n-{\"se_or\",\tSE_RR(17,0),\tSE_RR_MASK,\tPPCVLE,\t0,\t\t{RX, RY}},\n-{\"se_andc\",\tSE_RR(17,1),\tSE_RR_MASK,\tPPCVLE,\t0,\t\t{RX, RY}},\n-{\"se_and\",\tSE_RR(17,2),\tSE_RR_MASK,\tPPCVLE,\t0,\t\t{RX, RY}},\n-{\"se_and.\",\tSE_RR(17,3),\tSE_RR_MASK,\tPPCVLE,\t0,\t\t{RX, RY}},\n-{\"se_li\",\tIM7(9),\t\tIM7_MASK,\tPPCVLE,\t0,\t\t{RX, UI7}},\n-\n-{\"e_lwz\",\tOP(20),\t\tOP_MASK,\tPPCVLE,\t0,\t\t{RT, D, RA0}},\n-{\"e_stw\",\tOP(21),\t\tOP_MASK,\tPPCVLE,\t0,\t\t{RT, D, RA0}},\n-{\"e_lhz\",\tOP(22),\t\tOP_MASK,\tPPCVLE,\t0,\t\t{RT, D, RA0}},\n-{\"e_sth\",\tOP(23),\t\tOP_MASK,\tPPCVLE,\t0,\t\t{RT, D, RA0}},\n-\n-{\"se_bclri\",\tSE_IM5(24,0),\tSE_IM5_MASK,\tPPCVLE,\t0,\t\t{RX, UI5}},\n-{\"se_bgeni\",\tSE_IM5(24,1),\tSE_IM5_MASK,\tPPCVLE,\t0,\t\t{RX, UI5}},\n-{\"se_bseti\",\tSE_IM5(25,0),\tSE_IM5_MASK,\tPPCVLE,\t0,\t\t{RX, UI5}},\n-{\"se_btsti\",\tSE_IM5(25,1),\tSE_IM5_MASK,\tPPCVLE,\t0,\t\t{RX, UI5}},\n-{\"se_srwi\",\tSE_IM5(26,0),\tSE_IM5_MASK,\tPPCVLE,\t0,\t\t{RX, UI5}},\n-{\"se_srawi\",\tSE_IM5(26,1),\tSE_IM5_MASK,\tPPCVLE,\t0,\t\t{RX, UI5}},\n-{\"se_slwi\",\tSE_IM5(27,0),\tSE_IM5_MASK,\tPPCVLE,\t0,\t\t{RX, UI5}},\n-\n-{\"e_lis\",\tI16L(28,28),\tI16L_MASK,\tPPCVLE,\t0,\t\t{RD, VLEUIMML}},\n-{\"e_and2is.\",\tI16L(28,29),\tI16L_MASK,\tPPCVLE,\t0,\t\t{RD, VLEUIMML}},\n-{\"e_or2is\",\tI16L(28,26),\tI16L_MASK,\tPPCVLE,\t0,\t\t{RD, VLEUIMML}},\n-{\"e_and2i.\",\tI16L(28,25),\tI16L_MASK,\tPPCVLE,\t0,\t\t{RD, VLEUIMML}},\n-{\"e_or2i\",\tI16L(28,24),\tI16L_MASK,\tPPCVLE,\t0,\t\t{RD, VLEUIMML}},\n-{\"e_cmphl16i\",\tIA16(28,23),\tIA16_MASK,\tPPCVLE,\t0,\t\t{RA, VLEUIMM}},\n-{\"e_cmph16i\",\tIA16(28,22),\tIA16_MASK,\tPPCVLE,\t0,\t\t{RA, VLESIMM}},\n-{\"e_cmpl16i\",\tI16A(28,21),\tI16A_MASK,\tPPCVLE,\t0,\t\t{RA, VLEUIMM}},\n-{\"e_mull2i\",\tI16A(28,20),\tI16A_MASK,\tPPCVLE,\t0,\t\t{RA, VLESIMM}},\n-{\"e_cmp16i\",\tIA16(28,19),\tIA16_MASK,\tPPCVLE,\t0,\t\t{RA, VLESIMM}},\n-{\"e_sub2is\",\tI16A(28,18),\tI16A_MASK,\tPPCVLE,\tEXT,\t\t{RA, VLENSIMM}},\n-{\"e_add2is\",\tI16A(28,18),\tI16A_MASK,\tPPCVLE,\t0,\t\t{RA, VLESIMM}},\n-{\"e_sub2i.\",\tI16A(28,17),\tI16A_MASK,\tPPCVLE,\tEXT,\t\t{RA, VLENSIMM}},\n-{\"e_add2i.\",\tI16A(28,17),\tI16A_MASK,\tPPCVLE,\t0,\t\t{RA, VLESIMM}},\n-{\"e_li\",\tLI20(28,0),\tLI20_MASK,\tPPCVLE,\t0,\t\t{RT, IMM20}},\n-{\"e_rlwimi\",\tM(29,0),\tM_MASK,\t\tPPCVLE,\t0,\t\t{RA, RS, SH, MB, ME}},\n-{\"e_inslwi\",\tM(29,0),\tM_MASK,\t\tPPCVLE, EXT,\t\t{RA, RS, ILWn, ILWb}},\n-{\"e_insrwi\",\tM(29,0),\tM_MASK,\t\tPPCVLE, EXT,\t\t{RA, RS, IRWn, IRWb}},\n-{\"e_rotlwi\",\tMME(29,31,1),\tMMBME_MASK,\tPPCVLE, EXT,\t\t{RA, RS, SH}},\n-{\"e_rotrwi\",\tMME(29,31,1),\tMMBME_MASK,\tPPCVLE, EXT,\t\t{RA, RS, RRWn}},\n-{\"e_clrlwi\",\tMME(29,31,1),\tMSHME_MASK,\tPPCVLE, EXT,\t\t{RA, RS, MB}},\n-{\"e_clrrwi\",\tM(29,1),\tMSHMB_MASK,\tPPCVLE, EXT,\t\t{RA, RS, CRWn}},\n-{\"e_rlwinm\",\tM(29,1),\tM_MASK,\t\tPPCVLE,\t0,\t\t{RA, RS, SH, MBE, ME}},\n-{\"e_extlwi\",\tM(29,1),\tMMB_MASK,\tPPCVLE, EXT,\t\t{RA, RS, ELWn, SH}},\n-{\"e_extrwi\",\tMME(29,31,1),\tMME_MASK,\tPPCVLE, EXT,\t\t{RA, RS, ERWn, ERWb}},\n-{\"e_clrlslwi\",\tM(29,1),\tM_MASK,\t\tPPCVLE, EXT,\t\t{RA, RS, CSLWb, CSLWn}},\n-{\"e_b\",\t\tBD24(30,0,0),\tBD24_MASK,\tPPCVLE,\t0,\t\t{B24}},\n-{\"e_bl\",\tBD24(30,0,1),\tBD24_MASK,\tPPCVLE,\t0,\t\t{B24}},\n-{\"e_bdnz\",\tEBD15(30,8,BO32DNZ,0),\tEBD15_MASK, PPCVLE, EXT,\t{B15}},\n-{\"e_bdnzl\",\tEBD15(30,8,BO32DNZ,1),\tEBD15_MASK, PPCVLE, EXT,\t{B15}},\n-{\"e_bdz\",\tEBD15(30,8,BO32DZ,0),\tEBD15_MASK, PPCVLE, EXT,\t{B15}},\n-{\"e_bdzl\",\tEBD15(30,8,BO32DZ,1),\tEBD15_MASK, PPCVLE, EXT,\t{B15}},\n-{\"e_bge\",\tEBD15BI(30,8,BO32F,CBLT,0), EBD15BI_MASK, PPCVLE, EXT,\t{CRS,B15}},\n-{\"e_bgel\",\tEBD15BI(30,8,BO32F,CBLT,1), EBD15BI_MASK, PPCVLE, EXT,\t{CRS,B15}},\n-{\"e_bnl\",\tEBD15BI(30,8,BO32F,CBLT,0), EBD15BI_MASK, PPCVLE, EXT,\t{CRS,B15}},\n-{\"e_bnll\",\tEBD15BI(30,8,BO32F,CBLT,1), EBD15BI_MASK, PPCVLE, EXT,\t{CRS,B15}},\n-{\"e_blt\",\tEBD15BI(30,8,BO32T,CBLT,0), EBD15BI_MASK, PPCVLE, EXT,\t{CRS,B15}},\n-{\"e_bltl\",\tEBD15BI(30,8,BO32T,CBLT,1), EBD15BI_MASK, PPCVLE, EXT,\t{CRS,B15}},\n-{\"e_bgt\",\tEBD15BI(30,8,BO32T,CBGT,0), EBD15BI_MASK, PPCVLE, EXT,\t{CRS,B15}},\n-{\"e_bgtl\",\tEBD15BI(30,8,BO32T,CBGT,1), EBD15BI_MASK, PPCVLE, EXT,\t{CRS,B15}},\n-{\"e_ble\",\tEBD15BI(30,8,BO32F,CBGT,0), EBD15BI_MASK, PPCVLE, EXT,\t{CRS,B15}},\n-{\"e_blel\",\tEBD15BI(30,8,BO32F,CBGT,1), EBD15BI_MASK, PPCVLE, EXT,\t{CRS,B15}},\n-{\"e_bng\",\tEBD15BI(30,8,BO32F,CBGT,0), EBD15BI_MASK, PPCVLE, EXT,\t{CRS,B15}},\n-{\"e_bngl\",\tEBD15BI(30,8,BO32F,CBGT,1), EBD15BI_MASK, PPCVLE, EXT,\t{CRS,B15}},\n-{\"e_bne\",\tEBD15BI(30,8,BO32F,CBEQ,0), EBD15BI_MASK, PPCVLE, EXT,\t{CRS,B15}},\n-{\"e_bnel\",\tEBD15BI(30,8,BO32F,CBEQ,1), EBD15BI_MASK, PPCVLE, EXT,\t{CRS,B15}},\n-{\"e_beq\",\tEBD15BI(30,8,BO32T,CBEQ,0), EBD15BI_MASK, PPCVLE, EXT,\t{CRS,B15}},\n-{\"e_beql\",\tEBD15BI(30,8,BO32T,CBEQ,1), EBD15BI_MASK, PPCVLE, EXT,\t{CRS,B15}},\n-{\"e_bso\",\tEBD15BI(30,8,BO32T,CBSO,0), EBD15BI_MASK, PPCVLE, EXT,\t{CRS,B15}},\n-{\"e_bsol\",\tEBD15BI(30,8,BO32T,CBSO,1), EBD15BI_MASK, PPCVLE, EXT,\t{CRS,B15}},\n-{\"e_bun\",\tEBD15BI(30,8,BO32T,CBSO,0), EBD15BI_MASK, PPCVLE, EXT,\t{CRS,B15}},\n-{\"e_bunl\",\tEBD15BI(30,8,BO32T,CBSO,1), EBD15BI_MASK, PPCVLE, EXT,\t{CRS,B15}},\n-{\"e_bns\",\tEBD15BI(30,8,BO32F,CBSO,0), EBD15BI_MASK, PPCVLE, EXT,\t{CRS,B15}},\n-{\"e_bnsl\",\tEBD15BI(30,8,BO32F,CBSO,1), EBD15BI_MASK, PPCVLE, EXT,\t{CRS,B15}},\n-{\"e_bnu\",\tEBD15BI(30,8,BO32F,CBSO,0), EBD15BI_MASK, PPCVLE, EXT,\t{CRS,B15}},\n-{\"e_bnul\",\tEBD15BI(30,8,BO32F,CBSO,1), EBD15BI_MASK, PPCVLE, EXT,\t{CRS,B15}},\n-{\"e_bc\",\tBD15(30,8,0),\tBD15_MASK,\tPPCVLE,\t0,\t\t{BO32, BI32, B15}},\n-{\"e_bcl\",\tBD15(30,8,1),\tBD15_MASK,\tPPCVLE,\t0,\t\t{BO32, BI32, B15}},\n-\n-{\"e_bf\",\tEBD15(30,8,BO32F,0), EBD15_MASK, PPCVLE, EXT,\t\t{BI32,B15}},\n-{\"e_bfl\",\tEBD15(30,8,BO32F,1), EBD15_MASK, PPCVLE, EXT,\t\t{BI32,B15}},\n-{\"e_bt\",\tEBD15(30,8,BO32T,0), EBD15_MASK, PPCVLE, EXT,\t\t{BI32,B15}},\n-{\"e_btl\",\tEBD15(30,8,BO32T,1), EBD15_MASK, PPCVLE, EXT,\t\t{BI32,B15}},\n-\n-{\"e_cmph\",\tX(31,14),\tX_MASK,\t\tPPCVLE,\t0,\t\t{CRD, RA, RB}},\n-{\"e_sc\",\tX(31,36),\tXRTRA_MASK,\tPPCVLE,\t0,\t\t{ELEV}},\n-{\"e_cmphl\",\tX(31,46),\tX_MASK,\t\tPPCVLE,\t0,\t\t{CRD, RA, RB}},\n-{\"e_crandc\",\tXL(31,129),\tXL_MASK,\tPPCVLE,\t0,\t\t{BT, BA, BB}},\n-{\"e_crnand\",\tXL(31,225),\tXL_MASK,\tPPCVLE,\t0,\t\t{BT, BA, BB}},\n-{\"e_crnot\",\tXL(31,33),\tXL_MASK,\tPPCVLE,\tEXT,\t\t{BT, BAB}},\n-{\"e_crnor\",\tXL(31,33),\tXL_MASK,\tPPCVLE,\t0,\t\t{BT, BA, BB}},\n-{\"e_crclr\",\tXL(31,193),\tXL_MASK,\tPPCVLE,\tEXT,\t\t{BTAB}},\n-{\"e_crxor\",\tXL(31,193),\tXL_MASK,\tPPCVLE,\t0,\t\t{BT, B 100 73194 100 73044 100 150 679k 1428 --:--:-- --:--:-- --:--:-- 680k A, BB}},\n-{\"e_mcrf\",\tXL(31,16),\tXL_MASK,\tPPCVLE,\t0,\t\t{CRD, CR}},\n-{\"e_slwi\",\tEX(31,112),\tEX_MASK,\tPPCVLE,\t0,\t\t{RA, RS, SH}},\n-{\"e_slwi.\",\tEX(31,113),\tEX_MASK,\tPPCVLE,\t0,\t\t{RA, RS, SH}},\n-\n-{\"e_crand\",\tXL(31,257),\tXL_MASK,\tPPCVLE,\t0,\t\t{BT, BA, BB}},\n-\n-{\"e_rlw\",\tEX(31,560),\tEX_MASK,\tPPCVLE,\t0,\t\t{RA, RS, RB}},\n-{\"e_rlw.\",\tEX(31,561),\tEX_MASK,\tPPCVLE,\t0,\t\t{RA, RS, RB}},\n-\n-{\"e_crset\",\tXL(31,289),\tXL_MASK,\tPPCVLE,\tEXT,\t\t{BTAB}},\n-{\"e_creqv\",\tXL(31,289),\tXL_MASK,\tPPCVLE,\t0,\t\t{BT, BA, BB}},\n-\n-{\"e_rlwi\",\tEX(31,624),\tEX_MASK,\tPPCVLE,\t0,\t\t{RA, RS, SH}},\n-{\"e_rlwi.\",\tEX(31,625),\tEX_MASK,\tPPCVLE,\t0,\t\t{RA, RS, SH}},\n-\n-{\"e_crorc\",\tXL(31,417),\tXL_MASK,\tPPCVLE,\t0,\t\t{BT, BA, BB}},\n-\n-{\"e_crmove\",\tXL(31,449),\tXL_MASK,\tPPCVLE,\tEXT,\t\t{BT, BAB}},\n-{\"e_cror\",\tXL(31,449),\tXL_MASK,\tPPCVLE,\t0,\t\t{BT, BA, BB}},\n-\n-{\"mtmas1\",\tXSPR(31,467,625), XSPR_MASK,\tPPCVLE,\tEXT,\t\t{RS}},\n-\n-{\"e_srwi\",\tEX(31,1136),\tEX_MASK,\tPPCVLE,\t0,\t\t{RA, RS, SH}},\n-{\"e_srwi.\",\tEX(31,1137),\tEX_MASK,\tPPCVLE,\t0,\t\t{RA, RS, SH}},\n-\n-{\"se_lbz\",\tSD4(8),\t\tSD4_MASK,\tPPCVLE,\t0,\t\t{RZ, SE_SD, RX}},\n-\n-{\"se_stb\",\tSD4(9),\t\tSD4_MASK,\tPPCVLE,\t0,\t\t{RZ, SE_SD, RX}},\n-\n-{\"se_lhz\",\tSD4(10),\tSD4_MASK,\tPPCVLE,\t0,\t\t{RZ, SE_SDH, RX}},\n-\n-{\"se_sth\",\tSD4(11),\tSD4_MASK,\tPPCVLE,\t0,\t\t{RZ, SE_SDH, RX}},\n-\n-{\"se_lwz\",\tSD4(12),\tSD4_MASK,\tPPCVLE,\t0,\t\t{RZ, SE_SDW, RX}},\n-\n-{\"se_stw\",\tSD4(13),\tSD4_MASK,\tPPCVLE,\t0,\t\t{RZ, SE_SDW, RX}},\n-\n-{\"se_bge\",\tEBD8IO(28,0,0),\tEBD8IO3_MASK,\tPPCVLE,\tEXT,\t\t{B8}},\n-{\"se_bnl\",\tEBD8IO(28,0,0),\tEBD8IO3_MASK,\tPPCVLE,\tEXT,\t\t{B8}},\n-{\"se_ble\",\tEBD8IO(28,0,1),\tEBD8IO3_MASK,\tPPCVLE,\tEXT,\t\t{B8}},\n-{\"se_bng\",\tEBD8IO(28,0,1),\tEBD8IO3_MASK,\tPPCVLE,\tEXT,\t\t{B8}},\n-{\"se_bne\",\tEBD8IO(28,0,2),\tEBD8IO3_MASK,\tPPCVLE,\tEXT,\t\t{B8}},\n-{\"se_bns\",\tEBD8IO(28,0,3),\tEBD8IO3_MASK,\tPPCVLE,\tEXT,\t\t{B8}},\n-{\"se_bnu\",\tEBD8IO(28,0,3),\tEBD8IO3_MASK,\tPPCVLE,\tEXT,\t\t{B8}},\n-{\"se_bf\",\tEBD8IO(28,0,0),\tEBD8IO2_MASK,\tPPCVLE,\tEXT,\t\t{BI16, B8}},\n-{\"se_blt\",\tEBD8IO(28,1,0),\tEBD8IO3_MASK,\tPPCVLE,\tEXT,\t\t{B8}},\n-{\"se_bgt\",\tEBD8IO(28,1,1),\tEBD8IO3_MASK,\tPPCVLE,\tEXT,\t\t{B8}},\n-{\"se_beq\",\tEBD8IO(28,1,2),\tEBD8IO3_MASK,\tPPCVLE,\tEXT,\t\t{B8}},\n-{\"se_bso\",\tEBD8IO(28,1,3),\tEBD8IO3_MASK,\tPPCVLE,\tEXT,\t\t{B8}},\n-{\"se_bun\",\tEBD8IO(28,1,3),\tEBD8IO3_MASK,\tPPCVLE,\tEXT,\t\t{B8}},\n-{\"se_bt\",\tEBD8IO(28,1,0),\tEBD8IO2_MASK,\tPPCVLE,\tEXT,\t\t{BI16, B8}},\n-{\"se_bc\",\tBD8IO(28),\tBD8IO_MASK,\tPPCVLE,\t0,\t\t{BO16, BI16, B8}},\n-{\"se_b\",\tBD8(58,0,0),\tBD8_MASK,\tPPCVLE,\t0,\t\t{B8}},\n-{\"se_bl\",\tBD8(58,0,1),\tBD8_MASK,\tPPCVLE,\t0,\t\t{B8}},\n };\n \n-const unsigned int vle_num_opcodes =\n- sizeof (vle_opcodes) / sizeof (vle_opcodes[0]);\n+const unsigned int lsp_num_opcodes = ARRAY_SIZE (lsp_opcodes);\n \n /* SPE v2 instruction set from SPE2PIM Rev. 2 08/2011 */\n const struct powerpc_opcode spe2_opcodes[] = {\n@@ -11391,5 +11392,4 @@ const struct powerpc_opcode spe2_opcodes[] = {\n {\"evavgdsr\",\t\t VX (4, 1663),\t\tVX_MASK,\t\tPPCSPE2, 0, {RD, RA, RB}},\n };\n \n-const unsigned int spe2_num_opcodes =\n- sizeof (spe2_opcodes) / sizeof (spe2_opcodes[0]);\n+const unsigned int spe2_num_opcodes = ARRAY_SIZE (spe2_opcodes);\n","prefixes":[]}+ exit 1 Build step 'Execute shell' marked build as failure Finished: FAILURE