| Message ID | 20230302021905.2777-1-jammy_huang@aspeedtech.com |
|---|---|
| State | New |
| Headers |
Return-Path: <linux-kernel-owner@vger.kernel.org>
Delivered-To: ouuuleilei@gmail.com
Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp4001331wrd;
Wed, 1 Mar 2023 18:42:31 -0800 (PST)
X-Google-Smtp-Source:
AK7set+NUw+wWhSr3shwNpm3K3oBRTgnXq+DlbuOcOFDv8xMZY9OWN1v8KSVmzK0BKMBUX+vvQRT
X-Received: by 2002:a17:906:792:b0:8d9:8f8f:d542 with SMTP id
l18-20020a170906079200b008d98f8fd542mr506738ejc.32.1677724951149;
Wed, 01 Mar 2023 18:42:31 -0800 (PST)
ARC-Seal: i=1; a=rsa-sha256; t=1677724951; cv=none;
d=google.com; s=arc-20160816;
b=emdrMPVJgwxxYLS5A8RViSyxakxH37vCCHfzoE1Gx8Zd552K7uinsSOqV553HMbFWY
k5FMHN3vmSN9qShT1zzsvbyMs4yJpOqI5lMAsD/leUUr+rwHX29dugeeoVHY8X8rTMu4
HUaJuWhmtLLkPUzw8s+xQcdmMljLIIrxwkAhU/EnMqKHsENv3yhNPHVLye1zdYXNWebs
O/7KTrKDKZu9Vp3PIK7ulEBp+Ucc0AZEDMq5FWkFOiYQCfvlmxKjpV2roc3eo9/6UYdj
q4oemdfwEa2eZ26+VLPJxhizl3kgelMTkVdCpd/V97fIJBr5vCm3TMeHsUXh/D+hoj23
QJiw==
ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com;
s=arc-20160816;
h=list-id:precedence:content-transfer-encoding:mime-version
:message-id:date:subject:cc:to:from;
bh=tMjFH0gZt1exblEku8EqT6XSQB9iU3AHoL19bSRt71U=;
b=OEujs6MDgDYy3KS2nbMBY/iAFtmWn4zPri0tgHNjt3SAlOWljp8A+52Pjy4j3DJQTy
k3LcfYdkyrWEiXOlikqGkzI+9KsDaB/RWkxkw9YTf5zj4jmEszRIE7r9GZlzhfT0W7sv
9Rq91OmmCvXqJfg99NxJxOksXlCKobW1NWZsZbE1TrGisAAwZ1Z48dBL5tuZ4RIHky/2
e1BCz2xJsuSPDz2d2lOAyq/ds0179vTMo8FW/7nqfU5nok5eMZp5dP+yATvxH9ZnL+mm
AIjId63dW4upeR7rhDK0xTQCWcW/iPSwmhCkLOpBSBSy2KuPE6a2eW7N7A7LzLziSvDH
x4UA==
ARC-Authentication-Results: i=1; mx.google.com;
spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org
designates 2620:137:e000::1:20 as permitted sender)
smtp.mailfrom=linux-kernel-owner@vger.kernel.org
Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20])
by mx.google.com with ESMTP id
o19-20020a1709062e9300b008b17b550d11si1290433eji.382.2023.03.01.18.42.08;
Wed, 01 Mar 2023 18:42:31 -0800 (PST)
Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org
designates 2620:137:e000::1:20 as permitted sender)
client-ip=2620:137:e000::1:20;
Authentication-Results: mx.google.com;
spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org
designates 2620:137:e000::1:20 as permitted sender)
smtp.mailfrom=linux-kernel-owner@vger.kernel.org
Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand
id S229686AbjCBCTw (ORCPT <rfc822;davidbtadokoro@gmail.com>
+ 99 others); Wed, 1 Mar 2023 21:19:52 -0500
Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48744 "EHLO
lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org
with ESMTP id S229541AbjCBCTu (ORCPT
<rfc822;linux-kernel@vger.kernel.org>);
Wed, 1 Mar 2023 21:19:50 -0500
Received: from twspam01.aspeedtech.com (twspam01.aspeedtech.com
[211.20.114.71])
by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2087C22794
for <linux-kernel@vger.kernel.org>;
Wed, 1 Mar 2023 18:19:44 -0800 (PST)
Received: from mail.aspeedtech.com ([192.168.0.24])
by twspam01.aspeedtech.com with ESMTP id 32225huK008905;
Thu, 2 Mar 2023 10:05:43 +0800 (GMT-8)
(envelope-from jammy_huang@aspeedtech.com)
Received: from JammyHuang-PC.aspeed.com (192.168.2.115) by TWMBX02.aspeed.com
(192.168.0.24) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 2 Mar
2023 10:19:08 +0800
From: Jammy Huang <jammy_huang@aspeedtech.com>
To: <airlied@redhat.com>, <tzimmermann@suse.de>, <airlied@gmail.com>,
<daniel@ffwll.ch>
CC: <dri-devel@lists.freedesktop.org>, <linux-kernel@vger.kernel.org>
Subject: [PATCH] drm/ast: Fix ARM compatibility
Date: Thu, 2 Mar 2023 10:19:05 +0800
Message-ID: <20230302021905.2777-1-jammy_huang@aspeedtech.com>
X-Mailer: git-send-email 2.25.1
MIME-Version: 1.0
Content-Transfer-Encoding: 7BIT
Content-Type: text/plain; charset=US-ASCII
X-Originating-IP: [192.168.2.115]
X-ClientProxiedBy: TWMBX02.aspeed.com (192.168.0.24) To TWMBX02.aspeed.com
(192.168.0.24)
X-DNSRBL:
X-MAIL: twspam01.aspeedtech.com 32225huK008905
X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,SPF_HELO_NONE,
SPF_PASS autolearn=ham autolearn_force=no version=3.4.6
X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on
lindbergh.monkeyblade.net
Precedence: bulk
List-ID: <linux-kernel.vger.kernel.org>
X-Mailing-List: linux-kernel@vger.kernel.org
X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?=
X-GMAIL-THRID: =?utf-8?q?1759222118276083028?=
X-GMAIL-MSGID: =?utf-8?q?1759222118276083028?=
|
| Series |
drm/ast: Fix ARM compatibility
|
|
Commit Message
Jammy Huang
March 2, 2023, 2:19 a.m. UTC
ARM architecture only has 'memory', so all devices are accessed by MMIO.
Signed-off-by: Jammy Huang <jammy_huang@aspeedtech.com>
---
drivers/gpu/drm/ast/ast_main.c | 17 +----------------
1 file changed, 1 insertion(+), 16 deletions(-)
base-commit: 254986e324add8a30d0019c6da59f81adc8b565f
Comments
Hi Thomas, Could you help review this patch?? We met some problem on nvidia's ARM platfrom and need this patch to fix it. On 2023/3/2 上午 10:19, Jammy Huang wrote: > ARM architecture only has 'memory', so all devices are accessed by MMIO. > > Signed-off-by: Jammy Huang <jammy_huang@aspeedtech.com> > --- > drivers/gpu/drm/ast/ast_main.c | 17 +---------------- > 1 file changed, 1 insertion(+), 16 deletions(-) > > diff --git a/drivers/gpu/drm/ast/ast_main.c b/drivers/gpu/drm/ast/ast_main.c > index 794ffd4a29c5..f86d01e9f024 100644 > --- a/drivers/gpu/drm/ast/ast_main.c > +++ b/drivers/gpu/drm/ast/ast_main.c > @@ -424,22 +424,7 @@ struct ast_device *ast_device_create(const struct drm_driver *drv, > if (!ast->regs) > return ERR_PTR(-EIO); > > - /* > - * If we don't have IO space at all, use MMIO now and > - * assume the chip has MMIO enabled by default (rev 0x20 > - * and higher). > - */ > - if (!(pci_resource_flags(pdev, 2) & IORESOURCE_IO)) { > - drm_info(dev, "platform has no IO space, trying MMIO\n"); > - ast->ioregs = ast->regs + AST_IO_MM_OFFSET; > - } > - > - /* "map" IO regs if the above hasn't done so already */ > - if (!ast->ioregs) { > - ast->ioregs = pcim_iomap(pdev, 2, 0); > - if (!ast->ioregs) > - return ERR_PTR(-EIO); > - } > + ast->ioregs = ast->regs + AST_IO_MM_OFFSET; > > ast_detect_chip(dev, &need_post); > > > base-commit: 254986e324add8a30d0019c6da59f81adc8b565f
Hi Am 07.04.23 um 04:09 schrieb Jammy Huang: > Hi Thomas, > > Could you help review this patch?? > > We met some problem on nvidia's ARM platfrom and need this patch to fix it. > > On 2023/3/2 上午 10:19, Jammy Huang wrote: >> ARM architecture only has 'memory', so all devices are accessed by MMIO. >> >> Signed-off-by: Jammy Huang <jammy_huang@aspeedtech.com> >> --- >> drivers/gpu/drm/ast/ast_main.c | 17 +---------------- >> 1 file changed, 1 insertion(+), 16 deletions(-) >> >> diff --git a/drivers/gpu/drm/ast/ast_main.c >> b/drivers/gpu/drm/ast/ast_main.c >> index 794ffd4a29c5..f86d01e9f024 100644 >> --- a/drivers/gpu/drm/ast/ast_main.c >> +++ b/drivers/gpu/drm/ast/ast_main.c >> @@ -424,22 +424,7 @@ struct ast_device *ast_device_create(const struct >> drm_driver *drv, >> if (!ast->regs) >> return ERR_PTR(-EIO); >> - /* >> - * If we don't have IO space at all, use MMIO now and >> - * assume the chip has MMIO enabled by default (rev 0x20 >> - * and higher). >> - */ >> - if (!(pci_resource_flags(pdev, 2) & IORESOURCE_IO)) { >> - drm_info(dev, "platform has no IO space, trying MMIO\n"); >> - ast->ioregs = ast->regs + AST_IO_MM_OFFSET; >> - } >> - >> - /* "map" IO regs if the above hasn't done so already */ >> - if (!ast->ioregs) { >> - ast->ioregs = pcim_iomap(pdev, 2, 0); What happens on systems that use this branch? Best regards Thomas >> - if (!ast->ioregs) >> - return ERR_PTR(-EIO); >> - } >> + ast->ioregs = ast->regs + AST_IO_MM_OFFSET; >> ast_detect_chip(dev, &need_post); >> >> base-commit: 254986e324add8a30d0019c6da59f81adc8b565f > -- Thomas Zimmermann Graphics Driver Developer SUSE Software Solutions Germany GmbH Maxfeldstr. 5, 90409 Nürnberg, Germany (HRB 36809, AG Nürnberg) Geschäftsführer: Ivo Totev
Hi Am 18.04.23 um 03:23 schrieb Jammy Huang: > Hi Thomas, > > The Intel(x86) CPUs have a separate address space for "IO", but the ARM > architecture only has "memory", so all IO devices are accessed as if > they were memory. Which means ARM does not support isolated IO. Here is > a related discussion on ARM's forum. > > https://community.arm.com/support-forums/f/architectures-and-processors-forum/52046/how-to-read-write-an-i-o-port-in-aarch64 > > Thus, we want to adapt MMIO only after this patch. What I mean is that there's a comment that says "assume the chip has MMIO enabled by default (rev 0x20 and higher)". We also support revs before 0x20. What happens to them? Best regards Thomas > > On 2023/4/17 下午 07:51, Thomas Zimmermann wrote: >> Hi >> >> Am 07.04.23 um 04:09 schrieb Jammy Huang: >>> Hi Thomas, >>> >>> Could you help review this patch?? >>> >>> We met some problem on nvidia's ARM platfrom and need this patch to >>> fix it. >>> >>> On 2023/3/2 上午 10:19, Jammy Huang wrote: >>>> ARM architecture only has 'memory', so all devices are accessed by >>>> MMIO. >>>> >>>> Signed-off-by: Jammy Huang <jammy_huang@aspeedtech.com> >>>> --- >>>> drivers/gpu/drm/ast/ast_main.c | 17 +---------------- >>>> 1 file changed, 1 insertion(+), 16 deletions(-) >>>> >>>> diff --git a/drivers/gpu/drm/ast/ast_main.c >>>> b/drivers/gpu/drm/ast/ast_main.c >>>> index 794ffd4a29c5..f86d01e9f024 100644 >>>> --- a/drivers/gpu/drm/ast/ast_main.c >>>> +++ b/drivers/gpu/drm/ast/ast_main.c >>>> @@ -424,22 +424,7 @@ struct ast_device *ast_device_create(const >>>> struct drm_driver *drv, >>>> if (!ast->regs) >>>> return ERR_PTR(-EIO); >>>> - /* >>>> - * If we don't have IO space at all, use MMIO now and >>>> - * assume the chip has MMIO enabled by default (rev 0x20 >>>> - * and higher). >>>> - */ >>>> - if (!(pci_resource_flags(pdev, 2) & IORESOURCE_IO)) { >>>> - drm_info(dev, "platform has no IO space, trying MMIO\n"); >>>> - ast->ioregs = ast->regs + AST_IO_MM_OFFSET; >>>> - } >>>> - >>>> - /* "map" IO regs if the above hasn't done so already */ >>>> - if (!ast->ioregs) { >>>> - ast->ioregs = pcim_iomap(pdev, 2, 0); >> >> What happens on systems that use this branch? >> >> Best regards >> Thomas >> >>>> - if (!ast->ioregs) >>>> - return ERR_PTR(-EIO); >>>> - } >>>> + ast->ioregs = ast->regs + AST_IO_MM_OFFSET; >>>> ast_detect_chip(dev, &need_post); >>>> >>>> base-commit: 254986e324add8a30d0019c6da59f81adc8b565f >>> >> > -- > Best Regards > Jammy > -- Thomas Zimmermann Graphics Driver Developer SUSE Software Solutions Germany GmbH Maxfeldstr. 5, 90409 Nürnberg, Germany (HRB 36809, AG Nürnberg) Geschäftsführer: Ivo Totev
Hi Thomas, Thanks for you reminder. The comment you mentioned is added in 2014 for AST2400 rev 0x20, which means MMIO is not enable by default before that revision. I will send another patch to handle it. On 2023/4/18 下午 03:24, Thomas Zimmermann wrote: > Hi > > Am 18.04.23 um 03:23 schrieb Jammy Huang: >> Hi Thomas, >> >> The Intel(x86) CPUs have a separate address space for "IO", but the >> ARM architecture only has "memory", so all IO devices are accessed as >> if they were memory. Which means ARM does not support isolated IO. >> Here is a related discussion on ARM's forum. >> >> https://community.arm.com/support-forums/f/architectures-and-processors-forum/52046/how-to-read-write-an-i-o-port-in-aarch64 >> >> >> Thus, we want to adapt MMIO only after this patch. > > What I mean is that there's a comment that says "assume the chip has > MMIO enabled by default (rev 0x20 and higher)". We also support revs > before 0x20. What happens to them? > > Best regards > Thomas > >> >> On 2023/4/17 下午 07:51, Thomas Zimmermann wrote: >>> Hi >>> >>> Am 07.04.23 um 04:09 schrieb Jammy Huang: >>>> Hi Thomas, >>>> >>>> Could you help review this patch?? >>>> >>>> We met some problem on nvidia's ARM platfrom and need this patch to >>>> fix it. >>>> >>>> On 2023/3/2 上午 10:19, Jammy Huang wrote: >>>>> ARM architecture only has 'memory', so all devices are accessed by >>>>> MMIO. >>>>> >>>>> Signed-off-by: Jammy Huang <jammy_huang@aspeedtech.com> >>>>> --- >>>>> drivers/gpu/drm/ast/ast_main.c | 17 +---------------- >>>>> 1 file changed, 1 insertion(+), 16 deletions(-) >>>>> >>>>> diff --git a/drivers/gpu/drm/ast/ast_main.c >>>>> b/drivers/gpu/drm/ast/ast_main.c >>>>> index 794ffd4a29c5..f86d01e9f024 100644 >>>>> --- a/drivers/gpu/drm/ast/ast_main.c >>>>> +++ b/drivers/gpu/drm/ast/ast_main.c >>>>> @@ -424,22 +424,7 @@ struct ast_device *ast_device_create(const >>>>> struct drm_driver *drv, >>>>> if (!ast->regs) >>>>> return ERR_PTR(-EIO); >>>>> - /* >>>>> - * If we don't have IO space at all, use MMIO now and >>>>> - * assume the chip has MMIO enabled by default (rev 0x20 >>>>> - * and higher). >>>>> - */ >>>>> - if (!(pci_resource_flags(pdev, 2) & IORESOURCE_IO)) { >>>>> - drm_info(dev, "platform has no IO space, trying MMIO\n"); >>>>> - ast->ioregs = ast->regs + AST_IO_MM_OFFSET; >>>>> - } >>>>> - >>>>> - /* "map" IO regs if the above hasn't done so already */ >>>>> - if (!ast->ioregs) { >>>>> - ast->ioregs = pcim_iomap(pdev, 2, 0); >>> >>> What happens on systems that use this branch? >>> >>> Best regards >>> Thomas >>> >>>>> - if (!ast->ioregs) >>>>> - return ERR_PTR(-EIO); >>>>> - } >>>>> + ast->ioregs = ast->regs + AST_IO_MM_OFFSET; >>>>> ast_detect_chip(dev, &need_post); >>>>> >>>>> base-commit: 254986e324add8a30d0019c6da59f81adc8b565f >>>> >>> >> -- >> Best Regards >> Jammy >> >
diff --git a/drivers/gpu/drm/ast/ast_main.c b/drivers/gpu/drm/ast/ast_main.c index 794ffd4a29c5..f86d01e9f024 100644 --- a/drivers/gpu/drm/ast/ast_main.c +++ b/drivers/gpu/drm/ast/ast_main.c @@ -424,22 +424,7 @@ struct ast_device *ast_device_create(const struct drm_driver *drv, if (!ast->regs) return ERR_PTR(-EIO); - /* - * If we don't have IO space at all, use MMIO now and - * assume the chip has MMIO enabled by default (rev 0x20 - * and higher). - */ - if (!(pci_resource_flags(pdev, 2) & IORESOURCE_IO)) { - drm_info(dev, "platform has no IO space, trying MMIO\n"); - ast->ioregs = ast->regs + AST_IO_MM_OFFSET; - } - - /* "map" IO regs if the above hasn't done so already */ - if (!ast->ioregs) { - ast->ioregs = pcim_iomap(pdev, 2, 0); - if (!ast->ioregs) - return ERR_PTR(-EIO); - } + ast->ioregs = ast->regs + AST_IO_MM_OFFSET; ast_detect_chip(dev, &need_post);