[v5,2/2] arm64: dts: qcom: sm6115: Add USB SS qmp phy node
Commit Message
Add USB superspeed qmp phy node to dtsi.
Make sure that the various board dts files (which include sm4250.dtsi file)
continue to work as intended.
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
---
.../boot/dts/qcom/sm4250-oneplus-billie2.dts | 3 ++
arch/arm64/boot/dts/qcom/sm6115.dtsi | 36 +++++++++++++++++--
.../boot/dts/qcom/sm6115p-lenovo-j606f.dts | 3 ++
3 files changed, 40 insertions(+), 2 deletions(-)
Comments
On Wed, 5 Apr 2023 at 22:19, Bhupesh Sharma <bhupesh.sharma@linaro.org> wrote:
>
> Add USB superspeed qmp phy node to dtsi.
>
> Make sure that the various board dts files (which include sm4250.dtsi file)
> continue to work as intended.
>
> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
> ---
> .../boot/dts/qcom/sm4250-oneplus-billie2.dts | 3 ++
> arch/arm64/boot/dts/qcom/sm6115.dtsi | 36 +++++++++++++++++--
> .../boot/dts/qcom/sm6115p-lenovo-j606f.dts | 3 ++
> 3 files changed, 40 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm4250-oneplus-billie2.dts b/arch/arm64/boot/dts/qcom/sm4250-oneplus-billie2.dts
> index a1f0622db5a0..75951fd439df 100644
> --- a/arch/arm64/boot/dts/qcom/sm4250-oneplus-billie2.dts
> +++ b/arch/arm64/boot/dts/qcom/sm4250-oneplus-billie2.dts
> @@ -242,6 +242,9 @@ &usb {
> &usb_dwc3 {
> maximum-speed = "high-speed";
> dr_mode = "peripheral";
> +
> + phys = <&usb_hsphy>;
> + phy-names = "usb2-phy";
> };
>
> &usb_hsphy {
> diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi
> index 2a51c938bbcb..b2fa565e4816 100644
> --- a/arch/arm64/boot/dts/qcom/sm6115.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi
> @@ -650,6 +650,38 @@ usb_hsphy: phy@1613000 {
> status = "disabled";
> };
>
> + usb_qmpphy: phy@1615000 {
> + compatible = "qcom,sm6115-qmp-usb3-phy";
> + reg = <0x0 0x01615000 0x0 0x200>;
> + clocks = <&gcc GCC_AHB2PHY_USB_CLK>,
> + <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
> + <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
> + clock-names = "cfg_ahb",
> + "ref",
> + "com_aux";
> + resets = <&gcc GCC_USB3PHY_PHY_PRIM_SP0_BCR>,
> + <&gcc GCC_USB3_PHY_PRIM_SP0_BCR>;
> + reset-names = "phy_phy", "phy";
> + status = "disabled";
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +
> + usb_ssphy: phy@1615200 {
> + reg = <0x0 0x01615200 0x0 0x200>,
> + <0x0 0x01615400 0x0 0x200>,
> + <0x0 0x01615c00 0x0 0x400>,
> + <0x0 0x01615600 0x0 0x200>,
> + <0x0 0x01615800 0x0 0x200>,
> + <0x0 0x01615a00 0x0 0x100>;
> + #clock-cells = <0>;
> + #phy-cells = <0>;
> + clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
> + clock-names = "pipe0";
> + clock-output-names = "usb3_phy_pipe_clk_src";
> + };
> + };
I can repeat previous message:
Please update this to newer style bindings (see
qcom,sc8280xp-qmp-usb3-uni-phy.yaml).
We are going to switch all QMP PHYs to use a newer style of bindings.
I have started the work to convert existing usecases. As you are
adding a new DT node, please add it in a good shape from the
beginning.
> +
> qfprom@1b40000 {
> compatible = "qcom,sm6115-qfprom", "qcom,qfprom";
> reg = <0x0 0x01b40000 0x0 0x7000>;
> @@ -1100,8 +1132,8 @@ usb_dwc3: usb@4e00000 {
> compatible = "snps,dwc3";
> reg = <0x0 0x04e00000 0x0 0xcd00>;
> interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
> - phys = <&usb_hsphy>;
> - phy-names = "usb2-phy";
> + phys = <&usb_hsphy>, <&usb_ssphy>;
> + phy-names = "usb2-phy", "usb3-phy";
> iommus = <&apps_smmu 0x120 0x0>;
> snps,dis_u2_susphy_quirk;
> snps,dis_enblslpm_quirk;
> diff --git a/arch/arm64/boot/dts/qcom/sm6115p-lenovo-j606f.dts b/arch/arm64/boot/dts/qcom/sm6115p-lenovo-j606f.dts
> index 10c9d338446c..d60cc024749b 100644
> --- a/arch/arm64/boot/dts/qcom/sm6115p-lenovo-j606f.dts
> +++ b/arch/arm64/boot/dts/qcom/sm6115p-lenovo-j606f.dts
> @@ -280,6 +280,9 @@ &usb {
> &usb_dwc3 {
> maximum-speed = "high-speed";
> dr_mode = "peripheral";
> +
> + phys = <&usb_hsphy>;
> + phy-names = "usb2-phy";
> };
>
> &usb_hsphy {
> --
> 2.38.1
>
On Thu, 6 Apr 2023 at 01:06, Dmitry Baryshkov
<dmitry.baryshkov@linaro.org> wrote:
>
> On Wed, 5 Apr 2023 at 22:19, Bhupesh Sharma <bhupesh.sharma@linaro.org> wrote:
> >
> > Add USB superspeed qmp phy node to dtsi.
> >
> > Make sure that the various board dts files (which include sm4250.dtsi file)
> > continue to work as intended.
> >
> > Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
> > ---
> > .../boot/dts/qcom/sm4250-oneplus-billie2.dts | 3 ++
> > arch/arm64/boot/dts/qcom/sm6115.dtsi | 36 +++++++++++++++++--
> > .../boot/dts/qcom/sm6115p-lenovo-j606f.dts | 3 ++
> > 3 files changed, 40 insertions(+), 2 deletions(-)
> >
> > diff --git a/arch/arm64/boot/dts/qcom/sm4250-oneplus-billie2.dts b/arch/arm64/boot/dts/qcom/sm4250-oneplus-billie2.dts
> > index a1f0622db5a0..75951fd439df 100644
> > --- a/arch/arm64/boot/dts/qcom/sm4250-oneplus-billie2.dts
> > +++ b/arch/arm64/boot/dts/qcom/sm4250-oneplus-billie2.dts
> > @@ -242,6 +242,9 @@ &usb {
> > &usb_dwc3 {
> > maximum-speed = "high-speed";
> > dr_mode = "peripheral";
> > +
> > + phys = <&usb_hsphy>;
> > + phy-names = "usb2-phy";
> > };
> >
> > &usb_hsphy {
> > diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi
> > index 2a51c938bbcb..b2fa565e4816 100644
> > --- a/arch/arm64/boot/dts/qcom/sm6115.dtsi
> > +++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi
> > @@ -650,6 +650,38 @@ usb_hsphy: phy@1613000 {
> > status = "disabled";
> > };
> >
> > + usb_qmpphy: phy@1615000 {
> > + compatible = "qcom,sm6115-qmp-usb3-phy";
> > + reg = <0x0 0x01615000 0x0 0x200>;
> > + clocks = <&gcc GCC_AHB2PHY_USB_CLK>,
> > + <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
> > + <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
> > + clock-names = "cfg_ahb",
> > + "ref",
> > + "com_aux";
> > + resets = <&gcc GCC_USB3PHY_PHY_PRIM_SP0_BCR>,
> > + <&gcc GCC_USB3_PHY_PRIM_SP0_BCR>;
> > + reset-names = "phy_phy", "phy";
> > + status = "disabled";
> > + #address-cells = <2>;
> > + #size-cells = <2>;
> > + ranges;
> > +
> > + usb_ssphy: phy@1615200 {
> > + reg = <0x0 0x01615200 0x0 0x200>,
> > + <0x0 0x01615400 0x0 0x200>,
> > + <0x0 0x01615c00 0x0 0x400>,
> > + <0x0 0x01615600 0x0 0x200>,
> > + <0x0 0x01615800 0x0 0x200>,
> > + <0x0 0x01615a00 0x0 0x100>;
> > + #clock-cells = <0>;
> > + #phy-cells = <0>;
> > + clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
> > + clock-names = "pipe0";
> > + clock-output-names = "usb3_phy_pipe_clk_src";
> > + };
> > + };
>
> I can repeat previous message:
>
> Please update this to newer style bindings (see
> qcom,sc8280xp-qmp-usb3-uni-phy.yaml).
>
> We are going to switch all QMP PHYs to use a newer style of bindings.
> I have started the work to convert existing usecases. As you are
> adding a new DT node, please add it in a good shape from the
> beginning.
Your earlier message was not clear and I sent out a reply for the
cover letter query you had, but got no reply. I think a pointer to
<https://patchwork.kernel.org/project/linux-phy/list/?series=733714>
would have been more clear.
I will rework and send v6 accordingly.
Thanks,
Bhupesh
@@ -242,6 +242,9 @@ &usb {
&usb_dwc3 {
maximum-speed = "high-speed";
dr_mode = "peripheral";
+
+ phys = <&usb_hsphy>;
+ phy-names = "usb2-phy";
};
&usb_hsphy {
@@ -650,6 +650,38 @@ usb_hsphy: phy@1613000 {
status = "disabled";
};
+ usb_qmpphy: phy@1615000 {
+ compatible = "qcom,sm6115-qmp-usb3-phy";
+ reg = <0x0 0x01615000 0x0 0x200>;
+ clocks = <&gcc GCC_AHB2PHY_USB_CLK>,
+ <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
+ <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
+ clock-names = "cfg_ahb",
+ "ref",
+ "com_aux";
+ resets = <&gcc GCC_USB3PHY_PHY_PRIM_SP0_BCR>,
+ <&gcc GCC_USB3_PHY_PRIM_SP0_BCR>;
+ reset-names = "phy_phy", "phy";
+ status = "disabled";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ usb_ssphy: phy@1615200 {
+ reg = <0x0 0x01615200 0x0 0x200>,
+ <0x0 0x01615400 0x0 0x200>,
+ <0x0 0x01615c00 0x0 0x400>,
+ <0x0 0x01615600 0x0 0x200>,
+ <0x0 0x01615800 0x0 0x200>,
+ <0x0 0x01615a00 0x0 0x100>;
+ #clock-cells = <0>;
+ #phy-cells = <0>;
+ clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
+ clock-names = "pipe0";
+ clock-output-names = "usb3_phy_pipe_clk_src";
+ };
+ };
+
qfprom@1b40000 {
compatible = "qcom,sm6115-qfprom", "qcom,qfprom";
reg = <0x0 0x01b40000 0x0 0x7000>;
@@ -1100,8 +1132,8 @@ usb_dwc3: usb@4e00000 {
compatible = "snps,dwc3";
reg = <0x0 0x04e00000 0x0 0xcd00>;
interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
- phys = <&usb_hsphy>;
- phy-names = "usb2-phy";
+ phys = <&usb_hsphy>, <&usb_ssphy>;
+ phy-names = "usb2-phy", "usb3-phy";
iommus = <&apps_smmu 0x120 0x0>;
snps,dis_u2_susphy_quirk;
snps,dis_enblslpm_quirk;
@@ -280,6 +280,9 @@ &usb {
&usb_dwc3 {
maximum-speed = "high-speed";
dr_mode = "peripheral";
+
+ phys = <&usb_hsphy>;
+ phy-names = "usb2-phy";
};
&usb_hsphy {