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From: Michael Sit Wei Hong <michael.wei.hong.sit@intel.com>
To: Giuseppe Cavallaro <peppe.cavallaro@st.com>,
Alexandre Torgue <alexandre.torgue@foss.st.com>,
Jose Abreu <joabreu@synopsys.com>,
"David S . Miller" <davem@davemloft.net>,
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Cc: Looi Hong Aun <hong.aun.looi@intel.com>,
Voon Weifeng <weifeng.voon@intel.com>,
Lai Peter Jun Ann <peter.jun.ann.lai@intel.com>
Subject: [PATCH net v5 2/3] net: stmmac: check if MAC needs to attach to a PHY
Date: Thu, 30 Mar 2023 17:14:03 +0800
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| Series |
Fix PHY handle no longer parsing
|
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Commit Message
Sit, Michael Wei Hong
March 30, 2023, 9:14 a.m. UTC
After the introduction of the fixed-link support, the MAC driver
no longer attempt to scan for a PHY to attach to. This causes the
non fixed-link setups to stop working.
Using the phylink_expects_phy() to check and determine if the MAC
should expect and attach a PHY.
Fixes: ab21cf920928 ("net: stmmac: make mdio register skips PHY scanning for fixed-link")
Signed-off-by: Michael Sit Wei Hong <michael.wei.hong.sit@intel.com>
Signed-off-by: Lai Peter Jun Ann <peter.jun.ann.lai@intel.com>
---
drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
Comments
Hello, [...] > @@ -1144,10 +1145,11 @@ static int stmmac_init_phy(struct net_device *dev) > if (fwnode) > ret = phylink_fwnode_phy_connect(priv->phylink, fwnode, 0); > > + phy_needed = phylink_expects_phy(priv->phylink); > /* Some DT bindings do not set-up the PHY handle. Let's try to > * manually parse it > */ > - if (!fwnode || ret) { > + if (!fwnode || phy_needed || ret) { Unfortunately this breaks Ethernet on my X96 Air board (the .dts file can be found upstream in: arch/arm64/boot/dts/amlogic/meson-sm1-x96-air-gbit.dts) Working boot-log: # dmesg | grep dwmac [ 3.699961] meson8b-dwmac ff3f0000.ethernet: IRQ eth_wake_irq not found [ 3.700944] meson8b-dwmac ff3f0000.ethernet: IRQ eth_lpi not found [ 3.707196] meson8b-dwmac ff3f0000.ethernet: PTP uses main clock [ 3.713688] meson8b-dwmac ff3f0000.ethernet: User ID: 0x11, Synopsys ID: 0x37 [ 3.720201] meson8b-dwmac ff3f0000.ethernet: DWMAC1000 [ 3.725387] meson8b-dwmac ff3f0000.ethernet: DMA HW capability register supported [ 3.732832] meson8b-dwmac ff3f0000.ethernet: RX Checksum Offload Engine supported [ 3.740301] meson8b-dwmac ff3f0000.ethernet: COE Type 2 [ 3.745491] meson8b-dwmac ff3f0000.ethernet: TX Checksum insertion supported [ 3.752504] meson8b-dwmac ff3f0000.ethernet: Wake-Up On Lan supported [ 3.758993] meson8b-dwmac ff3f0000.ethernet: Normal descriptors [ 3.764813] meson8b-dwmac ff3f0000.ethernet: Ring mode enabled [ 3.770629] meson8b-dwmac ff3f0000.ethernet: Enable RX Mitigation via HW Watchdog Timer [ 13.565781] meson8b-dwmac ff3f0000.ethernet end0: renamed from eth0 [ 14.036061] meson8b-dwmac ff3f0000.ethernet end0: Register MEM_TYPE_PAGE_POOL RxQ-0 [ 14.255617] meson8b-dwmac ff3f0000.ethernet end0: PHY [mdio_mux-0.0:00] driver [RTL8211F Gigabit Ethernet] (irq=33) [ 14.265404] meson8b-dwmac ff3f0000.ethernet end0: No Safety Features support found [ 14.267977] meson8b-dwmac ff3f0000.ethernet end0: PTP not supported by HW [ 14.275723] meson8b-dwmac ff3f0000.ethernet end0: configuring for phy/rgmii-txid link mode [ 17.394262] meson8b-dwmac ff3f0000.ethernet end0: Link is Up - 1Gbps/Full - flow control rx/tx Non-working boot-log: # dmesg | grep dwmac [ 3.730072] meson8b-dwmac ff3f0000.ethernet: IRQ eth_wake_irq not found [ 3.731053] meson8b-dwmac ff3f0000.ethernet: IRQ eth_lpi not found [ 3.737303] meson8b-dwmac ff3f0000.ethernet: PTP uses main clock [ 3.743795] meson8b-dwmac ff3f0000.ethernet: User ID: 0x11, Synopsys ID: 0x37 [ 3.750311] meson8b-dwmac ff3f0000.ethernet: DWMAC1000 [ 3.755498] meson8b-dwmac ff3f0000.ethernet: DMA HW capability register supported [ 3.762944] meson8b-dwmac ff3f0000.ethernet: RX Checksum Offload Engine supported [ 3.770412] meson8b-dwmac ff3f0000.ethernet: COE Type 2 [ 3.775603] meson8b-dwmac ff3f0000.ethernet: TX Checksum insertion supported [ 3.782615] meson8b-dwmac ff3f0000.ethernet: Wake-Up On Lan supported [ 3.789106] meson8b-dwmac ff3f0000.ethernet: Normal descriptors [ 3.794924] meson8b-dwmac ff3f0000.ethernet: Ring mode enabled [ 3.800738] meson8b-dwmac ff3f0000.ethernet: Enable RX Mitigation via HW Watchdog Timer [ 13.052942] meson8b-dwmac ff3f0000.ethernet end0: renamed from eth0 [ 13.594285] meson8b-dwmac ff3f0000.ethernet end0: Register MEM_TYPE_PAGE_POOL RxQ-0 [ 13.825578] meson8b-dwmac ff3f0000.ethernet end0: PHY [mdio_mux-0.0:00] driver [RTL8211F Gigabit Ethernet] (irq=33) [ 13.831358] meson8b-dwmac ff3f0000.ethernet end0: no phy found [ 13.836229] meson8b-dwmac ff3f0000.ethernet end0: __stmmac_open: Cannot attach to PHY (error: -19) Reverting this patch fixes that problem. I think the reason is a logic error in the patch: As you can see the PHY is found and attached (my understanding is that this happens through phylink_fwnode_phy_connect()). But we now also go to that if block below even fwnode != NULL && ret == 0 (which indicates that phylink_fwnode_phy_connect() was successful). Inside that if block priv->plat->phy_addr then has the default value (-1) that was set in stmmac_probe_config_dt(). I am running out of time for today. Could you please look into this and follow up with a patch (on top of this one, as this one has already been applied) that considers your original issues as well as the case of my board (I suspect that all Amlogic boards that are supported upstream are affected)? Please keep me Cc'ed so I can test your additional patch and then add my Tested-by. Thank you! Martin
Same happens on ARC HSDK [1]: # dmesg | grep stmmaceth stmmaceth f0008000.ethernet: use coherent DMA ops stmmaceth f0008000.ethernet: IRQ eth_wake_irq not found stmmaceth f0008000.ethernet: IRQ eth_lpi not found stmmaceth f0008000.ethernet: PTP uses main clock stmmaceth f0008000.ethernet: User ID: 0x10, Synopsys ID: 0x37 stmmaceth f0008000.ethernet: DWMAC1000 stmmaceth f0008000.ethernet: DMA HW capability register supported stmmaceth f0008000.ethernet: RX Checksum Offload Engine supported stmmaceth f0008000.ethernet: COE Type 2 stmmaceth f0008000.ethernet: TX Checksum insertion supported stmmaceth f0008000.ethernet: Normal descriptors stmmaceth f0008000.ethernet: Ring mode enabled stmmaceth f0008000.ethernet: Enable RX Mitigation via HW Watchdog Timer stmmaceth f0008000.ethernet: device MAC address 7e:14:df:5f:b8:78 stmmaceth f0008000.ethernet eth0: Register MEM_TYPE_PAGE_POOL RxQ-0 stmmaceth f0008000.ethernet eth0: PHY [stmmac-0:00] driver [Micrel KSZ9031 Gigabit PHY] (irq=POLL) stmmaceth f0008000.ethernet eth0: no phy found stmmaceth f0008000.ethernet eth0: __stmmac_open: Cannot attach to PHY (error: -19) After reverting this patch: # dmesg | grep stmmaceth stmmaceth f0008000.ethernet: use coherent DMA ops stmmaceth f0008000.ethernet: IRQ eth_wake_irq not found stmmaceth f0008000.ethernet: IRQ eth_lpi not found stmmaceth f0008000.ethernet: PTP uses main clock stmmaceth f0008000.ethernet: User ID: 0x10, Synopsys ID: 0x37 stmmaceth f0008000.ethernet: DWMAC1000 stmmaceth f0008000.ethernet: DMA HW capability register supported stmmaceth f0008000.ethernet: RX Checksum Offload Engine supported stmmaceth f0008000.ethernet: COE Type 2 stmmaceth f0008000.ethernet: TX Checksum insertion supported stmmaceth f0008000.ethernet: Normal descriptors stmmaceth f0008000.ethernet: Ring mode enabled stmmaceth f0008000.ethernet: Enable RX Mitigation via HW Watchdog Timer stmmaceth f0008000.ethernet: device MAC address 26:05:ea:c0:66:16 stmmaceth f0008000.ethernet eth0: Register MEM_TYPE_PAGE_POOL RxQ-0 stmmaceth f0008000.ethernet eth0: PHY [stmmac-0:00] driver [Micrel KSZ9031 Gigabit PHY] (irq=POLL) stmmaceth f0008000.ethernet eth0: No Safety Features support found stmmaceth f0008000.ethernet eth0: PTP not supported by HW stmmaceth f0008000.ethernet eth0: configuring for phy/rgmii-id link mode stmmaceth f0008000.ethernet eth0: Link is Up - 1Gbps/Full - flow control off [1] arch/arc/boot/dts/hsdk.dts -- Shahab
Fixing the CC header. Apologies for the inconvenience. ------ Same happens on ARC HSDK [1]: # dmesg | grep stmmaceth stmmaceth f0008000.ethernet: use coherent DMA ops stmmaceth f0008000.ethernet: IRQ eth_wake_irq not found stmmaceth f0008000.ethernet: IRQ eth_lpi not found stmmaceth f0008000.ethernet: PTP uses main clock stmmaceth f0008000.ethernet: User ID: 0x10, Synopsys ID: 0x37 stmmaceth f0008000.ethernet: DWMAC1000 stmmaceth f0008000.ethernet: DMA HW capability register supported stmmaceth f0008000.ethernet: RX Checksum Offload Engine supported stmmaceth f0008000.ethernet: COE Type 2 stmmaceth f0008000.ethernet: TX Checksum insertion supported stmmaceth f0008000.ethernet: Normal descriptors stmmaceth f0008000.ethernet: Ring mode enabled stmmaceth f0008000.ethernet: Enable RX Mitigation via HW Watchdog Timer stmmaceth f0008000.ethernet: device MAC address 7e:14:df:5f:b8:78 stmmaceth f0008000.ethernet eth0: Register MEM_TYPE_PAGE_POOL RxQ-0 stmmaceth f0008000.ethernet eth0: PHY [stmmac-0:00] driver [Micrel KSZ9031 Gigabit PHY] (irq=POLL) stmmaceth f0008000.ethernet eth0: no phy found stmmaceth f0008000.ethernet eth0: __stmmac_open: Cannot attach to PHY (error: -19) After reverting this patch: # dmesg | grep stmmaceth stmmaceth f0008000.ethernet: use coherent DMA ops stmmaceth f0008000.ethernet: IRQ eth_wake_irq not found stmmaceth f0008000.ethernet: IRQ eth_lpi not found stmmaceth f0008000.ethernet: PTP uses main clock stmmaceth f0008000.ethernet: User ID: 0x10, Synopsys ID: 0x37 stmmaceth f0008000.ethernet: DWMAC1000 stmmaceth f0008000.ethernet: DMA HW capability register supported stmmaceth f0008000.ethernet: RX Checksum Offload Engine supported stmmaceth f0008000.ethernet: COE Type 2 stmmaceth f0008000.ethernet: TX Checksum insertion supported stmmaceth f0008000.ethernet: Normal descriptors stmmaceth f0008000.ethernet: Ring mode enabled stmmaceth f0008000.ethernet: Enable RX Mitigation via HW Watchdog Timer stmmaceth f0008000.ethernet: device MAC address 26:05:ea:c0:66:16 stmmaceth f0008000.ethernet eth0: Register MEM_TYPE_PAGE_POOL RxQ-0 stmmaceth f0008000.ethernet eth0: PHY [stmmac-0:00] driver [Micrel KSZ9031 Gigabit PHY] (irq=POLL) stmmaceth f0008000.ethernet eth0: No Safety Features support found stmmaceth f0008000.ethernet eth0: PTP not supported by HW stmmaceth f0008000.ethernet eth0: configuring for phy/rgmii-id link mode stmmaceth f0008000.ethernet eth0: Link is Up - 1Gbps/Full - flow control off [1] arch/arc/boot/dts/hsdk.dts -- Shahab
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c index 8f543c3ab5c5..41f0f3b74933 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c @@ -1135,6 +1135,7 @@ static int stmmac_init_phy(struct net_device *dev) { struct stmmac_priv *priv = netdev_priv(dev); struct fwnode_handle *fwnode; + bool phy_needed; int ret; fwnode = of_fwnode_handle(priv->plat->phylink_node); @@ -1144,10 +1145,11 @@ static int stmmac_init_phy(struct net_device *dev) if (fwnode) ret = phylink_fwnode_phy_connect(priv->phylink, fwnode, 0); + phy_needed = phylink_expects_phy(priv->phylink); /* Some DT bindings do not set-up the PHY handle. Let's try to * manually parse it */ - if (!fwnode || ret) { + if (!fwnode || phy_needed || ret) { int addr = priv->plat->phy_addr; struct phy_device *phydev;