Message ID | 20221024031351.4135651-6-peng.fan@oss.nxp.com |
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State | New |
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Received: from PA4PR04MB9416.eurprd04.prod.outlook.com (2603:10a6:102:2ab::21) by AM9PR04MB8340.eurprd04.prod.outlook.com (2603:10a6:20b:3e0::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5746.21; Mon, 24 Oct 2022 03:12:39 +0000 Received: from PA4PR04MB9416.eurprd04.prod.outlook.com ([fe80::9344:660:a20d:8a85]) by PA4PR04MB9416.eurprd04.prod.outlook.com ([fe80::9344:660:a20d:8a85%7]) with mapi id 15.20.5746.021; Mon, 24 Oct 2022 03:12:39 +0000 From: "Peng Fan (OSS)" <peng.fan@oss.nxp.com> To: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, shawnguo@kernel.org, s.hauer@pengutronix.de Cc: kernel@pengutronix.de, festevam@gmail.com, linux-imx@nxp.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Peng Fan <peng.fan@nxp.com> Subject: [PATCH V2 05/15] arm64: dts: imx8mp-evk: enable uart1/3 ports Date: Mon, 24 Oct 2022 11:13:41 +0800 Message-Id: <20221024031351.4135651-6-peng.fan@oss.nxp.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20221024031351.4135651-1-peng.fan@oss.nxp.com> References: <20221024031351.4135651-1-peng.fan@oss.nxp.com> Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: SG2PR02CA0042.apcprd02.prod.outlook.com (2603:1096:3:18::30) To PA4PR04MB9416.eurprd04.prod.outlook.com (2603:10a6:102:2ab::21) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: PA4PR04MB9416:EE_|AM9PR04MB8340:EE_ X-MS-Office365-Filtering-Correlation-Id: 0062bd97-de73-4d43-cf20-08dab56d9bc3 X-MS-Exchange-SharedMailbox-RoutingAgent-Processed: True X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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arm64: dts: imx8m-evk: misc dts update
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Commit Message
Peng Fan (OSS)
Oct. 24, 2022, 3:13 a.m. UTC
From: Peng Fan <peng.fan@nxp.com> Enable uart1/3 ports for evk board. Configure the clock to source from IMX8MP_SYS_PLL1_80M, because the uart could only support max 1.5M buadrate if using OSC_24M as clock source. Signed-off-by: Peng Fan <peng.fan@nxp.com> --- arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 36 ++++++++++++++++++++ 1 file changed, 36 insertions(+)
Comments
On 22-10-24, Peng Fan (OSS) wrote: > From: Peng Fan <peng.fan@nxp.com> > > Enable uart1/3 ports for evk board. > Configure the clock to source from IMX8MP_SYS_PLL1_80M, because the uart > could only support max 1.5M buadrate if using OSC_24M as clock source. > > Signed-off-by: Peng Fan <peng.fan@nxp.com> LGTM, feel free to add my: Reviewed-by: Marco Felsch <m.felsch@pengutronix.de> > --- > arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 36 ++++++++++++++++++++ > 1 file changed, 36 insertions(+) > > diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts > index 316390f917a4..b8a7de87ce4c 100644 > --- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts > +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts > @@ -428,6 +428,15 @@ &snvs_pwrkey { > status = "okay"; > }; > > +&uart1 { /* BT */ > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_uart1>; > + assigned-clocks = <&clk IMX8MP_CLK_UART1>; > + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; > + fsl,uart-has-rtscts; > + status = "okay"; > +}; > + > &uart2 { > /* console */ > pinctrl-names = "default"; > @@ -450,6 +459,15 @@ &usb_dwc3_1 { > status = "okay"; > }; > > +&uart3 { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_uart3>; > + assigned-clocks = <&clk IMX8MP_CLK_UART3>; > + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; > + fsl,uart-has-rtscts; > + status = "okay"; > +}; > + > &usdhc2 { > assigned-clocks = <&clk IMX8MP_CLK_USDHC2>; > assigned-clock-rates = <400000000>; > @@ -625,6 +643,15 @@ MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x40 > >; > }; > > + pinctrl_uart1: uart1grp { > + fsl,pins = < > + MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140 > + MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140 > + MX8MP_IOMUXC_UART3_RXD__UART1_DCE_CTS 0x140 > + MX8MP_IOMUXC_UART3_TXD__UART1_DCE_RTS 0x140 > + >; > + }; > + > pinctrl_uart2: uart2grp { > fsl,pins = < > MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x140 > @@ -638,6 +665,15 @@ MX8MP_IOMUXC_GPIO1_IO14__USB2_OTG_PWR 0x10 > >; > }; > > + pinctrl_uart3: uart3grp { > + fsl,pins = < > + MX8MP_IOMUXC_ECSPI1_SCLK__UART3_DCE_RX 0x140 > + MX8MP_IOMUXC_ECSPI1_MOSI__UART3_DCE_TX 0x140 > + MX8MP_IOMUXC_ECSPI1_SS0__UART3_DCE_RTS 0x140 > + MX8MP_IOMUXC_ECSPI1_MISO__UART3_DCE_CTS 0x140 > + >; > + }; > + > pinctrl_usdhc2: usdhc2grp { > fsl,pins = < > MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 > -- > 2.37.1 > > >
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts index 316390f917a4..b8a7de87ce4c 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts @@ -428,6 +428,15 @@ &snvs_pwrkey { status = "okay"; }; +&uart1 { /* BT */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + assigned-clocks = <&clk IMX8MP_CLK_UART1>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; + fsl,uart-has-rtscts; + status = "okay"; +}; + &uart2 { /* console */ pinctrl-names = "default"; @@ -450,6 +459,15 @@ &usb_dwc3_1 { status = "okay"; }; +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + assigned-clocks = <&clk IMX8MP_CLK_UART3>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; + fsl,uart-has-rtscts; + status = "okay"; +}; + &usdhc2 { assigned-clocks = <&clk IMX8MP_CLK_USDHC2>; assigned-clock-rates = <400000000>; @@ -625,6 +643,15 @@ MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x40 >; }; + pinctrl_uart1: uart1grp { + fsl,pins = < + MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140 + MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140 + MX8MP_IOMUXC_UART3_RXD__UART1_DCE_CTS 0x140 + MX8MP_IOMUXC_UART3_TXD__UART1_DCE_RTS 0x140 + >; + }; + pinctrl_uart2: uart2grp { fsl,pins = < MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x140 @@ -638,6 +665,15 @@ MX8MP_IOMUXC_GPIO1_IO14__USB2_OTG_PWR 0x10 >; }; + pinctrl_uart3: uart3grp { + fsl,pins = < + MX8MP_IOMUXC_ECSPI1_SCLK__UART3_DCE_RX 0x140 + MX8MP_IOMUXC_ECSPI1_MOSI__UART3_DCE_TX 0x140 + MX8MP_IOMUXC_ECSPI1_SS0__UART3_DCE_RTS 0x140 + MX8MP_IOMUXC_ECSPI1_MISO__UART3_DCE_CTS 0x140 + >; + }; + pinctrl_usdhc2: usdhc2grp { fsl,pins = < MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190