[v3,1/4] dts: arm64: qcom: sdm845: add SLPI remoteproc
Commit Message
Add the SLPI remoteproc to the SDM845 Qualcomm SoC which is responsible
for exposing the sensors connected to the SoC. The SLPI communicates
over GLink edge 'dsps' and is similar to other DSPs e.g. ADSP or CDSP.
This patch allows the SLPI to boot and expose itself over QRTR as
service 400.
Signed-off-by: Dylan Van Assche <me@dylanvanassche.be>
---
arch/arm64/boot/dts/qcom/sdm845.dtsi | 36 ++++++++++++++++++++++++++++
1 file changed, 36 insertions(+)
Comments
On 30/03/2023 18:53, Dylan Van Assche wrote:
> Add the SLPI remoteproc to the SDM845 Qualcomm SoC which is responsible
> for exposing the sensors connected to the SoC. The SLPI communicates
> over GLink edge 'dsps' and is similar to other DSPs e.g. ADSP or CDSP.
> This patch allows the SLPI to boot and expose itself over QRTR as
> service 400.
>
> Signed-off-by: Dylan Van Assche <me@dylanvanassche.be>
> ---
> arch/arm64/boot/dts/qcom/sdm845.dtsi | 36 ++++++++++++++++++++++++++++
> 1 file changed, 36 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
> index 2f32179c7d1b..3b547cb7aeb8 100644
> --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
> @@ -3311,6 +3311,42 @@ glink-edge {
> };
> };
>
> + slpi_pas: remoteproc@5c00000 {
This does not look like correct place. Are you sure you followed the
order by unit address?
Best regards,
Krzysztof
Hi Krzysztof,
On Fri, 2023-03-31 at 11:05 +0200, Krzysztof Kozlowski wrote:
> On 30/03/2023 18:53, Dylan Van Assche wrote:
> > Add the SLPI remoteproc to the SDM845 Qualcomm SoC which is
> > responsible
> > for exposing the sensors connected to the SoC. The SLPI
> > communicates
> > over GLink edge 'dsps' and is similar to other DSPs e.g. ADSP or
> > CDSP.
> > This patch allows the SLPI to boot and expose itself over QRTR as
> > service 400.
> >
> > Signed-off-by: Dylan Van Assche <me@dylanvanassche.be>
> > ---
> > arch/arm64/boot/dts/qcom/sdm845.dtsi | 36
> > ++++++++++++++++++++++++++++
> > 1 file changed, 36 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi
> > b/arch/arm64/boot/dts/qcom/sdm845.dtsi
> > index 2f32179c7d1b..3b547cb7aeb8 100644
> > --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
> > +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
> > @@ -3311,6 +3311,42 @@ glink-edge {
> > };
> > };
> >
> > + slpi_pas: remoteproc@5c00000 {
>
> This does not look like correct place. Are you sure you followed the
> order by unit address?
>
>
I think I misunderstood...
I sorted them alphabetically by name, but it has to be unit address.
Will fix in v4.
>
> Best regards,
> Krzysztof
>
Kind regards,
Dylan
@@ -3311,6 +3311,42 @@ glink-edge {
};
};
+ slpi_pas: remoteproc@5c00000 {
+ compatible = "qcom,sdm845-slpi-pas";
+ reg = <0 0x5c00000 0 0x4000>;
+
+ interrupts-extended = <&intc GIC_SPI 494 IRQ_TYPE_EDGE_RISING>,
+ <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
+ <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
+ <&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
+ <&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "wdog", "fatal", "ready",
+ "handover", "stop-ack";
+
+ clocks = <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "xo";
+
+ qcom,qmp = <&aoss_qmp>;
+
+ power-domains = <&rpmhpd SDM845_CX>,
+ <&rpmhpd SDM845_MX>;
+ power-domain-names = "lcx", "lmx";
+
+ memory-region = <&slpi_mem>;
+
+ qcom,smem-states = <&slpi_smp2p_out 0>;
+ qcom,smem-state-names = "stop";
+
+ status = "disabled";
+
+ glink-edge {
+ interrupts = <GIC_SPI 170 IRQ_TYPE_EDGE_RISING>;
+ label = "dsps";
+ qcom,remote-pid = <3>;
+ mboxes = <&apss_shared 24>;
+ };
+ };
+
gpucc: clock-controller@5090000 {
compatible = "qcom,sdm845-gpucc";
reg = <0 0x05090000 0 0x9000>;