Message ID | 20230207-iommu-support-v1-6-4a902f9aa412@baylibre.com |
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State | New |
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[93.5.22.158]) by smtp.googlemail.com with ESMTPSA id a18-20020a5d4d52000000b002d1e49cff35sm29667158wru.40.2023.03.29.02.52.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 Mar 2023 02:52:37 -0700 (PDT) From: Alexandre Mergnat <amergnat@baylibre.com> Date: Wed, 29 Mar 2023 11:52:25 +0200 Subject: [PATCH RESEND 6/6] arm64: dts: mediatek: add iommu support for mt8365 SoC MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20230207-iommu-support-v1-6-4a902f9aa412@baylibre.com> References: <20230207-iommu-support-v1-0-4a902f9aa412@baylibre.com> In-Reply-To: <20230207-iommu-support-v1-0-4a902f9aa412@baylibre.com> To: Yong Wu <yong.wu@mediatek.com>, Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>, Rob Herring <robh+dt@kernel.org>, Matthias Brugger <matthias.bgg@gmail.com>, AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org> Cc: linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Alexandre Mergnat <amergnat@baylibre.com> X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=966; i=amergnat@baylibre.com; h=from:subject:message-id; bh=nW+TPcLBymBQumCyH7WLeKWdyOoyUYLYkL7HqpljFxc=; b=owEBbQKS/ZANAwAKAStGSZ1+MdRFAcsmYgBkJApfW1/fAC/a3iYXOsk9RlBGKnGk0HAwAjRg6xvk hYEdgMSJAjMEAAEKAB0WIQQjG17X8+qqcA5g/osrRkmdfjHURQUCZCQKXwAKCRArRkmdfjHURQqyEA CvE6mTUTCNWwjiA70MqDxweWMM/VPe2qK6QHZGay3IFpYohw1Z5F04gtPUJsecxo0gCwGZERF26YMo +pZCs3d2+bVfxztMABmi7B4AGQcXpNISVGseGoyVNMVS8Dqd5RoIzl5vVA/vTKpwCPxWaxxuzBtLKT dSYTe5I6LK0jBbCzOw/VuJptjQUY6yX5eYUMNsW58ecrVWFsR72ZTSgiTCHdWBSrNeKFQI57W0yhXA 4jYf8PUNp2nJhwlapg7QIOueAaJynx9Xra5N17+jk0rVl2/rI3n3RsspgflsrWcOEuijUOcNCE7tYF DYGILJecNpQekLdvfjUW0QumB2teAHOk6iTg6hkwsN4TrjddhwvgFMbcK5YrBPyfkFZqLjMRPbSPyu SpW13uNZ6B1rSKpNlrDEseKj/ZX1mKxOrfZJIcxyz2AMW4gOlwynnD4Ry9rcdlmQJ8rhf9AgzMfwaP cUEpwnti33jNP1tlZrjZhnhiks3vxz4cED4nlyPUdpY9rVDimi+J2rgYejDmv66Q5kWyC+yfT/g1Ez aRDFtF4Mxamljws1Rr6xWldfSfurQ1rXxW+J4exwcrs0WVGH5LXS0TXqMxhAdTWx6sNJETzxqak7uV 9MbPXIrCMGpQMST4WJWhu8ioojdCaexIp7p2tgYEVerXHMe5arDLtq1XPSGg== X-Developer-Key: i=amergnat@baylibre.com; a=openpgp; fpr=231B5ED7F3EAAA700E60FE8B2B46499D7E31D445 X-Spam-Status: No, score=0.0 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: <linux-kernel.vger.kernel.org> X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1761695815596301188?= X-GMAIL-MSGID: =?utf-8?q?1761695815596301188?= |
Series |
Add IOMMU support to MT8365 SoC
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Commit Message
Alexandre Mergnat
March 29, 2023, 9:52 a.m. UTC
Add iommu support in the SoC DTS using the 4 local arbiters (LARBs)
Signed-off-by: Alexandre Mergnat <amergnat@baylibre.com>
---
arch/arm64/boot/dts/mediatek/mt8365.dtsi | 8 ++++++++
1 file changed, 8 insertions(+)
Comments
Il 29/03/23 11:52, Alexandre Mergnat ha scritto: > Add iommu support in the SoC DTS using the 4 local arbiters (LARBs) > > Signed-off-by: Alexandre Mergnat <amergnat@baylibre.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
On Wed, 2023-03-29 at 11:52 +0200, Alexandre Mergnat wrote: > > Add iommu support in the SoC DTS using the 4 local arbiters (LARBs) > > Signed-off-by: Alexandre Mergnat <amergnat@baylibre.com> Reviewed-by: Yong Wu <yong.wu@mediatek.com>
diff --git a/arch/arm64/boot/dts/mediatek/mt8365.dtsi b/arch/arm64/boot/dts/mediatek/mt8365.dtsi index db0b897f58bb..c713471c59dc 100644 --- a/arch/arm64/boot/dts/mediatek/mt8365.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8365.dtsi @@ -456,6 +456,14 @@ sysirq: interrupt-controller@10200a80 { reg = <0 0x10200a80 0 0x20>; }; + iommu: iommu@10205000 { + compatible = "mediatek,mt8365-m4u"; + reg = <0 0x10205000 0 0x1000>; + interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_LOW>; + mediatek,larbs = <&larb0>, <&larb1>, <&larb2>, <&larb3>; + #iommu-cells = <1>; + }; + infracfg_nao: infracfg@1020e000 { compatible = "mediatek,mt8365-infracfg", "syscon"; reg = <0 0x1020e000 0 0x1000>;