[RESEND,6/6] arm64: dts: mediatek: add iommu support for mt8365 SoC

Message ID 20230207-iommu-support-v1-6-4a902f9aa412@baylibre.com
State New
Headers
Series Add IOMMU support to MT8365 SoC |

Commit Message

Alexandre Mergnat March 29, 2023, 9:52 a.m. UTC
  Add iommu support in the SoC DTS using the 4 local arbiters (LARBs)

Signed-off-by: Alexandre Mergnat <amergnat@baylibre.com>
---
 arch/arm64/boot/dts/mediatek/mt8365.dtsi | 8 ++++++++
 1 file changed, 8 insertions(+)
  

Comments

AngeloGioacchino Del Regno March 29, 2023, 1:37 p.m. UTC | #1
Il 29/03/23 11:52, Alexandre Mergnat ha scritto:
> Add iommu support in the SoC DTS using the 4 local arbiters (LARBs)
> 
> Signed-off-by: Alexandre Mergnat <amergnat@baylibre.com>

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
  
Yong Wu March 30, 2023, 1:52 a.m. UTC | #2
On Wed, 2023-03-29 at 11:52 +0200, Alexandre Mergnat wrote:
> 
> Add iommu support in the SoC DTS using the 4 local arbiters (LARBs)
> 
> Signed-off-by: Alexandre Mergnat <amergnat@baylibre.com>

Reviewed-by: Yong Wu <yong.wu@mediatek.com>
  

Patch

diff --git a/arch/arm64/boot/dts/mediatek/mt8365.dtsi b/arch/arm64/boot/dts/mediatek/mt8365.dtsi
index db0b897f58bb..c713471c59dc 100644
--- a/arch/arm64/boot/dts/mediatek/mt8365.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8365.dtsi
@@ -456,6 +456,14 @@  sysirq: interrupt-controller@10200a80 {
 			reg = <0 0x10200a80 0 0x20>;
 		};
 
+		iommu: iommu@10205000 {
+			compatible = "mediatek,mt8365-m4u";
+			reg = <0 0x10205000 0 0x1000>;
+			interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_LOW>;
+			mediatek,larbs = <&larb0>, <&larb1>, <&larb2>, <&larb3>;
+			#iommu-cells = <1>;
+		};
+
 		infracfg_nao: infracfg@1020e000 {
 			compatible = "mediatek,mt8365-infracfg", "syscon";
 			reg = <0 0x1020e000 0 0x1000>;