[v2] iommu/mediatek: Set dma_mask for PGTABLE_PA_35_EN

Message ID 20230316064251.7346-1-yong.wu@mediatek.com
State New
Headers
Series [v2] iommu/mediatek: Set dma_mask for PGTABLE_PA_35_EN |

Commit Message

Yong Wu March 16, 2023, 6:42 a.m. UTC
  When we enable PGTABLE_PA_35_EN, the PA for pgtable may be 35bits.
Thus add dma_mask for it.

Fixes: 301c3ca12576 ("iommu/mediatek: Allow page table PA up to 35bit")
Signed-off-by: Chengci.Xu <chengci.xu@mediatek.com>
Signed-off-by: Yong Wu <yong.wu@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
v2: Just move this out from mt8188 series. Nothing change.

v1: https://lore.kernel.org/linux-mediatek/20230307080555.14399-3-yong.wu@mediatek.com/
---
 drivers/iommu/mtk_iommu.c | 8 ++++++++
 1 file changed, 8 insertions(+)
  

Comments

Joerg Roedel March 22, 2023, 2:32 p.m. UTC | #1
On Thu, Mar 16, 2023 at 02:42:51PM +0800, Yong Wu wrote:
>  drivers/iommu/mtk_iommu.c | 8 ++++++++
>  1 file changed, 8 insertions(+)

Applied, thanks.
  
Yong Wu March 23, 2023, 11:32 a.m. UTC | #2
On Wed, 2023-03-22 at 15:32 +0100, Joerg Roedel wrote:
> On Thu, Mar 16, 2023 at 02:42:51PM +0800, Yong Wu wrote:
> >  drivers/iommu/mtk_iommu.c | 8 ++++++++
> >  1 file changed, 8 insertions(+)
> 
> Applied, thanks.

Hi Joerg,

Thanks very much for the applying. I'm sorry I had a typo in this
version. Is it possible to use v3 instead?


https://lore.kernel.org/linux-iommu/20230316101445.12443-1-yong.wu@mediatek.com/
  
Joerg Roedel March 28, 2023, 1:18 p.m. UTC | #3
On Thu, Mar 23, 2023 at 11:32:38AM +0000, Yong Wu (吴勇) wrote:
> Thanks very much for the applying. I'm sorry I had a typo in this
> version. Is it possible to use v3 instead?

Done. Thanks for the heads-up.
  

Patch

diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
index d5a4955910ff..1a75b4382a92 100644
--- a/drivers/iommu/mtk_iommu.c
+++ b/drivers/iommu/mtk_iommu.c
@@ -1258,6 +1258,14 @@  static int mtk_iommu_probe(struct platform_device *pdev)
 			return PTR_ERR(data->bclk);
 	}
 
+	if (MTK_IOMMU_HAS_FLAG(data->plat_data, PGTABLE_PA_35_EN)) {
+		ret = dma_set_mask(dev, DMA_BIT_MASK(35));
+		if (!ret) {
+			dev_err(dev, "Failed to set dma_mask 35.\n");
+			return ret;
+		}
+	}
+
 	pm_runtime_enable(dev);
 
 	if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_MM)) {