[5/8] ARM: dts: at91-sama5d27_wlsom1: Set sst26vf064b SPI NOR flash at its maximum frequency
| Message ID | 20221117105249.115649-6-tudor.ambarus@microchip.com |
|---|---|
| State | New |
| Headers |
Return-Path: <linux-kernel-owner@vger.kernel.org>
Delivered-To: ouuuleilei@gmail.com
Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp331772wrr;
Thu, 17 Nov 2022 02:55:58 -0800 (PST)
X-Google-Smtp-Source:
AA0mqf4smzIT7qJhHMPgBG4iA7I5Ma0Fj2Oj0pNGtbRAHowadqPeHOsu5zdZLqkeY7d+w1P5dkpk
X-Received: by 2002:a17:906:eb54:b0:7ae:415:3fb5 with SMTP id
mc20-20020a170906eb5400b007ae04153fb5mr1555682ejb.255.1668682557905;
Thu, 17 Nov 2022 02:55:57 -0800 (PST)
ARC-Seal: i=1; a=rsa-sha256; t=1668682557; cv=none;
d=google.com; s=arc-20160816;
b=kz8e8ru2XgMrWkRbsUxrDPG+SJlC21b7Dor1mHfDJoMG5t1CkElynK3Q27xBLhsw39
mAHCt1KGUpsvVxhuySHCvavbuqnCXOqnZc4KALFIhJY/u/WXXaOMbzpJigtdK0axsRsI
tr+juHznxp4JJJxJ8SADpSPNjnJ9VQZ19y0STgMEL8HTs2L81aOru9Qa0hzrObEKMybc
4P/AK3KMS2QeEAyerxXo/Q8ZaVzhuN7cGA2wfIlDb0yxUDt5ccpVY8dLIP4641ekYUiW
rJ/OHooyeo+iG8xhHYQ9voh+F6EaQopg/l8BEA7iv1GtDdW22NIJymy+stc/MD6Gr3KR
5vjQ==
ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com;
s=arc-20160816;
h=list-id:precedence:content-transfer-encoding:mime-version
:references:in-reply-to:message-id:date:subject:cc:to:from
:dkim-signature;
bh=GDE8ClJ6PkxhwVCALsq32DTIjfDnSooH/tbirMBUgaw=;
b=jQnLxvEk9uwwmunzCrueElf54N9pxF97f5ImDxi40yKD5eGW7LU6cwAJcCcNJkKJBb
3+rRBDmAER7cRkd3fd8wyKmLzauUut24VwVqrUc0lT031g18liQr5vLZqM6hiqEwDr80
Jod2glBu+RYBfacJ7eIn9CHFpb4mzoM4NcVqBVcS1stt7YSSmejmRyJt8vQ+jLKibBSJ
6gbgs0M9dAbR3YyR7D7byyoeil6DXpPLG2JNJlynST41Rw23yuIjyM86BOCUUW7dmptl
k/dA/FoecM8yo8VTSx1W8T2HXiuY+Tg1AnoKqGOvJQsFU/1fHd/WNLO1/AVs35Ky+bk9
D2oQ==
ARC-Authentication-Results: i=1; mx.google.com;
dkim=pass header.i=@microchip.com header.s=mchp header.b="ZyH/St2N";
spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org
designates 2620:137:e000::1:20 as permitted sender)
smtp.mailfrom=linux-kernel-owner@vger.kernel.org;
dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE)
header.from=microchip.com
Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20])
by mx.google.com with ESMTP id
dt17-20020a170907729100b007317ad1f9a4si317648ejc.310.2022.11.17.02.55.34;
Thu, 17 Nov 2022 02:55:57 -0800 (PST)
Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org
designates 2620:137:e000::1:20 as permitted sender)
client-ip=2620:137:e000::1:20;
Authentication-Results: mx.google.com;
dkim=pass header.i=@microchip.com header.s=mchp header.b="ZyH/St2N";
spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org
designates 2620:137:e000::1:20 as permitted sender)
smtp.mailfrom=linux-kernel-owner@vger.kernel.org;
dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE)
header.from=microchip.com
Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand
id S239690AbiKQKyU (ORCPT <rfc822;just.gull.subs@gmail.com>
+ 99 others); Thu, 17 Nov 2022 05:54:20 -0500
Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42138 "EHLO
lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org
with ESMTP id S239524AbiKQKxR (ORCPT
<rfc822;linux-kernel@vger.kernel.org>);
Thu, 17 Nov 2022 05:53:17 -0500
Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com
[68.232.153.233])
by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EFC165B5AD;
Thu, 17 Nov 2022 02:53:10 -0800 (PST)
DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple;
d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp;
t=1668682391; x=1700218391;
h=from:to:cc:subject:date:message-id:in-reply-to:
references:mime-version:content-transfer-encoding;
bh=V+B/oow35dGgcpcT99slHtwXN+81/1x8fB2BGyRH3ZM=;
b=ZyH/St2Np4muxa8WcdPP+tqUDbW62bytbVIg57RPAfYBLXX4nOwXB0NJ
98RvqoA+csqF0/mhcogdD6+gdI5VSrS9GiQshykWWp78cV5dsjUf80cLg
RXJlaY/gkPvgYCz2yITrX0HwF6qkMvRGJhJycK5C8cFcDVJLaw9QmWCmF
i/txwxacyY15VENiIUq5IifkFfReoygh458Uot6roxbJpjoerwJy0hbUI
w/H81gb2AtxluaP0KxT9Fc8PEIuINrmLRmHNcwGDX7tO8ZF/4+LH2mvcZ
CDHNOrTRzk792uGMKik/AEfTtNY2+tGhHrNLPiaZof11SoYcTqYvEpco7
g==;
X-IronPort-AV: E=Sophos;i="5.96,171,1665471600";
d="scan'208";a="189356168"
Received: from unknown (HELO email.microchip.com) ([170.129.1.10])
by esa5.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256;
17 Nov 2022 03:53:11 -0700
Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by
chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server
(version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id
15.1.2507.12; Thu, 17 Nov 2022 03:53:08 -0700
Received: from ROB-ULT-M18064N.mchp-main.com (10.10.115.15) by
chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id
15.1.2507.12 via Frontend Transport; Thu, 17 Nov 2022 03:53:06 -0700
From: Tudor Ambarus <tudor.ambarus@microchip.com>
To: <broonie@kernel.org>, <robh+dt@kernel.org>,
<krzysztof.kozlowski+dt@linaro.org>, <nicolas.ferre@microchip.com>,
<alexandre.belloni@bootlin.com>, <claudiu.beznea@microchip.com>
CC: <linux-spi@vger.kernel.org>, <devicetree@vger.kernel.org>,
<linux-kernel@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-mtd@lists.infradead.org>,
Tudor Ambarus <tudor.ambarus@microchip.com>
Subject: [PATCH 5/8] ARM: dts: at91-sama5d27_wlsom1: Set sst26vf064b SPI NOR
flash at its maximum frequency
Date: Thu, 17 Nov 2022 12:52:46 +0200
Message-ID: <20221117105249.115649-6-tudor.ambarus@microchip.com>
X-Mailer: git-send-email 2.25.1
In-Reply-To: <20221117105249.115649-1-tudor.ambarus@microchip.com>
References: <20221117105249.115649-1-tudor.ambarus@microchip.com>
MIME-Version: 1.0
Content-Transfer-Encoding: 8bit
Content-Type: text/plain
X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH,
DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,
RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_PASS autolearn=ham
autolearn_force=no version=3.4.6
X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on
lindbergh.monkeyblade.net
Precedence: bulk
List-ID: <linux-kernel.vger.kernel.org>
X-Mailing-List: linux-kernel@vger.kernel.org
X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?=
X-GMAIL-THRID: =?utf-8?q?1749740481563422745?=
X-GMAIL-MSGID: =?utf-8?q?1749740481563422745?=
|
| Series |
spi: Introduce spi-cs-setup-ns dt property
|
|
Commit Message
Tudor Ambarus
Nov. 17, 2022, 10:52 a.m. UTC
sama5d27-wlsom1 populates an sst26vf064b SPI NOR flash. Its maximum
operating frequency for 2.7-3.6V is 104 MHz. As the flash is operated
at 3.3V, increase its maximum supported frequency to 104MHz. The
increasing of the spi-max-frequency value requires the setting of the
"CE# Not Active Hold Time", thus set the spi-cs-setup-ns to a value of 7.
The sst26vf064b datasheet specifies just a minimum value for the
"CE# Not Active Hold Time" and it advertises it to 5 ns. There's no
maximum time specified. I determined experimentally that 5 ns for the
spi-cs-setup-ns is not enough when the flash is operated close to its
maximum frequency and tests showed that 7 ns is just fine, so set the
spi-cs-setup-ns dt property to 7.
With the increase of frequency the reads are now faster with ~37%.
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
---
arch/arm/boot/dts/at91-sama5d27_wlsom1.dtsi | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
Comments
Hi Tudor, On 17/11/2022 at 11:52, Tudor Ambarus wrote: > sama5d27-wlsom1 populates an sst26vf064b SPI NOR flash. Its maximum > operating frequency for 2.7-3.6V is 104 MHz. As the flash is operated > at 3.3V, increase its maximum supported frequency to 104MHz. The > increasing of the spi-max-frequency value requires the setting of the > "CE# Not Active Hold Time", thus set the spi-cs-setup-ns to a value of 7. > > The sst26vf064b datasheet specifies just a minimum value for the > "CE# Not Active Hold Time" and it advertises it to 5 ns. There's no > maximum time specified. I determined experimentally that 5 ns for the > spi-cs-setup-ns is not enough when the flash is operated close to its > maximum frequency and tests showed that 7 ns is just fine, so set the > spi-cs-setup-ns dt property to 7. > > With the increase of frequency the reads are now faster with ~37%. > > Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> > --- > arch/arm/boot/dts/at91-sama5d27_wlsom1.dtsi | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/arch/arm/boot/dts/at91-sama5d27_wlsom1.dtsi b/arch/arm/boot/dts/at91-sama5d27_wlsom1.dtsi > index 83bcf9fe0152..20caf40b4755 100644 > --- a/arch/arm/boot/dts/at91-sama5d27_wlsom1.dtsi > +++ b/arch/arm/boot/dts/at91-sama5d27_wlsom1.dtsi > @@ -220,7 +220,8 @@ qspi1_flash: flash@0 { > #size-cells = <1>; > compatible = "jedec,spi-nor"; > reg = <0>; > - spi-max-frequency = <80000000>; > + spi-max-frequency = <104000000>; > + spi-cs-setup-ns = /bits/ 16 <7>; Following the different changes that happened to this property after this post, am I right saying that this must now be changed to: spi-cs-setup-delay-ns = <7>; ? Thanks for your insight. Best regards, Nicolas > spi-rx-bus-width = <4>; > spi-tx-bus-width = <4>; > m25p,fast-read;
On 3/28/23 09:51, Nicolas Ferre wrote: > Hi Tudor, Hi! > > On 17/11/2022 at 11:52, Tudor Ambarus wrote: >> sama5d27-wlsom1 populates an sst26vf064b SPI NOR flash. Its maximum >> operating frequency for 2.7-3.6V is 104 MHz. As the flash is operated >> at 3.3V, increase its maximum supported frequency to 104MHz. The >> increasing of the spi-max-frequency value requires the setting of the >> "CE# Not Active Hold Time", thus set the spi-cs-setup-ns to a value of 7. >> >> The sst26vf064b datasheet specifies just a minimum value for the >> "CE# Not Active Hold Time" and it advertises it to 5 ns. There's no >> maximum time specified. I determined experimentally that 5 ns for the >> spi-cs-setup-ns is not enough when the flash is operated close to its >> maximum frequency and tests showed that 7 ns is just fine, so set the >> spi-cs-setup-ns dt property to 7. >> >> With the increase of frequency the reads are now faster with ~37%. >> >> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> >> --- >> arch/arm/boot/dts/at91-sama5d27_wlsom1.dtsi | 3 ++- >> 1 file changed, 2 insertions(+), 1 deletion(-) >> >> diff --git a/arch/arm/boot/dts/at91-sama5d27_wlsom1.dtsi >> b/arch/arm/boot/dts/at91-sama5d27_wlsom1.dtsi >> index 83bcf9fe0152..20caf40b4755 100644 >> --- a/arch/arm/boot/dts/at91-sama5d27_wlsom1.dtsi >> +++ b/arch/arm/boot/dts/at91-sama5d27_wlsom1.dtsi >> @@ -220,7 +220,8 @@ qspi1_flash: flash@0 { >> #size-cells = <1>; >> compatible = "jedec,spi-nor"; >> reg = <0>; >> - spi-max-frequency = <80000000>; >> + spi-max-frequency = <104000000>; >> + spi-cs-setup-ns = /bits/ 16 <7>; > > Following the different changes that happened to this property after > this post, am I right saying that this must now be changed to: > > spi-cs-setup-delay-ns = <7>; > > ? > Yes, that should do it. I'm amending the series right now. Can you do a little test on your side so that we make sure everything is in place? After the update, something like that should be run on any board (maybe wlsom1-ek?): #!/bin/sh dd if=/dev/urandom of=./qspi_test bs=1M count=6 mtd_debug write /dev/mtd5 0 6291456 qspi_test mtd_debug erase /dev/mtd5 0 6291456 mtd_debug read /dev/mtd5 0 6291456 qspi_read hexdump qspi_read mtd_debug write /dev/mtd5 0 6291456 qspi_test mtd_debug read /dev/mtd5 0 6291456 qspi_read sha1sum qspi_test qspi_read brb, ta
diff --git a/arch/arm/boot/dts/at91-sama5d27_wlsom1.dtsi b/arch/arm/boot/dts/at91-sama5d27_wlsom1.dtsi index 83bcf9fe0152..20caf40b4755 100644 --- a/arch/arm/boot/dts/at91-sama5d27_wlsom1.dtsi +++ b/arch/arm/boot/dts/at91-sama5d27_wlsom1.dtsi @@ -220,7 +220,8 @@ qspi1_flash: flash@0 { #size-cells = <1>; compatible = "jedec,spi-nor"; reg = <0>; - spi-max-frequency = <80000000>; + spi-max-frequency = <104000000>; + spi-cs-setup-ns = /bits/ 16 <7>; spi-rx-bus-width = <4>; spi-tx-bus-width = <4>; m25p,fast-read;