[v4,1/3] dt-bindings: usb: cdns-imx8qm: add imx8qm cdns3 glue layer
Commit Message
NXP imx8qm integrates 1 cdns3 IP. This is glue layer device bindings.
Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
Change from v3 to v4
- Drop all clock-assign
Change from v2 to v3
- Drop two fixed frequency clocks, it is system reset value, no need set now.
If need, futher work/discuss on driver or dts change. It will not block this
basic enablement work.
- Drop lable
- Drop some descriptions
- Reg as second property.
Change from v1 to v2.
- new add binding doc
.../bindings/usb/fsl,imx8qm-cdns3.yaml | 104 ++++++++++++++++++
1 file changed, 104 insertions(+)
create mode 100644 Documentation/devicetree/bindings/usb/fsl,imx8qm-cdns3.yaml
Comments
On 23/03/2023 17:31, Frank Li wrote:
> NXP imx8qm integrates 1 cdns3 IP. This is glue layer device bindings.
>
> Signed-off-by: Frank Li <Frank.Li@nxp.com>
> ---
> Change from v3 to v4
> - Drop all clock-assign
>
> Change from v2 to v3
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
On Thu, Mar 23, 2023 at 12:31:14PM -0400, Frank Li wrote:
> NXP imx8qm integrates 1 cdns3 IP. This is glue layer device bindings.
>
> Signed-off-by: Frank Li <Frank.Li@nxp.com>
> ---
> Change from v3 to v4
> - Drop all clock-assign
>
> Change from v2 to v3
> - Drop two fixed frequency clocks, it is system reset value, no need set now.
> If need, futher work/discuss on driver or dts change. It will not block this
> basic enablement work.
> - Drop lable
> - Drop some descriptions
> - Reg as second property.
>
> Change from v1 to v2.
> - new add binding doc
>
> .../bindings/usb/fsl,imx8qm-cdns3.yaml | 104 ++++++++++++++++++
> 1 file changed, 104 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/usb/fsl,imx8qm-cdns3.yaml
>
> diff --git a/Documentation/devicetree/bindings/usb/fsl,imx8qm-cdns3.yaml b/Documentation/devicetree/bindings/usb/fsl,imx8qm-cdns3.yaml
> new file mode 100644
> index 000000000000..654d8704aa6f
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/usb/fsl,imx8qm-cdns3.yaml
> @@ -0,0 +1,104 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +# Copyright (c) 2020 NXP
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/usb/fsl,imx8qm-cdns3.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: NXP iMX8QM Soc USB Controller
> +
> +maintainers:
> + - Frank Li <Frank.Li@nxp.com>
> +
> +properties:
> + compatible:
> + const: fsl,imx8qm-usb3
> +
> + reg:
> + items:
> + - description: Register set for iMX USB3 Platform Control
> +
> + "#address-cells":
> + enum: [ 1, 2 ]
> +
> + "#size-cells":
> + enum: [ 1, 2 ]
> +
> + ranges: true
> +
> + clocks:
> + items:
> + - description: Standby clock. Used during ultra low power states.
> + - description: USB bus clock for usb3 controller.
> + - description: AXI clock for AXI interface.
> + - description: ipg clock for register access.
> + - description: Core clock for usb3 controller.
> +
> + clock-names:
> + items:
> + - const: usb3_lpm_clk
> + - const: usb3_bus_clk
> + - const: usb3_aclk
> + - const: usb3_ipg_clk
> + - const: usb3_core_pclk
lpm, bus, aclk, ipg, core (or core_pclk) are sufficient.
> +
> + power-domains:
> + maxItems: 1
> +
> +# Required child node:
> +
> +patternProperties:
> + "^usb@[0-9a-f]+$":
> + $ref: cdns,usb3.yaml#
> +
> +required:
> + - compatible
> + - reg
> + - "#address-cells"
> + - "#size-cells"
> + - ranges
> + - clocks
> + - clock-names
> + - power-domains
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/imx8-lpcg.h>
> + #include <dt-bindings/firmware/imx/rsrc.h>
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> + usb@5b110000 {
> + compatible = "fsl,imx8qm-usb3";
> + reg = <0x5b110000 0x10000>;
> + ranges;
> + clocks = <&usb3_lpcg IMX_LPCG_CLK_1>,
> + <&usb3_lpcg IMX_LPCG_CLK_0>,
> + <&usb3_lpcg IMX_LPCG_CLK_7>,
> + <&usb3_lpcg IMX_LPCG_CLK_4>,
> + <&usb3_lpcg IMX_LPCG_CLK_5>;
> + clock-names = "usb3_lpm_clk", "usb3_bus_clk", "usb3_aclk",
> + "usb3_ipg_clk", "usb3_core_pclk";
> + assigned-clocks = <&clk IMX_SC_R_USB_2 IMX_SC_PM_CLK_MST_BUS>;
> + assigned-clock-rates = <250000000>;
> + power-domains = <&pd IMX_SC_R_USB_2>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + usb@5b120000 {
> + compatible = "cdns,usb3";
> + reg = <0x5b120000 0x10000>, /* memory area for OTG/DRD registers */
> + <0x5b130000 0x10000>, /* memory area for HOST registers */
> + <0x5b140000 0x10000>; /* memory area for DEVICE registers */
> + reg-names = "otg", "xhci", "dev";
> + interrupt-parent = <&gic>;
> + interrupts = <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "host", "peripheral", "otg", "wakeup";
> + phys = <&usb3_phy>;
> + phy-names = "cdns3,usb3-phy";
> + };
> + };
> --
> 2.34.1
>
new file mode 100644
@@ -0,0 +1,104 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (c) 2020 NXP
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/usb/fsl,imx8qm-cdns3.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NXP iMX8QM Soc USB Controller
+
+maintainers:
+ - Frank Li <Frank.Li@nxp.com>
+
+properties:
+ compatible:
+ const: fsl,imx8qm-usb3
+
+ reg:
+ items:
+ - description: Register set for iMX USB3 Platform Control
+
+ "#address-cells":
+ enum: [ 1, 2 ]
+
+ "#size-cells":
+ enum: [ 1, 2 ]
+
+ ranges: true
+
+ clocks:
+ items:
+ - description: Standby clock. Used during ultra low power states.
+ - description: USB bus clock for usb3 controller.
+ - description: AXI clock for AXI interface.
+ - description: ipg clock for register access.
+ - description: Core clock for usb3 controller.
+
+ clock-names:
+ items:
+ - const: usb3_lpm_clk
+ - const: usb3_bus_clk
+ - const: usb3_aclk
+ - const: usb3_ipg_clk
+ - const: usb3_core_pclk
+
+ power-domains:
+ maxItems: 1
+
+# Required child node:
+
+patternProperties:
+ "^usb@[0-9a-f]+$":
+ $ref: cdns,usb3.yaml#
+
+required:
+ - compatible
+ - reg
+ - "#address-cells"
+ - "#size-cells"
+ - ranges
+ - clocks
+ - clock-names
+ - power-domains
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/imx8-lpcg.h>
+ #include <dt-bindings/firmware/imx/rsrc.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ usb@5b110000 {
+ compatible = "fsl,imx8qm-usb3";
+ reg = <0x5b110000 0x10000>;
+ ranges;
+ clocks = <&usb3_lpcg IMX_LPCG_CLK_1>,
+ <&usb3_lpcg IMX_LPCG_CLK_0>,
+ <&usb3_lpcg IMX_LPCG_CLK_7>,
+ <&usb3_lpcg IMX_LPCG_CLK_4>,
+ <&usb3_lpcg IMX_LPCG_CLK_5>;
+ clock-names = "usb3_lpm_clk", "usb3_bus_clk", "usb3_aclk",
+ "usb3_ipg_clk", "usb3_core_pclk";
+ assigned-clocks = <&clk IMX_SC_R_USB_2 IMX_SC_PM_CLK_MST_BUS>;
+ assigned-clock-rates = <250000000>;
+ power-domains = <&pd IMX_SC_R_USB_2>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ usb@5b120000 {
+ compatible = "cdns,usb3";
+ reg = <0x5b120000 0x10000>, /* memory area for OTG/DRD registers */
+ <0x5b130000 0x10000>, /* memory area for HOST registers */
+ <0x5b140000 0x10000>; /* memory area for DEVICE registers */
+ reg-names = "otg", "xhci", "dev";
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "host", "peripheral", "otg", "wakeup";
+ phys = <&usb3_phy>;
+ phy-names = "cdns3,usb3-phy";
+ };
+ };