Message ID | 1718196085461c37138c194c49146efa5c5503dc.1666288432.git.quic_asutoshd@quicinc.com |
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Bottomley" <jejb@linux.ibm.com>, "open list" <linux-kernel@vger.kernel.org> Subject: [PATCH v3 03/17] ufs: core: Introduce Multi-circular queue capability Date: Thu, 20 Oct 2022 11:03:32 -0700 Message-ID: <1718196085461c37138c194c49146efa5c5503dc.1666288432.git.quic_asutoshd@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <cover.1666288432.git.quic_asutoshd@quicinc.com> References: <cover.1666288432.git.quic_asutoshd@quicinc.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01a.na.qualcomm.com (10.52.223.231) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: 0POcqdq33VyLsn9Biasy7DYf6Vz9ZUgF X-Proofpoint-ORIG-GUID: 0POcqdq33VyLsn9Biasy7DYf6Vz9ZUgF X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2022-10-20_09,2022-10-20_01,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 malwarescore=0 spamscore=0 lowpriorityscore=0 priorityscore=1501 mlxlogscore=999 impostorscore=0 bulkscore=0 clxscore=1015 mlxscore=0 adultscore=0 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2209130000 definitions=main-2210200108 X-Spam-Status: No, score=-2.8 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_LOW,SPF_HELO_NONE, SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: <linux-kernel.vger.kernel.org> X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1747230923736484153?= X-GMAIL-MSGID: =?utf-8?q?1747230923736484153?= |
Series |
[v3,01/17] ufs: core: Probe for ext_iid support
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Commit Message
Asutosh Das
Oct. 20, 2022, 6:03 p.m. UTC
Add support to check for MCQ capability in the UFSHC. This capability can be used by host drivers to control MCQ enablement. Co-developed-by: Can Guo <quic_cang@quicinc.com> Signed-off-by: Can Guo <quic_cang@quicinc.com> Signed-off-by: Asutosh Das <quic_asutoshd@quicinc.com> --- drivers/ufs/core/ufshcd.c | 4 ++++ include/ufs/ufshcd.h | 13 +++++++++++++ 2 files changed, 17 insertions(+)
Comments
On 10/20/22 11:03, Asutosh Das wrote: > + > + /* > + * This capability allows the host controller driver to turn on/off > + * MCQ mode. MCQ mode may be used to increase performance. > + */ > + UFSHCD_CAP_MCQ_EN = 1 << 12, > }; I prefer that the above flag would only be introduced after a need appears to disable MCQ, e.g. discovery of a host controller that is too broken to enable MCQ. Since UFSHCI 4.0 controllers must support UFSHCI 3.0, shouldn't users have a way to disable MCQ, e.g. via a kernel module parameter? Thanks, Bart.
On Thu, Oct 27 2022 at 14:10 -0700, Bart Van Assche wrote: >On 10/20/22 11:03, Asutosh Das wrote: >>+ >>+ /* >>+ * This capability allows the host controller driver to turn on/off >>+ * MCQ mode. MCQ mode may be used to increase performance. >>+ */ >>+ UFSHCD_CAP_MCQ_EN = 1 << 12, >> }; > >I prefer that the above flag would only be introduced after a need >appears to disable MCQ, e.g. discovery of a host controller that is >too broken to enable MCQ. > I think this flag is useful during chip bring-ups &/or debugs. Considering that this is a fairly new hardware block even though the HC supports MCQ there could be times to keep it disabled. >Since UFSHCI 4.0 controllers must support UFSHCI 3.0, shouldn't users >have a way to disable MCQ, e.g. via a kernel module parameter? > I can add a kernel module parameter to disable MCQ. I think adding it to host driver (e.g. ufs-qcom) would be good. Please let me know if you have a better place in mind. >Thanks, > >Bart.
On 10/28/22 09:51, Asutosh Das wrote: > On Thu, Oct 27 2022 at 14:10 -0700, Bart Van Assche wrote: >> Since UFSHCI 4.0 controllers must support UFSHCI 3.0, shouldn't users >> have a way to disable MCQ, e.g. via a kernel module parameter? >> > I can add a kernel module parameter to disable MCQ. > I think adding it to host driver (e.g. ufs-qcom) would be good. > Please let me know if you have a better place in mind. Since this functionality is useful for all host controllers please add it in the core UFS host controller driver (drivers/ufs/core/ufshcd.c). Thanks, Bart.
> > On 10/20/22 11:03, Asutosh Das wrote: > > + > > + /* > > + * This capability allows the host controller driver to turn on/off > > + * MCQ mode. MCQ mode may be used to increase performance. > > + */ > > + UFSHCD_CAP_MCQ_EN = 1 << 12, Needs rebase? UFSHCD_CAP_WB_WITH_CLK_SCALING already occupies that bit. Thanks, Avri > > }; > > I prefer that the above flag would only be introduced after a need > appears to disable MCQ, e.g. discovery of a host controller that is too > broken to enable MCQ. > > Since UFSHCI 4.0 controllers must support UFSHCI 3.0, shouldn't users > have a way to disable MCQ, e.g. via a kernel module parameter? > > Thanks, > > Bart.
diff --git a/drivers/ufs/core/ufshcd.c b/drivers/ufs/core/ufshcd.c index e2be3f4..8d93797 100644 --- a/drivers/ufs/core/ufshcd.c +++ b/drivers/ufs/core/ufshcd.c @@ -2250,6 +2250,10 @@ static inline int ufshcd_hba_capabilities(struct ufs_hba *hba) if (err) dev_err(hba->dev, "crypto setup failed\n"); + hba->mcq_sup = FIELD_GET(MASK_MCQ_SUPPORT, hba->capabilities); + if (!hba->mcq_sup) + return err; + hba->mcq_capabilities = ufshcd_readl(hba, REG_MCQCAP); hba->ext_iid_sup = FIELD_GET(MASK_EXT_IID_SUPPORT, hba->mcq_capabilities); diff --git a/include/ufs/ufshcd.h b/include/ufs/ufshcd.h index c29f4c8..e779bc6 100644 --- a/include/ufs/ufshcd.h +++ b/include/ufs/ufshcd.h @@ -660,6 +660,12 @@ enum ufshcd_caps { * notification if it is supported by the UFS device. */ UFSHCD_CAP_TEMP_NOTIF = 1 << 11, + + /* + * This capability allows the host controller driver to turn on/off + * MCQ mode. MCQ mode may be used to increase performance. + */ + UFSHCD_CAP_MCQ_EN = 1 << 12, }; struct ufs_hba_variant_params { @@ -820,6 +826,7 @@ struct ufs_hba_monitor { * @complete_put: whether or not to call ufshcd_rpm_put() from inside * ufshcd_resume_complete() * @ext_iid_sup: is EXT_IID is supported by UFSHC + * @mcq_sup: is mcq supported by UFSHC */ struct ufs_hba { void __iomem *mmio_base; @@ -969,8 +976,14 @@ struct ufs_hba { u32 luns_avail; bool complete_put; bool ext_iid_sup; + bool mcq_sup; }; +static inline bool is_mcq_supported(struct ufs_hba *hba) +{ + return hba->mcq_sup && (hba->caps & UFSHCD_CAP_MCQ_EN); +} + /* Returns true if clocks can be gated. Otherwise false */ static inline bool ufshcd_is_clkgating_allowed(struct ufs_hba *hba) {