diff mbox series

[3/4] arm64/signal: Add tpidr2/za/zt sigframe size in comment

Message ID 20230317124915.1263-4-sundongxu3@huawei.com
State New
Headers
Series arm64: Use specific checking for TPIDR2 and some comments update |

Commit Message

sundongxu (A) March 17, 2023, 12:49 p.m. UTC 
  Update the comments of sigcontext.__reserved[], since we already
support SME/SME2.

Signed-off-by: Dongxu Sun <sundongxu3@huawei.com>
---
 arch/arm64/include/uapi/asm/sigcontext.h | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

Comments

Mark Brown March 17, 2023, 1:03 p.m. UTC | #1 
On Fri, Mar 17, 2023 at 08:49:14PM +0800, Dongxu Sun wrote:

>   *	0x8a0		sve_context (vl <= 64) (optional)
> + *	 0x10		tpidr2_context (optional)
> + *	 0x10		za_context (optional)

The size of the ZA context is variable, going with what the SVE has a VL
which might fit into the base context should be included but that's
complicated what with it likely appearing after another variably sized
frame.

> + *	 0x10		zt_context (optional)

The ZT context is never this small, it's always got register contents if
present.

>   *	 0x20		extra_context (optional)
>   *	 0x10		terminator (null _aarch64_ctx)
>   *
> - *	0x510		(reserved for future allocation)
> + *	0x4e0		(reserved for future allocation)

TBH I'm not sure this comment is actually useful or helpful, it's
already not fully taking into account the variablility of the SVE frame
size (quoting a fixed value) and with the way we allocate things once
we've gone into the extra_context we'll allocate new frames from there
so even smaller frames like the tpidr2_context will go there.  I'm not
sure trying to suggest a layout/ordering is clarifying anything for
anyone.
sundongxu (A) March 22, 2023, 2:42 a.m. UTC | #2 
On 2023/3/17 21:03, Mark Brown wrote:
> On Fri, Mar 17, 2023 at 08:49:14PM +0800, Dongxu Sun wrote:
> 
>>   *	0x8a0		sve_context (vl <= 64) (optional)
>> + *	 0x10		tpidr2_context (optional)
>> + *	 0x10		za_context (optional)
> 
> The size of the ZA context is variable, going with what the SVE has a VL
> which might fit into the base context should be included but that's
> complicated what with it likely appearing after another variably sized
> frame.
> 
>> + *	 0x10		zt_context (optional)
> 
> The ZT context is never this small, it's always got register contents if
> present.

The context size of ZA and ZT here is wrong due to oversight. The ZA context size is related to the SVL, and the ZT context size may also get changed with further extensions.
> 
>>   *	 0x20		extra_context (optional)
>>   *	 0x10		terminator (null _aarch64_ctx)
>>   *
>> - *	0x510		(reserved for future allocation)
>> + *	0x4e0		(reserved for future allocation)
> 
> TBH I'm not sure this comment is actually useful or helpful, it's
> already not fully taking into account the variablility of the SVE frame
> size (quoting a fixed value) and with the way we allocate things once
> we've gone into the extra_context we'll allocate new frames from there
> so even smaller frames like the tpidr2_context will go there.  I'm not
> sure trying to suggest a layout/ordering is clarifying anything for
> anyone.

Thanks for your point, considering the scalability of SME/SME2, maybe there is no need to add layout suggestion. So, let's discard this commit:)

Thanks，
Dongxu
diff mbox series

Patch

diff --git a/arch/arm64/include/uapi/asm/sigcontext.h b/arch/arm64/include/uapi/asm/sigcontext.h
index 656a10ea6c67..d85e3079474d 100644
--- a/arch/arm64/include/uapi/asm/sigcontext.h
+++ b/arch/arm64/include/uapi/asm/sigcontext.h
@@ -45,10 +45,13 @@  struct sigcontext {
  *	0x210		fpsimd_context
  *	 0x10		esr_context
  *	0x8a0		sve_context (vl <= 64) (optional)
+ *	 0x10		tpidr2_context (optional)
+ *	 0x10		za_context (optional)
+ *	 0x10		zt_context (optional)
  *	 0x20		extra_context (optional)
  *	 0x10		terminator (null _aarch64_ctx)
  *
- *	0x510		(reserved for future allocation)
+ *	0x4e0		(reserved for future allocation)
  *
  * New records that can exceed this space need to be opt-in for userspace, so
  * that an expanded signal frame is not generated unexpectedly.  The mechanism