Message ID | 20230315-topic-lagoon_gpu-v1-2-a74cbec4ecfc@linaro.org |
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State | New |
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[83.9.29.16]) by smtp.gmail.com with ESMTPSA id u28-20020ac243dc000000b004db2978e330sm1194222lfl.258.2023.03.16.04.17.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 16 Mar 2023 04:17:10 -0700 (PDT) From: Konrad Dybcio <konrad.dybcio@linaro.org> Date: Thu, 16 Mar 2023 12:16:57 +0100 Subject: [PATCH 2/5] arm64: dts: qcom: sm6350: Add GPUCC node MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20230315-topic-lagoon_gpu-v1-2-a74cbec4ecfc@linaro.org> References: <20230315-topic-lagoon_gpu-v1-0-a74cbec4ecfc@linaro.org> In-Reply-To: <20230315-topic-lagoon_gpu-v1-0-a74cbec4ecfc@linaro.org> To: Bjorn Andersson <andersson@kernel.org>, Andy Gross <agross@kernel.org>, Michael Turquette <mturquette@baylibre.com>, Stephen Boyd <sboyd@kernel.org>, Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Cc: Marijn Suijten <marijn.suijten@somainline.org>, Rob Herring <robh@kernel.org>, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio <konrad.dybcio@linaro.org>, Konrad Dybcio <konrad.dybcio@somainline.org> X-Mailer: b4 0.12.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1678965426; l=1355; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=T20D47wMamblhuymG4piRjU7EdKqlSdzz5tYbFiNa2w=; b=qHCpq8IzdrchOe9Nka2ARSw2XI8dsUnV0vG4qZ9B79vhLm1Y2OdA9GLcppgj/Ea2IjD8mSL68RjO NGIm8Kc7DgxE3QNAfwdeVvpcUpRPCVwsth7JCOHBK1UYKKIjtmry X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-Spam-Status: No, score=-0.2 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, RCVD_IN_SORBS_HTTP,RCVD_IN_SORBS_SOCKS,SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: <linux-kernel.vger.kernel.org> X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1760523271267249344?= X-GMAIL-MSGID: =?utf-8?q?1760523271267249344?= |
Series | SM6350 GPU | |
Commit Message
Konrad Dybcio
March 16, 2023, 11:16 a.m. UTC
From: Konrad Dybcio <konrad.dybcio@somainline.org> Add and configure a node for the GPU clock controller. Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> --- arch/arm64/boot/dts/qcom/sm6350.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+)
Comments
On Thu Mar 16, 2023 at 12:16 PM CET, Konrad Dybcio wrote: > From: Konrad Dybcio <konrad.dybcio@somainline.org> > > Add and configure a node for the GPU clock controller. > > Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> > Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Luca Weiss <luca.weiss@fairphone.com> > --- > arch/arm64/boot/dts/qcom/sm6350.dtsi | 15 +++++++++++++++ > 1 file changed, 15 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi > index c46bb6dab6a1..523c7edfa4b3 100644 > --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi > @@ -5,6 +5,7 @@ > */ > > #include <dt-bindings/clock/qcom,gcc-sm6350.h> > +#include <dt-bindings/clock/qcom,gpucc-sm6350.h> > #include <dt-bindings/clock/qcom,rpmh.h> > #include <dt-bindings/clock/qcom,sm6350-camcc.h> > #include <dt-bindings/dma/qcom-gpi.h> > @@ -1125,6 +1126,20 @@ compute-cb@5 { > }; > }; > > + gpucc: clock-controller@3d90000 { > + compatible = "qcom,sm6350-gpucc"; > + reg = <0 0x03d90000 0 0x9000>; > + clocks = <&rpmhcc RPMH_CXO_CLK>, > + <&gcc GCC_GPU_GPLL0_CLK>, > + <&gcc GCC_GPU_GPLL0_DIV_CLK>; > + clock-names = "bi_tcxo", > + "gcc_gpu_gpll0_clk", > + "gcc_gpu_gpll0_div_clk"; > + #clock-cells = <1>; > + #reset-cells = <1>; > + #power-domain-cells = <1>; > + }; > + > mpss: remoteproc@4080000 { > compatible = "qcom,sm6350-mpss-pas"; > reg = <0x0 0x04080000 0x0 0x4040>; > > -- > 2.39.2
diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi index c46bb6dab6a1..523c7edfa4b3 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -5,6 +5,7 @@ */ #include <dt-bindings/clock/qcom,gcc-sm6350.h> +#include <dt-bindings/clock/qcom,gpucc-sm6350.h> #include <dt-bindings/clock/qcom,rpmh.h> #include <dt-bindings/clock/qcom,sm6350-camcc.h> #include <dt-bindings/dma/qcom-gpi.h> @@ -1125,6 +1126,20 @@ compute-cb@5 { }; }; + gpucc: clock-controller@3d90000 { + compatible = "qcom,sm6350-gpucc"; + reg = <0 0x03d90000 0 0x9000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_GPU_GPLL0_CLK>, + <&gcc GCC_GPU_GPLL0_DIV_CLK>; + clock-names = "bi_tcxo", + "gcc_gpu_gpll0_clk", + "gcc_gpu_gpll0_div_clk"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + mpss: remoteproc@4080000 { compatible = "qcom,sm6350-mpss-pas"; reg = <0x0 0x04080000 0x0 0x4040>;