Message ID | 20230315-topic-kamorta_adrsmmu-v1-1-d1c0dea90bd9@linaro.org |
---|---|
State | New |
Headers |
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[83.9.29.16]) by smtp.gmail.com with ESMTPSA id q3-20020ac25fc3000000b004d856fe5121sm767791lfg.194.2023.03.15.03.52.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Mar 2023 03:52:13 -0700 (PDT) From: Konrad Dybcio <konrad.dybcio@linaro.org> Date: Wed, 15 Mar 2023 11:52:08 +0100 Subject: [PATCH 1/2] dt-bindings: arm-smmu: Document SM61[12]5 GPU SMMU MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20230315-topic-kamorta_adrsmmu-v1-1-d1c0dea90bd9@linaro.org> References: <20230315-topic-kamorta_adrsmmu-v1-0-d1c0dea90bd9@linaro.org> In-Reply-To: <20230315-topic-kamorta_adrsmmu-v1-0-d1c0dea90bd9@linaro.org> To: Will Deacon <will@kernel.org>, Robin Murphy <robin.murphy@arm.com>, Joerg Roedel <joro@8bytes.org>, Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Andy Gross <agross@kernel.org>, Bjorn Andersson <andersson@kernel.org> Cc: Marijn Suijten <marijn.suijten@somainline.org>, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, Konrad Dybcio <konrad.dybcio@linaro.org> X-Mailer: b4 0.12.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1678877530; l=2607; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=JaZgFPnneZ9HeE1XCgzUVaq2L6fgv/yMBSZREyHciPk=; b=48Y0l+WzxQs+J6eAfEUnHyzPTYixLUt3M2Rwl5Wjv2xfr7A36Ze5/S2CuGUaF3mMhSsxRylG5ps7 gKNRazM3B660iLR1/7lohJ6QuscG1v1OLkNhjtCwlcP+3YbpnbyT X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-Spam-Status: No, score=-0.2 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, RCVD_IN_SORBS_HTTP,RCVD_IN_SORBS_SOCKS,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: <linux-kernel.vger.kernel.org> X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1760431584510737122?= X-GMAIL-MSGID: =?utf-8?q?1760431584510737122?= |
Series |
SM6115 GPU SMMU
|
|
Commit Message
Konrad Dybcio
March 15, 2023, 10:52 a.m. UTC
Both of these SoCs have a Qualcomm MMU500 implementation of SMMU
in front of their GPUs that expect 3 clocks. Both of them also have
an APPS SMMU that expects no clocks. Remove qcom,sm61[12]5-smmu-500
from the "no clocks" list (intentionally 'breaking' the schema checks
of APPS SMMU, as now it *can* accept clocks - with the current
structure of this file it would have taken a wastefully-long time to
sort this out properly..) and add necessary yaml to describe the
clocks required by the GPU SMMUs.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
.../devicetree/bindings/iommu/arm,smmu.yaml | 28 ++++++++++++++++++++--
1 file changed, 26 insertions(+), 2 deletions(-)
Comments
On 15/03/2023 11:52, Konrad Dybcio wrote: > Both of these SoCs have a Qualcomm MMU500 implementation of SMMU > in front of their GPUs that expect 3 clocks. Both of them also have > an APPS SMMU that expects no clocks. Remove qcom,sm61[12]5-smmu-500 > from the "no clocks" list (intentionally 'breaking' the schema checks > of APPS SMMU, as now it *can* accept clocks - with the current > structure of this file it would have taken a wastefully-long time to > sort this out properly..) and add necessary yaml to describe the > clocks required by the GPU SMMUs. > + properties: > + compatible: > + items: > + - enum: > + - qcom,sm6115-smmu-500 > + - qcom,sm6125-smmu-500 > + - const: qcom,adreno-smmu > + - const: qcom,smmu-500 > + - const: arm,mmu-500 If you drop the hunk later (from allOf:if), then what clocks do you expect for non-GPU SMMU? > + then: > + properties: > + clock-names: > + items: > + - const: mem > + - const: hlos > + - const: iface > + > + clocks: > + items: > + - description: GPU memory bus clock > + - description: Voter clock required for HLOS SMMU access > + - description: Interface clock required for register access > + > # Disallow clocks for all other platforms with specific compatibles > - if: > properties: > @@ -394,8 +420,6 @@ allOf: > - qcom,sdm845-smmu-500 > - qcom,sdx55-smmu-500 > - qcom,sdx65-smmu-500 > - - qcom,sm6115-smmu-500 > - - qcom,sm6125-smmu-500 > - qcom,sm6350-smmu-500 > - qcom,sm6375-smmu-500 > - qcom,sm8350-smmu-500 > Best regards, Krzysztof
On 16.03.2023 20:29, Krzysztof Kozlowski wrote: > On 15/03/2023 11:52, Konrad Dybcio wrote: >> Both of these SoCs have a Qualcomm MMU500 implementation of SMMU >> in front of their GPUs that expect 3 clocks. Both of them also have >> an APPS SMMU that expects no clocks. Remove qcom,sm61[12]5-smmu-500 >> from the "no clocks" list (intentionally 'breaking' the schema checks >> of APPS SMMU, as now it *can* accept clocks - with the current >> structure of this file it would have taken a wastefully-long time to >> sort this out properly..) and add necessary yaml to describe the >> clocks required by the GPU SMMUs. > > >> + properties: >> + compatible: >> + items: >> + - enum: >> + - qcom,sm6115-smmu-500 >> + - qcom,sm6125-smmu-500 >> + - const: qcom,adreno-smmu >> + - const: qcom,smmu-500 >> + - const: arm,mmu-500 > > If you drop the hunk later (from allOf:if), then what clocks do you > expect for non-GPU SMMU? Both 6115 and 6125 require no clocks under the APPS (non-GPU) SMMU. However, the list below uses a `contains:` which means I'd have to add a whole another hunk like - items: - enum: - qcom,sm6115-smmu-500 - qcom,sm6125-smmu-500 - const: qcom,smmu-500 - const: arm,mmu-500 and add another level of indentation to the previous one I figured skipping that was less messy (I think we discussed this once as well), but if you prefer to keep it strict, I can. Konrad > >> + then: >> + properties: >> + clock-names: >> + items: >> + - const: mem >> + - const: hlos >> + - const: iface >> + >> + clocks: >> + items: >> + - description: GPU memory bus clock >> + - description: Voter clock required for HLOS SMMU access >> + - description: Interface clock required for register access >> + >> # Disallow clocks for all other platforms with specific compatibles >> - if: >> properties: >> @@ -394,8 +420,6 @@ allOf: >> - qcom,sdm845-smmu-500 >> - qcom,sdx55-smmu-500 >> - qcom,sdx65-smmu-500 >> - - qcom,sm6115-smmu-500 >> - - qcom,sm6125-smmu-500 >> - qcom,sm6350-smmu-500 >> - qcom,sm6375-smmu-500 >> - qcom,sm8350-smmu-500 >> > > Best regards, > Krzysztof >
On 16/03/2023 22:59, Konrad Dybcio wrote: > > > On 16.03.2023 20:29, Krzysztof Kozlowski wrote: >> On 15/03/2023 11:52, Konrad Dybcio wrote: >>> Both of these SoCs have a Qualcomm MMU500 implementation of SMMU >>> in front of their GPUs that expect 3 clocks. Both of them also have >>> an APPS SMMU that expects no clocks. Remove qcom,sm61[12]5-smmu-500 >>> from the "no clocks" list (intentionally 'breaking' the schema checks >>> of APPS SMMU, as now it *can* accept clocks - with the current >>> structure of this file it would have taken a wastefully-long time to >>> sort this out properly..) and add necessary yaml to describe the >>> clocks required by the GPU SMMUs. >> >> >>> + properties: >>> + compatible: >>> + items: >>> + - enum: >>> + - qcom,sm6115-smmu-500 >>> + - qcom,sm6125-smmu-500 >>> + - const: qcom,adreno-smmu >>> + - const: qcom,smmu-500 >>> + - const: arm,mmu-500 >> >> If you drop the hunk later (from allOf:if), then what clocks do you >> expect for non-GPU SMMU? > Both 6115 and 6125 require no clocks under the APPS (non-GPU) SMMU. > However, the list below uses a `contains:` which means I'd have > to add a whole another hunk like > > - items: > - enum: > - qcom,sm6115-smmu-500 > - qcom,sm6125-smmu-500 > - const: qcom,smmu-500 > - const: arm,mmu-500 > > and add another level of indentation to the previous one > > I figured skipping that was less messy (I think we discussed this > once as well), but if you prefer to keep it strict, I can. Nah, ok, it's fine. Best regards, Krzysztof
On 15/03/2023 11:52, Konrad Dybcio wrote: > Both of these SoCs have a Qualcomm MMU500 implementation of SMMU > in front of their GPUs that expect 3 clocks. Both of them also have > an APPS SMMU that expects no clocks. Remove qcom,sm61[12]5-smmu-500 > from the "no clocks" list (intentionally 'breaking' the schema checks > of APPS SMMU, as now it *can* accept clocks - with the current > structure of this file it would have taken a wastefully-long time to > sort this out properly..) and add necessary yaml to describe the > clocks required by the GPU SMMUs. > > Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> > --- Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Best regards, Krzysztof
diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml index a6224b7e5310..62c7a5ff148e 100644 --- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml @@ -79,6 +79,8 @@ properties: items: - enum: - qcom,sc7280-smmu-500 + - qcom,sm6115-smmu-500 + - qcom,sm6125-smmu-500 - qcom,sm8150-smmu-500 - qcom,sm8250-smmu-500 - qcom,sm8350-smmu-500 @@ -375,6 +377,30 @@ allOf: - description: interface clock required to access smmu's registers through the TCU's programming interface. + - if: + properties: + compatible: + items: + - enum: + - qcom,sm6115-smmu-500 + - qcom,sm6125-smmu-500 + - const: qcom,adreno-smmu + - const: qcom,smmu-500 + - const: arm,mmu-500 + then: + properties: + clock-names: + items: + - const: mem + - const: hlos + - const: iface + + clocks: + items: + - description: GPU memory bus clock + - description: Voter clock required for HLOS SMMU access + - description: Interface clock required for register access + # Disallow clocks for all other platforms with specific compatibles - if: properties: @@ -394,8 +420,6 @@ allOf: - qcom,sdm845-smmu-500 - qcom,sdx55-smmu-500 - qcom,sdx65-smmu-500 - - qcom,sm6115-smmu-500 - - qcom,sm6125-smmu-500 - qcom,sm6350-smmu-500 - qcom,sm6375-smmu-500 - qcom,sm8350-smmu-500