Message ID | 20230308012854.294939-1-konrad.dybcio@linaro.org |
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State | New |
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[83.9.29.16]) by smtp.gmail.com with ESMTPSA id u17-20020ac25191000000b004db3aa3c542sm2174173lfi.47.2023.03.07.17.28.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Mar 2023 17:28:59 -0800 (PST) From: Konrad Dybcio <konrad.dybcio@linaro.org> To: linux-arm-msm@vger.kernel.org, andersson@kernel.org, agross@kernel.org Cc: marijn.suijten@somainline.org, Konrad Dybcio <konrad.dybcio@linaro.org>, Daniel Lezcano <daniel.lezcano@linaro.org>, Thomas Gleixner <tglx@linutronix.de>, Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Marc Zyngier <maz@kernel.org>, Mark Rutland <mark.rutland@arm.com>, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH] dt-bindings: timer: armv7: Don't sanction address/size-cells values Date: Wed, 8 Mar 2023 02:28:53 +0100 Message-Id: <20230308012854.294939-1-konrad.dybcio@linaro.org> X-Mailer: git-send-email 2.39.2 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-0.2 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, RCVD_IN_SORBS_HTTP,RCVD_IN_SORBS_SOCKS,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: <linux-kernel.vger.kernel.org> X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1759763311310220945?= X-GMAIL-MSGID: =?utf-8?q?1759763311310220945?= |
Series |
dt-bindings: timer: armv7: Don't sanction address/size-cells values
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Commit Message
Konrad Dybcio
March 8, 2023, 1:28 a.m. UTC
The driver itself does not read the -cells values (and frankly, it
shouldn't), so there's little sense in only allowing [1, 2] x [1].
Allow any values.
Fixes: 4d2bb3e65035 ("dt-bindings: timer: Convert ARM timer bindings to json-schema")
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
.../devicetree/bindings/timer/arm,arch_timer_mmio.yaml | 6 ++----
1 file changed, 2 insertions(+), 4 deletions(-)
Comments
On Wed, Mar 08, 2023 at 02:28:53AM +0100, Konrad Dybcio wrote: > The driver itself does not read the -cells values (and frankly, it > shouldn't), Agreed, because this is standard address translation and only the DT core address functions should read cells props. > so there's little sense in only allowing [1, 2] x [1]. Why does the timer need 64-bits of address space? It doesn't, so that's the reason for restricting it. > Allow any values. > > Fixes: 4d2bb3e65035 ("dt-bindings: timer: Convert ARM timer bindings to json-schema") > Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> > --- > .../devicetree/bindings/timer/arm,arch_timer_mmio.yaml | 6 ++---- > 1 file changed, 2 insertions(+), 4 deletions(-) > > diff --git a/Documentation/devicetree/bindings/timer/arm,arch_timer_mmio.yaml b/Documentation/devicetree/bindings/timer/arm,arch_timer_mmio.yaml > index f6efa48c4256..236e2a05c1ad 100644 > --- a/Documentation/devicetree/bindings/timer/arm,arch_timer_mmio.yaml > +++ b/Documentation/devicetree/bindings/timer/arm,arch_timer_mmio.yaml > @@ -26,11 +26,9 @@ properties: > maxItems: 1 > description: The control frame base address > > - '#address-cells': > - enum: [1, 2] > + '#address-cells': true So 3 address cells is valid? Until recently (and not yet in a dtschema release), there was no constraint on #address-cells or #size-cells values other than the #.*-cells constraint of 8. Now it is 3 and 2. > > - '#size-cells': > - const: 1 > + '#size-cells': true > > ranges: true > > -- > 2.39.2 >
On 16.03.2023 23:47, Rob Herring wrote: > On Wed, Mar 08, 2023 at 02:28:53AM +0100, Konrad Dybcio wrote: >> The driver itself does not read the -cells values (and frankly, it >> shouldn't), > > Agreed, because this is standard address translation and only the DT > core address functions should read cells props. > >> so there's little sense in only allowing [1, 2] x [1]. > > Why does the timer need 64-bits of address space? It doesn't, so that's > the reason for restricting it. > >> Allow any values. >> >> Fixes: 4d2bb3e65035 ("dt-bindings: timer: Convert ARM timer bindings to json-schema") >> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> >> --- >> .../devicetree/bindings/timer/arm,arch_timer_mmio.yaml | 6 ++---- >> 1 file changed, 2 insertions(+), 4 deletions(-) >> >> diff --git a/Documentation/devicetree/bindings/timer/arm,arch_timer_mmio.yaml b/Documentation/devicetree/bindings/timer/arm,arch_timer_mmio.yaml >> index f6efa48c4256..236e2a05c1ad 100644 >> --- a/Documentation/devicetree/bindings/timer/arm,arch_timer_mmio.yaml >> +++ b/Documentation/devicetree/bindings/timer/arm,arch_timer_mmio.yaml >> @@ -26,11 +26,9 @@ properties: >> maxItems: 1 >> description: The control frame base address >> >> - '#address-cells': >> - enum: [1, 2] >> + '#address-cells': true > > So 3 address cells is valid? > > Until recently (and not yet in a dtschema release), there was no > constraint on #address-cells or #size-cells values other than the > #.*-cells constraint of 8. Now it is 3 and 2. Okay, I didn't know that. I suppose we can forget about this patch. Konrad > >> >> - '#size-cells': >> - const: 1 >> + '#size-cells': true >> >> ranges: true >> >> -- >> 2.39.2 >>
diff --git a/Documentation/devicetree/bindings/timer/arm,arch_timer_mmio.yaml b/Documentation/devicetree/bindings/timer/arm,arch_timer_mmio.yaml index f6efa48c4256..236e2a05c1ad 100644 --- a/Documentation/devicetree/bindings/timer/arm,arch_timer_mmio.yaml +++ b/Documentation/devicetree/bindings/timer/arm,arch_timer_mmio.yaml @@ -26,11 +26,9 @@ properties: maxItems: 1 description: The control frame base address - '#address-cells': - enum: [1, 2] + '#address-cells': true - '#size-cells': - const: 1 + '#size-cells': true ranges: true