[1/3] dt-bindings: clock: qcom: Add bindings for videocc on SM8450
Commit Message
Add device tree bindings for the video clock controller on Qualcomm
SM8450 platform.
Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
---
.../bindings/clock/qcom,sm8450-videocc.yaml | 84 +++++++++++++++++++
.../dt-bindings/clock/qcom,videocc-sm8450.h | 38 +++++++++
2 files changed, 122 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml
create mode 100644 include/dt-bindings/clock/qcom,videocc-sm8450.h
Comments
On 16/03/2023 09:30, Taniya Das wrote:
> Add device tree bindings for the video clock controller on Qualcomm
> SM8450 platform.
Subject: drop second/last, redundant "bindings for". The "dt-bindings"
prefix is already stating that these are bindings.
>
> Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
> ---
> .../bindings/clock/qcom,sm8450-videocc.yaml | 84 +++++++++++++++++++
> .../dt-bindings/clock/qcom,videocc-sm8450.h | 38 +++++++++
> 2 files changed, 122 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml
> create mode 100644 include/dt-bindings/clock/qcom,videocc-sm8450.h
>
> diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml
> new file mode 100644
> index 000000000000..909da704c123
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml
> @@ -0,0 +1,84 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/qcom,sm8450-videocc.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm Video Clock & Reset Controller on SM8450
> +
> +maintainers:
> + - Taniya Das <quic_tdas@quicinc.com>
> +
> +description: |
> + Qualcomm video clock control module provides the clocks, resets and power
> + domains on SM8450.
> +
> + See also:: include/dt-bindings/clock/qcom,videocc-sm8450.h
> +
> +properties:
> + compatible:
> + const: qcom,sm8450-videocc
> +
> + clocks:
> + items:
> + - description: Video AHB clock from GCC
> + - description: Board XO source
> +
> + clock-names:
> + items:
> + - const: iface
> + - const: bi_tcxo
> +
> + power-domains:
> + maxItems: 1
> + description:
> + A phandle and PM domain specifier for the MMCX power domain.
Drop "A phandle and PM domain specifier for the"
> +
> + required-opps:
> + maxItems: 1
> + description:
> + A phandle to an OPP node describing required MMCX performance point.
> +
> + '#clock-cells':
> + const: 1
> +
> + '#reset-cells':
> + const: 1
> +
> + '#power-domain-cells':
> + const: 1
> +
> + reg:
> + maxItems: 1
That's a unusual ordering. Either order elements by name or use some
custom order... but then reg is always second property.
> +
> +required:
> + - compatible
> + - reg
> + - clocks
> + - clock-names
> + - power-domains
> + - required-opps
> + - '#clock-cells'
> + - '#reset-cells'
> + - '#power-domain-cells'
And keep same order in required.
> +
> +additionalProperties: false
Best regards,
Krzysztof
Hi Krzysztof,
Thank you for the review.
On 3/17/2023 1:04 AM, Krzysztof Kozlowski wrote:
> On 16/03/2023 09:30, Taniya Das wrote:
>> Add device tree bindings for the video clock controller on Qualcomm
>> SM8450 platform.
>
> Subject: drop second/last, redundant "bindings for". The "dt-bindings"
> prefix is already stating that these are bindings.
>
sure, will update it in the next patch.
>>
>> Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
>> ---
>> .../bindings/clock/qcom,sm8450-videocc.yaml | 84 +++++++++++++++++++
>> .../dt-bindings/clock/qcom,videocc-sm8450.h | 38 +++++++++
>> 2 files changed, 122 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml
>> create mode 100644 include/dt-bindings/clock/qcom,videocc-sm8450.h
>>
>> diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml
>> new file mode 100644
>> index 000000000000..909da704c123
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml
>> @@ -0,0 +1,84 @@
>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/clock/qcom,sm8450-videocc.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: Qualcomm Video Clock & Reset Controller on SM8450
>> +
>> +maintainers:
>> + - Taniya Das <quic_tdas@quicinc.com>
>> +
>> +description: |
>> + Qualcomm video clock control module provides the clocks, resets and power
>> + domains on SM8450.
>> +
>> + See also:: include/dt-bindings/clock/qcom,videocc-sm8450.h
>> +
>> +properties:
>> + compatible:
>> + const: qcom,sm8450-videocc
>> +
>> + clocks:
>> + items:
>> + - description: Video AHB clock from GCC
>> + - description: Board XO source
>> +
>> + clock-names:
>> + items:
>> + - const: iface
>> + - const: bi_tcxo
>> +
>> + power-domains:
>> + maxItems: 1
>> + description:
>> + A phandle and PM domain specifier for the MMCX power domain.
>
> Drop "A phandle and PM domain specifier for the"
>
Done.
>> +
>> + required-opps:
>> + maxItems: 1
>> + description:
>> + A phandle to an OPP node describing required MMCX performance point.
>> +
>> + '#clock-cells':
>> + const: 1
>> +
>> + '#reset-cells':
>> + const: 1
>> +
>> + '#power-domain-cells':
>> + const: 1
>> +
>> + reg:
>> + maxItems: 1
>
> That's a unusual ordering. Either order elements by name or use some
> custom order... but then reg is always second property.
>
Will fix in the next patch set.
>> +
>> +required:
>> + - compatible
>> + - reg
>> + - clocks
>> + - clock-names
>> + - power-domains
>> + - required-opps
>> + - '#clock-cells'
>> + - '#reset-cells'
>> + - '#power-domain-cells'
>
> And keep same order in required.
>
Done.
>> +
>> +additionalProperties: false
>
>
> Best regards,
> Krzysztof
>
new file mode 100644
@@ -0,0 +1,84 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,sm8450-videocc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Video Clock & Reset Controller on SM8450
+
+maintainers:
+ - Taniya Das <quic_tdas@quicinc.com>
+
+description: |
+ Qualcomm video clock control module provides the clocks, resets and power
+ domains on SM8450.
+
+ See also:: include/dt-bindings/clock/qcom,videocc-sm8450.h
+
+properties:
+ compatible:
+ const: qcom,sm8450-videocc
+
+ clocks:
+ items:
+ - description: Video AHB clock from GCC
+ - description: Board XO source
+
+ clock-names:
+ items:
+ - const: iface
+ - const: bi_tcxo
+
+ power-domains:
+ maxItems: 1
+ description:
+ A phandle and PM domain specifier for the MMCX power domain.
+
+ required-opps:
+ maxItems: 1
+ description:
+ A phandle to an OPP node describing required MMCX performance point.
+
+ '#clock-cells':
+ const: 1
+
+ '#reset-cells':
+ const: 1
+
+ '#power-domain-cells':
+ const: 1
+
+ reg:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - power-domains
+ - required-opps
+ - '#clock-cells'
+ - '#reset-cells'
+ - '#power-domain-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,gcc-sm8450.h>
+ #include <dt-bindings/clock/qcom,rpmh.h>
+ #include <dt-bindings/power/qcom-rpmpd.h>
+ videocc: clock-controller@aaf0000 {
+ compatible = "qcom,sm8450-videocc";
+ reg = <0x0aaf0000 0x10000>;
+ clocks = <&gcc GCC_VIDEO_AHB_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "iface", "bi_tcxo";
+ power-domains = <&rpmhpd SM8450_MMCX>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+...
new file mode 100644
@@ -0,0 +1,38 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_VIDEO_CC_SM8450_H
+#define _DT_BINDINGS_CLK_QCOM_VIDEO_CC_SM8450_H
+
+/* VIDEO_CC clocks */
+#define VIDEO_CC_MVS0_CLK 0
+#define VIDEO_CC_MVS0_CLK_SRC 1
+#define VIDEO_CC_MVS0_DIV_CLK_SRC 2
+#define VIDEO_CC_MVS0C_CLK 3
+#define VIDEO_CC_MVS0C_DIV2_DIV_CLK_SRC 4
+#define VIDEO_CC_MVS1_CLK 5
+#define VIDEO_CC_MVS1_CLK_SRC 6
+#define VIDEO_CC_MVS1_DIV_CLK_SRC 7
+#define VIDEO_CC_MVS1C_CLK 8
+#define VIDEO_CC_MVS1C_DIV2_DIV_CLK_SRC 9
+#define VIDEO_CC_PLL0 10
+#define VIDEO_CC_PLL1 11
+
+/* VIDEO_CC power domains */
+#define VIDEO_CC_MVS0C_GDSC 0
+#define VIDEO_CC_MVS0_GDSC 1
+#define VIDEO_CC_MVS1C_GDSC 2
+#define VIDEO_CC_MVS1_GDSC 3
+
+/* VIDEO_CC resets */
+#define CVP_VIDEO_CC_INTERFACE_BCR 0
+#define CVP_VIDEO_CC_MVS0_BCR 1
+#define CVP_VIDEO_CC_MVS0C_BCR 2
+#define CVP_VIDEO_CC_MVS1_BCR 3
+#define CVP_VIDEO_CC_MVS1C_BCR 4
+#define VIDEO_CC_MVS0C_CLK_ARES 5
+#define VIDEO_CC_MVS1C_CLK_ARES 6
+
+#endif