diff mbox series

[4/5] arm64: dts: qcom: sm6350: Add GPU nodes

Message ID	20230315-topic-lagoon_gpu-v1-4-a74cbec4ecfc@linaro.org
State	New
Headers	Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; From: Konrad Dybcio <konrad.dybcio@linaro.org> Date: Thu, 16 Mar 2023 12:16:59 +0100 Subject: [PATCH 4/5] arm64: dts: qcom: sm6350: Add GPU nodes MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20230315-topic-lagoon_gpu-v1-4-a74cbec4ecfc@linaro.org> References: <20230315-topic-lagoon_gpu-v1-0-a74cbec4ecfc@linaro.org> In-Reply-To: <20230315-topic-lagoon_gpu-v1-0-a74cbec4ecfc@linaro.org> To: Bjorn Andersson <andersson@kernel.org>, Andy Gross <agross@kernel.org>, Michael Turquette <mturquette@baylibre.com>, Stephen Boyd <sboyd@kernel.org>, Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Cc: Marijn Suijten <marijn.suijten@somainline.org>, Rob Herring <robh@kernel.org>, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio <konrad.dybcio@linaro.org>, Konrad Dybcio <konrad.dybcio@somainline.org>, Luca Weiss <luca.weiss@fairphone.com> Precedence: bulk
Series	SM6350 GPU \| [0/5] SM6350 GPU [1/5] dt-bindings: clock: qcom,gpucc: Fix SM6350 clock names [2/5] arm64: dts: qcom: sm6350: Add GPUCC node [3/5] arm64: dts: qcom: sm6350: Add QFPROM node [4/5] arm64: dts: qcom: sm6350: Add GPU nodes [5/5] arm64: dts: qcom: sm6350: Fix ZAP region

Commit Message

Konrad Dybcio March 16, 2023, 11:16 a.m. UTC

  From: Konrad Dybcio <konrad.dybcio@somainline.org>

Add Adreno, GPU SMMU and GMU nodes to hook up everything that
the A619 needs to function properly.

Co-developed-by: Luca Weiss <luca.weiss@fairphone.com>
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
 arch/arm64/boot/dts/qcom/sm6350.dtsi | 140 +++++++++++++++++++++++++++++++++++
 1 file changed, 140 insertions(+)

Comments

Luca Weiss March 16, 2023, 11:30 a.m. UTC | #1

On Thu Mar 16, 2023 at 12:16 PM CET, Konrad Dybcio wrote:
> From: Konrad Dybcio <konrad.dybcio@somainline.org>
>
> Add Adreno, GPU SMMU and GMU nodes to hook up everything that
> the A619 needs to function properly.
>
> Co-developed-by: Luca Weiss <luca.weiss@fairphone.com>

I believe my signoff is missing here since I'm Co-developed-by:

Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>

> Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> ---
>  arch/arm64/boot/dts/qcom/sm6350.dtsi | 140 +++++++++++++++++++++++++++++++++++
>  1 file changed, 140 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi
> index 60b68d305e53..e967d06b0ad4 100644
> --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi
> @@ -1138,6 +1138,74 @@ compute-cb@5 {
>  			};
>  		};
>  
> +		gpu: gpu@3d00000 {
> +			compatible = "qcom,adreno-619.0", "qcom,adreno";
> +			reg = <0 0x03d00000 0 0x40000>,
> +			      <0 0x03d9e000 0 0x1000>;
> +			reg-names = "kgsl_3d0_reg_memory",
> +				    "cx_mem";
> +			interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
> +
> +			iommus = <&adreno_smmu 0>;
> +			operating-points-v2 = <&gpu_opp_table>;
> +			qcom,gmu = <&gmu>;
> +			nvmem-cells = <&gpu_speed_bin>;
> +			nvmem-cell-names = "speed_bin";
> +
> +			status = "disabled";
> +
> +			zap-shader {
> +				memory-region = <&pil_gpu_mem>;
> +			};
> +
> +			gpu_opp_table: opp-table {
> +				compatible = "operating-points-v2";
> +
> +				opp-850000000 {
> +					opp-hz = /bits/ 64 <850000000>;
> +					opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
> +					opp-supported-hw = <0x02>;
> +				};
> +
> +				opp-800000000 {
> +					opp-hz = /bits/ 64 <800000000>;
> +					opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
> +					opp-supported-hw = <0x04>;
> +				};
> +
> +				opp-650000000 {
> +					opp-hz = /bits/ 64 <650000000>;
> +					opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
> +					opp-supported-hw = <0x08>;
> +				};
> +
> +				opp-565000000 {
> +					opp-hz = /bits/ 64 <565000000>;
> +					opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
> +					opp-supported-hw = <0x10>;
> +				};
> +
> +				opp-430000000 {
> +					opp-hz = /bits/ 64 <430000000>;
> +					opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
> +					opp-supported-hw = <0xff>;
> +				};
> +
> +				opp-355000000 {
> +					opp-hz = /bits/ 64 <355000000>;
> +					opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
> +					opp-supported-hw = <0xff>;
> +				};
> +
> +				opp-253000000 {
> +					opp-hz = /bits/ 64 <253000000>;
> +					opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
> +					opp-supported-hw = <0xff>;
> +				};
> +			};
> +		};
> +
> +
>  		gpucc: clock-controller@3d90000 {
>  			compatible = "qcom,sm6350-gpucc";
>  			reg = <0 0x03d90000 0 0x9000>;
> @@ -1152,6 +1220,78 @@ gpucc: clock-controller@3d90000 {
>  			#power-domain-cells = <1>;
>  		};
>  
> +		adreno_smmu: iommu@3d40000 {
> +			compatible = "qcom,sm6350-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2";
> +			reg = <0 0x03d40000 0 0x10000>;
> +			#iommu-cells = <1>;
> +			#global-interrupts = <2>;
> +			interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
> +
> +			clocks = <&gpucc GPU_CC_AHB_CLK>,
> +				 <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
> +				 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>;
> +			clock-names = "ahb",
> +				      "bus",
> +				      "iface";
> +
> +			power-domains = <&gpucc GPU_CX_GDSC>;
> +		};
> +
> +		gmu: gmu@3d6a000 {
> +			compatible = "qcom,adreno-gmu-619.0", "qcom,adreno-gmu";
> +			reg = <0 0x03d6a000 0 0x31000>,
> +			      <0 0x0b290000 0 0x10000>,
> +			      <0 0x0b490000 0 0x10000>;
> +			reg-names = "gmu",
> +				    "gmu_pdc",
> +				    "gmu_pdc_seq";
> +
> +			interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupt-names = "hfi",
> +					  "gmu";
> +
> +			clocks = <&gpucc GPU_CC_AHB_CLK>,
> +				 <&gpucc GPU_CC_CX_GMU_CLK>,
> +				 <&gpucc GPU_CC_CXO_CLK>,
> +				 <&gcc GCC_DDRSS_GPU_AXI_CLK>,
> +				 <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
> +			clock-names = "ahb",
> +				      "gmu",
> +				      "cxo",
> +				      "axi",
> +				      "memnoc";
> +
> +			power-domains = <&gpucc GPU_CX_GDSC>,
> +					<&gpucc GPU_GX_GDSC>;
> +			power-domain-names = "cx",
> +					     "gx";
> +
> +			iommus = <&adreno_smmu 5>;
> +
> +			operating-points-v2 = <&gmu_opp_table>;
> +
> +			status = "disabled";
> +
> +			gmu_opp_table: opp-table {
> +				compatible = "operating-points-v2";
> +
> +				opp-200000000 {
> +					opp-hz = /bits/ 64 <200000000>;
> +					opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
> +				};
> +			};
> +		};
> +
>  		mpss: remoteproc@4080000 {
>  			compatible = "qcom,sm6350-mpss-pas";
>  			reg = <0x0 0x04080000 0x0 0x4040>;
>
> -- 
> 2.39.2

Luca Weiss March 17, 2023, 8:56 a.m. UTC | #2

On Thu Mar 16, 2023 at 12:16 PM CET, Konrad Dybcio wrote:
> From: Konrad Dybcio <konrad.dybcio@somainline.org>
>
> Add Adreno, GPU SMMU and GMU nodes to hook up everything that
> the A619 needs to function properly.
>
> Co-developed-by: Luca Weiss <luca.weiss@fairphone.com>
> Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> ---
>  arch/arm64/boot/dts/qcom/sm6350.dtsi | 140 +++++++++++++++++++++++++++++++++++
>  1 file changed, 140 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi
> index 60b68d305e53..e967d06b0ad4 100644
> --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi
> @@ -1138,6 +1138,74 @@ compute-cb@5 {
>  			};
>  		};
>  
> +		gpu: gpu@3d00000 {
> +			compatible = "qcom,adreno-619.0", "qcom,adreno";
> +			reg = <0 0x03d00000 0 0x40000>,
> +			      <0 0x03d9e000 0 0x1000>;
> +			reg-names = "kgsl_3d0_reg_memory",
> +				    "cx_mem";
> +			interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
> +
> +			iommus = <&adreno_smmu 0>;
> +			operating-points-v2 = <&gpu_opp_table>;
> +			qcom,gmu = <&gmu>;
> +			nvmem-cells = <&gpu_speed_bin>;
> +			nvmem-cell-names = "speed_bin";

What about adding interconnect already? I also have opp-peak-kBps
additions in the opp table for that. I'll attach the diff I have at the
end of the email.

> +
> +			status = "disabled";
> +
> +			zap-shader {
> +				memory-region = <&pil_gpu_mem>;
> +			};
> +
> +			gpu_opp_table: opp-table {
> +				compatible = "operating-points-v2";
> +
> +				opp-850000000 {
> +					opp-hz = /bits/ 64 <850000000>;
> +					opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
> +					opp-supported-hw = <0x02>;
> +				};
> +
> +				opp-800000000 {
> +					opp-hz = /bits/ 64 <800000000>;
> +					opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
> +					opp-supported-hw = <0x04>;
> +				};
> +
> +				opp-650000000 {
> +					opp-hz = /bits/ 64 <650000000>;
> +					opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
> +					opp-supported-hw = <0x08>;
> +				};
> +
> +				opp-565000000 {
> +					opp-hz = /bits/ 64 <565000000>;
> +					opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
> +					opp-supported-hw = <0x10>;
> +				};
> +
> +				opp-430000000 {
> +					opp-hz = /bits/ 64 <430000000>;
> +					opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
> +					opp-supported-hw = <0xff>;
> +				};
> +
> +				opp-355000000 {
> +					opp-hz = /bits/ 64 <355000000>;
> +					opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
> +					opp-supported-hw = <0xff>;
> +				};
> +
> +				opp-253000000 {
> +					opp-hz = /bits/ 64 <253000000>;
> +					opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
> +					opp-supported-hw = <0xff>;
> +				};
> +			};
> +		};
> +
> +
>  		gpucc: clock-controller@3d90000 {
>  			compatible = "qcom,sm6350-gpucc";
>  			reg = <0 0x03d90000 0 0x9000>;
> @@ -1152,6 +1220,78 @@ gpucc: clock-controller@3d90000 {
>  			#power-domain-cells = <1>;
>  		};
>  
> +		adreno_smmu: iommu@3d40000 {

This and gmu should be above gpucc @3d90000?

> +			compatible = "qcom,sm6350-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2";
> +			reg = <0 0x03d40000 0 0x10000>;
> +			#iommu-cells = <1>;
> +			#global-interrupts = <2>;
> +			interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
> +
> +			clocks = <&gpucc GPU_CC_AHB_CLK>,
> +				 <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
> +				 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>;
> +			clock-names = "ahb",
> +				      "bus",
> +				      "iface";
> +
> +			power-domains = <&gpucc GPU_CX_GDSC>;
> +		};
> +
> +		gmu: gmu@3d6a000 {
> +			compatible = "qcom,adreno-gmu-619.0", "qcom,adreno-gmu";
> +			reg = <0 0x03d6a000 0 0x31000>,
> +			      <0 0x0b290000 0 0x10000>,
> +			      <0 0x0b490000 0 0x10000>;
> +			reg-names = "gmu",
> +				    "gmu_pdc",
> +				    "gmu_pdc_seq";
> +
> +			interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupt-names = "hfi",
> +					  "gmu";
> +
> +			clocks = <&gpucc GPU_CC_AHB_CLK>,
> +				 <&gpucc GPU_CC_CX_GMU_CLK>,
> +				 <&gpucc GPU_CC_CXO_CLK>,
> +				 <&gcc GCC_DDRSS_GPU_AXI_CLK>,
> +				 <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
> +			clock-names = "ahb",
> +				      "gmu",
> +				      "cxo",
> +				      "axi",
> +				      "memnoc";
> +
> +			power-domains = <&gpucc GPU_CX_GDSC>,
> +					<&gpucc GPU_GX_GDSC>;
> +			power-domain-names = "cx",
> +					     "gx";
> +
> +			iommus = <&adreno_smmu 5>;
> +
> +			operating-points-v2 = <&gmu_opp_table>;
> +
> +			status = "disabled";
> +
> +			gmu_opp_table: opp-table {
> +				compatible = "operating-points-v2";
> +
> +				opp-200000000 {
> +					opp-hz = /bits/ 64 <200000000>;
> +					opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
> +				};
> +			};
> +		};
> +
>  		mpss: remoteproc@4080000 {
>  			compatible = "qcom,sm6350-mpss-pas";
>  			reg = <0x0 0x04080000 0x0 0x4040>;
>
> -- 
> 2.39.2

Here's the diff I have for interconnect on top of this:

diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi
index 4954cbc2c0fc..51c5ac679a32 100644
--- a/arch/arm64/boot/dts/qcom/sm6350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi
@@ -1142,6 +1142,8 @@ gpu: gpu@3d00000 {
 			iommus = <&adreno_smmu 0>;
 			operating-points-v2 = <&gpu_opp_table>;
 			qcom,gmu = <&gmu>;
+			interconnects = <&gem_noc MASTER_GRAPHICS_3D 0 &clk_virt SLAVE_EBI_CH0 0>;
+			interconnect-names = "gfx-mem";
 			nvmem-cells = <&gpu_speed_bin>;
 			nvmem-cell-names = "speed_bin";
 
@@ -1157,42 +1159,49 @@ gpu_opp_table: opp-table {
 				opp-850000000 {
 					opp-hz = /bits/ 64 <850000000>;
 					opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
+					opp-peak-kBps = <8371200>;
 					opp-supported-hw = <0x02>;
 				};
 
 				opp-800000000 {
 					opp-hz = /bits/ 64 <800000000>;
 					opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
+					opp-peak-kBps = <8371200>;
 					opp-supported-hw = <0x04>;
 				};
 
 				opp-650000000 {
 					opp-hz = /bits/ 64 <650000000>;
 					opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
+					opp-peak-kBps = <6220000>;
 					opp-supported-hw = <0x08>;
 				};
 
 				opp-565000000 {
 					opp-hz = /bits/ 64 <565000000>;
 					opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
+					opp-peak-kBps = <5412000>;
 					opp-supported-hw = <0x10>;
 				};
 
 				opp-430000000 {
 					opp-hz = /bits/ 64 <430000000>;
 					opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
+					opp-peak-kBps = <4068000>;
 					opp-supported-hw = <0xff>;
 				};
 
 				opp-355000000 {
 					opp-hz = /bits/ 64 <355000000>;
 					opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
+					opp-peak-kBps = <3072000>;
 					opp-supported-hw = <0xff>;
 				};
 
 				opp-253000000 {
 					opp-hz = /bits/ 64 <253000000>;
 					opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
+					opp-peak-kBps = <2188000>;
 					opp-supported-hw = <0xff>;
 				};
 			};

Konrad Dybcio March 18, 2023, 1:45 p.m. UTC | #3

On 17.03.2023 09:56, Luca Weiss wrote:
> On Thu Mar 16, 2023 at 12:16 PM CET, Konrad Dybcio wrote:
>> From: Konrad Dybcio <konrad.dybcio@somainline.org>
>>
>> Add Adreno, GPU SMMU and GMU nodes to hook up everything that
>> the A619 needs to function properly.
>>
>> Co-developed-by: Luca Weiss <luca.weiss@fairphone.com>
>> Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
>> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
>> ---
[...]

> What about adding interconnect already? I also have opp-peak-kBps
> additions in the opp table for that. I'll attach the diff I have at the
> end of the email.
I believe the GMU takes care of it internally (or at least should)
with the bandwidth tables we send in a6xx_hfi.c : a6xx_hfi_send_bw_table()


[...]

>>  
>> +		adreno_smmu: iommu@3d40000 {
> 
> This and gmu should be above gpucc @3d90000?
Absolutely.

Konrad
> 
>> +			compatible = "qcom,sm6350-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2";
>> +			reg = <0 0x03d40000 0 0x10000>;
>> +			#iommu-cells = <1>;
>> +			#global-interrupts = <2>;
>> +			interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
>> +				     <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
>> +				     <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>,
>> +				     <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>,
>> +				     <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>,
>> +				     <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>,
>> +				     <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>,
>> +				     <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>,
>> +				     <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>,
>> +				     <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
>> +
>> +			clocks = <&gpucc GPU_CC_AHB_CLK>,
>> +				 <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
>> +				 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>;
>> +			clock-names = "ahb",
>> +				      "bus",
>> +				      "iface";
>> +
>> +			power-domains = <&gpucc GPU_CX_GDSC>;
>> +		};
>> +
>> +		gmu: gmu@3d6a000 {
>> +			compatible = "qcom,adreno-gmu-619.0", "qcom,adreno-gmu";
>> +			reg = <0 0x03d6a000 0 0x31000>,
>> +			      <0 0x0b290000 0 0x10000>,
>> +			      <0 0x0b490000 0 0x10000>;
>> +			reg-names = "gmu",
>> +				    "gmu_pdc",
>> +				    "gmu_pdc_seq";
>> +
>> +			interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
>> +				     <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
>> +			interrupt-names = "hfi",
>> +					  "gmu";
>> +
>> +			clocks = <&gpucc GPU_CC_AHB_CLK>,
>> +				 <&gpucc GPU_CC_CX_GMU_CLK>,
>> +				 <&gpucc GPU_CC_CXO_CLK>,
>> +				 <&gcc GCC_DDRSS_GPU_AXI_CLK>,
>> +				 <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
>> +			clock-names = "ahb",
>> +				      "gmu",
>> +				      "cxo",
>> +				      "axi",
>> +				      "memnoc";
>> +
>> +			power-domains = <&gpucc GPU_CX_GDSC>,
>> +					<&gpucc GPU_GX_GDSC>;
>> +			power-domain-names = "cx",
>> +					     "gx";
>> +
>> +			iommus = <&adreno_smmu 5>;
>> +
>> +			operating-points-v2 = <&gmu_opp_table>;
>> +
>> +			status = "disabled";
>> +
>> +			gmu_opp_table: opp-table {
>> +				compatible = "operating-points-v2";
>> +
>> +				opp-200000000 {
>> +					opp-hz = /bits/ 64 <200000000>;
>> +					opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
>> +				};
>> +			};
>> +		};
>> +
>>  		mpss: remoteproc@4080000 {
>>  			compatible = "qcom,sm6350-mpss-pas";
>>  			reg = <0x0 0x04080000 0x0 0x4040>;
>>
>> -- 
>> 2.39.2
> 
> Here's the diff I have for interconnect on top of this:
> 
> diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi
> index 4954cbc2c0fc..51c5ac679a32 100644
> --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi
> @@ -1142,6 +1142,8 @@ gpu: gpu@3d00000 {
>  			iommus = <&adreno_smmu 0>;
>  			operating-points-v2 = <&gpu_opp_table>;
>  			qcom,gmu = <&gmu>;
> +			interconnects = <&gem_noc MASTER_GRAPHICS_3D 0 &clk_virt SLAVE_EBI_CH0 0>;
> +			interconnect-names = "gfx-mem";
>  			nvmem-cells = <&gpu_speed_bin>;
>  			nvmem-cell-names = "speed_bin";
>  
> @@ -1157,42 +1159,49 @@ gpu_opp_table: opp-table {
>  				opp-850000000 {
>  					opp-hz = /bits/ 64 <850000000>;
>  					opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
> +					opp-peak-kBps = <8371200>;
>  					opp-supported-hw = <0x02>;
>  				};
>  
>  				opp-800000000 {
>  					opp-hz = /bits/ 64 <800000000>;
>  					opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
> +					opp-peak-kBps = <8371200>;
>  					opp-supported-hw = <0x04>;
>  				};
>  
>  				opp-650000000 {
>  					opp-hz = /bits/ 64 <650000000>;
>  					opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
> +					opp-peak-kBps = <6220000>;
>  					opp-supported-hw = <0x08>;
>  				};
>  
>  				opp-565000000 {
>  					opp-hz = /bits/ 64 <565000000>;
>  					opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
> +					opp-peak-kBps = <5412000>;
>  					opp-supported-hw = <0x10>;
>  				};
>  
>  				opp-430000000 {
>  					opp-hz = /bits/ 64 <430000000>;
>  					opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
> +					opp-peak-kBps = <4068000>;
>  					opp-supported-hw = <0xff>;
>  				};
>  
>  				opp-355000000 {
>  					opp-hz = /bits/ 64 <355000000>;
>  					opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
> +					opp-peak-kBps = <3072000>;
>  					opp-supported-hw = <0xff>;
>  				};
>  
>  				opp-253000000 {
>  					opp-hz = /bits/ 64 <253000000>;
>  					opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
> +					opp-peak-kBps = <2188000>;
>  					opp-supported-hw = <0xff>;
>  				};
>  			};
>

Dmitry Baryshkov April 3, 2023, 6:50 p.m. UTC | #4

On 18/03/2023 15:45, Konrad Dybcio wrote:
> 
> 
> On 17.03.2023 09:56, Luca Weiss wrote:
>> On Thu Mar 16, 2023 at 12:16 PM CET, Konrad Dybcio wrote:
>>> From: Konrad Dybcio <konrad.dybcio@somainline.org>
>>>
>>> Add Adreno, GPU SMMU and GMU nodes to hook up everything that
>>> the A619 needs to function properly.
>>>
>>> Co-developed-by: Luca Weiss <luca.weiss@fairphone.com>
>>> Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
>>> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
>>> ---
> [...]
> 
>> What about adding interconnect already? I also have opp-peak-kBps
>> additions in the opp table for that. I'll attach the diff I have at the
>> end of the email.
> I believe the GMU takes care of it internally (or at least should)
> with the bandwidth tables we send in a6xx_hfi.c : a6xx_hfi_send_bw_table()

We should still declare the interconnects. If at some point we attempt 
to fill these tables in a proper way, the interconnects will be required 
to get addresses of the nodes.

> 
> 
> [...]
> 
>>>   
>>> +		adreno_smmu: iommu@3d40000 {
>>
>> This and gmu should be above gpucc @3d90000?
> Absolutely.
> 
> Konrad
>>
>>> +			compatible = "qcom,sm6350-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2";
>>> +			reg = <0 0x03d40000 0 0x10000>;
>>> +			#iommu-cells = <1>;
>>> +			#global-interrupts = <2>;
>>> +			interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
>>> +				     <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
>>> +				     <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>,
>>> +				     <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>,
>>> +				     <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>,
>>> +				     <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>,
>>> +				     <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>,
>>> +				     <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>,
>>> +				     <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>,
>>> +				     <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
>>> +
>>> +			clocks = <&gpucc GPU_CC_AHB_CLK>,
>>> +				 <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
>>> +				 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>;
>>> +			clock-names = "ahb",
>>> +				      "bus",
>>> +				      "iface";
>>> +
>>> +			power-domains = <&gpucc GPU_CX_GDSC>;
>>> +		};
>>> +
>>> +		gmu: gmu@3d6a000 {
>>> +			compatible = "qcom,adreno-gmu-619.0", "qcom,adreno-gmu";
>>> +			reg = <0 0x03d6a000 0 0x31000>,
>>> +			      <0 0x0b290000 0 0x10000>,
>>> +			      <0 0x0b490000 0 0x10000>;
>>> +			reg-names = "gmu",
>>> +				    "gmu_pdc",
>>> +				    "gmu_pdc_seq";
>>> +
>>> +			interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
>>> +				     <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
>>> +			interrupt-names = "hfi",
>>> +					  "gmu";
>>> +
>>> +			clocks = <&gpucc GPU_CC_AHB_CLK>,
>>> +				 <&gpucc GPU_CC_CX_GMU_CLK>,
>>> +				 <&gpucc GPU_CC_CXO_CLK>,
>>> +				 <&gcc GCC_DDRSS_GPU_AXI_CLK>,
>>> +				 <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
>>> +			clock-names = "ahb",
>>> +				      "gmu",
>>> +				      "cxo",
>>> +				      "axi",
>>> +				      "memnoc";
>>> +
>>> +			power-domains = <&gpucc GPU_CX_GDSC>,
>>> +					<&gpucc GPU_GX_GDSC>;
>>> +			power-domain-names = "cx",
>>> +					     "gx";
>>> +
>>> +			iommus = <&adreno_smmu 5>;
>>> +
>>> +			operating-points-v2 = <&gmu_opp_table>;
>>> +
>>> +			status = "disabled";
>>> +
>>> +			gmu_opp_table: opp-table {
>>> +				compatible = "operating-points-v2";
>>> +
>>> +				opp-200000000 {
>>> +					opp-hz = /bits/ 64 <200000000>;
>>> +					opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
>>> +				};
>>> +			};
>>> +		};
>>> +
>>>   		mpss: remoteproc@4080000 {
>>>   			compatible = "qcom,sm6350-mpss-pas";
>>>   			reg = <0x0 0x04080000 0x0 0x4040>;
>>>
>>> -- 
>>> 2.39.2
>>
>> Here's the diff I have for interconnect on top of this:
>>
>> diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi
>> index 4954cbc2c0fc..51c5ac679a32 100644
>> --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi
>> @@ -1142,6 +1142,8 @@ gpu: gpu@3d00000 {
>>   			iommus = <&adreno_smmu 0>;
>>   			operating-points-v2 = <&gpu_opp_table>;
>>   			qcom,gmu = <&gmu>;
>> +			interconnects = <&gem_noc MASTER_GRAPHICS_3D 0 &clk_virt SLAVE_EBI_CH0 0>;
>> +			interconnect-names = "gfx-mem";
>>   			nvmem-cells = <&gpu_speed_bin>;
>>   			nvmem-cell-names = "speed_bin";
>>   
>> @@ -1157,42 +1159,49 @@ gpu_opp_table: opp-table {
>>   				opp-850000000 {
>>   					opp-hz = /bits/ 64 <850000000>;
>>   					opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
>> +					opp-peak-kBps = <8371200>;
>>   					opp-supported-hw = <0x02>;
>>   				};
>>   
>>   				opp-800000000 {
>>   					opp-hz = /bits/ 64 <800000000>;
>>   					opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
>> +					opp-peak-kBps = <8371200>;
>>   					opp-supported-hw = <0x04>;
>>   				};
>>   
>>   				opp-650000000 {
>>   					opp-hz = /bits/ 64 <650000000>;
>>   					opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
>> +					opp-peak-kBps = <6220000>;
>>   					opp-supported-hw = <0x08>;
>>   				};
>>   
>>   				opp-565000000 {
>>   					opp-hz = /bits/ 64 <565000000>;
>>   					opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
>> +					opp-peak-kBps = <5412000>;
>>   					opp-supported-hw = <0x10>;
>>   				};
>>   
>>   				opp-430000000 {
>>   					opp-hz = /bits/ 64 <430000000>;
>>   					opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
>> +					opp-peak-kBps = <4068000>;
>>   					opp-supported-hw = <0xff>;
>>   				};
>>   
>>   				opp-355000000 {
>>   					opp-hz = /bits/ 64 <355000000>;
>>   					opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
>> +					opp-peak-kBps = <3072000>;
>>   					opp-supported-hw = <0xff>;
>>   				};
>>   
>>   				opp-253000000 {
>>   					opp-hz = /bits/ 64 <253000000>;
>>   					opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
>> +					opp-peak-kBps = <2188000>;
>>   					opp-supported-hw = <0xff>;
>>   				};
>>   			};
>>

Konrad Dybcio April 3, 2023, 6:52 p.m. UTC | #5

On 3.04.2023 20:50, Dmitry Baryshkov wrote:
> On 18/03/2023 15:45, Konrad Dybcio wrote:
>>
>>
>> On 17.03.2023 09:56, Luca Weiss wrote:
>>> On Thu Mar 16, 2023 at 12:16 PM CET, Konrad Dybcio wrote:
>>>> From: Konrad Dybcio <konrad.dybcio@somainline.org>
>>>>
>>>> Add Adreno, GPU SMMU and GMU nodes to hook up everything that
>>>> the A619 needs to function properly.
>>>>
>>>> Co-developed-by: Luca Weiss <luca.weiss@fairphone.com>
>>>> Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
>>>> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
>>>> ---
>> [...]
>>
>>> What about adding interconnect already? I also have opp-peak-kBps
>>> additions in the opp table for that. I'll attach the diff I have at the
>>> end of the email.
>> I believe the GMU takes care of it internally (or at least should)
>> with the bandwidth tables we send in a6xx_hfi.c : a6xx_hfi_send_bw_table()
> 
> We should still declare the interconnects. If at some point we attempt to fill these tables in a proper way, the interconnects will be required to get addresses of the nodes.
A619 has all the "proper" data filled in. This should arguably
be switched to per-SoC and not per-GPU btw.

The interconnect endpoints should be looked up through the cmd_db
function like Bjorn did in the A690 patchset.

Konrad
> 
>>
>>
>> [...]
>>
>>>>   +        adreno_smmu: iommu@3d40000 {
>>>
>>> This and gmu should be above gpucc @3d90000?
>> Absolutely.
>>
>> Konrad
>>>
>>>> +            compatible = "qcom,sm6350-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2";
>>>> +            reg = <0 0x03d40000 0 0x10000>;
>>>> +            #iommu-cells = <1>;
>>>> +            #global-interrupts = <2>;
>>>> +            interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
>>>> +                     <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
>>>> +                     <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>,
>>>> +                     <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>,
>>>> +                     <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>,
>>>> +                     <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>,
>>>> +                     <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>,
>>>> +                     <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>,
>>>> +                     <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>,
>>>> +                     <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
>>>> +
>>>> +            clocks = <&gpucc GPU_CC_AHB_CLK>,
>>>> +                 <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
>>>> +                 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>;
>>>> +            clock-names = "ahb",
>>>> +                      "bus",
>>>> +                      "iface";
>>>> +
>>>> +            power-domains = <&gpucc GPU_CX_GDSC>;
>>>> +        };
>>>> +
>>>> +        gmu: gmu@3d6a000 {
>>>> +            compatible = "qcom,adreno-gmu-619.0", "qcom,adreno-gmu";
>>>> +            reg = <0 0x03d6a000 0 0x31000>,
>>>> +                  <0 0x0b290000 0 0x10000>,
>>>> +                  <0 0x0b490000 0 0x10000>;
>>>> +            reg-names = "gmu",
>>>> +                    "gmu_pdc",
>>>> +                    "gmu_pdc_seq";
>>>> +
>>>> +            interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
>>>> +                     <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
>>>> +            interrupt-names = "hfi",
>>>> +                      "gmu";
>>>> +
>>>> +            clocks = <&gpucc GPU_CC_AHB_CLK>,
>>>> +                 <&gpucc GPU_CC_CX_GMU_CLK>,
>>>> +                 <&gpucc GPU_CC_CXO_CLK>,
>>>> +                 <&gcc GCC_DDRSS_GPU_AXI_CLK>,
>>>> +                 <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
>>>> +            clock-names = "ahb",
>>>> +                      "gmu",
>>>> +                      "cxo",
>>>> +                      "axi",
>>>> +                      "memnoc";
>>>> +
>>>> +            power-domains = <&gpucc GPU_CX_GDSC>,
>>>> +                    <&gpucc GPU_GX_GDSC>;
>>>> +            power-domain-names = "cx",
>>>> +                         "gx";
>>>> +
>>>> +            iommus = <&adreno_smmu 5>;
>>>> +
>>>> +            operating-points-v2 = <&gmu_opp_table>;
>>>> +
>>>> +            status = "disabled";
>>>> +
>>>> +            gmu_opp_table: opp-table {
>>>> +                compatible = "operating-points-v2";
>>>> +
>>>> +                opp-200000000 {
>>>> +                    opp-hz = /bits/ 64 <200000000>;
>>>> +                    opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
>>>> +                };
>>>> +            };
>>>> +        };
>>>> +
>>>>           mpss: remoteproc@4080000 {
>>>>               compatible = "qcom,sm6350-mpss-pas";
>>>>               reg = <0x0 0x04080000 0x0 0x4040>;
>>>>
>>>> -- 
>>>> 2.39.2
>>>
>>> Here's the diff I have for interconnect on top of this:
>>>
>>> diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi
>>> index 4954cbc2c0fc..51c5ac679a32 100644
>>> --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi
>>> +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi
>>> @@ -1142,6 +1142,8 @@ gpu: gpu@3d00000 {
>>>               iommus = <&adreno_smmu 0>;
>>>               operating-points-v2 = <&gpu_opp_table>;
>>>               qcom,gmu = <&gmu>;
>>> +            interconnects = <&gem_noc MASTER_GRAPHICS_3D 0 &clk_virt SLAVE_EBI_CH0 0>;
>>> +            interconnect-names = "gfx-mem";
>>>               nvmem-cells = <&gpu_speed_bin>;
>>>               nvmem-cell-names = "speed_bin";
>>>   @@ -1157,42 +1159,49 @@ gpu_opp_table: opp-table {
>>>                   opp-850000000 {
>>>                       opp-hz = /bits/ 64 <850000000>;
>>>                       opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
>>> +                    opp-peak-kBps = <8371200>;
>>>                       opp-supported-hw = <0x02>;
>>>                   };
>>>                     opp-800000000 {
>>>                       opp-hz = /bits/ 64 <800000000>;
>>>                       opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
>>> +                    opp-peak-kBps = <8371200>;
>>>                       opp-supported-hw = <0x04>;
>>>                   };
>>>                     opp-650000000 {
>>>                       opp-hz = /bits/ 64 <650000000>;
>>>                       opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
>>> +                    opp-peak-kBps = <6220000>;
>>>                       opp-supported-hw = <0x08>;
>>>                   };
>>>                     opp-565000000 {
>>>                       opp-hz = /bits/ 64 <565000000>;
>>>                       opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
>>> +                    opp-peak-kBps = <5412000>;
>>>                       opp-supported-hw = <0x10>;
>>>                   };
>>>                     opp-430000000 {
>>>                       opp-hz = /bits/ 64 <430000000>;
>>>                       opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
>>> +                    opp-peak-kBps = <4068000>;
>>>                       opp-supported-hw = <0xff>;
>>>                   };
>>>                     opp-355000000 {
>>>                       opp-hz = /bits/ 64 <355000000>;
>>>                       opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
>>> +                    opp-peak-kBps = <3072000>;
>>>                       opp-supported-hw = <0xff>;
>>>                   };
>>>                     opp-253000000 {
>>>                       opp-hz = /bits/ 64 <253000000>;
>>>                       opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
>>> +                    opp-peak-kBps = <2188000>;
>>>                       opp-supported-hw = <0xff>;
>>>                   };
>>>               };
>>>
>

diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi
index 60b68d305e53..e967d06b0ad4 100644
--- a/arch/arm64/boot/dts/qcom/sm6350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi
@@ -1138,6 +1138,74 @@  compute-cb@5 {
 			};
 		};
 
+		gpu: gpu@3d00000 {
+			compatible = "qcom,adreno-619.0", "qcom,adreno";
+			reg = <0 0x03d00000 0 0x40000>,
+			      <0 0x03d9e000 0 0x1000>;
+			reg-names = "kgsl_3d0_reg_memory",
+				    "cx_mem";
+			interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
+
+			iommus = <&adreno_smmu 0>;
+			operating-points-v2 = <&gpu_opp_table>;
+			qcom,gmu = <&gmu>;
+			nvmem-cells = <&gpu_speed_bin>;
+			nvmem-cell-names = "speed_bin";
+
+			status = "disabled";
+
+			zap-shader {
+				memory-region = <&pil_gpu_mem>;
+			};
+
+			gpu_opp_table: opp-table {
+				compatible = "operating-points-v2";
+
+				opp-850000000 {
+					opp-hz = /bits/ 64 <850000000>;
+					opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
+					opp-supported-hw = <0x02>;
+				};
+
+				opp-800000000 {
+					opp-hz = /bits/ 64 <800000000>;
+					opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
+					opp-supported-hw = <0x04>;
+				};
+
+				opp-650000000 {
+					opp-hz = /bits/ 64 <650000000>;
+					opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
+					opp-supported-hw = <0x08>;
+				};
+
+				opp-565000000 {
+					opp-hz = /bits/ 64 <565000000>;
+					opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
+					opp-supported-hw = <0x10>;
+				};
+
+				opp-430000000 {
+					opp-hz = /bits/ 64 <430000000>;
+					opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
+					opp-supported-hw = <0xff>;
+				};
+
+				opp-355000000 {
+					opp-hz = /bits/ 64 <355000000>;
+					opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
+					opp-supported-hw = <0xff>;
+				};
+
+				opp-253000000 {
+					opp-hz = /bits/ 64 <253000000>;
+					opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
+					opp-supported-hw = <0xff>;
+				};
+			};
+		};
+
+
 		gpucc: clock-controller@3d90000 {
 			compatible = "qcom,sm6350-gpucc";
 			reg = <0 0x03d90000 0 0x9000>;
@@ -1152,6 +1220,78 @@  gpucc: clock-controller@3d90000 {
 			#power-domain-cells = <1>;
 		};
 
+		adreno_smmu: iommu@3d40000 {
+			compatible = "qcom,sm6350-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2";
+			reg = <0 0x03d40000 0 0x10000>;
+			#iommu-cells = <1>;
+			#global-interrupts = <2>;
+			interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
+
+			clocks = <&gpucc GPU_CC_AHB_CLK>,
+				 <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
+				 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>;
+			clock-names = "ahb",
+				      "bus",
+				      "iface";
+
+			power-domains = <&gpucc GPU_CX_GDSC>;
+		};
+
+		gmu: gmu@3d6a000 {
+			compatible = "qcom,adreno-gmu-619.0", "qcom,adreno-gmu";
+			reg = <0 0x03d6a000 0 0x31000>,
+			      <0 0x0b290000 0 0x10000>,
+			      <0 0x0b490000 0 0x10000>;
+			reg-names = "gmu",
+				    "gmu_pdc",
+				    "gmu_pdc_seq";
+
+			interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "hfi",
+					  "gmu";
+
+			clocks = <&gpucc GPU_CC_AHB_CLK>,
+				 <&gpucc GPU_CC_CX_GMU_CLK>,
+				 <&gpucc GPU_CC_CXO_CLK>,
+				 <&gcc GCC_DDRSS_GPU_AXI_CLK>,
+				 <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
+			clock-names = "ahb",
+				      "gmu",
+				      "cxo",
+				      "axi",
+				      "memnoc";
+
+			power-domains = <&gpucc GPU_CX_GDSC>,
+					<&gpucc GPU_GX_GDSC>;
+			power-domain-names = "cx",
+					     "gx";
+
+			iommus = <&adreno_smmu 5>;
+
+			operating-points-v2 = <&gmu_opp_table>;
+
+			status = "disabled";
+
+			gmu_opp_table: opp-table {
+				compatible = "operating-points-v2";
+
+				opp-200000000 {
+					opp-hz = /bits/ 64 <200000000>;
+					opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
+				};
+			};
+		};
+
 		mpss: remoteproc@4080000 {
 			compatible = "qcom,sm6350-mpss-pas";
 			reg = <0x0 0x04080000 0x0 0x4040>;