Message ID | 20221231220146.646-4-samuel@sholland.org |
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State | New |
Headers |
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Miller" <davem@davemloft.net>, Chen-Yu Tsai <wens@csie.org>, Jernej Skrabec <jernej.skrabec@gmail.com>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Rob Herring <robh+dt@kernel.org> Cc: Samuel Holland <samuel@sholland.org>, Albert Ou <aou@eecs.berkeley.edu>, Conor Dooley <conor@kernel.org>, Palmer Dabbelt <palmer@dabbelt.com>, Paul Walmsley <paul.walmsley@sifive.com>, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-crypto@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-sunxi@lists.linux.dev Subject: [PATCH v2 3/3] riscv: dts: allwinner: d1: Add crypto engine node Date: Sat, 31 Dec 2022 16:01:45 -0600 Message-Id: <20221231220146.646-4-samuel@sholland.org> X-Mailer: git-send-email 2.37.4 In-Reply-To: <20221231220146.646-1-samuel@sholland.org> References: <20221231220146.646-1-samuel@sholland.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-2.8 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_LOW, RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: <linux-kernel.vger.kernel.org> X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1753768755677705659?= X-GMAIL-MSGID: =?utf-8?q?1753768755677705659?= |
Series |
crypto: Allwinner D1 crypto support
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Commit Message
Samuel Holland
Dec. 31, 2022, 10:01 p.m. UTC
D1 contains a crypto engine which is supported by the sun8i-ce driver.
Signed-off-by: Samuel Holland <samuel@sholland.org>
---
Changes in v2:
- New patch for v2
arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi | 12 ++++++++++++
1 file changed, 12 insertions(+)
Comments
Dne sobota, 31. december 2022 ob 23:01:45 CET je Samuel Holland napisal(a): > D1 contains a crypto engine which is supported by the sun8i-ce driver. > > Signed-off-by: Samuel Holland <samuel@sholland.org> Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com> Best regards, Jernej
On Sat, 31 Dec 2022 14:01:45 PST (-0800), samuel@sholland.org wrote: > D1 contains a crypto engine which is supported by the sun8i-ce driver. > > Signed-off-by: Samuel Holland <samuel@sholland.org> > --- > > Changes in v2: > - New patch for v2 > > arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi | 12 ++++++++++++ > 1 file changed, 12 insertions(+) > > diff --git a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi > index dff363a3c934..b30b4b1465f6 100644 > --- a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi > +++ b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi > @@ -378,6 +378,18 @@ sid: efuse@3006000 { > #size-cells = <1>; > }; > > + crypto: crypto@3040000 { > + compatible = "allwinner,sun20i-d1-crypto"; > + reg = <0x3040000 0x800>; > + interrupts = <SOC_PERIPHERAL_IRQ(52) IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&ccu CLK_BUS_CE>, > + <&ccu CLK_CE>, > + <&ccu CLK_MBUS_CE>, > + <&rtc CLK_IOSC>; > + clock-names = "bus", "mod", "ram", "trng"; > + resets = <&ccu RST_BUS_CE>; > + }; > + > mbus: dram-controller@3102000 { > compatible = "allwinner,sun20i-d1-mbus"; > reg = <0x3102000 0x1000>, Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
Dne sobota, 31. december 2022 ob 23:01:45 CET je Samuel Holland napisal(a): > D1 contains a crypto engine which is supported by the sun8i-ce driver. > > Signed-off-by: Samuel Holland <samuel@sholland.org> Applied patch 3, thanks! Best regards, Jernej
diff --git a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi index dff363a3c934..b30b4b1465f6 100644 --- a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi +++ b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi @@ -378,6 +378,18 @@ sid: efuse@3006000 { #size-cells = <1>; }; + crypto: crypto@3040000 { + compatible = "allwinner,sun20i-d1-crypto"; + reg = <0x3040000 0x800>; + interrupts = <SOC_PERIPHERAL_IRQ(52) IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_CE>, + <&ccu CLK_CE>, + <&ccu CLK_MBUS_CE>, + <&rtc CLK_IOSC>; + clock-names = "bus", "mod", "ram", "trng"; + resets = <&ccu RST_BUS_CE>; + }; + mbus: dram-controller@3102000 { compatible = "allwinner,sun20i-d1-mbus"; reg = <0x3102000 0x1000>,