diff mbox series

[5/6] tools/perf/json: Add cache metrics for s390 z13

Message ID	20230313080201.2440201-5-tmricht@linux.ibm.com
State	New
Headers	Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; From: Thomas Richter <tmricht@linux.ibm.com> To: linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, acme@kernel.org, sumanthk@linux.ibm.com Cc: svens@linux.ibm.com, gor@linux.ibm.com, hca@linux.ibm.com, Thomas Richter <tmricht@linux.ibm.com> Subject: [PATCH 5/6] tools/perf/json: Add cache metrics for s390 z13 Date: Mon, 13 Mar 2023 09:02:00 +0100 Message-Id: <20230313080201.2440201-5-tmricht@linux.ibm.com> In-Reply-To: <20230313080201.2440201-1-tmricht@linux.ibm.com> References: <20230313080201.2440201-1-tmricht@linux.ibm.com> Content-Transfer-Encoding: 8bit MIME-Version: 1.0 Precedence: bulk
Series	[1/6] tools/perf/json: Add common metrics for s390 \| [1/6] tools/perf/json: Add common metrics for s390 [2/6] tools/perf/json: Add cache metrics for s390 z16 [3/6] tools/perf/json: Add cache metrics for s390 z15 [4/6] tools/perf/json: Add cache metrics for s390 z14 [5/6] tools/perf/json: Add cache metrics for s390 z13 [6/6] tools/perf/json: Add metric for tlb and cache s390

Commit Message

Thomas Richter March 13, 2023, 8:02 a.m. UTC

  Add metrics for s390 z13
- Percentage sourced from Level 2 cache
- Percentage sourced from Level 3 on same chip cache
- Percentage sourced from Level 4 Local cache on same book
- Percentage sourced from Level 4 Remote cache on different book
- Percentage sourced from memory

For details about the formulas see this documentation:
https://www.ibm.com/support/pages/system/files/inline-files/CPU%20MF%20Formulas%20including%20z16%20-%20May%202022_1.pdf

Output after:

 # ./perf stat -M l4rp -- find /
   ...find output deleted

 Performance counter stats for 'find /':

            2      L1I_OFFDRAWER_SCOL_L4_SOURCED_WRITES #     0.02 l4rp
          252      L1D_ONDRAWER_L4_SOURCED_WRITES
        3,465      L1D_ONDRAWER_L3_SOURCED_WRITES_IV
           80      L1D_OFFDRAWER_SCOL_L4_SOURCED_WRITES
          761      L1D_ONDRAWER_L3_SOURCED_WRITES
            0      L1I_OFFDRAWER_SCOL_L3_SOURCED_WRITES
  131,817,067      L1I_DIR_WRITES
            1      L1I_OFFDRAWER_FCOL_L4_SOURCED_WRITES
          447      L1D_OFFDRAWER_SCOL_L3_SOURCED_WRITES
           22      L1D_OFFDRAWER_FCOL_L4_SOURCED_WRITES
            7      L1I_ONDRAWER_L4_SOURCED_WRITES
            0      L1I_OFFDRAWER_FCOL_L3_SOURCED_WRITES
        1,071      L1D_OFFDRAWER_FCOL_L3_SOURCED_WRITES
            3      L1I_ONDRAWER_L3_SOURCED_WRITES
       13,352      L1D_OFFDRAWER_FCOL_L3_SOURCED_WRITES_IV
       15,252      L1D_OFFDRAWER_SCOL_L3_SOURCED_WRITES_IV
            0      L1I_ONDRAWER_L3_SOURCED_WRITES_IV
            0      L1I_OFFDRAWER_FCOL_L3_SOURCED_WRITES_IV
   57,431,083      L1D_DIR_WRITES
            0      L1I_OFFDRAWER_SCOL_L3_SOURCED_WRITES_IV

      15.386502874 seconds time elapsed

       0.647348000 seconds user
       3.537041000 seconds sys

 #

Signed-off-by: Thomas Richter <tmricht@linux.ibm.com>
Acked-By: Sumanth Korikkar <sumanthk@linux.ibm.com>
---
 .../arch/s390/cf_z13/transaction.json         | 25 +++++++++++++++++++
 1 file changed, 25 insertions(+)

Comments

Ian Rogers March 13, 2023, 3:28 p.m. UTC | #1

On Mon, Mar 13, 2023 at 1:06 AM Thomas Richter <tmricht@linux.ibm.com> wrote:
>
> Add metrics for s390 z13
> - Percentage sourced from Level 2 cache
> - Percentage sourced from Level 3 on same chip cache
> - Percentage sourced from Level 4 Local cache on same book
> - Percentage sourced from Level 4 Remote cache on different book
> - Percentage sourced from memory
>
> For details about the formulas see this documentation:
> https://www.ibm.com/support/pages/system/files/inline-files/CPU%20MF%20Formulas%20including%20z16%20-%20May%202022_1.pdf
>
> Output after:
>
>  # ./perf stat -M l4rp -- find /
>    ...find output deleted
>
>  Performance counter stats for 'find /':
>
>             2      L1I_OFFDRAWER_SCOL_L4_SOURCED_WRITES #     0.02 l4rp
>           252      L1D_ONDRAWER_L4_SOURCED_WRITES
>         3,465      L1D_ONDRAWER_L3_SOURCED_WRITES_IV
>            80      L1D_OFFDRAWER_SCOL_L4_SOURCED_WRITES
>           761      L1D_ONDRAWER_L3_SOURCED_WRITES
>             0      L1I_OFFDRAWER_SCOL_L3_SOURCED_WRITES
>   131,817,067      L1I_DIR_WRITES
>             1      L1I_OFFDRAWER_FCOL_L4_SOURCED_WRITES
>           447      L1D_OFFDRAWER_SCOL_L3_SOURCED_WRITES
>            22      L1D_OFFDRAWER_FCOL_L4_SOURCED_WRITES
>             7      L1I_ONDRAWER_L4_SOURCED_WRITES
>             0      L1I_OFFDRAWER_FCOL_L3_SOURCED_WRITES
>         1,071      L1D_OFFDRAWER_FCOL_L3_SOURCED_WRITES
>             3      L1I_ONDRAWER_L3_SOURCED_WRITES
>        13,352      L1D_OFFDRAWER_FCOL_L3_SOURCED_WRITES_IV
>        15,252      L1D_OFFDRAWER_SCOL_L3_SOURCED_WRITES_IV
>             0      L1I_ONDRAWER_L3_SOURCED_WRITES_IV
>             0      L1I_OFFDRAWER_FCOL_L3_SOURCED_WRITES_IV
>    57,431,083      L1D_DIR_WRITES
>             0      L1I_OFFDRAWER_SCOL_L3_SOURCED_WRITES_IV
>
>       15.386502874 seconds time elapsed
>
>        0.647348000 seconds user
>        3.537041000 seconds sys
>
>  #
>
> Signed-off-by: Thomas Richter <tmricht@linux.ibm.com>
> Acked-By: Sumanth Korikkar <sumanthk@linux.ibm.com>
> ---
>  .../arch/s390/cf_z13/transaction.json         | 25 +++++++++++++++++++
>  1 file changed, 25 insertions(+)
>
> diff --git a/tools/perf/pmu-events/arch/s390/cf_z13/transaction.json b/tools/perf/pmu-events/arch/s390/cf_z13/transaction.json
> index 86bf83b4504e..71e2c7fa734c 100644
> --- a/tools/perf/pmu-events/arch/s390/cf_z13/transaction.json
> +++ b/tools/perf/pmu-events/arch/s390/cf_z13/transaction.json
> @@ -18,5 +18,30 @@
>      "BriefDescription": "Level One Miss per 100 Instructions",
>      "MetricName": "l1mp",
>      "MetricExpr": "((L1I_DIR_WRITES + L1D_DIR_WRITES) / INSTRUCTIONS) * 100"
> +  },
> +  {
> +    "BriefDescription": "Percentage sourced from Level 2 cache",
> +    "MetricName": "l2p",
> +    "MetricExpr": "((L1D_L2D_SOURCED_WRITES + L1I_L2I_SOURCED_WRITES) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100"

Looks good but the same comment about using ScaleUnit.

Thanks,
Ian

> +  },
> +  {
> +    "BriefDescription": "Percentage sourced from Level 3 on same chip cache",
> +    "MetricName": "l3p",
> +    "MetricExpr": "((L1D_ONCHIP_L3_SOURCED_WRITES + L1D_ONCHIP_L3_SOURCED_WRITES_IV + L1I_ONCHIP_L3_SOURCED_WRITES + L1I_ONCHIP_L3_SOURCED_WRITES_IV) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100"
> +  },
> +  {
> +    "BriefDescription": "Percentage sourced from Level 4 Local cache on same book",
> +    "MetricName": "l4lp",
> +    "MetricExpr": "((L1D_ONNODE_L4_SOURCED_WRITES + L1D_ONNODE_L3_SOURCED_WRITES_IV + L1D_ONNODE_L3_SOURCED_WRITES + L1I_ONNODE_L4_SOURCED_WRITES + L1I_ONNODE_L3_SOURCED_WRITES_IV + L1I_ONNODE_L3_SOURCED_WRITES) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100"
> +  },
> +  {
> +    "BriefDescription": "Percentage sourced from Level 4 Remote cache on different book",
> +    "MetricName": "l4rp",
> +    "MetricExpr": "((L1D_ONDRAWER_L4_SOURCED_WRITES + L1D_ONDRAWER_L3_SOURCED_WRITES_IV + L1D_ONDRAWER_L3_SOURCED_WRITES + L1D_OFFDRAWER_SCOL_L4_SOURCED_WRITES + L1D_OFFDRAWER_SCOL_L3_SOURCED_WRITES_IV + L1D_OFFDRAWER_SCOL_L3_SOURCED_WRITES + L1D_OFFDRAWER_FCOL_L4_SOURCED_WRITES + L1D_OFFDRAWER_FCOL_L3_SOURCED_WRITES_IV + L1D_OFFDRAWER_FCOL_L3_SOURCED_WRITES + L1I_ONDRAWER_L4_SOURCED_WRITES + L1I_ONDRAWER_L3_SOURCED_WRITES_IV + L1I_ONDRAWER_L3_SOURCED_WRITES + L1I_OFFDRAWER_SCOL_L4_SOURCED_WRITES + L1I_OFFDRAWER_SCOL_L3_SOURCED_WRITES_IV + L1I_OFFDRAWER_SCOL_L3_SOURCED_WRITES + L1I_OFFDRAWER_FCOL_L4_SOURCED_WRITES + L1I_OFFDRAWER_FCOL_L3_SOURCED_WRITES_IV + L1I_OFFDRAWER_FCOL_L3_SOURCED_WRITES) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100"
> +  },
> +  {
> +    "BriefDescription": "Percentage sourced from memory",
> +    "MetricName": "memp",
> +    "MetricExpr": "((L1D_ONNODE_MEM_SOURCED_WRITES + L1D_ONDRAWER_MEM_SOURCED_WRITES + L1D_OFFDRAWER_MEM_SOURCED_WRITES + L1D_ONCHIP_MEM_SOURCED_WRITES + L1I_ONNODE_MEM_SOURCED_WRITES + L1I_ONDRAWER_MEM_SOURCED_WRITES + L1I_OFFDRAWER_MEM_SOURCED_WRITES + L1I_ONCHIP_MEM_SOURCED_WRITES) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100"
>    }
>  ]
> --
> 2.39.1
>

diff mbox series

Patch

diff --git a/tools/perf/pmu-events/arch/s390/cf_z13/transaction.json b/tools/perf/pmu-events/arch/s390/cf_z13/transaction.json
index 86bf83b4504e..71e2c7fa734c 100644
--- a/tools/perf/pmu-events/arch/s390/cf_z13/transaction.json
+++ b/tools/perf/pmu-events/arch/s390/cf_z13/transaction.json
@@ -18,5 +18,30 @@ 
     "BriefDescription": "Level One Miss per 100 Instructions",
     "MetricName": "l1mp",
     "MetricExpr": "((L1I_DIR_WRITES + L1D_DIR_WRITES) / INSTRUCTIONS) * 100"
+  },
+  {
+    "BriefDescription": "Percentage sourced from Level 2 cache",
+    "MetricName": "l2p",
+    "MetricExpr": "((L1D_L2D_SOURCED_WRITES + L1I_L2I_SOURCED_WRITES) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100"
+  },
+  {
+    "BriefDescription": "Percentage sourced from Level 3 on same chip cache",
+    "MetricName": "l3p",
+    "MetricExpr": "((L1D_ONCHIP_L3_SOURCED_WRITES + L1D_ONCHIP_L3_SOURCED_WRITES_IV + L1I_ONCHIP_L3_SOURCED_WRITES + L1I_ONCHIP_L3_SOURCED_WRITES_IV) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100"
+  },
+  {
+    "BriefDescription": "Percentage sourced from Level 4 Local cache on same book",
+    "MetricName": "l4lp",
+    "MetricExpr": "((L1D_ONNODE_L4_SOURCED_WRITES + L1D_ONNODE_L3_SOURCED_WRITES_IV + L1D_ONNODE_L3_SOURCED_WRITES + L1I_ONNODE_L4_SOURCED_WRITES + L1I_ONNODE_L3_SOURCED_WRITES_IV + L1I_ONNODE_L3_SOURCED_WRITES) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100"
+  },
+  {
+    "BriefDescription": "Percentage sourced from Level 4 Remote cache on different book",
+    "MetricName": "l4rp",
+    "MetricExpr": "((L1D_ONDRAWER_L4_SOURCED_WRITES + L1D_ONDRAWER_L3_SOURCED_WRITES_IV + L1D_ONDRAWER_L3_SOURCED_WRITES + L1D_OFFDRAWER_SCOL_L4_SOURCED_WRITES + L1D_OFFDRAWER_SCOL_L3_SOURCED_WRITES_IV + L1D_OFFDRAWER_SCOL_L3_SOURCED_WRITES + L1D_OFFDRAWER_FCOL_L4_SOURCED_WRITES + L1D_OFFDRAWER_FCOL_L3_SOURCED_WRITES_IV + L1D_OFFDRAWER_FCOL_L3_SOURCED_WRITES + L1I_ONDRAWER_L4_SOURCED_WRITES + L1I_ONDRAWER_L3_SOURCED_WRITES_IV + L1I_ONDRAWER_L3_SOURCED_WRITES + L1I_OFFDRAWER_SCOL_L4_SOURCED_WRITES + L1I_OFFDRAWER_SCOL_L3_SOURCED_WRITES_IV + L1I_OFFDRAWER_SCOL_L3_SOURCED_WRITES + L1I_OFFDRAWER_FCOL_L4_SOURCED_WRITES + L1I_OFFDRAWER_FCOL_L3_SOURCED_WRITES_IV + L1I_OFFDRAWER_FCOL_L3_SOURCED_WRITES) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100"
+  },
+  {
+    "BriefDescription": "Percentage sourced from memory",
+    "MetricName": "memp",
+    "MetricExpr": "((L1D_ONNODE_MEM_SOURCED_WRITES + L1D_ONDRAWER_MEM_SOURCED_WRITES + L1D_OFFDRAWER_MEM_SOURCED_WRITES + L1D_ONCHIP_MEM_SOURCED_WRITES + L1I_ONNODE_MEM_SOURCED_WRITES + L1I_ONDRAWER_MEM_SOURCED_WRITES + L1I_OFFDRAWER_MEM_SOURCED_WRITES + L1I_ONCHIP_MEM_SOURCED_WRITES) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100"
   }
 ]