dt-bindings: pinctrl: qcom: lpass-lpi: correct description of second reg
Commit Message
The description of second IO address is a bit confusing. It is supposed
to be the MCC range which contains the slew rate registers, not the slew
rate register base. The Linux driver then accesses slew rate register
with hard-coded offset (0xa000).
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
.../bindings/pinctrl/qcom,sc8280xp-lpass-lpi-pinctrl.yaml | 2 +-
.../bindings/pinctrl/qcom,sm8450-lpass-lpi-pinctrl.yaml | 2 +-
.../bindings/pinctrl/qcom,sm8550-lpass-lpi-pinctrl.yaml | 2 +-
3 files changed, 3 insertions(+), 3 deletions(-)
Comments
On Thu, Mar 2, 2023 at 4:52 PM Krzysztof Kozlowski
<krzysztof.kozlowski@linaro.org> wrote:
> The description of second IO address is a bit confusing. It is supposed
> to be the MCC range which contains the slew rate registers, not the slew
> rate register base. The Linux driver then accesses slew rate register
> with hard-coded offset (0xa000).
>
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
LGTM, is this something I should just apply or will you collect a larger
series of Qcom DT patches this time around as well?
Yours,
Linus Walleij
On 07/03/2023 14:32, Linus Walleij wrote:
> On Thu, Mar 2, 2023 at 4:52 PM Krzysztof Kozlowski
> <krzysztof.kozlowski@linaro.org> wrote:
>
>> The description of second IO address is a bit confusing. It is supposed
>> to be the MCC range which contains the slew rate registers, not the slew
>> rate register base. The Linux driver then accesses slew rate register
>> with hard-coded offset (0xa000).
>>
>> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
>
> LGTM, is this something I should just apply or will you collect a larger
> series of Qcom DT patches this time around as well?
Please grab it. I think I cleaned up Qualcomm pinctrl bindings from
technical debt, thus no more work for me!
Best regards,
Krzysztof
On Thu, 02 Mar 2023 16:52:55 +0100, Krzysztof Kozlowski wrote:
> The description of second IO address is a bit confusing. It is supposed
> to be the MCC range which contains the slew rate registers, not the slew
> rate register base. The Linux driver then accesses slew rate register
> with hard-coded offset (0xa000).
>
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> ---
> .../bindings/pinctrl/qcom,sc8280xp-lpass-lpi-pinctrl.yaml | 2 +-
> .../bindings/pinctrl/qcom,sm8450-lpass-lpi-pinctrl.yaml | 2 +-
> .../bindings/pinctrl/qcom,sm8550-lpass-lpi-pinctrl.yaml | 2 +-
> 3 files changed, 3 insertions(+), 3 deletions(-)
>
Acked-by: Rob Herring <robh@kernel.org>
On Tue, Mar 7, 2023 at 2:40 PM Krzysztof Kozlowski
<krzysztof.kozlowski@linaro.org> wrote:
> On 07/03/2023 14:32, Linus Walleij wrote:
> > On Thu, Mar 2, 2023 at 4:52 PM Krzysztof Kozlowski
> > <krzysztof.kozlowski@linaro.org> wrote:
> >
> >> The description of second IO address is a bit confusing. It is supposed
> >> to be the MCC range which contains the slew rate registers, not the slew
> >> rate register base. The Linux driver then accesses slew rate register
> >> with hard-coded offset (0xa000).
> >>
> >> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> >
> > LGTM, is this something I should just apply or will you collect a larger
> > series of Qcom DT patches this time around as well?
>
> Please grab it. I think I cleaned up Qualcomm pinctrl bindings from
> technical debt, thus no more work for me!
OK patch applied!
Also: good job! The Qualcomm bindings look very nice now.
But what about these oldskool bindings?
$ ls Documentation/devicetree/bindings/pinctrl/qcom,*.txt
Documentation/devicetree/bindings/pinctrl/qcom,apq8064-pinctrl.txt
Documentation/devicetree/bindings/pinctrl/qcom,ipq4019-pinctrl.txt
Documentation/devicetree/bindings/pinctrl/qcom,apq8084-pinctrl.txt
Documentation/devicetree/bindings/pinctrl/qcom,ipq8064-pinctrl.txt
Yours,
Linus Walleij
On 09/03/2023 14:46, Linus Walleij wrote:
>> Please grab it. I think I cleaned up Qualcomm pinctrl bindings from
>> technical debt, thus no more work for me!
>
> OK patch applied!
>
> Also: good job! The Qualcomm bindings look very nice now.
>
> But what about these oldskool bindings?
> $ ls Documentation/devicetree/bindings/pinctrl/qcom,*.txt
> Documentation/devicetree/bindings/pinctrl/qcom,apq8064-pinctrl.txt
> Documentation/devicetree/bindings/pinctrl/qcom,ipq4019-pinctrl.txt
> Documentation/devicetree/bindings/pinctrl/qcom,apq8084-pinctrl.txt
> Documentation/devicetree/bindings/pinctrl/qcom,ipq8064-pinctrl.txt
Low priority for me, but I will get to them at some point :)
Best regards,
Krzysztof
@@ -20,7 +20,7 @@ properties:
reg:
items:
- description: LPASS LPI TLMM Control and Status registers
- - description: LPASS LPI pins SLEW registers
+ - description: LPASS LPI MCC registers
clocks:
items:
@@ -20,7 +20,7 @@ properties:
reg:
items:
- description: LPASS LPI TLMM Control and Status registers
- - description: LPASS LPI pins SLEW registers
+ - description: LPASS LPI MCC registers
clocks:
items:
@@ -21,7 +21,7 @@ properties:
reg:
items:
- description: LPASS LPI TLMM Control and Status registers
- - description: LPASS LPI pins SLEW registers
+ - description: LPASS LPI MCC registers
clocks:
items: