Message ID | 20230308104009.260451-8-brgl@bgdev.pl |
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arm64: dts: qcom: sa8775p-ride: enable relevant QUPv3 IPs
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Commit Message
Bartosz Golaszewski
March 8, 2023, 10:40 a.m. UTC
From: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Add two UART nodes that are known to be used by existing development boards with this SoC. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> --- arch/arm64/boot/dts/qcom/sa8775p.dtsi | 31 +++++++++++++++++++++++++++ 1 file changed, 31 insertions(+)
Comments
On 8.03.2023 11:40, Bartosz Golaszewski wrote: > From: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> > > Add two UART nodes that are known to be used by existing development > boards with this SoC. > > Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> > --- > arch/arm64/boot/dts/qcom/sa8775p.dtsi | 31 +++++++++++++++++++++++++++ > 1 file changed, 31 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi > index 992864e3e0c8..5ebfe8c10eac 100644 > --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi > +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi > @@ -490,6 +490,21 @@ &clk_virt SLAVE_QUP_CORE_1 0>, > operating-points-v2 = <&qup_opp_table_100mhz>; > status = "disabled"; > }; > + > + uart12: serial@a94000 { > + compatible = "qcom,geni-uart"; > + reg = <0x0 0x00a94000 0x0 0x4000>; > + interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; > + clock-names = "se"; > + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS > + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, > + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS > + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; > + interconnect-names = "qup-core", "qup-config"; > + power-domains = <&rpmhpd SA8775P_CX>; > + status = "disabled"; > + }; > }; > > qupv3_id_2: geniqup@8c0000 { > @@ -525,6 +540,22 @@ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, > status = "disabled"; > }; > > + uart17: serial@88c000 { > + compatible = "qcom,geni-uart"; > + reg = <0x0 0x0088c000 0x0 0x4000>; > + interrupts-extended = <&intc GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>, > + <&tlmm 94 IRQ_TYPE_LEVEL_HIGH>; This hunk is board-specific and only makes sense if bluetooth (or some other "important" peripheral) is connected to this uart. Generally the uart interrupt is the one coming from the GIC and the other one should probably go to the board dtsi. Konrad > + clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; > + clock-names = "se"; > + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS > + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, > + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS > + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; > + interconnect-names = "qup-core", "qup-config"; > + power-domains = <&rpmhpd SA8775P_CX>; > + status = "disabled"; > + }; > + > i2c18: i2c@890000 { > compatible = "qcom,geni-i2c"; > reg = <0x0 0x00890000 0x0 0x4000>;
On Wed, Mar 8, 2023 at 11:57 AM Konrad Dybcio <konrad.dybcio@linaro.org> wrote: > > > > On 8.03.2023 11:40, Bartosz Golaszewski wrote: > > From: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> > > > > Add two UART nodes that are known to be used by existing development > > boards with this SoC. > > > > Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> > > --- > > arch/arm64/boot/dts/qcom/sa8775p.dtsi | 31 +++++++++++++++++++++++++++ > > 1 file changed, 31 insertions(+) > > > > diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi > > index 992864e3e0c8..5ebfe8c10eac 100644 > > --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi > > +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi > > @@ -490,6 +490,21 @@ &clk_virt SLAVE_QUP_CORE_1 0>, > > operating-points-v2 = <&qup_opp_table_100mhz>; > > status = "disabled"; > > }; > > + > > + uart12: serial@a94000 { > > + compatible = "qcom,geni-uart"; > > + reg = <0x0 0x00a94000 0x0 0x4000>; > > + interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; > > + clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; > > + clock-names = "se"; > > + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS > > + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, > > + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS > > + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; > > + interconnect-names = "qup-core", "qup-config"; > > + power-domains = <&rpmhpd SA8775P_CX>; > > + status = "disabled"; > > + }; > > }; > > > > qupv3_id_2: geniqup@8c0000 { > > @@ -525,6 +540,22 @@ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, > > status = "disabled"; > > }; > > > > + uart17: serial@88c000 { > > + compatible = "qcom,geni-uart"; > > + reg = <0x0 0x0088c000 0x0 0x4000>; > > + interrupts-extended = <&intc GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>, > > + <&tlmm 94 IRQ_TYPE_LEVEL_HIGH>; > This hunk is board-specific and only makes sense if bluetooth > (or some other "important" peripheral) is connected to this > uart. Generally the uart interrupt is the one coming from the GIC > and the other one should probably go to the board dtsi. > Right, the second one will be consumed by whatever driver will be there to control GNSS or bluetooth. I'll drop it in the next spin. Bart > Konrad > > + clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; > > + clock-names = "se"; > > + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS > > + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, > > + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS > > + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; > > + interconnect-names = "qup-core", "qup-config"; > > + power-domains = <&rpmhpd SA8775P_CX>; > > + status = "disabled"; > > + }; > > + > > i2c18: i2c@890000 { > > compatible = "qcom,geni-i2c"; > > reg = <0x0 0x00890000 0x0 0x4000>;
diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi index 992864e3e0c8..5ebfe8c10eac 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -490,6 +490,21 @@ &clk_virt SLAVE_QUP_CORE_1 0>, operating-points-v2 = <&qup_opp_table_100mhz>; status = "disabled"; }; + + uart12: serial@a94000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0x00a94000 0x0 0x4000>; + interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", "qup-config"; + power-domains = <&rpmhpd SA8775P_CX>; + status = "disabled"; + }; }; qupv3_id_2: geniqup@8c0000 { @@ -525,6 +540,22 @@ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, status = "disabled"; }; + uart17: serial@88c000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0x0088c000 0x0 0x4000>; + interrupts-extended = <&intc GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>, + <&tlmm 94 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", "qup-config"; + power-domains = <&rpmhpd SA8775P_CX>; + status = "disabled"; + }; + i2c18: i2c@890000 { compatible = "qcom,geni-i2c"; reg = <0x0 0x00890000 0x0 0x4000>;