diff mbox series

[v3,4/7] arm64: dts: mediatek: mt8186: Add ADSP node

Message ID 20230303031728.24251-5-allen-kh.cheng@mediatek.com
State New
Headers
Series Add and update some driver nodes for MT8186 SoC |

Commit Message

Allen-KH Cheng March 3, 2023, 3:17 a.m. UTC 
  Add ADSP node for MT8186 SoC.

Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
---
 arch/arm64/boot/dts/mediatek/mt8186.dtsi | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

Comments

AngeloGioacchino Del Regno March 3, 2023, 11:31 a.m. UTC | #1 
Il 03/03/23 04:17, Allen-KH Cheng ha scritto:
> Add ADSP node for MT8186 SoC.
> 
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> ---
>   arch/arm64/boot/dts/mediatek/mt8186.dtsi | 16 ++++++++++++++++
>   1 file changed, 16 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
> index 0e42bdbd2cb6..337bcf3c1571 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
> @@ -633,6 +633,22 @@
>   			interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH 0>;
>   		};
>   
> +		adsp: adsp@10680000 {
> +			compatible = "mediatek,mt8186-dsp";
> +			reg = <0 0x10680000 0 0x2000>, <0 0x10800000 0 0x100000>,
> +			      <0 0x1068b000 0 0x100>, <0 0x1068f000 0 0x1000>;
> +			reg-names = "cfg", "sram", "sec", "bus";
> +			clocks = <&topckgen CLK_TOP_AUDIODSP>, <&topckgen CLK_TOP_ADSP_BUS>;

Was missing <&topckgen CLK_TOP_AUDIO_H> intentional here?

AFAIK, that's required for the ADSP.

Regards,
Angelo
Allen-KH Cheng March 17, 2023, 5:17 a.m. UTC | #2 
Hi Angelo,

On Fri, 2023-03-03 at 12:31 +0100, AngeloGioacchino Del Regno wrote:
> Il 03/03/23 04:17, Allen-KH Cheng ha scritto:
> > Add ADSP node for MT8186 SoC.
> > 
> > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> > ---
> >   arch/arm64/boot/dts/mediatek/mt8186.dtsi | 16 ++++++++++++++++
> >   1 file changed, 16 insertions(+)
> > 
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi
> > b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
> > index 0e42bdbd2cb6..337bcf3c1571 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
> > @@ -633,6 +633,22 @@
> >   			interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
> > 0>;
> >   		};
> >   
> > +		adsp: adsp@10680000 {
> > +			compatible = "mediatek,mt8186-dsp";
> > +			reg = <0 0x10680000 0 0x2000>, <0 0x10800000 0
> > 0x100000>,
> > +			      <0 0x1068b000 0 0x100>, <0 0x1068f000 0
> > 0x1000>;
> > +			reg-names = "cfg", "sram", "sec", "bus";
> > +			clocks = <&topckgen CLK_TOP_AUDIODSP>,
> > <&topckgen CLK_TOP_ADSP_BUS>;
> 
> Was missing <&topckgen CLK_TOP_AUDIO_H> intentional here?
> 
> AFAIK, that's required for the ADSP.
> 
> Regards,
> Angelo


This may be dependent on the design of the chipset.

CLK_TOP_AUDIO_H will be used by the afe (audio-controller) node. This
is not used for DSP in the MT8186 architecture.

Thanks,
Allen
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
index 0e42bdbd2cb6..337bcf3c1571 100644
--- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
@@ -633,6 +633,22 @@ 
 			interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH 0>;
 		};
 
+		adsp: adsp@10680000 {
+			compatible = "mediatek,mt8186-dsp";
+			reg = <0 0x10680000 0 0x2000>, <0 0x10800000 0 0x100000>,
+			      <0 0x1068b000 0 0x100>, <0 0x1068f000 0 0x1000>;
+			reg-names = "cfg", "sram", "sec", "bus";
+			clocks = <&topckgen CLK_TOP_AUDIODSP>, <&topckgen CLK_TOP_ADSP_BUS>;
+			clock-names = "audiodsp", "adsp_bus";
+			assigned-clocks = <&topckgen CLK_TOP_AUDIODSP>,
+					  <&topckgen CLK_TOP_ADSP_BUS>;
+			assigned-clock-parents = <&clk26m>, <&topckgen CLK_TOP_MAINPLL_D2_D2>;
+			mbox-names = "rx", "tx";
+			mboxes = <&adsp_mailbox0>, <&adsp_mailbox1>;
+			power-domains = <&spm MT8186_POWER_DOMAIN_ADSP_TOP>;
+			status = "disabled";
+		};
+
 		adsp_mailbox0: mailbox@10686000 {
 			compatible = "mediatek,mt8186-adsp-mbox";
 			#mbox-cells = <0>;