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From: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
To: andersson@kernel.org
Cc: konrad.dybcio@linaro.org, robh+dt@kernel.org,
krzysztof.kozlowski+dt@linaro.org, linux-arm-msm@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
arnd@arndb.de,
Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Subject: [PATCH 01/16] arm64: dts: qcom: sdm845: Fix the PCI I/O port range
Date: Tue, 28 Feb 2023 22:17:37 +0530
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| Series |
Qcom: Fix PCI I/O range defined in devicetree
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Commit Message
Manivannan Sadhasivam
Feb. 28, 2023, 4:47 p.m. UTC
For 1MiB of the I/O region, the I/O ports of the legacy PCI devices are
located in the range of 0x0 to 0x100000. Hence, fix the bogus PCI addresses
(0x60200000, 0x40200000) specified in the ranges property for I/O region.
While at it, let's use the missing 0x prefix for the addresses.
Fixes: 42ad231338c1 ("arm64: dts: qcom: sdm845: Add second PCIe PHY and controller")
Fixes: 5c538e09cb19 ("arm64: dts: qcom: sdm845: Add first PCIe controller and PHY")
Reported-by: Arnd Bergmann <arnd@arndb.de>
Link: https://lore.kernel.org/linux-arm-msm/7c5dfa87-41df-4ba7-b0e4-72c8386402a8@app.fastmail.com/
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
arch/arm64/boot/dts/qcom/sdm845.dtsi | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
Comments
On Tue, Feb 28, 2023, at 17:47, Manivannan Sadhasivam wrote: > For 1MiB of the I/O region, the I/O ports of the legacy PCI devices are > located in the range of 0x0 to 0x100000. Hence, fix the bogus PCI addresses > (0x60200000, 0x40200000) specified in the ranges property for I/O region. > - ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>, > - <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0xd00000>; > + ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, > + <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0xd00000>; > This fixes the offset, but I wonder if the size of the I/O window should be changed as well. The normal size is 64KB (0x10000) per bus or less, while this one has 1MB. It's probably harmless since each device would only use a few bytes, and most devices don't need any I/O ports at all. Arnd
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 479859bd8ab3..1c060ea960ff 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -2292,8 +2292,8 @@ pcie0: pci@1c00000 { #address-cells = <3>; #size-cells = <2>; - ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>, - <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0xd00000>; + ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, + <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0xd00000>; interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "msi"; @@ -2397,7 +2397,7 @@ pcie1: pci@1c08000 { #address-cells = <3>; #size-cells = <2>; - ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>, + ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; interrupts = <GIC_SPI 307 IRQ_TYPE_EDGE_RISING>;