Message ID | 20230221083323.302471-11-xingyu.wu@starfivetech.com |
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State | New |
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[2620:137:e000::1:20]) by mx.google.com with ESMTP id a28-20020a631a1c000000b004da39026083si17928627pga.345.2023.02.21.01.10.36; Tue, 21 Feb 2023 01:10:50 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233807AbjBUIeK convert rfc822-to-8bit (ORCPT <rfc822;kautuk.consul.80@gmail.com> + 99 others); Tue, 21 Feb 2023 03:34:10 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49420 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233762AbjBUIdo (ORCPT <rfc822;linux-kernel@vger.kernel.org>); Tue, 21 Feb 2023 03:33:44 -0500 Received: from fd01.gateway.ufhost.com (fd01.gateway.ufhost.com [61.152.239.71]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F356A8684; Tue, 21 Feb 2023 00:33:42 -0800 (PST) Received: from EXMBX165.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX165", Issuer "EXMBX165" (not verified)) by fd01.gateway.ufhost.com (Postfix) with ESMTP id 7E7AC24E3A3; Tue, 21 Feb 2023 16:33:38 +0800 (CST) Received: from EXMBX061.cuchost.com (172.16.6.61) by EXMBX165.cuchost.com (172.16.6.75) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Tue, 21 Feb 2023 16:33:38 +0800 Received: from localhost.localdomain (183.27.98.67) by EXMBX061.cuchost.com (172.16.6.61) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Tue, 21 Feb 2023 16:33:37 +0800 From: Xingyu Wu <xingyu.wu@starfivetech.com> To: <linux-riscv@lists.infradead.org>, <devicetree@vger.kernel.org>, "Michael Turquette" <mturquette@baylibre.com>, Stephen Boyd <sboyd@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Philipp Zabel <p.zabel@pengutronix.de>, Emil Renner Berthing <kernel@esmil.dk> CC: Rob Herring <robh+dt@kernel.org>, Conor Dooley <conor@kernel.org>, "Paul Walmsley" <paul.walmsley@sifive.com>, Palmer Dabbelt <palmer@dabbelt.com>, Albert Ou <aou@eecs.berkeley.edu>, Hal Feng <hal.feng@starfivetech.com>, Xingyu Wu <xingyu.wu@starfivetech.com>, <linux-kernel@vger.kernel.org>, <linux-clk@vger.kernel.org> Subject: [PATCH v2 10/11] riscv: dts: starfive: jh7110: Add DVP and HDMI TX pixel external clocks Date: Tue, 21 Feb 2023 16:33:22 +0800 Message-ID: <20230221083323.302471-11-xingyu.wu@starfivetech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230221083323.302471-1-xingyu.wu@starfivetech.com> References: <20230221083323.302471-1-xingyu.wu@starfivetech.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [183.27.98.67] X-ClientProxiedBy: EXCAS066.cuchost.com (172.16.6.26) To EXMBX061.cuchost.com (172.16.6.61) X-YovoleRuleAgent: yovoleflag Content-Transfer-Encoding: 8BIT X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,RCVD_IN_MSPIKE_H2, SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: <linux-kernel.vger.kernel.org> X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1758431175988620204?= X-GMAIL-MSGID: =?utf-8?q?1758431175988620204?= |
Series |
Add new partial clock and reset drivers for StarFive JH7110
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Commit Message
Xingyu Wu
Feb. 21, 2023, 8:33 a.m. UTC
Add DVP and HDMI TX pixel external fixed clocks and the rates are
74.25MHz and 297MHz.
Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
---
.../dts/starfive/jh7110-starfive-visionfive-2.dtsi | 8 ++++++++
arch/riscv/boot/dts/starfive/jh7110.dtsi | 12 ++++++++++++
2 files changed, 20 insertions(+)
Comments
On Tue, Feb 21, 2023 at 04:33:22PM +0800, Xingyu Wu wrote: > Add DVP and HDMI TX pixel external fixed clocks and the rates are > 74.25MHz and 297MHz. > > Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com> > --- > .../dts/starfive/jh7110-starfive-visionfive-2.dtsi | 8 ++++++++ > arch/riscv/boot/dts/starfive/jh7110.dtsi | 12 ++++++++++++ > 2 files changed, 20 insertions(+) > > diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi > index c2aa8946a0f1..27af817a55aa 100644 > --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi > +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi > @@ -86,6 +86,14 @@ &mclk_ext { > clock-frequency = <12288000>; > }; > > +&dvp_clk { > + clock-frequency = <74250000>; > +}; > + > +&hdmitx0_pixelclk { > + clock-frequency = <297000000>; > +}; > + > &uart0 { > pinctrl-names = "default"; > pinctrl-0 = <&uart0_pins>; > diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi > index 005ead2624d4..a5e6fb3ad188 100644 > --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi > +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi > @@ -245,6 +245,18 @@ mclk_ext: mclk-ext-clock { > #clock-cells = <0>; > }; > > + dvp_clk: dvp-clk-clock { > + compatible = "fixed-clock"; > + clock-output-names = "dvp_clk"; > + #clock-cells = <0>; > + }; > + > + hdmitx0_pixelclk: hdmitx0-pixelclk-clock { > + compatible = "fixed-clock"; > + clock-output-names = "hdmitx0_pixelclk"; > + #clock-cells = <0>; > + }; > + Hmm, would you mind adding these entries with no unit addresses in alphanumerical order? Both in the soc & board dtsi files. Thanks, Conor.
On 2023/2/28 3:55, Conor Dooley wrote: > On Tue, Feb 21, 2023 at 04:33:22PM +0800, Xingyu Wu wrote: >> Add DVP and HDMI TX pixel external fixed clocks and the rates are >> 74.25MHz and 297MHz. >> >> Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com> >> --- >> .../dts/starfive/jh7110-starfive-visionfive-2.dtsi | 8 ++++++++ >> arch/riscv/boot/dts/starfive/jh7110.dtsi | 12 ++++++++++++ >> 2 files changed, 20 insertions(+) >> >> diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi >> index c2aa8946a0f1..27af817a55aa 100644 >> --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi >> +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi >> @@ -86,6 +86,14 @@ &mclk_ext { >> clock-frequency = <12288000>; >> }; >> >> +&dvp_clk { >> + clock-frequency = <74250000>; >> +}; >> + >> +&hdmitx0_pixelclk { >> + clock-frequency = <297000000>; >> +}; >> + >> &uart0 { >> pinctrl-names = "default"; >> pinctrl-0 = <&uart0_pins>; >> diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi >> index 005ead2624d4..a5e6fb3ad188 100644 >> --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi >> +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi >> @@ -245,6 +245,18 @@ mclk_ext: mclk-ext-clock { >> #clock-cells = <0>; >> }; >> >> + dvp_clk: dvp-clk-clock { >> + compatible = "fixed-clock"; >> + clock-output-names = "dvp_clk"; >> + #clock-cells = <0>; >> + }; >> + >> + hdmitx0_pixelclk: hdmitx0-pixelclk-clock { >> + compatible = "fixed-clock"; >> + clock-output-names = "hdmitx0_pixelclk"; >> + #clock-cells = <0>; >> + }; >> + > > Hmm, would you mind adding these entries with no unit addresses in > alphanumerical order? Both in the soc & board dtsi files. > Oh, It was my negligence. I will adjust it. Thanks. Best regards, Xingyu Wu
diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi index c2aa8946a0f1..27af817a55aa 100644 --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi @@ -86,6 +86,14 @@ &mclk_ext { clock-frequency = <12288000>; }; +&dvp_clk { + clock-frequency = <74250000>; +}; + +&hdmitx0_pixelclk { + clock-frequency = <297000000>; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pins>; diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi index 005ead2624d4..a5e6fb3ad188 100644 --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi @@ -245,6 +245,18 @@ mclk_ext: mclk-ext-clock { #clock-cells = <0>; }; + dvp_clk: dvp-clk-clock { + compatible = "fixed-clock"; + clock-output-names = "dvp_clk"; + #clock-cells = <0>; + }; + + hdmitx0_pixelclk: hdmitx0-pixelclk-clock { + compatible = "fixed-clock"; + clock-output-names = "hdmitx0_pixelclk"; + #clock-cells = <0>; + }; + soc { compatible = "simple-bus"; interrupt-parent = <&plic>;