diff mbox series

[GAS,Aarch64] Add Binutils support for MEC

Message ID 877651c1-3d70-6985-54b3-e4416bed3048@arm.com
State Not Applicable
Headers
Series [GAS,Aarch64] Add Binutils support for MEC |

Checks

Context Check Description
snail/binutils-gdb-check fail Git am fail log

Commit Message

Richard Ball Feb. 23, 2023, 3:18 p.m. UTC 
  This patch adds support for 8 new system registers.

MECIDR_EL2
MECID_P0_EL2
MECID_A0_EL2
MECID_P1_EL2
MECID_A1_EL2
VMECID_P_EL2
VMECID_A_EL2
MECID_RL_A_EL3

This change supports MEC which is part of RME
(Realm Management Extension).

All tests pass on aarch64-none-elf

gas/ChangeLog:

	* testsuite/gas/aarch64/mec-invalid.d: New test.
	* testsuite/gas/aarch64/mec-invalid.l: New test.
	* testsuite/gas/aarch64/mec-invalid.s: New test.
	* testsuite/gas/aarch64/mec.d: New test.
	* testsuite/gas/aarch64/mec.s: New test.

opcodes/ChangeLog:

	* aarch64-opc.c: Add MEC system registers.

Comments

Nick Clifton Feb. 27, 2023, 10:14 a.m. UTC | #1 
Hi Richard,

> This patch adds support for 8 new system registers.
> 
> MECIDR_EL2
> MECID_P0_EL2
> MECID_A0_EL2
> MECID_P1_EL2
> MECID_A1_EL2
> VMECID_P_EL2
> VMECID_A_EL2
> MECID_RL_A_EL3
> 
> This change supports MEC which is part of RME
> (Realm Management Extension).
> 
> All tests pass on aarch64-none-elf
> 
> gas/ChangeLog:
> 
>      * testsuite/gas/aarch64/mec-invalid.d: New test.
>      * testsuite/gas/aarch64/mec-invalid.l: New test.
>      * testsuite/gas/aarch64/mec-invalid.s: New test.
>      * testsuite/gas/aarch64/mec.d: New test.
>      * testsuite/gas/aarch64/mec.s: New test.
> 
> opcodes/ChangeLog:
> 
>      * aarch64-opc.c: Add MEC system registers.

Patch approved - please apply.

Cheers
   Nick
Richard Ball Feb. 27, 2023, 4:39 p.m. UTC | #2 
Hi Nick,

Apologies for not mentioning in my original patch,
could you please commit this patch on my behalf as
I don't have commit rights yet.

It is a patch for binutils-2.41.

On 2/27/2023 10:14 AM, Nick Clifton wrote:
> Hi Richard,
> 
>> This patch adds support for 8 new system registers.
>>
>> MECIDR_EL2
>> MECID_P0_EL2
>> MECID_A0_EL2
>> MECID_P1_EL2
>> MECID_A1_EL2
>> VMECID_P_EL2
>> VMECID_A_EL2
>> MECID_RL_A_EL3
>>
>> This change supports MEC which is part of RME
>> (Realm Management Extension).
>>
>> All tests pass on aarch64-none-elf
>>
>> gas/ChangeLog:
>>
>>      * testsuite/gas/aarch64/mec-invalid.d: New test.
>>      * testsuite/gas/aarch64/mec-invalid.l: New test.
>>      * testsuite/gas/aarch64/mec-invalid.s: New test.
>>      * testsuite/gas/aarch64/mec.d: New test.
>>      * testsuite/gas/aarch64/mec.s: New test.
>>
>> opcodes/ChangeLog:
>>
>>      * aarch64-opc.c: Add MEC system registers.
> 
> Patch approved - please apply.
> 
> Cheers
>    Nick
> 
> 

Thanks very much,
Richard
Nick Clifton Feb. 28, 2023, 12:04 p.m. UTC | #3 
Hi Richard,

> Apologies for not mentioning in my original patch,
> could you please commit this patch on my behalf as
> I don't have commit rights yet.

Done.

Cheers
   Nick
diff mbox series

Patch

diff --git a/gas/testsuite/gas/aarch64/mec-invalid.d 
b/gas/testsuite/gas/aarch64/mec-invalid.d
new file mode 100644
index 
0000000000000000000000000000000000000000..b071a34837ad075324f7ca6445f7a0bcc3e0c7f3
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/mec-invalid.d
@@ -0,0 +1,3 @@ 
+#name: Invalid MEC System registers usage
+#source: mec-invalid.s
+#warning_output: mec-invalid.l
diff --git a/gas/testsuite/gas/aarch64/mec-invalid.l 
b/gas/testsuite/gas/aarch64/mec-invalid.l
new file mode 100644
index 
0000000000000000000000000000000000000000..32e7f53960a4c74491f5ce651e1e23ec8af5af7b
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/mec-invalid.l
@@ -0,0 +1,2 @@ 
+.*: Assembler messages:
+.*: Warning: specified register cannot be written to at operand 1 -- 
`msr mecidr_el2,x0'
diff --git a/gas/testsuite/gas/aarch64/mec-invalid.s 
b/gas/testsuite/gas/aarch64/mec-invalid.s
new file mode 100644
index 
0000000000000000000000000000000000000000..9f7f1cd9fb210fbd7503760e48a125feeb411308
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/mec-invalid.s
@@ -0,0 +1,4 @@ 
+// Memory Encryption Contexts, an extension of RME.
+
+// Illegal write to MEC system registers.
+msr mecidr_el2, x0
diff --git a/gas/testsuite/gas/aarch64/mec.d 
b/gas/testsuite/gas/aarch64/mec.d
new file mode 100644
index 
0000000000000000000000000000000000000000..118575d642b8581c5b95a4cb7f4d1b9c6e73d075
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/mec.d
@@ -0,0 +1,24 @@ 
+#name: MEC System registers
+#objdump: -dr
+
+.*:     file format .*
+
+Disassembly of section .text:
+
+0+ <.*>:
+
+[^:]*:	d53ca8e0 	mrs	x0, mecidr_el2
+[^:]*:	d53ca800 	mrs	x0, mecid_p0_el2
+[^:]*:	d53ca820 	mrs	x0, mecid_a0_el2
+[^:]*:	d53ca840 	mrs	x0, mecid_p1_el2
+[^:]*:	d53ca860 	mrs	x0, mecid_a1_el2
+[^:]*:	d53ca900 	mrs	x0, vmecid_p_el2
+[^:]*:	d53ca920 	mrs	x0, vmecid_a_el2
+[^:]*:	d53eaa20 	mrs	x0, mecid_rl_a_el3
+[^:]*:	d51ca800 	msr	mecid_p0_el2, x0
+[^:]*:	d51ca820 	msr	mecid_a0_el2, x0
+[^:]*:	d51ca840 	msr	mecid_p1_el2, x0
+[^:]*:	d51ca860 	msr	mecid_a1_el2, x0
+[^:]*:	d51ca900 	msr	vmecid_p_el2, x0
+[^:]*:	d51ca920 	msr	vmecid_a_el2, x0
+[^:]*:	d51eaa20 	msr	mecid_rl_a_el3, x0
diff --git a/gas/testsuite/gas/aarch64/mec.s 
b/gas/testsuite/gas/aarch64/mec.s
new file mode 100644
index 
0000000000000000000000000000000000000000..d89a2748d9b913e00353af9ca08812afc3db4eb6
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/mec.s
@@ -0,0 +1,20 @@ 
+// Memory Encryption Contexts, an extension of RME.
+
+// Read from MEC system registers.
+mrs x0, mecidr_el2
+mrs x0, mecid_p0_el2
+mrs x0, mecid_a0_el2
+mrs x0, mecid_p1_el2
+mrs x0, mecid_a1_el2
+mrs x0, vmecid_p_el2
+mrs x0, vmecid_a_el2
+mrs x0, mecid_rl_a_el3
+
+// Write to MEC system registers.
+msr mecid_p0_el2, x0
+msr mecid_a0_el2, x0
+msr mecid_p1_el2, x0
+msr mecid_a1_el2, x0
+msr vmecid_p_el2, x0
+msr vmecid_a_el2, x0
+msr mecid_rl_a_el3, x0
diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
index 
886befff99e60d6a7e2ec5d8ef40e911b4c075c8..e271b0d5e8edeeefe6e2735a14116f248b8c0f9a 
100644
--- a/opcodes/aarch64-opc.c
+++ b/opcodes/aarch64-opc.c
@@ -5010,6 +5010,15 @@  const aarch64_sys_reg aarch64_sys_regs [] =
    SR_CORE ("gpccr_el3",     CPENC (3,6,C2,C1,6), 0),
    SR_CORE ("gptbr_el3",     CPENC (3,6,C2,C1,4), 0),

+  SR_CORE ("mecidr_el2",    CPENC (3,4,C10,C8,7),  F_REG_READ),
+  SR_CORE ("mecid_p0_el2",  CPENC (3,4,C10,C8,0),  0),
+  SR_CORE ("mecid_a0_el2",  CPENC (3,4,C10,C8,1),  0),
+  SR_CORE ("mecid_p1_el2",  CPENC (3,4,C10,C8,2),  0),
+  SR_CORE ("mecid_a1_el2",  CPENC (3,4,C10,C8,3),  0),
+  SR_CORE ("vmecid_p_el2",  CPENC (3,4,C10,C9,0),  0),
+  SR_CORE ("vmecid_a_el2",  CPENC (3,4,C10,C9,1),  0),
+  SR_CORE ("mecid_rl_a_el3",CPENC (3,6,C10,C10,1), 0),
+
    SR_SME ("svcr",             CPENC (3,3,C4,C2,2),  0),
    SR_SME ("id_aa64smfr0_el1", CPENC (3,0,C0,C4,5),  F_REG_READ),
    SR_SME ("smcr_el1",         CPENC (3,0,C1,C2,6),  0),