@@ -1,5 +1,7 @@
-*- text -*-
+* Add support for Intel MSRLIST instructions.
+
* Add support for Intel WRMSRNS instructions.
* Add support for Intel RAO-INT instructions.
@@ -1100,6 +1100,7 @@ static const arch_entry cpu_arch[] =
SUBARCH (cmpccxadd, CMPCCXADD, ANY_CMPCCXADD, false),
SUBARCH (raoint, RAOINT, ANY_RAOINT, false),
SUBARCH (wrmsrns, WRMSRNS, ANY_WRMSRNS, false),
+ SUBARCH (msrlist, MSRLIST, ANY_MSRLIST, false),
};
#undef SUBARCH
@@ -219,6 +219,7 @@ accept various extension mnemonics. For example,
@code{cmpccxadd},
@code{raoint},
@code{wrmsrns},
+@code{msrlist},
@code{noavx512f},
@code{noavx512cd},
@code{noavx512er},
@@ -245,6 +246,7 @@ accept various extension mnemonics. For example,
@code{nocmpccxadd},
@code{noraoint},
@code{nowrmsrns},
+@code{nomsrlist},
@code{noenqcmd},
@code{noserialize},
@code{notsxldtrk},
@@ -1547,6 +1549,7 @@ supported on the CPU specified. The choices for @var{cpu_type} are:
@item @samp{.clwb} @tab @samp{.rdpid} @tab @samp{.ptwrite} @tab @samp{.ibt}
@item @samp{.avx_ifma} @tab @samp{.avx_vnni_int8} @tab @samp{.avx_ne_convert}
@item @samp{.cmpccxadd} @tab @samp{.raoint} @tab @samp{.wrmsrns}
+@item @samp{.msrlist}
@item @samp{.wbnoinvd} @tab @samp{.pconfig} @tab @samp{.waitpkg} @tab @samp{.cldemote}
@item @samp{.shstk} @tab @samp{.gfni} @tab @samp{.vaes} @tab @samp{.vpclmulqdq}
@item @samp{.movdiri} @tab @samp{.movdir64b} @tab @samp{.enqcmd} @tab @samp{.tsxldtrk}
@@ -490,6 +490,7 @@ if [gas_32_check] then {
run_dump_test "raoint-intel"
run_dump_test "wrmsrns"
run_dump_test "wrmsrns-intel"
+ run_list_test "msrlist-inval"
run_list_test "sg"
run_dump_test "clzero"
run_dump_test "invlpgb"
@@ -1170,6 +1171,8 @@ if [gas_64_check] then {
run_dump_test "x86-64-raoint-intel"
run_dump_test "x86-64-wrmsrns"
run_dump_test "x86-64-wrmsrns-intel"
+ run_dump_test "x86-64-msrlist"
+ run_dump_test "x86-64-msrlist-intel"
run_dump_test "x86-64-clzero"
run_dump_test "x86-64-mwaitx-bdver4"
run_list_test "x86-64-mwaitx-reg"
new file mode 100644
@@ -0,0 +1,3 @@
+.* Assembler messages:
+.*:6: Error: `rdmsrlist' is only supported in 64-bit mode
+.*:7: Error: `wrmsrlist' is only supported in 64-bit mode
new file mode 100644
@@ -0,0 +1,7 @@
+# Check Illegal MSRLIST instructions
+
+ .allow_index_reg
+ .text
+_start:
+ rdmsrlist #MSRLIST
+ wrmsrlist #MSRLIST
@@ -37,10 +37,10 @@
.*:42: Error: .*
.*:43: Error: .*
.*:44: Error: .*
-.*:47: Error: .*
-.*:48: Error: .*
+.*:45: Error: .*
+.*:46: Error: .*
+.*:49: Error: .*
.*:50: Error: .*
-.*:51: Error: .*
.*:52: Error: .*
.*:53: Error: .*
.*:54: Error: .*
@@ -67,14 +67,18 @@
.*:75: Error: .*
.*:76: Error: .*
.*:77: Error: .*
+.*:78: Error: .*
.*:79: Error: .*
-.*:80: Error: .*
.*:81: Error: .*
.*:82: Error: .*
.*:83: Error: .*
.*:84: Error: .*
.*:85: Error: .*
.*:86: Error: .*
+.*:87: Error: .*
+.*:88: Error: .*
+.*:89: Error: .*
+.*:90: Error: .*
GAS LISTING .*
@@ -122,48 +126,52 @@ GAS LISTING .*
[ ]*42[ ]+lock sub \(%rbx\), %eax
[ ]*43[ ]+lock xor \(%rbx\), %eax
[ ]*44[ ]+lock wrmsrns
-[ ]*45[ ]+
-[ ]*46[ ]+\.intel_syntax noprefix
-[ ]*47[ ]+lock mov eax,ebx
-[ ]*48[ ]+lock mov eax,DWORD PTR \[rbx\]
-[ ]*49[ ]+
-[ ]*50[ ]+lock add eax,ebx
-[ ]*51[ ]+lock add ebx,0x64
-[ ]*52[ ]+lock adc eax,ebx
-[ ]*53[ ]+lock adc ebx,0x64
-[ ]*54[ ]+lock and eax,ebx
-[ ]*55[ ]+lock and ebx,0x64
-[ ]*56[ ]+lock btc ebx,eax
-[ ]*57[ ]+lock btc ebx,0x64
+[ ]*45[ ]+lock rdmsrlist
+[ ]*46[ ]+lock wrmsrlist
+[ ]*47[ ]+
+[ ]*48[ ]+\.intel_syntax noprefix
+[ ]*49[ ]+lock mov eax,ebx
+[ ]*50[ ]+lock mov eax,DWORD PTR \[rbx\]
+[ ]*51[ ]+
+[ ]*52[ ]+lock add eax,ebx
+[ ]*53[ ]+lock add ebx,0x64
+[ ]*54[ ]+lock adc eax,ebx
+[ ]*55[ ]+lock adc ebx,0x64
+[ ]*56[ ]+lock and eax,ebx
+[ ]*57[ ]+lock and ebx,0x64
GAS LISTING .*
-[ ]*58[ ]+lock btr ebx,eax
-[ ]*59[ ]+lock btr ebx,0x64
-[ ]*60[ ]+lock bts ebx,eax
-[ ]*61[ ]+lock bts ebx,0x64
-[ ]*62[ ]+lock cmpxchg ebx,eax
-[ ]*63[ ]+lock dec ebx
-[ ]*64[ ]+lock inc ebx
-[ ]*65[ ]+lock neg ebx
-[ ]*66[ ]+lock not ebx
-[ ]*67[ ]+lock or eax,ebx
-[ ]*68[ ]+lock or ebx,0x64
-[ ]*69[ ]+lock sbb eax,ebx
-[ ]*70[ ]+lock sbb ebx,0x64
-[ ]*71[ ]+lock sub eax,ebx
-[ ]*72[ ]+lock sub ebx,0x64
-[ ]*73[ ]+lock xadd ebx,eax
-[ ]*74[ ]+lock xchg ebx,eax
-[ ]*75[ ]+lock xchg ebx,eax
-[ ]*76[ ]+lock xor eax,ebx
-[ ]*77[ ]+lock xor ebx,0x64
-[ ]*78[ ]+
-[ ]*79[ ]+lock add eax,DWORD PTR \[rbx\]
-[ ]*80[ ]+lock adc eax,DWORD PTR \[rbx\]
-[ ]*81[ ]+lock and eax,DWORD PTR \[rbx\]
-[ ]*82[ ]+lock or eax,DWORD PTR \[rbx\]
-[ ]*83[ ]+lock sbb eax,DWORD PTR \[rbx\]
-[ ]*84[ ]+lock sub eax,DWORD PTR \[rbx\]
-[ ]*85[ ]+lock xor eax,DWORD PTR \[rbx\]
-[ ]*86[ ]+lock wrmsrns
+[ ]*58[ ]+lock btc ebx,eax
+[ ]*59[ ]+lock btc ebx,0x64
+[ ]*60[ ]+lock btr ebx,eax
+[ ]*61[ ]+lock btr ebx,0x64
+[ ]*62[ ]+lock bts ebx,eax
+[ ]*63[ ]+lock bts ebx,0x64
+[ ]*64[ ]+lock cmpxchg ebx,eax
+[ ]*65[ ]+lock dec ebx
+[ ]*66[ ]+lock inc ebx
+[ ]*67[ ]+lock neg ebx
+[ ]*68[ ]+lock not ebx
+[ ]*69[ ]+lock or eax,ebx
+[ ]*70[ ]+lock or ebx,0x64
+[ ]*71[ ]+lock sbb eax,ebx
+[ ]*72[ ]+lock sbb ebx,0x64
+[ ]*73[ ]+lock sub eax,ebx
+[ ]*74[ ]+lock sub ebx,0x64
+[ ]*75[ ]+lock xadd ebx,eax
+[ ]*76[ ]+lock xchg ebx,eax
+[ ]*77[ ]+lock xchg ebx,eax
+[ ]*78[ ]+lock xor eax,ebx
+[ ]*79[ ]+lock xor ebx,0x64
+[ ]*80[ ]+
+[ ]*81[ ]+lock add eax,DWORD PTR \[rbx\]
+[ ]*82[ ]+lock adc eax,DWORD PTR \[rbx\]
+[ ]*83[ ]+lock and eax,DWORD PTR \[rbx\]
+[ ]*84[ ]+lock or eax,DWORD PTR \[rbx\]
+[ ]*85[ ]+lock sbb eax,DWORD PTR \[rbx\]
+[ ]*86[ ]+lock sub eax,DWORD PTR \[rbx\]
+[ ]*87[ ]+lock xor eax,DWORD PTR \[rbx\]
+[ ]*88[ ]+lock wrmsrns
+[ ]*89[ ]+lock rdmsrlist
+[ ]*90[ ]+lock wrmsrlist
@@ -42,6 +42,8 @@ foo:
lock sub (%rbx), %eax
lock xor (%rbx), %eax
lock wrmsrns
+ lock rdmsrlist
+ lock wrmsrlist
.intel_syntax noprefix
lock mov eax,ebx
@@ -84,3 +86,5 @@ foo:
lock sub eax,DWORD PTR [rbx]
lock xor eax,DWORD PTR [rbx]
lock wrmsrns
+ lock rdmsrlist
+ lock wrmsrlist
new file mode 100644
@@ -0,0 +1,14 @@
+#as:
+#objdump: -dw -Mintel
+#name: x86_64 MSRLIST insns (Intel disassembly)
+#source: x86-64-msrlist.s
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+0+ <_start>:
+\s*[a-f0-9]+:\s*f2 0f 01 c6\s+rdmsrlist
+\s*[a-f0-9]+:\s*f3 0f 01 c6\s+wrmsrlist
+\s*[a-f0-9]+:\s*f2 0f 01 c6\s+rdmsrlist
+\s*[a-f0-9]+:\s*f3 0f 01 c6\s+wrmsrlist
new file mode 100644
@@ -0,0 +1,14 @@
+#as:
+#objdump: -dw
+#name: x86_64 MSRLIST insns
+#source: x86-64-msrlist.s
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+0+ <_start>:
+\s*[a-f0-9]+:\s*f2 0f 01 c6\s+rdmsrlist
+\s*[a-f0-9]+:\s*f3 0f 01 c6\s+wrmsrlist
+\s*[a-f0-9]+:\s*f2 0f 01 c6\s+rdmsrlist
+\s*[a-f0-9]+:\s*f3 0f 01 c6\s+wrmsrlist
new file mode 100644
@@ -0,0 +1,11 @@
+# Check 64bit MSRLIST instructions
+
+ .allow_index_reg
+ .text
+_start:
+ rdmsrlist #MSRLIST
+ wrmsrlist #MSRLIST
+
+.intel_syntax noprefix
+ rdmsrlist #MSRLIST
+ wrmsrlist #MSRLIST
@@ -1281,6 +1281,8 @@ enum
X86_64_E9,
X86_64_EA,
X86_64_0F01_REG_0,
+ X86_64_0F01_REG_0_MOD_3_RM_6_P_1,
+ X86_64_0F01_REG_0_MOD_3_RM_6_P_3,
X86_64_0F01_REG_1,
X86_64_0F01_REG_1_RM_5_PREFIX_2,
X86_64_0F01_REG_1_RM_6_PREFIX_2,
@@ -2974,6 +2976,9 @@ static const struct dis386 prefix_table[][4] = {
/* PREFIX_0F01_REG_0_MOD_3_RM_6 */
{
{ "wrmsrns", { Skip_MODRM }, 0 },
+ { X86_64_TABLE (X86_64_0F01_REG_0_MOD_3_RM_6_P_1) },
+ { Bad_Opcode },
+ { X86_64_TABLE (X86_64_0F01_REG_0_MOD_3_RM_6_P_3) },
},
/* PREFIX_0F01_REG_1_RM_4 */
@@ -4315,6 +4320,18 @@ static const struct dis386 x86_64_table[][2] = {
{ "sgdt", { M }, 0 },
},
+ /* X86_64_0F01_REG_0_MOD_3_RM_6_P_1 */
+ {
+ { Bad_Opcode },
+ { "wrmsrlist", { Skip_MODRM }, 0 },
+ },
+
+ /* X86_64_0F01_REG_0_MOD_3_RM_6_P_3 */
+ {
+ { Bad_Opcode },
+ { "rdmsrlist", { Skip_MODRM }, 0 },
+ },
+
/* X86_64_0F01_REG_1 */
{
{ "sidt{Q|Q}", { M }, 0 },
@@ -257,6 +257,8 @@ static initializer cpu_flag_init[] =
"CpuRAOINT" },
{ "CPU_WRMSRNS_FLAGS",
"CpuWRMSRNS" },
+ { "CPU_MSRLIST_FLAGS",
+ "CpuMSRLIST" },
{ "CPU_IAMCU_FLAGS",
"Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuIAMCU" },
{ "CPU_ADX_FLAGS",
@@ -463,6 +465,8 @@ static initializer cpu_flag_init[] =
"CpuRAOINT" },
{ "CPU_ANY_WRMSRNS_FLAGS",
"CpuWRMSRNS" },
+ { "CPU_ANY_MSRLIST_FLAGS",
+ "CpuMSRLIST" },
};
static initializer operand_type_init[] =
@@ -670,6 +674,7 @@ static bitfield cpu_flags[] =
BITFIELD (CpuCMPCCXADD),
BITFIELD (CpuRAOINT),
BITFIELD (CpuWRMSRNS),
+ BITFIELD (CpuMSRLIST),
BITFIELD (CpuMWAITX),
BITFIELD (CpuCLZERO),
BITFIELD (CpuOSPKE),
@@ -221,6 +221,8 @@ enum
CpuRAOINT,
/* Intel WRMSRNS Instructions support required */
CpuWRMSRNS,
+ /* Intel MSRLIST Instructions support required. */
+ CpuMSRLIST,
/* mwaitx instruction required */
CpuMWAITX,
/* Clzero instruction required */
@@ -406,6 +408,7 @@ typedef union i386_cpu_flags
unsigned int cpucmpccxadd:1;
unsigned int cpuraoint:1;
unsigned int cpuwrmsrns:1;
+ unsigned int cpumsrlist:1;
unsigned int cpumwaitx:1;
unsigned int cpuclzero:1;
unsigned int cpuospke:1;
@@ -3332,3 +3332,10 @@ axor, 0xf30f38fc, None, CpuRAOINT, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_l
wrmsrns, 0x0f01c6, None, CpuWRMSRNS, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
// WRMSRNS instructions end.
+
+// MSRLIST instructions.
+
+rdmsrlist, 0xf20f01c6, None, CpuMSRLIST|Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
+wrmsrlist, 0xf30f01c6, None, CpuMSRLIST|Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
+
+// MSRLIST instructions end.