Message ID | 20230203181245.3523937-1-quic_bjorande@quicinc.com |
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State | New |
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[2620:137:e000::1:20]) by mx.google.com with ESMTP id v12-20020a056402348c00b004a114d3e1easi3951950edc.406.2023.02.03.10.20.08; Fri, 03 Feb 2023 10:20:36 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=lNFM6t6K; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233119AbjBCSNE (ORCPT <rfc822;il.mystafa@gmail.com> + 99 others); Fri, 3 Feb 2023 13:13:04 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46344 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231755AbjBCSND (ORCPT <rfc822;linux-kernel@vger.kernel.org>); Fri, 3 Feb 2023 13:13:03 -0500 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B0474211E; Fri, 3 Feb 2023 10:12:59 -0800 (PST) Received: from pps.filterd (m0279868.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 313HKuGj015312; Fri, 3 Feb 2023 18:12:52 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : mime-version : content-transfer-encoding : content-type; s=qcppdkim1; bh=fqQpv3FLRrrFIU3VTK6WAjqSO36QpMpTsucAWSbwDcM=; b=lNFM6t6KtSv/xt0oulbkPshGMGSq/v5mSkUSakTFv6ci49mj+FCr31wELyubSR64fhJX AOX60bmS/Xa4Tj/GjQXNRidBKV/u0NDi8q1WhMXXQoUbplKC7h1XvwleCuHDlgOyW6wq +Wg9poFNXV02FHbl8UDJ5ifQ3MSGO7QpMEvDIO9oVbjFxRPejjSSb8kpGIBXxFFbgxQq gbq4+8eDB9/FlWjXTGCRhKZ2poQtOPKGETF8a2ajJK/Afk31vfTGvbqjSnJpuRz5VpJv mwoxT8dcJ/TNAQR5DqHJcHhpgnZo/CZ+fd2loQ/F/cGyhHieyqoIwB4yiuSLwwTnOVhh yg== Received: from nalasppmta05.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3ngw4p9f1x-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 03 Feb 2023 18:12:52 +0000 Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA05.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 313ICpk9012727 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 3 Feb 2023 18:12:51 GMT Received: from hu-bjorande-lv.qualcomm.com (10.49.16.6) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.36; Fri, 3 Feb 2023 10:12:50 -0800 From: Bjorn Andersson <quic_bjorande@quicinc.com> To: Rob Clark <robdclark@gmail.com>, Abhinav Kumar <quic_abhinavk@quicinc.com>, Dmitry Baryshkov <dmitry.baryshkov@linaro.org>, Akhil P Oommen <quic_akhilpo@quicinc.com> CC: Sean Paul <sean@poorly.run>, David Airlie <airlied@gmail.com>, "Daniel Vetter" <daniel@ffwll.ch>, Konrad Dybcio <konrad.dybcio@somainline.org>, <linux-arm-msm@vger.kernel.org>, <dri-devel@lists.freedesktop.org>, <freedreno@lists.freedesktop.org>, <linux-kernel@vger.kernel.org> Subject: [RFC] drm/msm/adreno: Balance pm_runtime enable Date: Fri, 3 Feb 2023 10:12:45 -0800 Message-ID: <20230203181245.3523937-1-quic_bjorande@quicinc.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.49.16.6] X-ClientProxiedBy: nalasex01b.na.qualcomm.com (10.47.209.197) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: 0OTKZfOuRO0MlWtDZk3Pums6klRY0Mz1 X-Proofpoint-ORIG-GUID: 0OTKZfOuRO0MlWtDZk3Pums6klRY0Mz1 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.219,Aquarius:18.0.930,Hydra:6.0.562,FMLib:17.11.122.1 definitions=2023-02-03_17,2023-02-03_01,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 impostorscore=0 spamscore=0 suspectscore=0 adultscore=0 clxscore=1011 lowpriorityscore=0 mlxscore=0 phishscore=0 bulkscore=0 mlxlogscore=999 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2212070000 definitions=main-2302030166 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: <linux-kernel.vger.kernel.org> X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1756835019577874497?= X-GMAIL-MSGID: =?utf-8?q?1756835019577874497?= |
Series |
[RFC] drm/msm/adreno: Balance pm_runtime enable
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Commit Message
Bjorn Andersson
Feb. 3, 2023, 6:12 p.m. UTC
When any of the components in the mdss hierarchy fails to bind,
previously bound components are being unbound again.
One such case happens when the DP controller fails to find its bridge or
panel, where adreno_unbind() will be invoked without adreno_load_gpu()
being called to invoke pm_runtime_enable().
The result is that once everything is bound the pm_runtime_get_sync()
call find the power-domain to have a positive disable_depth, fails
with -EACCESS and prevents the GPU device to be powered up.
Move the pm_runtime_enable() to adreno_bind(), in order to balance it
with any calls to adreno_unbind().
Fixes: 4b18299b3365 ("drm/msm/adreno: Defer enabling runpm until hw_init()")
Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com>
---
drivers/gpu/drm/msm/adreno/adreno_device.c | 11 ++---------
1 file changed, 2 insertions(+), 9 deletions(-)
Comments
On Fri, Feb 3, 2023 at 10:12 AM Bjorn Andersson <quic_bjorande@quicinc.com> wrote: > > When any of the components in the mdss hierarchy fails to bind, > previously bound components are being unbound again. > > One such case happens when the DP controller fails to find its bridge or > panel, where adreno_unbind() will be invoked without adreno_load_gpu() > being called to invoke pm_runtime_enable(). > > The result is that once everything is bound the pm_runtime_get_sync() > call find the power-domain to have a positive disable_depth, fails > with -EACCESS and prevents the GPU device to be powered up. > > Move the pm_runtime_enable() to adreno_bind(), in order to balance it > with any calls to adreno_unbind(). I think instead we want to move where the pm_runtime_disable() is.. since pm_runtime_enable() was moved because we can't actually enable runpm until we have GMU firmware BR, -R > Fixes: 4b18299b3365 ("drm/msm/adreno: Defer enabling runpm until hw_init()") > Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com> > --- > drivers/gpu/drm/msm/adreno/adreno_device.c | 11 ++--------- > 1 file changed, 2 insertions(+), 9 deletions(-) > > diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c > index 36f062c7582f..ca38b837dedb 100644 > --- a/drivers/gpu/drm/msm/adreno/adreno_device.c > +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c > @@ -432,15 +432,6 @@ struct msm_gpu *adreno_load_gpu(struct drm_device *dev) > if (ret) > return NULL; > > - /* > - * Now that we have firmware loaded, and are ready to begin > - * booting the gpu, go ahead and enable runpm: > - */ > - pm_runtime_enable(&pdev->dev); > - > - /* Make sure pm runtime is active and reset any previous errors */ > - pm_runtime_set_active(&pdev->dev); > - > ret = pm_runtime_get_sync(&pdev->dev); > if (ret < 0) { > pm_runtime_put_sync(&pdev->dev); > @@ -548,6 +539,8 @@ static int adreno_bind(struct device *dev, struct device *master, void *data) > return PTR_ERR(gpu); > } > > + pm_runtime_enable(dev); > + > return 0; > } > > -- > 2.25.1 >
On Fri, Feb 10, 2023 at 08:10:00AM -0800, Rob Clark wrote: > On Fri, Feb 3, 2023 at 10:12 AM Bjorn Andersson > <quic_bjorande@quicinc.com> wrote: > > > > When any of the components in the mdss hierarchy fails to bind, > > previously bound components are being unbound again. > > > > One such case happens when the DP controller fails to find its bridge or > > panel, where adreno_unbind() will be invoked without adreno_load_gpu() > > being called to invoke pm_runtime_enable(). > > > > The result is that once everything is bound the pm_runtime_get_sync() > > call find the power-domain to have a positive disable_depth, fails > > with -EACCESS and prevents the GPU device to be powered up. > > > > Move the pm_runtime_enable() to adreno_bind(), in order to balance it > > with any calls to adreno_unbind(). > > I think instead we want to move where the pm_runtime_disable() is.. > since pm_runtime_enable() was moved because we can't actually enable > runpm until we have GMU firmware Here's a fix for this issue which does not move pm_runtime_enable() from first open(): https://lore.kernel.org/lkml/20230221101430.14546-1-johan+linaro@kernel.org/ Johan
diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c index 36f062c7582f..ca38b837dedb 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_device.c +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c @@ -432,15 +432,6 @@ struct msm_gpu *adreno_load_gpu(struct drm_device *dev) if (ret) return NULL; - /* - * Now that we have firmware loaded, and are ready to begin - * booting the gpu, go ahead and enable runpm: - */ - pm_runtime_enable(&pdev->dev); - - /* Make sure pm runtime is active and reset any previous errors */ - pm_runtime_set_active(&pdev->dev); - ret = pm_runtime_get_sync(&pdev->dev); if (ret < 0) { pm_runtime_put_sync(&pdev->dev); @@ -548,6 +539,8 @@ static int adreno_bind(struct device *dev, struct device *master, void *data) return PTR_ERR(gpu); } + pm_runtime_enable(dev); + return 0; }