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[2/7] PCI: qcom: Add IPQ9574 PCIe support

Message ID	20230214164135.17039-3-quic_devipriy@quicinc.com
State	New
Headers	Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; From: Devi Priya <quic_devipriy@quicinc.com> To: <agross@kernel.org>, <andersson@kernel.org>, <konrad.dybcio@linaro.org>, <lpieralisi@kernel.org>, <kw@linux.com>, <robh@kernel.org>, <bhelgaas@google.com>, <krzysztof.kozlowski+dt@linaro.org>, <vkoul@kernel.org>, <kishon@kernel.org>, <mturquette@baylibre.com>, <sboyd@kernel.org>, <mani@kernel.org>, <p.zabel@pengutronix.de>, <svarbanov@mm-sol.com>, <linux-arm-msm@vger.kernel.org>, <linux-pci@vger.kernel.org>, <devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>, <linux-phy@lists.infradead.org>, <linux-clk@vger.kernel.org> CC: <quic_srichara@quicinc.com>, <quic_gokulsri@quicinc.com>, <quic_sjaganat@quicinc.com>, <quic_kathirav@quicinc.com>, <quic_arajkuma@quicinc.com>, <quic_anusha@quicinc.com> Subject: [PATCH 2/7] PCI: qcom: Add IPQ9574 PCIe support Date: Tue, 14 Feb 2023 22:11:30 +0530 Message-ID: <20230214164135.17039-3-quic_devipriy@quicinc.com> In-Reply-To: <20230214164135.17039-1-quic_devipriy@quicinc.com> References: <20230214164135.17039-1-quic_devipriy@quicinc.com> MIME-Version: 1.0 Content-Type: text/plain Precedence: bulk
Series	Add PCIe support for IPQ9574 \| [0/7] Add PCIe support for IPQ9574 [1/7] dt-bindings: PCI: qcom: Add IPQ9574 specific compatible [2/7] PCI: qcom: Add IPQ9574 PCIe support [3/7] dt-bindings: phy: qcom,qmp-pcie: Add ipq9574 compatible [4/7] phy: qcom-qmp-pcie: Add support for IPQ9574 platform [5/7] dt-bindings: clock: Add PCIe pipe clock definitions [6/7] clk: qcom: gcc-ipq9574: Add PCIe related clocks [7/7] arm64: dts: qcom: ipq9574: Add PCIe PHYs and controller nodes

Commit Message

Devi Priya Feb. 14, 2023, 4:41 p.m. UTC

  Adding PCIe support for IPQ9574 SoC

Co-developed-by: Anusha Rao <quic_anusha@quicinc.com>
Signed-off-by: Anusha Rao <quic_anusha@quicinc.com>
Signed-off-by: Devi Priya <quic_devipriy@quicinc.com>
---
 drivers/pci/controller/dwc/pcie-qcom.c | 119 +++++++++++++++++++++++++
 1 file changed, 119 insertions(+)

Comments

Sricharan Ramabadhran Feb. 16, 2023, 11:38 a.m. UTC | #1

Hi Devi,

On 2/14/2023 10:11 PM, Devi Priya wrote:
> Adding PCIe support for IPQ9574 SoC
> 
> Co-developed-by: Anusha Rao <quic_anusha@quicinc.com>
> Signed-off-by: Anusha Rao <quic_anusha@quicinc.com>
> Signed-off-by: Devi Priya <quic_devipriy@quicinc.com>
> ---
>   drivers/pci/controller/dwc/pcie-qcom.c | 119 +++++++++++++++++++++++++
>   1 file changed, 119 insertions(+)
> 
> diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
> index a232b04af048..57606c113d45 100644
> --- a/drivers/pci/controller/dwc/pcie-qcom.c
> +++ b/drivers/pci/controller/dwc/pcie-qcom.c
> @@ -193,6 +193,12 @@ struct qcom_pcie_resources_2_9_0 {
>   	struct reset_control *rst;
>   };
>   
> +struct qcom_pcie_resources_1_27_0 {
> +	struct clk_bulk_data *clks;
> +	struct reset_control *rst;
> +	int num_clks;
> +};
> +
>   union qcom_pcie_resources {
>   	struct qcom_pcie_resources_1_0_0 v1_0_0;
>   	struct qcom_pcie_resources_2_1_0 v2_1_0;
> @@ -201,6 +207,7 @@ union qcom_pcie_resources {
>   	struct qcom_pcie_resources_2_4_0 v2_4_0;
>   	struct qcom_pcie_resources_2_7_0 v2_7_0;
>   	struct qcom_pcie_resources_2_9_0 v2_9_0;
> +	struct qcom_pcie_resources_1_27_0 v1_27_0;
>   };
>   
>   struct qcom_pcie;
> @@ -1409,6 +1416,104 @@ static int qcom_pcie_post_init_2_9_0(struct qcom_pcie *pcie)
>   	return 0;
>   }
>   
> +static int qcom_pcie_get_resources_1_27_0(struct qcom_pcie *pcie)
> +{
> +	struct qcom_pcie_resources_1_27_0 *res = &pcie->res.v1_27_0;
> +	struct dw_pcie *pci = pcie->pci;
> +	struct device *dev = pci->dev;
> +
> +	res->num_clks = devm_clk_bulk_get_all(dev, &res->clks);
> +	if (res->clks < 0)
> +		return res->num_clks;
> +
> +	res->rst = devm_reset_control_array_get_exclusive(dev);
> +	if (IS_ERR(res->rst))
> +		return PTR_ERR(res->rst);
> +
> +	return 0;
> +}
> +
> +static void qcom_pcie_deinit_1_27_0(struct qcom_pcie *pcie)
> +{
> +	struct qcom_pcie_resources_1_27_0 *res = &pcie->res.v1_27_0;
> +
> +	clk_bulk_disable_unprepare(res->num_clks, res->clks);
> +}
> +
> +static int qcom_pcie_init_1_27_0(struct qcom_pcie *pcie)
> +{
> +	struct qcom_pcie_resources_1_27_0 *res = &pcie->res.v1_27_0;
> +	struct device *dev = pcie->pci->dev;
> +	int ret;
> +
> +	ret = reset_control_assert(res->rst);
> +	if (ret) {
> +		dev_err(dev, "reset assert failed (%d)\n", ret);
> +		return ret;
> +	}
> +
> +	/*
> +	 * Delay periods before and after reset deassert are working values
> +	 * from downstream Codeaurora kernel
> +	 */
> +	usleep_range(2000, 2500);
> +
> +	ret = reset_control_deassert(res->rst);
> +	if (ret) {
> +		dev_err(dev, "reset deassert failed (%d)\n", ret);
> +		return ret;
> +	}
> +
> +	usleep_range(2000, 2500);
> +
> +	return clk_bulk_prepare_enable(res->num_clks, res->clks);
> +}
> +
> +static int qcom_pcie_post_init_1_27_0(struct qcom_pcie *pcie)
> +{
> +	struct dw_pcie *pci = pcie->pci;
> +	u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
> +	u32 val;
> +	int i;
> +
> +	writel(0x8000000, pcie->parf + PCIE20_v3_PARF_SLV_ADDR_SPACE_SIZE);
> +
> +	val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL);
> +	val &= ~BIT(0);
> +	writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL);
> +
> +	writel(0, pcie->parf + PCIE20_PARF_DBI_BASE_ADDR);
> +
> +	writel(DEVICE_TYPE_RC, pcie->parf + PCIE20_PARF_DEVICE_TYPE);
> +	writel(BYPASS | MSTR_AXI_CLK_EN | AHB_CLK_EN,
> +	       pcie->parf + PCIE20_PARF_MHI_CLOCK_RESET_CTRL);
> +	writel(GEN3_RELATED_OFF_RXEQ_RGRDLESS_RXTS |
> +	       GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL,
> +	       pci->dbi_base + GEN3_RELATED_OFF);
> +
> +	writel(MST_WAKEUP_EN | SLV_WAKEUP_EN | MSTR_ACLK_CGC_DIS |
> +	       SLV_ACLK_CGC_DIS | CORE_CLK_CGC_DIS |
> +	       AUX_PWR_DET | L23_CLK_RMV_DIS | L1_CLK_RMV_DIS,
> +	       pcie->parf + PCIE20_PARF_SYS_CTRL);
> +
> +	writel(0, pcie->parf + PCIE20_PARF_Q2A_FLUSH);
> +
> +	dw_pcie_dbi_ro_wr_en(pci);
> +	writel(PCIE_CAP_SLOT_VAL, pci->dbi_base + offset + PCI_EXP_SLTCAP);
> +
> +	val = readl(pci->dbi_base + offset + PCI_EXP_LNKCAP);
> +	val &= ~PCI_EXP_LNKCAP_ASPMS;
> +	writel(val, pci->dbi_base + offset + PCI_EXP_LNKCAP);
> +
> +	writel(PCI_EXP_DEVCTL2_COMP_TMOUT_DIS, pci->dbi_base + offset +
> +	       PCI_EXP_DEVCTL2);
> +
> +	for (i = 0; i < 256; i++)
> +		writel(0, pcie->parf + PCIE20_PARF_BDF_TO_SID_TABLE_N + (4 * i));
> +
> +	return 0;
> +}
> +
>   static int qcom_pcie_link_up(struct dw_pcie *pci)
>   {
>   	u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
> @@ -1620,6 +1725,15 @@ static const struct qcom_pcie_ops ops_2_9_0 = {
>   	.ltssm_enable = qcom_pcie_2_3_2_ltssm_enable,
>   };
>   
> +/* Qcom IP rev.: 1.27.0 Synopsys IP rev.: 5.80a */
> +static const struct qcom_pcie_ops ops_1_27_0 = {
> +	.get_resources = qcom_pcie_get_resources_1_27_0,
> +	.init = qcom_pcie_init_1_27_0,
> +	.post_init = qcom_pcie_post_init_1_27_0,
> +	.deinit = qcom_pcie_deinit_1_27_0,
> +	.ltssm_enable = qcom_pcie_2_3_2_ltssm_enable,
> +};
> +
>   static const struct qcom_pcie_cfg cfg_1_0_0 = {
>   	.ops = &ops_1_0_0,
>   };
> @@ -1652,6 +1766,10 @@ static const struct qcom_pcie_cfg cfg_2_9_0 = {
>   	.ops = &ops_2_9_0,
>   };
>   
> +static const struct qcom_pcie_cfg cfg_1_27_0 = {
> +	.ops = &ops_1_27_0,
> +};
> +
>   static const struct dw_pcie_ops dw_pcie_ops = {
>   	.link_up = qcom_pcie_link_up,
>   	.start_link = qcom_pcie_start_link,
> @@ -1829,6 +1947,7 @@ static const struct of_device_id qcom_pcie_match[] = {
>   	{ .compatible = "qcom,pcie-ipq8064-v2", .data = &cfg_2_1_0 },
>   	{ .compatible = "qcom,pcie-ipq8074", .data = &cfg_2_3_3 },
>   	{ .compatible = "qcom,pcie-ipq8074-gen3", .data = &cfg_2_9_0 },
> +	{ .compatible = "qcom,pcie-ipq9574", .data = &cfg_1_27_0 },

   I do not see much difference between 2_9_0 and 1_27_0. Is this patch
   really required. Can you check if it works with 2_9_0 itself ?

Regards,
  Sricharan

Devi Priya Feb. 20, 2023, 1:41 p.m. UTC | #2

Hi Sri,
Thanks for taking time to review the patch!

On 2/16/2023 5:08 PM, Sricharan Ramabadhran wrote:
> Hi Devi,
> 
> On 2/14/2023 10:11 PM, Devi Priya wrote:
>> Adding PCIe support for IPQ9574 SoC
>>
>> Co-developed-by: Anusha Rao <quic_anusha@quicinc.com>
>> Signed-off-by: Anusha Rao <quic_anusha@quicinc.com>
>> Signed-off-by: Devi Priya <quic_devipriy@quicinc.com>
>> ---
>>   drivers/pci/controller/dwc/pcie-qcom.c | 119 +++++++++++++++++++++++++
>>   1 file changed, 119 insertions(+)
>>
>> diff --git a/drivers/pci/controller/dwc/pcie-qcom.c 
>> b/drivers/pci/controller/dwc/pcie-qcom.c
>> index a232b04af048..57606c113d45 100644
>> --- a/drivers/pci/controller/dwc/pcie-qcom.c
>> +++ b/drivers/pci/controller/dwc/pcie-qcom.c
>> @@ -193,6 +193,12 @@ struct qcom_pcie_resources_2_9_0 {
>>       struct reset_control *rst;
>>   };
>> +struct qcom_pcie_resources_1_27_0 {
>> +    struct clk_bulk_data *clks;
>> +    struct reset_control *rst;
>> +    int num_clks;
>> +};
>> +
>>   union qcom_pcie_resources {
>>       struct qcom_pcie_resources_1_0_0 v1_0_0;
>>       struct qcom_pcie_resources_2_1_0 v2_1_0;
>> @@ -201,6 +207,7 @@ union qcom_pcie_resources {
>>       struct qcom_pcie_resources_2_4_0 v2_4_0;
>>       struct qcom_pcie_resources_2_7_0 v2_7_0;
>>       struct qcom_pcie_resources_2_9_0 v2_9_0;
>> +    struct qcom_pcie_resources_1_27_0 v1_27_0;
>>   };
>>   struct qcom_pcie;
>> @@ -1409,6 +1416,104 @@ static int qcom_pcie_post_init_2_9_0(struct 
>> qcom_pcie *pcie)
>>       return 0;
>>   }
>> +static int qcom_pcie_get_resources_1_27_0(struct qcom_pcie *pcie)
>> +{
>> +    struct qcom_pcie_resources_1_27_0 *res = &pcie->res.v1_27_0;
>> +    struct dw_pcie *pci = pcie->pci;
>> +    struct device *dev = pci->dev;
>> +
>> +    res->num_clks = devm_clk_bulk_get_all(dev, &res->clks);
>> +    if (res->clks < 0)
>> +        return res->num_clks;
>> +
>> +    res->rst = devm_reset_control_array_get_exclusive(dev);
>> +    if (IS_ERR(res->rst))
>> +        return PTR_ERR(res->rst);
>> +
>> +    return 0;
>> +}
>> +
>> +static void qcom_pcie_deinit_1_27_0(struct qcom_pcie *pcie)
>> +{
>> +    struct qcom_pcie_resources_1_27_0 *res = &pcie->res.v1_27_0;
>> +
>> +    clk_bulk_disable_unprepare(res->num_clks, res->clks);
>> +}
>> +
>> +static int qcom_pcie_init_1_27_0(struct qcom_pcie *pcie)
>> +{
>> +    struct qcom_pcie_resources_1_27_0 *res = &pcie->res.v1_27_0;
>> +    struct device *dev = pcie->pci->dev;
>> +    int ret;
>> +
>> +    ret = reset_control_assert(res->rst);
>> +    if (ret) {
>> +        dev_err(dev, "reset assert failed (%d)\n", ret);
>> +        return ret;
>> +    }
>> +
>> +    /*
>> +     * Delay periods before and after reset deassert are working values
>> +     * from downstream Codeaurora kernel
>> +     */
>> +    usleep_range(2000, 2500);
>> +
>> +    ret = reset_control_deassert(res->rst);
>> +    if (ret) {
>> +        dev_err(dev, "reset deassert failed (%d)\n", ret);
>> +        return ret;
>> +    }
>> +
>> +    usleep_range(2000, 2500);
>> +
>> +    return clk_bulk_prepare_enable(res->num_clks, res->clks);
>> +}
>> +
>> +static int qcom_pcie_post_init_1_27_0(struct qcom_pcie *pcie)
>> +{
>> +    struct dw_pcie *pci = pcie->pci;
>> +    u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
>> +    u32 val;
>> +    int i;
>> +
>> +    writel(0x8000000, pcie->parf + PCIE20_v3_PARF_SLV_ADDR_SPACE_SIZE);
>> +
>> +    val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL);
>> +    val &= ~BIT(0);
>> +    writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL);
>> +
>> +    writel(0, pcie->parf + PCIE20_PARF_DBI_BASE_ADDR);
>> +
>> +    writel(DEVICE_TYPE_RC, pcie->parf + PCIE20_PARF_DEVICE_TYPE);
>> +    writel(BYPASS | MSTR_AXI_CLK_EN | AHB_CLK_EN,
>> +           pcie->parf + PCIE20_PARF_MHI_CLOCK_RESET_CTRL);
>> +    writel(GEN3_RELATED_OFF_RXEQ_RGRDLESS_RXTS |
>> +           GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL,
>> +           pci->dbi_base + GEN3_RELATED_OFF);
>> +
>> +    writel(MST_WAKEUP_EN | SLV_WAKEUP_EN | MSTR_ACLK_CGC_DIS |
>> +           SLV_ACLK_CGC_DIS | CORE_CLK_CGC_DIS |
>> +           AUX_PWR_DET | L23_CLK_RMV_DIS | L1_CLK_RMV_DIS,
>> +           pcie->parf + PCIE20_PARF_SYS_CTRL);
>> +
>> +    writel(0, pcie->parf + PCIE20_PARF_Q2A_FLUSH);
>> +
>> +    dw_pcie_dbi_ro_wr_en(pci);
>> +    writel(PCIE_CAP_SLOT_VAL, pci->dbi_base + offset + PCI_EXP_SLTCAP);
>> +
>> +    val = readl(pci->dbi_base + offset + PCI_EXP_LNKCAP);
>> +    val &= ~PCI_EXP_LNKCAP_ASPMS;
>> +    writel(val, pci->dbi_base + offset + PCI_EXP_LNKCAP);
>> +
>> +    writel(PCI_EXP_DEVCTL2_COMP_TMOUT_DIS, pci->dbi_base + offset +
>> +           PCI_EXP_DEVCTL2);
>> +
>> +    for (i = 0; i < 256; i++)
>> +        writel(0, pcie->parf + PCIE20_PARF_BDF_TO_SID_TABLE_N + (4 * 
>> i));
>> +
>> +    return 0;
>> +}
>> +
>>   static int qcom_pcie_link_up(struct dw_pcie *pci)
>>   {
>>       u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
>> @@ -1620,6 +1725,15 @@ static const struct qcom_pcie_ops ops_2_9_0 = {
>>       .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable,
>>   };
>> +/* Qcom IP rev.: 1.27.0 Synopsys IP rev.: 5.80a */
>> +static const struct qcom_pcie_ops ops_1_27_0 = {
>> +    .get_resources = qcom_pcie_get_resources_1_27_0,
>> +    .init = qcom_pcie_init_1_27_0,
>> +    .post_init = qcom_pcie_post_init_1_27_0,
>> +    .deinit = qcom_pcie_deinit_1_27_0,
>> +    .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable,
>> +};
>> +
>>   static const struct qcom_pcie_cfg cfg_1_0_0 = {
>>       .ops = &ops_1_0_0,
>>   };
>> @@ -1652,6 +1766,10 @@ static const struct qcom_pcie_cfg cfg_2_9_0 = {
>>       .ops = &ops_2_9_0,
>>   };
>> +static const struct qcom_pcie_cfg cfg_1_27_0 = {
>> +    .ops = &ops_1_27_0,
>> +};
>> +
>>   static const struct dw_pcie_ops dw_pcie_ops = {
>>       .link_up = qcom_pcie_link_up,
>>       .start_link = qcom_pcie_start_link,
>> @@ -1829,6 +1947,7 @@ static const struct of_device_id 
>> qcom_pcie_match[] = {
>>       { .compatible = "qcom,pcie-ipq8064-v2", .data = &cfg_2_1_0 },
>>       { .compatible = "qcom,pcie-ipq8074", .data = &cfg_2_3_3 },
>>       { .compatible = "qcom,pcie-ipq8074-gen3", .data = &cfg_2_9_0 },
>> +    { .compatible = "qcom,pcie-ipq9574", .data = &cfg_1_27_0 },
> 
>    I do not see much difference between 2_9_0 and 1_27_0. Is this patch
>    really required. Can you check if it works with 2_9_0 itself ?
Yes right Sri, Only the clocks seem to differ between 2_9_0 and 1_27_0.
Will update 2_9_0 ops to get the clocks from the DT and use the same for 
ipq9574 in the next spin.

Best Regards,
Devi Priya
> 
> Regards,
>   Sricharan

Kathiravan Thirumoorthy Feb. 20, 2023, 2:51 p.m. UTC | #3

On 2/20/2023 7:11 PM, Devi Priya wrote:
> Hi Sri,
> Thanks for taking time to review the patch!
>
> On 2/16/2023 5:08 PM, Sricharan Ramabadhran wrote:
>> Hi Devi,
>>
>> On 2/14/2023 10:11 PM, Devi Priya wrote:
>>> Adding PCIe support for IPQ9574 SoC
>>>
>>> Co-developed-by: Anusha Rao <quic_anusha@quicinc.com>
>>> Signed-off-by: Anusha Rao <quic_anusha@quicinc.com>
>>> Signed-off-by: Devi Priya <quic_devipriy@quicinc.com>
>>> ---
>>>   drivers/pci/controller/dwc/pcie-qcom.c | 119 
>>> +++++++++++++++++++++++++
>>>   1 file changed, 119 insertions(+)
>>>
>>> diff --git a/drivers/pci/controller/dwc/pcie-qcom.c 
>>> b/drivers/pci/controller/dwc/pcie-qcom.c
>>> index a232b04af048..57606c113d45 100644
>>> --- a/drivers/pci/controller/dwc/pcie-qcom.c
>>> +++ b/drivers/pci/controller/dwc/pcie-qcom.c
>>> @@ -193,6 +193,12 @@ struct qcom_pcie_resources_2_9_0 {
>>>       struct reset_control *rst;
>>>   };
>>> +struct qcom_pcie_resources_1_27_0 {
>>> +    struct clk_bulk_data *clks;
>>> +    struct reset_control *rst;
>>> +    int num_clks;
>>> +};
>>> +
>>>   union qcom_pcie_resources {
>>>       struct qcom_pcie_resources_1_0_0 v1_0_0;
>>>       struct qcom_pcie_resources_2_1_0 v2_1_0;
>>> @@ -201,6 +207,7 @@ union qcom_pcie_resources {
>>>       struct qcom_pcie_resources_2_4_0 v2_4_0;
>>>       struct qcom_pcie_resources_2_7_0 v2_7_0;
>>>       struct qcom_pcie_resources_2_9_0 v2_9_0;
>>> +    struct qcom_pcie_resources_1_27_0 v1_27_0;
>>>   };
>>>   struct qcom_pcie;
>>> @@ -1409,6 +1416,104 @@ static int qcom_pcie_post_init_2_9_0(struct 
>>> qcom_pcie *pcie)
>>>       return 0;
>>>   }
>>> +static int qcom_pcie_get_resources_1_27_0(struct qcom_pcie *pcie)
>>> +{
>>> +    struct qcom_pcie_resources_1_27_0 *res = &pcie->res.v1_27_0;
>>> +    struct dw_pcie *pci = pcie->pci;
>>> +    struct device *dev = pci->dev;
>>> +
>>> +    res->num_clks = devm_clk_bulk_get_all(dev, &res->clks);
>>> +    if (res->clks < 0)
>>> +        return res->num_clks;
>>> +
>>> +    res->rst = devm_reset_control_array_get_exclusive(dev);
>>> +    if (IS_ERR(res->rst))
>>> +        return PTR_ERR(res->rst);
>>> +
>>> +    return 0;
>>> +}
>>> +
>>> +static void qcom_pcie_deinit_1_27_0(struct qcom_pcie *pcie)
>>> +{
>>> +    struct qcom_pcie_resources_1_27_0 *res = &pcie->res.v1_27_0;
>>> +
>>> +    clk_bulk_disable_unprepare(res->num_clks, res->clks);
>>> +}
>>> +
>>> +static int qcom_pcie_init_1_27_0(struct qcom_pcie *pcie)
>>> +{
>>> +    struct qcom_pcie_resources_1_27_0 *res = &pcie->res.v1_27_0;
>>> +    struct device *dev = pcie->pci->dev;
>>> +    int ret;
>>> +
>>> +    ret = reset_control_assert(res->rst);
>>> +    if (ret) {
>>> +        dev_err(dev, "reset assert failed (%d)\n", ret);
>>> +        return ret;
>>> +    }
>>> +
>>> +    /*
>>> +     * Delay periods before and after reset deassert are working 
>>> values
>>> +     * from downstream Codeaurora kernel
>>> +     */
>>> +    usleep_range(2000, 2500);
>>> +
>>> +    ret = reset_control_deassert(res->rst);
>>> +    if (ret) {
>>> +        dev_err(dev, "reset deassert failed (%d)\n", ret);
>>> +        return ret;
>>> +    }
>>> +
>>> +    usleep_range(2000, 2500);
>>> +
>>> +    return clk_bulk_prepare_enable(res->num_clks, res->clks);
>>> +}
>>> +
>>> +static int qcom_pcie_post_init_1_27_0(struct qcom_pcie *pcie)
>>> +{
>>> +    struct dw_pcie *pci = pcie->pci;
>>> +    u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
>>> +    u32 val;
>>> +    int i;
>>> +
>>> +    writel(0x8000000, pcie->parf + 
>>> PCIE20_v3_PARF_SLV_ADDR_SPACE_SIZE);


Devi,


Above statement also differs. You need to consider this also when you 
use the 2_9_0 ops.


Thanks,


>>> +
>>> +    val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL);
>>> +    val &= ~BIT(0);
>>> +    writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL);
>>> +
>>> +    writel(0, pcie->parf + PCIE20_PARF_DBI_BASE_ADDR);
>>> +
>>> +    writel(DEVICE_TYPE_RC, pcie->parf + PCIE20_PARF_DEVICE_TYPE);
>>> +    writel(BYPASS | MSTR_AXI_CLK_EN | AHB_CLK_EN,
>>> +           pcie->parf + PCIE20_PARF_MHI_CLOCK_RESET_CTRL);
>>> +    writel(GEN3_RELATED_OFF_RXEQ_RGRDLESS_RXTS |
>>> +           GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL,
>>> +           pci->dbi_base + GEN3_RELATED_OFF);
>>> +
>>> +    writel(MST_WAKEUP_EN | SLV_WAKEUP_EN | MSTR_ACLK_CGC_DIS |
>>> +           SLV_ACLK_CGC_DIS | CORE_CLK_CGC_DIS |
>>> +           AUX_PWR_DET | L23_CLK_RMV_DIS | L1_CLK_RMV_DIS,
>>> +           pcie->parf + PCIE20_PARF_SYS_CTRL);
>>> +
>>> +    writel(0, pcie->parf + PCIE20_PARF_Q2A_FLUSH);
>>> +
>>> +    dw_pcie_dbi_ro_wr_en(pci);
>>> +    writel(PCIE_CAP_SLOT_VAL, pci->dbi_base + offset + 
>>> PCI_EXP_SLTCAP);
>>> +
>>> +    val = readl(pci->dbi_base + offset + PCI_EXP_LNKCAP);
>>> +    val &= ~PCI_EXP_LNKCAP_ASPMS;
>>> +    writel(val, pci->dbi_base + offset + PCI_EXP_LNKCAP);
>>> +
>>> +    writel(PCI_EXP_DEVCTL2_COMP_TMOUT_DIS, pci->dbi_base + offset +
>>> +           PCI_EXP_DEVCTL2);
>>> +
>>> +    for (i = 0; i < 256; i++)
>>> +        writel(0, pcie->parf + PCIE20_PARF_BDF_TO_SID_TABLE_N + (4 
>>> * i));
>>> +
>>> +    return 0;
>>> +}
>>> +
>>>   static int qcom_pcie_link_up(struct dw_pcie *pci)
>>>   {
>>>       u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
>>> @@ -1620,6 +1725,15 @@ static const struct qcom_pcie_ops ops_2_9_0 = {
>>>       .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable,
>>>   };
>>> +/* Qcom IP rev.: 1.27.0 Synopsys IP rev.: 5.80a */
>>> +static const struct qcom_pcie_ops ops_1_27_0 = {
>>> +    .get_resources = qcom_pcie_get_resources_1_27_0,
>>> +    .init = qcom_pcie_init_1_27_0,
>>> +    .post_init = qcom_pcie_post_init_1_27_0,
>>> +    .deinit = qcom_pcie_deinit_1_27_0,
>>> +    .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable,
>>> +};
>>> +
>>>   static const struct qcom_pcie_cfg cfg_1_0_0 = {
>>>       .ops = &ops_1_0_0,
>>>   };
>>> @@ -1652,6 +1766,10 @@ static const struct qcom_pcie_cfg cfg_2_9_0 = {
>>>       .ops = &ops_2_9_0,
>>>   };
>>> +static const struct qcom_pcie_cfg cfg_1_27_0 = {
>>> +    .ops = &ops_1_27_0,
>>> +};
>>> +
>>>   static const struct dw_pcie_ops dw_pcie_ops = {
>>>       .link_up = qcom_pcie_link_up,
>>>       .start_link = qcom_pcie_start_link,
>>> @@ -1829,6 +1947,7 @@ static const struct of_device_id 
>>> qcom_pcie_match[] = {
>>>       { .compatible = "qcom,pcie-ipq8064-v2", .data = &cfg_2_1_0 },
>>>       { .compatible = "qcom,pcie-ipq8074", .data = &cfg_2_3_3 },
>>>       { .compatible = "qcom,pcie-ipq8074-gen3", .data = &cfg_2_9_0 },
>>> +    { .compatible = "qcom,pcie-ipq9574", .data = &cfg_1_27_0 },
>>
>>    I do not see much difference between 2_9_0 and 1_27_0. Is this patch
>>    really required. Can you check if it works with 2_9_0 itself ?
> Yes right Sri, Only the clocks seem to differ between 2_9_0 and 1_27_0.
> Will update 2_9_0 ops to get the clocks from the DT and use the same 
> for ipq9574 in the next spin.
>
> Best Regards,
> Devi Priya
>>
>> Regards,
>>   Sricharan

Devi Priya Feb. 20, 2023, 3:25 p.m. UTC | #4

On 2/20/2023 8:21 PM, Kathiravan T wrote:
> 
> On 2/20/2023 7:11 PM, Devi Priya wrote:
>> Hi Sri,
>> Thanks for taking time to review the patch!
>>
>> On 2/16/2023 5:08 PM, Sricharan Ramabadhran wrote:
>>> Hi Devi,
>>>
>>> On 2/14/2023 10:11 PM, Devi Priya wrote:
>>>> Adding PCIe support for IPQ9574 SoC
>>>>
>>>> Co-developed-by: Anusha Rao <quic_anusha@quicinc.com>
>>>> Signed-off-by: Anusha Rao <quic_anusha@quicinc.com>
>>>> Signed-off-by: Devi Priya <quic_devipriy@quicinc.com>
>>>> ---
>>>>   drivers/pci/controller/dwc/pcie-qcom.c | 119 
>>>> +++++++++++++++++++++++++
>>>>   1 file changed, 119 insertions(+)
>>>>
>>>> diff --git a/drivers/pci/controller/dwc/pcie-qcom.c 
>>>> b/drivers/pci/controller/dwc/pcie-qcom.c
>>>> index a232b04af048..57606c113d45 100644
>>>> --- a/drivers/pci/controller/dwc/pcie-qcom.c
>>>> +++ b/drivers/pci/controller/dwc/pcie-qcom.c
>>>> @@ -193,6 +193,12 @@ struct qcom_pcie_resources_2_9_0 {
>>>>       struct reset_control *rst;
>>>>   };
>>>> +struct qcom_pcie_resources_1_27_0 {
>>>> +    struct clk_bulk_data *clks;
>>>> +    struct reset_control *rst;
>>>> +    int num_clks;
>>>> +};
>>>> +
>>>>   union qcom_pcie_resources {
>>>>       struct qcom_pcie_resources_1_0_0 v1_0_0;
>>>>       struct qcom_pcie_resources_2_1_0 v2_1_0;
>>>> @@ -201,6 +207,7 @@ union qcom_pcie_resources {
>>>>       struct qcom_pcie_resources_2_4_0 v2_4_0;
>>>>       struct qcom_pcie_resources_2_7_0 v2_7_0;
>>>>       struct qcom_pcie_resources_2_9_0 v2_9_0;
>>>> +    struct qcom_pcie_resources_1_27_0 v1_27_0;
>>>>   };
>>>>   struct qcom_pcie;
>>>> @@ -1409,6 +1416,104 @@ static int qcom_pcie_post_init_2_9_0(struct 
>>>> qcom_pcie *pcie)
>>>>       return 0;
>>>>   }
>>>> +static int qcom_pcie_get_resources_1_27_0(struct qcom_pcie *pcie)
>>>> +{
>>>> +    struct qcom_pcie_resources_1_27_0 *res = &pcie->res.v1_27_0;
>>>> +    struct dw_pcie *pci = pcie->pci;
>>>> +    struct device *dev = pci->dev;
>>>> +
>>>> +    res->num_clks = devm_clk_bulk_get_all(dev, &res->clks);
>>>> +    if (res->clks < 0)
>>>> +        return res->num_clks;
>>>> +
>>>> +    res->rst = devm_reset_control_array_get_exclusive(dev);
>>>> +    if (IS_ERR(res->rst))
>>>> +        return PTR_ERR(res->rst);
>>>> +
>>>> +    return 0;
>>>> +}
>>>> +
>>>> +static void qcom_pcie_deinit_1_27_0(struct qcom_pcie *pcie)
>>>> +{
>>>> +    struct qcom_pcie_resources_1_27_0 *res = &pcie->res.v1_27_0;
>>>> +
>>>> +    clk_bulk_disable_unprepare(res->num_clks, res->clks);
>>>> +}
>>>> +
>>>> +static int qcom_pcie_init_1_27_0(struct qcom_pcie *pcie)
>>>> +{
>>>> +    struct qcom_pcie_resources_1_27_0 *res = &pcie->res.v1_27_0;
>>>> +    struct device *dev = pcie->pci->dev;
>>>> +    int ret;
>>>> +
>>>> +    ret = reset_control_assert(res->rst);
>>>> +    if (ret) {
>>>> +        dev_err(dev, "reset assert failed (%d)\n", ret);
>>>> +        return ret;
>>>> +    }
>>>> +
>>>> +    /*
>>>> +     * Delay periods before and after reset deassert are working 
>>>> values
>>>> +     * from downstream Codeaurora kernel
>>>> +     */
>>>> +    usleep_range(2000, 2500);
>>>> +
>>>> +    ret = reset_control_deassert(res->rst);
>>>> +    if (ret) {
>>>> +        dev_err(dev, "reset deassert failed (%d)\n", ret);
>>>> +        return ret;
>>>> +    }
>>>> +
>>>> +    usleep_range(2000, 2500);
>>>> +
>>>> +    return clk_bulk_prepare_enable(res->num_clks, res->clks);
>>>> +}
>>>> +
>>>> +static int qcom_pcie_post_init_1_27_0(struct qcom_pcie *pcie)
>>>> +{
>>>> +    struct dw_pcie *pci = pcie->pci;
>>>> +    u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
>>>> +    u32 val;
>>>> +    int i;
>>>> +
>>>> +    writel(0x8000000, pcie->parf + 
>>>> PCIE20_v3_PARF_SLV_ADDR_SPACE_SIZE);
> 
> 
> Devi,
> 
> 
> Above statement also differs. You need to consider this also when you 
> use the 2_9_0 ops.
> 
Sure, thanks kathir. Will take care of this as well
> 
Best Regards,
Devi Priya

> Thanks,
> 
> 
>>>> +
>>>> +    val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL);
>>>> +    val &= ~BIT(0);
>>>> +    writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL);
>>>> +
>>>> +    writel(0, pcie->parf + PCIE20_PARF_DBI_BASE_ADDR);
>>>> +
>>>> +    writel(DEVICE_TYPE_RC, pcie->parf + PCIE20_PARF_DEVICE_TYPE);
>>>> +    writel(BYPASS | MSTR_AXI_CLK_EN | AHB_CLK_EN,
>>>> +           pcie->parf + PCIE20_PARF_MHI_CLOCK_RESET_CTRL);
>>>> +    writel(GEN3_RELATED_OFF_RXEQ_RGRDLESS_RXTS |
>>>> +           GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL,
>>>> +           pci->dbi_base + GEN3_RELATED_OFF);
>>>> +
>>>> +    writel(MST_WAKEUP_EN | SLV_WAKEUP_EN | MSTR_ACLK_CGC_DIS |
>>>> +           SLV_ACLK_CGC_DIS | CORE_CLK_CGC_DIS |
>>>> +           AUX_PWR_DET | L23_CLK_RMV_DIS | L1_CLK_RMV_DIS,
>>>> +           pcie->parf + PCIE20_PARF_SYS_CTRL);
>>>> +
>>>> +    writel(0, pcie->parf + PCIE20_PARF_Q2A_FLUSH);
>>>> +
>>>> +    dw_pcie_dbi_ro_wr_en(pci);
>>>> +    writel(PCIE_CAP_SLOT_VAL, pci->dbi_base + offset + 
>>>> PCI_EXP_SLTCAP);
>>>> +
>>>> +    val = readl(pci->dbi_base + offset + PCI_EXP_LNKCAP);
>>>> +    val &= ~PCI_EXP_LNKCAP_ASPMS;
>>>> +    writel(val, pci->dbi_base + offset + PCI_EXP_LNKCAP);
>>>> +
>>>> +    writel(PCI_EXP_DEVCTL2_COMP_TMOUT_DIS, pci->dbi_base + offset +
>>>> +           PCI_EXP_DEVCTL2);
>>>> +
>>>> +    for (i = 0; i < 256; i++)
>>>> +        writel(0, pcie->parf + PCIE20_PARF_BDF_TO_SID_TABLE_N + (4 
>>>> * i));
>>>> +
>>>> +    return 0;
>>>> +}
>>>> +
>>>>   static int qcom_pcie_link_up(struct dw_pcie *pci)
>>>>   {
>>>>       u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
>>>> @@ -1620,6 +1725,15 @@ static const struct qcom_pcie_ops ops_2_9_0 = {
>>>>       .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable,
>>>>   };
>>>> +/* Qcom IP rev.: 1.27.0 Synopsys IP rev.: 5.80a */
>>>> +static const struct qcom_pcie_ops ops_1_27_0 = {
>>>> +    .get_resources = qcom_pcie_get_resources_1_27_0,
>>>> +    .init = qcom_pcie_init_1_27_0,
>>>> +    .post_init = qcom_pcie_post_init_1_27_0,
>>>> +    .deinit = qcom_pcie_deinit_1_27_0,
>>>> +    .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable,
>>>> +};
>>>> +
>>>>   static const struct qcom_pcie_cfg cfg_1_0_0 = {
>>>>       .ops = &ops_1_0_0,
>>>>   };
>>>> @@ -1652,6 +1766,10 @@ static const struct qcom_pcie_cfg cfg_2_9_0 = {
>>>>       .ops = &ops_2_9_0,
>>>>   };
>>>> +static const struct qcom_pcie_cfg cfg_1_27_0 = {
>>>> +    .ops = &ops_1_27_0,
>>>> +};
>>>> +
>>>>   static const struct dw_pcie_ops dw_pcie_ops = {
>>>>       .link_up = qcom_pcie_link_up,
>>>>       .start_link = qcom_pcie_start_link,
>>>> @@ -1829,6 +1947,7 @@ static const struct of_device_id 
>>>> qcom_pcie_match[] = {
>>>>       { .compatible = "qcom,pcie-ipq8064-v2", .data = &cfg_2_1_0 },
>>>>       { .compatible = "qcom,pcie-ipq8074", .data = &cfg_2_3_3 },
>>>>       { .compatible = "qcom,pcie-ipq8074-gen3", .data = &cfg_2_9_0 },
>>>> +    { .compatible = "qcom,pcie-ipq9574", .data = &cfg_1_27_0 },
>>>
>>>    I do not see much difference between 2_9_0 and 1_27_0. Is this patch
>>>    really required. Can you check if it works with 2_9_0 itself ?
>> Yes right Sri, Only the clocks seem to differ between 2_9_0 and 1_27_0.
>> Will update 2_9_0 ops to get the clocks from the DT and use the same 
>> for ipq9574 in the next spin.
>>
>> Best Regards,
>> Devi Priya
>>>
>>> Regards,
>>>   Sricharan

Manivannan Sadhasivam Feb. 24, 2023, 8:29 a.m. UTC | #5

On Tue, Feb 14, 2023 at 10:11:30PM +0530, Devi Priya wrote:
> Adding PCIe support for IPQ9574 SoC
> 

Please add some information about the PCIe IP in the commit message.
Like, the Synopsys IP version, Gen speed etc... and how the support
is added (using existing config or a new one).

As others have mentioned, you could reuse the existing config. In that
case, add the info in commit message as I suggested above.

And the PCI patch should come last in the series after bindings and dts
patches.

Thanks,
Mani

> Co-developed-by: Anusha Rao <quic_anusha@quicinc.com>
> Signed-off-by: Anusha Rao <quic_anusha@quicinc.com>
> Signed-off-by: Devi Priya <quic_devipriy@quicinc.com>
> ---
>  drivers/pci/controller/dwc/pcie-qcom.c | 119 +++++++++++++++++++++++++
>  1 file changed, 119 insertions(+)
> 
> diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
> index a232b04af048..57606c113d45 100644
> --- a/drivers/pci/controller/dwc/pcie-qcom.c
> +++ b/drivers/pci/controller/dwc/pcie-qcom.c
> @@ -193,6 +193,12 @@ struct qcom_pcie_resources_2_9_0 {
>  	struct reset_control *rst;
>  };
>  
> +struct qcom_pcie_resources_1_27_0 {
> +	struct clk_bulk_data *clks;
> +	struct reset_control *rst;
> +	int num_clks;
> +};
> +
>  union qcom_pcie_resources {
>  	struct qcom_pcie_resources_1_0_0 v1_0_0;
>  	struct qcom_pcie_resources_2_1_0 v2_1_0;
> @@ -201,6 +207,7 @@ union qcom_pcie_resources {
>  	struct qcom_pcie_resources_2_4_0 v2_4_0;
>  	struct qcom_pcie_resources_2_7_0 v2_7_0;
>  	struct qcom_pcie_resources_2_9_0 v2_9_0;
> +	struct qcom_pcie_resources_1_27_0 v1_27_0;
>  };
>  
>  struct qcom_pcie;
> @@ -1409,6 +1416,104 @@ static int qcom_pcie_post_init_2_9_0(struct qcom_pcie *pcie)
>  	return 0;
>  }
>  
> +static int qcom_pcie_get_resources_1_27_0(struct qcom_pcie *pcie)
> +{
> +	struct qcom_pcie_resources_1_27_0 *res = &pcie->res.v1_27_0;
> +	struct dw_pcie *pci = pcie->pci;
> +	struct device *dev = pci->dev;
> +
> +	res->num_clks = devm_clk_bulk_get_all(dev, &res->clks);
> +	if (res->clks < 0)
> +		return res->num_clks;
> +
> +	res->rst = devm_reset_control_array_get_exclusive(dev);
> +	if (IS_ERR(res->rst))
> +		return PTR_ERR(res->rst);
> +
> +	return 0;
> +}
> +
> +static void qcom_pcie_deinit_1_27_0(struct qcom_pcie *pcie)
> +{
> +	struct qcom_pcie_resources_1_27_0 *res = &pcie->res.v1_27_0;
> +
> +	clk_bulk_disable_unprepare(res->num_clks, res->clks);
> +}
> +
> +static int qcom_pcie_init_1_27_0(struct qcom_pcie *pcie)
> +{
> +	struct qcom_pcie_resources_1_27_0 *res = &pcie->res.v1_27_0;
> +	struct device *dev = pcie->pci->dev;
> +	int ret;
> +
> +	ret = reset_control_assert(res->rst);
> +	if (ret) {
> +		dev_err(dev, "reset assert failed (%d)\n", ret);
> +		return ret;
> +	}
> +
> +	/*
> +	 * Delay periods before and after reset deassert are working values
> +	 * from downstream Codeaurora kernel
> +	 */
> +	usleep_range(2000, 2500);
> +
> +	ret = reset_control_deassert(res->rst);
> +	if (ret) {
> +		dev_err(dev, "reset deassert failed (%d)\n", ret);
> +		return ret;
> +	}
> +
> +	usleep_range(2000, 2500);
> +
> +	return clk_bulk_prepare_enable(res->num_clks, res->clks);
> +}
> +
> +static int qcom_pcie_post_init_1_27_0(struct qcom_pcie *pcie)
> +{
> +	struct dw_pcie *pci = pcie->pci;
> +	u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
> +	u32 val;
> +	int i;
> +
> +	writel(0x8000000, pcie->parf + PCIE20_v3_PARF_SLV_ADDR_SPACE_SIZE);
> +
> +	val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL);
> +	val &= ~BIT(0);
> +	writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL);
> +
> +	writel(0, pcie->parf + PCIE20_PARF_DBI_BASE_ADDR);
> +
> +	writel(DEVICE_TYPE_RC, pcie->parf + PCIE20_PARF_DEVICE_TYPE);
> +	writel(BYPASS | MSTR_AXI_CLK_EN | AHB_CLK_EN,
> +	       pcie->parf + PCIE20_PARF_MHI_CLOCK_RESET_CTRL);
> +	writel(GEN3_RELATED_OFF_RXEQ_RGRDLESS_RXTS |
> +	       GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL,
> +	       pci->dbi_base + GEN3_RELATED_OFF);
> +
> +	writel(MST_WAKEUP_EN | SLV_WAKEUP_EN | MSTR_ACLK_CGC_DIS |
> +	       SLV_ACLK_CGC_DIS | CORE_CLK_CGC_DIS |
> +	       AUX_PWR_DET | L23_CLK_RMV_DIS | L1_CLK_RMV_DIS,
> +	       pcie->parf + PCIE20_PARF_SYS_CTRL);
> +
> +	writel(0, pcie->parf + PCIE20_PARF_Q2A_FLUSH);
> +
> +	dw_pcie_dbi_ro_wr_en(pci);
> +	writel(PCIE_CAP_SLOT_VAL, pci->dbi_base + offset + PCI_EXP_SLTCAP);
> +
> +	val = readl(pci->dbi_base + offset + PCI_EXP_LNKCAP);
> +	val &= ~PCI_EXP_LNKCAP_ASPMS;
> +	writel(val, pci->dbi_base + offset + PCI_EXP_LNKCAP);
> +
> +	writel(PCI_EXP_DEVCTL2_COMP_TMOUT_DIS, pci->dbi_base + offset +
> +	       PCI_EXP_DEVCTL2);
> +
> +	for (i = 0; i < 256; i++)
> +		writel(0, pcie->parf + PCIE20_PARF_BDF_TO_SID_TABLE_N + (4 * i));
> +
> +	return 0;
> +}
> +
>  static int qcom_pcie_link_up(struct dw_pcie *pci)
>  {
>  	u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
> @@ -1620,6 +1725,15 @@ static const struct qcom_pcie_ops ops_2_9_0 = {
>  	.ltssm_enable = qcom_pcie_2_3_2_ltssm_enable,
>  };
>  
> +/* Qcom IP rev.: 1.27.0 Synopsys IP rev.: 5.80a */
> +static const struct qcom_pcie_ops ops_1_27_0 = {
> +	.get_resources = qcom_pcie_get_resources_1_27_0,
> +	.init = qcom_pcie_init_1_27_0,
> +	.post_init = qcom_pcie_post_init_1_27_0,
> +	.deinit = qcom_pcie_deinit_1_27_0,
> +	.ltssm_enable = qcom_pcie_2_3_2_ltssm_enable,
> +};
> +
>  static const struct qcom_pcie_cfg cfg_1_0_0 = {
>  	.ops = &ops_1_0_0,
>  };
> @@ -1652,6 +1766,10 @@ static const struct qcom_pcie_cfg cfg_2_9_0 = {
>  	.ops = &ops_2_9_0,
>  };
>  
> +static const struct qcom_pcie_cfg cfg_1_27_0 = {
> +	.ops = &ops_1_27_0,
> +};
> +
>  static const struct dw_pcie_ops dw_pcie_ops = {
>  	.link_up = qcom_pcie_link_up,
>  	.start_link = qcom_pcie_start_link,
> @@ -1829,6 +1947,7 @@ static const struct of_device_id qcom_pcie_match[] = {
>  	{ .compatible = "qcom,pcie-ipq8064-v2", .data = &cfg_2_1_0 },
>  	{ .compatible = "qcom,pcie-ipq8074", .data = &cfg_2_3_3 },
>  	{ .compatible = "qcom,pcie-ipq8074-gen3", .data = &cfg_2_9_0 },
> +	{ .compatible = "qcom,pcie-ipq9574", .data = &cfg_1_27_0 },
>  	{ .compatible = "qcom,pcie-msm8996", .data = &cfg_2_3_2 },
>  	{ .compatible = "qcom,pcie-qcs404", .data = &cfg_2_4_0 },
>  	{ .compatible = "qcom,pcie-sa8540p", .data = &cfg_1_9_0 },
> -- 
> 2.17.1
>

Devi Priya Feb. 28, 2023, 5:28 a.m. UTC | #6

On 2/24/2023 1:59 PM, Manivannan Sadhasivam wrote:
> On Tue, Feb 14, 2023 at 10:11:30PM +0530, Devi Priya wrote:
>> Adding PCIe support for IPQ9574 SoC
>>
> 
> Please add some information about the PCIe IP in the commit message.
> Like, the Synopsys IP version, Gen speed etc... and how the support
> is added (using existing config or a new one).
> 
> As others have mentioned, you could reuse the existing config. In that
> case, add the info in commit message as I suggested above.
> 
> And the PCI patch should come last in the series after bindings and dts
> patches.
> 
Sure, will update this accordingly in the next spin
> Thanks,
> Mani
> 
>> Co-developed-by: Anusha Rao <quic_anusha@quicinc.com>
>> Signed-off-by: Anusha Rao <quic_anusha@quicinc.com>
>> Signed-off-by: Devi Priya <quic_devipriy@quicinc.com>
>> ---
>>   drivers/pci/controller/dwc/pcie-qcom.c | 119 +++++++++++++++++++++++++
>>   1 file changed, 119 insertions(+)
>>
>> diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
>> index a232b04af048..57606c113d45 100644
>> --- a/drivers/pci/controller/dwc/pcie-qcom.c
>> +++ b/drivers/pci/controller/dwc/pcie-qcom.c
>> @@ -193,6 +193,12 @@ struct qcom_pcie_resources_2_9_0 {
>>   	struct reset_control *rst;
>>   };
>>   
>> +struct qcom_pcie_resources_1_27_0 {
>> +	struct clk_bulk_data *clks;
>> +	struct reset_control *rst;
>> +	int num_clks;
>> +};
>> +
>>   union qcom_pcie_resources {
>>   	struct qcom_pcie_resources_1_0_0 v1_0_0;
>>   	struct qcom_pcie_resources_2_1_0 v2_1_0;
>> @@ -201,6 +207,7 @@ union qcom_pcie_resources {
>>   	struct qcom_pcie_resources_2_4_0 v2_4_0;
>>   	struct qcom_pcie_resources_2_7_0 v2_7_0;
>>   	struct qcom_pcie_resources_2_9_0 v2_9_0;
>> +	struct qcom_pcie_resources_1_27_0 v1_27_0;
>>   };
>>   
>>   struct qcom_pcie;
>> @@ -1409,6 +1416,104 @@ static int qcom_pcie_post_init_2_9_0(struct qcom_pcie *pcie)
>>   	return 0;
>>   }
>>   
>> +static int qcom_pcie_get_resources_1_27_0(struct qcom_pcie *pcie)
>> +{
>> +	struct qcom_pcie_resources_1_27_0 *res = &pcie->res.v1_27_0;
>> +	struct dw_pcie *pci = pcie->pci;
>> +	struct device *dev = pci->dev;
>> +
>> +	res->num_clks = devm_clk_bulk_get_all(dev, &res->clks);
>> +	if (res->clks < 0)
>> +		return res->num_clks;
>> +
>> +	res->rst = devm_reset_control_array_get_exclusive(dev);
>> +	if (IS_ERR(res->rst))
>> +		return PTR_ERR(res->rst);
>> +
>> +	return 0;
>> +}
>> +
>> +static void qcom_pcie_deinit_1_27_0(struct qcom_pcie *pcie)
>> +{
>> +	struct qcom_pcie_resources_1_27_0 *res = &pcie->res.v1_27_0;
>> +
>> +	clk_bulk_disable_unprepare(res->num_clks, res->clks);
>> +}
>> +
>> +static int qcom_pcie_init_1_27_0(struct qcom_pcie *pcie)
>> +{
>> +	struct qcom_pcie_resources_1_27_0 *res = &pcie->res.v1_27_0;
>> +	struct device *dev = pcie->pci->dev;
>> +	int ret;
>> +
>> +	ret = reset_control_assert(res->rst);
>> +	if (ret) {
>> +		dev_err(dev, "reset assert failed (%d)\n", ret);
>> +		return ret;
>> +	}
>> +
>> +	/*
>> +	 * Delay periods before and after reset deassert are working values
>> +	 * from downstream Codeaurora kernel
>> +	 */
>> +	usleep_range(2000, 2500);
>> +
>> +	ret = reset_control_deassert(res->rst);
>> +	if (ret) {
>> +		dev_err(dev, "reset deassert failed (%d)\n", ret);
>> +		return ret;
>> +	}
>> +
>> +	usleep_range(2000, 2500);
>> +
>> +	return clk_bulk_prepare_enable(res->num_clks, res->clks);
>> +}
>> +
>> +static int qcom_pcie_post_init_1_27_0(struct qcom_pcie *pcie)
>> +{
>> +	struct dw_pcie *pci = pcie->pci;
>> +	u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
>> +	u32 val;
>> +	int i;
>> +
>> +	writel(0x8000000, pcie->parf + PCIE20_v3_PARF_SLV_ADDR_SPACE_SIZE);
>> +
>> +	val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL);
>> +	val &= ~BIT(0);
>> +	writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL);
>> +
>> +	writel(0, pcie->parf + PCIE20_PARF_DBI_BASE_ADDR);
>> +
>> +	writel(DEVICE_TYPE_RC, pcie->parf + PCIE20_PARF_DEVICE_TYPE);
>> +	writel(BYPASS | MSTR_AXI_CLK_EN | AHB_CLK_EN,
>> +	       pcie->parf + PCIE20_PARF_MHI_CLOCK_RESET_CTRL);
>> +	writel(GEN3_RELATED_OFF_RXEQ_RGRDLESS_RXTS |
>> +	       GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL,
>> +	       pci->dbi_base + GEN3_RELATED_OFF);
>> +
>> +	writel(MST_WAKEUP_EN | SLV_WAKEUP_EN | MSTR_ACLK_CGC_DIS |
>> +	       SLV_ACLK_CGC_DIS | CORE_CLK_CGC_DIS |
>> +	       AUX_PWR_DET | L23_CLK_RMV_DIS | L1_CLK_RMV_DIS,
>> +	       pcie->parf + PCIE20_PARF_SYS_CTRL);
>> +
>> +	writel(0, pcie->parf + PCIE20_PARF_Q2A_FLUSH);
>> +
>> +	dw_pcie_dbi_ro_wr_en(pci);
>> +	writel(PCIE_CAP_SLOT_VAL, pci->dbi_base + offset + PCI_EXP_SLTCAP);
>> +
>> +	val = readl(pci->dbi_base + offset + PCI_EXP_LNKCAP);
>> +	val &= ~PCI_EXP_LNKCAP_ASPMS;
>> +	writel(val, pci->dbi_base + offset + PCI_EXP_LNKCAP);
>> +
>> +	writel(PCI_EXP_DEVCTL2_COMP_TMOUT_DIS, pci->dbi_base + offset +
>> +	       PCI_EXP_DEVCTL2);
>> +
>> +	for (i = 0; i < 256; i++)
>> +		writel(0, pcie->parf + PCIE20_PARF_BDF_TO_SID_TABLE_N + (4 * i));
>> +
>> +	return 0;
>> +}
>> +
>>   static int qcom_pcie_link_up(struct dw_pcie *pci)
>>   {
>>   	u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
>> @@ -1620,6 +1725,15 @@ static const struct qcom_pcie_ops ops_2_9_0 = {
>>   	.ltssm_enable = qcom_pcie_2_3_2_ltssm_enable,
>>   };
>>   
>> +/* Qcom IP rev.: 1.27.0 Synopsys IP rev.: 5.80a */
>> +static const struct qcom_pcie_ops ops_1_27_0 = {
>> +	.get_resources = qcom_pcie_get_resources_1_27_0,
>> +	.init = qcom_pcie_init_1_27_0,
>> +	.post_init = qcom_pcie_post_init_1_27_0,
>> +	.deinit = qcom_pcie_deinit_1_27_0,
>> +	.ltssm_enable = qcom_pcie_2_3_2_ltssm_enable,
>> +};
>> +
>>   static const struct qcom_pcie_cfg cfg_1_0_0 = {
>>   	.ops = &ops_1_0_0,
>>   };
>> @@ -1652,6 +1766,10 @@ static const struct qcom_pcie_cfg cfg_2_9_0 = {
>>   	.ops = &ops_2_9_0,
>>   };
>>   
>> +static const struct qcom_pcie_cfg cfg_1_27_0 = {
>> +	.ops = &ops_1_27_0,
>> +};
>> +
>>   static const struct dw_pcie_ops dw_pcie_ops = {
>>   	.link_up = qcom_pcie_link_up,
>>   	.start_link = qcom_pcie_start_link,
>> @@ -1829,6 +1947,7 @@ static const struct of_device_id qcom_pcie_match[] = {
>>   	{ .compatible = "qcom,pcie-ipq8064-v2", .data = &cfg_2_1_0 },
>>   	{ .compatible = "qcom,pcie-ipq8074", .data = &cfg_2_3_3 },
>>   	{ .compatible = "qcom,pcie-ipq8074-gen3", .data = &cfg_2_9_0 },
>> +	{ .compatible = "qcom,pcie-ipq9574", .data = &cfg_1_27_0 },
>>   	{ .compatible = "qcom,pcie-msm8996", .data = &cfg_2_3_2 },
>>   	{ .compatible = "qcom,pcie-qcs404", .data = &cfg_2_4_0 },
>>   	{ .compatible = "qcom,pcie-sa8540p", .data = &cfg_1_9_0 },
>> -- 
>> 2.17.1
>>
> 
Thanks,
Devi Priya

diff mbox series

Patch

diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
index a232b04af048..57606c113d45 100644
--- a/drivers/pci/controller/dwc/pcie-qcom.c
+++ b/drivers/pci/controller/dwc/pcie-qcom.c
@@ -193,6 +193,12 @@  struct qcom_pcie_resources_2_9_0 {
 	struct reset_control *rst;
 };
 
+struct qcom_pcie_resources_1_27_0 {
+	struct clk_bulk_data *clks;
+	struct reset_control *rst;
+	int num_clks;
+};
+
 union qcom_pcie_resources {
 	struct qcom_pcie_resources_1_0_0 v1_0_0;
 	struct qcom_pcie_resources_2_1_0 v2_1_0;
@@ -201,6 +207,7 @@  union qcom_pcie_resources {
 	struct qcom_pcie_resources_2_4_0 v2_4_0;
 	struct qcom_pcie_resources_2_7_0 v2_7_0;
 	struct qcom_pcie_resources_2_9_0 v2_9_0;
+	struct qcom_pcie_resources_1_27_0 v1_27_0;
 };
 
 struct qcom_pcie;
@@ -1409,6 +1416,104 @@  static int qcom_pcie_post_init_2_9_0(struct qcom_pcie *pcie)
 	return 0;
 }
 
+static int qcom_pcie_get_resources_1_27_0(struct qcom_pcie *pcie)
+{
+	struct qcom_pcie_resources_1_27_0 *res = &pcie->res.v1_27_0;
+	struct dw_pcie *pci = pcie->pci;
+	struct device *dev = pci->dev;
+
+	res->num_clks = devm_clk_bulk_get_all(dev, &res->clks);
+	if (res->clks < 0)
+		return res->num_clks;
+
+	res->rst = devm_reset_control_array_get_exclusive(dev);
+	if (IS_ERR(res->rst))
+		return PTR_ERR(res->rst);
+
+	return 0;
+}
+
+static void qcom_pcie_deinit_1_27_0(struct qcom_pcie *pcie)
+{
+	struct qcom_pcie_resources_1_27_0 *res = &pcie->res.v1_27_0;
+
+	clk_bulk_disable_unprepare(res->num_clks, res->clks);
+}
+
+static int qcom_pcie_init_1_27_0(struct qcom_pcie *pcie)
+{
+	struct qcom_pcie_resources_1_27_0 *res = &pcie->res.v1_27_0;
+	struct device *dev = pcie->pci->dev;
+	int ret;
+
+	ret = reset_control_assert(res->rst);
+	if (ret) {
+		dev_err(dev, "reset assert failed (%d)\n", ret);
+		return ret;
+	}
+
+	/*
+	 * Delay periods before and after reset deassert are working values
+	 * from downstream Codeaurora kernel
+	 */
+	usleep_range(2000, 2500);
+
+	ret = reset_control_deassert(res->rst);
+	if (ret) {
+		dev_err(dev, "reset deassert failed (%d)\n", ret);
+		return ret;
+	}
+
+	usleep_range(2000, 2500);
+
+	return clk_bulk_prepare_enable(res->num_clks, res->clks);
+}
+
+static int qcom_pcie_post_init_1_27_0(struct qcom_pcie *pcie)
+{
+	struct dw_pcie *pci = pcie->pci;
+	u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
+	u32 val;
+	int i;
+
+	writel(0x8000000, pcie->parf + PCIE20_v3_PARF_SLV_ADDR_SPACE_SIZE);
+
+	val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL);
+	val &= ~BIT(0);
+	writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL);
+
+	writel(0, pcie->parf + PCIE20_PARF_DBI_BASE_ADDR);
+
+	writel(DEVICE_TYPE_RC, pcie->parf + PCIE20_PARF_DEVICE_TYPE);
+	writel(BYPASS | MSTR_AXI_CLK_EN | AHB_CLK_EN,
+	       pcie->parf + PCIE20_PARF_MHI_CLOCK_RESET_CTRL);
+	writel(GEN3_RELATED_OFF_RXEQ_RGRDLESS_RXTS |
+	       GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL,
+	       pci->dbi_base + GEN3_RELATED_OFF);
+
+	writel(MST_WAKEUP_EN | SLV_WAKEUP_EN | MSTR_ACLK_CGC_DIS |
+	       SLV_ACLK_CGC_DIS | CORE_CLK_CGC_DIS |
+	       AUX_PWR_DET | L23_CLK_RMV_DIS | L1_CLK_RMV_DIS,
+	       pcie->parf + PCIE20_PARF_SYS_CTRL);
+
+	writel(0, pcie->parf + PCIE20_PARF_Q2A_FLUSH);
+
+	dw_pcie_dbi_ro_wr_en(pci);
+	writel(PCIE_CAP_SLOT_VAL, pci->dbi_base + offset + PCI_EXP_SLTCAP);
+
+	val = readl(pci->dbi_base + offset + PCI_EXP_LNKCAP);
+	val &= ~PCI_EXP_LNKCAP_ASPMS;
+	writel(val, pci->dbi_base + offset + PCI_EXP_LNKCAP);
+
+	writel(PCI_EXP_DEVCTL2_COMP_TMOUT_DIS, pci->dbi_base + offset +
+	       PCI_EXP_DEVCTL2);
+
+	for (i = 0; i < 256; i++)
+		writel(0, pcie->parf + PCIE20_PARF_BDF_TO_SID_TABLE_N + (4 * i));
+
+	return 0;
+}
+
 static int qcom_pcie_link_up(struct dw_pcie *pci)
 {
 	u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
@@ -1620,6 +1725,15 @@  static const struct qcom_pcie_ops ops_2_9_0 = {
 	.ltssm_enable = qcom_pcie_2_3_2_ltssm_enable,
 };
 
+/* Qcom IP rev.: 1.27.0 Synopsys IP rev.: 5.80a */
+static const struct qcom_pcie_ops ops_1_27_0 = {
+	.get_resources = qcom_pcie_get_resources_1_27_0,
+	.init = qcom_pcie_init_1_27_0,
+	.post_init = qcom_pcie_post_init_1_27_0,
+	.deinit = qcom_pcie_deinit_1_27_0,
+	.ltssm_enable = qcom_pcie_2_3_2_ltssm_enable,
+};
+
 static const struct qcom_pcie_cfg cfg_1_0_0 = {
 	.ops = &ops_1_0_0,
 };
@@ -1652,6 +1766,10 @@  static const struct qcom_pcie_cfg cfg_2_9_0 = {
 	.ops = &ops_2_9_0,
 };
 
+static const struct qcom_pcie_cfg cfg_1_27_0 = {
+	.ops = &ops_1_27_0,
+};
+
 static const struct dw_pcie_ops dw_pcie_ops = {
 	.link_up = qcom_pcie_link_up,
 	.start_link = qcom_pcie_start_link,
@@ -1829,6 +1947,7 @@  static const struct of_device_id qcom_pcie_match[] = {
 	{ .compatible = "qcom,pcie-ipq8064-v2", .data = &cfg_2_1_0 },
 	{ .compatible = "qcom,pcie-ipq8074", .data = &cfg_2_3_3 },
 	{ .compatible = "qcom,pcie-ipq8074-gen3", .data = &cfg_2_9_0 },
+	{ .compatible = "qcom,pcie-ipq9574", .data = &cfg_1_27_0 },
 	{ .compatible = "qcom,pcie-msm8996", .data = &cfg_2_3_2 },
 	{ .compatible = "qcom,pcie-qcs404", .data = &cfg_2_4_0 },
 	{ .compatible = "qcom,pcie-sa8540p", .data = &cfg_1_9_0 },