[1/3] arm64: dts: qcom: qdu1000: Add IPCC, MPSS, AOSS nodes
Commit Message
Add nodes for IPCC, MPSS, and AOSS drivers. Also update
the scm node to include its interconnect.
Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
---
arch/arm64/boot/dts/qcom/qdu1000.dtsi | 105 ++++++++++++++++++++++++++
1 file changed, 105 insertions(+)
Comments
On 13/02/2023 20:01, Melody Olvera wrote:
> Add nodes for IPCC, MPSS, and AOSS drivers. Also update
> the scm node to include its interconnect.
>
> Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
> ---
>
> + aoss_qmp: power-controller@c300000 {
> + compatible = "qcom,qdu1000-aoss-qmp", "qcom,aoss-qmp";
> + reg = <0x0 0xc300000 0x0 0x400>;
> + interrupts-extended = <&ipcc IPCC_CLIENT_AOP
> + IPCC_MPROC_SIGNAL_GLINK_QMP
> + IRQ_TYPE_EDGE_RISING>;
> + mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>;
> +
> + #clock-cells = <0>;
> + #power-domain-cells = <1>;
This does not look right. Which part of aoss-qmp registers power domains?
Best regards,
Krzysztof
On 2/14/2023 1:47 AM, Krzysztof Kozlowski wrote:
> On 13/02/2023 20:01, Melody Olvera wrote:
>> Add nodes for IPCC, MPSS, and AOSS drivers. Also update
>> the scm node to include its interconnect.
>>
>> Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
>> ---
>
>>
>> + aoss_qmp: power-controller@c300000 {
>> + compatible = "qcom,qdu1000-aoss-qmp", "qcom,aoss-qmp";
>> + reg = <0x0 0xc300000 0x0 0x400>;
>> + interrupts-extended = <&ipcc IPCC_CLIENT_AOP
>> + IPCC_MPROC_SIGNAL_GLINK_QMP
>> + IRQ_TYPE_EDGE_RISING>;
>> + mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>;
>> +
>> + #clock-cells = <0>;
>> + #power-domain-cells = <1>;
> This does not look right. Which part of aoss-qmp registers power domains?
You're right; I didn't realize part of the driver that registered this had been removed. Will drop
that line.
Thanks,
Melody
>
> Best regards,
> Krzysztof
>
@@ -8,6 +8,7 @@
#include <dt-bindings/dma/qcom-gpi.h>
#include <dt-bindings/interconnect/qcom,qdu1000-rpmh.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/mailbox/qcom-ipcc.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
@@ -141,6 +142,7 @@ CLUSTER_SLEEP_1: cluster-sleep-1 {
firmware {
scm {
compatible = "qcom,scm-qdu1000", "qcom,scm";
+ interconnects = <&system_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>;
};
};
@@ -326,6 +328,11 @@ q6_mpss_dtb_mem: q6-mpss-dtb@9ec00000 {
no-map;
};
+ mpss_dsm_mem: mpss-dsm@9ec80000 {
+ reg = <0x0 0x9ec80000 0x0 0x880000>;
+ no-map;
+ };
+
tenx_mem: tenx@a0000000 {
reg = <0x0 0xa0000000 0x0 0x19600000>;
no-map;
@@ -347,6 +354,28 @@ ipa_buffer_mem: ipa-buffer@c3200000 {
};
};
+ smp2p-modem {
+ compatible = "qcom,smp2p";
+ qcom,smem = <435>, <428>;
+ interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
+ IPCC_MPROC_SIGNAL_SMP2P
+ IRQ_TYPE_EDGE_RISING>;
+ mboxes = <&ipcc IPCC_CLIENT_MPSS IPCC_MPROC_SIGNAL_SMP2P>;
+ qcom,local-pid = <0>;
+ qcom,remote-pid = <1>;
+
+ smp2p_modem_out: master-kernel {
+ qcom,entry-name = "master-kernel";
+ #qcom,smem-state-cells = <1>;
+ };
+
+ smp2p_modem_in: slave-kernel {
+ qcom,entry-name = "slave-kernel";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
soc: soc@0 {
compatible = "simple-bus";
#address-cells = <2>;
@@ -367,6 +396,15 @@ gcc: clock-controller@80000 {
#power-domain-cells = <1>;
};
+ ipcc: mailbox@408000 {
+ compatible = "qcom,qdu1000-ipcc", "qcom,ipcc";
+ reg = <0x0 0x408000 0x0 0x1000>;
+ interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ #mbox-cells = <2>;
+ };
+
gpi_dma0: dma-controller@900000 {
compatible = "qcom,qdu1000-gpi-dma", "qcom,sm6350-gpi-dma";
reg = <0x0 0x900000 0x0 0x60000>;
@@ -842,6 +880,49 @@ tcsr_mutex: hwlock@1f40000 {
#hwlock-cells = <1>;
};
+ remoteproc_mpss: remoteproc@4080000 {
+ compatible = "qcom,qdu1000-mpss-pas";
+ reg = <0x0 0x4080000 0x0 0x4040>,
+ <0x0 0x4180000 0x0 0x1000>;
+
+ interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "wdog", "fatal", "ready", "handover",
+ "stop-ack", "shutdown-ack";
+
+ clocks = <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "xo";
+
+ power-domains = <&rpmhpd QDU1000_CX>,
+ <&rpmhpd QDU1000_MSS>;
+ power-domain-names = "cx", "mss";
+
+ memory-region = <&mpss_mem>, <&q6_mpss_dtb_mem>, <&mpss_dsm_mem>;
+
+ interconnects = <&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>;
+
+ qcom,qmp = <&aoss_qmp>;
+
+ qcom,smem-states = <&smp2p_modem_out 0>;
+ qcom,smem-state-names = "stop";
+
+ status = "disabled";
+
+ glink-edge {
+ interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
+ IPCC_MPROC_SIGNAL_GLINK_QMP
+ IRQ_TYPE_EDGE_RISING>;
+ mboxes = <&ipcc IPCC_CLIENT_MPSS
+ IPCC_MPROC_SIGNAL_GLINK_QMP>;
+ label = "modem";
+ qcom,remote-pid = <1>;
+ };
+ };
+
pdc: interrupt-controller@b220000 {
compatible = "qcom,qdu1000-pdc", "qcom,pdc";
reg = <0x0 0xb220000 0x0 0x30000>, <0x0 0x174000f0 0x0 0x64>;
@@ -852,6 +933,30 @@ pdc: interrupt-controller@b220000 {
interrupt-controller;
};
+ aoss_qmp: power-controller@c300000 {
+ compatible = "qcom,qdu1000-aoss-qmp", "qcom,aoss-qmp";
+ reg = <0x0 0xc300000 0x0 0x400>;
+ interrupts-extended = <&ipcc IPCC_CLIENT_AOP
+ IPCC_MPROC_SIGNAL_GLINK_QMP
+ IRQ_TYPE_EDGE_RISING>;
+ mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>;
+
+ #clock-cells = <0>;
+ #power-domain-cells = <1>;
+
+ cx_cdev: cx {
+ #cooling-cells = <2>;
+ };
+
+ mx_cdev: mx {
+ #cooling-cells = <2>;
+ };
+
+ ebi_cdev: ebi {
+ #cooling-cells = <2>;
+ };
+ };
+
spmi_bus: spmi@c400000 {
compatible = "qcom,spmi-pmic-arb";
reg = <0x0 0xc400000 0x0 0x3000>,