Message ID | 20230210061713.6449-2-changhuang.liang@starfivetech.com |
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State | New |
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[2620:137:e000::1:20]) by mx.google.com with ESMTP id t10-20020a170906c38a00b00878809a0f92si4403448ejz.541.2023.02.09.22.21.30; Thu, 09 Feb 2023 22:21:53 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231341AbjBJGRb convert rfc822-to-8bit (ORCPT <rfc822;ybw1215001957@gmail.com> + 99 others); Fri, 10 Feb 2023 01:17:31 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47198 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231295AbjBJGRZ (ORCPT <rfc822;linux-kernel@vger.kernel.org>); Fri, 10 Feb 2023 01:17:25 -0500 Received: from ex01.ufhost.com (ex01.ufhost.com [61.152.239.75]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DB1035C49F; Thu, 9 Feb 2023 22:17:23 -0800 (PST) Received: from EXMBX165.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX165", Issuer "EXMBX165" (not verified)) by ex01.ufhost.com (Postfix) with ESMTP id 3866124E26A; Fri, 10 Feb 2023 14:17:17 +0800 (CST) Received: from EXMBX162.cuchost.com (172.16.6.72) by EXMBX165.cuchost.com (172.16.6.75) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Fri, 10 Feb 2023 14:17:17 +0800 Received: from ubuntu.localdomain (183.27.96.33) by EXMBX162.cuchost.com (172.16.6.72) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Fri, 10 Feb 2023 14:17:16 +0800 From: Changhuang Liang <changhuang.liang@starfivetech.com> To: Vinod Koul <vkoul@kernel.org>, Kishon Vijay Abraham I <kishon@kernel.org>, Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Emil Renner Berthing <kernel@esmil.dk>, Conor Dooley <conor@kernel.org>, Paul Walmsley <paul.walmsley@sifive.com>, Palmer Dabbelt <palmer@dabbelt.com>, Albert Ou <aou@eecs.berkeley.edu>, Philipp Zabel <p.zabel@pengutronix.de> CC: Jack Zhu <jack.zhu@starfivetech.com>, Changhuang Liang <changhuang.liang@starfivetech.com>, <linux-phy@lists.infradead.org>, <devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>, <linux-riscv@lists.infradead.org> Subject: [PATCH v1 1/4] riscv: dts: starfive: jh7110: Add aon syscon node Date: Thu, 9 Feb 2023 22:17:10 -0800 Message-ID: <20230210061713.6449-2-changhuang.liang@starfivetech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230210061713.6449-1-changhuang.liang@starfivetech.com> References: <20230210061713.6449-1-changhuang.liang@starfivetech.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [183.27.96.33] X-ClientProxiedBy: EXCAS064.cuchost.com (172.16.6.24) To EXMBX162.cuchost.com (172.16.6.72) X-YovoleRuleAgent: yovoleflag Content-Transfer-Encoding: 8BIT X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: <linux-kernel.vger.kernel.org> X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1757423980938757030?= X-GMAIL-MSGID: =?utf-8?q?1757423980938757030?= |
Series |
Add JH7110 MIPI DPHY RX support
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Commit Message
Changhuang Liang
Feb. 10, 2023, 6:17 a.m. UTC
Add aon syscon node for the Starfive JH7110 SoC. It can be used by
other modules such as DPHY.
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
---
arch/riscv/boot/dts/starfive/jh7110.dtsi | 5 +++++
1 file changed, 5 insertions(+)
Comments
On 10/02/2023 07:17, Changhuang Liang wrote: > Add aon syscon node for the Starfive JH7110 SoC. It can be used by > other modules such as DPHY. > > Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com> > --- > arch/riscv/boot/dts/starfive/jh7110.dtsi | 5 +++++ > 1 file changed, 5 insertions(+) > > diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi > index cfbaff4ea64b..bce3e407ab60 100644 > --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi > +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi > @@ -251,6 +251,11 @@ soc { > #size-cells = <2>; > ranges; > > + aon_syscon: aon_syscon@17010000 { No underscores in node names, generic node names. https://devicetree-specification.readthedocs.io/en/latest/chapter2-devicetree-basics.html#generic-names-recommendation > + compatible = "syscon"; Nope. syscon cannot be alone. Run dtbs_check before sending DTS. Best regards, Krzysztof
On 2023/2/13 17:28, Krzysztof Kozlowski wrote: > On 10/02/2023 07:17, Changhuang Liang wrote: >> Add aon syscon node for the Starfive JH7110 SoC. It can be used by >> other modules such as DPHY. >> >> Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com> >> --- >> arch/riscv/boot/dts/starfive/jh7110.dtsi | 5 +++++ >> 1 file changed, 5 insertions(+) >> >> diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi >> index cfbaff4ea64b..bce3e407ab60 100644 >> --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi >> +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi >> @@ -251,6 +251,11 @@ soc { >> #size-cells = <2>; >> ranges; >> >> + aon_syscon: aon_syscon@17010000 { > > No underscores in node names, generic node names. > OK, will change to "syscon". > https://devicetree-specification.readthedocs.io/en/latest/chapter2-devicetree-basics.html#generic-names-recommendation > >> + compatible = "syscon"; > > Nope. syscon cannot be alone. Run dtbs_check before sending DTS. > OK, will fix it. > > Best regards, > Krzysztof >
diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi index cfbaff4ea64b..bce3e407ab60 100644 --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi @@ -251,6 +251,11 @@ soc { #size-cells = <2>; ranges; + aon_syscon: aon_syscon@17010000 { + compatible = "syscon"; + reg = <0x0 0x17010000 0x0 0x1000>; + }; + clint: clint@2000000 { compatible = "starfive,jh7110-clint", "sifive,clint0"; reg = <0x0 0x2000000 0x0 0x10000>;