diff mbox series

[V3] tty: serial: fsl_lpuart: don't break the on-going transfer when global reset

Message ID 20221020131938.32454-1-sherry.sun@nxp.com
State New
Headers
Series [V3] tty: serial: fsl_lpuart: don't break the on-going transfer when global reset |

Commit Message

Sherry Sun Oct. 20, 2022, 1:19 p.m. UTC 
  lpuart_global_reset() shouldn't break the on-going transmit engine, need
to recover the on-going data transfer after reset.

This can help earlycon here, since commit 60f361722ad2 ("serial:
fsl_lpuart: Reset prior to registration") moved lpuart_global_reset()
before uart_add_one_port(), earlycon is writing during global reset,
as global reset will disable the TX and clear the baud rate register,
which caused the earlycon cannot work any more after reset, needs to
restore the baud rate and re-enable the transmitter to recover the
earlycon write.

Also move the lpuart_global_reset() down, then we can reuse the
lpuart32_tx_empty() without declaration.

Fixes: bd5305dcabbc ("tty: serial: fsl_lpuart: do software reset for imx7ulp and imx8qxp")
Signed-off-by: Sherry Sun <sherry.sun@nxp.com>
---
Changes in V3:
1. Replace "engin" with "engine".
2. Use read_poll_timeout_atomic() to add a 100ms timeout when polling the
transmit engine to complete.
3. Restore the whole ctrl register after global reset to avoid any confusion. 
4. Move the lpuart_global_reset() down, then we can reuse lpuart32_tx_empty()
without declaration.

Changes in V2:
1. The while loop may never exit as the stat and sfifo are not re-read inside
the loop, fix that.
---
 drivers/tty/serial/fsl_lpuart.c | 76 +++++++++++++++++++++------------
 1 file changed, 49 insertions(+), 27 deletions(-)

Comments

Jiri Slaby Oct. 24, 2022, 6:37 a.m. UTC | #1 
On 20. 10. 22, 15:19, Sherry Sun wrote:
> @@ -2636,6 +2610,54 @@ static const struct serial_rs485 lpuart_rs485_supported = {
>   	/* delay_rts_* and RX_DURING_TX are not supported */
>   };
>   
> +static int lpuart_global_reset(struct lpuart_port *sport)
> +{
> +	struct uart_port *port = &sport->port;
> +	void __iomem *global_addr;
> +	unsigned long ctrl, bd;
> +	unsigned int val = 0;
> +	int ret;
> +
> +	ret = clk_prepare_enable(sport->ipg_clk);
> +	if (ret) {
> +		dev_err(sport->port.dev, "failed to enable uart ipg clk: %d\n", ret);
> +		return ret;
> +	}
> +
> +	if (is_imx7ulp_lpuart(sport) || is_imx8qxp_lpuart(sport)) {
> +		/*
> +		 * If the transmitter is used by earlycon, wait for transmit engine to
> +		 * complete and then reset.
> +		 */
> +		ctrl = lpuart32_read(port, UARTCTRL);
> +		if (ctrl & UARTCTRL_TE) {
> +			bd = lpuart32_read(&sport->port, UARTBAUD);
> +			if (read_poll_timeout_atomic(lpuart32_tx_empty, val, val, 1, 100000,
> +						     false, port)) {

Ah, this is not atomic context (clk_prepare_enable() above and 
usleep_range() below), so no need for _atomic here too.

thanks,
Sherry Sun Oct. 24, 2022, 8:16 a.m. UTC | #2 
> -----Original Message-----
> From: Jiri Slaby <jirislaby@kernel.org>
> Sent: 2022年10月24日 14:37
> To: Sherry Sun <sherry.sun@nxp.com>; gregkh@linuxfoundation.org;
> lukas@wunner.de; ilpo.jarvinen@linux.intel.com
> Cc: linux-serial@vger.kernel.org; linux-kernel@vger.kernel.org; dl-linux-imx
> <linux-imx@nxp.com>
> Subject: Re: [PATCH V3] tty: serial: fsl_lpuart: don't break the on-going
> transfer when global reset
> 
> On 20. 10. 22, 15:19, Sherry Sun wrote:
> > @@ -2636,6 +2610,54 @@ static const struct serial_rs485
> lpuart_rs485_supported = {
> >   	/* delay_rts_* and RX_DURING_TX are not supported */
> >   };
> >
> > +static int lpuart_global_reset(struct lpuart_port *sport) {
> > +	struct uart_port *port = &sport->port;
> > +	void __iomem *global_addr;
> > +	unsigned long ctrl, bd;
> > +	unsigned int val = 0;
> > +	int ret;
> > +
> > +	ret = clk_prepare_enable(sport->ipg_clk);
> > +	if (ret) {
> > +		dev_err(sport->port.dev, "failed to enable uart ipg clk: %d\n",
> ret);
> > +		return ret;
> > +	}
> > +
> > +	if (is_imx7ulp_lpuart(sport) || is_imx8qxp_lpuart(sport)) {
> > +		/*
> > +		 * If the transmitter is used by earlycon, wait for transmit
> engine to
> > +		 * complete and then reset.
> > +		 */
> > +		ctrl = lpuart32_read(port, UARTCTRL);
> > +		if (ctrl & UARTCTRL_TE) {
> > +			bd = lpuart32_read(&sport->port, UARTBAUD);
> > +			if (read_poll_timeout_atomic(lpuart32_tx_empty, val,
> val, 1, 100000,
> > +						     false, port)) {
> 
> Ah, this is not atomic context (clk_prepare_enable() above and
> usleep_range() below), so no need for _atomic here too.
> 

Hi Jiri,
You are right, thanks for the correction, will fix it in V4.

Best Regards
Sherry
diff mbox series

Patch

diff --git a/drivers/tty/serial/fsl_lpuart.c b/drivers/tty/serial/fsl_lpuart.c
index 67fa113f77d4..be78c61e8a0b 100644
--- a/drivers/tty/serial/fsl_lpuart.c
+++ b/drivers/tty/serial/fsl_lpuart.c
@@ -12,6 +12,7 @@ 
 #include <linux/dmaengine.h>
 #include <linux/dmapool.h>
 #include <linux/io.h>
+#include <linux/iopoll.h>
 #include <linux/irq.h>
 #include <linux/module.h>
 #include <linux/of.h>
@@ -404,33 +405,6 @@  static unsigned int lpuart_get_baud_clk_rate(struct lpuart_port *sport)
 #define lpuart_enable_clks(x)	__lpuart_enable_clks(x, true)
 #define lpuart_disable_clks(x)	__lpuart_enable_clks(x, false)
 
-static int lpuart_global_reset(struct lpuart_port *sport)
-{
-	struct uart_port *port = &sport->port;
-	void __iomem *global_addr;
-	int ret;
-
-	if (uart_console(port))
-		return 0;
-
-	ret = clk_prepare_enable(sport->ipg_clk);
-	if (ret) {
-		dev_err(sport->port.dev, "failed to enable uart ipg clk: %d\n", ret);
-		return ret;
-	}
-
-	if (is_imx7ulp_lpuart(sport) || is_imx8qxp_lpuart(sport)) {
-		global_addr = port->membase + UART_GLOBAL - IMX_REG_OFF;
-		writel(UART_GLOBAL_RST, global_addr);
-		usleep_range(GLOBAL_RST_MIN_US, GLOBAL_RST_MAX_US);
-		writel(0, global_addr);
-		usleep_range(GLOBAL_RST_MIN_US, GLOBAL_RST_MAX_US);
-	}
-
-	clk_disable_unprepare(sport->ipg_clk);
-	return 0;
-}
-
 static void lpuart_stop_tx(struct uart_port *port)
 {
 	unsigned char temp;
@@ -2636,6 +2610,54 @@  static const struct serial_rs485 lpuart_rs485_supported = {
 	/* delay_rts_* and RX_DURING_TX are not supported */
 };
 
+static int lpuart_global_reset(struct lpuart_port *sport)
+{
+	struct uart_port *port = &sport->port;
+	void __iomem *global_addr;
+	unsigned long ctrl, bd;
+	unsigned int val = 0;
+	int ret;
+
+	ret = clk_prepare_enable(sport->ipg_clk);
+	if (ret) {
+		dev_err(sport->port.dev, "failed to enable uart ipg clk: %d\n", ret);
+		return ret;
+	}
+
+	if (is_imx7ulp_lpuart(sport) || is_imx8qxp_lpuart(sport)) {
+		/*
+		 * If the transmitter is used by earlycon, wait for transmit engine to
+		 * complete and then reset.
+		 */
+		ctrl = lpuart32_read(port, UARTCTRL);
+		if (ctrl & UARTCTRL_TE) {
+			bd = lpuart32_read(&sport->port, UARTBAUD);
+			if (read_poll_timeout_atomic(lpuart32_tx_empty, val, val, 1, 100000,
+						     false, port)) {
+				dev_warn(sport->port.dev,
+					 "timeout waiting for transmit engine to complete\n");
+				clk_disable_unprepare(sport->ipg_clk);
+				return 0;
+			}
+		}
+
+		global_addr = port->membase + UART_GLOBAL - IMX_REG_OFF;
+		writel(UART_GLOBAL_RST, global_addr);
+		usleep_range(GLOBAL_RST_MIN_US, GLOBAL_RST_MAX_US);
+		writel(0, global_addr);
+		usleep_range(GLOBAL_RST_MIN_US, GLOBAL_RST_MAX_US);
+
+		/* Recover the transmitter for earlycon. */
+		if (ctrl & UARTCTRL_TE) {
+			lpuart32_write(port, bd, UARTBAUD);
+			lpuart32_write(port, ctrl, UARTCTRL);
+		}
+	}
+
+	clk_disable_unprepare(sport->ipg_clk);
+	return 0;
+}
+
 static int lpuart_probe(struct platform_device *pdev)
 {
 	const struct lpuart_soc_data *sdata = of_device_get_match_data(&pdev->dev);