[06/10] Support Intel RAO-INT
Checks
Commit Message
From: Kong Lingling <lingling.kong@intel.com>
gas/ChangeLog:
* NEWS: Support Intel RAO-INT.
* config/tc-i386.c: Add raoint.
* doc/c-i386.texi: Document .raoint and noraoint.
* testsuite/gas/i386/i386.exp: Run RAOINT tests.
* testsuite/gas/i386/raoint-intel.d: New test.
* testsuite/gas/i386/raoint.d: Ditto.
* testsuite/gas/i386/raoint.s: Ditto.
* testsuite/gas/i386/x86-64-raoint-intel.d: Ditto.
* testsuite/gas/i386/x86-64-raoint.d: Ditto.
* testsuite/gas/i386/x86-64-raoint.s: Ditto.
opcodes/ChangeLog:
* i386-dis.c (MOD_0F38FC): New.
(PREFIX_0F38FC): Ditto.
(mod_table): Add MOD_0F38FC.
(prefix_table): Add PREFIX_0F38FC.
* i386-gen.c: (cpu_flag_init): Add CPU_RAOINT_FLAGS and
CPU_ANY_RAOINT_FLAGS.
* i386-init.h: Regenerated.
* i386-opc.h: (CpuRAOINT): New.
(i386_cpu_flags): Add cpuraoint.
* i386-opc.tbl: Add RAOINT instructions.
* i386-tbl.h: Regenerated.
---
gas/NEWS | 2 +
gas/config/tc-i386.c | 3 +-
gas/doc/c-i386.texi | 4 +-
gas/testsuite/gas/i386/i386.exp | 4 +
gas/testsuite/gas/i386/raoint-intel.d | 18 +
gas/testsuite/gas/i386/raoint.d | 18 +
gas/testsuite/gas/i386/raoint.s | 15 +
gas/testsuite/gas/i386/x86-64-raoint-intel.d | 18 +
gas/testsuite/gas/i386/x86-64-raoint.d | 18 +
gas/testsuite/gas/i386/x86-64-raoint.s | 15 +
opcodes/i386-dis.c | 16 +-
opcodes/i386-gen.c | 5 +
opcodes/i386-init.h | 514 +-
opcodes/i386-opc.h | 5 +-
opcodes/i386-opc.tbl | 9 +
opcodes/i386-tbl.h | 7874 +++++++++---------
16 files changed, 4379 insertions(+), 4159 deletions(-)
create mode 100644 gas/testsuite/gas/i386/raoint-intel.d
create mode 100644 gas/testsuite/gas/i386/raoint.d
create mode 100644 gas/testsuite/gas/i386/raoint.s
create mode 100644 gas/testsuite/gas/i386/x86-64-raoint-intel.d
create mode 100644 gas/testsuite/gas/i386/x86-64-raoint.d
create mode 100644 gas/testsuite/gas/i386/x86-64-raoint.s
Comments
On 14.10.2022 11:12, Haochen Jiang wrote:
> --- a/gas/config/tc-i386.c
> +++ b/gas/config/tc-i386.c
> @@ -1097,7 +1097,8 @@ static const arch_entry cpu_arch[] =
> SUBARCH (avx_ifma, AVX_IFMA, ANY_AVX_IFMA, false),
> SUBARCH (avx_vnni_int8, AVX_VNNI_INT8, ANY_AVX_VNNI_INT8, false),
> SUBARCH (avx_ne_convert, AVX_NE_CONVERT, ANY_AVX_NE_CONVERT, false),
> - SUBARCH (cmpccxadd, CMPCCXADD, ANY_CMPCCXADD, false)
> + SUBARCH (cmpccxadd, CMPCCXADD, ANY_CMPCCXADD, false),
> + SUBARCH (raoint, RAOINT, ANY_RAOINT, false),
As for the earlier patch - likely no need for ANY_RAOINT. Also please
have the earlier patch add the comma so you don't need to touch that
line again here (helping at least "git blame").
> --- a/opcodes/i386-dis.c
> +++ b/opcodes/i386-dis.c
> @@ -887,6 +887,7 @@ enum
> MOD_0F38F9,
> MOD_0F38FA_PREFIX_1,
> MOD_0F38FB_PREFIX_1,
> + MOD_0F38FC,
> MOD_0F3A0F_PREFIX_1,
>
> MOD_VEX_0F12_PREFIX_0,
> @@ -1086,6 +1087,7 @@ enum
> PREFIX_0F38F8,
> PREFIX_0F38FA,
> PREFIX_0F38FB,
> + PREFIX_0F38FC,
PREFIX_0F38FC_M_0 please (see comment on an earlier patch). However,
like in the earlier patch - if you used Mdq below, you could avoid
going through mod_table[] altogether.
> @@ -3598,6 +3600,14 @@ static const struct dis386 prefix_table[][4] = {
> { MOD_TABLE (MOD_0F38FB_PREFIX_1) },
> },
>
> + /* PREFIX_0F38FC */
> + {
> + { "aadd", { Edq, Gdq }, PREFIX_OPCODE },
> + { "axor", { Edq, Gdq }, PREFIX_OPCODE },
> + { "aand", { Edq, Gdq }, PREFIX_OPCODE },
> + { "aor", { Edq, Gdq }, PREFIX_OPCODE },
> + },
Once having gone through prefix_table[], PREFIX_OPCODE (and
PREFIX_DATA) are meaningless iirc and should hence be omitted.
> --- a/opcodes/i386-opc.tbl
> +++ b/opcodes/i386-opc.tbl
> @@ -3317,3 +3317,12 @@ cmpsxadd, 0x66e8, None, CpuCMPCCXADD|Cpu64, Modrm|Vex128|Space0F38|VexVVVV=1|Swa
> cmpzxadd, 0x66e4, None, CpuCMPCCXADD|Cpu64, Modrm|Vex128|Space0F38|VexVVVV=1|SwapSources|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Reg64, Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex }
>
> // CMPCCXADD instructions end.
> +
> +// RAOINT instructions.
Nit: Better RAO-INT, like in the title?
> +aadd, 0xf38fc, None, CpuRAOINT, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf,{ Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex}
> +aand, 0x660f38fc, None, CpuRAOINT, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf,{ Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex}
> +aor, 0xf20f38fc, None, CpuRAOINT, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf,{ Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex}
> +axor, 0xf30f38fc, None, CpuRAOINT, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf,{ Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex}
Why IgnoreSize? Instead I think you need CheckRegSize (assuming it does
enough for Intel syntax memory operands - please double check; if not
this will need fixing).
Jan
On 14.10.2022 16:38, Jan Beulich wrote:
> On 14.10.2022 11:12, Haochen Jiang wrote:
>> --- a/opcodes/i386-opc.tbl
>> +++ b/opcodes/i386-opc.tbl
>> @@ -3317,3 +3317,12 @@ cmpsxadd, 0x66e8, None, CpuCMPCCXADD|Cpu64, Modrm|Vex128|Space0F38|VexVVVV=1|Swa
>> cmpzxadd, 0x66e4, None, CpuCMPCCXADD|Cpu64, Modrm|Vex128|Space0F38|VexVVVV=1|SwapSources|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Reg64, Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex }
>>
>> // CMPCCXADD instructions end.
>> +
>> +// RAOINT instructions.
>
> Nit: Better RAO-INT, like in the title?
>
>> +aadd, 0xf38fc, None, CpuRAOINT, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf,{ Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex}
>> +aand, 0x660f38fc, None, CpuRAOINT, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf,{ Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex}
>> +aor, 0xf20f38fc, None, CpuRAOINT, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf,{ Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex}
>> +axor, 0xf30f38fc, None, CpuRAOINT, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf,{ Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex}
>
> Why IgnoreSize?
I take back this one question - for the time being IgnoreSize continues to
be needed for legacy-encoded insns to not have an operand size prefix emitted
in 16-bit code.
Jan
On Fri, Oct 14, 2022 at 2:15 AM Haochen Jiang <haochen.jiang@intel.com> wrote:
>
> From: Kong Lingling <lingling.kong@intel.com>
>
> gas/ChangeLog:
>
> * NEWS: Support Intel RAO-INT.
> * config/tc-i386.c: Add raoint.
> * doc/c-i386.texi: Document .raoint and noraoint.
> * testsuite/gas/i386/i386.exp: Run RAOINT tests.
> * testsuite/gas/i386/raoint-intel.d: New test.
> * testsuite/gas/i386/raoint.d: Ditto.
> * testsuite/gas/i386/raoint.s: Ditto.
> * testsuite/gas/i386/x86-64-raoint-intel.d: Ditto.
> * testsuite/gas/i386/x86-64-raoint.d: Ditto.
> * testsuite/gas/i386/x86-64-raoint.s: Ditto.
>
> opcodes/ChangeLog:
>
> * i386-dis.c (MOD_0F38FC): New.
> (PREFIX_0F38FC): Ditto.
> (mod_table): Add MOD_0F38FC.
> (prefix_table): Add PREFIX_0F38FC.
> * i386-gen.c: (cpu_flag_init): Add CPU_RAOINT_FLAGS and
> CPU_ANY_RAOINT_FLAGS.
> * i386-init.h: Regenerated.
> * i386-opc.h: (CpuRAOINT): New.
> (i386_cpu_flags): Add cpuraoint.
> * i386-opc.tbl: Add RAOINT instructions.
> * i386-tbl.h: Regenerated.
> ---
> gas/NEWS | 2 +
> gas/config/tc-i386.c | 3 +-
> gas/doc/c-i386.texi | 4 +-
> gas/testsuite/gas/i386/i386.exp | 4 +
> gas/testsuite/gas/i386/raoint-intel.d | 18 +
> gas/testsuite/gas/i386/raoint.d | 18 +
> gas/testsuite/gas/i386/raoint.s | 15 +
> gas/testsuite/gas/i386/x86-64-raoint-intel.d | 18 +
> gas/testsuite/gas/i386/x86-64-raoint.d | 18 +
> gas/testsuite/gas/i386/x86-64-raoint.s | 15 +
> opcodes/i386-dis.c | 16 +-
> opcodes/i386-gen.c | 5 +
> opcodes/i386-init.h | 514 +-
> opcodes/i386-opc.h | 5 +-
> opcodes/i386-opc.tbl | 9 +
> opcodes/i386-tbl.h | 7874 +++++++++---------
> 16 files changed, 4379 insertions(+), 4159 deletions(-)
> create mode 100644 gas/testsuite/gas/i386/raoint-intel.d
> create mode 100644 gas/testsuite/gas/i386/raoint.d
> create mode 100644 gas/testsuite/gas/i386/raoint.s
> create mode 100644 gas/testsuite/gas/i386/x86-64-raoint-intel.d
> create mode 100644 gas/testsuite/gas/i386/x86-64-raoint.d
> create mode 100644 gas/testsuite/gas/i386/x86-64-raoint.s
>
> diff --git a/gas/NEWS b/gas/NEWS
> index 9757209a9f..f352c5ab89 100644
> --- a/gas/NEWS
> +++ b/gas/NEWS
> @@ -1,5 +1,7 @@
> -*- text -*-
>
> +* Add support for Intel RAO-INT instructions.
> +
> * Add support for Intel CMPccXADD instructions.
>
> * Add support for Intel AVX-NE-CONVERT instructions.
> diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c
> index 7045e18cff..07d72d1af1 100644
> --- a/gas/config/tc-i386.c
> +++ b/gas/config/tc-i386.c
> @@ -1097,7 +1097,8 @@ static const arch_entry cpu_arch[] =
> SUBARCH (avx_ifma, AVX_IFMA, ANY_AVX_IFMA, false),
> SUBARCH (avx_vnni_int8, AVX_VNNI_INT8, ANY_AVX_VNNI_INT8, false),
> SUBARCH (avx_ne_convert, AVX_NE_CONVERT, ANY_AVX_NE_CONVERT, false),
> - SUBARCH (cmpccxadd, CMPCCXADD, ANY_CMPCCXADD, false)
> + SUBARCH (cmpccxadd, CMPCCXADD, ANY_CMPCCXADD, false),
> + SUBARCH (raoint, RAOINT, ANY_RAOINT, false),
> };
>
> #undef SUBARCH
> diff --git a/gas/doc/c-i386.texi b/gas/doc/c-i386.texi
> index 62202157b3..3832628e6e 100644
> --- a/gas/doc/c-i386.texi
> +++ b/gas/doc/c-i386.texi
> @@ -217,6 +217,7 @@ accept various extension mnemonics. For example,
> @code{avx_vnni_int8},
> @code{avx_ne_convert},
> @code{cmpccxadd},
> +@code{raoint},
> @code{noavx512f},
> @code{noavx512cd},
> @code{noavx512er},
> @@ -241,6 +242,7 @@ accept various extension mnemonics. For example,
> @code{noavx_vnni_int8},
> @code{noavx_ne_convert},
> @code{nocmpccxadd},
> +@code{noraoint},
> @code{noenqcmd},
> @code{noserialize},
> @code{notsxldtrk},
> @@ -1542,7 +1544,7 @@ supported on the CPU specified. The choices for @var{cpu_type} are:
> @item @samp{.tdx} @tab @samp{.avx_vnni} @tab @samp{.avx512_fp16}
> @item @samp{.clwb} @tab @samp{.rdpid} @tab @samp{.ptwrite} @tab @samp{.ibt}
> @item @samp{.avx_ifma} @tab @samp{.avx_vnni_int8} @tab @samp{.avx_ne_convert}
> -@item @samp{.cmpccxadd}
> +@item @samp{.cmpccxadd} @tab @samp{.raoint}
> @item @samp{.wbnoinvd} @tab @samp{.pconfig} @tab @samp{.waitpkg} @tab @samp{.cldemote}
> @item @samp{.shstk} @tab @samp{.gfni} @tab @samp{.vaes} @tab @samp{.vpclmulqdq}
> @item @samp{.movdiri} @tab @samp{.movdir64b} @tab @samp{.enqcmd} @tab @samp{.tsxldtrk}
> diff --git a/gas/testsuite/gas/i386/i386.exp b/gas/testsuite/gas/i386/i386.exp
> index fb2e2aa446..1eb0eabb6b 100644
> --- a/gas/testsuite/gas/i386/i386.exp
> +++ b/gas/testsuite/gas/i386/i386.exp
> @@ -486,6 +486,8 @@ if [gas_32_check] then {
> run_dump_test "avx-ne-convert"
> run_dump_test "avx-ne-convert-intel"
> run_list_test "cmpccxadd-inval"
> + run_dump_test "raoint"
> + run_dump_test "raoint-intel"
> run_list_test "sg"
> run_dump_test "clzero"
> run_dump_test "invlpgb"
> @@ -1162,6 +1164,8 @@ if [gas_64_check] then {
> run_dump_test "x86-64-avx-ne-convert-intel"
> run_dump_test "x86-64-cmpccxadd"
> run_dump_test "x86-64-cmpccxadd-intel"
> + run_dump_test "x86-64-raoint"
> + run_dump_test "x86-64-raoint-intel"
> run_dump_test "x86-64-clzero"
> run_dump_test "x86-64-mwaitx-bdver4"
> run_list_test "x86-64-mwaitx-reg"
> diff --git a/gas/testsuite/gas/i386/raoint-intel.d b/gas/testsuite/gas/i386/raoint-intel.d
> new file mode 100644
> index 0000000000..b50d423a5f
> --- /dev/null
> +++ b/gas/testsuite/gas/i386/raoint-intel.d
> @@ -0,0 +1,18 @@
> +#as:
> +#objdump: -dw -Mintel
> +#name: i386 RAOINT insns (Intel disassembly)
> +#source: raoint.s
> +
> +.*: +file format .*
> +
> +Disassembly of section \.text:
> +
> +0+ <_start>:
> +\s*[a-f0-9]+:\s*0f 38 fc 10\s+aadd DWORD PTR \[eax\],edx
> +\s*[a-f0-9]+:\s*66 0f 38 fc 10\s+aand DWORD PTR \[eax\],edx
> +\s*[a-f0-9]+:\s*f2 0f 38 fc 10\s+aor DWORD PTR \[eax\],edx
> +\s*[a-f0-9]+:\s*f3 0f 38 fc 10\s+axor DWORD PTR \[eax\],edx
> +\s*[a-f0-9]+:\s*0f 38 fc 10\s+aadd DWORD PTR \[eax\],edx
> +\s*[a-f0-9]+:\s*66 0f 38 fc 10\s+aand DWORD PTR \[eax\],edx
> +\s*[a-f0-9]+:\s*f2 0f 38 fc 10\s+aor DWORD PTR \[eax\],edx
> +\s*[a-f0-9]+:\s*f3 0f 38 fc 10\s+axor DWORD PTR \[eax\],edx
> diff --git a/gas/testsuite/gas/i386/raoint.d b/gas/testsuite/gas/i386/raoint.d
> new file mode 100644
> index 0000000000..2c310c5cc7
> --- /dev/null
> +++ b/gas/testsuite/gas/i386/raoint.d
> @@ -0,0 +1,18 @@
> +#as:
> +#objdump: -dw
> +#name: i386 RAOINT insns
> +#source: raoint.s
> +
> +.*: +file format .*
> +
> +Disassembly of section \.text:
> +
> +0+ <_start>:
> +\s*[a-f0-9]+:\s*0f 38 fc 10\s+aadd %edx,\(%eax\)
> +\s*[a-f0-9]+:\s*66 0f 38 fc 10\s+aand %edx,\(%eax\)
> +\s*[a-f0-9]+:\s*f2 0f 38 fc 10\s+aor %edx,\(%eax\)
> +\s*[a-f0-9]+:\s*f3 0f 38 fc 10\s+axor %edx,\(%eax\)
> +\s*[a-f0-9]+:\s*0f 38 fc 10\s+aadd %edx,\(%eax\)
> +\s*[a-f0-9]+:\s*66 0f 38 fc 10\s+aand %edx,\(%eax\)
> +\s*[a-f0-9]+:\s*f2 0f 38 fc 10\s+aor %edx,\(%eax\)
> +\s*[a-f0-9]+:\s*f3 0f 38 fc 10\s+axor %edx,\(%eax\)
> diff --git a/gas/testsuite/gas/i386/raoint.s b/gas/testsuite/gas/i386/raoint.s
> new file mode 100644
> index 0000000000..63398dfb82
> --- /dev/null
> +++ b/gas/testsuite/gas/i386/raoint.s
> @@ -0,0 +1,15 @@
> +# Check 32bit AVX-NE-CONVERT instructions
> +
> + .allow_index_reg
> + .text
> +_start:
> + aadd %edx, (%eax) #RAO-INT
> + aand %edx, (%eax) #RAO-INT
> + aor %edx, (%eax) #RAO-INT
> + axor %edx, (%eax) #RAO-INT
> +
> +.intel_syntax noprefix
> + aadd DWORD PTR [eax], %edx #RAO-INT
> + aand DWORD PTR [eax], %edx #RAO-INT
> + aor DWORD PTR [eax], %edx #RAO-INT
> + axor DWORD PTR [eax], %edx #RAO-INT
> diff --git a/gas/testsuite/gas/i386/x86-64-raoint-intel.d b/gas/testsuite/gas/i386/x86-64-raoint-intel.d
> new file mode 100644
> index 0000000000..d7de4849a2
> --- /dev/null
> +++ b/gas/testsuite/gas/i386/x86-64-raoint-intel.d
> @@ -0,0 +1,18 @@
> +#as:
> +#objdump: -dw -Mintel
> +#name: x86_64 RAOINT insns (Intel disassembly)
> +#source: x86-64-raoint.s
> +
> +.*: +file format .*
> +
> +Disassembly of section \.text:
> +
> +0+ <_start>:
> +\s*[a-f0-9]+:\s*48 0f 38 fc 10\s+aadd QWORD PTR \[rax\],rdx
> +\s*[a-f0-9]+:\s*66 48 0f 38 fc 10\s+aand QWORD PTR \[rax\],rdx
> +\s*[a-f0-9]+:\s*f2 48 0f 38 fc 10\s+aor QWORD PTR \[rax\],rdx
> +\s*[a-f0-9]+:\s*f3 48 0f 38 fc 10\s+axor QWORD PTR \[rax\],rdx
> +\s*[a-f0-9]+:\s*48 0f 38 fc 10\s+aadd QWORD PTR \[rax\],rdx
> +\s*[a-f0-9]+:\s*66 48 0f 38 fc 10\s+aand QWORD PTR \[rax\],rdx
> +\s*[a-f0-9]+:\s*f2 48 0f 38 fc 10\s+aor QWORD PTR \[rax\],rdx
> +\s*[a-f0-9]+:\s*f3 48 0f 38 fc 10\s+axor QWORD PTR \[rax\],rdx
> diff --git a/gas/testsuite/gas/i386/x86-64-raoint.d b/gas/testsuite/gas/i386/x86-64-raoint.d
> new file mode 100644
> index 0000000000..711fe48064
> --- /dev/null
> +++ b/gas/testsuite/gas/i386/x86-64-raoint.d
> @@ -0,0 +1,18 @@
> +#as:
> +#objdump: -dw
> +#name: x86_64 RAOINT insns
> +#source: x86-64-raoint.s
> +
> +.*: +file format .*
> +
> +Disassembly of section \.text:
> +
> +0+ <_start>:
> +\s*[a-f0-9]+:\s*48 0f 38 fc 10\s+aadd %rdx,\(%rax\)
> +\s*[a-f0-9]+:\s*66 48 0f 38 fc 10\s+aand %rdx,\(%rax\)
> +\s*[a-f0-9]+:\s*f2 48 0f 38 fc 10\s+aor %rdx,\(%rax\)
> +\s*[a-f0-9]+:\s*f3 48 0f 38 fc 10\s+axor %rdx,\(%rax\)
> +\s*[a-f0-9]+:\s*48 0f 38 fc 10\s+aadd %rdx,\(%rax\)
> +\s*[a-f0-9]+:\s*66 48 0f 38 fc 10\s+aand %rdx,\(%rax\)
> +\s*[a-f0-9]+:\s*f2 48 0f 38 fc 10\s+aor %rdx,\(%rax\)
> +\s*[a-f0-9]+:\s*f3 48 0f 38 fc 10\s+axor %rdx,\(%rax\)
> diff --git a/gas/testsuite/gas/i386/x86-64-raoint.s b/gas/testsuite/gas/i386/x86-64-raoint.s
> new file mode 100644
> index 0000000000..28590626ca
> --- /dev/null
> +++ b/gas/testsuite/gas/i386/x86-64-raoint.s
> @@ -0,0 +1,15 @@
> +# Check 64bit RAOINT instructions
> +
> + .allow_index_reg
> + .text
> +_start:
> + aadd %rdx, (%rax) #RAO-INT
> + aand %rdx, (%rax) #RAO-INT
> + aor %rdx, (%rax) #RAO-INT
> + axor %rdx, (%rax) #RAO-INT
> +
> +.intel_syntax noprefix
> + aadd QWORD PTR [rax], %rdx #RAO-INT
> + aand QWORD PTR [rax], %rdx #RAO-INT
> + aor QWORD PTR [rax], %rdx #RAO-INT
> + axor QWORD PTR [rax], %rdx #RAO-INT
> diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c
> index 37bbbd3815..60a334bbd6 100644
> --- a/opcodes/i386-dis.c
> +++ b/opcodes/i386-dis.c
> @@ -887,6 +887,7 @@ enum
> MOD_0F38F9,
> MOD_0F38FA_PREFIX_1,
> MOD_0F38FB_PREFIX_1,
> + MOD_0F38FC,
> MOD_0F3A0F_PREFIX_1,
>
> MOD_VEX_0F12_PREFIX_0,
> @@ -1086,6 +1087,7 @@ enum
> PREFIX_0F38F8,
> PREFIX_0F38FA,
> PREFIX_0F38FB,
> + PREFIX_0F38FC,
> PREFIX_0F3A0F,
> PREFIX_VEX_0F10,
> PREFIX_VEX_0F11,
> @@ -3598,6 +3600,14 @@ static const struct dis386 prefix_table[][4] = {
> { MOD_TABLE (MOD_0F38FB_PREFIX_1) },
> },
>
> + /* PREFIX_0F38FC */
> + {
> + { "aadd", { Edq, Gdq }, PREFIX_OPCODE },
> + { "axor", { Edq, Gdq }, PREFIX_OPCODE },
> + { "aand", { Edq, Gdq }, PREFIX_OPCODE },
> + { "aor", { Edq, Gdq }, PREFIX_OPCODE },
-Msuffix doesn't print suffixes.
> + },
> +
> /* PREFIX_0F3A0F */
> {
> { Bad_Opcode },
> @@ -4802,7 +4812,7 @@ static const struct dis386 three_byte_table[][256] = {
> { MOD_TABLE (MOD_0F38F9) },
> { PREFIX_TABLE (PREFIX_0F38FA) },
> { PREFIX_TABLE (PREFIX_0F38FB) },
> - { Bad_Opcode },
> + { MOD_TABLE (MOD_0F38FC) },
> { Bad_Opcode },
> { Bad_Opcode },
> { Bad_Opcode },
> @@ -8374,6 +8384,10 @@ static const struct dis386 mod_table[][2] = {
> { Bad_Opcode },
> { "encodekey256", { Gd, Ed }, 0 },
> },
> + {
> + /* MOD_0F38FC */
> + { PREFIX_TABLE (PREFIX_0F38FC) },
> + },
> {
> /* MOD_0F3A0F_PREFIX_1 */
> { Bad_Opcode },
> diff --git a/opcodes/i386-gen.c b/opcodes/i386-gen.c
> index 96d8d2ceb8..3a7511a242 100644
> --- a/opcodes/i386-gen.c
> +++ b/opcodes/i386-gen.c
> @@ -253,6 +253,8 @@ static initializer cpu_flag_init[] =
> "CPU_AVX2_FLAGS|CpuAVX_NE_CONVERT" },
> { "CPU_CMPCCXADD_FLAGS",
> "CpuCMPCCXADD" },
> + { "CPU_RAOINT_FLAGS",
> + "CpuRAOINT" },
> { "CPU_IAMCU_FLAGS",
> "Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuIAMCU" },
> { "CPU_ADX_FLAGS",
> @@ -455,6 +457,8 @@ static initializer cpu_flag_init[] =
> "CpuAVX_NE_CONVERT" },
> { "CPU_ANY_CMPCCXADD_FLAGS",
> "CpuCMPCCXADD" },
> + { "CPU_ANY_RAOINT_FLAGS",
> + "CpuRAOINT" },
> };
>
> static initializer operand_type_init[] =
> @@ -660,6 +664,7 @@ static bitfield cpu_flags[] =
> BITFIELD (CpuAVX_VNNI_INT8),
> BITFIELD (CpuAVX_NE_CONVERT),
> BITFIELD (CpuCMPCCXADD),
> + BITFIELD (CpuRAOINT),
> BITFIELD (CpuMWAITX),
> BITFIELD (CpuCLZERO),
> BITFIELD (CpuOSPKE),
> diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h
> index 052c59b162..cb6c372203 100644
> --- a/opcodes/i386-opc.h
> +++ b/opcodes/i386-opc.h
> @@ -217,6 +217,8 @@ enum
> CpuAVX_NE_CONVERT,
> /* Intel CMPccXADD instructions support required. */
> CpuCMPCCXADD,
> + /* Intel RAO INT Instructions support required. */
> + CpuRAOINT,
> /* mwaitx instruction required */
> CpuMWAITX,
> /* Clzero instruction required */
> @@ -400,6 +402,7 @@ typedef union i386_cpu_flags
> unsigned int cpuavx_vnni_int8:1;
> unsigned int cpuavx_ne_convert:1;
> unsigned int cpucmpccxadd:1;
> + unsigned int cpuraoint:1;
> unsigned int cpumwaitx:1;
> unsigned int cpuclzero:1;
> unsigned int cpuospke:1;
> @@ -436,7 +439,7 @@ typedef union i386_cpu_flags
> unsigned int cpu64:1;
> unsigned int cpuno64:1;
> #ifdef CpuUnused
> - // unsigned int unused:(CpuNumOfBits - CpuUnused);
> + unsigned int unused:(CpuNumOfBits - CpuUnused);
> #endif
> } bitfield;
> unsigned int array[CpuNumOfUints];
> diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl
> index 2b704708a4..4affd056b2 100644
> --- a/opcodes/i386-opc.tbl
> +++ b/opcodes/i386-opc.tbl
> @@ -3317,3 +3317,12 @@ cmpsxadd, 0x66e8, None, CpuCMPCCXADD|Cpu64, Modrm|Vex128|Space0F38|VexVVVV=1|Swa
> cmpzxadd, 0x66e4, None, CpuCMPCCXADD|Cpu64, Modrm|Vex128|Space0F38|VexVVVV=1|SwapSources|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Reg64, Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex }
>
> // CMPCCXADD instructions end.
> +
> +// RAOINT instructions.
> +
> +aadd, 0xf38fc, None, CpuRAOINT, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf,{ Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex}
> +aand, 0x660f38fc, None, CpuRAOINT, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf,{ Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex}
> +aor, 0xf20f38fc, None, CpuRAOINT, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf,{ Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex}
> +axor, 0xf30f38fc, None, CpuRAOINT, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf,{ Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex}
l and q suffixes are allowed. Personally, I think l and q suffixes
should be used
only when they are needed in some forms.
> +// RAOINT instructions end.
> --
> 2.18.2
>
On 18.10.2022 01:23, H.J. Lu wrote:
> On Fri, Oct 14, 2022 at 2:15 AM Haochen Jiang <haochen.jiang@intel.com> wrote:
>> --- a/opcodes/i386-opc.tbl
>> +++ b/opcodes/i386-opc.tbl
>> @@ -3317,3 +3317,12 @@ cmpsxadd, 0x66e8, None, CpuCMPCCXADD|Cpu64, Modrm|Vex128|Space0F38|VexVVVV=1|Swa
>> cmpzxadd, 0x66e4, None, CpuCMPCCXADD|Cpu64, Modrm|Vex128|Space0F38|VexVVVV=1|SwapSources|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Reg64, Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex }
>>
>> // CMPCCXADD instructions end.
>> +
>> +// RAOINT instructions.
>> +
>> +aadd, 0xf38fc, None, CpuRAOINT, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf,{ Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex}
>> +aand, 0x660f38fc, None, CpuRAOINT, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf,{ Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex}
>> +aor, 0xf20f38fc, None, CpuRAOINT, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf,{ Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex}
>> +axor, 0xf30f38fc, None, CpuRAOINT, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf,{ Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex}
>
> l and q suffixes are allowed. Personally, I think l and q suffixes
> should be used
> only when they are needed in some forms.
As said elsewhere (repeating here mainly for the authors' sake): The
spirit of the only AT&T doc I'm aware of looks to be to mandate use of
suffixes wherever sized memory operands are involved (non-sized ones
would e.g. be those used by PREFETCH*). Plus disallowing their use
(also relevant for CMPccXADD) introduces inconsistencies.
Jan
> -----Original Message-----
> From: Jan Beulich <jbeulich@suse.com>
> Sent: Friday, October 14, 2022 10:38 PM
> To: Jiang, Haochen <haochen.jiang@intel.com>
> Cc: hjl.tools@gmail.com; Kong, Lingling <lingling.kong@intel.com>;
> binutils@sourceware.org
> Subject: Re: [PATCH 06/10] Support Intel RAO-INT
>
> On 14.10.2022 11:12, Haochen Jiang wrote:
> > --- a/gas/config/tc-i386.c
> > +++ b/gas/config/tc-i386.c
> > @@ -1097,7 +1097,8 @@ static const arch_entry cpu_arch[] =
> > SUBARCH (avx_ifma, AVX_IFMA, ANY_AVX_IFMA, false),
> > SUBARCH (avx_vnni_int8, AVX_VNNI_INT8, ANY_AVX_VNNI_INT8, false),
> > SUBARCH (avx_ne_convert, AVX_NE_CONVERT, ANY_AVX_NE_CONVERT,
> > false),
> > - SUBARCH (cmpccxadd, CMPCCXADD, ANY_CMPCCXADD, false)
> > + SUBARCH (cmpccxadd, CMPCCXADD, ANY_CMPCCXADD, false), SUBARCH
> > + (raoint, RAOINT, ANY_RAOINT, false),
>
> As for the earlier patch - likely no need for ANY_RAOINT. Also please have the
> earlier patch add the comma so you don't need to touch that line again here
> (helping at least "git blame").
Done and fixed for CMPccXADD patch.
>
> > --- a/opcodes/i386-dis.c
> > +++ b/opcodes/i386-dis.c
> > @@ -887,6 +887,7 @@ enum
> > MOD_0F38F9,
> > MOD_0F38FA_PREFIX_1,
> > MOD_0F38FB_PREFIX_1,
> > + MOD_0F38FC,
> > MOD_0F3A0F_PREFIX_1,
> >
> > MOD_VEX_0F12_PREFIX_0,
> > @@ -1086,6 +1087,7 @@ enum
> > PREFIX_0F38F8,
> > PREFIX_0F38FA,
> > PREFIX_0F38FB,
> > + PREFIX_0F38FC,
>
> PREFIX_0F38FC_M_0 please (see comment on an earlier patch). However, like in
> the earlier patch - if you used Mdq below, you could avoid going through
> mod_table[] altogether.
Removed pass modrm table since Edq seems also judges modrm.
>
> > @@ -3598,6 +3600,14 @@ static const struct dis386 prefix_table[][4] = {
> > { MOD_TABLE (MOD_0F38FB_PREFIX_1) },
> > },
> >
> > + /* PREFIX_0F38FC */
> > + {
> > + { "aadd", { Edq, Gdq }, PREFIX_OPCODE },
> > + { "axor", { Edq, Gdq }, PREFIX_OPCODE },
> > + { "aand", { Edq, Gdq }, PREFIX_OPCODE },
> > + { "aor", { Edq, Gdq }, PREFIX_OPCODE },
> > + },
>
> Once having gone through prefix_table[], PREFIX_OPCODE (and
> PREFIX_DATA) are meaningless iirc and should hence be omitted.
>
Fixed.
> > --- a/opcodes/i386-opc.tbl
> > +++ b/opcodes/i386-opc.tbl
> > @@ -3317,3 +3317,12 @@ cmpsxadd, 0x66e8, None, CpuCMPCCXADD|Cpu64,
> > Modrm|Vex128|Space0F38|VexVVVV=1|Swa
> > cmpzxadd, 0x66e4, None, CpuCMPCCXADD|Cpu64,
> >
> Modrm|Vex128|Space0F38|VexVVVV=1|SwapSources|CheckRegSize|No_bSuf|
> No_w
> > Suf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Reg64, Reg32|Reg64,
> > Dword|Qword|Unspecified|BaseIndex }
> >
> > // CMPCCXADD instructions end.
> > +
> > +// RAOINT instructions.
>
> Nit: Better RAO-INT, like in the title?
Done.
>
> > +aadd, 0xf38fc, None, CpuRAOINT,
> > +Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf,{ Reg32|Reg64,
> > +Dword|Qword|Unspecified|BaseIndex}
> > +aand, 0x660f38fc, None, CpuRAOINT,
> > +Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf,{ Reg32|Reg64,
> > +Dword|Qword|Unspecified|BaseIndex}
> > +aor, 0xf20f38fc, None, CpuRAOINT,
> > +Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf,{ Reg32|Reg64,
> > +Dword|Qword|Unspecified|BaseIndex}
> > +axor, 0xf30f38fc, None, CpuRAOINT,
> > +Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf,{ Reg32|Reg64,
> > +Dword|Qword|Unspecified|BaseIndex}
>
> Why IgnoreSize? Instead I think you need CheckRegSize (assuming it does
> enough for Intel syntax memory operands - please double check; if not this will
> need fixing).
>
For table, we aligned with CMPccXADD and added No_lSuf and No_qSuf since
the suffixes are not required.
In future, if suffixes are not required, we will add all the No_xxSuf.
BTW, can we write a macro named No_allSuf including all of them to shorten
the line?
Haochen
> Jan
On Sun, Oct 23, 2022 at 8:12 PM Jiang, Haochen <haochen.jiang@intel.com> wrote:
>
> > -----Original Message-----
> > From: Jan Beulich <jbeulich@suse.com>
> > Sent: Friday, October 14, 2022 10:38 PM
> > To: Jiang, Haochen <haochen.jiang@intel.com>
> > Cc: hjl.tools@gmail.com; Kong, Lingling <lingling.kong@intel.com>;
> > binutils@sourceware.org
> > Subject: Re: [PATCH 06/10] Support Intel RAO-INT
> >
> > On 14.10.2022 11:12, Haochen Jiang wrote:
> > > --- a/gas/config/tc-i386.c
> > > +++ b/gas/config/tc-i386.c
> > > @@ -1097,7 +1097,8 @@ static const arch_entry cpu_arch[] =
> > > SUBARCH (avx_ifma, AVX_IFMA, ANY_AVX_IFMA, false),
> > > SUBARCH (avx_vnni_int8, AVX_VNNI_INT8, ANY_AVX_VNNI_INT8, false),
> > > SUBARCH (avx_ne_convert, AVX_NE_CONVERT, ANY_AVX_NE_CONVERT,
> > > false),
> > > - SUBARCH (cmpccxadd, CMPCCXADD, ANY_CMPCCXADD, false)
> > > + SUBARCH (cmpccxadd, CMPCCXADD, ANY_CMPCCXADD, false), SUBARCH
> > > + (raoint, RAOINT, ANY_RAOINT, false),
> >
> > As for the earlier patch - likely no need for ANY_RAOINT. Also please have the
> > earlier patch add the comma so you don't need to touch that line again here
> > (helping at least "git blame").
>
> Done and fixed for CMPccXADD patch.
Please also remove CPU_ANY_RAO_INT_FLAGS since it isn't used.
>
> >
> > > --- a/opcodes/i386-dis.c
> > > +++ b/opcodes/i386-dis.c
> > > @@ -887,6 +887,7 @@ enum
> > > MOD_0F38F9,
> > > MOD_0F38FA_PREFIX_1,
> > > MOD_0F38FB_PREFIX_1,
> > > + MOD_0F38FC,
> > > MOD_0F3A0F_PREFIX_1,
> > >
> > > MOD_VEX_0F12_PREFIX_0,
> > > @@ -1086,6 +1087,7 @@ enum
> > > PREFIX_0F38F8,
> > > PREFIX_0F38FA,
> > > PREFIX_0F38FB,
> > > + PREFIX_0F38FC,
> >
> > PREFIX_0F38FC_M_0 please (see comment on an earlier patch). However, like in
> > the earlier patch - if you used Mdq below, you could avoid going through
> > mod_table[] altogether.
>
> Removed pass modrm table since Edq seems also judges modrm.
>
> >
> > > @@ -3598,6 +3600,14 @@ static const struct dis386 prefix_table[][4] = {
> > > { MOD_TABLE (MOD_0F38FB_PREFIX_1) },
> > > },
> > >
> > > + /* PREFIX_0F38FC */
> > > + {
> > > + { "aadd", { Edq, Gdq }, PREFIX_OPCODE },
> > > + { "axor", { Edq, Gdq }, PREFIX_OPCODE },
> > > + { "aand", { Edq, Gdq }, PREFIX_OPCODE },
> > > + { "aor", { Edq, Gdq }, PREFIX_OPCODE },
> > > + },
> >
> > Once having gone through prefix_table[], PREFIX_OPCODE (and
> > PREFIX_DATA) are meaningless iirc and should hence be omitted.
> >
>
> Fixed.
>
> > > --- a/opcodes/i386-opc.tbl
> > > +++ b/opcodes/i386-opc.tbl
> > > @@ -3317,3 +3317,12 @@ cmpsxadd, 0x66e8, None, CpuCMPCCXADD|Cpu64,
> > > Modrm|Vex128|Space0F38|VexVVVV=1|Swa
> > > cmpzxadd, 0x66e4, None, CpuCMPCCXADD|Cpu64,
> > >
> > Modrm|Vex128|Space0F38|VexVVVV=1|SwapSources|CheckRegSize|No_bSuf|
> > No_w
> > > Suf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Reg64, Reg32|Reg64,
> > > Dword|Qword|Unspecified|BaseIndex }
> > >
> > > // CMPCCXADD instructions end.
> > > +
> > > +// RAOINT instructions.
> >
> > Nit: Better RAO-INT, like in the title?
>
> Done.
>
> >
> > > +aadd, 0xf38fc, None, CpuRAOINT,
> > > +Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf,{ Reg32|Reg64,
> > > +Dword|Qword|Unspecified|BaseIndex}
> > > +aand, 0x660f38fc, None, CpuRAOINT,
> > > +Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf,{ Reg32|Reg64,
> > > +Dword|Qword|Unspecified|BaseIndex}
> > > +aor, 0xf20f38fc, None, CpuRAOINT,
> > > +Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf,{ Reg32|Reg64,
> > > +Dword|Qword|Unspecified|BaseIndex}
> > > +axor, 0xf30f38fc, None, CpuRAOINT,
> > > +Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf,{ Reg32|Reg64,
> > > +Dword|Qword|Unspecified|BaseIndex}
> >
> > Why IgnoreSize? Instead I think you need CheckRegSize (assuming it does
> > enough for Intel syntax memory operands - please double check; if not this will
> > need fixing).
> >
>
> For table, we aligned with CMPccXADD and added No_lSuf and No_qSuf since
> the suffixes are not required.
>
> In future, if suffixes are not required, we will add all the No_xxSuf.
>
> BTW, can we write a macro named No_allSuf including all of them to shorten
> the line?
>
> Haochen
> > Jan
On 24.10.2022 07:56, Jiang, Haochen wrote:
>> -----Original Message-----
>> From: Jan Beulich <jbeulich@suse.com>
>> Sent: Friday, October 14, 2022 10:38 PM
>>
>> On 14.10.2022 11:12, Haochen Jiang wrote:
>>> --- a/opcodes/i386-dis.c
>>> +++ b/opcodes/i386-dis.c
>>> @@ -887,6 +887,7 @@ enum
>>> MOD_0F38F9,
>>> MOD_0F38FA_PREFIX_1,
>>> MOD_0F38FB_PREFIX_1,
>>> + MOD_0F38FC,
>>> MOD_0F3A0F_PREFIX_1,
>>>
>>> MOD_VEX_0F12_PREFIX_0,
>>> @@ -1086,6 +1087,7 @@ enum
>>> PREFIX_0F38F8,
>>> PREFIX_0F38FA,
>>> PREFIX_0F38FB,
>>> + PREFIX_0F38FC,
>>
>> PREFIX_0F38FC_M_0 please (see comment on an earlier patch). However, like in
>> the earlier patch - if you used Mdq below, you could avoid going through
>> mod_table[] altogether.
>
> Removed pass modrm table since Edq seems also judges modrm.
Edq? That one allows for register operands as well. I did suggest to use
Mdq (iirc introduced by an earlier patch).
>>> --- a/opcodes/i386-opc.tbl
>>> +++ b/opcodes/i386-opc.tbl
>>> @@ -3317,3 +3317,12 @@ cmpsxadd, 0x66e8, None, CpuCMPCCXADD|Cpu64,
>>> Modrm|Vex128|Space0F38|VexVVVV=1|Swa
>>> cmpzxadd, 0x66e4, None, CpuCMPCCXADD|Cpu64,
>>>
>> Modrm|Vex128|Space0F38|VexVVVV=1|SwapSources|CheckRegSize|No_bSuf|
>> No_w
>>> Suf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Reg64, Reg32|Reg64,
>>> Dword|Qword|Unspecified|BaseIndex }
>>>
>>> // CMPCCXADD instructions end.
>>> +
>>> +// RAOINT instructions.
>>
>> Nit: Better RAO-INT, like in the title?
>
> Done.
>
>>
>>> +aadd, 0xf38fc, None, CpuRAOINT,
>>> +Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf,{ Reg32|Reg64,
>>> +Dword|Qword|Unspecified|BaseIndex}
>>> +aand, 0x660f38fc, None, CpuRAOINT,
>>> +Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf,{ Reg32|Reg64,
>>> +Dword|Qword|Unspecified|BaseIndex}
>>> +aor, 0xf20f38fc, None, CpuRAOINT,
>>> +Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf,{ Reg32|Reg64,
>>> +Dword|Qword|Unspecified|BaseIndex}
>>> +axor, 0xf30f38fc, None, CpuRAOINT,
>>> +Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf,{ Reg32|Reg64,
>>> +Dword|Qword|Unspecified|BaseIndex}
>>
>> Why IgnoreSize? Instead I think you need CheckRegSize (assuming it does
>> enough for Intel syntax memory operands - please double check; if not this will
>> need fixing).
>>
>
> For table, we aligned with CMPccXADD and added No_lSuf and No_qSuf since
> the suffixes are not required.
Which, as said, I consider wrong both here and there.
There's also still no CheckRegSize here.
> In future, if suffixes are not required, we will add all the No_xxSuf.
>
> BTW, can we write a macro named No_allSuf including all of them to shorten
> the line?
We probably could (yet then perhaps named No_Suf or NoSuf), but I have
other patches pending to help this at least some. In the long run we
really want to turn things around and specify which suffixes are
permitted, as the majority of insns doesn't permit any.
Jan
> -----Original Message-----
> From: Jan Beulich <jbeulich@suse.com>
> Sent: Tuesday, October 25, 2022 3:01 PM
> To: Jiang, Haochen <haochen.jiang@intel.com>
> Cc: hjl.tools@gmail.com; Kong, Lingling <lingling.kong@intel.com>;
> binutils@sourceware.org
> Subject: Re: [PATCH 06/10] Support Intel RAO-INT
>
> On 24.10.2022 07:56, Jiang, Haochen wrote:
> >> -----Original Message-----
> >> From: Jan Beulich <jbeulich@suse.com>
> >> Sent: Friday, October 14, 2022 10:38 PM
> >>
> >> On 14.10.2022 11:12, Haochen Jiang wrote:
> >>> --- a/opcodes/i386-dis.c
> >>> +++ b/opcodes/i386-dis.c
> >>> @@ -887,6 +887,7 @@ enum
> >>> MOD_0F38F9,
> >>> MOD_0F38FA_PREFIX_1,
> >>> MOD_0F38FB_PREFIX_1,
> >>> + MOD_0F38FC,
> >>> MOD_0F3A0F_PREFIX_1,
> >>>
> >>> MOD_VEX_0F12_PREFIX_0,
> >>> @@ -1086,6 +1087,7 @@ enum
> >>> PREFIX_0F38F8,
> >>> PREFIX_0F38FA,
> >>> PREFIX_0F38FB,
> >>> + PREFIX_0F38FC,
> >>
> >> PREFIX_0F38FC_M_0 please (see comment on an earlier patch). However,
> like in
> >> the earlier patch - if you used Mdq below, you could avoid going through
> >> mod_table[] altogether.
> >
> > Removed pass modrm table since Edq seems also judges modrm.
>
> Edq? That one allows for register operands as well. I did suggest to use
> Mdq (iirc introduced by an earlier patch).
It should be Mdq here, will change that.
> >>> +aadd, 0xf38fc, None, CpuRAOINT,
> >>>
> +Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf,{ Reg32|Reg64,
> >>> +Dword|Qword|Unspecified|BaseIndex}
> >>> +aand, 0x660f38fc, None, CpuRAOINT,
> >>>
> +Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf,{ Reg32|Reg64,
> >>> +Dword|Qword|Unspecified|BaseIndex}
> >>> +aor, 0xf20f38fc, None, CpuRAOINT,
> >>>
> +Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf,{ Reg32|Reg64,
> >>> +Dword|Qword|Unspecified|BaseIndex}
> >>> +axor, 0xf30f38fc, None, CpuRAOINT,
> >>>
> +Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf,{ Reg32|Reg64,
> >>> +Dword|Qword|Unspecified|BaseIndex}
> >>
> >> Why IgnoreSize? Instead I think you need CheckRegSize (assuming it does
> >> enough for Intel syntax memory operands - please double check; if not
> this will
> >> need fixing).
> >>
> >
> > For table, we aligned with CMPccXADD and added No_lSuf and No_qSuf
> since
> > the suffixes are not required.
>
> Which, as said, I consider wrong both here and there.
I still agree with H.J.. Also I suppose the previous usage of suffixes are quite
messy and we should not stick on the confusing code.
Keeping consistent with SPEC from now on to avoid confusion on that might
be a better solution for future.
>
> There's also still no CheckRegSize here.
I suppose you take that question back before. But I realized that there are two
questions there. I checked testcases and they might not be sufficient. Let me
add some testcases with author @Kong, Lingling to see whether CheckRegSize
might be needed here. My answer now is yes but might change.
Haochen
On 26.10.2022 07:16, Jiang, Haochen wrote:
>> -----Original Message-----
>> From: Jan Beulich <jbeulich@suse.com>
>> Sent: Tuesday, October 25, 2022 3:01 PM
>>
>> On 24.10.2022 07:56, Jiang, Haochen wrote:
>>>> -----Original Message-----
>>>> From: Jan Beulich <jbeulich@suse.com>
>>>> Sent: Friday, October 14, 2022 10:38 PM
>>>>
>>>> On 14.10.2022 11:12, Haochen Jiang wrote:
>>>>> +aadd, 0xf38fc, None, CpuRAOINT,
>>>>>
>> +Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf,{ Reg32|Reg64,
>>>>> +Dword|Qword|Unspecified|BaseIndex}
>>>>> +aand, 0x660f38fc, None, CpuRAOINT,
>>>>>
>> +Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf,{ Reg32|Reg64,
>>>>> +Dword|Qword|Unspecified|BaseIndex}
>>>>> +aor, 0xf20f38fc, None, CpuRAOINT,
>>>>>
>> +Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf,{ Reg32|Reg64,
>>>>> +Dword|Qword|Unspecified|BaseIndex}
>>>>> +axor, 0xf30f38fc, None, CpuRAOINT,
>>>>>
>> +Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf,{ Reg32|Reg64,
>>>>> +Dword|Qword|Unspecified|BaseIndex}
>>>>
>>>> Why IgnoreSize? Instead I think you need CheckRegSize (assuming it does
>>>> enough for Intel syntax memory operands - please double check; if not
>> this will
>>>> need fixing).
>>>>
>>>
>>> For table, we aligned with CMPccXADD and added No_lSuf and No_qSuf
>> since
>>> the suffixes are not required.
>>
>> Which, as said, I consider wrong both here and there.
>
> I still agree with H.J.. Also I suppose the previous usage of suffixes are quite
> messy and we should not stick on the confusing code.
>
> Keeping consistent with SPEC from now on to avoid confusion on that might
> be a better solution for future.
Same question to you then: Which spec? As said in reply to H.J., the only
spec I'm aware of suggests prefixes ought to be used _whenever_ there's a
sized memory operand [1]. If we want to deal with the present "mess", I
think we ought to simply allow suffixes consistently. Please point out any
other messy aspects beyond that.
Jan
[1] They further say "long" is implied when there's no suffix, which imo
gas validly doesn't follow in cases where a further register operand
indicates otherwise.
> -----Original Message-----
> From: Jan Beulich <jbeulich@suse.com>
> Sent: Wednesday, October 26, 2022 4:57 PM
> To: Jiang, Haochen <haochen.jiang@intel.com>
> Cc: hjl.tools@gmail.com; binutils@sourceware.org; Kong, Lingling
> <lingling.kong@intel.com>
> Subject: Re: [PATCH 06/10] Support Intel RAO-INT
>
> On 26.10.2022 07:16, Jiang, Haochen wrote:
> >> -----Original Message-----
> >> From: Jan Beulich <jbeulich@suse.com>
> >> Sent: Tuesday, October 25, 2022 3:01 PM
> >>
> >> On 24.10.2022 07:56, Jiang, Haochen wrote:
> >>>> -----Original Message-----
> >>>> From: Jan Beulich <jbeulich@suse.com>
> >>>> Sent: Friday, October 14, 2022 10:38 PM
> >>>>
> >>>> On 14.10.2022 11:12, Haochen Jiang wrote:
> >>>>> +aadd, 0xf38fc, None, CpuRAOINT,
> >>>>>
> >>
> +Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf,{ Reg32|Reg64,
> >>>>> +Dword|Qword|Unspecified|BaseIndex}
> >>>>> +aand, 0x660f38fc, None, CpuRAOINT,
> >>>>>
> >>
> +Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf,{ Reg32|Reg64,
> >>>>> +Dword|Qword|Unspecified|BaseIndex}
> >>>>> +aor, 0xf20f38fc, None, CpuRAOINT,
> >>>>>
> >>
> +Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf,{ Reg32|Reg64,
> >>>>> +Dword|Qword|Unspecified|BaseIndex}
> >>>>> +axor, 0xf30f38fc, None, CpuRAOINT,
> >>>>>
> >>
> +Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf,{ Reg32|Reg64,
> >>>>> +Dword|Qword|Unspecified|BaseIndex}
> >>>>
> >>>> Why IgnoreSize? Instead I think you need CheckRegSize (assuming it
> does
> >>>> enough for Intel syntax memory operands - please double check; if not
> >> this will
> >>>> need fixing).
> >>>>
> >>>
> >>> For table, we aligned with CMPccXADD and added No_lSuf and No_qSuf
> >> since
> >>> the suffixes are not required.
> >>
> >> Which, as said, I consider wrong both here and there.
> >
> > I still agree with H.J.. Also I suppose the previous usage of suffixes are quite
> > messy and we should not stick on the confusing code.
> >
> > Keeping consistent with SPEC from now on to avoid confusion on that
> might
> > be a better solution for future.
>
> Same question to you then: Which spec? As said in reply to H.J., the only
> spec I'm aware of suggests prefixes ought to be used _whenever_ there's a
> sized memory operand [1]. If we want to deal with the present "mess", I
> think we ought to simply allow suffixes consistently. Please point out any
> other messy aspects beyond that.
The default behavior for current ISA is when there is no suffix required, it won't
mention that.
Haochen
>
> Jan
>
> [1] They further say "long" is implied when there's no suffix, which imo
> gas validly doesn't follow in cases where a further register operand
> indicates otherwise.
On 27.10.2022 05:50, Jiang, Haochen wrote:
>> -----Original Message-----
>> From: Jan Beulich <jbeulich@suse.com>
>> Sent: Wednesday, October 26, 2022 4:57 PM
>> To: Jiang, Haochen <haochen.jiang@intel.com>
>> Cc: hjl.tools@gmail.com; binutils@sourceware.org; Kong, Lingling
>> <lingling.kong@intel.com>
>> Subject: Re: [PATCH 06/10] Support Intel RAO-INT
>>
>> On 26.10.2022 07:16, Jiang, Haochen wrote:
>>>> -----Original Message-----
>>>> From: Jan Beulich <jbeulich@suse.com>
>>>> Sent: Tuesday, October 25, 2022 3:01 PM
>>>>
>>>> On 24.10.2022 07:56, Jiang, Haochen wrote:
>>>>>> -----Original Message-----
>>>>>> From: Jan Beulich <jbeulich@suse.com>
>>>>>> Sent: Friday, October 14, 2022 10:38 PM
>>>>>>
>>>>>> On 14.10.2022 11:12, Haochen Jiang wrote:
>>>>>>> +aadd, 0xf38fc, None, CpuRAOINT,
>>>>>>>
>>>>
>> +Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf,{ Reg32|Reg64,
>>>>>>> +Dword|Qword|Unspecified|BaseIndex}
>>>>>>> +aand, 0x660f38fc, None, CpuRAOINT,
>>>>>>>
>>>>
>> +Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf,{ Reg32|Reg64,
>>>>>>> +Dword|Qword|Unspecified|BaseIndex}
>>>>>>> +aor, 0xf20f38fc, None, CpuRAOINT,
>>>>>>>
>>>>
>> +Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf,{ Reg32|Reg64,
>>>>>>> +Dword|Qword|Unspecified|BaseIndex}
>>>>>>> +axor, 0xf30f38fc, None, CpuRAOINT,
>>>>>>>
>>>>
>> +Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf,{ Reg32|Reg64,
>>>>>>> +Dword|Qword|Unspecified|BaseIndex}
>>>>>>
>>>>>> Why IgnoreSize? Instead I think you need CheckRegSize (assuming it
>> does
>>>>>> enough for Intel syntax memory operands - please double check; if not
>>>> this will
>>>>>> need fixing).
>>>>>>
>>>>>
>>>>> For table, we aligned with CMPccXADD and added No_lSuf and No_qSuf
>>>> since
>>>>> the suffixes are not required.
>>>>
>>>> Which, as said, I consider wrong both here and there.
>>>
>>> I still agree with H.J.. Also I suppose the previous usage of suffixes are quite
>>> messy and we should not stick on the confusing code.
>>>
>>> Keeping consistent with SPEC from now on to avoid confusion on that
>> might
>>> be a better solution for future.
>>
>> Same question to you then: Which spec? As said in reply to H.J., the only
>> spec I'm aware of suggests prefixes ought to be used _whenever_ there's a
>> sized memory operand [1]. If we want to deal with the present "mess", I
>> think we ought to simply allow suffixes consistently. Please point out any
>> other messy aspects beyond that.
>
> The default behavior for current ISA is when there is no suffix required, it won't
> mention that.
What is "current ISA" here? Looking over the whole set of insns which we
support, it's the vast majority which behaves differently from what you
say. It's been several times that I mentioned that we would better
eliminate this inconsistency.
Jan
On Wed, Oct 26, 2022 at 11:39 PM Jan Beulich <jbeulich@suse.com> wrote:
>
> On 27.10.2022 05:50, Jiang, Haochen wrote:
> >> -----Original Message-----
> >> From: Jan Beulich <jbeulich@suse.com>
> >> Sent: Wednesday, October 26, 2022 4:57 PM
> >> To: Jiang, Haochen <haochen.jiang@intel.com>
> >> Cc: hjl.tools@gmail.com; binutils@sourceware.org; Kong, Lingling
> >> <lingling.kong@intel.com>
> >> Subject: Re: [PATCH 06/10] Support Intel RAO-INT
> >>
> >> On 26.10.2022 07:16, Jiang, Haochen wrote:
> >>>> -----Original Message-----
> >>>> From: Jan Beulich <jbeulich@suse.com>
> >>>> Sent: Tuesday, October 25, 2022 3:01 PM
> >>>>
> >>>> On 24.10.2022 07:56, Jiang, Haochen wrote:
> >>>>>> -----Original Message-----
> >>>>>> From: Jan Beulich <jbeulich@suse.com>
> >>>>>> Sent: Friday, October 14, 2022 10:38 PM
> >>>>>>
> >>>>>> On 14.10.2022 11:12, Haochen Jiang wrote:
> >>>>>>> +aadd, 0xf38fc, None, CpuRAOINT,
> >>>>>>>
> >>>>
> >> +Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf,{ Reg32|Reg64,
> >>>>>>> +Dword|Qword|Unspecified|BaseIndex}
> >>>>>>> +aand, 0x660f38fc, None, CpuRAOINT,
> >>>>>>>
> >>>>
> >> +Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf,{ Reg32|Reg64,
> >>>>>>> +Dword|Qword|Unspecified|BaseIndex}
> >>>>>>> +aor, 0xf20f38fc, None, CpuRAOINT,
> >>>>>>>
> >>>>
> >> +Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf,{ Reg32|Reg64,
> >>>>>>> +Dword|Qword|Unspecified|BaseIndex}
> >>>>>>> +axor, 0xf30f38fc, None, CpuRAOINT,
> >>>>>>>
> >>>>
> >> +Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf,{ Reg32|Reg64,
> >>>>>>> +Dword|Qword|Unspecified|BaseIndex}
> >>>>>>
> >>>>>> Why IgnoreSize? Instead I think you need CheckRegSize (assuming it
> >> does
> >>>>>> enough for Intel syntax memory operands - please double check; if not
> >>>> this will
> >>>>>> need fixing).
> >>>>>>
> >>>>>
> >>>>> For table, we aligned with CMPccXADD and added No_lSuf and No_qSuf
> >>>> since
> >>>>> the suffixes are not required.
> >>>>
> >>>> Which, as said, I consider wrong both here and there.
> >>>
> >>> I still agree with H.J.. Also I suppose the previous usage of suffixes are quite
> >>> messy and we should not stick on the confusing code.
> >>>
> >>> Keeping consistent with SPEC from now on to avoid confusion on that
> >> might
> >>> be a better solution for future.
> >>
> >> Same question to you then: Which spec? As said in reply to H.J., the only
> >> spec I'm aware of suggests prefixes ought to be used _whenever_ there's a
> >> sized memory operand [1]. If we want to deal with the present "mess", I
> >> think we ought to simply allow suffixes consistently. Please point out any
> >> other messy aspects beyond that.
> >
> > The default behavior for current ISA is when there is no suffix required, it won't
> > mention that.
>
> What is "current ISA" here? Looking over the whole set of insns which we
> support, it's the vast majority which behaves differently from what you
> say. It's been several times that I mentioned that we would better
> eliminate this inconsistency.
>
There is no ambiguity in the RAO-INT spec which requires a suffix.
No suffix in A&T syntax is different from legacy instructions. But
it is consistent with the RAO-INT spec.
On 27.10.2022 20:46, H.J. Lu wrote:
> On Wed, Oct 26, 2022 at 11:39 PM Jan Beulich <jbeulich@suse.com> wrote:
>>
>> On 27.10.2022 05:50, Jiang, Haochen wrote:
>>>> -----Original Message-----
>>>> From: Jan Beulich <jbeulich@suse.com>
>>>> Sent: Wednesday, October 26, 2022 4:57 PM
>>>> To: Jiang, Haochen <haochen.jiang@intel.com>
>>>> Cc: hjl.tools@gmail.com; binutils@sourceware.org; Kong, Lingling
>>>> <lingling.kong@intel.com>
>>>> Subject: Re: [PATCH 06/10] Support Intel RAO-INT
>>>>
>>>> On 26.10.2022 07:16, Jiang, Haochen wrote:
>>>>>> -----Original Message-----
>>>>>> From: Jan Beulich <jbeulich@suse.com>
>>>>>> Sent: Tuesday, October 25, 2022 3:01 PM
>>>>>>
>>>>>> On 24.10.2022 07:56, Jiang, Haochen wrote:
>>>>>>>> -----Original Message-----
>>>>>>>> From: Jan Beulich <jbeulich@suse.com>
>>>>>>>> Sent: Friday, October 14, 2022 10:38 PM
>>>>>>>>
>>>>>>>> On 14.10.2022 11:12, Haochen Jiang wrote:
>>>>>>>>> +aadd, 0xf38fc, None, CpuRAOINT,
>>>>>>>>>
>>>>>>
>>>> +Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf,{ Reg32|Reg64,
>>>>>>>>> +Dword|Qword|Unspecified|BaseIndex}
>>>>>>>>> +aand, 0x660f38fc, None, CpuRAOINT,
>>>>>>>>>
>>>>>>
>>>> +Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf,{ Reg32|Reg64,
>>>>>>>>> +Dword|Qword|Unspecified|BaseIndex}
>>>>>>>>> +aor, 0xf20f38fc, None, CpuRAOINT,
>>>>>>>>>
>>>>>>
>>>> +Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf,{ Reg32|Reg64,
>>>>>>>>> +Dword|Qword|Unspecified|BaseIndex}
>>>>>>>>> +axor, 0xf30f38fc, None, CpuRAOINT,
>>>>>>>>>
>>>>>>
>>>> +Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf,{ Reg32|Reg64,
>>>>>>>>> +Dword|Qword|Unspecified|BaseIndex}
>>>>>>>>
>>>>>>>> Why IgnoreSize? Instead I think you need CheckRegSize (assuming it
>>>> does
>>>>>>>> enough for Intel syntax memory operands - please double check; if not
>>>>>> this will
>>>>>>>> need fixing).
>>>>>>>>
>>>>>>>
>>>>>>> For table, we aligned with CMPccXADD and added No_lSuf and No_qSuf
>>>>>> since
>>>>>>> the suffixes are not required.
>>>>>>
>>>>>> Which, as said, I consider wrong both here and there.
>>>>>
>>>>> I still agree with H.J.. Also I suppose the previous usage of suffixes are quite
>>>>> messy and we should not stick on the confusing code.
>>>>>
>>>>> Keeping consistent with SPEC from now on to avoid confusion on that
>>>> might
>>>>> be a better solution for future.
>>>>
>>>> Same question to you then: Which spec? As said in reply to H.J., the only
>>>> spec I'm aware of suggests prefixes ought to be used _whenever_ there's a
>>>> sized memory operand [1]. If we want to deal with the present "mess", I
>>>> think we ought to simply allow suffixes consistently. Please point out any
>>>> other messy aspects beyond that.
>>>
>>> The default behavior for current ISA is when there is no suffix required, it won't
>>> mention that.
>>
>> What is "current ISA" here? Looking over the whole set of insns which we
>> support, it's the vast majority which behaves differently from what you
>> say. It's been several times that I mentioned that we would better
>> eliminate this inconsistency.
>>
>
> There is no ambiguity in the RAO-INT spec which requires a suffix.
> No suffix in A&T syntax is different from legacy instructions. But
> it is consistent with the RAO-INT spec.
The RAO-INT spec doesn't even know of AT&T syntax, so can't be taken as a
reference when deciding what the behavior there should be.
Jan
> -----Original Message-----
> From: Jan Beulich <jbeulich@suse.com>
> Sent: Friday, October 28, 2022 2:53 PM
> To: H.J. Lu <hjl.tools@gmail.com>
> Cc: Jiang, Haochen <haochen.jiang@intel.com>; binutils@sourceware.org;
> Kong, Lingling <lingling.kong@intel.com>
> Subject: Re: [PATCH 06/10] Support Intel RAO-INT
>
> On 27.10.2022 20:46, H.J. Lu wrote:
> > On Wed, Oct 26, 2022 at 11:39 PM Jan Beulich <jbeulich@suse.com> wrote:
> >>
> >> On 27.10.2022 05:50, Jiang, Haochen wrote:
> >>>> -----Original Message-----
> >>>> From: Jan Beulich <jbeulich@suse.com>
> >>>> Sent: Wednesday, October 26, 2022 4:57 PM
> >>>> To: Jiang, Haochen <haochen.jiang@intel.com>
> >>>> Cc: hjl.tools@gmail.com; binutils@sourceware.org; Kong, Lingling
> >>>> <lingling.kong@intel.com>
> >>>> Subject: Re: [PATCH 06/10] Support Intel RAO-INT
> >>>>
> >>>> On 26.10.2022 07:16, Jiang, Haochen wrote:
> >>>>>> -----Original Message-----
> >>>>>> From: Jan Beulich <jbeulich@suse.com>
> >>>>>> Sent: Tuesday, October 25, 2022 3:01 PM
> >>>>>>
> >>>>>> On 24.10.2022 07:56, Jiang, Haochen wrote:
> >>>>>>>> -----Original Message-----
> >>>>>>>> From: Jan Beulich <jbeulich@suse.com>
> >>>>>>>> Sent: Friday, October 14, 2022 10:38 PM
> >>>>>>>>
> >>>>>>>> On 14.10.2022 11:12, Haochen Jiang wrote:
> >>>>>>>>> +aadd, 0xf38fc, None, CpuRAOINT,
> >>>>>>>>>
> >>>>>>
> >>>>
> +Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf,{ Reg32|Reg64,
> >>>>>>>>> +Dword|Qword|Unspecified|BaseIndex}
> >>>>>>>>> +aand, 0x660f38fc, None, CpuRAOINT,
> >>>>>>>>>
> >>>>>>
> >>>>
> +Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf,{ Reg32|Reg64,
> >>>>>>>>> +Dword|Qword|Unspecified|BaseIndex}
> >>>>>>>>> +aor, 0xf20f38fc, None, CpuRAOINT,
> >>>>>>>>>
> >>>>>>
> >>>>
> +Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf,{ Reg32|Reg64,
> >>>>>>>>> +Dword|Qword|Unspecified|BaseIndex}
> >>>>>>>>> +axor, 0xf30f38fc, None, CpuRAOINT,
> >>>>>>>>>
> >>>>>>
> >>>>
> +Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf,{ Reg32|Reg64,
> >>>>>>>>> +Dword|Qword|Unspecified|BaseIndex}
> >>>>>>>>
> >>>>>>>> Why IgnoreSize? Instead I think you need CheckRegSize
> (assuming
> >>>>>>>> it
> >>>> does
> >>>>>>>> enough for Intel syntax memory operands - please double check;
> >>>>>>>> if not
> >>>>>> this will
> >>>>>>>> need fixing).
> >>>>>>>>
> >>>>>>>
> >>>>>>> For table, we aligned with CMPccXADD and added No_lSuf and
> >>>>>>> No_qSuf
> >>>>>> since
> >>>>>>> the suffixes are not required.
> >>>>>>
> >>>>>> Which, as said, I consider wrong both here and there.
> >>>>>
> >>>>> I still agree with H.J.. Also I suppose the previous usage of
> >>>>> suffixes are quite messy and we should not stick on the confusing
> code.
> >>>>>
> >>>>> Keeping consistent with SPEC from now on to avoid confusion on
> >>>>> that
> >>>> might
> >>>>> be a better solution for future.
> >>>>
> >>>> Same question to you then: Which spec? As said in reply to H.J.,
> >>>> the only spec I'm aware of suggests prefixes ought to be used
> >>>> _whenever_ there's a sized memory operand [1]. If we want to deal
> >>>> with the present "mess", I think we ought to simply allow suffixes
> >>>> consistently. Please point out any other messy aspects beyond that.
> >>>
> >>> The default behavior for current ISA is when there is no suffix
> >>> required, it won't mention that.
> >>
> >> What is "current ISA" here? Looking over the whole set of insns which
> >> we support, it's the vast majority which behaves differently from
> >> what you say. It's been several times that I mentioned that we would
> >> better eliminate this inconsistency.
> >>
> >
> > There is no ambiguity in the RAO-INT spec which requires a suffix.
> > No suffix in A&T syntax is different from legacy instructions. But it
> > is consistent with the RAO-INT spec.
>
> The RAO-INT spec doesn't even know of AT&T syntax, so can't be taken as a
> reference when deciding what the behavior there should be.
For instruction xadd, which is quite similar with RAO-INT, when we are using
AT&T syntax, we also do not have suffix.]
I suppose if that is not required, we do not need that since we can also know
them from the register operand size.
BTW, should the suffix instruction dependent? It might be more operand
related from my opinion. If that is the truth, could we just judge whether we
should add them when dealing with memory operands?
Haochen
>
> Jan
On 28.10.2022 10:10, Jiang, Haochen wrote:
>> -----Original Message-----
>> From: Jan Beulich <jbeulich@suse.com>
>> Sent: Friday, October 28, 2022 2:53 PM
>> To: H.J. Lu <hjl.tools@gmail.com>
>> Cc: Jiang, Haochen <haochen.jiang@intel.com>; binutils@sourceware.org;
>> Kong, Lingling <lingling.kong@intel.com>
>> Subject: Re: [PATCH 06/10] Support Intel RAO-INT
>>
>> On 27.10.2022 20:46, H.J. Lu wrote:
>>> On Wed, Oct 26, 2022 at 11:39 PM Jan Beulich <jbeulich@suse.com> wrote:
>>>>
>>>> On 27.10.2022 05:50, Jiang, Haochen wrote:
>>>>>> -----Original Message-----
>>>>>> From: Jan Beulich <jbeulich@suse.com>
>>>>>> Sent: Wednesday, October 26, 2022 4:57 PM
>>>>>> To: Jiang, Haochen <haochen.jiang@intel.com>
>>>>>> Cc: hjl.tools@gmail.com; binutils@sourceware.org; Kong, Lingling
>>>>>> <lingling.kong@intel.com>
>>>>>> Subject: Re: [PATCH 06/10] Support Intel RAO-INT
>>>>>>
>>>>>> On 26.10.2022 07:16, Jiang, Haochen wrote:
>>>>>>>> -----Original Message-----
>>>>>>>> From: Jan Beulich <jbeulich@suse.com>
>>>>>>>> Sent: Tuesday, October 25, 2022 3:01 PM
>>>>>>>>
>>>>>>>> On 24.10.2022 07:56, Jiang, Haochen wrote:
>>>>>>>>>> -----Original Message-----
>>>>>>>>>> From: Jan Beulich <jbeulich@suse.com>
>>>>>>>>>> Sent: Friday, October 14, 2022 10:38 PM
>>>>>>>>>>
>>>>>>>>>> On 14.10.2022 11:12, Haochen Jiang wrote:
>>>>>>>>>>> +aadd, 0xf38fc, None, CpuRAOINT,
>>>>>>>>>>>
>>>>>>>>
>>>>>>
>> +Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf,{ Reg32|Reg64,
>>>>>>>>>>> +Dword|Qword|Unspecified|BaseIndex}
>>>>>>>>>>> +aand, 0x660f38fc, None, CpuRAOINT,
>>>>>>>>>>>
>>>>>>>>
>>>>>>
>> +Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf,{ Reg32|Reg64,
>>>>>>>>>>> +Dword|Qword|Unspecified|BaseIndex}
>>>>>>>>>>> +aor, 0xf20f38fc, None, CpuRAOINT,
>>>>>>>>>>>
>>>>>>>>
>>>>>>
>> +Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf,{ Reg32|Reg64,
>>>>>>>>>>> +Dword|Qword|Unspecified|BaseIndex}
>>>>>>>>>>> +axor, 0xf30f38fc, None, CpuRAOINT,
>>>>>>>>>>>
>>>>>>>>
>>>>>>
>> +Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf,{ Reg32|Reg64,
>>>>>>>>>>> +Dword|Qword|Unspecified|BaseIndex}
>>>>>>>>>>
>>>>>>>>>> Why IgnoreSize? Instead I think you need CheckRegSize
>> (assuming
>>>>>>>>>> it
>>>>>> does
>>>>>>>>>> enough for Intel syntax memory operands - please double check;
>>>>>>>>>> if not
>>>>>>>> this will
>>>>>>>>>> need fixing).
>>>>>>>>>>
>>>>>>>>>
>>>>>>>>> For table, we aligned with CMPccXADD and added No_lSuf and
>>>>>>>>> No_qSuf
>>>>>>>> since
>>>>>>>>> the suffixes are not required.
>>>>>>>>
>>>>>>>> Which, as said, I consider wrong both here and there.
>>>>>>>
>>>>>>> I still agree with H.J.. Also I suppose the previous usage of
>>>>>>> suffixes are quite messy and we should not stick on the confusing
>> code.
>>>>>>>
>>>>>>> Keeping consistent with SPEC from now on to avoid confusion on
>>>>>>> that
>>>>>> might
>>>>>>> be a better solution for future.
>>>>>>
>>>>>> Same question to you then: Which spec? As said in reply to H.J.,
>>>>>> the only spec I'm aware of suggests prefixes ought to be used
>>>>>> _whenever_ there's a sized memory operand [1]. If we want to deal
>>>>>> with the present "mess", I think we ought to simply allow suffixes
>>>>>> consistently. Please point out any other messy aspects beyond that.
>>>>>
>>>>> The default behavior for current ISA is when there is no suffix
>>>>> required, it won't mention that.
>>>>
>>>> What is "current ISA" here? Looking over the whole set of insns which
>>>> we support, it's the vast majority which behaves differently from
>>>> what you say. It's been several times that I mentioned that we would
>>>> better eliminate this inconsistency.
>>>>
>>>
>>> There is no ambiguity in the RAO-INT spec which requires a suffix.
>>> No suffix in A&T syntax is different from legacy instructions. But it
>>> is consistent with the RAO-INT spec.
>>
>> The RAO-INT spec doesn't even know of AT&T syntax, so can't be taken as a
>> reference when deciding what the behavior there should be.
>
> For instruction xadd, which is quite similar with RAO-INT, when we are using
> AT&T syntax, we also do not have suffix.]
Where do you take that from? The present table entry is
xadd, 0xfc0, None, Cpu486, W|CheckRegSize|Modrm|No_sSuf|No_ldSuf|HLEPrefixLock, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
which demonstrates that b, w, l, and q suffixes are all permitted.
> I suppose if that is not required, we do not need that since we can also know
> them from the register operand size.
Sure, the suffix can be derived from the involved registers. Therefore
on such insns it isn't required. But its use still ought to be permitted.
> BTW, should the suffix instruction dependent? It might be more operand
> related from my opinion. If that is the truth, could we just judge whether we
> should add them when dealing with memory operands?
I'm afraid I don't really understand what you're saying/asking here.
In any event - whether a suffix is required indeed depends on insn
operands. Yet even insns with (only) GPR operands _may_ use a suffix
in AT&T mode, irrespective of it being derivable from those GPR
operands. We actually apply consistency checks between registers used
and the suffix (if present).
Jan
> -----Original Message-----
> From: Jan Beulich <jbeulich@suse.com>
> Sent: Friday, October 28, 2022 4:22 PM
> To: Jiang, Haochen <haochen.jiang@intel.com>
> Cc: binutils@sourceware.org; Kong, Lingling <lingling.kong@intel.com>; H.J.
> Lu <hjl.tools@gmail.com>
> Subject: Re: [PATCH 06/10] Support Intel RAO-INT
>
> On 28.10.2022 10:10, Jiang, Haochen wrote:
> >> -----Original Message-----
> >> From: Jan Beulich <jbeulich@suse.com>
> >> Sent: Friday, October 28, 2022 2:53 PM
> >> To: H.J. Lu <hjl.tools@gmail.com>
> >> Cc: Jiang, Haochen <haochen.jiang@intel.com>;
> >> binutils@sourceware.org; Kong, Lingling <lingling.kong@intel.com>
> >> Subject: Re: [PATCH 06/10] Support Intel RAO-INT
> >>
> >> On 27.10.2022 20:46, H.J. Lu wrote:
> >>> On Wed, Oct 26, 2022 at 11:39 PM Jan Beulich <jbeulich@suse.com>
> wrote:
> >>>>
> >>>> On 27.10.2022 05:50, Jiang, Haochen wrote:
> >>>>>> -----Original Message-----
> >>>>>> From: Jan Beulich <jbeulich@suse.com>
> >>>>>> Sent: Wednesday, October 26, 2022 4:57 PM
> >>>>>> To: Jiang, Haochen <haochen.jiang@intel.com>
> >>>>>> Cc: hjl.tools@gmail.com; binutils@sourceware.org; Kong, Lingling
> >>>>>> <lingling.kong@intel.com>
> >>>>>> Subject: Re: [PATCH 06/10] Support Intel RAO-INT
> >>>>>>
> >>>>>> On 26.10.2022 07:16, Jiang, Haochen wrote:
> >>>>>>>> -----Original Message-----
> >>>>>>>> From: Jan Beulich <jbeulich@suse.com>
> >>>>>>>> Sent: Tuesday, October 25, 2022 3:01 PM
> >>>>>>>>
> >>>>>>>> On 24.10.2022 07:56, Jiang, Haochen wrote:
> >>>>>>>>>> -----Original Message-----
> >>>>>>>>>> From: Jan Beulich <jbeulich@suse.com>
> >>>>>>>>>> Sent: Friday, October 14, 2022 10:38 PM
> >>>>>>>>>>
> >>>>>>>>>> On 14.10.2022 11:12, Haochen Jiang wrote:
> >>>>>>>>>>> +aadd, 0xf38fc, None, CpuRAOINT,
> >>>>>>>>>>>
> >>>>>>>>
> >>>>>>
> >>
> +Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf,{ Reg32|Reg64,
> >>>>>>>>>>> +Dword|Qword|Unspecified|BaseIndex}
> >>>>>>>>>>> +aand, 0x660f38fc, None, CpuRAOINT,
> >>>>>>>>>>>
> >>>>>>>>
> >>>>>>
> >>
> +Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf,{ Reg32|Reg64,
> >>>>>>>>>>> +Dword|Qword|Unspecified|BaseIndex}
> >>>>>>>>>>> +aor, 0xf20f38fc, None, CpuRAOINT,
> >>>>>>>>>>>
> >>>>>>>>
> >>>>>>
> >>
> +Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf,{ Reg32|Reg64,
> >>>>>>>>>>> +Dword|Qword|Unspecified|BaseIndex}
> >>>>>>>>>>> +axor, 0xf30f38fc, None, CpuRAOINT,
> >>>>>>>>>>>
> >>>>>>>>
> >>>>>>
> >>
> +Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf,{ Reg32|Reg64,
> >>>>>>>>>>> +Dword|Qword|Unspecified|BaseIndex}
> >>>>>>>>>>
> >>>>>>>>>> Why IgnoreSize? Instead I think you need CheckRegSize
> >> (assuming
> >>>>>>>>>> it
> >>>>>> does
> >>>>>>>>>> enough for Intel syntax memory operands - please double
> >>>>>>>>>> check; if not
> >>>>>>>> this will
> >>>>>>>>>> need fixing).
> >>>>>>>>>>
> >>>>>>>>>
> >>>>>>>>> For table, we aligned with CMPccXADD and added No_lSuf and
> >>>>>>>>> No_qSuf
> >>>>>>>> since
> >>>>>>>>> the suffixes are not required.
> >>>>>>>>
> >>>>>>>> Which, as said, I consider wrong both here and there.
> >>>>>>>
> >>>>>>> I still agree with H.J.. Also I suppose the previous usage of
> >>>>>>> suffixes are quite messy and we should not stick on the
> >>>>>>> confusing
> >> code.
> >>>>>>>
> >>>>>>> Keeping consistent with SPEC from now on to avoid confusion on
> >>>>>>> that
> >>>>>> might
> >>>>>>> be a better solution for future.
> >>>>>>
> >>>>>> Same question to you then: Which spec? As said in reply to H.J.,
> >>>>>> the only spec I'm aware of suggests prefixes ought to be used
> >>>>>> _whenever_ there's a sized memory operand [1]. If we want to deal
> >>>>>> with the present "mess", I think we ought to simply allow
> >>>>>> suffixes consistently. Please point out any other messy aspects
> beyond that.
> >>>>>
> >>>>> The default behavior for current ISA is when there is no suffix
> >>>>> required, it won't mention that.
> >>>>
> >>>> What is "current ISA" here? Looking over the whole set of insns
> >>>> which we support, it's the vast majority which behaves differently
> >>>> from what you say. It's been several times that I mentioned that we
> >>>> would better eliminate this inconsistency.
> >>>>
> >>>
> >>> There is no ambiguity in the RAO-INT spec which requires a suffix.
> >>> No suffix in A&T syntax is different from legacy instructions. But
> >>> it is consistent with the RAO-INT spec.
> >>
> >> The RAO-INT spec doesn't even know of AT&T syntax, so can't be taken
> >> as a reference when deciding what the behavior there should be.
> >
> > For instruction xadd, which is quite similar with RAO-INT, when we are
> > using AT&T syntax, we also do not have suffix.]
>
> Where do you take that from? The present table entry is
>
> xadd, 0xfc0, None, Cpu486,
> W|CheckRegSize|Modrm|No_sSuf|No_ldSuf|HLEPrefixLock,
> { Reg8|Reg16|Reg32|Reg64,
> Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIn
> dex }
>
> which demonstrates that b, w, l, and q suffixes are all permitted.
I messed up with encode/decode thing. My bad.
>
> > I suppose if that is not required, we do not need that since we can
> > also know them from the register operand size.
>
> Sure, the suffix can be derived from the involved registers. Therefore on
> such insns it isn't required. But its use still ought to be permitted.
>
> > BTW, should the suffix instruction dependent? It might be more operand
> > related from my opinion. If that is the truth, could we just judge
> > whether we should add them when dealing with memory operands?
>
> I'm afraid I don't really understand what you're saying/asking here.
> In any event - whether a suffix is required indeed depends on insn operands.
> Yet even insns with (only) GPR operands _may_ use a suffix in AT&T mode,
> irrespective of it being derivable from those GPR operands. We actually apply
> consistency checks between registers used and the suffix (if present).
What I am saying is we could put all the suffix module out of instructions. If we
found that are using those variable GPR operands, then to determine whether
we should allow suffixes instead of determining at instructions.
Haochen
>
> Jan
On 28.10.2022 10:31, Jiang, Haochen wrote:
>> -----Original Message-----
>> From: Jan Beulich <jbeulich@suse.com>
>> Sent: Friday, October 28, 2022 4:22 PM
>>
>> On 28.10.2022 10:10, Jiang, Haochen wrote:
>>> BTW, should the suffix instruction dependent? It might be more operand
>>> related from my opinion. If that is the truth, could we just judge
>>> whether we should add them when dealing with memory operands?
>>
>> I'm afraid I don't really understand what you're saying/asking here.
>> In any event - whether a suffix is required indeed depends on insn operands.
>> Yet even insns with (only) GPR operands _may_ use a suffix in AT&T mode,
>> irrespective of it being derivable from those GPR operands. We actually apply
>> consistency checks between registers used and the suffix (if present).
>
> What I am saying is we could put all the suffix module out of instructions. If we
> found that are using those variable GPR operands, then to determine whether
> we should allow suffixes instead of determining at instructions.
Once again - even with GPR operands use of suffixes is permitted (and
actually kind of mandated by the only AT&T spec I'm aware of). You
may have seen the series that I have pending to re-work some of the
suffix recognition, but that's certainly not going in the direction
you're suggesting (if I understand what you're saying; perhaps if you
gave an example it might become more clear).
Jan
On Fri, Oct 28, 2022 at 1:40 AM Jan Beulich <jbeulich@suse.com> wrote:
>
> On 28.10.2022 10:31, Jiang, Haochen wrote:
> >> -----Original Message-----
> >> From: Jan Beulich <jbeulich@suse.com>
> >> Sent: Friday, October 28, 2022 4:22 PM
> >>
> >> On 28.10.2022 10:10, Jiang, Haochen wrote:
> >>> BTW, should the suffix instruction dependent? It might be more operand
> >>> related from my opinion. If that is the truth, could we just judge
> >>> whether we should add them when dealing with memory operands?
> >>
> >> I'm afraid I don't really understand what you're saying/asking here.
> >> In any event - whether a suffix is required indeed depends on insn operands.
> >> Yet even insns with (only) GPR operands _may_ use a suffix in AT&T mode,
> >> irrespective of it being derivable from those GPR operands. We actually apply
> >> consistency checks between registers used and the suffix (if present).
> >
> > What I am saying is we could put all the suffix module out of instructions. If we
> > found that are using those variable GPR operands, then to determine whether
> > we should allow suffixes instead of determining at instructions.
>
> Once again - even with GPR operands use of suffixes is permitted (and
> actually kind of mandated by the only AT&T spec I'm aware of). You
> may have seen the series that I have pending to re-work some of the
> suffix recognition, but that's certainly not going in the direction
> you're suggesting (if I understand what you're saying; perhaps if you
> gave an example it might become more clear).
>
The old AT&T syntax rules, which are quite vague, don't apply to new
instructions.
For new instructions, the suffix should be permitted and required only
if it must
be used to specify the operand size.
On 28.10.2022 18:08, H.J. Lu wrote:
> On Fri, Oct 28, 2022 at 1:40 AM Jan Beulich <jbeulich@suse.com> wrote:
>>
>> On 28.10.2022 10:31, Jiang, Haochen wrote:
>>>> -----Original Message-----
>>>> From: Jan Beulich <jbeulich@suse.com>
>>>> Sent: Friday, October 28, 2022 4:22 PM
>>>>
>>>> On 28.10.2022 10:10, Jiang, Haochen wrote:
>>>>> BTW, should the suffix instruction dependent? It might be more operand
>>>>> related from my opinion. If that is the truth, could we just judge
>>>>> whether we should add them when dealing with memory operands?
>>>>
>>>> I'm afraid I don't really understand what you're saying/asking here.
>>>> In any event - whether a suffix is required indeed depends on insn operands.
>>>> Yet even insns with (only) GPR operands _may_ use a suffix in AT&T mode,
>>>> irrespective of it being derivable from those GPR operands. We actually apply
>>>> consistency checks between registers used and the suffix (if present).
>>>
>>> What I am saying is we could put all the suffix module out of instructions. If we
>>> found that are using those variable GPR operands, then to determine whether
>>> we should allow suffixes instead of determining at instructions.
>>
>> Once again - even with GPR operands use of suffixes is permitted (and
>> actually kind of mandated by the only AT&T spec I'm aware of). You
>> may have seen the series that I have pending to re-work some of the
>> suffix recognition, but that's certainly not going in the direction
>> you're suggesting (if I understand what you're saying; perhaps if you
>> gave an example it might become more clear).
>>
>
> The old AT&T syntax rules, which are quite vague, don't apply to new
> instructions.
Why would they not? These rules are intended to cover the full set of
insns. I'm afraid I need to keep repeating myself: Inconsistency here
leads to non-predictable overall behavior of the assembler (and of
the disassembler as well, in suffix-always mode, just that there it
won't lead to unexpected errors).
Jan
> For new instructions, the suffix should be permitted and required only
> if it must
> be used to specify the operand size.
>
>
On Mon, Oct 31, 2022 at 2:42 AM Jan Beulich <jbeulich@suse.com> wrote:
>
> On 28.10.2022 18:08, H.J. Lu wrote:
> > On Fri, Oct 28, 2022 at 1:40 AM Jan Beulich <jbeulich@suse.com> wrote:
> >>
> >> On 28.10.2022 10:31, Jiang, Haochen wrote:
> >>>> -----Original Message-----
> >>>> From: Jan Beulich <jbeulich@suse.com>
> >>>> Sent: Friday, October 28, 2022 4:22 PM
> >>>>
> >>>> On 28.10.2022 10:10, Jiang, Haochen wrote:
> >>>>> BTW, should the suffix instruction dependent? It might be more operand
> >>>>> related from my opinion. If that is the truth, could we just judge
> >>>>> whether we should add them when dealing with memory operands?
> >>>>
> >>>> I'm afraid I don't really understand what you're saying/asking here.
> >>>> In any event - whether a suffix is required indeed depends on insn operands.
> >>>> Yet even insns with (only) GPR operands _may_ use a suffix in AT&T mode,
> >>>> irrespective of it being derivable from those GPR operands. We actually apply
> >>>> consistency checks between registers used and the suffix (if present).
> >>>
> >>> What I am saying is we could put all the suffix module out of instructions. If we
> >>> found that are using those variable GPR operands, then to determine whether
> >>> we should allow suffixes instead of determining at instructions.
> >>
> >> Once again - even with GPR operands use of suffixes is permitted (and
> >> actually kind of mandated by the only AT&T spec I'm aware of). You
> >> may have seen the series that I have pending to re-work some of the
> >> suffix recognition, but that's certainly not going in the direction
> >> you're suggesting (if I understand what you're saying; perhaps if you
> >> gave an example it might become more clear).
> >>
> >
> > The old AT&T syntax rules, which are quite vague, don't apply to new
> > instructions.
>
> Why would they not? These rules are intended to cover the full set of
The rules are quite vague and the same mnemonic can mean very
different instructions, depending on the operands.
> insns. I'm afraid I need to keep repeating myself: Inconsistency here
> leads to non-predictable overall behavior of the assembler (and of
> the disassembler as well, in suffix-always mode, just that there it
> won't lead to unexpected errors).
We can't change the behavior of old instructions. For new instructions,
the unnecessary suffixes should be avoided.
> Jan
>
> > For new instructions, the suffix should be permitted and required only
> > if it must
> > be used to specify the operand size.
> >
> >
>
Hi Jan,
I modified the patch based on your previous comments, thanks so much for you reviewing!
> >> PREFIX_0F38FC_M_0 please (see comment on an earlier patch). However,
> >> like in the earlier patch - if you used Mdq below, you could avoid
> >> going through mod_table[] altogether.
> >
> > Removed pass modrm table since Edq seems also judges modrm.
>
> Edq? That one allows for register operands as well. I did suggest to use Mdq (iirc
> introduced by an earlier patch).
>
Fixed, thanks a lot!
> >>> +aadd, 0xf38fc, None, CpuRAOINT,
> >>> +Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf,{ Reg32|Reg64,
> >>> +Dword|Qword|Unspecified|BaseIndex}
> >>> +aand, 0x660f38fc, None, CpuRAOINT,
> >>> +Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf,{ Reg32|Reg64,
> >>> +Dword|Qword|Unspecified|BaseIndex}
> >>> +aor, 0xf20f38fc, None, CpuRAOINT,
> >>> +Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf,{ Reg32|Reg64,
> >>> +Dword|Qword|Unspecified|BaseIndex}
> >>> +axor, 0xf30f38fc, None, CpuRAOINT,
> >>> +Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf,{ Reg32|Reg64,
> >>> +Dword|Qword|Unspecified|BaseIndex}
> >>
> >> Why IgnoreSize? Instead I think you need CheckRegSize (assuming it
> >> does enough for Intel syntax memory operands - please double check;
> >> if not this will need fixing).
> >>
Yes, now it changed to CheckRegSize.
gas/ChangeLog:
* NEWS: Support Intel RAO-INT.
* config/tc-i386.c: Add raoint.
* doc/c-i386.texi: Document .raoint.
* testsuite/gas/i386/i386.exp: Run RAO_INT tests.
* testsuite/gas/i386/raoint-intel.d: New test.
* testsuite/gas/i386/raoint.d: Ditto.
* testsuite/gas/i386/raoint.s: Ditto.
* testsuite/gas/i386/x86-64-raoint-intel.d: Ditto.
* testsuite/gas/i386/x86-64-raoint.d: Ditto.
* testsuite/gas/i386/x86-64-raoint.s: Ditto.
opcodes/ChangeLog:
* i386-dis.c (PREFIX_0F38FC): New.
(prefix_table): Add PREFIX_0F38FC.
* i386-gen.c: (cpu_flag_init): Add CPU_RAO_INT_FLAGS and
CPU_ANY_RAO_INT_FLAGS.
* i386-init.h: Regenerated.
* i386-opc.h: (CpuRAO_INT): New.
(i386_cpu_flags): Add cpuraoint.
* i386-opc.tbl: Add RAO_INT instructions.
* i386-tbl.h: Regenerated.
---
gas/NEWS | 2 +
gas/config/tc-i386.c | 1 +
gas/doc/c-i386.texi | 3 +-
gas/testsuite/gas/i386/i386.exp | 4 +
gas/testsuite/gas/i386/raoint-intel.d | 18 +
gas/testsuite/gas/i386/raoint.d | 18 +
gas/testsuite/gas/i386/raoint.s | 15 +
gas/testsuite/gas/i386/x86-64-raoint-intel.d | 18 +
gas/testsuite/gas/i386/x86-64-raoint.d | 18 +
gas/testsuite/gas/i386/x86-64-raoint.s | 15 +
opcodes/i386-dis.c | 11 +-
opcodes/i386-gen.c | 5 +
opcodes/i386-init.h | 518 +-
opcodes/i386-opc.h | 3 +
opcodes/i386-opc.tbl | 9 +
opcodes/i386-tbl.h | 7906 +++++++++---------
16 files changed, 4389 insertions(+), 4175 deletions(-) create mode 100644 gas/testsuite/gas/i386/raoint-intel.d
create mode 100644 gas/testsuite/gas/i386/raoint.d create mode 100644 gas/testsuite/gas/i386/raoint.s create mode 100644 gas/testsuite/gas/i386/x86-64-raoint-intel.d
create mode 100644 gas/testsuite/gas/i386/x86-64-raoint.d
create mode 100644 gas/testsuite/gas/i386/x86-64-raoint.s
diff --git a/gas/NEWS b/gas/NEWS
index f35e8a93a0..86731348e3 100644
--- a/gas/NEWS
+++ b/gas/NEWS
@@ -1,5 +1,7 @@
-*- text -*-
+* Add support for Intel RAO-INT instructions.
+
* Add support for Intel AVX-NE-CONVERT instructions.
* Add support for Intel MSRLIST instructions.
diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c index a846b9e865..6dcf11470c 100644
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -1102,6 +1102,7 @@ static const arch_entry cpu_arch[] =
SUBARCH (wrmsrns, WRMSRNS, ANY_WRMSRNS, false),
SUBARCH (msrlist, MSRLIST, ANY_MSRLIST, false),
SUBARCH (avx_ne_convert, AVX_NE_CONVERT, ANY_AVX_NE_CONVERT, false),
+ SUBARCH (rao_int, RAO_INT, ANY_RAO_INT, false),
};
#undef SUBARCH
diff --git a/gas/doc/c-i386.texi b/gas/doc/c-i386.texi index 0ef1cece48..6fa1199f32 100644
--- a/gas/doc/c-i386.texi
+++ b/gas/doc/c-i386.texi
@@ -201,6 +201,7 @@ accept various extension mnemonics. For example, @code{wrmsrns}, @code{msrlist}, @code{avx_ne_convert},
+@code{rao_int},
@code{amx_int8},
@code{amx_bf16},
@code{amx_fp16},
@@ -1496,7 +1497,7 @@ supported on the CPU specified. The choices for @var{cpu_type} are:
@item @samp{.clwb} @tab @samp{.rdpid} @tab @samp{.ptwrite} @tab @samp{.ibt} @item @samp{.prefetchi} @tab @samp{.avx_ifma} @tab @samp{.avx_vnni_int8} @item @samp{.cmpccxadd} @tab @samp{.wrmsrns} @tab @samp{.msrlist} -@item @samp{.avx_ne_convert}
+@item @samp{.avx_ne_convert} @tab @samp{.rao_int}
@item @samp{.wbnoinvd} @tab @samp{.pconfig} @tab @samp{.waitpkg} @tab @samp{.cldemote} @item @samp{.shstk} @tab @samp{.gfni} @tab @samp{.vaes} @tab @samp{.vpclmulqdq} @item @samp{.movdiri} @tab @samp{.movdir64b} @tab @samp{.enqcmd} @tab @samp{.tsxldtrk} diff --git a/gas/testsuite/gas/i386/i386.exp b/gas/testsuite/gas/i386/i386.exp index 9ddf2b451e..5b20ac7ce5 100644
--- a/gas/testsuite/gas/i386/i386.exp
+++ b/gas/testsuite/gas/i386/i386.exp
@@ -485,6 +485,8 @@ if [gas_32_check] then {
run_list_test "msrlist-inval"
run_dump_test "avx-ne-convert"
run_dump_test "avx-ne-convert-intel"
+ run_dump_test "raoint"
+ run_dump_test "raoint-intel"
run_list_test "sg"
run_dump_test "clzero"
run_dump_test "invlpgb"
@@ -1166,6 +1168,8 @@ if [gas_64_check] then {
run_dump_test "x86-64-msrlist-intel"
run_dump_test "x86-64-avx-ne-convert"
run_dump_test "x86-64-avx-ne-convert-intel"
+ run_dump_test "x86-64-raoint"
+ run_dump_test "x86-64-raoint-intel"
run_dump_test "x86-64-clzero"
run_dump_test "x86-64-mwaitx-bdver4"
run_list_test "x86-64-mwaitx-reg"
diff --git a/gas/testsuite/gas/i386/raoint-intel.d b/gas/testsuite/gas/i386/raoint-intel.d
new file mode 100644
index 0000000000..2c22b9c8d0
--- /dev/null
+++ b/gas/testsuite/gas/i386/raoint-intel.d
@@ -0,0 +1,18 @@
+#as:
+#objdump: -dw -Mintel
+#name: i386 RAO_INT insns (Intel disassembly)
+#source: raoint.s
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+0+ <_start>:
+\s*[a-f0-9]+:\s*0f 38 fc 10\s+aadd DWORD PTR \[eax\],edx
+\s*[a-f0-9]+:\s*66 0f 38 fc 10\s+aand DWORD PTR \[eax\],edx
+\s*[a-f0-9]+:\s*f2 0f 38 fc 10\s+aor DWORD PTR \[eax\],edx
+\s*[a-f0-9]+:\s*f3 0f 38 fc 10\s+axor DWORD PTR \[eax\],edx
+\s*[a-f0-9]+:\s*0f 38 fc 10\s+aadd DWORD PTR \[eax\],edx
+\s*[a-f0-9]+:\s*66 0f 38 fc 10\s+aand DWORD PTR \[eax\],edx
+\s*[a-f0-9]+:\s*f2 0f 38 fc 10\s+aor DWORD PTR \[eax\],edx
+\s*[a-f0-9]+:\s*f3 0f 38 fc 10\s+axor DWORD PTR \[eax\],edx
diff --git a/gas/testsuite/gas/i386/raoint.d b/gas/testsuite/gas/i386/raoint.d new file mode 100644 index 0000000000..4a6a4e9b21
--- /dev/null
+++ b/gas/testsuite/gas/i386/raoint.d
@@ -0,0 +1,18 @@
+#as:
+#objdump: -dw
+#name: i386 RAO_INT insns
+#source: raoint.s
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+0+ <_start>:
+\s*[a-f0-9]+:\s*0f 38 fc 10\s+aadd %edx,\(%eax\)
+\s*[a-f0-9]+:\s*66 0f 38 fc 10\s+aand %edx,\(%eax\)
+\s*[a-f0-9]+:\s*f2 0f 38 fc 10\s+aor %edx,\(%eax\)
+\s*[a-f0-9]+:\s*f3 0f 38 fc 10\s+axor %edx,\(%eax\)
+\s*[a-f0-9]+:\s*0f 38 fc 10\s+aadd %edx,\(%eax\)
+\s*[a-f0-9]+:\s*66 0f 38 fc 10\s+aand %edx,\(%eax\)
+\s*[a-f0-9]+:\s*f2 0f 38 fc 10\s+aor %edx,\(%eax\)
+\s*[a-f0-9]+:\s*f3 0f 38 fc 10\s+axor %edx,\(%eax\)
diff --git a/gas/testsuite/gas/i386/raoint.s b/gas/testsuite/gas/i386/raoint.s new file mode 100644 index 0000000000..04a13ddeb9
--- /dev/null
+++ b/gas/testsuite/gas/i386/raoint.s
@@ -0,0 +1,15 @@
+# Check 32bit RAO-INT instructions
+
+ .allow_index_reg
+ .text
+_start:
+ aadd %edx, (%eax) #RAO-INT
+ aand %edx, (%eax) #RAO-INT
+ aor %edx, (%eax) #RAO-INT
+ axor %edx, (%eax) #RAO-INT
+
+.intel_syntax noprefix
+ aadd DWORD PTR [eax], %edx #RAO-INT
+ aand DWORD PTR [eax], %edx #RAO-INT
+ aor DWORD PTR [eax], %edx #RAO-INT
+ axor DWORD PTR [eax], %edx #RAO-INT
diff --git a/gas/testsuite/gas/i386/x86-64-raoint-intel.d b/gas/testsuite/gas/i386/x86-64-raoint-intel.d
new file mode 100644
index 0000000000..5b5c9051ac
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-raoint-intel.d
@@ -0,0 +1,18 @@
+#as:
+#objdump: -dw -Mintel
+#name: x86_64 RAO_INT insns (Intel disassembly)
+#source: x86-64-raoint.s
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+0+ <_start>:
+\s*[a-f0-9]+:\s*48 0f 38 fc 10\s+aadd QWORD PTR \[rax\],rdx
+\s*[a-f0-9]+:\s*66 48 0f 38 fc 10\s+aand QWORD PTR \[rax\],rdx
+\s*[a-f0-9]+:\s*f2 48 0f 38 fc 10\s+aor QWORD PTR \[rax\],rdx
+\s*[a-f0-9]+:\s*f3 48 0f 38 fc 10\s+axor QWORD PTR \[rax\],rdx
+\s*[a-f0-9]+:\s*48 0f 38 fc 10\s+aadd QWORD PTR \[rax\],rdx
+\s*[a-f0-9]+:\s*66 48 0f 38 fc 10\s+aand QWORD PTR \[rax\],rdx
+\s*[a-f0-9]+:\s*f2 48 0f 38 fc 10\s+aor QWORD PTR \[rax\],rdx
+\s*[a-f0-9]+:\s*f3 48 0f 38 fc 10\s+axor QWORD PTR \[rax\],rdx
diff --git a/gas/testsuite/gas/i386/x86-64-raoint.d b/gas/testsuite/gas/i386/x86-64-raoint.d
new file mode 100644
index 0000000000..ccdf027737
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-raoint.d
@@ -0,0 +1,18 @@
+#as:
+#objdump: -dw
+#name: x86_64 RAO_INT insns
+#source: x86-64-raoint.s
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+0+ <_start>:
+\s*[a-f0-9]+:\s*48 0f 38 fc 10\s+aadd %rdx,\(%rax\)
+\s*[a-f0-9]+:\s*66 48 0f 38 fc 10\s+aand %rdx,\(%rax\)
+\s*[a-f0-9]+:\s*f2 48 0f 38 fc 10\s+aor %rdx,\(%rax\)
+\s*[a-f0-9]+:\s*f3 48 0f 38 fc 10\s+axor %rdx,\(%rax\)
+\s*[a-f0-9]+:\s*48 0f 38 fc 10\s+aadd %rdx,\(%rax\)
+\s*[a-f0-9]+:\s*66 48 0f 38 fc 10\s+aand %rdx,\(%rax\)
+\s*[a-f0-9]+:\s*f2 48 0f 38 fc 10\s+aor %rdx,\(%rax\)
+\s*[a-f0-9]+:\s*f3 48 0f 38 fc 10\s+axor %rdx,\(%rax\)
diff --git a/gas/testsuite/gas/i386/x86-64-raoint.s b/gas/testsuite/gas/i386/x86-64-raoint.s
new file mode 100644
index 0000000000..645bcfc3c4
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-raoint.s
@@ -0,0 +1,15 @@
+# Check 64bit RAO_INT instructions
+
+ .allow_index_reg
+ .text
+_start:
+ aadd %rdx, (%rax) #RAO-INT
+ aand %rdx, (%rax) #RAO-INT
+ aor %rdx, (%rax) #RAO-INT
+ axor %rdx, (%rax) #RAO-INT
+
+.intel_syntax noprefix
+ aadd QWORD PTR [rax], %rdx #RAO-INT
+ aand QWORD PTR [rax], %rdx #RAO-INT
+ aor QWORD PTR [rax], %rdx #RAO-INT
+ axor QWORD PTR [rax], %rdx #RAO-INT
diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c index f0638a3193..ee7fc09932 100644
--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -1076,6 +1076,7 @@ enum
PREFIX_0F38F8,
PREFIX_0F38FA,
PREFIX_0F38FB,
+ PREFIX_0F38FC,
PREFIX_0F3A0F,
PREFIX_VEX_0F10,
PREFIX_VEX_0F11,
@@ -3620,6 +3621,14 @@ static const struct dis386 prefix_table[][4] = {
{ MOD_TABLE (MOD_0F38FB_PREFIX_1) },
},
+ /* PREFIX_0F38FC */
+ {
+ { "aadd", { Mdq, Gdq }, 0 },
+ { "axor", { Mdq, Gdq }, 0 },
+ { "aand", { Mdq, Gdq }, 0 },
+ { "aor", { Mdq, Gdq }, 0 },
+ },
+
/* PREFIX_0F3A0F */
{
{ Bad_Opcode },
@@ -4846,7 +4855,7 @@ static const struct dis386 three_byte_table[][256] = {
{ MOD_TABLE (MOD_0F38F9) },
{ PREFIX_TABLE (PREFIX_0F38FA) },
{ PREFIX_TABLE (PREFIX_0F38FB) },
- { Bad_Opcode },
+ { PREFIX_TABLE (PREFIX_0F38FC) },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
diff --git a/opcodes/i386-gen.c b/opcodes/i386-gen.c index 6e723681df..60e6d89a29 100644
--- a/opcodes/i386-gen.c
+++ b/opcodes/i386-gen.c
@@ -259,6 +259,8 @@ static initializer cpu_flag_init[] =
"CpuMSRLIST" },
{ "CPU_AVX_NE_CONVERT_FLAGS",
"CPU_AVX2_FLAGS|CpuAVX_NE_CONVERT" },
+ { "CPU_RAO_INT_FLAGS",
+ "CpuRAO_INT" },
{ "CPU_IAMCU_FLAGS",
"Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuIAMCU" },
{ "CPU_ADX_FLAGS",
@@ -467,6 +469,8 @@ static initializer cpu_flag_init[] =
"CpuMSRLIST" },
{ "CPU_ANY_AVX_NE_CONVERT_FLAGS",
"CpuAVX_NE_CONVERT" },
+ { "CPU_ANY_RAO_INT_FLAGS",
+ "CpuRAO_INT"},
};
static initializer operand_type_init[] = @@ -673,6 +677,7 @@ static bitfield cpu_flags[] =
BITFIELD (CpuWRMSRNS),
BITFIELD (CpuMSRLIST),
BITFIELD (CpuAVX_NE_CONVERT),
+ BITFIELD (CpuRAO_INT),
BITFIELD (CpuMWAITX),
BITFIELD (CpuCLZERO),
BITFIELD (CpuOSPKE),
diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h index 78fc019c3c..b93a402f9f 100644
--- a/opcodes/i386-opc.h
+++ b/opcodes/i386-opc.h
@@ -223,6 +223,8 @@ enum
CpuMSRLIST,
/* Intel AVX NE CONVERT Instructions support required. */
CpuAVX_NE_CONVERT,
+ /* Intel RAO INT Instructions support required. */ CpuRAO_INT,
/* mwaitx instruction required */
CpuMWAITX,
/* Clzero instruction required */
@@ -411,6 +413,7 @@ typedef union i386_cpu_flags
unsigned int cpuwrmsrns:1;
unsigned int cpumsrlist:1;
unsigned int cpuavx_ne_convert:1;
+ unsigned int cpurao_int:1;
unsigned int cpumwaitx:1;
unsigned int cpuclzero:1;
unsigned int cpuospke:1;
diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl index 16f59d3476..2c6e424a9a 100644
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -3321,3 +3321,12 @@ rdmsrlist, 0xf20f01c6, None, CpuMSRLIST|Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|N wrmsrlist, 0xf30f01c6, None, CpuMSRLIST|Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
// MSRLIST instructions end.
+
+// RAO-INT instructions.
+
+aadd, 0xf38fc, None, CpuRAO_INT,
+Modrm|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf,{
+Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex } aand, 0x660f38fc,
+None, CpuRAO_INT,
+Modrm|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf,{
+Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex } aor, 0xf20f38fc, None,
+CpuRAO_INT,
+Modrm|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf,{
+Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex } axor, 0xf30f38fc,
+None, CpuRAO_INT,
+Modrm|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf,{
+Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex }
+
+// RAO-INT instructions end.
--
2.27.0
Thanks,
Lingling
On 06.11.2022 13:50, Kong, Lingling wrote:
>>>>> +aadd, 0xf38fc, None, CpuRAOINT,
>>>>> +Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf,{ Reg32|Reg64,
>>>>> +Dword|Qword|Unspecified|BaseIndex}
>>>>> +aand, 0x660f38fc, None, CpuRAOINT,
>>>>> +Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf,{ Reg32|Reg64,
>>>>> +Dword|Qword|Unspecified|BaseIndex}
>>>>> +aor, 0xf20f38fc, None, CpuRAOINT,
>>>>> +Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf,{ Reg32|Reg64,
>>>>> +Dword|Qword|Unspecified|BaseIndex}
>>>>> +axor, 0xf30f38fc, None, CpuRAOINT,
>>>>> +Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf,{ Reg32|Reg64,
>>>>> +Dword|Qword|Unspecified|BaseIndex}
>>>>
>>>> Why IgnoreSize? Instead I think you need CheckRegSize (assuming it
>>>> does enough for Intel syntax memory operands - please double check;
>>>> if not this will need fixing).
>>>>
> Yes, now it changed to CheckRegSize.
For one I'm pretty sure I said I was wrong about IgnoreSize. And as to
CheckRegSize - did you actually double check as indicated? While I
think the attribute should be there, I've also observed recently that
it missing on e.g. MOVBE does not currently make any difference (there
are the same bogus diagnostics with and without it). So while I don't
mind it being put there, H.J. may view this differently as long as the
attribute doesn't really have any effect.
> --- a/opcodes/i386-opc.h
> +++ b/opcodes/i386-opc.h
> @@ -223,6 +223,8 @@ enum
> CpuMSRLIST,
> /* Intel AVX NE CONVERT Instructions support required. */
> CpuAVX_NE_CONVERT,
> + /* Intel RAO INT Instructions support required. */ CpuRAO_INT,
> /* mwaitx instruction required */
> CpuMWAITX,
> /* Clzero instruction required */
This and ...
> --- a/opcodes/i386-opc.tbl
> +++ b/opcodes/i386-opc.tbl
> @@ -3321,3 +3321,12 @@ rdmsrlist, 0xf20f01c6, None, CpuMSRLIST|Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|N wrmsrlist, 0xf30f01c6, None, CpuMSRLIST|Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
>
> // MSRLIST instructions end.
> +
> +// RAO-INT instructions.
> +
> +aadd, 0xf38fc, None, CpuRAO_INT,
> +Modrm|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf,{
> +Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex } aand, 0x660f38fc,
> +None, CpuRAO_INT,
> +Modrm|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf,{
> +Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex } aor, 0xf20f38fc, None,
> +CpuRAO_INT,
> +Modrm|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf,{
> +Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex } axor, 0xf30f38fc,
> +None, CpuRAO_INT,
> +Modrm|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf,{
> +Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex }
> +
> +// RAO-INT instructions end.
... this doesn't look like valid changes - line breaks are at the wrong spots.
Jan
> On 06.11.2022 13:50, Kong, Lingling wrote:
> >>>>> +aadd, 0xf38fc, None, CpuRAOINT,
> >>>>>
> +Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf,{ Reg32|Reg64,
> >>>>> +Dword|Qword|Unspecified|BaseIndex}
> >>>>> +aand, 0x660f38fc, None, CpuRAOINT,
> >>>>>
> +Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf,{ Reg32|Reg64,
> >>>>> +Dword|Qword|Unspecified|BaseIndex}
> >>>>> +aor, 0xf20f38fc, None, CpuRAOINT,
> >>>>>
> +Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf,{ Reg32|Reg64,
> >>>>> +Dword|Qword|Unspecified|BaseIndex}
> >>>>> +axor, 0xf30f38fc, None, CpuRAOINT,
> >>>>>
> +Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf,{ Reg32|Reg64,
> >>>>> +Dword|Qword|Unspecified|BaseIndex}
> >>>>
> >>>> Why IgnoreSize? Instead I think you need CheckRegSize (assuming it
> >>>> does enough for Intel syntax memory operands - please double check;
> >>>> if not this will need fixing).
> >>>>
> > Yes, now it changed to CheckRegSize.
>
> For one I'm pretty sure I said I was wrong about IgnoreSize. And as to
> CheckRegSize - did you actually double check as indicated? While I think the
> attribute should be there, I've also observed recently that it missing on e.g.
> MOVBE does not currently make any difference (there are the same bogus
> diagnostics with and without it). So while I don't mind it being put there, H.J.
> may view this differently as long as the attribute doesn't really have any effect.
Thanks for reminding, IgnoreSize was deleted by mistake. Although I tested some difference Intel syntax memory operands, there is no difference in the result with or without CheckRegSize. For CheckRegSize, as far as the semantics of rao-int's operand is concerned, it needs to be checked.
> > --- a/opcodes/i386-opc.h
> > +++ b/opcodes/i386-opc.h
> > @@ -223,6 +223,8 @@ enum
> > CpuMSRLIST,
> > /* Intel AVX NE CONVERT Instructions support required. */
> > CpuAVX_NE_CONVERT,
> > + /* Intel RAO INT Instructions support required. */ CpuRAO_INT,
> > /* mwaitx instruction required */
> > CpuMWAITX,
> > /* Clzero instruction required */
>
> This and ...
>
> > --- a/opcodes/i386-opc.tbl
> > +++ b/opcodes/i386-opc.tbl
> > @@ -3321,3 +3321,12 @@ rdmsrlist, 0xf20f01c6, None, CpuMSRLIST|Cpu64,
> > No_bSuf|No_wSuf|No_lSuf|No_sSuf|N wrmsrlist, 0xf30f01c6, None,
> > CpuMSRLIST|Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf,
> {}
> >
> > // MSRLIST instructions end.
> > +
> > +// RAO-INT instructions.
> > +
> > +aadd, 0xf38fc, None, CpuRAO_INT,
> >
> +Modrm|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldS
> uf,{
> > +Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex } aand, 0x660f38fc,
> > +None, CpuRAO_INT,
> >
> +Modrm|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldS
> uf,{
> > +Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex } aor, 0xf20f38fc,
> > +Reg32|None,
> > +CpuRAO_INT,
> >
> +Modrm|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldS
> uf,{
> > +Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex } axor, 0xf30f38fc,
> > +None, CpuRAO_INT,
> >
> +Modrm|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldS
> uf,{
> > +Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex }
> > +
> > +// RAO-INT instructions end.
>
> ... this doesn't look like valid changes - line breaks are at the wrong spots.
>
> Jan
Sorry, It is mistake about my git send-email, updated again.
Subject: [PATCH] Support Intel RAO-INT
gas/ChangeLog:
* NEWS: Support Intel RAO-INT.
* config/tc-i386.c: Add raoint.
* doc/c-i386.texi: Document .raoint.
* testsuite/gas/i386/i386.exp: Run RAO_INT tests.
* testsuite/gas/i386/raoint-intel.d: New test.
* testsuite/gas/i386/raoint.d: Ditto.
* testsuite/gas/i386/raoint.s: Ditto.
* testsuite/gas/i386/x86-64-raoint-intel.d: Ditto.
* testsuite/gas/i386/x86-64-raoint.d: Ditto.
* testsuite/gas/i386/x86-64-raoint.s: Ditto.
opcodes/ChangeLog:
* i386-dis.c (PREFIX_0F38FC): New.
(prefix_table): Add PREFIX_0F38FC.
* i386-gen.c: (cpu_flag_init): Add CPU_RAO_INT_FLAGS and
CPU_ANY_RAO_INT_FLAGS.
* i386-init.h: Regenerated.
* i386-opc.h: (CpuRAO_INT): New.
(i386_cpu_flags): Add cpuraoint.
* i386-opc.tbl: Add RAO_INT instructions.
* i386-tbl.h: Regenerated.
---
gas/NEWS | 2 +
gas/config/tc-i386.c | 1 +
gas/doc/c-i386.texi | 3 +-
gas/testsuite/gas/i386/i386.exp | 4 +
gas/testsuite/gas/i386/raoint-intel.d | 18 +
gas/testsuite/gas/i386/raoint.d | 18 +
gas/testsuite/gas/i386/raoint.s | 15 +
gas/testsuite/gas/i386/x86-64-raoint-intel.d | 18 +
gas/testsuite/gas/i386/x86-64-raoint.d | 18 +
gas/testsuite/gas/i386/x86-64-raoint.s | 15 +
opcodes/i386-dis.c | 11 +-
opcodes/i386-gen.c | 5 +
opcodes/i386-init.h | 518 +-
opcodes/i386-opc.h | 3 +
opcodes/i386-opc.tbl | 9 +
opcodes/i386-tbl.h | 7906 +++++++++---------
16 files changed, 4389 insertions(+), 4175 deletions(-)
create mode 100644 gas/testsuite/gas/i386/raoint-intel.d
create mode 100644 gas/testsuite/gas/i386/raoint.d
create mode 100644 gas/testsuite/gas/i386/raoint.s
create mode 100644 gas/testsuite/gas/i386/x86-64-raoint-intel.d
create mode 100644 gas/testsuite/gas/i386/x86-64-raoint.d
create mode 100644 gas/testsuite/gas/i386/x86-64-raoint.s
diff --git a/gas/NEWS b/gas/NEWS
index f35e8a93a0..86731348e3 100644
--- a/gas/NEWS
+++ b/gas/NEWS
@@ -1,5 +1,7 @@
-*- text -*-
+* Add support for Intel RAO-INT instructions.
+
* Add support for Intel AVX-NE-CONVERT instructions.
* Add support for Intel MSRLIST instructions.
diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c
index a846b9e865..6dcf11470c 100644
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -1102,6 +1102,7 @@ static const arch_entry cpu_arch[] =
SUBARCH (wrmsrns, WRMSRNS, ANY_WRMSRNS, false),
SUBARCH (msrlist, MSRLIST, ANY_MSRLIST, false),
SUBARCH (avx_ne_convert, AVX_NE_CONVERT, ANY_AVX_NE_CONVERT, false),
+ SUBARCH (rao_int, RAO_INT, ANY_RAO_INT, false),
};
#undef SUBARCH
diff --git a/gas/doc/c-i386.texi b/gas/doc/c-i386.texi
index 0ef1cece48..6fa1199f32 100644
--- a/gas/doc/c-i386.texi
+++ b/gas/doc/c-i386.texi
@@ -201,6 +201,7 @@ accept various extension mnemonics. For example,
@code{wrmsrns},
@code{msrlist},
@code{avx_ne_convert},
+@code{rao_int},
@code{amx_int8},
@code{amx_bf16},
@code{amx_fp16},
@@ -1496,7 +1497,7 @@ supported on the CPU specified. The choices for @var{cpu_type} are:
@item @samp{.clwb} @tab @samp{.rdpid} @tab @samp{.ptwrite} @tab @samp{.ibt}
@item @samp{.prefetchi} @tab @samp{.avx_ifma} @tab @samp{.avx_vnni_int8}
@item @samp{.cmpccxadd} @tab @samp{.wrmsrns} @tab @samp{.msrlist}
-@item @samp{.avx_ne_convert}
+@item @samp{.avx_ne_convert} @tab @samp{.rao_int}
@item @samp{.wbnoinvd} @tab @samp{.pconfig} @tab @samp{.waitpkg} @tab @samp{.cldemote}
@item @samp{.shstk} @tab @samp{.gfni} @tab @samp{.vaes} @tab @samp{.vpclmulqdq}
@item @samp{.movdiri} @tab @samp{.movdir64b} @tab @samp{.enqcmd} @tab @samp{.tsxldtrk}
diff --git a/gas/testsuite/gas/i386/i386.exp b/gas/testsuite/gas/i386/i386.exp
index 9ddf2b451e..5b20ac7ce5 100644
--- a/gas/testsuite/gas/i386/i386.exp
+++ b/gas/testsuite/gas/i386/i386.exp
@@ -485,6 +485,8 @@ if [gas_32_check] then {
run_list_test "msrlist-inval"
run_dump_test "avx-ne-convert"
run_dump_test "avx-ne-convert-intel"
+ run_dump_test "raoint"
+ run_dump_test "raoint-intel"
run_list_test "sg"
run_dump_test "clzero"
run_dump_test "invlpgb"
@@ -1166,6 +1168,8 @@ if [gas_64_check] then {
run_dump_test "x86-64-msrlist-intel"
run_dump_test "x86-64-avx-ne-convert"
run_dump_test "x86-64-avx-ne-convert-intel"
+ run_dump_test "x86-64-raoint"
+ run_dump_test "x86-64-raoint-intel"
run_dump_test "x86-64-clzero"
run_dump_test "x86-64-mwaitx-bdver4"
run_list_test "x86-64-mwaitx-reg"
diff --git a/gas/testsuite/gas/i386/raoint-intel.d b/gas/testsuite/gas/i386/raoint-intel.d
new file mode 100644
index 0000000000..2c22b9c8d0
--- /dev/null
+++ b/gas/testsuite/gas/i386/raoint-intel.d
@@ -0,0 +1,18 @@
+#as:
+#objdump: -dw -Mintel
+#name: i386 RAO_INT insns (Intel disassembly)
+#source: raoint.s
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+0+ <_start>:
+\s*[a-f0-9]+:\s*0f 38 fc 10\s+aadd DWORD PTR \[eax\],edx
+\s*[a-f0-9]+:\s*66 0f 38 fc 10\s+aand DWORD PTR \[eax\],edx
+\s*[a-f0-9]+:\s*f2 0f 38 fc 10\s+aor DWORD PTR \[eax\],edx
+\s*[a-f0-9]+:\s*f3 0f 38 fc 10\s+axor DWORD PTR \[eax\],edx
+\s*[a-f0-9]+:\s*0f 38 fc 10\s+aadd DWORD PTR \[eax\],edx
+\s*[a-f0-9]+:\s*66 0f 38 fc 10\s+aand DWORD PTR \[eax\],edx
+\s*[a-f0-9]+:\s*f2 0f 38 fc 10\s+aor DWORD PTR \[eax\],edx
+\s*[a-f0-9]+:\s*f3 0f 38 fc 10\s+axor DWORD PTR \[eax\],edx
diff --git a/gas/testsuite/gas/i386/raoint.d b/gas/testsuite/gas/i386/raoint.d
new file mode 100644
index 0000000000..4a6a4e9b21
--- /dev/null
+++ b/gas/testsuite/gas/i386/raoint.d
@@ -0,0 +1,18 @@
+#as:
+#objdump: -dw
+#name: i386 RAO_INT insns
+#source: raoint.s
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+0+ <_start>:
+\s*[a-f0-9]+:\s*0f 38 fc 10\s+aadd %edx,\(%eax\)
+\s*[a-f0-9]+:\s*66 0f 38 fc 10\s+aand %edx,\(%eax\)
+\s*[a-f0-9]+:\s*f2 0f 38 fc 10\s+aor %edx,\(%eax\)
+\s*[a-f0-9]+:\s*f3 0f 38 fc 10\s+axor %edx,\(%eax\)
+\s*[a-f0-9]+:\s*0f 38 fc 10\s+aadd %edx,\(%eax\)
+\s*[a-f0-9]+:\s*66 0f 38 fc 10\s+aand %edx,\(%eax\)
+\s*[a-f0-9]+:\s*f2 0f 38 fc 10\s+aor %edx,\(%eax\)
+\s*[a-f0-9]+:\s*f3 0f 38 fc 10\s+axor %edx,\(%eax\)
diff --git a/gas/testsuite/gas/i386/raoint.s b/gas/testsuite/gas/i386/raoint.s
new file mode 100644
index 0000000000..04a13ddeb9
--- /dev/null
+++ b/gas/testsuite/gas/i386/raoint.s
@@ -0,0 +1,15 @@
+# Check 32bit RAO-INT instructions
+
+ .allow_index_reg
+ .text
+_start:
+ aadd %edx, (%eax) #RAO-INT
+ aand %edx, (%eax) #RAO-INT
+ aor %edx, (%eax) #RAO-INT
+ axor %edx, (%eax) #RAO-INT
+
+.intel_syntax noprefix
+ aadd DWORD PTR [eax], %edx #RAO-INT
+ aand DWORD PTR [eax], %edx #RAO-INT
+ aor DWORD PTR [eax], %edx #RAO-INT
+ axor DWORD PTR [eax], %edx #RAO-INT
diff --git a/gas/testsuite/gas/i386/x86-64-raoint-intel.d b/gas/testsuite/gas/i386/x86-64-raoint-intel.d
new file mode 100644
index 0000000000..5b5c9051ac
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-raoint-intel.d
@@ -0,0 +1,18 @@
+#as:
+#objdump: -dw -Mintel
+#name: x86_64 RAO_INT insns (Intel disassembly)
+#source: x86-64-raoint.s
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+0+ <_start>:
+\s*[a-f0-9]+:\s*48 0f 38 fc 10\s+aadd QWORD PTR \[rax\],rdx
+\s*[a-f0-9]+:\s*66 48 0f 38 fc 10\s+aand QWORD PTR \[rax\],rdx
+\s*[a-f0-9]+:\s*f2 48 0f 38 fc 10\s+aor QWORD PTR \[rax\],rdx
+\s*[a-f0-9]+:\s*f3 48 0f 38 fc 10\s+axor QWORD PTR \[rax\],rdx
+\s*[a-f0-9]+:\s*48 0f 38 fc 10\s+aadd QWORD PTR \[rax\],rdx
+\s*[a-f0-9]+:\s*66 48 0f 38 fc 10\s+aand QWORD PTR \[rax\],rdx
+\s*[a-f0-9]+:\s*f2 48 0f 38 fc 10\s+aor QWORD PTR \[rax\],rdx
+\s*[a-f0-9]+:\s*f3 48 0f 38 fc 10\s+axor QWORD PTR \[rax\],rdx
diff --git a/gas/testsuite/gas/i386/x86-64-raoint.d b/gas/testsuite/gas/i386/x86-64-raoint.d
new file mode 100644
index 0000000000..ccdf027737
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-raoint.d
@@ -0,0 +1,18 @@
+#as:
+#objdump: -dw
+#name: x86_64 RAO_INT insns
+#source: x86-64-raoint.s
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+0+ <_start>:
+\s*[a-f0-9]+:\s*48 0f 38 fc 10\s+aadd %rdx,\(%rax\)
+\s*[a-f0-9]+:\s*66 48 0f 38 fc 10\s+aand %rdx,\(%rax\)
+\s*[a-f0-9]+:\s*f2 48 0f 38 fc 10\s+aor %rdx,\(%rax\)
+\s*[a-f0-9]+:\s*f3 48 0f 38 fc 10\s+axor %rdx,\(%rax\)
+\s*[a-f0-9]+:\s*48 0f 38 fc 10\s+aadd %rdx,\(%rax\)
+\s*[a-f0-9]+:\s*66 48 0f 38 fc 10\s+aand %rdx,\(%rax\)
+\s*[a-f0-9]+:\s*f2 48 0f 38 fc 10\s+aor %rdx,\(%rax\)
+\s*[a-f0-9]+:\s*f3 48 0f 38 fc 10\s+axor %rdx,\(%rax\)
diff --git a/gas/testsuite/gas/i386/x86-64-raoint.s b/gas/testsuite/gas/i386/x86-64-raoint.s
new file mode 100644
index 0000000000..645bcfc3c4
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-raoint.s
@@ -0,0 +1,15 @@
+# Check 64bit RAO_INT instructions
+
+ .allow_index_reg
+ .text
+_start:
+ aadd %rdx, (%rax) #RAO-INT
+ aand %rdx, (%rax) #RAO-INT
+ aor %rdx, (%rax) #RAO-INT
+ axor %rdx, (%rax) #RAO-INT
+
+.intel_syntax noprefix
+ aadd QWORD PTR [rax], %rdx #RAO-INT
+ aand QWORD PTR [rax], %rdx #RAO-INT
+ aor QWORD PTR [rax], %rdx #RAO-INT
+ axor QWORD PTR [rax], %rdx #RAO-INT
diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c
index f0638a3193..ee7fc09932 100644
--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -1076,6 +1076,7 @@ enum
PREFIX_0F38F8,
PREFIX_0F38FA,
PREFIX_0F38FB,
+ PREFIX_0F38FC,
PREFIX_0F3A0F,
PREFIX_VEX_0F10,
PREFIX_VEX_0F11,
@@ -3620,6 +3621,14 @@ static const struct dis386 prefix_table[][4] = {
{ MOD_TABLE (MOD_0F38FB_PREFIX_1) },
},
+ /* PREFIX_0F38FC */
+ {
+ { "aadd", { Mdq, Gdq }, 0 },
+ { "axor", { Mdq, Gdq }, 0 },
+ { "aand", { Mdq, Gdq }, 0 },
+ { "aor", { Mdq, Gdq }, 0 },
+ },
+
/* PREFIX_0F3A0F */
{
{ Bad_Opcode },
@@ -4846,7 +4855,7 @@ static const struct dis386 three_byte_table[][256] = {
{ MOD_TABLE (MOD_0F38F9) },
{ PREFIX_TABLE (PREFIX_0F38FA) },
{ PREFIX_TABLE (PREFIX_0F38FB) },
- { Bad_Opcode },
+ { PREFIX_TABLE (PREFIX_0F38FC) },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
diff --git a/opcodes/i386-gen.c b/opcodes/i386-gen.c
index 6e723681df..60e6d89a29 100644
--- a/opcodes/i386-gen.c
+++ b/opcodes/i386-gen.c
@@ -259,6 +259,8 @@ static initializer cpu_flag_init[] =
"CpuMSRLIST" },
{ "CPU_AVX_NE_CONVERT_FLAGS",
"CPU_AVX2_FLAGS|CpuAVX_NE_CONVERT" },
+ { "CPU_RAO_INT_FLAGS",
+ "CpuRAO_INT" },
{ "CPU_IAMCU_FLAGS",
"Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuIAMCU" },
{ "CPU_ADX_FLAGS",
@@ -467,6 +469,8 @@ static initializer cpu_flag_init[] =
"CpuMSRLIST" },
{ "CPU_ANY_AVX_NE_CONVERT_FLAGS",
"CpuAVX_NE_CONVERT" },
+ { "CPU_ANY_RAO_INT_FLAGS",
+ "CpuRAO_INT"},
};
static initializer operand_type_init[] =
@@ -673,6 +677,7 @@ static bitfield cpu_flags[] =
BITFIELD (CpuWRMSRNS),
BITFIELD (CpuMSRLIST),
BITFIELD (CpuAVX_NE_CONVERT),
+ BITFIELD (CpuRAO_INT),
BITFIELD (CpuMWAITX),
BITFIELD (CpuCLZERO),
BITFIELD (CpuOSPKE),
diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h
index 78fc019c3c..b93a402f9f 100644
--- a/opcodes/i386-opc.h
+++ b/opcodes/i386-opc.h
@@ -223,6 +223,8 @@ enum
CpuMSRLIST,
/* Intel AVX NE CONVERT Instructions support required. */
CpuAVX_NE_CONVERT,
+ /* Intel RAO INT Instructions support required. */
+ CpuRAO_INT,
/* mwaitx instruction required */
CpuMWAITX,
/* Clzero instruction required */
@@ -411,6 +413,7 @@ typedef union i386_cpu_flags
unsigned int cpuwrmsrns:1;
unsigned int cpumsrlist:1;
unsigned int cpuavx_ne_convert:1;
+ unsigned int cpurao_int:1;
unsigned int cpumwaitx:1;
unsigned int cpuclzero:1;
unsigned int cpuospke:1;
diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl
index 16f59d3476..2c6e424a9a 100644
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -3321,3 +3321,12 @@ rdmsrlist, 0xf20f01c6, None, CpuMSRLIST|Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|N
wrmsrlist, 0xf30f01c6, None, CpuMSRLIST|Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
// MSRLIST instructions end.
+
+// RAO-INT instructions.
+
+aadd, 0xf38fc, None, CpuRAO_INT, Modrm|IgnoreSize|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex }
+aand, 0x660f38fc, None, CpuRAO_INT, Modrm|IgnoreSize|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex }
+aor, 0xf20f38fc, None, CpuRAO_INT, Modrm|IgnoreSize|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex }
+axor, 0xf30f38fc, None, CpuRAO_INT, Modrm|IgnoreSize|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex }+
+// RAO-INT instructions end.
--
2.27.0
On Mon, Nov 7, 2022 at 5:37 AM Kong, Lingling <lingling.kong@intel.com> wrote:
>
> > On 06.11.2022 13:50, Kong, Lingling wrote:
> > >>>>> +aadd, 0xf38fc, None, CpuRAOINT,
> > >>>>>
> > +Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf,{ Reg32|Reg64,
> > >>>>> +Dword|Qword|Unspecified|BaseIndex}
> > >>>>> +aand, 0x660f38fc, None, CpuRAOINT,
> > >>>>>
> > +Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf,{ Reg32|Reg64,
> > >>>>> +Dword|Qword|Unspecified|BaseIndex}
> > >>>>> +aor, 0xf20f38fc, None, CpuRAOINT,
> > >>>>>
> > +Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf,{ Reg32|Reg64,
> > >>>>> +Dword|Qword|Unspecified|BaseIndex}
> > >>>>> +axor, 0xf30f38fc, None, CpuRAOINT,
> > >>>>>
> > +Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf,{ Reg32|Reg64,
> > >>>>> +Dword|Qword|Unspecified|BaseIndex}
> > >>>>
> > >>>> Why IgnoreSize? Instead I think you need CheckRegSize (assuming it
> > >>>> does enough for Intel syntax memory operands - please double check;
> > >>>> if not this will need fixing).
> > >>>>
> > > Yes, now it changed to CheckRegSize.
> >
> > For one I'm pretty sure I said I was wrong about IgnoreSize. And as to
> > CheckRegSize - did you actually double check as indicated? While I think the
> > attribute should be there, I've also observed recently that it missing on e.g.
> > MOVBE does not currently make any difference (there are the same bogus
> > diagnostics with and without it). So while I don't mind it being put there, H.J.
> > may view this differently as long as the attribute doesn't really have any effect.
>
> Thanks for reminding, IgnoreSize was deleted by mistake. Although I tested some difference Intel syntax memory operands, there is no difference in the result with or without CheckRegSize. For CheckRegSize, as far as the semantics of rao-int's operand is concerned, it needs to be checked.
>
> > > --- a/opcodes/i386-opc.h
> > > +++ b/opcodes/i386-opc.h
> > > @@ -223,6 +223,8 @@ enum
> > > CpuMSRLIST,
> > > /* Intel AVX NE CONVERT Instructions support required. */
> > > CpuAVX_NE_CONVERT,
> > > + /* Intel RAO INT Instructions support required. */ CpuRAO_INT,
> > > /* mwaitx instruction required */
> > > CpuMWAITX,
> > > /* Clzero instruction required */
> >
> > This and ...
> >
> > > --- a/opcodes/i386-opc.tbl
> > > +++ b/opcodes/i386-opc.tbl
> > > @@ -3321,3 +3321,12 @@ rdmsrlist, 0xf20f01c6, None, CpuMSRLIST|Cpu64,
> > > No_bSuf|No_wSuf|No_lSuf|No_sSuf|N wrmsrlist, 0xf30f01c6, None,
> > > CpuMSRLIST|Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf,
> > {}
> > >
> > > // MSRLIST instructions end.
> > > +
> > > +// RAO-INT instructions.
> > > +
> > > +aadd, 0xf38fc, None, CpuRAO_INT,
> > >
> > +Modrm|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldS
> > uf,{
> > > +Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex } aand, 0x660f38fc,
> > > +None, CpuRAO_INT,
> > >
> > +Modrm|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldS
> > uf,{
> > > +Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex } aor, 0xf20f38fc,
> > > +Reg32|None,
> > > +CpuRAO_INT,
> > >
> > +Modrm|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldS
> > uf,{
> > > +Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex } axor, 0xf30f38fc,
> > > +None, CpuRAO_INT,
> > >
> > +Modrm|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldS
> > uf,{
> > > +Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex }
> > > +
> > > +// RAO-INT instructions end.
> >
> > ... this doesn't look like valid changes - line breaks are at the wrong spots.
> >
> > Jan
>
> Sorry, It is mistake about my git send-email, updated again.
>
> Subject: [PATCH] Support Intel RAO-INT
>
> gas/ChangeLog:
>
> * NEWS: Support Intel RAO-INT.
> * config/tc-i386.c: Add raoint.
> * doc/c-i386.texi: Document .raoint.
> * testsuite/gas/i386/i386.exp: Run RAO_INT tests.
> * testsuite/gas/i386/raoint-intel.d: New test.
> * testsuite/gas/i386/raoint.d: Ditto.
> * testsuite/gas/i386/raoint.s: Ditto.
> * testsuite/gas/i386/x86-64-raoint-intel.d: Ditto.
> * testsuite/gas/i386/x86-64-raoint.d: Ditto.
> * testsuite/gas/i386/x86-64-raoint.s: Ditto.
>
> opcodes/ChangeLog:
>
> * i386-dis.c (PREFIX_0F38FC): New.
> (prefix_table): Add PREFIX_0F38FC.
> * i386-gen.c: (cpu_flag_init): Add CPU_RAO_INT_FLAGS and
> CPU_ANY_RAO_INT_FLAGS.
> * i386-init.h: Regenerated.
> * i386-opc.h: (CpuRAO_INT): New.
> (i386_cpu_flags): Add cpuraoint.
> * i386-opc.tbl: Add RAO_INT instructions.
> * i386-tbl.h: Regenerated.
> ---
> gas/NEWS | 2 +
> gas/config/tc-i386.c | 1 +
> gas/doc/c-i386.texi | 3 +-
> gas/testsuite/gas/i386/i386.exp | 4 +
> gas/testsuite/gas/i386/raoint-intel.d | 18 +
> gas/testsuite/gas/i386/raoint.d | 18 +
> gas/testsuite/gas/i386/raoint.s | 15 +
> gas/testsuite/gas/i386/x86-64-raoint-intel.d | 18 +
> gas/testsuite/gas/i386/x86-64-raoint.d | 18 +
> gas/testsuite/gas/i386/x86-64-raoint.s | 15 +
> opcodes/i386-dis.c | 11 +-
> opcodes/i386-gen.c | 5 +
> opcodes/i386-init.h | 518 +-
> opcodes/i386-opc.h | 3 +
> opcodes/i386-opc.tbl | 9 +
> opcodes/i386-tbl.h | 7906 +++++++++---------
> 16 files changed, 4389 insertions(+), 4175 deletions(-)
> create mode 100644 gas/testsuite/gas/i386/raoint-intel.d
> create mode 100644 gas/testsuite/gas/i386/raoint.d
> create mode 100644 gas/testsuite/gas/i386/raoint.s
> create mode 100644 gas/testsuite/gas/i386/x86-64-raoint-intel.d
> create mode 100644 gas/testsuite/gas/i386/x86-64-raoint.d
> create mode 100644 gas/testsuite/gas/i386/x86-64-raoint.s
>
> diff --git a/gas/NEWS b/gas/NEWS
> index f35e8a93a0..86731348e3 100644
> --- a/gas/NEWS
> +++ b/gas/NEWS
> @@ -1,5 +1,7 @@
> -*- text -*-
>
> +* Add support for Intel RAO-INT instructions.
> +
> * Add support for Intel AVX-NE-CONVERT instructions.
>
> * Add support for Intel MSRLIST instructions.
> diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c
> index a846b9e865..6dcf11470c 100644
> --- a/gas/config/tc-i386.c
> +++ b/gas/config/tc-i386.c
> @@ -1102,6 +1102,7 @@ static const arch_entry cpu_arch[] =
> SUBARCH (wrmsrns, WRMSRNS, ANY_WRMSRNS, false),
> SUBARCH (msrlist, MSRLIST, ANY_MSRLIST, false),
> SUBARCH (avx_ne_convert, AVX_NE_CONVERT, ANY_AVX_NE_CONVERT, false),
> + SUBARCH (rao_int, RAO_INT, ANY_RAO_INT, false),
> };
>
> #undef SUBARCH
> diff --git a/gas/doc/c-i386.texi b/gas/doc/c-i386.texi
> index 0ef1cece48..6fa1199f32 100644
> --- a/gas/doc/c-i386.texi
> +++ b/gas/doc/c-i386.texi
> @@ -201,6 +201,7 @@ accept various extension mnemonics. For example,
> @code{wrmsrns},
> @code{msrlist},
> @code{avx_ne_convert},
> +@code{rao_int},
> @code{amx_int8},
> @code{amx_bf16},
> @code{amx_fp16},
> @@ -1496,7 +1497,7 @@ supported on the CPU specified. The choices for @var{cpu_type} are:
> @item @samp{.clwb} @tab @samp{.rdpid} @tab @samp{.ptwrite} @tab @samp{.ibt}
> @item @samp{.prefetchi} @tab @samp{.avx_ifma} @tab @samp{.avx_vnni_int8}
> @item @samp{.cmpccxadd} @tab @samp{.wrmsrns} @tab @samp{.msrlist}
> -@item @samp{.avx_ne_convert}
> +@item @samp{.avx_ne_convert} @tab @samp{.rao_int}
> @item @samp{.wbnoinvd} @tab @samp{.pconfig} @tab @samp{.waitpkg} @tab @samp{.cldemote}
> @item @samp{.shstk} @tab @samp{.gfni} @tab @samp{.vaes} @tab @samp{.vpclmulqdq}
> @item @samp{.movdiri} @tab @samp{.movdir64b} @tab @samp{.enqcmd} @tab @samp{.tsxldtrk}
> diff --git a/gas/testsuite/gas/i386/i386.exp b/gas/testsuite/gas/i386/i386.exp
> index 9ddf2b451e..5b20ac7ce5 100644
> --- a/gas/testsuite/gas/i386/i386.exp
> +++ b/gas/testsuite/gas/i386/i386.exp
> @@ -485,6 +485,8 @@ if [gas_32_check] then {
> run_list_test "msrlist-inval"
> run_dump_test "avx-ne-convert"
> run_dump_test "avx-ne-convert-intel"
> + run_dump_test "raoint"
> + run_dump_test "raoint-intel"
> run_list_test "sg"
> run_dump_test "clzero"
> run_dump_test "invlpgb"
> @@ -1166,6 +1168,8 @@ if [gas_64_check] then {
> run_dump_test "x86-64-msrlist-intel"
> run_dump_test "x86-64-avx-ne-convert"
> run_dump_test "x86-64-avx-ne-convert-intel"
> + run_dump_test "x86-64-raoint"
> + run_dump_test "x86-64-raoint-intel"
> run_dump_test "x86-64-clzero"
> run_dump_test "x86-64-mwaitx-bdver4"
> run_list_test "x86-64-mwaitx-reg"
> diff --git a/gas/testsuite/gas/i386/raoint-intel.d b/gas/testsuite/gas/i386/raoint-intel.d
> new file mode 100644
> index 0000000000..2c22b9c8d0
> --- /dev/null
> +++ b/gas/testsuite/gas/i386/raoint-intel.d
> @@ -0,0 +1,18 @@
> +#as:
> +#objdump: -dw -Mintel
> +#name: i386 RAO_INT insns (Intel disassembly)
> +#source: raoint.s
> +
> +.*: +file format .*
> +
> +Disassembly of section \.text:
> +
> +0+ <_start>:
> +\s*[a-f0-9]+:\s*0f 38 fc 10\s+aadd DWORD PTR \[eax\],edx
> +\s*[a-f0-9]+:\s*66 0f 38 fc 10\s+aand DWORD PTR \[eax\],edx
> +\s*[a-f0-9]+:\s*f2 0f 38 fc 10\s+aor DWORD PTR \[eax\],edx
> +\s*[a-f0-9]+:\s*f3 0f 38 fc 10\s+axor DWORD PTR \[eax\],edx
> +\s*[a-f0-9]+:\s*0f 38 fc 10\s+aadd DWORD PTR \[eax\],edx
> +\s*[a-f0-9]+:\s*66 0f 38 fc 10\s+aand DWORD PTR \[eax\],edx
> +\s*[a-f0-9]+:\s*f2 0f 38 fc 10\s+aor DWORD PTR \[eax\],edx
> +\s*[a-f0-9]+:\s*f3 0f 38 fc 10\s+axor DWORD PTR \[eax\],edx
> diff --git a/gas/testsuite/gas/i386/raoint.d b/gas/testsuite/gas/i386/raoint.d
> new file mode 100644
> index 0000000000..4a6a4e9b21
> --- /dev/null
> +++ b/gas/testsuite/gas/i386/raoint.d
> @@ -0,0 +1,18 @@
> +#as:
> +#objdump: -dw
> +#name: i386 RAO_INT insns
> +#source: raoint.s
> +
> +.*: +file format .*
> +
> +Disassembly of section \.text:
> +
> +0+ <_start>:
> +\s*[a-f0-9]+:\s*0f 38 fc 10\s+aadd %edx,\(%eax\)
> +\s*[a-f0-9]+:\s*66 0f 38 fc 10\s+aand %edx,\(%eax\)
> +\s*[a-f0-9]+:\s*f2 0f 38 fc 10\s+aor %edx,\(%eax\)
> +\s*[a-f0-9]+:\s*f3 0f 38 fc 10\s+axor %edx,\(%eax\)
> +\s*[a-f0-9]+:\s*0f 38 fc 10\s+aadd %edx,\(%eax\)
> +\s*[a-f0-9]+:\s*66 0f 38 fc 10\s+aand %edx,\(%eax\)
> +\s*[a-f0-9]+:\s*f2 0f 38 fc 10\s+aor %edx,\(%eax\)
> +\s*[a-f0-9]+:\s*f3 0f 38 fc 10\s+axor %edx,\(%eax\)
> diff --git a/gas/testsuite/gas/i386/raoint.s b/gas/testsuite/gas/i386/raoint.s
> new file mode 100644
> index 0000000000..04a13ddeb9
> --- /dev/null
> +++ b/gas/testsuite/gas/i386/raoint.s
> @@ -0,0 +1,15 @@
> +# Check 32bit RAO-INT instructions
> +
> + .allow_index_reg
> + .text
> +_start:
> + aadd %edx, (%eax) #RAO-INT
> + aand %edx, (%eax) #RAO-INT
> + aor %edx, (%eax) #RAO-INT
> + axor %edx, (%eax) #RAO-INT
> +
> +.intel_syntax noprefix
> + aadd DWORD PTR [eax], %edx #RAO-INT
> + aand DWORD PTR [eax], %edx #RAO-INT
> + aor DWORD PTR [eax], %edx #RAO-INT
> + axor DWORD PTR [eax], %edx #RAO-INT
> diff --git a/gas/testsuite/gas/i386/x86-64-raoint-intel.d b/gas/testsuite/gas/i386/x86-64-raoint-intel.d
> new file mode 100644
> index 0000000000..5b5c9051ac
> --- /dev/null
> +++ b/gas/testsuite/gas/i386/x86-64-raoint-intel.d
> @@ -0,0 +1,18 @@
> +#as:
> +#objdump: -dw -Mintel
> +#name: x86_64 RAO_INT insns (Intel disassembly)
> +#source: x86-64-raoint.s
> +
> +.*: +file format .*
> +
> +Disassembly of section \.text:
> +
> +0+ <_start>:
> +\s*[a-f0-9]+:\s*48 0f 38 fc 10\s+aadd QWORD PTR \[rax\],rdx
> +\s*[a-f0-9]+:\s*66 48 0f 38 fc 10\s+aand QWORD PTR \[rax\],rdx
> +\s*[a-f0-9]+:\s*f2 48 0f 38 fc 10\s+aor QWORD PTR \[rax\],rdx
> +\s*[a-f0-9]+:\s*f3 48 0f 38 fc 10\s+axor QWORD PTR \[rax\],rdx
> +\s*[a-f0-9]+:\s*48 0f 38 fc 10\s+aadd QWORD PTR \[rax\],rdx
> +\s*[a-f0-9]+:\s*66 48 0f 38 fc 10\s+aand QWORD PTR \[rax\],rdx
> +\s*[a-f0-9]+:\s*f2 48 0f 38 fc 10\s+aor QWORD PTR \[rax\],rdx
> +\s*[a-f0-9]+:\s*f3 48 0f 38 fc 10\s+axor QWORD PTR \[rax\],rdx
> diff --git a/gas/testsuite/gas/i386/x86-64-raoint.d b/gas/testsuite/gas/i386/x86-64-raoint.d
> new file mode 100644
> index 0000000000..ccdf027737
> --- /dev/null
> +++ b/gas/testsuite/gas/i386/x86-64-raoint.d
> @@ -0,0 +1,18 @@
> +#as:
> +#objdump: -dw
> +#name: x86_64 RAO_INT insns
> +#source: x86-64-raoint.s
> +
> +.*: +file format .*
> +
> +Disassembly of section \.text:
> +
> +0+ <_start>:
> +\s*[a-f0-9]+:\s*48 0f 38 fc 10\s+aadd %rdx,\(%rax\)
> +\s*[a-f0-9]+:\s*66 48 0f 38 fc 10\s+aand %rdx,\(%rax\)
> +\s*[a-f0-9]+:\s*f2 48 0f 38 fc 10\s+aor %rdx,\(%rax\)
> +\s*[a-f0-9]+:\s*f3 48 0f 38 fc 10\s+axor %rdx,\(%rax\)
> +\s*[a-f0-9]+:\s*48 0f 38 fc 10\s+aadd %rdx,\(%rax\)
> +\s*[a-f0-9]+:\s*66 48 0f 38 fc 10\s+aand %rdx,\(%rax\)
> +\s*[a-f0-9]+:\s*f2 48 0f 38 fc 10\s+aor %rdx,\(%rax\)
> +\s*[a-f0-9]+:\s*f3 48 0f 38 fc 10\s+axor %rdx,\(%rax\)
> diff --git a/gas/testsuite/gas/i386/x86-64-raoint.s b/gas/testsuite/gas/i386/x86-64-raoint.s
> new file mode 100644
> index 0000000000..645bcfc3c4
> --- /dev/null
> +++ b/gas/testsuite/gas/i386/x86-64-raoint.s
> @@ -0,0 +1,15 @@
> +# Check 64bit RAO_INT instructions
> +
> + .allow_index_reg
> + .text
> +_start:
> + aadd %rdx, (%rax) #RAO-INT
> + aand %rdx, (%rax) #RAO-INT
> + aor %rdx, (%rax) #RAO-INT
> + axor %rdx, (%rax) #RAO-INT
> +
> +.intel_syntax noprefix
> + aadd QWORD PTR [rax], %rdx #RAO-INT
> + aand QWORD PTR [rax], %rdx #RAO-INT
> + aor QWORD PTR [rax], %rdx #RAO-INT
> + axor QWORD PTR [rax], %rdx #RAO-INT
> diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c
> index f0638a3193..ee7fc09932 100644
> --- a/opcodes/i386-dis.c
> +++ b/opcodes/i386-dis.c
> @@ -1076,6 +1076,7 @@ enum
> PREFIX_0F38F8,
> PREFIX_0F38FA,
> PREFIX_0F38FB,
> + PREFIX_0F38FC,
> PREFIX_0F3A0F,
> PREFIX_VEX_0F10,
> PREFIX_VEX_0F11,
> @@ -3620,6 +3621,14 @@ static const struct dis386 prefix_table[][4] = {
> { MOD_TABLE (MOD_0F38FB_PREFIX_1) },
> },
>
> + /* PREFIX_0F38FC */
> + {
> + { "aadd", { Mdq, Gdq }, 0 },
> + { "axor", { Mdq, Gdq }, 0 },
> + { "aand", { Mdq, Gdq }, 0 },
> + { "aor", { Mdq, Gdq }, 0 },
> + },
> +
> /* PREFIX_0F3A0F */
> {
> { Bad_Opcode },
> @@ -4846,7 +4855,7 @@ static const struct dis386 three_byte_table[][256] = {
> { MOD_TABLE (MOD_0F38F9) },
> { PREFIX_TABLE (PREFIX_0F38FA) },
> { PREFIX_TABLE (PREFIX_0F38FB) },
> - { Bad_Opcode },
> + { PREFIX_TABLE (PREFIX_0F38FC) },
> { Bad_Opcode },
> { Bad_Opcode },
> { Bad_Opcode },
> diff --git a/opcodes/i386-gen.c b/opcodes/i386-gen.c
> index 6e723681df..60e6d89a29 100644
> --- a/opcodes/i386-gen.c
> +++ b/opcodes/i386-gen.c
> @@ -259,6 +259,8 @@ static initializer cpu_flag_init[] =
> "CpuMSRLIST" },
> { "CPU_AVX_NE_CONVERT_FLAGS",
> "CPU_AVX2_FLAGS|CpuAVX_NE_CONVERT" },
> + { "CPU_RAO_INT_FLAGS",
> + "CpuRAO_INT" },
> { "CPU_IAMCU_FLAGS",
> "Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuIAMCU" },
> { "CPU_ADX_FLAGS",
> @@ -467,6 +469,8 @@ static initializer cpu_flag_init[] =
> "CpuMSRLIST" },
> { "CPU_ANY_AVX_NE_CONVERT_FLAGS",
> "CpuAVX_NE_CONVERT" },
> + { "CPU_ANY_RAO_INT_FLAGS",
> + "CpuRAO_INT"},
> };
>
> static initializer operand_type_init[] =
> @@ -673,6 +677,7 @@ static bitfield cpu_flags[] =
> BITFIELD (CpuWRMSRNS),
> BITFIELD (CpuMSRLIST),
> BITFIELD (CpuAVX_NE_CONVERT),
> + BITFIELD (CpuRAO_INT),
> BITFIELD (CpuMWAITX),
> BITFIELD (CpuCLZERO),
> BITFIELD (CpuOSPKE),
> diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h
> index 78fc019c3c..b93a402f9f 100644
> --- a/opcodes/i386-opc.h
> +++ b/opcodes/i386-opc.h
> @@ -223,6 +223,8 @@ enum
> CpuMSRLIST,
> /* Intel AVX NE CONVERT Instructions support required. */
> CpuAVX_NE_CONVERT,
> + /* Intel RAO INT Instructions support required. */
> + CpuRAO_INT,
> /* mwaitx instruction required */
> CpuMWAITX,
> /* Clzero instruction required */
> @@ -411,6 +413,7 @@ typedef union i386_cpu_flags
> unsigned int cpuwrmsrns:1;
> unsigned int cpumsrlist:1;
> unsigned int cpuavx_ne_convert:1;
> + unsigned int cpurao_int:1;
> unsigned int cpumwaitx:1;
> unsigned int cpuclzero:1;
> unsigned int cpuospke:1;
> diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl
> index 16f59d3476..2c6e424a9a 100644
> --- a/opcodes/i386-opc.tbl
> +++ b/opcodes/i386-opc.tbl
> @@ -3321,3 +3321,12 @@ rdmsrlist, 0xf20f01c6, None, CpuMSRLIST|Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|N
> wrmsrlist, 0xf30f01c6, None, CpuMSRLIST|Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
>
> // MSRLIST instructions end.
> +
> +// RAO-INT instructions.
> +
> +aadd, 0xf38fc, None, CpuRAO_INT, Modrm|IgnoreSize|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex }
> +aand, 0x660f38fc, None, CpuRAO_INT, Modrm|IgnoreSize|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex }
> +aor, 0xf20f38fc, None, CpuRAO_INT, Modrm|IgnoreSize|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex }
> +axor, 0xf30f38fc, None, CpuRAO_INT, Modrm|IgnoreSize|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex }+
> +// RAO-INT instructions end.
> --
> 2.27.0
OK.
Thanks.
@@ -1,5 +1,7 @@
-*- text -*-
+* Add support for Intel RAO-INT instructions.
+
* Add support for Intel CMPccXADD instructions.
* Add support for Intel AVX-NE-CONVERT instructions.
@@ -1097,7 +1097,8 @@ static const arch_entry cpu_arch[] =
SUBARCH (avx_ifma, AVX_IFMA, ANY_AVX_IFMA, false),
SUBARCH (avx_vnni_int8, AVX_VNNI_INT8, ANY_AVX_VNNI_INT8, false),
SUBARCH (avx_ne_convert, AVX_NE_CONVERT, ANY_AVX_NE_CONVERT, false),
- SUBARCH (cmpccxadd, CMPCCXADD, ANY_CMPCCXADD, false)
+ SUBARCH (cmpccxadd, CMPCCXADD, ANY_CMPCCXADD, false),
+ SUBARCH (raoint, RAOINT, ANY_RAOINT, false),
};
#undef SUBARCH
@@ -217,6 +217,7 @@ accept various extension mnemonics. For example,
@code{avx_vnni_int8},
@code{avx_ne_convert},
@code{cmpccxadd},
+@code{raoint},
@code{noavx512f},
@code{noavx512cd},
@code{noavx512er},
@@ -241,6 +242,7 @@ accept various extension mnemonics. For example,
@code{noavx_vnni_int8},
@code{noavx_ne_convert},
@code{nocmpccxadd},
+@code{noraoint},
@code{noenqcmd},
@code{noserialize},
@code{notsxldtrk},
@@ -1542,7 +1544,7 @@ supported on the CPU specified. The choices for @var{cpu_type} are:
@item @samp{.tdx} @tab @samp{.avx_vnni} @tab @samp{.avx512_fp16}
@item @samp{.clwb} @tab @samp{.rdpid} @tab @samp{.ptwrite} @tab @samp{.ibt}
@item @samp{.avx_ifma} @tab @samp{.avx_vnni_int8} @tab @samp{.avx_ne_convert}
-@item @samp{.cmpccxadd}
+@item @samp{.cmpccxadd} @tab @samp{.raoint}
@item @samp{.wbnoinvd} @tab @samp{.pconfig} @tab @samp{.waitpkg} @tab @samp{.cldemote}
@item @samp{.shstk} @tab @samp{.gfni} @tab @samp{.vaes} @tab @samp{.vpclmulqdq}
@item @samp{.movdiri} @tab @samp{.movdir64b} @tab @samp{.enqcmd} @tab @samp{.tsxldtrk}
@@ -486,6 +486,8 @@ if [gas_32_check] then {
run_dump_test "avx-ne-convert"
run_dump_test "avx-ne-convert-intel"
run_list_test "cmpccxadd-inval"
+ run_dump_test "raoint"
+ run_dump_test "raoint-intel"
run_list_test "sg"
run_dump_test "clzero"
run_dump_test "invlpgb"
@@ -1162,6 +1164,8 @@ if [gas_64_check] then {
run_dump_test "x86-64-avx-ne-convert-intel"
run_dump_test "x86-64-cmpccxadd"
run_dump_test "x86-64-cmpccxadd-intel"
+ run_dump_test "x86-64-raoint"
+ run_dump_test "x86-64-raoint-intel"
run_dump_test "x86-64-clzero"
run_dump_test "x86-64-mwaitx-bdver4"
run_list_test "x86-64-mwaitx-reg"
new file mode 100644
@@ -0,0 +1,18 @@
+#as:
+#objdump: -dw -Mintel
+#name: i386 RAOINT insns (Intel disassembly)
+#source: raoint.s
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+0+ <_start>:
+\s*[a-f0-9]+:\s*0f 38 fc 10\s+aadd DWORD PTR \[eax\],edx
+\s*[a-f0-9]+:\s*66 0f 38 fc 10\s+aand DWORD PTR \[eax\],edx
+\s*[a-f0-9]+:\s*f2 0f 38 fc 10\s+aor DWORD PTR \[eax\],edx
+\s*[a-f0-9]+:\s*f3 0f 38 fc 10\s+axor DWORD PTR \[eax\],edx
+\s*[a-f0-9]+:\s*0f 38 fc 10\s+aadd DWORD PTR \[eax\],edx
+\s*[a-f0-9]+:\s*66 0f 38 fc 10\s+aand DWORD PTR \[eax\],edx
+\s*[a-f0-9]+:\s*f2 0f 38 fc 10\s+aor DWORD PTR \[eax\],edx
+\s*[a-f0-9]+:\s*f3 0f 38 fc 10\s+axor DWORD PTR \[eax\],edx
new file mode 100644
@@ -0,0 +1,18 @@
+#as:
+#objdump: -dw
+#name: i386 RAOINT insns
+#source: raoint.s
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+0+ <_start>:
+\s*[a-f0-9]+:\s*0f 38 fc 10\s+aadd %edx,\(%eax\)
+\s*[a-f0-9]+:\s*66 0f 38 fc 10\s+aand %edx,\(%eax\)
+\s*[a-f0-9]+:\s*f2 0f 38 fc 10\s+aor %edx,\(%eax\)
+\s*[a-f0-9]+:\s*f3 0f 38 fc 10\s+axor %edx,\(%eax\)
+\s*[a-f0-9]+:\s*0f 38 fc 10\s+aadd %edx,\(%eax\)
+\s*[a-f0-9]+:\s*66 0f 38 fc 10\s+aand %edx,\(%eax\)
+\s*[a-f0-9]+:\s*f2 0f 38 fc 10\s+aor %edx,\(%eax\)
+\s*[a-f0-9]+:\s*f3 0f 38 fc 10\s+axor %edx,\(%eax\)
new file mode 100644
@@ -0,0 +1,15 @@
+# Check 32bit AVX-NE-CONVERT instructions
+
+ .allow_index_reg
+ .text
+_start:
+ aadd %edx, (%eax) #RAO-INT
+ aand %edx, (%eax) #RAO-INT
+ aor %edx, (%eax) #RAO-INT
+ axor %edx, (%eax) #RAO-INT
+
+.intel_syntax noprefix
+ aadd DWORD PTR [eax], %edx #RAO-INT
+ aand DWORD PTR [eax], %edx #RAO-INT
+ aor DWORD PTR [eax], %edx #RAO-INT
+ axor DWORD PTR [eax], %edx #RAO-INT
new file mode 100644
@@ -0,0 +1,18 @@
+#as:
+#objdump: -dw -Mintel
+#name: x86_64 RAOINT insns (Intel disassembly)
+#source: x86-64-raoint.s
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+0+ <_start>:
+\s*[a-f0-9]+:\s*48 0f 38 fc 10\s+aadd QWORD PTR \[rax\],rdx
+\s*[a-f0-9]+:\s*66 48 0f 38 fc 10\s+aand QWORD PTR \[rax\],rdx
+\s*[a-f0-9]+:\s*f2 48 0f 38 fc 10\s+aor QWORD PTR \[rax\],rdx
+\s*[a-f0-9]+:\s*f3 48 0f 38 fc 10\s+axor QWORD PTR \[rax\],rdx
+\s*[a-f0-9]+:\s*48 0f 38 fc 10\s+aadd QWORD PTR \[rax\],rdx
+\s*[a-f0-9]+:\s*66 48 0f 38 fc 10\s+aand QWORD PTR \[rax\],rdx
+\s*[a-f0-9]+:\s*f2 48 0f 38 fc 10\s+aor QWORD PTR \[rax\],rdx
+\s*[a-f0-9]+:\s*f3 48 0f 38 fc 10\s+axor QWORD PTR \[rax\],rdx
new file mode 100644
@@ -0,0 +1,18 @@
+#as:
+#objdump: -dw
+#name: x86_64 RAOINT insns
+#source: x86-64-raoint.s
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+0+ <_start>:
+\s*[a-f0-9]+:\s*48 0f 38 fc 10\s+aadd %rdx,\(%rax\)
+\s*[a-f0-9]+:\s*66 48 0f 38 fc 10\s+aand %rdx,\(%rax\)
+\s*[a-f0-9]+:\s*f2 48 0f 38 fc 10\s+aor %rdx,\(%rax\)
+\s*[a-f0-9]+:\s*f3 48 0f 38 fc 10\s+axor %rdx,\(%rax\)
+\s*[a-f0-9]+:\s*48 0f 38 fc 10\s+aadd %rdx,\(%rax\)
+\s*[a-f0-9]+:\s*66 48 0f 38 fc 10\s+aand %rdx,\(%rax\)
+\s*[a-f0-9]+:\s*f2 48 0f 38 fc 10\s+aor %rdx,\(%rax\)
+\s*[a-f0-9]+:\s*f3 48 0f 38 fc 10\s+axor %rdx,\(%rax\)
new file mode 100644
@@ -0,0 +1,15 @@
+# Check 64bit RAOINT instructions
+
+ .allow_index_reg
+ .text
+_start:
+ aadd %rdx, (%rax) #RAO-INT
+ aand %rdx, (%rax) #RAO-INT
+ aor %rdx, (%rax) #RAO-INT
+ axor %rdx, (%rax) #RAO-INT
+
+.intel_syntax noprefix
+ aadd QWORD PTR [rax], %rdx #RAO-INT
+ aand QWORD PTR [rax], %rdx #RAO-INT
+ aor QWORD PTR [rax], %rdx #RAO-INT
+ axor QWORD PTR [rax], %rdx #RAO-INT
@@ -887,6 +887,7 @@ enum
MOD_0F38F9,
MOD_0F38FA_PREFIX_1,
MOD_0F38FB_PREFIX_1,
+ MOD_0F38FC,
MOD_0F3A0F_PREFIX_1,
MOD_VEX_0F12_PREFIX_0,
@@ -1086,6 +1087,7 @@ enum
PREFIX_0F38F8,
PREFIX_0F38FA,
PREFIX_0F38FB,
+ PREFIX_0F38FC,
PREFIX_0F3A0F,
PREFIX_VEX_0F10,
PREFIX_VEX_0F11,
@@ -3598,6 +3600,14 @@ static const struct dis386 prefix_table[][4] = {
{ MOD_TABLE (MOD_0F38FB_PREFIX_1) },
},
+ /* PREFIX_0F38FC */
+ {
+ { "aadd", { Edq, Gdq }, PREFIX_OPCODE },
+ { "axor", { Edq, Gdq }, PREFIX_OPCODE },
+ { "aand", { Edq, Gdq }, PREFIX_OPCODE },
+ { "aor", { Edq, Gdq }, PREFIX_OPCODE },
+ },
+
/* PREFIX_0F3A0F */
{
{ Bad_Opcode },
@@ -4802,7 +4812,7 @@ static const struct dis386 three_byte_table[][256] = {
{ MOD_TABLE (MOD_0F38F9) },
{ PREFIX_TABLE (PREFIX_0F38FA) },
{ PREFIX_TABLE (PREFIX_0F38FB) },
- { Bad_Opcode },
+ { MOD_TABLE (MOD_0F38FC) },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
@@ -8374,6 +8384,10 @@ static const struct dis386 mod_table[][2] = {
{ Bad_Opcode },
{ "encodekey256", { Gd, Ed }, 0 },
},
+ {
+ /* MOD_0F38FC */
+ { PREFIX_TABLE (PREFIX_0F38FC) },
+ },
{
/* MOD_0F3A0F_PREFIX_1 */
{ Bad_Opcode },
@@ -253,6 +253,8 @@ static initializer cpu_flag_init[] =
"CPU_AVX2_FLAGS|CpuAVX_NE_CONVERT" },
{ "CPU_CMPCCXADD_FLAGS",
"CpuCMPCCXADD" },
+ { "CPU_RAOINT_FLAGS",
+ "CpuRAOINT" },
{ "CPU_IAMCU_FLAGS",
"Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuIAMCU" },
{ "CPU_ADX_FLAGS",
@@ -455,6 +457,8 @@ static initializer cpu_flag_init[] =
"CpuAVX_NE_CONVERT" },
{ "CPU_ANY_CMPCCXADD_FLAGS",
"CpuCMPCCXADD" },
+ { "CPU_ANY_RAOINT_FLAGS",
+ "CpuRAOINT" },
};
static initializer operand_type_init[] =
@@ -660,6 +664,7 @@ static bitfield cpu_flags[] =
BITFIELD (CpuAVX_VNNI_INT8),
BITFIELD (CpuAVX_NE_CONVERT),
BITFIELD (CpuCMPCCXADD),
+ BITFIELD (CpuRAOINT),
BITFIELD (CpuMWAITX),
BITFIELD (CpuCLZERO),
BITFIELD (CpuOSPKE),
@@ -217,6 +217,8 @@ enum
CpuAVX_NE_CONVERT,
/* Intel CMPccXADD instructions support required. */
CpuCMPCCXADD,
+ /* Intel RAO INT Instructions support required. */
+ CpuRAOINT,
/* mwaitx instruction required */
CpuMWAITX,
/* Clzero instruction required */
@@ -400,6 +402,7 @@ typedef union i386_cpu_flags
unsigned int cpuavx_vnni_int8:1;
unsigned int cpuavx_ne_convert:1;
unsigned int cpucmpccxadd:1;
+ unsigned int cpuraoint:1;
unsigned int cpumwaitx:1;
unsigned int cpuclzero:1;
unsigned int cpuospke:1;
@@ -436,7 +439,7 @@ typedef union i386_cpu_flags
unsigned int cpu64:1;
unsigned int cpuno64:1;
#ifdef CpuUnused
- // unsigned int unused:(CpuNumOfBits - CpuUnused);
+ unsigned int unused:(CpuNumOfBits - CpuUnused);
#endif
} bitfield;
unsigned int array[CpuNumOfUints];
@@ -3317,3 +3317,12 @@ cmpsxadd, 0x66e8, None, CpuCMPCCXADD|Cpu64, Modrm|Vex128|Space0F38|VexVVVV=1|Swa
cmpzxadd, 0x66e4, None, CpuCMPCCXADD|Cpu64, Modrm|Vex128|Space0F38|VexVVVV=1|SwapSources|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Reg64, Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex }
// CMPCCXADD instructions end.
+
+// RAOINT instructions.
+
+aadd, 0xf38fc, None, CpuRAOINT, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf,{ Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex}
+aand, 0x660f38fc, None, CpuRAOINT, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf,{ Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex}
+aor, 0xf20f38fc, None, CpuRAOINT, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf,{ Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex}
+axor, 0xf30f38fc, None, CpuRAOINT, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf,{ Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex}
+
+// RAOINT instructions end.