drm/amd/display: Revert logic for plane modifiers
Commit Message
This file was split in commit 5d945cbcd4b16a29d6470a80dfb19738f9a4319f
("drm/amd/display: Create a file dedicated to planes") and the logic in
dm_plane_format_mod_supported() function got changed by a switch logic.
That change broke drm_plane modifiers setting on series 5000 APUs
(tested on OXP mini AMD 5800U and HP Dev One 5850U PRO)
leading to Gamescope not working as reported on GitHub[1]
To reproduce the issue, enter a TTY and run:
$ gamescope -- vkcube
With said commit applied it will abort. This one restores the old logic,
fixing the issue that affects Gamescope.
[1](https://github.com/Plagman/gamescope/issues/624)
Signed-off-by: Joaquín Ignacio Aramendía <samsagax@gmail.com>
---
.../amd/display/amdgpu_dm/amdgpu_dm_plane.c | 51 +++----------------
1 file changed, 8 insertions(+), 43 deletions(-)
--
2.38.1
Comments
Please also add a
Cc: <stable@vger.kernel.org> # 6.0.x
to ensure it gets backported.
On Fri, Oct 21, 2022 at 9:24 AM Joaquín Ignacio Aramendía
<samsagax@gmail.com> wrote:
>
> This file was split in commit 5d945cbcd4b16a29d6470a80dfb19738f9a4319f
> ("drm/amd/display: Create a file dedicated to planes") and the logic in
> dm_plane_format_mod_supported() function got changed by a switch logic.
> That change broke drm_plane modifiers setting on series 5000 APUs
> (tested on OXP mini AMD 5800U and HP Dev One 5850U PRO)
> leading to Gamescope not working as reported on GitHub[1]
>
> To reproduce the issue, enter a TTY and run:
>
> $ gamescope -- vkcube
>
> With said commit applied it will abort. This one restores the old logic,
> fixing the issue that affects Gamescope.
>
> [1](https://github.com/Plagman/gamescope/issues/624)
>
> Signed-off-by: Joaquín Ignacio Aramendía <samsagax@gmail.com>
> ---
> .../amd/display/amdgpu_dm/amdgpu_dm_plane.c | 51 +++----------------
> 1 file changed, 8 insertions(+), 43 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
> index dfd3be49eac8..1d47d2d69781 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
> @@ -1369,7 +1369,8 @@ static bool dm_plane_format_mod_supported(struct drm_plane *plane,
> {
> struct amdgpu_device *adev = drm_to_adev(plane->dev);
> const struct drm_format_info *info = drm_format_info(format);
> - struct hw_asic_id asic_id = adev->dm.dc->ctx->asic_id;
> +
Can remove this newline.
With that removed, this patch is
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Thanks,
Bas
> + int i;
>
> enum dm_micro_swizzle microtile = modifier_gfx9_swizzle_mode(modifier) & 3;
>
> @@ -1386,49 +1387,13 @@ static bool dm_plane_format_mod_supported(struct drm_plane *plane,
> return true;
> }
>
> - /* check if swizzle mode is supported by this version of DCN */
> - switch (asic_id.chip_family) {
> - case FAMILY_SI:
> - case FAMILY_CI:
> - case FAMILY_KV:
> - case FAMILY_CZ:
> - case FAMILY_VI:
> - /* asics before AI does not have modifier support */
> - return false;
> - case FAMILY_AI:
> - case FAMILY_RV:
> - case FAMILY_NV:
> - case FAMILY_VGH:
> - case FAMILY_YELLOW_CARP:
> - case AMDGPU_FAMILY_GC_10_3_6:
> - case AMDGPU_FAMILY_GC_10_3_7:
> - switch (AMD_FMT_MOD_GET(TILE, modifier)) {
> - case AMD_FMT_MOD_TILE_GFX9_64K_R_X:
> - case AMD_FMT_MOD_TILE_GFX9_64K_D_X:
> - case AMD_FMT_MOD_TILE_GFX9_64K_S_X:
> - case AMD_FMT_MOD_TILE_GFX9_64K_D:
> - return true;
> - default:
> - return false;
> - }
> - break;
> - case AMDGPU_FAMILY_GC_11_0_0:
> - case AMDGPU_FAMILY_GC_11_0_1:
> - switch (AMD_FMT_MOD_GET(TILE, modifier)) {
> - case AMD_FMT_MOD_TILE_GFX11_256K_R_X:
> - case AMD_FMT_MOD_TILE_GFX9_64K_R_X:
> - case AMD_FMT_MOD_TILE_GFX9_64K_D_X:
> - case AMD_FMT_MOD_TILE_GFX9_64K_S_X:
> - case AMD_FMT_MOD_TILE_GFX9_64K_D:
> - return true;
> - default:
> - return false;
> - }
> - break;
> - default:
> - ASSERT(0); /* Unknown asic */
> - break;
> + /* Check that the modifier is on the list of the plane's supported modifiers. */
> + for (i = 0; i < plane->modifier_count; i++) {
> + if (modifier == plane->modifiers[i])
> + break;
> }
> + if (i == plane->modifier_count)
> + return false;
>
> /*
> * For D swizzle the canonical modifier depends on the bpp, so check
> --
> 2.38.1
>
@@ -1369,7 +1369,8 @@ static bool dm_plane_format_mod_supported(struct drm_plane *plane,
{
struct amdgpu_device *adev = drm_to_adev(plane->dev);
const struct drm_format_info *info = drm_format_info(format);
- struct hw_asic_id asic_id = adev->dm.dc->ctx->asic_id;
+
+ int i;
enum dm_micro_swizzle microtile = modifier_gfx9_swizzle_mode(modifier) & 3;
@@ -1386,49 +1387,13 @@ static bool dm_plane_format_mod_supported(struct drm_plane *plane,
return true;
}
- /* check if swizzle mode is supported by this version of DCN */
- switch (asic_id.chip_family) {
- case FAMILY_SI:
- case FAMILY_CI:
- case FAMILY_KV:
- case FAMILY_CZ:
- case FAMILY_VI:
- /* asics before AI does not have modifier support */
- return false;
- case FAMILY_AI:
- case FAMILY_RV:
- case FAMILY_NV:
- case FAMILY_VGH:
- case FAMILY_YELLOW_CARP:
- case AMDGPU_FAMILY_GC_10_3_6:
- case AMDGPU_FAMILY_GC_10_3_7:
- switch (AMD_FMT_MOD_GET(TILE, modifier)) {
- case AMD_FMT_MOD_TILE_GFX9_64K_R_X:
- case AMD_FMT_MOD_TILE_GFX9_64K_D_X:
- case AMD_FMT_MOD_TILE_GFX9_64K_S_X:
- case AMD_FMT_MOD_TILE_GFX9_64K_D:
- return true;
- default:
- return false;
- }
- break;
- case AMDGPU_FAMILY_GC_11_0_0:
- case AMDGPU_FAMILY_GC_11_0_1:
- switch (AMD_FMT_MOD_GET(TILE, modifier)) {
- case AMD_FMT_MOD_TILE_GFX11_256K_R_X:
- case AMD_FMT_MOD_TILE_GFX9_64K_R_X:
- case AMD_FMT_MOD_TILE_GFX9_64K_D_X:
- case AMD_FMT_MOD_TILE_GFX9_64K_S_X:
- case AMD_FMT_MOD_TILE_GFX9_64K_D:
- return true;
- default:
- return false;
- }
- break;
- default:
- ASSERT(0); /* Unknown asic */
- break;
+ /* Check that the modifier is on the list of the plane's supported modifiers. */
+ for (i = 0; i < plane->modifier_count; i++) {
+ if (modifier == plane->modifiers[i])
+ break;
}
+ if (i == plane->modifier_count)
+ return false;
/*
* For D swizzle the canonical modifier depends on the bpp, so check