[net-next,v2,1/5] dt-bindings: net: Add Motorcomm yt8xxx ethernet phy
Commit Message
Add a YAML binding document for the Motorcom yt8xxx Ethernet phy driver.
Signed-off-by: Frank Sae <Frank.Sae@motor-comm.com>
---
.../bindings/net/motorcomm,yt8xxx.yaml | 102 ++++++++++++++++++
.../devicetree/bindings/vendor-prefixes.yaml | 2 +
MAINTAINERS | 1 +
3 files changed, 105 insertions(+)
create mode 100644 Documentation/devicetree/bindings/net/motorcomm,yt8xxx.yaml
Comments
> +properties:
> + rx-internal-delay-ps:
> + description: |
> + RGMII RX Clock Delay used only when PHY operates in RGMII mode with
> + internal delay (phy-mode is 'rgmii-id' or 'rgmii-rxid') in pico-seconds.
> + enum: [ 0, 150, 300, 450, 600, 750, 900, 1050, 1200, 1350, 1500, 1650,
> + 1800, 1900, 1950, 2050, 2100, 2200, 2250, 2350, 2500, 2650, 2800,
> + 2950, 3100, 3250, 3400, 3550, 3700, 3850, 4000, 4150 ]
> + default: 1900
> +
> + tx-internal-delay-ps:
> + description: |
> + RGMII TX Clock Delay used only when PHY operates in RGMII mode with
> + internal delay (phy-mode is 'rgmii-id' or 'rgmii-txid') in pico-seconds.
> + enum: [ 0, 150, 300, 450, 600, 750, 900, 1050, 1200, 1350, 1500, 1650, 1800,
> + 1950, 2100, 2250 ]
> + default: 150
That is an odd default to choose. rgmii-id or rgmii-txid means the PHY
should be added around 2ns of delay. So a default of 1950 makes more
sense.
Andrew
On 28/01/2023 04:13, Frank Sae wrote:
> Add a YAML binding document for the Motorcom yt8xxx Ethernet phy driver.
>
> Signed-off-by: Frank Sae <Frank.Sae@motor-comm.com>
Please use scripts/get_maintainers.pl to get a list of necessary people
and lists to CC. It might happen, that command when run on an older
kernel, gives you outdated entries. Therefore please be sure you base
your patches on recent Linux kernel.
This missed also DT list so it means it won't be tested.
> ---
> .../bindings/net/motorcomm,yt8xxx.yaml | 102 ++++++++++++++++++
> .../devicetree/bindings/vendor-prefixes.yaml | 2 +
> MAINTAINERS | 1 +
> 3 files changed, 105 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/net/motorcomm,yt8xxx.yaml
>
> diff --git a/Documentation/devicetree/bindings/net/motorcomm,yt8xxx.yaml b/Documentation/devicetree/bindings/net/motorcomm,yt8xxx.yaml
> new file mode 100644
> index 000000000000..b666584d51eb
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/net/motorcomm,yt8xxx.yaml
> @@ -0,0 +1,102 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/net/motorcomm,yt8xxx.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: MotorComm yt8xxx Ethernet PHY
> +
> +maintainers:
> + - frank sae <frank.sae@motor-comm.com>
> +
> +allOf:
> + - $ref: ethernet-phy.yaml#
> +
> +properties:
I think the problem of missing compatible is still not solved...
> + rx-internal-delay-ps:
> + description: |
> + RGMII RX Clock Delay used only when PHY operates in RGMII mode with
> + internal delay (phy-mode is 'rgmii-id' or 'rgmii-rxid') in pico-seconds.
> + enum: [ 0, 150, 300, 450, 600, 750, 900, 1050, 1200, 1350, 1500, 1650,
> + 1800, 1900, 1950, 2050, 2100, 2200, 2250, 2350, 2500, 2650, 2800,
> + 2950, 3100, 3250, 3400, 3550, 3700, 3850, 4000, 4150 ]
> + default: 1900
> +
> + tx-internal-delay-ps:
> + description: |
> + RGMII TX Clock Delay used only when PHY operates in RGMII mode with
> + internal delay (phy-mode is 'rgmii-id' or 'rgmii-txid') in pico-seconds.
> + enum: [ 0, 150, 300, 450, 600, 750, 900, 1050, 1200, 1350, 1500, 1650, 1800,
> + 1950, 2100, 2250 ]
> + default: 150
> +
> + motorcomm,clk-out-frequency-hz:
> + description: clock output on clock output pin.
> + enum: [0, 25000000, 125000000]
> + default: 0
> +
> + motorcomm,keep-pll-enabled:
> + description: |
> + If set, keep the PLL enabled even if there is no link. Useful if you
> + want to use the clock output without an ethernet link.
> + type: boolean
> +
> + motorcomm,auto-sleep-disabled:
> + description: |
> + If set, PHY will not enter sleep mode and close AFE after unplug cable
> + for a timer.
> + type: boolean
> +
> + motorcomm,tx-clk-adj-enabled:
> + description: |
> + This configuration is mainly to adapt to VF2 with JH7110 SoC.
> + Useful if you want to use tx-clk-xxxx-inverted to adj the delay of tx clk.
> + type: boolean
> +
> + motorcomm,tx-clk-10-inverted:
> + description: |
> + Use original or inverted RGMII Transmit PHY Clock to drive the RGMII
> + Transmit PHY Clock delay train configuration when speed is 10Mbps.
> + type: boolean
> +
> + motorcomm,tx-clk-100-inverted:
> + description: |
> + Use original or inverted RGMII Transmit PHY Clock to drive the RGMII
> + Transmit PHY Clock delay train configuration when speed is 100Mbps.
> + type: boolean
> +
> + motorcomm,tx-clk-1000-inverted:
> + description: |
> + Use original or inverted RGMII Transmit PHY Clock to drive the RGMII
> + Transmit PHY Clock delay train configuration when speed is 1000Mbps.
> + type: boolean
> +
> +unevaluatedProperties: false
> +
> +examples:
> + - |
> + mdio0 {
mdio
> + #address-cells = <1>;
> + #size-cells = <0>;
> + phy-mode = "rgmii-id";
> + ethernet-phy@4 {
> + reg = <4>;
> + rx-internal-delay-ps = <2100>;
> + tx-internal-delay-ps = <150>;
> + motorcomm,clk-out-frequency-hz = <0>;
> + motorcomm,keep-pll-enabled;
> + motorcomm,auto-sleep-disabled;
> + };
> + };
> + - |
> + mdio0 {
mdio
> + #address-cells = <1>;
> + #size-cells = <0>;
> + phy-mode = "rgmii";
> + ethernet-phy@5 {
> + reg = <5>;
> + motorcomm,clk-out-frequency-hz = <125000000>;
> + motorcomm,keep-pll-enabled;
> + motorcomm,auto-sleep-disabled;
> + };
> + };
Best regards,
Krzysztof
new file mode 100644
@@ -0,0 +1,102 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/net/motorcomm,yt8xxx.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MotorComm yt8xxx Ethernet PHY
+
+maintainers:
+ - frank sae <frank.sae@motor-comm.com>
+
+allOf:
+ - $ref: ethernet-phy.yaml#
+
+properties:
+ rx-internal-delay-ps:
+ description: |
+ RGMII RX Clock Delay used only when PHY operates in RGMII mode with
+ internal delay (phy-mode is 'rgmii-id' or 'rgmii-rxid') in pico-seconds.
+ enum: [ 0, 150, 300, 450, 600, 750, 900, 1050, 1200, 1350, 1500, 1650,
+ 1800, 1900, 1950, 2050, 2100, 2200, 2250, 2350, 2500, 2650, 2800,
+ 2950, 3100, 3250, 3400, 3550, 3700, 3850, 4000, 4150 ]
+ default: 1900
+
+ tx-internal-delay-ps:
+ description: |
+ RGMII TX Clock Delay used only when PHY operates in RGMII mode with
+ internal delay (phy-mode is 'rgmii-id' or 'rgmii-txid') in pico-seconds.
+ enum: [ 0, 150, 300, 450, 600, 750, 900, 1050, 1200, 1350, 1500, 1650, 1800,
+ 1950, 2100, 2250 ]
+ default: 150
+
+ motorcomm,clk-out-frequency-hz:
+ description: clock output on clock output pin.
+ enum: [0, 25000000, 125000000]
+ default: 0
+
+ motorcomm,keep-pll-enabled:
+ description: |
+ If set, keep the PLL enabled even if there is no link. Useful if you
+ want to use the clock output without an ethernet link.
+ type: boolean
+
+ motorcomm,auto-sleep-disabled:
+ description: |
+ If set, PHY will not enter sleep mode and close AFE after unplug cable
+ for a timer.
+ type: boolean
+
+ motorcomm,tx-clk-adj-enabled:
+ description: |
+ This configuration is mainly to adapt to VF2 with JH7110 SoC.
+ Useful if you want to use tx-clk-xxxx-inverted to adj the delay of tx clk.
+ type: boolean
+
+ motorcomm,tx-clk-10-inverted:
+ description: |
+ Use original or inverted RGMII Transmit PHY Clock to drive the RGMII
+ Transmit PHY Clock delay train configuration when speed is 10Mbps.
+ type: boolean
+
+ motorcomm,tx-clk-100-inverted:
+ description: |
+ Use original or inverted RGMII Transmit PHY Clock to drive the RGMII
+ Transmit PHY Clock delay train configuration when speed is 100Mbps.
+ type: boolean
+
+ motorcomm,tx-clk-1000-inverted:
+ description: |
+ Use original or inverted RGMII Transmit PHY Clock to drive the RGMII
+ Transmit PHY Clock delay train configuration when speed is 1000Mbps.
+ type: boolean
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ mdio0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ phy-mode = "rgmii-id";
+ ethernet-phy@4 {
+ reg = <4>;
+ rx-internal-delay-ps = <2100>;
+ tx-internal-delay-ps = <150>;
+ motorcomm,clk-out-frequency-hz = <0>;
+ motorcomm,keep-pll-enabled;
+ motorcomm,auto-sleep-disabled;
+ };
+ };
+ - |
+ mdio0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ phy-mode = "rgmii";
+ ethernet-phy@5 {
+ reg = <5>;
+ motorcomm,clk-out-frequency-hz = <125000000>;
+ motorcomm,keep-pll-enabled;
+ motorcomm,auto-sleep-disabled;
+ };
+ };
@@ -847,6 +847,8 @@ patternProperties:
description: Moortec Semiconductor Ltd.
"^mosaixtech,.*":
description: Mosaix Technologies, Inc.
+ "^motorcomm,.*":
+ description: MotorComm, Inc.
"^motorola,.*":
description: Motorola, Inc.
"^moxa,.*":
@@ -14163,6 +14163,7 @@ M: Peter Geis <pgwipeout@gmail.com>
M: Frank <Frank.Sae@motor-comm.com>
L: netdev@vger.kernel.org
S: Maintained
+F: Documentation/devicetree/bindings/net/motorcomm,yt8xxx.yaml
F: drivers/net/phy/motorcomm.c
MOXA SMARTIO/INDUSTIO/INTELLIO SERIAL CARD